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Added few more stubs so that control reaches to DestroyDevice().
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 bool src_render_loop,
58 VkImageLayout dst_layout,
59 bool dst_render_loop,
60 uint32_t src_family,
61 uint32_t dst_family,
62 const VkImageSubresourceRange *range,
63 struct radv_sample_locations_state *sample_locs);
64
65 const struct radv_dynamic_state default_dynamic_state = {
66 .viewport = {
67 .count = 0,
68 },
69 .scissor = {
70 .count = 0,
71 },
72 .line_width = 1.0f,
73 .depth_bias = {
74 .bias = 0.0f,
75 .clamp = 0.0f,
76 .slope = 0.0f,
77 },
78 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
79 .depth_bounds = {
80 .min = 0.0f,
81 .max = 1.0f,
82 },
83 .stencil_compare_mask = {
84 .front = ~0u,
85 .back = ~0u,
86 },
87 .stencil_write_mask = {
88 .front = ~0u,
89 .back = ~0u,
90 },
91 .stencil_reference = {
92 .front = 0u,
93 .back = 0u,
94 },
95 .line_stipple = {
96 .factor = 0u,
97 .pattern = 0u,
98 },
99 .cull_mode = 0u,
100 .front_face = 0u,
101 .primitive_topology = 0u,
102 };
103
104 static void
105 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
106 const struct radv_dynamic_state *src)
107 {
108 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
109 uint32_t copy_mask = src->mask;
110 uint32_t dest_mask = 0;
111
112 dest->discard_rectangle.count = src->discard_rectangle.count;
113 dest->sample_location.count = src->sample_location.count;
114
115 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
116 if (dest->viewport.count != src->viewport.count) {
117 dest->viewport.count = src->viewport.count;
118 dest_mask |= RADV_DYNAMIC_VIEWPORT;
119 }
120
121 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
122 src->viewport.count * sizeof(VkViewport))) {
123 typed_memcpy(dest->viewport.viewports,
124 src->viewport.viewports,
125 src->viewport.count);
126 dest_mask |= RADV_DYNAMIC_VIEWPORT;
127 }
128 }
129
130 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
131 if (dest->scissor.count != src->scissor.count) {
132 dest->scissor.count = src->scissor.count;
133 dest_mask |= RADV_DYNAMIC_SCISSOR;
134 }
135
136 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
137 src->scissor.count * sizeof(VkRect2D))) {
138 typed_memcpy(dest->scissor.scissors,
139 src->scissor.scissors, src->scissor.count);
140 dest_mask |= RADV_DYNAMIC_SCISSOR;
141 }
142 }
143
144 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
145 if (dest->line_width != src->line_width) {
146 dest->line_width = src->line_width;
147 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
148 }
149 }
150
151 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
152 if (memcmp(&dest->depth_bias, &src->depth_bias,
153 sizeof(src->depth_bias))) {
154 dest->depth_bias = src->depth_bias;
155 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
156 }
157 }
158
159 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
160 if (memcmp(&dest->blend_constants, &src->blend_constants,
161 sizeof(src->blend_constants))) {
162 typed_memcpy(dest->blend_constants,
163 src->blend_constants, 4);
164 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
165 }
166 }
167
168 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
169 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
170 sizeof(src->depth_bounds))) {
171 dest->depth_bounds = src->depth_bounds;
172 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
173 }
174 }
175
176 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
177 if (memcmp(&dest->stencil_compare_mask,
178 &src->stencil_compare_mask,
179 sizeof(src->stencil_compare_mask))) {
180 dest->stencil_compare_mask = src->stencil_compare_mask;
181 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
182 }
183 }
184
185 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
186 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
187 sizeof(src->stencil_write_mask))) {
188 dest->stencil_write_mask = src->stencil_write_mask;
189 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
190 }
191 }
192
193 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
194 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
195 sizeof(src->stencil_reference))) {
196 dest->stencil_reference = src->stencil_reference;
197 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
198 }
199 }
200
201 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
202 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
203 src->discard_rectangle.count * sizeof(VkRect2D))) {
204 typed_memcpy(dest->discard_rectangle.rectangles,
205 src->discard_rectangle.rectangles,
206 src->discard_rectangle.count);
207 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
208 }
209 }
210
211 if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
212 if (dest->sample_location.per_pixel != src->sample_location.per_pixel ||
213 dest->sample_location.grid_size.width != src->sample_location.grid_size.width ||
214 dest->sample_location.grid_size.height != src->sample_location.grid_size.height ||
215 memcmp(&dest->sample_location.locations,
216 &src->sample_location.locations,
217 src->sample_location.count * sizeof(VkSampleLocationEXT))) {
218 dest->sample_location.per_pixel = src->sample_location.per_pixel;
219 dest->sample_location.grid_size = src->sample_location.grid_size;
220 typed_memcpy(dest->sample_location.locations,
221 src->sample_location.locations,
222 src->sample_location.count);
223 dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
224 }
225 }
226
227 if (copy_mask & RADV_DYNAMIC_LINE_STIPPLE) {
228 if (memcmp(&dest->line_stipple, &src->line_stipple,
229 sizeof(src->line_stipple))) {
230 dest->line_stipple = src->line_stipple;
231 dest_mask |= RADV_DYNAMIC_LINE_STIPPLE;
232 }
233 }
234
235 if (copy_mask & RADV_DYNAMIC_CULL_MODE) {
236 if (dest->cull_mode != src->cull_mode) {
237 dest->cull_mode = src->cull_mode;
238 dest_mask |= RADV_DYNAMIC_CULL_MODE;
239 }
240 }
241
242 if (copy_mask & RADV_DYNAMIC_FRONT_FACE) {
243 if (dest->front_face != src->front_face) {
244 dest->front_face = src->front_face;
245 dest_mask |= RADV_DYNAMIC_FRONT_FACE;
246 }
247 }
248
249 if (copy_mask & RADV_DYNAMIC_PRIMITIVE_TOPOLOGY) {
250 if (dest->primitive_topology != src->primitive_topology) {
251 dest->primitive_topology = src->primitive_topology;
252 dest_mask |= RADV_DYNAMIC_PRIMITIVE_TOPOLOGY;
253 }
254 }
255
256 if (copy_mask & RADV_DYNAMIC_DEPTH_TEST_ENABLE) {
257 if (dest->depth_test_enable != src->depth_test_enable) {
258 dest->depth_test_enable = src->depth_test_enable;
259 dest_mask |= RADV_DYNAMIC_DEPTH_TEST_ENABLE;
260 }
261 }
262
263 if (copy_mask & RADV_DYNAMIC_DEPTH_WRITE_ENABLE) {
264 if (dest->depth_write_enable != src->depth_write_enable) {
265 dest->depth_write_enable = src->depth_write_enable;
266 dest_mask |= RADV_DYNAMIC_DEPTH_WRITE_ENABLE;
267 }
268 }
269
270 if (copy_mask & RADV_DYNAMIC_DEPTH_COMPARE_OP) {
271 if (dest->depth_compare_op != src->depth_compare_op) {
272 dest->depth_compare_op = src->depth_compare_op;
273 dest_mask |= RADV_DYNAMIC_DEPTH_COMPARE_OP;
274 }
275 }
276
277 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE) {
278 if (dest->depth_bounds_test_enable != src->depth_bounds_test_enable) {
279 dest->depth_bounds_test_enable = src->depth_bounds_test_enable;
280 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE;
281 }
282 }
283
284 if (copy_mask & RADV_DYNAMIC_STENCIL_TEST_ENABLE) {
285 if (dest->stencil_test_enable != src->stencil_test_enable) {
286 dest->stencil_test_enable = src->stencil_test_enable;
287 dest_mask |= RADV_DYNAMIC_STENCIL_TEST_ENABLE;
288 }
289 }
290
291 if (copy_mask & RADV_DYNAMIC_STENCIL_OP) {
292 if (memcmp(&dest->stencil_op, &src->stencil_op,
293 sizeof(src->stencil_op))) {
294 dest->stencil_op = src->stencil_op;
295 dest_mask |= RADV_DYNAMIC_STENCIL_OP;
296 }
297 }
298
299 cmd_buffer->state.dirty |= dest_mask;
300 }
301
302 static void
303 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
304 struct radv_pipeline *pipeline)
305 {
306 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
307 struct radv_shader_info *info;
308
309 if (!pipeline->streamout_shader ||
310 cmd_buffer->device->physical_device->use_ngg_streamout)
311 return;
312
313 info = &pipeline->streamout_shader->info;
314 for (int i = 0; i < MAX_SO_BUFFERS; i++)
315 so->stride_in_dw[i] = info->so.strides[i];
316
317 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
318 }
319
320 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
321 {
322 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
323 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
324 }
325
326 enum ring_type radv_queue_family_to_ring(int f) {
327 switch (f) {
328 case RADV_QUEUE_GENERAL:
329 return RING_GFX;
330 case RADV_QUEUE_COMPUTE:
331 return RING_COMPUTE;
332 case RADV_QUEUE_TRANSFER:
333 return RING_DMA;
334 default:
335 unreachable("Unknown queue family");
336 }
337 }
338
339 static void
340 radv_destroy_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
341 {
342 list_del(&cmd_buffer->pool_link);
343
344 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
345 &cmd_buffer->upload.list, list) {
346 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
347 list_del(&up->list);
348 free(up);
349 }
350
351 if (cmd_buffer->upload.upload_bo)
352 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
353
354 if (cmd_buffer->cs)
355 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
356
357 for (unsigned i = 0; i < MAX_BIND_POINTS; i++)
358 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
359
360 vk_object_base_finish(&cmd_buffer->base);
361 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
362 }
363
364 static VkResult radv_create_cmd_buffer(
365 struct radv_device * device,
366 struct radv_cmd_pool * pool,
367 VkCommandBufferLevel level,
368 VkCommandBuffer* pCommandBuffer)
369 {
370 struct radv_cmd_buffer *cmd_buffer;
371 unsigned ring;
372 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
373 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
374 if (cmd_buffer == NULL)
375 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
376
377 vk_object_base_init(&device->vk, &cmd_buffer->base,
378 VK_OBJECT_TYPE_COMMAND_BUFFER);
379
380 cmd_buffer->device = device;
381 cmd_buffer->pool = pool;
382 cmd_buffer->level = level;
383
384 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
385 cmd_buffer->queue_family_index = pool->queue_family_index;
386
387 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
388
389 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
390 if (!cmd_buffer->cs) {
391 radv_destroy_cmd_buffer(cmd_buffer);
392 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
393 }
394
395 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
396
397 list_inithead(&cmd_buffer->upload.list);
398
399 return VK_SUCCESS;
400 }
401
402 static VkResult
403 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
404 {
405 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
406
407 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
408 &cmd_buffer->upload.list, list) {
409 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
410 list_del(&up->list);
411 free(up);
412 }
413
414 cmd_buffer->push_constant_stages = 0;
415 cmd_buffer->scratch_size_per_wave_needed = 0;
416 cmd_buffer->scratch_waves_wanted = 0;
417 cmd_buffer->compute_scratch_size_per_wave_needed = 0;
418 cmd_buffer->compute_scratch_waves_wanted = 0;
419 cmd_buffer->esgs_ring_size_needed = 0;
420 cmd_buffer->gsvs_ring_size_needed = 0;
421 cmd_buffer->tess_rings_needed = false;
422 cmd_buffer->gds_needed = false;
423 cmd_buffer->gds_oa_needed = false;
424 cmd_buffer->sample_positions_needed = false;
425
426 if (cmd_buffer->upload.upload_bo)
427 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
428 cmd_buffer->upload.upload_bo);
429 cmd_buffer->upload.offset = 0;
430
431 cmd_buffer->record_result = VK_SUCCESS;
432
433 memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
434
435 for (unsigned i = 0; i < MAX_BIND_POINTS; i++) {
436 cmd_buffer->descriptors[i].dirty = 0;
437 cmd_buffer->descriptors[i].valid = 0;
438 cmd_buffer->descriptors[i].push_dirty = false;
439 }
440
441 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
442 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
443 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
444 unsigned fence_offset, eop_bug_offset;
445 void *fence_ptr;
446
447 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
448 &fence_ptr);
449
450 cmd_buffer->gfx9_fence_va =
451 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
452 cmd_buffer->gfx9_fence_va += fence_offset;
453
454 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
455 /* Allocate a buffer for the EOP bug on GFX9. */
456 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
457 &eop_bug_offset, &fence_ptr);
458 cmd_buffer->gfx9_eop_bug_va =
459 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
460 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
461 }
462 }
463
464 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
465
466 return cmd_buffer->record_result;
467 }
468
469 static bool
470 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
471 uint64_t min_needed)
472 {
473 uint64_t new_size;
474 struct radeon_winsys_bo *bo;
475 struct radv_cmd_buffer_upload *upload;
476 struct radv_device *device = cmd_buffer->device;
477
478 new_size = MAX2(min_needed, 16 * 1024);
479 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
480
481 bo = device->ws->buffer_create(device->ws,
482 new_size, 4096,
483 RADEON_DOMAIN_GTT,
484 RADEON_FLAG_CPU_ACCESS|
485 RADEON_FLAG_NO_INTERPROCESS_SHARING |
486 RADEON_FLAG_32BIT |
487 RADEON_FLAG_GTT_WC,
488 RADV_BO_PRIORITY_UPLOAD_BUFFER);
489
490 if (!bo) {
491 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
492 return false;
493 }
494
495 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
496 if (cmd_buffer->upload.upload_bo) {
497 upload = malloc(sizeof(*upload));
498
499 if (!upload) {
500 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
501 device->ws->buffer_destroy(bo);
502 return false;
503 }
504
505 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
506 list_add(&upload->list, &cmd_buffer->upload.list);
507 }
508
509 cmd_buffer->upload.upload_bo = bo;
510 cmd_buffer->upload.size = new_size;
511 cmd_buffer->upload.offset = 0;
512 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
513
514 if (!cmd_buffer->upload.map) {
515 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
516 return false;
517 }
518
519 return true;
520 }
521
522 bool
523 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
524 unsigned size,
525 unsigned alignment,
526 unsigned *out_offset,
527 void **ptr)
528 {
529 assert(util_is_power_of_two_nonzero(alignment));
530
531 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
532 if (offset + size > cmd_buffer->upload.size) {
533 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
534 return false;
535 offset = 0;
536 }
537
538 *out_offset = offset;
539 *ptr = cmd_buffer->upload.map + offset;
540
541 cmd_buffer->upload.offset = offset + size;
542 return true;
543 }
544
545 bool
546 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
547 unsigned size, unsigned alignment,
548 const void *data, unsigned *out_offset)
549 {
550 uint8_t *ptr;
551
552 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
553 out_offset, (void **)&ptr))
554 return false;
555
556 if (ptr)
557 memcpy(ptr, data, size);
558
559 return true;
560 }
561
562 static void
563 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
564 unsigned count, const uint32_t *data)
565 {
566 struct radeon_cmdbuf *cs = cmd_buffer->cs;
567
568 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
569
570 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
571 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
572 S_370_WR_CONFIRM(1) |
573 S_370_ENGINE_SEL(V_370_ME));
574 radeon_emit(cs, va);
575 radeon_emit(cs, va >> 32);
576 radeon_emit_array(cs, data, count);
577 }
578
579 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
580 {
581 struct radv_device *device = cmd_buffer->device;
582 struct radeon_cmdbuf *cs = cmd_buffer->cs;
583 uint64_t va;
584
585 va = radv_buffer_get_va(device->trace_bo);
586 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
587 va += 4;
588
589 ++cmd_buffer->state.trace_id;
590 radv_emit_write_data_packet(cmd_buffer, va, 1,
591 &cmd_buffer->state.trace_id);
592
593 radeon_check_space(cmd_buffer->device->ws, cs, 2);
594
595 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
596 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
597 }
598
599 static void
600 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
601 enum radv_cmd_flush_bits flags)
602 {
603 if (unlikely(cmd_buffer->device->thread_trace_bo)) {
604 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
605 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_THREAD_TRACE_MARKER) | EVENT_INDEX(0));
606 }
607
608 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
609 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
610 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
611
612 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
613
614 /* Force wait for graphics or compute engines to be idle. */
615 si_cs_emit_cache_flush(cmd_buffer->cs,
616 cmd_buffer->device->physical_device->rad_info.chip_class,
617 &cmd_buffer->gfx9_fence_idx,
618 cmd_buffer->gfx9_fence_va,
619 radv_cmd_buffer_uses_mec(cmd_buffer),
620 flags, cmd_buffer->gfx9_eop_bug_va);
621 }
622
623 if (unlikely(cmd_buffer->device->trace_bo))
624 radv_cmd_buffer_trace_emit(cmd_buffer);
625 }
626
627 static void
628 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
629 struct radv_pipeline *pipeline)
630 {
631 struct radv_device *device = cmd_buffer->device;
632 enum ring_type ring;
633 uint32_t data[2];
634 uint64_t va;
635
636 va = radv_buffer_get_va(device->trace_bo);
637
638 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
639
640 switch (ring) {
641 case RING_GFX:
642 va += 8;
643 break;
644 case RING_COMPUTE:
645 va += 16;
646 break;
647 default:
648 assert(!"invalid ring type");
649 }
650
651 uint64_t pipeline_address = (uintptr_t)pipeline;
652 data[0] = pipeline_address;
653 data[1] = pipeline_address >> 32;
654
655 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
656 }
657
658 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
659 VkPipelineBindPoint bind_point,
660 struct radv_descriptor_set *set,
661 unsigned idx)
662 {
663 struct radv_descriptor_state *descriptors_state =
664 radv_get_descriptors_state(cmd_buffer, bind_point);
665
666 descriptors_state->sets[idx] = set;
667
668 descriptors_state->valid |= (1u << idx); /* active descriptors */
669 descriptors_state->dirty |= (1u << idx);
670 }
671
672 static void
673 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
674 VkPipelineBindPoint bind_point)
675 {
676 struct radv_descriptor_state *descriptors_state =
677 radv_get_descriptors_state(cmd_buffer, bind_point);
678 struct radv_device *device = cmd_buffer->device;
679 uint32_t data[MAX_SETS * 2] = {};
680 uint64_t va;
681 unsigned i;
682 va = radv_buffer_get_va(device->trace_bo) + 24;
683
684 for_each_bit(i, descriptors_state->valid) {
685 struct radv_descriptor_set *set = descriptors_state->sets[i];
686 data[i * 2] = (uint64_t)(uintptr_t)set;
687 data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
688 }
689
690 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
691 }
692
693 struct radv_userdata_info *
694 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
695 gl_shader_stage stage,
696 int idx)
697 {
698 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
699 return &shader->info.user_sgprs_locs.shader_data[idx];
700 }
701
702 static void
703 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
704 struct radv_pipeline *pipeline,
705 gl_shader_stage stage,
706 int idx, uint64_t va)
707 {
708 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
709 uint32_t base_reg = pipeline->user_data_0[stage];
710 if (loc->sgpr_idx == -1)
711 return;
712
713 assert(loc->num_sgprs == 1);
714
715 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
716 base_reg + loc->sgpr_idx * 4, va, false);
717 }
718
719 static void
720 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
721 struct radv_pipeline *pipeline,
722 struct radv_descriptor_state *descriptors_state,
723 gl_shader_stage stage)
724 {
725 struct radv_device *device = cmd_buffer->device;
726 struct radeon_cmdbuf *cs = cmd_buffer->cs;
727 uint32_t sh_base = pipeline->user_data_0[stage];
728 struct radv_userdata_locations *locs =
729 &pipeline->shaders[stage]->info.user_sgprs_locs;
730 unsigned mask = locs->descriptor_sets_enabled;
731
732 mask &= descriptors_state->dirty & descriptors_state->valid;
733
734 while (mask) {
735 int start, count;
736
737 u_bit_scan_consecutive_range(&mask, &start, &count);
738
739 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
740 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
741
742 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
743 for (int i = 0; i < count; i++) {
744 struct radv_descriptor_set *set =
745 descriptors_state->sets[start + i];
746
747 radv_emit_shader_pointer_body(device, cs, set->va, true);
748 }
749 }
750 }
751
752 /**
753 * Convert the user sample locations to hardware sample locations (the values
754 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
755 */
756 static void
757 radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
758 uint32_t x, uint32_t y, VkOffset2D *sample_locs)
759 {
760 uint32_t x_offset = x % state->grid_size.width;
761 uint32_t y_offset = y % state->grid_size.height;
762 uint32_t num_samples = (uint32_t)state->per_pixel;
763 VkSampleLocationEXT *user_locs;
764 uint32_t pixel_offset;
765
766 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
767
768 assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
769 user_locs = &state->locations[pixel_offset];
770
771 for (uint32_t i = 0; i < num_samples; i++) {
772 float shifted_pos_x = user_locs[i].x - 0.5;
773 float shifted_pos_y = user_locs[i].y - 0.5;
774
775 int32_t scaled_pos_x = floorf(shifted_pos_x * 16);
776 int32_t scaled_pos_y = floorf(shifted_pos_y * 16);
777
778 sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
779 sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
780 }
781 }
782
783 /**
784 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
785 * locations.
786 */
787 static void
788 radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
789 uint32_t *sample_locs_pixel)
790 {
791 for (uint32_t i = 0; i < num_samples; i++) {
792 uint32_t sample_reg_idx = i / 4;
793 uint32_t sample_loc_idx = i % 4;
794 int32_t pos_x = sample_locs[i].x;
795 int32_t pos_y = sample_locs[i].y;
796
797 uint32_t shift_x = 8 * sample_loc_idx;
798 uint32_t shift_y = shift_x + 4;
799
800 sample_locs_pixel[sample_reg_idx] |= (pos_x & 0xf) << shift_x;
801 sample_locs_pixel[sample_reg_idx] |= (pos_y & 0xf) << shift_y;
802 }
803 }
804
805 /**
806 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
807 * sample locations.
808 */
809 static uint64_t
810 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer,
811 VkOffset2D *sample_locs,
812 uint32_t num_samples)
813 {
814 uint32_t centroid_priorities[num_samples];
815 uint32_t sample_mask = num_samples - 1;
816 uint32_t distances[num_samples];
817 uint64_t centroid_priority = 0;
818
819 /* Compute the distances from center for each sample. */
820 for (int i = 0; i < num_samples; i++) {
821 distances[i] = (sample_locs[i].x * sample_locs[i].x) +
822 (sample_locs[i].y * sample_locs[i].y);
823 }
824
825 /* Compute the centroid priorities by looking at the distances array. */
826 for (int i = 0; i < num_samples; i++) {
827 uint32_t min_idx = 0;
828
829 for (int j = 1; j < num_samples; j++) {
830 if (distances[j] < distances[min_idx])
831 min_idx = j;
832 }
833
834 centroid_priorities[i] = min_idx;
835 distances[min_idx] = 0xffffffff;
836 }
837
838 /* Compute the final centroid priority. */
839 for (int i = 0; i < 8; i++) {
840 centroid_priority |=
841 centroid_priorities[i & sample_mask] << (i * 4);
842 }
843
844 return centroid_priority << 32 | centroid_priority;
845 }
846
847 /**
848 * Emit the sample locations that are specified with VK_EXT_sample_locations.
849 */
850 static void
851 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
852 {
853 struct radv_sample_locations_state *sample_location =
854 &cmd_buffer->state.dynamic.sample_location;
855 uint32_t num_samples = (uint32_t)sample_location->per_pixel;
856 struct radeon_cmdbuf *cs = cmd_buffer->cs;
857 uint32_t sample_locs_pixel[4][2] = {};
858 VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
859 uint32_t max_sample_dist = 0;
860 uint64_t centroid_priority;
861
862 if (!cmd_buffer->state.dynamic.sample_location.count)
863 return;
864
865 /* Convert the user sample locations to hardware sample locations. */
866 radv_convert_user_sample_locs(sample_location, 0, 0, sample_locs[0]);
867 radv_convert_user_sample_locs(sample_location, 1, 0, sample_locs[1]);
868 radv_convert_user_sample_locs(sample_location, 0, 1, sample_locs[2]);
869 radv_convert_user_sample_locs(sample_location, 1, 1, sample_locs[3]);
870
871 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
872 for (uint32_t i = 0; i < 4; i++) {
873 radv_compute_sample_locs_pixel(num_samples, sample_locs[i],
874 sample_locs_pixel[i]);
875 }
876
877 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
878 centroid_priority =
879 radv_compute_centroid_priority(cmd_buffer, sample_locs[0],
880 num_samples);
881
882 /* Compute the maximum sample distance from the specified locations. */
883 for (unsigned i = 0; i < 4; ++i) {
884 for (uint32_t j = 0; j < num_samples; j++) {
885 VkOffset2D offset = sample_locs[i][j];
886 max_sample_dist = MAX2(max_sample_dist,
887 MAX2(abs(offset.x), abs(offset.y)));
888 }
889 }
890
891 /* Emit the specified user sample locations. */
892 switch (num_samples) {
893 case 2:
894 case 4:
895 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
896 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
897 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
898 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
899 break;
900 case 8:
901 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
902 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
903 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
904 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
905 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs_pixel[0][1]);
906 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs_pixel[1][1]);
907 radeon_set_context_reg(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs_pixel[2][1]);
908 radeon_set_context_reg(cs, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs_pixel[3][1]);
909 break;
910 default:
911 unreachable("invalid number of samples");
912 }
913
914 /* Emit the maximum sample distance and the centroid priority. */
915 radeon_set_context_reg_rmw(cs, R_028BE0_PA_SC_AA_CONFIG,
916 S_028BE0_MAX_SAMPLE_DIST(max_sample_dist),
917 ~C_028BE0_MAX_SAMPLE_DIST);
918
919 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
920 radeon_emit(cs, centroid_priority);
921 radeon_emit(cs, centroid_priority >> 32);
922
923 /* GFX9: Flush DFSM when the AA mode changes. */
924 if (cmd_buffer->device->dfsm_allowed) {
925 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
926 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
927 }
928
929 cmd_buffer->state.context_roll_without_scissor_emitted = true;
930 }
931
932 static void
933 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
934 struct radv_pipeline *pipeline,
935 gl_shader_stage stage,
936 int idx, int count, uint32_t *values)
937 {
938 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
939 uint32_t base_reg = pipeline->user_data_0[stage];
940 if (loc->sgpr_idx == -1)
941 return;
942
943 assert(loc->num_sgprs == count);
944
945 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
946 radeon_emit_array(cmd_buffer->cs, values, count);
947 }
948
949 static void
950 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
951 struct radv_pipeline *pipeline)
952 {
953 int num_samples = pipeline->graphics.ms.num_samples;
954 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
955
956 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.needs_sample_positions)
957 cmd_buffer->sample_positions_needed = true;
958
959 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
960 return;
961
962 radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
963
964 cmd_buffer->state.context_roll_without_scissor_emitted = true;
965 }
966
967 static void
968 radv_update_binning_state(struct radv_cmd_buffer *cmd_buffer,
969 struct radv_pipeline *pipeline)
970 {
971 const struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
972
973
974 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
975 return;
976
977 if (old_pipeline &&
978 old_pipeline->graphics.binning.pa_sc_binner_cntl_0 == pipeline->graphics.binning.pa_sc_binner_cntl_0 &&
979 old_pipeline->graphics.binning.db_dfsm_control == pipeline->graphics.binning.db_dfsm_control)
980 return;
981
982 bool binning_flush = false;
983 if (cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA12 ||
984 cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA20 ||
985 cmd_buffer->device->physical_device->rad_info.family == CHIP_RAVEN2 ||
986 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
987 binning_flush = !old_pipeline ||
988 G_028C44_BINNING_MODE(old_pipeline->graphics.binning.pa_sc_binner_cntl_0) !=
989 G_028C44_BINNING_MODE(pipeline->graphics.binning.pa_sc_binner_cntl_0);
990 }
991
992 radeon_set_context_reg(cmd_buffer->cs, R_028C44_PA_SC_BINNER_CNTL_0,
993 pipeline->graphics.binning.pa_sc_binner_cntl_0 |
994 S_028C44_FLUSH_ON_BINNING_TRANSITION(!!binning_flush));
995
996 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
997 radeon_set_context_reg(cmd_buffer->cs, R_028038_DB_DFSM_CONTROL,
998 pipeline->graphics.binning.db_dfsm_control);
999 } else {
1000 radeon_set_context_reg(cmd_buffer->cs, R_028060_DB_DFSM_CONTROL,
1001 pipeline->graphics.binning.db_dfsm_control);
1002 }
1003
1004 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1005 }
1006
1007
1008 static void
1009 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
1010 struct radv_shader_variant *shader)
1011 {
1012 uint64_t va;
1013
1014 if (!shader)
1015 return;
1016
1017 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
1018
1019 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
1020 }
1021
1022 static void
1023 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
1024 struct radv_pipeline *pipeline,
1025 bool vertex_stage_only)
1026 {
1027 struct radv_cmd_state *state = &cmd_buffer->state;
1028 uint32_t mask = state->prefetch_L2_mask;
1029
1030 if (vertex_stage_only) {
1031 /* Fast prefetch path for starting draws as soon as possible.
1032 */
1033 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
1034 RADV_PREFETCH_VBO_DESCRIPTORS);
1035 }
1036
1037 if (mask & RADV_PREFETCH_VS)
1038 radv_emit_shader_prefetch(cmd_buffer,
1039 pipeline->shaders[MESA_SHADER_VERTEX]);
1040
1041 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
1042 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
1043
1044 if (mask & RADV_PREFETCH_TCS)
1045 radv_emit_shader_prefetch(cmd_buffer,
1046 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
1047
1048 if (mask & RADV_PREFETCH_TES)
1049 radv_emit_shader_prefetch(cmd_buffer,
1050 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
1051
1052 if (mask & RADV_PREFETCH_GS) {
1053 radv_emit_shader_prefetch(cmd_buffer,
1054 pipeline->shaders[MESA_SHADER_GEOMETRY]);
1055 if (radv_pipeline_has_gs_copy_shader(pipeline))
1056 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
1057 }
1058
1059 if (mask & RADV_PREFETCH_PS)
1060 radv_emit_shader_prefetch(cmd_buffer,
1061 pipeline->shaders[MESA_SHADER_FRAGMENT]);
1062
1063 state->prefetch_L2_mask &= ~mask;
1064 }
1065
1066 static void
1067 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
1068 {
1069 if (!cmd_buffer->device->physical_device->rad_info.rbplus_allowed)
1070 return;
1071
1072 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1073 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1074
1075 unsigned sx_ps_downconvert = 0;
1076 unsigned sx_blend_opt_epsilon = 0;
1077 unsigned sx_blend_opt_control = 0;
1078
1079 if (!cmd_buffer->state.attachments || !subpass)
1080 return;
1081
1082 for (unsigned i = 0; i < subpass->color_count; ++i) {
1083 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1084 /* We don't set the DISABLE bits, because the HW can't have holes,
1085 * so the SPI color format is set to 32-bit 1-component. */
1086 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1087 continue;
1088 }
1089
1090 int idx = subpass->color_attachments[i].attachment;
1091 struct radv_color_buffer_info *cb = &cmd_buffer->state.attachments[idx].cb;
1092
1093 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
1094 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
1095 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
1096 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
1097
1098 bool has_alpha, has_rgb;
1099
1100 /* Set if RGB and A are present. */
1101 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
1102
1103 if (format == V_028C70_COLOR_8 ||
1104 format == V_028C70_COLOR_16 ||
1105 format == V_028C70_COLOR_32)
1106 has_rgb = !has_alpha;
1107 else
1108 has_rgb = true;
1109
1110 /* Check the colormask and export format. */
1111 if (!(colormask & 0x7))
1112 has_rgb = false;
1113 if (!(colormask & 0x8))
1114 has_alpha = false;
1115
1116 if (spi_format == V_028714_SPI_SHADER_ZERO) {
1117 has_rgb = false;
1118 has_alpha = false;
1119 }
1120
1121 /* Disable value checking for disabled channels. */
1122 if (!has_rgb)
1123 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1124 if (!has_alpha)
1125 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1126
1127 /* Enable down-conversion for 32bpp and smaller formats. */
1128 switch (format) {
1129 case V_028C70_COLOR_8:
1130 case V_028C70_COLOR_8_8:
1131 case V_028C70_COLOR_8_8_8_8:
1132 /* For 1 and 2-channel formats, use the superset thereof. */
1133 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
1134 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1135 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1136 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
1137 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
1138 }
1139 break;
1140
1141 case V_028C70_COLOR_5_6_5:
1142 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1143 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
1144 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
1145 }
1146 break;
1147
1148 case V_028C70_COLOR_1_5_5_5:
1149 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1150 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
1151 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
1152 }
1153 break;
1154
1155 case V_028C70_COLOR_4_4_4_4:
1156 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1157 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
1158 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
1159 }
1160 break;
1161
1162 case V_028C70_COLOR_32:
1163 if (swap == V_028C70_SWAP_STD &&
1164 spi_format == V_028714_SPI_SHADER_32_R)
1165 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1166 else if (swap == V_028C70_SWAP_ALT_REV &&
1167 spi_format == V_028714_SPI_SHADER_32_AR)
1168 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
1169 break;
1170
1171 case V_028C70_COLOR_16:
1172 case V_028C70_COLOR_16_16:
1173 /* For 1-channel formats, use the superset thereof. */
1174 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
1175 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
1176 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1177 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1178 if (swap == V_028C70_SWAP_STD ||
1179 swap == V_028C70_SWAP_STD_REV)
1180 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
1181 else
1182 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
1183 }
1184 break;
1185
1186 case V_028C70_COLOR_10_11_11:
1187 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1188 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
1189 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
1190 }
1191 break;
1192
1193 case V_028C70_COLOR_2_10_10_10:
1194 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1195 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
1196 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
1197 }
1198 break;
1199 }
1200 }
1201
1202 /* Do not set the DISABLE bits for the unused attachments, as that
1203 * breaks dual source blending in SkQP and does not seem to improve
1204 * performance. */
1205
1206 if (sx_ps_downconvert == cmd_buffer->state.last_sx_ps_downconvert &&
1207 sx_blend_opt_epsilon == cmd_buffer->state.last_sx_blend_opt_epsilon &&
1208 sx_blend_opt_control == cmd_buffer->state.last_sx_blend_opt_control)
1209 return;
1210
1211 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
1212 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
1213 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
1214 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
1215
1216 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1217
1218 cmd_buffer->state.last_sx_ps_downconvert = sx_ps_downconvert;
1219 cmd_buffer->state.last_sx_blend_opt_epsilon = sx_blend_opt_epsilon;
1220 cmd_buffer->state.last_sx_blend_opt_control = sx_blend_opt_control;
1221 }
1222
1223 static void
1224 radv_emit_batch_break_on_new_ps(struct radv_cmd_buffer *cmd_buffer)
1225 {
1226 if (!cmd_buffer->device->pbb_allowed)
1227 return;
1228
1229 struct radv_binning_settings settings =
1230 radv_get_binning_settings(cmd_buffer->device->physical_device);
1231 bool break_for_new_ps =
1232 (!cmd_buffer->state.emitted_pipeline ||
1233 cmd_buffer->state.emitted_pipeline->shaders[MESA_SHADER_FRAGMENT] !=
1234 cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT]) &&
1235 (settings.context_states_per_bin > 1 ||
1236 settings.persistent_states_per_bin > 1);
1237 bool break_for_new_cb_target_mask =
1238 (!cmd_buffer->state.emitted_pipeline ||
1239 cmd_buffer->state.emitted_pipeline->graphics.cb_target_mask !=
1240 cmd_buffer->state.pipeline->graphics.cb_target_mask) &&
1241 settings.context_states_per_bin > 1;
1242
1243 if (!break_for_new_ps && !break_for_new_cb_target_mask)
1244 return;
1245
1246 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1247 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1248 }
1249
1250 static void
1251 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1252 {
1253 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1254
1255 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1256 return;
1257
1258 radv_update_multisample_state(cmd_buffer, pipeline);
1259 radv_update_binning_state(cmd_buffer, pipeline);
1260
1261 cmd_buffer->scratch_size_per_wave_needed = MAX2(cmd_buffer->scratch_size_per_wave_needed,
1262 pipeline->scratch_bytes_per_wave);
1263 cmd_buffer->scratch_waves_wanted = MAX2(cmd_buffer->scratch_waves_wanted,
1264 pipeline->max_waves);
1265
1266 if (!cmd_buffer->state.emitted_pipeline ||
1267 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1268 pipeline->graphics.can_use_guardband)
1269 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1270
1271 if (!cmd_buffer->state.emitted_pipeline ||
1272 cmd_buffer->state.emitted_pipeline->graphics.pa_su_sc_mode_cntl !=
1273 pipeline->graphics.pa_su_sc_mode_cntl)
1274 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_CULL_MODE |
1275 RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE;
1276
1277 if (!cmd_buffer->state.emitted_pipeline)
1278 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY;
1279
1280 if (!cmd_buffer->state.emitted_pipeline ||
1281 cmd_buffer->state.emitted_pipeline->graphics.db_depth_control !=
1282 pipeline->graphics.db_depth_control)
1283 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE |
1284 RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE |
1285 RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP |
1286 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE |
1287 RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE |
1288 RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP;
1289
1290 if (!cmd_buffer->state.emitted_pipeline)
1291 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP;
1292
1293 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
1294
1295 if (!cmd_buffer->state.emitted_pipeline ||
1296 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
1297 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
1298 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
1299 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
1300 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
1301 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1302 }
1303
1304 radv_emit_batch_break_on_new_ps(cmd_buffer);
1305
1306 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
1307 if (!pipeline->shaders[i])
1308 continue;
1309
1310 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1311 pipeline->shaders[i]->bo);
1312 }
1313
1314 if (radv_pipeline_has_gs_copy_shader(pipeline))
1315 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1316 pipeline->gs_copy_shader->bo);
1317
1318 if (unlikely(cmd_buffer->device->trace_bo))
1319 radv_save_pipeline(cmd_buffer, pipeline);
1320
1321 cmd_buffer->state.emitted_pipeline = pipeline;
1322
1323 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1324 }
1325
1326 static void
1327 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1328 {
1329 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1330 cmd_buffer->state.dynamic.viewport.viewports);
1331 }
1332
1333 static void
1334 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1335 {
1336 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1337
1338 si_write_scissors(cmd_buffer->cs, 0, count,
1339 cmd_buffer->state.dynamic.scissor.scissors,
1340 cmd_buffer->state.dynamic.viewport.viewports,
1341 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1342
1343 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1344 }
1345
1346 static void
1347 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1348 {
1349 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1350 return;
1351
1352 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1353 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1354 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1355 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1356 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1357 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1358 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1359 }
1360 }
1361
1362 static void
1363 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1364 {
1365 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1366
1367 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1368 S_028A08_WIDTH(CLAMP(width, 0, 0xFFFF)));
1369 }
1370
1371 static void
1372 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1373 {
1374 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1375
1376 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1377 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1378 }
1379
1380 static void
1381 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1382 {
1383 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1384
1385 radeon_set_context_reg_seq(cmd_buffer->cs,
1386 R_028430_DB_STENCILREFMASK, 2);
1387 radeon_emit(cmd_buffer->cs,
1388 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1389 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1390 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1391 S_028430_STENCILOPVAL(1));
1392 radeon_emit(cmd_buffer->cs,
1393 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1394 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1395 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1396 S_028434_STENCILOPVAL_BF(1));
1397 }
1398
1399 static void
1400 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1401 {
1402 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1403
1404 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1405 fui(d->depth_bounds.min));
1406 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1407 fui(d->depth_bounds.max));
1408 }
1409
1410 static void
1411 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1412 {
1413 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1414 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1415 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1416
1417
1418 radeon_set_context_reg_seq(cmd_buffer->cs,
1419 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1420 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1421 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1422 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1423 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1424 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1425 }
1426
1427 static void
1428 radv_emit_line_stipple(struct radv_cmd_buffer *cmd_buffer)
1429 {
1430 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1431 uint32_t auto_reset_cntl = 1;
1432
1433 if (d->primitive_topology == V_008958_DI_PT_LINESTRIP)
1434 auto_reset_cntl = 2;
1435
1436 radeon_set_context_reg(cmd_buffer->cs, R_028A0C_PA_SC_LINE_STIPPLE,
1437 S_028A0C_LINE_PATTERN(d->line_stipple.pattern) |
1438 S_028A0C_REPEAT_COUNT(d->line_stipple.factor - 1) |
1439 S_028A0C_AUTO_RESET_CNTL(auto_reset_cntl));
1440 }
1441
1442 static void
1443 radv_emit_culling(struct radv_cmd_buffer *cmd_buffer, uint32_t states)
1444 {
1445 unsigned pa_su_sc_mode_cntl = cmd_buffer->state.pipeline->graphics.pa_su_sc_mode_cntl;
1446 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1447
1448 if (states & RADV_CMD_DIRTY_DYNAMIC_CULL_MODE) {
1449 pa_su_sc_mode_cntl &= C_028814_CULL_FRONT;
1450 pa_su_sc_mode_cntl |= S_028814_CULL_FRONT(!!(d->cull_mode & VK_CULL_MODE_FRONT_BIT));
1451
1452 pa_su_sc_mode_cntl &= C_028814_CULL_BACK;
1453 pa_su_sc_mode_cntl |= S_028814_CULL_BACK(!!(d->cull_mode & VK_CULL_MODE_BACK_BIT));
1454 }
1455
1456 if (states & RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE) {
1457 pa_su_sc_mode_cntl &= C_028814_FACE;
1458 pa_su_sc_mode_cntl |= S_028814_FACE(d->front_face);
1459 }
1460
1461 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
1462 pa_su_sc_mode_cntl);
1463 }
1464
1465 static void
1466 radv_emit_primitive_topology(struct radv_cmd_buffer *cmd_buffer)
1467 {
1468 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1469
1470 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1471 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
1472 cmd_buffer->cs,
1473 R_030908_VGT_PRIMITIVE_TYPE, 1,
1474 d->primitive_topology);
1475 } else {
1476 radeon_set_config_reg(cmd_buffer->cs,
1477 R_008958_VGT_PRIMITIVE_TYPE,
1478 d->primitive_topology);
1479 }
1480 }
1481
1482 static void
1483 radv_emit_depth_control(struct radv_cmd_buffer *cmd_buffer, uint32_t states)
1484 {
1485 unsigned db_depth_control = cmd_buffer->state.pipeline->graphics.db_depth_control;
1486 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1487
1488 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE) {
1489 db_depth_control &= C_028800_Z_ENABLE;
1490 db_depth_control |= S_028800_Z_ENABLE(d->depth_test_enable ? 1 : 0);
1491 }
1492
1493 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE) {
1494 db_depth_control &= C_028800_Z_WRITE_ENABLE;
1495 db_depth_control |= S_028800_Z_WRITE_ENABLE(d->depth_write_enable ? 1 : 0);
1496 }
1497
1498 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP) {
1499 db_depth_control &= C_028800_ZFUNC;
1500 db_depth_control |= S_028800_ZFUNC(d->depth_compare_op);
1501 }
1502
1503 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE) {
1504 db_depth_control &= C_028800_DEPTH_BOUNDS_ENABLE;
1505 db_depth_control |= S_028800_DEPTH_BOUNDS_ENABLE(d->depth_bounds_test_enable ? 1 : 0);
1506 }
1507
1508 if (states & RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE) {
1509 db_depth_control &= C_028800_STENCIL_ENABLE;
1510 db_depth_control |= S_028800_STENCIL_ENABLE(d->stencil_test_enable ? 1 : 0);
1511
1512 db_depth_control &= C_028800_BACKFACE_ENABLE;
1513 db_depth_control |= S_028800_BACKFACE_ENABLE(d->stencil_test_enable ? 1 : 0);
1514 }
1515
1516 if (states & RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP) {
1517 db_depth_control &= C_028800_STENCILFUNC;
1518 db_depth_control |= S_028800_STENCILFUNC(d->stencil_op.front.compare_op);
1519
1520 db_depth_control &= C_028800_STENCILFUNC_BF;
1521 db_depth_control |= S_028800_STENCILFUNC_BF(d->stencil_op.back.compare_op);
1522 }
1523
1524 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL,
1525 db_depth_control);
1526 }
1527
1528 static void
1529 radv_emit_stencil_control(struct radv_cmd_buffer *cmd_buffer)
1530 {
1531 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1532
1533 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL,
1534 S_02842C_STENCILFAIL(si_translate_stencil_op(d->stencil_op.front.fail_op)) |
1535 S_02842C_STENCILZPASS(si_translate_stencil_op(d->stencil_op.front.pass_op)) |
1536 S_02842C_STENCILZFAIL(si_translate_stencil_op(d->stencil_op.front.depth_fail_op)) |
1537 S_02842C_STENCILFAIL_BF(si_translate_stencil_op(d->stencil_op.back.fail_op)) |
1538 S_02842C_STENCILZPASS_BF(si_translate_stencil_op(d->stencil_op.back.pass_op)) |
1539 S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(d->stencil_op.back.depth_fail_op)));
1540 }
1541
1542 static void
1543 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1544 int index,
1545 struct radv_color_buffer_info *cb,
1546 struct radv_image_view *iview,
1547 VkImageLayout layout,
1548 bool in_render_loop)
1549 {
1550 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
1551 uint32_t cb_color_info = cb->cb_color_info;
1552 struct radv_image *image = iview->image;
1553
1554 if (!radv_layout_dcc_compressed(cmd_buffer->device, image, layout, in_render_loop,
1555 radv_image_queue_family_mask(image,
1556 cmd_buffer->queue_family_index,
1557 cmd_buffer->queue_family_index))) {
1558 cb_color_info &= C_028C70_DCC_ENABLE;
1559 }
1560
1561 if (!radv_layout_can_fast_clear(image, layout, in_render_loop,
1562 radv_image_queue_family_mask(image,
1563 cmd_buffer->queue_family_index,
1564 cmd_buffer->queue_family_index))) {
1565 cb_color_info &= C_028C70_COMPRESSION;
1566 }
1567
1568 if (radv_image_is_tc_compat_cmask(image) &&
1569 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1570 radv_is_dcc_decompress_pipeline(cmd_buffer))) {
1571 /* If this bit is set, the FMASK decompression operation
1572 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1573 */
1574 cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
1575 }
1576
1577 if (radv_image_has_fmask(image) &&
1578 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1579 radv_is_hw_resolve_pipeline(cmd_buffer))) {
1580 /* Make sure FMASK is enabled if it has been cleared because:
1581 *
1582 * 1) it's required for FMASK_DECOMPRESS operations to avoid
1583 * GPU hangs
1584 * 2) it's necessary for CB_RESOLVE which can read compressed
1585 * FMASK data anyways.
1586 */
1587 cb_color_info |= S_028C70_COMPRESSION(1);
1588 }
1589
1590 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1591 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1592 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1593 radeon_emit(cmd_buffer->cs, 0);
1594 radeon_emit(cmd_buffer->cs, 0);
1595 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1596 radeon_emit(cmd_buffer->cs, cb_color_info);
1597 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1598 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1599 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1600 radeon_emit(cmd_buffer->cs, 0);
1601 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1602 radeon_emit(cmd_buffer->cs, 0);
1603
1604 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 1);
1605 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1606
1607 radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4,
1608 cb->cb_color_base >> 32);
1609 radeon_set_context_reg(cmd_buffer->cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + index * 4,
1610 cb->cb_color_cmask >> 32);
1611 radeon_set_context_reg(cmd_buffer->cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + index * 4,
1612 cb->cb_color_fmask >> 32);
1613 radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4,
1614 cb->cb_dcc_base >> 32);
1615 radeon_set_context_reg(cmd_buffer->cs, R_028EC0_CB_COLOR0_ATTRIB2 + index * 4,
1616 cb->cb_color_attrib2);
1617 radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4,
1618 cb->cb_color_attrib3);
1619 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1620 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1621 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1622 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1623 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1624 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1625 radeon_emit(cmd_buffer->cs, cb_color_info);
1626 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1627 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1628 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1629 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1630 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1631 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1632
1633 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1634 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1635 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1636
1637 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1638 cb->cb_mrt_epitch);
1639 } else {
1640 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1641 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1642 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1643 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1644 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1645 radeon_emit(cmd_buffer->cs, cb_color_info);
1646 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1647 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1648 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1649 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1650 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1651 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1652
1653 if (is_vi) { /* DCC BASE */
1654 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1655 }
1656 }
1657
1658 if (radv_dcc_enabled(image, iview->base_mip)) {
1659 /* Drawing with DCC enabled also compresses colorbuffers. */
1660 VkImageSubresourceRange range = {
1661 .aspectMask = iview->aspect_mask,
1662 .baseMipLevel = iview->base_mip,
1663 .levelCount = iview->level_count,
1664 .baseArrayLayer = iview->base_layer,
1665 .layerCount = iview->layer_count,
1666 };
1667
1668 radv_update_dcc_metadata(cmd_buffer, image, &range, true);
1669 }
1670 }
1671
1672 static void
1673 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1674 struct radv_ds_buffer_info *ds,
1675 const struct radv_image_view *iview,
1676 VkImageLayout layout,
1677 bool in_render_loop, bool requires_cond_exec)
1678 {
1679 const struct radv_image *image = iview->image;
1680 uint32_t db_z_info = ds->db_z_info;
1681 uint32_t db_z_info_reg;
1682
1683 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug ||
1684 !radv_image_is_tc_compat_htile(image))
1685 return;
1686
1687 if (!radv_layout_is_htile_compressed(image, layout, in_render_loop,
1688 radv_image_queue_family_mask(image,
1689 cmd_buffer->queue_family_index,
1690 cmd_buffer->queue_family_index))) {
1691 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1692 }
1693
1694 db_z_info &= C_028040_ZRANGE_PRECISION;
1695
1696 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1697 db_z_info_reg = R_028038_DB_Z_INFO;
1698 } else {
1699 db_z_info_reg = R_028040_DB_Z_INFO;
1700 }
1701
1702 /* When we don't know the last fast clear value we need to emit a
1703 * conditional packet that will eventually skip the following
1704 * SET_CONTEXT_REG packet.
1705 */
1706 if (requires_cond_exec) {
1707 uint64_t va = radv_get_tc_compat_zrange_va(image, iview->base_mip);
1708
1709 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1710 radeon_emit(cmd_buffer->cs, va);
1711 radeon_emit(cmd_buffer->cs, va >> 32);
1712 radeon_emit(cmd_buffer->cs, 0);
1713 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1714 }
1715
1716 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1717 }
1718
1719 static void
1720 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1721 struct radv_ds_buffer_info *ds,
1722 struct radv_image_view *iview,
1723 VkImageLayout layout,
1724 bool in_render_loop)
1725 {
1726 const struct radv_image *image = iview->image;
1727 uint32_t db_z_info = ds->db_z_info;
1728 uint32_t db_stencil_info = ds->db_stencil_info;
1729
1730 if (!radv_layout_is_htile_compressed(image, layout, in_render_loop,
1731 radv_image_queue_family_mask(image,
1732 cmd_buffer->queue_family_index,
1733 cmd_buffer->queue_family_index))) {
1734 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1735 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1736 }
1737
1738 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1739 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1740
1741 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1742 /* Enable HTILE caching in L2 for small chips. */
1743 unsigned meta_write_policy, meta_read_policy;
1744 /* TODO: investigate whether LRU improves performance on other chips too */
1745 if (cmd_buffer->device->physical_device->rad_info.num_render_backends <= 4) {
1746 meta_write_policy = V_02807C_CACHE_LRU_WR; /* cache writes */
1747 meta_read_policy = V_02807C_CACHE_LRU_RD; /* cache reads */
1748 } else {
1749 meta_write_policy = V_02807C_CACHE_STREAM; /* write combine */
1750 meta_read_policy = V_02807C_CACHE_NOA; /* don't cache reads */
1751 }
1752
1753 bool zs_big_page = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10_3 &&
1754 (image->alignment % (64 * 1024) == 0);
1755
1756 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1757 radeon_set_context_reg(cmd_buffer->cs, R_02801C_DB_DEPTH_SIZE_XY, ds->db_depth_size);
1758
1759 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 7);
1760 radeon_emit(cmd_buffer->cs, S_02803C_RESOURCE_LEVEL(1));
1761 radeon_emit(cmd_buffer->cs, db_z_info);
1762 radeon_emit(cmd_buffer->cs, db_stencil_info);
1763 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1764 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1765 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1766 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1767
1768 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_READ_BASE_HI, 6);
1769 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1770 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1771 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1772 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1773 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1774 radeon_emit(cmd_buffer->cs,
1775 S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM) |
1776 S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM) |
1777 S_02807C_HTILE_WR_POLICY(meta_write_policy) |
1778 S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM) |
1779 S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA) |
1780 S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA) |
1781 S_02807C_HTILE_RD_POLICY(meta_read_policy) |
1782 S_02807C_Z_BIG_PAGE(zs_big_page) |
1783 S_02807C_S_BIG_PAGE(zs_big_page));
1784 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1785 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1786 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1787 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1788 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1789
1790 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1791 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1792 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1793 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1794 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1795 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1796 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1797 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1798 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1799 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1800 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1801
1802 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1803 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1804 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1805 } else {
1806 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1807
1808 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1809 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1810 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1811 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1812 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1813 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1814 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1815 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1816 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1817 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1818
1819 }
1820
1821 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1822 radv_update_zrange_precision(cmd_buffer, ds, iview, layout,
1823 in_render_loop, true);
1824
1825 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1826 ds->pa_su_poly_offset_db_fmt_cntl);
1827 }
1828
1829 /**
1830 * Update the fast clear depth/stencil values if the image is bound as a
1831 * depth/stencil buffer.
1832 */
1833 static void
1834 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1835 const struct radv_image_view *iview,
1836 VkClearDepthStencilValue ds_clear_value,
1837 VkImageAspectFlags aspects)
1838 {
1839 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1840 const struct radv_image *image = iview->image;
1841 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1842 uint32_t att_idx;
1843
1844 if (!cmd_buffer->state.attachments || !subpass)
1845 return;
1846
1847 if (!subpass->depth_stencil_attachment)
1848 return;
1849
1850 att_idx = subpass->depth_stencil_attachment->attachment;
1851 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1852 return;
1853
1854 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1855 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1856 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1857 radeon_emit(cs, ds_clear_value.stencil);
1858 radeon_emit(cs, fui(ds_clear_value.depth));
1859 } else if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1860 radeon_set_context_reg_seq(cs, R_02802C_DB_DEPTH_CLEAR, 1);
1861 radeon_emit(cs, fui(ds_clear_value.depth));
1862 } else {
1863 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1864 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 1);
1865 radeon_emit(cs, ds_clear_value.stencil);
1866 }
1867
1868 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1869 * only needed when clearing Z to 0.0.
1870 */
1871 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1872 ds_clear_value.depth == 0.0) {
1873 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1874 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
1875
1876 radv_update_zrange_precision(cmd_buffer, &cmd_buffer->state.attachments[att_idx].ds,
1877 iview, layout, in_render_loop, false);
1878 }
1879
1880 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1881 }
1882
1883 /**
1884 * Set the clear depth/stencil values to the image's metadata.
1885 */
1886 static void
1887 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1888 struct radv_image *image,
1889 const VkImageSubresourceRange *range,
1890 VkClearDepthStencilValue ds_clear_value,
1891 VkImageAspectFlags aspects)
1892 {
1893 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1894 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel);
1895 uint32_t level_count = radv_get_levelCount(image, range);
1896
1897 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1898 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1899 /* Use the fastest way when both aspects are used. */
1900 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + 2 * level_count, cmd_buffer->state.predicating));
1901 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1902 S_370_WR_CONFIRM(1) |
1903 S_370_ENGINE_SEL(V_370_PFP));
1904 radeon_emit(cs, va);
1905 radeon_emit(cs, va >> 32);
1906
1907 for (uint32_t l = 0; l < level_count; l++) {
1908 radeon_emit(cs, ds_clear_value.stencil);
1909 radeon_emit(cs, fui(ds_clear_value.depth));
1910 }
1911 } else {
1912 /* Otherwise we need one WRITE_DATA packet per level. */
1913 for (uint32_t l = 0; l < level_count; l++) {
1914 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel + l);
1915 unsigned value;
1916
1917 if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1918 value = fui(ds_clear_value.depth);
1919 va += 4;
1920 } else {
1921 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1922 value = ds_clear_value.stencil;
1923 }
1924
1925 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1926 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1927 S_370_WR_CONFIRM(1) |
1928 S_370_ENGINE_SEL(V_370_PFP));
1929 radeon_emit(cs, va);
1930 radeon_emit(cs, va >> 32);
1931 radeon_emit(cs, value);
1932 }
1933 }
1934 }
1935
1936 /**
1937 * Update the TC-compat metadata value for this image.
1938 */
1939 static void
1940 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1941 struct radv_image *image,
1942 const VkImageSubresourceRange *range,
1943 uint32_t value)
1944 {
1945 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1946
1947 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug)
1948 return;
1949
1950 uint64_t va = radv_get_tc_compat_zrange_va(image, range->baseMipLevel);
1951 uint32_t level_count = radv_get_levelCount(image, range);
1952
1953 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + level_count, cmd_buffer->state.predicating));
1954 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1955 S_370_WR_CONFIRM(1) |
1956 S_370_ENGINE_SEL(V_370_PFP));
1957 radeon_emit(cs, va);
1958 radeon_emit(cs, va >> 32);
1959
1960 for (uint32_t l = 0; l < level_count; l++)
1961 radeon_emit(cs, value);
1962 }
1963
1964 static void
1965 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1966 const struct radv_image_view *iview,
1967 VkClearDepthStencilValue ds_clear_value)
1968 {
1969 VkImageSubresourceRange range = {
1970 .aspectMask = iview->aspect_mask,
1971 .baseMipLevel = iview->base_mip,
1972 .levelCount = iview->level_count,
1973 .baseArrayLayer = iview->base_layer,
1974 .layerCount = iview->layer_count,
1975 };
1976 uint32_t cond_val;
1977
1978 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1979 * depth clear value is 0.0f.
1980 */
1981 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1982
1983 radv_set_tc_compat_zrange_metadata(cmd_buffer, iview->image, &range,
1984 cond_val);
1985 }
1986
1987 /**
1988 * Update the clear depth/stencil values for this image.
1989 */
1990 void
1991 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1992 const struct radv_image_view *iview,
1993 VkClearDepthStencilValue ds_clear_value,
1994 VkImageAspectFlags aspects)
1995 {
1996 VkImageSubresourceRange range = {
1997 .aspectMask = iview->aspect_mask,
1998 .baseMipLevel = iview->base_mip,
1999 .levelCount = iview->level_count,
2000 .baseArrayLayer = iview->base_layer,
2001 .layerCount = iview->layer_count,
2002 };
2003 struct radv_image *image = iview->image;
2004
2005 assert(radv_image_has_htile(image));
2006
2007 radv_set_ds_clear_metadata(cmd_buffer, iview->image, &range,
2008 ds_clear_value, aspects);
2009
2010 if (radv_image_is_tc_compat_htile(image) &&
2011 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
2012 radv_update_tc_compat_zrange_metadata(cmd_buffer, iview,
2013 ds_clear_value);
2014 }
2015
2016 radv_update_bound_fast_clear_ds(cmd_buffer, iview, ds_clear_value,
2017 aspects);
2018 }
2019
2020 /**
2021 * Load the clear depth/stencil values from the image's metadata.
2022 */
2023 static void
2024 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
2025 const struct radv_image_view *iview)
2026 {
2027 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2028 const struct radv_image *image = iview->image;
2029 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
2030 uint64_t va = radv_get_ds_clear_value_va(image, iview->base_mip);
2031 unsigned reg_offset = 0, reg_count = 0;
2032
2033 if (!radv_image_has_htile(image))
2034 return;
2035
2036 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
2037 ++reg_count;
2038 } else {
2039 ++reg_offset;
2040 va += 4;
2041 }
2042 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
2043 ++reg_count;
2044
2045 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
2046
2047 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
2048 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG_INDEX, 3, 0));
2049 radeon_emit(cs, va);
2050 radeon_emit(cs, va >> 32);
2051 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
2052 radeon_emit(cs, reg_count);
2053 } else {
2054 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2055 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2056 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2057 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
2058 radeon_emit(cs, va);
2059 radeon_emit(cs, va >> 32);
2060 radeon_emit(cs, reg >> 2);
2061 radeon_emit(cs, 0);
2062
2063 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
2064 radeon_emit(cs, 0);
2065 }
2066 }
2067
2068 /*
2069 * With DCC some colors don't require CMASK elimination before being
2070 * used as a texture. This sets a predicate value to determine if the
2071 * cmask eliminate is required.
2072 */
2073 void
2074 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
2075 struct radv_image *image,
2076 const VkImageSubresourceRange *range, bool value)
2077 {
2078 uint64_t pred_val = value;
2079 uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
2080 uint32_t level_count = radv_get_levelCount(image, range);
2081 uint32_t count = 2 * level_count;
2082
2083 assert(radv_dcc_enabled(image, range->baseMipLevel));
2084
2085 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
2086 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
2087 S_370_WR_CONFIRM(1) |
2088 S_370_ENGINE_SEL(V_370_PFP));
2089 radeon_emit(cmd_buffer->cs, va);
2090 radeon_emit(cmd_buffer->cs, va >> 32);
2091
2092 for (uint32_t l = 0; l < level_count; l++) {
2093 radeon_emit(cmd_buffer->cs, pred_val);
2094 radeon_emit(cmd_buffer->cs, pred_val >> 32);
2095 }
2096 }
2097
2098 /**
2099 * Update the DCC predicate to reflect the compression state.
2100 */
2101 void
2102 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
2103 struct radv_image *image,
2104 const VkImageSubresourceRange *range, bool value)
2105 {
2106 uint64_t pred_val = value;
2107 uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
2108 uint32_t level_count = radv_get_levelCount(image, range);
2109 uint32_t count = 2 * level_count;
2110
2111 assert(radv_dcc_enabled(image, range->baseMipLevel));
2112
2113 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
2114 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
2115 S_370_WR_CONFIRM(1) |
2116 S_370_ENGINE_SEL(V_370_PFP));
2117 radeon_emit(cmd_buffer->cs, va);
2118 radeon_emit(cmd_buffer->cs, va >> 32);
2119
2120 for (uint32_t l = 0; l < level_count; l++) {
2121 radeon_emit(cmd_buffer->cs, pred_val);
2122 radeon_emit(cmd_buffer->cs, pred_val >> 32);
2123 }
2124 }
2125
2126 /**
2127 * Update the fast clear color values if the image is bound as a color buffer.
2128 */
2129 static void
2130 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
2131 struct radv_image *image,
2132 int cb_idx,
2133 uint32_t color_values[2])
2134 {
2135 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2136 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2137 uint32_t att_idx;
2138
2139 if (!cmd_buffer->state.attachments || !subpass)
2140 return;
2141
2142 att_idx = subpass->color_attachments[cb_idx].attachment;
2143 if (att_idx == VK_ATTACHMENT_UNUSED)
2144 return;
2145
2146 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
2147 return;
2148
2149 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
2150 radeon_emit(cs, color_values[0]);
2151 radeon_emit(cs, color_values[1]);
2152
2153 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2154 }
2155
2156 /**
2157 * Set the clear color values to the image's metadata.
2158 */
2159 static void
2160 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
2161 struct radv_image *image,
2162 const VkImageSubresourceRange *range,
2163 uint32_t color_values[2])
2164 {
2165 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2166 uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
2167 uint32_t level_count = radv_get_levelCount(image, range);
2168 uint32_t count = 2 * level_count;
2169
2170 assert(radv_image_has_cmask(image) ||
2171 radv_dcc_enabled(image, range->baseMipLevel));
2172
2173 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
2174 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
2175 S_370_WR_CONFIRM(1) |
2176 S_370_ENGINE_SEL(V_370_PFP));
2177 radeon_emit(cs, va);
2178 radeon_emit(cs, va >> 32);
2179
2180 for (uint32_t l = 0; l < level_count; l++) {
2181 radeon_emit(cs, color_values[0]);
2182 radeon_emit(cs, color_values[1]);
2183 }
2184 }
2185
2186 /**
2187 * Update the clear color values for this image.
2188 */
2189 void
2190 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
2191 const struct radv_image_view *iview,
2192 int cb_idx,
2193 uint32_t color_values[2])
2194 {
2195 struct radv_image *image = iview->image;
2196 VkImageSubresourceRange range = {
2197 .aspectMask = iview->aspect_mask,
2198 .baseMipLevel = iview->base_mip,
2199 .levelCount = iview->level_count,
2200 .baseArrayLayer = iview->base_layer,
2201 .layerCount = iview->layer_count,
2202 };
2203
2204 assert(radv_image_has_cmask(image) ||
2205 radv_dcc_enabled(image, iview->base_mip));
2206
2207 radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
2208
2209 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
2210 color_values);
2211 }
2212
2213 /**
2214 * Load the clear color values from the image's metadata.
2215 */
2216 static void
2217 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
2218 struct radv_image_view *iview,
2219 int cb_idx)
2220 {
2221 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2222 struct radv_image *image = iview->image;
2223 uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
2224
2225 if (!radv_image_has_cmask(image) &&
2226 !radv_dcc_enabled(image, iview->base_mip))
2227 return;
2228
2229 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
2230
2231 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
2232 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG_INDEX, 3, cmd_buffer->state.predicating));
2233 radeon_emit(cs, va);
2234 radeon_emit(cs, va >> 32);
2235 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
2236 radeon_emit(cs, 2);
2237 } else {
2238 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
2239 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2240 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2241 COPY_DATA_COUNT_SEL);
2242 radeon_emit(cs, va);
2243 radeon_emit(cs, va >> 32);
2244 radeon_emit(cs, reg >> 2);
2245 radeon_emit(cs, 0);
2246
2247 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
2248 radeon_emit(cs, 0);
2249 }
2250 }
2251
2252 static void
2253 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
2254 {
2255 int i;
2256 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
2257 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2258 bool color_big_page = true;
2259
2260 /* this may happen for inherited secondary recording */
2261 if (!framebuffer)
2262 return;
2263
2264 for (i = 0; i < 8; ++i) {
2265 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
2266 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2267 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2268 continue;
2269 }
2270
2271 int idx = subpass->color_attachments[i].attachment;
2272 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
2273 VkImageLayout layout = subpass->color_attachments[i].layout;
2274 bool in_render_loop = subpass->color_attachments[i].in_render_loop;
2275
2276 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, iview->bo);
2277
2278 assert(iview->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
2279 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
2280 radv_emit_fb_color_state(cmd_buffer, i, &cmd_buffer->state.attachments[idx].cb, iview, layout, in_render_loop);
2281
2282 radv_load_color_clear_metadata(cmd_buffer, iview, i);
2283
2284 /* BIG_PAGE is an optimization that can only be enabled if all
2285 * color targets are compatible.
2286 */
2287 color_big_page &= cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10_3 &&
2288 (iview->image->alignment % (64 * 1024) == 0);
2289 }
2290
2291 if (subpass->depth_stencil_attachment) {
2292 int idx = subpass->depth_stencil_attachment->attachment;
2293 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
2294 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
2295 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
2296 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, cmd_buffer->state.attachments[idx].iview->bo);
2297
2298 radv_emit_fb_ds_state(cmd_buffer, &cmd_buffer->state.attachments[idx].ds, iview, layout, in_render_loop);
2299
2300 if (cmd_buffer->state.attachments[idx].ds.offset_scale != cmd_buffer->state.offset_scale) {
2301 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2302 cmd_buffer->state.offset_scale = cmd_buffer->state.attachments[idx].ds.offset_scale;
2303 }
2304 radv_load_ds_clear_metadata(cmd_buffer, iview);
2305 } else {
2306 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9)
2307 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
2308 else
2309 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
2310
2311 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
2312 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
2313 }
2314 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2315 S_028208_BR_X(framebuffer->width) |
2316 S_028208_BR_Y(framebuffer->height));
2317
2318 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
2319 bool disable_constant_encode =
2320 cmd_buffer->device->physical_device->rad_info.has_dcc_constant_encode;
2321 enum chip_class chip_class =
2322 cmd_buffer->device->physical_device->rad_info.chip_class;
2323 uint8_t watermark = chip_class >= GFX10 ? 6 : 4;
2324
2325 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
2326 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class <= GFX9) |
2327 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
2328 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
2329 }
2330
2331 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2332 /* Enable CMASK/FMASK/DCC caching in L2 for small chips. */
2333 unsigned meta_write_policy, meta_read_policy;
2334 /* TODO: investigate whether LRU improves performance on other chips too */
2335 if (cmd_buffer->device->physical_device->rad_info.num_render_backends <= 4) {
2336 meta_write_policy = V_02807C_CACHE_LRU_WR; /* cache writes */
2337 meta_read_policy = V_02807C_CACHE_LRU_RD; /* cache reads */
2338 } else {
2339 meta_write_policy = V_02807C_CACHE_STREAM; /* write combine */
2340 meta_read_policy = V_02807C_CACHE_NOA; /* don't cache reads */
2341 }
2342
2343 radeon_set_context_reg(cmd_buffer->cs, R_028410_CB_RMI_GL2_CACHE_CONTROL,
2344 S_028410_CMASK_WR_POLICY(meta_write_policy) |
2345 S_028410_FMASK_WR_POLICY(meta_write_policy) |
2346 S_028410_DCC_WR_POLICY(meta_write_policy) |
2347 S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM) |
2348 S_028410_CMASK_RD_POLICY(meta_read_policy) |
2349 S_028410_FMASK_RD_POLICY(meta_read_policy) |
2350 S_028410_DCC_RD_POLICY(meta_read_policy) |
2351 S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA) |
2352 S_028410_FMASK_BIG_PAGE(color_big_page) |
2353 S_028410_COLOR_BIG_PAGE(color_big_page));
2354 }
2355
2356 if (cmd_buffer->device->dfsm_allowed) {
2357 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2358 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
2359 }
2360
2361 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
2362 }
2363
2364 static void
2365 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer, bool indirect)
2366 {
2367 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2368 struct radv_cmd_state *state = &cmd_buffer->state;
2369
2370 if (state->index_type != state->last_index_type) {
2371 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2372 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2373 cs, R_03090C_VGT_INDEX_TYPE,
2374 2, state->index_type);
2375 } else {
2376 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2377 radeon_emit(cs, state->index_type);
2378 }
2379
2380 state->last_index_type = state->index_type;
2381 }
2382
2383 /* For the direct indexed draws we use DRAW_INDEX_2, which includes
2384 * the index_va and max_index_count already. */
2385 if (!indirect)
2386 return;
2387
2388 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2389 radeon_emit(cs, state->index_va);
2390 radeon_emit(cs, state->index_va >> 32);
2391
2392 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2393 radeon_emit(cs, state->max_index_count);
2394
2395 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
2396 }
2397
2398 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
2399 {
2400 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
2401 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2402 uint32_t pa_sc_mode_cntl_1 =
2403 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
2404 uint32_t db_count_control;
2405
2406 if(!cmd_buffer->state.active_occlusion_queries) {
2407 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2408 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2409 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2410 has_perfect_queries) {
2411 /* Re-enable out-of-order rasterization if the
2412 * bound pipeline supports it and if it's has
2413 * been disabled before starting any perfect
2414 * occlusion queries.
2415 */
2416 radeon_set_context_reg(cmd_buffer->cs,
2417 R_028A4C_PA_SC_MODE_CNTL_1,
2418 pa_sc_mode_cntl_1);
2419 }
2420 }
2421 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
2422 } else {
2423 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2424 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
2425 bool gfx10_perfect = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10 && has_perfect_queries;
2426
2427 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2428 /* Always enable PERFECT_ZPASS_COUNTS due to issues with partially
2429 * covered tiles, discards, and early depth testing. For more details,
2430 * see https://gitlab.freedesktop.org/mesa/mesa/-/issues/3218 */
2431 db_count_control =
2432 S_028004_PERFECT_ZPASS_COUNTS(1) |
2433 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
2434 S_028004_SAMPLE_RATE(sample_rate) |
2435 S_028004_ZPASS_ENABLE(1) |
2436 S_028004_SLICE_EVEN_ENABLE(1) |
2437 S_028004_SLICE_ODD_ENABLE(1);
2438
2439 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2440 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2441 has_perfect_queries) {
2442 /* If the bound pipeline has enabled
2443 * out-of-order rasterization, we should
2444 * disable it before starting any perfect
2445 * occlusion queries.
2446 */
2447 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
2448
2449 radeon_set_context_reg(cmd_buffer->cs,
2450 R_028A4C_PA_SC_MODE_CNTL_1,
2451 pa_sc_mode_cntl_1);
2452 }
2453 } else {
2454 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
2455 S_028004_SAMPLE_RATE(sample_rate);
2456 }
2457 }
2458
2459 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
2460
2461 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2462 }
2463
2464 static void
2465 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
2466 {
2467 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
2468
2469 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
2470 radv_emit_viewport(cmd_buffer);
2471
2472 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
2473 !cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
2474 radv_emit_scissor(cmd_buffer);
2475
2476 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
2477 radv_emit_line_width(cmd_buffer);
2478
2479 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
2480 radv_emit_blend_constants(cmd_buffer);
2481
2482 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
2483 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
2484 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
2485 radv_emit_stencil(cmd_buffer);
2486
2487 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
2488 radv_emit_depth_bounds(cmd_buffer);
2489
2490 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
2491 radv_emit_depth_bias(cmd_buffer);
2492
2493 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
2494 radv_emit_discard_rectangle(cmd_buffer);
2495
2496 if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)
2497 radv_emit_sample_locations(cmd_buffer);
2498
2499 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE)
2500 radv_emit_line_stipple(cmd_buffer);
2501
2502 if (states & (RADV_CMD_DIRTY_DYNAMIC_CULL_MODE |
2503 RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE))
2504 radv_emit_culling(cmd_buffer, states);
2505
2506 if (states & RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY)
2507 radv_emit_primitive_topology(cmd_buffer);
2508
2509 if (states & (RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE |
2510 RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE |
2511 RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP |
2512 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE |
2513 RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE |
2514 RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP))
2515 radv_emit_depth_control(cmd_buffer, states);
2516
2517 if (states & RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP)
2518 radv_emit_stencil_control(cmd_buffer);
2519
2520 cmd_buffer->state.dirty &= ~states;
2521 }
2522
2523 static void
2524 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
2525 VkPipelineBindPoint bind_point)
2526 {
2527 struct radv_descriptor_state *descriptors_state =
2528 radv_get_descriptors_state(cmd_buffer, bind_point);
2529 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
2530 unsigned bo_offset;
2531
2532 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
2533 set->mapped_ptr,
2534 &bo_offset))
2535 return;
2536
2537 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2538 set->va += bo_offset;
2539 }
2540
2541 static void
2542 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
2543 VkPipelineBindPoint bind_point)
2544 {
2545 struct radv_descriptor_state *descriptors_state =
2546 radv_get_descriptors_state(cmd_buffer, bind_point);
2547 uint32_t size = MAX_SETS * 4;
2548 uint32_t offset;
2549 void *ptr;
2550
2551 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
2552 256, &offset, &ptr))
2553 return;
2554
2555 for (unsigned i = 0; i < MAX_SETS; i++) {
2556 uint32_t *uptr = ((uint32_t *)ptr) + i;
2557 uint64_t set_va = 0;
2558 struct radv_descriptor_set *set = descriptors_state->sets[i];
2559 if (descriptors_state->valid & (1u << i))
2560 set_va = set->va;
2561 uptr[0] = set_va & 0xffffffff;
2562 }
2563
2564 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2565 va += offset;
2566
2567 if (cmd_buffer->state.pipeline) {
2568 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
2569 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2570 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2571
2572 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
2573 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
2574 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2575
2576 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
2577 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2578 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2579
2580 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2581 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
2582 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2583
2584 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2585 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
2586 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2587 }
2588
2589 if (cmd_buffer->state.compute_pipeline)
2590 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
2591 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2592 }
2593
2594 static void
2595 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
2596 VkShaderStageFlags stages)
2597 {
2598 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2599 VK_PIPELINE_BIND_POINT_COMPUTE :
2600 VK_PIPELINE_BIND_POINT_GRAPHICS;
2601 struct radv_descriptor_state *descriptors_state =
2602 radv_get_descriptors_state(cmd_buffer, bind_point);
2603 struct radv_cmd_state *state = &cmd_buffer->state;
2604 bool flush_indirect_descriptors;
2605
2606 if (!descriptors_state->dirty)
2607 return;
2608
2609 if (descriptors_state->push_dirty)
2610 radv_flush_push_descriptors(cmd_buffer, bind_point);
2611
2612 flush_indirect_descriptors =
2613 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
2614 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
2615 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
2616 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
2617
2618 if (flush_indirect_descriptors)
2619 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
2620
2621 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2622 cmd_buffer->cs,
2623 MAX_SETS * MESA_SHADER_STAGES * 4);
2624
2625 if (cmd_buffer->state.pipeline) {
2626 radv_foreach_stage(stage, stages) {
2627 if (!cmd_buffer->state.pipeline->shaders[stage])
2628 continue;
2629
2630 radv_emit_descriptor_pointers(cmd_buffer,
2631 cmd_buffer->state.pipeline,
2632 descriptors_state, stage);
2633 }
2634 }
2635
2636 if (cmd_buffer->state.compute_pipeline &&
2637 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
2638 radv_emit_descriptor_pointers(cmd_buffer,
2639 cmd_buffer->state.compute_pipeline,
2640 descriptors_state,
2641 MESA_SHADER_COMPUTE);
2642 }
2643
2644 descriptors_state->dirty = 0;
2645 descriptors_state->push_dirty = false;
2646
2647 assert(cmd_buffer->cs->cdw <= cdw_max);
2648
2649 if (unlikely(cmd_buffer->device->trace_bo))
2650 radv_save_descriptors(cmd_buffer, bind_point);
2651 }
2652
2653 static void
2654 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
2655 VkShaderStageFlags stages)
2656 {
2657 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
2658 ? cmd_buffer->state.compute_pipeline
2659 : cmd_buffer->state.pipeline;
2660 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2661 VK_PIPELINE_BIND_POINT_COMPUTE :
2662 VK_PIPELINE_BIND_POINT_GRAPHICS;
2663 struct radv_descriptor_state *descriptors_state =
2664 radv_get_descriptors_state(cmd_buffer, bind_point);
2665 struct radv_pipeline_layout *layout = pipeline->layout;
2666 struct radv_shader_variant *shader, *prev_shader;
2667 bool need_push_constants = false;
2668 unsigned offset;
2669 void *ptr;
2670 uint64_t va;
2671
2672 stages &= cmd_buffer->push_constant_stages;
2673 if (!stages ||
2674 (!layout->push_constant_size && !layout->dynamic_offset_count))
2675 return;
2676
2677 radv_foreach_stage(stage, stages) {
2678 shader = radv_get_shader(pipeline, stage);
2679 if (!shader)
2680 continue;
2681
2682 need_push_constants |= shader->info.loads_push_constants;
2683 need_push_constants |= shader->info.loads_dynamic_offsets;
2684
2685 uint8_t base = shader->info.base_inline_push_consts;
2686 uint8_t count = shader->info.num_inline_push_consts;
2687
2688 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
2689 AC_UD_INLINE_PUSH_CONSTANTS,
2690 count,
2691 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
2692 }
2693
2694 if (need_push_constants) {
2695 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
2696 16 * layout->dynamic_offset_count,
2697 256, &offset, &ptr))
2698 return;
2699
2700 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
2701 memcpy((char*)ptr + layout->push_constant_size,
2702 descriptors_state->dynamic_buffers,
2703 16 * layout->dynamic_offset_count);
2704
2705 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2706 va += offset;
2707
2708 ASSERTED unsigned cdw_max =
2709 radeon_check_space(cmd_buffer->device->ws,
2710 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
2711
2712 prev_shader = NULL;
2713 radv_foreach_stage(stage, stages) {
2714 shader = radv_get_shader(pipeline, stage);
2715
2716 /* Avoid redundantly emitting the address for merged stages. */
2717 if (shader && shader != prev_shader) {
2718 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
2719 AC_UD_PUSH_CONSTANTS, va);
2720
2721 prev_shader = shader;
2722 }
2723 }
2724 assert(cmd_buffer->cs->cdw <= cdw_max);
2725 }
2726
2727 cmd_buffer->push_constant_stages &= ~stages;
2728 }
2729
2730 static void
2731 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
2732 bool pipeline_is_dirty)
2733 {
2734 if ((pipeline_is_dirty ||
2735 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
2736 cmd_buffer->state.pipeline->num_vertex_bindings &&
2737 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.has_vertex_buffers) {
2738 unsigned vb_offset;
2739 void *vb_ptr;
2740 uint32_t i = 0;
2741 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
2742 uint64_t va;
2743
2744 /* allocate some descriptor state for vertex buffers */
2745 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2746 &vb_offset, &vb_ptr))
2747 return;
2748
2749 for (i = 0; i < count; i++) {
2750 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2751 uint32_t offset;
2752 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2753 unsigned num_records;
2754 unsigned stride;
2755
2756 if (!buffer)
2757 continue;
2758
2759 va = radv_buffer_get_va(buffer->bo);
2760
2761 offset = cmd_buffer->vertex_bindings[i].offset;
2762 va += offset + buffer->offset;
2763
2764 if (cmd_buffer->vertex_bindings[i].size) {
2765 num_records = cmd_buffer->vertex_bindings[i].size;
2766 } else {
2767 num_records = buffer->size - offset;
2768 }
2769
2770 if (cmd_buffer->state.pipeline->graphics.uses_dynamic_stride) {
2771 stride = cmd_buffer->vertex_bindings[i].stride;
2772 } else {
2773 stride = cmd_buffer->state.pipeline->binding_stride[i];
2774 }
2775
2776 if (cmd_buffer->device->physical_device->rad_info.chip_class != GFX8 && stride)
2777 num_records /= stride;
2778
2779 uint32_t rsrc_word3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2780 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2781 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2782 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2783
2784 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2785 /* OOB_SELECT chooses the out-of-bounds check:
2786 * - 1: index >= NUM_RECORDS (Structured)
2787 * - 3: offset >= NUM_RECORDS (Raw)
2788 */
2789 int oob_select = stride ? V_008F0C_OOB_SELECT_STRUCTURED : V_008F0C_OOB_SELECT_RAW;
2790
2791 rsrc_word3 |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT) |
2792 S_008F0C_OOB_SELECT(oob_select) |
2793 S_008F0C_RESOURCE_LEVEL(1);
2794 } else {
2795 rsrc_word3 |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2796 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2797 }
2798
2799 desc[0] = va;
2800 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2801 desc[2] = num_records;
2802 desc[3] = rsrc_word3;
2803 }
2804
2805 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2806 va += vb_offset;
2807
2808 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2809 AC_UD_VS_VERTEX_BUFFERS, va);
2810
2811 cmd_buffer->state.vb_va = va;
2812 cmd_buffer->state.vb_size = count * 16;
2813 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2814 }
2815 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2816 }
2817
2818 static void
2819 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2820 {
2821 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2822 struct radv_userdata_info *loc;
2823 uint32_t base_reg;
2824
2825 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2826 if (!radv_get_shader(pipeline, stage))
2827 continue;
2828
2829 loc = radv_lookup_user_sgpr(pipeline, stage,
2830 AC_UD_STREAMOUT_BUFFERS);
2831 if (loc->sgpr_idx == -1)
2832 continue;
2833
2834 base_reg = pipeline->user_data_0[stage];
2835
2836 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2837 base_reg + loc->sgpr_idx * 4, va, false);
2838 }
2839
2840 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
2841 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2842 if (loc->sgpr_idx != -1) {
2843 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2844
2845 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2846 base_reg + loc->sgpr_idx * 4, va, false);
2847 }
2848 }
2849 }
2850
2851 static void
2852 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2853 {
2854 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2855 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2856 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2857 unsigned so_offset;
2858 void *so_ptr;
2859 uint64_t va;
2860
2861 /* Allocate some descriptor state for streamout buffers. */
2862 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2863 MAX_SO_BUFFERS * 16, 256,
2864 &so_offset, &so_ptr))
2865 return;
2866
2867 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2868 struct radv_buffer *buffer = sb[i].buffer;
2869 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2870
2871 if (!(so->enabled_mask & (1 << i)))
2872 continue;
2873
2874 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2875
2876 va += sb[i].offset;
2877
2878 /* Set the descriptor.
2879 *
2880 * On GFX8, the format must be non-INVALID, otherwise
2881 * the buffer will be considered not bound and store
2882 * instructions will be no-ops.
2883 */
2884 uint32_t size = 0xffffffff;
2885
2886 /* Compute the correct buffer size for NGG streamout
2887 * because it's used to determine the max emit per
2888 * buffer.
2889 */
2890 if (cmd_buffer->device->physical_device->use_ngg_streamout)
2891 size = buffer->size - sb[i].offset;
2892
2893 uint32_t rsrc_word3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2894 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2895 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2896 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2897
2898 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2899 rsrc_word3 |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2900 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
2901 S_008F0C_RESOURCE_LEVEL(1);
2902 } else {
2903 rsrc_word3 |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2904 }
2905
2906 desc[0] = va;
2907 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2908 desc[2] = size;
2909 desc[3] = rsrc_word3;
2910 }
2911
2912 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2913 va += so_offset;
2914
2915 radv_emit_streamout_buffers(cmd_buffer, va);
2916 }
2917
2918 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2919 }
2920
2921 static void
2922 radv_flush_ngg_gs_state(struct radv_cmd_buffer *cmd_buffer)
2923 {
2924 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2925 struct radv_userdata_info *loc;
2926 uint32_t ngg_gs_state = 0;
2927 uint32_t base_reg;
2928
2929 if (!radv_pipeline_has_gs(pipeline) ||
2930 !radv_pipeline_has_ngg(pipeline))
2931 return;
2932
2933 /* By default NGG GS queries are disabled but they are enabled if the
2934 * command buffer has active GDS queries or if it's a secondary command
2935 * buffer that inherits the number of generated primitives.
2936 */
2937 if (cmd_buffer->state.active_pipeline_gds_queries ||
2938 (cmd_buffer->state.inherited_pipeline_statistics & VK_QUERY_PIPELINE_STATISTIC_GEOMETRY_SHADER_PRIMITIVES_BIT))
2939 ngg_gs_state = 1;
2940
2941 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_GEOMETRY,
2942 AC_UD_NGG_GS_STATE);
2943 base_reg = pipeline->user_data_0[MESA_SHADER_GEOMETRY];
2944 assert(loc->sgpr_idx != -1);
2945
2946 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
2947 ngg_gs_state);
2948 }
2949
2950 static void
2951 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2952 {
2953 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2954 radv_flush_streamout_descriptors(cmd_buffer);
2955 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2956 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2957 radv_flush_ngg_gs_state(cmd_buffer);
2958 }
2959
2960 struct radv_draw_info {
2961 /**
2962 * Number of vertices.
2963 */
2964 uint32_t count;
2965
2966 /**
2967 * Index of the first vertex.
2968 */
2969 int32_t vertex_offset;
2970
2971 /**
2972 * First instance id.
2973 */
2974 uint32_t first_instance;
2975
2976 /**
2977 * Number of instances.
2978 */
2979 uint32_t instance_count;
2980
2981 /**
2982 * First index (indexed draws only).
2983 */
2984 uint32_t first_index;
2985
2986 /**
2987 * Whether it's an indexed draw.
2988 */
2989 bool indexed;
2990
2991 /**
2992 * Indirect draw parameters resource.
2993 */
2994 struct radv_buffer *indirect;
2995 uint64_t indirect_offset;
2996 uint32_t stride;
2997
2998 /**
2999 * Draw count parameters resource.
3000 */
3001 struct radv_buffer *count_buffer;
3002 uint64_t count_buffer_offset;
3003
3004 /**
3005 * Stream output parameters resource.
3006 */
3007 struct radv_buffer *strmout_buffer;
3008 uint64_t strmout_buffer_offset;
3009 };
3010
3011 static uint32_t
3012 radv_get_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
3013 {
3014 switch (cmd_buffer->state.index_type) {
3015 case V_028A7C_VGT_INDEX_8:
3016 return 0xffu;
3017 case V_028A7C_VGT_INDEX_16:
3018 return 0xffffu;
3019 case V_028A7C_VGT_INDEX_32:
3020 return 0xffffffffu;
3021 default:
3022 unreachable("invalid index type");
3023 }
3024 }
3025
3026 static void
3027 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
3028 bool instanced_draw, bool indirect_draw,
3029 bool count_from_stream_output,
3030 uint32_t draw_vertex_count)
3031 {
3032 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
3033 struct radv_cmd_state *state = &cmd_buffer->state;
3034 unsigned topology = state->dynamic.primitive_topology;
3035 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3036 unsigned ia_multi_vgt_param;
3037
3038 ia_multi_vgt_param =
3039 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
3040 indirect_draw,
3041 count_from_stream_output,
3042 draw_vertex_count,
3043 topology);
3044
3045 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
3046 if (info->chip_class == GFX9) {
3047 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
3048 cs,
3049 R_030960_IA_MULTI_VGT_PARAM,
3050 4, ia_multi_vgt_param);
3051 } else if (info->chip_class >= GFX7) {
3052 radeon_set_context_reg_idx(cs,
3053 R_028AA8_IA_MULTI_VGT_PARAM,
3054 1, ia_multi_vgt_param);
3055 } else {
3056 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
3057 ia_multi_vgt_param);
3058 }
3059 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
3060 }
3061 }
3062
3063 static void
3064 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
3065 const struct radv_draw_info *draw_info)
3066 {
3067 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
3068 struct radv_cmd_state *state = &cmd_buffer->state;
3069 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3070 int32_t primitive_reset_en;
3071
3072 /* Draw state. */
3073 if (info->chip_class < GFX10) {
3074 si_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
3075 draw_info->indirect,
3076 !!draw_info->strmout_buffer,
3077 draw_info->indirect ? 0 : draw_info->count);
3078 }
3079
3080 /* Primitive restart. */
3081 primitive_reset_en =
3082 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
3083
3084 if (primitive_reset_en != state->last_primitive_reset_en) {
3085 state->last_primitive_reset_en = primitive_reset_en;
3086 if (info->chip_class >= GFX9) {
3087 radeon_set_uconfig_reg(cs,
3088 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
3089 primitive_reset_en);
3090 } else {
3091 radeon_set_context_reg(cs,
3092 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
3093 primitive_reset_en);
3094 }
3095 }
3096
3097 if (primitive_reset_en) {
3098 uint32_t primitive_reset_index =
3099 radv_get_primitive_reset_index(cmd_buffer);
3100
3101 if (primitive_reset_index != state->last_primitive_reset_index) {
3102 radeon_set_context_reg(cs,
3103 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
3104 primitive_reset_index);
3105 state->last_primitive_reset_index = primitive_reset_index;
3106 }
3107 }
3108
3109 if (draw_info->strmout_buffer) {
3110 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
3111
3112 va += draw_info->strmout_buffer->offset +
3113 draw_info->strmout_buffer_offset;
3114
3115 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
3116 draw_info->stride);
3117
3118 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3119 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
3120 COPY_DATA_DST_SEL(COPY_DATA_REG) |
3121 COPY_DATA_WR_CONFIRM);
3122 radeon_emit(cs, va);
3123 radeon_emit(cs, va >> 32);
3124 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
3125 radeon_emit(cs, 0); /* unused */
3126
3127 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
3128 }
3129 }
3130
3131 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
3132 VkPipelineStageFlags src_stage_mask)
3133 {
3134 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
3135 VK_PIPELINE_STAGE_TRANSFER_BIT |
3136 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
3137 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
3138 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
3139 }
3140
3141 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
3142 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
3143 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
3144 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
3145 VK_PIPELINE_STAGE_TRANSFER_BIT |
3146 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
3147 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
3148 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
3149 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
3150 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
3151 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
3152 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
3153 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
3154 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
3155 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
3156 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
3157 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
3158 }
3159 }
3160
3161 static enum radv_cmd_flush_bits
3162 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
3163 VkAccessFlags src_flags,
3164 struct radv_image *image)
3165 {
3166 bool flush_CB_meta = true, flush_DB_meta = true;
3167 enum radv_cmd_flush_bits flush_bits = 0;
3168 uint32_t b;
3169
3170 if (image) {
3171 if (!radv_image_has_CB_metadata(image))
3172 flush_CB_meta = false;
3173 if (!radv_image_has_htile(image))
3174 flush_DB_meta = false;
3175 }
3176
3177 for_each_bit(b, src_flags) {
3178 switch ((VkAccessFlagBits)(1 << b)) {
3179 case VK_ACCESS_SHADER_WRITE_BIT:
3180 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
3181 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
3182 flush_bits |= RADV_CMD_FLAG_WB_L2;
3183 break;
3184 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
3185 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
3186 if (flush_CB_meta)
3187 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3188 break;
3189 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
3190 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
3191 if (flush_DB_meta)
3192 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3193 break;
3194 case VK_ACCESS_TRANSFER_WRITE_BIT:
3195 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3196 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3197 RADV_CMD_FLAG_INV_L2;
3198
3199 if (flush_CB_meta)
3200 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3201 if (flush_DB_meta)
3202 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3203 break;
3204 case VK_ACCESS_MEMORY_WRITE_BIT:
3205 flush_bits |= RADV_CMD_FLAG_INV_L2 |
3206 RADV_CMD_FLAG_WB_L2 |
3207 RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3208 RADV_CMD_FLAG_FLUSH_AND_INV_DB;
3209
3210 if (flush_CB_meta)
3211 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3212 if (flush_DB_meta)
3213 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3214 break;
3215 default:
3216 break;
3217 }
3218 }
3219 return flush_bits;
3220 }
3221
3222 static enum radv_cmd_flush_bits
3223 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
3224 VkAccessFlags dst_flags,
3225 struct radv_image *image)
3226 {
3227 bool flush_CB_meta = true, flush_DB_meta = true;
3228 enum radv_cmd_flush_bits flush_bits = 0;
3229 bool flush_CB = true, flush_DB = true;
3230 bool image_is_coherent = false;
3231 uint32_t b;
3232
3233 if (image) {
3234 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
3235 flush_CB = false;
3236 flush_DB = false;
3237 }
3238
3239 if (!radv_image_has_CB_metadata(image))
3240 flush_CB_meta = false;
3241 if (!radv_image_has_htile(image))
3242 flush_DB_meta = false;
3243
3244 /* TODO: implement shader coherent for GFX10 */
3245
3246 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
3247 if (image->info.samples == 1 &&
3248 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
3249 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
3250 !vk_format_is_stencil(image->vk_format)) {
3251 /* Single-sample color and single-sample depth
3252 * (not stencil) are coherent with shaders on
3253 * GFX9.
3254 */
3255 image_is_coherent = true;
3256 }
3257 }
3258 }
3259
3260 for_each_bit(b, dst_flags) {
3261 switch ((VkAccessFlagBits)(1 << b)) {
3262 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
3263 case VK_ACCESS_INDEX_READ_BIT:
3264 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
3265 break;
3266 case VK_ACCESS_UNIFORM_READ_BIT:
3267 flush_bits |= RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_SCACHE;
3268 break;
3269 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
3270 case VK_ACCESS_TRANSFER_READ_BIT:
3271 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
3272 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
3273 RADV_CMD_FLAG_INV_L2;
3274 break;
3275 case VK_ACCESS_SHADER_READ_BIT:
3276 flush_bits |= RADV_CMD_FLAG_INV_VCACHE;
3277 /* Unlike LLVM, ACO uses SMEM for SSBOs and we have to
3278 * invalidate the scalar cache. */
3279 if (!cmd_buffer->device->physical_device->use_llvm)
3280 flush_bits |= RADV_CMD_FLAG_INV_SCACHE;
3281
3282 if (!image_is_coherent)
3283 flush_bits |= RADV_CMD_FLAG_INV_L2;
3284 break;
3285 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
3286 if (flush_CB)
3287 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
3288 if (flush_CB_meta)
3289 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3290 break;
3291 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
3292 if (flush_DB)
3293 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
3294 if (flush_DB_meta)
3295 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3296 break;
3297 case VK_ACCESS_MEMORY_READ_BIT:
3298 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
3299 RADV_CMD_FLAG_INV_SCACHE |
3300 RADV_CMD_FLAG_INV_L2;
3301 if (flush_CB)
3302 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
3303 if (flush_CB_meta)
3304 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3305 if (flush_DB)
3306 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
3307 if (flush_DB_meta)
3308 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3309 break;
3310 default:
3311 break;
3312 }
3313 }
3314 return flush_bits;
3315 }
3316
3317 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
3318 const struct radv_subpass_barrier *barrier)
3319 {
3320 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
3321 NULL);
3322 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
3323 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
3324 NULL);
3325 }
3326
3327 uint32_t
3328 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
3329 {
3330 struct radv_cmd_state *state = &cmd_buffer->state;
3331 uint32_t subpass_id = state->subpass - state->pass->subpasses;
3332
3333 /* The id of this subpass shouldn't exceed the number of subpasses in
3334 * this render pass minus 1.
3335 */
3336 assert(subpass_id < state->pass->subpass_count);
3337 return subpass_id;
3338 }
3339
3340 static struct radv_sample_locations_state *
3341 radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer,
3342 uint32_t att_idx,
3343 bool begin_subpass)
3344 {
3345 struct radv_cmd_state *state = &cmd_buffer->state;
3346 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
3347 struct radv_image_view *view = state->attachments[att_idx].iview;
3348
3349 if (view->image->info.samples == 1)
3350 return NULL;
3351
3352 if (state->pass->attachments[att_idx].first_subpass_idx == subpass_id) {
3353 /* Return the initial sample locations if this is the initial
3354 * layout transition of the given subpass attachemnt.
3355 */
3356 if (state->attachments[att_idx].sample_location.count > 0)
3357 return &state->attachments[att_idx].sample_location;
3358 } else {
3359 /* Otherwise return the subpass sample locations if defined. */
3360 if (state->subpass_sample_locs) {
3361 /* Because the driver sets the current subpass before
3362 * initial layout transitions, we should use the sample
3363 * locations from the previous subpass to avoid an
3364 * off-by-one problem. Otherwise, use the sample
3365 * locations for the current subpass for final layout
3366 * transitions.
3367 */
3368 if (begin_subpass)
3369 subpass_id--;
3370
3371 for (uint32_t i = 0; i < state->num_subpass_sample_locs; i++) {
3372 if (state->subpass_sample_locs[i].subpass_idx == subpass_id)
3373 return &state->subpass_sample_locs[i].sample_location;
3374 }
3375 }
3376 }
3377
3378 return NULL;
3379 }
3380
3381 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
3382 struct radv_subpass_attachment att,
3383 bool begin_subpass)
3384 {
3385 unsigned idx = att.attachment;
3386 struct radv_image_view *view = cmd_buffer->state.attachments[idx].iview;
3387 struct radv_sample_locations_state *sample_locs;
3388 VkImageSubresourceRange range;
3389 range.aspectMask = view->aspect_mask;
3390 range.baseMipLevel = view->base_mip;
3391 range.levelCount = 1;
3392 range.baseArrayLayer = view->base_layer;
3393 range.layerCount = cmd_buffer->state.framebuffer->layers;
3394
3395 if (cmd_buffer->state.subpass->view_mask) {
3396 /* If the current subpass uses multiview, the driver might have
3397 * performed a fast color/depth clear to the whole image
3398 * (including all layers). To make sure the driver will
3399 * decompress the image correctly (if needed), we have to
3400 * account for the "real" number of layers. If the view mask is
3401 * sparse, this will decompress more layers than needed.
3402 */
3403 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
3404 }
3405
3406 /* Get the subpass sample locations for the given attachment, if NULL
3407 * is returned the driver will use the default HW locations.
3408 */
3409 sample_locs = radv_get_attachment_sample_locations(cmd_buffer, idx,
3410 begin_subpass);
3411
3412 /* Determine if the subpass uses separate depth/stencil layouts. */
3413 bool uses_separate_depth_stencil_layouts = false;
3414 if ((cmd_buffer->state.attachments[idx].current_layout !=
3415 cmd_buffer->state.attachments[idx].current_stencil_layout) ||
3416 (att.layout != att.stencil_layout)) {
3417 uses_separate_depth_stencil_layouts = true;
3418 }
3419
3420 /* For separate layouts, perform depth and stencil transitions
3421 * separately.
3422 */
3423 if (uses_separate_depth_stencil_layouts &&
3424 (range.aspectMask == (VK_IMAGE_ASPECT_DEPTH_BIT |
3425 VK_IMAGE_ASPECT_STENCIL_BIT))) {
3426 /* Depth-only transitions. */
3427 range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3428 radv_handle_image_transition(cmd_buffer,
3429 view->image,
3430 cmd_buffer->state.attachments[idx].current_layout,
3431 cmd_buffer->state.attachments[idx].current_in_render_loop,
3432 att.layout, att.in_render_loop,
3433 0, 0, &range, sample_locs);
3434
3435 /* Stencil-only transitions. */
3436 range.aspectMask = VK_IMAGE_ASPECT_STENCIL_BIT;
3437 radv_handle_image_transition(cmd_buffer,
3438 view->image,
3439 cmd_buffer->state.attachments[idx].current_stencil_layout,
3440 cmd_buffer->state.attachments[idx].current_in_render_loop,
3441 att.stencil_layout, att.in_render_loop,
3442 0, 0, &range, sample_locs);
3443 } else {
3444 radv_handle_image_transition(cmd_buffer,
3445 view->image,
3446 cmd_buffer->state.attachments[idx].current_layout,
3447 cmd_buffer->state.attachments[idx].current_in_render_loop,
3448 att.layout, att.in_render_loop,
3449 0, 0, &range, sample_locs);
3450 }
3451
3452 cmd_buffer->state.attachments[idx].current_layout = att.layout;
3453 cmd_buffer->state.attachments[idx].current_stencil_layout = att.stencil_layout;
3454 cmd_buffer->state.attachments[idx].current_in_render_loop = att.in_render_loop;
3455
3456
3457 }
3458
3459 void
3460 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
3461 const struct radv_subpass *subpass)
3462 {
3463 cmd_buffer->state.subpass = subpass;
3464
3465 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
3466 }
3467
3468 static VkResult
3469 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
3470 struct radv_render_pass *pass,
3471 const VkRenderPassBeginInfo *info)
3472 {
3473 const struct VkRenderPassSampleLocationsBeginInfoEXT *sample_locs =
3474 vk_find_struct_const(info->pNext,
3475 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT);
3476 struct radv_cmd_state *state = &cmd_buffer->state;
3477
3478 if (!sample_locs) {
3479 state->subpass_sample_locs = NULL;
3480 return VK_SUCCESS;
3481 }
3482
3483 for (uint32_t i = 0; i < sample_locs->attachmentInitialSampleLocationsCount; i++) {
3484 const VkAttachmentSampleLocationsEXT *att_sample_locs =
3485 &sample_locs->pAttachmentInitialSampleLocations[i];
3486 uint32_t att_idx = att_sample_locs->attachmentIndex;
3487 struct radv_image *image = cmd_buffer->state.attachments[att_idx].iview->image;
3488
3489 assert(vk_format_is_depth_or_stencil(image->vk_format));
3490
3491 /* From the Vulkan spec 1.1.108:
3492 *
3493 * "If the image referenced by the framebuffer attachment at
3494 * index attachmentIndex was not created with
3495 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
3496 * then the values specified in sampleLocationsInfo are
3497 * ignored."
3498 */
3499 if (!(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT))
3500 continue;
3501
3502 const VkSampleLocationsInfoEXT *sample_locs_info =
3503 &att_sample_locs->sampleLocationsInfo;
3504
3505 state->attachments[att_idx].sample_location.per_pixel =
3506 sample_locs_info->sampleLocationsPerPixel;
3507 state->attachments[att_idx].sample_location.grid_size =
3508 sample_locs_info->sampleLocationGridSize;
3509 state->attachments[att_idx].sample_location.count =
3510 sample_locs_info->sampleLocationsCount;
3511 typed_memcpy(&state->attachments[att_idx].sample_location.locations[0],
3512 sample_locs_info->pSampleLocations,
3513 sample_locs_info->sampleLocationsCount);
3514 }
3515
3516 state->subpass_sample_locs = vk_alloc(&cmd_buffer->pool->alloc,
3517 sample_locs->postSubpassSampleLocationsCount *
3518 sizeof(state->subpass_sample_locs[0]),
3519 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3520 if (state->subpass_sample_locs == NULL) {
3521 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3522 return cmd_buffer->record_result;
3523 }
3524
3525 state->num_subpass_sample_locs = sample_locs->postSubpassSampleLocationsCount;
3526
3527 for (uint32_t i = 0; i < sample_locs->postSubpassSampleLocationsCount; i++) {
3528 const VkSubpassSampleLocationsEXT *subpass_sample_locs_info =
3529 &sample_locs->pPostSubpassSampleLocations[i];
3530 const VkSampleLocationsInfoEXT *sample_locs_info =
3531 &subpass_sample_locs_info->sampleLocationsInfo;
3532
3533 state->subpass_sample_locs[i].subpass_idx =
3534 subpass_sample_locs_info->subpassIndex;
3535 state->subpass_sample_locs[i].sample_location.per_pixel =
3536 sample_locs_info->sampleLocationsPerPixel;
3537 state->subpass_sample_locs[i].sample_location.grid_size =
3538 sample_locs_info->sampleLocationGridSize;
3539 state->subpass_sample_locs[i].sample_location.count =
3540 sample_locs_info->sampleLocationsCount;
3541 typed_memcpy(&state->subpass_sample_locs[i].sample_location.locations[0],
3542 sample_locs_info->pSampleLocations,
3543 sample_locs_info->sampleLocationsCount);
3544 }
3545
3546 return VK_SUCCESS;
3547 }
3548
3549 static VkResult
3550 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
3551 struct radv_render_pass *pass,
3552 const VkRenderPassBeginInfo *info)
3553 {
3554 struct radv_cmd_state *state = &cmd_buffer->state;
3555 const struct VkRenderPassAttachmentBeginInfo *attachment_info = NULL;
3556
3557 if (info) {
3558 attachment_info = vk_find_struct_const(info->pNext,
3559 RENDER_PASS_ATTACHMENT_BEGIN_INFO);
3560 }
3561
3562
3563 if (pass->attachment_count == 0) {
3564 state->attachments = NULL;
3565 return VK_SUCCESS;
3566 }
3567
3568 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
3569 pass->attachment_count *
3570 sizeof(state->attachments[0]),
3571 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3572 if (state->attachments == NULL) {
3573 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3574 return cmd_buffer->record_result;
3575 }
3576
3577 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
3578 struct radv_render_pass_attachment *att = &pass->attachments[i];
3579 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
3580 VkImageAspectFlags clear_aspects = 0;
3581
3582 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
3583 /* color attachment */
3584 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3585 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
3586 }
3587 } else {
3588 /* depthstencil attachment */
3589 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
3590 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3591 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
3592 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3593 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
3594 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3595 }
3596 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3597 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3598 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3599 }
3600 }
3601
3602 state->attachments[i].pending_clear_aspects = clear_aspects;
3603 state->attachments[i].cleared_views = 0;
3604 if (clear_aspects && info) {
3605 assert(info->clearValueCount > i);
3606 state->attachments[i].clear_value = info->pClearValues[i];
3607 }
3608
3609 state->attachments[i].current_layout = att->initial_layout;
3610 state->attachments[i].current_in_render_loop = false;
3611 state->attachments[i].current_stencil_layout = att->stencil_initial_layout;
3612 state->attachments[i].sample_location.count = 0;
3613
3614 struct radv_image_view *iview;
3615 if (attachment_info && attachment_info->attachmentCount > i) {
3616 iview = radv_image_view_from_handle(attachment_info->pAttachments[i]);
3617 } else {
3618 iview = state->framebuffer->attachments[i];
3619 }
3620
3621 state->attachments[i].iview = iview;
3622 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3623 radv_initialise_ds_surface(cmd_buffer->device, &state->attachments[i].ds, iview);
3624 } else {
3625 radv_initialise_color_surface(cmd_buffer->device, &state->attachments[i].cb, iview);
3626 }
3627 }
3628
3629 return VK_SUCCESS;
3630 }
3631
3632 VkResult radv_AllocateCommandBuffers(
3633 VkDevice _device,
3634 const VkCommandBufferAllocateInfo *pAllocateInfo,
3635 VkCommandBuffer *pCommandBuffers)
3636 {
3637 RADV_FROM_HANDLE(radv_device, device, _device);
3638 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
3639
3640 VkResult result = VK_SUCCESS;
3641 uint32_t i;
3642
3643 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
3644
3645 if (!list_is_empty(&pool->free_cmd_buffers)) {
3646 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
3647
3648 list_del(&cmd_buffer->pool_link);
3649 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
3650
3651 result = radv_reset_cmd_buffer(cmd_buffer);
3652 cmd_buffer->level = pAllocateInfo->level;
3653
3654 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
3655 } else {
3656 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
3657 &pCommandBuffers[i]);
3658 }
3659 if (result != VK_SUCCESS)
3660 break;
3661 }
3662
3663 if (result != VK_SUCCESS) {
3664 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
3665 i, pCommandBuffers);
3666
3667 /* From the Vulkan 1.0.66 spec:
3668 *
3669 * "vkAllocateCommandBuffers can be used to create multiple
3670 * command buffers. If the creation of any of those command
3671 * buffers fails, the implementation must destroy all
3672 * successfully created command buffer objects from this
3673 * command, set all entries of the pCommandBuffers array to
3674 * NULL and return the error."
3675 */
3676 memset(pCommandBuffers, 0,
3677 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
3678 }
3679
3680 return result;
3681 }
3682
3683 void radv_FreeCommandBuffers(
3684 VkDevice device,
3685 VkCommandPool commandPool,
3686 uint32_t commandBufferCount,
3687 const VkCommandBuffer *pCommandBuffers)
3688 {
3689 for (uint32_t i = 0; i < commandBufferCount; i++) {
3690 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
3691
3692 if (cmd_buffer) {
3693 if (cmd_buffer->pool) {
3694 list_del(&cmd_buffer->pool_link);
3695 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
3696 } else
3697 radv_destroy_cmd_buffer(cmd_buffer);
3698
3699 }
3700 }
3701 }
3702
3703 VkResult radv_ResetCommandBuffer(
3704 VkCommandBuffer commandBuffer,
3705 VkCommandBufferResetFlags flags)
3706 {
3707 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3708 return radv_reset_cmd_buffer(cmd_buffer);
3709 }
3710
3711 VkResult radv_BeginCommandBuffer(
3712 VkCommandBuffer commandBuffer,
3713 const VkCommandBufferBeginInfo *pBeginInfo)
3714 {
3715 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3716 VkResult result = VK_SUCCESS;
3717
3718 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
3719 /* If the command buffer has already been resetted with
3720 * vkResetCommandBuffer, no need to do it again.
3721 */
3722 result = radv_reset_cmd_buffer(cmd_buffer);
3723 if (result != VK_SUCCESS)
3724 return result;
3725 }
3726
3727 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
3728 cmd_buffer->state.last_primitive_reset_en = -1;
3729 cmd_buffer->state.last_index_type = -1;
3730 cmd_buffer->state.last_num_instances = -1;
3731 cmd_buffer->state.last_vertex_offset = -1;
3732 cmd_buffer->state.last_first_instance = -1;
3733 cmd_buffer->state.predication_type = -1;
3734 cmd_buffer->state.last_sx_ps_downconvert = -1;
3735 cmd_buffer->state.last_sx_blend_opt_epsilon = -1;
3736 cmd_buffer->state.last_sx_blend_opt_control = -1;
3737 cmd_buffer->usage_flags = pBeginInfo->flags;
3738
3739 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
3740 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
3741 assert(pBeginInfo->pInheritanceInfo);
3742 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
3743 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
3744
3745 struct radv_subpass *subpass =
3746 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
3747
3748 if (cmd_buffer->state.framebuffer) {
3749 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
3750 if (result != VK_SUCCESS)
3751 return result;
3752 }
3753
3754 cmd_buffer->state.inherited_pipeline_statistics =
3755 pBeginInfo->pInheritanceInfo->pipelineStatistics;
3756
3757 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3758 }
3759
3760 if (unlikely(cmd_buffer->device->trace_bo))
3761 radv_cmd_buffer_trace_emit(cmd_buffer);
3762
3763 radv_describe_begin_cmd_buffer(cmd_buffer);
3764
3765 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
3766
3767 return result;
3768 }
3769
3770 void radv_CmdBindVertexBuffers(
3771 VkCommandBuffer commandBuffer,
3772 uint32_t firstBinding,
3773 uint32_t bindingCount,
3774 const VkBuffer* pBuffers,
3775 const VkDeviceSize* pOffsets)
3776 {
3777 radv_CmdBindVertexBuffers2EXT(commandBuffer, firstBinding,
3778 bindingCount, pBuffers, pOffsets,
3779 NULL, NULL);
3780 }
3781
3782 void radv_CmdBindVertexBuffers2EXT(
3783 VkCommandBuffer commandBuffer,
3784 uint32_t firstBinding,
3785 uint32_t bindingCount,
3786 const VkBuffer* pBuffers,
3787 const VkDeviceSize* pOffsets,
3788 const VkDeviceSize* pSizes,
3789 const VkDeviceSize* pStrides)
3790 {
3791 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3792 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
3793 bool changed = false;
3794
3795 /* We have to defer setting up vertex buffer since we need the buffer
3796 * stride from the pipeline. */
3797
3798 assert(firstBinding + bindingCount <= MAX_VBS);
3799 for (uint32_t i = 0; i < bindingCount; i++) {
3800 RADV_FROM_HANDLE(radv_buffer, buffer, pBuffers[i]);
3801 uint32_t idx = firstBinding + i;
3802 VkDeviceSize size = pSizes ? pSizes[i] : 0;
3803 VkDeviceSize stride = pStrides ? pStrides[i] : 0;
3804
3805 /* pSizes and pStrides are optional. */
3806 if (!changed &&
3807 (vb[idx].buffer != buffer ||
3808 vb[idx].offset != pOffsets[i] ||
3809 vb[idx].size != size ||
3810 vb[idx].stride != stride)) {
3811 changed = true;
3812 }
3813
3814 vb[idx].buffer = buffer;
3815 vb[idx].offset = pOffsets[i];
3816 vb[idx].size = size;
3817 vb[idx].stride = stride;
3818
3819 if (buffer) {
3820 radv_cs_add_buffer(cmd_buffer->device->ws,
3821 cmd_buffer->cs, vb[idx].buffer->bo);
3822 }
3823 }
3824
3825 if (!changed) {
3826 /* No state changes. */
3827 return;
3828 }
3829
3830 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
3831 }
3832
3833 static uint32_t
3834 vk_to_index_type(VkIndexType type)
3835 {
3836 switch (type) {
3837 case VK_INDEX_TYPE_UINT8_EXT:
3838 return V_028A7C_VGT_INDEX_8;
3839 case VK_INDEX_TYPE_UINT16:
3840 return V_028A7C_VGT_INDEX_16;
3841 case VK_INDEX_TYPE_UINT32:
3842 return V_028A7C_VGT_INDEX_32;
3843 default:
3844 unreachable("invalid index type");
3845 }
3846 }
3847
3848 static uint32_t
3849 radv_get_vgt_index_size(uint32_t type)
3850 {
3851 switch (type) {
3852 case V_028A7C_VGT_INDEX_8:
3853 return 1;
3854 case V_028A7C_VGT_INDEX_16:
3855 return 2;
3856 case V_028A7C_VGT_INDEX_32:
3857 return 4;
3858 default:
3859 unreachable("invalid index type");
3860 }
3861 }
3862
3863 void radv_CmdBindIndexBuffer(
3864 VkCommandBuffer commandBuffer,
3865 VkBuffer buffer,
3866 VkDeviceSize offset,
3867 VkIndexType indexType)
3868 {
3869 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3870 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
3871
3872 if (cmd_buffer->state.index_buffer == index_buffer &&
3873 cmd_buffer->state.index_offset == offset &&
3874 cmd_buffer->state.index_type == indexType) {
3875 /* No state changes. */
3876 return;
3877 }
3878
3879 cmd_buffer->state.index_buffer = index_buffer;
3880 cmd_buffer->state.index_offset = offset;
3881 cmd_buffer->state.index_type = vk_to_index_type(indexType);
3882 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
3883 cmd_buffer->state.index_va += index_buffer->offset + offset;
3884
3885 int index_size = radv_get_vgt_index_size(vk_to_index_type(indexType));
3886 cmd_buffer->state.max_index_count = (index_buffer->size - offset) / index_size;
3887 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3888 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
3889 }
3890
3891
3892 static void
3893 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3894 VkPipelineBindPoint bind_point,
3895 struct radv_descriptor_set *set, unsigned idx)
3896 {
3897 struct radeon_winsys *ws = cmd_buffer->device->ws;
3898
3899 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
3900
3901 assert(set);
3902 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
3903
3904 if (!cmd_buffer->device->use_global_bo_list) {
3905 for (unsigned j = 0; j < set->buffer_count; ++j)
3906 if (set->descriptors[j])
3907 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
3908 }
3909
3910 if(set->bo)
3911 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
3912 }
3913
3914 void radv_CmdBindDescriptorSets(
3915 VkCommandBuffer commandBuffer,
3916 VkPipelineBindPoint pipelineBindPoint,
3917 VkPipelineLayout _layout,
3918 uint32_t firstSet,
3919 uint32_t descriptorSetCount,
3920 const VkDescriptorSet* pDescriptorSets,
3921 uint32_t dynamicOffsetCount,
3922 const uint32_t* pDynamicOffsets)
3923 {
3924 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3925 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3926 unsigned dyn_idx = 0;
3927
3928 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
3929 struct radv_descriptor_state *descriptors_state =
3930 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3931
3932 for (unsigned i = 0; i < descriptorSetCount; ++i) {
3933 unsigned idx = i + firstSet;
3934 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
3935
3936 /* If the set is already bound we only need to update the
3937 * (potentially changed) dynamic offsets. */
3938 if (descriptors_state->sets[idx] != set ||
3939 !(descriptors_state->valid & (1u << idx))) {
3940 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
3941 }
3942
3943 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
3944 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
3945 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
3946 assert(dyn_idx < dynamicOffsetCount);
3947
3948 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
3949 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
3950 dst[0] = va;
3951 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
3952 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
3953 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3954 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3955 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3956 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3957
3958 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
3959 dst[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3960 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3961 S_008F0C_RESOURCE_LEVEL(1);
3962 } else {
3963 dst[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3964 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3965 }
3966
3967 cmd_buffer->push_constant_stages |=
3968 set->layout->dynamic_shader_stages;
3969 }
3970 }
3971 }
3972
3973 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3974 struct radv_descriptor_set *set,
3975 struct radv_descriptor_set_layout *layout,
3976 VkPipelineBindPoint bind_point)
3977 {
3978 struct radv_descriptor_state *descriptors_state =
3979 radv_get_descriptors_state(cmd_buffer, bind_point);
3980 set->size = layout->size;
3981 set->layout = layout;
3982
3983 if (descriptors_state->push_set.capacity < set->size) {
3984 size_t new_size = MAX2(set->size, 1024);
3985 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
3986 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
3987
3988 free(set->mapped_ptr);
3989 set->mapped_ptr = malloc(new_size);
3990
3991 if (!set->mapped_ptr) {
3992 descriptors_state->push_set.capacity = 0;
3993 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3994 return false;
3995 }
3996
3997 descriptors_state->push_set.capacity = new_size;
3998 }
3999
4000 return true;
4001 }
4002
4003 void radv_meta_push_descriptor_set(
4004 struct radv_cmd_buffer* cmd_buffer,
4005 VkPipelineBindPoint pipelineBindPoint,
4006 VkPipelineLayout _layout,
4007 uint32_t set,
4008 uint32_t descriptorWriteCount,
4009 const VkWriteDescriptorSet* pDescriptorWrites)
4010 {
4011 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
4012 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
4013 unsigned bo_offset;
4014
4015 assert(set == 0);
4016 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
4017
4018 push_set->size = layout->set[set].layout->size;
4019 push_set->layout = layout->set[set].layout;
4020
4021 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
4022 &bo_offset,
4023 (void**) &push_set->mapped_ptr))
4024 return;
4025
4026 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
4027 push_set->va += bo_offset;
4028
4029 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
4030 radv_descriptor_set_to_handle(push_set),
4031 descriptorWriteCount, pDescriptorWrites, 0, NULL);
4032
4033 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
4034 }
4035
4036 void radv_CmdPushDescriptorSetKHR(
4037 VkCommandBuffer commandBuffer,
4038 VkPipelineBindPoint pipelineBindPoint,
4039 VkPipelineLayout _layout,
4040 uint32_t set,
4041 uint32_t descriptorWriteCount,
4042 const VkWriteDescriptorSet* pDescriptorWrites)
4043 {
4044 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4045 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
4046 struct radv_descriptor_state *descriptors_state =
4047 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
4048 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
4049
4050 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
4051
4052 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
4053 layout->set[set].layout,
4054 pipelineBindPoint))
4055 return;
4056
4057 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
4058 * because it is invalid, according to Vulkan spec.
4059 */
4060 for (int i = 0; i < descriptorWriteCount; i++) {
4061 ASSERTED const VkWriteDescriptorSet *writeset = &pDescriptorWrites[i];
4062 assert(writeset->descriptorType != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT);
4063 }
4064
4065 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
4066 radv_descriptor_set_to_handle(push_set),
4067 descriptorWriteCount, pDescriptorWrites, 0, NULL);
4068
4069 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
4070 descriptors_state->push_dirty = true;
4071 }
4072
4073 void radv_CmdPushDescriptorSetWithTemplateKHR(
4074 VkCommandBuffer commandBuffer,
4075 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
4076 VkPipelineLayout _layout,
4077 uint32_t set,
4078 const void* pData)
4079 {
4080 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4081 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
4082 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
4083 struct radv_descriptor_state *descriptors_state =
4084 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
4085 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
4086
4087 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
4088
4089 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
4090 layout->set[set].layout,
4091 templ->bind_point))
4092 return;
4093
4094 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
4095 descriptorUpdateTemplate, pData);
4096
4097 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
4098 descriptors_state->push_dirty = true;
4099 }
4100
4101 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
4102 VkPipelineLayout layout,
4103 VkShaderStageFlags stageFlags,
4104 uint32_t offset,
4105 uint32_t size,
4106 const void* pValues)
4107 {
4108 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4109 memcpy(cmd_buffer->push_constants + offset, pValues, size);
4110 cmd_buffer->push_constant_stages |= stageFlags;
4111 }
4112
4113 VkResult radv_EndCommandBuffer(
4114 VkCommandBuffer commandBuffer)
4115 {
4116 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4117
4118 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
4119 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6)
4120 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WB_L2;
4121
4122 /* Make sure to sync all pending active queries at the end of
4123 * command buffer.
4124 */
4125 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
4126
4127 /* Since NGG streamout uses GDS, we need to make GDS idle when
4128 * we leave the IB, otherwise another process might overwrite
4129 * it while our shaders are busy.
4130 */
4131 if (cmd_buffer->gds_needed)
4132 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
4133
4134 si_emit_cache_flush(cmd_buffer);
4135 }
4136
4137 /* Make sure CP DMA is idle at the end of IBs because the kernel
4138 * doesn't wait for it.
4139 */
4140 si_cp_dma_wait_for_idle(cmd_buffer);
4141
4142 radv_describe_end_cmd_buffer(cmd_buffer);
4143
4144 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
4145 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
4146
4147 VkResult result = cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs);
4148 if (result != VK_SUCCESS)
4149 return vk_error(cmd_buffer->device->instance, result);
4150
4151 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
4152
4153 return cmd_buffer->record_result;
4154 }
4155
4156 static void
4157 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
4158 {
4159 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4160
4161 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
4162 return;
4163
4164 assert(!pipeline->ctx_cs.cdw);
4165
4166 cmd_buffer->state.emitted_compute_pipeline = pipeline;
4167
4168 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
4169 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
4170
4171 cmd_buffer->compute_scratch_size_per_wave_needed = MAX2(cmd_buffer->compute_scratch_size_per_wave_needed,
4172 pipeline->scratch_bytes_per_wave);
4173 cmd_buffer->compute_scratch_waves_wanted = MAX2(cmd_buffer->compute_scratch_waves_wanted,
4174 pipeline->max_waves);
4175
4176 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
4177 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
4178
4179 if (unlikely(cmd_buffer->device->trace_bo))
4180 radv_save_pipeline(cmd_buffer, pipeline);
4181 }
4182
4183 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
4184 VkPipelineBindPoint bind_point)
4185 {
4186 struct radv_descriptor_state *descriptors_state =
4187 radv_get_descriptors_state(cmd_buffer, bind_point);
4188
4189 descriptors_state->dirty |= descriptors_state->valid;
4190 }
4191
4192 void radv_CmdBindPipeline(
4193 VkCommandBuffer commandBuffer,
4194 VkPipelineBindPoint pipelineBindPoint,
4195 VkPipeline _pipeline)
4196 {
4197 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4198 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
4199
4200 switch (pipelineBindPoint) {
4201 case VK_PIPELINE_BIND_POINT_COMPUTE:
4202 if (cmd_buffer->state.compute_pipeline == pipeline)
4203 return;
4204 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
4205
4206 cmd_buffer->state.compute_pipeline = pipeline;
4207 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
4208 break;
4209 case VK_PIPELINE_BIND_POINT_GRAPHICS:
4210 if (cmd_buffer->state.pipeline == pipeline)
4211 return;
4212 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
4213
4214 cmd_buffer->state.pipeline = pipeline;
4215 if (!pipeline)
4216 break;
4217
4218 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
4219 cmd_buffer->push_constant_stages |= pipeline->active_stages;
4220
4221 /* the new vertex shader might not have the same user regs */
4222 cmd_buffer->state.last_first_instance = -1;
4223 cmd_buffer->state.last_vertex_offset = -1;
4224
4225 /* Prefetch all pipeline shaders at first draw time. */
4226 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
4227
4228 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX10 &&
4229 cmd_buffer->state.emitted_pipeline &&
4230 radv_pipeline_has_ngg(cmd_buffer->state.emitted_pipeline) &&
4231 !radv_pipeline_has_ngg(cmd_buffer->state.pipeline)) {
4232 /* Transitioning from NGG to legacy GS requires
4233 * VGT_FLUSH on Navi10-14. VGT_FLUSH is also emitted
4234 * at the beginning of IBs when legacy GS ring pointers
4235 * are set.
4236 */
4237 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
4238 }
4239
4240 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
4241 radv_bind_streamout_state(cmd_buffer, pipeline);
4242
4243 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
4244 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
4245 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
4246 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
4247
4248 if (radv_pipeline_has_tess(pipeline))
4249 cmd_buffer->tess_rings_needed = true;
4250 break;
4251 default:
4252 assert(!"invalid bind point");
4253 break;
4254 }
4255 }
4256
4257 void radv_CmdSetViewport(
4258 VkCommandBuffer commandBuffer,
4259 uint32_t firstViewport,
4260 uint32_t viewportCount,
4261 const VkViewport* pViewports)
4262 {
4263 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4264 struct radv_cmd_state *state = &cmd_buffer->state;
4265 ASSERTED const uint32_t total_count = firstViewport + viewportCount;
4266
4267 assert(firstViewport < MAX_VIEWPORTS);
4268 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
4269
4270 if (total_count <= state->dynamic.viewport.count &&
4271 !memcmp(state->dynamic.viewport.viewports + firstViewport,
4272 pViewports, viewportCount * sizeof(*pViewports))) {
4273 return;
4274 }
4275
4276 if (state->dynamic.viewport.count < total_count)
4277 state->dynamic.viewport.count = total_count;
4278
4279 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
4280 viewportCount * sizeof(*pViewports));
4281
4282 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
4283 }
4284
4285 void radv_CmdSetScissor(
4286 VkCommandBuffer commandBuffer,
4287 uint32_t firstScissor,
4288 uint32_t scissorCount,
4289 const VkRect2D* pScissors)
4290 {
4291 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4292 struct radv_cmd_state *state = &cmd_buffer->state;
4293 ASSERTED const uint32_t total_count = firstScissor + scissorCount;
4294
4295 assert(firstScissor < MAX_SCISSORS);
4296 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
4297
4298 if (total_count <= state->dynamic.scissor.count &&
4299 !memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
4300 scissorCount * sizeof(*pScissors))) {
4301 return;
4302 }
4303
4304 if (state->dynamic.scissor.count < total_count)
4305 state->dynamic.scissor.count = total_count;
4306
4307 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
4308 scissorCount * sizeof(*pScissors));
4309
4310 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
4311 }
4312
4313 void radv_CmdSetLineWidth(
4314 VkCommandBuffer commandBuffer,
4315 float lineWidth)
4316 {
4317 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4318
4319 if (cmd_buffer->state.dynamic.line_width == lineWidth)
4320 return;
4321
4322 cmd_buffer->state.dynamic.line_width = lineWidth;
4323 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
4324 }
4325
4326 void radv_CmdSetDepthBias(
4327 VkCommandBuffer commandBuffer,
4328 float depthBiasConstantFactor,
4329 float depthBiasClamp,
4330 float depthBiasSlopeFactor)
4331 {
4332 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4333 struct radv_cmd_state *state = &cmd_buffer->state;
4334
4335 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
4336 state->dynamic.depth_bias.clamp == depthBiasClamp &&
4337 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
4338 return;
4339 }
4340
4341 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
4342 state->dynamic.depth_bias.clamp = depthBiasClamp;
4343 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
4344
4345 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
4346 }
4347
4348 void radv_CmdSetBlendConstants(
4349 VkCommandBuffer commandBuffer,
4350 const float blendConstants[4])
4351 {
4352 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4353 struct radv_cmd_state *state = &cmd_buffer->state;
4354
4355 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
4356 return;
4357
4358 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
4359
4360 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
4361 }
4362
4363 void radv_CmdSetDepthBounds(
4364 VkCommandBuffer commandBuffer,
4365 float minDepthBounds,
4366 float maxDepthBounds)
4367 {
4368 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4369 struct radv_cmd_state *state = &cmd_buffer->state;
4370
4371 if (state->dynamic.depth_bounds.min == minDepthBounds &&
4372 state->dynamic.depth_bounds.max == maxDepthBounds) {
4373 return;
4374 }
4375
4376 state->dynamic.depth_bounds.min = minDepthBounds;
4377 state->dynamic.depth_bounds.max = maxDepthBounds;
4378
4379 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
4380 }
4381
4382 void radv_CmdSetStencilCompareMask(
4383 VkCommandBuffer commandBuffer,
4384 VkStencilFaceFlags faceMask,
4385 uint32_t compareMask)
4386 {
4387 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4388 struct radv_cmd_state *state = &cmd_buffer->state;
4389 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
4390 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
4391
4392 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4393 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4394 return;
4395 }
4396
4397 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4398 state->dynamic.stencil_compare_mask.front = compareMask;
4399 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4400 state->dynamic.stencil_compare_mask.back = compareMask;
4401
4402 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
4403 }
4404
4405 void radv_CmdSetStencilWriteMask(
4406 VkCommandBuffer commandBuffer,
4407 VkStencilFaceFlags faceMask,
4408 uint32_t writeMask)
4409 {
4410 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4411 struct radv_cmd_state *state = &cmd_buffer->state;
4412 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
4413 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
4414
4415 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4416 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4417 return;
4418 }
4419
4420 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4421 state->dynamic.stencil_write_mask.front = writeMask;
4422 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4423 state->dynamic.stencil_write_mask.back = writeMask;
4424
4425 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
4426 }
4427
4428 void radv_CmdSetStencilReference(
4429 VkCommandBuffer commandBuffer,
4430 VkStencilFaceFlags faceMask,
4431 uint32_t reference)
4432 {
4433 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4434 struct radv_cmd_state *state = &cmd_buffer->state;
4435 bool front_same = state->dynamic.stencil_reference.front == reference;
4436 bool back_same = state->dynamic.stencil_reference.back == reference;
4437
4438 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4439 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4440 return;
4441 }
4442
4443 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4444 cmd_buffer->state.dynamic.stencil_reference.front = reference;
4445 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4446 cmd_buffer->state.dynamic.stencil_reference.back = reference;
4447
4448 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
4449 }
4450
4451 void radv_CmdSetDiscardRectangleEXT(
4452 VkCommandBuffer commandBuffer,
4453 uint32_t firstDiscardRectangle,
4454 uint32_t discardRectangleCount,
4455 const VkRect2D* pDiscardRectangles)
4456 {
4457 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4458 struct radv_cmd_state *state = &cmd_buffer->state;
4459 ASSERTED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
4460
4461 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
4462 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
4463
4464 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
4465 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
4466 return;
4467 }
4468
4469 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
4470 pDiscardRectangles, discardRectangleCount);
4471
4472 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
4473 }
4474
4475 void radv_CmdSetSampleLocationsEXT(
4476 VkCommandBuffer commandBuffer,
4477 const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
4478 {
4479 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4480 struct radv_cmd_state *state = &cmd_buffer->state;
4481
4482 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
4483
4484 state->dynamic.sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
4485 state->dynamic.sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
4486 state->dynamic.sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
4487 typed_memcpy(&state->dynamic.sample_location.locations[0],
4488 pSampleLocationsInfo->pSampleLocations,
4489 pSampleLocationsInfo->sampleLocationsCount);
4490
4491 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS;
4492 }
4493
4494 void radv_CmdSetLineStippleEXT(
4495 VkCommandBuffer commandBuffer,
4496 uint32_t lineStippleFactor,
4497 uint16_t lineStipplePattern)
4498 {
4499 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4500 struct radv_cmd_state *state = &cmd_buffer->state;
4501
4502 state->dynamic.line_stipple.factor = lineStippleFactor;
4503 state->dynamic.line_stipple.pattern = lineStipplePattern;
4504
4505 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE;
4506 }
4507
4508 void radv_CmdSetCullModeEXT(
4509 VkCommandBuffer commandBuffer,
4510 VkCullModeFlags cullMode)
4511 {
4512 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4513 struct radv_cmd_state *state = &cmd_buffer->state;
4514
4515 if (state->dynamic.cull_mode == cullMode)
4516 return;
4517
4518 state->dynamic.cull_mode = cullMode;
4519
4520 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_CULL_MODE;
4521 }
4522
4523 void radv_CmdSetFrontFaceEXT(
4524 VkCommandBuffer commandBuffer,
4525 VkFrontFace frontFace)
4526 {
4527 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4528 struct radv_cmd_state *state = &cmd_buffer->state;
4529
4530 if (state->dynamic.front_face == frontFace)
4531 return;
4532
4533 state->dynamic.front_face = frontFace;
4534
4535 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE;
4536 }
4537
4538 void radv_CmdSetPrimitiveTopologyEXT(
4539 VkCommandBuffer commandBuffer,
4540 VkPrimitiveTopology primitiveTopology)
4541 {
4542 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4543 struct radv_cmd_state *state = &cmd_buffer->state;
4544 unsigned primitive_topology = si_translate_prim(primitiveTopology);
4545
4546 if (state->dynamic.primitive_topology == primitive_topology)
4547 return;
4548
4549 state->dynamic.primitive_topology = primitive_topology;
4550
4551 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY;
4552 }
4553
4554 void radv_CmdSetViewportWithCountEXT(
4555 VkCommandBuffer commandBuffer,
4556 uint32_t viewportCount,
4557 const VkViewport* pViewports)
4558 {
4559 radv_CmdSetViewport(commandBuffer, 0, viewportCount, pViewports);
4560 }
4561
4562 void radv_CmdSetScissorWithCountEXT(
4563 VkCommandBuffer commandBuffer,
4564 uint32_t scissorCount,
4565 const VkRect2D* pScissors)
4566 {
4567 radv_CmdSetScissor(commandBuffer, 0, scissorCount, pScissors);
4568 }
4569
4570 void radv_CmdSetDepthTestEnableEXT(
4571 VkCommandBuffer commandBuffer,
4572 VkBool32 depthTestEnable)
4573
4574 {
4575 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4576 struct radv_cmd_state *state = &cmd_buffer->state;
4577
4578 if (state->dynamic.depth_test_enable == depthTestEnable)
4579 return;
4580
4581 state->dynamic.depth_test_enable = depthTestEnable;
4582
4583 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE;
4584 }
4585
4586 void radv_CmdSetDepthWriteEnableEXT(
4587 VkCommandBuffer commandBuffer,
4588 VkBool32 depthWriteEnable)
4589 {
4590 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4591 struct radv_cmd_state *state = &cmd_buffer->state;
4592
4593 if (state->dynamic.depth_write_enable == depthWriteEnable)
4594 return;
4595
4596 state->dynamic.depth_write_enable = depthWriteEnable;
4597
4598 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE;
4599 }
4600
4601 void radv_CmdSetDepthCompareOpEXT(
4602 VkCommandBuffer commandBuffer,
4603 VkCompareOp depthCompareOp)
4604 {
4605 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4606 struct radv_cmd_state *state = &cmd_buffer->state;
4607
4608 if (state->dynamic.depth_compare_op == depthCompareOp)
4609 return;
4610
4611 state->dynamic.depth_compare_op = depthCompareOp;
4612
4613 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP;
4614 }
4615
4616 void radv_CmdSetDepthBoundsTestEnableEXT(
4617 VkCommandBuffer commandBuffer,
4618 VkBool32 depthBoundsTestEnable)
4619 {
4620 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4621 struct radv_cmd_state *state = &cmd_buffer->state;
4622
4623 if (state->dynamic.depth_bounds_test_enable == depthBoundsTestEnable)
4624 return;
4625
4626 state->dynamic.depth_bounds_test_enable = depthBoundsTestEnable;
4627
4628 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE;
4629 }
4630
4631 void radv_CmdSetStencilTestEnableEXT(
4632 VkCommandBuffer commandBuffer,
4633 VkBool32 stencilTestEnable)
4634 {
4635 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4636 struct radv_cmd_state *state = &cmd_buffer->state;
4637
4638 if (state->dynamic.stencil_test_enable == stencilTestEnable)
4639 return;
4640
4641 state->dynamic.stencil_test_enable = stencilTestEnable;
4642
4643 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE;
4644 }
4645
4646 void radv_CmdSetStencilOpEXT(
4647 VkCommandBuffer commandBuffer,
4648 VkStencilFaceFlags faceMask,
4649 VkStencilOp failOp,
4650 VkStencilOp passOp,
4651 VkStencilOp depthFailOp,
4652 VkCompareOp compareOp)
4653 {
4654 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4655 struct radv_cmd_state *state = &cmd_buffer->state;
4656 bool front_same =
4657 state->dynamic.stencil_op.front.fail_op == failOp &&
4658 state->dynamic.stencil_op.front.pass_op == passOp &&
4659 state->dynamic.stencil_op.front.depth_fail_op == depthFailOp &&
4660 state->dynamic.stencil_op.front.compare_op == compareOp;
4661 bool back_same =
4662 state->dynamic.stencil_op.back.fail_op == failOp &&
4663 state->dynamic.stencil_op.back.pass_op == passOp &&
4664 state->dynamic.stencil_op.back.depth_fail_op == depthFailOp &&
4665 state->dynamic.stencil_op.back.compare_op == compareOp;
4666
4667 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4668 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same))
4669 return;
4670
4671 if (faceMask & VK_STENCIL_FACE_FRONT_BIT) {
4672 state->dynamic.stencil_op.front.fail_op = failOp;
4673 state->dynamic.stencil_op.front.pass_op = passOp;
4674 state->dynamic.stencil_op.front.depth_fail_op = depthFailOp;
4675 state->dynamic.stencil_op.front.compare_op = compareOp;
4676 }
4677
4678 if (faceMask & VK_STENCIL_FACE_BACK_BIT) {
4679 state->dynamic.stencil_op.back.fail_op = failOp;
4680 state->dynamic.stencil_op.back.pass_op = passOp;
4681 state->dynamic.stencil_op.back.depth_fail_op = depthFailOp;
4682 state->dynamic.stencil_op.back.compare_op = compareOp;
4683 }
4684
4685 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP;
4686 }
4687
4688 void radv_CmdExecuteCommands(
4689 VkCommandBuffer commandBuffer,
4690 uint32_t commandBufferCount,
4691 const VkCommandBuffer* pCmdBuffers)
4692 {
4693 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
4694
4695 assert(commandBufferCount > 0);
4696
4697 /* Emit pending flushes on primary prior to executing secondary */
4698 si_emit_cache_flush(primary);
4699
4700 for (uint32_t i = 0; i < commandBufferCount; i++) {
4701 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
4702
4703 primary->scratch_size_per_wave_needed = MAX2(primary->scratch_size_per_wave_needed,
4704 secondary->scratch_size_per_wave_needed);
4705 primary->scratch_waves_wanted = MAX2(primary->scratch_waves_wanted,
4706 secondary->scratch_waves_wanted);
4707 primary->compute_scratch_size_per_wave_needed = MAX2(primary->compute_scratch_size_per_wave_needed,
4708 secondary->compute_scratch_size_per_wave_needed);
4709 primary->compute_scratch_waves_wanted = MAX2(primary->compute_scratch_waves_wanted,
4710 secondary->compute_scratch_waves_wanted);
4711
4712 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
4713 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
4714 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
4715 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
4716 if (secondary->tess_rings_needed)
4717 primary->tess_rings_needed = true;
4718 if (secondary->sample_positions_needed)
4719 primary->sample_positions_needed = true;
4720 if (secondary->gds_needed)
4721 primary->gds_needed = true;
4722
4723 if (!secondary->state.framebuffer &&
4724 (primary->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)) {
4725 /* Emit the framebuffer state from primary if secondary
4726 * has been recorded without a framebuffer, otherwise
4727 * fast color/depth clears can't work.
4728 */
4729 radv_emit_framebuffer_state(primary);
4730 }
4731
4732 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
4733
4734
4735 /* When the secondary command buffer is compute only we don't
4736 * need to re-emit the current graphics pipeline.
4737 */
4738 if (secondary->state.emitted_pipeline) {
4739 primary->state.emitted_pipeline =
4740 secondary->state.emitted_pipeline;
4741 }
4742
4743 /* When the secondary command buffer is graphics only we don't
4744 * need to re-emit the current compute pipeline.
4745 */
4746 if (secondary->state.emitted_compute_pipeline) {
4747 primary->state.emitted_compute_pipeline =
4748 secondary->state.emitted_compute_pipeline;
4749 }
4750
4751 /* Only re-emit the draw packets when needed. */
4752 if (secondary->state.last_primitive_reset_en != -1) {
4753 primary->state.last_primitive_reset_en =
4754 secondary->state.last_primitive_reset_en;
4755 }
4756
4757 if (secondary->state.last_primitive_reset_index) {
4758 primary->state.last_primitive_reset_index =
4759 secondary->state.last_primitive_reset_index;
4760 }
4761
4762 if (secondary->state.last_ia_multi_vgt_param) {
4763 primary->state.last_ia_multi_vgt_param =
4764 secondary->state.last_ia_multi_vgt_param;
4765 }
4766
4767 primary->state.last_first_instance = secondary->state.last_first_instance;
4768 primary->state.last_num_instances = secondary->state.last_num_instances;
4769 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
4770 primary->state.last_sx_ps_downconvert = secondary->state.last_sx_ps_downconvert;
4771 primary->state.last_sx_blend_opt_epsilon = secondary->state.last_sx_blend_opt_epsilon;
4772 primary->state.last_sx_blend_opt_control = secondary->state.last_sx_blend_opt_control;
4773
4774 if (secondary->state.last_index_type != -1) {
4775 primary->state.last_index_type =
4776 secondary->state.last_index_type;
4777 }
4778 }
4779
4780 /* After executing commands from secondary buffers we have to dirty
4781 * some states.
4782 */
4783 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
4784 RADV_CMD_DIRTY_INDEX_BUFFER |
4785 RADV_CMD_DIRTY_DYNAMIC_ALL;
4786 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
4787 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
4788 }
4789
4790 VkResult radv_CreateCommandPool(
4791 VkDevice _device,
4792 const VkCommandPoolCreateInfo* pCreateInfo,
4793 const VkAllocationCallbacks* pAllocator,
4794 VkCommandPool* pCmdPool)
4795 {
4796 RADV_FROM_HANDLE(radv_device, device, _device);
4797 struct radv_cmd_pool *pool;
4798
4799 pool = vk_alloc2(&device->vk.alloc, pAllocator, sizeof(*pool), 8,
4800 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4801 if (pool == NULL)
4802 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4803
4804 vk_object_base_init(&device->vk, &pool->base,
4805 VK_OBJECT_TYPE_COMMAND_POOL);
4806
4807 if (pAllocator)
4808 pool->alloc = *pAllocator;
4809 else
4810 pool->alloc = device->vk.alloc;
4811
4812 list_inithead(&pool->cmd_buffers);
4813 list_inithead(&pool->free_cmd_buffers);
4814
4815 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
4816
4817 *pCmdPool = radv_cmd_pool_to_handle(pool);
4818
4819 return VK_SUCCESS;
4820
4821 }
4822
4823 void radv_DestroyCommandPool(
4824 VkDevice _device,
4825 VkCommandPool commandPool,
4826 const VkAllocationCallbacks* pAllocator)
4827 {
4828 RADV_FROM_HANDLE(radv_device, device, _device);
4829 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4830
4831 if (!pool)
4832 return;
4833
4834 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4835 &pool->cmd_buffers, pool_link) {
4836 radv_destroy_cmd_buffer(cmd_buffer);
4837 }
4838
4839 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4840 &pool->free_cmd_buffers, pool_link) {
4841 radv_destroy_cmd_buffer(cmd_buffer);
4842 }
4843
4844 vk_object_base_finish(&pool->base);
4845 vk_free2(&device->vk.alloc, pAllocator, pool);
4846 }
4847
4848 VkResult radv_ResetCommandPool(
4849 VkDevice device,
4850 VkCommandPool commandPool,
4851 VkCommandPoolResetFlags flags)
4852 {
4853 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4854 VkResult result;
4855
4856 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
4857 &pool->cmd_buffers, pool_link) {
4858 result = radv_reset_cmd_buffer(cmd_buffer);
4859 if (result != VK_SUCCESS)
4860 return result;
4861 }
4862
4863 return VK_SUCCESS;
4864 }
4865
4866 void radv_TrimCommandPool(
4867 VkDevice device,
4868 VkCommandPool commandPool,
4869 VkCommandPoolTrimFlags flags)
4870 {
4871 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4872
4873 if (!pool)
4874 return;
4875
4876 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4877 &pool->free_cmd_buffers, pool_link) {
4878 radv_destroy_cmd_buffer(cmd_buffer);
4879 }
4880 }
4881
4882 static void
4883 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
4884 uint32_t subpass_id)
4885 {
4886 struct radv_cmd_state *state = &cmd_buffer->state;
4887 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
4888
4889 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
4890 cmd_buffer->cs, 4096);
4891
4892 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
4893
4894 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
4895
4896 radv_describe_barrier_start(cmd_buffer, RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC);
4897
4898 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4899 const uint32_t a = subpass->attachments[i].attachment;
4900 if (a == VK_ATTACHMENT_UNUSED)
4901 continue;
4902
4903 radv_handle_subpass_image_transition(cmd_buffer,
4904 subpass->attachments[i],
4905 true);
4906 }
4907
4908 radv_describe_barrier_end(cmd_buffer);
4909
4910 radv_cmd_buffer_clear_subpass(cmd_buffer);
4911
4912 assert(cmd_buffer->cs->cdw <= cdw_max);
4913 }
4914
4915 static void
4916 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
4917 {
4918 struct radv_cmd_state *state = &cmd_buffer->state;
4919 const struct radv_subpass *subpass = state->subpass;
4920 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
4921
4922 radv_cmd_buffer_resolve_subpass(cmd_buffer);
4923
4924 radv_describe_barrier_start(cmd_buffer, RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC);
4925
4926 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4927 const uint32_t a = subpass->attachments[i].attachment;
4928 if (a == VK_ATTACHMENT_UNUSED)
4929 continue;
4930
4931 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
4932 continue;
4933
4934 VkImageLayout layout = state->pass->attachments[a].final_layout;
4935 VkImageLayout stencil_layout = state->pass->attachments[a].stencil_final_layout;
4936 struct radv_subpass_attachment att = { a, layout, stencil_layout };
4937 radv_handle_subpass_image_transition(cmd_buffer, att, false);
4938 }
4939
4940 radv_describe_barrier_end(cmd_buffer);
4941 }
4942
4943 void
4944 radv_cmd_buffer_begin_render_pass(struct radv_cmd_buffer *cmd_buffer,
4945 const VkRenderPassBeginInfo *pRenderPassBegin)
4946 {
4947 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
4948 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
4949 VkResult result;
4950
4951 cmd_buffer->state.framebuffer = framebuffer;
4952 cmd_buffer->state.pass = pass;
4953 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
4954
4955 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
4956 if (result != VK_SUCCESS)
4957 return;
4958
4959 result = radv_cmd_state_setup_sample_locations(cmd_buffer, pass, pRenderPassBegin);
4960 if (result != VK_SUCCESS)
4961 return;
4962 }
4963
4964 void radv_CmdBeginRenderPass(
4965 VkCommandBuffer commandBuffer,
4966 const VkRenderPassBeginInfo* pRenderPassBegin,
4967 VkSubpassContents contents)
4968 {
4969 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4970
4971 radv_cmd_buffer_begin_render_pass(cmd_buffer, pRenderPassBegin);
4972
4973 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
4974 }
4975
4976 void radv_CmdBeginRenderPass2(
4977 VkCommandBuffer commandBuffer,
4978 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
4979 const VkSubpassBeginInfo* pSubpassBeginInfo)
4980 {
4981 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
4982 pSubpassBeginInfo->contents);
4983 }
4984
4985 void radv_CmdNextSubpass(
4986 VkCommandBuffer commandBuffer,
4987 VkSubpassContents contents)
4988 {
4989 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4990
4991 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
4992 radv_cmd_buffer_end_subpass(cmd_buffer);
4993 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
4994 }
4995
4996 void radv_CmdNextSubpass2(
4997 VkCommandBuffer commandBuffer,
4998 const VkSubpassBeginInfo* pSubpassBeginInfo,
4999 const VkSubpassEndInfo* pSubpassEndInfo)
5000 {
5001 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
5002 }
5003
5004 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
5005 {
5006 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
5007 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
5008 if (!radv_get_shader(pipeline, stage))
5009 continue;
5010
5011 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
5012 if (loc->sgpr_idx == -1)
5013 continue;
5014 uint32_t base_reg = pipeline->user_data_0[stage];
5015 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
5016
5017 }
5018 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
5019 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
5020 if (loc->sgpr_idx != -1) {
5021 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
5022 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
5023 }
5024 }
5025 }
5026
5027 static void
5028 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
5029 uint32_t vertex_count,
5030 bool use_opaque)
5031 {
5032 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
5033 radeon_emit(cmd_buffer->cs, vertex_count);
5034 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
5035 S_0287F0_USE_OPAQUE(use_opaque));
5036 }
5037
5038 static void
5039 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
5040 uint64_t index_va,
5041 uint32_t index_count)
5042 {
5043 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
5044 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
5045 radeon_emit(cmd_buffer->cs, index_va);
5046 radeon_emit(cmd_buffer->cs, index_va >> 32);
5047 radeon_emit(cmd_buffer->cs, index_count);
5048 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
5049 }
5050
5051 static void
5052 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
5053 bool indexed,
5054 uint32_t draw_count,
5055 uint64_t count_va,
5056 uint32_t stride)
5057 {
5058 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5059 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
5060 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
5061 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id;
5062 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
5063 bool predicating = cmd_buffer->state.predicating;
5064 assert(base_reg);
5065
5066 /* just reset draw state for vertex data */
5067 cmd_buffer->state.last_first_instance = -1;
5068 cmd_buffer->state.last_num_instances = -1;
5069 cmd_buffer->state.last_vertex_offset = -1;
5070
5071 if (draw_count == 1 && !count_va && !draw_id_enable) {
5072 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
5073 PKT3_DRAW_INDIRECT, 3, predicating));
5074 radeon_emit(cs, 0);
5075 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
5076 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
5077 radeon_emit(cs, di_src_sel);
5078 } else {
5079 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
5080 PKT3_DRAW_INDIRECT_MULTI,
5081 8, predicating));
5082 radeon_emit(cs, 0);
5083 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
5084 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
5085 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
5086 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
5087 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
5088 radeon_emit(cs, draw_count); /* count */
5089 radeon_emit(cs, count_va); /* count_addr */
5090 radeon_emit(cs, count_va >> 32);
5091 radeon_emit(cs, stride); /* stride */
5092 radeon_emit(cs, di_src_sel);
5093 }
5094 }
5095
5096 static void
5097 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
5098 const struct radv_draw_info *info)
5099 {
5100 struct radv_cmd_state *state = &cmd_buffer->state;
5101 struct radeon_winsys *ws = cmd_buffer->device->ws;
5102 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5103
5104 if (info->indirect) {
5105 uint64_t va = radv_buffer_get_va(info->indirect->bo);
5106 uint64_t count_va = 0;
5107
5108 va += info->indirect->offset + info->indirect_offset;
5109
5110 radv_cs_add_buffer(ws, cs, info->indirect->bo);
5111
5112 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
5113 radeon_emit(cs, 1);
5114 radeon_emit(cs, va);
5115 radeon_emit(cs, va >> 32);
5116
5117 if (info->count_buffer) {
5118 count_va = radv_buffer_get_va(info->count_buffer->bo);
5119 count_va += info->count_buffer->offset +
5120 info->count_buffer_offset;
5121
5122 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
5123 }
5124
5125 if (!state->subpass->view_mask) {
5126 radv_cs_emit_indirect_draw_packet(cmd_buffer,
5127 info->indexed,
5128 info->count,
5129 count_va,
5130 info->stride);
5131 } else {
5132 unsigned i;
5133 for_each_bit(i, state->subpass->view_mask) {
5134 radv_emit_view_index(cmd_buffer, i);
5135
5136 radv_cs_emit_indirect_draw_packet(cmd_buffer,
5137 info->indexed,
5138 info->count,
5139 count_va,
5140 info->stride);
5141 }
5142 }
5143 } else {
5144 assert(state->pipeline->graphics.vtx_base_sgpr);
5145
5146 if (info->vertex_offset != state->last_vertex_offset ||
5147 info->first_instance != state->last_first_instance) {
5148 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
5149 state->pipeline->graphics.vtx_emit_num);
5150
5151 radeon_emit(cs, info->vertex_offset);
5152 radeon_emit(cs, info->first_instance);
5153 if (state->pipeline->graphics.vtx_emit_num == 3)
5154 radeon_emit(cs, 0);
5155 state->last_first_instance = info->first_instance;
5156 state->last_vertex_offset = info->vertex_offset;
5157 }
5158
5159 if (state->last_num_instances != info->instance_count) {
5160 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
5161 radeon_emit(cs, info->instance_count);
5162 state->last_num_instances = info->instance_count;
5163 }
5164
5165 if (info->indexed) {
5166 int index_size = radv_get_vgt_index_size(state->index_type);
5167 uint64_t index_va;
5168
5169 /* Skip draw calls with 0-sized index buffers. They
5170 * cause a hang on some chips, like Navi10-14.
5171 */
5172 if (!cmd_buffer->state.max_index_count)
5173 return;
5174
5175 index_va = state->index_va;
5176 index_va += info->first_index * index_size;
5177
5178 if (!state->subpass->view_mask) {
5179 radv_cs_emit_draw_indexed_packet(cmd_buffer,
5180 index_va,
5181 info->count);
5182 } else {
5183 unsigned i;
5184 for_each_bit(i, state->subpass->view_mask) {
5185 radv_emit_view_index(cmd_buffer, i);
5186
5187 radv_cs_emit_draw_indexed_packet(cmd_buffer,
5188 index_va,
5189 info->count);
5190 }
5191 }
5192 } else {
5193 if (!state->subpass->view_mask) {
5194 radv_cs_emit_draw_packet(cmd_buffer,
5195 info->count,
5196 !!info->strmout_buffer);
5197 } else {
5198 unsigned i;
5199 for_each_bit(i, state->subpass->view_mask) {
5200 radv_emit_view_index(cmd_buffer, i);
5201
5202 radv_cs_emit_draw_packet(cmd_buffer,
5203 info->count,
5204 !!info->strmout_buffer);
5205 }
5206 }
5207 }
5208 }
5209 }
5210
5211 /*
5212 * Vega and raven have a bug which triggers if there are multiple context
5213 * register contexts active at the same time with different scissor values.
5214 *
5215 * There are two possible workarounds:
5216 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
5217 * there is only ever 1 active set of scissor values at the same time.
5218 *
5219 * 2) Whenever the hardware switches contexts we have to set the scissor
5220 * registers again even if it is a noop. That way the new context gets
5221 * the correct scissor values.
5222 *
5223 * This implements option 2. radv_need_late_scissor_emission needs to
5224 * return true on affected HW if radv_emit_all_graphics_states sets
5225 * any context registers.
5226 */
5227 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
5228 const struct radv_draw_info *info)
5229 {
5230 struct radv_cmd_state *state = &cmd_buffer->state;
5231
5232 if (!cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
5233 return false;
5234
5235 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
5236 return true;
5237
5238 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
5239
5240 /* Index, vertex and streamout buffers don't change context regs, and
5241 * pipeline is already handled.
5242 */
5243 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
5244 RADV_CMD_DIRTY_VERTEX_BUFFER |
5245 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
5246 RADV_CMD_DIRTY_PIPELINE);
5247
5248 if (cmd_buffer->state.dirty & used_states)
5249 return true;
5250
5251 uint32_t primitive_reset_index =
5252 radv_get_primitive_reset_index(cmd_buffer);
5253
5254 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
5255 primitive_reset_index != state->last_primitive_reset_index)
5256 return true;
5257
5258 return false;
5259 }
5260
5261 static void
5262 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
5263 const struct radv_draw_info *info)
5264 {
5265 bool late_scissor_emission;
5266
5267 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
5268 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
5269 radv_emit_rbplus_state(cmd_buffer);
5270
5271 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
5272 radv_emit_graphics_pipeline(cmd_buffer);
5273
5274 /* This should be before the cmd_buffer->state.dirty is cleared
5275 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
5276 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
5277 late_scissor_emission =
5278 radv_need_late_scissor_emission(cmd_buffer, info);
5279
5280 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
5281 radv_emit_framebuffer_state(cmd_buffer);
5282
5283 if (info->indexed) {
5284 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
5285 radv_emit_index_buffer(cmd_buffer, info->indirect);
5286 } else {
5287 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
5288 * so the state must be re-emitted before the next indexed
5289 * draw.
5290 */
5291 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
5292 cmd_buffer->state.last_index_type = -1;
5293 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
5294 }
5295 }
5296
5297 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
5298
5299 radv_emit_draw_registers(cmd_buffer, info);
5300
5301 if (late_scissor_emission)
5302 radv_emit_scissor(cmd_buffer);
5303 }
5304
5305 static void
5306 radv_draw(struct radv_cmd_buffer *cmd_buffer,
5307 const struct radv_draw_info *info)
5308 {
5309 struct radeon_info *rad_info =
5310 &cmd_buffer->device->physical_device->rad_info;
5311 bool has_prefetch =
5312 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
5313 bool pipeline_is_dirty =
5314 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
5315 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
5316
5317 ASSERTED unsigned cdw_max =
5318 radeon_check_space(cmd_buffer->device->ws,
5319 cmd_buffer->cs, 4096);
5320
5321 if (likely(!info->indirect)) {
5322 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
5323 * no workaround for indirect draws, but we can at least skip
5324 * direct draws.
5325 */
5326 if (unlikely(!info->instance_count))
5327 return;
5328
5329 /* Handle count == 0. */
5330 if (unlikely(!info->count && !info->strmout_buffer))
5331 return;
5332 }
5333
5334 radv_describe_draw(cmd_buffer);
5335
5336 /* Use optimal packet order based on whether we need to sync the
5337 * pipeline.
5338 */
5339 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5340 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5341 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
5342 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
5343 /* If we have to wait for idle, set all states first, so that
5344 * all SET packets are processed in parallel with previous draw
5345 * calls. Then upload descriptors, set shader pointers, and
5346 * draw, and prefetch at the end. This ensures that the time
5347 * the CUs are idle is very short. (there are only SET_SH
5348 * packets between the wait and the draw)
5349 */
5350 radv_emit_all_graphics_states(cmd_buffer, info);
5351 si_emit_cache_flush(cmd_buffer);
5352 /* <-- CUs are idle here --> */
5353
5354 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
5355
5356 radv_emit_draw_packets(cmd_buffer, info);
5357 /* <-- CUs are busy here --> */
5358
5359 /* Start prefetches after the draw has been started. Both will
5360 * run in parallel, but starting the draw first is more
5361 * important.
5362 */
5363 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
5364 radv_emit_prefetch_L2(cmd_buffer,
5365 cmd_buffer->state.pipeline, false);
5366 }
5367 } else {
5368 /* If we don't wait for idle, start prefetches first, then set
5369 * states, and draw at the end.
5370 */
5371 si_emit_cache_flush(cmd_buffer);
5372
5373 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
5374 /* Only prefetch the vertex shader and VBO descriptors
5375 * in order to start the draw as soon as possible.
5376 */
5377 radv_emit_prefetch_L2(cmd_buffer,
5378 cmd_buffer->state.pipeline, true);
5379 }
5380
5381 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
5382
5383 radv_emit_all_graphics_states(cmd_buffer, info);
5384 radv_emit_draw_packets(cmd_buffer, info);
5385
5386 /* Prefetch the remaining shaders after the draw has been
5387 * started.
5388 */
5389 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
5390 radv_emit_prefetch_L2(cmd_buffer,
5391 cmd_buffer->state.pipeline, false);
5392 }
5393 }
5394
5395 /* Workaround for a VGT hang when streamout is enabled.
5396 * It must be done after drawing.
5397 */
5398 if (cmd_buffer->state.streamout.streamout_enabled &&
5399 (rad_info->family == CHIP_HAWAII ||
5400 rad_info->family == CHIP_TONGA ||
5401 rad_info->family == CHIP_FIJI)) {
5402 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
5403 }
5404
5405 assert(cmd_buffer->cs->cdw <= cdw_max);
5406 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
5407 }
5408
5409 void radv_CmdDraw(
5410 VkCommandBuffer commandBuffer,
5411 uint32_t vertexCount,
5412 uint32_t instanceCount,
5413 uint32_t firstVertex,
5414 uint32_t firstInstance)
5415 {
5416 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5417 struct radv_draw_info info = {};
5418
5419 info.count = vertexCount;
5420 info.instance_count = instanceCount;
5421 info.first_instance = firstInstance;
5422 info.vertex_offset = firstVertex;
5423
5424 radv_draw(cmd_buffer, &info);
5425 }
5426
5427 void radv_CmdDrawIndexed(
5428 VkCommandBuffer commandBuffer,
5429 uint32_t indexCount,
5430 uint32_t instanceCount,
5431 uint32_t firstIndex,
5432 int32_t vertexOffset,
5433 uint32_t firstInstance)
5434 {
5435 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5436 struct radv_draw_info info = {};
5437
5438 info.indexed = true;
5439 info.count = indexCount;
5440 info.instance_count = instanceCount;
5441 info.first_index = firstIndex;
5442 info.vertex_offset = vertexOffset;
5443 info.first_instance = firstInstance;
5444
5445 radv_draw(cmd_buffer, &info);
5446 }
5447
5448 void radv_CmdDrawIndirect(
5449 VkCommandBuffer commandBuffer,
5450 VkBuffer _buffer,
5451 VkDeviceSize offset,
5452 uint32_t drawCount,
5453 uint32_t stride)
5454 {
5455 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5456 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5457 struct radv_draw_info info = {};
5458
5459 info.count = drawCount;
5460 info.indirect = buffer;
5461 info.indirect_offset = offset;
5462 info.stride = stride;
5463
5464 radv_draw(cmd_buffer, &info);
5465 }
5466
5467 void radv_CmdDrawIndexedIndirect(
5468 VkCommandBuffer commandBuffer,
5469 VkBuffer _buffer,
5470 VkDeviceSize offset,
5471 uint32_t drawCount,
5472 uint32_t stride)
5473 {
5474 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5475 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5476 struct radv_draw_info info = {};
5477
5478 info.indexed = true;
5479 info.count = drawCount;
5480 info.indirect = buffer;
5481 info.indirect_offset = offset;
5482 info.stride = stride;
5483
5484 radv_draw(cmd_buffer, &info);
5485 }
5486
5487 void radv_CmdDrawIndirectCount(
5488 VkCommandBuffer commandBuffer,
5489 VkBuffer _buffer,
5490 VkDeviceSize offset,
5491 VkBuffer _countBuffer,
5492 VkDeviceSize countBufferOffset,
5493 uint32_t maxDrawCount,
5494 uint32_t stride)
5495 {
5496 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5497 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5498 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
5499 struct radv_draw_info info = {};
5500
5501 info.count = maxDrawCount;
5502 info.indirect = buffer;
5503 info.indirect_offset = offset;
5504 info.count_buffer = count_buffer;
5505 info.count_buffer_offset = countBufferOffset;
5506 info.stride = stride;
5507
5508 radv_draw(cmd_buffer, &info);
5509 }
5510
5511 void radv_CmdDrawIndexedIndirectCount(
5512 VkCommandBuffer commandBuffer,
5513 VkBuffer _buffer,
5514 VkDeviceSize offset,
5515 VkBuffer _countBuffer,
5516 VkDeviceSize countBufferOffset,
5517 uint32_t maxDrawCount,
5518 uint32_t stride)
5519 {
5520 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5521 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5522 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
5523 struct radv_draw_info info = {};
5524
5525 info.indexed = true;
5526 info.count = maxDrawCount;
5527 info.indirect = buffer;
5528 info.indirect_offset = offset;
5529 info.count_buffer = count_buffer;
5530 info.count_buffer_offset = countBufferOffset;
5531 info.stride = stride;
5532
5533 radv_draw(cmd_buffer, &info);
5534 }
5535
5536 struct radv_dispatch_info {
5537 /**
5538 * Determine the layout of the grid (in block units) to be used.
5539 */
5540 uint32_t blocks[3];
5541
5542 /**
5543 * A starting offset for the grid. If unaligned is set, the offset
5544 * must still be aligned.
5545 */
5546 uint32_t offsets[3];
5547 /**
5548 * Whether it's an unaligned compute dispatch.
5549 */
5550 bool unaligned;
5551
5552 /**
5553 * Indirect compute parameters resource.
5554 */
5555 struct radv_buffer *indirect;
5556 uint64_t indirect_offset;
5557 };
5558
5559 static void
5560 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
5561 const struct radv_dispatch_info *info)
5562 {
5563 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
5564 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
5565 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
5566 struct radeon_winsys *ws = cmd_buffer->device->ws;
5567 bool predicating = cmd_buffer->state.predicating;
5568 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5569 struct radv_userdata_info *loc;
5570
5571 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
5572 AC_UD_CS_GRID_SIZE);
5573
5574 ASSERTED unsigned cdw_max = radeon_check_space(ws, cs, 25);
5575
5576 if (compute_shader->info.wave_size == 32) {
5577 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
5578 dispatch_initiator |= S_00B800_CS_W32_EN(1);
5579 }
5580
5581 if (info->indirect) {
5582 uint64_t va = radv_buffer_get_va(info->indirect->bo);
5583
5584 va += info->indirect->offset + info->indirect_offset;
5585
5586 radv_cs_add_buffer(ws, cs, info->indirect->bo);
5587
5588 if (loc->sgpr_idx != -1) {
5589 for (unsigned i = 0; i < 3; ++i) {
5590 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5591 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5592 COPY_DATA_DST_SEL(COPY_DATA_REG));
5593 radeon_emit(cs, (va + 4 * i));
5594 radeon_emit(cs, (va + 4 * i) >> 32);
5595 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
5596 + loc->sgpr_idx * 4) >> 2) + i);
5597 radeon_emit(cs, 0);
5598 }
5599 }
5600
5601 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
5602 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
5603 PKT3_SHADER_TYPE_S(1));
5604 radeon_emit(cs, va);
5605 radeon_emit(cs, va >> 32);
5606 radeon_emit(cs, dispatch_initiator);
5607 } else {
5608 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
5609 PKT3_SHADER_TYPE_S(1));
5610 radeon_emit(cs, 1);
5611 radeon_emit(cs, va);
5612 radeon_emit(cs, va >> 32);
5613
5614 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
5615 PKT3_SHADER_TYPE_S(1));
5616 radeon_emit(cs, 0);
5617 radeon_emit(cs, dispatch_initiator);
5618 }
5619 } else {
5620 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
5621 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
5622
5623 if (info->unaligned) {
5624 unsigned *cs_block_size = compute_shader->info.cs.block_size;
5625 unsigned remainder[3];
5626
5627 /* If aligned, these should be an entire block size,
5628 * not 0.
5629 */
5630 remainder[0] = blocks[0] + cs_block_size[0] -
5631 align_u32_npot(blocks[0], cs_block_size[0]);
5632 remainder[1] = blocks[1] + cs_block_size[1] -
5633 align_u32_npot(blocks[1], cs_block_size[1]);
5634 remainder[2] = blocks[2] + cs_block_size[2] -
5635 align_u32_npot(blocks[2], cs_block_size[2]);
5636
5637 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
5638 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
5639 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
5640
5641 for(unsigned i = 0; i < 3; ++i) {
5642 assert(offsets[i] % cs_block_size[i] == 0);
5643 offsets[i] /= cs_block_size[i];
5644 }
5645
5646 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
5647 radeon_emit(cs,
5648 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
5649 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
5650 radeon_emit(cs,
5651 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
5652 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
5653 radeon_emit(cs,
5654 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
5655 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
5656
5657 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
5658 }
5659
5660 if (loc->sgpr_idx != -1) {
5661 assert(loc->num_sgprs == 3);
5662
5663 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
5664 loc->sgpr_idx * 4, 3);
5665 radeon_emit(cs, blocks[0]);
5666 radeon_emit(cs, blocks[1]);
5667 radeon_emit(cs, blocks[2]);
5668 }
5669
5670 if (offsets[0] || offsets[1] || offsets[2]) {
5671 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
5672 radeon_emit(cs, offsets[0]);
5673 radeon_emit(cs, offsets[1]);
5674 radeon_emit(cs, offsets[2]);
5675
5676 /* The blocks in the packet are not counts but end values. */
5677 for (unsigned i = 0; i < 3; ++i)
5678 blocks[i] += offsets[i];
5679 } else {
5680 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
5681 }
5682
5683 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
5684 PKT3_SHADER_TYPE_S(1));
5685 radeon_emit(cs, blocks[0]);
5686 radeon_emit(cs, blocks[1]);
5687 radeon_emit(cs, blocks[2]);
5688 radeon_emit(cs, dispatch_initiator);
5689 }
5690
5691 assert(cmd_buffer->cs->cdw <= cdw_max);
5692 }
5693
5694 static void
5695 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
5696 {
5697 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
5698 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
5699 }
5700
5701 static void
5702 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
5703 const struct radv_dispatch_info *info)
5704 {
5705 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
5706 bool has_prefetch =
5707 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
5708 bool pipeline_is_dirty = pipeline &&
5709 pipeline != cmd_buffer->state.emitted_compute_pipeline;
5710
5711 radv_describe_dispatch(cmd_buffer, 8, 8, 8);
5712
5713 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5714 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5715 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
5716 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
5717 /* If we have to wait for idle, set all states first, so that
5718 * all SET packets are processed in parallel with previous draw
5719 * calls. Then upload descriptors, set shader pointers, and
5720 * dispatch, and prefetch at the end. This ensures that the
5721 * time the CUs are idle is very short. (there are only SET_SH
5722 * packets between the wait and the draw)
5723 */
5724 radv_emit_compute_pipeline(cmd_buffer);
5725 si_emit_cache_flush(cmd_buffer);
5726 /* <-- CUs are idle here --> */
5727
5728 radv_upload_compute_shader_descriptors(cmd_buffer);
5729
5730 radv_emit_dispatch_packets(cmd_buffer, info);
5731 /* <-- CUs are busy here --> */
5732
5733 /* Start prefetches after the dispatch has been started. Both
5734 * will run in parallel, but starting the dispatch first is
5735 * more important.
5736 */
5737 if (has_prefetch && pipeline_is_dirty) {
5738 radv_emit_shader_prefetch(cmd_buffer,
5739 pipeline->shaders[MESA_SHADER_COMPUTE]);
5740 }
5741 } else {
5742 /* If we don't wait for idle, start prefetches first, then set
5743 * states, and dispatch at the end.
5744 */
5745 si_emit_cache_flush(cmd_buffer);
5746
5747 if (has_prefetch && pipeline_is_dirty) {
5748 radv_emit_shader_prefetch(cmd_buffer,
5749 pipeline->shaders[MESA_SHADER_COMPUTE]);
5750 }
5751
5752 radv_upload_compute_shader_descriptors(cmd_buffer);
5753
5754 radv_emit_compute_pipeline(cmd_buffer);
5755 radv_emit_dispatch_packets(cmd_buffer, info);
5756 }
5757
5758 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
5759 }
5760
5761 void radv_CmdDispatchBase(
5762 VkCommandBuffer commandBuffer,
5763 uint32_t base_x,
5764 uint32_t base_y,
5765 uint32_t base_z,
5766 uint32_t x,
5767 uint32_t y,
5768 uint32_t z)
5769 {
5770 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5771 struct radv_dispatch_info info = {};
5772
5773 info.blocks[0] = x;
5774 info.blocks[1] = y;
5775 info.blocks[2] = z;
5776
5777 info.offsets[0] = base_x;
5778 info.offsets[1] = base_y;
5779 info.offsets[2] = base_z;
5780 radv_dispatch(cmd_buffer, &info);
5781 }
5782
5783 void radv_CmdDispatch(
5784 VkCommandBuffer commandBuffer,
5785 uint32_t x,
5786 uint32_t y,
5787 uint32_t z)
5788 {
5789 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
5790 }
5791
5792 void radv_CmdDispatchIndirect(
5793 VkCommandBuffer commandBuffer,
5794 VkBuffer _buffer,
5795 VkDeviceSize offset)
5796 {
5797 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5798 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5799 struct radv_dispatch_info info = {};
5800
5801 info.indirect = buffer;
5802 info.indirect_offset = offset;
5803
5804 radv_dispatch(cmd_buffer, &info);
5805 }
5806
5807 void radv_unaligned_dispatch(
5808 struct radv_cmd_buffer *cmd_buffer,
5809 uint32_t x,
5810 uint32_t y,
5811 uint32_t z)
5812 {
5813 struct radv_dispatch_info info = {};
5814
5815 info.blocks[0] = x;
5816 info.blocks[1] = y;
5817 info.blocks[2] = z;
5818 info.unaligned = 1;
5819
5820 radv_dispatch(cmd_buffer, &info);
5821 }
5822
5823 void
5824 radv_cmd_buffer_end_render_pass(struct radv_cmd_buffer *cmd_buffer)
5825 {
5826 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
5827 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
5828
5829 cmd_buffer->state.pass = NULL;
5830 cmd_buffer->state.subpass = NULL;
5831 cmd_buffer->state.attachments = NULL;
5832 cmd_buffer->state.framebuffer = NULL;
5833 cmd_buffer->state.subpass_sample_locs = NULL;
5834 }
5835
5836 void radv_CmdEndRenderPass(
5837 VkCommandBuffer commandBuffer)
5838 {
5839 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5840
5841 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
5842
5843 radv_cmd_buffer_end_subpass(cmd_buffer);
5844
5845 radv_cmd_buffer_end_render_pass(cmd_buffer);
5846 }
5847
5848 void radv_CmdEndRenderPass2(
5849 VkCommandBuffer commandBuffer,
5850 const VkSubpassEndInfo* pSubpassEndInfo)
5851 {
5852 radv_CmdEndRenderPass(commandBuffer);
5853 }
5854
5855 /*
5856 * For HTILE we have the following interesting clear words:
5857 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
5858 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
5859 * 0xfffffff0: Clear depth to 1.0
5860 * 0x00000000: Clear depth to 0.0
5861 */
5862 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
5863 struct radv_image *image,
5864 const VkImageSubresourceRange *range)
5865 {
5866 assert(range->baseMipLevel == 0);
5867 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
5868 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
5869 struct radv_cmd_state *state = &cmd_buffer->state;
5870 uint32_t htile_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
5871 VkClearDepthStencilValue value = {};
5872 struct radv_barrier_data barrier = {};
5873
5874 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5875 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5876
5877 barrier.layout_transitions.init_mask_ram = 1;
5878 radv_describe_layout_transition(cmd_buffer, &barrier);
5879
5880 state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, htile_value);
5881
5882 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5883
5884 if (vk_format_is_stencil(image->vk_format))
5885 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
5886
5887 radv_set_ds_clear_metadata(cmd_buffer, image, range, value, aspects);
5888
5889 if (radv_image_is_tc_compat_htile(image)) {
5890 /* Initialize the TC-compat metada value to 0 because by
5891 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
5892 * need have to conditionally update its value when performing
5893 * a fast depth clear.
5894 */
5895 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, range, 0);
5896 }
5897 }
5898
5899 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
5900 struct radv_image *image,
5901 VkImageLayout src_layout,
5902 bool src_render_loop,
5903 VkImageLayout dst_layout,
5904 bool dst_render_loop,
5905 unsigned src_queue_mask,
5906 unsigned dst_queue_mask,
5907 const VkImageSubresourceRange *range,
5908 struct radv_sample_locations_state *sample_locs)
5909 {
5910 if (!radv_image_has_htile(image))
5911 return;
5912
5913 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5914 radv_initialize_htile(cmd_buffer, image, range);
5915 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5916 radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5917 radv_initialize_htile(cmd_buffer, image, range);
5918 } else if (radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5919 !radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5920 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5921 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5922
5923 radv_decompress_depth_stencil(cmd_buffer, image, range,
5924 sample_locs);
5925
5926 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5927 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5928 }
5929 }
5930
5931 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
5932 struct radv_image *image,
5933 const VkImageSubresourceRange *range,
5934 uint32_t value)
5935 {
5936 struct radv_cmd_state *state = &cmd_buffer->state;
5937 struct radv_barrier_data barrier = {};
5938
5939 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5940 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5941
5942 barrier.layout_transitions.init_mask_ram = 1;
5943 radv_describe_layout_transition(cmd_buffer, &barrier);
5944
5945 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, range, value);
5946
5947 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5948 }
5949
5950 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
5951 struct radv_image *image,
5952 const VkImageSubresourceRange *range)
5953 {
5954 struct radv_cmd_state *state = &cmd_buffer->state;
5955 static const uint32_t fmask_clear_values[4] = {
5956 0x00000000,
5957 0x02020202,
5958 0xE4E4E4E4,
5959 0x76543210
5960 };
5961 uint32_t log2_samples = util_logbase2(image->info.samples);
5962 uint32_t value = fmask_clear_values[log2_samples];
5963 struct radv_barrier_data barrier = {};
5964
5965 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5966 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5967
5968 barrier.layout_transitions.init_mask_ram = 1;
5969 radv_describe_layout_transition(cmd_buffer, &barrier);
5970
5971 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, range, value);
5972
5973 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5974 }
5975
5976 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
5977 struct radv_image *image,
5978 const VkImageSubresourceRange *range, uint32_t value)
5979 {
5980 struct radv_cmd_state *state = &cmd_buffer->state;
5981 struct radv_barrier_data barrier = {};
5982 unsigned size = 0;
5983
5984 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5985 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5986
5987 barrier.layout_transitions.init_mask_ram = 1;
5988 radv_describe_layout_transition(cmd_buffer, &barrier);
5989
5990 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
5991
5992 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) {
5993 /* When DCC is enabled with mipmaps, some levels might not
5994 * support fast clears and we have to initialize them as "fully
5995 * expanded".
5996 */
5997 /* Compute the size of all fast clearable DCC levels. */
5998 for (unsigned i = 0; i < image->planes[0].surface.num_dcc_levels; i++) {
5999 struct legacy_surf_level *surf_level =
6000 &image->planes[0].surface.u.legacy.level[i];
6001 unsigned dcc_fast_clear_size =
6002 surf_level->dcc_slice_fast_clear_size * image->info.array_size;
6003
6004 if (!dcc_fast_clear_size)
6005 break;
6006
6007 size = surf_level->dcc_offset + dcc_fast_clear_size;
6008 }
6009
6010 /* Initialize the mipmap levels without DCC. */
6011 if (size != image->planes[0].surface.dcc_size) {
6012 state->flush_bits |=
6013 radv_fill_buffer(cmd_buffer, image->bo,
6014 image->offset + image->planes[0].surface.dcc_offset + size,
6015 image->planes[0].surface.dcc_size - size,
6016 0xffffffff);
6017 }
6018 }
6019
6020 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
6021 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
6022 }
6023
6024 /**
6025 * Initialize DCC/FMASK/CMASK metadata for a color image.
6026 */
6027 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
6028 struct radv_image *image,
6029 VkImageLayout src_layout,
6030 bool src_render_loop,
6031 VkImageLayout dst_layout,
6032 bool dst_render_loop,
6033 unsigned src_queue_mask,
6034 unsigned dst_queue_mask,
6035 const VkImageSubresourceRange *range)
6036 {
6037 if (radv_image_has_cmask(image)) {
6038 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
6039
6040 /* TODO: clarify this. */
6041 if (radv_image_has_fmask(image)) {
6042 value = 0xccccccccu;
6043 }
6044
6045 radv_initialise_cmask(cmd_buffer, image, range, value);
6046 }
6047
6048 if (radv_image_has_fmask(image)) {
6049 radv_initialize_fmask(cmd_buffer, image, range);
6050 }
6051
6052 if (radv_dcc_enabled(image, range->baseMipLevel)) {
6053 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
6054 bool need_decompress_pass = false;
6055
6056 if (radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout,
6057 dst_render_loop,
6058 dst_queue_mask)) {
6059 value = 0x20202020u;
6060 need_decompress_pass = true;
6061 }
6062
6063 radv_initialize_dcc(cmd_buffer, image, range, value);
6064
6065 radv_update_fce_metadata(cmd_buffer, image, range,
6066 need_decompress_pass);
6067 }
6068
6069 if (radv_image_has_cmask(image) ||
6070 radv_dcc_enabled(image, range->baseMipLevel)) {
6071 uint32_t color_values[2] = {};
6072 radv_set_color_clear_metadata(cmd_buffer, image, range,
6073 color_values);
6074 }
6075 }
6076
6077 /**
6078 * Handle color image transitions for DCC/FMASK/CMASK.
6079 */
6080 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
6081 struct radv_image *image,
6082 VkImageLayout src_layout,
6083 bool src_render_loop,
6084 VkImageLayout dst_layout,
6085 bool dst_render_loop,
6086 unsigned src_queue_mask,
6087 unsigned dst_queue_mask,
6088 const VkImageSubresourceRange *range)
6089 {
6090 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
6091 radv_init_color_image_metadata(cmd_buffer, image,
6092 src_layout, src_render_loop,
6093 dst_layout, dst_render_loop,
6094 src_queue_mask, dst_queue_mask,
6095 range);
6096 return;
6097 }
6098
6099 if (radv_dcc_enabled(image, range->baseMipLevel)) {
6100 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
6101 radv_initialize_dcc(cmd_buffer, image, range, 0xffffffffu);
6102 } else if (radv_layout_dcc_compressed(cmd_buffer->device, image, src_layout, src_render_loop, src_queue_mask) &&
6103 !radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout, dst_render_loop, dst_queue_mask)) {
6104 radv_decompress_dcc(cmd_buffer, image, range);
6105 } else if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
6106 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
6107 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
6108 }
6109 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
6110 bool fce_eliminate = false, fmask_expand = false;
6111
6112 if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
6113 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
6114 fce_eliminate = true;
6115 }
6116
6117 if (radv_image_has_fmask(image)) {
6118 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
6119 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
6120 /* A FMASK decompress is required before doing
6121 * a MSAA decompress using FMASK.
6122 */
6123 fmask_expand = true;
6124 }
6125 }
6126
6127 if (fce_eliminate || fmask_expand)
6128 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
6129
6130 if (fmask_expand) {
6131 struct radv_barrier_data barrier = {};
6132 barrier.layout_transitions.fmask_color_expand = 1;
6133 radv_describe_layout_transition(cmd_buffer, &barrier);
6134
6135 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
6136 }
6137 }
6138 }
6139
6140 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
6141 struct radv_image *image,
6142 VkImageLayout src_layout,
6143 bool src_render_loop,
6144 VkImageLayout dst_layout,
6145 bool dst_render_loop,
6146 uint32_t src_family,
6147 uint32_t dst_family,
6148 const VkImageSubresourceRange *range,
6149 struct radv_sample_locations_state *sample_locs)
6150 {
6151 if (image->exclusive && src_family != dst_family) {
6152 /* This is an acquire or a release operation and there will be
6153 * a corresponding release/acquire. Do the transition in the
6154 * most flexible queue. */
6155
6156 assert(src_family == cmd_buffer->queue_family_index ||
6157 dst_family == cmd_buffer->queue_family_index);
6158
6159 if (src_family == VK_QUEUE_FAMILY_EXTERNAL ||
6160 src_family == VK_QUEUE_FAMILY_FOREIGN_EXT)
6161 return;
6162
6163 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
6164 return;
6165
6166 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
6167 (src_family == RADV_QUEUE_GENERAL ||
6168 dst_family == RADV_QUEUE_GENERAL))
6169 return;
6170 }
6171
6172 if (src_layout == dst_layout)
6173 return;
6174
6175 unsigned src_queue_mask =
6176 radv_image_queue_family_mask(image, src_family,
6177 cmd_buffer->queue_family_index);
6178 unsigned dst_queue_mask =
6179 radv_image_queue_family_mask(image, dst_family,
6180 cmd_buffer->queue_family_index);
6181
6182 if (vk_format_is_depth(image->vk_format)) {
6183 radv_handle_depth_image_transition(cmd_buffer, image,
6184 src_layout, src_render_loop,
6185 dst_layout, dst_render_loop,
6186 src_queue_mask, dst_queue_mask,
6187 range, sample_locs);
6188 } else {
6189 radv_handle_color_image_transition(cmd_buffer, image,
6190 src_layout, src_render_loop,
6191 dst_layout, dst_render_loop,
6192 src_queue_mask, dst_queue_mask,
6193 range);
6194 }
6195 }
6196
6197 struct radv_barrier_info {
6198 enum rgp_barrier_reason reason;
6199 uint32_t eventCount;
6200 const VkEvent *pEvents;
6201 VkPipelineStageFlags srcStageMask;
6202 VkPipelineStageFlags dstStageMask;
6203 };
6204
6205 static void
6206 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
6207 uint32_t memoryBarrierCount,
6208 const VkMemoryBarrier *pMemoryBarriers,
6209 uint32_t bufferMemoryBarrierCount,
6210 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
6211 uint32_t imageMemoryBarrierCount,
6212 const VkImageMemoryBarrier *pImageMemoryBarriers,
6213 const struct radv_barrier_info *info)
6214 {
6215 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6216 enum radv_cmd_flush_bits src_flush_bits = 0;
6217 enum radv_cmd_flush_bits dst_flush_bits = 0;
6218
6219 radv_describe_barrier_start(cmd_buffer, info->reason);
6220
6221 for (unsigned i = 0; i < info->eventCount; ++i) {
6222 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
6223 uint64_t va = radv_buffer_get_va(event->bo);
6224
6225 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
6226
6227 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
6228
6229 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
6230 assert(cmd_buffer->cs->cdw <= cdw_max);
6231 }
6232
6233 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
6234 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
6235 NULL);
6236 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
6237 NULL);
6238 }
6239
6240 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
6241 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
6242 NULL);
6243 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
6244 NULL);
6245 }
6246
6247 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
6248 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
6249
6250 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
6251 image);
6252 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
6253 image);
6254 }
6255
6256 /* The Vulkan spec 1.1.98 says:
6257 *
6258 * "An execution dependency with only
6259 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
6260 * will only prevent that stage from executing in subsequently
6261 * submitted commands. As this stage does not perform any actual
6262 * execution, this is not observable - in effect, it does not delay
6263 * processing of subsequent commands. Similarly an execution dependency
6264 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
6265 * will effectively not wait for any prior commands to complete."
6266 */
6267 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
6268 radv_stage_flush(cmd_buffer, info->srcStageMask);
6269 cmd_buffer->state.flush_bits |= src_flush_bits;
6270
6271 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
6272 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
6273
6274 const struct VkSampleLocationsInfoEXT *sample_locs_info =
6275 vk_find_struct_const(pImageMemoryBarriers[i].pNext,
6276 SAMPLE_LOCATIONS_INFO_EXT);
6277 struct radv_sample_locations_state sample_locations = {};
6278
6279 if (sample_locs_info) {
6280 assert(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
6281 sample_locations.per_pixel = sample_locs_info->sampleLocationsPerPixel;
6282 sample_locations.grid_size = sample_locs_info->sampleLocationGridSize;
6283 sample_locations.count = sample_locs_info->sampleLocationsCount;
6284 typed_memcpy(&sample_locations.locations[0],
6285 sample_locs_info->pSampleLocations,
6286 sample_locs_info->sampleLocationsCount);
6287 }
6288
6289 radv_handle_image_transition(cmd_buffer, image,
6290 pImageMemoryBarriers[i].oldLayout,
6291 false, /* Outside of a renderpass we are never in a renderloop */
6292 pImageMemoryBarriers[i].newLayout,
6293 false, /* Outside of a renderpass we are never in a renderloop */
6294 pImageMemoryBarriers[i].srcQueueFamilyIndex,
6295 pImageMemoryBarriers[i].dstQueueFamilyIndex,
6296 &pImageMemoryBarriers[i].subresourceRange,
6297 sample_locs_info ? &sample_locations : NULL);
6298 }
6299
6300 /* Make sure CP DMA is idle because the driver might have performed a
6301 * DMA operation for copying or filling buffers/images.
6302 */
6303 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
6304 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
6305 si_cp_dma_wait_for_idle(cmd_buffer);
6306
6307 cmd_buffer->state.flush_bits |= dst_flush_bits;
6308
6309 radv_describe_barrier_end(cmd_buffer);
6310 }
6311
6312 void radv_CmdPipelineBarrier(
6313 VkCommandBuffer commandBuffer,
6314 VkPipelineStageFlags srcStageMask,
6315 VkPipelineStageFlags destStageMask,
6316 VkBool32 byRegion,
6317 uint32_t memoryBarrierCount,
6318 const VkMemoryBarrier* pMemoryBarriers,
6319 uint32_t bufferMemoryBarrierCount,
6320 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
6321 uint32_t imageMemoryBarrierCount,
6322 const VkImageMemoryBarrier* pImageMemoryBarriers)
6323 {
6324 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6325 struct radv_barrier_info info;
6326
6327 info.reason = RGP_BARRIER_EXTERNAL_CMD_PIPELINE_BARRIER;
6328 info.eventCount = 0;
6329 info.pEvents = NULL;
6330 info.srcStageMask = srcStageMask;
6331 info.dstStageMask = destStageMask;
6332
6333 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
6334 bufferMemoryBarrierCount, pBufferMemoryBarriers,
6335 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
6336 }
6337
6338
6339 static void write_event(struct radv_cmd_buffer *cmd_buffer,
6340 struct radv_event *event,
6341 VkPipelineStageFlags stageMask,
6342 unsigned value)
6343 {
6344 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6345 uint64_t va = radv_buffer_get_va(event->bo);
6346
6347 si_emit_cache_flush(cmd_buffer);
6348
6349 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
6350
6351 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 21);
6352
6353 /* Flags that only require a top-of-pipe event. */
6354 VkPipelineStageFlags top_of_pipe_flags =
6355 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
6356
6357 /* Flags that only require a post-index-fetch event. */
6358 VkPipelineStageFlags post_index_fetch_flags =
6359 top_of_pipe_flags |
6360 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
6361 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
6362
6363 /* Make sure CP DMA is idle because the driver might have performed a
6364 * DMA operation for copying or filling buffers/images.
6365 */
6366 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
6367 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
6368 si_cp_dma_wait_for_idle(cmd_buffer);
6369
6370 /* TODO: Emit EOS events for syncing PS/CS stages. */
6371
6372 if (!(stageMask & ~top_of_pipe_flags)) {
6373 /* Just need to sync the PFP engine. */
6374 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
6375 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
6376 S_370_WR_CONFIRM(1) |
6377 S_370_ENGINE_SEL(V_370_PFP));
6378 radeon_emit(cs, va);
6379 radeon_emit(cs, va >> 32);
6380 radeon_emit(cs, value);
6381 } else if (!(stageMask & ~post_index_fetch_flags)) {
6382 /* Sync ME because PFP reads index and indirect buffers. */
6383 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
6384 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
6385 S_370_WR_CONFIRM(1) |
6386 S_370_ENGINE_SEL(V_370_ME));
6387 radeon_emit(cs, va);
6388 radeon_emit(cs, va >> 32);
6389 radeon_emit(cs, value);
6390 } else {
6391 /* Otherwise, sync all prior GPU work using an EOP event. */
6392 si_cs_emit_write_event_eop(cs,
6393 cmd_buffer->device->physical_device->rad_info.chip_class,
6394 radv_cmd_buffer_uses_mec(cmd_buffer),
6395 V_028A90_BOTTOM_OF_PIPE_TS, 0,
6396 EOP_DST_SEL_MEM,
6397 EOP_DATA_SEL_VALUE_32BIT, va, value,
6398 cmd_buffer->gfx9_eop_bug_va);
6399 }
6400
6401 assert(cmd_buffer->cs->cdw <= cdw_max);
6402 }
6403
6404 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
6405 VkEvent _event,
6406 VkPipelineStageFlags stageMask)
6407 {
6408 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6409 RADV_FROM_HANDLE(radv_event, event, _event);
6410
6411 write_event(cmd_buffer, event, stageMask, 1);
6412 }
6413
6414 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
6415 VkEvent _event,
6416 VkPipelineStageFlags stageMask)
6417 {
6418 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6419 RADV_FROM_HANDLE(radv_event, event, _event);
6420
6421 write_event(cmd_buffer, event, stageMask, 0);
6422 }
6423
6424 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
6425 uint32_t eventCount,
6426 const VkEvent* pEvents,
6427 VkPipelineStageFlags srcStageMask,
6428 VkPipelineStageFlags dstStageMask,
6429 uint32_t memoryBarrierCount,
6430 const VkMemoryBarrier* pMemoryBarriers,
6431 uint32_t bufferMemoryBarrierCount,
6432 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
6433 uint32_t imageMemoryBarrierCount,
6434 const VkImageMemoryBarrier* pImageMemoryBarriers)
6435 {
6436 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6437 struct radv_barrier_info info;
6438
6439 info.reason = RGP_BARRIER_EXTERNAL_CMD_WAIT_EVENTS;
6440 info.eventCount = eventCount;
6441 info.pEvents = pEvents;
6442 info.srcStageMask = 0;
6443
6444 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
6445 bufferMemoryBarrierCount, pBufferMemoryBarriers,
6446 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
6447 }
6448
6449
6450 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
6451 uint32_t deviceMask)
6452 {
6453 /* No-op */
6454 }
6455
6456 /* VK_EXT_conditional_rendering */
6457 void radv_CmdBeginConditionalRenderingEXT(
6458 VkCommandBuffer commandBuffer,
6459 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
6460 {
6461 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6462 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
6463 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6464 bool draw_visible = true;
6465 uint64_t pred_value = 0;
6466 uint64_t va, new_va;
6467 unsigned pred_offset;
6468
6469 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
6470
6471 /* By default, if the 32-bit value at offset in buffer memory is zero,
6472 * then the rendering commands are discarded, otherwise they are
6473 * executed as normal. If the inverted flag is set, all commands are
6474 * discarded if the value is non zero.
6475 */
6476 if (pConditionalRenderingBegin->flags &
6477 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
6478 draw_visible = false;
6479 }
6480
6481 si_emit_cache_flush(cmd_buffer);
6482
6483 /* From the Vulkan spec 1.1.107:
6484 *
6485 * "If the 32-bit value at offset in buffer memory is zero, then the
6486 * rendering commands are discarded, otherwise they are executed as
6487 * normal. If the value of the predicate in buffer memory changes while
6488 * conditional rendering is active, the rendering commands may be
6489 * discarded in an implementation-dependent way. Some implementations
6490 * may latch the value of the predicate upon beginning conditional
6491 * rendering while others may read it before every rendering command."
6492 *
6493 * But, the AMD hardware treats the predicate as a 64-bit value which
6494 * means we need a workaround in the driver. Luckily, it's not required
6495 * to support if the value changes when predication is active.
6496 *
6497 * The workaround is as follows:
6498 * 1) allocate a 64-value in the upload BO and initialize it to 0
6499 * 2) copy the 32-bit predicate value to the upload BO
6500 * 3) use the new allocated VA address for predication
6501 *
6502 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
6503 * in ME (+ sync PFP) instead of PFP.
6504 */
6505 radv_cmd_buffer_upload_data(cmd_buffer, 8, 16, &pred_value, &pred_offset);
6506
6507 new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
6508
6509 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
6510 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
6511 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
6512 COPY_DATA_WR_CONFIRM);
6513 radeon_emit(cs, va);
6514 radeon_emit(cs, va >> 32);
6515 radeon_emit(cs, new_va);
6516 radeon_emit(cs, new_va >> 32);
6517
6518 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
6519 radeon_emit(cs, 0);
6520
6521 /* Enable predication for this command buffer. */
6522 si_emit_set_predication_state(cmd_buffer, draw_visible, new_va);
6523 cmd_buffer->state.predicating = true;
6524
6525 /* Store conditional rendering user info. */
6526 cmd_buffer->state.predication_type = draw_visible;
6527 cmd_buffer->state.predication_va = new_va;
6528 }
6529
6530 void radv_CmdEndConditionalRenderingEXT(
6531 VkCommandBuffer commandBuffer)
6532 {
6533 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6534
6535 /* Disable predication for this command buffer. */
6536 si_emit_set_predication_state(cmd_buffer, false, 0);
6537 cmd_buffer->state.predicating = false;
6538
6539 /* Reset conditional rendering user info. */
6540 cmd_buffer->state.predication_type = -1;
6541 cmd_buffer->state.predication_va = 0;
6542 }
6543
6544 /* VK_EXT_transform_feedback */
6545 void radv_CmdBindTransformFeedbackBuffersEXT(
6546 VkCommandBuffer commandBuffer,
6547 uint32_t firstBinding,
6548 uint32_t bindingCount,
6549 const VkBuffer* pBuffers,
6550 const VkDeviceSize* pOffsets,
6551 const VkDeviceSize* pSizes)
6552 {
6553 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6554 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
6555 uint8_t enabled_mask = 0;
6556
6557 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
6558 for (uint32_t i = 0; i < bindingCount; i++) {
6559 uint32_t idx = firstBinding + i;
6560
6561 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
6562 sb[idx].offset = pOffsets[i];
6563
6564 if (!pSizes || pSizes[i] == VK_WHOLE_SIZE) {
6565 sb[idx].size = sb[idx].buffer->size - sb[idx].offset;
6566 } else {
6567 sb[idx].size = pSizes[i];
6568 }
6569
6570 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
6571 sb[idx].buffer->bo);
6572
6573 enabled_mask |= 1 << idx;
6574 }
6575
6576 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
6577
6578 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
6579 }
6580
6581 static void
6582 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
6583 {
6584 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6585 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6586
6587 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
6588 radeon_emit(cs,
6589 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
6590 S_028B94_RAST_STREAM(0) |
6591 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
6592 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
6593 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
6594 radeon_emit(cs, so->hw_enabled_mask &
6595 so->enabled_stream_buffers_mask);
6596
6597 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6598 }
6599
6600 static void
6601 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
6602 {
6603 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6604 bool old_streamout_enabled = so->streamout_enabled;
6605 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
6606
6607 so->streamout_enabled = enable;
6608
6609 so->hw_enabled_mask = so->enabled_mask |
6610 (so->enabled_mask << 4) |
6611 (so->enabled_mask << 8) |
6612 (so->enabled_mask << 12);
6613
6614 if (!cmd_buffer->device->physical_device->use_ngg_streamout &&
6615 ((old_streamout_enabled != so->streamout_enabled) ||
6616 (old_hw_enabled_mask != so->hw_enabled_mask)))
6617 radv_emit_streamout_enable(cmd_buffer);
6618
6619 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6620 cmd_buffer->gds_needed = true;
6621 cmd_buffer->gds_oa_needed = true;
6622 }
6623 }
6624
6625 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
6626 {
6627 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6628 unsigned reg_strmout_cntl;
6629
6630 /* The register is at different places on different ASICs. */
6631 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
6632 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
6633 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
6634 } else {
6635 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
6636 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
6637 }
6638
6639 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
6640 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
6641
6642 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
6643 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
6644 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
6645 radeon_emit(cs, 0);
6646 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
6647 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
6648 radeon_emit(cs, 4); /* poll interval */
6649 }
6650
6651 static void
6652 radv_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
6653 uint32_t firstCounterBuffer,
6654 uint32_t counterBufferCount,
6655 const VkBuffer *pCounterBuffers,
6656 const VkDeviceSize *pCounterBufferOffsets)
6657
6658 {
6659 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
6660 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6661 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6662 uint32_t i;
6663
6664 radv_flush_vgt_streamout(cmd_buffer);
6665
6666 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6667 for_each_bit(i, so->enabled_mask) {
6668 int32_t counter_buffer_idx = i - firstCounterBuffer;
6669 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6670 counter_buffer_idx = -1;
6671
6672 /* AMD GCN binds streamout buffers as shader resources.
6673 * VGT only counts primitives and tells the shader through
6674 * SGPRs what to do.
6675 */
6676 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
6677 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
6678 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
6679
6680 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6681
6682 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6683 /* The array of counter buffers is optional. */
6684 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6685 uint64_t va = radv_buffer_get_va(buffer->bo);
6686
6687 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6688
6689 /* Append */
6690 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6691 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6692 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6693 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
6694 radeon_emit(cs, 0); /* unused */
6695 radeon_emit(cs, 0); /* unused */
6696 radeon_emit(cs, va); /* src address lo */
6697 radeon_emit(cs, va >> 32); /* src address hi */
6698
6699 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6700 } else {
6701 /* Start from the beginning. */
6702 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6703 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6704 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6705 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
6706 radeon_emit(cs, 0); /* unused */
6707 radeon_emit(cs, 0); /* unused */
6708 radeon_emit(cs, 0); /* unused */
6709 radeon_emit(cs, 0); /* unused */
6710 }
6711 }
6712
6713 radv_set_streamout_enable(cmd_buffer, true);
6714 }
6715
6716 static void
6717 gfx10_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
6718 uint32_t firstCounterBuffer,
6719 uint32_t counterBufferCount,
6720 const VkBuffer *pCounterBuffers,
6721 const VkDeviceSize *pCounterBufferOffsets)
6722 {
6723 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6724 unsigned last_target = util_last_bit(so->enabled_mask) - 1;
6725 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6726 uint32_t i;
6727
6728 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6729 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6730
6731 /* Sync because the next streamout operation will overwrite GDS and we
6732 * have to make sure it's idle.
6733 * TODO: Improve by tracking if there is a streamout operation in
6734 * flight.
6735 */
6736 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
6737 si_emit_cache_flush(cmd_buffer);
6738
6739 for_each_bit(i, so->enabled_mask) {
6740 int32_t counter_buffer_idx = i - firstCounterBuffer;
6741 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6742 counter_buffer_idx = -1;
6743
6744 bool append = counter_buffer_idx >= 0 &&
6745 pCounterBuffers && pCounterBuffers[counter_buffer_idx];
6746 uint64_t va = 0;
6747
6748 if (append) {
6749 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6750
6751 va += radv_buffer_get_va(buffer->bo);
6752 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6753
6754 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6755 }
6756
6757 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
6758 radeon_emit(cs, S_411_SRC_SEL(append ? V_411_SRC_ADDR_TC_L2 : V_411_DATA) |
6759 S_411_DST_SEL(V_411_GDS) |
6760 S_411_CP_SYNC(i == last_target));
6761 radeon_emit(cs, va);
6762 radeon_emit(cs, va >> 32);
6763 radeon_emit(cs, 4 * i); /* destination in GDS */
6764 radeon_emit(cs, 0);
6765 radeon_emit(cs, S_414_BYTE_COUNT_GFX9(4) |
6766 S_414_DISABLE_WR_CONFIRM_GFX9(i != last_target));
6767 }
6768
6769 radv_set_streamout_enable(cmd_buffer, true);
6770 }
6771
6772 void radv_CmdBeginTransformFeedbackEXT(
6773 VkCommandBuffer commandBuffer,
6774 uint32_t firstCounterBuffer,
6775 uint32_t counterBufferCount,
6776 const VkBuffer* pCounterBuffers,
6777 const VkDeviceSize* pCounterBufferOffsets)
6778 {
6779 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6780
6781 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6782 gfx10_emit_streamout_begin(cmd_buffer,
6783 firstCounterBuffer, counterBufferCount,
6784 pCounterBuffers, pCounterBufferOffsets);
6785 } else {
6786 radv_emit_streamout_begin(cmd_buffer,
6787 firstCounterBuffer, counterBufferCount,
6788 pCounterBuffers, pCounterBufferOffsets);
6789 }
6790 }
6791
6792 static void
6793 radv_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6794 uint32_t firstCounterBuffer,
6795 uint32_t counterBufferCount,
6796 const VkBuffer *pCounterBuffers,
6797 const VkDeviceSize *pCounterBufferOffsets)
6798 {
6799 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6800 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6801 uint32_t i;
6802
6803 radv_flush_vgt_streamout(cmd_buffer);
6804
6805 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6806 for_each_bit(i, so->enabled_mask) {
6807 int32_t counter_buffer_idx = i - firstCounterBuffer;
6808 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6809 counter_buffer_idx = -1;
6810
6811 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6812 /* The array of counters buffer is optional. */
6813 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6814 uint64_t va = radv_buffer_get_va(buffer->bo);
6815
6816 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6817
6818 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6819 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6820 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6821 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
6822 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
6823 radeon_emit(cs, va); /* dst address lo */
6824 radeon_emit(cs, va >> 32); /* dst address hi */
6825 radeon_emit(cs, 0); /* unused */
6826 radeon_emit(cs, 0); /* unused */
6827
6828 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6829 }
6830
6831 /* Deactivate transform feedback by zeroing the buffer size.
6832 * The counters (primitives generated, primitives emitted) may
6833 * be enabled even if there is not buffer bound. This ensures
6834 * that the primitives-emitted query won't increment.
6835 */
6836 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
6837
6838 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6839 }
6840
6841 radv_set_streamout_enable(cmd_buffer, false);
6842 }
6843
6844 static void
6845 gfx10_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6846 uint32_t firstCounterBuffer,
6847 uint32_t counterBufferCount,
6848 const VkBuffer *pCounterBuffers,
6849 const VkDeviceSize *pCounterBufferOffsets)
6850 {
6851 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6852 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6853 uint32_t i;
6854
6855 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6856 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6857
6858 for_each_bit(i, so->enabled_mask) {
6859 int32_t counter_buffer_idx = i - firstCounterBuffer;
6860 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6861 counter_buffer_idx = -1;
6862
6863 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6864 /* The array of counters buffer is optional. */
6865 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6866 uint64_t va = radv_buffer_get_va(buffer->bo);
6867
6868 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6869
6870 si_cs_emit_write_event_eop(cs,
6871 cmd_buffer->device->physical_device->rad_info.chip_class,
6872 radv_cmd_buffer_uses_mec(cmd_buffer),
6873 V_028A90_PS_DONE, 0,
6874 EOP_DST_SEL_TC_L2,
6875 EOP_DATA_SEL_GDS,
6876 va, EOP_DATA_GDS(i, 1), 0);
6877
6878 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6879 }
6880 }
6881
6882 radv_set_streamout_enable(cmd_buffer, false);
6883 }
6884
6885 void radv_CmdEndTransformFeedbackEXT(
6886 VkCommandBuffer commandBuffer,
6887 uint32_t firstCounterBuffer,
6888 uint32_t counterBufferCount,
6889 const VkBuffer* pCounterBuffers,
6890 const VkDeviceSize* pCounterBufferOffsets)
6891 {
6892 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6893
6894 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6895 gfx10_emit_streamout_end(cmd_buffer,
6896 firstCounterBuffer, counterBufferCount,
6897 pCounterBuffers, pCounterBufferOffsets);
6898 } else {
6899 radv_emit_streamout_end(cmd_buffer,
6900 firstCounterBuffer, counterBufferCount,
6901 pCounterBuffers, pCounterBufferOffsets);
6902 }
6903 }
6904
6905 void radv_CmdDrawIndirectByteCountEXT(
6906 VkCommandBuffer commandBuffer,
6907 uint32_t instanceCount,
6908 uint32_t firstInstance,
6909 VkBuffer _counterBuffer,
6910 VkDeviceSize counterBufferOffset,
6911 uint32_t counterOffset,
6912 uint32_t vertexStride)
6913 {
6914 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6915 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
6916 struct radv_draw_info info = {};
6917
6918 info.instance_count = instanceCount;
6919 info.first_instance = firstInstance;
6920 info.strmout_buffer = counterBuffer;
6921 info.strmout_buffer_offset = counterBufferOffset;
6922 info.stride = vertexStride;
6923
6924 radv_draw(cmd_buffer, &info);
6925 }
6926
6927 /* VK_AMD_buffer_marker */
6928 void radv_CmdWriteBufferMarkerAMD(
6929 VkCommandBuffer commandBuffer,
6930 VkPipelineStageFlagBits pipelineStage,
6931 VkBuffer dstBuffer,
6932 VkDeviceSize dstOffset,
6933 uint32_t marker)
6934 {
6935 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6936 RADV_FROM_HANDLE(radv_buffer, buffer, dstBuffer);
6937 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6938 uint64_t va = radv_buffer_get_va(buffer->bo) + dstOffset;
6939
6940 si_emit_cache_flush(cmd_buffer);
6941
6942 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 12);
6943
6944 if (!(pipelineStage & ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT)) {
6945 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
6946 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
6947 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
6948 COPY_DATA_WR_CONFIRM);
6949 radeon_emit(cs, marker);
6950 radeon_emit(cs, 0);
6951 radeon_emit(cs, va);
6952 radeon_emit(cs, va >> 32);
6953 } else {
6954 si_cs_emit_write_event_eop(cs,
6955 cmd_buffer->device->physical_device->rad_info.chip_class,
6956 radv_cmd_buffer_uses_mec(cmd_buffer),
6957 V_028A90_BOTTOM_OF_PIPE_TS, 0,
6958 EOP_DST_SEL_MEM,
6959 EOP_DATA_SEL_VALUE_32BIT,
6960 va, marker,
6961 cmd_buffer->gfx9_eop_bug_va);
6962 }
6963
6964 assert(cmd_buffer->cs->cdw <= cdw_max);
6965 }