1c2784bdeeac190e7e7c8426157b95fd3f03ea3c
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 bool src_render_loop,
58 VkImageLayout dst_layout,
59 bool dst_render_loop,
60 uint32_t src_family,
61 uint32_t dst_family,
62 const VkImageSubresourceRange *range,
63 struct radv_sample_locations_state *sample_locs);
64
65 const struct radv_dynamic_state default_dynamic_state = {
66 .viewport = {
67 .count = 0,
68 },
69 .scissor = {
70 .count = 0,
71 },
72 .line_width = 1.0f,
73 .depth_bias = {
74 .bias = 0.0f,
75 .clamp = 0.0f,
76 .slope = 0.0f,
77 },
78 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
79 .depth_bounds = {
80 .min = 0.0f,
81 .max = 1.0f,
82 },
83 .stencil_compare_mask = {
84 .front = ~0u,
85 .back = ~0u,
86 },
87 .stencil_write_mask = {
88 .front = ~0u,
89 .back = ~0u,
90 },
91 .stencil_reference = {
92 .front = 0u,
93 .back = 0u,
94 },
95 .line_stipple = {
96 .factor = 0u,
97 .pattern = 0u,
98 },
99 };
100
101 static void
102 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
103 const struct radv_dynamic_state *src)
104 {
105 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
106 uint32_t copy_mask = src->mask;
107 uint32_t dest_mask = 0;
108
109 /* Make sure to copy the number of viewports/scissors because they can
110 * only be specified at pipeline creation time.
111 */
112 dest->viewport.count = src->viewport.count;
113 dest->scissor.count = src->scissor.count;
114 dest->discard_rectangle.count = src->discard_rectangle.count;
115 dest->sample_location.count = src->sample_location.count;
116
117 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
118 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
119 src->viewport.count * sizeof(VkViewport))) {
120 typed_memcpy(dest->viewport.viewports,
121 src->viewport.viewports,
122 src->viewport.count);
123 dest_mask |= RADV_DYNAMIC_VIEWPORT;
124 }
125 }
126
127 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
128 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
129 src->scissor.count * sizeof(VkRect2D))) {
130 typed_memcpy(dest->scissor.scissors,
131 src->scissor.scissors, src->scissor.count);
132 dest_mask |= RADV_DYNAMIC_SCISSOR;
133 }
134 }
135
136 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
137 if (dest->line_width != src->line_width) {
138 dest->line_width = src->line_width;
139 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
140 }
141 }
142
143 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
144 if (memcmp(&dest->depth_bias, &src->depth_bias,
145 sizeof(src->depth_bias))) {
146 dest->depth_bias = src->depth_bias;
147 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
148 }
149 }
150
151 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
152 if (memcmp(&dest->blend_constants, &src->blend_constants,
153 sizeof(src->blend_constants))) {
154 typed_memcpy(dest->blend_constants,
155 src->blend_constants, 4);
156 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
157 }
158 }
159
160 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
161 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
162 sizeof(src->depth_bounds))) {
163 dest->depth_bounds = src->depth_bounds;
164 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
165 }
166 }
167
168 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
169 if (memcmp(&dest->stencil_compare_mask,
170 &src->stencil_compare_mask,
171 sizeof(src->stencil_compare_mask))) {
172 dest->stencil_compare_mask = src->stencil_compare_mask;
173 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
174 }
175 }
176
177 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
178 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
179 sizeof(src->stencil_write_mask))) {
180 dest->stencil_write_mask = src->stencil_write_mask;
181 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
182 }
183 }
184
185 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
186 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
187 sizeof(src->stencil_reference))) {
188 dest->stencil_reference = src->stencil_reference;
189 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
190 }
191 }
192
193 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
194 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
195 src->discard_rectangle.count * sizeof(VkRect2D))) {
196 typed_memcpy(dest->discard_rectangle.rectangles,
197 src->discard_rectangle.rectangles,
198 src->discard_rectangle.count);
199 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
200 }
201 }
202
203 if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
204 if (dest->sample_location.per_pixel != src->sample_location.per_pixel ||
205 dest->sample_location.grid_size.width != src->sample_location.grid_size.width ||
206 dest->sample_location.grid_size.height != src->sample_location.grid_size.height ||
207 memcmp(&dest->sample_location.locations,
208 &src->sample_location.locations,
209 src->sample_location.count * sizeof(VkSampleLocationEXT))) {
210 dest->sample_location.per_pixel = src->sample_location.per_pixel;
211 dest->sample_location.grid_size = src->sample_location.grid_size;
212 typed_memcpy(dest->sample_location.locations,
213 src->sample_location.locations,
214 src->sample_location.count);
215 dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
216 }
217 }
218
219 if (copy_mask & RADV_DYNAMIC_LINE_STIPPLE) {
220 if (memcmp(&dest->line_stipple, &src->line_stipple,
221 sizeof(src->line_stipple))) {
222 dest->line_stipple = src->line_stipple;
223 dest_mask |= RADV_DYNAMIC_LINE_STIPPLE;
224 }
225 }
226
227 cmd_buffer->state.dirty |= dest_mask;
228 }
229
230 static void
231 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
232 struct radv_pipeline *pipeline)
233 {
234 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
235 struct radv_shader_info *info;
236
237 if (!pipeline->streamout_shader ||
238 cmd_buffer->device->physical_device->use_ngg_streamout)
239 return;
240
241 info = &pipeline->streamout_shader->info;
242 for (int i = 0; i < MAX_SO_BUFFERS; i++)
243 so->stride_in_dw[i] = info->so.strides[i];
244
245 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
246 }
247
248 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
249 {
250 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
251 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
252 }
253
254 enum ring_type radv_queue_family_to_ring(int f) {
255 switch (f) {
256 case RADV_QUEUE_GENERAL:
257 return RING_GFX;
258 case RADV_QUEUE_COMPUTE:
259 return RING_COMPUTE;
260 case RADV_QUEUE_TRANSFER:
261 return RING_DMA;
262 default:
263 unreachable("Unknown queue family");
264 }
265 }
266
267 static VkResult radv_create_cmd_buffer(
268 struct radv_device * device,
269 struct radv_cmd_pool * pool,
270 VkCommandBufferLevel level,
271 VkCommandBuffer* pCommandBuffer)
272 {
273 struct radv_cmd_buffer *cmd_buffer;
274 unsigned ring;
275 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
276 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
277 if (cmd_buffer == NULL)
278 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
279
280 vk_object_base_init(&device->vk, &cmd_buffer->base,
281 VK_OBJECT_TYPE_COMMAND_BUFFER);
282
283 cmd_buffer->device = device;
284 cmd_buffer->pool = pool;
285 cmd_buffer->level = level;
286
287 if (pool) {
288 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
289 cmd_buffer->queue_family_index = pool->queue_family_index;
290
291 } else {
292 /* Init the pool_link so we can safely call list_del when we destroy
293 * the command buffer
294 */
295 list_inithead(&cmd_buffer->pool_link);
296 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
297 }
298
299 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
300
301 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
302 if (!cmd_buffer->cs) {
303 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
304 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
305 }
306
307 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
308
309 list_inithead(&cmd_buffer->upload.list);
310
311 return VK_SUCCESS;
312 }
313
314 static void
315 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
316 {
317 list_del(&cmd_buffer->pool_link);
318
319 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
320 &cmd_buffer->upload.list, list) {
321 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
322 list_del(&up->list);
323 free(up);
324 }
325
326 if (cmd_buffer->upload.upload_bo)
327 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
328 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
329
330 for (unsigned i = 0; i < MAX_BIND_POINTS; i++)
331 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
332
333 vk_object_base_finish(&cmd_buffer->base);
334
335 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
336 }
337
338 static VkResult
339 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
340 {
341 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
342
343 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
344 &cmd_buffer->upload.list, list) {
345 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
346 list_del(&up->list);
347 free(up);
348 }
349
350 cmd_buffer->push_constant_stages = 0;
351 cmd_buffer->scratch_size_per_wave_needed = 0;
352 cmd_buffer->scratch_waves_wanted = 0;
353 cmd_buffer->compute_scratch_size_per_wave_needed = 0;
354 cmd_buffer->compute_scratch_waves_wanted = 0;
355 cmd_buffer->esgs_ring_size_needed = 0;
356 cmd_buffer->gsvs_ring_size_needed = 0;
357 cmd_buffer->tess_rings_needed = false;
358 cmd_buffer->gds_needed = false;
359 cmd_buffer->gds_oa_needed = false;
360 cmd_buffer->sample_positions_needed = false;
361
362 if (cmd_buffer->upload.upload_bo)
363 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
364 cmd_buffer->upload.upload_bo);
365 cmd_buffer->upload.offset = 0;
366
367 cmd_buffer->record_result = VK_SUCCESS;
368
369 memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
370
371 for (unsigned i = 0; i < MAX_BIND_POINTS; i++) {
372 cmd_buffer->descriptors[i].dirty = 0;
373 cmd_buffer->descriptors[i].valid = 0;
374 cmd_buffer->descriptors[i].push_dirty = false;
375 }
376
377 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
378 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
379 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
380 unsigned fence_offset, eop_bug_offset;
381 void *fence_ptr;
382
383 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
384 &fence_ptr);
385
386 cmd_buffer->gfx9_fence_va =
387 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
388 cmd_buffer->gfx9_fence_va += fence_offset;
389
390 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
391 /* Allocate a buffer for the EOP bug on GFX9. */
392 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
393 &eop_bug_offset, &fence_ptr);
394 cmd_buffer->gfx9_eop_bug_va =
395 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
396 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
397 }
398 }
399
400 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
401
402 return cmd_buffer->record_result;
403 }
404
405 static bool
406 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
407 uint64_t min_needed)
408 {
409 uint64_t new_size;
410 struct radeon_winsys_bo *bo;
411 struct radv_cmd_buffer_upload *upload;
412 struct radv_device *device = cmd_buffer->device;
413
414 new_size = MAX2(min_needed, 16 * 1024);
415 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
416
417 bo = device->ws->buffer_create(device->ws,
418 new_size, 4096,
419 RADEON_DOMAIN_GTT,
420 RADEON_FLAG_CPU_ACCESS|
421 RADEON_FLAG_NO_INTERPROCESS_SHARING |
422 RADEON_FLAG_32BIT,
423 RADV_BO_PRIORITY_UPLOAD_BUFFER);
424
425 if (!bo) {
426 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
427 return false;
428 }
429
430 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
431 if (cmd_buffer->upload.upload_bo) {
432 upload = malloc(sizeof(*upload));
433
434 if (!upload) {
435 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
436 device->ws->buffer_destroy(bo);
437 return false;
438 }
439
440 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
441 list_add(&upload->list, &cmd_buffer->upload.list);
442 }
443
444 cmd_buffer->upload.upload_bo = bo;
445 cmd_buffer->upload.size = new_size;
446 cmd_buffer->upload.offset = 0;
447 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
448
449 if (!cmd_buffer->upload.map) {
450 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
451 return false;
452 }
453
454 return true;
455 }
456
457 bool
458 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
459 unsigned size,
460 unsigned alignment,
461 unsigned *out_offset,
462 void **ptr)
463 {
464 assert(util_is_power_of_two_nonzero(alignment));
465
466 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
467 if (offset + size > cmd_buffer->upload.size) {
468 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
469 return false;
470 offset = 0;
471 }
472
473 *out_offset = offset;
474 *ptr = cmd_buffer->upload.map + offset;
475
476 cmd_buffer->upload.offset = offset + size;
477 return true;
478 }
479
480 bool
481 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
482 unsigned size, unsigned alignment,
483 const void *data, unsigned *out_offset)
484 {
485 uint8_t *ptr;
486
487 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
488 out_offset, (void **)&ptr))
489 return false;
490
491 if (ptr)
492 memcpy(ptr, data, size);
493
494 return true;
495 }
496
497 static void
498 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
499 unsigned count, const uint32_t *data)
500 {
501 struct radeon_cmdbuf *cs = cmd_buffer->cs;
502
503 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
504
505 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
506 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
507 S_370_WR_CONFIRM(1) |
508 S_370_ENGINE_SEL(V_370_ME));
509 radeon_emit(cs, va);
510 radeon_emit(cs, va >> 32);
511 radeon_emit_array(cs, data, count);
512 }
513
514 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
515 {
516 struct radv_device *device = cmd_buffer->device;
517 struct radeon_cmdbuf *cs = cmd_buffer->cs;
518 uint64_t va;
519
520 va = radv_buffer_get_va(device->trace_bo);
521 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
522 va += 4;
523
524 ++cmd_buffer->state.trace_id;
525 radv_emit_write_data_packet(cmd_buffer, va, 1,
526 &cmd_buffer->state.trace_id);
527
528 radeon_check_space(cmd_buffer->device->ws, cs, 2);
529
530 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
531 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
532 }
533
534 static void
535 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
536 enum radv_cmd_flush_bits flags)
537 {
538 if (unlikely(cmd_buffer->device->thread_trace_bo)) {
539 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
540 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_THREAD_TRACE_MARKER) | EVENT_INDEX(0));
541 }
542
543 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
544 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
545 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
546
547 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
548
549 /* Force wait for graphics or compute engines to be idle. */
550 si_cs_emit_cache_flush(cmd_buffer->cs,
551 cmd_buffer->device->physical_device->rad_info.chip_class,
552 &cmd_buffer->gfx9_fence_idx,
553 cmd_buffer->gfx9_fence_va,
554 radv_cmd_buffer_uses_mec(cmd_buffer),
555 flags, cmd_buffer->gfx9_eop_bug_va);
556 }
557
558 if (unlikely(cmd_buffer->device->trace_bo))
559 radv_cmd_buffer_trace_emit(cmd_buffer);
560 }
561
562 static void
563 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
564 struct radv_pipeline *pipeline, enum ring_type ring)
565 {
566 struct radv_device *device = cmd_buffer->device;
567 uint32_t data[2];
568 uint64_t va;
569
570 va = radv_buffer_get_va(device->trace_bo);
571
572 switch (ring) {
573 case RING_GFX:
574 va += 8;
575 break;
576 case RING_COMPUTE:
577 va += 16;
578 break;
579 default:
580 assert(!"invalid ring type");
581 }
582
583 uint64_t pipeline_address = (uintptr_t)pipeline;
584 data[0] = pipeline_address;
585 data[1] = pipeline_address >> 32;
586
587 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
588 }
589
590 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
591 VkPipelineBindPoint bind_point,
592 struct radv_descriptor_set *set,
593 unsigned idx)
594 {
595 struct radv_descriptor_state *descriptors_state =
596 radv_get_descriptors_state(cmd_buffer, bind_point);
597
598 descriptors_state->sets[idx] = set;
599
600 descriptors_state->valid |= (1u << idx); /* active descriptors */
601 descriptors_state->dirty |= (1u << idx);
602 }
603
604 static void
605 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
606 VkPipelineBindPoint bind_point)
607 {
608 struct radv_descriptor_state *descriptors_state =
609 radv_get_descriptors_state(cmd_buffer, bind_point);
610 struct radv_device *device = cmd_buffer->device;
611 uint32_t data[MAX_SETS * 2] = {};
612 uint64_t va;
613 unsigned i;
614 va = radv_buffer_get_va(device->trace_bo) + 24;
615
616 for_each_bit(i, descriptors_state->valid) {
617 struct radv_descriptor_set *set = descriptors_state->sets[i];
618 data[i * 2] = (uint64_t)(uintptr_t)set;
619 data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
620 }
621
622 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
623 }
624
625 struct radv_userdata_info *
626 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
627 gl_shader_stage stage,
628 int idx)
629 {
630 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
631 return &shader->info.user_sgprs_locs.shader_data[idx];
632 }
633
634 static void
635 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
636 struct radv_pipeline *pipeline,
637 gl_shader_stage stage,
638 int idx, uint64_t va)
639 {
640 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
641 uint32_t base_reg = pipeline->user_data_0[stage];
642 if (loc->sgpr_idx == -1)
643 return;
644
645 assert(loc->num_sgprs == 1);
646
647 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
648 base_reg + loc->sgpr_idx * 4, va, false);
649 }
650
651 static void
652 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
653 struct radv_pipeline *pipeline,
654 struct radv_descriptor_state *descriptors_state,
655 gl_shader_stage stage)
656 {
657 struct radv_device *device = cmd_buffer->device;
658 struct radeon_cmdbuf *cs = cmd_buffer->cs;
659 uint32_t sh_base = pipeline->user_data_0[stage];
660 struct radv_userdata_locations *locs =
661 &pipeline->shaders[stage]->info.user_sgprs_locs;
662 unsigned mask = locs->descriptor_sets_enabled;
663
664 mask &= descriptors_state->dirty & descriptors_state->valid;
665
666 while (mask) {
667 int start, count;
668
669 u_bit_scan_consecutive_range(&mask, &start, &count);
670
671 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
672 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
673
674 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
675 for (int i = 0; i < count; i++) {
676 struct radv_descriptor_set *set =
677 descriptors_state->sets[start + i];
678
679 radv_emit_shader_pointer_body(device, cs, set->va, true);
680 }
681 }
682 }
683
684 /**
685 * Convert the user sample locations to hardware sample locations (the values
686 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
687 */
688 static void
689 radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
690 uint32_t x, uint32_t y, VkOffset2D *sample_locs)
691 {
692 uint32_t x_offset = x % state->grid_size.width;
693 uint32_t y_offset = y % state->grid_size.height;
694 uint32_t num_samples = (uint32_t)state->per_pixel;
695 VkSampleLocationEXT *user_locs;
696 uint32_t pixel_offset;
697
698 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
699
700 assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
701 user_locs = &state->locations[pixel_offset];
702
703 for (uint32_t i = 0; i < num_samples; i++) {
704 float shifted_pos_x = user_locs[i].x - 0.5;
705 float shifted_pos_y = user_locs[i].y - 0.5;
706
707 int32_t scaled_pos_x = floorf(shifted_pos_x * 16);
708 int32_t scaled_pos_y = floorf(shifted_pos_y * 16);
709
710 sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
711 sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
712 }
713 }
714
715 /**
716 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
717 * locations.
718 */
719 static void
720 radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
721 uint32_t *sample_locs_pixel)
722 {
723 for (uint32_t i = 0; i < num_samples; i++) {
724 uint32_t sample_reg_idx = i / 4;
725 uint32_t sample_loc_idx = i % 4;
726 int32_t pos_x = sample_locs[i].x;
727 int32_t pos_y = sample_locs[i].y;
728
729 uint32_t shift_x = 8 * sample_loc_idx;
730 uint32_t shift_y = shift_x + 4;
731
732 sample_locs_pixel[sample_reg_idx] |= (pos_x & 0xf) << shift_x;
733 sample_locs_pixel[sample_reg_idx] |= (pos_y & 0xf) << shift_y;
734 }
735 }
736
737 /**
738 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
739 * sample locations.
740 */
741 static uint64_t
742 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer,
743 VkOffset2D *sample_locs,
744 uint32_t num_samples)
745 {
746 uint32_t centroid_priorities[num_samples];
747 uint32_t sample_mask = num_samples - 1;
748 uint32_t distances[num_samples];
749 uint64_t centroid_priority = 0;
750
751 /* Compute the distances from center for each sample. */
752 for (int i = 0; i < num_samples; i++) {
753 distances[i] = (sample_locs[i].x * sample_locs[i].x) +
754 (sample_locs[i].y * sample_locs[i].y);
755 }
756
757 /* Compute the centroid priorities by looking at the distances array. */
758 for (int i = 0; i < num_samples; i++) {
759 uint32_t min_idx = 0;
760
761 for (int j = 1; j < num_samples; j++) {
762 if (distances[j] < distances[min_idx])
763 min_idx = j;
764 }
765
766 centroid_priorities[i] = min_idx;
767 distances[min_idx] = 0xffffffff;
768 }
769
770 /* Compute the final centroid priority. */
771 for (int i = 0; i < 8; i++) {
772 centroid_priority |=
773 centroid_priorities[i & sample_mask] << (i * 4);
774 }
775
776 return centroid_priority << 32 | centroid_priority;
777 }
778
779 /**
780 * Emit the sample locations that are specified with VK_EXT_sample_locations.
781 */
782 static void
783 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
784 {
785 struct radv_sample_locations_state *sample_location =
786 &cmd_buffer->state.dynamic.sample_location;
787 uint32_t num_samples = (uint32_t)sample_location->per_pixel;
788 struct radeon_cmdbuf *cs = cmd_buffer->cs;
789 uint32_t sample_locs_pixel[4][2] = {};
790 VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
791 uint32_t max_sample_dist = 0;
792 uint64_t centroid_priority;
793
794 if (!cmd_buffer->state.dynamic.sample_location.count)
795 return;
796
797 /* Convert the user sample locations to hardware sample locations. */
798 radv_convert_user_sample_locs(sample_location, 0, 0, sample_locs[0]);
799 radv_convert_user_sample_locs(sample_location, 1, 0, sample_locs[1]);
800 radv_convert_user_sample_locs(sample_location, 0, 1, sample_locs[2]);
801 radv_convert_user_sample_locs(sample_location, 1, 1, sample_locs[3]);
802
803 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
804 for (uint32_t i = 0; i < 4; i++) {
805 radv_compute_sample_locs_pixel(num_samples, sample_locs[i],
806 sample_locs_pixel[i]);
807 }
808
809 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
810 centroid_priority =
811 radv_compute_centroid_priority(cmd_buffer, sample_locs[0],
812 num_samples);
813
814 /* Compute the maximum sample distance from the specified locations. */
815 for (unsigned i = 0; i < 4; ++i) {
816 for (uint32_t j = 0; j < num_samples; j++) {
817 VkOffset2D offset = sample_locs[i][j];
818 max_sample_dist = MAX2(max_sample_dist,
819 MAX2(abs(offset.x), abs(offset.y)));
820 }
821 }
822
823 /* Emit the specified user sample locations. */
824 switch (num_samples) {
825 case 2:
826 case 4:
827 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
828 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
829 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
830 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
831 break;
832 case 8:
833 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
834 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
835 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
836 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
837 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs_pixel[0][1]);
838 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs_pixel[1][1]);
839 radeon_set_context_reg(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs_pixel[2][1]);
840 radeon_set_context_reg(cs, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs_pixel[3][1]);
841 break;
842 default:
843 unreachable("invalid number of samples");
844 }
845
846 /* Emit the maximum sample distance and the centroid priority. */
847 radeon_set_context_reg_rmw(cs, R_028BE0_PA_SC_AA_CONFIG,
848 S_028BE0_MAX_SAMPLE_DIST(max_sample_dist),
849 ~C_028BE0_MAX_SAMPLE_DIST);
850
851 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
852 radeon_emit(cs, centroid_priority);
853 radeon_emit(cs, centroid_priority >> 32);
854
855 /* GFX9: Flush DFSM when the AA mode changes. */
856 if (cmd_buffer->device->dfsm_allowed) {
857 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
858 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
859 }
860
861 cmd_buffer->state.context_roll_without_scissor_emitted = true;
862 }
863
864 static void
865 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
866 struct radv_pipeline *pipeline,
867 gl_shader_stage stage,
868 int idx, int count, uint32_t *values)
869 {
870 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
871 uint32_t base_reg = pipeline->user_data_0[stage];
872 if (loc->sgpr_idx == -1)
873 return;
874
875 assert(loc->num_sgprs == count);
876
877 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
878 radeon_emit_array(cmd_buffer->cs, values, count);
879 }
880
881 static void
882 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
883 struct radv_pipeline *pipeline)
884 {
885 int num_samples = pipeline->graphics.ms.num_samples;
886 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
887
888 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.needs_sample_positions)
889 cmd_buffer->sample_positions_needed = true;
890
891 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
892 return;
893
894 radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
895
896 cmd_buffer->state.context_roll_without_scissor_emitted = true;
897 }
898
899 static void
900 radv_update_binning_state(struct radv_cmd_buffer *cmd_buffer,
901 struct radv_pipeline *pipeline)
902 {
903 const struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
904
905
906 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
907 return;
908
909 if (old_pipeline &&
910 old_pipeline->graphics.binning.pa_sc_binner_cntl_0 == pipeline->graphics.binning.pa_sc_binner_cntl_0 &&
911 old_pipeline->graphics.binning.db_dfsm_control == pipeline->graphics.binning.db_dfsm_control)
912 return;
913
914 bool binning_flush = false;
915 if (cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA12 ||
916 cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA20 ||
917 cmd_buffer->device->physical_device->rad_info.family == CHIP_RAVEN2 ||
918 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
919 binning_flush = !old_pipeline ||
920 G_028C44_BINNING_MODE(old_pipeline->graphics.binning.pa_sc_binner_cntl_0) !=
921 G_028C44_BINNING_MODE(pipeline->graphics.binning.pa_sc_binner_cntl_0);
922 }
923
924 radeon_set_context_reg(cmd_buffer->cs, R_028C44_PA_SC_BINNER_CNTL_0,
925 pipeline->graphics.binning.pa_sc_binner_cntl_0 |
926 S_028C44_FLUSH_ON_BINNING_TRANSITION(!!binning_flush));
927
928 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
929 radeon_set_context_reg(cmd_buffer->cs, R_028038_DB_DFSM_CONTROL,
930 pipeline->graphics.binning.db_dfsm_control);
931 } else {
932 radeon_set_context_reg(cmd_buffer->cs, R_028060_DB_DFSM_CONTROL,
933 pipeline->graphics.binning.db_dfsm_control);
934 }
935
936 cmd_buffer->state.context_roll_without_scissor_emitted = true;
937 }
938
939
940 static void
941 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
942 struct radv_shader_variant *shader)
943 {
944 uint64_t va;
945
946 if (!shader)
947 return;
948
949 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
950
951 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
952 }
953
954 static void
955 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
956 struct radv_pipeline *pipeline,
957 bool vertex_stage_only)
958 {
959 struct radv_cmd_state *state = &cmd_buffer->state;
960 uint32_t mask = state->prefetch_L2_mask;
961
962 if (vertex_stage_only) {
963 /* Fast prefetch path for starting draws as soon as possible.
964 */
965 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
966 RADV_PREFETCH_VBO_DESCRIPTORS);
967 }
968
969 if (mask & RADV_PREFETCH_VS)
970 radv_emit_shader_prefetch(cmd_buffer,
971 pipeline->shaders[MESA_SHADER_VERTEX]);
972
973 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
974 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
975
976 if (mask & RADV_PREFETCH_TCS)
977 radv_emit_shader_prefetch(cmd_buffer,
978 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
979
980 if (mask & RADV_PREFETCH_TES)
981 radv_emit_shader_prefetch(cmd_buffer,
982 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
983
984 if (mask & RADV_PREFETCH_GS) {
985 radv_emit_shader_prefetch(cmd_buffer,
986 pipeline->shaders[MESA_SHADER_GEOMETRY]);
987 if (radv_pipeline_has_gs_copy_shader(pipeline))
988 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
989 }
990
991 if (mask & RADV_PREFETCH_PS)
992 radv_emit_shader_prefetch(cmd_buffer,
993 pipeline->shaders[MESA_SHADER_FRAGMENT]);
994
995 state->prefetch_L2_mask &= ~mask;
996 }
997
998 static void
999 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
1000 {
1001 if (!cmd_buffer->device->physical_device->rad_info.rbplus_allowed)
1002 return;
1003
1004 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1005 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1006
1007 unsigned sx_ps_downconvert = 0;
1008 unsigned sx_blend_opt_epsilon = 0;
1009 unsigned sx_blend_opt_control = 0;
1010
1011 if (!cmd_buffer->state.attachments || !subpass)
1012 return;
1013
1014 for (unsigned i = 0; i < subpass->color_count; ++i) {
1015 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1016 /* We don't set the DISABLE bits, because the HW can't have holes,
1017 * so the SPI color format is set to 32-bit 1-component. */
1018 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1019 continue;
1020 }
1021
1022 int idx = subpass->color_attachments[i].attachment;
1023 struct radv_color_buffer_info *cb = &cmd_buffer->state.attachments[idx].cb;
1024
1025 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
1026 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
1027 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
1028 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
1029
1030 bool has_alpha, has_rgb;
1031
1032 /* Set if RGB and A are present. */
1033 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
1034
1035 if (format == V_028C70_COLOR_8 ||
1036 format == V_028C70_COLOR_16 ||
1037 format == V_028C70_COLOR_32)
1038 has_rgb = !has_alpha;
1039 else
1040 has_rgb = true;
1041
1042 /* Check the colormask and export format. */
1043 if (!(colormask & 0x7))
1044 has_rgb = false;
1045 if (!(colormask & 0x8))
1046 has_alpha = false;
1047
1048 if (spi_format == V_028714_SPI_SHADER_ZERO) {
1049 has_rgb = false;
1050 has_alpha = false;
1051 }
1052
1053 /* Disable value checking for disabled channels. */
1054 if (!has_rgb)
1055 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1056 if (!has_alpha)
1057 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1058
1059 /* Enable down-conversion for 32bpp and smaller formats. */
1060 switch (format) {
1061 case V_028C70_COLOR_8:
1062 case V_028C70_COLOR_8_8:
1063 case V_028C70_COLOR_8_8_8_8:
1064 /* For 1 and 2-channel formats, use the superset thereof. */
1065 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
1066 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1067 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1068 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
1069 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
1070 }
1071 break;
1072
1073 case V_028C70_COLOR_5_6_5:
1074 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1075 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
1076 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
1077 }
1078 break;
1079
1080 case V_028C70_COLOR_1_5_5_5:
1081 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1082 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
1083 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
1084 }
1085 break;
1086
1087 case V_028C70_COLOR_4_4_4_4:
1088 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1089 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
1090 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
1091 }
1092 break;
1093
1094 case V_028C70_COLOR_32:
1095 if (swap == V_028C70_SWAP_STD &&
1096 spi_format == V_028714_SPI_SHADER_32_R)
1097 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1098 else if (swap == V_028C70_SWAP_ALT_REV &&
1099 spi_format == V_028714_SPI_SHADER_32_AR)
1100 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
1101 break;
1102
1103 case V_028C70_COLOR_16:
1104 case V_028C70_COLOR_16_16:
1105 /* For 1-channel formats, use the superset thereof. */
1106 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
1107 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
1108 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1109 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1110 if (swap == V_028C70_SWAP_STD ||
1111 swap == V_028C70_SWAP_STD_REV)
1112 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
1113 else
1114 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
1115 }
1116 break;
1117
1118 case V_028C70_COLOR_10_11_11:
1119 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1120 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
1121 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
1122 }
1123 break;
1124
1125 case V_028C70_COLOR_2_10_10_10:
1126 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1127 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
1128 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
1129 }
1130 break;
1131 }
1132 }
1133
1134 /* Do not set the DISABLE bits for the unused attachments, as that
1135 * breaks dual source blending in SkQP and does not seem to improve
1136 * performance. */
1137
1138 if (sx_ps_downconvert == cmd_buffer->state.last_sx_ps_downconvert &&
1139 sx_blend_opt_epsilon == cmd_buffer->state.last_sx_blend_opt_epsilon &&
1140 sx_blend_opt_control == cmd_buffer->state.last_sx_blend_opt_control)
1141 return;
1142
1143 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
1144 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
1145 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
1146 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
1147
1148 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1149
1150 cmd_buffer->state.last_sx_ps_downconvert = sx_ps_downconvert;
1151 cmd_buffer->state.last_sx_blend_opt_epsilon = sx_blend_opt_epsilon;
1152 cmd_buffer->state.last_sx_blend_opt_control = sx_blend_opt_control;
1153 }
1154
1155 static void
1156 radv_emit_batch_break_on_new_ps(struct radv_cmd_buffer *cmd_buffer)
1157 {
1158 if (!cmd_buffer->device->pbb_allowed)
1159 return;
1160
1161 struct radv_binning_settings settings =
1162 radv_get_binning_settings(cmd_buffer->device->physical_device);
1163 bool break_for_new_ps =
1164 (!cmd_buffer->state.emitted_pipeline ||
1165 cmd_buffer->state.emitted_pipeline->shaders[MESA_SHADER_FRAGMENT] !=
1166 cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT]) &&
1167 (settings.context_states_per_bin > 1 ||
1168 settings.persistent_states_per_bin > 1);
1169 bool break_for_new_cb_target_mask =
1170 (!cmd_buffer->state.emitted_pipeline ||
1171 cmd_buffer->state.emitted_pipeline->graphics.cb_target_mask !=
1172 cmd_buffer->state.pipeline->graphics.cb_target_mask) &&
1173 settings.context_states_per_bin > 1;
1174
1175 if (!break_for_new_ps && !break_for_new_cb_target_mask)
1176 return;
1177
1178 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1179 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1180 }
1181
1182 static void
1183 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1184 {
1185 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1186
1187 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1188 return;
1189
1190 radv_update_multisample_state(cmd_buffer, pipeline);
1191 radv_update_binning_state(cmd_buffer, pipeline);
1192
1193 cmd_buffer->scratch_size_per_wave_needed = MAX2(cmd_buffer->scratch_size_per_wave_needed,
1194 pipeline->scratch_bytes_per_wave);
1195 cmd_buffer->scratch_waves_wanted = MAX2(cmd_buffer->scratch_waves_wanted,
1196 pipeline->max_waves);
1197
1198 if (!cmd_buffer->state.emitted_pipeline ||
1199 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1200 pipeline->graphics.can_use_guardband)
1201 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1202
1203 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
1204
1205 if (!cmd_buffer->state.emitted_pipeline ||
1206 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
1207 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
1208 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
1209 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
1210 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
1211 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1212 }
1213
1214 radv_emit_batch_break_on_new_ps(cmd_buffer);
1215
1216 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
1217 if (!pipeline->shaders[i])
1218 continue;
1219
1220 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1221 pipeline->shaders[i]->bo);
1222 }
1223
1224 if (radv_pipeline_has_gs_copy_shader(pipeline))
1225 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1226 pipeline->gs_copy_shader->bo);
1227
1228 if (unlikely(cmd_buffer->device->trace_bo))
1229 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1230
1231 cmd_buffer->state.emitted_pipeline = pipeline;
1232
1233 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1234 }
1235
1236 static void
1237 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1238 {
1239 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1240 cmd_buffer->state.dynamic.viewport.viewports);
1241 }
1242
1243 static void
1244 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1245 {
1246 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1247
1248 si_write_scissors(cmd_buffer->cs, 0, count,
1249 cmd_buffer->state.dynamic.scissor.scissors,
1250 cmd_buffer->state.dynamic.viewport.viewports,
1251 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1252
1253 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1254 }
1255
1256 static void
1257 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1258 {
1259 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1260 return;
1261
1262 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1263 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1264 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1265 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1266 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1267 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1268 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1269 }
1270 }
1271
1272 static void
1273 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1274 {
1275 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1276
1277 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1278 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1279 }
1280
1281 static void
1282 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1283 {
1284 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1285
1286 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1287 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1288 }
1289
1290 static void
1291 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1292 {
1293 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1294
1295 radeon_set_context_reg_seq(cmd_buffer->cs,
1296 R_028430_DB_STENCILREFMASK, 2);
1297 radeon_emit(cmd_buffer->cs,
1298 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1299 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1300 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1301 S_028430_STENCILOPVAL(1));
1302 radeon_emit(cmd_buffer->cs,
1303 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1304 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1305 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1306 S_028434_STENCILOPVAL_BF(1));
1307 }
1308
1309 static void
1310 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1311 {
1312 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1313
1314 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1315 fui(d->depth_bounds.min));
1316 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1317 fui(d->depth_bounds.max));
1318 }
1319
1320 static void
1321 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1322 {
1323 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1324 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1325 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1326
1327
1328 radeon_set_context_reg_seq(cmd_buffer->cs,
1329 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1330 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1331 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1332 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1333 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1334 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1335 }
1336
1337 static void
1338 radv_emit_line_stipple(struct radv_cmd_buffer *cmd_buffer)
1339 {
1340 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1341 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1342 uint32_t auto_reset_cntl = 1;
1343
1344 if (pipeline->graphics.topology == VK_PRIMITIVE_TOPOLOGY_LINE_STRIP)
1345 auto_reset_cntl = 2;
1346
1347 radeon_set_context_reg(cmd_buffer->cs, R_028A0C_PA_SC_LINE_STIPPLE,
1348 S_028A0C_LINE_PATTERN(d->line_stipple.pattern) |
1349 S_028A0C_REPEAT_COUNT(d->line_stipple.factor - 1) |
1350 S_028A0C_AUTO_RESET_CNTL(auto_reset_cntl));
1351 }
1352
1353 static void
1354 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1355 int index,
1356 struct radv_color_buffer_info *cb,
1357 struct radv_image_view *iview,
1358 VkImageLayout layout,
1359 bool in_render_loop)
1360 {
1361 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
1362 uint32_t cb_color_info = cb->cb_color_info;
1363 struct radv_image *image = iview->image;
1364
1365 if (!radv_layout_dcc_compressed(cmd_buffer->device, image, layout, in_render_loop,
1366 radv_image_queue_family_mask(image,
1367 cmd_buffer->queue_family_index,
1368 cmd_buffer->queue_family_index))) {
1369 cb_color_info &= C_028C70_DCC_ENABLE;
1370 }
1371
1372 if (radv_image_is_tc_compat_cmask(image) &&
1373 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1374 radv_is_dcc_decompress_pipeline(cmd_buffer))) {
1375 /* If this bit is set, the FMASK decompression operation
1376 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1377 */
1378 cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
1379 }
1380
1381 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1382 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1383 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1384 radeon_emit(cmd_buffer->cs, 0);
1385 radeon_emit(cmd_buffer->cs, 0);
1386 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1387 radeon_emit(cmd_buffer->cs, cb_color_info);
1388 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1389 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1390 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1391 radeon_emit(cmd_buffer->cs, 0);
1392 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1393 radeon_emit(cmd_buffer->cs, 0);
1394
1395 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 1);
1396 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1397
1398 radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4,
1399 cb->cb_color_base >> 32);
1400 radeon_set_context_reg(cmd_buffer->cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + index * 4,
1401 cb->cb_color_cmask >> 32);
1402 radeon_set_context_reg(cmd_buffer->cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + index * 4,
1403 cb->cb_color_fmask >> 32);
1404 radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4,
1405 cb->cb_dcc_base >> 32);
1406 radeon_set_context_reg(cmd_buffer->cs, R_028EC0_CB_COLOR0_ATTRIB2 + index * 4,
1407 cb->cb_color_attrib2);
1408 radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4,
1409 cb->cb_color_attrib3);
1410 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1411 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1412 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1413 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1414 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1415 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1416 radeon_emit(cmd_buffer->cs, cb_color_info);
1417 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1418 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1419 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1420 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1421 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1422 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1423
1424 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1425 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1426 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1427
1428 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1429 cb->cb_mrt_epitch);
1430 } else {
1431 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1432 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1433 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1434 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1435 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1436 radeon_emit(cmd_buffer->cs, cb_color_info);
1437 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1438 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1439 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1440 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1441 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1442 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1443
1444 if (is_vi) { /* DCC BASE */
1445 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1446 }
1447 }
1448
1449 if (radv_dcc_enabled(image, iview->base_mip)) {
1450 /* Drawing with DCC enabled also compresses colorbuffers. */
1451 VkImageSubresourceRange range = {
1452 .aspectMask = iview->aspect_mask,
1453 .baseMipLevel = iview->base_mip,
1454 .levelCount = iview->level_count,
1455 .baseArrayLayer = iview->base_layer,
1456 .layerCount = iview->layer_count,
1457 };
1458
1459 radv_update_dcc_metadata(cmd_buffer, image, &range, true);
1460 }
1461 }
1462
1463 static void
1464 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1465 struct radv_ds_buffer_info *ds,
1466 const struct radv_image_view *iview,
1467 VkImageLayout layout,
1468 bool in_render_loop, bool requires_cond_exec)
1469 {
1470 const struct radv_image *image = iview->image;
1471 uint32_t db_z_info = ds->db_z_info;
1472 uint32_t db_z_info_reg;
1473
1474 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug ||
1475 !radv_image_is_tc_compat_htile(image))
1476 return;
1477
1478 if (!radv_layout_is_htile_compressed(image, layout, in_render_loop,
1479 radv_image_queue_family_mask(image,
1480 cmd_buffer->queue_family_index,
1481 cmd_buffer->queue_family_index))) {
1482 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1483 }
1484
1485 db_z_info &= C_028040_ZRANGE_PRECISION;
1486
1487 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1488 db_z_info_reg = R_028038_DB_Z_INFO;
1489 } else {
1490 db_z_info_reg = R_028040_DB_Z_INFO;
1491 }
1492
1493 /* When we don't know the last fast clear value we need to emit a
1494 * conditional packet that will eventually skip the following
1495 * SET_CONTEXT_REG packet.
1496 */
1497 if (requires_cond_exec) {
1498 uint64_t va = radv_get_tc_compat_zrange_va(image, iview->base_mip);
1499
1500 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1501 radeon_emit(cmd_buffer->cs, va);
1502 radeon_emit(cmd_buffer->cs, va >> 32);
1503 radeon_emit(cmd_buffer->cs, 0);
1504 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1505 }
1506
1507 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1508 }
1509
1510 static void
1511 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1512 struct radv_ds_buffer_info *ds,
1513 struct radv_image_view *iview,
1514 VkImageLayout layout,
1515 bool in_render_loop)
1516 {
1517 const struct radv_image *image = iview->image;
1518 uint32_t db_z_info = ds->db_z_info;
1519 uint32_t db_stencil_info = ds->db_stencil_info;
1520
1521 if (!radv_layout_is_htile_compressed(image, layout, in_render_loop,
1522 radv_image_queue_family_mask(image,
1523 cmd_buffer->queue_family_index,
1524 cmd_buffer->queue_family_index))) {
1525 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1526 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1527 }
1528
1529 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1530 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1531
1532 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1533 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1534 radeon_set_context_reg(cmd_buffer->cs, R_02801C_DB_DEPTH_SIZE_XY, ds->db_depth_size);
1535
1536 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 7);
1537 radeon_emit(cmd_buffer->cs, S_02803C_RESOURCE_LEVEL(1));
1538 radeon_emit(cmd_buffer->cs, db_z_info);
1539 radeon_emit(cmd_buffer->cs, db_stencil_info);
1540 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1541 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1542 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1543 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1544
1545 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_READ_BASE_HI, 5);
1546 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1547 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1548 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1549 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1550 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1551 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1552 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1553 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1554 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1555 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1556
1557 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1558 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1559 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1560 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1561 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1562 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1563 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1564 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1565 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1566 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1567 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1568
1569 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1570 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1571 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1572 } else {
1573 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1574
1575 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1576 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1577 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1578 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1579 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1580 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1581 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1582 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1583 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1584 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1585
1586 }
1587
1588 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1589 radv_update_zrange_precision(cmd_buffer, ds, iview, layout,
1590 in_render_loop, true);
1591
1592 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1593 ds->pa_su_poly_offset_db_fmt_cntl);
1594 }
1595
1596 /**
1597 * Update the fast clear depth/stencil values if the image is bound as a
1598 * depth/stencil buffer.
1599 */
1600 static void
1601 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1602 const struct radv_image_view *iview,
1603 VkClearDepthStencilValue ds_clear_value,
1604 VkImageAspectFlags aspects)
1605 {
1606 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1607 const struct radv_image *image = iview->image;
1608 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1609 uint32_t att_idx;
1610
1611 if (!cmd_buffer->state.attachments || !subpass)
1612 return;
1613
1614 if (!subpass->depth_stencil_attachment)
1615 return;
1616
1617 att_idx = subpass->depth_stencil_attachment->attachment;
1618 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1619 return;
1620
1621 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1622 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1623 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1624 radeon_emit(cs, ds_clear_value.stencil);
1625 radeon_emit(cs, fui(ds_clear_value.depth));
1626 } else if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1627 radeon_set_context_reg_seq(cs, R_02802C_DB_DEPTH_CLEAR, 1);
1628 radeon_emit(cs, fui(ds_clear_value.depth));
1629 } else {
1630 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1631 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 1);
1632 radeon_emit(cs, ds_clear_value.stencil);
1633 }
1634
1635 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1636 * only needed when clearing Z to 0.0.
1637 */
1638 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1639 ds_clear_value.depth == 0.0) {
1640 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1641 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
1642
1643 radv_update_zrange_precision(cmd_buffer, &cmd_buffer->state.attachments[att_idx].ds,
1644 iview, layout, in_render_loop, false);
1645 }
1646
1647 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1648 }
1649
1650 /**
1651 * Set the clear depth/stencil values to the image's metadata.
1652 */
1653 static void
1654 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1655 struct radv_image *image,
1656 const VkImageSubresourceRange *range,
1657 VkClearDepthStencilValue ds_clear_value,
1658 VkImageAspectFlags aspects)
1659 {
1660 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1661 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel);
1662 uint32_t level_count = radv_get_levelCount(image, range);
1663
1664 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1665 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1666 /* Use the fastest way when both aspects are used. */
1667 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + 2 * level_count, cmd_buffer->state.predicating));
1668 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1669 S_370_WR_CONFIRM(1) |
1670 S_370_ENGINE_SEL(V_370_PFP));
1671 radeon_emit(cs, va);
1672 radeon_emit(cs, va >> 32);
1673
1674 for (uint32_t l = 0; l < level_count; l++) {
1675 radeon_emit(cs, ds_clear_value.stencil);
1676 radeon_emit(cs, fui(ds_clear_value.depth));
1677 }
1678 } else {
1679 /* Otherwise we need one WRITE_DATA packet per level. */
1680 for (uint32_t l = 0; l < level_count; l++) {
1681 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel + l);
1682 unsigned value;
1683
1684 if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1685 value = fui(ds_clear_value.depth);
1686 va += 4;
1687 } else {
1688 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1689 value = ds_clear_value.stencil;
1690 }
1691
1692 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1693 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1694 S_370_WR_CONFIRM(1) |
1695 S_370_ENGINE_SEL(V_370_PFP));
1696 radeon_emit(cs, va);
1697 radeon_emit(cs, va >> 32);
1698 radeon_emit(cs, value);
1699 }
1700 }
1701 }
1702
1703 /**
1704 * Update the TC-compat metadata value for this image.
1705 */
1706 static void
1707 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1708 struct radv_image *image,
1709 const VkImageSubresourceRange *range,
1710 uint32_t value)
1711 {
1712 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1713
1714 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug)
1715 return;
1716
1717 uint64_t va = radv_get_tc_compat_zrange_va(image, range->baseMipLevel);
1718 uint32_t level_count = radv_get_levelCount(image, range);
1719
1720 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + level_count, cmd_buffer->state.predicating));
1721 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1722 S_370_WR_CONFIRM(1) |
1723 S_370_ENGINE_SEL(V_370_PFP));
1724 radeon_emit(cs, va);
1725 radeon_emit(cs, va >> 32);
1726
1727 for (uint32_t l = 0; l < level_count; l++)
1728 radeon_emit(cs, value);
1729 }
1730
1731 static void
1732 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1733 const struct radv_image_view *iview,
1734 VkClearDepthStencilValue ds_clear_value)
1735 {
1736 VkImageSubresourceRange range = {
1737 .aspectMask = iview->aspect_mask,
1738 .baseMipLevel = iview->base_mip,
1739 .levelCount = iview->level_count,
1740 .baseArrayLayer = iview->base_layer,
1741 .layerCount = iview->layer_count,
1742 };
1743 uint32_t cond_val;
1744
1745 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1746 * depth clear value is 0.0f.
1747 */
1748 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1749
1750 radv_set_tc_compat_zrange_metadata(cmd_buffer, iview->image, &range,
1751 cond_val);
1752 }
1753
1754 /**
1755 * Update the clear depth/stencil values for this image.
1756 */
1757 void
1758 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1759 const struct radv_image_view *iview,
1760 VkClearDepthStencilValue ds_clear_value,
1761 VkImageAspectFlags aspects)
1762 {
1763 VkImageSubresourceRange range = {
1764 .aspectMask = iview->aspect_mask,
1765 .baseMipLevel = iview->base_mip,
1766 .levelCount = iview->level_count,
1767 .baseArrayLayer = iview->base_layer,
1768 .layerCount = iview->layer_count,
1769 };
1770 struct radv_image *image = iview->image;
1771
1772 assert(radv_image_has_htile(image));
1773
1774 radv_set_ds_clear_metadata(cmd_buffer, iview->image, &range,
1775 ds_clear_value, aspects);
1776
1777 if (radv_image_is_tc_compat_htile(image) &&
1778 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1779 radv_update_tc_compat_zrange_metadata(cmd_buffer, iview,
1780 ds_clear_value);
1781 }
1782
1783 radv_update_bound_fast_clear_ds(cmd_buffer, iview, ds_clear_value,
1784 aspects);
1785 }
1786
1787 /**
1788 * Load the clear depth/stencil values from the image's metadata.
1789 */
1790 static void
1791 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1792 const struct radv_image_view *iview)
1793 {
1794 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1795 const struct radv_image *image = iview->image;
1796 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1797 uint64_t va = radv_get_ds_clear_value_va(image, iview->base_mip);
1798 unsigned reg_offset = 0, reg_count = 0;
1799
1800 if (!radv_image_has_htile(image))
1801 return;
1802
1803 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1804 ++reg_count;
1805 } else {
1806 ++reg_offset;
1807 va += 4;
1808 }
1809 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1810 ++reg_count;
1811
1812 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1813
1814 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
1815 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG_INDEX, 3, 0));
1816 radeon_emit(cs, va);
1817 radeon_emit(cs, va >> 32);
1818 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1819 radeon_emit(cs, reg_count);
1820 } else {
1821 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1822 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1823 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1824 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1825 radeon_emit(cs, va);
1826 radeon_emit(cs, va >> 32);
1827 radeon_emit(cs, reg >> 2);
1828 radeon_emit(cs, 0);
1829
1830 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1831 radeon_emit(cs, 0);
1832 }
1833 }
1834
1835 /*
1836 * With DCC some colors don't require CMASK elimination before being
1837 * used as a texture. This sets a predicate value to determine if the
1838 * cmask eliminate is required.
1839 */
1840 void
1841 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1842 struct radv_image *image,
1843 const VkImageSubresourceRange *range, bool value)
1844 {
1845 uint64_t pred_val = value;
1846 uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
1847 uint32_t level_count = radv_get_levelCount(image, range);
1848 uint32_t count = 2 * level_count;
1849
1850 assert(radv_dcc_enabled(image, range->baseMipLevel));
1851
1852 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1853 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1854 S_370_WR_CONFIRM(1) |
1855 S_370_ENGINE_SEL(V_370_PFP));
1856 radeon_emit(cmd_buffer->cs, va);
1857 radeon_emit(cmd_buffer->cs, va >> 32);
1858
1859 for (uint32_t l = 0; l < level_count; l++) {
1860 radeon_emit(cmd_buffer->cs, pred_val);
1861 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1862 }
1863 }
1864
1865 /**
1866 * Update the DCC predicate to reflect the compression state.
1867 */
1868 void
1869 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1870 struct radv_image *image,
1871 const VkImageSubresourceRange *range, bool value)
1872 {
1873 uint64_t pred_val = value;
1874 uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
1875 uint32_t level_count = radv_get_levelCount(image, range);
1876 uint32_t count = 2 * level_count;
1877
1878 assert(radv_dcc_enabled(image, range->baseMipLevel));
1879
1880 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1881 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1882 S_370_WR_CONFIRM(1) |
1883 S_370_ENGINE_SEL(V_370_PFP));
1884 radeon_emit(cmd_buffer->cs, va);
1885 radeon_emit(cmd_buffer->cs, va >> 32);
1886
1887 for (uint32_t l = 0; l < level_count; l++) {
1888 radeon_emit(cmd_buffer->cs, pred_val);
1889 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1890 }
1891 }
1892
1893 /**
1894 * Update the fast clear color values if the image is bound as a color buffer.
1895 */
1896 static void
1897 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1898 struct radv_image *image,
1899 int cb_idx,
1900 uint32_t color_values[2])
1901 {
1902 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1903 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1904 uint32_t att_idx;
1905
1906 if (!cmd_buffer->state.attachments || !subpass)
1907 return;
1908
1909 att_idx = subpass->color_attachments[cb_idx].attachment;
1910 if (att_idx == VK_ATTACHMENT_UNUSED)
1911 return;
1912
1913 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1914 return;
1915
1916 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1917 radeon_emit(cs, color_values[0]);
1918 radeon_emit(cs, color_values[1]);
1919
1920 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1921 }
1922
1923 /**
1924 * Set the clear color values to the image's metadata.
1925 */
1926 static void
1927 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1928 struct radv_image *image,
1929 const VkImageSubresourceRange *range,
1930 uint32_t color_values[2])
1931 {
1932 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1933 uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
1934 uint32_t level_count = radv_get_levelCount(image, range);
1935 uint32_t count = 2 * level_count;
1936
1937 assert(radv_image_has_cmask(image) ||
1938 radv_dcc_enabled(image, range->baseMipLevel));
1939
1940 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
1941 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1942 S_370_WR_CONFIRM(1) |
1943 S_370_ENGINE_SEL(V_370_PFP));
1944 radeon_emit(cs, va);
1945 radeon_emit(cs, va >> 32);
1946
1947 for (uint32_t l = 0; l < level_count; l++) {
1948 radeon_emit(cs, color_values[0]);
1949 radeon_emit(cs, color_values[1]);
1950 }
1951 }
1952
1953 /**
1954 * Update the clear color values for this image.
1955 */
1956 void
1957 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1958 const struct radv_image_view *iview,
1959 int cb_idx,
1960 uint32_t color_values[2])
1961 {
1962 struct radv_image *image = iview->image;
1963 VkImageSubresourceRange range = {
1964 .aspectMask = iview->aspect_mask,
1965 .baseMipLevel = iview->base_mip,
1966 .levelCount = iview->level_count,
1967 .baseArrayLayer = iview->base_layer,
1968 .layerCount = iview->layer_count,
1969 };
1970
1971 assert(radv_image_has_cmask(image) ||
1972 radv_dcc_enabled(image, iview->base_mip));
1973
1974 radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
1975
1976 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1977 color_values);
1978 }
1979
1980 /**
1981 * Load the clear color values from the image's metadata.
1982 */
1983 static void
1984 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1985 struct radv_image_view *iview,
1986 int cb_idx)
1987 {
1988 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1989 struct radv_image *image = iview->image;
1990 uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
1991
1992 if (!radv_image_has_cmask(image) &&
1993 !radv_dcc_enabled(image, iview->base_mip))
1994 return;
1995
1996 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1997
1998 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
1999 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG_INDEX, 3, cmd_buffer->state.predicating));
2000 radeon_emit(cs, va);
2001 radeon_emit(cs, va >> 32);
2002 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
2003 radeon_emit(cs, 2);
2004 } else {
2005 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
2006 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2007 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2008 COPY_DATA_COUNT_SEL);
2009 radeon_emit(cs, va);
2010 radeon_emit(cs, va >> 32);
2011 radeon_emit(cs, reg >> 2);
2012 radeon_emit(cs, 0);
2013
2014 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
2015 radeon_emit(cs, 0);
2016 }
2017 }
2018
2019 static void
2020 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
2021 {
2022 int i;
2023 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
2024 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2025
2026 /* this may happen for inherited secondary recording */
2027 if (!framebuffer)
2028 return;
2029
2030 for (i = 0; i < 8; ++i) {
2031 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
2032 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2033 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2034 continue;
2035 }
2036
2037 int idx = subpass->color_attachments[i].attachment;
2038 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
2039 VkImageLayout layout = subpass->color_attachments[i].layout;
2040 bool in_render_loop = subpass->color_attachments[i].in_render_loop;
2041
2042 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, iview->bo);
2043
2044 assert(iview->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
2045 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
2046 radv_emit_fb_color_state(cmd_buffer, i, &cmd_buffer->state.attachments[idx].cb, iview, layout, in_render_loop);
2047
2048 radv_load_color_clear_metadata(cmd_buffer, iview, i);
2049 }
2050
2051 if (subpass->depth_stencil_attachment) {
2052 int idx = subpass->depth_stencil_attachment->attachment;
2053 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
2054 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
2055 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
2056 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, cmd_buffer->state.attachments[idx].iview->bo);
2057
2058 radv_emit_fb_ds_state(cmd_buffer, &cmd_buffer->state.attachments[idx].ds, iview, layout, in_render_loop);
2059
2060 if (cmd_buffer->state.attachments[idx].ds.offset_scale != cmd_buffer->state.offset_scale) {
2061 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2062 cmd_buffer->state.offset_scale = cmd_buffer->state.attachments[idx].ds.offset_scale;
2063 }
2064 radv_load_ds_clear_metadata(cmd_buffer, iview);
2065 } else {
2066 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9)
2067 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
2068 else
2069 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
2070
2071 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
2072 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
2073 }
2074 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2075 S_028208_BR_X(framebuffer->width) |
2076 S_028208_BR_Y(framebuffer->height));
2077
2078 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
2079 bool disable_constant_encode =
2080 cmd_buffer->device->physical_device->rad_info.has_dcc_constant_encode;
2081 enum chip_class chip_class =
2082 cmd_buffer->device->physical_device->rad_info.chip_class;
2083 uint8_t watermark = chip_class >= GFX10 ? 6 : 4;
2084
2085 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
2086 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class <= GFX9) |
2087 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
2088 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
2089 }
2090
2091 if (cmd_buffer->device->dfsm_allowed) {
2092 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2093 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
2094 }
2095
2096 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
2097 }
2098
2099 static void
2100 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer, bool indirect)
2101 {
2102 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2103 struct radv_cmd_state *state = &cmd_buffer->state;
2104
2105 if (state->index_type != state->last_index_type) {
2106 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2107 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2108 cs, R_03090C_VGT_INDEX_TYPE,
2109 2, state->index_type);
2110 } else {
2111 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2112 radeon_emit(cs, state->index_type);
2113 }
2114
2115 state->last_index_type = state->index_type;
2116 }
2117
2118 /* For the direct indexed draws we use DRAW_INDEX_2, which includes
2119 * the index_va and max_index_count already. */
2120 if (!indirect)
2121 return;
2122
2123 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2124 radeon_emit(cs, state->index_va);
2125 radeon_emit(cs, state->index_va >> 32);
2126
2127 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2128 radeon_emit(cs, state->max_index_count);
2129
2130 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
2131 }
2132
2133 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
2134 {
2135 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
2136 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2137 uint32_t pa_sc_mode_cntl_1 =
2138 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
2139 uint32_t db_count_control;
2140
2141 if(!cmd_buffer->state.active_occlusion_queries) {
2142 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2143 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2144 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2145 has_perfect_queries) {
2146 /* Re-enable out-of-order rasterization if the
2147 * bound pipeline supports it and if it's has
2148 * been disabled before starting any perfect
2149 * occlusion queries.
2150 */
2151 radeon_set_context_reg(cmd_buffer->cs,
2152 R_028A4C_PA_SC_MODE_CNTL_1,
2153 pa_sc_mode_cntl_1);
2154 }
2155 }
2156 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
2157 } else {
2158 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2159 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
2160 bool gfx10_perfect = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10 && has_perfect_queries;
2161
2162 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2163 db_count_control =
2164 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
2165 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
2166 S_028004_SAMPLE_RATE(sample_rate) |
2167 S_028004_ZPASS_ENABLE(1) |
2168 S_028004_SLICE_EVEN_ENABLE(1) |
2169 S_028004_SLICE_ODD_ENABLE(1);
2170
2171 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2172 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2173 has_perfect_queries) {
2174 /* If the bound pipeline has enabled
2175 * out-of-order rasterization, we should
2176 * disable it before starting any perfect
2177 * occlusion queries.
2178 */
2179 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
2180
2181 radeon_set_context_reg(cmd_buffer->cs,
2182 R_028A4C_PA_SC_MODE_CNTL_1,
2183 pa_sc_mode_cntl_1);
2184 }
2185 } else {
2186 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
2187 S_028004_SAMPLE_RATE(sample_rate);
2188 }
2189 }
2190
2191 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
2192
2193 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2194 }
2195
2196 static void
2197 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
2198 {
2199 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
2200
2201 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
2202 radv_emit_viewport(cmd_buffer);
2203
2204 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
2205 !cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
2206 radv_emit_scissor(cmd_buffer);
2207
2208 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
2209 radv_emit_line_width(cmd_buffer);
2210
2211 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
2212 radv_emit_blend_constants(cmd_buffer);
2213
2214 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
2215 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
2216 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
2217 radv_emit_stencil(cmd_buffer);
2218
2219 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
2220 radv_emit_depth_bounds(cmd_buffer);
2221
2222 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
2223 radv_emit_depth_bias(cmd_buffer);
2224
2225 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
2226 radv_emit_discard_rectangle(cmd_buffer);
2227
2228 if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)
2229 radv_emit_sample_locations(cmd_buffer);
2230
2231 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE)
2232 radv_emit_line_stipple(cmd_buffer);
2233
2234 cmd_buffer->state.dirty &= ~states;
2235 }
2236
2237 static void
2238 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
2239 VkPipelineBindPoint bind_point)
2240 {
2241 struct radv_descriptor_state *descriptors_state =
2242 radv_get_descriptors_state(cmd_buffer, bind_point);
2243 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
2244 unsigned bo_offset;
2245
2246 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
2247 set->mapped_ptr,
2248 &bo_offset))
2249 return;
2250
2251 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2252 set->va += bo_offset;
2253 }
2254
2255 static void
2256 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
2257 VkPipelineBindPoint bind_point)
2258 {
2259 struct radv_descriptor_state *descriptors_state =
2260 radv_get_descriptors_state(cmd_buffer, bind_point);
2261 uint32_t size = MAX_SETS * 4;
2262 uint32_t offset;
2263 void *ptr;
2264
2265 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
2266 256, &offset, &ptr))
2267 return;
2268
2269 for (unsigned i = 0; i < MAX_SETS; i++) {
2270 uint32_t *uptr = ((uint32_t *)ptr) + i;
2271 uint64_t set_va = 0;
2272 struct radv_descriptor_set *set = descriptors_state->sets[i];
2273 if (descriptors_state->valid & (1u << i))
2274 set_va = set->va;
2275 uptr[0] = set_va & 0xffffffff;
2276 }
2277
2278 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2279 va += offset;
2280
2281 if (cmd_buffer->state.pipeline) {
2282 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
2283 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2284 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2285
2286 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
2287 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
2288 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2289
2290 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
2291 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2292 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2293
2294 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2295 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
2296 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2297
2298 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2299 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
2300 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2301 }
2302
2303 if (cmd_buffer->state.compute_pipeline)
2304 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
2305 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2306 }
2307
2308 static void
2309 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
2310 VkShaderStageFlags stages)
2311 {
2312 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2313 VK_PIPELINE_BIND_POINT_COMPUTE :
2314 VK_PIPELINE_BIND_POINT_GRAPHICS;
2315 struct radv_descriptor_state *descriptors_state =
2316 radv_get_descriptors_state(cmd_buffer, bind_point);
2317 struct radv_cmd_state *state = &cmd_buffer->state;
2318 bool flush_indirect_descriptors;
2319
2320 if (!descriptors_state->dirty)
2321 return;
2322
2323 if (descriptors_state->push_dirty)
2324 radv_flush_push_descriptors(cmd_buffer, bind_point);
2325
2326 flush_indirect_descriptors =
2327 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
2328 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
2329 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
2330 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
2331
2332 if (flush_indirect_descriptors)
2333 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
2334
2335 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2336 cmd_buffer->cs,
2337 MAX_SETS * MESA_SHADER_STAGES * 4);
2338
2339 if (cmd_buffer->state.pipeline) {
2340 radv_foreach_stage(stage, stages) {
2341 if (!cmd_buffer->state.pipeline->shaders[stage])
2342 continue;
2343
2344 radv_emit_descriptor_pointers(cmd_buffer,
2345 cmd_buffer->state.pipeline,
2346 descriptors_state, stage);
2347 }
2348 }
2349
2350 if (cmd_buffer->state.compute_pipeline &&
2351 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
2352 radv_emit_descriptor_pointers(cmd_buffer,
2353 cmd_buffer->state.compute_pipeline,
2354 descriptors_state,
2355 MESA_SHADER_COMPUTE);
2356 }
2357
2358 descriptors_state->dirty = 0;
2359 descriptors_state->push_dirty = false;
2360
2361 assert(cmd_buffer->cs->cdw <= cdw_max);
2362
2363 if (unlikely(cmd_buffer->device->trace_bo))
2364 radv_save_descriptors(cmd_buffer, bind_point);
2365 }
2366
2367 static void
2368 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
2369 VkShaderStageFlags stages)
2370 {
2371 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
2372 ? cmd_buffer->state.compute_pipeline
2373 : cmd_buffer->state.pipeline;
2374 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2375 VK_PIPELINE_BIND_POINT_COMPUTE :
2376 VK_PIPELINE_BIND_POINT_GRAPHICS;
2377 struct radv_descriptor_state *descriptors_state =
2378 radv_get_descriptors_state(cmd_buffer, bind_point);
2379 struct radv_pipeline_layout *layout = pipeline->layout;
2380 struct radv_shader_variant *shader, *prev_shader;
2381 bool need_push_constants = false;
2382 unsigned offset;
2383 void *ptr;
2384 uint64_t va;
2385
2386 stages &= cmd_buffer->push_constant_stages;
2387 if (!stages ||
2388 (!layout->push_constant_size && !layout->dynamic_offset_count))
2389 return;
2390
2391 radv_foreach_stage(stage, stages) {
2392 shader = radv_get_shader(pipeline, stage);
2393 if (!shader)
2394 continue;
2395
2396 need_push_constants |= shader->info.loads_push_constants;
2397 need_push_constants |= shader->info.loads_dynamic_offsets;
2398
2399 uint8_t base = shader->info.base_inline_push_consts;
2400 uint8_t count = shader->info.num_inline_push_consts;
2401
2402 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
2403 AC_UD_INLINE_PUSH_CONSTANTS,
2404 count,
2405 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
2406 }
2407
2408 if (need_push_constants) {
2409 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
2410 16 * layout->dynamic_offset_count,
2411 256, &offset, &ptr))
2412 return;
2413
2414 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
2415 memcpy((char*)ptr + layout->push_constant_size,
2416 descriptors_state->dynamic_buffers,
2417 16 * layout->dynamic_offset_count);
2418
2419 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2420 va += offset;
2421
2422 ASSERTED unsigned cdw_max =
2423 radeon_check_space(cmd_buffer->device->ws,
2424 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
2425
2426 prev_shader = NULL;
2427 radv_foreach_stage(stage, stages) {
2428 shader = radv_get_shader(pipeline, stage);
2429
2430 /* Avoid redundantly emitting the address for merged stages. */
2431 if (shader && shader != prev_shader) {
2432 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
2433 AC_UD_PUSH_CONSTANTS, va);
2434
2435 prev_shader = shader;
2436 }
2437 }
2438 assert(cmd_buffer->cs->cdw <= cdw_max);
2439 }
2440
2441 cmd_buffer->push_constant_stages &= ~stages;
2442 }
2443
2444 static void
2445 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
2446 bool pipeline_is_dirty)
2447 {
2448 if ((pipeline_is_dirty ||
2449 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
2450 cmd_buffer->state.pipeline->num_vertex_bindings &&
2451 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.has_vertex_buffers) {
2452 unsigned vb_offset;
2453 void *vb_ptr;
2454 uint32_t i = 0;
2455 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
2456 uint64_t va;
2457
2458 /* allocate some descriptor state for vertex buffers */
2459 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2460 &vb_offset, &vb_ptr))
2461 return;
2462
2463 for (i = 0; i < count; i++) {
2464 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2465 uint32_t offset;
2466 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2467 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[i];
2468 unsigned num_records;
2469
2470 if (!buffer)
2471 continue;
2472
2473 va = radv_buffer_get_va(buffer->bo);
2474
2475 offset = cmd_buffer->vertex_bindings[i].offset;
2476 va += offset + buffer->offset;
2477
2478 num_records = buffer->size - offset;
2479 if (cmd_buffer->device->physical_device->rad_info.chip_class != GFX8 && stride)
2480 num_records /= stride;
2481
2482 desc[0] = va;
2483 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2484 desc[2] = num_records;
2485 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2486 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2487 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2488 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2489
2490 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2491 /* OOB_SELECT chooses the out-of-bounds check:
2492 * - 1: index >= NUM_RECORDS (Structured)
2493 * - 3: offset >= NUM_RECORDS (Raw)
2494 */
2495 int oob_select = stride ? V_008F0C_OOB_SELECT_STRUCTURED : V_008F0C_OOB_SELECT_RAW;
2496
2497 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT) |
2498 S_008F0C_OOB_SELECT(oob_select) |
2499 S_008F0C_RESOURCE_LEVEL(1);
2500 } else {
2501 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2502 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2503 }
2504 }
2505
2506 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2507 va += vb_offset;
2508
2509 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2510 AC_UD_VS_VERTEX_BUFFERS, va);
2511
2512 cmd_buffer->state.vb_va = va;
2513 cmd_buffer->state.vb_size = count * 16;
2514 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2515 }
2516 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2517 }
2518
2519 static void
2520 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2521 {
2522 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2523 struct radv_userdata_info *loc;
2524 uint32_t base_reg;
2525
2526 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2527 if (!radv_get_shader(pipeline, stage))
2528 continue;
2529
2530 loc = radv_lookup_user_sgpr(pipeline, stage,
2531 AC_UD_STREAMOUT_BUFFERS);
2532 if (loc->sgpr_idx == -1)
2533 continue;
2534
2535 base_reg = pipeline->user_data_0[stage];
2536
2537 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2538 base_reg + loc->sgpr_idx * 4, va, false);
2539 }
2540
2541 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
2542 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2543 if (loc->sgpr_idx != -1) {
2544 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2545
2546 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2547 base_reg + loc->sgpr_idx * 4, va, false);
2548 }
2549 }
2550 }
2551
2552 static void
2553 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2554 {
2555 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2556 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2557 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2558 unsigned so_offset;
2559 void *so_ptr;
2560 uint64_t va;
2561
2562 /* Allocate some descriptor state for streamout buffers. */
2563 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2564 MAX_SO_BUFFERS * 16, 256,
2565 &so_offset, &so_ptr))
2566 return;
2567
2568 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2569 struct radv_buffer *buffer = sb[i].buffer;
2570 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2571
2572 if (!(so->enabled_mask & (1 << i)))
2573 continue;
2574
2575 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2576
2577 va += sb[i].offset;
2578
2579 /* Set the descriptor.
2580 *
2581 * On GFX8, the format must be non-INVALID, otherwise
2582 * the buffer will be considered not bound and store
2583 * instructions will be no-ops.
2584 */
2585 uint32_t size = 0xffffffff;
2586
2587 /* Compute the correct buffer size for NGG streamout
2588 * because it's used to determine the max emit per
2589 * buffer.
2590 */
2591 if (cmd_buffer->device->physical_device->use_ngg_streamout)
2592 size = buffer->size - sb[i].offset;
2593
2594 desc[0] = va;
2595 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2596 desc[2] = size;
2597 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2598 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2599 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2600 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2601
2602 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2603 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2604 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
2605 S_008F0C_RESOURCE_LEVEL(1);
2606 } else {
2607 desc[3] |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2608 }
2609 }
2610
2611 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2612 va += so_offset;
2613
2614 radv_emit_streamout_buffers(cmd_buffer, va);
2615 }
2616
2617 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2618 }
2619
2620 static void
2621 radv_flush_ngg_gs_state(struct radv_cmd_buffer *cmd_buffer)
2622 {
2623 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2624 struct radv_userdata_info *loc;
2625 uint32_t ngg_gs_state = 0;
2626 uint32_t base_reg;
2627
2628 if (!radv_pipeline_has_gs(pipeline) ||
2629 !radv_pipeline_has_ngg(pipeline))
2630 return;
2631
2632 /* By default NGG GS queries are disabled but they are enabled if the
2633 * command buffer has active GDS queries or if it's a secondary command
2634 * buffer that inherits the number of generated primitives.
2635 */
2636 if (cmd_buffer->state.active_pipeline_gds_queries ||
2637 (cmd_buffer->state.inherited_pipeline_statistics & VK_QUERY_PIPELINE_STATISTIC_GEOMETRY_SHADER_PRIMITIVES_BIT))
2638 ngg_gs_state = 1;
2639
2640 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_GEOMETRY,
2641 AC_UD_NGG_GS_STATE);
2642 base_reg = pipeline->user_data_0[MESA_SHADER_GEOMETRY];
2643 assert(loc->sgpr_idx != -1);
2644
2645 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
2646 ngg_gs_state);
2647 }
2648
2649 static void
2650 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2651 {
2652 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2653 radv_flush_streamout_descriptors(cmd_buffer);
2654 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2655 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2656 radv_flush_ngg_gs_state(cmd_buffer);
2657 }
2658
2659 struct radv_draw_info {
2660 /**
2661 * Number of vertices.
2662 */
2663 uint32_t count;
2664
2665 /**
2666 * Index of the first vertex.
2667 */
2668 int32_t vertex_offset;
2669
2670 /**
2671 * First instance id.
2672 */
2673 uint32_t first_instance;
2674
2675 /**
2676 * Number of instances.
2677 */
2678 uint32_t instance_count;
2679
2680 /**
2681 * First index (indexed draws only).
2682 */
2683 uint32_t first_index;
2684
2685 /**
2686 * Whether it's an indexed draw.
2687 */
2688 bool indexed;
2689
2690 /**
2691 * Indirect draw parameters resource.
2692 */
2693 struct radv_buffer *indirect;
2694 uint64_t indirect_offset;
2695 uint32_t stride;
2696
2697 /**
2698 * Draw count parameters resource.
2699 */
2700 struct radv_buffer *count_buffer;
2701 uint64_t count_buffer_offset;
2702
2703 /**
2704 * Stream output parameters resource.
2705 */
2706 struct radv_buffer *strmout_buffer;
2707 uint64_t strmout_buffer_offset;
2708 };
2709
2710 static uint32_t
2711 radv_get_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
2712 {
2713 switch (cmd_buffer->state.index_type) {
2714 case V_028A7C_VGT_INDEX_8:
2715 return 0xffu;
2716 case V_028A7C_VGT_INDEX_16:
2717 return 0xffffu;
2718 case V_028A7C_VGT_INDEX_32:
2719 return 0xffffffffu;
2720 default:
2721 unreachable("invalid index type");
2722 }
2723 }
2724
2725 static void
2726 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
2727 bool instanced_draw, bool indirect_draw,
2728 bool count_from_stream_output,
2729 uint32_t draw_vertex_count)
2730 {
2731 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2732 struct radv_cmd_state *state = &cmd_buffer->state;
2733 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2734 unsigned ia_multi_vgt_param;
2735
2736 ia_multi_vgt_param =
2737 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
2738 indirect_draw,
2739 count_from_stream_output,
2740 draw_vertex_count);
2741
2742 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2743 if (info->chip_class == GFX9) {
2744 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2745 cs,
2746 R_030960_IA_MULTI_VGT_PARAM,
2747 4, ia_multi_vgt_param);
2748 } else if (info->chip_class >= GFX7) {
2749 radeon_set_context_reg_idx(cs,
2750 R_028AA8_IA_MULTI_VGT_PARAM,
2751 1, ia_multi_vgt_param);
2752 } else {
2753 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2754 ia_multi_vgt_param);
2755 }
2756 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2757 }
2758 }
2759
2760 static void
2761 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2762 const struct radv_draw_info *draw_info)
2763 {
2764 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2765 struct radv_cmd_state *state = &cmd_buffer->state;
2766 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2767 int32_t primitive_reset_en;
2768
2769 /* Draw state. */
2770 if (info->chip_class < GFX10) {
2771 si_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2772 draw_info->indirect,
2773 !!draw_info->strmout_buffer,
2774 draw_info->indirect ? 0 : draw_info->count);
2775 }
2776
2777 /* Primitive restart. */
2778 primitive_reset_en =
2779 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2780
2781 if (primitive_reset_en != state->last_primitive_reset_en) {
2782 state->last_primitive_reset_en = primitive_reset_en;
2783 if (info->chip_class >= GFX9) {
2784 radeon_set_uconfig_reg(cs,
2785 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2786 primitive_reset_en);
2787 } else {
2788 radeon_set_context_reg(cs,
2789 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2790 primitive_reset_en);
2791 }
2792 }
2793
2794 if (primitive_reset_en) {
2795 uint32_t primitive_reset_index =
2796 radv_get_primitive_reset_index(cmd_buffer);
2797
2798 if (primitive_reset_index != state->last_primitive_reset_index) {
2799 radeon_set_context_reg(cs,
2800 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2801 primitive_reset_index);
2802 state->last_primitive_reset_index = primitive_reset_index;
2803 }
2804 }
2805
2806 if (draw_info->strmout_buffer) {
2807 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2808
2809 va += draw_info->strmout_buffer->offset +
2810 draw_info->strmout_buffer_offset;
2811
2812 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2813 draw_info->stride);
2814
2815 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2816 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2817 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2818 COPY_DATA_WR_CONFIRM);
2819 radeon_emit(cs, va);
2820 radeon_emit(cs, va >> 32);
2821 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2822 radeon_emit(cs, 0); /* unused */
2823
2824 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2825 }
2826 }
2827
2828 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2829 VkPipelineStageFlags src_stage_mask)
2830 {
2831 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2832 VK_PIPELINE_STAGE_TRANSFER_BIT |
2833 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2834 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2835 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2836 }
2837
2838 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2839 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2840 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2841 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2842 VK_PIPELINE_STAGE_TRANSFER_BIT |
2843 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2844 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2845 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2846 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2847 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2848 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2849 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2850 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2851 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2852 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2853 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2854 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2855 }
2856 }
2857
2858 static enum radv_cmd_flush_bits
2859 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2860 VkAccessFlags src_flags,
2861 struct radv_image *image)
2862 {
2863 bool flush_CB_meta = true, flush_DB_meta = true;
2864 enum radv_cmd_flush_bits flush_bits = 0;
2865 uint32_t b;
2866
2867 if (image) {
2868 if (!radv_image_has_CB_metadata(image))
2869 flush_CB_meta = false;
2870 if (!radv_image_has_htile(image))
2871 flush_DB_meta = false;
2872 }
2873
2874 for_each_bit(b, src_flags) {
2875 switch ((VkAccessFlagBits)(1 << b)) {
2876 case VK_ACCESS_SHADER_WRITE_BIT:
2877 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2878 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2879 flush_bits |= RADV_CMD_FLAG_WB_L2;
2880 break;
2881 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2882 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2883 if (flush_CB_meta)
2884 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2885 break;
2886 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2887 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2888 if (flush_DB_meta)
2889 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2890 break;
2891 case VK_ACCESS_TRANSFER_WRITE_BIT:
2892 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2893 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2894 RADV_CMD_FLAG_INV_L2;
2895
2896 if (flush_CB_meta)
2897 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2898 if (flush_DB_meta)
2899 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2900 break;
2901 default:
2902 break;
2903 }
2904 }
2905 return flush_bits;
2906 }
2907
2908 static enum radv_cmd_flush_bits
2909 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2910 VkAccessFlags dst_flags,
2911 struct radv_image *image)
2912 {
2913 bool flush_CB_meta = true, flush_DB_meta = true;
2914 enum radv_cmd_flush_bits flush_bits = 0;
2915 bool flush_CB = true, flush_DB = true;
2916 bool image_is_coherent = false;
2917 uint32_t b;
2918
2919 if (image) {
2920 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2921 flush_CB = false;
2922 flush_DB = false;
2923 }
2924
2925 if (!radv_image_has_CB_metadata(image))
2926 flush_CB_meta = false;
2927 if (!radv_image_has_htile(image))
2928 flush_DB_meta = false;
2929
2930 /* TODO: implement shader coherent for GFX10 */
2931
2932 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
2933 if (image->info.samples == 1 &&
2934 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2935 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2936 !vk_format_is_stencil(image->vk_format)) {
2937 /* Single-sample color and single-sample depth
2938 * (not stencil) are coherent with shaders on
2939 * GFX9.
2940 */
2941 image_is_coherent = true;
2942 }
2943 }
2944 }
2945
2946 for_each_bit(b, dst_flags) {
2947 switch ((VkAccessFlagBits)(1 << b)) {
2948 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2949 case VK_ACCESS_INDEX_READ_BIT:
2950 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2951 break;
2952 case VK_ACCESS_UNIFORM_READ_BIT:
2953 flush_bits |= RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_SCACHE;
2954 break;
2955 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2956 case VK_ACCESS_TRANSFER_READ_BIT:
2957 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2958 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
2959 RADV_CMD_FLAG_INV_L2;
2960 break;
2961 case VK_ACCESS_SHADER_READ_BIT:
2962 flush_bits |= RADV_CMD_FLAG_INV_VCACHE;
2963 /* Unlike LLVM, ACO uses SMEM for SSBOs and we have to
2964 * invalidate the scalar cache. */
2965 if (cmd_buffer->device->physical_device->use_aco &&
2966 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8)
2967 flush_bits |= RADV_CMD_FLAG_INV_SCACHE;
2968
2969 if (!image_is_coherent)
2970 flush_bits |= RADV_CMD_FLAG_INV_L2;
2971 break;
2972 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2973 if (flush_CB)
2974 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2975 if (flush_CB_meta)
2976 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2977 break;
2978 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2979 if (flush_DB)
2980 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2981 if (flush_DB_meta)
2982 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2983 break;
2984 default:
2985 break;
2986 }
2987 }
2988 return flush_bits;
2989 }
2990
2991 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2992 const struct radv_subpass_barrier *barrier)
2993 {
2994 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2995 NULL);
2996 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2997 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2998 NULL);
2999 }
3000
3001 uint32_t
3002 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
3003 {
3004 struct radv_cmd_state *state = &cmd_buffer->state;
3005 uint32_t subpass_id = state->subpass - state->pass->subpasses;
3006
3007 /* The id of this subpass shouldn't exceed the number of subpasses in
3008 * this render pass minus 1.
3009 */
3010 assert(subpass_id < state->pass->subpass_count);
3011 return subpass_id;
3012 }
3013
3014 static struct radv_sample_locations_state *
3015 radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer,
3016 uint32_t att_idx,
3017 bool begin_subpass)
3018 {
3019 struct radv_cmd_state *state = &cmd_buffer->state;
3020 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
3021 struct radv_image_view *view = state->attachments[att_idx].iview;
3022
3023 if (view->image->info.samples == 1)
3024 return NULL;
3025
3026 if (state->pass->attachments[att_idx].first_subpass_idx == subpass_id) {
3027 /* Return the initial sample locations if this is the initial
3028 * layout transition of the given subpass attachemnt.
3029 */
3030 if (state->attachments[att_idx].sample_location.count > 0)
3031 return &state->attachments[att_idx].sample_location;
3032 } else {
3033 /* Otherwise return the subpass sample locations if defined. */
3034 if (state->subpass_sample_locs) {
3035 /* Because the driver sets the current subpass before
3036 * initial layout transitions, we should use the sample
3037 * locations from the previous subpass to avoid an
3038 * off-by-one problem. Otherwise, use the sample
3039 * locations for the current subpass for final layout
3040 * transitions.
3041 */
3042 if (begin_subpass)
3043 subpass_id--;
3044
3045 for (uint32_t i = 0; i < state->num_subpass_sample_locs; i++) {
3046 if (state->subpass_sample_locs[i].subpass_idx == subpass_id)
3047 return &state->subpass_sample_locs[i].sample_location;
3048 }
3049 }
3050 }
3051
3052 return NULL;
3053 }
3054
3055 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
3056 struct radv_subpass_attachment att,
3057 bool begin_subpass)
3058 {
3059 unsigned idx = att.attachment;
3060 struct radv_image_view *view = cmd_buffer->state.attachments[idx].iview;
3061 struct radv_sample_locations_state *sample_locs;
3062 VkImageSubresourceRange range;
3063 range.aspectMask = view->aspect_mask;
3064 range.baseMipLevel = view->base_mip;
3065 range.levelCount = 1;
3066 range.baseArrayLayer = view->base_layer;
3067 range.layerCount = cmd_buffer->state.framebuffer->layers;
3068
3069 if (cmd_buffer->state.subpass->view_mask) {
3070 /* If the current subpass uses multiview, the driver might have
3071 * performed a fast color/depth clear to the whole image
3072 * (including all layers). To make sure the driver will
3073 * decompress the image correctly (if needed), we have to
3074 * account for the "real" number of layers. If the view mask is
3075 * sparse, this will decompress more layers than needed.
3076 */
3077 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
3078 }
3079
3080 /* Get the subpass sample locations for the given attachment, if NULL
3081 * is returned the driver will use the default HW locations.
3082 */
3083 sample_locs = radv_get_attachment_sample_locations(cmd_buffer, idx,
3084 begin_subpass);
3085
3086 /* Determine if the subpass uses separate depth/stencil layouts. */
3087 bool uses_separate_depth_stencil_layouts = false;
3088 if ((cmd_buffer->state.attachments[idx].current_layout !=
3089 cmd_buffer->state.attachments[idx].current_stencil_layout) ||
3090 (att.layout != att.stencil_layout)) {
3091 uses_separate_depth_stencil_layouts = true;
3092 }
3093
3094 /* For separate layouts, perform depth and stencil transitions
3095 * separately.
3096 */
3097 if (uses_separate_depth_stencil_layouts &&
3098 (range.aspectMask == (VK_IMAGE_ASPECT_DEPTH_BIT |
3099 VK_IMAGE_ASPECT_STENCIL_BIT))) {
3100 /* Depth-only transitions. */
3101 range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3102 radv_handle_image_transition(cmd_buffer,
3103 view->image,
3104 cmd_buffer->state.attachments[idx].current_layout,
3105 cmd_buffer->state.attachments[idx].current_in_render_loop,
3106 att.layout, att.in_render_loop,
3107 0, 0, &range, sample_locs);
3108
3109 /* Stencil-only transitions. */
3110 range.aspectMask = VK_IMAGE_ASPECT_STENCIL_BIT;
3111 radv_handle_image_transition(cmd_buffer,
3112 view->image,
3113 cmd_buffer->state.attachments[idx].current_stencil_layout,
3114 cmd_buffer->state.attachments[idx].current_in_render_loop,
3115 att.stencil_layout, att.in_render_loop,
3116 0, 0, &range, sample_locs);
3117 } else {
3118 radv_handle_image_transition(cmd_buffer,
3119 view->image,
3120 cmd_buffer->state.attachments[idx].current_layout,
3121 cmd_buffer->state.attachments[idx].current_in_render_loop,
3122 att.layout, att.in_render_loop,
3123 0, 0, &range, sample_locs);
3124 }
3125
3126 cmd_buffer->state.attachments[idx].current_layout = att.layout;
3127 cmd_buffer->state.attachments[idx].current_stencil_layout = att.stencil_layout;
3128 cmd_buffer->state.attachments[idx].current_in_render_loop = att.in_render_loop;
3129
3130
3131 }
3132
3133 void
3134 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
3135 const struct radv_subpass *subpass)
3136 {
3137 cmd_buffer->state.subpass = subpass;
3138
3139 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
3140 }
3141
3142 static VkResult
3143 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
3144 struct radv_render_pass *pass,
3145 const VkRenderPassBeginInfo *info)
3146 {
3147 const struct VkRenderPassSampleLocationsBeginInfoEXT *sample_locs =
3148 vk_find_struct_const(info->pNext,
3149 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT);
3150 struct radv_cmd_state *state = &cmd_buffer->state;
3151
3152 if (!sample_locs) {
3153 state->subpass_sample_locs = NULL;
3154 return VK_SUCCESS;
3155 }
3156
3157 for (uint32_t i = 0; i < sample_locs->attachmentInitialSampleLocationsCount; i++) {
3158 const VkAttachmentSampleLocationsEXT *att_sample_locs =
3159 &sample_locs->pAttachmentInitialSampleLocations[i];
3160 uint32_t att_idx = att_sample_locs->attachmentIndex;
3161 struct radv_image *image = cmd_buffer->state.attachments[att_idx].iview->image;
3162
3163 assert(vk_format_is_depth_or_stencil(image->vk_format));
3164
3165 /* From the Vulkan spec 1.1.108:
3166 *
3167 * "If the image referenced by the framebuffer attachment at
3168 * index attachmentIndex was not created with
3169 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
3170 * then the values specified in sampleLocationsInfo are
3171 * ignored."
3172 */
3173 if (!(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT))
3174 continue;
3175
3176 const VkSampleLocationsInfoEXT *sample_locs_info =
3177 &att_sample_locs->sampleLocationsInfo;
3178
3179 state->attachments[att_idx].sample_location.per_pixel =
3180 sample_locs_info->sampleLocationsPerPixel;
3181 state->attachments[att_idx].sample_location.grid_size =
3182 sample_locs_info->sampleLocationGridSize;
3183 state->attachments[att_idx].sample_location.count =
3184 sample_locs_info->sampleLocationsCount;
3185 typed_memcpy(&state->attachments[att_idx].sample_location.locations[0],
3186 sample_locs_info->pSampleLocations,
3187 sample_locs_info->sampleLocationsCount);
3188 }
3189
3190 state->subpass_sample_locs = vk_alloc(&cmd_buffer->pool->alloc,
3191 sample_locs->postSubpassSampleLocationsCount *
3192 sizeof(state->subpass_sample_locs[0]),
3193 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3194 if (state->subpass_sample_locs == NULL) {
3195 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3196 return cmd_buffer->record_result;
3197 }
3198
3199 state->num_subpass_sample_locs = sample_locs->postSubpassSampleLocationsCount;
3200
3201 for (uint32_t i = 0; i < sample_locs->postSubpassSampleLocationsCount; i++) {
3202 const VkSubpassSampleLocationsEXT *subpass_sample_locs_info =
3203 &sample_locs->pPostSubpassSampleLocations[i];
3204 const VkSampleLocationsInfoEXT *sample_locs_info =
3205 &subpass_sample_locs_info->sampleLocationsInfo;
3206
3207 state->subpass_sample_locs[i].subpass_idx =
3208 subpass_sample_locs_info->subpassIndex;
3209 state->subpass_sample_locs[i].sample_location.per_pixel =
3210 sample_locs_info->sampleLocationsPerPixel;
3211 state->subpass_sample_locs[i].sample_location.grid_size =
3212 sample_locs_info->sampleLocationGridSize;
3213 state->subpass_sample_locs[i].sample_location.count =
3214 sample_locs_info->sampleLocationsCount;
3215 typed_memcpy(&state->subpass_sample_locs[i].sample_location.locations[0],
3216 sample_locs_info->pSampleLocations,
3217 sample_locs_info->sampleLocationsCount);
3218 }
3219
3220 return VK_SUCCESS;
3221 }
3222
3223 static VkResult
3224 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
3225 struct radv_render_pass *pass,
3226 const VkRenderPassBeginInfo *info)
3227 {
3228 struct radv_cmd_state *state = &cmd_buffer->state;
3229 const struct VkRenderPassAttachmentBeginInfo *attachment_info = NULL;
3230
3231 if (info) {
3232 attachment_info = vk_find_struct_const(info->pNext,
3233 RENDER_PASS_ATTACHMENT_BEGIN_INFO);
3234 }
3235
3236
3237 if (pass->attachment_count == 0) {
3238 state->attachments = NULL;
3239 return VK_SUCCESS;
3240 }
3241
3242 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
3243 pass->attachment_count *
3244 sizeof(state->attachments[0]),
3245 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3246 if (state->attachments == NULL) {
3247 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3248 return cmd_buffer->record_result;
3249 }
3250
3251 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
3252 struct radv_render_pass_attachment *att = &pass->attachments[i];
3253 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
3254 VkImageAspectFlags clear_aspects = 0;
3255
3256 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
3257 /* color attachment */
3258 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3259 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
3260 }
3261 } else {
3262 /* depthstencil attachment */
3263 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
3264 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3265 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
3266 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3267 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
3268 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3269 }
3270 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3271 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3272 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3273 }
3274 }
3275
3276 state->attachments[i].pending_clear_aspects = clear_aspects;
3277 state->attachments[i].cleared_views = 0;
3278 if (clear_aspects && info) {
3279 assert(info->clearValueCount > i);
3280 state->attachments[i].clear_value = info->pClearValues[i];
3281 }
3282
3283 state->attachments[i].current_layout = att->initial_layout;
3284 state->attachments[i].current_stencil_layout = att->stencil_initial_layout;
3285 state->attachments[i].sample_location.count = 0;
3286
3287 struct radv_image_view *iview;
3288 if (attachment_info && attachment_info->attachmentCount > i) {
3289 iview = radv_image_view_from_handle(attachment_info->pAttachments[i]);
3290 } else {
3291 iview = state->framebuffer->attachments[i];
3292 }
3293
3294 state->attachments[i].iview = iview;
3295 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3296 radv_initialise_ds_surface(cmd_buffer->device, &state->attachments[i].ds, iview);
3297 } else {
3298 radv_initialise_color_surface(cmd_buffer->device, &state->attachments[i].cb, iview);
3299 }
3300 }
3301
3302 return VK_SUCCESS;
3303 }
3304
3305 VkResult radv_AllocateCommandBuffers(
3306 VkDevice _device,
3307 const VkCommandBufferAllocateInfo *pAllocateInfo,
3308 VkCommandBuffer *pCommandBuffers)
3309 {
3310 RADV_FROM_HANDLE(radv_device, device, _device);
3311 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
3312
3313 VkResult result = VK_SUCCESS;
3314 uint32_t i;
3315
3316 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
3317
3318 if (!list_is_empty(&pool->free_cmd_buffers)) {
3319 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
3320
3321 list_del(&cmd_buffer->pool_link);
3322 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
3323
3324 result = radv_reset_cmd_buffer(cmd_buffer);
3325 cmd_buffer->level = pAllocateInfo->level;
3326
3327 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
3328 } else {
3329 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
3330 &pCommandBuffers[i]);
3331 }
3332 if (result != VK_SUCCESS)
3333 break;
3334 }
3335
3336 if (result != VK_SUCCESS) {
3337 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
3338 i, pCommandBuffers);
3339
3340 /* From the Vulkan 1.0.66 spec:
3341 *
3342 * "vkAllocateCommandBuffers can be used to create multiple
3343 * command buffers. If the creation of any of those command
3344 * buffers fails, the implementation must destroy all
3345 * successfully created command buffer objects from this
3346 * command, set all entries of the pCommandBuffers array to
3347 * NULL and return the error."
3348 */
3349 memset(pCommandBuffers, 0,
3350 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
3351 }
3352
3353 return result;
3354 }
3355
3356 void radv_FreeCommandBuffers(
3357 VkDevice device,
3358 VkCommandPool commandPool,
3359 uint32_t commandBufferCount,
3360 const VkCommandBuffer *pCommandBuffers)
3361 {
3362 for (uint32_t i = 0; i < commandBufferCount; i++) {
3363 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
3364
3365 if (cmd_buffer) {
3366 if (cmd_buffer->pool) {
3367 list_del(&cmd_buffer->pool_link);
3368 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
3369 } else
3370 radv_cmd_buffer_destroy(cmd_buffer);
3371
3372 }
3373 }
3374 }
3375
3376 VkResult radv_ResetCommandBuffer(
3377 VkCommandBuffer commandBuffer,
3378 VkCommandBufferResetFlags flags)
3379 {
3380 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3381 return radv_reset_cmd_buffer(cmd_buffer);
3382 }
3383
3384 VkResult radv_BeginCommandBuffer(
3385 VkCommandBuffer commandBuffer,
3386 const VkCommandBufferBeginInfo *pBeginInfo)
3387 {
3388 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3389 VkResult result = VK_SUCCESS;
3390
3391 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
3392 /* If the command buffer has already been resetted with
3393 * vkResetCommandBuffer, no need to do it again.
3394 */
3395 result = radv_reset_cmd_buffer(cmd_buffer);
3396 if (result != VK_SUCCESS)
3397 return result;
3398 }
3399
3400 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
3401 cmd_buffer->state.last_primitive_reset_en = -1;
3402 cmd_buffer->state.last_index_type = -1;
3403 cmd_buffer->state.last_num_instances = -1;
3404 cmd_buffer->state.last_vertex_offset = -1;
3405 cmd_buffer->state.last_first_instance = -1;
3406 cmd_buffer->state.predication_type = -1;
3407 cmd_buffer->state.last_sx_ps_downconvert = -1;
3408 cmd_buffer->state.last_sx_blend_opt_epsilon = -1;
3409 cmd_buffer->state.last_sx_blend_opt_control = -1;
3410 cmd_buffer->usage_flags = pBeginInfo->flags;
3411
3412 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
3413 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
3414 assert(pBeginInfo->pInheritanceInfo);
3415 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
3416 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
3417
3418 struct radv_subpass *subpass =
3419 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
3420
3421 if (cmd_buffer->state.framebuffer) {
3422 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
3423 if (result != VK_SUCCESS)
3424 return result;
3425 }
3426
3427 cmd_buffer->state.inherited_pipeline_statistics =
3428 pBeginInfo->pInheritanceInfo->pipelineStatistics;