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873549677c505d4be9f0ee546d02d0e7969916cd
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 bool src_render_loop,
58 VkImageLayout dst_layout,
59 bool dst_render_loop,
60 uint32_t src_family,
61 uint32_t dst_family,
62 const VkImageSubresourceRange *range,
63 struct radv_sample_locations_state *sample_locs);
64
65 const struct radv_dynamic_state default_dynamic_state = {
66 .viewport = {
67 .count = 0,
68 },
69 .scissor = {
70 .count = 0,
71 },
72 .line_width = 1.0f,
73 .depth_bias = {
74 .bias = 0.0f,
75 .clamp = 0.0f,
76 .slope = 0.0f,
77 },
78 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
79 .depth_bounds = {
80 .min = 0.0f,
81 .max = 1.0f,
82 },
83 .stencil_compare_mask = {
84 .front = ~0u,
85 .back = ~0u,
86 },
87 .stencil_write_mask = {
88 .front = ~0u,
89 .back = ~0u,
90 },
91 .stencil_reference = {
92 .front = 0u,
93 .back = 0u,
94 },
95 .line_stipple = {
96 .factor = 0u,
97 .pattern = 0u,
98 },
99 .cull_mode = 0u,
100 .front_face = 0u,
101 .primitive_topology = 0u,
102 };
103
104 static void
105 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
106 const struct radv_dynamic_state *src)
107 {
108 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
109 uint32_t copy_mask = src->mask;
110 uint32_t dest_mask = 0;
111
112 dest->discard_rectangle.count = src->discard_rectangle.count;
113 dest->sample_location.count = src->sample_location.count;
114
115 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
116 if (dest->viewport.count != src->viewport.count) {
117 dest->viewport.count = src->viewport.count;
118 dest_mask |= RADV_DYNAMIC_VIEWPORT;
119 }
120
121 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
122 src->viewport.count * sizeof(VkViewport))) {
123 typed_memcpy(dest->viewport.viewports,
124 src->viewport.viewports,
125 src->viewport.count);
126 dest_mask |= RADV_DYNAMIC_VIEWPORT;
127 }
128 }
129
130 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
131 if (dest->scissor.count != src->scissor.count) {
132 dest->scissor.count = src->scissor.count;
133 dest_mask |= RADV_DYNAMIC_SCISSOR;
134 }
135
136 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
137 src->scissor.count * sizeof(VkRect2D))) {
138 typed_memcpy(dest->scissor.scissors,
139 src->scissor.scissors, src->scissor.count);
140 dest_mask |= RADV_DYNAMIC_SCISSOR;
141 }
142 }
143
144 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
145 if (dest->line_width != src->line_width) {
146 dest->line_width = src->line_width;
147 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
148 }
149 }
150
151 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
152 if (memcmp(&dest->depth_bias, &src->depth_bias,
153 sizeof(src->depth_bias))) {
154 dest->depth_bias = src->depth_bias;
155 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
156 }
157 }
158
159 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
160 if (memcmp(&dest->blend_constants, &src->blend_constants,
161 sizeof(src->blend_constants))) {
162 typed_memcpy(dest->blend_constants,
163 src->blend_constants, 4);
164 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
165 }
166 }
167
168 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
169 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
170 sizeof(src->depth_bounds))) {
171 dest->depth_bounds = src->depth_bounds;
172 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
173 }
174 }
175
176 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
177 if (memcmp(&dest->stencil_compare_mask,
178 &src->stencil_compare_mask,
179 sizeof(src->stencil_compare_mask))) {
180 dest->stencil_compare_mask = src->stencil_compare_mask;
181 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
182 }
183 }
184
185 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
186 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
187 sizeof(src->stencil_write_mask))) {
188 dest->stencil_write_mask = src->stencil_write_mask;
189 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
190 }
191 }
192
193 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
194 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
195 sizeof(src->stencil_reference))) {
196 dest->stencil_reference = src->stencil_reference;
197 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
198 }
199 }
200
201 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
202 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
203 src->discard_rectangle.count * sizeof(VkRect2D))) {
204 typed_memcpy(dest->discard_rectangle.rectangles,
205 src->discard_rectangle.rectangles,
206 src->discard_rectangle.count);
207 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
208 }
209 }
210
211 if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
212 if (dest->sample_location.per_pixel != src->sample_location.per_pixel ||
213 dest->sample_location.grid_size.width != src->sample_location.grid_size.width ||
214 dest->sample_location.grid_size.height != src->sample_location.grid_size.height ||
215 memcmp(&dest->sample_location.locations,
216 &src->sample_location.locations,
217 src->sample_location.count * sizeof(VkSampleLocationEXT))) {
218 dest->sample_location.per_pixel = src->sample_location.per_pixel;
219 dest->sample_location.grid_size = src->sample_location.grid_size;
220 typed_memcpy(dest->sample_location.locations,
221 src->sample_location.locations,
222 src->sample_location.count);
223 dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
224 }
225 }
226
227 if (copy_mask & RADV_DYNAMIC_LINE_STIPPLE) {
228 if (memcmp(&dest->line_stipple, &src->line_stipple,
229 sizeof(src->line_stipple))) {
230 dest->line_stipple = src->line_stipple;
231 dest_mask |= RADV_DYNAMIC_LINE_STIPPLE;
232 }
233 }
234
235 if (copy_mask & RADV_DYNAMIC_CULL_MODE) {
236 if (dest->cull_mode != src->cull_mode) {
237 dest->cull_mode = src->cull_mode;
238 dest_mask |= RADV_DYNAMIC_CULL_MODE;
239 }
240 }
241
242 if (copy_mask & RADV_DYNAMIC_FRONT_FACE) {
243 if (dest->front_face != src->front_face) {
244 dest->front_face = src->front_face;
245 dest_mask |= RADV_DYNAMIC_FRONT_FACE;
246 }
247 }
248
249 if (copy_mask & RADV_DYNAMIC_PRIMITIVE_TOPOLOGY) {
250 if (dest->primitive_topology != src->primitive_topology) {
251 dest->primitive_topology = src->primitive_topology;
252 dest_mask |= RADV_DYNAMIC_PRIMITIVE_TOPOLOGY;
253 }
254 }
255
256 if (copy_mask & RADV_DYNAMIC_DEPTH_TEST_ENABLE) {
257 if (dest->depth_test_enable != src->depth_test_enable) {
258 dest->depth_test_enable = src->depth_test_enable;
259 dest_mask |= RADV_DYNAMIC_DEPTH_TEST_ENABLE;
260 }
261 }
262
263 if (copy_mask & RADV_DYNAMIC_DEPTH_WRITE_ENABLE) {
264 if (dest->depth_write_enable != src->depth_write_enable) {
265 dest->depth_write_enable = src->depth_write_enable;
266 dest_mask |= RADV_DYNAMIC_DEPTH_WRITE_ENABLE;
267 }
268 }
269
270 if (copy_mask & RADV_DYNAMIC_DEPTH_COMPARE_OP) {
271 if (dest->depth_compare_op != src->depth_compare_op) {
272 dest->depth_compare_op = src->depth_compare_op;
273 dest_mask |= RADV_DYNAMIC_DEPTH_COMPARE_OP;
274 }
275 }
276
277 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE) {
278 if (dest->depth_bounds_test_enable != src->depth_bounds_test_enable) {
279 dest->depth_bounds_test_enable = src->depth_bounds_test_enable;
280 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE;
281 }
282 }
283
284 if (copy_mask & RADV_DYNAMIC_STENCIL_TEST_ENABLE) {
285 if (dest->stencil_test_enable != src->stencil_test_enable) {
286 dest->stencil_test_enable = src->stencil_test_enable;
287 dest_mask |= RADV_DYNAMIC_STENCIL_TEST_ENABLE;
288 }
289 }
290
291 if (copy_mask & RADV_DYNAMIC_STENCIL_OP) {
292 if (memcmp(&dest->stencil_op, &src->stencil_op,
293 sizeof(src->stencil_op))) {
294 dest->stencil_op = src->stencil_op;
295 dest_mask |= RADV_DYNAMIC_STENCIL_OP;
296 }
297 }
298
299 cmd_buffer->state.dirty |= dest_mask;
300 }
301
302 static void
303 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
304 struct radv_pipeline *pipeline)
305 {
306 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
307 struct radv_shader_info *info;
308
309 if (!pipeline->streamout_shader ||
310 cmd_buffer->device->physical_device->use_ngg_streamout)
311 return;
312
313 info = &pipeline->streamout_shader->info;
314 for (int i = 0; i < MAX_SO_BUFFERS; i++)
315 so->stride_in_dw[i] = info->so.strides[i];
316
317 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
318 }
319
320 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
321 {
322 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
323 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
324 }
325
326 enum ring_type radv_queue_family_to_ring(int f) {
327 switch (f) {
328 case RADV_QUEUE_GENERAL:
329 return RING_GFX;
330 case RADV_QUEUE_COMPUTE:
331 return RING_COMPUTE;
332 case RADV_QUEUE_TRANSFER:
333 return RING_DMA;
334 default:
335 unreachable("Unknown queue family");
336 }
337 }
338
339 static void
340 radv_destroy_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
341 {
342 list_del(&cmd_buffer->pool_link);
343
344 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
345 &cmd_buffer->upload.list, list) {
346 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
347 list_del(&up->list);
348 free(up);
349 }
350
351 if (cmd_buffer->upload.upload_bo)
352 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
353
354 if (cmd_buffer->cs)
355 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
356
357 for (unsigned i = 0; i < MAX_BIND_POINTS; i++)
358 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
359
360 vk_object_base_finish(&cmd_buffer->base);
361 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
362 }
363
364 static VkResult radv_create_cmd_buffer(
365 struct radv_device * device,
366 struct radv_cmd_pool * pool,
367 VkCommandBufferLevel level,
368 VkCommandBuffer* pCommandBuffer)
369 {
370 struct radv_cmd_buffer *cmd_buffer;
371 unsigned ring;
372 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
373 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
374 if (cmd_buffer == NULL)
375 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
376
377 vk_object_base_init(&device->vk, &cmd_buffer->base,
378 VK_OBJECT_TYPE_COMMAND_BUFFER);
379
380 cmd_buffer->device = device;
381 cmd_buffer->pool = pool;
382 cmd_buffer->level = level;
383
384 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
385 cmd_buffer->queue_family_index = pool->queue_family_index;
386
387 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
388
389 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
390 if (!cmd_buffer->cs) {
391 radv_destroy_cmd_buffer(cmd_buffer);
392 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
393 }
394
395 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
396
397 list_inithead(&cmd_buffer->upload.list);
398
399 return VK_SUCCESS;
400 }
401
402 static VkResult
403 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
404 {
405 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
406
407 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
408 &cmd_buffer->upload.list, list) {
409 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
410 list_del(&up->list);
411 free(up);
412 }
413
414 cmd_buffer->push_constant_stages = 0;
415 cmd_buffer->scratch_size_per_wave_needed = 0;
416 cmd_buffer->scratch_waves_wanted = 0;
417 cmd_buffer->compute_scratch_size_per_wave_needed = 0;
418 cmd_buffer->compute_scratch_waves_wanted = 0;
419 cmd_buffer->esgs_ring_size_needed = 0;
420 cmd_buffer->gsvs_ring_size_needed = 0;
421 cmd_buffer->tess_rings_needed = false;
422 cmd_buffer->gds_needed = false;
423 cmd_buffer->gds_oa_needed = false;
424 cmd_buffer->sample_positions_needed = false;
425
426 if (cmd_buffer->upload.upload_bo)
427 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
428 cmd_buffer->upload.upload_bo);
429 cmd_buffer->upload.offset = 0;
430
431 cmd_buffer->record_result = VK_SUCCESS;
432
433 memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
434
435 for (unsigned i = 0; i < MAX_BIND_POINTS; i++) {
436 cmd_buffer->descriptors[i].dirty = 0;
437 cmd_buffer->descriptors[i].valid = 0;
438 cmd_buffer->descriptors[i].push_dirty = false;
439 }
440
441 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
442 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
443 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
444 unsigned fence_offset, eop_bug_offset;
445 void *fence_ptr;
446
447 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
448 &fence_ptr);
449
450 cmd_buffer->gfx9_fence_va =
451 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
452 cmd_buffer->gfx9_fence_va += fence_offset;
453
454 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
455 /* Allocate a buffer for the EOP bug on GFX9. */
456 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
457 &eop_bug_offset, &fence_ptr);
458 cmd_buffer->gfx9_eop_bug_va =
459 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
460 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
461 }
462 }
463
464 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
465
466 return cmd_buffer->record_result;
467 }
468
469 static bool
470 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
471 uint64_t min_needed)
472 {
473 uint64_t new_size;
474 struct radeon_winsys_bo *bo;
475 struct radv_cmd_buffer_upload *upload;
476 struct radv_device *device = cmd_buffer->device;
477
478 new_size = MAX2(min_needed, 16 * 1024);
479 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
480
481 bo = device->ws->buffer_create(device->ws,
482 new_size, 4096,
483 RADEON_DOMAIN_GTT,
484 RADEON_FLAG_CPU_ACCESS|
485 RADEON_FLAG_NO_INTERPROCESS_SHARING |
486 RADEON_FLAG_32BIT |
487 RADEON_FLAG_GTT_WC,
488 RADV_BO_PRIORITY_UPLOAD_BUFFER);
489
490 if (!bo) {
491 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
492 return false;
493 }
494
495 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
496 if (cmd_buffer->upload.upload_bo) {
497 upload = malloc(sizeof(*upload));
498
499 if (!upload) {
500 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
501 device->ws->buffer_destroy(bo);
502 return false;
503 }
504
505 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
506 list_add(&upload->list, &cmd_buffer->upload.list);
507 }
508
509 cmd_buffer->upload.upload_bo = bo;
510 cmd_buffer->upload.size = new_size;
511 cmd_buffer->upload.offset = 0;
512 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
513
514 if (!cmd_buffer->upload.map) {
515 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
516 return false;
517 }
518
519 return true;
520 }
521
522 bool
523 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
524 unsigned size,
525 unsigned alignment,
526 unsigned *out_offset,
527 void **ptr)
528 {
529 assert(util_is_power_of_two_nonzero(alignment));
530
531 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
532 if (offset + size > cmd_buffer->upload.size) {
533 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
534 return false;
535 offset = 0;
536 }
537
538 *out_offset = offset;
539 *ptr = cmd_buffer->upload.map + offset;
540
541 cmd_buffer->upload.offset = offset + size;
542 return true;
543 }
544
545 bool
546 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
547 unsigned size, unsigned alignment,
548 const void *data, unsigned *out_offset)
549 {
550 uint8_t *ptr;
551
552 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
553 out_offset, (void **)&ptr))
554 return false;
555
556 if (ptr)
557 memcpy(ptr, data, size);
558
559 return true;
560 }
561
562 static void
563 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
564 unsigned count, const uint32_t *data)
565 {
566 struct radeon_cmdbuf *cs = cmd_buffer->cs;
567
568 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
569
570 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
571 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
572 S_370_WR_CONFIRM(1) |
573 S_370_ENGINE_SEL(V_370_ME));
574 radeon_emit(cs, va);
575 radeon_emit(cs, va >> 32);
576 radeon_emit_array(cs, data, count);
577 }
578
579 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
580 {
581 struct radv_device *device = cmd_buffer->device;
582 struct radeon_cmdbuf *cs = cmd_buffer->cs;
583 uint64_t va;
584
585 va = radv_buffer_get_va(device->trace_bo);
586 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
587 va += 4;
588
589 ++cmd_buffer->state.trace_id;
590 radv_emit_write_data_packet(cmd_buffer, va, 1,
591 &cmd_buffer->state.trace_id);
592
593 radeon_check_space(cmd_buffer->device->ws, cs, 2);
594
595 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
596 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
597 }
598
599 static void
600 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
601 enum radv_cmd_flush_bits flags)
602 {
603 if (unlikely(cmd_buffer->device->thread_trace_bo)) {
604 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
605 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_THREAD_TRACE_MARKER) | EVENT_INDEX(0));
606 }
607
608 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
609 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
610 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
611
612 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
613
614 /* Force wait for graphics or compute engines to be idle. */
615 si_cs_emit_cache_flush(cmd_buffer->cs,
616 cmd_buffer->device->physical_device->rad_info.chip_class,
617 &cmd_buffer->gfx9_fence_idx,
618 cmd_buffer->gfx9_fence_va,
619 radv_cmd_buffer_uses_mec(cmd_buffer),
620 flags, cmd_buffer->gfx9_eop_bug_va);
621 }
622
623 if (unlikely(cmd_buffer->device->trace_bo))
624 radv_cmd_buffer_trace_emit(cmd_buffer);
625 }
626
627 static void
628 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
629 struct radv_pipeline *pipeline, enum ring_type ring)
630 {
631 struct radv_device *device = cmd_buffer->device;
632 uint32_t data[2];
633 uint64_t va;
634
635 va = radv_buffer_get_va(device->trace_bo);
636
637 switch (ring) {
638 case RING_GFX:
639 va += 8;
640 break;
641 case RING_COMPUTE:
642 va += 16;
643 break;
644 default:
645 assert(!"invalid ring type");
646 }
647
648 uint64_t pipeline_address = (uintptr_t)pipeline;
649 data[0] = pipeline_address;
650 data[1] = pipeline_address >> 32;
651
652 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
653 }
654
655 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
656 VkPipelineBindPoint bind_point,
657 struct radv_descriptor_set *set,
658 unsigned idx)
659 {
660 struct radv_descriptor_state *descriptors_state =
661 radv_get_descriptors_state(cmd_buffer, bind_point);
662
663 descriptors_state->sets[idx] = set;
664
665 descriptors_state->valid |= (1u << idx); /* active descriptors */
666 descriptors_state->dirty |= (1u << idx);
667 }
668
669 static void
670 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
671 VkPipelineBindPoint bind_point)
672 {
673 struct radv_descriptor_state *descriptors_state =
674 radv_get_descriptors_state(cmd_buffer, bind_point);
675 struct radv_device *device = cmd_buffer->device;
676 uint32_t data[MAX_SETS * 2] = {};
677 uint64_t va;
678 unsigned i;
679 va = radv_buffer_get_va(device->trace_bo) + 24;
680
681 for_each_bit(i, descriptors_state->valid) {
682 struct radv_descriptor_set *set = descriptors_state->sets[i];
683 data[i * 2] = (uint64_t)(uintptr_t)set;
684 data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
685 }
686
687 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
688 }
689
690 struct radv_userdata_info *
691 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
692 gl_shader_stage stage,
693 int idx)
694 {
695 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
696 return &shader->info.user_sgprs_locs.shader_data[idx];
697 }
698
699 static void
700 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
701 struct radv_pipeline *pipeline,
702 gl_shader_stage stage,
703 int idx, uint64_t va)
704 {
705 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
706 uint32_t base_reg = pipeline->user_data_0[stage];
707 if (loc->sgpr_idx == -1)
708 return;
709
710 assert(loc->num_sgprs == 1);
711
712 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
713 base_reg + loc->sgpr_idx * 4, va, false);
714 }
715
716 static void
717 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
718 struct radv_pipeline *pipeline,
719 struct radv_descriptor_state *descriptors_state,
720 gl_shader_stage stage)
721 {
722 struct radv_device *device = cmd_buffer->device;
723 struct radeon_cmdbuf *cs = cmd_buffer->cs;
724 uint32_t sh_base = pipeline->user_data_0[stage];
725 struct radv_userdata_locations *locs =
726 &pipeline->shaders[stage]->info.user_sgprs_locs;
727 unsigned mask = locs->descriptor_sets_enabled;
728
729 mask &= descriptors_state->dirty & descriptors_state->valid;
730
731 while (mask) {
732 int start, count;
733
734 u_bit_scan_consecutive_range(&mask, &start, &count);
735
736 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
737 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
738
739 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
740 for (int i = 0; i < count; i++) {
741 struct radv_descriptor_set *set =
742 descriptors_state->sets[start + i];
743
744 radv_emit_shader_pointer_body(device, cs, set->va, true);
745 }
746 }
747 }
748
749 /**
750 * Convert the user sample locations to hardware sample locations (the values
751 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
752 */
753 static void
754 radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
755 uint32_t x, uint32_t y, VkOffset2D *sample_locs)
756 {
757 uint32_t x_offset = x % state->grid_size.width;
758 uint32_t y_offset = y % state->grid_size.height;
759 uint32_t num_samples = (uint32_t)state->per_pixel;
760 VkSampleLocationEXT *user_locs;
761 uint32_t pixel_offset;
762
763 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
764
765 assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
766 user_locs = &state->locations[pixel_offset];
767
768 for (uint32_t i = 0; i < num_samples; i++) {
769 float shifted_pos_x = user_locs[i].x - 0.5;
770 float shifted_pos_y = user_locs[i].y - 0.5;
771
772 int32_t scaled_pos_x = floorf(shifted_pos_x * 16);
773 int32_t scaled_pos_y = floorf(shifted_pos_y * 16);
774
775 sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
776 sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
777 }
778 }
779
780 /**
781 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
782 * locations.
783 */
784 static void
785 radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
786 uint32_t *sample_locs_pixel)
787 {
788 for (uint32_t i = 0; i < num_samples; i++) {
789 uint32_t sample_reg_idx = i / 4;
790 uint32_t sample_loc_idx = i % 4;
791 int32_t pos_x = sample_locs[i].x;
792 int32_t pos_y = sample_locs[i].y;
793
794 uint32_t shift_x = 8 * sample_loc_idx;
795 uint32_t shift_y = shift_x + 4;
796
797 sample_locs_pixel[sample_reg_idx] |= (pos_x & 0xf) << shift_x;
798 sample_locs_pixel[sample_reg_idx] |= (pos_y & 0xf) << shift_y;
799 }
800 }
801
802 /**
803 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
804 * sample locations.
805 */
806 static uint64_t
807 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer,
808 VkOffset2D *sample_locs,
809 uint32_t num_samples)
810 {
811 uint32_t centroid_priorities[num_samples];
812 uint32_t sample_mask = num_samples - 1;
813 uint32_t distances[num_samples];
814 uint64_t centroid_priority = 0;
815
816 /* Compute the distances from center for each sample. */
817 for (int i = 0; i < num_samples; i++) {
818 distances[i] = (sample_locs[i].x * sample_locs[i].x) +
819 (sample_locs[i].y * sample_locs[i].y);
820 }
821
822 /* Compute the centroid priorities by looking at the distances array. */
823 for (int i = 0; i < num_samples; i++) {
824 uint32_t min_idx = 0;
825
826 for (int j = 1; j < num_samples; j++) {
827 if (distances[j] < distances[min_idx])
828 min_idx = j;
829 }
830
831 centroid_priorities[i] = min_idx;
832 distances[min_idx] = 0xffffffff;
833 }
834
835 /* Compute the final centroid priority. */
836 for (int i = 0; i < 8; i++) {
837 centroid_priority |=
838 centroid_priorities[i & sample_mask] << (i * 4);
839 }
840
841 return centroid_priority << 32 | centroid_priority;
842 }
843
844 /**
845 * Emit the sample locations that are specified with VK_EXT_sample_locations.
846 */
847 static void
848 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
849 {
850 struct radv_sample_locations_state *sample_location =
851 &cmd_buffer->state.dynamic.sample_location;
852 uint32_t num_samples = (uint32_t)sample_location->per_pixel;
853 struct radeon_cmdbuf *cs = cmd_buffer->cs;
854 uint32_t sample_locs_pixel[4][2] = {};
855 VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
856 uint32_t max_sample_dist = 0;
857 uint64_t centroid_priority;
858
859 if (!cmd_buffer->state.dynamic.sample_location.count)
860 return;
861
862 /* Convert the user sample locations to hardware sample locations. */
863 radv_convert_user_sample_locs(sample_location, 0, 0, sample_locs[0]);
864 radv_convert_user_sample_locs(sample_location, 1, 0, sample_locs[1]);
865 radv_convert_user_sample_locs(sample_location, 0, 1, sample_locs[2]);
866 radv_convert_user_sample_locs(sample_location, 1, 1, sample_locs[3]);
867
868 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
869 for (uint32_t i = 0; i < 4; i++) {
870 radv_compute_sample_locs_pixel(num_samples, sample_locs[i],
871 sample_locs_pixel[i]);
872 }
873
874 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
875 centroid_priority =
876 radv_compute_centroid_priority(cmd_buffer, sample_locs[0],
877 num_samples);
878
879 /* Compute the maximum sample distance from the specified locations. */
880 for (unsigned i = 0; i < 4; ++i) {
881 for (uint32_t j = 0; j < num_samples; j++) {
882 VkOffset2D offset = sample_locs[i][j];
883 max_sample_dist = MAX2(max_sample_dist,
884 MAX2(abs(offset.x), abs(offset.y)));
885 }
886 }
887
888 /* Emit the specified user sample locations. */
889 switch (num_samples) {
890 case 2:
891 case 4:
892 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
893 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
894 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
895 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
896 break;
897 case 8:
898 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
899 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
900 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
901 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
902 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs_pixel[0][1]);
903 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs_pixel[1][1]);
904 radeon_set_context_reg(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs_pixel[2][1]);
905 radeon_set_context_reg(cs, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs_pixel[3][1]);
906 break;
907 default:
908 unreachable("invalid number of samples");
909 }
910
911 /* Emit the maximum sample distance and the centroid priority. */
912 radeon_set_context_reg_rmw(cs, R_028BE0_PA_SC_AA_CONFIG,
913 S_028BE0_MAX_SAMPLE_DIST(max_sample_dist),
914 ~C_028BE0_MAX_SAMPLE_DIST);
915
916 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
917 radeon_emit(cs, centroid_priority);
918 radeon_emit(cs, centroid_priority >> 32);
919
920 /* GFX9: Flush DFSM when the AA mode changes. */
921 if (cmd_buffer->device->dfsm_allowed) {
922 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
923 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
924 }
925
926 cmd_buffer->state.context_roll_without_scissor_emitted = true;
927 }
928
929 static void
930 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
931 struct radv_pipeline *pipeline,
932 gl_shader_stage stage,
933 int idx, int count, uint32_t *values)
934 {
935 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
936 uint32_t base_reg = pipeline->user_data_0[stage];
937 if (loc->sgpr_idx == -1)
938 return;
939
940 assert(loc->num_sgprs == count);
941
942 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
943 radeon_emit_array(cmd_buffer->cs, values, count);
944 }
945
946 static void
947 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
948 struct radv_pipeline *pipeline)
949 {
950 int num_samples = pipeline->graphics.ms.num_samples;
951 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
952
953 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.needs_sample_positions)
954 cmd_buffer->sample_positions_needed = true;
955
956 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
957 return;
958
959 radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
960
961 cmd_buffer->state.context_roll_without_scissor_emitted = true;
962 }
963
964 static void
965 radv_update_binning_state(struct radv_cmd_buffer *cmd_buffer,
966 struct radv_pipeline *pipeline)
967 {
968 const struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
969
970
971 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
972 return;
973
974 if (old_pipeline &&
975 old_pipeline->graphics.binning.pa_sc_binner_cntl_0 == pipeline->graphics.binning.pa_sc_binner_cntl_0 &&
976 old_pipeline->graphics.binning.db_dfsm_control == pipeline->graphics.binning.db_dfsm_control)
977 return;
978
979 bool binning_flush = false;
980 if (cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA12 ||
981 cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA20 ||
982 cmd_buffer->device->physical_device->rad_info.family == CHIP_RAVEN2 ||
983 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
984 binning_flush = !old_pipeline ||
985 G_028C44_BINNING_MODE(old_pipeline->graphics.binning.pa_sc_binner_cntl_0) !=
986 G_028C44_BINNING_MODE(pipeline->graphics.binning.pa_sc_binner_cntl_0);
987 }
988
989 radeon_set_context_reg(cmd_buffer->cs, R_028C44_PA_SC_BINNER_CNTL_0,
990 pipeline->graphics.binning.pa_sc_binner_cntl_0 |
991 S_028C44_FLUSH_ON_BINNING_TRANSITION(!!binning_flush));
992
993 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
994 radeon_set_context_reg(cmd_buffer->cs, R_028038_DB_DFSM_CONTROL,
995 pipeline->graphics.binning.db_dfsm_control);
996 } else {
997 radeon_set_context_reg(cmd_buffer->cs, R_028060_DB_DFSM_CONTROL,
998 pipeline->graphics.binning.db_dfsm_control);
999 }
1000
1001 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1002 }
1003
1004
1005 static void
1006 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
1007 struct radv_shader_variant *shader)
1008 {
1009 uint64_t va;
1010
1011 if (!shader)
1012 return;
1013
1014 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
1015
1016 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
1017 }
1018
1019 static void
1020 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
1021 struct radv_pipeline *pipeline,
1022 bool vertex_stage_only)
1023 {
1024 struct radv_cmd_state *state = &cmd_buffer->state;
1025 uint32_t mask = state->prefetch_L2_mask;
1026
1027 if (vertex_stage_only) {
1028 /* Fast prefetch path for starting draws as soon as possible.
1029 */
1030 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
1031 RADV_PREFETCH_VBO_DESCRIPTORS);
1032 }
1033
1034 if (mask & RADV_PREFETCH_VS)
1035 radv_emit_shader_prefetch(cmd_buffer,
1036 pipeline->shaders[MESA_SHADER_VERTEX]);
1037
1038 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
1039 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
1040
1041 if (mask & RADV_PREFETCH_TCS)
1042 radv_emit_shader_prefetch(cmd_buffer,
1043 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
1044
1045 if (mask & RADV_PREFETCH_TES)
1046 radv_emit_shader_prefetch(cmd_buffer,
1047 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
1048
1049 if (mask & RADV_PREFETCH_GS) {
1050 radv_emit_shader_prefetch(cmd_buffer,
1051 pipeline->shaders[MESA_SHADER_GEOMETRY]);
1052 if (radv_pipeline_has_gs_copy_shader(pipeline))
1053 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
1054 }
1055
1056 if (mask & RADV_PREFETCH_PS)
1057 radv_emit_shader_prefetch(cmd_buffer,
1058 pipeline->shaders[MESA_SHADER_FRAGMENT]);
1059
1060 state->prefetch_L2_mask &= ~mask;
1061 }
1062
1063 static void
1064 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
1065 {
1066 if (!cmd_buffer->device->physical_device->rad_info.rbplus_allowed)
1067 return;
1068
1069 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1070 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1071
1072 unsigned sx_ps_downconvert = 0;
1073 unsigned sx_blend_opt_epsilon = 0;
1074 unsigned sx_blend_opt_control = 0;
1075
1076 if (!cmd_buffer->state.attachments || !subpass)
1077 return;
1078
1079 for (unsigned i = 0; i < subpass->color_count; ++i) {
1080 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1081 /* We don't set the DISABLE bits, because the HW can't have holes,
1082 * so the SPI color format is set to 32-bit 1-component. */
1083 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1084 continue;
1085 }
1086
1087 int idx = subpass->color_attachments[i].attachment;
1088 struct radv_color_buffer_info *cb = &cmd_buffer->state.attachments[idx].cb;
1089
1090 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
1091 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
1092 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
1093 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
1094
1095 bool has_alpha, has_rgb;
1096
1097 /* Set if RGB and A are present. */
1098 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
1099
1100 if (format == V_028C70_COLOR_8 ||
1101 format == V_028C70_COLOR_16 ||
1102 format == V_028C70_COLOR_32)
1103 has_rgb = !has_alpha;
1104 else
1105 has_rgb = true;
1106
1107 /* Check the colormask and export format. */
1108 if (!(colormask & 0x7))
1109 has_rgb = false;
1110 if (!(colormask & 0x8))
1111 has_alpha = false;
1112
1113 if (spi_format == V_028714_SPI_SHADER_ZERO) {
1114 has_rgb = false;
1115 has_alpha = false;
1116 }
1117
1118 /* Disable value checking for disabled channels. */
1119 if (!has_rgb)
1120 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1121 if (!has_alpha)
1122 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1123
1124 /* Enable down-conversion for 32bpp and smaller formats. */
1125 switch (format) {
1126 case V_028C70_COLOR_8:
1127 case V_028C70_COLOR_8_8:
1128 case V_028C70_COLOR_8_8_8_8:
1129 /* For 1 and 2-channel formats, use the superset thereof. */
1130 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
1131 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1132 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1133 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
1134 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
1135 }
1136 break;
1137
1138 case V_028C70_COLOR_5_6_5:
1139 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1140 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
1141 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
1142 }
1143 break;
1144
1145 case V_028C70_COLOR_1_5_5_5:
1146 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1147 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
1148 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
1149 }
1150 break;
1151
1152 case V_028C70_COLOR_4_4_4_4:
1153 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1154 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
1155 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
1156 }
1157 break;
1158
1159 case V_028C70_COLOR_32:
1160 if (swap == V_028C70_SWAP_STD &&
1161 spi_format == V_028714_SPI_SHADER_32_R)
1162 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1163 else if (swap == V_028C70_SWAP_ALT_REV &&
1164 spi_format == V_028714_SPI_SHADER_32_AR)
1165 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
1166 break;
1167
1168 case V_028C70_COLOR_16:
1169 case V_028C70_COLOR_16_16:
1170 /* For 1-channel formats, use the superset thereof. */
1171 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
1172 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
1173 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1174 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1175 if (swap == V_028C70_SWAP_STD ||
1176 swap == V_028C70_SWAP_STD_REV)
1177 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
1178 else
1179 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
1180 }
1181 break;
1182
1183 case V_028C70_COLOR_10_11_11:
1184 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1185 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
1186 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
1187 }
1188 break;
1189
1190 case V_028C70_COLOR_2_10_10_10:
1191 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1192 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
1193 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
1194 }
1195 break;
1196 }
1197 }
1198
1199 /* Do not set the DISABLE bits for the unused attachments, as that
1200 * breaks dual source blending in SkQP and does not seem to improve
1201 * performance. */
1202
1203 if (sx_ps_downconvert == cmd_buffer->state.last_sx_ps_downconvert &&
1204 sx_blend_opt_epsilon == cmd_buffer->state.last_sx_blend_opt_epsilon &&
1205 sx_blend_opt_control == cmd_buffer->state.last_sx_blend_opt_control)
1206 return;
1207
1208 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
1209 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
1210 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
1211 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
1212
1213 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1214
1215 cmd_buffer->state.last_sx_ps_downconvert = sx_ps_downconvert;
1216 cmd_buffer->state.last_sx_blend_opt_epsilon = sx_blend_opt_epsilon;
1217 cmd_buffer->state.last_sx_blend_opt_control = sx_blend_opt_control;
1218 }
1219
1220 static void
1221 radv_emit_batch_break_on_new_ps(struct radv_cmd_buffer *cmd_buffer)
1222 {
1223 if (!cmd_buffer->device->pbb_allowed)
1224 return;
1225
1226 struct radv_binning_settings settings =
1227 radv_get_binning_settings(cmd_buffer->device->physical_device);
1228 bool break_for_new_ps =
1229 (!cmd_buffer->state.emitted_pipeline ||
1230 cmd_buffer->state.emitted_pipeline->shaders[MESA_SHADER_FRAGMENT] !=
1231 cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT]) &&
1232 (settings.context_states_per_bin > 1 ||
1233 settings.persistent_states_per_bin > 1);
1234 bool break_for_new_cb_target_mask =
1235 (!cmd_buffer->state.emitted_pipeline ||
1236 cmd_buffer->state.emitted_pipeline->graphics.cb_target_mask !=
1237 cmd_buffer->state.pipeline->graphics.cb_target_mask) &&
1238 settings.context_states_per_bin > 1;
1239
1240 if (!break_for_new_ps && !break_for_new_cb_target_mask)
1241 return;
1242
1243 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1244 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1245 }
1246
1247 static void
1248 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1249 {
1250 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1251
1252 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1253 return;
1254
1255 radv_update_multisample_state(cmd_buffer, pipeline);
1256 radv_update_binning_state(cmd_buffer, pipeline);
1257
1258 cmd_buffer->scratch_size_per_wave_needed = MAX2(cmd_buffer->scratch_size_per_wave_needed,
1259 pipeline->scratch_bytes_per_wave);
1260 cmd_buffer->scratch_waves_wanted = MAX2(cmd_buffer->scratch_waves_wanted,
1261 pipeline->max_waves);
1262
1263 if (!cmd_buffer->state.emitted_pipeline ||
1264 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1265 pipeline->graphics.can_use_guardband)
1266 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1267
1268 if (!cmd_buffer->state.emitted_pipeline ||
1269 cmd_buffer->state.emitted_pipeline->graphics.pa_su_sc_mode_cntl !=
1270 pipeline->graphics.pa_su_sc_mode_cntl)
1271 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_CULL_MODE |
1272 RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE;
1273
1274 if (!cmd_buffer->state.emitted_pipeline)
1275 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY;
1276
1277 if (!cmd_buffer->state.emitted_pipeline ||
1278 cmd_buffer->state.emitted_pipeline->graphics.db_depth_control !=
1279 pipeline->graphics.db_depth_control)
1280 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE |
1281 RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE |
1282 RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP |
1283 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE |
1284 RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE |
1285 RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP;
1286
1287 if (!cmd_buffer->state.emitted_pipeline)
1288 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP;
1289
1290 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
1291
1292 if (!cmd_buffer->state.emitted_pipeline ||
1293 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
1294 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
1295 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
1296 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
1297 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
1298 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1299 }
1300
1301 radv_emit_batch_break_on_new_ps(cmd_buffer);
1302
1303 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
1304 if (!pipeline->shaders[i])
1305 continue;
1306
1307 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1308 pipeline->shaders[i]->bo);
1309 }
1310
1311 if (radv_pipeline_has_gs_copy_shader(pipeline))
1312 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1313 pipeline->gs_copy_shader->bo);
1314
1315 if (unlikely(cmd_buffer->device->trace_bo))
1316 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1317
1318 cmd_buffer->state.emitted_pipeline = pipeline;
1319
1320 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1321 }
1322
1323 static void
1324 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1325 {
1326 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1327 cmd_buffer->state.dynamic.viewport.viewports);
1328 }
1329
1330 static void
1331 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1332 {
1333 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1334
1335 si_write_scissors(cmd_buffer->cs, 0, count,
1336 cmd_buffer->state.dynamic.scissor.scissors,
1337 cmd_buffer->state.dynamic.viewport.viewports,
1338 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1339
1340 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1341 }
1342
1343 static void
1344 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1345 {
1346 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1347 return;
1348
1349 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1350 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1351 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1352 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1353 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1354 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1355 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1356 }
1357 }
1358
1359 static void
1360 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1361 {
1362 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1363
1364 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1365 S_028A08_WIDTH(CLAMP(width, 0, 0xFFFF)));
1366 }
1367
1368 static void
1369 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1370 {
1371 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1372
1373 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1374 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1375 }
1376
1377 static void
1378 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1379 {
1380 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1381
1382 radeon_set_context_reg_seq(cmd_buffer->cs,
1383 R_028430_DB_STENCILREFMASK, 2);
1384 radeon_emit(cmd_buffer->cs,
1385 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1386 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1387 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1388 S_028430_STENCILOPVAL(1));
1389 radeon_emit(cmd_buffer->cs,
1390 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1391 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1392 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1393 S_028434_STENCILOPVAL_BF(1));
1394 }
1395
1396 static void
1397 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1398 {
1399 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1400
1401 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1402 fui(d->depth_bounds.min));
1403 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1404 fui(d->depth_bounds.max));
1405 }
1406
1407 static void
1408 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1409 {
1410 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1411 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1412 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1413
1414
1415 radeon_set_context_reg_seq(cmd_buffer->cs,
1416 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1417 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1418 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1419 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1420 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1421 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1422 }
1423
1424 static void
1425 radv_emit_line_stipple(struct radv_cmd_buffer *cmd_buffer)
1426 {
1427 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1428 uint32_t auto_reset_cntl = 1;
1429
1430 if (d->primitive_topology == V_008958_DI_PT_LINESTRIP)
1431 auto_reset_cntl = 2;
1432
1433 radeon_set_context_reg(cmd_buffer->cs, R_028A0C_PA_SC_LINE_STIPPLE,
1434 S_028A0C_LINE_PATTERN(d->line_stipple.pattern) |
1435 S_028A0C_REPEAT_COUNT(d->line_stipple.factor - 1) |
1436 S_028A0C_AUTO_RESET_CNTL(auto_reset_cntl));
1437 }
1438
1439 static void
1440 radv_emit_culling(struct radv_cmd_buffer *cmd_buffer, uint32_t states)
1441 {
1442 unsigned pa_su_sc_mode_cntl = cmd_buffer->state.pipeline->graphics.pa_su_sc_mode_cntl;
1443 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1444
1445 if (states & RADV_CMD_DIRTY_DYNAMIC_CULL_MODE) {
1446 pa_su_sc_mode_cntl &= C_028814_CULL_FRONT;
1447 pa_su_sc_mode_cntl |= S_028814_CULL_FRONT(!!(d->cull_mode & VK_CULL_MODE_FRONT_BIT));
1448
1449 pa_su_sc_mode_cntl &= C_028814_CULL_BACK;
1450 pa_su_sc_mode_cntl |= S_028814_CULL_BACK(!!(d->cull_mode & VK_CULL_MODE_BACK_BIT));
1451 }
1452
1453 if (states & RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE) {
1454 pa_su_sc_mode_cntl &= C_028814_FACE;
1455 pa_su_sc_mode_cntl |= S_028814_FACE(d->front_face);
1456 }
1457
1458 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
1459 pa_su_sc_mode_cntl);
1460 }
1461
1462 static void
1463 radv_emit_primitive_topology(struct radv_cmd_buffer *cmd_buffer)
1464 {
1465 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1466
1467 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1468 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
1469 cmd_buffer->cs,
1470 R_030908_VGT_PRIMITIVE_TYPE, 1,
1471 d->primitive_topology);
1472 } else {
1473 radeon_set_config_reg(cmd_buffer->cs,
1474 R_008958_VGT_PRIMITIVE_TYPE,
1475 d->primitive_topology);
1476 }
1477 }
1478
1479 static void
1480 radv_emit_depth_control(struct radv_cmd_buffer *cmd_buffer, uint32_t states)
1481 {
1482 unsigned db_depth_control = cmd_buffer->state.pipeline->graphics.db_depth_control;
1483 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1484
1485 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE) {
1486 db_depth_control &= C_028800_Z_ENABLE;
1487 db_depth_control |= S_028800_Z_ENABLE(d->depth_test_enable ? 1 : 0);
1488 }
1489
1490 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE) {
1491 db_depth_control &= C_028800_Z_WRITE_ENABLE;
1492 db_depth_control |= S_028800_Z_WRITE_ENABLE(d->depth_write_enable ? 1 : 0);
1493 }
1494
1495 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP) {
1496 db_depth_control &= C_028800_ZFUNC;
1497 db_depth_control |= S_028800_ZFUNC(d->depth_compare_op);
1498 }
1499
1500 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE) {
1501 db_depth_control &= C_028800_DEPTH_BOUNDS_ENABLE;
1502 db_depth_control |= S_028800_DEPTH_BOUNDS_ENABLE(d->depth_bounds_test_enable ? 1 : 0);
1503 }
1504
1505 if (states & RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE) {
1506 db_depth_control &= C_028800_STENCIL_ENABLE;
1507 db_depth_control |= S_028800_STENCIL_ENABLE(d->stencil_test_enable ? 1 : 0);
1508
1509 db_depth_control &= C_028800_BACKFACE_ENABLE;
1510 db_depth_control |= S_028800_BACKFACE_ENABLE(d->stencil_test_enable ? 1 : 0);
1511 }
1512
1513 if (states & RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP) {
1514 db_depth_control &= C_028800_STENCILFUNC;
1515 db_depth_control |= S_028800_STENCILFUNC(d->stencil_op.front.compare_op);
1516
1517 db_depth_control &= C_028800_STENCILFUNC_BF;
1518 db_depth_control |= S_028800_STENCILFUNC_BF(d->stencil_op.back.compare_op);
1519 }
1520
1521 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL,
1522 db_depth_control);
1523 }
1524
1525 static void
1526 radv_emit_stencil_control(struct radv_cmd_buffer *cmd_buffer)
1527 {
1528 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1529
1530 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL,
1531 S_02842C_STENCILFAIL(si_translate_stencil_op(d->stencil_op.front.fail_op)) |
1532 S_02842C_STENCILZPASS(si_translate_stencil_op(d->stencil_op.front.pass_op)) |
1533 S_02842C_STENCILZFAIL(si_translate_stencil_op(d->stencil_op.front.depth_fail_op)) |
1534 S_02842C_STENCILFAIL_BF(si_translate_stencil_op(d->stencil_op.back.fail_op)) |
1535 S_02842C_STENCILZPASS_BF(si_translate_stencil_op(d->stencil_op.back.pass_op)) |
1536 S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(d->stencil_op.back.depth_fail_op)));
1537 }
1538
1539 static void
1540 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1541 int index,
1542 struct radv_color_buffer_info *cb,
1543 struct radv_image_view *iview,
1544 VkImageLayout layout,
1545 bool in_render_loop)
1546 {
1547 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
1548 uint32_t cb_color_info = cb->cb_color_info;
1549 struct radv_image *image = iview->image;
1550
1551 if (!radv_layout_dcc_compressed(cmd_buffer->device, image, layout, in_render_loop,
1552 radv_image_queue_family_mask(image,
1553 cmd_buffer->queue_family_index,
1554 cmd_buffer->queue_family_index))) {
1555 cb_color_info &= C_028C70_DCC_ENABLE;
1556 }
1557
1558 if (!radv_layout_can_fast_clear(image, layout, in_render_loop,
1559 radv_image_queue_family_mask(image,
1560 cmd_buffer->queue_family_index,
1561 cmd_buffer->queue_family_index))) {
1562 cb_color_info &= C_028C70_COMPRESSION;
1563 }
1564
1565 if (radv_image_is_tc_compat_cmask(image) &&
1566 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1567 radv_is_dcc_decompress_pipeline(cmd_buffer))) {
1568 /* If this bit is set, the FMASK decompression operation
1569 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1570 */
1571 cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
1572 }
1573
1574 if (radv_image_has_fmask(image) &&
1575 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1576 radv_is_hw_resolve_pipeline(cmd_buffer))) {
1577 /* Make sure FMASK is enabled if it has been cleared because:
1578 *
1579 * 1) it's required for FMASK_DECOMPRESS operations to avoid
1580 * GPU hangs
1581 * 2) it's necessary for CB_RESOLVE which can read compressed
1582 * FMASK data anyways.
1583 */
1584 cb_color_info |= S_028C70_COMPRESSION(1);
1585 }
1586
1587 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1588 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1589 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1590 radeon_emit(cmd_buffer->cs, 0);
1591 radeon_emit(cmd_buffer->cs, 0);
1592 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1593 radeon_emit(cmd_buffer->cs, cb_color_info);
1594 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1595 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1596 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1597 radeon_emit(cmd_buffer->cs, 0);
1598 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1599 radeon_emit(cmd_buffer->cs, 0);
1600
1601 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 1);
1602 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1603
1604 radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4,
1605 cb->cb_color_base >> 32);
1606 radeon_set_context_reg(cmd_buffer->cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + index * 4,
1607 cb->cb_color_cmask >> 32);
1608 radeon_set_context_reg(cmd_buffer->cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + index * 4,
1609 cb->cb_color_fmask >> 32);
1610 radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4,
1611 cb->cb_dcc_base >> 32);
1612 radeon_set_context_reg(cmd_buffer->cs, R_028EC0_CB_COLOR0_ATTRIB2 + index * 4,
1613 cb->cb_color_attrib2);
1614 radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4,
1615 cb->cb_color_attrib3);
1616 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1617 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1618 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1619 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1620 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1621 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1622 radeon_emit(cmd_buffer->cs, cb_color_info);
1623 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1624 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1625 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1626 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1627 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1628 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1629
1630 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1631 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1632 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1633
1634 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1635 cb->cb_mrt_epitch);
1636 } else {
1637 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1638 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1639 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1640 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1641 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1642 radeon_emit(cmd_buffer->cs, cb_color_info);
1643 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1644 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1645 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1646 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1647 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1648 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1649
1650 if (is_vi) { /* DCC BASE */
1651 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1652 }
1653 }
1654
1655 if (radv_dcc_enabled(image, iview->base_mip)) {
1656 /* Drawing with DCC enabled also compresses colorbuffers. */
1657 VkImageSubresourceRange range = {
1658 .aspectMask = iview->aspect_mask,
1659 .baseMipLevel = iview->base_mip,
1660 .levelCount = iview->level_count,
1661 .baseArrayLayer = iview->base_layer,
1662 .layerCount = iview->layer_count,
1663 };
1664
1665 radv_update_dcc_metadata(cmd_buffer, image, &range, true);
1666 }
1667 }
1668
1669 static void
1670 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1671 struct radv_ds_buffer_info *ds,
1672 const struct radv_image_view *iview,
1673 VkImageLayout layout,
1674 bool in_render_loop, bool requires_cond_exec)
1675 {
1676 const struct radv_image *image = iview->image;
1677 uint32_t db_z_info = ds->db_z_info;
1678 uint32_t db_z_info_reg;
1679
1680 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug ||
1681 !radv_image_is_tc_compat_htile(image))
1682 return;
1683
1684 if (!radv_layout_is_htile_compressed(image, layout, in_render_loop,
1685 radv_image_queue_family_mask(image,
1686 cmd_buffer->queue_family_index,
1687 cmd_buffer->queue_family_index))) {
1688 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1689 }
1690
1691 db_z_info &= C_028040_ZRANGE_PRECISION;
1692
1693 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1694 db_z_info_reg = R_028038_DB_Z_INFO;
1695 } else {
1696 db_z_info_reg = R_028040_DB_Z_INFO;
1697 }
1698
1699 /* When we don't know the last fast clear value we need to emit a
1700 * conditional packet that will eventually skip the following
1701 * SET_CONTEXT_REG packet.
1702 */
1703 if (requires_cond_exec) {
1704 uint64_t va = radv_get_tc_compat_zrange_va(image, iview->base_mip);
1705
1706 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1707 radeon_emit(cmd_buffer->cs, va);
1708 radeon_emit(cmd_buffer->cs, va >> 32);
1709 radeon_emit(cmd_buffer->cs, 0);
1710 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1711 }
1712
1713 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1714 }
1715
1716 static void
1717 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1718 struct radv_ds_buffer_info *ds,
1719 struct radv_image_view *iview,
1720 VkImageLayout layout,
1721 bool in_render_loop)
1722 {
1723 const struct radv_image *image = iview->image;
1724 uint32_t db_z_info = ds->db_z_info;
1725 uint32_t db_stencil_info = ds->db_stencil_info;
1726
1727 if (!radv_layout_is_htile_compressed(image, layout, in_render_loop,
1728 radv_image_queue_family_mask(image,
1729 cmd_buffer->queue_family_index,
1730 cmd_buffer->queue_family_index))) {
1731 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1732 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1733 }
1734
1735 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1736 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1737
1738 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1739 /* Enable HTILE caching in L2 for small chips. */
1740 unsigned meta_write_policy, meta_read_policy;
1741 /* TODO: investigate whether LRU improves performance on other chips too */
1742 if (cmd_buffer->device->physical_device->rad_info.num_render_backends <= 4) {
1743 meta_write_policy = V_02807C_CACHE_LRU_WR; /* cache writes */
1744 meta_read_policy = V_02807C_CACHE_LRU_RD; /* cache reads */
1745 } else {
1746 meta_write_policy = V_02807C_CACHE_STREAM_WR; /* write combine */
1747 meta_read_policy = V_02807C_CACHE_NOA_RD; /* don't cache reads */
1748 }
1749
1750 bool zs_big_page = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10_3 &&
1751 (image->alignment % (64 * 1024) == 0);
1752
1753 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1754 radeon_set_context_reg(cmd_buffer->cs, R_02801C_DB_DEPTH_SIZE_XY, ds->db_depth_size);
1755
1756 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 7);
1757 radeon_emit(cmd_buffer->cs, S_02803C_RESOURCE_LEVEL(1));
1758 radeon_emit(cmd_buffer->cs, db_z_info);
1759 radeon_emit(cmd_buffer->cs, db_stencil_info);
1760 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1761 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1762 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1763 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1764
1765 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_READ_BASE_HI, 6);
1766 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1767 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1768 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1769 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1770 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1771 radeon_emit(cmd_buffer->cs,
1772 S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
1773 S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
1774 S_02807C_HTILE_WR_POLICY(meta_write_policy) |
1775 S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
1776 S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_RD) |
1777 S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_RD) |
1778 S_02807C_HTILE_RD_POLICY(meta_read_policy) |
1779 S_02807C_Z_BIG_PAGE(zs_big_page) |
1780 S_02807C_S_BIG_PAGE(zs_big_page));
1781 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1782 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1783 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1784 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1785 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1786
1787 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1788 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1789 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1790 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1791 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1792 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1793 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1794 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1795 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1796 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1797 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1798
1799 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1800 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1801 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1802 } else {
1803 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1804
1805 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1806 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1807 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1808 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1809 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1810 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1811 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1812 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1813 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1814 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1815
1816 }
1817
1818 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1819 radv_update_zrange_precision(cmd_buffer, ds, iview, layout,
1820 in_render_loop, true);
1821
1822 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1823 ds->pa_su_poly_offset_db_fmt_cntl);
1824 }
1825
1826 /**
1827 * Update the fast clear depth/stencil values if the image is bound as a
1828 * depth/stencil buffer.
1829 */
1830 static void
1831 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1832 const struct radv_image_view *iview,
1833 VkClearDepthStencilValue ds_clear_value,
1834 VkImageAspectFlags aspects)
1835 {
1836 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1837 const struct radv_image *image = iview->image;
1838 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1839 uint32_t att_idx;
1840
1841 if (!cmd_buffer->state.attachments || !subpass)
1842 return;
1843
1844 if (!subpass->depth_stencil_attachment)
1845 return;
1846
1847 att_idx = subpass->depth_stencil_attachment->attachment;
1848 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1849 return;
1850
1851 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1852 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1853 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1854 radeon_emit(cs, ds_clear_value.stencil);
1855 radeon_emit(cs, fui(ds_clear_value.depth));
1856 } else if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1857 radeon_set_context_reg_seq(cs, R_02802C_DB_DEPTH_CLEAR, 1);
1858 radeon_emit(cs, fui(ds_clear_value.depth));
1859 } else {
1860 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1861 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 1);
1862 radeon_emit(cs, ds_clear_value.stencil);
1863 }
1864
1865 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1866 * only needed when clearing Z to 0.0.
1867 */
1868 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1869 ds_clear_value.depth == 0.0) {
1870 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1871 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
1872
1873 radv_update_zrange_precision(cmd_buffer, &cmd_buffer->state.attachments[att_idx].ds,
1874 iview, layout, in_render_loop, false);
1875 }
1876
1877 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1878 }
1879
1880 /**
1881 * Set the clear depth/stencil values to the image's metadata.
1882 */
1883 static void
1884 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1885 struct radv_image *image,
1886 const VkImageSubresourceRange *range,
1887 VkClearDepthStencilValue ds_clear_value,
1888 VkImageAspectFlags aspects)
1889 {
1890 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1891 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel);
1892 uint32_t level_count = radv_get_levelCount(image, range);
1893
1894 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1895 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1896 /* Use the fastest way when both aspects are used. */
1897 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + 2 * level_count, cmd_buffer->state.predicating));
1898 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1899 S_370_WR_CONFIRM(1) |
1900 S_370_ENGINE_SEL(V_370_PFP));
1901 radeon_emit(cs, va);
1902 radeon_emit(cs, va >> 32);
1903
1904 for (uint32_t l = 0; l < level_count; l++) {
1905 radeon_emit(cs, ds_clear_value.stencil);
1906 radeon_emit(cs, fui(ds_clear_value.depth));
1907 }
1908 } else {
1909 /* Otherwise we need one WRITE_DATA packet per level. */
1910 for (uint32_t l = 0; l < level_count; l++) {
1911 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel + l);
1912 unsigned value;
1913
1914 if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1915 value = fui(ds_clear_value.depth);
1916 va += 4;
1917 } else {
1918 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1919 value = ds_clear_value.stencil;
1920 }
1921
1922 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1923 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1924 S_370_WR_CONFIRM(1) |
1925 S_370_ENGINE_SEL(V_370_PFP));
1926 radeon_emit(cs, va);
1927 radeon_emit(cs, va >> 32);
1928 radeon_emit(cs, value);
1929 }
1930 }
1931 }
1932
1933 /**
1934 * Update the TC-compat metadata value for this image.
1935 */
1936 static void
1937 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1938 struct radv_image *image,
1939 const VkImageSubresourceRange *range,
1940 uint32_t value)
1941 {
1942 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1943
1944 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug)
1945 return;
1946
1947 uint64_t va = radv_get_tc_compat_zrange_va(image, range->baseMipLevel);
1948 uint32_t level_count = radv_get_levelCount(image, range);
1949
1950 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + level_count, cmd_buffer->state.predicating));
1951 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1952 S_370_WR_CONFIRM(1) |
1953 S_370_ENGINE_SEL(V_370_PFP));
1954 radeon_emit(cs, va);
1955 radeon_emit(cs, va >> 32);
1956
1957 for (uint32_t l = 0; l < level_count; l++)
1958 radeon_emit(cs, value);
1959 }
1960
1961 static void
1962 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1963 const struct radv_image_view *iview,
1964 VkClearDepthStencilValue ds_clear_value)
1965 {
1966 VkImageSubresourceRange range = {
1967 .aspectMask = iview->aspect_mask,
1968 .baseMipLevel = iview->base_mip,
1969 .levelCount = iview->level_count,
1970 .baseArrayLayer = iview->base_layer,
1971 .layerCount = iview->layer_count,
1972 };
1973 uint32_t cond_val;
1974
1975 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1976 * depth clear value is 0.0f.
1977 */
1978 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1979
1980 radv_set_tc_compat_zrange_metadata(cmd_buffer, iview->image, &range,
1981 cond_val);
1982 }
1983
1984 /**
1985 * Update the clear depth/stencil values for this image.
1986 */
1987 void
1988 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1989 const struct radv_image_view *iview,
1990 VkClearDepthStencilValue ds_clear_value,
1991 VkImageAspectFlags aspects)
1992 {
1993 VkImageSubresourceRange range = {
1994 .aspectMask = iview->aspect_mask,
1995 .baseMipLevel = iview->base_mip,
1996 .levelCount = iview->level_count,
1997 .baseArrayLayer = iview->base_layer,
1998 .layerCount = iview->layer_count,
1999 };
2000 struct radv_image *image = iview->image;
2001
2002 assert(radv_image_has_htile(image));
2003
2004 radv_set_ds_clear_metadata(cmd_buffer, iview->image, &range,
2005 ds_clear_value, aspects);
2006
2007 if (radv_image_is_tc_compat_htile(image) &&
2008 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
2009 radv_update_tc_compat_zrange_metadata(cmd_buffer, iview,
2010 ds_clear_value);
2011 }
2012
2013 radv_update_bound_fast_clear_ds(cmd_buffer, iview, ds_clear_value,
2014 aspects);
2015 }
2016
2017 /**
2018 * Load the clear depth/stencil values from the image's metadata.
2019 */
2020 static void
2021 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
2022 const struct radv_image_view *iview)
2023 {
2024 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2025 const struct radv_image *image = iview->image;
2026 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
2027 uint64_t va = radv_get_ds_clear_value_va(image, iview->base_mip);
2028 unsigned reg_offset = 0, reg_count = 0;
2029
2030 if (!radv_image_has_htile(image))
2031 return;
2032
2033 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
2034 ++reg_count;
2035 } else {
2036 ++reg_offset;
2037 va += 4;
2038 }
2039 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
2040 ++reg_count;
2041
2042 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
2043
2044 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
2045 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG_INDEX, 3, 0));
2046 radeon_emit(cs, va);
2047 radeon_emit(cs, va >> 32);
2048 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
2049 radeon_emit(cs, reg_count);
2050 } else {
2051 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2052 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2053 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2054 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
2055 radeon_emit(cs, va);
2056 radeon_emit(cs, va >> 32);
2057 radeon_emit(cs, reg >> 2);
2058 radeon_emit(cs, 0);
2059
2060 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
2061 radeon_emit(cs, 0);
2062 }
2063 }
2064
2065 /*
2066 * With DCC some colors don't require CMASK elimination before being
2067 * used as a texture. This sets a predicate value to determine if the
2068 * cmask eliminate is required.
2069 */
2070 void
2071 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
2072 struct radv_image *image,
2073 const VkImageSubresourceRange *range, bool value)
2074 {
2075 uint64_t pred_val = value;
2076 uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
2077 uint32_t level_count = radv_get_levelCount(image, range);
2078 uint32_t count = 2 * level_count;
2079
2080 assert(radv_dcc_enabled(image, range->baseMipLevel));
2081
2082 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
2083 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
2084 S_370_WR_CONFIRM(1) |
2085 S_370_ENGINE_SEL(V_370_PFP));
2086 radeon_emit(cmd_buffer->cs, va);
2087 radeon_emit(cmd_buffer->cs, va >> 32);
2088
2089 for (uint32_t l = 0; l < level_count; l++) {
2090 radeon_emit(cmd_buffer->cs, pred_val);
2091 radeon_emit(cmd_buffer->cs, pred_val >> 32);
2092 }
2093 }
2094
2095 /**
2096 * Update the DCC predicate to reflect the compression state.
2097 */
2098 void
2099 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
2100 struct radv_image *image,
2101 const VkImageSubresourceRange *range, bool value)
2102 {
2103 uint64_t pred_val = value;
2104 uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
2105 uint32_t level_count = radv_get_levelCount(image, range);
2106 uint32_t count = 2 * level_count;
2107
2108 assert(radv_dcc_enabled(image, range->baseMipLevel));
2109
2110 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
2111 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
2112 S_370_WR_CONFIRM(1) |
2113 S_370_ENGINE_SEL(V_370_PFP));
2114 radeon_emit(cmd_buffer->cs, va);
2115 radeon_emit(cmd_buffer->cs, va >> 32);
2116
2117 for (uint32_t l = 0; l < level_count; l++) {
2118 radeon_emit(cmd_buffer->cs, pred_val);
2119 radeon_emit(cmd_buffer->cs, pred_val >> 32);
2120 }
2121 }
2122
2123 /**
2124 * Update the fast clear color values if the image is bound as a color buffer.
2125 */
2126 static void
2127 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
2128 struct radv_image *image,
2129 int cb_idx,
2130 uint32_t color_values[2])
2131 {
2132 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2133 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2134 uint32_t att_idx;
2135
2136 if (!cmd_buffer->state.attachments || !subpass)
2137 return;
2138
2139 att_idx = subpass->color_attachments[cb_idx].attachment;
2140 if (att_idx == VK_ATTACHMENT_UNUSED)
2141 return;
2142
2143 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
2144 return;
2145
2146 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
2147 radeon_emit(cs, color_values[0]);
2148 radeon_emit(cs, color_values[1]);
2149
2150 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2151 }
2152
2153 /**
2154 * Set the clear color values to the image's metadata.
2155 */
2156 static void
2157 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
2158 struct radv_image *image,
2159 const VkImageSubresourceRange *range,
2160 uint32_t color_values[2])
2161 {
2162 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2163 uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
2164 uint32_t level_count = radv_get_levelCount(image, range);
2165 uint32_t count = 2 * level_count;
2166
2167 assert(radv_image_has_cmask(image) ||
2168 radv_dcc_enabled(image, range->baseMipLevel));
2169
2170 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
2171 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
2172 S_370_WR_CONFIRM(1) |
2173 S_370_ENGINE_SEL(V_370_PFP));
2174 radeon_emit(cs, va);
2175 radeon_emit(cs, va >> 32);
2176
2177 for (uint32_t l = 0; l < level_count; l++) {
2178 radeon_emit(cs, color_values[0]);
2179 radeon_emit(cs, color_values[1]);
2180 }
2181 }
2182
2183 /**
2184 * Update the clear color values for this image.
2185 */
2186 void
2187 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
2188 const struct radv_image_view *iview,
2189 int cb_idx,
2190 uint32_t color_values[2])
2191 {
2192 struct radv_image *image = iview->image;
2193 VkImageSubresourceRange range = {
2194 .aspectMask = iview->aspect_mask,
2195 .baseMipLevel = iview->base_mip,
2196 .levelCount = iview->level_count,
2197 .baseArrayLayer = iview->base_layer,
2198 .layerCount = iview->layer_count,
2199 };
2200
2201 assert(radv_image_has_cmask(image) ||
2202 radv_dcc_enabled(image, iview->base_mip));
2203
2204 radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
2205
2206 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
2207 color_values);
2208 }
2209
2210 /**
2211 * Load the clear color values from the image's metadata.
2212 */
2213 static void
2214 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
2215 struct radv_image_view *iview,
2216 int cb_idx)
2217 {
2218 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2219 struct radv_image *image = iview->image;
2220 uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
2221
2222 if (!radv_image_has_cmask(image) &&
2223 !radv_dcc_enabled(image, iview->base_mip))
2224 return;
2225
2226 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
2227
2228 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
2229 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG_INDEX, 3, cmd_buffer->state.predicating));
2230 radeon_emit(cs, va);
2231 radeon_emit(cs, va >> 32);
2232 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
2233 radeon_emit(cs, 2);
2234 } else {
2235 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
2236 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2237 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2238 COPY_DATA_COUNT_SEL);
2239 radeon_emit(cs, va);
2240 radeon_emit(cs, va >> 32);
2241 radeon_emit(cs, reg >> 2);
2242 radeon_emit(cs, 0);
2243
2244 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
2245 radeon_emit(cs, 0);
2246 }
2247 }
2248
2249 static void
2250 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
2251 {
2252 int i;
2253 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
2254 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2255 bool color_big_page = true;
2256
2257 /* this may happen for inherited secondary recording */
2258 if (!framebuffer)
2259 return;
2260
2261 for (i = 0; i < 8; ++i) {
2262 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
2263 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2264 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2265 continue;
2266 }
2267
2268 int idx = subpass->color_attachments[i].attachment;
2269 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
2270 VkImageLayout layout = subpass->color_attachments[i].layout;
2271 bool in_render_loop = subpass->color_attachments[i].in_render_loop;
2272
2273 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, iview->bo);
2274
2275 assert(iview->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
2276 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
2277 radv_emit_fb_color_state(cmd_buffer, i, &cmd_buffer->state.attachments[idx].cb, iview, layout, in_render_loop);
2278
2279 radv_load_color_clear_metadata(cmd_buffer, iview, i);
2280
2281 /* BIG_PAGE is an optimization that can only be enabled if all
2282 * color targets are compatible.
2283 */
2284 color_big_page &= cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10_3 &&
2285 (iview->image->alignment % (64 * 1024) == 0);
2286 }
2287
2288 if (subpass->depth_stencil_attachment) {
2289 int idx = subpass->depth_stencil_attachment->attachment;
2290 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
2291 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
2292 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
2293 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, cmd_buffer->state.attachments[idx].iview->bo);
2294
2295 radv_emit_fb_ds_state(cmd_buffer, &cmd_buffer->state.attachments[idx].ds, iview, layout, in_render_loop);
2296
2297 if (cmd_buffer->state.attachments[idx].ds.offset_scale != cmd_buffer->state.offset_scale) {
2298 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2299 cmd_buffer->state.offset_scale = cmd_buffer->state.attachments[idx].ds.offset_scale;
2300 }
2301 radv_load_ds_clear_metadata(cmd_buffer, iview);
2302 } else {
2303 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9)
2304 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
2305 else
2306 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
2307
2308 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
2309 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
2310 }
2311 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2312 S_028208_BR_X(framebuffer->width) |
2313 S_028208_BR_Y(framebuffer->height));
2314
2315 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
2316 bool disable_constant_encode =
2317 cmd_buffer->device->physical_device->rad_info.has_dcc_constant_encode;
2318 enum chip_class chip_class =
2319 cmd_buffer->device->physical_device->rad_info.chip_class;
2320 uint8_t watermark = chip_class >= GFX10 ? 6 : 4;
2321
2322 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
2323 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class <= GFX9) |
2324 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
2325 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
2326 }
2327
2328 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2329 /* Enable CMASK/FMASK/DCC caching in L2 for small chips. */
2330 unsigned meta_write_policy, meta_read_policy;
2331 /* TODO: investigate whether LRU improves performance on other chips too */
2332 if (cmd_buffer->device->physical_device->rad_info.num_render_backends <= 4) {
2333 meta_write_policy = V_02807C_CACHE_LRU_WR; /* cache writes */
2334 meta_read_policy = V_02807C_CACHE_LRU_RD; /* cache reads */
2335 } else {
2336 meta_write_policy = V_02807C_CACHE_STREAM_WR; /* write combine */
2337 meta_read_policy = V_02807C_CACHE_NOA_RD; /* don't cache reads */
2338 }
2339
2340 radeon_set_context_reg(cmd_buffer->cs, R_028410_CB_RMI_GL2_CACHE_CONTROL,
2341 S_028410_CMASK_WR_POLICY(meta_write_policy) |
2342 S_028410_FMASK_WR_POLICY(meta_write_policy) |
2343 S_028410_DCC_WR_POLICY(meta_write_policy) |
2344 S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM_WR) |
2345 S_028410_CMASK_RD_POLICY(meta_read_policy) |
2346 S_028410_FMASK_RD_POLICY(meta_read_policy) |
2347 S_028410_DCC_RD_POLICY(meta_read_policy) |
2348 S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD) |
2349 S_028410_FMASK_BIG_PAGE(color_big_page) |
2350 S_028410_COLOR_BIG_PAGE(color_big_page));
2351 }
2352
2353 if (cmd_buffer->device->dfsm_allowed) {
2354 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2355 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
2356 }
2357
2358 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
2359 }
2360
2361 static void
2362 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer, bool indirect)
2363 {
2364 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2365 struct radv_cmd_state *state = &cmd_buffer->state;
2366
2367 if (state->index_type != state->last_index_type) {
2368 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2369 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2370 cs, R_03090C_VGT_INDEX_TYPE,
2371 2, state->index_type);
2372 } else {
2373 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2374 radeon_emit(cs, state->index_type);
2375 }
2376
2377 state->last_index_type = state->index_type;
2378 }
2379
2380 /* For the direct indexed draws we use DRAW_INDEX_2, which includes
2381 * the index_va and max_index_count already. */
2382 if (!indirect)
2383 return;
2384
2385 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2386 radeon_emit(cs, state->index_va);
2387 radeon_emit(cs, state->index_va >> 32);
2388
2389 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2390 radeon_emit(cs, state->max_index_count);
2391
2392 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
2393 }
2394
2395 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
2396 {
2397 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
2398 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2399 uint32_t pa_sc_mode_cntl_1 =
2400 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
2401 uint32_t db_count_control;
2402
2403 if(!cmd_buffer->state.active_occlusion_queries) {
2404 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2405 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2406 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2407 has_perfect_queries) {
2408 /* Re-enable out-of-order rasterization if the
2409 * bound pipeline supports it and if it's has
2410 * been disabled before starting any perfect
2411 * occlusion queries.
2412 */
2413 radeon_set_context_reg(cmd_buffer->cs,
2414 R_028A4C_PA_SC_MODE_CNTL_1,
2415 pa_sc_mode_cntl_1);
2416 }
2417 }
2418 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
2419 } else {
2420 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2421 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
2422 bool gfx10_perfect = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10 && has_perfect_queries;
2423
2424 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2425 /* Always enable PERFECT_ZPASS_COUNTS due to issues with partially
2426 * covered tiles, discards, and early depth testing. For more details,
2427 * see https://gitlab.freedesktop.org/mesa/mesa/-/issues/3218 */
2428 db_count_control =
2429 S_028004_PERFECT_ZPASS_COUNTS(1) |
2430 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
2431 S_028004_SAMPLE_RATE(sample_rate) |
2432 S_028004_ZPASS_ENABLE(1) |
2433 S_028004_SLICE_EVEN_ENABLE(1) |
2434 S_028004_SLICE_ODD_ENABLE(1);
2435
2436 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2437 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2438 has_perfect_queries) {
2439 /* If the bound pipeline has enabled
2440 * out-of-order rasterization, we should
2441 * disable it before starting any perfect
2442 * occlusion queries.
2443 */
2444 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
2445
2446 radeon_set_context_reg(cmd_buffer->cs,
2447 R_028A4C_PA_SC_MODE_CNTL_1,
2448 pa_sc_mode_cntl_1);
2449 }
2450 } else {
2451 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
2452 S_028004_SAMPLE_RATE(sample_rate);
2453 }
2454 }
2455
2456 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
2457
2458 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2459 }
2460
2461 static void
2462 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
2463 {
2464 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
2465
2466 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
2467 radv_emit_viewport(cmd_buffer);
2468
2469 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
2470 !cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
2471 radv_emit_scissor(cmd_buffer);
2472
2473 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
2474 radv_emit_line_width(cmd_buffer);
2475
2476 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
2477 radv_emit_blend_constants(cmd_buffer);
2478
2479 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
2480 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
2481 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
2482 radv_emit_stencil(cmd_buffer);
2483
2484 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
2485 radv_emit_depth_bounds(cmd_buffer);
2486
2487 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
2488 radv_emit_depth_bias(cmd_buffer);
2489
2490 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
2491 radv_emit_discard_rectangle(cmd_buffer);
2492
2493 if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)
2494 radv_emit_sample_locations(cmd_buffer);
2495
2496 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE)
2497 radv_emit_line_stipple(cmd_buffer);
2498
2499 if (states & (RADV_CMD_DIRTY_DYNAMIC_CULL_MODE |
2500 RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE))
2501 radv_emit_culling(cmd_buffer, states);
2502
2503 if (states & RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY)
2504 radv_emit_primitive_topology(cmd_buffer);
2505
2506 if (states & (RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE |
2507 RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE |
2508 RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP |
2509 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE |
2510 RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE |
2511 RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP))
2512 radv_emit_depth_control(cmd_buffer, states);
2513
2514 if (states & RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP)
2515 radv_emit_stencil_control(cmd_buffer);
2516
2517 cmd_buffer->state.dirty &= ~states;
2518 }
2519
2520 static void
2521 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
2522 VkPipelineBindPoint bind_point)
2523 {
2524 struct radv_descriptor_state *descriptors_state =
2525 radv_get_descriptors_state(cmd_buffer, bind_point);
2526 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
2527 unsigned bo_offset;
2528
2529 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
2530 set->mapped_ptr,
2531 &bo_offset))
2532 return;
2533
2534 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2535 set->va += bo_offset;
2536 }
2537
2538 static void
2539 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
2540 VkPipelineBindPoint bind_point)
2541 {
2542 struct radv_descriptor_state *descriptors_state =
2543 radv_get_descriptors_state(cmd_buffer, bind_point);
2544 uint32_t size = MAX_SETS * 4;
2545 uint32_t offset;
2546 void *ptr;
2547
2548 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
2549 256, &offset, &ptr))
2550 return;
2551
2552 for (unsigned i = 0; i < MAX_SETS; i++) {
2553 uint32_t *uptr = ((uint32_t *)ptr) + i;
2554 uint64_t set_va = 0;
2555 struct radv_descriptor_set *set = descriptors_state->sets[i];
2556 if (descriptors_state->valid & (1u << i))
2557 set_va = set->va;
2558 uptr[0] = set_va & 0xffffffff;
2559 }
2560
2561 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2562 va += offset;
2563
2564 if (cmd_buffer->state.pipeline) {
2565 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
2566 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2567 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2568
2569 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
2570 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
2571 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2572
2573 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
2574 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2575 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2576
2577 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2578 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
2579 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2580
2581 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2582 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
2583 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2584 }
2585
2586 if (cmd_buffer->state.compute_pipeline)
2587 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
2588 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2589 }
2590
2591 static void
2592 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
2593 VkShaderStageFlags stages)
2594 {
2595 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2596 VK_PIPELINE_BIND_POINT_COMPUTE :
2597 VK_PIPELINE_BIND_POINT_GRAPHICS;
2598 struct radv_descriptor_state *descriptors_state =
2599 radv_get_descriptors_state(cmd_buffer, bind_point);
2600 struct radv_cmd_state *state = &cmd_buffer->state;
2601 bool flush_indirect_descriptors;
2602
2603 if (!descriptors_state->dirty)
2604 return;
2605
2606 if (descriptors_state->push_dirty)
2607 radv_flush_push_descriptors(cmd_buffer, bind_point);
2608
2609 flush_indirect_descriptors =
2610 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
2611 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
2612 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
2613 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
2614
2615 if (flush_indirect_descriptors)
2616 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
2617
2618 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2619 cmd_buffer->cs,
2620 MAX_SETS * MESA_SHADER_STAGES * 4);
2621
2622 if (cmd_buffer->state.pipeline) {
2623 radv_foreach_stage(stage, stages) {
2624 if (!cmd_buffer->state.pipeline->shaders[stage])
2625 continue;
2626
2627 radv_emit_descriptor_pointers(cmd_buffer,
2628 cmd_buffer->state.pipeline,
2629 descriptors_state, stage);
2630 }
2631 }
2632
2633 if (cmd_buffer->state.compute_pipeline &&
2634 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
2635 radv_emit_descriptor_pointers(cmd_buffer,
2636 cmd_buffer->state.compute_pipeline,
2637 descriptors_state,
2638 MESA_SHADER_COMPUTE);
2639 }
2640
2641 descriptors_state->dirty = 0;
2642 descriptors_state->push_dirty = false;
2643
2644 assert(cmd_buffer->cs->cdw <= cdw_max);
2645
2646 if (unlikely(cmd_buffer->device->trace_bo))
2647 radv_save_descriptors(cmd_buffer, bind_point);
2648 }
2649
2650 static void
2651 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
2652 VkShaderStageFlags stages)
2653 {
2654 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
2655 ? cmd_buffer->state.compute_pipeline
2656 : cmd_buffer->state.pipeline;
2657 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2658 VK_PIPELINE_BIND_POINT_COMPUTE :
2659 VK_PIPELINE_BIND_POINT_GRAPHICS;
2660 struct radv_descriptor_state *descriptors_state =
2661 radv_get_descriptors_state(cmd_buffer, bind_point);
2662 struct radv_pipeline_layout *layout = pipeline->layout;
2663 struct radv_shader_variant *shader, *prev_shader;
2664 bool need_push_constants = false;
2665 unsigned offset;
2666 void *ptr;
2667 uint64_t va;
2668
2669 stages &= cmd_buffer->push_constant_stages;
2670 if (!stages ||
2671 (!layout->push_constant_size && !layout->dynamic_offset_count))
2672 return;
2673
2674 radv_foreach_stage(stage, stages) {
2675 shader = radv_get_shader(pipeline, stage);
2676 if (!shader)
2677 continue;
2678
2679 need_push_constants |= shader->info.loads_push_constants;
2680 need_push_constants |= shader->info.loads_dynamic_offsets;
2681
2682 uint8_t base = shader->info.base_inline_push_consts;
2683 uint8_t count = shader->info.num_inline_push_consts;
2684
2685 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
2686 AC_UD_INLINE_PUSH_CONSTANTS,
2687 count,
2688 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
2689 }
2690
2691 if (need_push_constants) {
2692 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
2693 16 * layout->dynamic_offset_count,
2694 256, &offset, &ptr))
2695 return;
2696
2697 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
2698 memcpy((char*)ptr + layout->push_constant_size,
2699 descriptors_state->dynamic_buffers,
2700 16 * layout->dynamic_offset_count);
2701
2702 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2703 va += offset;
2704
2705 ASSERTED unsigned cdw_max =
2706 radeon_check_space(cmd_buffer->device->ws,
2707 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
2708
2709 prev_shader = NULL;
2710 radv_foreach_stage(stage, stages) {
2711 shader = radv_get_shader(pipeline, stage);
2712
2713 /* Avoid redundantly emitting the address for merged stages. */
2714 if (shader && shader != prev_shader) {
2715 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
2716 AC_UD_PUSH_CONSTANTS, va);
2717
2718 prev_shader = shader;
2719 }
2720 }
2721 assert(cmd_buffer->cs->cdw <= cdw_max);
2722 }
2723
2724 cmd_buffer->push_constant_stages &= ~stages;
2725 }
2726
2727 static void
2728 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
2729 bool pipeline_is_dirty)
2730 {
2731 if ((pipeline_is_dirty ||
2732 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
2733 cmd_buffer->state.pipeline->num_vertex_bindings &&
2734 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.has_vertex_buffers) {
2735 unsigned vb_offset;
2736 void *vb_ptr;
2737 uint32_t i = 0;
2738 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
2739 uint64_t va;
2740
2741 /* allocate some descriptor state for vertex buffers */
2742 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2743 &vb_offset, &vb_ptr))
2744 return;
2745
2746 for (i = 0; i < count; i++) {
2747 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2748 uint32_t offset;
2749 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2750 unsigned num_records;
2751 unsigned stride;
2752
2753 if (!buffer)
2754 continue;
2755
2756 va = radv_buffer_get_va(buffer->bo);
2757
2758 offset = cmd_buffer->vertex_bindings[i].offset;
2759 va += offset + buffer->offset;
2760
2761 if (cmd_buffer->vertex_bindings[i].size) {
2762 num_records = cmd_buffer->vertex_bindings[i].size;
2763 } else {
2764 num_records = buffer->size - offset;
2765 }
2766
2767 if (cmd_buffer->state.pipeline->graphics.uses_dynamic_stride) {
2768 stride = cmd_buffer->vertex_bindings[i].stride;
2769 } else {
2770 stride = cmd_buffer->state.pipeline->binding_stride[i];
2771 }
2772
2773 if (cmd_buffer->device->physical_device->rad_info.chip_class != GFX8 && stride)
2774 num_records /= stride;
2775
2776 uint32_t rsrc_word3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2777 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2778 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2779 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2780
2781 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2782 /* OOB_SELECT chooses the out-of-bounds check:
2783 * - 1: index >= NUM_RECORDS (Structured)
2784 * - 3: offset >= NUM_RECORDS (Raw)
2785 */
2786 int oob_select = stride ? V_008F0C_OOB_SELECT_STRUCTURED : V_008F0C_OOB_SELECT_RAW;
2787
2788 rsrc_word3 |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT) |
2789 S_008F0C_OOB_SELECT(oob_select) |
2790 S_008F0C_RESOURCE_LEVEL(1);
2791 } else {
2792 rsrc_word3 |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2793 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2794 }
2795
2796 desc[0] = va;
2797 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2798 desc[2] = num_records;
2799 desc[3] = rsrc_word3;
2800 }
2801
2802 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2803 va += vb_offset;
2804
2805 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2806 AC_UD_VS_VERTEX_BUFFERS, va);
2807
2808 cmd_buffer->state.vb_va = va;
2809 cmd_buffer->state.vb_size = count * 16;
2810 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2811 }
2812 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2813 }
2814
2815 static void
2816 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2817 {
2818 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2819 struct radv_userdata_info *loc;
2820 uint32_t base_reg;
2821
2822 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2823 if (!radv_get_shader(pipeline, stage))
2824 continue;
2825
2826 loc = radv_lookup_user_sgpr(pipeline, stage,
2827 AC_UD_STREAMOUT_BUFFERS);
2828 if (loc->sgpr_idx == -1)
2829 continue;
2830
2831 base_reg = pipeline->user_data_0[stage];
2832
2833 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2834 base_reg + loc->sgpr_idx * 4, va, false);
2835 }
2836
2837 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
2838 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2839 if (loc->sgpr_idx != -1) {
2840 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2841
2842 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2843 base_reg + loc->sgpr_idx * 4, va, false);
2844 }
2845 }
2846 }
2847
2848 static void
2849 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2850 {
2851 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2852 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2853 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2854 unsigned so_offset;
2855 void *so_ptr;
2856 uint64_t va;
2857
2858 /* Allocate some descriptor state for streamout buffers. */
2859 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2860 MAX_SO_BUFFERS * 16, 256,
2861 &so_offset, &so_ptr))
2862 return;
2863
2864 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2865 struct radv_buffer *buffer = sb[i].buffer;
2866 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2867
2868 if (!(so->enabled_mask & (1 << i)))
2869 continue;
2870
2871 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2872
2873 va += sb[i].offset;
2874
2875 /* Set the descriptor.
2876 *
2877 * On GFX8, the format must be non-INVALID, otherwise
2878 * the buffer will be considered not bound and store
2879 * instructions will be no-ops.
2880 */
2881 uint32_t size = 0xffffffff;
2882
2883 /* Compute the correct buffer size for NGG streamout
2884 * because it's used to determine the max emit per
2885 * buffer.
2886 */
2887 if (cmd_buffer->device->physical_device->use_ngg_streamout)
2888 size = buffer->size - sb[i].offset;
2889
2890 uint32_t rsrc_word3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2891 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2892 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2893 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2894
2895 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2896 rsrc_word3 |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2897 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
2898 S_008F0C_RESOURCE_LEVEL(1);
2899 } else {
2900 rsrc_word3 |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2901 }
2902
2903 desc[0] = va;
2904 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2905 desc[2] = size;
2906 desc[3] = rsrc_word3;
2907 }
2908
2909 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2910 va += so_offset;
2911
2912 radv_emit_streamout_buffers(cmd_buffer, va);
2913 }
2914
2915 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2916 }
2917
2918 static void
2919 radv_flush_ngg_gs_state(struct radv_cmd_buffer *cmd_buffer)
2920 {
2921 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2922 struct radv_userdata_info *loc;
2923 uint32_t ngg_gs_state = 0;
2924 uint32_t base_reg;
2925
2926 if (!radv_pipeline_has_gs(pipeline) ||
2927 !radv_pipeline_has_ngg(pipeline))
2928 return;
2929
2930 /* By default NGG GS queries are disabled but they are enabled if the
2931 * command buffer has active GDS queries or if it's a secondary command
2932 * buffer that inherits the number of generated primitives.
2933 */
2934 if (cmd_buffer->state.active_pipeline_gds_queries ||
2935 (cmd_buffer->state.inherited_pipeline_statistics & VK_QUERY_PIPELINE_STATISTIC_GEOMETRY_SHADER_PRIMITIVES_BIT))
2936 ngg_gs_state = 1;
2937
2938 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_GEOMETRY,
2939 AC_UD_NGG_GS_STATE);
2940 base_reg = pipeline->user_data_0[MESA_SHADER_GEOMETRY];
2941 assert(loc->sgpr_idx != -1);
2942
2943 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
2944 ngg_gs_state);
2945 }
2946
2947 static void
2948 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2949 {
2950 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2951 radv_flush_streamout_descriptors(cmd_buffer);
2952 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2953 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2954 radv_flush_ngg_gs_state(cmd_buffer);
2955 }
2956
2957 struct radv_draw_info {
2958 /**
2959 * Number of vertices.
2960 */
2961 uint32_t count;
2962
2963 /**
2964 * Index of the first vertex.
2965 */
2966 int32_t vertex_offset;
2967
2968 /**
2969 * First instance id.
2970 */
2971 uint32_t first_instance;
2972
2973 /**
2974 * Number of instances.
2975 */
2976 uint32_t instance_count;
2977
2978 /**
2979 * First index (indexed draws only).
2980 */
2981 uint32_t first_index;
2982
2983 /**
2984 * Whether it's an indexed draw.
2985 */
2986 bool indexed;
2987
2988 /**
2989 * Indirect draw parameters resource.
2990 */
2991 struct radv_buffer *indirect;
2992 uint64_t indirect_offset;
2993 uint32_t stride;
2994
2995 /**
2996 * Draw count parameters resource.
2997 */
2998 struct radv_buffer *count_buffer;
2999 uint64_t count_buffer_offset;
3000
3001 /**
3002 * Stream output parameters resource.
3003 */
3004 struct radv_buffer *strmout_buffer;
3005 uint64_t strmout_buffer_offset;
3006 };
3007
3008 static uint32_t
3009 radv_get_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
3010 {
3011 switch (cmd_buffer->state.index_type) {
3012 case V_028A7C_VGT_INDEX_8:
3013 return 0xffu;
3014 case V_028A7C_VGT_INDEX_16:
3015 return 0xffffu;
3016 case V_028A7C_VGT_INDEX_32:
3017 return 0xffffffffu;
3018 default:
3019 unreachable("invalid index type");
3020 }
3021 }
3022
3023 static void
3024 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
3025 bool instanced_draw, bool indirect_draw,
3026 bool count_from_stream_output,
3027 uint32_t draw_vertex_count)
3028 {
3029 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
3030 struct radv_cmd_state *state = &cmd_buffer->state;
3031 unsigned topology = state->dynamic.primitive_topology;
3032 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3033 unsigned ia_multi_vgt_param;
3034
3035 ia_multi_vgt_param =
3036 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
3037 indirect_draw,
3038 count_from_stream_output,
3039 draw_vertex_count,
3040 topology);
3041
3042 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
3043 if (info->chip_class == GFX9) {
3044 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
3045 cs,
3046 R_030960_IA_MULTI_VGT_PARAM,
3047 4, ia_multi_vgt_param);
3048 } else if (info->chip_class >= GFX7) {
3049 radeon_set_context_reg_idx(cs,
3050 R_028AA8_IA_MULTI_VGT_PARAM,
3051 1, ia_multi_vgt_param);
3052 } else {
3053 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
3054 ia_multi_vgt_param);
3055 }
3056 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
3057 }
3058 }
3059
3060 static void
3061 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
3062 const struct radv_draw_info *draw_info)
3063 {
3064 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
3065 struct radv_cmd_state *state = &cmd_buffer->state;
3066 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3067 int32_t primitive_reset_en;
3068
3069 /* Draw state. */
3070 if (info->chip_class < GFX10) {
3071 si_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
3072 draw_info->indirect,
3073 !!draw_info->strmout_buffer,
3074 draw_info->indirect ? 0 : draw_info->count);
3075 }
3076
3077 /* Primitive restart. */
3078 primitive_reset_en =
3079 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
3080
3081 if (primitive_reset_en != state->last_primitive_reset_en) {
3082 state->last_primitive_reset_en = primitive_reset_en;
3083 if (info->chip_class >= GFX9) {
3084 radeon_set_uconfig_reg(cs,
3085 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
3086 primitive_reset_en);
3087 } else {
3088 radeon_set_context_reg(cs,
3089 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
3090 primitive_reset_en);
3091 }
3092 }
3093
3094 if (primitive_reset_en) {
3095 uint32_t primitive_reset_index =
3096 radv_get_primitive_reset_index(cmd_buffer);
3097
3098 if (primitive_reset_index != state->last_primitive_reset_index) {
3099 radeon_set_context_reg(cs,
3100 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
3101 primitive_reset_index);
3102 state->last_primitive_reset_index = primitive_reset_index;
3103 }
3104 }
3105
3106 if (draw_info->strmout_buffer) {
3107 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
3108
3109 va += draw_info->strmout_buffer->offset +
3110 draw_info->strmout_buffer_offset;
3111
3112 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
3113 draw_info->stride);
3114
3115 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3116 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
3117 COPY_DATA_DST_SEL(COPY_DATA_REG) |
3118 COPY_DATA_WR_CONFIRM);
3119 radeon_emit(cs, va);
3120 radeon_emit(cs, va >> 32);
3121 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
3122 radeon_emit(cs, 0); /* unused */
3123
3124 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
3125 }
3126 }
3127
3128 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
3129 VkPipelineStageFlags src_stage_mask)
3130 {
3131 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
3132 VK_PIPELINE_STAGE_TRANSFER_BIT |
3133 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
3134 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
3135 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
3136 }
3137
3138 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
3139 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
3140 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
3141 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
3142 VK_PIPELINE_STAGE_TRANSFER_BIT |
3143 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
3144 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
3145 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
3146 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
3147 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
3148 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
3149 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
3150 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
3151 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
3152 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
3153 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
3154 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
3155 }
3156 }
3157
3158 static enum radv_cmd_flush_bits
3159 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
3160 VkAccessFlags src_flags,
3161 struct radv_image *image)
3162 {
3163 bool flush_CB_meta = true, flush_DB_meta = true;
3164 enum radv_cmd_flush_bits flush_bits = 0;
3165 uint32_t b;
3166
3167 if (image) {
3168 if (!radv_image_has_CB_metadata(image))
3169 flush_CB_meta = false;
3170 if (!radv_image_has_htile(image))
3171 flush_DB_meta = false;
3172 }
3173
3174 for_each_bit(b, src_flags) {
3175 switch ((VkAccessFlagBits)(1 << b)) {
3176 case VK_ACCESS_SHADER_WRITE_BIT:
3177 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
3178 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
3179 flush_bits |= RADV_CMD_FLAG_WB_L2;
3180 break;
3181 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
3182 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
3183 if (flush_CB_meta)
3184 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3185 break;
3186 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
3187 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
3188 if (flush_DB_meta)
3189 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3190 break;
3191 case VK_ACCESS_TRANSFER_WRITE_BIT:
3192 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3193 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3194 RADV_CMD_FLAG_INV_L2;
3195
3196 if (flush_CB_meta)
3197 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3198 if (flush_DB_meta)
3199 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3200 break;
3201 case VK_ACCESS_MEMORY_WRITE_BIT:
3202 flush_bits |= RADV_CMD_FLAG_INV_L2 |
3203 RADV_CMD_FLAG_WB_L2 |
3204 RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3205 RADV_CMD_FLAG_FLUSH_AND_INV_DB;
3206
3207 if (flush_CB_meta)
3208 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3209 if (flush_DB_meta)
3210 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3211 break;
3212 default:
3213 break;
3214 }
3215 }
3216 return flush_bits;
3217 }
3218
3219 static enum radv_cmd_flush_bits
3220 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
3221 VkAccessFlags dst_flags,
3222 struct radv_image *image)
3223 {
3224 bool flush_CB_meta = true, flush_DB_meta = true;
3225 enum radv_cmd_flush_bits flush_bits = 0;
3226 bool flush_CB = true, flush_DB = true;
3227 bool image_is_coherent = false;
3228 uint32_t b;
3229
3230 if (image) {
3231 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
3232 flush_CB = false;
3233 flush_DB = false;
3234 }
3235
3236 if (!radv_image_has_CB_metadata(image))
3237 flush_CB_meta = false;
3238 if (!radv_image_has_htile(image))
3239 flush_DB_meta = false;
3240
3241 /* TODO: implement shader coherent for GFX10 */
3242
3243 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
3244 if (image->info.samples == 1 &&
3245 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
3246 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
3247 !vk_format_is_stencil(image->vk_format)) {
3248 /* Single-sample color and single-sample depth
3249 * (not stencil) are coherent with shaders on
3250 * GFX9.
3251 */
3252 image_is_coherent = true;
3253 }
3254 }
3255 }
3256
3257 for_each_bit(b, dst_flags) {
3258 switch ((VkAccessFlagBits)(1 << b)) {
3259 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
3260 case VK_ACCESS_INDEX_READ_BIT:
3261 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
3262 break;
3263 case VK_ACCESS_UNIFORM_READ_BIT:
3264 flush_bits |= RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_SCACHE;
3265 break;
3266 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
3267 case VK_ACCESS_TRANSFER_READ_BIT:
3268 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
3269 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
3270 RADV_CMD_FLAG_INV_L2;
3271 break;
3272 case VK_ACCESS_SHADER_READ_BIT:
3273 flush_bits |= RADV_CMD_FLAG_INV_VCACHE;
3274 /* Unlike LLVM, ACO uses SMEM for SSBOs and we have to
3275 * invalidate the scalar cache. */
3276 if (!cmd_buffer->device->physical_device->use_llvm)
3277 flush_bits |= RADV_CMD_FLAG_INV_SCACHE;
3278
3279 if (!image_is_coherent)
3280 flush_bits |= RADV_CMD_FLAG_INV_L2;
3281 break;
3282 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
3283 if (flush_CB)
3284 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
3285 if (flush_CB_meta)
3286 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3287 break;
3288 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
3289 if (flush_DB)
3290 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
3291 if (flush_DB_meta)
3292 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3293 break;
3294 case VK_ACCESS_MEMORY_READ_BIT:
3295 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
3296 RADV_CMD_FLAG_INV_SCACHE |
3297 RADV_CMD_FLAG_INV_L2;
3298 if (flush_CB)
3299 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
3300 if (flush_CB_meta)
3301 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3302 if (flush_DB)
3303 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
3304 if (flush_DB_meta)
3305 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3306 break;
3307 default:
3308 break;
3309 }
3310 }
3311 return flush_bits;
3312 }
3313
3314 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
3315 const struct radv_subpass_barrier *barrier)
3316 {
3317 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
3318 NULL);
3319 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
3320 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
3321 NULL);
3322 }
3323
3324 uint32_t
3325 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
3326 {
3327 struct radv_cmd_state *state = &cmd_buffer->state;
3328 uint32_t subpass_id = state->subpass - state->pass->subpasses;
3329
3330 /* The id of this subpass shouldn't exceed the number of subpasses in
3331 * this render pass minus 1.
3332 */
3333 assert(subpass_id < state->pass->subpass_count);
3334 return subpass_id;
3335 }
3336
3337 static struct radv_sample_locations_state *
3338 radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer,
3339 uint32_t att_idx,
3340 bool begin_subpass)
3341 {
3342 struct radv_cmd_state *state = &cmd_buffer->state;
3343 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
3344 struct radv_image_view *view = state->attachments[att_idx].iview;
3345
3346 if (view->image->info.samples == 1)
3347 return NULL;
3348
3349 if (state->pass->attachments[att_idx].first_subpass_idx == subpass_id) {
3350 /* Return the initial sample locations if this is the initial
3351 * layout transition of the given subpass attachemnt.
3352 */
3353 if (state->attachments[att_idx].sample_location.count > 0)
3354 return &state->attachments[att_idx].sample_location;
3355 } else {
3356 /* Otherwise return the subpass sample locations if defined. */
3357 if (state->subpass_sample_locs) {
3358 /* Because the driver sets the current subpass before
3359 * initial layout transitions, we should use the sample
3360 * locations from the previous subpass to avoid an
3361 * off-by-one problem. Otherwise, use the sample
3362 * locations for the current subpass for final layout
3363 * transitions.
3364 */
3365 if (begin_subpass)
3366 subpass_id--;
3367
3368 for (uint32_t i = 0; i < state->num_subpass_sample_locs; i++) {
3369 if (state->subpass_sample_locs[i].subpass_idx == subpass_id)
3370 return &state->subpass_sample_locs[i].sample_location;
3371 }
3372 }
3373 }
3374
3375 return NULL;
3376 }
3377
3378 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
3379 struct radv_subpass_attachment att,
3380 bool begin_subpass)
3381 {
3382 unsigned idx = att.attachment;
3383 struct radv_image_view *view = cmd_buffer->state.attachments[idx].iview;
3384 struct radv_sample_locations_state *sample_locs;
3385 VkImageSubresourceRange range;
3386 range.aspectMask = view->aspect_mask;
3387 range.baseMipLevel = view->base_mip;
3388 range.levelCount = 1;
3389 range.baseArrayLayer = view->base_layer;
3390 range.layerCount = cmd_buffer->state.framebuffer->layers;
3391
3392 if (cmd_buffer->state.subpass->view_mask) {
3393 /* If the current subpass uses multiview, the driver might have
3394 * performed a fast color/depth clear to the whole image
3395 * (including all layers). To make sure the driver will
3396 * decompress the image correctly (if needed), we have to
3397 * account for the "real" number of layers. If the view mask is
3398 * sparse, this will decompress more layers than needed.
3399 */
3400 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
3401 }
3402
3403 /* Get the subpass sample locations for the given attachment, if NULL
3404 * is returned the driver will use the default HW locations.
3405 */
3406 sample_locs = radv_get_attachment_sample_locations(cmd_buffer, idx,
3407 begin_subpass);
3408
3409 /* Determine if the subpass uses separate depth/stencil layouts. */
3410 bool uses_separate_depth_stencil_layouts = false;
3411 if ((cmd_buffer->state.attachments[idx].current_layout !=
3412 cmd_buffer->state.attachments[idx].current_stencil_layout) ||
3413 (att.layout != att.stencil_layout)) {
3414 uses_separate_depth_stencil_layouts = true;
3415 }
3416
3417 /* For separate layouts, perform depth and stencil transitions
3418 * separately.
3419 */
3420 if (uses_separate_depth_stencil_layouts &&
3421 (range.aspectMask == (VK_IMAGE_ASPECT_DEPTH_BIT |
3422 VK_IMAGE_ASPECT_STENCIL_BIT))) {
3423 /* Depth-only transitions. */
3424 range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3425 radv_handle_image_transition(cmd_buffer,
3426 view->image,
3427 cmd_buffer->state.attachments[idx].current_layout,
3428 cmd_buffer->state.attachments[idx].current_in_render_loop,
3429 att.layout, att.in_render_loop,
3430 0, 0, &range, sample_locs);
3431
3432 /* Stencil-only transitions. */
3433 range.aspectMask = VK_IMAGE_ASPECT_STENCIL_BIT;
3434 radv_handle_image_transition(cmd_buffer,
3435 view->image,
3436 cmd_buffer->state.attachments[idx].current_stencil_layout,
3437 cmd_buffer->state.attachments[idx].current_in_render_loop,
3438 att.stencil_layout, att.in_render_loop,
3439 0, 0, &range, sample_locs);
3440 } else {
3441 radv_handle_image_transition(cmd_buffer,
3442 view->image,
3443 cmd_buffer->state.attachments[idx].current_layout,
3444 cmd_buffer->state.attachments[idx].current_in_render_loop,
3445 att.layout, att.in_render_loop,
3446 0, 0, &range, sample_locs);
3447 }
3448
3449 cmd_buffer->state.attachments[idx].current_layout = att.layout;
3450 cmd_buffer->state.attachments[idx].current_stencil_layout = att.stencil_layout;
3451 cmd_buffer->state.attachments[idx].current_in_render_loop = att.in_render_loop;
3452
3453
3454 }
3455
3456 void
3457 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
3458 const struct radv_subpass *subpass)
3459 {
3460 cmd_buffer->state.subpass = subpass;
3461
3462 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
3463 }
3464
3465 static VkResult
3466 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
3467 struct radv_render_pass *pass,
3468 const VkRenderPassBeginInfo *info)
3469 {
3470 const struct VkRenderPassSampleLocationsBeginInfoEXT *sample_locs =
3471 vk_find_struct_const(info->pNext,
3472 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT);
3473 struct radv_cmd_state *state = &cmd_buffer->state;
3474
3475 if (!sample_locs) {
3476 state->subpass_sample_locs = NULL;
3477 return VK_SUCCESS;
3478 }
3479
3480 for (uint32_t i = 0; i < sample_locs->attachmentInitialSampleLocationsCount; i++) {
3481 const VkAttachmentSampleLocationsEXT *att_sample_locs =
3482 &sample_locs->pAttachmentInitialSampleLocations[i];
3483 uint32_t att_idx = att_sample_locs->attachmentIndex;
3484 struct radv_image *image = cmd_buffer->state.attachments[att_idx].iview->image;
3485
3486 assert(vk_format_is_depth_or_stencil(image->vk_format));
3487
3488 /* From the Vulkan spec 1.1.108:
3489 *
3490 * "If the image referenced by the framebuffer attachment at
3491 * index attachmentIndex was not created with
3492 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
3493 * then the values specified in sampleLocationsInfo are
3494 * ignored."
3495 */
3496 if (!(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT))
3497 continue;
3498
3499 const VkSampleLocationsInfoEXT *sample_locs_info =
3500 &att_sample_locs->sampleLocationsInfo;
3501
3502 state->attachments[att_idx].sample_location.per_pixel =
3503 sample_locs_info->sampleLocationsPerPixel;
3504 state->attachments[att_idx].sample_location.grid_size =
3505 sample_locs_info->sampleLocationGridSize;
3506 state->attachments[att_idx].sample_location.count =
3507 sample_locs_info->sampleLocationsCount;
3508 typed_memcpy(&state->attachments[att_idx].sample_location.locations[0],
3509 sample_locs_info->pSampleLocations,
3510 sample_locs_info->sampleLocationsCount);
3511 }
3512
3513 state->subpass_sample_locs = vk_alloc(&cmd_buffer->pool->alloc,
3514 sample_locs->postSubpassSampleLocationsCount *
3515 sizeof(state->subpass_sample_locs[0]),
3516 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3517 if (state->subpass_sample_locs == NULL) {
3518 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3519 return cmd_buffer->record_result;
3520 }
3521
3522 state->num_subpass_sample_locs = sample_locs->postSubpassSampleLocationsCount;
3523
3524 for (uint32_t i = 0; i < sample_locs->postSubpassSampleLocationsCount; i++) {
3525 const VkSubpassSampleLocationsEXT *subpass_sample_locs_info =
3526 &sample_locs->pPostSubpassSampleLocations[i];
3527 const VkSampleLocationsInfoEXT *sample_locs_info =
3528 &subpass_sample_locs_info->sampleLocationsInfo;
3529
3530 state->subpass_sample_locs[i].subpass_idx =
3531 subpass_sample_locs_info->subpassIndex;
3532 state->subpass_sample_locs[i].sample_location.per_pixel =
3533 sample_locs_info->sampleLocationsPerPixel;
3534 state->subpass_sample_locs[i].sample_location.grid_size =
3535 sample_locs_info->sampleLocationGridSize;
3536 state->subpass_sample_locs[i].sample_location.count =
3537 sample_locs_info->sampleLocationsCount;
3538 typed_memcpy(&state->subpass_sample_locs[i].sample_location.locations[0],
3539 sample_locs_info->pSampleLocations,
3540 sample_locs_info->sampleLocationsCount);
3541 }
3542
3543 return VK_SUCCESS;
3544 }
3545
3546 static VkResult
3547 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
3548 struct radv_render_pass *pass,
3549 const VkRenderPassBeginInfo *info)
3550 {
3551 struct radv_cmd_state *state = &cmd_buffer->state;
3552 const struct VkRenderPassAttachmentBeginInfo *attachment_info = NULL;
3553
3554 if (info) {
3555 attachment_info = vk_find_struct_const(info->pNext,
3556 RENDER_PASS_ATTACHMENT_BEGIN_INFO);
3557 }
3558
3559
3560 if (pass->attachment_count == 0) {
3561 state->attachments = NULL;
3562 return VK_SUCCESS;
3563 }
3564
3565 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
3566 pass->attachment_count *
3567 sizeof(state->attachments[0]),
3568 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3569 if (state->attachments == NULL) {
3570 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3571 return cmd_buffer->record_result;
3572 }
3573
3574 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
3575 struct radv_render_pass_attachment *att = &pass->attachments[i];
3576 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
3577 VkImageAspectFlags clear_aspects = 0;
3578
3579 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
3580 /* color attachment */
3581 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3582 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
3583 }
3584 } else {
3585 /* depthstencil attachment */
3586 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
3587 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3588 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
3589 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3590 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
3591 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3592 }
3593 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3594 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3595 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3596 }
3597 }
3598
3599 state->attachments[i].pending_clear_aspects = clear_aspects;
3600 state->attachments[i].cleared_views = 0;
3601 if (clear_aspects && info) {
3602 assert(info->clearValueCount > i);
3603 state->attachments[i].clear_value = info->pClearValues[i];
3604 }
3605
3606 state->attachments[i].current_layout = att->initial_layout;
3607 state->attachments[i].current_in_render_loop = false;
3608 state->attachments[i].current_stencil_layout = att->stencil_initial_layout;
3609 state->attachments[i].sample_location.count = 0;
3610
3611 struct radv_image_view *iview;
3612 if (attachment_info && attachment_info->attachmentCount > i) {
3613 iview = radv_image_view_from_handle(attachment_info->pAttachments[i]);
3614 } else {
3615 iview = state->framebuffer->attachments[i];
3616 }
3617
3618 state->attachments[i].iview = iview;
3619 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3620 radv_initialise_ds_surface(cmd_buffer->device, &state->attachments[i].ds, iview);
3621 } else {
3622 radv_initialise_color_surface(cmd_buffer->device, &state->attachments[i].cb, iview);
3623 }
3624 }
3625
3626 return VK_SUCCESS;
3627 }
3628
3629 VkResult radv_AllocateCommandBuffers(
3630 VkDevice _device,
3631 const VkCommandBufferAllocateInfo *pAllocateInfo,
3632 VkCommandBuffer *pCommandBuffers)
3633 {
3634 RADV_FROM_HANDLE(radv_device, device, _device);
3635 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
3636
3637 VkResult result = VK_SUCCESS;
3638 uint32_t i;
3639
3640 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
3641
3642 if (!list_is_empty(&pool->free_cmd_buffers)) {
3643 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
3644
3645 list_del(&cmd_buffer->pool_link);
3646 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
3647
3648 result = radv_reset_cmd_buffer(cmd_buffer);
3649 cmd_buffer->level = pAllocateInfo->level;
3650
3651 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
3652 } else {
3653 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
3654 &pCommandBuffers[i]);
3655 }
3656 if (result != VK_SUCCESS)
3657 break;
3658 }
3659
3660 if (result != VK_SUCCESS) {
3661 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
3662 i, pCommandBuffers);
3663
3664 /* From the Vulkan 1.0.66 spec:
3665 *
3666 * "vkAllocateCommandBuffers can be used to create multiple
3667 * command buffers. If the creation of any of those command
3668 * buffers fails, the implementation must destroy all
3669 * successfully created command buffer objects from this
3670 * command, set all entries of the pCommandBuffers array to
3671 * NULL and return the error."
3672 */
3673 memset(pCommandBuffers, 0,
3674 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
3675 }
3676
3677 return result;
3678 }
3679
3680 void radv_FreeCommandBuffers(
3681 VkDevice device,
3682 VkCommandPool commandPool,
3683 uint32_t commandBufferCount,
3684 const VkCommandBuffer *pCommandBuffers)
3685 {
3686 for (uint32_t i = 0; i < commandBufferCount; i++) {
3687 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
3688
3689 if (cmd_buffer) {
3690 if (cmd_buffer->pool) {
3691 list_del(&cmd_buffer->pool_link);
3692 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
3693 } else
3694 radv_destroy_cmd_buffer(cmd_buffer);
3695
3696 }
3697 }
3698 }
3699
3700 VkResult radv_ResetCommandBuffer(
3701 VkCommandBuffer commandBuffer,
3702 VkCommandBufferResetFlags flags)
3703 {
3704 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3705 return radv_reset_cmd_buffer(cmd_buffer);
3706 }
3707
3708 VkResult radv_BeginCommandBuffer(
3709 VkCommandBuffer commandBuffer,
3710 const VkCommandBufferBeginInfo *pBeginInfo)
3711 {
3712 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3713 VkResult result = VK_SUCCESS;
3714
3715 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
3716 /* If the command buffer has already been resetted with
3717 * vkResetCommandBuffer, no need to do it again.
3718 */
3719 result = radv_reset_cmd_buffer(cmd_buffer);
3720 if (result != VK_SUCCESS)
3721 return result;
3722 }
3723
3724 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
3725 cmd_buffer->state.last_primitive_reset_en = -1;
3726 cmd_buffer->state.last_index_type = -1;
3727 cmd_buffer->state.last_num_instances = -1;
3728 cmd_buffer->state.last_vertex_offset = -1;
3729 cmd_buffer->state.last_first_instance = -1;
3730 cmd_buffer->state.predication_type = -1;
3731 cmd_buffer->state.last_sx_ps_downconvert = -1;
3732 cmd_buffer->state.last_sx_blend_opt_epsilon = -1;
3733 cmd_buffer->state.last_sx_blend_opt_control = -1;
3734 cmd_buffer->usage_flags = pBeginInfo->flags;
3735
3736 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
3737 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
3738 assert(pBeginInfo->pInheritanceInfo);
3739 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
3740 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
3741
3742 struct radv_subpass *subpass =
3743 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
3744
3745 if (cmd_buffer->state.framebuffer) {
3746 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
3747 if (result != VK_SUCCESS)
3748 return result;
3749 }
3750
3751 cmd_buffer->state.inherited_pipeline_statistics =
3752 pBeginInfo->pInheritanceInfo->pipelineStatistics;
3753
3754 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3755 }
3756
3757 if (unlikely(cmd_buffer->device->trace_bo))
3758 radv_cmd_buffer_trace_emit(cmd_buffer);
3759
3760 radv_describe_begin_cmd_buffer(cmd_buffer);
3761
3762 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
3763
3764 return result;
3765 }
3766
3767 void radv_CmdBindVertexBuffers(
3768 VkCommandBuffer commandBuffer,
3769 uint32_t firstBinding,
3770 uint32_t bindingCount,
3771 const VkBuffer* pBuffers,
3772 const VkDeviceSize* pOffsets)
3773 {
3774 radv_CmdBindVertexBuffers2EXT(commandBuffer, firstBinding,
3775 bindingCount, pBuffers, pOffsets,
3776 NULL, NULL);
3777 }
3778
3779 void radv_CmdBindVertexBuffers2EXT(
3780 VkCommandBuffer commandBuffer,
3781 uint32_t firstBinding,
3782 uint32_t bindingCount,
3783 const VkBuffer* pBuffers,
3784 const VkDeviceSize* pOffsets,
3785 const VkDeviceSize* pSizes,
3786 const VkDeviceSize* pStrides)
3787 {
3788 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3789 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
3790 bool changed = false;
3791
3792 /* We have to defer setting up vertex buffer since we need the buffer
3793 * stride from the pipeline. */
3794
3795 assert(firstBinding + bindingCount <= MAX_VBS);
3796 for (uint32_t i = 0; i < bindingCount; i++) {
3797 RADV_FROM_HANDLE(radv_buffer, buffer, pBuffers[i]);
3798 uint32_t idx = firstBinding + i;
3799 VkDeviceSize size = pSizes ? pSizes[i] : 0;
3800 VkDeviceSize stride = pStrides ? pStrides[i] : 0;
3801
3802 /* pSizes and pStrides are optional. */
3803 if (!changed &&
3804 (vb[idx].buffer != buffer ||
3805 vb[idx].offset != pOffsets[i] ||
3806 vb[idx].size != size ||
3807 vb[idx].stride != stride)) {
3808 changed = true;
3809 }
3810
3811 vb[idx].buffer = buffer;
3812 vb[idx].offset = pOffsets[i];
3813 vb[idx].size = size;
3814 vb[idx].stride = stride;
3815
3816 if (buffer) {
3817 radv_cs_add_buffer(cmd_buffer->device->ws,
3818 cmd_buffer->cs, vb[idx].buffer->bo);
3819 }
3820 }
3821
3822 if (!changed) {
3823 /* No state changes. */
3824 return;
3825 }
3826
3827 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
3828 }
3829
3830 static uint32_t
3831 vk_to_index_type(VkIndexType type)
3832 {
3833 switch (type) {
3834 case VK_INDEX_TYPE_UINT8_EXT:
3835 return V_028A7C_VGT_INDEX_8;
3836 case VK_INDEX_TYPE_UINT16:
3837 return V_028A7C_VGT_INDEX_16;
3838 case VK_INDEX_TYPE_UINT32:
3839 return V_028A7C_VGT_INDEX_32;
3840 default:
3841 unreachable("invalid index type");
3842 }
3843 }
3844
3845 static uint32_t
3846 radv_get_vgt_index_size(uint32_t type)
3847 {
3848 switch (type) {
3849 case V_028A7C_VGT_INDEX_8:
3850 return 1;
3851 case V_028A7C_VGT_INDEX_16:
3852 return 2;
3853 case V_028A7C_VGT_INDEX_32:
3854 return 4;
3855 default:
3856 unreachable("invalid index type");
3857 }
3858 }
3859
3860 void radv_CmdBindIndexBuffer(
3861 VkCommandBuffer commandBuffer,
3862 VkBuffer buffer,
3863 VkDeviceSize offset,
3864 VkIndexType indexType)
3865 {
3866 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3867 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
3868
3869 if (cmd_buffer->state.index_buffer == index_buffer &&
3870 cmd_buffer->state.index_offset == offset &&
3871 cmd_buffer->state.index_type == indexType) {
3872 /* No state changes. */
3873 return;
3874 }
3875
3876 cmd_buffer->state.index_buffer = index_buffer;
3877 cmd_buffer->state.index_offset = offset;
3878 cmd_buffer->state.index_type = vk_to_index_type(indexType);
3879 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
3880 cmd_buffer->state.index_va += index_buffer->offset + offset;
3881
3882 int index_size = radv_get_vgt_index_size(vk_to_index_type(indexType));
3883 cmd_buffer->state.max_index_count = (index_buffer->size - offset) / index_size;
3884 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3885 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
3886 }
3887
3888
3889 static void
3890 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3891 VkPipelineBindPoint bind_point,
3892 struct radv_descriptor_set *set, unsigned idx)
3893 {
3894 struct radeon_winsys *ws = cmd_buffer->device->ws;
3895
3896 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
3897
3898 assert(set);
3899 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
3900
3901 if (!cmd_buffer->device->use_global_bo_list) {
3902 for (unsigned j = 0; j < set->buffer_count; ++j)
3903 if (set->descriptors[j])
3904 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
3905 }
3906
3907 if(set->bo)
3908 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
3909 }
3910
3911 void radv_CmdBindDescriptorSets(
3912 VkCommandBuffer commandBuffer,
3913 VkPipelineBindPoint pipelineBindPoint,
3914 VkPipelineLayout _layout,
3915 uint32_t firstSet,
3916 uint32_t descriptorSetCount,
3917 const VkDescriptorSet* pDescriptorSets,
3918 uint32_t dynamicOffsetCount,
3919 const uint32_t* pDynamicOffsets)
3920 {
3921 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3922 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3923 unsigned dyn_idx = 0;
3924
3925 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
3926 struct radv_descriptor_state *descriptors_state =
3927 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3928
3929 for (unsigned i = 0; i < descriptorSetCount; ++i) {
3930 unsigned idx = i + firstSet;
3931 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
3932
3933 /* If the set is already bound we only need to update the
3934 * (potentially changed) dynamic offsets. */
3935 if (descriptors_state->sets[idx] != set ||
3936 !(descriptors_state->valid & (1u << idx))) {
3937 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
3938 }
3939
3940 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
3941 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
3942 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
3943 assert(dyn_idx < dynamicOffsetCount);
3944
3945 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
3946 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
3947 dst[0] = va;
3948 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
3949 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
3950 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3951 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3952 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3953 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3954
3955 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
3956 dst[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3957 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3958 S_008F0C_RESOURCE_LEVEL(1);
3959 } else {
3960 dst[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3961 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3962 }
3963
3964 cmd_buffer->push_constant_stages |=
3965 set->layout->dynamic_shader_stages;
3966 }
3967 }
3968 }
3969
3970 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3971 struct radv_descriptor_set *set,
3972 struct radv_descriptor_set_layout *layout,
3973 VkPipelineBindPoint bind_point)
3974 {
3975 struct radv_descriptor_state *descriptors_state =
3976 radv_get_descriptors_state(cmd_buffer, bind_point);
3977 set->size = layout->size;
3978 set->layout = layout;
3979
3980 if (descriptors_state->push_set.capacity < set->size) {
3981 size_t new_size = MAX2(set->size, 1024);
3982 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
3983 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
3984
3985 free(set->mapped_ptr);
3986 set->mapped_ptr = malloc(new_size);
3987
3988 if (!set->mapped_ptr) {
3989 descriptors_state->push_set.capacity = 0;
3990 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3991 return false;
3992 }
3993
3994 descriptors_state->push_set.capacity = new_size;
3995 }
3996
3997 return true;
3998 }
3999
4000 void radv_meta_push_descriptor_set(
4001 struct radv_cmd_buffer* cmd_buffer,
4002 VkPipelineBindPoint pipelineBindPoint,
4003 VkPipelineLayout _layout,
4004 uint32_t set,
4005 uint32_t descriptorWriteCount,
4006 const VkWriteDescriptorSet* pDescriptorWrites)
4007 {
4008 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
4009 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
4010 unsigned bo_offset;
4011
4012 assert(set == 0);
4013 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
4014
4015 push_set->size = layout->set[set].layout->size;
4016 push_set->layout = layout->set[set].layout;
4017
4018 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
4019 &bo_offset,
4020 (void**) &push_set->mapped_ptr))
4021 return;
4022
4023 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
4024 push_set->va += bo_offset;
4025
4026 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
4027 radv_descriptor_set_to_handle(push_set),
4028 descriptorWriteCount, pDescriptorWrites, 0, NULL);
4029
4030 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
4031 }
4032
4033 void radv_CmdPushDescriptorSetKHR(
4034 VkCommandBuffer commandBuffer,
4035 VkPipelineBindPoint pipelineBindPoint,
4036 VkPipelineLayout _layout,
4037 uint32_t set,
4038 uint32_t descriptorWriteCount,
4039 const VkWriteDescriptorSet* pDescriptorWrites)
4040 {
4041 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4042 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
4043 struct radv_descriptor_state *descriptors_state =
4044 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
4045 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
4046
4047 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
4048
4049 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
4050 layout->set[set].layout,
4051 pipelineBindPoint))
4052 return;
4053
4054 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
4055 * because it is invalid, according to Vulkan spec.
4056 */
4057 for (int i = 0; i < descriptorWriteCount; i++) {
4058 ASSERTED const VkWriteDescriptorSet *writeset = &pDescriptorWrites[i];
4059 assert(writeset->descriptorType != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT);
4060 }
4061
4062 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
4063 radv_descriptor_set_to_handle(push_set),
4064 descriptorWriteCount, pDescriptorWrites, 0, NULL);
4065
4066 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
4067 descriptors_state->push_dirty = true;
4068 }
4069
4070 void radv_CmdPushDescriptorSetWithTemplateKHR(
4071 VkCommandBuffer commandBuffer,
4072 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
4073 VkPipelineLayout _layout,
4074 uint32_t set,
4075 const void* pData)
4076 {
4077 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4078 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
4079 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
4080 struct radv_descriptor_state *descriptors_state =
4081 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
4082 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
4083
4084 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
4085
4086 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
4087 layout->set[set].layout,
4088 templ->bind_point))
4089 return;
4090
4091 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
4092 descriptorUpdateTemplate, pData);
4093
4094 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
4095 descriptors_state->push_dirty = true;
4096 }
4097
4098 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
4099 VkPipelineLayout layout,
4100 VkShaderStageFlags stageFlags,
4101 uint32_t offset,
4102 uint32_t size,
4103 const void* pValues)
4104 {
4105 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4106 memcpy(cmd_buffer->push_constants + offset, pValues, size);
4107 cmd_buffer->push_constant_stages |= stageFlags;
4108 }
4109
4110 VkResult radv_EndCommandBuffer(
4111 VkCommandBuffer commandBuffer)
4112 {
4113 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4114
4115 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
4116 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6)
4117 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WB_L2;
4118
4119 /* Make sure to sync all pending active queries at the end of
4120 * command buffer.
4121 */
4122 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
4123
4124 /* Since NGG streamout uses GDS, we need to make GDS idle when
4125 * we leave the IB, otherwise another process might overwrite
4126 * it while our shaders are busy.
4127 */
4128 if (cmd_buffer->gds_needed)
4129 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
4130
4131 si_emit_cache_flush(cmd_buffer);
4132 }
4133
4134 /* Make sure CP DMA is idle at the end of IBs because the kernel
4135 * doesn't wait for it.
4136 */
4137 si_cp_dma_wait_for_idle(cmd_buffer);
4138
4139 radv_describe_end_cmd_buffer(cmd_buffer);
4140
4141 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
4142 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
4143
4144 VkResult result = cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs);
4145 if (result != VK_SUCCESS)
4146 return vk_error(cmd_buffer->device->instance, result);
4147
4148 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
4149
4150 return cmd_buffer->record_result;
4151 }
4152
4153 static void
4154 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
4155 {
4156 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4157
4158 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
4159 return;
4160
4161 assert(!pipeline->ctx_cs.cdw);
4162
4163 cmd_buffer->state.emitted_compute_pipeline = pipeline;
4164
4165 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
4166 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
4167
4168 cmd_buffer->compute_scratch_size_per_wave_needed = MAX2(cmd_buffer->compute_scratch_size_per_wave_needed,
4169 pipeline->scratch_bytes_per_wave);
4170 cmd_buffer->compute_scratch_waves_wanted = MAX2(cmd_buffer->compute_scratch_waves_wanted,
4171 pipeline->max_waves);
4172
4173 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
4174 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
4175
4176 if (unlikely(cmd_buffer->device->trace_bo))
4177 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
4178 }
4179
4180 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
4181 VkPipelineBindPoint bind_point)
4182 {
4183 struct radv_descriptor_state *descriptors_state =
4184 radv_get_descriptors_state(cmd_buffer, bind_point);
4185
4186 descriptors_state->dirty |= descriptors_state->valid;
4187 }
4188
4189 void radv_CmdBindPipeline(
4190 VkCommandBuffer commandBuffer,
4191 VkPipelineBindPoint pipelineBindPoint,
4192 VkPipeline _pipeline)
4193 {
4194 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4195 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
4196
4197 switch (pipelineBindPoint) {
4198 case VK_PIPELINE_BIND_POINT_COMPUTE:
4199 if (cmd_buffer->state.compute_pipeline == pipeline)
4200 return;
4201 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
4202
4203 cmd_buffer->state.compute_pipeline = pipeline;
4204 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
4205 break;
4206 case VK_PIPELINE_BIND_POINT_GRAPHICS:
4207 if (cmd_buffer->state.pipeline == pipeline)
4208 return;
4209 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
4210
4211 cmd_buffer->state.pipeline = pipeline;
4212 if (!pipeline)
4213 break;
4214
4215 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
4216 cmd_buffer->push_constant_stages |= pipeline->active_stages;
4217
4218 /* the new vertex shader might not have the same user regs */
4219 cmd_buffer->state.last_first_instance = -1;
4220 cmd_buffer->state.last_vertex_offset = -1;
4221
4222 /* Prefetch all pipeline shaders at first draw time. */
4223 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
4224
4225 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX10 &&
4226 cmd_buffer->state.emitted_pipeline &&
4227 radv_pipeline_has_ngg(cmd_buffer->state.emitted_pipeline) &&
4228 !radv_pipeline_has_ngg(cmd_buffer->state.pipeline)) {
4229 /* Transitioning from NGG to legacy GS requires
4230 * VGT_FLUSH on Navi10-14. VGT_FLUSH is also emitted
4231 * at the beginning of IBs when legacy GS ring pointers
4232 * are set.
4233 */
4234 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
4235 }
4236
4237 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
4238 radv_bind_streamout_state(cmd_buffer, pipeline);
4239
4240 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
4241 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
4242 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
4243 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
4244
4245 if (radv_pipeline_has_tess(pipeline))
4246 cmd_buffer->tess_rings_needed = true;
4247 break;
4248 default:
4249 assert(!"invalid bind point");
4250 break;
4251 }
4252 }
4253
4254 void radv_CmdSetViewport(
4255 VkCommandBuffer commandBuffer,
4256 uint32_t firstViewport,
4257 uint32_t viewportCount,
4258 const VkViewport* pViewports)
4259 {
4260 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4261 struct radv_cmd_state *state = &cmd_buffer->state;
4262 ASSERTED const uint32_t total_count = firstViewport + viewportCount;
4263
4264 assert(firstViewport < MAX_VIEWPORTS);
4265 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
4266
4267 if (total_count <= state->dynamic.viewport.count &&
4268 !memcmp(state->dynamic.viewport.viewports + firstViewport,
4269 pViewports, viewportCount * sizeof(*pViewports))) {
4270 return;
4271 }
4272
4273 if (state->dynamic.viewport.count < total_count)
4274 state->dynamic.viewport.count = total_count;
4275
4276 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
4277 viewportCount * sizeof(*pViewports));
4278
4279 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
4280 }
4281
4282 void radv_CmdSetScissor(
4283 VkCommandBuffer commandBuffer,
4284 uint32_t firstScissor,
4285 uint32_t scissorCount,
4286 const VkRect2D* pScissors)
4287 {
4288 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4289 struct radv_cmd_state *state = &cmd_buffer->state;
4290 ASSERTED const uint32_t total_count = firstScissor + scissorCount;
4291
4292 assert(firstScissor < MAX_SCISSORS);
4293 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
4294
4295 if (total_count <= state->dynamic.scissor.count &&
4296 !memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
4297 scissorCount * sizeof(*pScissors))) {
4298 return;
4299 }
4300
4301 if (state->dynamic.scissor.count < total_count)
4302 state->dynamic.scissor.count = total_count;
4303
4304 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
4305 scissorCount * sizeof(*pScissors));
4306
4307 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
4308 }
4309
4310 void radv_CmdSetLineWidth(
4311 VkCommandBuffer commandBuffer,
4312 float lineWidth)
4313 {
4314 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4315
4316 if (cmd_buffer->state.dynamic.line_width == lineWidth)
4317 return;
4318
4319 cmd_buffer->state.dynamic.line_width = lineWidth;
4320 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
4321 }
4322
4323 void radv_CmdSetDepthBias(
4324 VkCommandBuffer commandBuffer,
4325 float depthBiasConstantFactor,
4326 float depthBiasClamp,
4327 float depthBiasSlopeFactor)
4328 {
4329 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4330 struct radv_cmd_state *state = &cmd_buffer->state;
4331
4332 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
4333 state->dynamic.depth_bias.clamp == depthBiasClamp &&
4334 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
4335 return;
4336 }
4337
4338 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
4339 state->dynamic.depth_bias.clamp = depthBiasClamp;
4340 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
4341
4342 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
4343 }
4344
4345 void radv_CmdSetBlendConstants(
4346 VkCommandBuffer commandBuffer,
4347 const float blendConstants[4])
4348 {
4349 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4350 struct radv_cmd_state *state = &cmd_buffer->state;
4351
4352 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
4353 return;
4354
4355 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
4356
4357 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
4358 }
4359
4360 void radv_CmdSetDepthBounds(
4361 VkCommandBuffer commandBuffer,
4362 float minDepthBounds,
4363 float maxDepthBounds)
4364 {
4365 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4366 struct radv_cmd_state *state = &cmd_buffer->state;
4367
4368 if (state->dynamic.depth_bounds.min == minDepthBounds &&
4369 state->dynamic.depth_bounds.max == maxDepthBounds) {
4370 return;
4371 }
4372
4373 state->dynamic.depth_bounds.min = minDepthBounds;
4374 state->dynamic.depth_bounds.max = maxDepthBounds;
4375
4376 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
4377 }
4378
4379 void radv_CmdSetStencilCompareMask(
4380 VkCommandBuffer commandBuffer,
4381 VkStencilFaceFlags faceMask,
4382 uint32_t compareMask)
4383 {
4384 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4385 struct radv_cmd_state *state = &cmd_buffer->state;
4386 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
4387 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
4388
4389 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4390 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4391 return;
4392 }
4393
4394 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4395 state->dynamic.stencil_compare_mask.front = compareMask;
4396 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4397 state->dynamic.stencil_compare_mask.back = compareMask;
4398
4399 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
4400 }
4401
4402 void radv_CmdSetStencilWriteMask(
4403 VkCommandBuffer commandBuffer,
4404 VkStencilFaceFlags faceMask,
4405 uint32_t writeMask)
4406 {
4407 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4408 struct radv_cmd_state *state = &cmd_buffer->state;
4409 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
4410 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
4411
4412 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4413 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4414 return;
4415 }
4416
4417 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4418 state->dynamic.stencil_write_mask.front = writeMask;
4419 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4420 state->dynamic.stencil_write_mask.back = writeMask;
4421
4422 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
4423 }
4424
4425 void radv_CmdSetStencilReference(
4426 VkCommandBuffer commandBuffer,
4427 VkStencilFaceFlags faceMask,
4428 uint32_t reference)
4429 {
4430 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4431 struct radv_cmd_state *state = &cmd_buffer->state;
4432 bool front_same = state->dynamic.stencil_reference.front == reference;
4433 bool back_same = state->dynamic.stencil_reference.back == reference;
4434
4435 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4436 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4437 return;
4438 }
4439
4440 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4441 cmd_buffer->state.dynamic.stencil_reference.front = reference;
4442 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4443 cmd_buffer->state.dynamic.stencil_reference.back = reference;
4444
4445 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
4446 }
4447
4448 void radv_CmdSetDiscardRectangleEXT(
4449 VkCommandBuffer commandBuffer,
4450 uint32_t firstDiscardRectangle,
4451 uint32_t discardRectangleCount,
4452 const VkRect2D* pDiscardRectangles)
4453 {
4454 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4455 struct radv_cmd_state *state = &cmd_buffer->state;
4456 ASSERTED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
4457
4458 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
4459 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
4460
4461 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
4462 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
4463 return;
4464 }
4465
4466 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
4467 pDiscardRectangles, discardRectangleCount);
4468
4469 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
4470 }
4471
4472 void radv_CmdSetSampleLocationsEXT(
4473 VkCommandBuffer commandBuffer,
4474 const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
4475 {
4476 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4477 struct radv_cmd_state *state = &cmd_buffer->state;
4478
4479 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
4480
4481 state->dynamic.sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
4482 state->dynamic.sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
4483 state->dynamic.sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
4484 typed_memcpy(&state->dynamic.sample_location.locations[0],
4485 pSampleLocationsInfo->pSampleLocations,
4486 pSampleLocationsInfo->sampleLocationsCount);
4487
4488 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS;
4489 }
4490
4491 void radv_CmdSetLineStippleEXT(
4492 VkCommandBuffer commandBuffer,
4493 uint32_t lineStippleFactor,
4494 uint16_t lineStipplePattern)
4495 {
4496 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4497 struct radv_cmd_state *state = &cmd_buffer->state;
4498
4499 state->dynamic.line_stipple.factor = lineStippleFactor;
4500 state->dynamic.line_stipple.pattern = lineStipplePattern;
4501
4502 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE;
4503 }
4504
4505 void radv_CmdSetCullModeEXT(
4506 VkCommandBuffer commandBuffer,
4507 VkCullModeFlags cullMode)
4508 {
4509 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4510 struct radv_cmd_state *state = &cmd_buffer->state;
4511
4512 if (state->dynamic.cull_mode == cullMode)
4513 return;
4514
4515 state->dynamic.cull_mode = cullMode;
4516
4517 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_CULL_MODE;
4518 }
4519
4520 void radv_CmdSetFrontFaceEXT(
4521 VkCommandBuffer commandBuffer,
4522 VkFrontFace frontFace)
4523 {
4524 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4525 struct radv_cmd_state *state = &cmd_buffer->state;
4526
4527 if (state->dynamic.front_face == frontFace)
4528 return;
4529
4530 state->dynamic.front_face = frontFace;
4531
4532 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE;
4533 }
4534
4535 void radv_CmdSetPrimitiveTopologyEXT(
4536 VkCommandBuffer commandBuffer,
4537 VkPrimitiveTopology primitiveTopology)
4538 {
4539 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4540 struct radv_cmd_state *state = &cmd_buffer->state;
4541 unsigned primitive_topology = si_translate_prim(primitiveTopology);
4542
4543 if (state->dynamic.primitive_topology == primitive_topology)
4544 return;
4545
4546 state->dynamic.primitive_topology = primitive_topology;
4547
4548 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY;
4549 }
4550
4551 void radv_CmdSetViewportWithCountEXT(
4552 VkCommandBuffer commandBuffer,
4553 uint32_t viewportCount,
4554 const VkViewport* pViewports)
4555 {
4556 radv_CmdSetViewport(commandBuffer, 0, viewportCount, pViewports);
4557 }
4558
4559 void radv_CmdSetScissorWithCountEXT(
4560 VkCommandBuffer commandBuffer,
4561 uint32_t scissorCount,
4562 const VkRect2D* pScissors)
4563 {
4564 radv_CmdSetScissor(commandBuffer, 0, scissorCount, pScissors);
4565 }
4566
4567 void radv_CmdSetDepthTestEnableEXT(
4568 VkCommandBuffer commandBuffer,
4569 VkBool32 depthTestEnable)
4570
4571 {
4572 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4573 struct radv_cmd_state *state = &cmd_buffer->state;
4574
4575 if (state->dynamic.depth_test_enable == depthTestEnable)
4576 return;
4577
4578 state->dynamic.depth_test_enable = depthTestEnable;
4579
4580 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE;
4581 }
4582
4583 void radv_CmdSetDepthWriteEnableEXT(
4584 VkCommandBuffer commandBuffer,
4585 VkBool32 depthWriteEnable)
4586 {
4587 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4588 struct radv_cmd_state *state = &cmd_buffer->state;
4589
4590 if (state->dynamic.depth_write_enable == depthWriteEnable)
4591 return;
4592
4593 state->dynamic.depth_write_enable = depthWriteEnable;
4594
4595 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE;
4596 }
4597
4598 void radv_CmdSetDepthCompareOpEXT(
4599 VkCommandBuffer commandBuffer,
4600 VkCompareOp depthCompareOp)
4601 {
4602 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4603 struct radv_cmd_state *state = &cmd_buffer->state;
4604
4605 if (state->dynamic.depth_compare_op == depthCompareOp)
4606 return;
4607
4608 state->dynamic.depth_compare_op = depthCompareOp;
4609
4610 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP;
4611 }
4612
4613 void radv_CmdSetDepthBoundsTestEnableEXT(
4614 VkCommandBuffer commandBuffer,
4615 VkBool32 depthBoundsTestEnable)
4616 {
4617 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4618 struct radv_cmd_state *state = &cmd_buffer->state;
4619
4620 if (state->dynamic.depth_bounds_test_enable == depthBoundsTestEnable)
4621 return;
4622
4623 state->dynamic.depth_bounds_test_enable = depthBoundsTestEnable;
4624
4625 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE;
4626 }
4627
4628 void radv_CmdSetStencilTestEnableEXT(
4629 VkCommandBuffer commandBuffer,
4630 VkBool32 stencilTestEnable)
4631 {
4632 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4633 struct radv_cmd_state *state = &cmd_buffer->state;
4634
4635 if (state->dynamic.stencil_test_enable == stencilTestEnable)
4636 return;
4637
4638 state->dynamic.stencil_test_enable = stencilTestEnable;
4639
4640 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE;
4641 }
4642
4643 void radv_CmdSetStencilOpEXT(
4644 VkCommandBuffer commandBuffer,
4645 VkStencilFaceFlags faceMask,
4646 VkStencilOp failOp,
4647 VkStencilOp passOp,
4648 VkStencilOp depthFailOp,
4649 VkCompareOp compareOp)
4650 {
4651 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4652 struct radv_cmd_state *state = &cmd_buffer->state;
4653 bool front_same =
4654 state->dynamic.stencil_op.front.fail_op == failOp &&
4655 state->dynamic.stencil_op.front.pass_op == passOp &&
4656 state->dynamic.stencil_op.front.depth_fail_op == depthFailOp &&
4657 state->dynamic.stencil_op.front.compare_op == compareOp;
4658 bool back_same =
4659 state->dynamic.stencil_op.back.fail_op == failOp &&
4660 state->dynamic.stencil_op.back.pass_op == passOp &&
4661 state->dynamic.stencil_op.back.depth_fail_op == depthFailOp &&
4662 state->dynamic.stencil_op.back.compare_op == compareOp;
4663
4664 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4665 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same))
4666 return;
4667
4668 if (faceMask & VK_STENCIL_FACE_FRONT_BIT) {
4669 state->dynamic.stencil_op.front.fail_op = failOp;
4670 state->dynamic.stencil_op.front.pass_op = passOp;
4671 state->dynamic.stencil_op.front.depth_fail_op = depthFailOp;
4672 state->dynamic.stencil_op.front.compare_op = compareOp;
4673 }
4674
4675 if (faceMask & VK_STENCIL_FACE_BACK_BIT) {
4676 state->dynamic.stencil_op.back.fail_op = failOp;
4677 state->dynamic.stencil_op.back.pass_op = passOp;
4678 state->dynamic.stencil_op.back.depth_fail_op = depthFailOp;
4679 state->dynamic.stencil_op.back.compare_op = compareOp;
4680 }
4681
4682 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP;
4683 }
4684
4685 void radv_CmdExecuteCommands(
4686 VkCommandBuffer commandBuffer,
4687 uint32_t commandBufferCount,
4688 const VkCommandBuffer* pCmdBuffers)
4689 {
4690 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
4691
4692 assert(commandBufferCount > 0);
4693
4694 /* Emit pending flushes on primary prior to executing secondary */
4695 si_emit_cache_flush(primary);
4696
4697 for (uint32_t i = 0; i < commandBufferCount; i++) {
4698 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
4699
4700 primary->scratch_size_per_wave_needed = MAX2(primary->scratch_size_per_wave_needed,
4701 secondary->scratch_size_per_wave_needed);
4702 primary->scratch_waves_wanted = MAX2(primary->scratch_waves_wanted,
4703 secondary->scratch_waves_wanted);
4704 primary->compute_scratch_size_per_wave_needed = MAX2(primary->compute_scratch_size_per_wave_needed,
4705 secondary->compute_scratch_size_per_wave_needed);
4706 primary->compute_scratch_waves_wanted = MAX2(primary->compute_scratch_waves_wanted,
4707 secondary->compute_scratch_waves_wanted);
4708
4709 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
4710 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
4711 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
4712 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
4713 if (secondary->tess_rings_needed)
4714 primary->tess_rings_needed = true;
4715 if (secondary->sample_positions_needed)
4716 primary->sample_positions_needed = true;
4717 if (secondary->gds_needed)
4718 primary->gds_needed = true;
4719
4720 if (!secondary->state.framebuffer &&
4721 (primary->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)) {
4722 /* Emit the framebuffer state from primary if secondary
4723 * has been recorded without a framebuffer, otherwise
4724 * fast color/depth clears can't work.
4725 */
4726 radv_emit_framebuffer_state(primary);
4727 }
4728
4729 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
4730
4731
4732 /* When the secondary command buffer is compute only we don't
4733 * need to re-emit the current graphics pipeline.
4734 */
4735 if (secondary->state.emitted_pipeline) {
4736 primary->state.emitted_pipeline =
4737 secondary->state.emitted_pipeline;
4738 }
4739
4740 /* When the secondary command buffer is graphics only we don't
4741 * need to re-emit the current compute pipeline.
4742 */
4743 if (secondary->state.emitted_compute_pipeline) {
4744 primary->state.emitted_compute_pipeline =
4745 secondary->state.emitted_compute_pipeline;
4746 }
4747
4748 /* Only re-emit the draw packets when needed. */
4749 if (secondary->state.last_primitive_reset_en != -1) {
4750 primary->state.last_primitive_reset_en =
4751 secondary->state.last_primitive_reset_en;
4752 }
4753
4754 if (secondary->state.last_primitive_reset_index) {
4755 primary->state.last_primitive_reset_index =
4756 secondary->state.last_primitive_reset_index;
4757 }
4758
4759 if (secondary->state.last_ia_multi_vgt_param) {
4760 primary->state.last_ia_multi_vgt_param =
4761 secondary->state.last_ia_multi_vgt_param;
4762 }
4763
4764 primary->state.last_first_instance = secondary->state.last_first_instance;
4765 primary->state.last_num_instances = secondary->state.last_num_instances;
4766 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
4767 primary->state.last_sx_ps_downconvert = secondary->state.last_sx_ps_downconvert;
4768 primary->state.last_sx_blend_opt_epsilon = secondary->state.last_sx_blend_opt_epsilon;
4769 primary->state.last_sx_blend_opt_control = secondary->state.last_sx_blend_opt_control;
4770
4771 if (secondary->state.last_index_type != -1) {
4772 primary->state.last_index_type =
4773 secondary->state.last_index_type;
4774 }
4775 }
4776
4777 /* After executing commands from secondary buffers we have to dirty
4778 * some states.
4779 */
4780 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
4781 RADV_CMD_DIRTY_INDEX_BUFFER |
4782 RADV_CMD_DIRTY_DYNAMIC_ALL;
4783 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
4784 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
4785 }
4786
4787 VkResult radv_CreateCommandPool(
4788 VkDevice _device,
4789 const VkCommandPoolCreateInfo* pCreateInfo,
4790 const VkAllocationCallbacks* pAllocator,
4791 VkCommandPool* pCmdPool)
4792 {
4793 RADV_FROM_HANDLE(radv_device, device, _device);
4794 struct radv_cmd_pool *pool;
4795
4796 pool = vk_alloc2(&device->vk.alloc, pAllocator, sizeof(*pool), 8,
4797 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4798 if (pool == NULL)
4799 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4800
4801 vk_object_base_init(&device->vk, &pool->base,
4802 VK_OBJECT_TYPE_COMMAND_POOL);
4803
4804 if (pAllocator)
4805 pool->alloc = *pAllocator;
4806 else
4807 pool->alloc = device->vk.alloc;
4808
4809 list_inithead(&pool->cmd_buffers);
4810 list_inithead(&pool->free_cmd_buffers);
4811
4812 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
4813
4814 *pCmdPool = radv_cmd_pool_to_handle(pool);
4815
4816 return VK_SUCCESS;
4817
4818 }
4819
4820 void radv_DestroyCommandPool(
4821 VkDevice _device,
4822 VkCommandPool commandPool,
4823 const VkAllocationCallbacks* pAllocator)
4824 {
4825 RADV_FROM_HANDLE(radv_device, device, _device);
4826 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4827
4828 if (!pool)
4829 return;
4830
4831 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4832 &pool->cmd_buffers, pool_link) {
4833 radv_destroy_cmd_buffer(cmd_buffer);
4834 }
4835
4836 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4837 &pool->free_cmd_buffers, pool_link) {
4838 radv_destroy_cmd_buffer(cmd_buffer);
4839 }
4840
4841 vk_object_base_finish(&pool->base);
4842 vk_free2(&device->vk.alloc, pAllocator, pool);
4843 }
4844
4845 VkResult radv_ResetCommandPool(
4846 VkDevice device,
4847 VkCommandPool commandPool,
4848 VkCommandPoolResetFlags flags)
4849 {
4850 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4851 VkResult result;
4852
4853 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
4854 &pool->cmd_buffers, pool_link) {
4855 result = radv_reset_cmd_buffer(cmd_buffer);
4856 if (result != VK_SUCCESS)
4857 return result;
4858 }
4859
4860 return VK_SUCCESS;
4861 }
4862
4863 void radv_TrimCommandPool(
4864 VkDevice device,
4865 VkCommandPool commandPool,
4866 VkCommandPoolTrimFlags flags)
4867 {
4868 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4869
4870 if (!pool)
4871 return;
4872
4873 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4874 &pool->free_cmd_buffers, pool_link) {
4875 radv_destroy_cmd_buffer(cmd_buffer);
4876 }
4877 }
4878
4879 static void
4880 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
4881 uint32_t subpass_id)
4882 {
4883 struct radv_cmd_state *state = &cmd_buffer->state;
4884 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
4885
4886 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
4887 cmd_buffer->cs, 4096);
4888
4889 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
4890
4891 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
4892
4893 radv_describe_barrier_start(cmd_buffer, RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC);
4894
4895 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4896 const uint32_t a = subpass->attachments[i].attachment;
4897 if (a == VK_ATTACHMENT_UNUSED)
4898 continue;
4899
4900 radv_handle_subpass_image_transition(cmd_buffer,
4901 subpass->attachments[i],
4902 true);
4903 }
4904
4905 radv_describe_barrier_end(cmd_buffer);
4906
4907 radv_cmd_buffer_clear_subpass(cmd_buffer);
4908
4909 assert(cmd_buffer->cs->cdw <= cdw_max);
4910 }
4911
4912 static void
4913 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
4914 {
4915 struct radv_cmd_state *state = &cmd_buffer->state;
4916 const struct radv_subpass *subpass = state->subpass;
4917 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
4918
4919 radv_cmd_buffer_resolve_subpass(cmd_buffer);
4920
4921 radv_describe_barrier_start(cmd_buffer, RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC);
4922
4923 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4924 const uint32_t a = subpass->attachments[i].attachment;
4925 if (a == VK_ATTACHMENT_UNUSED)
4926 continue;
4927
4928 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
4929 continue;
4930
4931 VkImageLayout layout = state->pass->attachments[a].final_layout;
4932 VkImageLayout stencil_layout = state->pass->attachments[a].stencil_final_layout;
4933 struct radv_subpass_attachment att = { a, layout, stencil_layout };
4934 radv_handle_subpass_image_transition(cmd_buffer, att, false);
4935 }
4936
4937 radv_describe_barrier_end(cmd_buffer);
4938 }
4939
4940 void
4941 radv_cmd_buffer_begin_render_pass(struct radv_cmd_buffer *cmd_buffer,
4942 const VkRenderPassBeginInfo *pRenderPassBegin)
4943 {
4944 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
4945 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
4946 VkResult result;
4947
4948 cmd_buffer->state.framebuffer = framebuffer;
4949 cmd_buffer->state.pass = pass;
4950 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
4951
4952 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
4953 if (result != VK_SUCCESS)
4954 return;
4955
4956 result = radv_cmd_state_setup_sample_locations(cmd_buffer, pass, pRenderPassBegin);
4957 if (result != VK_SUCCESS)
4958 return;
4959 }
4960
4961 void radv_CmdBeginRenderPass(
4962 VkCommandBuffer commandBuffer,
4963 const VkRenderPassBeginInfo* pRenderPassBegin,
4964 VkSubpassContents contents)
4965 {
4966 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4967
4968 radv_cmd_buffer_begin_render_pass(cmd_buffer, pRenderPassBegin);
4969
4970 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
4971 }
4972
4973 void radv_CmdBeginRenderPass2(
4974 VkCommandBuffer commandBuffer,
4975 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
4976 const VkSubpassBeginInfo* pSubpassBeginInfo)
4977 {
4978 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
4979 pSubpassBeginInfo->contents);
4980 }
4981
4982 void radv_CmdNextSubpass(
4983 VkCommandBuffer commandBuffer,
4984 VkSubpassContents contents)
4985 {
4986 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4987
4988 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
4989 radv_cmd_buffer_end_subpass(cmd_buffer);
4990 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
4991 }
4992
4993 void radv_CmdNextSubpass2(
4994 VkCommandBuffer commandBuffer,
4995 const VkSubpassBeginInfo* pSubpassBeginInfo,
4996 const VkSubpassEndInfo* pSubpassEndInfo)
4997 {
4998 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
4999 }
5000
5001 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
5002 {
5003 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
5004 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
5005 if (!radv_get_shader(pipeline, stage))
5006 continue;
5007
5008 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
5009 if (loc->sgpr_idx == -1)
5010 continue;
5011 uint32_t base_reg = pipeline->user_data_0[stage];
5012 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
5013
5014 }
5015 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
5016 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
5017 if (loc->sgpr_idx != -1) {
5018 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
5019 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
5020 }
5021 }
5022 }
5023
5024 static void
5025 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
5026 uint32_t vertex_count,
5027 bool use_opaque)
5028 {
5029 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
5030 radeon_emit(cmd_buffer->cs, vertex_count);
5031 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
5032 S_0287F0_USE_OPAQUE(use_opaque));
5033 }
5034
5035 static void
5036 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
5037 uint64_t index_va,
5038 uint32_t index_count)
5039 {
5040 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
5041 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
5042 radeon_emit(cmd_buffer->cs, index_va);
5043 radeon_emit(cmd_buffer->cs, index_va >> 32);
5044 radeon_emit(cmd_buffer->cs, index_count);
5045 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
5046 }
5047
5048 static void
5049 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
5050 bool indexed,
5051 uint32_t draw_count,
5052 uint64_t count_va,
5053 uint32_t stride)
5054 {
5055 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5056 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
5057 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
5058 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id;
5059 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
5060 bool predicating = cmd_buffer->state.predicating;
5061 assert(base_reg);
5062
5063 /* just reset draw state for vertex data */
5064 cmd_buffer->state.last_first_instance = -1;
5065 cmd_buffer->state.last_num_instances = -1;
5066 cmd_buffer->state.last_vertex_offset = -1;
5067
5068 if (draw_count == 1 && !count_va && !draw_id_enable) {
5069 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
5070 PKT3_DRAW_INDIRECT, 3, predicating));
5071 radeon_emit(cs, 0);
5072 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
5073 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
5074 radeon_emit(cs, di_src_sel);
5075 } else {
5076 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
5077 PKT3_DRAW_INDIRECT_MULTI,
5078 8, predicating));
5079 radeon_emit(cs, 0);
5080 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
5081 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
5082 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
5083 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
5084 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
5085 radeon_emit(cs, draw_count); /* count */
5086 radeon_emit(cs, count_va); /* count_addr */
5087 radeon_emit(cs, count_va >> 32);
5088 radeon_emit(cs, stride); /* stride */
5089 radeon_emit(cs, di_src_sel);
5090 }
5091 }
5092
5093 static void
5094 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
5095 const struct radv_draw_info *info)
5096 {
5097 struct radv_cmd_state *state = &cmd_buffer->state;
5098 struct radeon_winsys *ws = cmd_buffer->device->ws;
5099 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5100
5101 if (info->indirect) {
5102 uint64_t va = radv_buffer_get_va(info->indirect->bo);
5103 uint64_t count_va = 0;
5104
5105 va += info->indirect->offset + info->indirect_offset;
5106
5107 radv_cs_add_buffer(ws, cs, info->indirect->bo);
5108
5109 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
5110 radeon_emit(cs, 1);
5111 radeon_emit(cs, va);
5112 radeon_emit(cs, va >> 32);
5113
5114 if (info->count_buffer) {
5115 count_va = radv_buffer_get_va(info->count_buffer->bo);
5116 count_va += info->count_buffer->offset +
5117 info->count_buffer_offset;
5118
5119 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
5120 }
5121
5122 if (!state->subpass->view_mask) {
5123 radv_cs_emit_indirect_draw_packet(cmd_buffer,
5124 info->indexed,
5125 info->count,
5126 count_va,
5127 info->stride);
5128 } else {
5129 unsigned i;
5130 for_each_bit(i, state->subpass->view_mask) {
5131 radv_emit_view_index(cmd_buffer, i);
5132
5133 radv_cs_emit_indirect_draw_packet(cmd_buffer,
5134 info->indexed,
5135 info->count,
5136 count_va,
5137 info->stride);
5138 }
5139 }
5140 } else {
5141 assert(state->pipeline->graphics.vtx_base_sgpr);
5142
5143 if (info->vertex_offset != state->last_vertex_offset ||
5144 info->first_instance != state->last_first_instance) {
5145 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
5146 state->pipeline->graphics.vtx_emit_num);
5147
5148 radeon_emit(cs, info->vertex_offset);
5149 radeon_emit(cs, info->first_instance);
5150 if (state->pipeline->graphics.vtx_emit_num == 3)
5151 radeon_emit(cs, 0);
5152 state->last_first_instance = info->first_instance;
5153 state->last_vertex_offset = info->vertex_offset;
5154 }
5155
5156 if (state->last_num_instances != info->instance_count) {
5157 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
5158 radeon_emit(cs, info->instance_count);
5159 state->last_num_instances = info->instance_count;
5160 }
5161
5162 if (info->indexed) {
5163 int index_size = radv_get_vgt_index_size(state->index_type);
5164 uint64_t index_va;
5165
5166 /* Skip draw calls with 0-sized index buffers. They
5167 * cause a hang on some chips, like Navi10-14.
5168 */
5169 if (!cmd_buffer->state.max_index_count)
5170 return;
5171
5172 index_va = state->index_va;
5173 index_va += info->first_index * index_size;
5174
5175 if (!state->subpass->view_mask) {
5176 radv_cs_emit_draw_indexed_packet(cmd_buffer,
5177 index_va,
5178 info->count);
5179 } else {
5180 unsigned i;
5181 for_each_bit(i, state->subpass->view_mask) {
5182 radv_emit_view_index(cmd_buffer, i);
5183
5184 radv_cs_emit_draw_indexed_packet(cmd_buffer,
5185 index_va,
5186 info->count);
5187 }
5188 }
5189 } else {
5190 if (!state->subpass->view_mask) {
5191 radv_cs_emit_draw_packet(cmd_buffer,
5192 info->count,
5193 !!info->strmout_buffer);
5194 } else {
5195 unsigned i;
5196 for_each_bit(i, state->subpass->view_mask) {
5197 radv_emit_view_index(cmd_buffer, i);
5198
5199 radv_cs_emit_draw_packet(cmd_buffer,
5200 info->count,
5201 !!info->strmout_buffer);
5202 }
5203 }
5204 }
5205 }
5206 }
5207
5208 /*
5209 * Vega and raven have a bug which triggers if there are multiple context
5210 * register contexts active at the same time with different scissor values.
5211 *
5212 * There are two possible workarounds:
5213 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
5214 * there is only ever 1 active set of scissor values at the same time.
5215 *
5216 * 2) Whenever the hardware switches contexts we have to set the scissor
5217 * registers again even if it is a noop. That way the new context gets
5218 * the correct scissor values.
5219 *
5220 * This implements option 2. radv_need_late_scissor_emission needs to
5221 * return true on affected HW if radv_emit_all_graphics_states sets
5222 * any context registers.
5223 */
5224 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
5225 const struct radv_draw_info *info)
5226 {
5227 struct radv_cmd_state *state = &cmd_buffer->state;
5228
5229 if (!cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
5230 return false;
5231
5232 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
5233 return true;
5234
5235 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
5236
5237 /* Index, vertex and streamout buffers don't change context regs, and
5238 * pipeline is already handled.
5239 */
5240 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
5241 RADV_CMD_DIRTY_VERTEX_BUFFER |
5242 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
5243 RADV_CMD_DIRTY_PIPELINE);
5244
5245 if (cmd_buffer->state.dirty & used_states)
5246 return true;
5247
5248 uint32_t primitive_reset_index =
5249 radv_get_primitive_reset_index(cmd_buffer);
5250
5251 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
5252 primitive_reset_index != state->last_primitive_reset_index)
5253 return true;
5254
5255 return false;
5256 }
5257
5258 static void
5259 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
5260 const struct radv_draw_info *info)
5261 {
5262 bool late_scissor_emission;
5263
5264 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
5265 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
5266 radv_emit_rbplus_state(cmd_buffer);
5267
5268 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
5269 radv_emit_graphics_pipeline(cmd_buffer);
5270
5271 /* This should be before the cmd_buffer->state.dirty is cleared
5272 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
5273 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
5274 late_scissor_emission =
5275 radv_need_late_scissor_emission(cmd_buffer, info);
5276
5277 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
5278 radv_emit_framebuffer_state(cmd_buffer);
5279
5280 if (info->indexed) {
5281 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
5282 radv_emit_index_buffer(cmd_buffer, info->indirect);
5283 } else {
5284 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
5285 * so the state must be re-emitted before the next indexed
5286 * draw.
5287 */
5288 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
5289 cmd_buffer->state.last_index_type = -1;
5290 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
5291 }
5292 }
5293
5294 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
5295
5296 radv_emit_draw_registers(cmd_buffer, info);
5297
5298 if (late_scissor_emission)
5299 radv_emit_scissor(cmd_buffer);
5300 }
5301
5302 static void
5303 radv_draw(struct radv_cmd_buffer *cmd_buffer,
5304 const struct radv_draw_info *info)
5305 {
5306 struct radeon_info *rad_info =
5307 &cmd_buffer->device->physical_device->rad_info;
5308 bool has_prefetch =
5309 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
5310 bool pipeline_is_dirty =
5311 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
5312 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
5313
5314 ASSERTED unsigned cdw_max =
5315 radeon_check_space(cmd_buffer->device->ws,
5316 cmd_buffer->cs, 4096);
5317
5318 if (likely(!info->indirect)) {
5319 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
5320 * no workaround for indirect draws, but we can at least skip
5321 * direct draws.
5322 */
5323 if (unlikely(!info->instance_count))
5324 return;
5325
5326 /* Handle count == 0. */
5327 if (unlikely(!info->count && !info->strmout_buffer))
5328 return;
5329 }
5330
5331 radv_describe_draw(cmd_buffer);
5332
5333 /* Use optimal packet order based on whether we need to sync the
5334 * pipeline.
5335 */
5336 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5337 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5338 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
5339 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
5340 /* If we have to wait for idle, set all states first, so that
5341 * all SET packets are processed in parallel with previous draw
5342 * calls. Then upload descriptors, set shader pointers, and
5343 * draw, and prefetch at the end. This ensures that the time
5344 * the CUs are idle is very short. (there are only SET_SH
5345 * packets between the wait and the draw)
5346 */
5347 radv_emit_all_graphics_states(cmd_buffer, info);
5348 si_emit_cache_flush(cmd_buffer);
5349 /* <-- CUs are idle here --> */
5350
5351 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
5352
5353 radv_emit_draw_packets(cmd_buffer, info);
5354 /* <-- CUs are busy here --> */
5355
5356 /* Start prefetches after the draw has been started. Both will
5357 * run in parallel, but starting the draw first is more
5358 * important.
5359 */
5360 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
5361 radv_emit_prefetch_L2(cmd_buffer,
5362 cmd_buffer->state.pipeline, false);
5363 }
5364 } else {
5365 /* If we don't wait for idle, start prefetches first, then set
5366 * states, and draw at the end.
5367 */
5368 si_emit_cache_flush(cmd_buffer);
5369
5370 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
5371 /* Only prefetch the vertex shader and VBO descriptors
5372 * in order to start the draw as soon as possible.
5373 */
5374 radv_emit_prefetch_L2(cmd_buffer,
5375 cmd_buffer->state.pipeline, true);
5376 }
5377
5378 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
5379
5380 radv_emit_all_graphics_states(cmd_buffer, info);
5381 radv_emit_draw_packets(cmd_buffer, info);
5382
5383 /* Prefetch the remaining shaders after the draw has been
5384 * started.
5385 */
5386 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
5387 radv_emit_prefetch_L2(cmd_buffer,
5388 cmd_buffer->state.pipeline, false);
5389 }
5390 }
5391
5392 /* Workaround for a VGT hang when streamout is enabled.
5393 * It must be done after drawing.
5394 */
5395 if (cmd_buffer->state.streamout.streamout_enabled &&
5396 (rad_info->family == CHIP_HAWAII ||
5397 rad_info->family == CHIP_TONGA ||
5398 rad_info->family == CHIP_FIJI)) {
5399 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
5400 }
5401
5402 assert(cmd_buffer->cs->cdw <= cdw_max);
5403 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
5404 }
5405
5406 void radv_CmdDraw(
5407 VkCommandBuffer commandBuffer,
5408 uint32_t vertexCount,
5409 uint32_t instanceCount,
5410 uint32_t firstVertex,
5411 uint32_t firstInstance)
5412 {
5413 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5414 struct radv_draw_info info = {};
5415
5416 info.count = vertexCount;
5417 info.instance_count = instanceCount;
5418 info.first_instance = firstInstance;
5419 info.vertex_offset = firstVertex;
5420
5421 radv_draw(cmd_buffer, &info);
5422 }
5423
5424 void radv_CmdDrawIndexed(
5425 VkCommandBuffer commandBuffer,
5426 uint32_t indexCount,
5427 uint32_t instanceCount,
5428 uint32_t firstIndex,
5429 int32_t vertexOffset,
5430 uint32_t firstInstance)
5431 {
5432 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5433 struct radv_draw_info info = {};
5434
5435 info.indexed = true;
5436 info.count = indexCount;
5437 info.instance_count = instanceCount;
5438 info.first_index = firstIndex;
5439 info.vertex_offset = vertexOffset;
5440 info.first_instance = firstInstance;
5441
5442 radv_draw(cmd_buffer, &info);
5443 }
5444
5445 void radv_CmdDrawIndirect(
5446 VkCommandBuffer commandBuffer,
5447 VkBuffer _buffer,
5448 VkDeviceSize offset,
5449 uint32_t drawCount,
5450 uint32_t stride)
5451 {
5452 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5453 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5454 struct radv_draw_info info = {};
5455
5456 info.count = drawCount;
5457 info.indirect = buffer;
5458 info.indirect_offset = offset;
5459 info.stride = stride;
5460
5461 radv_draw(cmd_buffer, &info);
5462 }
5463
5464 void radv_CmdDrawIndexedIndirect(
5465 VkCommandBuffer commandBuffer,
5466 VkBuffer _buffer,
5467 VkDeviceSize offset,
5468 uint32_t drawCount,
5469 uint32_t stride)
5470 {
5471 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5472 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5473 struct radv_draw_info info = {};
5474
5475 info.indexed = true;
5476 info.count = drawCount;
5477 info.indirect = buffer;
5478 info.indirect_offset = offset;
5479 info.stride = stride;
5480
5481 radv_draw(cmd_buffer, &info);
5482 }
5483
5484 void radv_CmdDrawIndirectCount(
5485 VkCommandBuffer commandBuffer,
5486 VkBuffer _buffer,
5487 VkDeviceSize offset,
5488 VkBuffer _countBuffer,
5489 VkDeviceSize countBufferOffset,
5490 uint32_t maxDrawCount,
5491 uint32_t stride)
5492 {
5493 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5494 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5495 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
5496 struct radv_draw_info info = {};
5497
5498 info.count = maxDrawCount;
5499 info.indirect = buffer;
5500 info.indirect_offset = offset;
5501 info.count_buffer = count_buffer;
5502 info.count_buffer_offset = countBufferOffset;
5503 info.stride = stride;
5504
5505 radv_draw(cmd_buffer, &info);
5506 }
5507
5508 void radv_CmdDrawIndexedIndirectCount(
5509 VkCommandBuffer commandBuffer,
5510 VkBuffer _buffer,
5511 VkDeviceSize offset,
5512 VkBuffer _countBuffer,
5513 VkDeviceSize countBufferOffset,
5514 uint32_t maxDrawCount,
5515 uint32_t stride)
5516 {
5517 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5518 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5519 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
5520 struct radv_draw_info info = {};
5521
5522 info.indexed = true;
5523 info.count = maxDrawCount;
5524 info.indirect = buffer;
5525 info.indirect_offset = offset;
5526 info.count_buffer = count_buffer;
5527 info.count_buffer_offset = countBufferOffset;
5528 info.stride = stride;
5529
5530 radv_draw(cmd_buffer, &info);
5531 }
5532
5533 struct radv_dispatch_info {
5534 /**
5535 * Determine the layout of the grid (in block units) to be used.
5536 */
5537 uint32_t blocks[3];
5538
5539 /**
5540 * A starting offset for the grid. If unaligned is set, the offset
5541 * must still be aligned.
5542 */
5543 uint32_t offsets[3];
5544 /**
5545 * Whether it's an unaligned compute dispatch.
5546 */
5547 bool unaligned;
5548
5549 /**
5550 * Indirect compute parameters resource.
5551 */
5552 struct radv_buffer *indirect;
5553 uint64_t indirect_offset;
5554 };
5555
5556 static void
5557 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
5558 const struct radv_dispatch_info *info)
5559 {
5560 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
5561 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
5562 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
5563 struct radeon_winsys *ws = cmd_buffer->device->ws;
5564 bool predicating = cmd_buffer->state.predicating;
5565 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5566 struct radv_userdata_info *loc;
5567
5568 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
5569 AC_UD_CS_GRID_SIZE);
5570
5571 ASSERTED unsigned cdw_max = radeon_check_space(ws, cs, 25);
5572
5573 if (compute_shader->info.wave_size == 32) {
5574 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
5575 dispatch_initiator |= S_00B800_CS_W32_EN(1);
5576 }
5577
5578 if (info->indirect) {
5579 uint64_t va = radv_buffer_get_va(info->indirect->bo);
5580
5581 va += info->indirect->offset + info->indirect_offset;
5582
5583 radv_cs_add_buffer(ws, cs, info->indirect->bo);
5584
5585 if (loc->sgpr_idx != -1) {
5586 for (unsigned i = 0; i < 3; ++i) {
5587 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5588 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5589 COPY_DATA_DST_SEL(COPY_DATA_REG));
5590 radeon_emit(cs, (va + 4 * i));
5591 radeon_emit(cs, (va + 4 * i) >> 32);
5592 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
5593 + loc->sgpr_idx * 4) >> 2) + i);
5594 radeon_emit(cs, 0);
5595 }
5596 }
5597
5598 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
5599 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
5600 PKT3_SHADER_TYPE_S(1));
5601 radeon_emit(cs, va);
5602 radeon_emit(cs, va >> 32);
5603 radeon_emit(cs, dispatch_initiator);
5604 } else {
5605 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
5606 PKT3_SHADER_TYPE_S(1));
5607 radeon_emit(cs, 1);
5608 radeon_emit(cs, va);
5609 radeon_emit(cs, va >> 32);
5610
5611 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
5612 PKT3_SHADER_TYPE_S(1));
5613 radeon_emit(cs, 0);
5614 radeon_emit(cs, dispatch_initiator);
5615 }
5616 } else {
5617 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
5618 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
5619
5620 if (info->unaligned) {
5621 unsigned *cs_block_size = compute_shader->info.cs.block_size;
5622 unsigned remainder[3];
5623
5624 /* If aligned, these should be an entire block size,
5625 * not 0.
5626 */
5627 remainder[0] = blocks[0] + cs_block_size[0] -
5628 align_u32_npot(blocks[0], cs_block_size[0]);
5629 remainder[1] = blocks[1] + cs_block_size[1] -
5630 align_u32_npot(blocks[1], cs_block_size[1]);
5631 remainder[2] = blocks[2] + cs_block_size[2] -
5632 align_u32_npot(blocks[2], cs_block_size[2]);
5633
5634 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
5635 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
5636 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
5637
5638 for(unsigned i = 0; i < 3; ++i) {
5639 assert(offsets[i] % cs_block_size[i] == 0);
5640 offsets[i] /= cs_block_size[i];
5641 }
5642
5643 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
5644 radeon_emit(cs,
5645 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
5646 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
5647 radeon_emit(cs,
5648 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
5649 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
5650 radeon_emit(cs,
5651 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
5652 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
5653
5654 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
5655 }
5656
5657 if (loc->sgpr_idx != -1) {
5658 assert(loc->num_sgprs == 3);
5659
5660 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
5661 loc->sgpr_idx * 4, 3);
5662 radeon_emit(cs, blocks[0]);
5663 radeon_emit(cs, blocks[1]);
5664 radeon_emit(cs, blocks[2]);
5665 }
5666
5667 if (offsets[0] || offsets[1] || offsets[2]) {
5668 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
5669 radeon_emit(cs, offsets[0]);
5670 radeon_emit(cs, offsets[1]);
5671 radeon_emit(cs, offsets[2]);
5672
5673 /* The blocks in the packet are not counts but end values. */
5674 for (unsigned i = 0; i < 3; ++i)
5675 blocks[i] += offsets[i];
5676 } else {
5677 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
5678 }
5679
5680 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
5681 PKT3_SHADER_TYPE_S(1));
5682 radeon_emit(cs, blocks[0]);
5683 radeon_emit(cs, blocks[1]);
5684 radeon_emit(cs, blocks[2]);
5685 radeon_emit(cs, dispatch_initiator);
5686 }
5687
5688 assert(cmd_buffer->cs->cdw <= cdw_max);
5689 }
5690
5691 static void
5692 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
5693 {
5694 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
5695 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
5696 }
5697
5698 static void
5699 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
5700 const struct radv_dispatch_info *info)
5701 {
5702 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
5703 bool has_prefetch =
5704 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
5705 bool pipeline_is_dirty = pipeline &&
5706 pipeline != cmd_buffer->state.emitted_compute_pipeline;
5707
5708 radv_describe_dispatch(cmd_buffer, 8, 8, 8);
5709
5710 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5711 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5712 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
5713 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
5714 /* If we have to wait for idle, set all states first, so that
5715 * all SET packets are processed in parallel with previous draw
5716 * calls. Then upload descriptors, set shader pointers, and
5717 * dispatch, and prefetch at the end. This ensures that the
5718 * time the CUs are idle is very short. (there are only SET_SH
5719 * packets between the wait and the draw)
5720 */
5721 radv_emit_compute_pipeline(cmd_buffer);
5722 si_emit_cache_flush(cmd_buffer);
5723 /* <-- CUs are idle here --> */
5724
5725 radv_upload_compute_shader_descriptors(cmd_buffer);
5726
5727 radv_emit_dispatch_packets(cmd_buffer, info);
5728 /* <-- CUs are busy here --> */
5729
5730 /* Start prefetches after the dispatch has been started. Both
5731 * will run in parallel, but starting the dispatch first is
5732 * more important.
5733 */
5734 if (has_prefetch && pipeline_is_dirty) {
5735 radv_emit_shader_prefetch(cmd_buffer,
5736 pipeline->shaders[MESA_SHADER_COMPUTE]);
5737 }
5738 } else {
5739 /* If we don't wait for idle, start prefetches first, then set
5740 * states, and dispatch at the end.
5741 */
5742 si_emit_cache_flush(cmd_buffer);
5743
5744 if (has_prefetch && pipeline_is_dirty) {
5745 radv_emit_shader_prefetch(cmd_buffer,
5746 pipeline->shaders[MESA_SHADER_COMPUTE]);
5747 }
5748
5749 radv_upload_compute_shader_descriptors(cmd_buffer);
5750
5751 radv_emit_compute_pipeline(cmd_buffer);
5752 radv_emit_dispatch_packets(cmd_buffer, info);
5753 }
5754
5755 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
5756 }
5757
5758 void radv_CmdDispatchBase(
5759 VkCommandBuffer commandBuffer,
5760 uint32_t base_x,
5761 uint32_t base_y,
5762 uint32_t base_z,
5763 uint32_t x,
5764 uint32_t y,
5765 uint32_t z)
5766 {
5767 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5768 struct radv_dispatch_info info = {};
5769
5770 info.blocks[0] = x;
5771 info.blocks[1] = y;
5772 info.blocks[2] = z;
5773
5774 info.offsets[0] = base_x;
5775 info.offsets[1] = base_y;
5776 info.offsets[2] = base_z;
5777 radv_dispatch(cmd_buffer, &info);
5778 }
5779
5780 void radv_CmdDispatch(
5781 VkCommandBuffer commandBuffer,
5782 uint32_t x,
5783 uint32_t y,
5784 uint32_t z)
5785 {
5786 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
5787 }
5788
5789 void radv_CmdDispatchIndirect(
5790 VkCommandBuffer commandBuffer,
5791 VkBuffer _buffer,
5792 VkDeviceSize offset)
5793 {
5794 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5795 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5796 struct radv_dispatch_info info = {};
5797
5798 info.indirect = buffer;
5799 info.indirect_offset = offset;
5800
5801 radv_dispatch(cmd_buffer, &info);
5802 }
5803
5804 void radv_unaligned_dispatch(
5805 struct radv_cmd_buffer *cmd_buffer,
5806 uint32_t x,
5807 uint32_t y,
5808 uint32_t z)
5809 {
5810 struct radv_dispatch_info info = {};
5811
5812 info.blocks[0] = x;
5813 info.blocks[1] = y;
5814 info.blocks[2] = z;
5815 info.unaligned = 1;
5816
5817 radv_dispatch(cmd_buffer, &info);
5818 }
5819
5820 void
5821 radv_cmd_buffer_end_render_pass(struct radv_cmd_buffer *cmd_buffer)
5822 {
5823 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
5824 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
5825
5826 cmd_buffer->state.pass = NULL;
5827 cmd_buffer->state.subpass = NULL;
5828 cmd_buffer->state.attachments = NULL;
5829 cmd_buffer->state.framebuffer = NULL;
5830 cmd_buffer->state.subpass_sample_locs = NULL;
5831 }
5832
5833 void radv_CmdEndRenderPass(
5834 VkCommandBuffer commandBuffer)
5835 {
5836 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5837
5838 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
5839
5840 radv_cmd_buffer_end_subpass(cmd_buffer);
5841
5842 radv_cmd_buffer_end_render_pass(cmd_buffer);
5843 }
5844
5845 void radv_CmdEndRenderPass2(
5846 VkCommandBuffer commandBuffer,
5847 const VkSubpassEndInfo* pSubpassEndInfo)
5848 {
5849 radv_CmdEndRenderPass(commandBuffer);
5850 }
5851
5852 /*
5853 * For HTILE we have the following interesting clear words:
5854 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
5855 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
5856 * 0xfffffff0: Clear depth to 1.0
5857 * 0x00000000: Clear depth to 0.0
5858 */
5859 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
5860 struct radv_image *image,
5861 const VkImageSubresourceRange *range)
5862 {
5863 assert(range->baseMipLevel == 0);
5864 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
5865 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
5866 struct radv_cmd_state *state = &cmd_buffer->state;
5867 uint32_t htile_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
5868 VkClearDepthStencilValue value = {};
5869 struct radv_barrier_data barrier = {};
5870
5871 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5872 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5873
5874 barrier.layout_transitions.init_mask_ram = 1;
5875 radv_describe_layout_transition(cmd_buffer, &barrier);
5876
5877 state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, htile_value);
5878
5879 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5880
5881 if (vk_format_is_stencil(image->vk_format))
5882 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
5883
5884 radv_set_ds_clear_metadata(cmd_buffer, image, range, value, aspects);
5885
5886 if (radv_image_is_tc_compat_htile(image)) {
5887 /* Initialize the TC-compat metada value to 0 because by
5888 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
5889 * need have to conditionally update its value when performing
5890 * a fast depth clear.
5891 */
5892 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, range, 0);
5893 }
5894 }
5895
5896 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
5897 struct radv_image *image,
5898 VkImageLayout src_layout,
5899 bool src_render_loop,
5900 VkImageLayout dst_layout,
5901 bool dst_render_loop,
5902 unsigned src_queue_mask,
5903 unsigned dst_queue_mask,
5904 const VkImageSubresourceRange *range,
5905 struct radv_sample_locations_state *sample_locs)
5906 {
5907 if (!radv_image_has_htile(image))
5908 return;
5909
5910 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5911 radv_initialize_htile(cmd_buffer, image, range);
5912 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5913 radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5914 radv_initialize_htile(cmd_buffer, image, range);
5915 } else if (radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5916 !radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5917 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5918 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5919
5920 radv_decompress_depth_stencil(cmd_buffer, image, range,
5921 sample_locs);
5922
5923 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5924 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5925 }
5926 }
5927
5928 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
5929 struct radv_image *image,
5930 const VkImageSubresourceRange *range,
5931 uint32_t value)
5932 {
5933 struct radv_cmd_state *state = &cmd_buffer->state;
5934 struct radv_barrier_data barrier = {};
5935
5936 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5937 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5938
5939 barrier.layout_transitions.init_mask_ram = 1;
5940 radv_describe_layout_transition(cmd_buffer, &barrier);
5941
5942 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, range, value);
5943
5944 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5945 }
5946
5947 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
5948 struct radv_image *image,
5949 const VkImageSubresourceRange *range)
5950 {
5951 struct radv_cmd_state *state = &cmd_buffer->state;
5952 static const uint32_t fmask_clear_values[4] = {
5953 0x00000000,
5954 0x02020202,
5955 0xE4E4E4E4,
5956 0x76543210
5957 };
5958 uint32_t log2_samples = util_logbase2(image->info.samples);
5959 uint32_t value = fmask_clear_values[log2_samples];
5960 struct radv_barrier_data barrier = {};
5961
5962 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5963 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5964
5965 barrier.layout_transitions.init_mask_ram = 1;
5966 radv_describe_layout_transition(cmd_buffer, &barrier);
5967
5968 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, range, value);
5969
5970 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5971 }
5972
5973 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
5974 struct radv_image *image,
5975 const VkImageSubresourceRange *range, uint32_t value)
5976 {
5977 struct radv_cmd_state *state = &cmd_buffer->state;
5978 struct radv_barrier_data barrier = {};
5979 unsigned size = 0;
5980
5981 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5982 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5983
5984 barrier.layout_transitions.init_mask_ram = 1;
5985 radv_describe_layout_transition(cmd_buffer, &barrier);
5986
5987 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
5988
5989 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) {
5990 /* When DCC is enabled with mipmaps, some levels might not
5991 * support fast clears and we have to initialize them as "fully
5992 * expanded".
5993 */
5994 /* Compute the size of all fast clearable DCC levels. */
5995 for (unsigned i = 0; i < image->planes[0].surface.num_dcc_levels; i++) {
5996 struct legacy_surf_level *surf_level =
5997 &image->planes[0].surface.u.legacy.level[i];
5998 unsigned dcc_fast_clear_size =
5999 surf_level->dcc_slice_fast_clear_size * image->info.array_size;
6000
6001 if (!dcc_fast_clear_size)
6002 break;
6003
6004 size = surf_level->dcc_offset + dcc_fast_clear_size;
6005 }
6006
6007 /* Initialize the mipmap levels without DCC. */
6008 if (size != image->planes[0].surface.dcc_size) {
6009 state->flush_bits |=
6010 radv_fill_buffer(cmd_buffer, image->bo,
6011 image->offset + image->planes[0].surface.dcc_offset + size,
6012 image->planes[0].surface.dcc_size - size,
6013 0xffffffff);
6014 }
6015 }
6016
6017 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
6018 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
6019 }
6020
6021 /**
6022 * Initialize DCC/FMASK/CMASK metadata for a color image.
6023 */
6024 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
6025 struct radv_image *image,
6026 VkImageLayout src_layout,
6027 bool src_render_loop,
6028 VkImageLayout dst_layout,
6029 bool dst_render_loop,
6030 unsigned src_queue_mask,
6031 unsigned dst_queue_mask,
6032 const VkImageSubresourceRange *range)
6033 {
6034 if (radv_image_has_cmask(image)) {
6035 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
6036
6037 /* TODO: clarify this. */
6038 if (radv_image_has_fmask(image)) {
6039 value = 0xccccccccu;
6040 }
6041
6042 radv_initialise_cmask(cmd_buffer, image, range, value);
6043 }
6044
6045 if (radv_image_has_fmask(image)) {
6046 radv_initialize_fmask(cmd_buffer, image, range);
6047 }
6048
6049 if (radv_dcc_enabled(image, range->baseMipLevel)) {
6050 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
6051 bool need_decompress_pass = false;
6052
6053 if (radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout,
6054 dst_render_loop,
6055 dst_queue_mask)) {
6056 value = 0x20202020u;
6057 need_decompress_pass = true;
6058 }
6059
6060 radv_initialize_dcc(cmd_buffer, image, range, value);
6061
6062 radv_update_fce_metadata(cmd_buffer, image, range,
6063 need_decompress_pass);
6064 }
6065
6066 if (radv_image_has_cmask(image) ||
6067 radv_dcc_enabled(image, range->baseMipLevel)) {
6068 uint32_t color_values[2] = {};
6069 radv_set_color_clear_metadata(cmd_buffer, image, range,
6070 color_values);
6071 }
6072 }
6073
6074 /**
6075 * Handle color image transitions for DCC/FMASK/CMASK.
6076 */
6077 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
6078 struct radv_image *image,
6079 VkImageLayout src_layout,
6080 bool src_render_loop,
6081 VkImageLayout dst_layout,
6082 bool dst_render_loop,
6083 unsigned src_queue_mask,
6084 unsigned dst_queue_mask,
6085 const VkImageSubresourceRange *range)
6086 {
6087 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
6088 radv_init_color_image_metadata(cmd_buffer, image,
6089 src_layout, src_render_loop,
6090 dst_layout, dst_render_loop,
6091 src_queue_mask, dst_queue_mask,
6092 range);
6093 return;
6094 }
6095
6096 if (radv_dcc_enabled(image, range->baseMipLevel)) {
6097 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
6098 radv_initialize_dcc(cmd_buffer, image, range, 0xffffffffu);
6099 } else if (radv_layout_dcc_compressed(cmd_buffer->device, image, src_layout, src_render_loop, src_queue_mask) &&
6100 !radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout, dst_render_loop, dst_queue_mask)) {
6101 radv_decompress_dcc(cmd_buffer, image, range);
6102 } else if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
6103 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
6104 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
6105 }
6106 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
6107 bool fce_eliminate = false, fmask_expand = false;
6108
6109 if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
6110 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
6111 fce_eliminate = true;
6112 }
6113
6114 if (radv_image_has_fmask(image)) {
6115 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
6116 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
6117 /* A FMASK decompress is required before doing
6118 * a MSAA decompress using FMASK.
6119 */
6120 fmask_expand = true;
6121 }
6122 }
6123
6124 if (fce_eliminate || fmask_expand)
6125 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
6126
6127 if (fmask_expand) {
6128 struct radv_barrier_data barrier = {};
6129 barrier.layout_transitions.fmask_color_expand = 1;
6130 radv_describe_layout_transition(cmd_buffer, &barrier);
6131
6132 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
6133 }
6134 }
6135 }
6136
6137 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
6138 struct radv_image *image,
6139 VkImageLayout src_layout,
6140 bool src_render_loop,
6141 VkImageLayout dst_layout,
6142 bool dst_render_loop,
6143 uint32_t src_family,
6144 uint32_t dst_family,
6145 const VkImageSubresourceRange *range,
6146 struct radv_sample_locations_state *sample_locs)
6147 {
6148 if (image->exclusive && src_family != dst_family) {
6149 /* This is an acquire or a release operation and there will be
6150 * a corresponding release/acquire. Do the transition in the
6151 * most flexible queue. */
6152
6153 assert(src_family == cmd_buffer->queue_family_index ||
6154 dst_family == cmd_buffer->queue_family_index);
6155
6156 if (src_family == VK_QUEUE_FAMILY_EXTERNAL ||
6157 src_family == VK_QUEUE_FAMILY_FOREIGN_EXT)
6158 return;
6159
6160 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
6161 return;
6162
6163 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
6164 (src_family == RADV_QUEUE_GENERAL ||
6165 dst_family == RADV_QUEUE_GENERAL))
6166 return;
6167 }
6168
6169 if (src_layout == dst_layout)
6170 return;
6171
6172 unsigned src_queue_mask =
6173 radv_image_queue_family_mask(image, src_family,
6174 cmd_buffer->queue_family_index);
6175 unsigned dst_queue_mask =
6176 radv_image_queue_family_mask(image, dst_family,
6177 cmd_buffer->queue_family_index);
6178
6179 if (vk_format_is_depth(image->vk_format)) {
6180 radv_handle_depth_image_transition(cmd_buffer, image,
6181 src_layout, src_render_loop,
6182 dst_layout, dst_render_loop,
6183 src_queue_mask, dst_queue_mask,
6184 range, sample_locs);
6185 } else {
6186 radv_handle_color_image_transition(cmd_buffer, image,
6187 src_layout, src_render_loop,
6188 dst_layout, dst_render_loop,
6189 src_queue_mask, dst_queue_mask,
6190 range);
6191 }
6192 }
6193
6194 struct radv_barrier_info {
6195 enum rgp_barrier_reason reason;
6196 uint32_t eventCount;
6197 const VkEvent *pEvents;
6198 VkPipelineStageFlags srcStageMask;
6199 VkPipelineStageFlags dstStageMask;
6200 };
6201
6202 static void
6203 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
6204 uint32_t memoryBarrierCount,
6205 const VkMemoryBarrier *pMemoryBarriers,
6206 uint32_t bufferMemoryBarrierCount,
6207 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
6208 uint32_t imageMemoryBarrierCount,
6209 const VkImageMemoryBarrier *pImageMemoryBarriers,
6210 const struct radv_barrier_info *info)
6211 {
6212 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6213 enum radv_cmd_flush_bits src_flush_bits = 0;
6214 enum radv_cmd_flush_bits dst_flush_bits = 0;
6215
6216 radv_describe_barrier_start(cmd_buffer, info->reason);
6217
6218 for (unsigned i = 0; i < info->eventCount; ++i) {
6219 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
6220 uint64_t va = radv_buffer_get_va(event->bo);
6221
6222 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
6223
6224 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
6225
6226 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
6227 assert(cmd_buffer->cs->cdw <= cdw_max);
6228 }
6229
6230 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
6231 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
6232 NULL);
6233 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
6234 NULL);
6235 }
6236
6237 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
6238 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
6239 NULL);
6240 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
6241 NULL);
6242 }
6243
6244 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
6245 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
6246
6247 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
6248 image);
6249 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
6250 image);
6251 }
6252
6253 /* The Vulkan spec 1.1.98 says:
6254 *
6255 * "An execution dependency with only
6256 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
6257 * will only prevent that stage from executing in subsequently
6258 * submitted commands. As this stage does not perform any actual
6259 * execution, this is not observable - in effect, it does not delay
6260 * processing of subsequent commands. Similarly an execution dependency
6261 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
6262 * will effectively not wait for any prior commands to complete."
6263 */
6264 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
6265 radv_stage_flush(cmd_buffer, info->srcStageMask);
6266 cmd_buffer->state.flush_bits |= src_flush_bits;
6267
6268 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
6269 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
6270
6271 const struct VkSampleLocationsInfoEXT *sample_locs_info =
6272 vk_find_struct_const(pImageMemoryBarriers[i].pNext,
6273 SAMPLE_LOCATIONS_INFO_EXT);
6274 struct radv_sample_locations_state sample_locations = {};
6275
6276 if (sample_locs_info) {
6277 assert(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
6278 sample_locations.per_pixel = sample_locs_info->sampleLocationsPerPixel;
6279 sample_locations.grid_size = sample_locs_info->sampleLocationGridSize;
6280 sample_locations.count = sample_locs_info->sampleLocationsCount;
6281 typed_memcpy(&sample_locations.locations[0],
6282 sample_locs_info->pSampleLocations,
6283 sample_locs_info->sampleLocationsCount);
6284 }
6285
6286 radv_handle_image_transition(cmd_buffer, image,
6287 pImageMemoryBarriers[i].oldLayout,
6288 false, /* Outside of a renderpass we are never in a renderloop */
6289 pImageMemoryBarriers[i].newLayout,
6290 false, /* Outside of a renderpass we are never in a renderloop */
6291 pImageMemoryBarriers[i].srcQueueFamilyIndex,
6292 pImageMemoryBarriers[i].dstQueueFamilyIndex,
6293 &pImageMemoryBarriers[i].subresourceRange,
6294 sample_locs_info ? &sample_locations : NULL);
6295 }
6296
6297 /* Make sure CP DMA is idle because the driver might have performed a
6298 * DMA operation for copying or filling buffers/images.
6299 */
6300 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
6301 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
6302 si_cp_dma_wait_for_idle(cmd_buffer);
6303
6304 cmd_buffer->state.flush_bits |= dst_flush_bits;
6305
6306 radv_describe_barrier_end(cmd_buffer);
6307 }
6308
6309 void radv_CmdPipelineBarrier(
6310 VkCommandBuffer commandBuffer,
6311 VkPipelineStageFlags srcStageMask,
6312 VkPipelineStageFlags destStageMask,
6313 VkBool32 byRegion,
6314 uint32_t memoryBarrierCount,
6315 const VkMemoryBarrier* pMemoryBarriers,
6316 uint32_t bufferMemoryBarrierCount,
6317 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
6318 uint32_t imageMemoryBarrierCount,
6319 const VkImageMemoryBarrier* pImageMemoryBarriers)
6320 {
6321 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6322 struct radv_barrier_info info;
6323
6324 info.reason = RGP_BARRIER_EXTERNAL_CMD_PIPELINE_BARRIER;
6325 info.eventCount = 0;
6326 info.pEvents = NULL;
6327 info.srcStageMask = srcStageMask;
6328 info.dstStageMask = destStageMask;
6329
6330 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
6331 bufferMemoryBarrierCount, pBufferMemoryBarriers,
6332 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
6333 }
6334
6335
6336 static void write_event(struct radv_cmd_buffer *cmd_buffer,
6337 struct radv_event *event,
6338 VkPipelineStageFlags stageMask,
6339 unsigned value)
6340 {
6341 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6342 uint64_t va = radv_buffer_get_va(event->bo);
6343
6344 si_emit_cache_flush(cmd_buffer);
6345
6346 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
6347
6348 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 21);
6349
6350 /* Flags that only require a top-of-pipe event. */
6351 VkPipelineStageFlags top_of_pipe_flags =
6352 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
6353
6354 /* Flags that only require a post-index-fetch event. */
6355 VkPipelineStageFlags post_index_fetch_flags =
6356 top_of_pipe_flags |
6357 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
6358 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
6359
6360 /* Make sure CP DMA is idle because the driver might have performed a
6361 * DMA operation for copying or filling buffers/images.
6362 */
6363 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
6364 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
6365 si_cp_dma_wait_for_idle(cmd_buffer);
6366
6367 /* TODO: Emit EOS events for syncing PS/CS stages. */
6368
6369 if (!(stageMask & ~top_of_pipe_flags)) {
6370 /* Just need to sync the PFP engine. */
6371 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
6372 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
6373 S_370_WR_CONFIRM(1) |
6374 S_370_ENGINE_SEL(V_370_PFP));
6375 radeon_emit(cs, va);
6376 radeon_emit(cs, va >> 32);
6377 radeon_emit(cs, value);
6378 } else if (!(stageMask & ~post_index_fetch_flags)) {
6379 /* Sync ME because PFP reads index and indirect buffers. */
6380 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
6381 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
6382 S_370_WR_CONFIRM(1) |
6383 S_370_ENGINE_SEL(V_370_ME));
6384 radeon_emit(cs, va);
6385 radeon_emit(cs, va >> 32);
6386 radeon_emit(cs, value);
6387 } else {
6388 /* Otherwise, sync all prior GPU work using an EOP event. */
6389 si_cs_emit_write_event_eop(cs,
6390 cmd_buffer->device->physical_device->rad_info.chip_class,
6391 radv_cmd_buffer_uses_mec(cmd_buffer),
6392 V_028A90_BOTTOM_OF_PIPE_TS, 0,
6393 EOP_DST_SEL_MEM,
6394 EOP_DATA_SEL_VALUE_32BIT, va, value,
6395 cmd_buffer->gfx9_eop_bug_va);
6396 }
6397
6398 assert(cmd_buffer->cs->cdw <= cdw_max);
6399 }
6400
6401 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
6402 VkEvent _event,
6403 VkPipelineStageFlags stageMask)
6404 {
6405 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6406 RADV_FROM_HANDLE(radv_event, event, _event);
6407
6408 write_event(cmd_buffer, event, stageMask, 1);
6409 }
6410
6411 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
6412 VkEvent _event,
6413 VkPipelineStageFlags stageMask)
6414 {
6415 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6416 RADV_FROM_HANDLE(radv_event, event, _event);
6417
6418 write_event(cmd_buffer, event, stageMask, 0);
6419 }
6420
6421 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
6422 uint32_t eventCount,
6423 const VkEvent* pEvents,
6424 VkPipelineStageFlags srcStageMask,
6425 VkPipelineStageFlags dstStageMask,
6426 uint32_t memoryBarrierCount,
6427 const VkMemoryBarrier* pMemoryBarriers,
6428 uint32_t bufferMemoryBarrierCount,
6429 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
6430 uint32_t imageMemoryBarrierCount,
6431 const VkImageMemoryBarrier* pImageMemoryBarriers)
6432 {
6433 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6434 struct radv_barrier_info info;
6435
6436 info.reason = RGP_BARRIER_EXTERNAL_CMD_WAIT_EVENTS;
6437 info.eventCount = eventCount;
6438 info.pEvents = pEvents;
6439 info.srcStageMask = 0;
6440
6441 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
6442 bufferMemoryBarrierCount, pBufferMemoryBarriers,
6443 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
6444 }
6445
6446
6447 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
6448 uint32_t deviceMask)
6449 {
6450 /* No-op */
6451 }
6452
6453 /* VK_EXT_conditional_rendering */
6454 void radv_CmdBeginConditionalRenderingEXT(
6455 VkCommandBuffer commandBuffer,
6456 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
6457 {
6458 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6459 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
6460 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6461 bool draw_visible = true;
6462 uint64_t pred_value = 0;
6463 uint64_t va, new_va;
6464 unsigned pred_offset;
6465
6466 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
6467
6468 /* By default, if the 32-bit value at offset in buffer memory is zero,
6469 * then the rendering commands are discarded, otherwise they are
6470 * executed as normal. If the inverted flag is set, all commands are
6471 * discarded if the value is non zero.
6472 */
6473 if (pConditionalRenderingBegin->flags &
6474 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
6475 draw_visible = false;
6476 }
6477
6478 si_emit_cache_flush(cmd_buffer);
6479
6480 /* From the Vulkan spec 1.1.107:
6481 *
6482 * "If the 32-bit value at offset in buffer memory is zero, then the
6483 * rendering commands are discarded, otherwise they are executed as
6484 * normal. If the value of the predicate in buffer memory changes while
6485 * conditional rendering is active, the rendering commands may be
6486 * discarded in an implementation-dependent way. Some implementations
6487 * may latch the value of the predicate upon beginning conditional
6488 * rendering while others may read it before every rendering command."
6489 *
6490 * But, the AMD hardware treats the predicate as a 64-bit value which
6491 * means we need a workaround in the driver. Luckily, it's not required
6492 * to support if the value changes when predication is active.
6493 *
6494 * The workaround is as follows:
6495 * 1) allocate a 64-value in the upload BO and initialize it to 0
6496 * 2) copy the 32-bit predicate value to the upload BO
6497 * 3) use the new allocated VA address for predication
6498 *
6499 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
6500 * in ME (+ sync PFP) instead of PFP.
6501 */
6502 radv_cmd_buffer_upload_data(cmd_buffer, 8, 16, &pred_value, &pred_offset);
6503
6504 new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
6505
6506 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
6507 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
6508 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
6509 COPY_DATA_WR_CONFIRM);
6510 radeon_emit(cs, va);
6511 radeon_emit(cs, va >> 32);
6512 radeon_emit(cs, new_va);
6513 radeon_emit(cs, new_va >> 32);
6514
6515 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
6516 radeon_emit(cs, 0);
6517
6518 /* Enable predication for this command buffer. */
6519 si_emit_set_predication_state(cmd_buffer, draw_visible, new_va);
6520 cmd_buffer->state.predicating = true;
6521
6522 /* Store conditional rendering user info. */
6523 cmd_buffer->state.predication_type = draw_visible;
6524 cmd_buffer->state.predication_va = new_va;
6525 }
6526
6527 void radv_CmdEndConditionalRenderingEXT(
6528 VkCommandBuffer commandBuffer)
6529 {
6530 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6531
6532 /* Disable predication for this command buffer. */
6533 si_emit_set_predication_state(cmd_buffer, false, 0);
6534 cmd_buffer->state.predicating = false;
6535
6536 /* Reset conditional rendering user info. */
6537 cmd_buffer->state.predication_type = -1;
6538 cmd_buffer->state.predication_va = 0;
6539 }
6540
6541 /* VK_EXT_transform_feedback */
6542 void radv_CmdBindTransformFeedbackBuffersEXT(
6543 VkCommandBuffer commandBuffer,
6544 uint32_t firstBinding,
6545 uint32_t bindingCount,
6546 const VkBuffer* pBuffers,
6547 const VkDeviceSize* pOffsets,
6548 const VkDeviceSize* pSizes)
6549 {
6550 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6551 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
6552 uint8_t enabled_mask = 0;
6553
6554 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
6555 for (uint32_t i = 0; i < bindingCount; i++) {
6556 uint32_t idx = firstBinding + i;
6557
6558 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
6559 sb[idx].offset = pOffsets[i];
6560
6561 if (!pSizes || pSizes[i] == VK_WHOLE_SIZE) {
6562 sb[idx].size = sb[idx].buffer->size - sb[idx].offset;
6563 } else {
6564 sb[idx].size = pSizes[i];
6565 }
6566
6567 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
6568 sb[idx].buffer->bo);
6569
6570 enabled_mask |= 1 << idx;
6571 }
6572
6573 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
6574
6575 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
6576 }
6577
6578 static void
6579 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
6580 {
6581 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6582 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6583
6584 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
6585 radeon_emit(cs,
6586 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
6587 S_028B94_RAST_STREAM(0) |
6588 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
6589 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
6590 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
6591 radeon_emit(cs, so->hw_enabled_mask &
6592 so->enabled_stream_buffers_mask);
6593
6594 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6595 }
6596
6597 static void
6598 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
6599 {
6600 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6601 bool old_streamout_enabled = so->streamout_enabled;
6602 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
6603
6604 so->streamout_enabled = enable;
6605
6606 so->hw_enabled_mask = so->enabled_mask |
6607 (so->enabled_mask << 4) |
6608 (so->enabled_mask << 8) |
6609 (so->enabled_mask << 12);
6610
6611 if (!cmd_buffer->device->physical_device->use_ngg_streamout &&
6612 ((old_streamout_enabled != so->streamout_enabled) ||
6613 (old_hw_enabled_mask != so->hw_enabled_mask)))
6614 radv_emit_streamout_enable(cmd_buffer);
6615
6616 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6617 cmd_buffer->gds_needed = true;
6618 cmd_buffer->gds_oa_needed = true;
6619 }
6620 }
6621
6622 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
6623 {
6624 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6625 unsigned reg_strmout_cntl;
6626
6627 /* The register is at different places on different ASICs. */
6628 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
6629 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
6630 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
6631 } else {
6632 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
6633 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
6634 }
6635
6636 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
6637 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
6638
6639 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
6640 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
6641 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
6642 radeon_emit(cs, 0);
6643 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
6644 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
6645 radeon_emit(cs, 4); /* poll interval */
6646 }
6647
6648 static void
6649 radv_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
6650 uint32_t firstCounterBuffer,
6651 uint32_t counterBufferCount,
6652 const VkBuffer *pCounterBuffers,
6653 const VkDeviceSize *pCounterBufferOffsets)
6654
6655 {
6656 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
6657 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6658 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6659 uint32_t i;
6660
6661 radv_flush_vgt_streamout(cmd_buffer);
6662
6663 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6664 for_each_bit(i, so->enabled_mask) {
6665 int32_t counter_buffer_idx = i - firstCounterBuffer;
6666 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6667 counter_buffer_idx = -1;
6668
6669 /* AMD GCN binds streamout buffers as shader resources.
6670 * VGT only counts primitives and tells the shader through
6671 * SGPRs what to do.
6672 */
6673 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
6674 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
6675 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
6676
6677 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6678
6679 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6680 /* The array of counter buffers is optional. */
6681 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6682 uint64_t va = radv_buffer_get_va(buffer->bo);
6683
6684 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6685
6686 /* Append */
6687 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6688 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6689 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6690 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
6691 radeon_emit(cs, 0); /* unused */
6692 radeon_emit(cs, 0); /* unused */
6693 radeon_emit(cs, va); /* src address lo */
6694 radeon_emit(cs, va >> 32); /* src address hi */
6695
6696 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6697 } else {
6698 /* Start from the beginning. */
6699 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6700 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6701 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6702 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
6703 radeon_emit(cs, 0); /* unused */
6704 radeon_emit(cs, 0); /* unused */
6705 radeon_emit(cs, 0); /* unused */
6706 radeon_emit(cs, 0); /* unused */
6707 }
6708 }
6709
6710 radv_set_streamout_enable(cmd_buffer, true);
6711 }
6712
6713 static void
6714 gfx10_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
6715 uint32_t firstCounterBuffer,
6716 uint32_t counterBufferCount,
6717 const VkBuffer *pCounterBuffers,
6718 const VkDeviceSize *pCounterBufferOffsets)
6719 {
6720 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6721 unsigned last_target = util_last_bit(so->enabled_mask) - 1;
6722 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6723 uint32_t i;
6724
6725 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6726 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6727
6728 /* Sync because the next streamout operation will overwrite GDS and we
6729 * have to make sure it's idle.
6730 * TODO: Improve by tracking if there is a streamout operation in
6731 * flight.
6732 */
6733 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
6734 si_emit_cache_flush(cmd_buffer);
6735
6736 for_each_bit(i, so->enabled_mask) {
6737 int32_t counter_buffer_idx = i - firstCounterBuffer;
6738 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6739 counter_buffer_idx = -1;
6740
6741 bool append = counter_buffer_idx >= 0 &&
6742 pCounterBuffers && pCounterBuffers[counter_buffer_idx];
6743 uint64_t va = 0;
6744
6745 if (append) {
6746 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6747
6748 va += radv_buffer_get_va(buffer->bo);
6749 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6750
6751 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6752 }
6753
6754 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
6755 radeon_emit(cs, S_411_SRC_SEL(append ? V_411_SRC_ADDR_TC_L2 : V_411_DATA) |
6756 S_411_DST_SEL(V_411_GDS) |
6757 S_411_CP_SYNC(i == last_target));
6758 radeon_emit(cs, va);
6759 radeon_emit(cs, va >> 32);
6760 radeon_emit(cs, 4 * i); /* destination in GDS */
6761 radeon_emit(cs, 0);
6762 radeon_emit(cs, S_414_BYTE_COUNT_GFX9(4) |
6763 S_414_DISABLE_WR_CONFIRM_GFX9(i != last_target));
6764 }
6765
6766 radv_set_streamout_enable(cmd_buffer, true);
6767 }
6768
6769 void radv_CmdBeginTransformFeedbackEXT(
6770 VkCommandBuffer commandBuffer,
6771 uint32_t firstCounterBuffer,
6772 uint32_t counterBufferCount,
6773 const VkBuffer* pCounterBuffers,
6774 const VkDeviceSize* pCounterBufferOffsets)
6775 {
6776 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6777
6778 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6779 gfx10_emit_streamout_begin(cmd_buffer,
6780 firstCounterBuffer, counterBufferCount,
6781 pCounterBuffers, pCounterBufferOffsets);
6782 } else {
6783 radv_emit_streamout_begin(cmd_buffer,
6784 firstCounterBuffer, counterBufferCount,
6785 pCounterBuffers, pCounterBufferOffsets);
6786 }
6787 }
6788
6789 static void
6790 radv_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6791 uint32_t firstCounterBuffer,
6792 uint32_t counterBufferCount,
6793 const VkBuffer *pCounterBuffers,
6794 const VkDeviceSize *pCounterBufferOffsets)
6795 {
6796 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6797 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6798 uint32_t i;
6799
6800 radv_flush_vgt_streamout(cmd_buffer);
6801
6802 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6803 for_each_bit(i, so->enabled_mask) {
6804 int32_t counter_buffer_idx = i - firstCounterBuffer;
6805 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6806 counter_buffer_idx = -1;
6807
6808 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6809 /* The array of counters buffer is optional. */
6810 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6811 uint64_t va = radv_buffer_get_va(buffer->bo);
6812
6813 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6814
6815 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6816 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6817 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6818 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
6819 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
6820 radeon_emit(cs, va); /* dst address lo */
6821 radeon_emit(cs, va >> 32); /* dst address hi */
6822 radeon_emit(cs, 0); /* unused */
6823 radeon_emit(cs, 0); /* unused */
6824
6825 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6826 }
6827
6828 /* Deactivate transform feedback by zeroing the buffer size.
6829 * The counters (primitives generated, primitives emitted) may
6830 * be enabled even if there is not buffer bound. This ensures
6831 * that the primitives-emitted query won't increment.
6832 */
6833 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
6834
6835 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6836 }
6837
6838 radv_set_streamout_enable(cmd_buffer, false);
6839 }
6840
6841 static void
6842 gfx10_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6843 uint32_t firstCounterBuffer,
6844 uint32_t counterBufferCount,
6845 const VkBuffer *pCounterBuffers,
6846 const VkDeviceSize *pCounterBufferOffsets)
6847 {
6848 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6849 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6850 uint32_t i;
6851
6852 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6853 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6854
6855 for_each_bit(i, so->enabled_mask) {
6856 int32_t counter_buffer_idx = i - firstCounterBuffer;
6857 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6858 counter_buffer_idx = -1;
6859
6860 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6861 /* The array of counters buffer is optional. */
6862 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6863 uint64_t va = radv_buffer_get_va(buffer->bo);
6864
6865 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6866
6867 si_cs_emit_write_event_eop(cs,
6868 cmd_buffer->device->physical_device->rad_info.chip_class,
6869 radv_cmd_buffer_uses_mec(cmd_buffer),
6870 V_028A90_PS_DONE, 0,
6871 EOP_DST_SEL_TC_L2,
6872 EOP_DATA_SEL_GDS,
6873 va, EOP_DATA_GDS(i, 1), 0);
6874
6875 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6876 }
6877 }
6878
6879 radv_set_streamout_enable(cmd_buffer, false);
6880 }
6881
6882 void radv_CmdEndTransformFeedbackEXT(
6883 VkCommandBuffer commandBuffer,
6884 uint32_t firstCounterBuffer,
6885 uint32_t counterBufferCount,
6886 const VkBuffer* pCounterBuffers,
6887 const VkDeviceSize* pCounterBufferOffsets)
6888 {
6889 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6890
6891 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6892 gfx10_emit_streamout_end(cmd_buffer,
6893 firstCounterBuffer, counterBufferCount,
6894 pCounterBuffers, pCounterBufferOffsets);
6895 } else {
6896 radv_emit_streamout_end(cmd_buffer,
6897 firstCounterBuffer, counterBufferCount,
6898 pCounterBuffers, pCounterBufferOffsets);
6899 }
6900 }
6901
6902 void radv_CmdDrawIndirectByteCountEXT(
6903 VkCommandBuffer commandBuffer,
6904 uint32_t instanceCount,
6905 uint32_t firstInstance,
6906 VkBuffer _counterBuffer,
6907 VkDeviceSize counterBufferOffset,
6908 uint32_t counterOffset,
6909 uint32_t vertexStride)
6910 {
6911 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6912 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
6913 struct radv_draw_info info = {};
6914
6915 info.instance_count = instanceCount;
6916 info.first_instance = firstInstance;
6917 info.strmout_buffer = counterBuffer;
6918 info.strmout_buffer_offset = counterBufferOffset;
6919 info.stride = vertexStride;
6920
6921 radv_draw(cmd_buffer, &info);
6922 }
6923
6924 /* VK_AMD_buffer_marker */
6925 void radv_CmdWriteBufferMarkerAMD(
6926 VkCommandBuffer commandBuffer,
6927 VkPipelineStageFlagBits pipelineStage,
6928 VkBuffer dstBuffer,
6929 VkDeviceSize dstOffset,
6930 uint32_t marker)
6931 {
6932 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6933 RADV_FROM_HANDLE(radv_buffer, buffer, dstBuffer);
6934 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6935 uint64_t va = radv_buffer_get_va(buffer->bo) + dstOffset;
6936
6937 si_emit_cache_flush(cmd_buffer);
6938
6939 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 12);
6940
6941 if (!(pipelineStage & ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT)) {
6942 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
6943 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
6944 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
6945 COPY_DATA_WR_CONFIRM);
6946 radeon_emit(cs, marker);
6947 radeon_emit(cs, 0);
6948 radeon_emit(cs, va);
6949 radeon_emit(cs, va >> 32);
6950 } else {
6951 si_cs_emit_write_event_eop(cs,
6952 cmd_buffer->device->physical_device->rad_info.chip_class,
6953 radv_cmd_buffer_uses_mec(cmd_buffer),
6954 V_028A90_BOTTOM_OF_PIPE_TS, 0,
6955 EOP_DST_SEL_MEM,
6956 EOP_DATA_SEL_VALUE_32BIT,
6957 va, marker,
6958 cmd_buffer->gfx9_eop_bug_va);
6959 }
6960
6961 assert(cmd_buffer->cs->cdw <= cdw_max);
6962 }