radv: set BIG_PAGE to improve performance on GFX10.3
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 bool src_render_loop,
58 VkImageLayout dst_layout,
59 bool dst_render_loop,
60 uint32_t src_family,
61 uint32_t dst_family,
62 const VkImageSubresourceRange *range,
63 struct radv_sample_locations_state *sample_locs);
64
65 const struct radv_dynamic_state default_dynamic_state = {
66 .viewport = {
67 .count = 0,
68 },
69 .scissor = {
70 .count = 0,
71 },
72 .line_width = 1.0f,
73 .depth_bias = {
74 .bias = 0.0f,
75 .clamp = 0.0f,
76 .slope = 0.0f,
77 },
78 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
79 .depth_bounds = {
80 .min = 0.0f,
81 .max = 1.0f,
82 },
83 .stencil_compare_mask = {
84 .front = ~0u,
85 .back = ~0u,
86 },
87 .stencil_write_mask = {
88 .front = ~0u,
89 .back = ~0u,
90 },
91 .stencil_reference = {
92 .front = 0u,
93 .back = 0u,
94 },
95 .line_stipple = {
96 .factor = 0u,
97 .pattern = 0u,
98 },
99 .cull_mode = 0u,
100 .front_face = 0u,
101 .primitive_topology = 0u,
102 };
103
104 static void
105 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
106 const struct radv_dynamic_state *src)
107 {
108 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
109 uint32_t copy_mask = src->mask;
110 uint32_t dest_mask = 0;
111
112 dest->discard_rectangle.count = src->discard_rectangle.count;
113 dest->sample_location.count = src->sample_location.count;
114
115 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
116 if (dest->viewport.count != src->viewport.count) {
117 dest->viewport.count = src->viewport.count;
118 dest_mask |= RADV_DYNAMIC_VIEWPORT;
119 }
120
121 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
122 src->viewport.count * sizeof(VkViewport))) {
123 typed_memcpy(dest->viewport.viewports,
124 src->viewport.viewports,
125 src->viewport.count);
126 dest_mask |= RADV_DYNAMIC_VIEWPORT;
127 }
128 }
129
130 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
131 if (dest->scissor.count != src->scissor.count) {
132 dest->scissor.count = src->scissor.count;
133 dest_mask |= RADV_DYNAMIC_SCISSOR;
134 }
135
136 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
137 src->scissor.count * sizeof(VkRect2D))) {
138 typed_memcpy(dest->scissor.scissors,
139 src->scissor.scissors, src->scissor.count);
140 dest_mask |= RADV_DYNAMIC_SCISSOR;
141 }
142 }
143
144 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
145 if (dest->line_width != src->line_width) {
146 dest->line_width = src->line_width;
147 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
148 }
149 }
150
151 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
152 if (memcmp(&dest->depth_bias, &src->depth_bias,
153 sizeof(src->depth_bias))) {
154 dest->depth_bias = src->depth_bias;
155 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
156 }
157 }
158
159 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
160 if (memcmp(&dest->blend_constants, &src->blend_constants,
161 sizeof(src->blend_constants))) {
162 typed_memcpy(dest->blend_constants,
163 src->blend_constants, 4);
164 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
165 }
166 }
167
168 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
169 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
170 sizeof(src->depth_bounds))) {
171 dest->depth_bounds = src->depth_bounds;
172 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
173 }
174 }
175
176 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
177 if (memcmp(&dest->stencil_compare_mask,
178 &src->stencil_compare_mask,
179 sizeof(src->stencil_compare_mask))) {
180 dest->stencil_compare_mask = src->stencil_compare_mask;
181 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
182 }
183 }
184
185 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
186 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
187 sizeof(src->stencil_write_mask))) {
188 dest->stencil_write_mask = src->stencil_write_mask;
189 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
190 }
191 }
192
193 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
194 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
195 sizeof(src->stencil_reference))) {
196 dest->stencil_reference = src->stencil_reference;
197 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
198 }
199 }
200
201 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
202 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
203 src->discard_rectangle.count * sizeof(VkRect2D))) {
204 typed_memcpy(dest->discard_rectangle.rectangles,
205 src->discard_rectangle.rectangles,
206 src->discard_rectangle.count);
207 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
208 }
209 }
210
211 if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
212 if (dest->sample_location.per_pixel != src->sample_location.per_pixel ||
213 dest->sample_location.grid_size.width != src->sample_location.grid_size.width ||
214 dest->sample_location.grid_size.height != src->sample_location.grid_size.height ||
215 memcmp(&dest->sample_location.locations,
216 &src->sample_location.locations,
217 src->sample_location.count * sizeof(VkSampleLocationEXT))) {
218 dest->sample_location.per_pixel = src->sample_location.per_pixel;
219 dest->sample_location.grid_size = src->sample_location.grid_size;
220 typed_memcpy(dest->sample_location.locations,
221 src->sample_location.locations,
222 src->sample_location.count);
223 dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
224 }
225 }
226
227 if (copy_mask & RADV_DYNAMIC_LINE_STIPPLE) {
228 if (memcmp(&dest->line_stipple, &src->line_stipple,
229 sizeof(src->line_stipple))) {
230 dest->line_stipple = src->line_stipple;
231 dest_mask |= RADV_DYNAMIC_LINE_STIPPLE;
232 }
233 }
234
235 if (copy_mask & RADV_DYNAMIC_CULL_MODE) {
236 if (dest->cull_mode != src->cull_mode) {
237 dest->cull_mode = src->cull_mode;
238 dest_mask |= RADV_DYNAMIC_CULL_MODE;
239 }
240 }
241
242 if (copy_mask & RADV_DYNAMIC_FRONT_FACE) {
243 if (dest->front_face != src->front_face) {
244 dest->front_face = src->front_face;
245 dest_mask |= RADV_DYNAMIC_FRONT_FACE;
246 }
247 }
248
249 if (copy_mask & RADV_DYNAMIC_PRIMITIVE_TOPOLOGY) {
250 if (dest->primitive_topology != src->primitive_topology) {
251 dest->primitive_topology = src->primitive_topology;
252 dest_mask |= RADV_DYNAMIC_PRIMITIVE_TOPOLOGY;
253 }
254 }
255
256 if (copy_mask & RADV_DYNAMIC_DEPTH_TEST_ENABLE) {
257 if (dest->depth_test_enable != src->depth_test_enable) {
258 dest->depth_test_enable = src->depth_test_enable;
259 dest_mask |= RADV_DYNAMIC_DEPTH_TEST_ENABLE;
260 }
261 }
262
263 if (copy_mask & RADV_DYNAMIC_DEPTH_WRITE_ENABLE) {
264 if (dest->depth_write_enable != src->depth_write_enable) {
265 dest->depth_write_enable = src->depth_write_enable;
266 dest_mask |= RADV_DYNAMIC_DEPTH_WRITE_ENABLE;
267 }
268 }
269
270 if (copy_mask & RADV_DYNAMIC_DEPTH_COMPARE_OP) {
271 if (dest->depth_compare_op != src->depth_compare_op) {
272 dest->depth_compare_op = src->depth_compare_op;
273 dest_mask |= RADV_DYNAMIC_DEPTH_COMPARE_OP;
274 }
275 }
276
277 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE) {
278 if (dest->depth_bounds_test_enable != src->depth_bounds_test_enable) {
279 dest->depth_bounds_test_enable = src->depth_bounds_test_enable;
280 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE;
281 }
282 }
283
284 if (copy_mask & RADV_DYNAMIC_STENCIL_TEST_ENABLE) {
285 if (dest->stencil_test_enable != src->stencil_test_enable) {
286 dest->stencil_test_enable = src->stencil_test_enable;
287 dest_mask |= RADV_DYNAMIC_STENCIL_TEST_ENABLE;
288 }
289 }
290
291 if (copy_mask & RADV_DYNAMIC_STENCIL_OP) {
292 if (memcmp(&dest->stencil_op, &src->stencil_op,
293 sizeof(src->stencil_op))) {
294 dest->stencil_op = src->stencil_op;
295 dest_mask |= RADV_DYNAMIC_STENCIL_OP;
296 }
297 }
298
299 cmd_buffer->state.dirty |= dest_mask;
300 }
301
302 static void
303 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
304 struct radv_pipeline *pipeline)
305 {
306 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
307 struct radv_shader_info *info;
308
309 if (!pipeline->streamout_shader ||
310 cmd_buffer->device->physical_device->use_ngg_streamout)
311 return;
312
313 info = &pipeline->streamout_shader->info;
314 for (int i = 0; i < MAX_SO_BUFFERS; i++)
315 so->stride_in_dw[i] = info->so.strides[i];
316
317 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
318 }
319
320 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
321 {
322 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
323 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
324 }
325
326 enum ring_type radv_queue_family_to_ring(int f) {
327 switch (f) {
328 case RADV_QUEUE_GENERAL:
329 return RING_GFX;
330 case RADV_QUEUE_COMPUTE:
331 return RING_COMPUTE;
332 case RADV_QUEUE_TRANSFER:
333 return RING_DMA;
334 default:
335 unreachable("Unknown queue family");
336 }
337 }
338
339 static void
340 radv_destroy_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
341 {
342 list_del(&cmd_buffer->pool_link);
343
344 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
345 &cmd_buffer->upload.list, list) {
346 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
347 list_del(&up->list);
348 free(up);
349 }
350
351 if (cmd_buffer->upload.upload_bo)
352 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
353
354 if (cmd_buffer->cs)
355 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
356
357 for (unsigned i = 0; i < MAX_BIND_POINTS; i++)
358 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
359
360 vk_object_base_finish(&cmd_buffer->base);
361 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
362 }
363
364 static VkResult radv_create_cmd_buffer(
365 struct radv_device * device,
366 struct radv_cmd_pool * pool,
367 VkCommandBufferLevel level,
368 VkCommandBuffer* pCommandBuffer)
369 {
370 struct radv_cmd_buffer *cmd_buffer;
371 unsigned ring;
372 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
373 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
374 if (cmd_buffer == NULL)
375 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
376
377 vk_object_base_init(&device->vk, &cmd_buffer->base,
378 VK_OBJECT_TYPE_COMMAND_BUFFER);
379
380 cmd_buffer->device = device;
381 cmd_buffer->pool = pool;
382 cmd_buffer->level = level;
383
384 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
385 cmd_buffer->queue_family_index = pool->queue_family_index;
386
387 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
388
389 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
390 if (!cmd_buffer->cs) {
391 radv_destroy_cmd_buffer(cmd_buffer);
392 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
393 }
394
395 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
396
397 list_inithead(&cmd_buffer->upload.list);
398
399 return VK_SUCCESS;
400 }
401
402 static VkResult
403 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
404 {
405 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
406
407 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
408 &cmd_buffer->upload.list, list) {
409 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
410 list_del(&up->list);
411 free(up);
412 }
413
414 cmd_buffer->push_constant_stages = 0;
415 cmd_buffer->scratch_size_per_wave_needed = 0;
416 cmd_buffer->scratch_waves_wanted = 0;
417 cmd_buffer->compute_scratch_size_per_wave_needed = 0;
418 cmd_buffer->compute_scratch_waves_wanted = 0;
419 cmd_buffer->esgs_ring_size_needed = 0;
420 cmd_buffer->gsvs_ring_size_needed = 0;
421 cmd_buffer->tess_rings_needed = false;
422 cmd_buffer->gds_needed = false;
423 cmd_buffer->gds_oa_needed = false;
424 cmd_buffer->sample_positions_needed = false;
425
426 if (cmd_buffer->upload.upload_bo)
427 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
428 cmd_buffer->upload.upload_bo);
429 cmd_buffer->upload.offset = 0;
430
431 cmd_buffer->record_result = VK_SUCCESS;
432
433 memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
434
435 for (unsigned i = 0; i < MAX_BIND_POINTS; i++) {
436 cmd_buffer->descriptors[i].dirty = 0;
437 cmd_buffer->descriptors[i].valid = 0;
438 cmd_buffer->descriptors[i].push_dirty = false;
439 }
440
441 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
442 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
443 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
444 unsigned fence_offset, eop_bug_offset;
445 void *fence_ptr;
446
447 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
448 &fence_ptr);
449
450 cmd_buffer->gfx9_fence_va =
451 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
452 cmd_buffer->gfx9_fence_va += fence_offset;
453
454 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
455 /* Allocate a buffer for the EOP bug on GFX9. */
456 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
457 &eop_bug_offset, &fence_ptr);
458 cmd_buffer->gfx9_eop_bug_va =
459 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
460 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
461 }
462 }
463
464 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
465
466 return cmd_buffer->record_result;
467 }
468
469 static bool
470 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
471 uint64_t min_needed)
472 {
473 uint64_t new_size;
474 struct radeon_winsys_bo *bo;
475 struct radv_cmd_buffer_upload *upload;
476 struct radv_device *device = cmd_buffer->device;
477
478 new_size = MAX2(min_needed, 16 * 1024);
479 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
480
481 bo = device->ws->buffer_create(device->ws,
482 new_size, 4096,
483 RADEON_DOMAIN_GTT,
484 RADEON_FLAG_CPU_ACCESS|
485 RADEON_FLAG_NO_INTERPROCESS_SHARING |
486 RADEON_FLAG_32BIT |
487 RADEON_FLAG_GTT_WC,
488 RADV_BO_PRIORITY_UPLOAD_BUFFER);
489
490 if (!bo) {
491 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
492 return false;
493 }
494
495 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
496 if (cmd_buffer->upload.upload_bo) {
497 upload = malloc(sizeof(*upload));
498
499 if (!upload) {
500 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
501 device->ws->buffer_destroy(bo);
502 return false;
503 }
504
505 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
506 list_add(&upload->list, &cmd_buffer->upload.list);
507 }
508
509 cmd_buffer->upload.upload_bo = bo;
510 cmd_buffer->upload.size = new_size;
511 cmd_buffer->upload.offset = 0;
512 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
513
514 if (!cmd_buffer->upload.map) {
515 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
516 return false;
517 }
518
519 return true;
520 }
521
522 bool
523 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
524 unsigned size,
525 unsigned alignment,
526 unsigned *out_offset,
527 void **ptr)
528 {
529 assert(util_is_power_of_two_nonzero(alignment));
530
531 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
532 if (offset + size > cmd_buffer->upload.size) {
533 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
534 return false;
535 offset = 0;
536 }
537
538 *out_offset = offset;
539 *ptr = cmd_buffer->upload.map + offset;
540
541 cmd_buffer->upload.offset = offset + size;
542 return true;
543 }
544
545 bool
546 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
547 unsigned size, unsigned alignment,
548 const void *data, unsigned *out_offset)
549 {
550 uint8_t *ptr;
551
552 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
553 out_offset, (void **)&ptr))
554 return false;
555
556 if (ptr)
557 memcpy(ptr, data, size);
558
559 return true;
560 }
561
562 static void
563 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
564 unsigned count, const uint32_t *data)
565 {
566 struct radeon_cmdbuf *cs = cmd_buffer->cs;
567
568 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
569
570 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
571 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
572 S_370_WR_CONFIRM(1) |
573 S_370_ENGINE_SEL(V_370_ME));
574 radeon_emit(cs, va);
575 radeon_emit(cs, va >> 32);
576 radeon_emit_array(cs, data, count);
577 }
578
579 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
580 {
581 struct radv_device *device = cmd_buffer->device;
582 struct radeon_cmdbuf *cs = cmd_buffer->cs;
583 uint64_t va;
584
585 va = radv_buffer_get_va(device->trace_bo);
586 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
587 va += 4;
588
589 ++cmd_buffer->state.trace_id;
590 radv_emit_write_data_packet(cmd_buffer, va, 1,
591 &cmd_buffer->state.trace_id);
592
593 radeon_check_space(cmd_buffer->device->ws, cs, 2);
594
595 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
596 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
597 }
598
599 static void
600 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
601 enum radv_cmd_flush_bits flags)
602 {
603 if (unlikely(cmd_buffer->device->thread_trace_bo)) {
604 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
605 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_THREAD_TRACE_MARKER) | EVENT_INDEX(0));
606 }
607
608 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
609 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
610 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
611
612 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
613
614 /* Force wait for graphics or compute engines to be idle. */
615 si_cs_emit_cache_flush(cmd_buffer->cs,
616 cmd_buffer->device->physical_device->rad_info.chip_class,
617 &cmd_buffer->gfx9_fence_idx,
618 cmd_buffer->gfx9_fence_va,
619 radv_cmd_buffer_uses_mec(cmd_buffer),
620 flags, cmd_buffer->gfx9_eop_bug_va);
621 }
622
623 if (unlikely(cmd_buffer->device->trace_bo))
624 radv_cmd_buffer_trace_emit(cmd_buffer);
625 }
626
627 static void
628 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
629 struct radv_pipeline *pipeline, enum ring_type ring)
630 {
631 struct radv_device *device = cmd_buffer->device;
632 uint32_t data[2];
633 uint64_t va;
634
635 va = radv_buffer_get_va(device->trace_bo);
636
637 switch (ring) {
638 case RING_GFX:
639 va += 8;
640 break;
641 case RING_COMPUTE:
642 va += 16;
643 break;
644 default:
645 assert(!"invalid ring type");
646 }
647
648 uint64_t pipeline_address = (uintptr_t)pipeline;
649 data[0] = pipeline_address;
650 data[1] = pipeline_address >> 32;
651
652 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
653 }
654
655 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
656 VkPipelineBindPoint bind_point,
657 struct radv_descriptor_set *set,
658 unsigned idx)
659 {
660 struct radv_descriptor_state *descriptors_state =
661 radv_get_descriptors_state(cmd_buffer, bind_point);
662
663 descriptors_state->sets[idx] = set;
664
665 descriptors_state->valid |= (1u << idx); /* active descriptors */
666 descriptors_state->dirty |= (1u << idx);
667 }
668
669 static void
670 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
671 VkPipelineBindPoint bind_point)
672 {
673 struct radv_descriptor_state *descriptors_state =
674 radv_get_descriptors_state(cmd_buffer, bind_point);
675 struct radv_device *device = cmd_buffer->device;
676 uint32_t data[MAX_SETS * 2] = {};
677 uint64_t va;
678 unsigned i;
679 va = radv_buffer_get_va(device->trace_bo) + 24;
680
681 for_each_bit(i, descriptors_state->valid) {
682 struct radv_descriptor_set *set = descriptors_state->sets[i];
683 data[i * 2] = (uint64_t)(uintptr_t)set;
684 data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
685 }
686
687 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
688 }
689
690 struct radv_userdata_info *
691 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
692 gl_shader_stage stage,
693 int idx)
694 {
695 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
696 return &shader->info.user_sgprs_locs.shader_data[idx];
697 }
698
699 static void
700 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
701 struct radv_pipeline *pipeline,
702 gl_shader_stage stage,
703 int idx, uint64_t va)
704 {
705 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
706 uint32_t base_reg = pipeline->user_data_0[stage];
707 if (loc->sgpr_idx == -1)
708 return;
709
710 assert(loc->num_sgprs == 1);
711
712 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
713 base_reg + loc->sgpr_idx * 4, va, false);
714 }
715
716 static void
717 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
718 struct radv_pipeline *pipeline,
719 struct radv_descriptor_state *descriptors_state,
720 gl_shader_stage stage)
721 {
722 struct radv_device *device = cmd_buffer->device;
723 struct radeon_cmdbuf *cs = cmd_buffer->cs;
724 uint32_t sh_base = pipeline->user_data_0[stage];
725 struct radv_userdata_locations *locs =
726 &pipeline->shaders[stage]->info.user_sgprs_locs;
727 unsigned mask = locs->descriptor_sets_enabled;
728
729 mask &= descriptors_state->dirty & descriptors_state->valid;
730
731 while (mask) {
732 int start, count;
733
734 u_bit_scan_consecutive_range(&mask, &start, &count);
735
736 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
737 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
738
739 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
740 for (int i = 0; i < count; i++) {
741 struct radv_descriptor_set *set =
742 descriptors_state->sets[start + i];
743
744 radv_emit_shader_pointer_body(device, cs, set->va, true);
745 }
746 }
747 }
748
749 /**
750 * Convert the user sample locations to hardware sample locations (the values
751 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
752 */
753 static void
754 radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
755 uint32_t x, uint32_t y, VkOffset2D *sample_locs)
756 {
757 uint32_t x_offset = x % state->grid_size.width;
758 uint32_t y_offset = y % state->grid_size.height;
759 uint32_t num_samples = (uint32_t)state->per_pixel;
760 VkSampleLocationEXT *user_locs;
761 uint32_t pixel_offset;
762
763 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
764
765 assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
766 user_locs = &state->locations[pixel_offset];
767
768 for (uint32_t i = 0; i < num_samples; i++) {
769 float shifted_pos_x = user_locs[i].x - 0.5;
770 float shifted_pos_y = user_locs[i].y - 0.5;
771
772 int32_t scaled_pos_x = floorf(shifted_pos_x * 16);
773 int32_t scaled_pos_y = floorf(shifted_pos_y * 16);
774
775 sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
776 sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
777 }
778 }
779
780 /**
781 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
782 * locations.
783 */
784 static void
785 radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
786 uint32_t *sample_locs_pixel)
787 {
788 for (uint32_t i = 0; i < num_samples; i++) {
789 uint32_t sample_reg_idx = i / 4;
790 uint32_t sample_loc_idx = i % 4;
791 int32_t pos_x = sample_locs[i].x;
792 int32_t pos_y = sample_locs[i].y;
793
794 uint32_t shift_x = 8 * sample_loc_idx;
795 uint32_t shift_y = shift_x + 4;
796
797 sample_locs_pixel[sample_reg_idx] |= (pos_x & 0xf) << shift_x;
798 sample_locs_pixel[sample_reg_idx] |= (pos_y & 0xf) << shift_y;
799 }
800 }
801
802 /**
803 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
804 * sample locations.
805 */
806 static uint64_t
807 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer,
808 VkOffset2D *sample_locs,
809 uint32_t num_samples)
810 {
811 uint32_t centroid_priorities[num_samples];
812 uint32_t sample_mask = num_samples - 1;
813 uint32_t distances[num_samples];
814 uint64_t centroid_priority = 0;
815
816 /* Compute the distances from center for each sample. */
817 for (int i = 0; i < num_samples; i++) {
818 distances[i] = (sample_locs[i].x * sample_locs[i].x) +
819 (sample_locs[i].y * sample_locs[i].y);
820 }
821
822 /* Compute the centroid priorities by looking at the distances array. */
823 for (int i = 0; i < num_samples; i++) {
824 uint32_t min_idx = 0;
825
826 for (int j = 1; j < num_samples; j++) {
827 if (distances[j] < distances[min_idx])
828 min_idx = j;
829 }
830
831 centroid_priorities[i] = min_idx;
832 distances[min_idx] = 0xffffffff;
833 }
834
835 /* Compute the final centroid priority. */
836 for (int i = 0; i < 8; i++) {
837 centroid_priority |=
838 centroid_priorities[i & sample_mask] << (i * 4);
839 }
840
841 return centroid_priority << 32 | centroid_priority;
842 }
843
844 /**
845 * Emit the sample locations that are specified with VK_EXT_sample_locations.
846 */
847 static void
848 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
849 {
850 struct radv_sample_locations_state *sample_location =
851 &cmd_buffer->state.dynamic.sample_location;
852 uint32_t num_samples = (uint32_t)sample_location->per_pixel;
853 struct radeon_cmdbuf *cs = cmd_buffer->cs;
854 uint32_t sample_locs_pixel[4][2] = {};
855 VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
856 uint32_t max_sample_dist = 0;
857 uint64_t centroid_priority;
858
859 if (!cmd_buffer->state.dynamic.sample_location.count)
860 return;
861
862 /* Convert the user sample locations to hardware sample locations. */
863 radv_convert_user_sample_locs(sample_location, 0, 0, sample_locs[0]);
864 radv_convert_user_sample_locs(sample_location, 1, 0, sample_locs[1]);
865 radv_convert_user_sample_locs(sample_location, 0, 1, sample_locs[2]);
866 radv_convert_user_sample_locs(sample_location, 1, 1, sample_locs[3]);
867
868 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
869 for (uint32_t i = 0; i < 4; i++) {
870 radv_compute_sample_locs_pixel(num_samples, sample_locs[i],
871 sample_locs_pixel[i]);
872 }
873
874 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
875 centroid_priority =
876 radv_compute_centroid_priority(cmd_buffer, sample_locs[0],
877 num_samples);
878
879 /* Compute the maximum sample distance from the specified locations. */
880 for (unsigned i = 0; i < 4; ++i) {
881 for (uint32_t j = 0; j < num_samples; j++) {
882 VkOffset2D offset = sample_locs[i][j];
883 max_sample_dist = MAX2(max_sample_dist,
884 MAX2(abs(offset.x), abs(offset.y)));
885 }
886 }
887
888 /* Emit the specified user sample locations. */
889 switch (num_samples) {
890 case 2:
891 case 4:
892 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
893 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
894 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
895 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
896 break;
897 case 8:
898 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
899 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
900 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
901 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
902 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs_pixel[0][1]);
903 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs_pixel[1][1]);
904 radeon_set_context_reg(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs_pixel[2][1]);
905 radeon_set_context_reg(cs, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs_pixel[3][1]);
906 break;
907 default:
908 unreachable("invalid number of samples");
909 }
910
911 /* Emit the maximum sample distance and the centroid priority. */
912 radeon_set_context_reg_rmw(cs, R_028BE0_PA_SC_AA_CONFIG,
913 S_028BE0_MAX_SAMPLE_DIST(max_sample_dist),
914 ~C_028BE0_MAX_SAMPLE_DIST);
915
916 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
917 radeon_emit(cs, centroid_priority);
918 radeon_emit(cs, centroid_priority >> 32);
919
920 /* GFX9: Flush DFSM when the AA mode changes. */
921 if (cmd_buffer->device->dfsm_allowed) {
922 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
923 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
924 }
925
926 cmd_buffer->state.context_roll_without_scissor_emitted = true;
927 }
928
929 static void
930 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
931 struct radv_pipeline *pipeline,
932 gl_shader_stage stage,
933 int idx, int count, uint32_t *values)
934 {
935 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
936 uint32_t base_reg = pipeline->user_data_0[stage];
937 if (loc->sgpr_idx == -1)
938 return;
939
940 assert(loc->num_sgprs == count);
941
942 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
943 radeon_emit_array(cmd_buffer->cs, values, count);
944 }
945
946 static void
947 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
948 struct radv_pipeline *pipeline)
949 {
950 int num_samples = pipeline->graphics.ms.num_samples;
951 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
952
953 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.needs_sample_positions)
954 cmd_buffer->sample_positions_needed = true;
955
956 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
957 return;
958
959 radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
960
961 cmd_buffer->state.context_roll_without_scissor_emitted = true;
962 }
963
964 static void
965 radv_update_binning_state(struct radv_cmd_buffer *cmd_buffer,
966 struct radv_pipeline *pipeline)
967 {
968 const struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
969
970
971 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
972 return;
973
974 if (old_pipeline &&
975 old_pipeline->graphics.binning.pa_sc_binner_cntl_0 == pipeline->graphics.binning.pa_sc_binner_cntl_0 &&
976 old_pipeline->graphics.binning.db_dfsm_control == pipeline->graphics.binning.db_dfsm_control)
977 return;
978
979 bool binning_flush = false;
980 if (cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA12 ||
981 cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA20 ||
982 cmd_buffer->device->physical_device->rad_info.family == CHIP_RAVEN2 ||
983 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
984 binning_flush = !old_pipeline ||
985 G_028C44_BINNING_MODE(old_pipeline->graphics.binning.pa_sc_binner_cntl_0) !=
986 G_028C44_BINNING_MODE(pipeline->graphics.binning.pa_sc_binner_cntl_0);
987 }
988
989 radeon_set_context_reg(cmd_buffer->cs, R_028C44_PA_SC_BINNER_CNTL_0,
990 pipeline->graphics.binning.pa_sc_binner_cntl_0 |
991 S_028C44_FLUSH_ON_BINNING_TRANSITION(!!binning_flush));
992
993 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
994 radeon_set_context_reg(cmd_buffer->cs, R_028038_DB_DFSM_CONTROL,
995 pipeline->graphics.binning.db_dfsm_control);
996 } else {
997 radeon_set_context_reg(cmd_buffer->cs, R_028060_DB_DFSM_CONTROL,
998 pipeline->graphics.binning.db_dfsm_control);
999 }
1000
1001 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1002 }
1003
1004
1005 static void
1006 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
1007 struct radv_shader_variant *shader)
1008 {
1009 uint64_t va;
1010
1011 if (!shader)
1012 return;
1013
1014 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
1015
1016 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
1017 }
1018
1019 static void
1020 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
1021 struct radv_pipeline *pipeline,
1022 bool vertex_stage_only)
1023 {
1024 struct radv_cmd_state *state = &cmd_buffer->state;
1025 uint32_t mask = state->prefetch_L2_mask;
1026
1027 if (vertex_stage_only) {
1028 /* Fast prefetch path for starting draws as soon as possible.
1029 */
1030 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
1031 RADV_PREFETCH_VBO_DESCRIPTORS);
1032 }
1033
1034 if (mask & RADV_PREFETCH_VS)
1035 radv_emit_shader_prefetch(cmd_buffer,
1036 pipeline->shaders[MESA_SHADER_VERTEX]);
1037
1038 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
1039 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
1040
1041 if (mask & RADV_PREFETCH_TCS)
1042 radv_emit_shader_prefetch(cmd_buffer,
1043 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
1044
1045 if (mask & RADV_PREFETCH_TES)
1046 radv_emit_shader_prefetch(cmd_buffer,
1047 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
1048
1049 if (mask & RADV_PREFETCH_GS) {
1050 radv_emit_shader_prefetch(cmd_buffer,
1051 pipeline->shaders[MESA_SHADER_GEOMETRY]);
1052 if (radv_pipeline_has_gs_copy_shader(pipeline))
1053 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
1054 }
1055
1056 if (mask & RADV_PREFETCH_PS)
1057 radv_emit_shader_prefetch(cmd_buffer,
1058 pipeline->shaders[MESA_SHADER_FRAGMENT]);
1059
1060 state->prefetch_L2_mask &= ~mask;
1061 }
1062
1063 static void
1064 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
1065 {
1066 if (!cmd_buffer->device->physical_device->rad_info.rbplus_allowed)
1067 return;
1068
1069 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1070 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1071
1072 unsigned sx_ps_downconvert = 0;
1073 unsigned sx_blend_opt_epsilon = 0;
1074 unsigned sx_blend_opt_control = 0;
1075
1076 if (!cmd_buffer->state.attachments || !subpass)
1077 return;
1078
1079 for (unsigned i = 0; i < subpass->color_count; ++i) {
1080 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1081 /* We don't set the DISABLE bits, because the HW can't have holes,
1082 * so the SPI color format is set to 32-bit 1-component. */
1083 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1084 continue;
1085 }
1086
1087 int idx = subpass->color_attachments[i].attachment;
1088 struct radv_color_buffer_info *cb = &cmd_buffer->state.attachments[idx].cb;
1089
1090 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
1091 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
1092 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
1093 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
1094
1095 bool has_alpha, has_rgb;
1096
1097 /* Set if RGB and A are present. */
1098 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
1099
1100 if (format == V_028C70_COLOR_8 ||
1101 format == V_028C70_COLOR_16 ||
1102 format == V_028C70_COLOR_32)
1103 has_rgb = !has_alpha;
1104 else
1105 has_rgb = true;
1106
1107 /* Check the colormask and export format. */
1108 if (!(colormask & 0x7))
1109 has_rgb = false;
1110 if (!(colormask & 0x8))
1111 has_alpha = false;
1112
1113 if (spi_format == V_028714_SPI_SHADER_ZERO) {
1114 has_rgb = false;
1115 has_alpha = false;
1116 }
1117
1118 /* Disable value checking for disabled channels. */
1119 if (!has_rgb)
1120 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1121 if (!has_alpha)
1122 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1123
1124 /* Enable down-conversion for 32bpp and smaller formats. */
1125 switch (format) {
1126 case V_028C70_COLOR_8:
1127 case V_028C70_COLOR_8_8:
1128 case V_028C70_COLOR_8_8_8_8:
1129 /* For 1 and 2-channel formats, use the superset thereof. */
1130 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
1131 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1132 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1133 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
1134 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
1135 }
1136 break;
1137
1138 case V_028C70_COLOR_5_6_5:
1139 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1140 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
1141 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
1142 }
1143 break;
1144
1145 case V_028C70_COLOR_1_5_5_5:
1146 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1147 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
1148 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
1149 }
1150 break;
1151
1152 case V_028C70_COLOR_4_4_4_4:
1153 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1154 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
1155 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
1156 }
1157 break;
1158
1159 case V_028C70_COLOR_32:
1160 if (swap == V_028C70_SWAP_STD &&
1161 spi_format == V_028714_SPI_SHADER_32_R)
1162 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1163 else if (swap == V_028C70_SWAP_ALT_REV &&
1164 spi_format == V_028714_SPI_SHADER_32_AR)
1165 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
1166 break;
1167
1168 case V_028C70_COLOR_16:
1169 case V_028C70_COLOR_16_16:
1170 /* For 1-channel formats, use the superset thereof. */
1171 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
1172 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
1173 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1174 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1175 if (swap == V_028C70_SWAP_STD ||
1176 swap == V_028C70_SWAP_STD_REV)
1177 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
1178 else
1179 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
1180 }
1181 break;
1182
1183 case V_028C70_COLOR_10_11_11:
1184 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1185 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
1186 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
1187 }
1188 break;
1189
1190 case V_028C70_COLOR_2_10_10_10:
1191 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1192 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
1193 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
1194 }
1195 break;
1196 }
1197 }
1198
1199 /* Do not set the DISABLE bits for the unused attachments, as that
1200 * breaks dual source blending in SkQP and does not seem to improve
1201 * performance. */
1202
1203 if (sx_ps_downconvert == cmd_buffer->state.last_sx_ps_downconvert &&
1204 sx_blend_opt_epsilon == cmd_buffer->state.last_sx_blend_opt_epsilon &&
1205 sx_blend_opt_control == cmd_buffer->state.last_sx_blend_opt_control)
1206 return;
1207
1208 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
1209 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
1210 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
1211 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
1212
1213 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1214
1215 cmd_buffer->state.last_sx_ps_downconvert = sx_ps_downconvert;
1216 cmd_buffer->state.last_sx_blend_opt_epsilon = sx_blend_opt_epsilon;
1217 cmd_buffer->state.last_sx_blend_opt_control = sx_blend_opt_control;
1218 }
1219
1220 static void
1221 radv_emit_batch_break_on_new_ps(struct radv_cmd_buffer *cmd_buffer)
1222 {
1223 if (!cmd_buffer->device->pbb_allowed)
1224 return;
1225
1226 struct radv_binning_settings settings =
1227 radv_get_binning_settings(cmd_buffer->device->physical_device);
1228 bool break_for_new_ps =
1229 (!cmd_buffer->state.emitted_pipeline ||
1230 cmd_buffer->state.emitted_pipeline->shaders[MESA_SHADER_FRAGMENT] !=
1231 cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT]) &&
1232 (settings.context_states_per_bin > 1 ||
1233 settings.persistent_states_per_bin > 1);
1234 bool break_for_new_cb_target_mask =
1235 (!cmd_buffer->state.emitted_pipeline ||
1236 cmd_buffer->state.emitted_pipeline->graphics.cb_target_mask !=
1237 cmd_buffer->state.pipeline->graphics.cb_target_mask) &&
1238 settings.context_states_per_bin > 1;
1239
1240 if (!break_for_new_ps && !break_for_new_cb_target_mask)
1241 return;
1242
1243 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1244 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1245 }
1246
1247 static void
1248 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1249 {
1250 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1251
1252 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1253 return;
1254
1255 radv_update_multisample_state(cmd_buffer, pipeline);
1256 radv_update_binning_state(cmd_buffer, pipeline);
1257
1258 cmd_buffer->scratch_size_per_wave_needed = MAX2(cmd_buffer->scratch_size_per_wave_needed,
1259 pipeline->scratch_bytes_per_wave);
1260 cmd_buffer->scratch_waves_wanted = MAX2(cmd_buffer->scratch_waves_wanted,
1261 pipeline->max_waves);
1262
1263 if (!cmd_buffer->state.emitted_pipeline ||
1264 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1265 pipeline->graphics.can_use_guardband)
1266 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1267
1268 if (!cmd_buffer->state.emitted_pipeline ||
1269 cmd_buffer->state.emitted_pipeline->graphics.pa_su_sc_mode_cntl !=
1270 pipeline->graphics.pa_su_sc_mode_cntl)
1271 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_CULL_MODE |
1272 RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE;
1273
1274 if (!cmd_buffer->state.emitted_pipeline)
1275 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY;
1276
1277 if (!cmd_buffer->state.emitted_pipeline ||
1278 cmd_buffer->state.emitted_pipeline->graphics.db_depth_control !=
1279 pipeline->graphics.db_depth_control)
1280 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE |
1281 RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE |
1282 RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP |
1283 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE |
1284 RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE |
1285 RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP;
1286
1287 if (!cmd_buffer->state.emitted_pipeline)
1288 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP;
1289
1290 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
1291
1292 if (!cmd_buffer->state.emitted_pipeline ||
1293 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
1294 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
1295 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
1296 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
1297 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
1298 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1299 }
1300
1301 radv_emit_batch_break_on_new_ps(cmd_buffer);
1302
1303 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
1304 if (!pipeline->shaders[i])
1305 continue;
1306
1307 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1308 pipeline->shaders[i]->bo);
1309 }
1310
1311 if (radv_pipeline_has_gs_copy_shader(pipeline))
1312 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1313 pipeline->gs_copy_shader->bo);
1314
1315 if (unlikely(cmd_buffer->device->trace_bo))
1316 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1317
1318 cmd_buffer->state.emitted_pipeline = pipeline;
1319
1320 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1321 }
1322
1323 static void
1324 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1325 {
1326 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1327 cmd_buffer->state.dynamic.viewport.viewports);
1328 }
1329
1330 static void
1331 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1332 {
1333 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1334
1335 si_write_scissors(cmd_buffer->cs, 0, count,
1336 cmd_buffer->state.dynamic.scissor.scissors,
1337 cmd_buffer->state.dynamic.viewport.viewports,
1338 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1339
1340 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1341 }
1342
1343 static void
1344 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1345 {
1346 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1347 return;
1348
1349 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1350 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1351 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1352 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1353 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1354 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1355 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1356 }
1357 }
1358
1359 static void
1360 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1361 {
1362 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1363
1364 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1365 S_028A08_WIDTH(CLAMP(width, 0, 0xFFFF)));
1366 }
1367
1368 static void
1369 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1370 {
1371 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1372
1373 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1374 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1375 }
1376
1377 static void
1378 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1379 {
1380 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1381
1382 radeon_set_context_reg_seq(cmd_buffer->cs,
1383 R_028430_DB_STENCILREFMASK, 2);
1384 radeon_emit(cmd_buffer->cs,
1385 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1386 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1387 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1388 S_028430_STENCILOPVAL(1));
1389 radeon_emit(cmd_buffer->cs,
1390 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1391 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1392 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1393 S_028434_STENCILOPVAL_BF(1));
1394 }
1395
1396 static void
1397 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1398 {
1399 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1400
1401 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1402 fui(d->depth_bounds.min));
1403 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1404 fui(d->depth_bounds.max));
1405 }
1406
1407 static void
1408 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1409 {
1410 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1411 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1412 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1413
1414
1415 radeon_set_context_reg_seq(cmd_buffer->cs,
1416 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1417 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1418 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1419 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1420 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1421 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1422 }
1423
1424 static void
1425 radv_emit_line_stipple(struct radv_cmd_buffer *cmd_buffer)
1426 {
1427 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1428 uint32_t auto_reset_cntl = 1;
1429
1430 if (d->primitive_topology == V_008958_DI_PT_LINESTRIP)
1431 auto_reset_cntl = 2;
1432
1433 radeon_set_context_reg(cmd_buffer->cs, R_028A0C_PA_SC_LINE_STIPPLE,
1434 S_028A0C_LINE_PATTERN(d->line_stipple.pattern) |
1435 S_028A0C_REPEAT_COUNT(d->line_stipple.factor - 1) |
1436 S_028A0C_AUTO_RESET_CNTL(auto_reset_cntl));
1437 }
1438
1439 static void
1440 radv_emit_culling(struct radv_cmd_buffer *cmd_buffer, uint32_t states)
1441 {
1442 unsigned pa_su_sc_mode_cntl = cmd_buffer->state.pipeline->graphics.pa_su_sc_mode_cntl;
1443 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1444
1445 if (states & RADV_CMD_DIRTY_DYNAMIC_CULL_MODE) {
1446 pa_su_sc_mode_cntl &= C_028814_CULL_FRONT;
1447 pa_su_sc_mode_cntl |= S_028814_CULL_FRONT(!!(d->cull_mode & VK_CULL_MODE_FRONT_BIT));
1448
1449 pa_su_sc_mode_cntl &= C_028814_CULL_BACK;
1450 pa_su_sc_mode_cntl |= S_028814_CULL_BACK(!!(d->cull_mode & VK_CULL_MODE_BACK_BIT));
1451 }
1452
1453 if (states & RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE) {
1454 pa_su_sc_mode_cntl &= C_028814_FACE;
1455 pa_su_sc_mode_cntl |= S_028814_FACE(d->front_face);
1456 }
1457
1458 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
1459 pa_su_sc_mode_cntl);
1460 }
1461
1462 static void
1463 radv_emit_primitive_topology(struct radv_cmd_buffer *cmd_buffer)
1464 {
1465 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1466
1467 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1468 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
1469 cmd_buffer->cs,
1470 R_030908_VGT_PRIMITIVE_TYPE, 1,
1471 d->primitive_topology);
1472 } else {
1473 radeon_set_config_reg(cmd_buffer->cs,
1474 R_008958_VGT_PRIMITIVE_TYPE,
1475 d->primitive_topology);
1476 }
1477 }
1478
1479 static void
1480 radv_emit_depth_control(struct radv_cmd_buffer *cmd_buffer, uint32_t states)
1481 {
1482 unsigned db_depth_control = cmd_buffer->state.pipeline->graphics.db_depth_control;
1483 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1484
1485 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE) {
1486 db_depth_control &= C_028800_Z_ENABLE;
1487 db_depth_control |= S_028800_Z_ENABLE(d->depth_test_enable ? 1 : 0);
1488 }
1489
1490 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE) {
1491 db_depth_control &= C_028800_Z_WRITE_ENABLE;
1492 db_depth_control |= S_028800_Z_WRITE_ENABLE(d->depth_write_enable ? 1 : 0);
1493 }
1494
1495 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP) {
1496 db_depth_control &= C_028800_ZFUNC;
1497 db_depth_control |= S_028800_ZFUNC(d->depth_compare_op);
1498 }
1499
1500 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE) {
1501 db_depth_control &= C_028800_DEPTH_BOUNDS_ENABLE;
1502 db_depth_control |= S_028800_DEPTH_BOUNDS_ENABLE(d->depth_bounds_test_enable ? 1 : 0);
1503 }
1504
1505 if (states & RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE) {
1506 db_depth_control &= C_028800_STENCIL_ENABLE;
1507 db_depth_control |= S_028800_STENCIL_ENABLE(d->stencil_test_enable ? 1 : 0);
1508
1509 db_depth_control &= C_028800_BACKFACE_ENABLE;
1510 db_depth_control |= S_028800_BACKFACE_ENABLE(d->stencil_test_enable ? 1 : 0);
1511 }
1512
1513 if (states & RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP) {
1514 db_depth_control &= C_028800_STENCILFUNC;
1515 db_depth_control |= S_028800_STENCILFUNC(d->stencil_op.front.compare_op);
1516
1517 db_depth_control &= C_028800_STENCILFUNC_BF;
1518 db_depth_control |= S_028800_STENCILFUNC_BF(d->stencil_op.back.compare_op);
1519 }
1520
1521 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL,
1522 db_depth_control);
1523 }
1524
1525 static void
1526 radv_emit_stencil_control(struct radv_cmd_buffer *cmd_buffer)
1527 {
1528 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1529
1530 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL,
1531 S_02842C_STENCILFAIL(si_translate_stencil_op(d->stencil_op.front.fail_op)) |
1532 S_02842C_STENCILZPASS(si_translate_stencil_op(d->stencil_op.front.pass_op)) |
1533 S_02842C_STENCILZFAIL(si_translate_stencil_op(d->stencil_op.front.depth_fail_op)) |
1534 S_02842C_STENCILFAIL_BF(si_translate_stencil_op(d->stencil_op.back.fail_op)) |
1535 S_02842C_STENCILZPASS_BF(si_translate_stencil_op(d->stencil_op.back.pass_op)) |
1536 S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(d->stencil_op.back.depth_fail_op)));
1537 }
1538
1539 static void
1540 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1541 int index,
1542 struct radv_color_buffer_info *cb,
1543 struct radv_image_view *iview,
1544 VkImageLayout layout,
1545 bool in_render_loop)
1546 {
1547 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
1548 uint32_t cb_color_info = cb->cb_color_info;
1549 struct radv_image *image = iview->image;
1550
1551 if (!radv_layout_dcc_compressed(cmd_buffer->device, image, layout, in_render_loop,
1552 radv_image_queue_family_mask(image,
1553 cmd_buffer->queue_family_index,
1554 cmd_buffer->queue_family_index))) {
1555 cb_color_info &= C_028C70_DCC_ENABLE;
1556 }
1557
1558 if (!radv_layout_can_fast_clear(image, layout, in_render_loop,
1559 radv_image_queue_family_mask(image,
1560 cmd_buffer->queue_family_index,
1561 cmd_buffer->queue_family_index))) {
1562 cb_color_info &= C_028C70_COMPRESSION;
1563 }
1564
1565 if (radv_image_is_tc_compat_cmask(image) &&
1566 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1567 radv_is_dcc_decompress_pipeline(cmd_buffer))) {
1568 /* If this bit is set, the FMASK decompression operation
1569 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1570 */
1571 cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
1572 }
1573
1574 if (radv_image_has_fmask(image) &&
1575 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1576 radv_is_hw_resolve_pipeline(cmd_buffer))) {
1577 /* Make sure FMASK is enabled if it has been cleared because:
1578 *
1579 * 1) it's required for FMASK_DECOMPRESS operations to avoid
1580 * GPU hangs
1581 * 2) it's necessary for CB_RESOLVE which can read compressed
1582 * FMASK data anyways.
1583 */
1584 cb_color_info |= S_028C70_COMPRESSION(1);
1585 }
1586
1587 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1588 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1589 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1590 radeon_emit(cmd_buffer->cs, 0);
1591 radeon_emit(cmd_buffer->cs, 0);
1592 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1593 radeon_emit(cmd_buffer->cs, cb_color_info);
1594 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1595 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1596 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1597 radeon_emit(cmd_buffer->cs, 0);
1598 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1599 radeon_emit(cmd_buffer->cs, 0);
1600
1601 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 1);
1602 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1603
1604 radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4,
1605 cb->cb_color_base >> 32);
1606 radeon_set_context_reg(cmd_buffer->cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + index * 4,
1607 cb->cb_color_cmask >> 32);
1608 radeon_set_context_reg(cmd_buffer->cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + index * 4,
1609 cb->cb_color_fmask >> 32);
1610 radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4,
1611 cb->cb_dcc_base >> 32);
1612 radeon_set_context_reg(cmd_buffer->cs, R_028EC0_CB_COLOR0_ATTRIB2 + index * 4,
1613 cb->cb_color_attrib2);
1614 radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4,
1615 cb->cb_color_attrib3);
1616 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1617 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1618 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1619 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1620 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1621 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1622 radeon_emit(cmd_buffer->cs, cb_color_info);
1623 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1624 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1625 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1626 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1627 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1628 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1629
1630 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1631 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1632 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1633
1634 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1635 cb->cb_mrt_epitch);
1636 } else {
1637 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1638 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1639 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1640 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1641 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1642 radeon_emit(cmd_buffer->cs, cb_color_info);
1643 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1644 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1645 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1646 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1647 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1648 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1649
1650 if (is_vi) { /* DCC BASE */
1651 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1652 }
1653 }
1654
1655 if (radv_dcc_enabled(image, iview->base_mip)) {
1656 /* Drawing with DCC enabled also compresses colorbuffers. */
1657 VkImageSubresourceRange range = {
1658 .aspectMask = iview->aspect_mask,
1659 .baseMipLevel = iview->base_mip,
1660 .levelCount = iview->level_count,
1661 .baseArrayLayer = iview->base_layer,
1662 .layerCount = iview->layer_count,
1663 };
1664
1665 radv_update_dcc_metadata(cmd_buffer, image, &range, true);
1666 }
1667 }
1668
1669 static void
1670 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1671 struct radv_ds_buffer_info *ds,
1672 const struct radv_image_view *iview,
1673 VkImageLayout layout,
1674 bool in_render_loop, bool requires_cond_exec)
1675 {
1676 const struct radv_image *image = iview->image;
1677 uint32_t db_z_info = ds->db_z_info;
1678 uint32_t db_z_info_reg;
1679
1680 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug ||
1681 !radv_image_is_tc_compat_htile(image))
1682 return;
1683
1684 if (!radv_layout_is_htile_compressed(image, layout, in_render_loop,
1685 radv_image_queue_family_mask(image,
1686 cmd_buffer->queue_family_index,
1687 cmd_buffer->queue_family_index))) {
1688 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1689 }
1690
1691 db_z_info &= C_028040_ZRANGE_PRECISION;
1692
1693 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1694 db_z_info_reg = R_028038_DB_Z_INFO;
1695 } else {
1696 db_z_info_reg = R_028040_DB_Z_INFO;
1697 }
1698
1699 /* When we don't know the last fast clear value we need to emit a
1700 * conditional packet that will eventually skip the following
1701 * SET_CONTEXT_REG packet.
1702 */
1703 if (requires_cond_exec) {
1704 uint64_t va = radv_get_tc_compat_zrange_va(image, iview->base_mip);
1705
1706 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1707 radeon_emit(cmd_buffer->cs, va);
1708 radeon_emit(cmd_buffer->cs, va >> 32);
1709 radeon_emit(cmd_buffer->cs, 0);
1710 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1711 }
1712
1713 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1714 }
1715
1716 static void
1717 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1718 struct radv_ds_buffer_info *ds,
1719 struct radv_image_view *iview,
1720 VkImageLayout layout,
1721 bool in_render_loop)
1722 {
1723 const struct radv_image *image = iview->image;
1724 uint32_t db_z_info = ds->db_z_info;
1725 uint32_t db_stencil_info = ds->db_stencil_info;
1726
1727 if (!radv_layout_is_htile_compressed(image, layout, in_render_loop,
1728 radv_image_queue_family_mask(image,
1729 cmd_buffer->queue_family_index,
1730 cmd_buffer->queue_family_index))) {
1731 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1732 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1733 }
1734
1735 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1736 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1737
1738 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1739 /* Enable HTILE caching in L2 for small chips. */
1740 unsigned meta_write_policy, meta_read_policy;
1741 /* TODO: investigate whether LRU improves performance on other chips too */
1742 if (cmd_buffer->device->physical_device->rad_info.num_render_backends <= 4) {
1743 meta_write_policy = V_02807C_CACHE_LRU_WR; /* cache writes */
1744 meta_read_policy = V_02807C_CACHE_LRU_RD; /* cache reads */
1745 } else {
1746 meta_write_policy = V_02807C_CACHE_STREAM_WR; /* write combine */
1747 meta_read_policy = V_02807C_CACHE_NOA_RD; /* don't cache reads */
1748 }
1749
1750 bool zs_big_page = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10_3 &&
1751 (image->alignment % (64 * 1024) == 0);
1752
1753 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1754 radeon_set_context_reg(cmd_buffer->cs, R_02801C_DB_DEPTH_SIZE_XY, ds->db_depth_size);
1755
1756 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 7);
1757 radeon_emit(cmd_buffer->cs, S_02803C_RESOURCE_LEVEL(1));
1758 radeon_emit(cmd_buffer->cs, db_z_info);
1759 radeon_emit(cmd_buffer->cs, db_stencil_info);
1760 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1761 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1762 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1763 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1764
1765 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_READ_BASE_HI, 6);
1766 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1767 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1768 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1769 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1770 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1771 radeon_emit(cmd_buffer->cs,
1772 S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
1773 S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
1774 S_02807C_HTILE_WR_POLICY(meta_write_policy) |
1775 S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
1776 S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_RD) |
1777 S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_RD) |
1778 S_02807C_HTILE_RD_POLICY(meta_read_policy) |
1779 S_02807C_Z_BIG_PAGE(zs_big_page) |
1780 S_02807C_S_BIG_PAGE(zs_big_page));
1781 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1782 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1783 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1784 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1785 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1786
1787 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1788 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1789 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1790 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1791 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1792 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1793 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1794 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1795 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1796 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1797 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1798
1799 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1800 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1801 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1802 } else {
1803 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1804
1805 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1806 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1807 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1808 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1809 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1810 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1811 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1812 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1813 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1814 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1815
1816 }
1817
1818 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1819 radv_update_zrange_precision(cmd_buffer, ds, iview, layout,
1820 in_render_loop, true);
1821
1822 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1823 ds->pa_su_poly_offset_db_fmt_cntl);
1824 }
1825
1826 /**
1827 * Update the fast clear depth/stencil values if the image is bound as a
1828 * depth/stencil buffer.
1829 */
1830 static void
1831 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1832 const struct radv_image_view *iview,
1833 VkClearDepthStencilValue ds_clear_value,
1834 VkImageAspectFlags aspects)
1835 {
1836 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1837 const struct radv_image *image = iview->image;
1838 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1839 uint32_t att_idx;
1840
1841 if (!cmd_buffer->state.attachments || !subpass)
1842 return;
1843
1844 if (!subpass->depth_stencil_attachment)
1845 return;
1846
1847 att_idx = subpass->depth_stencil_attachment->attachment;
1848 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1849 return;
1850
1851 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1852 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1853 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1854 radeon_emit(cs, ds_clear_value.stencil);
1855 radeon_emit(cs, fui(ds_clear_value.depth));
1856 } else if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1857 radeon_set_context_reg_seq(cs, R_02802C_DB_DEPTH_CLEAR, 1);
1858 radeon_emit(cs, fui(ds_clear_value.depth));
1859 } else {
1860 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1861 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 1);
1862 radeon_emit(cs, ds_clear_value.stencil);
1863 }
1864
1865 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1866 * only needed when clearing Z to 0.0.
1867 */
1868 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1869 ds_clear_value.depth == 0.0) {
1870 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1871 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
1872
1873 radv_update_zrange_precision(cmd_buffer, &cmd_buffer->state.attachments[att_idx].ds,
1874 iview, layout, in_render_loop, false);
1875 }
1876
1877 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1878 }
1879
1880 /**
1881 * Set the clear depth/stencil values to the image's metadata.
1882 */
1883 static void
1884 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1885 struct radv_image *image,
1886 const VkImageSubresourceRange *range,
1887 VkClearDepthStencilValue ds_clear_value,
1888 VkImageAspectFlags aspects)
1889 {
1890 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1891 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel);
1892 uint32_t level_count = radv_get_levelCount(image, range);
1893
1894 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1895 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1896 /* Use the fastest way when both aspects are used. */
1897 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + 2 * level_count, cmd_buffer->state.predicating));
1898 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1899 S_370_WR_CONFIRM(1) |
1900 S_370_ENGINE_SEL(V_370_PFP));
1901 radeon_emit(cs, va);
1902 radeon_emit(cs, va >> 32);
1903
1904 for (uint32_t l = 0; l < level_count; l++) {
1905 radeon_emit(cs, ds_clear_value.stencil);
1906 radeon_emit(cs, fui(ds_clear_value.depth));
1907 }
1908 } else {
1909 /* Otherwise we need one WRITE_DATA packet per level. */
1910 for (uint32_t l = 0; l < level_count; l++) {
1911 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel + l);
1912 unsigned value;
1913
1914 if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1915 value = fui(ds_clear_value.depth);
1916 va += 4;
1917 } else {
1918 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1919 value = ds_clear_value.stencil;
1920 }
1921
1922 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1923 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1924 S_370_WR_CONFIRM(1) |
1925 S_370_ENGINE_SEL(V_370_PFP));
1926 radeon_emit(cs, va);
1927 radeon_emit(cs, va >> 32);
1928 radeon_emit(cs, value);
1929 }
1930 }
1931 }
1932
1933 /**
1934 * Update the TC-compat metadata value for this image.
1935 */
1936 static void
1937 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1938 struct radv_image *image,
1939 const VkImageSubresourceRange *range,
1940 uint32_t value)
1941 {
1942 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1943
1944 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug)
1945 return;
1946
1947 uint64_t va = radv_get_tc_compat_zrange_va(image, range->baseMipLevel);
1948 uint32_t level_count = radv_get_levelCount(image, range);
1949
1950 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + level_count, cmd_buffer->state.predicating));
1951 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1952 S_370_WR_CONFIRM(1) |
1953 S_370_ENGINE_SEL(V_370_PFP));
1954 radeon_emit(cs, va);
1955 radeon_emit(cs, va >> 32);
1956
1957 for (uint32_t l = 0; l < level_count; l++)
1958 radeon_emit(cs, value);
1959 }
1960
1961 static void
1962 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1963 const struct radv_image_view *iview,
1964 VkClearDepthStencilValue ds_clear_value)
1965 {
1966 VkImageSubresourceRange range = {
1967 .aspectMask = iview->aspect_mask,
1968 .baseMipLevel = iview->base_mip,
1969 .levelCount = iview->level_count,
1970 .baseArrayLayer = iview->base_layer,
1971 .layerCount = iview->layer_count,
1972 };
1973 uint32_t cond_val;
1974
1975 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1976 * depth clear value is 0.0f.
1977 */
1978 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1979
1980 radv_set_tc_compat_zrange_metadata(cmd_buffer, iview->image, &range,
1981 cond_val);
1982 }
1983
1984 /**
1985 * Update the clear depth/stencil values for this image.
1986 */
1987 void
1988 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1989 const struct radv_image_view *iview,
1990 VkClearDepthStencilValue ds_clear_value,
1991 VkImageAspectFlags aspects)
1992 {
1993 VkImageSubresourceRange range = {
1994 .aspectMask = iview->aspect_mask,
1995 .baseMipLevel = iview->base_mip,
1996 .levelCount = iview->level_count,
1997 .baseArrayLayer = iview->base_layer,
1998 .layerCount = iview->layer_count,
1999 };
2000 struct radv_image *image = iview->image;
2001
2002 assert(radv_image_has_htile(image));
2003
2004 radv_set_ds_clear_metadata(cmd_buffer, iview->image, &range,
2005 ds_clear_value, aspects);
2006
2007 if (radv_image_is_tc_compat_htile(image) &&
2008 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
2009 radv_update_tc_compat_zrange_metadata(cmd_buffer, iview,
2010 ds_clear_value);
2011 }
2012
2013 radv_update_bound_fast_clear_ds(cmd_buffer, iview, ds_clear_value,
2014 aspects);
2015 }
2016
2017 /**
2018 * Load the clear depth/stencil values from the image's metadata.
2019 */
2020 static void
2021 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
2022 const struct radv_image_view *iview)
2023 {
2024 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2025 const struct radv_image *image = iview->image;
2026 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
2027 uint64_t va = radv_get_ds_clear_value_va(image, iview->base_mip);
2028 unsigned reg_offset = 0, reg_count = 0;
2029
2030 if (!radv_image_has_htile(image))
2031 return;
2032
2033 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
2034 ++reg_count;
2035 } else {
2036 ++reg_offset;
2037 va += 4;
2038 }
2039 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
2040 ++reg_count;
2041
2042 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
2043
2044 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
2045 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG_INDEX, 3, 0));
2046 radeon_emit(cs, va);
2047 radeon_emit(cs, va >> 32);
2048 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
2049 radeon_emit(cs, reg_count);
2050 } else {
2051 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2052 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2053 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2054 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
2055 radeon_emit(cs, va);
2056 radeon_emit(cs, va >> 32);
2057 radeon_emit(cs, reg >> 2);
2058 radeon_emit(cs, 0);
2059
2060 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
2061 radeon_emit(cs, 0);
2062 }
2063 }
2064
2065 /*
2066 * With DCC some colors don't require CMASK elimination before being
2067 * used as a texture. This sets a predicate value to determine if the
2068 * cmask eliminate is required.
2069 */
2070 void
2071 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
2072 struct radv_image *image,
2073 const VkImageSubresourceRange *range, bool value)
2074 {
2075 uint64_t pred_val = value;
2076 uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
2077 uint32_t level_count = radv_get_levelCount(image, range);
2078 uint32_t count = 2 * level_count;
2079
2080 assert(radv_dcc_enabled(image, range->baseMipLevel));
2081
2082 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
2083 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
2084 S_370_WR_CONFIRM(1) |
2085 S_370_ENGINE_SEL(V_370_PFP));
2086 radeon_emit(cmd_buffer->cs, va);
2087 radeon_emit(cmd_buffer->cs, va >> 32);
2088
2089 for (uint32_t l = 0; l < level_count; l++) {
2090 radeon_emit(cmd_buffer->cs, pred_val);
2091 radeon_emit(cmd_buffer->cs, pred_val >> 32);
2092 }
2093 }
2094
2095 /**
2096 * Update the DCC predicate to reflect the compression state.
2097 */
2098 void
2099 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
2100 struct radv_image *image,
2101 const VkImageSubresourceRange *range, bool value)
2102 {
2103 uint64_t pred_val = value;
2104 uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
2105 uint32_t level_count = radv_get_levelCount(image, range);
2106 uint32_t count = 2 * level_count;
2107
2108 assert(radv_dcc_enabled(image, range->baseMipLevel));
2109
2110 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
2111 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
2112 S_370_WR_CONFIRM(1) |
2113 S_370_ENGINE_SEL(V_370_PFP));
2114 radeon_emit(cmd_buffer->cs, va);
2115 radeon_emit(cmd_buffer->cs, va >> 32);
2116
2117 for (uint32_t l = 0; l < level_count; l++) {
2118 radeon_emit(cmd_buffer->cs, pred_val);
2119 radeon_emit(cmd_buffer->cs, pred_val >> 32);
2120 }
2121 }
2122
2123 /**
2124 * Update the fast clear color values if the image is bound as a color buffer.
2125 */
2126 static void
2127 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
2128 struct radv_image *image,
2129 int cb_idx,
2130 uint32_t color_values[2])
2131 {
2132 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2133 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2134 uint32_t att_idx;
2135
2136 if (!cmd_buffer->state.attachments || !subpass)
2137 return;
2138
2139 att_idx = subpass->color_attachments[cb_idx].attachment;
2140 if (att_idx == VK_ATTACHMENT_UNUSED)
2141 return;
2142
2143 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
2144 return;
2145
2146 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
2147 radeon_emit(cs, color_values[0]);
2148 radeon_emit(cs, color_values[1]);
2149
2150 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2151 }
2152
2153 /**
2154 * Set the clear color values to the image's metadata.
2155 */
2156 static void
2157 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
2158 struct radv_image *image,
2159 const VkImageSubresourceRange *range,
2160 uint32_t color_values[2])
2161 {
2162 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2163 uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
2164 uint32_t level_count = radv_get_levelCount(image, range);
2165 uint32_t count = 2 * level_count;
2166
2167 assert(radv_image_has_cmask(image) ||
2168 radv_dcc_enabled(image, range->baseMipLevel));
2169
2170 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
2171 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
2172 S_370_WR_CONFIRM(1) |
2173 S_370_ENGINE_SEL(V_370_PFP));
2174 radeon_emit(cs, va);
2175 radeon_emit(cs, va >> 32);
2176
2177 for (uint32_t l = 0; l < level_count; l++) {
2178 radeon_emit(cs, color_values[0]);
2179 radeon_emit(cs, color_values[1]);
2180 }
2181 }
2182
2183 /**
2184 * Update the clear color values for this image.
2185 */
2186 void
2187 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
2188 const struct radv_image_view *iview,
2189 int cb_idx,
2190 uint32_t color_values[2])
2191 {
2192 struct radv_image *image = iview->image;
2193 VkImageSubresourceRange range = {
2194 .aspectMask = iview->aspect_mask,
2195 .baseMipLevel = iview->base_mip,
2196 .levelCount = iview->level_count,
2197 .baseArrayLayer = iview->base_layer,
2198 .layerCount = iview->layer_count,
2199 };
2200
2201 assert(radv_image_has_cmask(image) ||
2202 radv_dcc_enabled(image, iview->base_mip));
2203
2204 radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
2205
2206 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
2207 color_values);
2208 }
2209
2210 /**
2211 * Load the clear color values from the image's metadata.
2212 */
2213 static void
2214 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
2215 struct radv_image_view *iview,
2216 int cb_idx)
2217 {
2218 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2219 struct radv_image *image = iview->image;
2220 uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
2221
2222 if (!radv_image_has_cmask(image) &&
2223 !radv_dcc_enabled(image, iview->base_mip))
2224 return;
2225
2226 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
2227
2228 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
2229 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG_INDEX, 3, cmd_buffer->state.predicating));
2230 radeon_emit(cs, va);
2231 radeon_emit(cs, va >> 32);
2232 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
2233 radeon_emit(cs, 2);
2234 } else {
2235 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
2236 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2237 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2238 COPY_DATA_COUNT_SEL);
2239 radeon_emit(cs, va);
2240 radeon_emit(cs, va >> 32);
2241 radeon_emit(cs, reg >> 2);
2242 radeon_emit(cs, 0);
2243
2244 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
2245 radeon_emit(cs, 0);
2246 }
2247 }
2248
2249 static void
2250 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
2251 {
2252 int i;
2253 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
2254 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2255 bool color_big_page = true;
2256
2257 /* this may happen for inherited secondary recording */
2258 if (!framebuffer)
2259 return;
2260
2261 for (i = 0; i < 8; ++i) {
2262 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
2263 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2264 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2265 continue;
2266 }
2267
2268 int idx = subpass->color_attachments[i].attachment;
2269 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
2270 VkImageLayout layout = subpass->color_attachments[i].layout;
2271 bool in_render_loop = subpass->color_attachments[i].in_render_loop;
2272
2273 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, iview->bo);
2274
2275 assert(iview->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
2276 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
2277 radv_emit_fb_color_state(cmd_buffer, i, &cmd_buffer->state.attachments[idx].cb, iview, layout, in_render_loop);
2278
2279 radv_load_color_clear_metadata(cmd_buffer, iview, i);
2280
2281 /* BIG_PAGE is an optimization that can only be enabled if all
2282 * color targets are compatible.
2283 */
2284 color_big_page &= cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10_3 &&
2285 (iview->image->alignment % (64 * 1024) == 0);
2286 }
2287
2288 if (subpass->depth_stencil_attachment) {
2289 int idx = subpass->depth_stencil_attachment->attachment;
2290 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
2291 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
2292 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
2293 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, cmd_buffer->state.attachments[idx].iview->bo);
2294
2295 radv_emit_fb_ds_state(cmd_buffer, &cmd_buffer->state.attachments[idx].ds, iview, layout, in_render_loop);
2296
2297 if (cmd_buffer->state.attachments[idx].ds.offset_scale != cmd_buffer->state.offset_scale) {
2298 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2299 cmd_buffer->state.offset_scale = cmd_buffer->state.attachments[idx].ds.offset_scale;
2300 }
2301 radv_load_ds_clear_metadata(cmd_buffer, iview);
2302 } else {
2303 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9)
2304 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
2305 else
2306 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
2307
2308 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
2309 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
2310 }
2311 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2312 S_028208_BR_X(framebuffer->width) |
2313 S_028208_BR_Y(framebuffer->height));
2314
2315 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
2316 bool disable_constant_encode =
2317 cmd_buffer->device->physical_device->rad_info.has_dcc_constant_encode;
2318 enum chip_class chip_class =
2319 cmd_buffer->device->physical_device->rad_info.chip_class;
2320 uint8_t watermark = chip_class >= GFX10 ? 6 : 4;
2321
2322 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
2323 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class <= GFX9) |
2324 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
2325 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
2326 }
2327
2328 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2329 /* Enable CMASK/FMASK/DCC caching in L2 for small chips. */
2330 unsigned meta_write_policy, meta_read_policy;
2331 /* TODO: investigate whether LRU improves performance on other chips too */
2332 if (cmd_buffer->device->physical_device->rad_info.num_render_backends <= 4) {
2333 meta_write_policy = V_02807C_CACHE_LRU_WR; /* cache writes */
2334 meta_read_policy = V_02807C_CACHE_LRU_RD; /* cache reads */
2335 } else {
2336 meta_write_policy = V_02807C_CACHE_STREAM_WR; /* write combine */
2337 meta_read_policy = V_02807C_CACHE_NOA_RD; /* don't cache reads */
2338 }
2339
2340 radeon_set_context_reg(cmd_buffer->cs, R_028410_CB_RMI_GL2_CACHE_CONTROL,
2341 S_028410_CMASK_WR_POLICY(meta_write_policy) |
2342 S_028410_FMASK_WR_POLICY(meta_write_policy) |
2343 S_028410_DCC_WR_POLICY(meta_write_policy) |
2344 S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM_WR) |
2345 S_028410_CMASK_RD_POLICY(meta_read_policy) |
2346 S_028410_FMASK_RD_POLICY(meta_read_policy) |
2347 S_028410_DCC_RD_POLICY(meta_read_policy) |
2348 S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD) |
2349 S_028410_FMASK_BIG_PAGE(color_big_page) |
2350 S_028410_COLOR_BIG_PAGE(color_big_page));
2351 }
2352
2353 if (cmd_buffer->device->dfsm_allowed) {
2354 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2355 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
2356 }
2357
2358 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
2359 }
2360
2361 static void
2362 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer, bool indirect)
2363 {
2364 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2365 struct radv_cmd_state *state = &cmd_buffer->state;
2366
2367 if (state->index_type != state->last_index_type) {
2368 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2369 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2370 cs, R_03090C_VGT_INDEX_TYPE,
2371 2, state->index_type);
2372 } else {
2373 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2374 radeon_emit(cs, state->index_type);
2375 }
2376
2377 state->last_index_type = state->index_type;
2378 }
2379
2380 /* For the direct indexed draws we use DRAW_INDEX_2, which includes
2381 * the index_va and max_index_count already. */
2382 if (!indirect)
2383 return;
2384
2385 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2386 radeon_emit(cs, state->index_va);
2387 radeon_emit(cs, state->index_va >> 32);
2388
2389 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2390 radeon_emit(cs, state->max_index_count);
2391
2392 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
2393 }
2394
2395 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
2396 {
2397 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
2398 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2399 uint32_t pa_sc_mode_cntl_1 =
2400 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
2401 uint32_t db_count_control;
2402
2403 if(!cmd_buffer->state.active_occlusion_queries) {
2404 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2405 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2406 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2407 has_perfect_queries) {
2408 /* Re-enable out-of-order rasterization if the
2409 * bound pipeline supports it and if it's has
2410 * been disabled before starting any perfect
2411 * occlusion queries.
2412 */
2413 radeon_set_context_reg(cmd_buffer->cs,
2414 R_028A4C_PA_SC_MODE_CNTL_1,
2415 pa_sc_mode_cntl_1);
2416 }
2417 }
2418 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
2419 } else {
2420 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2421 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
2422 bool gfx10_perfect = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10 && has_perfect_queries;
2423
2424 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2425 /* Always enable PERFECT_ZPASS_COUNTS due to issues with partially
2426 * covered tiles, discards, and early depth testing. For more details,
2427 * see https://gitlab.freedesktop.org/mesa/mesa/-/issues/3218 */
2428 db_count_control =
2429 S_028004_PERFECT_ZPASS_COUNTS(1) |
2430 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
2431 S_028004_SAMPLE_RATE(sample_rate) |
2432 S_028004_ZPASS_ENABLE(1) |
2433 S_028004_SLICE_EVEN_ENABLE(1) |
2434 S_028004_SLICE_ODD_ENABLE(1);
2435
2436 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2437 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2438 has_perfect_queries) {
2439 /* If the bound pipeline has enabled
2440 * out-of-order rasterization, we should
2441 * disable it before starting any perfect
2442 * occlusion queries.
2443 */
2444 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
2445
2446 radeon_set_context_reg(cmd_buffer->cs,
2447 R_028A4C_PA_SC_MODE_CNTL_1,
2448 pa_sc_mode_cntl_1);
2449 }
2450 } else {
2451 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
2452 S_028004_SAMPLE_RATE(sample_rate);
2453 }
2454 }
2455
2456 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
2457
2458 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2459 }
2460
2461 static void
2462 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
2463 {
2464 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
2465
2466 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
2467 radv_emit_viewport(cmd_buffer);
2468
2469 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
2470 !cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
2471 radv_emit_scissor(cmd_buffer);
2472
2473 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
2474 radv_emit_line_width(cmd_buffer);
2475
2476 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
2477 radv_emit_blend_constants(cmd_buffer);
2478
2479 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
2480 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
2481 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
2482 radv_emit_stencil(cmd_buffer);
2483
2484 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
2485 radv_emit_depth_bounds(cmd_buffer);
2486
2487 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
2488 radv_emit_depth_bias(cmd_buffer);
2489
2490 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
2491 radv_emit_discard_rectangle(cmd_buffer);
2492
2493 if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)
2494 radv_emit_sample_locations(cmd_buffer);
2495
2496 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE)
2497 radv_emit_line_stipple(cmd_buffer);
2498
2499 if (states & (RADV_CMD_DIRTY_DYNAMIC_CULL_MODE |
2500 RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE))
2501 radv_emit_culling(cmd_buffer, states);
2502
2503 if (states & RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY)
2504 radv_emit_primitive_topology(cmd_buffer);
2505
2506 if (states & (RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE |
2507 RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE |
2508 RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP |
2509 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE |
2510 RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE |
2511 RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP))
2512 radv_emit_depth_control(cmd_buffer, states);
2513
2514 if (states & RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP)
2515 radv_emit_stencil_control(cmd_buffer);
2516
2517 cmd_buffer->state.dirty &= ~states;
2518 }
2519
2520 static void
2521 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
2522 VkPipelineBindPoint bind_point)
2523 {
2524 struct radv_descriptor_state *descriptors_state =
2525 radv_get_descriptors_state(cmd_buffer, bind_point);
2526 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
2527 unsigned bo_offset;
2528
2529 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
2530 set->mapped_ptr,
2531 &bo_offset))
2532 return;
2533
2534 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2535 set->va += bo_offset;
2536 }
2537
2538 static void
2539 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
2540 VkPipelineBindPoint bind_point)
2541 {
2542 struct radv_descriptor_state *descriptors_state =
2543 radv_get_descriptors_state(cmd_buffer, bind_point);
2544 uint32_t size = MAX_SETS * 4;
2545 uint32_t offset;
2546 void *ptr;
2547
2548 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
2549 256, &offset, &ptr))
2550 return;
2551
2552 for (unsigned i = 0; i < MAX_SETS; i++) {
2553 uint32_t *uptr = ((uint32_t *)ptr) + i;
2554 uint64_t set_va = 0;
2555 struct radv_descriptor_set *set = descriptors_state->sets[i];
2556 if (descriptors_state->valid & (1u << i))
2557 set_va = set->va;
2558 uptr[0] = set_va & 0xffffffff;
2559 }
2560
2561 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2562 va += offset;
2563
2564 if (cmd_buffer->state.pipeline) {
2565 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
2566 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2567 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2568
2569 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
2570 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
2571 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2572
2573 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
2574 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2575 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2576
2577 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2578 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
2579 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2580
2581 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2582 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
2583 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2584 }
2585
2586 if (cmd_buffer->state.compute_pipeline)
2587 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
2588 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2589 }
2590
2591 static void
2592 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
2593 VkShaderStageFlags stages)
2594 {
2595 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2596 VK_PIPELINE_BIND_POINT_COMPUTE :
2597 VK_PIPELINE_BIND_POINT_GRAPHICS;
2598 struct radv_descriptor_state *descriptors_state =
2599 radv_get_descriptors_state(cmd_buffer, bind_point);
2600 struct radv_cmd_state *state = &cmd_buffer->state;
2601 bool flush_indirect_descriptors;
2602
2603 if (!descriptors_state->dirty)
2604 return;
2605
2606 if (descriptors_state->push_dirty)
2607 radv_flush_push_descriptors(cmd_buffer, bind_point);
2608
2609 flush_indirect_descriptors =
2610 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
2611 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
2612 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
2613 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
2614
2615 if (flush_indirect_descriptors)
2616 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
2617
2618 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2619 cmd_buffer->cs,
2620 MAX_SETS * MESA_SHADER_STAGES * 4);
2621
2622 if (cmd_buffer->state.pipeline) {
2623 radv_foreach_stage(stage, stages) {
2624 if (!cmd_buffer->state.pipeline->shaders[stage])
2625 continue;
2626
2627 radv_emit_descriptor_pointers(cmd_buffer,
2628 cmd_buffer->state.pipeline,
2629 descriptors_state, stage);
2630 }
2631 }
2632
2633 if (cmd_buffer->state.compute_pipeline &&
2634 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
2635 radv_emit_descriptor_pointers(cmd_buffer,
2636 cmd_buffer->state.compute_pipeline,
2637 descriptors_state,
2638 MESA_SHADER_COMPUTE);
2639 }
2640
2641 descriptors_state->dirty = 0;
2642 descriptors_state->push_dirty = false;
2643
2644 assert(cmd_buffer->cs->cdw <= cdw_max);
2645
2646 if (unlikely(cmd_buffer->device->trace_bo))
2647 radv_save_descriptors(cmd_buffer, bind_point);
2648 }
2649
2650 static void
2651 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
2652 VkShaderStageFlags stages)
2653 {
2654 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
2655 ? cmd_buffer->state.compute_pipeline
2656 : cmd_buffer->state.pipeline;
2657 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2658 VK_PIPELINE_BIND_POINT_COMPUTE :
2659 VK_PIPELINE_BIND_POINT_GRAPHICS;
2660 struct radv_descriptor_state *descriptors_state =
2661 radv_get_descriptors_state(cmd_buffer, bind_point);
2662 struct radv_pipeline_layout *layout = pipeline->layout;
2663 struct radv_shader_variant *shader, *prev_shader;
2664 bool need_push_constants = false;
2665 unsigned offset;
2666 void *ptr;
2667 uint64_t va;
2668
2669 stages &= cmd_buffer->push_constant_stages;
2670 if (!stages ||
2671 (!layout->push_constant_size && !layout->dynamic_offset_count))
2672 return;
2673
2674 radv_foreach_stage(stage, stages) {
2675 shader = radv_get_shader(pipeline, stage);
2676 if (!shader)
2677 continue;
2678
2679 need_push_constants |= shader->info.loads_push_constants;
2680 need_push_constants |= shader->info.loads_dynamic_offsets;
2681
2682 uint8_t base = shader->info.base_inline_push_consts;
2683 uint8_t count = shader->info.num_inline_push_consts;
2684
2685 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
2686 AC_UD_INLINE_PUSH_CONSTANTS,
2687 count,
2688 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
2689 }
2690
2691 if (need_push_constants) {
2692 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
2693 16 * layout->dynamic_offset_count,
2694 256, &offset, &ptr))
2695 return;
2696
2697 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
2698 memcpy((char*)ptr + layout->push_constant_size,
2699 descriptors_state->dynamic_buffers,
2700 16 * layout->dynamic_offset_count);
2701
2702 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2703 va += offset;
2704
2705 ASSERTED unsigned cdw_max =
2706 radeon_check_space(cmd_buffer->device->ws,
2707 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
2708
2709 prev_shader = NULL;
2710 radv_foreach_stage(stage, stages) {
2711 shader = radv_get_shader(pipeline, stage);
2712
2713 /* Avoid redundantly emitting the address for merged stages. */
2714 if (shader && shader != prev_shader) {
2715 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
2716 AC_UD_PUSH_CONSTANTS, va);
2717
2718 prev_shader = shader;
2719 }
2720 }
2721 assert(cmd_buffer->cs->cdw <= cdw_max);
2722 }
2723
2724 cmd_buffer->push_constant_stages &= ~stages;
2725 }
2726
2727 static void
2728 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
2729 bool pipeline_is_dirty)
2730 {
2731 if ((pipeline_is_dirty ||
2732 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
2733 cmd_buffer->state.pipeline->num_vertex_bindings &&
2734 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.has_vertex_buffers) {
2735 unsigned vb_offset;
2736 void *vb_ptr;
2737 uint32_t i = 0;
2738 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
2739 uint64_t va;
2740
2741 /* allocate some descriptor state for vertex buffers */
2742 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2743 &vb_offset, &vb_ptr))
2744 return;
2745
2746 for (i = 0; i < count; i++) {
2747 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2748 uint32_t offset;
2749 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2750 unsigned num_records;
2751 unsigned stride;
2752
2753 if (!buffer)
2754 continue;
2755
2756 va = radv_buffer_get_va(buffer->bo);
2757
2758 offset = cmd_buffer->vertex_bindings[i].offset;
2759 va += offset + buffer->offset;
2760
2761 if (cmd_buffer->vertex_bindings[i].size) {
2762 num_records = cmd_buffer->vertex_bindings[i].size;
2763 } else {
2764 num_records = buffer->size - offset;
2765 }
2766
2767 if (cmd_buffer->state.pipeline->graphics.uses_dynamic_stride) {
2768 stride = cmd_buffer->vertex_bindings[i].stride;
2769 } else {
2770 stride = cmd_buffer->state.pipeline->binding_stride[i];
2771 }
2772
2773 if (cmd_buffer->device->physical_device->rad_info.chip_class != GFX8 && stride)
2774 num_records /= stride;
2775
2776 uint32_t rsrc_word3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2777 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2778 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2779 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2780
2781 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2782 /* OOB_SELECT chooses the out-of-bounds check:
2783 * - 1: index >= NUM_RECORDS (Structured)
2784 * - 3: offset >= NUM_RECORDS (Raw)
2785 */
2786 int oob_select = stride ? V_008F0C_OOB_SELECT_STRUCTURED : V_008F0C_OOB_SELECT_RAW;
2787
2788 rsrc_word3 |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT) |
2789 S_008F0C_OOB_SELECT(oob_select) |
2790 S_008F0C_RESOURCE_LEVEL(1);
2791 } else {
2792 rsrc_word3 |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2793 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2794 }
2795
2796 desc[0] = va;
2797 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2798 desc[2] = num_records;
2799 desc[3] = rsrc_word3;
2800 }
2801
2802 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2803 va += vb_offset;
2804
2805 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2806 AC_UD_VS_VERTEX_BUFFERS, va);
2807
2808 cmd_buffer->state.vb_va = va;
2809 cmd_buffer->state.vb_size = count * 16;
2810 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2811 }
2812 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2813 }
2814
2815 static void
2816 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2817 {
2818 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2819 struct radv_userdata_info *loc;
2820 uint32_t base_reg;
2821
2822 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2823 if (!radv_get_shader(pipeline, stage))
2824 continue;
2825
2826 loc = radv_lookup_user_sgpr(pipeline, stage,
2827 AC_UD_STREAMOUT_BUFFERS);
2828 if (loc->sgpr_idx == -1)
2829 continue;
2830
2831 base_reg = pipeline->user_data_0[stage];
2832
2833 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2834 base_reg + loc->sgpr_idx * 4, va, false);
2835 }
2836
2837 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
2838 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2839 if (loc->sgpr_idx != -1) {
2840 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2841
2842 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2843 base_reg + loc->sgpr_idx * 4, va, false);
2844 }
2845 }
2846 }
2847
2848 static void
2849 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2850 {
2851 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2852 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2853 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2854 unsigned so_offset;
2855 void *so_ptr;
2856 uint64_t va;
2857
2858 /* Allocate some descriptor state for streamout buffers. */
2859 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2860 MAX_SO_BUFFERS * 16, 256,
2861 &so_offset, &so_ptr))
2862 return;
2863
2864 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2865 struct radv_buffer *buffer = sb[i].buffer;
2866 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2867
2868 if (!(so->enabled_mask & (1 << i)))
2869 continue;
2870
2871 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2872
2873 va += sb[i].offset;
2874
2875 /* Set the descriptor.
2876 *
2877 * On GFX8, the format must be non-INVALID, otherwise
2878 * the buffer will be considered not bound and store
2879 * instructions will be no-ops.
2880 */
2881 uint32_t size = 0xffffffff;
2882
2883 /* Compute the correct buffer size for NGG streamout
2884 * because it's used to determine the max emit per
2885 * buffer.
2886 */
2887 if (cmd_buffer->device->physical_device->use_ngg_streamout)
2888 size = buffer->size - sb[i].offset;
2889
2890 uint32_t rsrc_word3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2891 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2892 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2893 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2894
2895 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2896 rsrc_word3 |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2897 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
2898 S_008F0C_RESOURCE_LEVEL(1);
2899 } else {
2900 rsrc_word3 |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2901 }
2902
2903 desc[0] = va;
2904 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2905 desc[2] = size;
2906 desc[3] = rsrc_word3;
2907 }
2908
2909 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2910 va += so_offset;
2911
2912 radv_emit_streamout_buffers(cmd_buffer, va);
2913 }
2914
2915 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2916 }
2917
2918 static void
2919 radv_flush_ngg_gs_state(struct radv_cmd_buffer *cmd_buffer)
2920 {
2921 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2922 struct radv_userdata_info *loc;
2923 uint32_t ngg_gs_state = 0;
2924 uint32_t base_reg;
2925
2926 if (!radv_pipeline_has_gs(pipeline) ||
2927 !radv_pipeline_has_ngg(pipeline))
2928 return;
2929
2930 /* By default NGG GS queries are disabled but they are enabled if the
2931 * command buffer has active GDS queries or if it's a secondary command
2932 * buffer that inherits the number of generated primitives.
2933 */
2934 if (cmd_buffer->state.active_pipeline_gds_queries ||
2935 (cmd_buffer->state.inherited_pipeline_statistics & VK_QUERY_PIPELINE_STATISTIC_GEOMETRY_SHADER_PRIMITIVES_BIT))
2936 ngg_gs_state = 1;
2937
2938 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_GEOMETRY,
2939 AC_UD_NGG_GS_STATE);
2940 base_reg = pipeline->user_data_0[MESA_SHADER_GEOMETRY];
2941 assert(loc->sgpr_idx != -1);
2942
2943 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
2944 ngg_gs_state);
2945 }
2946
2947 static void
2948 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2949 {
2950 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2951 radv_flush_streamout_descriptors(cmd_buffer);
2952 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2953 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2954 radv_flush_ngg_gs_state(cmd_buffer);
2955 }
2956
2957 struct radv_draw_info {
2958 /**
2959 * Number of vertices.
2960 */
2961 uint32_t count;
2962
2963 /**
2964 * Index of the first vertex.
2965 */
2966 int32_t vertex_offset;