ac: declare an enum for the OOB select field on GFX10
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 bool src_render_loop,
58 VkImageLayout dst_layout,
59 bool dst_render_loop,
60 uint32_t src_family,
61 uint32_t dst_family,
62 const VkImageSubresourceRange *range,
63 struct radv_sample_locations_state *sample_locs);
64
65 const struct radv_dynamic_state default_dynamic_state = {
66 .viewport = {
67 .count = 0,
68 },
69 .scissor = {
70 .count = 0,
71 },
72 .line_width = 1.0f,
73 .depth_bias = {
74 .bias = 0.0f,
75 .clamp = 0.0f,
76 .slope = 0.0f,
77 },
78 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
79 .depth_bounds = {
80 .min = 0.0f,
81 .max = 1.0f,
82 },
83 .stencil_compare_mask = {
84 .front = ~0u,
85 .back = ~0u,
86 },
87 .stencil_write_mask = {
88 .front = ~0u,
89 .back = ~0u,
90 },
91 .stencil_reference = {
92 .front = 0u,
93 .back = 0u,
94 },
95 };
96
97 static void
98 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
99 const struct radv_dynamic_state *src)
100 {
101 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
102 uint32_t copy_mask = src->mask;
103 uint32_t dest_mask = 0;
104
105 /* Make sure to copy the number of viewports/scissors because they can
106 * only be specified at pipeline creation time.
107 */
108 dest->viewport.count = src->viewport.count;
109 dest->scissor.count = src->scissor.count;
110 dest->discard_rectangle.count = src->discard_rectangle.count;
111 dest->sample_location.count = src->sample_location.count;
112
113 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
114 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
115 src->viewport.count * sizeof(VkViewport))) {
116 typed_memcpy(dest->viewport.viewports,
117 src->viewport.viewports,
118 src->viewport.count);
119 dest_mask |= RADV_DYNAMIC_VIEWPORT;
120 }
121 }
122
123 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
124 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
125 src->scissor.count * sizeof(VkRect2D))) {
126 typed_memcpy(dest->scissor.scissors,
127 src->scissor.scissors, src->scissor.count);
128 dest_mask |= RADV_DYNAMIC_SCISSOR;
129 }
130 }
131
132 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
133 if (dest->line_width != src->line_width) {
134 dest->line_width = src->line_width;
135 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
136 }
137 }
138
139 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
140 if (memcmp(&dest->depth_bias, &src->depth_bias,
141 sizeof(src->depth_bias))) {
142 dest->depth_bias = src->depth_bias;
143 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
144 }
145 }
146
147 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
148 if (memcmp(&dest->blend_constants, &src->blend_constants,
149 sizeof(src->blend_constants))) {
150 typed_memcpy(dest->blend_constants,
151 src->blend_constants, 4);
152 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
153 }
154 }
155
156 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
157 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
158 sizeof(src->depth_bounds))) {
159 dest->depth_bounds = src->depth_bounds;
160 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
161 }
162 }
163
164 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
165 if (memcmp(&dest->stencil_compare_mask,
166 &src->stencil_compare_mask,
167 sizeof(src->stencil_compare_mask))) {
168 dest->stencil_compare_mask = src->stencil_compare_mask;
169 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
170 }
171 }
172
173 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
174 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
175 sizeof(src->stencil_write_mask))) {
176 dest->stencil_write_mask = src->stencil_write_mask;
177 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
178 }
179 }
180
181 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
182 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
183 sizeof(src->stencil_reference))) {
184 dest->stencil_reference = src->stencil_reference;
185 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
186 }
187 }
188
189 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
190 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
191 src->discard_rectangle.count * sizeof(VkRect2D))) {
192 typed_memcpy(dest->discard_rectangle.rectangles,
193 src->discard_rectangle.rectangles,
194 src->discard_rectangle.count);
195 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
196 }
197 }
198
199 if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
200 if (dest->sample_location.per_pixel != src->sample_location.per_pixel ||
201 dest->sample_location.grid_size.width != src->sample_location.grid_size.width ||
202 dest->sample_location.grid_size.height != src->sample_location.grid_size.height ||
203 memcmp(&dest->sample_location.locations,
204 &src->sample_location.locations,
205 src->sample_location.count * sizeof(VkSampleLocationEXT))) {
206 dest->sample_location.per_pixel = src->sample_location.per_pixel;
207 dest->sample_location.grid_size = src->sample_location.grid_size;
208 typed_memcpy(dest->sample_location.locations,
209 src->sample_location.locations,
210 src->sample_location.count);
211 dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
212 }
213 }
214
215 cmd_buffer->state.dirty |= dest_mask;
216 }
217
218 static void
219 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
220 struct radv_pipeline *pipeline)
221 {
222 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
223 struct radv_shader_info *info;
224
225 if (!pipeline->streamout_shader ||
226 cmd_buffer->device->physical_device->use_ngg_streamout)
227 return;
228
229 info = &pipeline->streamout_shader->info;
230 for (int i = 0; i < MAX_SO_BUFFERS; i++)
231 so->stride_in_dw[i] = info->so.strides[i];
232
233 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
234 }
235
236 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
237 {
238 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
239 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
240 }
241
242 enum ring_type radv_queue_family_to_ring(int f) {
243 switch (f) {
244 case RADV_QUEUE_GENERAL:
245 return RING_GFX;
246 case RADV_QUEUE_COMPUTE:
247 return RING_COMPUTE;
248 case RADV_QUEUE_TRANSFER:
249 return RING_DMA;
250 default:
251 unreachable("Unknown queue family");
252 }
253 }
254
255 static VkResult radv_create_cmd_buffer(
256 struct radv_device * device,
257 struct radv_cmd_pool * pool,
258 VkCommandBufferLevel level,
259 VkCommandBuffer* pCommandBuffer)
260 {
261 struct radv_cmd_buffer *cmd_buffer;
262 unsigned ring;
263 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
264 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
265 if (cmd_buffer == NULL)
266 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
267
268 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
269 cmd_buffer->device = device;
270 cmd_buffer->pool = pool;
271 cmd_buffer->level = level;
272
273 if (pool) {
274 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
275 cmd_buffer->queue_family_index = pool->queue_family_index;
276
277 } else {
278 /* Init the pool_link so we can safely call list_del when we destroy
279 * the command buffer
280 */
281 list_inithead(&cmd_buffer->pool_link);
282 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
283 }
284
285 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
286
287 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
288 if (!cmd_buffer->cs) {
289 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
290 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
291 }
292
293 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
294
295 list_inithead(&cmd_buffer->upload.list);
296
297 return VK_SUCCESS;
298 }
299
300 static void
301 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
302 {
303 list_del(&cmd_buffer->pool_link);
304
305 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
306 &cmd_buffer->upload.list, list) {
307 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
308 list_del(&up->list);
309 free(up);
310 }
311
312 if (cmd_buffer->upload.upload_bo)
313 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
314 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
315
316 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
317 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
318
319 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
320 }
321
322 static VkResult
323 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
324 {
325 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
326
327 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
328 &cmd_buffer->upload.list, list) {
329 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
330 list_del(&up->list);
331 free(up);
332 }
333
334 cmd_buffer->push_constant_stages = 0;
335 cmd_buffer->scratch_size_per_wave_needed = 0;
336 cmd_buffer->scratch_waves_wanted = 0;
337 cmd_buffer->compute_scratch_size_per_wave_needed = 0;
338 cmd_buffer->compute_scratch_waves_wanted = 0;
339 cmd_buffer->esgs_ring_size_needed = 0;
340 cmd_buffer->gsvs_ring_size_needed = 0;
341 cmd_buffer->tess_rings_needed = false;
342 cmd_buffer->gds_needed = false;
343 cmd_buffer->sample_positions_needed = false;
344
345 if (cmd_buffer->upload.upload_bo)
346 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
347 cmd_buffer->upload.upload_bo);
348 cmd_buffer->upload.offset = 0;
349
350 cmd_buffer->record_result = VK_SUCCESS;
351
352 memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
353
354 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
355 cmd_buffer->descriptors[i].dirty = 0;
356 cmd_buffer->descriptors[i].valid = 0;
357 cmd_buffer->descriptors[i].push_dirty = false;
358 }
359
360 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
361 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
362 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
363 unsigned fence_offset, eop_bug_offset;
364 void *fence_ptr;
365
366 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
367 &fence_ptr);
368
369 cmd_buffer->gfx9_fence_va =
370 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
371 cmd_buffer->gfx9_fence_va += fence_offset;
372
373 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
374 /* Allocate a buffer for the EOP bug on GFX9. */
375 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
376 &eop_bug_offset, &fence_ptr);
377 cmd_buffer->gfx9_eop_bug_va =
378 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
379 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
380 }
381 }
382
383 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
384
385 return cmd_buffer->record_result;
386 }
387
388 static bool
389 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
390 uint64_t min_needed)
391 {
392 uint64_t new_size;
393 struct radeon_winsys_bo *bo;
394 struct radv_cmd_buffer_upload *upload;
395 struct radv_device *device = cmd_buffer->device;
396
397 new_size = MAX2(min_needed, 16 * 1024);
398 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
399
400 bo = device->ws->buffer_create(device->ws,
401 new_size, 4096,
402 RADEON_DOMAIN_GTT,
403 RADEON_FLAG_CPU_ACCESS|
404 RADEON_FLAG_NO_INTERPROCESS_SHARING |
405 RADEON_FLAG_32BIT,
406 RADV_BO_PRIORITY_UPLOAD_BUFFER);
407
408 if (!bo) {
409 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
410 return false;
411 }
412
413 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
414 if (cmd_buffer->upload.upload_bo) {
415 upload = malloc(sizeof(*upload));
416
417 if (!upload) {
418 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
419 device->ws->buffer_destroy(bo);
420 return false;
421 }
422
423 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
424 list_add(&upload->list, &cmd_buffer->upload.list);
425 }
426
427 cmd_buffer->upload.upload_bo = bo;
428 cmd_buffer->upload.size = new_size;
429 cmd_buffer->upload.offset = 0;
430 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
431
432 if (!cmd_buffer->upload.map) {
433 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
434 return false;
435 }
436
437 return true;
438 }
439
440 bool
441 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
442 unsigned size,
443 unsigned alignment,
444 unsigned *out_offset,
445 void **ptr)
446 {
447 assert(util_is_power_of_two_nonzero(alignment));
448
449 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
450 if (offset + size > cmd_buffer->upload.size) {
451 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
452 return false;
453 offset = 0;
454 }
455
456 *out_offset = offset;
457 *ptr = cmd_buffer->upload.map + offset;
458
459 cmd_buffer->upload.offset = offset + size;
460 return true;
461 }
462
463 bool
464 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
465 unsigned size, unsigned alignment,
466 const void *data, unsigned *out_offset)
467 {
468 uint8_t *ptr;
469
470 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
471 out_offset, (void **)&ptr))
472 return false;
473
474 if (ptr)
475 memcpy(ptr, data, size);
476
477 return true;
478 }
479
480 static void
481 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
482 unsigned count, const uint32_t *data)
483 {
484 struct radeon_cmdbuf *cs = cmd_buffer->cs;
485
486 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
487
488 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
489 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
490 S_370_WR_CONFIRM(1) |
491 S_370_ENGINE_SEL(V_370_ME));
492 radeon_emit(cs, va);
493 radeon_emit(cs, va >> 32);
494 radeon_emit_array(cs, data, count);
495 }
496
497 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
498 {
499 struct radv_device *device = cmd_buffer->device;
500 struct radeon_cmdbuf *cs = cmd_buffer->cs;
501 uint64_t va;
502
503 va = radv_buffer_get_va(device->trace_bo);
504 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
505 va += 4;
506
507 ++cmd_buffer->state.trace_id;
508 radv_emit_write_data_packet(cmd_buffer, va, 1,
509 &cmd_buffer->state.trace_id);
510
511 radeon_check_space(cmd_buffer->device->ws, cs, 2);
512
513 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
514 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
515 }
516
517 static void
518 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
519 enum radv_cmd_flush_bits flags)
520 {
521 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
522 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
523 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
524
525 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
526
527 /* Force wait for graphics or compute engines to be idle. */
528 si_cs_emit_cache_flush(cmd_buffer->cs,
529 cmd_buffer->device->physical_device->rad_info.chip_class,
530 &cmd_buffer->gfx9_fence_idx,
531 cmd_buffer->gfx9_fence_va,
532 radv_cmd_buffer_uses_mec(cmd_buffer),
533 flags, cmd_buffer->gfx9_eop_bug_va);
534 }
535
536 if (unlikely(cmd_buffer->device->trace_bo))
537 radv_cmd_buffer_trace_emit(cmd_buffer);
538 }
539
540 static void
541 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
542 struct radv_pipeline *pipeline, enum ring_type ring)
543 {
544 struct radv_device *device = cmd_buffer->device;
545 uint32_t data[2];
546 uint64_t va;
547
548 va = radv_buffer_get_va(device->trace_bo);
549
550 switch (ring) {
551 case RING_GFX:
552 va += 8;
553 break;
554 case RING_COMPUTE:
555 va += 16;
556 break;
557 default:
558 assert(!"invalid ring type");
559 }
560
561 uint64_t pipeline_address = (uintptr_t)pipeline;
562 data[0] = pipeline_address;
563 data[1] = pipeline_address >> 32;
564
565 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
566 }
567
568 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
569 VkPipelineBindPoint bind_point,
570 struct radv_descriptor_set *set,
571 unsigned idx)
572 {
573 struct radv_descriptor_state *descriptors_state =
574 radv_get_descriptors_state(cmd_buffer, bind_point);
575
576 descriptors_state->sets[idx] = set;
577
578 descriptors_state->valid |= (1u << idx); /* active descriptors */
579 descriptors_state->dirty |= (1u << idx);
580 }
581
582 static void
583 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
584 VkPipelineBindPoint bind_point)
585 {
586 struct radv_descriptor_state *descriptors_state =
587 radv_get_descriptors_state(cmd_buffer, bind_point);
588 struct radv_device *device = cmd_buffer->device;
589 uint32_t data[MAX_SETS * 2] = {};
590 uint64_t va;
591 unsigned i;
592 va = radv_buffer_get_va(device->trace_bo) + 24;
593
594 for_each_bit(i, descriptors_state->valid) {
595 struct radv_descriptor_set *set = descriptors_state->sets[i];
596 data[i * 2] = (uint64_t)(uintptr_t)set;
597 data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
598 }
599
600 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
601 }
602
603 struct radv_userdata_info *
604 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
605 gl_shader_stage stage,
606 int idx)
607 {
608 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
609 return &shader->info.user_sgprs_locs.shader_data[idx];
610 }
611
612 static void
613 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
614 struct radv_pipeline *pipeline,
615 gl_shader_stage stage,
616 int idx, uint64_t va)
617 {
618 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
619 uint32_t base_reg = pipeline->user_data_0[stage];
620 if (loc->sgpr_idx == -1)
621 return;
622
623 assert(loc->num_sgprs == 1);
624
625 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
626 base_reg + loc->sgpr_idx * 4, va, false);
627 }
628
629 static void
630 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
631 struct radv_pipeline *pipeline,
632 struct radv_descriptor_state *descriptors_state,
633 gl_shader_stage stage)
634 {
635 struct radv_device *device = cmd_buffer->device;
636 struct radeon_cmdbuf *cs = cmd_buffer->cs;
637 uint32_t sh_base = pipeline->user_data_0[stage];
638 struct radv_userdata_locations *locs =
639 &pipeline->shaders[stage]->info.user_sgprs_locs;
640 unsigned mask = locs->descriptor_sets_enabled;
641
642 mask &= descriptors_state->dirty & descriptors_state->valid;
643
644 while (mask) {
645 int start, count;
646
647 u_bit_scan_consecutive_range(&mask, &start, &count);
648
649 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
650 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
651
652 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
653 for (int i = 0; i < count; i++) {
654 struct radv_descriptor_set *set =
655 descriptors_state->sets[start + i];
656
657 radv_emit_shader_pointer_body(device, cs, set->va, true);
658 }
659 }
660 }
661
662 /**
663 * Convert the user sample locations to hardware sample locations (the values
664 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
665 */
666 static void
667 radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
668 uint32_t x, uint32_t y, VkOffset2D *sample_locs)
669 {
670 uint32_t x_offset = x % state->grid_size.width;
671 uint32_t y_offset = y % state->grid_size.height;
672 uint32_t num_samples = (uint32_t)state->per_pixel;
673 VkSampleLocationEXT *user_locs;
674 uint32_t pixel_offset;
675
676 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
677
678 assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
679 user_locs = &state->locations[pixel_offset];
680
681 for (uint32_t i = 0; i < num_samples; i++) {
682 float shifted_pos_x = user_locs[i].x - 0.5;
683 float shifted_pos_y = user_locs[i].y - 0.5;
684
685 int32_t scaled_pos_x = floor(shifted_pos_x * 16);
686 int32_t scaled_pos_y = floor(shifted_pos_y * 16);
687
688 sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
689 sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
690 }
691 }
692
693 /**
694 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
695 * locations.
696 */
697 static void
698 radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
699 uint32_t *sample_locs_pixel)
700 {
701 for (uint32_t i = 0; i < num_samples; i++) {
702 uint32_t sample_reg_idx = i / 4;
703 uint32_t sample_loc_idx = i % 4;
704 int32_t pos_x = sample_locs[i].x;
705 int32_t pos_y = sample_locs[i].y;
706
707 uint32_t shift_x = 8 * sample_loc_idx;
708 uint32_t shift_y = shift_x + 4;
709
710 sample_locs_pixel[sample_reg_idx] |= (pos_x & 0xf) << shift_x;
711 sample_locs_pixel[sample_reg_idx] |= (pos_y & 0xf) << shift_y;
712 }
713 }
714
715 /**
716 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
717 * sample locations.
718 */
719 static uint64_t
720 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer,
721 VkOffset2D *sample_locs,
722 uint32_t num_samples)
723 {
724 uint32_t centroid_priorities[num_samples];
725 uint32_t sample_mask = num_samples - 1;
726 uint32_t distances[num_samples];
727 uint64_t centroid_priority = 0;
728
729 /* Compute the distances from center for each sample. */
730 for (int i = 0; i < num_samples; i++) {
731 distances[i] = (sample_locs[i].x * sample_locs[i].x) +
732 (sample_locs[i].y * sample_locs[i].y);
733 }
734
735 /* Compute the centroid priorities by looking at the distances array. */
736 for (int i = 0; i < num_samples; i++) {
737 uint32_t min_idx = 0;
738
739 for (int j = 1; j < num_samples; j++) {
740 if (distances[j] < distances[min_idx])
741 min_idx = j;
742 }
743
744 centroid_priorities[i] = min_idx;
745 distances[min_idx] = 0xffffffff;
746 }
747
748 /* Compute the final centroid priority. */
749 for (int i = 0; i < 8; i++) {
750 centroid_priority |=
751 centroid_priorities[i & sample_mask] << (i * 4);
752 }
753
754 return centroid_priority << 32 | centroid_priority;
755 }
756
757 /**
758 * Emit the sample locations that are specified with VK_EXT_sample_locations.
759 */
760 static void
761 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
762 {
763 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
764 struct radv_multisample_state *ms = &pipeline->graphics.ms;
765 struct radv_sample_locations_state *sample_location =
766 &cmd_buffer->state.dynamic.sample_location;
767 uint32_t num_samples = (uint32_t)sample_location->per_pixel;
768 struct radeon_cmdbuf *cs = cmd_buffer->cs;
769 uint32_t sample_locs_pixel[4][2] = {};
770 VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
771 uint32_t max_sample_dist = 0;
772 uint64_t centroid_priority;
773
774 if (!cmd_buffer->state.dynamic.sample_location.count)
775 return;
776
777 /* Convert the user sample locations to hardware sample locations. */
778 radv_convert_user_sample_locs(sample_location, 0, 0, sample_locs[0]);
779 radv_convert_user_sample_locs(sample_location, 1, 0, sample_locs[1]);
780 radv_convert_user_sample_locs(sample_location, 0, 1, sample_locs[2]);
781 radv_convert_user_sample_locs(sample_location, 1, 1, sample_locs[3]);
782
783 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
784 for (uint32_t i = 0; i < 4; i++) {
785 radv_compute_sample_locs_pixel(num_samples, sample_locs[i],
786 sample_locs_pixel[i]);
787 }
788
789 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
790 centroid_priority =
791 radv_compute_centroid_priority(cmd_buffer, sample_locs[0],
792 num_samples);
793
794 /* Compute the maximum sample distance from the specified locations. */
795 for (uint32_t i = 0; i < num_samples; i++) {
796 VkOffset2D offset = sample_locs[0][i];
797 max_sample_dist = MAX2(max_sample_dist,
798 MAX2(abs(offset.x), abs(offset.y)));
799 }
800
801 /* Emit the specified user sample locations. */
802 switch (num_samples) {
803 case 2:
804 case 4:
805 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
806 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
807 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
808 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
809 break;
810 case 8:
811 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
812 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
813 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
814 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
815 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs_pixel[0][1]);
816 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs_pixel[1][1]);
817 radeon_set_context_reg(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs_pixel[2][1]);
818 radeon_set_context_reg(cs, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs_pixel[3][1]);
819 break;
820 default:
821 unreachable("invalid number of samples");
822 }
823
824 /* Emit the maximum sample distance and the centroid priority. */
825 uint32_t pa_sc_aa_config = ms->pa_sc_aa_config;
826
827 pa_sc_aa_config &= C_028BE0_MAX_SAMPLE_DIST;
828 pa_sc_aa_config |= S_028BE0_MAX_SAMPLE_DIST(max_sample_dist);
829
830 radeon_set_context_reg_seq(cs, R_028BE0_PA_SC_AA_CONFIG, 1);
831 radeon_emit(cs, pa_sc_aa_config);
832
833 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
834 radeon_emit(cs, centroid_priority);
835 radeon_emit(cs, centroid_priority >> 32);
836
837 /* GFX9: Flush DFSM when the AA mode changes. */
838 if (cmd_buffer->device->dfsm_allowed) {
839 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
840 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
841 }
842
843 cmd_buffer->state.context_roll_without_scissor_emitted = true;
844 }
845
846 static void
847 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
848 struct radv_pipeline *pipeline,
849 gl_shader_stage stage,
850 int idx, int count, uint32_t *values)
851 {
852 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
853 uint32_t base_reg = pipeline->user_data_0[stage];
854 if (loc->sgpr_idx == -1)
855 return;
856
857 assert(loc->num_sgprs == count);
858
859 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
860 radeon_emit_array(cmd_buffer->cs, values, count);
861 }
862
863 static void
864 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
865 struct radv_pipeline *pipeline)
866 {
867 int num_samples = pipeline->graphics.ms.num_samples;
868 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
869
870 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.needs_sample_positions)
871 cmd_buffer->sample_positions_needed = true;
872
873 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
874 return;
875
876 radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
877
878 cmd_buffer->state.context_roll_without_scissor_emitted = true;
879 }
880
881 static void
882 radv_update_binning_state(struct radv_cmd_buffer *cmd_buffer,
883 struct radv_pipeline *pipeline)
884 {
885 const struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
886
887
888 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
889 return;
890
891 if (old_pipeline &&
892 old_pipeline->graphics.binning.pa_sc_binner_cntl_0 == pipeline->graphics.binning.pa_sc_binner_cntl_0 &&
893 old_pipeline->graphics.binning.db_dfsm_control == pipeline->graphics.binning.db_dfsm_control)
894 return;
895
896 bool binning_flush = false;
897 if (cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA12 ||
898 cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA20 ||
899 cmd_buffer->device->physical_device->rad_info.family == CHIP_RAVEN2 ||
900 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
901 binning_flush = !old_pipeline ||
902 G_028C44_BINNING_MODE(old_pipeline->graphics.binning.pa_sc_binner_cntl_0) !=
903 G_028C44_BINNING_MODE(pipeline->graphics.binning.pa_sc_binner_cntl_0);
904 }
905
906 radeon_set_context_reg(cmd_buffer->cs, R_028C44_PA_SC_BINNER_CNTL_0,
907 pipeline->graphics.binning.pa_sc_binner_cntl_0 |
908 S_028C44_FLUSH_ON_BINNING_TRANSITION(!!binning_flush));
909
910 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
911 radeon_set_context_reg(cmd_buffer->cs, R_028038_DB_DFSM_CONTROL,
912 pipeline->graphics.binning.db_dfsm_control);
913 } else {
914 radeon_set_context_reg(cmd_buffer->cs, R_028060_DB_DFSM_CONTROL,
915 pipeline->graphics.binning.db_dfsm_control);
916 }
917
918 cmd_buffer->state.context_roll_without_scissor_emitted = true;
919 }
920
921
922 static void
923 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
924 struct radv_shader_variant *shader)
925 {
926 uint64_t va;
927
928 if (!shader)
929 return;
930
931 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
932
933 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
934 }
935
936 static void
937 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
938 struct radv_pipeline *pipeline,
939 bool vertex_stage_only)
940 {
941 struct radv_cmd_state *state = &cmd_buffer->state;
942 uint32_t mask = state->prefetch_L2_mask;
943
944 if (vertex_stage_only) {
945 /* Fast prefetch path for starting draws as soon as possible.
946 */
947 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
948 RADV_PREFETCH_VBO_DESCRIPTORS);
949 }
950
951 if (mask & RADV_PREFETCH_VS)
952 radv_emit_shader_prefetch(cmd_buffer,
953 pipeline->shaders[MESA_SHADER_VERTEX]);
954
955 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
956 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
957
958 if (mask & RADV_PREFETCH_TCS)
959 radv_emit_shader_prefetch(cmd_buffer,
960 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
961
962 if (mask & RADV_PREFETCH_TES)
963 radv_emit_shader_prefetch(cmd_buffer,
964 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
965
966 if (mask & RADV_PREFETCH_GS) {
967 radv_emit_shader_prefetch(cmd_buffer,
968 pipeline->shaders[MESA_SHADER_GEOMETRY]);
969 if (radv_pipeline_has_gs_copy_shader(pipeline))
970 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
971 }
972
973 if (mask & RADV_PREFETCH_PS)
974 radv_emit_shader_prefetch(cmd_buffer,
975 pipeline->shaders[MESA_SHADER_FRAGMENT]);
976
977 state->prefetch_L2_mask &= ~mask;
978 }
979
980 static void
981 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
982 {
983 if (!cmd_buffer->device->physical_device->rad_info.rbplus_allowed)
984 return;
985
986 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
987 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
988
989 unsigned sx_ps_downconvert = 0;
990 unsigned sx_blend_opt_epsilon = 0;
991 unsigned sx_blend_opt_control = 0;
992
993 if (!cmd_buffer->state.attachments || !subpass)
994 return;
995
996 for (unsigned i = 0; i < subpass->color_count; ++i) {
997 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
998 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
999 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1000 continue;
1001 }
1002
1003 int idx = subpass->color_attachments[i].attachment;
1004 struct radv_color_buffer_info *cb = &cmd_buffer->state.attachments[idx].cb;
1005
1006 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
1007 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
1008 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
1009 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
1010
1011 bool has_alpha, has_rgb;
1012
1013 /* Set if RGB and A are present. */
1014 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
1015
1016 if (format == V_028C70_COLOR_8 ||
1017 format == V_028C70_COLOR_16 ||
1018 format == V_028C70_COLOR_32)
1019 has_rgb = !has_alpha;
1020 else
1021 has_rgb = true;
1022
1023 /* Check the colormask and export format. */
1024 if (!(colormask & 0x7))
1025 has_rgb = false;
1026 if (!(colormask & 0x8))
1027 has_alpha = false;
1028
1029 if (spi_format == V_028714_SPI_SHADER_ZERO) {
1030 has_rgb = false;
1031 has_alpha = false;
1032 }
1033
1034 /* Disable value checking for disabled channels. */
1035 if (!has_rgb)
1036 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1037 if (!has_alpha)
1038 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1039
1040 /* Enable down-conversion for 32bpp and smaller formats. */
1041 switch (format) {
1042 case V_028C70_COLOR_8:
1043 case V_028C70_COLOR_8_8:
1044 case V_028C70_COLOR_8_8_8_8:
1045 /* For 1 and 2-channel formats, use the superset thereof. */
1046 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
1047 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1048 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1049 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
1050 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
1051 }
1052 break;
1053
1054 case V_028C70_COLOR_5_6_5:
1055 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1056 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
1057 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
1058 }
1059 break;
1060
1061 case V_028C70_COLOR_1_5_5_5:
1062 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1063 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
1064 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
1065 }
1066 break;
1067
1068 case V_028C70_COLOR_4_4_4_4:
1069 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1070 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
1071 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
1072 }
1073 break;
1074
1075 case V_028C70_COLOR_32:
1076 if (swap == V_028C70_SWAP_STD &&
1077 spi_format == V_028714_SPI_SHADER_32_R)
1078 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1079 else if (swap == V_028C70_SWAP_ALT_REV &&
1080 spi_format == V_028714_SPI_SHADER_32_AR)
1081 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
1082 break;
1083
1084 case V_028C70_COLOR_16:
1085 case V_028C70_COLOR_16_16:
1086 /* For 1-channel formats, use the superset thereof. */
1087 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
1088 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
1089 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1090 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1091 if (swap == V_028C70_SWAP_STD ||
1092 swap == V_028C70_SWAP_STD_REV)
1093 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
1094 else
1095 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
1096 }
1097 break;
1098
1099 case V_028C70_COLOR_10_11_11:
1100 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1101 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
1102 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
1103 }
1104 break;
1105
1106 case V_028C70_COLOR_2_10_10_10:
1107 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1108 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
1109 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
1110 }
1111 break;
1112 }
1113 }
1114
1115 for (unsigned i = subpass->color_count; i < 8; ++i) {
1116 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1117 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1118 }
1119 /* TODO: avoid redundantly setting context registers */
1120 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
1121 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
1122 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
1123 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
1124
1125 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1126 }
1127
1128 static void
1129 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1130 {
1131 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1132
1133 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1134 return;
1135
1136 radv_update_multisample_state(cmd_buffer, pipeline);
1137 radv_update_binning_state(cmd_buffer, pipeline);
1138
1139 cmd_buffer->scratch_size_per_wave_needed = MAX2(cmd_buffer->scratch_size_per_wave_needed,
1140 pipeline->scratch_bytes_per_wave);
1141 cmd_buffer->scratch_waves_wanted = MAX2(cmd_buffer->scratch_waves_wanted,
1142 pipeline->max_waves);
1143
1144 if (!cmd_buffer->state.emitted_pipeline ||
1145 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1146 pipeline->graphics.can_use_guardband)
1147 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1148
1149 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
1150
1151 if (!cmd_buffer->state.emitted_pipeline ||
1152 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
1153 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
1154 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
1155 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
1156 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
1157 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1158 }
1159
1160 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
1161 if (!pipeline->shaders[i])
1162 continue;
1163
1164 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1165 pipeline->shaders[i]->bo);
1166 }
1167
1168 if (radv_pipeline_has_gs_copy_shader(pipeline))
1169 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1170 pipeline->gs_copy_shader->bo);
1171
1172 if (unlikely(cmd_buffer->device->trace_bo))
1173 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1174
1175 cmd_buffer->state.emitted_pipeline = pipeline;
1176
1177 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1178 }
1179
1180 static void
1181 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1182 {
1183 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1184 cmd_buffer->state.dynamic.viewport.viewports);
1185 }
1186
1187 static void
1188 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1189 {
1190 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1191
1192 si_write_scissors(cmd_buffer->cs, 0, count,
1193 cmd_buffer->state.dynamic.scissor.scissors,
1194 cmd_buffer->state.dynamic.viewport.viewports,
1195 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1196
1197 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1198 }
1199
1200 static void
1201 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1202 {
1203 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1204 return;
1205
1206 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1207 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1208 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1209 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1210 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1211 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1212 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1213 }
1214 }
1215
1216 static void
1217 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1218 {
1219 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1220
1221 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1222 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1223 }
1224
1225 static void
1226 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1227 {
1228 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1229
1230 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1231 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1232 }
1233
1234 static void
1235 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1236 {
1237 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1238
1239 radeon_set_context_reg_seq(cmd_buffer->cs,
1240 R_028430_DB_STENCILREFMASK, 2);
1241 radeon_emit(cmd_buffer->cs,
1242 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1243 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1244 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1245 S_028430_STENCILOPVAL(1));
1246 radeon_emit(cmd_buffer->cs,
1247 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1248 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1249 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1250 S_028434_STENCILOPVAL_BF(1));
1251 }
1252
1253 static void
1254 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1255 {
1256 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1257
1258 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1259 fui(d->depth_bounds.min));
1260 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1261 fui(d->depth_bounds.max));
1262 }
1263
1264 static void
1265 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1266 {
1267 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1268 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1269 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1270
1271
1272 radeon_set_context_reg_seq(cmd_buffer->cs,
1273 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1274 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1275 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1276 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1277 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1278 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1279 }
1280
1281 static void
1282 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1283 int index,
1284 struct radv_color_buffer_info *cb,
1285 struct radv_image_view *iview,
1286 VkImageLayout layout,
1287 bool in_render_loop)
1288 {
1289 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
1290 uint32_t cb_color_info = cb->cb_color_info;
1291 struct radv_image *image = iview->image;
1292
1293 if (!radv_layout_dcc_compressed(cmd_buffer->device, image, layout, in_render_loop,
1294 radv_image_queue_family_mask(image,
1295 cmd_buffer->queue_family_index,
1296 cmd_buffer->queue_family_index))) {
1297 cb_color_info &= C_028C70_DCC_ENABLE;
1298 }
1299
1300 if (radv_image_is_tc_compat_cmask(image) &&
1301 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1302 radv_is_dcc_decompress_pipeline(cmd_buffer))) {
1303 /* If this bit is set, the FMASK decompression operation
1304 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1305 */
1306 cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
1307 }
1308
1309 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1310 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1311 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1312 radeon_emit(cmd_buffer->cs, 0);
1313 radeon_emit(cmd_buffer->cs, 0);
1314 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1315 radeon_emit(cmd_buffer->cs, cb_color_info);
1316 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1317 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1318 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1319 radeon_emit(cmd_buffer->cs, 0);
1320 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1321 radeon_emit(cmd_buffer->cs, 0);
1322
1323 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 1);
1324 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1325
1326 radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4,
1327 cb->cb_color_base >> 32);
1328 radeon_set_context_reg(cmd_buffer->cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + index * 4,
1329 cb->cb_color_cmask >> 32);
1330 radeon_set_context_reg(cmd_buffer->cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + index * 4,
1331 cb->cb_color_fmask >> 32);
1332 radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4,
1333 cb->cb_dcc_base >> 32);
1334 radeon_set_context_reg(cmd_buffer->cs, R_028EC0_CB_COLOR0_ATTRIB2 + index * 4,
1335 cb->cb_color_attrib2);
1336 radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4,
1337 cb->cb_color_attrib3);
1338 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1339 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1340 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1341 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1342 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1343 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1344 radeon_emit(cmd_buffer->cs, cb_color_info);
1345 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1346 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1347 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1348 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1349 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1350 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1351
1352 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1353 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1354 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1355
1356 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1357 cb->cb_mrt_epitch);
1358 } else {
1359 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1360 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1361 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1362 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1363 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1364 radeon_emit(cmd_buffer->cs, cb_color_info);
1365 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1366 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1367 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1368 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1369 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1370 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1371
1372 if (is_vi) { /* DCC BASE */
1373 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1374 }
1375 }
1376
1377 if (radv_dcc_enabled(image, iview->base_mip)) {
1378 /* Drawing with DCC enabled also compresses colorbuffers. */
1379 VkImageSubresourceRange range = {
1380 .aspectMask = iview->aspect_mask,
1381 .baseMipLevel = iview->base_mip,
1382 .levelCount = iview->level_count,
1383 .baseArrayLayer = iview->base_layer,
1384 .layerCount = iview->layer_count,
1385 };
1386
1387 radv_update_dcc_metadata(cmd_buffer, image, &range, true);
1388 }
1389 }
1390
1391 static void
1392 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1393 struct radv_ds_buffer_info *ds,
1394 const struct radv_image_view *iview,
1395 VkImageLayout layout,
1396 bool in_render_loop, bool requires_cond_exec)
1397 {
1398 const struct radv_image *image = iview->image;
1399 uint32_t db_z_info = ds->db_z_info;
1400 uint32_t db_z_info_reg;
1401
1402 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug ||
1403 !radv_image_is_tc_compat_htile(image))
1404 return;
1405
1406 if (!radv_layout_has_htile(image, layout, in_render_loop,
1407 radv_image_queue_family_mask(image,
1408 cmd_buffer->queue_family_index,
1409 cmd_buffer->queue_family_index))) {
1410 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1411 }
1412
1413 db_z_info &= C_028040_ZRANGE_PRECISION;
1414
1415 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1416 db_z_info_reg = R_028038_DB_Z_INFO;
1417 } else {
1418 db_z_info_reg = R_028040_DB_Z_INFO;
1419 }
1420
1421 /* When we don't know the last fast clear value we need to emit a
1422 * conditional packet that will eventually skip the following
1423 * SET_CONTEXT_REG packet.
1424 */
1425 if (requires_cond_exec) {
1426 uint64_t va = radv_get_tc_compat_zrange_va(image, iview->base_mip);
1427
1428 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1429 radeon_emit(cmd_buffer->cs, va);
1430 radeon_emit(cmd_buffer->cs, va >> 32);
1431 radeon_emit(cmd_buffer->cs, 0);
1432 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1433 }
1434
1435 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1436 }
1437
1438 static void
1439 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1440 struct radv_ds_buffer_info *ds,
1441 struct radv_image_view *iview,
1442 VkImageLayout layout,
1443 bool in_render_loop)
1444 {
1445 const struct radv_image *image = iview->image;
1446 uint32_t db_z_info = ds->db_z_info;
1447 uint32_t db_stencil_info = ds->db_stencil_info;
1448
1449 if (!radv_layout_has_htile(image, layout, in_render_loop,
1450 radv_image_queue_family_mask(image,
1451 cmd_buffer->queue_family_index,
1452 cmd_buffer->queue_family_index))) {
1453 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1454 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1455 }
1456
1457 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1458 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1459
1460 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1461 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1462 radeon_set_context_reg(cmd_buffer->cs, R_02801C_DB_DEPTH_SIZE_XY, ds->db_depth_size);
1463
1464 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 7);
1465 radeon_emit(cmd_buffer->cs, S_02803C_RESOURCE_LEVEL(1));
1466 radeon_emit(cmd_buffer->cs, db_z_info);
1467 radeon_emit(cmd_buffer->cs, db_stencil_info);
1468 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1469 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1470 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1471 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1472
1473 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_READ_BASE_HI, 5);
1474 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1475 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1476 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1477 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1478 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1479 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1480 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1481 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1482 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1483 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1484
1485 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1486 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1487 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1488 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1489 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1490 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1491 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1492 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1493 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1494 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1495 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1496
1497 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1498 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1499 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1500 } else {
1501 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1502
1503 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1504 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1505 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1506 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1507 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1508 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1509 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1510 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1511 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1512 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1513
1514 }
1515
1516 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1517 radv_update_zrange_precision(cmd_buffer, ds, iview, layout,
1518 in_render_loop, true);
1519
1520 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1521 ds->pa_su_poly_offset_db_fmt_cntl);
1522 }
1523
1524 /**
1525 * Update the fast clear depth/stencil values if the image is bound as a
1526 * depth/stencil buffer.
1527 */
1528 static void
1529 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1530 const struct radv_image_view *iview,
1531 VkClearDepthStencilValue ds_clear_value,
1532 VkImageAspectFlags aspects)
1533 {
1534 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1535 const struct radv_image *image = iview->image;
1536 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1537 uint32_t att_idx;
1538
1539 if (!cmd_buffer->state.attachments || !subpass)
1540 return;
1541
1542 if (!subpass->depth_stencil_attachment)
1543 return;
1544
1545 att_idx = subpass->depth_stencil_attachment->attachment;
1546 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1547 return;
1548
1549 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1550 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1551 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1552 radeon_emit(cs, ds_clear_value.stencil);
1553 radeon_emit(cs, fui(ds_clear_value.depth));
1554 } else if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1555 radeon_set_context_reg_seq(cs, R_02802C_DB_DEPTH_CLEAR, 1);
1556 radeon_emit(cs, fui(ds_clear_value.depth));
1557 } else {
1558 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1559 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 1);
1560 radeon_emit(cs, ds_clear_value.stencil);
1561 }
1562
1563 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1564 * only needed when clearing Z to 0.0.
1565 */
1566 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1567 ds_clear_value.depth == 0.0) {
1568 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1569 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
1570
1571 radv_update_zrange_precision(cmd_buffer, &cmd_buffer->state.attachments[att_idx].ds,
1572 iview, layout, in_render_loop, false);
1573 }
1574
1575 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1576 }
1577
1578 /**
1579 * Set the clear depth/stencil values to the image's metadata.
1580 */
1581 static void
1582 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1583 struct radv_image *image,
1584 const VkImageSubresourceRange *range,
1585 VkClearDepthStencilValue ds_clear_value,
1586 VkImageAspectFlags aspects)
1587 {
1588 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1589 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel);
1590 uint32_t level_count = radv_get_levelCount(image, range);
1591
1592 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1593 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1594 /* Use the fastest way when both aspects are used. */
1595 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + 2 * level_count, cmd_buffer->state.predicating));
1596 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1597 S_370_WR_CONFIRM(1) |
1598 S_370_ENGINE_SEL(V_370_PFP));
1599 radeon_emit(cs, va);
1600 radeon_emit(cs, va >> 32);
1601
1602 for (uint32_t l = 0; l < level_count; l++) {
1603 radeon_emit(cs, ds_clear_value.stencil);
1604 radeon_emit(cs, fui(ds_clear_value.depth));
1605 }
1606 } else {
1607 /* Otherwise we need one WRITE_DATA packet per level. */
1608 for (uint32_t l = 0; l < level_count; l++) {
1609 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel + l);
1610 unsigned value;
1611
1612 if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1613 value = fui(ds_clear_value.depth);
1614 va += 4;
1615 } else {
1616 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1617 value = ds_clear_value.stencil;
1618 }
1619
1620 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1621 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1622 S_370_WR_CONFIRM(1) |
1623 S_370_ENGINE_SEL(V_370_PFP));
1624 radeon_emit(cs, va);
1625 radeon_emit(cs, va >> 32);
1626 radeon_emit(cs, value);
1627 }
1628 }
1629 }
1630
1631 /**
1632 * Update the TC-compat metadata value for this image.
1633 */
1634 static void
1635 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1636 struct radv_image *image,
1637 const VkImageSubresourceRange *range,
1638 uint32_t value)
1639 {
1640 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1641
1642 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug)
1643 return;
1644
1645 uint64_t va = radv_get_tc_compat_zrange_va(image, range->baseMipLevel);
1646 uint32_t level_count = radv_get_levelCount(image, range);
1647
1648 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + level_count, cmd_buffer->state.predicating));
1649 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1650 S_370_WR_CONFIRM(1) |
1651 S_370_ENGINE_SEL(V_370_PFP));
1652 radeon_emit(cs, va);
1653 radeon_emit(cs, va >> 32);
1654
1655 for (uint32_t l = 0; l < level_count; l++)
1656 radeon_emit(cs, value);
1657 }
1658
1659 static void
1660 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1661 const struct radv_image_view *iview,
1662 VkClearDepthStencilValue ds_clear_value)
1663 {
1664 VkImageSubresourceRange range = {
1665 .aspectMask = iview->aspect_mask,
1666 .baseMipLevel = iview->base_mip,
1667 .levelCount = iview->level_count,
1668 .baseArrayLayer = iview->base_layer,
1669 .layerCount = iview->layer_count,
1670 };
1671 uint32_t cond_val;
1672
1673 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1674 * depth clear value is 0.0f.
1675 */
1676 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1677
1678 radv_set_tc_compat_zrange_metadata(cmd_buffer, iview->image, &range,
1679 cond_val);
1680 }
1681
1682 /**
1683 * Update the clear depth/stencil values for this image.
1684 */
1685 void
1686 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1687 const struct radv_image_view *iview,
1688 VkClearDepthStencilValue ds_clear_value,
1689 VkImageAspectFlags aspects)
1690 {
1691 VkImageSubresourceRange range = {
1692 .aspectMask = iview->aspect_mask,
1693 .baseMipLevel = iview->base_mip,
1694 .levelCount = iview->level_count,
1695 .baseArrayLayer = iview->base_layer,
1696 .layerCount = iview->layer_count,
1697 };
1698 struct radv_image *image = iview->image;
1699
1700 assert(radv_image_has_htile(image));
1701
1702 radv_set_ds_clear_metadata(cmd_buffer, iview->image, &range,
1703 ds_clear_value, aspects);
1704
1705 if (radv_image_is_tc_compat_htile(image) &&
1706 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1707 radv_update_tc_compat_zrange_metadata(cmd_buffer, iview,
1708 ds_clear_value);
1709 }
1710
1711 radv_update_bound_fast_clear_ds(cmd_buffer, iview, ds_clear_value,
1712 aspects);
1713 }
1714
1715 /**
1716 * Load the clear depth/stencil values from the image's metadata.
1717 */
1718 static void
1719 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1720 const struct radv_image_view *iview)
1721 {
1722 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1723 const struct radv_image *image = iview->image;
1724 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1725 uint64_t va = radv_get_ds_clear_value_va(image, iview->base_mip);
1726 unsigned reg_offset = 0, reg_count = 0;
1727
1728 if (!radv_image_has_htile(image))
1729 return;
1730
1731 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1732 ++reg_count;
1733 } else {
1734 ++reg_offset;
1735 va += 4;
1736 }
1737 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1738 ++reg_count;
1739
1740 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1741
1742 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
1743 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1744 radeon_emit(cs, va);
1745 radeon_emit(cs, va >> 32);
1746 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1747 radeon_emit(cs, reg_count);
1748 } else {
1749 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1750 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1751 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1752 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1753 radeon_emit(cs, va);
1754 radeon_emit(cs, va >> 32);
1755 radeon_emit(cs, reg >> 2);
1756 radeon_emit(cs, 0);
1757
1758 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1759 radeon_emit(cs, 0);
1760 }
1761 }
1762
1763 /*
1764 * With DCC some colors don't require CMASK elimination before being
1765 * used as a texture. This sets a predicate value to determine if the
1766 * cmask eliminate is required.
1767 */
1768 void
1769 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1770 struct radv_image *image,
1771 const VkImageSubresourceRange *range, bool value)
1772 {
1773 uint64_t pred_val = value;
1774 uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
1775 uint32_t level_count = radv_get_levelCount(image, range);
1776 uint32_t count = 2 * level_count;
1777
1778 assert(radv_dcc_enabled(image, range->baseMipLevel));
1779
1780 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1781 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1782 S_370_WR_CONFIRM(1) |
1783 S_370_ENGINE_SEL(V_370_PFP));
1784 radeon_emit(cmd_buffer->cs, va);
1785 radeon_emit(cmd_buffer->cs, va >> 32);
1786
1787 for (uint32_t l = 0; l < level_count; l++) {
1788 radeon_emit(cmd_buffer->cs, pred_val);
1789 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1790 }
1791 }
1792
1793 /**
1794 * Update the DCC predicate to reflect the compression state.
1795 */
1796 void
1797 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1798 struct radv_image *image,
1799 const VkImageSubresourceRange *range, bool value)
1800 {
1801 uint64_t pred_val = value;
1802 uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
1803 uint32_t level_count = radv_get_levelCount(image, range);
1804 uint32_t count = 2 * level_count;
1805
1806 assert(radv_dcc_enabled(image, range->baseMipLevel));
1807
1808 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1809 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1810 S_370_WR_CONFIRM(1) |
1811 S_370_ENGINE_SEL(V_370_PFP));
1812 radeon_emit(cmd_buffer->cs, va);
1813 radeon_emit(cmd_buffer->cs, va >> 32);
1814
1815 for (uint32_t l = 0; l < level_count; l++) {
1816 radeon_emit(cmd_buffer->cs, pred_val);
1817 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1818 }
1819 }
1820
1821 /**
1822 * Update the fast clear color values if the image is bound as a color buffer.
1823 */
1824 static void
1825 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1826 struct radv_image *image,
1827 int cb_idx,
1828 uint32_t color_values[2])
1829 {
1830 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1831 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1832 uint32_t att_idx;
1833
1834 if (!cmd_buffer->state.attachments || !subpass)
1835 return;
1836
1837 att_idx = subpass->color_attachments[cb_idx].attachment;
1838 if (att_idx == VK_ATTACHMENT_UNUSED)
1839 return;
1840
1841 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1842 return;
1843
1844 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1845 radeon_emit(cs, color_values[0]);
1846 radeon_emit(cs, color_values[1]);
1847
1848 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1849 }
1850
1851 /**
1852 * Set the clear color values to the image's metadata.
1853 */
1854 static void
1855 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1856 struct radv_image *image,
1857 const VkImageSubresourceRange *range,
1858 uint32_t color_values[2])
1859 {
1860 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1861 uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
1862 uint32_t level_count = radv_get_levelCount(image, range);
1863 uint32_t count = 2 * level_count;
1864
1865 assert(radv_image_has_cmask(image) ||
1866 radv_dcc_enabled(image, range->baseMipLevel));
1867
1868 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
1869 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1870 S_370_WR_CONFIRM(1) |
1871 S_370_ENGINE_SEL(V_370_PFP));
1872 radeon_emit(cs, va);
1873 radeon_emit(cs, va >> 32);
1874
1875 for (uint32_t l = 0; l < level_count; l++) {
1876 radeon_emit(cs, color_values[0]);
1877 radeon_emit(cs, color_values[1]);
1878 }
1879 }
1880
1881 /**
1882 * Update the clear color values for this image.
1883 */
1884 void
1885 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1886 const struct radv_image_view *iview,
1887 int cb_idx,
1888 uint32_t color_values[2])
1889 {
1890 struct radv_image *image = iview->image;
1891 VkImageSubresourceRange range = {
1892 .aspectMask = iview->aspect_mask,
1893 .baseMipLevel = iview->base_mip,
1894 .levelCount = iview->level_count,
1895 .baseArrayLayer = iview->base_layer,
1896 .layerCount = iview->layer_count,
1897 };
1898
1899 assert(radv_image_has_cmask(image) ||
1900 radv_dcc_enabled(image, iview->base_mip));
1901
1902 radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
1903
1904 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1905 color_values);
1906 }
1907
1908 /**
1909 * Load the clear color values from the image's metadata.
1910 */
1911 static void
1912 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1913 struct radv_image_view *iview,
1914 int cb_idx)
1915 {
1916 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1917 struct radv_image *image = iview->image;
1918 uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
1919
1920 if (!radv_image_has_cmask(image) &&
1921 !radv_dcc_enabled(image, iview->base_mip))
1922 return;
1923
1924 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1925
1926 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
1927 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1928 radeon_emit(cs, va);
1929 radeon_emit(cs, va >> 32);
1930 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1931 radeon_emit(cs, 2);
1932 } else {
1933 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1934 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1935 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1936 COPY_DATA_COUNT_SEL);
1937 radeon_emit(cs, va);
1938 radeon_emit(cs, va >> 32);
1939 radeon_emit(cs, reg >> 2);
1940 radeon_emit(cs, 0);
1941
1942 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1943 radeon_emit(cs, 0);
1944 }
1945 }
1946
1947 static void
1948 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1949 {
1950 int i;
1951 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1952 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1953
1954 /* this may happen for inherited secondary recording */
1955 if (!framebuffer)
1956 return;
1957
1958 for (i = 0; i < 8; ++i) {
1959 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1960 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1961 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1962 continue;
1963 }
1964
1965 int idx = subpass->color_attachments[i].attachment;
1966 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
1967 VkImageLayout layout = subpass->color_attachments[i].layout;
1968 bool in_render_loop = subpass->color_attachments[i].in_render_loop;
1969
1970 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, iview->bo);
1971
1972 assert(iview->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
1973 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
1974 radv_emit_fb_color_state(cmd_buffer, i, &cmd_buffer->state.attachments[idx].cb, iview, layout, in_render_loop);
1975
1976 radv_load_color_clear_metadata(cmd_buffer, iview, i);
1977 }
1978
1979 if (subpass->depth_stencil_attachment) {
1980 int idx = subpass->depth_stencil_attachment->attachment;
1981 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1982 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
1983 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
1984 struct radv_image *image = iview->image;
1985 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, cmd_buffer->state.attachments[idx].iview->bo);
1986 ASSERTED uint32_t queue_mask = radv_image_queue_family_mask(image,
1987 cmd_buffer->queue_family_index,
1988 cmd_buffer->queue_family_index);
1989 /* We currently don't support writing decompressed HTILE */
1990 assert(radv_layout_has_htile(image, layout, in_render_loop, queue_mask) ==
1991 radv_layout_is_htile_compressed(image, layout, in_render_loop, queue_mask));
1992
1993 radv_emit_fb_ds_state(cmd_buffer, &cmd_buffer->state.attachments[idx].ds, iview, layout, in_render_loop);
1994
1995 if (cmd_buffer->state.attachments[idx].ds.offset_scale != cmd_buffer->state.offset_scale) {
1996 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1997 cmd_buffer->state.offset_scale = cmd_buffer->state.attachments[idx].ds.offset_scale;
1998 }
1999 radv_load_ds_clear_metadata(cmd_buffer, iview);
2000 } else {
2001 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9)
2002 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
2003 else
2004 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
2005
2006 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
2007 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
2008 }
2009 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2010 S_028208_BR_X(framebuffer->width) |
2011 S_028208_BR_Y(framebuffer->height));
2012
2013 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
2014 bool disable_constant_encode =
2015 cmd_buffer->device->physical_device->rad_info.has_dcc_constant_encode;
2016 enum chip_class chip_class =
2017 cmd_buffer->device->physical_device->rad_info.chip_class;
2018 uint8_t watermark = chip_class >= GFX10 ? 6 : 4;
2019
2020 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
2021 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class <= GFX9) |
2022 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
2023 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
2024 }
2025
2026 if (cmd_buffer->device->dfsm_allowed) {
2027 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2028 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
2029 }
2030
2031 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
2032 }
2033
2034 static void
2035 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
2036 {
2037 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2038 struct radv_cmd_state *state = &cmd_buffer->state;
2039
2040 if (state->index_type != state->last_index_type) {
2041 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2042 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2043 cs, R_03090C_VGT_INDEX_TYPE,
2044 2, state->index_type);
2045 } else {
2046 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2047 radeon_emit(cs, state->index_type);
2048 }
2049
2050 state->last_index_type = state->index_type;
2051 }
2052
2053 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2054 radeon_emit(cs, state->index_va);
2055 radeon_emit(cs, state->index_va >> 32);
2056
2057 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2058 radeon_emit(cs, state->max_index_count);
2059
2060 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
2061 }
2062
2063 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
2064 {
2065 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
2066 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2067 uint32_t pa_sc_mode_cntl_1 =
2068 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
2069 uint32_t db_count_control;
2070
2071 if(!cmd_buffer->state.active_occlusion_queries) {
2072 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2073 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2074 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2075 has_perfect_queries) {
2076 /* Re-enable out-of-order rasterization if the
2077 * bound pipeline supports it and if it's has
2078 * been disabled before starting any perfect
2079 * occlusion queries.
2080 */
2081 radeon_set_context_reg(cmd_buffer->cs,
2082 R_028A4C_PA_SC_MODE_CNTL_1,
2083 pa_sc_mode_cntl_1);
2084 }
2085 }
2086 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
2087 } else {
2088 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2089 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
2090 bool gfx10_perfect = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10 && has_perfect_queries;
2091
2092 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2093 db_count_control =
2094 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
2095 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
2096 S_028004_SAMPLE_RATE(sample_rate) |
2097 S_028004_ZPASS_ENABLE(1) |
2098 S_028004_SLICE_EVEN_ENABLE(1) |
2099 S_028004_SLICE_ODD_ENABLE(1);
2100
2101 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2102 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2103 has_perfect_queries) {
2104 /* If the bound pipeline has enabled
2105 * out-of-order rasterization, we should
2106 * disable it before starting any perfect
2107 * occlusion queries.
2108 */
2109 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
2110
2111 radeon_set_context_reg(cmd_buffer->cs,
2112 R_028A4C_PA_SC_MODE_CNTL_1,
2113 pa_sc_mode_cntl_1);
2114 }
2115 } else {
2116 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
2117 S_028004_SAMPLE_RATE(sample_rate);
2118 }
2119 }
2120
2121 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
2122
2123 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2124 }
2125
2126 static void
2127 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
2128 {
2129 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
2130
2131 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
2132 radv_emit_viewport(cmd_buffer);
2133
2134 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
2135 !cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
2136 radv_emit_scissor(cmd_buffer);
2137
2138 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
2139 radv_emit_line_width(cmd_buffer);
2140
2141 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
2142 radv_emit_blend_constants(cmd_buffer);
2143
2144 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
2145 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
2146 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
2147 radv_emit_stencil(cmd_buffer);
2148
2149 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
2150 radv_emit_depth_bounds(cmd_buffer);
2151
2152 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
2153 radv_emit_depth_bias(cmd_buffer);
2154
2155 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
2156 radv_emit_discard_rectangle(cmd_buffer);
2157
2158 if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)
2159 radv_emit_sample_locations(cmd_buffer);
2160
2161 cmd_buffer->state.dirty &= ~states;
2162 }
2163
2164 static void
2165 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
2166 VkPipelineBindPoint bind_point)
2167 {
2168 struct radv_descriptor_state *descriptors_state =
2169 radv_get_descriptors_state(cmd_buffer, bind_point);
2170 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
2171 unsigned bo_offset;
2172
2173 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
2174 set->mapped_ptr,
2175 &bo_offset))
2176 return;
2177
2178 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2179 set->va += bo_offset;
2180 }
2181
2182 static void
2183 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
2184 VkPipelineBindPoint bind_point)
2185 {
2186 struct radv_descriptor_state *descriptors_state =
2187 radv_get_descriptors_state(cmd_buffer, bind_point);
2188 uint32_t size = MAX_SETS * 4;
2189 uint32_t offset;
2190 void *ptr;
2191
2192 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
2193 256, &offset, &ptr))
2194 return;
2195
2196 for (unsigned i = 0; i < MAX_SETS; i++) {
2197 uint32_t *uptr = ((uint32_t *)ptr) + i;
2198 uint64_t set_va = 0;
2199 struct radv_descriptor_set *set = descriptors_state->sets[i];
2200 if (descriptors_state->valid & (1u << i))
2201 set_va = set->va;
2202 uptr[0] = set_va & 0xffffffff;
2203 }
2204
2205 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2206 va += offset;
2207
2208 if (cmd_buffer->state.pipeline) {
2209 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
2210 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2211 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2212
2213 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
2214 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
2215 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2216
2217 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
2218 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2219 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2220
2221 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2222 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
2223 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2224
2225 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2226 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
2227 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2228 }
2229
2230 if (cmd_buffer->state.compute_pipeline)
2231 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
2232 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2233 }
2234
2235 static void
2236 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
2237 VkShaderStageFlags stages)
2238 {
2239 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2240 VK_PIPELINE_BIND_POINT_COMPUTE :
2241 VK_PIPELINE_BIND_POINT_GRAPHICS;
2242 struct radv_descriptor_state *descriptors_state =
2243 radv_get_descriptors_state(cmd_buffer, bind_point);
2244 struct radv_cmd_state *state = &cmd_buffer->state;
2245 bool flush_indirect_descriptors;
2246
2247 if (!descriptors_state->dirty)
2248 return;
2249
2250 if (descriptors_state->push_dirty)
2251 radv_flush_push_descriptors(cmd_buffer, bind_point);
2252
2253 flush_indirect_descriptors =
2254 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
2255 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
2256 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
2257 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
2258
2259 if (flush_indirect_descriptors)
2260 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
2261
2262 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2263 cmd_buffer->cs,
2264 MAX_SETS * MESA_SHADER_STAGES * 4);
2265
2266 if (cmd_buffer->state.pipeline) {
2267 radv_foreach_stage(stage, stages) {
2268 if (!cmd_buffer->state.pipeline->shaders[stage])
2269 continue;
2270
2271 radv_emit_descriptor_pointers(cmd_buffer,
2272 cmd_buffer->state.pipeline,
2273 descriptors_state, stage);
2274 }
2275 }
2276
2277 if (cmd_buffer->state.compute_pipeline &&
2278 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
2279 radv_emit_descriptor_pointers(cmd_buffer,
2280 cmd_buffer->state.compute_pipeline,
2281 descriptors_state,
2282 MESA_SHADER_COMPUTE);
2283 }
2284
2285 descriptors_state->dirty = 0;
2286 descriptors_state->push_dirty = false;
2287
2288 assert(cmd_buffer->cs->cdw <= cdw_max);
2289
2290 if (unlikely(cmd_buffer->device->trace_bo))
2291 radv_save_descriptors(cmd_buffer, bind_point);
2292 }
2293
2294 static void
2295 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
2296 VkShaderStageFlags stages)
2297 {
2298 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
2299 ? cmd_buffer->state.compute_pipeline
2300 : cmd_buffer->state.pipeline;
2301 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2302 VK_PIPELINE_BIND_POINT_COMPUTE :
2303 VK_PIPELINE_BIND_POINT_GRAPHICS;
2304 struct radv_descriptor_state *descriptors_state =
2305 radv_get_descriptors_state(cmd_buffer, bind_point);
2306 struct radv_pipeline_layout *layout = pipeline->layout;
2307 struct radv_shader_variant *shader, *prev_shader;
2308 bool need_push_constants = false;
2309 unsigned offset;
2310 void *ptr;
2311 uint64_t va;
2312
2313 stages &= cmd_buffer->push_constant_stages;
2314 if (!stages ||
2315 (!layout->push_constant_size && !layout->dynamic_offset_count))
2316 return;
2317
2318 radv_foreach_stage(stage, stages) {
2319 shader = radv_get_shader(pipeline, stage);
2320 if (!shader)
2321 continue;
2322
2323 need_push_constants |= shader->info.loads_push_constants;
2324 need_push_constants |= shader->info.loads_dynamic_offsets;
2325
2326 uint8_t base = shader->info.base_inline_push_consts;
2327 uint8_t count = shader->info.num_inline_push_consts;
2328
2329 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
2330 AC_UD_INLINE_PUSH_CONSTANTS,
2331 count,
2332 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
2333 }
2334
2335 if (need_push_constants) {
2336 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
2337 16 * layout->dynamic_offset_count,
2338 256, &offset, &ptr))
2339 return;
2340
2341 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
2342 memcpy((char*)ptr + layout->push_constant_size,
2343 descriptors_state->dynamic_buffers,
2344 16 * layout->dynamic_offset_count);
2345
2346 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2347 va += offset;
2348
2349 ASSERTED unsigned cdw_max =
2350 radeon_check_space(cmd_buffer->device->ws,
2351 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
2352
2353 prev_shader = NULL;
2354 radv_foreach_stage(stage, stages) {
2355 shader = radv_get_shader(pipeline, stage);
2356
2357 /* Avoid redundantly emitting the address for merged stages. */
2358 if (shader && shader != prev_shader) {
2359 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
2360 AC_UD_PUSH_CONSTANTS, va);
2361
2362 prev_shader = shader;
2363 }
2364 }
2365 assert(cmd_buffer->cs->cdw <= cdw_max);
2366 }
2367
2368 cmd_buffer->push_constant_stages &= ~stages;
2369 }
2370
2371 static void
2372 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
2373 bool pipeline_is_dirty)
2374 {
2375 if ((pipeline_is_dirty ||
2376 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
2377 cmd_buffer->state.pipeline->num_vertex_bindings &&
2378 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.has_vertex_buffers) {
2379 unsigned vb_offset;
2380 void *vb_ptr;
2381 uint32_t i = 0;
2382 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
2383 uint64_t va;
2384
2385 /* allocate some descriptor state for vertex buffers */
2386 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2387 &vb_offset, &vb_ptr))
2388 return;
2389
2390 for (i = 0; i < count; i++) {
2391 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2392 uint32_t offset;
2393 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2394 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[i];
2395 unsigned num_records;
2396
2397 if (!buffer)
2398 continue;
2399
2400 va = radv_buffer_get_va(buffer->bo);
2401
2402 offset = cmd_buffer->vertex_bindings[i].offset;
2403 va += offset + buffer->offset;
2404
2405 num_records = buffer->size - offset;
2406 if (cmd_buffer->device->physical_device->rad_info.chip_class != GFX8 && stride)
2407 num_records /= stride;
2408
2409 desc[0] = va;
2410 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2411 desc[2] = num_records;
2412 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2413 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2414 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2415 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2416
2417 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2418 /* OOB_SELECT chooses the out-of-bounds check:
2419 * - 1: index >= NUM_RECORDS (Structured)
2420 * - 3: offset >= NUM_RECORDS (Raw)
2421 */
2422 int oob_select = stride ? V_008F0C_OOB_SELECT_STRUCTURED : V_008F0C_OOB_SELECT_RAW;
2423
2424 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT) |
2425 S_008F0C_OOB_SELECT(oob_select) |
2426 S_008F0C_RESOURCE_LEVEL(1);
2427 } else {
2428 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2429 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2430 }
2431 }
2432
2433 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2434 va += vb_offset;
2435
2436 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2437 AC_UD_VS_VERTEX_BUFFERS, va);
2438
2439 cmd_buffer->state.vb_va = va;
2440 cmd_buffer->state.vb_size = count * 16;
2441 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2442 }
2443 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2444 }
2445
2446 static void
2447 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2448 {
2449 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2450 struct radv_userdata_info *loc;
2451 uint32_t base_reg;
2452
2453 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2454 if (!radv_get_shader(pipeline, stage))
2455 continue;
2456
2457 loc = radv_lookup_user_sgpr(pipeline, stage,
2458 AC_UD_STREAMOUT_BUFFERS);
2459 if (loc->sgpr_idx == -1)
2460 continue;
2461
2462 base_reg = pipeline->user_data_0[stage];
2463
2464 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2465 base_reg + loc->sgpr_idx * 4, va, false);
2466 }
2467
2468 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
2469 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2470 if (loc->sgpr_idx != -1) {
2471 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2472
2473 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2474 base_reg + loc->sgpr_idx * 4, va, false);
2475 }
2476 }
2477 }
2478
2479 static void
2480 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2481 {
2482 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2483 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2484 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2485 unsigned so_offset;
2486 void *so_ptr;
2487 uint64_t va;
2488
2489 /* Allocate some descriptor state for streamout buffers. */
2490 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2491 MAX_SO_BUFFERS * 16, 256,
2492 &so_offset, &so_ptr))
2493 return;
2494
2495 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2496 struct radv_buffer *buffer = sb[i].buffer;
2497 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2498
2499 if (!(so->enabled_mask & (1 << i)))
2500 continue;
2501
2502 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2503
2504 va += sb[i].offset;
2505
2506 /* Set the descriptor.
2507 *
2508 * On GFX8, the format must be non-INVALID, otherwise
2509 * the buffer will be considered not bound and store
2510 * instructions will be no-ops.
2511 */
2512 uint32_t size = 0xffffffff;
2513
2514 /* Compute the correct buffer size for NGG streamout
2515 * because it's used to determine the max emit per
2516 * buffer.
2517 */
2518 if (cmd_buffer->device->physical_device->use_ngg_streamout)
2519 size = buffer->size - sb[i].offset;
2520
2521 desc[0] = va;
2522 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2523 desc[2] = size;
2524 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2525 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2526 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2527 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2528
2529 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2530 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2531 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
2532 S_008F0C_RESOURCE_LEVEL(1);
2533 } else {
2534 desc[3] |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2535 }
2536 }
2537
2538 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2539 va += so_offset;
2540
2541 radv_emit_streamout_buffers(cmd_buffer, va);
2542 }
2543
2544 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2545 }
2546
2547 static void
2548 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2549 {
2550 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2551 radv_flush_streamout_descriptors(cmd_buffer);
2552 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2553 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2554 }
2555
2556 struct radv_draw_info {
2557 /**
2558 * Number of vertices.
2559 */
2560 uint32_t count;
2561
2562 /**
2563 * Index of the first vertex.
2564 */
2565 int32_t vertex_offset;
2566
2567 /**
2568 * First instance id.
2569 */
2570 uint32_t first_instance;
2571
2572 /**
2573 * Number of instances.
2574 */
2575 uint32_t instance_count;
2576
2577 /**
2578 * First index (indexed draws only).
2579 */
2580 uint32_t first_index;
2581
2582 /**
2583 * Whether it's an indexed draw.
2584 */
2585 bool indexed;
2586
2587 /**
2588 * Indirect draw parameters resource.
2589 */
2590 struct radv_buffer *indirect;
2591 uint64_t indirect_offset;
2592 uint32_t stride;
2593
2594 /**
2595 * Draw count parameters resource.
2596 */
2597 struct radv_buffer *count_buffer;
2598 uint64_t count_buffer_offset;
2599
2600 /**
2601 * Stream output parameters resource.
2602 */
2603 struct radv_buffer *strmout_buffer;
2604 uint64_t strmout_buffer_offset;
2605 };
2606
2607 static uint32_t
2608 radv_get_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
2609 {
2610 switch (cmd_buffer->state.index_type) {
2611 case V_028A7C_VGT_INDEX_8:
2612 return 0xffu;
2613 case V_028A7C_VGT_INDEX_16:
2614 return 0xffffu;
2615 case V_028A7C_VGT_INDEX_32:
2616 return 0xffffffffu;
2617 default:
2618 unreachable("invalid index type");
2619 }
2620 }
2621
2622 static void
2623 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
2624 bool instanced_draw, bool indirect_draw,
2625 bool count_from_stream_output,
2626 uint32_t draw_vertex_count)
2627 {
2628 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2629 struct radv_cmd_state *state = &cmd_buffer->state;
2630 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2631 unsigned ia_multi_vgt_param;
2632
2633 ia_multi_vgt_param =
2634 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
2635 indirect_draw,
2636 count_from_stream_output,
2637 draw_vertex_count);
2638
2639 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2640 if (info->chip_class == GFX9) {
2641 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2642 cs,
2643 R_030960_IA_MULTI_VGT_PARAM,
2644 4, ia_multi_vgt_param);
2645 } else if (info->chip_class >= GFX7) {
2646 radeon_set_context_reg_idx(cs,
2647 R_028AA8_IA_MULTI_VGT_PARAM,
2648 1, ia_multi_vgt_param);
2649 } else {
2650 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2651 ia_multi_vgt_param);
2652 }
2653 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2654 }
2655 }
2656
2657 static void
2658 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2659 const struct radv_draw_info *draw_info)
2660 {
2661 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2662 struct radv_cmd_state *state = &cmd_buffer->state;
2663 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2664 int32_t primitive_reset_en;
2665
2666 /* Draw state. */
2667 if (info->chip_class < GFX10) {
2668 si_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2669 draw_info->indirect,
2670 !!draw_info->strmout_buffer,
2671 draw_info->indirect ? 0 : draw_info->count);
2672 }
2673
2674 /* Primitive restart. */
2675 primitive_reset_en =
2676 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2677
2678 if (primitive_reset_en != state->last_primitive_reset_en) {
2679 state->last_primitive_reset_en = primitive_reset_en;
2680 if (info->chip_class >= GFX9) {
2681 radeon_set_uconfig_reg(cs,
2682 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2683 primitive_reset_en);
2684 } else {
2685 radeon_set_context_reg(cs,
2686 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2687 primitive_reset_en);
2688 }
2689 }
2690
2691 if (primitive_reset_en) {
2692 uint32_t primitive_reset_index =
2693 radv_get_primitive_reset_index(cmd_buffer);
2694
2695 if (primitive_reset_index != state->last_primitive_reset_index) {
2696 radeon_set_context_reg(cs,
2697 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2698 primitive_reset_index);
2699 state->last_primitive_reset_index = primitive_reset_index;
2700 }
2701 }
2702
2703 if (draw_info->strmout_buffer) {
2704 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2705
2706 va += draw_info->strmout_buffer->offset +
2707 draw_info->strmout_buffer_offset;
2708
2709 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2710 draw_info->stride);
2711
2712 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2713 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2714 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2715 COPY_DATA_WR_CONFIRM);
2716 radeon_emit(cs, va);
2717 radeon_emit(cs, va >> 32);
2718 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2719 radeon_emit(cs, 0); /* unused */
2720
2721 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2722 }
2723 }
2724
2725 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2726 VkPipelineStageFlags src_stage_mask)
2727 {
2728 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2729 VK_PIPELINE_STAGE_TRANSFER_BIT |
2730 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2731 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2732 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2733 }
2734
2735 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2736 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2737 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2738 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2739 VK_PIPELINE_STAGE_TRANSFER_BIT |
2740 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2741 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2742 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2743 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2744 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2745 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2746 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2747 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2748 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2749 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2750 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2751 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2752 }
2753 }
2754
2755 static enum radv_cmd_flush_bits
2756 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2757 VkAccessFlags src_flags,
2758 struct radv_image *image)
2759 {
2760 bool flush_CB_meta = true, flush_DB_meta = true;
2761 enum radv_cmd_flush_bits flush_bits = 0;
2762 uint32_t b;
2763
2764 if (image) {
2765 if (!radv_image_has_CB_metadata(image))
2766 flush_CB_meta = false;
2767 if (!radv_image_has_htile(image))
2768 flush_DB_meta = false;
2769 }
2770
2771 for_each_bit(b, src_flags) {
2772 switch ((VkAccessFlagBits)(1 << b)) {
2773 case VK_ACCESS_SHADER_WRITE_BIT:
2774 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2775 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2776 flush_bits |= RADV_CMD_FLAG_WB_L2;
2777 break;
2778 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2779 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2780 if (flush_CB_meta)
2781 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2782 break;
2783 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2784 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2785 if (flush_DB_meta)
2786 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2787 break;
2788 case VK_ACCESS_TRANSFER_WRITE_BIT:
2789 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2790 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2791 RADV_CMD_FLAG_INV_L2;
2792
2793 if (flush_CB_meta)
2794 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2795 if (flush_DB_meta)
2796 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2797 break;
2798 default:
2799 break;
2800 }
2801 }
2802 return flush_bits;
2803 }
2804
2805 static enum radv_cmd_flush_bits
2806 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2807 VkAccessFlags dst_flags,
2808 struct radv_image *image)
2809 {
2810 bool flush_CB_meta = true, flush_DB_meta = true;
2811 enum radv_cmd_flush_bits flush_bits = 0;
2812 bool flush_CB = true, flush_DB = true;
2813 bool image_is_coherent = false;
2814 uint32_t b;
2815
2816 if (image) {
2817 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2818 flush_CB = false;
2819 flush_DB = false;
2820 }
2821
2822 if (!radv_image_has_CB_metadata(image))
2823 flush_CB_meta = false;
2824 if (!radv_image_has_htile(image))
2825 flush_DB_meta = false;
2826
2827 /* TODO: implement shader coherent for GFX10 */
2828
2829 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
2830 if (image->info.samples == 1 &&
2831 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2832 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2833 !vk_format_is_stencil(image->vk_format)) {
2834 /* Single-sample color and single-sample depth
2835 * (not stencil) are coherent with shaders on
2836 * GFX9.
2837 */
2838 image_is_coherent = true;
2839 }
2840 }
2841 }
2842
2843 for_each_bit(b, dst_flags) {
2844 switch ((VkAccessFlagBits)(1 << b)) {
2845 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2846 case VK_ACCESS_INDEX_READ_BIT:
2847 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2848 break;
2849 case VK_ACCESS_UNIFORM_READ_BIT:
2850 flush_bits |= RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_SCACHE;
2851 break;
2852 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2853 case VK_ACCESS_TRANSFER_READ_BIT:
2854 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2855 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
2856 RADV_CMD_FLAG_INV_L2;
2857 break;
2858 case VK_ACCESS_SHADER_READ_BIT:
2859 flush_bits |= RADV_CMD_FLAG_INV_VCACHE;
2860 /* Unlike LLVM, ACO uses SMEM for SSBOs and we have to
2861 * invalidate the scalar cache. */
2862 if (cmd_buffer->device->physical_device->use_aco &&
2863 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8)
2864 flush_bits |= RADV_CMD_FLAG_INV_SCACHE;
2865
2866 if (!image_is_coherent)
2867 flush_bits |= RADV_CMD_FLAG_INV_L2;
2868 break;
2869 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2870 if (flush_CB)
2871 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2872 if (flush_CB_meta)
2873 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2874 break;
2875 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2876 if (flush_DB)
2877 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2878 if (flush_DB_meta)
2879 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2880 break;
2881 default:
2882 break;
2883 }
2884 }
2885 return flush_bits;
2886 }
2887
2888 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2889 const struct radv_subpass_barrier *barrier)
2890 {
2891 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2892 NULL);
2893 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2894 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2895 NULL);
2896 }
2897
2898 uint32_t
2899 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
2900 {
2901 struct radv_cmd_state *state = &cmd_buffer->state;
2902 uint32_t subpass_id = state->subpass - state->pass->subpasses;
2903
2904 /* The id of this subpass shouldn't exceed the number of subpasses in
2905 * this render pass minus 1.
2906 */
2907 assert(subpass_id < state->pass->subpass_count);
2908 return subpass_id;
2909 }
2910
2911 static struct radv_sample_locations_state *
2912 radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer,
2913 uint32_t att_idx,
2914 bool begin_subpass)
2915 {
2916 struct radv_cmd_state *state = &cmd_buffer->state;
2917 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
2918 struct radv_image_view *view = state->attachments[att_idx].iview;
2919
2920 if (view->image->info.samples == 1)
2921 return NULL;
2922
2923 if (state->pass->attachments[att_idx].first_subpass_idx == subpass_id) {
2924 /* Return the initial sample locations if this is the initial
2925 * layout transition of the given subpass attachemnt.
2926 */
2927 if (state->attachments[att_idx].sample_location.count > 0)
2928 return &state->attachments[att_idx].sample_location;
2929 } else {
2930 /* Otherwise return the subpass sample locations if defined. */
2931 if (state->subpass_sample_locs) {
2932 /* Because the driver sets the current subpass before
2933 * initial layout transitions, we should use the sample
2934 * locations from the previous subpass to avoid an
2935 * off-by-one problem. Otherwise, use the sample
2936 * locations for the current subpass for final layout
2937 * transitions.
2938 */
2939 if (begin_subpass)
2940 subpass_id--;
2941
2942 for (uint32_t i = 0; i < state->num_subpass_sample_locs; i++) {
2943 if (state->subpass_sample_locs[i].subpass_idx == subpass_id)
2944 return &state->subpass_sample_locs[i].sample_location;
2945 }
2946 }
2947 }
2948
2949 return NULL;
2950 }
2951
2952 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2953 struct radv_subpass_attachment att,
2954 bool begin_subpass)
2955 {
2956 unsigned idx = att.attachment;
2957 struct radv_image_view *view = cmd_buffer->state.attachments[idx].iview;
2958 struct radv_sample_locations_state *sample_locs;
2959 VkImageSubresourceRange range;
2960 range.aspectMask = view->aspect_mask;
2961 range.baseMipLevel = view->base_mip;
2962 range.levelCount = 1;
2963 range.baseArrayLayer = view->base_layer;
2964 range.layerCount = cmd_buffer->state.framebuffer->layers;
2965
2966 if (cmd_buffer->state.subpass->view_mask) {
2967 /* If the current subpass uses multiview, the driver might have
2968 * performed a fast color/depth clear to the whole image
2969 * (including all layers). To make sure the driver will
2970 * decompress the image correctly (if needed), we have to
2971 * account for the "real" number of layers. If the view mask is
2972 * sparse, this will decompress more layers than needed.
2973 */
2974 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
2975 }
2976
2977 /* Get the subpass sample locations for the given attachment, if NULL
2978 * is returned the driver will use the default HW locations.
2979 */
2980 sample_locs = radv_get_attachment_sample_locations(cmd_buffer, idx,
2981 begin_subpass);
2982
2983 /* Determine if the subpass uses separate depth/stencil layouts. */
2984 bool uses_separate_depth_stencil_layouts = false;
2985 if ((cmd_buffer->state.attachments[idx].current_layout !=