projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: fix possibly wrong PA_SC_AA_CONFIG value for conservative rast
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 bool src_render_loop,
58 VkImageLayout dst_layout,
59 bool dst_render_loop,
60 uint32_t src_family,
61 uint32_t dst_family,
62 const VkImageSubresourceRange *range,
63 struct radv_sample_locations_state *sample_locs);
64
65 const struct radv_dynamic_state default_dynamic_state = {
66 .viewport = {
67 .count = 0,
68 },
69 .scissor = {
70 .count = 0,
71 },
72 .line_width = 1.0f,
73 .depth_bias = {
74 .bias = 0.0f,
75 .clamp = 0.0f,
76 .slope = 0.0f,
77 },
78 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
79 .depth_bounds = {
80 .min = 0.0f,
81 .max = 1.0f,
82 },
83 .stencil_compare_mask = {
84 .front = ~0u,
85 .back = ~0u,
86 },
87 .stencil_write_mask = {
88 .front = ~0u,
89 .back = ~0u,
90 },
91 .stencil_reference = {
92 .front = 0u,
93 .back = 0u,
94 },
95 };
96
97 static void
98 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
99 const struct radv_dynamic_state *src)
100 {
101 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
102 uint32_t copy_mask = src->mask;
103 uint32_t dest_mask = 0;
104
105 /* Make sure to copy the number of viewports/scissors because they can
106 * only be specified at pipeline creation time.
107 */
108 dest->viewport.count = src->viewport.count;
109 dest->scissor.count = src->scissor.count;
110 dest->discard_rectangle.count = src->discard_rectangle.count;
111 dest->sample_location.count = src->sample_location.count;
112
113 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
114 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
115 src->viewport.count * sizeof(VkViewport))) {
116 typed_memcpy(dest->viewport.viewports,
117 src->viewport.viewports,
118 src->viewport.count);
119 dest_mask |= RADV_DYNAMIC_VIEWPORT;
120 }
121 }
122
123 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
124 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
125 src->scissor.count * sizeof(VkRect2D))) {
126 typed_memcpy(dest->scissor.scissors,
127 src->scissor.scissors, src->scissor.count);
128 dest_mask |= RADV_DYNAMIC_SCISSOR;
129 }
130 }
131
132 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
133 if (dest->line_width != src->line_width) {
134 dest->line_width = src->line_width;
135 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
136 }
137 }
138
139 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
140 if (memcmp(&dest->depth_bias, &src->depth_bias,
141 sizeof(src->depth_bias))) {
142 dest->depth_bias = src->depth_bias;
143 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
144 }
145 }
146
147 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
148 if (memcmp(&dest->blend_constants, &src->blend_constants,
149 sizeof(src->blend_constants))) {
150 typed_memcpy(dest->blend_constants,
151 src->blend_constants, 4);
152 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
153 }
154 }
155
156 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
157 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
158 sizeof(src->depth_bounds))) {
159 dest->depth_bounds = src->depth_bounds;
160 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
161 }
162 }
163
164 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
165 if (memcmp(&dest->stencil_compare_mask,
166 &src->stencil_compare_mask,
167 sizeof(src->stencil_compare_mask))) {
168 dest->stencil_compare_mask = src->stencil_compare_mask;
169 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
170 }
171 }
172
173 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
174 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
175 sizeof(src->stencil_write_mask))) {
176 dest->stencil_write_mask = src->stencil_write_mask;
177 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
178 }
179 }
180
181 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
182 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
183 sizeof(src->stencil_reference))) {
184 dest->stencil_reference = src->stencil_reference;
185 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
186 }
187 }
188
189 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
190 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
191 src->discard_rectangle.count * sizeof(VkRect2D))) {
192 typed_memcpy(dest->discard_rectangle.rectangles,
193 src->discard_rectangle.rectangles,
194 src->discard_rectangle.count);
195 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
196 }
197 }
198
199 if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
200 if (dest->sample_location.per_pixel != src->sample_location.per_pixel ||
201 dest->sample_location.grid_size.width != src->sample_location.grid_size.width ||
202 dest->sample_location.grid_size.height != src->sample_location.grid_size.height ||
203 memcmp(&dest->sample_location.locations,
204 &src->sample_location.locations,
205 src->sample_location.count * sizeof(VkSampleLocationEXT))) {
206 dest->sample_location.per_pixel = src->sample_location.per_pixel;
207 dest->sample_location.grid_size = src->sample_location.grid_size;
208 typed_memcpy(dest->sample_location.locations,
209 src->sample_location.locations,
210 src->sample_location.count);
211 dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
212 }
213 }
214
215 cmd_buffer->state.dirty |= dest_mask;
216 }
217
218 static void
219 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
220 struct radv_pipeline *pipeline)
221 {
222 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
223 struct radv_shader_info *info;
224
225 if (!pipeline->streamout_shader ||
226 cmd_buffer->device->physical_device->use_ngg_streamout)
227 return;
228
229 info = &pipeline->streamout_shader->info;
230 for (int i = 0; i < MAX_SO_BUFFERS; i++)
231 so->stride_in_dw[i] = info->so.strides[i];
232
233 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
234 }
235
236 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
237 {
238 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
239 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
240 }
241
242 enum ring_type radv_queue_family_to_ring(int f) {
243 switch (f) {
244 case RADV_QUEUE_GENERAL:
245 return RING_GFX;
246 case RADV_QUEUE_COMPUTE:
247 return RING_COMPUTE;
248 case RADV_QUEUE_TRANSFER:
249 return RING_DMA;
250 default:
251 unreachable("Unknown queue family");
252 }
253 }
254
255 static VkResult radv_create_cmd_buffer(
256 struct radv_device * device,
257 struct radv_cmd_pool * pool,
258 VkCommandBufferLevel level,
259 VkCommandBuffer* pCommandBuffer)
260 {
261 struct radv_cmd_buffer *cmd_buffer;
262 unsigned ring;
263 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
264 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
265 if (cmd_buffer == NULL)
266 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
267
268 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
269 cmd_buffer->device = device;
270 cmd_buffer->pool = pool;
271 cmd_buffer->level = level;
272
273 if (pool) {
274 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
275 cmd_buffer->queue_family_index = pool->queue_family_index;
276
277 } else {
278 /* Init the pool_link so we can safely call list_del when we destroy
279 * the command buffer
280 */
281 list_inithead(&cmd_buffer->pool_link);
282 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
283 }
284
285 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
286
287 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
288 if (!cmd_buffer->cs) {
289 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
290 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
291 }
292
293 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
294
295 list_inithead(&cmd_buffer->upload.list);
296
297 return VK_SUCCESS;
298 }
299
300 static void
301 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
302 {
303 list_del(&cmd_buffer->pool_link);
304
305 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
306 &cmd_buffer->upload.list, list) {
307 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
308 list_del(&up->list);
309 free(up);
310 }
311
312 if (cmd_buffer->upload.upload_bo)
313 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
314 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
315
316 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
317 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
318
319 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
320 }
321
322 static VkResult
323 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
324 {
325 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
326
327 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
328 &cmd_buffer->upload.list, list) {
329 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
330 list_del(&up->list);
331 free(up);
332 }
333
334 cmd_buffer->push_constant_stages = 0;
335 cmd_buffer->scratch_size_per_wave_needed = 0;
336 cmd_buffer->scratch_waves_wanted = 0;
337 cmd_buffer->compute_scratch_size_per_wave_needed = 0;
338 cmd_buffer->compute_scratch_waves_wanted = 0;
339 cmd_buffer->esgs_ring_size_needed = 0;
340 cmd_buffer->gsvs_ring_size_needed = 0;
341 cmd_buffer->tess_rings_needed = false;
342 cmd_buffer->gds_needed = false;
343 cmd_buffer->sample_positions_needed = false;
344
345 if (cmd_buffer->upload.upload_bo)
346 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
347 cmd_buffer->upload.upload_bo);
348 cmd_buffer->upload.offset = 0;
349
350 cmd_buffer->record_result = VK_SUCCESS;
351
352 memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
353
354 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
355 cmd_buffer->descriptors[i].dirty = 0;
356 cmd_buffer->descriptors[i].valid = 0;
357 cmd_buffer->descriptors[i].push_dirty = false;
358 }
359
360 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
361 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
362 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
363 unsigned fence_offset, eop_bug_offset;
364 void *fence_ptr;
365
366 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
367 &fence_ptr);
368
369 cmd_buffer->gfx9_fence_va =
370 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
371 cmd_buffer->gfx9_fence_va += fence_offset;
372
373 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
374 /* Allocate a buffer for the EOP bug on GFX9. */
375 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
376 &eop_bug_offset, &fence_ptr);
377 cmd_buffer->gfx9_eop_bug_va =
378 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
379 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
380 }
381 }
382
383 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
384
385 return cmd_buffer->record_result;
386 }
387
388 static bool
389 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
390 uint64_t min_needed)
391 {
392 uint64_t new_size;
393 struct radeon_winsys_bo *bo;
394 struct radv_cmd_buffer_upload *upload;
395 struct radv_device *device = cmd_buffer->device;
396
397 new_size = MAX2(min_needed, 16 * 1024);
398 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
399
400 bo = device->ws->buffer_create(device->ws,
401 new_size, 4096,
402 RADEON_DOMAIN_GTT,
403 RADEON_FLAG_CPU_ACCESS|
404 RADEON_FLAG_NO_INTERPROCESS_SHARING |
405 RADEON_FLAG_32BIT,
406 RADV_BO_PRIORITY_UPLOAD_BUFFER);
407
408 if (!bo) {
409 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
410 return false;
411 }
412
413 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
414 if (cmd_buffer->upload.upload_bo) {
415 upload = malloc(sizeof(*upload));
416
417 if (!upload) {
418 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
419 device->ws->buffer_destroy(bo);
420 return false;
421 }
422
423 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
424 list_add(&upload->list, &cmd_buffer->upload.list);
425 }
426
427 cmd_buffer->upload.upload_bo = bo;
428 cmd_buffer->upload.size = new_size;
429 cmd_buffer->upload.offset = 0;
430 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
431
432 if (!cmd_buffer->upload.map) {
433 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
434 return false;
435 }
436
437 return true;
438 }
439
440 bool
441 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
442 unsigned size,
443 unsigned alignment,
444 unsigned *out_offset,
445 void **ptr)
446 {
447 assert(util_is_power_of_two_nonzero(alignment));
448
449 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
450 if (offset + size > cmd_buffer->upload.size) {
451 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
452 return false;
453 offset = 0;
454 }
455
456 *out_offset = offset;
457 *ptr = cmd_buffer->upload.map + offset;
458
459 cmd_buffer->upload.offset = offset + size;
460 return true;
461 }
462
463 bool
464 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
465 unsigned size, unsigned alignment,
466 const void *data, unsigned *out_offset)
467 {
468 uint8_t *ptr;
469
470 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
471 out_offset, (void **)&ptr))
472 return false;
473
474 if (ptr)
475 memcpy(ptr, data, size);
476
477 return true;
478 }
479
480 static void
481 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
482 unsigned count, const uint32_t *data)
483 {
484 struct radeon_cmdbuf *cs = cmd_buffer->cs;
485
486 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
487
488 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
489 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
490 S_370_WR_CONFIRM(1) |
491 S_370_ENGINE_SEL(V_370_ME));
492 radeon_emit(cs, va);
493 radeon_emit(cs, va >> 32);
494 radeon_emit_array(cs, data, count);
495 }
496
497 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
498 {
499 struct radv_device *device = cmd_buffer->device;
500 struct radeon_cmdbuf *cs = cmd_buffer->cs;
501 uint64_t va;
502
503 va = radv_buffer_get_va(device->trace_bo);
504 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
505 va += 4;
506
507 ++cmd_buffer->state.trace_id;
508 radv_emit_write_data_packet(cmd_buffer, va, 1,
509 &cmd_buffer->state.trace_id);
510
511 radeon_check_space(cmd_buffer->device->ws, cs, 2);
512
513 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
514 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
515 }
516
517 static void
518 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
519 enum radv_cmd_flush_bits flags)
520 {
521 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
522 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
523 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
524
525 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
526
527 /* Force wait for graphics or compute engines to be idle. */
528 si_cs_emit_cache_flush(cmd_buffer->cs,
529 cmd_buffer->device->physical_device->rad_info.chip_class,
530 &cmd_buffer->gfx9_fence_idx,
531 cmd_buffer->gfx9_fence_va,
532 radv_cmd_buffer_uses_mec(cmd_buffer),
533 flags, cmd_buffer->gfx9_eop_bug_va);
534 }
535
536 if (unlikely(cmd_buffer->device->trace_bo))
537 radv_cmd_buffer_trace_emit(cmd_buffer);
538 }
539
540 static void
541 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
542 struct radv_pipeline *pipeline, enum ring_type ring)
543 {
544 struct radv_device *device = cmd_buffer->device;
545 uint32_t data[2];
546 uint64_t va;
547
548 va = radv_buffer_get_va(device->trace_bo);
549
550 switch (ring) {
551 case RING_GFX:
552 va += 8;
553 break;
554 case RING_COMPUTE:
555 va += 16;
556 break;
557 default:
558 assert(!"invalid ring type");
559 }
560
561 uint64_t pipeline_address = (uintptr_t)pipeline;
562 data[0] = pipeline_address;
563 data[1] = pipeline_address >> 32;
564
565 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
566 }
567
568 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
569 VkPipelineBindPoint bind_point,
570 struct radv_descriptor_set *set,
571 unsigned idx)
572 {
573 struct radv_descriptor_state *descriptors_state =
574 radv_get_descriptors_state(cmd_buffer, bind_point);
575
576 descriptors_state->sets[idx] = set;
577
578 descriptors_state->valid |= (1u << idx); /* active descriptors */
579 descriptors_state->dirty |= (1u << idx);
580 }
581
582 static void
583 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
584 VkPipelineBindPoint bind_point)
585 {
586 struct radv_descriptor_state *descriptors_state =
587 radv_get_descriptors_state(cmd_buffer, bind_point);
588 struct radv_device *device = cmd_buffer->device;
589 uint32_t data[MAX_SETS * 2] = {};
590 uint64_t va;
591 unsigned i;
592 va = radv_buffer_get_va(device->trace_bo) + 24;
593
594 for_each_bit(i, descriptors_state->valid) {
595 struct radv_descriptor_set *set = descriptors_state->sets[i];
596 data[i * 2] = (uint64_t)(uintptr_t)set;
597 data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
598 }
599
600 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
601 }
602
603 struct radv_userdata_info *
604 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
605 gl_shader_stage stage,
606 int idx)
607 {
608 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
609 return &shader->info.user_sgprs_locs.shader_data[idx];
610 }
611
612 static void
613 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
614 struct radv_pipeline *pipeline,
615 gl_shader_stage stage,
616 int idx, uint64_t va)
617 {
618 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
619 uint32_t base_reg = pipeline->user_data_0[stage];
620 if (loc->sgpr_idx == -1)
621 return;
622
623 assert(loc->num_sgprs == 1);
624
625 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
626 base_reg + loc->sgpr_idx * 4, va, false);
627 }
628
629 static void
630 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
631 struct radv_pipeline *pipeline,
632 struct radv_descriptor_state *descriptors_state,
633 gl_shader_stage stage)
634 {
635 struct radv_device *device = cmd_buffer->device;
636 struct radeon_cmdbuf *cs = cmd_buffer->cs;
637 uint32_t sh_base = pipeline->user_data_0[stage];
638 struct radv_userdata_locations *locs =
639 &pipeline->shaders[stage]->info.user_sgprs_locs;
640 unsigned mask = locs->descriptor_sets_enabled;
641
642 mask &= descriptors_state->dirty & descriptors_state->valid;
643
644 while (mask) {
645 int start, count;
646
647 u_bit_scan_consecutive_range(&mask, &start, &count);
648
649 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
650 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
651
652 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
653 for (int i = 0; i < count; i++) {
654 struct radv_descriptor_set *set =
655 descriptors_state->sets[start + i];
656
657 radv_emit_shader_pointer_body(device, cs, set->va, true);
658 }
659 }
660 }
661
662 /**
663 * Convert the user sample locations to hardware sample locations (the values
664 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
665 */
666 static void
667 radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
668 uint32_t x, uint32_t y, VkOffset2D *sample_locs)
669 {
670 uint32_t x_offset = x % state->grid_size.width;
671 uint32_t y_offset = y % state->grid_size.height;
672 uint32_t num_samples = (uint32_t)state->per_pixel;
673 VkSampleLocationEXT *user_locs;
674 uint32_t pixel_offset;
675
676 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
677
678 assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
679 user_locs = &state->locations[pixel_offset];
680
681 for (uint32_t i = 0; i < num_samples; i++) {
682 float shifted_pos_x = user_locs[i].x - 0.5;
683 float shifted_pos_y = user_locs[i].y - 0.5;
684
685 int32_t scaled_pos_x = floor(shifted_pos_x * 16);
686 int32_t scaled_pos_y = floor(shifted_pos_y * 16);
687
688 sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
689 sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
690 }
691 }
692
693 /**
694 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
695 * locations.
696 */
697 static void
698 radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
699 uint32_t *sample_locs_pixel)
700 {
701 for (uint32_t i = 0; i < num_samples; i++) {
702 uint32_t sample_reg_idx = i / 4;
703 uint32_t sample_loc_idx = i % 4;
704 int32_t pos_x = sample_locs[i].x;
705 int32_t pos_y = sample_locs[i].y;
706
707 uint32_t shift_x = 8 * sample_loc_idx;
708 uint32_t shift_y = shift_x + 4;
709
710 sample_locs_pixel[sample_reg_idx] |= (pos_x & 0xf) << shift_x;
711 sample_locs_pixel[sample_reg_idx] |= (pos_y & 0xf) << shift_y;
712 }
713 }
714
715 /**
716 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
717 * sample locations.
718 */
719 static uint64_t
720 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer,
721 VkOffset2D *sample_locs,
722 uint32_t num_samples)
723 {
724 uint32_t centroid_priorities[num_samples];
725 uint32_t sample_mask = num_samples - 1;
726 uint32_t distances[num_samples];
727 uint64_t centroid_priority = 0;
728
729 /* Compute the distances from center for each sample. */
730 for (int i = 0; i < num_samples; i++) {
731 distances[i] = (sample_locs[i].x * sample_locs[i].x) +
732 (sample_locs[i].y * sample_locs[i].y);
733 }
734
735 /* Compute the centroid priorities by looking at the distances array. */
736 for (int i = 0; i < num_samples; i++) {
737 uint32_t min_idx = 0;
738
739 for (int j = 1; j < num_samples; j++) {
740 if (distances[j] < distances[min_idx])
741 min_idx = j;
742 }
743
744 centroid_priorities[i] = min_idx;
745 distances[min_idx] = 0xffffffff;
746 }
747
748 /* Compute the final centroid priority. */
749 for (int i = 0; i < 8; i++) {
750 centroid_priority |=
751 centroid_priorities[i & sample_mask] << (i * 4);
752 }
753
754 return centroid_priority << 32 | centroid_priority;
755 }
756
757 /**
758 * Emit the sample locations that are specified with VK_EXT_sample_locations.
759 */
760 static void
761 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
762 {
763 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
764 struct radv_multisample_state *ms = &pipeline->graphics.ms;
765 struct radv_sample_locations_state *sample_location =
766 &cmd_buffer->state.dynamic.sample_location;
767 uint32_t num_samples = (uint32_t)sample_location->per_pixel;
768 struct radeon_cmdbuf *cs = cmd_buffer->cs;
769 uint32_t sample_locs_pixel[4][2] = {};
770 VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
771 uint32_t max_sample_dist = 0;
772 uint64_t centroid_priority;
773
774 if (!cmd_buffer->state.dynamic.sample_location.count)
775 return;
776
777 /* Convert the user sample locations to hardware sample locations. */
778 radv_convert_user_sample_locs(sample_location, 0, 0, sample_locs[0]);
779 radv_convert_user_sample_locs(sample_location, 1, 0, sample_locs[1]);
780 radv_convert_user_sample_locs(sample_location, 0, 1, sample_locs[2]);
781 radv_convert_user_sample_locs(sample_location, 1, 1, sample_locs[3]);
782
783 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
784 for (uint32_t i = 0; i < 4; i++) {
785 radv_compute_sample_locs_pixel(num_samples, sample_locs[i],
786 sample_locs_pixel[i]);
787 }
788
789 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
790 centroid_priority =
791 radv_compute_centroid_priority(cmd_buffer, sample_locs[0],
792 num_samples);
793
794 /* Compute the maximum sample distance from the specified locations. */
795 for (uint32_t i = 0; i < num_samples; i++) {
796 VkOffset2D offset = sample_locs[0][i];
797 max_sample_dist = MAX2(max_sample_dist,
798 MAX2(abs(offset.x), abs(offset.y)));
799 }
800
801 /* Emit the specified user sample locations. */
802 switch (num_samples) {
803 case 2:
804 case 4:
805 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
806 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
807 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
808 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
809 break;
810 case 8:
811 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
812 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
813 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
814 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
815 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs_pixel[0][1]);
816 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs_pixel[1][1]);
817 radeon_set_context_reg(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs_pixel[2][1]);
818 radeon_set_context_reg(cs, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs_pixel[3][1]);
819 break;
820 default:
821 unreachable("invalid number of samples");
822 }
823
824 /* Emit the maximum sample distance and the centroid priority. */
825 uint32_t pa_sc_aa_config = ms->pa_sc_aa_config;
826
827 pa_sc_aa_config &= C_028BE0_MAX_SAMPLE_DIST;
828 pa_sc_aa_config |= S_028BE0_MAX_SAMPLE_DIST(max_sample_dist);
829
830 radeon_set_context_reg_seq(cs, R_028BE0_PA_SC_AA_CONFIG, 1);
831 radeon_emit(cs, pa_sc_aa_config);
832
833 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
834 radeon_emit(cs, centroid_priority);
835 radeon_emit(cs, centroid_priority >> 32);
836
837 /* GFX9: Flush DFSM when the AA mode changes. */
838 if (cmd_buffer->device->dfsm_allowed) {
839 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
840 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
841 }
842
843 cmd_buffer->state.context_roll_without_scissor_emitted = true;
844 }
845
846 static void
847 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
848 struct radv_pipeline *pipeline,
849 gl_shader_stage stage,
850 int idx, int count, uint32_t *values)
851 {
852 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
853 uint32_t base_reg = pipeline->user_data_0[stage];
854 if (loc->sgpr_idx == -1)
855 return;
856
857 assert(loc->num_sgprs == count);
858
859 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
860 radeon_emit_array(cmd_buffer->cs, values, count);
861 }
862
863 static void
864 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
865 struct radv_pipeline *pipeline)
866 {
867 int num_samples = pipeline->graphics.ms.num_samples;
868 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
869
870 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.needs_sample_positions)
871 cmd_buffer->sample_positions_needed = true;
872
873 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
874 return;
875
876 radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
877
878 cmd_buffer->state.context_roll_without_scissor_emitted = true;
879 }
880
881 static void
882 radv_update_binning_state(struct radv_cmd_buffer *cmd_buffer,
883 struct radv_pipeline *pipeline)
884 {
885 const struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
886
887
888 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
889 return;
890
891 if (old_pipeline &&
892 old_pipeline->graphics.binning.pa_sc_binner_cntl_0 == pipeline->graphics.binning.pa_sc_binner_cntl_0 &&
893 old_pipeline->graphics.binning.db_dfsm_control == pipeline->graphics.binning.db_dfsm_control)
894 return;
895
896 bool binning_flush = false;
897 if (cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA12 ||
898 cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA20 ||
899 cmd_buffer->device->physical_device->rad_info.family == CHIP_RAVEN2 ||
900 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
901 binning_flush = !old_pipeline ||
902 G_028C44_BINNING_MODE(old_pipeline->graphics.binning.pa_sc_binner_cntl_0) !=
903 G_028C44_BINNING_MODE(pipeline->graphics.binning.pa_sc_binner_cntl_0);
904 }
905
906 radeon_set_context_reg(cmd_buffer->cs, R_028C44_PA_SC_BINNER_CNTL_0,
907 pipeline->graphics.binning.pa_sc_binner_cntl_0 |
908 S_028C44_FLUSH_ON_BINNING_TRANSITION(!!binning_flush));
909
910 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
911 radeon_set_context_reg(cmd_buffer->cs, R_028038_DB_DFSM_CONTROL,
912 pipeline->graphics.binning.db_dfsm_control);
913 } else {
914 radeon_set_context_reg(cmd_buffer->cs, R_028060_DB_DFSM_CONTROL,
915 pipeline->graphics.binning.db_dfsm_control);
916 }
917
918 cmd_buffer->state.context_roll_without_scissor_emitted = true;
919 }
920
921
922 static void
923 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
924 struct radv_shader_variant *shader)
925 {
926 uint64_t va;
927
928 if (!shader)
929 return;
930
931 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
932
933 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
934 }
935
936 static void
937 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
938 struct radv_pipeline *pipeline,
939 bool vertex_stage_only)
940 {
941 struct radv_cmd_state *state = &cmd_buffer->state;
942 uint32_t mask = state->prefetch_L2_mask;
943
944 if (vertex_stage_only) {
945 /* Fast prefetch path for starting draws as soon as possible.
946 */
947 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
948 RADV_PREFETCH_VBO_DESCRIPTORS);
949 }
950
951 if (mask & RADV_PREFETCH_VS)
952 radv_emit_shader_prefetch(cmd_buffer,
953 pipeline->shaders[MESA_SHADER_VERTEX]);
954
955 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
956 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
957
958 if (mask & RADV_PREFETCH_TCS)
959 radv_emit_shader_prefetch(cmd_buffer,
960 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
961
962 if (mask & RADV_PREFETCH_TES)
963 radv_emit_shader_prefetch(cmd_buffer,
964 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
965
966 if (mask & RADV_PREFETCH_GS) {
967 radv_emit_shader_prefetch(cmd_buffer,
968 pipeline->shaders[MESA_SHADER_GEOMETRY]);
969 if (radv_pipeline_has_gs_copy_shader(pipeline))
970 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
971 }
972
973 if (mask & RADV_PREFETCH_PS)
974 radv_emit_shader_prefetch(cmd_buffer,
975 pipeline->shaders[MESA_SHADER_FRAGMENT]);
976
977 state->prefetch_L2_mask &= ~mask;
978 }
979
980 static void
981 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
982 {
983 if (!cmd_buffer->device->physical_device->rad_info.rbplus_allowed)
984 return;
985
986 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
987 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
988
989 unsigned sx_ps_downconvert = 0;
990 unsigned sx_blend_opt_epsilon = 0;
991 unsigned sx_blend_opt_control = 0;
992
993 if (!cmd_buffer->state.attachments || !subpass)
994 return;
995
996 for (unsigned i = 0; i < subpass->color_count; ++i) {
997 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
998 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
999 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1000 continue;
1001 }
1002
1003 int idx = subpass->color_attachments[i].attachment;
1004 struct radv_color_buffer_info *cb = &cmd_buffer->state.attachments[idx].cb;
1005
1006 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
1007 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
1008 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
1009 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
1010
1011 bool has_alpha, has_rgb;
1012
1013 /* Set if RGB and A are present. */
1014 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
1015
1016 if (format == V_028C70_COLOR_8 ||
1017 format == V_028C70_COLOR_16 ||
1018 format == V_028C70_COLOR_32)
1019 has_rgb = !has_alpha;
1020 else
1021 has_rgb = true;
1022
1023 /* Check the colormask and export format. */
1024 if (!(colormask & 0x7))
1025 has_rgb = false;
1026 if (!(colormask & 0x8))
1027 has_alpha = false;
1028
1029 if (spi_format == V_028714_SPI_SHADER_ZERO) {
1030 has_rgb = false;
1031 has_alpha = false;
1032 }
1033
1034 /* Disable value checking for disabled channels. */
1035 if (!has_rgb)
1036 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1037 if (!has_alpha)
1038 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1039
1040 /* Enable down-conversion for 32bpp and smaller formats. */
1041 switch (format) {
1042 case V_028C70_COLOR_8:
1043 case V_028C70_COLOR_8_8:
1044 case V_028C70_COLOR_8_8_8_8:
1045 /* For 1 and 2-channel formats, use the superset thereof. */
1046 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
1047 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1048 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1049 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
1050 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
1051 }
1052 break;
1053
1054 case V_028C70_COLOR_5_6_5:
1055 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1056 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
1057 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
1058 }
1059 break;
1060
1061 case V_028C70_COLOR_1_5_5_5:
1062 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1063 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
1064 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
1065 }
1066 break;
1067
1068 case V_028C70_COLOR_4_4_4_4:
1069 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1070 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
1071 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
1072 }
1073 break;
1074
1075 case V_028C70_COLOR_32:
1076 if (swap == V_028C70_SWAP_STD &&
1077 spi_format == V_028714_SPI_SHADER_32_R)
1078 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1079 else if (swap == V_028C70_SWAP_ALT_REV &&
1080 spi_format == V_028714_SPI_SHADER_32_AR)
1081 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
1082 break;
1083
1084 case V_028C70_COLOR_16:
1085 case V_028C70_COLOR_16_16:
1086 /* For 1-channel formats, use the superset thereof. */
1087 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
1088 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
1089 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1090 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1091 if (swap == V_028C70_SWAP_STD ||
1092 swap == V_028C70_SWAP_STD_REV)
1093 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
1094 else
1095 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
1096 }
1097 break;
1098
1099 case V_028C70_COLOR_10_11_11:
1100 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1101 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
1102 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
1103 }
1104 break;
1105
1106 case V_028C70_COLOR_2_10_10_10:
1107 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1108 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
1109 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
1110 }
1111 break;
1112 }
1113 }
1114
1115 for (unsigned i = subpass->color_count; i < 8; ++i) {
1116 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1117 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1118 }
1119 /* TODO: avoid redundantly setting context registers */
1120 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
1121 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
1122 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
1123 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
1124
1125 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1126 }
1127
1128 static void
1129 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1130 {
1131 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1132
1133 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1134 return;
1135
1136 radv_update_multisample_state(cmd_buffer, pipeline);
1137 radv_update_binning_state(cmd_buffer, pipeline);
1138
1139 cmd_buffer->scratch_size_per_wave_needed = MAX2(cmd_buffer->scratch_size_per_wave_needed,
1140 pipeline->scratch_bytes_per_wave);
1141 cmd_buffer->scratch_waves_wanted = MAX2(cmd_buffer->scratch_waves_wanted,
1142 pipeline->max_waves);
1143
1144 if (!cmd_buffer->state.emitted_pipeline ||
1145 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1146 pipeline->graphics.can_use_guardband)
1147 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1148
1149 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
1150
1151 if (!cmd_buffer->state.emitted_pipeline ||
1152 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
1153 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
1154 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
1155 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
1156 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
1157 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1158 }
1159
1160 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
1161 if (!pipeline->shaders[i])
1162 continue;
1163
1164 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1165 pipeline->shaders[i]->bo);
1166 }
1167
1168 if (radv_pipeline_has_gs_copy_shader(pipeline))
1169 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1170 pipeline->gs_copy_shader->bo);
1171
1172 if (unlikely(cmd_buffer->device->trace_bo))
1173 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1174
1175 cmd_buffer->state.emitted_pipeline = pipeline;
1176
1177 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1178 }
1179
1180 static void
1181 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1182 {
1183 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1184 cmd_buffer->state.dynamic.viewport.viewports);
1185 }
1186
1187 static void
1188 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1189 {
1190 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1191
1192 si_write_scissors(cmd_buffer->cs, 0, count,
1193 cmd_buffer->state.dynamic.scissor.scissors,
1194 cmd_buffer->state.dynamic.viewport.viewports,
1195 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1196
1197 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1198 }
1199
1200 static void
1201 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1202 {
1203 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1204 return;
1205
1206 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1207 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1208 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1209 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1210 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1211 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1212 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1213 }
1214 }
1215
1216 static void
1217 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1218 {
1219 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1220
1221 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1222 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1223 }
1224
1225 static void
1226 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1227 {
1228 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1229
1230 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1231 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1232 }
1233
1234 static void
1235 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1236 {
1237 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1238
1239 radeon_set_context_reg_seq(cmd_buffer->cs,
1240 R_028430_DB_STENCILREFMASK, 2);
1241 radeon_emit(cmd_buffer->cs,
1242 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1243 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1244 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1245 S_028430_STENCILOPVAL(1));
1246 radeon_emit(cmd_buffer->cs,
1247 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1248 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1249 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1250 S_028434_STENCILOPVAL_BF(1));
1251 }
1252
1253 static void
1254 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1255 {
1256 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1257
1258 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1259 fui(d->depth_bounds.min));
1260 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1261 fui(d->depth_bounds.max));
1262 }
1263
1264 static void
1265 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1266 {
1267 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1268 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1269 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1270
1271
1272 radeon_set_context_reg_seq(cmd_buffer->cs,
1273 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1274 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1275 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1276 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1277 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1278 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1279 }
1280
1281 static void
1282 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1283 int index,
1284 struct radv_color_buffer_info *cb,
1285 struct radv_image_view *iview,
1286 VkImageLayout layout,
1287 bool in_render_loop)
1288 {
1289 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
1290 uint32_t cb_color_info = cb->cb_color_info;
1291 struct radv_image *image = iview->image;
1292
1293 if (!radv_layout_dcc_compressed(cmd_buffer->device, image, layout, in_render_loop,
1294 radv_image_queue_family_mask(image,
1295 cmd_buffer->queue_family_index,
1296 cmd_buffer->queue_family_index))) {
1297 cb_color_info &= C_028C70_DCC_ENABLE;
1298 }
1299
1300 if (radv_image_is_tc_compat_cmask(image) &&
1301 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1302 radv_is_dcc_decompress_pipeline(cmd_buffer))) {
1303 /* If this bit is set, the FMASK decompression operation
1304 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1305 */
1306 cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
1307 }
1308
1309 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1310 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1311 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1312 radeon_emit(cmd_buffer->cs, 0);
1313 radeon_emit(cmd_buffer->cs, 0);
1314 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1315 radeon_emit(cmd_buffer->cs, cb_color_info);
1316 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1317 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1318 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1319 radeon_emit(cmd_buffer->cs, 0);
1320 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1321 radeon_emit(cmd_buffer->cs, 0);
1322
1323 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 1);
1324 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1325
1326 radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4,
1327 cb->cb_color_base >> 32);
1328 radeon_set_context_reg(cmd_buffer->cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + index * 4,
1329 cb->cb_color_cmask >> 32);
1330 radeon_set_context_reg(cmd_buffer->cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + index * 4,
1331 cb->cb_color_fmask >> 32);
1332 radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4,
1333 cb->cb_dcc_base >> 32);
1334 radeon_set_context_reg(cmd_buffer->cs, R_028EC0_CB_COLOR0_ATTRIB2 + index * 4,
1335 cb->cb_color_attrib2);
1336 radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4,
1337 cb->cb_color_attrib3);
1338 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1339 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1340 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1341 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1342 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1343 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1344 radeon_emit(cmd_buffer->cs, cb_color_info);
1345 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1346 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1347 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1348 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1349 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1350 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1351
1352 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1353 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1354 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1355
1356 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1357 cb->cb_mrt_epitch);
1358 } else {
1359 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1360 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1361 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1362 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1363 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1364 radeon_emit(cmd_buffer->cs, cb_color_info);
1365 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1366 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1367 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1368 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1369 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1370 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1371
1372 if (is_vi) { /* DCC BASE */
1373 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1374 }
1375 }
1376
1377 if (radv_dcc_enabled(image, iview->base_mip)) {
1378 /* Drawing with DCC enabled also compresses colorbuffers. */
1379 VkImageSubresourceRange range = {
1380 .aspectMask = iview->aspect_mask,
1381 .baseMipLevel = iview->base_mip,
1382 .levelCount = iview->level_count,
1383 .baseArrayLayer = iview->base_layer,
1384 .layerCount = iview->layer_count,
1385 };
1386
1387 radv_update_dcc_metadata(cmd_buffer, image, &range, true);
1388 }
1389 }
1390
1391 static void
1392 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1393 struct radv_ds_buffer_info *ds,
1394 const struct radv_image_view *iview,
1395 VkImageLayout layout,
1396 bool in_render_loop, bool requires_cond_exec)
1397 {
1398 const struct radv_image *image = iview->image;
1399 uint32_t db_z_info = ds->db_z_info;
1400 uint32_t db_z_info_reg;
1401
1402 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug ||
1403 !radv_image_is_tc_compat_htile(image))
1404 return;
1405
1406 if (!radv_layout_has_htile(image, layout, in_render_loop,
1407 radv_image_queue_family_mask(image,
1408 cmd_buffer->queue_family_index,
1409 cmd_buffer->queue_family_index))) {
1410 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1411 }
1412
1413 db_z_info &= C_028040_ZRANGE_PRECISION;
1414
1415 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1416 db_z_info_reg = R_028038_DB_Z_INFO;
1417 } else {
1418 db_z_info_reg = R_028040_DB_Z_INFO;
1419 }
1420
1421 /* When we don't know the last fast clear value we need to emit a
1422 * conditional packet that will eventually skip the following
1423 * SET_CONTEXT_REG packet.
1424 */
1425 if (requires_cond_exec) {
1426 uint64_t va = radv_get_tc_compat_zrange_va(image, iview->base_mip);
1427
1428 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1429 radeon_emit(cmd_buffer->cs, va);
1430 radeon_emit(cmd_buffer->cs, va >> 32);
1431 radeon_emit(cmd_buffer->cs, 0);
1432 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1433 }
1434
1435 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1436 }
1437
1438 static void
1439 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1440 struct radv_ds_buffer_info *ds,
1441 struct radv_image_view *iview,
1442 VkImageLayout layout,
1443 bool in_render_loop)
1444 {
1445 const struct radv_image *image = iview->image;
1446 uint32_t db_z_info = ds->db_z_info;
1447 uint32_t db_stencil_info = ds->db_stencil_info;
1448
1449 if (!radv_layout_has_htile(image, layout, in_render_loop,
1450 radv_image_queue_family_mask(image,
1451 cmd_buffer->queue_family_index,
1452 cmd_buffer->queue_family_index))) {
1453 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1454 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1455 }
1456
1457 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1458 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1459
1460 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1461 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1462 radeon_set_context_reg(cmd_buffer->cs, R_02801C_DB_DEPTH_SIZE_XY, ds->db_depth_size);
1463
1464 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 7);
1465 radeon_emit(cmd_buffer->cs, S_02803C_RESOURCE_LEVEL(1));
1466 radeon_emit(cmd_buffer->cs, db_z_info);
1467 radeon_emit(cmd_buffer->cs, db_stencil_info);
1468 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1469 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1470 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1471 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1472
1473 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_READ_BASE_HI, 5);
1474 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1475 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1476 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1477 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1478 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1479 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1480 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1481 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1482 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1483 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1484
1485 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1486 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1487 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1488 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1489 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1490 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1491 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1492 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1493 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1494 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1495 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1496
1497 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1498 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1499 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1500 } else {
1501 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1502
1503 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1504 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1505 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1506 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1507 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1508 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1509 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1510 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1511 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1512 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1513
1514 }
1515
1516 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1517 radv_update_zrange_precision(cmd_buffer, ds, iview, layout,
1518 in_render_loop, true);
1519
1520 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1521 ds->pa_su_poly_offset_db_fmt_cntl);
1522 }
1523
1524 /**
1525 * Update the fast clear depth/stencil values if the image is bound as a
1526 * depth/stencil buffer.
1527 */
1528 static void
1529 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1530 const struct radv_image_view *iview,
1531 VkClearDepthStencilValue ds_clear_value,
1532 VkImageAspectFlags aspects)
1533 {
1534 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1535 const struct radv_image *image = iview->image;
1536 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1537 uint32_t att_idx;
1538
1539 if (!cmd_buffer->state.attachments || !subpass)
1540 return;
1541
1542 if (!subpass->depth_stencil_attachment)
1543 return;
1544
1545 att_idx = subpass->depth_stencil_attachment->attachment;
1546 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1547 return;
1548
1549 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1550 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1551 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1552 radeon_emit(cs, ds_clear_value.stencil);
1553 radeon_emit(cs, fui(ds_clear_value.depth));
1554 } else if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1555 radeon_set_context_reg_seq(cs, R_02802C_DB_DEPTH_CLEAR, 1);
1556 radeon_emit(cs, fui(ds_clear_value.depth));
1557 } else {
1558 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1559 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 1);
1560 radeon_emit(cs, ds_clear_value.stencil);
1561 }
1562
1563 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1564 * only needed when clearing Z to 0.0.
1565 */
1566 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1567 ds_clear_value.depth == 0.0) {
1568 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1569 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
1570
1571 radv_update_zrange_precision(cmd_buffer, &cmd_buffer->state.attachments[att_idx].ds,
1572 iview, layout, in_render_loop, false);
1573 }
1574
1575 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1576 }
1577
1578 /**
1579 * Set the clear depth/stencil values to the image's metadata.
1580 */
1581 static void
1582 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1583 struct radv_image *image,
1584 const VkImageSubresourceRange *range,
1585 VkClearDepthStencilValue ds_clear_value,
1586 VkImageAspectFlags aspects)
1587 {
1588 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1589 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel);
1590 uint32_t level_count = radv_get_levelCount(image, range);
1591
1592 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1593 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1594 /* Use the fastest way when both aspects are used. */
1595 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + 2 * level_count, cmd_buffer->state.predicating));
1596 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1597 S_370_WR_CONFIRM(1) |
1598 S_370_ENGINE_SEL(V_370_PFP));
1599 radeon_emit(cs, va);
1600 radeon_emit(cs, va >> 32);
1601
1602 for (uint32_t l = 0; l < level_count; l++) {
1603 radeon_emit(cs, ds_clear_value.stencil);
1604 radeon_emit(cs, fui(ds_clear_value.depth));
1605 }
1606 } else {
1607 /* Otherwise we need one WRITE_DATA packet per level. */
1608 for (uint32_t l = 0; l < level_count; l++) {
1609 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel + l);
1610 unsigned value;
1611
1612 if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1613 value = fui(ds_clear_value.depth);
1614 va += 4;
1615 } else {
1616 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1617 value = ds_clear_value.stencil;
1618 }
1619
1620 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1621 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1622 S_370_WR_CONFIRM(1) |
1623 S_370_ENGINE_SEL(V_370_PFP));
1624 radeon_emit(cs, va);
1625 radeon_emit(cs, va >> 32);
1626 radeon_emit(cs, value);
1627 }
1628 }
1629 }
1630
1631 /**
1632 * Update the TC-compat metadata value for this image.
1633 */
1634 static void
1635 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1636 struct radv_image *image,
1637 const VkImageSubresourceRange *range,
1638 uint32_t value)
1639 {
1640 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1641
1642 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug)
1643 return;
1644
1645 uint64_t va = radv_get_tc_compat_zrange_va(image, range->baseMipLevel);
1646 uint32_t level_count = radv_get_levelCount(image, range);
1647
1648 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + level_count, cmd_buffer->state.predicating));
1649 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1650 S_370_WR_CONFIRM(1) |
1651 S_370_ENGINE_SEL(V_370_PFP));
1652 radeon_emit(cs, va);
1653 radeon_emit(cs, va >> 32);
1654
1655 for (uint32_t l = 0; l < level_count; l++)
1656 radeon_emit(cs, value);
1657 }
1658
1659 static void
1660 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1661 const struct radv_image_view *iview,
1662 VkClearDepthStencilValue ds_clear_value)
1663 {
1664 VkImageSubresourceRange range = {
1665 .aspectMask = iview->aspect_mask,
1666 .baseMipLevel = iview->base_mip,
1667 .levelCount = iview->level_count,
1668 .baseArrayLayer = iview->base_layer,
1669 .layerCount = iview->layer_count,
1670 };
1671 uint32_t cond_val;
1672
1673 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1674 * depth clear value is 0.0f.
1675 */
1676 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1677
1678 radv_set_tc_compat_zrange_metadata(cmd_buffer, iview->image, &range,
1679 cond_val);
1680 }
1681
1682 /**
1683 * Update the clear depth/stencil values for this image.
1684 */
1685 void
1686 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1687 const struct radv_image_view *iview,
1688 VkClearDepthStencilValue ds_clear_value,
1689 VkImageAspectFlags aspects)
1690 {
1691 VkImageSubresourceRange range = {
1692 .aspectMask = iview->aspect_mask,
1693 .baseMipLevel = iview->base_mip,
1694 .levelCount = iview->level_count,
1695 .baseArrayLayer = iview->base_layer,
1696 .layerCount = iview->layer_count,
1697 };
1698 struct radv_image *image = iview->image;
1699
1700 assert(radv_image_has_htile(image));
1701
1702 radv_set_ds_clear_metadata(cmd_buffer, iview->image, &range,
1703 ds_clear_value, aspects);
1704
1705 if (radv_image_is_tc_compat_htile(image) &&
1706 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1707 radv_update_tc_compat_zrange_metadata(cmd_buffer, iview,
1708 ds_clear_value);
1709 }
1710
1711 radv_update_bound_fast_clear_ds(cmd_buffer, iview, ds_clear_value,
1712 aspects);
1713 }
1714
1715 /**
1716 * Load the clear depth/stencil values from the image's metadata.
1717 */
1718 static void
1719 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1720 const struct radv_image_view *iview)
1721 {
1722 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1723 const struct radv_image *image = iview->image;
1724 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1725 uint64_t va = radv_get_ds_clear_value_va(image, iview->base_mip);
1726 unsigned reg_offset = 0, reg_count = 0;
1727
1728 if (!radv_image_has_htile(image))
1729 return;
1730
1731 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1732 ++reg_count;
1733 } else {
1734 ++reg_offset;
1735 va += 4;
1736 }
1737 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1738 ++reg_count;
1739
1740 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1741
1742 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
1743 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1744 radeon_emit(cs, va);
1745 radeon_emit(cs, va >> 32);
1746 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1747 radeon_emit(cs, reg_count);
1748 } else {
1749 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1750 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1751 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1752 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1753 radeon_emit(cs, va);
1754 radeon_emit(cs, va >> 32);
1755 radeon_emit(cs, reg >> 2);
1756 radeon_emit(cs, 0);
1757
1758 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1759 radeon_emit(cs, 0);
1760 }
1761 }
1762
1763 /*
1764 * With DCC some colors don't require CMASK elimination before being
1765 * used as a texture. This sets a predicate value to determine if the
1766 * cmask eliminate is required.
1767 */
1768 void
1769 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1770 struct radv_image *image,
1771 const VkImageSubresourceRange *range, bool value)
1772 {
1773 uint64_t pred_val = value;
1774 uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
1775 uint32_t level_count = radv_get_levelCount(image, range);
1776 uint32_t count = 2 * level_count;
1777
1778 assert(radv_dcc_enabled(image, range->baseMipLevel));
1779
1780 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1781 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1782 S_370_WR_CONFIRM(1) |
1783 S_370_ENGINE_SEL(V_370_PFP));
1784 radeon_emit(cmd_buffer->cs, va);
1785 radeon_emit(cmd_buffer->cs, va >> 32);
1786
1787 for (uint32_t l = 0; l < level_count; l++) {
1788 radeon_emit(cmd_buffer->cs, pred_val);
1789 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1790 }
1791 }
1792
1793 /**
1794 * Update the DCC predicate to reflect the compression state.
1795 */
1796 void
1797 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1798 struct radv_image *image,
1799 const VkImageSubresourceRange *range, bool value)
1800 {
1801 uint64_t pred_val = value;
1802 uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
1803 uint32_t level_count = radv_get_levelCount(image, range);
1804 uint32_t count = 2 * level_count;
1805
1806 assert(radv_dcc_enabled(image, range->baseMipLevel));
1807
1808 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1809 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1810 S_370_WR_CONFIRM(1) |
1811 S_370_ENGINE_SEL(V_370_PFP));
1812 radeon_emit(cmd_buffer->cs, va);
1813 radeon_emit(cmd_buffer->cs, va >> 32);
1814
1815 for (uint32_t l = 0; l < level_count; l++) {
1816 radeon_emit(cmd_buffer->cs, pred_val);
1817 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1818 }
1819 }
1820
1821 /**
1822 * Update the fast clear color values if the image is bound as a color buffer.
1823 */
1824 static void
1825 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1826 struct radv_image *image,
1827 int cb_idx,
1828 uint32_t color_values[2])
1829 {
1830 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1831 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1832 uint32_t att_idx;
1833
1834 if (!cmd_buffer->state.attachments || !subpass)
1835 return;
1836
1837 att_idx = subpass->color_attachments[cb_idx].attachment;
1838 if (att_idx == VK_ATTACHMENT_UNUSED)
1839 return;
1840
1841 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1842 return;
1843
1844 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1845 radeon_emit(cs, color_values[0]);
1846 radeon_emit(cs, color_values[1]);
1847
1848 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1849 }
1850
1851 /**
1852 * Set the clear color values to the image's metadata.
1853 */
1854 static void
1855 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1856 struct radv_image *image,
1857 const VkImageSubresourceRange *range,
1858 uint32_t color_values[2])
1859 {
1860 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1861 uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
1862 uint32_t level_count = radv_get_levelCount(image, range);
1863 uint32_t count = 2 * level_count;
1864
1865 assert(radv_image_has_cmask(image) ||
1866 radv_dcc_enabled(image, range->baseMipLevel));
1867
1868 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
1869 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1870 S_370_WR_CONFIRM(1) |
1871 S_370_ENGINE_SEL(V_370_PFP));
1872 radeon_emit(cs, va);
1873 radeon_emit(cs, va >> 32);
1874
1875 for (uint32_t l = 0; l < level_count; l++) {
1876 radeon_emit(cs, color_values[0]);
1877 radeon_emit(cs, color_values[1]);
1878 }
1879 }
1880
1881 /**
1882 * Update the clear color values for this image.
1883 */
1884 void
1885 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1886 const struct radv_image_view *iview,
1887 int cb_idx,
1888 uint32_t color_values[2])
1889 {
1890 struct radv_image *image = iview->image;
1891 VkImageSubresourceRange range = {
1892 .aspectMask = iview->aspect_mask,
1893 .baseMipLevel = iview->base_mip,
1894 .levelCount = iview->level_count,
1895 .baseArrayLayer = iview->base_layer,
1896 .layerCount = iview->layer_count,
1897 };
1898
1899 assert(radv_image_has_cmask(image) ||
1900 radv_dcc_enabled(image, iview->base_mip));
1901
1902 radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
1903
1904 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1905 color_values);
1906 }
1907
1908 /**
1909 * Load the clear color values from the image's metadata.
1910 */
1911 static void
1912 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1913 struct radv_image_view *iview,
1914 int cb_idx)
1915 {
1916 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1917 struct radv_image *image = iview->image;
1918 uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
1919
1920 if (!radv_image_has_cmask(image) &&
1921 !radv_dcc_enabled(image, iview->base_mip))
1922 return;
1923
1924 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1925
1926 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
1927 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1928 radeon_emit(cs, va);
1929 radeon_emit(cs, va >> 32);
1930 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1931 radeon_emit(cs, 2);
1932 } else {
1933 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1934 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1935 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1936 COPY_DATA_COUNT_SEL);
1937 radeon_emit(cs, va);
1938 radeon_emit(cs, va >> 32);
1939 radeon_emit(cs, reg >> 2);
1940 radeon_emit(cs, 0);
1941
1942 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1943 radeon_emit(cs, 0);
1944 }
1945 }
1946
1947 static void
1948 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1949 {
1950 int i;
1951 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1952 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1953
1954 /* this may happen for inherited secondary recording */
1955 if (!framebuffer)
1956 return;
1957
1958 for (i = 0; i < 8; ++i) {
1959 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1960 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1961 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1962 continue;
1963 }
1964
1965 int idx = subpass->color_attachments[i].attachment;
1966 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
1967 VkImageLayout layout = subpass->color_attachments[i].layout;
1968 bool in_render_loop = subpass->color_attachments[i].in_render_loop;
1969
1970 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, iview->bo);
1971
1972 assert(iview->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
1973 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
1974 radv_emit_fb_color_state(cmd_buffer, i, &cmd_buffer->state.attachments[idx].cb, iview, layout, in_render_loop);
1975
1976 radv_load_color_clear_metadata(cmd_buffer, iview, i);
1977 }
1978
1979 if (subpass->depth_stencil_attachment) {
1980 int idx = subpass->depth_stencil_attachment->attachment;
1981 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1982 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
1983 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
1984 struct radv_image *image = iview->image;
1985 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, cmd_buffer->state.attachments[idx].iview->bo);
1986 ASSERTED uint32_t queue_mask = radv_image_queue_family_mask(image,
1987 cmd_buffer->queue_family_index,
1988 cmd_buffer->queue_family_index);
1989 /* We currently don't support writing decompressed HTILE */
1990 assert(radv_layout_has_htile(image, layout, in_render_loop, queue_mask) ==
1991 radv_layout_is_htile_compressed(image, layout, in_render_loop, queue_mask));
1992
1993 radv_emit_fb_ds_state(cmd_buffer, &cmd_buffer->state.attachments[idx].ds, iview, layout, in_render_loop);
1994
1995 if (cmd_buffer->state.attachments[idx].ds.offset_scale != cmd_buffer->state.offset_scale) {
1996 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1997 cmd_buffer->state.offset_scale = cmd_buffer->state.attachments[idx].ds.offset_scale;
1998 }
1999 radv_load_ds_clear_metadata(cmd_buffer, iview);
2000 } else {
2001 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9)
2002 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
2003 else
2004 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
2005
2006 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
2007 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
2008 }
2009 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2010 S_028208_BR_X(framebuffer->width) |
2011 S_028208_BR_Y(framebuffer->height));
2012
2013 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
2014 bool disable_constant_encode =
2015 cmd_buffer->device->physical_device->rad_info.has_dcc_constant_encode;
2016 enum chip_class chip_class =
2017 cmd_buffer->device->physical_device->rad_info.chip_class;
2018 uint8_t watermark = chip_class >= GFX10 ? 6 : 4;
2019
2020 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
2021 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class <= GFX9) |
2022 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
2023 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
2024 }
2025
2026 if (cmd_buffer->device->dfsm_allowed) {
2027 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2028 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
2029 }
2030
2031 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
2032 }
2033
2034 static void
2035 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
2036 {
2037 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2038 struct radv_cmd_state *state = &cmd_buffer->state;
2039
2040 if (state->index_type != state->last_index_type) {
2041 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2042 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2043 cs, R_03090C_VGT_INDEX_TYPE,
2044 2, state->index_type);
2045 } else {
2046 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2047 radeon_emit(cs, state->index_type);
2048 }
2049
2050 state->last_index_type = state->index_type;
2051 }
2052
2053 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2054 radeon_emit(cs, state->index_va);
2055 radeon_emit(cs, state->index_va >> 32);
2056
2057 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2058 radeon_emit(cs, state->max_index_count);
2059
2060 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
2061 }
2062
2063 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
2064 {
2065 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
2066 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2067 uint32_t pa_sc_mode_cntl_1 =
2068 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
2069 uint32_t db_count_control;
2070
2071 if(!cmd_buffer->state.active_occlusion_queries) {
2072 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2073 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2074 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2075 has_perfect_queries) {
2076 /* Re-enable out-of-order rasterization if the
2077 * bound pipeline supports it and if it's has
2078 * been disabled before starting any perfect
2079 * occlusion queries.
2080 */
2081 radeon_set_context_reg(cmd_buffer->cs,
2082 R_028A4C_PA_SC_MODE_CNTL_1,
2083 pa_sc_mode_cntl_1);
2084 }
2085 }
2086 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
2087 } else {
2088 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2089 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
2090 bool gfx10_perfect = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10 && has_perfect_queries;
2091
2092 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2093 db_count_control =
2094 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
2095 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
2096 S_028004_SAMPLE_RATE(sample_rate) |
2097 S_028004_ZPASS_ENABLE(1) |
2098 S_028004_SLICE_EVEN_ENABLE(1) |
2099 S_028004_SLICE_ODD_ENABLE(1);
2100
2101 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2102 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2103 has_perfect_queries) {
2104 /* If the bound pipeline has enabled
2105 * out-of-order rasterization, we should
2106 * disable it before starting any perfect
2107 * occlusion queries.
2108 */
2109 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
2110
2111 radeon_set_context_reg(cmd_buffer->cs,
2112 R_028A4C_PA_SC_MODE_CNTL_1,
2113 pa_sc_mode_cntl_1);
2114 }
2115 } else {
2116 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
2117 S_028004_SAMPLE_RATE(sample_rate);
2118 }
2119 }
2120
2121 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
2122
2123 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2124 }
2125
2126 static void
2127 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
2128 {
2129 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
2130
2131 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
2132 radv_emit_viewport(cmd_buffer);
2133
2134 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
2135 !cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
2136 radv_emit_scissor(cmd_buffer);
2137
2138 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
2139 radv_emit_line_width(cmd_buffer);
2140
2141 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
2142 radv_emit_blend_constants(cmd_buffer);
2143
2144 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
2145 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
2146 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
2147 radv_emit_stencil(cmd_buffer);
2148
2149 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
2150 radv_emit_depth_bounds(cmd_buffer);
2151
2152 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
2153 radv_emit_depth_bias(cmd_buffer);
2154
2155 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
2156 radv_emit_discard_rectangle(cmd_buffer);
2157
2158 if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)
2159 radv_emit_sample_locations(cmd_buffer);
2160
2161 cmd_buffer->state.dirty &= ~states;
2162 }
2163
2164 static void
2165 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
2166 VkPipelineBindPoint bind_point)
2167 {
2168 struct radv_descriptor_state *descriptors_state =
2169 radv_get_descriptors_state(cmd_buffer, bind_point);
2170 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
2171 unsigned bo_offset;
2172
2173 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
2174 set->mapped_ptr,
2175 &bo_offset))
2176 return;
2177
2178 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2179 set->va += bo_offset;
2180 }
2181
2182 static void
2183 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
2184 VkPipelineBindPoint bind_point)
2185 {
2186 struct radv_descriptor_state *descriptors_state =
2187 radv_get_descriptors_state(cmd_buffer, bind_point);
2188 uint32_t size = MAX_SETS * 4;
2189 uint32_t offset;
2190 void *ptr;
2191
2192 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
2193 256, &offset, &ptr))
2194 return;
2195
2196 for (unsigned i = 0; i < MAX_SETS; i++) {
2197 uint32_t *uptr = ((uint32_t *)ptr) + i;
2198 uint64_t set_va = 0;
2199 struct radv_descriptor_set *set = descriptors_state->sets[i];
2200 if (descriptors_state->valid & (1u << i))
2201 set_va = set->va;
2202 uptr[0] = set_va & 0xffffffff;
2203 }
2204
2205 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2206 va += offset;
2207
2208 if (cmd_buffer->state.pipeline) {
2209 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
2210 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2211 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2212
2213 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
2214 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
2215 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2216
2217 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
2218 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2219 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2220
2221 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2222 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
2223 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2224
2225 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2226 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
2227 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2228 }
2229
2230 if (cmd_buffer->state.compute_pipeline)
2231 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
2232 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2233 }
2234
2235 static void
2236 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
2237 VkShaderStageFlags stages)
2238 {
2239 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2240 VK_PIPELINE_BIND_POINT_COMPUTE :
2241 VK_PIPELINE_BIND_POINT_GRAPHICS;
2242 struct radv_descriptor_state *descriptors_state =
2243 radv_get_descriptors_state(cmd_buffer, bind_point);
2244 struct radv_cmd_state *state = &cmd_buffer->state;
2245 bool flush_indirect_descriptors;
2246
2247 if (!descriptors_state->dirty)
2248 return;
2249
2250 if (descriptors_state->push_dirty)
2251 radv_flush_push_descriptors(cmd_buffer, bind_point);
2252
2253 flush_indirect_descriptors =
2254 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
2255 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
2256 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
2257 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
2258
2259 if (flush_indirect_descriptors)
2260 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
2261
2262 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2263 cmd_buffer->cs,
2264 MAX_SETS * MESA_SHADER_STAGES * 4);
2265
2266 if (cmd_buffer->state.pipeline) {
2267 radv_foreach_stage(stage, stages) {
2268 if (!cmd_buffer->state.pipeline->shaders[stage])
2269 continue;
2270
2271 radv_emit_descriptor_pointers(cmd_buffer,
2272 cmd_buffer->state.pipeline,
2273 descriptors_state, stage);
2274 }
2275 }
2276
2277 if (cmd_buffer->state.compute_pipeline &&
2278 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
2279 radv_emit_descriptor_pointers(cmd_buffer,
2280 cmd_buffer->state.compute_pipeline,
2281 descriptors_state,
2282 MESA_SHADER_COMPUTE);
2283 }
2284
2285 descriptors_state->dirty = 0;
2286 descriptors_state->push_dirty = false;
2287
2288 assert(cmd_buffer->cs->cdw <= cdw_max);
2289
2290 if (unlikely(cmd_buffer->device->trace_bo))
2291 radv_save_descriptors(cmd_buffer, bind_point);
2292 }
2293
2294 static void
2295 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
2296 VkShaderStageFlags stages)
2297 {
2298 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
2299 ? cmd_buffer->state.compute_pipeline
2300 : cmd_buffer->state.pipeline;
2301 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2302 VK_PIPELINE_BIND_POINT_COMPUTE :
2303 VK_PIPELINE_BIND_POINT_GRAPHICS;
2304 struct radv_descriptor_state *descriptors_state =
2305 radv_get_descriptors_state(cmd_buffer, bind_point);
2306 struct radv_pipeline_layout *layout = pipeline->layout;
2307 struct radv_shader_variant *shader, *prev_shader;
2308 bool need_push_constants = false;
2309 unsigned offset;
2310 void *ptr;
2311 uint64_t va;
2312
2313 stages &= cmd_buffer->push_constant_stages;
2314 if (!stages ||
2315 (!layout->push_constant_size && !layout->dynamic_offset_count))
2316 return;
2317
2318 radv_foreach_stage(stage, stages) {
2319 shader = radv_get_shader(pipeline, stage);
2320 if (!shader)
2321 continue;
2322
2323 need_push_constants |= shader->info.loads_push_constants;
2324 need_push_constants |= shader->info.loads_dynamic_offsets;
2325
2326 uint8_t base = shader->info.base_inline_push_consts;
2327 uint8_t count = shader->info.num_inline_push_consts;
2328
2329 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
2330 AC_UD_INLINE_PUSH_CONSTANTS,
2331 count,
2332 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
2333 }
2334
2335 if (need_push_constants) {
2336 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
2337 16 * layout->dynamic_offset_count,
2338 256, &offset, &ptr))
2339 return;
2340
2341 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
2342 memcpy((char*)ptr + layout->push_constant_size,
2343 descriptors_state->dynamic_buffers,
2344 16 * layout->dynamic_offset_count);
2345
2346 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2347 va += offset;
2348
2349 ASSERTED unsigned cdw_max =
2350 radeon_check_space(cmd_buffer->device->ws,
2351 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
2352
2353 prev_shader = NULL;
2354 radv_foreach_stage(stage, stages) {
2355 shader = radv_get_shader(pipeline, stage);
2356
2357 /* Avoid redundantly emitting the address for merged stages. */
2358 if (shader && shader != prev_shader) {
2359 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
2360 AC_UD_PUSH_CONSTANTS, va);
2361
2362 prev_shader = shader;
2363 }
2364 }
2365 assert(cmd_buffer->cs->cdw <= cdw_max);
2366 }
2367
2368 cmd_buffer->push_constant_stages &= ~stages;
2369 }
2370
2371 static void
2372 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
2373 bool pipeline_is_dirty)
2374 {
2375 if ((pipeline_is_dirty ||
2376 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
2377 cmd_buffer->state.pipeline->num_vertex_bindings &&
2378 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.has_vertex_buffers) {
2379 unsigned vb_offset;
2380 void *vb_ptr;
2381 uint32_t i = 0;
2382 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
2383 uint64_t va;
2384
2385 /* allocate some descriptor state for vertex buffers */
2386 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2387 &vb_offset, &vb_ptr))
2388 return;
2389
2390 for (i = 0; i < count; i++) {
2391 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2392 uint32_t offset;
2393 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2394 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[i];
2395 unsigned num_records;
2396
2397 if (!buffer)
2398 continue;
2399
2400 va = radv_buffer_get_va(buffer->bo);
2401
2402 offset = cmd_buffer->vertex_bindings[i].offset;
2403 va += offset + buffer->offset;
2404
2405 num_records = buffer->size - offset;
2406 if (cmd_buffer->device->physical_device->rad_info.chip_class != GFX8 && stride)
2407 num_records /= stride;
2408
2409 desc[0] = va;
2410 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2411 desc[2] = num_records;
2412 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2413 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2414 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2415 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2416
2417 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2418 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT) |
2419 S_008F0C_OOB_SELECT(1) |
2420 S_008F0C_RESOURCE_LEVEL(1);
2421 } else {
2422 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2423 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2424 }
2425 }
2426
2427 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2428 va += vb_offset;
2429
2430 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2431 AC_UD_VS_VERTEX_BUFFERS, va);
2432
2433 cmd_buffer->state.vb_va = va;
2434 cmd_buffer->state.vb_size = count * 16;
2435 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2436 }
2437 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2438 }
2439
2440 static void
2441 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2442 {
2443 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2444 struct radv_userdata_info *loc;
2445 uint32_t base_reg;
2446
2447 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2448 if (!radv_get_shader(pipeline, stage))
2449 continue;
2450
2451 loc = radv_lookup_user_sgpr(pipeline, stage,
2452 AC_UD_STREAMOUT_BUFFERS);
2453 if (loc->sgpr_idx == -1)
2454 continue;
2455
2456 base_reg = pipeline->user_data_0[stage];
2457
2458 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2459 base_reg + loc->sgpr_idx * 4, va, false);
2460 }
2461
2462 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
2463 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2464 if (loc->sgpr_idx != -1) {
2465 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2466
2467 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2468 base_reg + loc->sgpr_idx * 4, va, false);
2469 }
2470 }
2471 }
2472
2473 static void
2474 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2475 {
2476 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2477 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2478 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2479 unsigned so_offset;
2480 void *so_ptr;
2481 uint64_t va;
2482
2483 /* Allocate some descriptor state for streamout buffers. */
2484 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2485 MAX_SO_BUFFERS * 16, 256,
2486 &so_offset, &so_ptr))
2487 return;
2488
2489 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2490 struct radv_buffer *buffer = sb[i].buffer;
2491 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2492
2493 if (!(so->enabled_mask & (1 << i)))
2494 continue;
2495
2496 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2497
2498 va += sb[i].offset;
2499
2500 /* Set the descriptor.
2501 *
2502 * On GFX8, the format must be non-INVALID, otherwise
2503 * the buffer will be considered not bound and store
2504 * instructions will be no-ops.
2505 */
2506 uint32_t size = 0xffffffff;
2507
2508 /* Compute the correct buffer size for NGG streamout
2509 * because it's used to determine the max emit per
2510 * buffer.
2511 */
2512 if (cmd_buffer->device->physical_device->use_ngg_streamout)
2513 size = buffer->size - sb[i].offset;
2514
2515 desc[0] = va;
2516 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2517 desc[2] = size;
2518 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2519 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2520 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2521 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2522
2523 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2524 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2525 S_008F0C_OOB_SELECT(3) |
2526 S_008F0C_RESOURCE_LEVEL(1);
2527 } else {
2528 desc[3] |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2529 }
2530 }
2531
2532 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2533 va += so_offset;
2534
2535 radv_emit_streamout_buffers(cmd_buffer, va);
2536 }
2537
2538 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2539 }
2540
2541 static void
2542 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2543 {
2544 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2545 radv_flush_streamout_descriptors(cmd_buffer);
2546 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2547 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2548 }
2549
2550 struct radv_draw_info {
2551 /**
2552 * Number of vertices.
2553 */
2554 uint32_t count;
2555
2556 /**
2557 * Index of the first vertex.
2558 */
2559 int32_t vertex_offset;
2560
2561 /**
2562 * First instance id.
2563 */
2564 uint32_t first_instance;
2565
2566 /**
2567 * Number of instances.
2568 */
2569 uint32_t instance_count;
2570
2571 /**
2572 * First index (indexed draws only).
2573 */
2574 uint32_t first_index;
2575
2576 /**
2577 * Whether it's an indexed draw.
2578 */
2579 bool indexed;
2580
2581 /**
2582 * Indirect draw parameters resource.
2583 */
2584 struct radv_buffer *indirect;
2585 uint64_t indirect_offset;
2586 uint32_t stride;
2587
2588 /**
2589 * Draw count parameters resource.
2590 */
2591 struct radv_buffer *count_buffer;
2592 uint64_t count_buffer_offset;
2593
2594 /**
2595 * Stream output parameters resource.
2596 */
2597 struct radv_buffer *strmout_buffer;
2598 uint64_t strmout_buffer_offset;
2599 };
2600
2601 static uint32_t
2602 radv_get_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
2603 {
2604 switch (cmd_buffer->state.index_type) {
2605 case V_028A7C_VGT_INDEX_8:
2606 return 0xffu;
2607 case V_028A7C_VGT_INDEX_16:
2608 return 0xffffu;
2609 case V_028A7C_VGT_INDEX_32:
2610 return 0xffffffffu;
2611 default:
2612 unreachable("invalid index type");
2613 }
2614 }
2615
2616 static void
2617 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
2618 bool instanced_draw, bool indirect_draw,
2619 bool count_from_stream_output,
2620 uint32_t draw_vertex_count)
2621 {
2622 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2623 struct radv_cmd_state *state = &cmd_buffer->state;
2624 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2625 unsigned ia_multi_vgt_param;
2626
2627 ia_multi_vgt_param =
2628 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
2629 indirect_draw,
2630 count_from_stream_output,
2631 draw_vertex_count);
2632
2633 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2634 if (info->chip_class == GFX9) {
2635 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2636 cs,
2637 R_030960_IA_MULTI_VGT_PARAM,
2638 4, ia_multi_vgt_param);
2639 } else if (info->chip_class >= GFX7) {
2640 radeon_set_context_reg_idx(cs,
2641 R_028AA8_IA_MULTI_VGT_PARAM,
2642 1, ia_multi_vgt_param);
2643 } else {
2644 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2645 ia_multi_vgt_param);
2646 }
2647 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2648 }
2649 }
2650
2651 static void
2652 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2653 const struct radv_draw_info *draw_info)
2654 {
2655 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2656 struct radv_cmd_state *state = &cmd_buffer->state;
2657 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2658 int32_t primitive_reset_en;
2659
2660 /* Draw state. */
2661 if (info->chip_class < GFX10) {
2662 si_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2663 draw_info->indirect,
2664 !!draw_info->strmout_buffer,
2665 draw_info->indirect ? 0 : draw_info->count);
2666 }
2667
2668 /* Primitive restart. */
2669 primitive_reset_en =
2670 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2671
2672 if (primitive_reset_en != state->last_primitive_reset_en) {
2673 state->last_primitive_reset_en = primitive_reset_en;
2674 if (info->chip_class >= GFX9) {
2675 radeon_set_uconfig_reg(cs,
2676 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2677 primitive_reset_en);
2678 } else {
2679 radeon_set_context_reg(cs,
2680 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2681 primitive_reset_en);
2682 }
2683 }
2684
2685 if (primitive_reset_en) {
2686 uint32_t primitive_reset_index =
2687 radv_get_primitive_reset_index(cmd_buffer);
2688
2689 if (primitive_reset_index != state->last_primitive_reset_index) {
2690 radeon_set_context_reg(cs,
2691 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2692 primitive_reset_index);
2693 state->last_primitive_reset_index = primitive_reset_index;
2694 }
2695 }
2696
2697 if (draw_info->strmout_buffer) {
2698 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2699
2700 va += draw_info->strmout_buffer->offset +
2701 draw_info->strmout_buffer_offset;
2702
2703 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2704 draw_info->stride);
2705
2706 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2707 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2708 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2709 COPY_DATA_WR_CONFIRM);
2710 radeon_emit(cs, va);
2711 radeon_emit(cs, va >> 32);
2712 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2713 radeon_emit(cs, 0); /* unused */
2714
2715 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2716 }
2717 }
2718
2719 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2720 VkPipelineStageFlags src_stage_mask)
2721 {
2722 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2723 VK_PIPELINE_STAGE_TRANSFER_BIT |
2724 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2725 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2726 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2727 }
2728
2729 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2730 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2731 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2732 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2733 VK_PIPELINE_STAGE_TRANSFER_BIT |
2734 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2735 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2736 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2737 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2738 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2739 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2740 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2741 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2742 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2743 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2744 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2745 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2746 }
2747 }
2748
2749 static enum radv_cmd_flush_bits
2750 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2751 VkAccessFlags src_flags,
2752 struct radv_image *image)
2753 {
2754 bool flush_CB_meta = true, flush_DB_meta = true;
2755 enum radv_cmd_flush_bits flush_bits = 0;
2756 uint32_t b;
2757
2758 if (image) {
2759 if (!radv_image_has_CB_metadata(image))
2760 flush_CB_meta = false;
2761 if (!radv_image_has_htile(image))
2762 flush_DB_meta = false;
2763 }
2764
2765 for_each_bit(b, src_flags) {
2766 switch ((VkAccessFlagBits)(1 << b)) {
2767 case VK_ACCESS_SHADER_WRITE_BIT:
2768 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2769 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2770 flush_bits |= RADV_CMD_FLAG_WB_L2;
2771 break;
2772 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2773 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2774 if (flush_CB_meta)
2775 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2776 break;
2777 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2778 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2779 if (flush_DB_meta)
2780 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2781 break;
2782 case VK_ACCESS_TRANSFER_WRITE_BIT:
2783 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2784 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2785 RADV_CMD_FLAG_INV_L2;
2786
2787 if (flush_CB_meta)
2788 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2789 if (flush_DB_meta)
2790 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2791 break;
2792 default:
2793 break;
2794 }
2795 }
2796 return flush_bits;
2797 }
2798
2799 static enum radv_cmd_flush_bits
2800 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2801 VkAccessFlags dst_flags,
2802 struct radv_image *image)
2803 {
2804 bool flush_CB_meta = true, flush_DB_meta = true;
2805 enum radv_cmd_flush_bits flush_bits = 0;
2806 bool flush_CB = true, flush_DB = true;
2807 bool image_is_coherent = false;
2808 uint32_t b;
2809
2810 if (image) {
2811 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2812 flush_CB = false;
2813 flush_DB = false;
2814 }
2815
2816 if (!radv_image_has_CB_metadata(image))
2817 flush_CB_meta = false;
2818 if (!radv_image_has_htile(image))
2819 flush_DB_meta = false;
2820
2821 /* TODO: implement shader coherent for GFX10 */
2822
2823 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
2824 if (image->info.samples == 1 &&
2825 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2826 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2827 !vk_format_is_stencil(image->vk_format)) {
2828 /* Single-sample color and single-sample depth
2829 * (not stencil) are coherent with shaders on
2830 * GFX9.
2831 */
2832 image_is_coherent = true;
2833 }
2834 }
2835 }
2836
2837 for_each_bit(b, dst_flags) {
2838 switch ((VkAccessFlagBits)(1 << b)) {
2839 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2840 case VK_ACCESS_INDEX_READ_BIT:
2841 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2842 break;
2843 case VK_ACCESS_UNIFORM_READ_BIT:
2844 flush_bits |= RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_SCACHE;
2845 break;
2846 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2847 case VK_ACCESS_TRANSFER_READ_BIT:
2848 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2849 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
2850 RADV_CMD_FLAG_INV_L2;
2851 break;
2852 case VK_ACCESS_SHADER_READ_BIT:
2853 flush_bits |= RADV_CMD_FLAG_INV_VCACHE;
2854 /* Unlike LLVM, ACO uses SMEM for SSBOs and we have to
2855 * invalidate the scalar cache. */
2856 if (cmd_buffer->device->physical_device->use_aco &&
2857 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8)
2858 flush_bits |= RADV_CMD_FLAG_INV_SCACHE;
2859
2860 if (!image_is_coherent)
2861 flush_bits |= RADV_CMD_FLAG_INV_L2;
2862 break;
2863 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2864 if (flush_CB)
2865 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2866 if (flush_CB_meta)
2867 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2868 break;
2869 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2870 if (flush_DB)
2871 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2872 if (flush_DB_meta)
2873 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2874 break;
2875 default:
2876 break;
2877 }
2878 }
2879 return flush_bits;
2880 }
2881
2882 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2883 const struct radv_subpass_barrier *barrier)
2884 {
2885 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2886 NULL);
2887 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2888 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2889 NULL);
2890 }
2891
2892 uint32_t
2893 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
2894 {
2895 struct radv_cmd_state *state = &cmd_buffer->state;
2896 uint32_t subpass_id = state->subpass - state->pass->subpasses;
2897
2898 /* The id of this subpass shouldn't exceed the number of subpasses in
2899 * this render pass minus 1.
2900 */
2901 assert(subpass_id < state->pass->subpass_count);
2902 return subpass_id;
2903 }
2904
2905 static struct radv_sample_locations_state *
2906 radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer,
2907 uint32_t att_idx,
2908 bool begin_subpass)
2909 {
2910 struct radv_cmd_state *state = &cmd_buffer->state;
2911 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
2912 struct radv_image_view *view = state->attachments[att_idx].iview;
2913
2914 if (view->image->info.samples == 1)
2915 return NULL;
2916
2917 if (state->pass->attachments[att_idx].first_subpass_idx == subpass_id) {
2918 /* Return the initial sample locations if this is the initial
2919 * layout transition of the given subpass attachemnt.
2920 */
2921 if (state->attachments[att_idx].sample_location.count > 0)
2922 return &state->attachments[att_idx].sample_location;
2923 } else {
2924 /* Otherwise return the subpass sample locations if defined. */
2925 if (state->subpass_sample_locs) {
2926 /* Because the driver sets the current subpass before
2927 * initial layout transitions, we should use the sample
2928 * locations from the previous subpass to avoid an
2929 * off-by-one problem. Otherwise, use the sample
2930 * locations for the current subpass for final layout
2931 * transitions.
2932 */
2933 if (begin_subpass)
2934 subpass_id--;
2935
2936 for (uint32_t i = 0; i < state->num_subpass_sample_locs; i++) {
2937 if (state->subpass_sample_locs[i].subpass_idx == subpass_id)
2938 return &state->subpass_sample_locs[i].sample_location;
2939 }
2940 }
2941 }
2942
2943 return NULL;
2944 }
2945
2946 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2947 struct radv_subpass_attachment att,
2948 bool begin_subpass)
2949 {
2950 unsigned idx = att.attachment;
2951 struct radv_image_view *view = cmd_buffer->state.attachments[idx].iview;
2952 struct radv_sample_locations_state *sample_locs;
2953 VkImageSubresourceRange range;
2954 range.aspectMask = view->aspect_mask;
2955 range.baseMipLevel = view->base_mip;
2956 range.levelCount = 1;
2957 range.baseArrayLayer = view->base_layer;
2958 range.layerCount = cmd_buffer->state.framebuffer->layers;
2959
2960 if (cmd_buffer->state.subpass->view_mask) {
2961 /* If the current subpass uses multiview, the driver might have
2962 * performed a fast color/depth clear to the whole image
2963 * (including all layers). To make sure the driver will
2964 * decompress the image correctly (if needed), we have to
2965 * account for the "real" number of layers. If the view mask is
2966 * sparse, this will decompress more layers than needed.
2967 */
2968 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
2969 }
2970
2971 /* Get the subpass sample locations for the given attachment, if NULL
2972 * is returned the driver will use the default HW locations.
2973 */
2974 sample_locs = radv_get_attachment_sample_locations(cmd_buffer, idx,
2975 begin_subpass);
2976
2977 radv_handle_image_transition(cmd_buffer,
2978 view->image,
2979 cmd_buffer->state.attachments[idx].current_layout,
2980 cmd_buffer->state.attachments[idx].current_in_render_loop,
2981 att.layout, att.in_render_loop,
2982 0, 0, &range, sample_locs);
2983
2984 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2985 cmd_buffer->state.attachments[idx].current_in_render_loop = att.in_render_loop;
2986
2987
2988 }
2989
2990 void
2991 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2992 const struct radv_subpass *subpass)
2993 {
2994 cmd_buffer->state.subpass = subpass;
2995
2996 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2997 }
2998
2999 static VkResult
3000 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
3001 struct radv_render_pass *pass,
3002 const VkRenderPassBeginInfo *info)
3003 {
3004 const struct VkRenderPassSampleLocationsBeginInfoEXT *sample_locs =
3005 vk_find_struct_const(info->pNext,
3006 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT);
3007 struct radv_cmd_state *state = &cmd_buffer->state;
3008
3009 if (!sample_locs) {
3010 state->subpass_sample_locs = NULL;
3011 return VK_SUCCESS;
3012 }
3013
3014 for (uint32_t i = 0; i < sample_locs->attachmentInitialSampleLocationsCount; i++) {
3015 const VkAttachmentSampleLocationsEXT *att_sample_locs =
3016 &sample_locs->pAttachmentInitialSampleLocations[i];
3017 uint32_t att_idx = att_sample_locs->attachmentIndex;
3018 struct radv_image *image = cmd_buffer->state.attachments[att_idx].iview->image;
3019
3020 assert(vk_format_is_depth_or_stencil(image->vk_format));
3021
3022 /* From the Vulkan spec 1.1.108:
3023 *
3024 * "If the image referenced by the framebuffer attachment at
3025 * index attachmentIndex was not created with
3026 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
3027 * then the values specified in sampleLocationsInfo are
3028 * ignored."
3029 */
3030 if (!(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT))
3031 continue;
3032
3033 const VkSampleLocationsInfoEXT *sample_locs_info =
3034 &att_sample_locs->sampleLocationsInfo;
3035
3036 state->attachments[att_idx].sample_location.per_pixel =
3037 sample_locs_info->sampleLocationsPerPixel;
3038 state->attachments[att_idx].sample_location.grid_size =
3039 sample_locs_info->sampleLocationGridSize;
3040 state->attachments[att_idx].sample_location.count =
3041 sample_locs_info->sampleLocationsCount;
3042 typed_memcpy(&state->attachments[att_idx].sample_location.locations[0],
3043 sample_locs_info->pSampleLocations,
3044 sample_locs_info->sampleLocationsCount);
3045 }
3046
3047 state->subpass_sample_locs = vk_alloc(&cmd_buffer->pool->alloc,
3048 sample_locs->postSubpassSampleLocationsCount *
3049 sizeof(state->subpass_sample_locs[0]),
3050 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3051 if (state->subpass_sample_locs == NULL) {
3052 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3053 return cmd_buffer->record_result;
3054 }
3055
3056 state->num_subpass_sample_locs = sample_locs->postSubpassSampleLocationsCount;
3057
3058 for (uint32_t i = 0; i < sample_locs->postSubpassSampleLocationsCount; i++) {
3059 const VkSubpassSampleLocationsEXT *subpass_sample_locs_info =
3060 &sample_locs->pPostSubpassSampleLocations[i];
3061 const VkSampleLocationsInfoEXT *sample_locs_info =
3062 &subpass_sample_locs_info->sampleLocationsInfo;
3063
3064 state->subpass_sample_locs[i].subpass_idx =
3065 subpass_sample_locs_info->subpassIndex;
3066 state->subpass_sample_locs[i].sample_location.per_pixel =
3067 sample_locs_info->sampleLocationsPerPixel;
3068 state->subpass_sample_locs[i].sample_location.grid_size =
3069 sample_locs_info->sampleLocationGridSize;
3070 state->subpass_sample_locs[i].sample_location.count =
3071 sample_locs_info->sampleLocationsCount;
3072 typed_memcpy(&state->subpass_sample_locs[i].sample_location.locations[0],
3073 sample_locs_info->pSampleLocations,
3074 sample_locs_info->sampleLocationsCount);
3075 }
3076
3077 return VK_SUCCESS;
3078 }
3079
3080 static VkResult
3081 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
3082 struct radv_render_pass *pass,
3083 const VkRenderPassBeginInfo *info)
3084 {
3085 struct radv_cmd_state *state = &cmd_buffer->state;
3086 const struct VkRenderPassAttachmentBeginInfoKHR *attachment_info = NULL;
3087
3088 if (info) {
3089 attachment_info = vk_find_struct_const(info->pNext,
3090 RENDER_PASS_ATTACHMENT_BEGIN_INFO_KHR);
3091 }
3092
3093
3094 if (pass->attachment_count == 0) {
3095 state->attachments = NULL;
3096 return VK_SUCCESS;
3097 }
3098
3099 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
3100 pass->attachment_count *
3101 sizeof(state->attachments[0]),
3102 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3103 if (state->attachments == NULL) {
3104 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3105 return cmd_buffer->record_result;
3106 }
3107
3108 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
3109 struct radv_render_pass_attachment *att = &pass->attachments[i];
3110 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
3111 VkImageAspectFlags clear_aspects = 0;
3112
3113 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
3114 /* color attachment */
3115 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3116 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
3117 }
3118 } else {
3119 /* depthstencil attachment */
3120 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
3121 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3122 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
3123 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3124 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
3125 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3126 }
3127 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3128 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3129 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3130 }
3131 }
3132
3133 state->attachments[i].pending_clear_aspects = clear_aspects;
3134 state->attachments[i].cleared_views = 0;
3135 if (clear_aspects && info) {
3136 assert(info->clearValueCount > i);
3137 state->attachments[i].clear_value = info->pClearValues[i];
3138 }
3139
3140 state->attachments[i].current_layout = att->initial_layout;
3141 state->attachments[i].sample_location.count = 0;
3142
3143 struct radv_image_view *iview;
3144 if (attachment_info && attachment_info->attachmentCount > i) {
3145 iview = radv_image_view_from_handle(attachment_info->pAttachments[i]);
3146 } else {
3147 iview = state->framebuffer->attachments[i];
3148 }
3149
3150 state->attachments[i].iview = iview;
3151 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3152 radv_initialise_ds_surface(cmd_buffer->device, &state->attachments[i].ds, iview);
3153 } else {
3154 radv_initialise_color_surface(cmd_buffer->device, &state->attachments[i].cb, iview);
3155 }
3156 }
3157
3158 return VK_SUCCESS;
3159 }
3160
3161 VkResult radv_AllocateCommandBuffers(
3162 VkDevice _device,
3163 const VkCommandBufferAllocateInfo *pAllocateInfo,
3164 VkCommandBuffer *pCommandBuffers)
3165 {
3166 RADV_FROM_HANDLE(radv_device, device, _device);
3167 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
3168
3169 VkResult result = VK_SUCCESS;
3170 uint32_t i;
3171
3172 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
3173
3174 if (!list_is_empty(&pool->free_cmd_buffers)) {
3175 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
3176
3177 list_del(&cmd_buffer->pool_link);
3178 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
3179
3180 result = radv_reset_cmd_buffer(cmd_buffer);
3181 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
3182 cmd_buffer->level = pAllocateInfo->level;
3183
3184 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
3185 } else {
3186 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
3187 &pCommandBuffers[i]);
3188 }
3189 if (result != VK_SUCCESS)
3190 break;
3191 }
3192
3193 if (result != VK_SUCCESS) {
3194 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
3195 i, pCommandBuffers);
3196
3197 /* From the Vulkan 1.0.66 spec:
3198 *
3199 * "vkAllocateCommandBuffers can be used to create multiple
3200 * command buffers. If the creation of any of those command
3201 * buffers fails, the implementation must destroy all
3202 * successfully created command buffer objects from this
3203 * command, set all entries of the pCommandBuffers array to
3204 * NULL and return the error."
3205 */
3206 memset(pCommandBuffers, 0,
3207 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
3208 }
3209
3210 return result;
3211 }
3212
3213 void radv_FreeCommandBuffers(
3214 VkDevice device,
3215 VkCommandPool commandPool,
3216 uint32_t commandBufferCount,
3217 const VkCommandBuffer *pCommandBuffers)
3218 {
3219 for (uint32_t i = 0; i < commandBufferCount; i++) {
3220 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
3221
3222 if (cmd_buffer) {
3223 if (cmd_buffer->pool) {
3224 list_del(&cmd_buffer->pool_link);
3225 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
3226 } else
3227 radv_cmd_buffer_destroy(cmd_buffer);
3228
3229 }
3230 }
3231 }
3232
3233 VkResult radv_ResetCommandBuffer(
3234 VkCommandBuffer commandBuffer,
3235 VkCommandBufferResetFlags flags)
3236 {
3237 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3238 return radv_reset_cmd_buffer(cmd_buffer);
3239 }
3240
3241 VkResult radv_BeginCommandBuffer(
3242 VkCommandBuffer commandBuffer,
3243 const VkCommandBufferBeginInfo *pBeginInfo)
3244 {
3245 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3246 VkResult result = VK_SUCCESS;
3247
3248 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
3249 /* If the command buffer has already been resetted with
3250 * vkResetCommandBuffer, no need to do it again.
3251 */
3252 result = radv_reset_cmd_buffer(cmd_buffer);
3253 if (result != VK_SUCCESS)
3254 return result;
3255 }
3256
3257 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
3258 cmd_buffer->state.last_primitive_reset_en = -1;
3259 cmd_buffer->state.last_index_type = -1;
3260 cmd_buffer->state.last_num_instances = -1;
3261 cmd_buffer->state.last_vertex_offset = -1;
3262 cmd_buffer->state.last_first_instance = -1;
3263 cmd_buffer->state.predication_type = -1;
3264 cmd_buffer->usage_flags = pBeginInfo->flags;
3265
3266 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
3267 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
3268 assert(pBeginInfo->pInheritanceInfo);
3269 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
3270 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
3271
3272 struct radv_subpass *subpass =
3273 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
3274
3275 if (cmd_buffer->state.framebuffer) {
3276 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
3277 if (result != VK_SUCCESS)
3278 return result;
3279 }
3280
3281 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3282 }
3283
3284 if (unlikely(cmd_buffer->device->trace_bo)) {
3285 struct radv_device *device = cmd_buffer->device;
3286
3287 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
3288 device->trace_bo);
3289
3290 radv_cmd_buffer_trace_emit(cmd_buffer);
3291 }
3292
3293 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
3294
3295 return result;
3296 }
3297
3298 void radv_CmdBindVertexBuffers(
3299 VkCommandBuffer commandBuffer,
3300 uint32_t firstBinding,
3301 uint32_t bindingCount,
3302 const VkBuffer* pBuffers,
3303 const VkDeviceSize* pOffsets)
3304 {
3305 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3306 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
3307 bool changed = false;
3308
3309 /* We have to defer setting up vertex buffer since we need the buffer
3310 * stride from the pipeline. */
3311
3312 assert(firstBinding + bindingCount <= MAX_VBS);
3313 for (uint32_t i = 0; i < bindingCount; i++) {
3314 uint32_t idx = firstBinding + i;
3315
3316 if (!changed &&
3317 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
3318 vb[idx].offset != pOffsets[i])) {
3319 changed = true;
3320 }
3321
3322 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
3323 vb[idx].offset = pOffsets[i];
3324
3325 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3326 vb[idx].buffer->bo);
3327 }
3328
3329 if (!changed) {
3330 /* No state changes. */
3331 return;
3332 }
3333
3334 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
3335 }
3336
3337 static uint32_t
3338 vk_to_index_type(VkIndexType type)
3339 {
3340 switch (type) {
3341 case VK_INDEX_TYPE_UINT8_EXT:
3342 return V_028A7C_VGT_INDEX_8;
3343 case VK_INDEX_TYPE_UINT16:
3344 return V_028A7C_VGT_INDEX_16;
3345 case VK_INDEX_TYPE_UINT32:
3346 return V_028A7C_VGT_INDEX_32;
3347 default:
3348 unreachable("invalid index type");
3349 }
3350 }
3351
3352 static uint32_t
3353 radv_get_vgt_index_size(uint32_t type)
3354 {
3355 switch (type) {
3356 case V_028A7C_VGT_INDEX_8:
3357 return 1;
3358 case V_028A7C_VGT_INDEX_16:
3359 return 2;
3360 case V_028A7C_VGT_INDEX_32:
3361 return 4;
3362 default:
3363 unreachable("invalid index type");
3364 }
3365 }
3366
3367 void radv_CmdBindIndexBuffer(
3368 VkCommandBuffer commandBuffer,
3369 VkBuffer buffer,
3370 VkDeviceSize offset,
3371 VkIndexType indexType)
3372 {
3373 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3374 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
3375
3376 if (cmd_buffer->state.index_buffer == index_buffer &&
3377 cmd_buffer->state.index_offset == offset &&
3378 cmd_buffer->state.index_type == indexType) {
3379 /* No state changes. */
3380 return;
3381 }
3382
3383 cmd_buffer->state.index_buffer = index_buffer;
3384 cmd_buffer->state.index_offset = offset;
3385 cmd_buffer->state.index_type = vk_to_index_type(indexType);
3386 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
3387 cmd_buffer->state.index_va += index_buffer->offset + offset;
3388
3389 int index_size = radv_get_vgt_index_size(vk_to_index_type(indexType));
3390 cmd_buffer->state.max_index_count = (index_buffer->size - offset) / index_size;
3391 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3392 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
3393 }
3394
3395
3396 static void
3397 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3398 VkPipelineBindPoint bind_point,
3399 struct radv_descriptor_set *set, unsigned idx)
3400 {
3401 struct radeon_winsys *ws = cmd_buffer->device->ws;
3402
3403 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
3404
3405 assert(set);
3406 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
3407
3408 if (!cmd_buffer->device->use_global_bo_list) {
3409 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3410 if (set->descriptors[j])
3411 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
3412 }
3413
3414 if(set->bo)
3415 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
3416 }
3417
3418 void radv_CmdBindDescriptorSets(
3419 VkCommandBuffer commandBuffer,
3420 VkPipelineBindPoint pipelineBindPoint,
3421 VkPipelineLayout _layout,
3422 uint32_t firstSet,
3423 uint32_t descriptorSetCount,
3424 const VkDescriptorSet* pDescriptorSets,
3425 uint32_t dynamicOffsetCount,
3426 const uint32_t* pDynamicOffsets)
3427 {
3428 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3429 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3430 unsigned dyn_idx = 0;
3431
3432 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
3433 struct radv_descriptor_state *descriptors_state =
3434 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3435
3436 for (unsigned i = 0; i < descriptorSetCount; ++i) {
3437 unsigned idx = i + firstSet;
3438 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
3439
3440 /* If the set is already bound we only need to update the
3441 * (potentially changed) dynamic offsets. */
3442 if (descriptors_state->sets[idx] != set ||
3443 !(descriptors_state->valid & (1u << idx))) {
3444 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
3445 }
3446
3447 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
3448 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
3449 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
3450 assert(dyn_idx < dynamicOffsetCount);
3451
3452 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
3453 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
3454 dst[0] = va;
3455 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
3456 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
3457 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3458 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3459 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3460 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3461
3462 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
3463 dst[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3464 S_008F0C_OOB_SELECT(3) |
3465 S_008F0C_RESOURCE_LEVEL(1);
3466 } else {
3467 dst[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3468 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3469 }
3470
3471 cmd_buffer->push_constant_stages |=
3472 set->layout->dynamic_shader_stages;
3473 }
3474 }
3475 }
3476
3477 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3478 struct radv_descriptor_set *set,
3479 struct radv_descriptor_set_layout *layout,
3480 VkPipelineBindPoint bind_point)
3481 {
3482 struct radv_descriptor_state *descriptors_state =
3483 radv_get_descriptors_state(cmd_buffer, bind_point);
3484 set->size = layout->size;
3485 set->layout = layout;
3486
3487 if (descriptors_state->push_set.capacity < set->size) {
3488 size_t new_size = MAX2(set->size, 1024);
3489 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
3490 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
3491
3492 free(set->mapped_ptr);
3493 set->mapped_ptr = malloc(new_size);
3494
3495 if (!set->mapped_ptr) {
3496 descriptors_state->push_set.capacity = 0;
3497 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3498 return false;
3499 }
3500
3501 descriptors_state->push_set.capacity = new_size;
3502 }
3503
3504 return true;
3505 }
3506
3507 void radv_meta_push_descriptor_set(
3508 struct radv_cmd_buffer* cmd_buffer,
3509 VkPipelineBindPoint pipelineBindPoint,
3510 VkPipelineLayout _layout,
3511 uint32_t set,
3512 uint32_t descriptorWriteCount,
3513 const VkWriteDescriptorSet* pDescriptorWrites)
3514 {
3515 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3516 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
3517 unsigned bo_offset;
3518
3519 assert(set == 0);
3520 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3521
3522 push_set->size = layout->set[set].layout->size;
3523 push_set->layout = layout->set[set].layout;
3524
3525 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
3526 &bo_offset,
3527 (void**) &push_set->mapped_ptr))
3528 return;
3529
3530 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
3531 push_set->va += bo_offset;
3532
3533 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3534 radv_descriptor_set_to_handle(push_set),
3535 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3536
3537 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3538 }
3539
3540 void radv_CmdPushDescriptorSetKHR(
3541 VkCommandBuffer commandBuffer,
3542 VkPipelineBindPoint pipelineBindPoint,
3543 VkPipelineLayout _layout,
3544 uint32_t set,
3545 uint32_t descriptorWriteCount,
3546 const VkWriteDescriptorSet* pDescriptorWrites)
3547 {
3548 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3549 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3550 struct radv_descriptor_state *descriptors_state =
3551 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3552 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3553
3554 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3555
3556 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3557 layout->set[set].layout,
3558 pipelineBindPoint))
3559 return;
3560
3561 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3562 * because it is invalid, according to Vulkan spec.
3563 */
3564 for (int i = 0; i < descriptorWriteCount; i++) {
3565 ASSERTED const VkWriteDescriptorSet *writeset = &pDescriptorWrites[i];
3566 assert(writeset->descriptorType != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT);
3567 }
3568
3569 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3570 radv_descriptor_set_to_handle(push_set),
3571 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3572
3573 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3574 descriptors_state->push_dirty = true;
3575 }
3576
3577 void radv_CmdPushDescriptorSetWithTemplateKHR(
3578 VkCommandBuffer commandBuffer,
3579 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
3580 VkPipelineLayout _layout,
3581 uint32_t set,
3582 const void* pData)
3583 {
3584 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3585 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3586 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
3587 struct radv_descriptor_state *descriptors_state =
3588 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
3589 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3590
3591 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3592
3593 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3594 layout->set[set].layout,
3595 templ->bind_point))
3596 return;
3597
3598 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
3599 descriptorUpdateTemplate, pData);
3600
3601 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
3602 descriptors_state->push_dirty = true;
3603 }
3604
3605 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
3606 VkPipelineLayout layout,
3607 VkShaderStageFlags stageFlags,
3608 uint32_t offset,
3609 uint32_t size,
3610 const void* pValues)
3611 {
3612 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3613 memcpy(cmd_buffer->push_constants + offset, pValues, size);
3614 cmd_buffer->push_constant_stages |= stageFlags;
3615 }
3616
3617 VkResult radv_EndCommandBuffer(
3618 VkCommandBuffer commandBuffer)
3619 {
3620 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3621
3622 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
3623 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6)
3624 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WB_L2;
3625
3626 /* Make sure to sync all pending active queries at the end of
3627 * command buffer.
3628 */
3629 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
3630
3631 /* Since NGG streamout uses GDS, we need to make GDS idle when
3632 * we leave the IB, otherwise another process might overwrite
3633 * it while our shaders are busy.
3634 */
3635 if (cmd_buffer->gds_needed)
3636 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
3637
3638 si_emit_cache_flush(cmd_buffer);
3639 }
3640
3641 /* Make sure CP DMA is idle at the end of IBs because the kernel
3642 * doesn't wait for it.
3643 */
3644 si_cp_dma_wait_for_idle(cmd_buffer);
3645
3646 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3647 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
3648
3649 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
3650 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3651
3652 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
3653
3654 return cmd_buffer->record_result;
3655 }
3656
3657 static void
3658 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
3659 {
3660 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3661
3662 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
3663 return;
3664
3665 assert(!pipeline->ctx_cs.cdw);
3666
3667 cmd_buffer->state.emitted_compute_pipeline = pipeline;
3668
3669 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
3670 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
3671
3672 cmd_buffer->compute_scratch_size_per_wave_needed = MAX2(cmd_buffer->compute_scratch_size_per_wave_needed,
3673 pipeline->scratch_bytes_per_wave);
3674 cmd_buffer->compute_scratch_waves_wanted = MAX2(cmd_buffer->compute_scratch_waves_wanted,
3675 pipeline->max_waves);
3676
3677 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3678 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
3679
3680 if (unlikely(cmd_buffer->device->trace_bo))
3681 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
3682 }
3683
3684 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
3685 VkPipelineBindPoint bind_point)
3686 {
3687 struct radv_descriptor_state *descriptors_state =
3688 radv_get_descriptors_state(cmd_buffer, bind_point);
3689
3690 descriptors_state->dirty |= descriptors_state->valid;
3691 }
3692
3693 void radv_CmdBindPipeline(
3694 VkCommandBuffer commandBuffer,
3695 VkPipelineBindPoint pipelineBindPoint,
3696 VkPipeline _pipeline)
3697 {
3698 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3699 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
3700
3701 switch (pipelineBindPoint) {
3702 case VK_PIPELINE_BIND_POINT_COMPUTE:
3703 if (cmd_buffer->state.compute_pipeline == pipeline)
3704 return;
3705 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3706
3707 cmd_buffer->state.compute_pipeline = pipeline;
3708 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
3709 break;
3710 case VK_PIPELINE_BIND_POINT_GRAPHICS:
3711 if (cmd_buffer->state.pipeline == pipeline)
3712 return;
3713 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3714
3715 cmd_buffer->state.pipeline = pipeline;
3716 if (!pipeline)
3717 break;
3718
3719 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
3720 cmd_buffer->push_constant_stages |= pipeline->active_stages;
3721
3722 /* the new vertex shader might not have the same user regs */
3723 cmd_buffer->state.last_first_instance = -1;
3724 cmd_buffer->state.last_vertex_offset = -1;
3725
3726 /* Prefetch all pipeline shaders at first draw time. */
3727 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
3728
3729 if ((cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI10 ||
3730 cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI12 ||
3731 cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI14) &&
3732 cmd_buffer->state.emitted_pipeline &&
3733 radv_pipeline_has_ngg(cmd_buffer->state.emitted_pipeline) &&
3734 !radv_pipeline_has_ngg(cmd_buffer->state.pipeline)) {
3735 /* Transitioning from NGG to legacy GS requires
3736 * VGT_FLUSH on Navi10-14. VGT_FLUSH is also emitted
3737 * at the beginning of IBs when legacy GS ring pointers
3738 * are set.
3739 */
3740 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
3741 }
3742
3743 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
3744 radv_bind_streamout_state(cmd_buffer, pipeline);
3745
3746 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
3747 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
3748 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
3749 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
3750
3751 if (radv_pipeline_has_tess(pipeline))
3752 cmd_buffer->tess_rings_needed = true;
3753 break;
3754 default:
3755 assert(!"invalid bind point");
3756 break;
3757 }
3758 }
3759
3760 void radv_CmdSetViewport(
3761 VkCommandBuffer commandBuffer,
3762 uint32_t firstViewport,
3763 uint32_t viewportCount,
3764 const VkViewport* pViewports)
3765 {
3766 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3767 struct radv_cmd_state *state = &cmd_buffer->state;
3768 ASSERTED const uint32_t total_count = firstViewport + viewportCount;
3769
3770 assert(firstViewport < MAX_VIEWPORTS);
3771 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
3772
3773 if (!memcmp(state->dynamic.viewport.viewports + firstViewport,
3774 pViewports, viewportCount * sizeof(*pViewports))) {
3775 return;
3776 }
3777
3778 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
3779 viewportCount * sizeof(*pViewports));
3780
3781 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
3782 }
3783
3784 void radv_CmdSetScissor(
3785 VkCommandBuffer commandBuffer,
3786 uint32_t firstScissor,
3787 uint32_t scissorCount,
3788 const VkRect2D* pScissors)
3789 {
3790 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3791 struct radv_cmd_state *state = &cmd_buffer->state;
3792 ASSERTED const uint32_t total_count = firstScissor + scissorCount;
3793
3794 assert(firstScissor < MAX_SCISSORS);
3795 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
3796
3797 if (!memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
3798 scissorCount * sizeof(*pScissors))) {
3799 return;
3800 }
3801
3802 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
3803 scissorCount * sizeof(*pScissors));
3804
3805 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
3806 }
3807
3808 void radv_CmdSetLineWidth(
3809 VkCommandBuffer commandBuffer,
3810 float lineWidth)
3811 {
3812 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3813
3814 if (cmd_buffer->state.dynamic.line_width == lineWidth)
3815 return;
3816
3817 cmd_buffer->state.dynamic.line_width = lineWidth;
3818 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
3819 }
3820
3821 void radv_CmdSetDepthBias(
3822 VkCommandBuffer commandBuffer,
3823 float depthBiasConstantFactor,
3824 float depthBiasClamp,
3825 float depthBiasSlopeFactor)
3826 {
3827 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3828 struct radv_cmd_state *state = &cmd_buffer->state;
3829
3830 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
3831 state->dynamic.depth_bias.clamp == depthBiasClamp &&
3832 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
3833 return;
3834 }
3835
3836 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
3837 state->dynamic.depth_bias.clamp = depthBiasClamp;
3838 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
3839
3840 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
3841 }
3842
3843 void radv_CmdSetBlendConstants(
3844 VkCommandBuffer commandBuffer,
3845 const float blendConstants[4])
3846 {
3847 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3848 struct radv_cmd_state *state = &cmd_buffer->state;
3849
3850 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
3851 return;
3852
3853 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
3854
3855 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
3856 }
3857
3858 void radv_CmdSetDepthBounds(
3859 VkCommandBuffer commandBuffer,
3860 float minDepthBounds,
3861 float maxDepthBounds)
3862 {
3863 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3864 struct radv_cmd_state *state = &cmd_buffer->state;
3865
3866 if (state->dynamic.depth_bounds.min == minDepthBounds &&
3867 state->dynamic.depth_bounds.max == maxDepthBounds) {
3868 return;
3869 }
3870
3871 state->dynamic.depth_bounds.min = minDepthBounds;
3872 state->dynamic.depth_bounds.max = maxDepthBounds;
3873
3874 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
3875 }
3876
3877 void radv_CmdSetStencilCompareMask(
3878 VkCommandBuffer commandBuffer,
3879 VkStencilFaceFlags faceMask,
3880 uint32_t compareMask)
3881 {
3882 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3883 struct radv_cmd_state *state = &cmd_buffer->state;
3884 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
3885 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
3886
3887 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3888 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3889 return;
3890 }
3891
3892 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3893 state->dynamic.stencil_compare_mask.front = compareMask;
3894 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3895 state->dynamic.stencil_compare_mask.back = compareMask;
3896
3897 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
3898 }
3899
3900 void radv_CmdSetStencilWriteMask(
3901 VkCommandBuffer commandBuffer,
3902 VkStencilFaceFlags faceMask,
3903 uint32_t writeMask)
3904 {
3905 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3906 struct radv_cmd_state *state = &cmd_buffer->state;
3907 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
3908 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
3909
3910 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3911 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3912 return;
3913 }
3914
3915 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3916 state->dynamic.stencil_write_mask.front = writeMask;
3917 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3918 state->dynamic.stencil_write_mask.back = writeMask;
3919
3920 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
3921 }
3922
3923 void radv_CmdSetStencilReference(
3924 VkCommandBuffer commandBuffer,
3925 VkStencilFaceFlags faceMask,
3926 uint32_t reference)
3927 {
3928 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3929 struct radv_cmd_state *state = &cmd_buffer->state;
3930 bool front_same = state->dynamic.stencil_reference.front == reference;
3931 bool back_same = state->dynamic.stencil_reference.back == reference;
3932
3933 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3934 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3935 return;
3936 }
3937
3938 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3939 cmd_buffer->state.dynamic.stencil_reference.front = reference;
3940 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3941 cmd_buffer->state.dynamic.stencil_reference.back = reference;
3942
3943 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
3944 }
3945
3946 void radv_CmdSetDiscardRectangleEXT(
3947 VkCommandBuffer commandBuffer,
3948 uint32_t firstDiscardRectangle,
3949 uint32_t discardRectangleCount,
3950 const VkRect2D* pDiscardRectangles)
3951 {
3952 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3953 struct radv_cmd_state *state = &cmd_buffer->state;
3954 ASSERTED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
3955
3956 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
3957 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
3958
3959 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
3960 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
3961 return;
3962 }
3963
3964 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
3965 pDiscardRectangles, discardRectangleCount);
3966
3967 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
3968 }
3969
3970 void radv_CmdSetSampleLocationsEXT(
3971 VkCommandBuffer commandBuffer,
3972 const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
3973 {
3974 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3975 struct radv_cmd_state *state = &cmd_buffer->state;
3976
3977 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
3978
3979 state->dynamic.sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
3980 state->dynamic.sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
3981 state->dynamic.sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
3982 typed_memcpy(&state->dynamic.sample_location.locations[0],
3983 pSampleLocationsInfo->pSampleLocations,
3984 pSampleLocationsInfo->sampleLocationsCount);
3985
3986 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS;
3987 }
3988
3989 void radv_CmdExecuteCommands(
3990 VkCommandBuffer commandBuffer,
3991 uint32_t commandBufferCount,
3992 const VkCommandBuffer* pCmdBuffers)
3993 {
3994 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
3995
3996 assert(commandBufferCount > 0);
3997
3998 /* Emit pending flushes on primary prior to executing secondary */
3999 si_emit_cache_flush(primary);
4000
4001 for (uint32_t i = 0; i < commandBufferCount; i++) {
4002 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
4003
4004 primary->scratch_size_per_wave_needed = MAX2(primary->scratch_size_per_wave_needed,
4005 secondary->scratch_size_per_wave_needed);
4006 primary->scratch_waves_wanted = MAX2(primary->scratch_waves_wanted,
4007 secondary->scratch_waves_wanted);
4008 primary->compute_scratch_size_per_wave_needed = MAX2(primary->compute_scratch_size_per_wave_needed,
4009 secondary->compute_scratch_size_per_wave_needed);
4010 primary->compute_scratch_waves_wanted = MAX2(primary->compute_scratch_waves_wanted,
4011 secondary->compute_scratch_waves_wanted);
4012
4013 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
4014 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
4015 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
4016 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
4017 if (secondary->tess_rings_needed)
4018 primary->tess_rings_needed = true;
4019 if (secondary->sample_positions_needed)
4020 primary->sample_positions_needed = true;
4021
4022 if (!secondary->state.framebuffer &&
4023 (primary->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)) {
4024 /* Emit the framebuffer state from primary if secondary
4025 * has been recorded without a framebuffer, otherwise
4026 * fast color/depth clears can't work.
4027 */
4028 radv_emit_framebuffer_state(primary);
4029 }
4030
4031 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
4032
4033
4034 /* When the secondary command buffer is compute only we don't
4035 * need to re-emit the current graphics pipeline.
4036 */
4037 if (secondary->state.emitted_pipeline) {
4038 primary->state.emitted_pipeline =
4039 secondary->state.emitted_pipeline;
4040 }
4041
4042 /* When the secondary command buffer is graphics only we don't
4043 * need to re-emit the current compute pipeline.
4044 */
4045 if (secondary->state.emitted_compute_pipeline) {
4046 primary->state.emitted_compute_pipeline =
4047 secondary->state.emitted_compute_pipeline;
4048 }
4049
4050 /* Only re-emit the draw packets when needed. */
4051 if (secondary->state.last_primitive_reset_en != -1) {
4052 primary->state.last_primitive_reset_en =
4053 secondary->state.last_primitive_reset_en;
4054 }
4055
4056 if (secondary->state.last_primitive_reset_index) {
4057 primary->state.last_primitive_reset_index =
4058 secondary->state.last_primitive_reset_index;
4059 }
4060
4061 if (secondary->state.last_ia_multi_vgt_param) {
4062 primary->state.last_ia_multi_vgt_param =
4063 secondary->state.last_ia_multi_vgt_param;
4064 }
4065
4066 primary->state.last_first_instance = secondary->state.last_first_instance;
4067 primary->state.last_num_instances = secondary->state.last_num_instances;
4068 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
4069
4070 if (secondary->state.last_index_type != -1) {
4071 primary->state.last_index_type =
4072 secondary->state.last_index_type;
4073 }
4074 }
4075
4076 /* After executing commands from secondary buffers we have to dirty
4077 * some states.
4078 */
4079 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
4080 RADV_CMD_DIRTY_INDEX_BUFFER |
4081 RADV_CMD_DIRTY_DYNAMIC_ALL;
4082 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
4083 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
4084 }
4085
4086 VkResult radv_CreateCommandPool(
4087 VkDevice _device,
4088 const VkCommandPoolCreateInfo* pCreateInfo,
4089 const VkAllocationCallbacks* pAllocator,
4090 VkCommandPool* pCmdPool)
4091 {
4092 RADV_FROM_HANDLE(radv_device, device, _device);
4093 struct radv_cmd_pool *pool;
4094
4095 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
4096 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4097 if (pool == NULL)
4098 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4099
4100 if (pAllocator)
4101 pool->alloc = *pAllocator;
4102 else
4103 pool->alloc = device->alloc;
4104
4105 list_inithead(&pool->cmd_buffers);
4106 list_inithead(&pool->free_cmd_buffers);
4107
4108 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
4109
4110 *pCmdPool = radv_cmd_pool_to_handle(pool);
4111
4112 return VK_SUCCESS;
4113
4114 }
4115
4116 void radv_DestroyCommandPool(
4117 VkDevice _device,
4118 VkCommandPool commandPool,
4119 const VkAllocationCallbacks* pAllocator)
4120 {
4121 RADV_FROM_HANDLE(radv_device, device, _device);
4122 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4123
4124 if (!pool)
4125 return;
4126
4127 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4128 &pool->cmd_buffers, pool_link) {
4129 radv_cmd_buffer_destroy(cmd_buffer);
4130 }
4131
4132 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4133 &pool->free_cmd_buffers, pool_link) {
4134 radv_cmd_buffer_destroy(cmd_buffer);
4135 }
4136
4137 vk_free2(&device->alloc, pAllocator, pool);
4138 }
4139
4140 VkResult radv_ResetCommandPool(
4141 VkDevice device,
4142 VkCommandPool commandPool,
4143 VkCommandPoolResetFlags flags)
4144 {
4145 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4146 VkResult result;
4147
4148 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
4149 &pool->cmd_buffers, pool_link) {
4150 result = radv_reset_cmd_buffer(cmd_buffer);
4151 if (result != VK_SUCCESS)
4152 return result;
4153 }
4154
4155 return VK_SUCCESS;
4156 }
4157
4158 void radv_TrimCommandPool(
4159 VkDevice device,
4160 VkCommandPool commandPool,
4161 VkCommandPoolTrimFlags flags)
4162 {
4163 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4164
4165 if (!pool)
4166 return;
4167
4168 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4169 &pool->free_cmd_buffers, pool_link) {
4170 radv_cmd_buffer_destroy(cmd_buffer);
4171 }
4172 }
4173
4174 static void
4175 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
4176 uint32_t subpass_id)
4177 {
4178 struct radv_cmd_state *state = &cmd_buffer->state;
4179 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
4180
4181 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
4182 cmd_buffer->cs, 4096);
4183
4184 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
4185
4186 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
4187
4188 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4189 const uint32_t a = subpass->attachments[i].attachment;
4190 if (a == VK_ATTACHMENT_UNUSED)
4191 continue;
4192
4193 radv_handle_subpass_image_transition(cmd_buffer,
4194 subpass->attachments[i],
4195 true);
4196 }
4197
4198 radv_cmd_buffer_clear_subpass(cmd_buffer);
4199
4200 assert(cmd_buffer->cs->cdw <= cdw_max);
4201 }
4202
4203 static void
4204 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
4205 {
4206 struct radv_cmd_state *state = &cmd_buffer->state;
4207 const struct radv_subpass *subpass = state->subpass;
4208 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
4209
4210 radv_cmd_buffer_resolve_subpass(cmd_buffer);
4211
4212 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4213 const uint32_t a = subpass->attachments[i].attachment;
4214 if (a == VK_ATTACHMENT_UNUSED)
4215 continue;
4216
4217 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
4218 continue;
4219
4220 VkImageLayout layout = state->pass->attachments[a].final_layout;
4221 struct radv_subpass_attachment att = { a, layout };
4222 radv_handle_subpass_image_transition(cmd_buffer, att, false);
4223 }
4224 }
4225
4226 void radv_CmdBeginRenderPass(
4227 VkCommandBuffer commandBuffer,
4228 const VkRenderPassBeginInfo* pRenderPassBegin,
4229 VkSubpassContents contents)
4230 {
4231 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4232 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
4233 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
4234 VkResult result;
4235
4236 cmd_buffer->state.framebuffer = framebuffer;
4237 cmd_buffer->state.pass = pass;
4238 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
4239
4240 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
4241 if (result != VK_SUCCESS)
4242 return;
4243
4244 result = radv_cmd_state_setup_sample_locations(cmd_buffer, pass, pRenderPassBegin);
4245 if (result != VK_SUCCESS)
4246 return;
4247
4248 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
4249 }
4250
4251 void radv_CmdBeginRenderPass2KHR(
4252 VkCommandBuffer commandBuffer,
4253 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
4254 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
4255 {
4256 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
4257 pSubpassBeginInfo->contents);
4258 }
4259
4260 void radv_CmdNextSubpass(
4261 VkCommandBuffer commandBuffer,
4262 VkSubpassContents contents)
4263 {
4264 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4265
4266 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
4267 radv_cmd_buffer_end_subpass(cmd_buffer);
4268 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
4269 }
4270
4271 void radv_CmdNextSubpass2KHR(
4272 VkCommandBuffer commandBuffer,
4273 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
4274 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4275 {
4276 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
4277 }
4278
4279 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
4280 {
4281 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
4282 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
4283 if (!radv_get_shader(pipeline, stage))
4284 continue;
4285
4286 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
4287 if (loc->sgpr_idx == -1)
4288 continue;
4289 uint32_t base_reg = pipeline->user_data_0[stage];
4290 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4291
4292 }
4293 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
4294 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
4295 if (loc->sgpr_idx != -1) {
4296 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
4297 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4298 }
4299 }
4300 }
4301
4302 static void
4303 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4304 uint32_t vertex_count,
4305 bool use_opaque)
4306 {
4307 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
4308 radeon_emit(cmd_buffer->cs, vertex_count);
4309 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
4310 S_0287F0_USE_OPAQUE(use_opaque));
4311 }
4312
4313 static void
4314 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
4315 uint64_t index_va,
4316 uint32_t index_count)
4317 {
4318 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
4319 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
4320 radeon_emit(cmd_buffer->cs, index_va);
4321 radeon_emit(cmd_buffer->cs, index_va >> 32);
4322 radeon_emit(cmd_buffer->cs, index_count);
4323 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
4324 }
4325
4326 static void
4327 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4328 bool indexed,
4329 uint32_t draw_count,
4330 uint64_t count_va,
4331 uint32_t stride)
4332 {
4333 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4334 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
4335 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
4336 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id;
4337 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
4338 bool predicating = cmd_buffer->state.predicating;
4339 assert(base_reg);
4340
4341 /* just reset draw state for vertex data */
4342 cmd_buffer->state.last_first_instance = -1;
4343 cmd_buffer->state.last_num_instances = -1;
4344 cmd_buffer->state.last_vertex_offset = -1;
4345
4346 if (draw_count == 1 && !count_va && !draw_id_enable) {
4347 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
4348 PKT3_DRAW_INDIRECT, 3, predicating));
4349 radeon_emit(cs, 0);
4350 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4351 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4352 radeon_emit(cs, di_src_sel);
4353 } else {
4354 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
4355 PKT3_DRAW_INDIRECT_MULTI,
4356 8, predicating));
4357 radeon_emit(cs, 0);
4358 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4359 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4360 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
4361 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
4362 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
4363 radeon_emit(cs, draw_count); /* count */
4364 radeon_emit(cs, count_va); /* count_addr */
4365 radeon_emit(cs, count_va >> 32);
4366 radeon_emit(cs, stride); /* stride */
4367 radeon_emit(cs, di_src_sel);
4368 }
4369 }
4370
4371 static void
4372 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
4373 const struct radv_draw_info *info)
4374 {
4375 struct radv_cmd_state *state = &cmd_buffer->state;
4376 struct radeon_winsys *ws = cmd_buffer->device->ws;
4377 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4378
4379 if (info->indirect) {
4380 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4381 uint64_t count_va = 0;
4382
4383 va += info->indirect->offset + info->indirect_offset;
4384
4385 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4386
4387 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
4388 radeon_emit(cs, 1);
4389 radeon_emit(cs, va);
4390 radeon_emit(cs, va >> 32);
4391
4392 if (info->count_buffer) {
4393 count_va = radv_buffer_get_va(info->count_buffer->bo);
4394 count_va += info->count_buffer->offset +
4395 info->count_buffer_offset;
4396
4397 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
4398 }
4399
4400 if (!state->subpass->view_mask) {
4401 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4402 info->indexed,
4403 info->count,
4404 count_va,
4405 info->stride);
4406 } else {
4407 unsigned i;
4408 for_each_bit(i, state->subpass->view_mask) {
4409 radv_emit_view_index(cmd_buffer, i);
4410
4411 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4412 info->indexed,
4413 info->count,
4414 count_va,
4415 info->stride);
4416 }
4417 }
4418 } else {
4419 assert(state->pipeline->graphics.vtx_base_sgpr);
4420
4421 if (info->vertex_offset != state->last_vertex_offset ||
4422 info->first_instance != state->last_first_instance) {
4423 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
4424 state->pipeline->graphics.vtx_emit_num);
4425
4426 radeon_emit(cs, info->vertex_offset);
4427 radeon_emit(cs, info->first_instance);
4428 if (state->pipeline->graphics.vtx_emit_num == 3)
4429 radeon_emit(cs, 0);
4430 state->last_first_instance = info->first_instance;
4431 state->last_vertex_offset = info->vertex_offset;
4432 }
4433
4434 if (state->last_num_instances != info->instance_count) {
4435 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
4436 radeon_emit(cs, info->instance_count);
4437 state->last_num_instances = info->instance_count;
4438 }
4439
4440 if (info->indexed) {
4441 int index_size = radv_get_vgt_index_size(state->index_type);
4442 uint64_t index_va;
4443
4444 /* Skip draw calls with 0-sized index buffers. They
4445 * cause a hang on some chips, like Navi10-14.
4446 */
4447 if (!cmd_buffer->state.max_index_count)
4448 return;
4449
4450 index_va = state->index_va;
4451 index_va += info->first_index * index_size;
4452
4453 if (!state->subpass->view_mask) {
4454 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4455 index_va,
4456 info->count);
4457 } else {
4458 unsigned i;
4459 for_each_bit(i, state->subpass->view_mask) {
4460 radv_emit_view_index(cmd_buffer, i);
4461
4462 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4463 index_va,
4464 info->count);
4465 }
4466 }
4467 } else {
4468 if (!state->subpass->view_mask) {
4469 radv_cs_emit_draw_packet(cmd_buffer,
4470 info->count,
4471 !!info->strmout_buffer);
4472 } else {
4473 unsigned i;
4474 for_each_bit(i, state->subpass->view_mask) {
4475 radv_emit_view_index(cmd_buffer, i);
4476
4477 radv_cs_emit_draw_packet(cmd_buffer,
4478 info->count,
4479 !!info->strmout_buffer);
4480 }
4481 }
4482 }
4483 }
4484 }
4485
4486 /*
4487 * Vega and raven have a bug which triggers if there are multiple context
4488 * register contexts active at the same time with different scissor values.
4489 *
4490 * There are two possible workarounds:
4491 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
4492 * there is only ever 1 active set of scissor values at the same time.
4493 *
4494 * 2) Whenever the hardware switches contexts we have to set the scissor
4495 * registers again even if it is a noop. That way the new context gets
4496 * the correct scissor values.
4497 *
4498 * This implements option 2. radv_need_late_scissor_emission needs to
4499 * return true on affected HW if radv_emit_all_graphics_states sets
4500 * any context registers.
4501 */
4502 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
4503 const struct radv_draw_info *info)
4504 {
4505 struct radv_cmd_state *state = &cmd_buffer->state;
4506
4507 if (!cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
4508 return false;
4509
4510 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
4511 return true;
4512
4513 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
4514
4515 /* Index, vertex and streamout buffers don't change context regs, and
4516 * pipeline is already handled.
4517 */
4518 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
4519 RADV_CMD_DIRTY_VERTEX_BUFFER |
4520 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
4521 RADV_CMD_DIRTY_PIPELINE);
4522
4523 if (cmd_buffer->state.dirty & used_states)
4524 return true;
4525
4526 uint32_t primitive_reset_index =
4527 radv_get_primitive_reset_index(cmd_buffer);
4528
4529 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
4530 primitive_reset_index != state->last_primitive_reset_index)
4531 return true;
4532
4533 return false;
4534 }
4535
4536 static void
4537 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
4538 const struct radv_draw_info *info)
4539 {
4540 bool late_scissor_emission;
4541
4542 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
4543 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
4544 radv_emit_rbplus_state(cmd_buffer);
4545
4546 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
4547 radv_emit_graphics_pipeline(cmd_buffer);
4548
4549 /* This should be before the cmd_buffer->state.dirty is cleared
4550 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4551 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4552 late_scissor_emission =
4553 radv_need_late_scissor_emission(cmd_buffer, info);
4554
4555 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
4556 radv_emit_framebuffer_state(cmd_buffer);
4557
4558 if (info->indexed) {
4559 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
4560 radv_emit_index_buffer(cmd_buffer);
4561 } else {
4562 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4563 * so the state must be re-emitted before the next indexed
4564 * draw.
4565 */
4566 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
4567 cmd_buffer->state.last_index_type = -1;
4568 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
4569 }
4570 }
4571
4572 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
4573
4574 radv_emit_draw_registers(cmd_buffer, info);
4575
4576 if (late_scissor_emission)
4577 radv_emit_scissor(cmd_buffer);
4578 }
4579
4580 static void
4581 radv_draw(struct radv_cmd_buffer *cmd_buffer,
4582 const struct radv_draw_info *info)
4583 {
4584 struct radeon_info *rad_info =
4585 &cmd_buffer->device->physical_device->rad_info;
4586 bool has_prefetch =
4587 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4588 bool pipeline_is_dirty =
4589 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
4590 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
4591
4592 ASSERTED unsigned cdw_max =
4593 radeon_check_space(cmd_buffer->device->ws,
4594 cmd_buffer->cs, 4096);
4595
4596 if (likely(!info->indirect)) {
4597 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4598 * no workaround for indirect draws, but we can at least skip
4599 * direct draws.
4600 */
4601 if (unlikely(!info->instance_count))
4602 return;
4603
4604 /* Handle count == 0. */
4605 if (unlikely(!info->count && !info->strmout_buffer))
4606 return;
4607 }
4608
4609 /* Use optimal packet order based on whether we need to sync the
4610 * pipeline.
4611 */
4612 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4613 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4614 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4615 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4616 /* If we have to wait for idle, set all states first, so that
4617 * all SET packets are processed in parallel with previous draw
4618 * calls. Then upload descriptors, set shader pointers, and
4619 * draw, and prefetch at the end. This ensures that the time
4620 * the CUs are idle is very short. (there are only SET_SH
4621 * packets between the wait and the draw)
4622 */
4623 radv_emit_all_graphics_states(cmd_buffer, info);
4624 si_emit_cache_flush(cmd_buffer);
4625 /* <-- CUs are idle here --> */
4626
4627 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4628
4629 radv_emit_draw_packets(cmd_buffer, info);
4630 /* <-- CUs are busy here --> */
4631
4632 /* Start prefetches after the draw has been started. Both will
4633 * run in parallel, but starting the draw first is more
4634 * important.
4635 */
4636 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4637 radv_emit_prefetch_L2(cmd_buffer,
4638 cmd_buffer->state.pipeline, false);
4639 }
4640 } else {
4641 /* If we don't wait for idle, start prefetches first, then set
4642 * states, and draw at the end.
4643 */
4644 si_emit_cache_flush(cmd_buffer);
4645
4646 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4647 /* Only prefetch the vertex shader and VBO descriptors
4648 * in order to start the draw as soon as possible.
4649 */
4650 radv_emit_prefetch_L2(cmd_buffer,
4651 cmd_buffer->state.pipeline, true);
4652 }
4653
4654 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4655
4656 radv_emit_all_graphics_states(cmd_buffer, info);
4657 radv_emit_draw_packets(cmd_buffer, info);
4658
4659 /* Prefetch the remaining shaders after the draw has been
4660 * started.
4661 */
4662 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4663 radv_emit_prefetch_L2(cmd_buffer,
4664 cmd_buffer->state.pipeline, false);
4665 }
4666 }
4667
4668 /* Workaround for a VGT hang when streamout is enabled.
4669 * It must be done after drawing.
4670 */
4671 if (cmd_buffer->state.streamout.streamout_enabled &&
4672 (rad_info->family == CHIP_HAWAII ||
4673 rad_info->family == CHIP_TONGA ||
4674 rad_info->family == CHIP_FIJI)) {
4675 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
4676 }
4677
4678 assert(cmd_buffer->cs->cdw <= cdw_max);
4679 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
4680 }
4681
4682 void radv_CmdDraw(
4683 VkCommandBuffer commandBuffer,
4684 uint32_t vertexCount,
4685 uint32_t instanceCount,
4686 uint32_t firstVertex,
4687 uint32_t firstInstance)
4688 {
4689 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4690 struct radv_draw_info info = {};
4691
4692 info.count = vertexCount;
4693 info.instance_count = instanceCount;
4694 info.first_instance = firstInstance;
4695 info.vertex_offset = firstVertex;
4696
4697 radv_draw(cmd_buffer, &info);
4698 }
4699
4700 void radv_CmdDrawIndexed(
4701 VkCommandBuffer commandBuffer,
4702 uint32_t indexCount,
4703 uint32_t instanceCount,
4704 uint32_t firstIndex,
4705 int32_t vertexOffset,
4706 uint32_t firstInstance)
4707 {
4708 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4709 struct radv_draw_info info = {};
4710
4711 info.indexed = true;
4712 info.count = indexCount;
4713 info.instance_count = instanceCount;
4714 info.first_index = firstIndex;
4715 info.vertex_offset = vertexOffset;
4716 info.first_instance = firstInstance;
4717
4718 radv_draw(cmd_buffer, &info);
4719 }
4720
4721 void radv_CmdDrawIndirect(
4722 VkCommandBuffer commandBuffer,
4723 VkBuffer _buffer,
4724 VkDeviceSize offset,
4725 uint32_t drawCount,
4726 uint32_t stride)
4727 {
4728 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4729 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4730 struct radv_draw_info info = {};
4731
4732 info.count = drawCount;
4733 info.indirect = buffer;
4734 info.indirect_offset = offset;
4735 info.stride = stride;
4736
4737 radv_draw(cmd_buffer, &info);
4738 }
4739
4740 void radv_CmdDrawIndexedIndirect(
4741 VkCommandBuffer commandBuffer,
4742 VkBuffer _buffer,
4743 VkDeviceSize offset,
4744 uint32_t drawCount,
4745 uint32_t stride)
4746 {
4747 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4748 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4749 struct radv_draw_info info = {};
4750
4751 info.indexed = true;
4752 info.count = drawCount;
4753 info.indirect = buffer;
4754 info.indirect_offset = offset;
4755 info.stride = stride;
4756
4757 radv_draw(cmd_buffer, &info);
4758 }
4759
4760 void radv_CmdDrawIndirectCountKHR(
4761 VkCommandBuffer commandBuffer,
4762 VkBuffer _buffer,
4763 VkDeviceSize offset,
4764 VkBuffer _countBuffer,
4765 VkDeviceSize countBufferOffset,
4766 uint32_t maxDrawCount,
4767 uint32_t stride)
4768 {
4769 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4770 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4771 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4772 struct radv_draw_info info = {};
4773
4774 info.count = maxDrawCount;
4775 info.indirect = buffer;
4776 info.indirect_offset = offset;
4777 info.count_buffer = count_buffer;
4778 info.count_buffer_offset = countBufferOffset;
4779 info.stride = stride;
4780
4781 radv_draw(cmd_buffer, &info);
4782 }
4783
4784 void radv_CmdDrawIndexedIndirectCountKHR(
4785 VkCommandBuffer commandBuffer,
4786 VkBuffer _buffer,
4787 VkDeviceSize offset,
4788 VkBuffer _countBuffer,
4789 VkDeviceSize countBufferOffset,
4790 uint32_t maxDrawCount,
4791 uint32_t stride)
4792 {
4793 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4794 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4795 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4796 struct radv_draw_info info = {};
4797
4798 info.indexed = true;
4799 info.count = maxDrawCount;
4800 info.indirect = buffer;
4801 info.indirect_offset = offset;
4802 info.count_buffer = count_buffer;
4803 info.count_buffer_offset = countBufferOffset;
4804 info.stride = stride;
4805
4806 radv_draw(cmd_buffer, &info);
4807 }
4808
4809 struct radv_dispatch_info {
4810 /**
4811 * Determine the layout of the grid (in block units) to be used.
4812 */
4813 uint32_t blocks[3];
4814
4815 /**
4816 * A starting offset for the grid. If unaligned is set, the offset
4817 * must still be aligned.
4818 */
4819 uint32_t offsets[3];
4820 /**
4821 * Whether it's an unaligned compute dispatch.
4822 */
4823 bool unaligned;
4824
4825 /**
4826 * Indirect compute parameters resource.
4827 */
4828 struct radv_buffer *indirect;
4829 uint64_t indirect_offset;
4830 };
4831
4832 static void
4833 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
4834 const struct radv_dispatch_info *info)
4835 {
4836 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4837 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4838 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
4839 struct radeon_winsys *ws = cmd_buffer->device->ws;
4840 bool predicating = cmd_buffer->state.predicating;
4841 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4842 struct radv_userdata_info *loc;
4843
4844 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
4845 AC_UD_CS_GRID_SIZE);
4846
4847 ASSERTED unsigned cdw_max = radeon_check_space(ws, cs, 25);
4848
4849 if (compute_shader->info.wave_size == 32) {
4850 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
4851 dispatch_initiator |= S_00B800_CS_W32_EN(1);
4852 }
4853
4854 if (info->indirect) {
4855 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4856
4857 va += info->indirect->offset + info->indirect_offset;
4858
4859 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4860
4861 if (loc->sgpr_idx != -1) {
4862 for (unsigned i = 0; i < 3; ++i) {
4863 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
4864 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
4865 COPY_DATA_DST_SEL(COPY_DATA_REG));
4866 radeon_emit(cs, (va + 4 * i));
4867 radeon_emit(cs, (va + 4 * i) >> 32);
4868 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
4869 + loc->sgpr_idx * 4) >> 2) + i);
4870 radeon_emit(cs, 0);
4871 }
4872 }
4873
4874 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
4875 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
4876 PKT3_SHADER_TYPE_S(1));
4877 radeon_emit(cs, va);
4878 radeon_emit(cs, va >> 32);
4879 radeon_emit(cs, dispatch_initiator);
4880 } else {
4881 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
4882 PKT3_SHADER_TYPE_S(1));
4883 radeon_emit(cs, 1);
4884 radeon_emit(cs, va);
4885 radeon_emit(cs, va >> 32);
4886
4887 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
4888 PKT3_SHADER_TYPE_S(1));
4889 radeon_emit(cs, 0);
4890 radeon_emit(cs, dispatch_initiator);
4891 }
4892 } else {
4893 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
4894 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
4895
4896 if (info->unaligned) {
4897 unsigned *cs_block_size = compute_shader->info.cs.block_size;
4898 unsigned remainder[3];
4899
4900 /* If aligned, these should be an entire block size,
4901 * not 0.
4902 */
4903 remainder[0] = blocks[0] + cs_block_size[0] -
4904 align_u32_npot(blocks[0], cs_block_size[0]);
4905 remainder[1] = blocks[1] + cs_block_size[1] -
4906 align_u32_npot(blocks[1], cs_block_size[1]);
4907 remainder[2] = blocks[2] + cs_block_size[2] -
4908 align_u32_npot(blocks[2], cs_block_size[2]);
4909
4910 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
4911 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
4912 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
4913
4914 for(unsigned i = 0; i < 3; ++i) {
4915 assert(offsets[i] % cs_block_size[i] == 0);
4916 offsets[i] /= cs_block_size[i];
4917 }
4918
4919 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4920 radeon_emit(cs,
4921 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
4922 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
4923 radeon_emit(cs,
4924 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
4925 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
4926 radeon_emit(cs,
4927 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
4928 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
4929
4930 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
4931 }
4932
4933 if (loc->sgpr_idx != -1) {
4934 assert(loc->num_sgprs == 3);
4935
4936 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
4937 loc->sgpr_idx * 4, 3);
4938 radeon_emit(cs, blocks[0]);
4939 radeon_emit(cs, blocks[1]);
4940 radeon_emit(cs, blocks[2]);
4941 }
4942
4943 if (offsets[0] || offsets[1] || offsets[2]) {
4944 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
4945 radeon_emit(cs, offsets[0]);
4946 radeon_emit(cs, offsets[1]);
4947 radeon_emit(cs, offsets[2]);
4948
4949 /* The blocks in the packet are not counts but end values. */
4950 for (unsigned i = 0; i < 3; ++i)
4951 blocks[i] += offsets[i];
4952 } else {
4953 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
4954 }
4955
4956 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
4957 PKT3_SHADER_TYPE_S(1));
4958 radeon_emit(cs, blocks[0]);
4959 radeon_emit(cs, blocks[1]);
4960 radeon_emit(cs, blocks[2]);
4961 radeon_emit(cs, dispatch_initiator);
4962 }
4963
4964 assert(cmd_buffer->cs->cdw <= cdw_max);
4965 }
4966
4967 static void
4968 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
4969 {
4970 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4971 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4972 }
4973
4974 static void
4975 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
4976 const struct radv_dispatch_info *info)
4977 {
4978 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4979 bool has_prefetch =
4980 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4981 bool pipeline_is_dirty = pipeline &&
4982 pipeline != cmd_buffer->state.emitted_compute_pipeline;
4983
4984 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4985 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4986 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4987 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4988 /* If we have to wait for idle, set all states first, so that
4989 * all SET packets are processed in parallel with previous draw
4990 * calls. Then upload descriptors, set shader pointers, and
4991 * dispatch, and prefetch at the end. This ensures that the
4992 * time the CUs are idle is very short. (there are only SET_SH
4993 * packets between the wait and the draw)
4994 */
4995 radv_emit_compute_pipeline(cmd_buffer);
4996 si_emit_cache_flush(cmd_buffer);
4997 /* <-- CUs are idle here --> */
4998
4999 radv_upload_compute_shader_descriptors(cmd_buffer);
5000
5001 radv_emit_dispatch_packets(cmd_buffer, info);
5002 /* <-- CUs are busy here --> */
5003
5004 /* Start prefetches after the dispatch has been started. Both
5005 * will run in parallel, but starting the dispatch first is
5006 * more important.
5007 */
5008 if (has_prefetch && pipeline_is_dirty) {
5009 radv_emit_shader_prefetch(cmd_buffer,
5010 pipeline->shaders[MESA_SHADER_COMPUTE]);
5011 }
5012 } else {
5013 /* If we don't wait for idle, start prefetches first, then set
5014 * states, and dispatch at the end.
5015 */
5016 si_emit_cache_flush(cmd_buffer);
5017
5018 if (has_prefetch && pipeline_is_dirty) {
5019 radv_emit_shader_prefetch(cmd_buffer,
5020 pipeline->shaders[MESA_SHADER_COMPUTE]);
5021 }
5022
5023 radv_upload_compute_shader_descriptors(cmd_buffer);
5024
5025 radv_emit_compute_pipeline(cmd_buffer);
5026 radv_emit_dispatch_packets(cmd_buffer, info);
5027 }
5028
5029 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
5030 }
5031
5032 void radv_CmdDispatchBase(
5033 VkCommandBuffer commandBuffer,
5034 uint32_t base_x,
5035 uint32_t base_y,
5036 uint32_t base_z,
5037 uint32_t x,
5038 uint32_t y,
5039 uint32_t z)
5040 {
5041 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5042 struct radv_dispatch_info info = {};
5043
5044 info.blocks[0] = x;
5045 info.blocks[1] = y;
5046 info.blocks[2] = z;
5047
5048 info.offsets[0] = base_x;
5049 info.offsets[1] = base_y;
5050 info.offsets[2] = base_z;
5051 radv_dispatch(cmd_buffer, &info);
5052 }
5053
5054 void radv_CmdDispatch(
5055 VkCommandBuffer commandBuffer,
5056 uint32_t x,
5057 uint32_t y,
5058 uint32_t z)
5059 {
5060 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
5061 }
5062
5063 void radv_CmdDispatchIndirect(
5064 VkCommandBuffer commandBuffer,
5065 VkBuffer _buffer,
5066 VkDeviceSize offset)
5067 {
5068 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5069 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5070 struct radv_dispatch_info info = {};
5071
5072 info.indirect = buffer;
5073 info.indirect_offset = offset;
5074
5075 radv_dispatch(cmd_buffer, &info);
5076 }
5077
5078 void radv_unaligned_dispatch(
5079 struct radv_cmd_buffer *cmd_buffer,
5080 uint32_t x,
5081 uint32_t y,
5082 uint32_t z)
5083 {
5084 struct radv_dispatch_info info = {};
5085
5086 info.blocks[0] = x;
5087 info.blocks[1] = y;
5088 info.blocks[2] = z;
5089 info.unaligned = 1;
5090
5091 radv_dispatch(cmd_buffer, &info);
5092 }
5093
5094 void radv_CmdEndRenderPass(
5095 VkCommandBuffer commandBuffer)
5096 {
5097 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5098
5099 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
5100
5101 radv_cmd_buffer_end_subpass(cmd_buffer);
5102
5103 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
5104 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
5105
5106 cmd_buffer->state.pass = NULL;
5107 cmd_buffer->state.subpass = NULL;
5108 cmd_buffer->state.attachments = NULL;
5109 cmd_buffer->state.framebuffer = NULL;
5110 cmd_buffer->state.subpass_sample_locs = NULL;
5111 }
5112
5113 void radv_CmdEndRenderPass2KHR(
5114 VkCommandBuffer commandBuffer,
5115 const VkSubpassEndInfoKHR* pSubpassEndInfo)
5116 {
5117 radv_CmdEndRenderPass(commandBuffer);
5118 }
5119
5120 /*
5121 * For HTILE we have the following interesting clear words:
5122 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
5123 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
5124 * 0xfffffff0: Clear depth to 1.0
5125 * 0x00000000: Clear depth to 0.0
5126 */
5127 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
5128 struct radv_image *image,
5129 const VkImageSubresourceRange *range,
5130 uint32_t clear_word)
5131 {
5132 assert(range->baseMipLevel == 0);
5133 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
5134 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
5135 struct radv_cmd_state *state = &cmd_buffer->state;
5136 VkClearDepthStencilValue value = {};
5137
5138 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5139 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5140
5141 state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, clear_word);
5142
5143 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5144
5145 if (vk_format_is_stencil(image->vk_format))
5146 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
5147
5148 radv_set_ds_clear_metadata(cmd_buffer, image, range, value, aspects);
5149
5150 if (radv_image_is_tc_compat_htile(image)) {
5151 /* Initialize the TC-compat metada value to 0 because by
5152 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
5153 * need have to conditionally update its value when performing
5154 * a fast depth clear.
5155 */
5156 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, range, 0);
5157 }
5158 }
5159
5160 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
5161 struct radv_image *image,
5162 VkImageLayout src_layout,
5163 bool src_render_loop,
5164 VkImageLayout dst_layout,
5165 bool dst_render_loop,
5166 unsigned src_queue_mask,
5167 unsigned dst_queue_mask,
5168 const VkImageSubresourceRange *range,
5169 struct radv_sample_locations_state *sample_locs)
5170 {
5171 if (!radv_image_has_htile(image))
5172 return;
5173
5174 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5175 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
5176
5177 if (radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop,
5178 dst_queue_mask)) {
5179 clear_value = 0;
5180 }
5181
5182 radv_initialize_htile(cmd_buffer, image, range, clear_value);
5183 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5184 radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5185 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
5186 radv_initialize_htile(cmd_buffer, image, range, clear_value);
5187 } else if (radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5188 !radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5189 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5190 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5191
5192 radv_decompress_depth_image_inplace(cmd_buffer, image, range,
5193 sample_locs);
5194
5195 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5196 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5197 }
5198 }
5199
5200 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
5201 struct radv_image *image,
5202 const VkImageSubresourceRange *range,
5203 uint32_t value)
5204 {
5205 struct radv_cmd_state *state = &cmd_buffer->state;
5206
5207 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5208 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5209
5210 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, range, value);
5211
5212 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5213 }
5214
5215 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
5216 struct radv_image *image,
5217 const VkImageSubresourceRange *range)
5218 {
5219 struct radv_cmd_state *state = &cmd_buffer->state;
5220 static const uint32_t fmask_clear_values[4] = {
5221 0x00000000,
5222 0x02020202,
5223 0xE4E4E4E4,
5224 0x76543210
5225 };
5226 uint32_t log2_samples = util_logbase2(image->info.samples);
5227 uint32_t value = fmask_clear_values[log2_samples];
5228
5229 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5230 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5231
5232 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, range, value);
5233
5234 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5235 }
5236
5237 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
5238 struct radv_image *image,
5239 const VkImageSubresourceRange *range, uint32_t value)
5240 {
5241 struct radv_cmd_state *state = &cmd_buffer->state;
5242 unsigned size = 0;
5243
5244 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5245 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5246
5247 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
5248
5249 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) {
5250 /* When DCC is enabled with mipmaps, some levels might not
5251 * support fast clears and we have to initialize them as "fully
5252 * expanded".
5253 */
5254 /* Compute the size of all fast clearable DCC levels. */
5255 for (unsigned i = 0; i < image->planes[0].surface.num_dcc_levels; i++) {
5256 struct legacy_surf_level *surf_level =
5257 &image->planes[0].surface.u.legacy.level[i];
5258 unsigned dcc_fast_clear_size =
5259 surf_level->dcc_slice_fast_clear_size * image->info.array_size;
5260
5261 if (!dcc_fast_clear_size)
5262 break;
5263
5264 size = surf_level->dcc_offset + dcc_fast_clear_size;
5265 }
5266
5267 /* Initialize the mipmap levels without DCC. */
5268 if (size != image->planes[0].surface.dcc_size) {
5269 state->flush_bits |=
5270 radv_fill_buffer(cmd_buffer, image->bo,
5271 image->offset + image->dcc_offset + size,
5272 image->planes[0].surface.dcc_size - size,
5273 0xffffffff);
5274 }
5275 }
5276
5277 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5278 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5279 }
5280
5281 /**
5282 * Initialize DCC/FMASK/CMASK metadata for a color image.
5283 */
5284 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
5285 struct radv_image *image,
5286 VkImageLayout src_layout,
5287 bool src_render_loop,
5288 VkImageLayout dst_layout,
5289 bool dst_render_loop,
5290 unsigned src_queue_mask,
5291 unsigned dst_queue_mask,
5292 const VkImageSubresourceRange *range)
5293 {
5294 if (radv_image_has_cmask(image)) {
5295 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5296
5297 /* TODO: clarify this. */
5298 if (radv_image_has_fmask(image)) {
5299 value = 0xccccccccu;
5300 }
5301
5302 radv_initialise_cmask(cmd_buffer, image, range, value);
5303 }
5304
5305 if (radv_image_has_fmask(image)) {
5306 radv_initialize_fmask(cmd_buffer, image, range);
5307 }
5308
5309 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5310 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5311 bool need_decompress_pass = false;
5312
5313 if (radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout,
5314 dst_render_loop,
5315 dst_queue_mask)) {
5316 value = 0x20202020u;
5317 need_decompress_pass = true;
5318 }
5319
5320 radv_initialize_dcc(cmd_buffer, image, range, value);
5321
5322 radv_update_fce_metadata(cmd_buffer, image, range,
5323 need_decompress_pass);
5324 }
5325
5326 if (radv_image_has_cmask(image) ||
5327 radv_dcc_enabled(image, range->baseMipLevel)) {
5328 uint32_t color_values[2] = {};
5329 radv_set_color_clear_metadata(cmd_buffer, image, range,
5330 color_values);
5331 }
5332 }
5333
5334 /**
5335 * Handle color image transitions for DCC/FMASK/CMASK.
5336 */
5337 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
5338 struct radv_image *image,
5339 VkImageLayout src_layout,
5340 bool src_render_loop,
5341 VkImageLayout dst_layout,
5342 bool dst_render_loop,
5343 unsigned src_queue_mask,
5344 unsigned dst_queue_mask,
5345 const VkImageSubresourceRange *range)
5346 {
5347 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5348 radv_init_color_image_metadata(cmd_buffer, image,
5349 src_layout, src_render_loop,
5350 dst_layout, dst_render_loop,
5351 src_queue_mask, dst_queue_mask,
5352 range);
5353 return;
5354 }
5355
5356 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5357 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
5358 radv_initialize_dcc(cmd_buffer, image, range, 0xffffffffu);
5359 } else if (radv_layout_dcc_compressed(cmd_buffer->device, image, src_layout, src_render_loop, src_queue_mask) &&
5360 !radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout, dst_render_loop, dst_queue_mask)) {
5361 radv_decompress_dcc(cmd_buffer, image, range);
5362 } else if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
5363 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5364 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5365 }
5366 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
5367 bool fce_eliminate = false, fmask_expand = false;
5368
5369 if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
5370 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5371 fce_eliminate = true;
5372 }
5373
5374 if (radv_image_has_fmask(image)) {
5375 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
5376 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
5377 /* A FMASK decompress is required before doing
5378 * a MSAA decompress using FMASK.
5379 */
5380 fmask_expand = true;
5381 }
5382 }
5383
5384 if (fce_eliminate || fmask_expand)
5385 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5386
5387 if (fmask_expand)
5388 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
5389 }
5390 }
5391
5392 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
5393 struct radv_image *image,
5394 VkImageLayout src_layout,
5395 bool src_render_loop,
5396 VkImageLayout dst_layout,
5397 bool dst_render_loop,
5398 uint32_t src_family,
5399 uint32_t dst_family,
5400 const VkImageSubresourceRange *range,
5401 struct radv_sample_locations_state *sample_locs)
5402 {
5403 if (image->exclusive && src_family != dst_family) {
5404 /* This is an acquire or a release operation and there will be
5405 * a corresponding release/acquire. Do the transition in the
5406 * most flexible queue. */
5407
5408 assert(src_family == cmd_buffer->queue_family_index ||
5409 dst_family == cmd_buffer->queue_family_index);
5410
5411 if (src_family == VK_QUEUE_FAMILY_EXTERNAL ||
5412 src_family == VK_QUEUE_FAMILY_FOREIGN_EXT)
5413 return;
5414
5415 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
5416 return;
5417
5418 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
5419 (src_family == RADV_QUEUE_GENERAL ||
5420 dst_family == RADV_QUEUE_GENERAL))
5421 return;
5422 }
5423
5424 if (src_layout == dst_layout)
5425 return;
5426
5427 unsigned src_queue_mask =
5428 radv_image_queue_family_mask(image, src_family,
5429 cmd_buffer->queue_family_index);
5430 unsigned dst_queue_mask =
5431 radv_image_queue_family_mask(image, dst_family,
5432 cmd_buffer->queue_family_index);
5433
5434 if (vk_format_is_depth(image->vk_format)) {
5435 radv_handle_depth_image_transition(cmd_buffer, image,
5436 src_layout, src_render_loop,
5437 dst_layout, dst_render_loop,
5438 src_queue_mask, dst_queue_mask,
5439 range, sample_locs);
5440 } else {
5441 radv_handle_color_image_transition(cmd_buffer, image,
5442 src_layout, src_render_loop,
5443 dst_layout, dst_render_loop,
5444 src_queue_mask, dst_queue_mask,
5445 range);
5446 }
5447 }
5448
5449 struct radv_barrier_info {
5450 uint32_t eventCount;
5451 const VkEvent *pEvents;
5452 VkPipelineStageFlags srcStageMask;
5453 VkPipelineStageFlags dstStageMask;
5454 };
5455
5456 static void
5457 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
5458 uint32_t memoryBarrierCount,
5459 const VkMemoryBarrier *pMemoryBarriers,
5460 uint32_t bufferMemoryBarrierCount,
5461 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
5462 uint32_t imageMemoryBarrierCount,
5463 const VkImageMemoryBarrier *pImageMemoryBarriers,
5464 const struct radv_barrier_info *info)
5465 {
5466 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5467 enum radv_cmd_flush_bits src_flush_bits = 0;
5468 enum radv_cmd_flush_bits dst_flush_bits = 0;
5469
5470 for (unsigned i = 0; i < info->eventCount; ++i) {
5471 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
5472 uint64_t va = radv_buffer_get_va(event->bo);
5473
5474 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5475
5476 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
5477
5478 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
5479 assert(cmd_buffer->cs->cdw <= cdw_max);
5480 }
5481
5482 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
5483 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
5484 NULL);
5485 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
5486 NULL);
5487 }
5488
5489 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
5490 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
5491 NULL);
5492 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
5493 NULL);
5494 }
5495
5496 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5497 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5498
5499 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
5500 image);
5501 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
5502 image);
5503 }
5504
5505 /* The Vulkan spec 1.1.98 says:
5506 *
5507 * "An execution dependency with only
5508 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
5509 * will only prevent that stage from executing in subsequently
5510 * submitted commands. As this stage does not perform any actual
5511 * execution, this is not observable - in effect, it does not delay
5512 * processing of subsequent commands. Similarly an execution dependency
5513 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
5514 * will effectively not wait for any prior commands to complete."
5515 */
5516 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
5517 radv_stage_flush(cmd_buffer, info->srcStageMask);
5518 cmd_buffer->state.flush_bits |= src_flush_bits;
5519
5520 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5521 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5522
5523 const struct VkSampleLocationsInfoEXT *sample_locs_info =
5524 vk_find_struct_const(pImageMemoryBarriers[i].pNext,
5525 SAMPLE_LOCATIONS_INFO_EXT);
5526 struct radv_sample_locations_state sample_locations = {};
5527
5528 if (sample_locs_info) {
5529 assert(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
5530 sample_locations.per_pixel = sample_locs_info->sampleLocationsPerPixel;
5531 sample_locations.grid_size = sample_locs_info->sampleLocationGridSize;
5532 sample_locations.count = sample_locs_info->sampleLocationsCount;
5533 typed_memcpy(&sample_locations.locations[0],
5534 sample_locs_info->pSampleLocations,
5535 sample_locs_info->sampleLocationsCount);
5536 }
5537
5538 radv_handle_image_transition(cmd_buffer, image,
5539 pImageMemoryBarriers[i].oldLayout,
5540 false, /* Outside of a renderpass we are never in a renderloop */
5541 pImageMemoryBarriers[i].newLayout,
5542 false, /* Outside of a renderpass we are never in a renderloop */
5543 pImageMemoryBarriers[i].srcQueueFamilyIndex,
5544 pImageMemoryBarriers[i].dstQueueFamilyIndex,
5545 &pImageMemoryBarriers[i].subresourceRange,
5546 sample_locs_info ? &sample_locations : NULL);
5547 }
5548
5549 /* Make sure CP DMA is idle because the driver might have performed a
5550 * DMA operation for copying or filling buffers/images.
5551 */
5552 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5553 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5554 si_cp_dma_wait_for_idle(cmd_buffer);
5555
5556 cmd_buffer->state.flush_bits |= dst_flush_bits;
5557 }
5558
5559 void radv_CmdPipelineBarrier(
5560 VkCommandBuffer commandBuffer,
5561 VkPipelineStageFlags srcStageMask,
5562 VkPipelineStageFlags destStageMask,
5563 VkBool32 byRegion,
5564 uint32_t memoryBarrierCount,
5565 const VkMemoryBarrier* pMemoryBarriers,
5566 uint32_t bufferMemoryBarrierCount,
5567 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5568 uint32_t imageMemoryBarrierCount,
5569 const VkImageMemoryBarrier* pImageMemoryBarriers)
5570 {
5571 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5572 struct radv_barrier_info info;
5573
5574 info.eventCount = 0;
5575 info.pEvents = NULL;
5576 info.srcStageMask = srcStageMask;
5577 info.dstStageMask = destStageMask;
5578
5579 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5580 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5581 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5582 }
5583
5584
5585 static void write_event(struct radv_cmd_buffer *cmd_buffer,
5586 struct radv_event *event,
5587 VkPipelineStageFlags stageMask,
5588 unsigned value)
5589 {
5590 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5591 uint64_t va = radv_buffer_get_va(event->bo);
5592
5593 si_emit_cache_flush(cmd_buffer);
5594
5595 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5596
5597 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 21);
5598
5599 /* Flags that only require a top-of-pipe event. */
5600 VkPipelineStageFlags top_of_pipe_flags =
5601 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
5602
5603 /* Flags that only require a post-index-fetch event. */
5604 VkPipelineStageFlags post_index_fetch_flags =
5605 top_of_pipe_flags |
5606 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
5607 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
5608
5609 /* Make sure CP DMA is idle because the driver might have performed a
5610 * DMA operation for copying or filling buffers/images.
5611 */
5612 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5613 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5614 si_cp_dma_wait_for_idle(cmd_buffer);
5615
5616 /* TODO: Emit EOS events for syncing PS/CS stages. */
5617
5618 if (!(stageMask & ~top_of_pipe_flags)) {
5619 /* Just need to sync the PFP engine. */
5620 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5621 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5622 S_370_WR_CONFIRM(1) |
5623 S_370_ENGINE_SEL(V_370_PFP));
5624 radeon_emit(cs, va);
5625 radeon_emit(cs, va >> 32);
5626 radeon_emit(cs, value);
5627 } else if (!(stageMask & ~post_index_fetch_flags)) {
5628 /* Sync ME because PFP reads index and indirect buffers. */
5629 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5630 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5631 S_370_WR_CONFIRM(1) |
5632 S_370_ENGINE_SEL(V_370_ME));
5633 radeon_emit(cs, va);
5634 radeon_emit(cs, va >> 32);
5635 radeon_emit(cs, value);
5636 } else {
5637 /* Otherwise, sync all prior GPU work using an EOP event. */
5638 si_cs_emit_write_event_eop(cs,
5639 cmd_buffer->device->physical_device->rad_info.chip_class,
5640 radv_cmd_buffer_uses_mec(cmd_buffer),
5641 V_028A90_BOTTOM_OF_PIPE_TS, 0,
5642 EOP_DST_SEL_MEM,
5643 EOP_DATA_SEL_VALUE_32BIT, va, value,
5644 cmd_buffer->gfx9_eop_bug_va);
5645 }
5646
5647 assert(cmd_buffer->cs->cdw <= cdw_max);
5648 }
5649
5650 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
5651 VkEvent _event,
5652 VkPipelineStageFlags stageMask)
5653 {
5654 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5655 RADV_FROM_HANDLE(radv_event, event, _event);
5656
5657 write_event(cmd_buffer, event, stageMask, 1);
5658 }
5659
5660 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
5661 VkEvent _event,
5662 VkPipelineStageFlags stageMask)
5663 {
5664 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5665 RADV_FROM_HANDLE(radv_event, event, _event);
5666
5667 write_event(cmd_buffer, event, stageMask, 0);
5668 }
5669
5670 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
5671 uint32_t eventCount,
5672 const VkEvent* pEvents,
5673 VkPipelineStageFlags srcStageMask,
5674 VkPipelineStageFlags dstStageMask,
5675 uint32_t memoryBarrierCount,
5676 const VkMemoryBarrier* pMemoryBarriers,
5677 uint32_t bufferMemoryBarrierCount,
5678 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5679 uint32_t imageMemoryBarrierCount,
5680 const VkImageMemoryBarrier* pImageMemoryBarriers)
5681 {
5682 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5683 struct radv_barrier_info info;
5684
5685 info.eventCount = eventCount;
5686 info.pEvents = pEvents;
5687 info.srcStageMask = 0;
5688
5689 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5690 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5691 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5692 }
5693
5694
5695 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
5696 uint32_t deviceMask)
5697 {
5698 /* No-op */
5699 }
5700
5701 /* VK_EXT_conditional_rendering */
5702 void radv_CmdBeginConditionalRenderingEXT(
5703 VkCommandBuffer commandBuffer,
5704 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
5705 {
5706 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5707 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
5708 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5709 bool draw_visible = true;
5710 uint64_t pred_value = 0;
5711 uint64_t va, new_va;
5712 unsigned pred_offset;
5713
5714 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
5715
5716 /* By default, if the 32-bit value at offset in buffer memory is zero,
5717 * then the rendering commands are discarded, otherwise they are
5718 * executed as normal. If the inverted flag is set, all commands are
5719 * discarded if the value is non zero.
5720 */
5721 if (pConditionalRenderingBegin->flags &
5722 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
5723 draw_visible = false;
5724 }
5725
5726 si_emit_cache_flush(cmd_buffer);
5727
5728 /* From the Vulkan spec 1.1.107:
5729 *
5730 * "If the 32-bit value at offset in buffer memory is zero, then the
5731 * rendering commands are discarded, otherwise they are executed as
5732 * normal. If the value of the predicate in buffer memory changes while
5733 * conditional rendering is active, the rendering commands may be
5734 * discarded in an implementation-dependent way. Some implementations
5735 * may latch the value of the predicate upon beginning conditional
5736 * rendering while others may read it before every rendering command."
5737 *
5738 * But, the AMD hardware treats the predicate as a 64-bit value which
5739 * means we need a workaround in the driver. Luckily, it's not required
5740 * to support if the value changes when predication is active.
5741 *
5742 * The workaround is as follows:
5743 * 1) allocate a 64-value in the upload BO and initialize it to 0
5744 * 2) copy the 32-bit predicate value to the upload BO
5745 * 3) use the new allocated VA address for predication
5746 *
5747 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
5748 * in ME (+ sync PFP) instead of PFP.
5749 */
5750 radv_cmd_buffer_upload_data(cmd_buffer, 8, 16, &pred_value, &pred_offset);
5751
5752 new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
5753
5754 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5755 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5756 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
5757 COPY_DATA_WR_CONFIRM);
5758 radeon_emit(cs, va);
5759 radeon_emit(cs, va >> 32);
5760 radeon_emit(cs, new_va);
5761 radeon_emit(cs, new_va >> 32);
5762
5763 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
5764 radeon_emit(cs, 0);
5765
5766 /* Enable predication for this command buffer. */
5767 si_emit_set_predication_state(cmd_buffer, draw_visible, new_va);
5768 cmd_buffer->state.predicating = true;
5769
5770 /* Store conditional rendering user info. */
5771 cmd_buffer->state.predication_type = draw_visible;
5772 cmd_buffer->state.predication_va = new_va;
5773 }
5774
5775 void radv_CmdEndConditionalRenderingEXT(
5776 VkCommandBuffer commandBuffer)
5777 {
5778 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5779
5780 /* Disable predication for this command buffer. */
5781 si_emit_set_predication_state(cmd_buffer, false, 0);
5782 cmd_buffer->state.predicating = false;
5783
5784 /* Reset conditional rendering user info. */
5785 cmd_buffer->state.predication_type = -1;
5786 cmd_buffer->state.predication_va = 0;
5787 }
5788
5789 /* VK_EXT_transform_feedback */
5790 void radv_CmdBindTransformFeedbackBuffersEXT(
5791 VkCommandBuffer commandBuffer,
5792 uint32_t firstBinding,
5793 uint32_t bindingCount,
5794 const VkBuffer* pBuffers,
5795 const VkDeviceSize* pOffsets,
5796 const VkDeviceSize* pSizes)
5797 {
5798 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5799 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5800 uint8_t enabled_mask = 0;
5801
5802 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
5803 for (uint32_t i = 0; i < bindingCount; i++) {
5804 uint32_t idx = firstBinding + i;
5805
5806 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
5807 sb[idx].offset = pOffsets[i];
5808 sb[idx].size = pSizes[i];
5809
5810 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
5811 sb[idx].buffer->bo);
5812
5813 enabled_mask |= 1 << idx;
5814 }
5815
5816 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
5817
5818 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
5819 }
5820
5821 static void
5822 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
5823 {
5824 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5825 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5826
5827 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
5828 radeon_emit(cs,
5829 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
5830 S_028B94_RAST_STREAM(0) |
5831 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
5832 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
5833 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
5834 radeon_emit(cs, so->hw_enabled_mask &
5835 so->enabled_stream_buffers_mask);
5836
5837 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5838 }
5839
5840 static void
5841 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
5842 {
5843 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5844 bool old_streamout_enabled = so->streamout_enabled;
5845 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
5846
5847 so->streamout_enabled = enable;
5848
5849 so->hw_enabled_mask = so->enabled_mask |
5850 (so->enabled_mask << 4) |
5851 (so->enabled_mask << 8) |
5852 (so->enabled_mask << 12);
5853
5854 if (!cmd_buffer->device->physical_device->use_ngg_streamout &&
5855 ((old_streamout_enabled != so->streamout_enabled) ||
5856 (old_hw_enabled_mask != so->hw_enabled_mask)))
5857 radv_emit_streamout_enable(cmd_buffer);
5858
5859 if (cmd_buffer->device->physical_device->use_ngg_streamout)
5860 cmd_buffer->gds_needed = true;
5861 }
5862
5863 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
5864 {
5865 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5866 unsigned reg_strmout_cntl;
5867
5868 /* The register is at different places on different ASICs. */
5869 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
5870 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
5871 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
5872 } else {
5873 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
5874 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
5875 }
5876
5877 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
5878 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
5879
5880 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
5881 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
5882 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
5883 radeon_emit(cs, 0);
5884 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
5885 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
5886 radeon_emit(cs, 4); /* poll interval */
5887 }
5888
5889 static void
5890 radv_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
5891 uint32_t firstCounterBuffer,
5892 uint32_t counterBufferCount,
5893 const VkBuffer *pCounterBuffers,
5894 const VkDeviceSize *pCounterBufferOffsets)
5895
5896 {
5897 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5898 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5899 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5900 uint32_t i;
5901
5902 radv_flush_vgt_streamout(cmd_buffer);
5903
5904 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5905 for_each_bit(i, so->enabled_mask) {
5906 int32_t counter_buffer_idx = i - firstCounterBuffer;
5907 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5908 counter_buffer_idx = -1;
5909
5910 /* AMD GCN binds streamout buffers as shader resources.
5911 * VGT only counts primitives and tells the shader through
5912 * SGPRs what to do.
5913 */
5914 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
5915 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
5916 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
5917
5918 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5919
5920 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5921 /* The array of counter buffers is optional. */
5922 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5923 uint64_t va = radv_buffer_get_va(buffer->bo);
5924
5925 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5926
5927 /* Append */
5928 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5929 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5930 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5931 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
5932 radeon_emit(cs, 0); /* unused */
5933 radeon_emit(cs, 0); /* unused */
5934 radeon_emit(cs, va); /* src address lo */
5935 radeon_emit(cs, va >> 32); /* src address hi */
5936
5937 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5938 } else {
5939 /* Start from the beginning. */
5940 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5941 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5942 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5943 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
5944 radeon_emit(cs, 0); /* unused */
5945 radeon_emit(cs, 0); /* unused */
5946 radeon_emit(cs, 0); /* unused */
5947 radeon_emit(cs, 0); /* unused */
5948 }
5949 }
5950
5951 radv_set_streamout_enable(cmd_buffer, true);
5952 }
5953
5954 static void
5955 gfx10_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
5956 uint32_t firstCounterBuffer,
5957 uint32_t counterBufferCount,
5958 const VkBuffer *pCounterBuffers,
5959 const VkDeviceSize *pCounterBufferOffsets)
5960 {
5961 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5962 unsigned last_target = util_last_bit(so->enabled_mask) - 1;
5963 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5964 uint32_t i;
5965
5966 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
5967 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5968
5969 /* Sync because the next streamout operation will overwrite GDS and we
5970 * have to make sure it's idle.
5971 * TODO: Improve by tracking if there is a streamout operation in
5972 * flight.
5973 */
5974 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
5975 si_emit_cache_flush(cmd_buffer);
5976
5977 for_each_bit(i, so->enabled_mask) {
5978 int32_t counter_buffer_idx = i - firstCounterBuffer;
5979 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5980 counter_buffer_idx = -1;
5981
5982 bool append = counter_buffer_idx >= 0 &&
5983 pCounterBuffers && pCounterBuffers[counter_buffer_idx];
5984 uint64_t va = 0;
5985
5986 if (append) {
5987 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5988
5989 va += radv_buffer_get_va(buffer->bo);
5990 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5991
5992 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5993 }
5994
5995 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
5996 radeon_emit(cs, S_411_SRC_SEL(append ? V_411_SRC_ADDR_TC_L2 : V_411_DATA) |
5997 S_411_DST_SEL(V_411_GDS) |
5998 S_411_CP_SYNC(i == last_target));
5999 radeon_emit(cs, va);
6000 radeon_emit(cs, va >> 32);
6001 radeon_emit(cs, 4 * i); /* destination in GDS */
6002 radeon_emit(cs, 0);
6003 radeon_emit(cs, S_414_BYTE_COUNT_GFX9(4) |
6004 S_414_DISABLE_WR_CONFIRM_GFX9(i != last_target));
6005 }
6006
6007 radv_set_streamout_enable(cmd_buffer, true);
6008 }
6009
6010 void radv_CmdBeginTransformFeedbackEXT(
6011 VkCommandBuffer commandBuffer,
6012 uint32_t firstCounterBuffer,
6013 uint32_t counterBufferCount,
6014 const VkBuffer* pCounterBuffers,
6015 const VkDeviceSize* pCounterBufferOffsets)
6016 {
6017 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6018
6019 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6020 gfx10_emit_streamout_begin(cmd_buffer,
6021 firstCounterBuffer, counterBufferCount,
6022 pCounterBuffers, pCounterBufferOffsets);
6023 } else {
6024 radv_emit_streamout_begin(cmd_buffer,
6025 firstCounterBuffer, counterBufferCount,
6026 pCounterBuffers, pCounterBufferOffsets);
6027 }
6028 }
6029
6030 static void
6031 radv_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6032 uint32_t firstCounterBuffer,
6033 uint32_t counterBufferCount,
6034 const VkBuffer *pCounterBuffers,
6035 const VkDeviceSize *pCounterBufferOffsets)
6036 {
6037 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6038 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6039 uint32_t i;
6040
6041 radv_flush_vgt_streamout(cmd_buffer);
6042
6043 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6044 for_each_bit(i, so->enabled_mask) {
6045 int32_t counter_buffer_idx = i - firstCounterBuffer;
6046 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6047 counter_buffer_idx = -1;
6048
6049 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6050 /* The array of counters buffer is optional. */
6051 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6052 uint64_t va = radv_buffer_get_va(buffer->bo);
6053
6054 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6055
6056 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6057 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6058 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6059 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
6060 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
6061 radeon_emit(cs, va); /* dst address lo */
6062 radeon_emit(cs, va >> 32); /* dst address hi */
6063 radeon_emit(cs, 0); /* unused */
6064 radeon_emit(cs, 0); /* unused */
6065
6066 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6067 }
6068
6069 /* Deactivate transform feedback by zeroing the buffer size.
6070 * The counters (primitives generated, primitives emitted) may
6071 * be enabled even if there is not buffer bound. This ensures
6072 * that the primitives-emitted query won't increment.
6073 */
6074 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
6075
6076 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6077 }
6078
6079 radv_set_streamout_enable(cmd_buffer, false);
6080 }
6081
6082 static void
6083 gfx10_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6084 uint32_t firstCounterBuffer,
6085 uint32_t counterBufferCount,
6086 const VkBuffer *pCounterBuffers,
6087 const VkDeviceSize *pCounterBufferOffsets)
6088 {
6089 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6090 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6091 uint32_t i;
6092
6093 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6094 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6095
6096 for_each_bit(i, so->enabled_mask) {
6097 int32_t counter_buffer_idx = i - firstCounterBuffer;
6098 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6099 counter_buffer_idx = -1;
6100
6101 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6102 /* The array of counters buffer is optional. */
6103 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6104 uint64_t va = radv_buffer_get_va(buffer->bo);
6105
6106 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6107
6108 si_cs_emit_write_event_eop(cs,
6109 cmd_buffer->device->physical_device->rad_info.chip_class,
6110 radv_cmd_buffer_uses_mec(cmd_buffer),
6111 V_028A90_PS_DONE, 0,
6112 EOP_DST_SEL_TC_L2,
6113 EOP_DATA_SEL_GDS,
6114 va, EOP_DATA_GDS(i, 1), 0);
6115
6116 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6117 }
6118 }
6119
6120 radv_set_streamout_enable(cmd_buffer, false);
6121 }
6122
6123 void radv_CmdEndTransformFeedbackEXT(
6124 VkCommandBuffer commandBuffer,
6125 uint32_t firstCounterBuffer,
6126 uint32_t counterBufferCount,
6127 const VkBuffer* pCounterBuffers,
6128 const VkDeviceSize* pCounterBufferOffsets)
6129 {
6130 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6131
6132 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6133 gfx10_emit_streamout_end(cmd_buffer,
6134 firstCounterBuffer, counterBufferCount,
6135 pCounterBuffers, pCounterBufferOffsets);
6136 } else {
6137 radv_emit_streamout_end(cmd_buffer,
6138 firstCounterBuffer, counterBufferCount,
6139 pCounterBuffers, pCounterBufferOffsets);
6140 }
6141 }
6142
6143 void radv_CmdDrawIndirectByteCountEXT(
6144 VkCommandBuffer commandBuffer,
6145 uint32_t instanceCount,
6146 uint32_t firstInstance,
6147 VkBuffer _counterBuffer,
6148 VkDeviceSize counterBufferOffset,
6149 uint32_t counterOffset,
6150 uint32_t vertexStride)
6151 {
6152 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6153 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
6154 struct radv_draw_info info = {};
6155
6156 info.instance_count = instanceCount;
6157 info.first_instance = firstInstance;
6158 info.strmout_buffer = counterBuffer;
6159 info.strmout_buffer_offset = counterBufferOffset;
6160 info.stride = vertexStride;
6161
6162 radv_draw(cmd_buffer, &info);
6163 }
6164
6165 /* VK_AMD_buffer_marker */
6166 void radv_CmdWriteBufferMarkerAMD(
6167 VkCommandBuffer commandBuffer,
6168 VkPipelineStageFlagBits pipelineStage,
6169 VkBuffer dstBuffer,
6170 VkDeviceSize dstOffset,
6171 uint32_t marker)
6172 {
6173 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6174 RADV_FROM_HANDLE(radv_buffer, buffer, dstBuffer);
6175 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6176 uint64_t va = radv_buffer_get_va(buffer->bo) + dstOffset;
6177
6178 si_emit_cache_flush(cmd_buffer);
6179
6180 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 12);
6181
6182 if (!(pipelineStage & ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT)) {
6183 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
6184 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
6185 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
6186 COPY_DATA_WR_CONFIRM);
6187 radeon_emit(cs, marker);
6188 radeon_emit(cs, 0);
6189 radeon_emit(cs, va);
6190 radeon_emit(cs, va >> 32);
6191 } else {
6192 si_cs_emit_write_event_eop(cs,
6193 cmd_buffer->device->physical_device->rad_info.chip_class,
6194 radv_cmd_buffer_uses_mec(cmd_buffer),
6195 V_028A90_BOTTOM_OF_PIPE_TS, 0,
6196 EOP_DST_SEL_MEM,
6197 EOP_DATA_SEL_VALUE_32BIT,
6198 va, marker,
6199 cmd_buffer->gfx9_eop_bug_va);
6200 }
6201
6202 assert(cmd_buffer->cs->cdw <= cdw_max);
6203 }