2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
33 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
41 RADV_PREFETCH_VBO_DESCRIPTORS
= (1 << 0),
42 RADV_PREFETCH_VS
= (1 << 1),
43 RADV_PREFETCH_TCS
= (1 << 2),
44 RADV_PREFETCH_TES
= (1 << 3),
45 RADV_PREFETCH_GS
= (1 << 4),
46 RADV_PREFETCH_PS
= (1 << 5),
47 RADV_PREFETCH_SHADERS
= (RADV_PREFETCH_VS
|
54 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
55 struct radv_image
*image
,
56 VkImageLayout src_layout
,
58 VkImageLayout dst_layout
,
62 const VkImageSubresourceRange
*range
,
63 struct radv_sample_locations_state
*sample_locs
);
65 const struct radv_dynamic_state default_dynamic_state
= {
78 .blend_constants
= { 0.0f
, 0.0f
, 0.0f
, 0.0f
},
83 .stencil_compare_mask
= {
87 .stencil_write_mask
= {
91 .stencil_reference
= {
98 radv_bind_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
,
99 const struct radv_dynamic_state
*src
)
101 struct radv_dynamic_state
*dest
= &cmd_buffer
->state
.dynamic
;
102 uint32_t copy_mask
= src
->mask
;
103 uint32_t dest_mask
= 0;
105 /* Make sure to copy the number of viewports/scissors because they can
106 * only be specified at pipeline creation time.
108 dest
->viewport
.count
= src
->viewport
.count
;
109 dest
->scissor
.count
= src
->scissor
.count
;
110 dest
->discard_rectangle
.count
= src
->discard_rectangle
.count
;
111 dest
->sample_location
.count
= src
->sample_location
.count
;
113 if (copy_mask
& RADV_DYNAMIC_VIEWPORT
) {
114 if (memcmp(&dest
->viewport
.viewports
, &src
->viewport
.viewports
,
115 src
->viewport
.count
* sizeof(VkViewport
))) {
116 typed_memcpy(dest
->viewport
.viewports
,
117 src
->viewport
.viewports
,
118 src
->viewport
.count
);
119 dest_mask
|= RADV_DYNAMIC_VIEWPORT
;
123 if (copy_mask
& RADV_DYNAMIC_SCISSOR
) {
124 if (memcmp(&dest
->scissor
.scissors
, &src
->scissor
.scissors
,
125 src
->scissor
.count
* sizeof(VkRect2D
))) {
126 typed_memcpy(dest
->scissor
.scissors
,
127 src
->scissor
.scissors
, src
->scissor
.count
);
128 dest_mask
|= RADV_DYNAMIC_SCISSOR
;
132 if (copy_mask
& RADV_DYNAMIC_LINE_WIDTH
) {
133 if (dest
->line_width
!= src
->line_width
) {
134 dest
->line_width
= src
->line_width
;
135 dest_mask
|= RADV_DYNAMIC_LINE_WIDTH
;
139 if (copy_mask
& RADV_DYNAMIC_DEPTH_BIAS
) {
140 if (memcmp(&dest
->depth_bias
, &src
->depth_bias
,
141 sizeof(src
->depth_bias
))) {
142 dest
->depth_bias
= src
->depth_bias
;
143 dest_mask
|= RADV_DYNAMIC_DEPTH_BIAS
;
147 if (copy_mask
& RADV_DYNAMIC_BLEND_CONSTANTS
) {
148 if (memcmp(&dest
->blend_constants
, &src
->blend_constants
,
149 sizeof(src
->blend_constants
))) {
150 typed_memcpy(dest
->blend_constants
,
151 src
->blend_constants
, 4);
152 dest_mask
|= RADV_DYNAMIC_BLEND_CONSTANTS
;
156 if (copy_mask
& RADV_DYNAMIC_DEPTH_BOUNDS
) {
157 if (memcmp(&dest
->depth_bounds
, &src
->depth_bounds
,
158 sizeof(src
->depth_bounds
))) {
159 dest
->depth_bounds
= src
->depth_bounds
;
160 dest_mask
|= RADV_DYNAMIC_DEPTH_BOUNDS
;
164 if (copy_mask
& RADV_DYNAMIC_STENCIL_COMPARE_MASK
) {
165 if (memcmp(&dest
->stencil_compare_mask
,
166 &src
->stencil_compare_mask
,
167 sizeof(src
->stencil_compare_mask
))) {
168 dest
->stencil_compare_mask
= src
->stencil_compare_mask
;
169 dest_mask
|= RADV_DYNAMIC_STENCIL_COMPARE_MASK
;
173 if (copy_mask
& RADV_DYNAMIC_STENCIL_WRITE_MASK
) {
174 if (memcmp(&dest
->stencil_write_mask
, &src
->stencil_write_mask
,
175 sizeof(src
->stencil_write_mask
))) {
176 dest
->stencil_write_mask
= src
->stencil_write_mask
;
177 dest_mask
|= RADV_DYNAMIC_STENCIL_WRITE_MASK
;
181 if (copy_mask
& RADV_DYNAMIC_STENCIL_REFERENCE
) {
182 if (memcmp(&dest
->stencil_reference
, &src
->stencil_reference
,
183 sizeof(src
->stencil_reference
))) {
184 dest
->stencil_reference
= src
->stencil_reference
;
185 dest_mask
|= RADV_DYNAMIC_STENCIL_REFERENCE
;
189 if (copy_mask
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
190 if (memcmp(&dest
->discard_rectangle
.rectangles
, &src
->discard_rectangle
.rectangles
,
191 src
->discard_rectangle
.count
* sizeof(VkRect2D
))) {
192 typed_memcpy(dest
->discard_rectangle
.rectangles
,
193 src
->discard_rectangle
.rectangles
,
194 src
->discard_rectangle
.count
);
195 dest_mask
|= RADV_DYNAMIC_DISCARD_RECTANGLE
;
199 if (copy_mask
& RADV_DYNAMIC_SAMPLE_LOCATIONS
) {
200 if (dest
->sample_location
.per_pixel
!= src
->sample_location
.per_pixel
||
201 dest
->sample_location
.grid_size
.width
!= src
->sample_location
.grid_size
.width
||
202 dest
->sample_location
.grid_size
.height
!= src
->sample_location
.grid_size
.height
||
203 memcmp(&dest
->sample_location
.locations
,
204 &src
->sample_location
.locations
,
205 src
->sample_location
.count
* sizeof(VkSampleLocationEXT
))) {
206 dest
->sample_location
.per_pixel
= src
->sample_location
.per_pixel
;
207 dest
->sample_location
.grid_size
= src
->sample_location
.grid_size
;
208 typed_memcpy(dest
->sample_location
.locations
,
209 src
->sample_location
.locations
,
210 src
->sample_location
.count
);
211 dest_mask
|= RADV_DYNAMIC_SAMPLE_LOCATIONS
;
215 cmd_buffer
->state
.dirty
|= dest_mask
;
219 radv_bind_streamout_state(struct radv_cmd_buffer
*cmd_buffer
,
220 struct radv_pipeline
*pipeline
)
222 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
223 struct radv_shader_info
*info
;
225 if (!pipeline
->streamout_shader
||
226 cmd_buffer
->device
->physical_device
->use_ngg_streamout
)
229 info
= &pipeline
->streamout_shader
->info
;
230 for (int i
= 0; i
< MAX_SO_BUFFERS
; i
++)
231 so
->stride_in_dw
[i
] = info
->so
.strides
[i
];
233 so
->enabled_stream_buffers_mask
= info
->so
.enabled_stream_buffers_mask
;
236 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
)
238 return cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
239 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
242 enum ring_type
radv_queue_family_to_ring(int f
) {
244 case RADV_QUEUE_GENERAL
:
246 case RADV_QUEUE_COMPUTE
:
248 case RADV_QUEUE_TRANSFER
:
251 unreachable("Unknown queue family");
255 static VkResult
radv_create_cmd_buffer(
256 struct radv_device
* device
,
257 struct radv_cmd_pool
* pool
,
258 VkCommandBufferLevel level
,
259 VkCommandBuffer
* pCommandBuffer
)
261 struct radv_cmd_buffer
*cmd_buffer
;
263 cmd_buffer
= vk_zalloc(&pool
->alloc
, sizeof(*cmd_buffer
), 8,
264 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
265 if (cmd_buffer
== NULL
)
266 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
268 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
269 cmd_buffer
->device
= device
;
270 cmd_buffer
->pool
= pool
;
271 cmd_buffer
->level
= level
;
274 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
275 cmd_buffer
->queue_family_index
= pool
->queue_family_index
;
278 /* Init the pool_link so we can safely call list_del when we destroy
281 list_inithead(&cmd_buffer
->pool_link
);
282 cmd_buffer
->queue_family_index
= RADV_QUEUE_GENERAL
;
285 ring
= radv_queue_family_to_ring(cmd_buffer
->queue_family_index
);
287 cmd_buffer
->cs
= device
->ws
->cs_create(device
->ws
, ring
);
288 if (!cmd_buffer
->cs
) {
289 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
290 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
293 *pCommandBuffer
= radv_cmd_buffer_to_handle(cmd_buffer
);
295 list_inithead(&cmd_buffer
->upload
.list
);
301 radv_cmd_buffer_destroy(struct radv_cmd_buffer
*cmd_buffer
)
303 list_del(&cmd_buffer
->pool_link
);
305 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
306 &cmd_buffer
->upload
.list
, list
) {
307 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
312 if (cmd_buffer
->upload
.upload_bo
)
313 cmd_buffer
->device
->ws
->buffer_destroy(cmd_buffer
->upload
.upload_bo
);
314 cmd_buffer
->device
->ws
->cs_destroy(cmd_buffer
->cs
);
316 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++)
317 free(cmd_buffer
->descriptors
[i
].push_set
.set
.mapped_ptr
);
319 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
323 radv_reset_cmd_buffer(struct radv_cmd_buffer
*cmd_buffer
)
325 cmd_buffer
->device
->ws
->cs_reset(cmd_buffer
->cs
);
327 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
328 &cmd_buffer
->upload
.list
, list
) {
329 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
334 cmd_buffer
->push_constant_stages
= 0;
335 cmd_buffer
->scratch_size_per_wave_needed
= 0;
336 cmd_buffer
->scratch_waves_wanted
= 0;
337 cmd_buffer
->compute_scratch_size_per_wave_needed
= 0;
338 cmd_buffer
->compute_scratch_waves_wanted
= 0;
339 cmd_buffer
->esgs_ring_size_needed
= 0;
340 cmd_buffer
->gsvs_ring_size_needed
= 0;
341 cmd_buffer
->tess_rings_needed
= false;
342 cmd_buffer
->gds_needed
= false;
343 cmd_buffer
->sample_positions_needed
= false;
345 if (cmd_buffer
->upload
.upload_bo
)
346 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
347 cmd_buffer
->upload
.upload_bo
);
348 cmd_buffer
->upload
.offset
= 0;
350 cmd_buffer
->record_result
= VK_SUCCESS
;
352 memset(cmd_buffer
->vertex_bindings
, 0, sizeof(cmd_buffer
->vertex_bindings
));
354 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++) {
355 cmd_buffer
->descriptors
[i
].dirty
= 0;
356 cmd_buffer
->descriptors
[i
].valid
= 0;
357 cmd_buffer
->descriptors
[i
].push_dirty
= false;
360 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
361 cmd_buffer
->queue_family_index
== RADV_QUEUE_GENERAL
) {
362 unsigned num_db
= cmd_buffer
->device
->physical_device
->rad_info
.num_render_backends
;
363 unsigned fence_offset
, eop_bug_offset
;
366 radv_cmd_buffer_upload_alloc(cmd_buffer
, 8, 8, &fence_offset
,
369 cmd_buffer
->gfx9_fence_va
=
370 radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
371 cmd_buffer
->gfx9_fence_va
+= fence_offset
;
373 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
374 /* Allocate a buffer for the EOP bug on GFX9. */
375 radv_cmd_buffer_upload_alloc(cmd_buffer
, 16 * num_db
, 8,
376 &eop_bug_offset
, &fence_ptr
);
377 cmd_buffer
->gfx9_eop_bug_va
=
378 radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
379 cmd_buffer
->gfx9_eop_bug_va
+= eop_bug_offset
;
383 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_INITIAL
;
385 return cmd_buffer
->record_result
;
389 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer
*cmd_buffer
,
393 struct radeon_winsys_bo
*bo
;
394 struct radv_cmd_buffer_upload
*upload
;
395 struct radv_device
*device
= cmd_buffer
->device
;
397 new_size
= MAX2(min_needed
, 16 * 1024);
398 new_size
= MAX2(new_size
, 2 * cmd_buffer
->upload
.size
);
400 bo
= device
->ws
->buffer_create(device
->ws
,
403 RADEON_FLAG_CPU_ACCESS
|
404 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
406 RADV_BO_PRIORITY_UPLOAD_BUFFER
);
409 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
413 radv_cs_add_buffer(device
->ws
, cmd_buffer
->cs
, bo
);
414 if (cmd_buffer
->upload
.upload_bo
) {
415 upload
= malloc(sizeof(*upload
));
418 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
419 device
->ws
->buffer_destroy(bo
);
423 memcpy(upload
, &cmd_buffer
->upload
, sizeof(*upload
));
424 list_add(&upload
->list
, &cmd_buffer
->upload
.list
);
427 cmd_buffer
->upload
.upload_bo
= bo
;
428 cmd_buffer
->upload
.size
= new_size
;
429 cmd_buffer
->upload
.offset
= 0;
430 cmd_buffer
->upload
.map
= device
->ws
->buffer_map(cmd_buffer
->upload
.upload_bo
);
432 if (!cmd_buffer
->upload
.map
) {
433 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
441 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
444 unsigned *out_offset
,
447 assert(util_is_power_of_two_nonzero(alignment
));
449 uint64_t offset
= align(cmd_buffer
->upload
.offset
, alignment
);
450 if (offset
+ size
> cmd_buffer
->upload
.size
) {
451 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer
, size
))
456 *out_offset
= offset
;
457 *ptr
= cmd_buffer
->upload
.map
+ offset
;
459 cmd_buffer
->upload
.offset
= offset
+ size
;
464 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
465 unsigned size
, unsigned alignment
,
466 const void *data
, unsigned *out_offset
)
470 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
, alignment
,
471 out_offset
, (void **)&ptr
))
475 memcpy(ptr
, data
, size
);
481 radv_emit_write_data_packet(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
482 unsigned count
, const uint32_t *data
)
484 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
486 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 4 + count
);
488 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, 0));
489 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
490 S_370_WR_CONFIRM(1) |
491 S_370_ENGINE_SEL(V_370_ME
));
493 radeon_emit(cs
, va
>> 32);
494 radeon_emit_array(cs
, data
, count
);
497 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
)
499 struct radv_device
*device
= cmd_buffer
->device
;
500 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
503 va
= radv_buffer_get_va(device
->trace_bo
);
504 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
)
507 ++cmd_buffer
->state
.trace_id
;
508 radv_emit_write_data_packet(cmd_buffer
, va
, 1,
509 &cmd_buffer
->state
.trace_id
);
511 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 2);
513 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
514 radeon_emit(cs
, AC_ENCODE_TRACE_POINT(cmd_buffer
->state
.trace_id
));
518 radv_cmd_buffer_after_draw(struct radv_cmd_buffer
*cmd_buffer
,
519 enum radv_cmd_flush_bits flags
)
521 if (cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_SYNC_SHADERS
) {
522 assert(flags
& (RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
523 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
));
525 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 4);
527 /* Force wait for graphics or compute engines to be idle. */
528 si_cs_emit_cache_flush(cmd_buffer
->cs
,
529 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
530 &cmd_buffer
->gfx9_fence_idx
,
531 cmd_buffer
->gfx9_fence_va
,
532 radv_cmd_buffer_uses_mec(cmd_buffer
),
533 flags
, cmd_buffer
->gfx9_eop_bug_va
);
536 if (unlikely(cmd_buffer
->device
->trace_bo
))
537 radv_cmd_buffer_trace_emit(cmd_buffer
);
541 radv_save_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
542 struct radv_pipeline
*pipeline
, enum ring_type ring
)
544 struct radv_device
*device
= cmd_buffer
->device
;
548 va
= radv_buffer_get_va(device
->trace_bo
);
558 assert(!"invalid ring type");
561 uint64_t pipeline_address
= (uintptr_t)pipeline
;
562 data
[0] = pipeline_address
;
563 data
[1] = pipeline_address
>> 32;
565 radv_emit_write_data_packet(cmd_buffer
, va
, 2, data
);
568 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
569 VkPipelineBindPoint bind_point
,
570 struct radv_descriptor_set
*set
,
573 struct radv_descriptor_state
*descriptors_state
=
574 radv_get_descriptors_state(cmd_buffer
, bind_point
);
576 descriptors_state
->sets
[idx
] = set
;
578 descriptors_state
->valid
|= (1u << idx
); /* active descriptors */
579 descriptors_state
->dirty
|= (1u << idx
);
583 radv_save_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
584 VkPipelineBindPoint bind_point
)
586 struct radv_descriptor_state
*descriptors_state
=
587 radv_get_descriptors_state(cmd_buffer
, bind_point
);
588 struct radv_device
*device
= cmd_buffer
->device
;
589 uint32_t data
[MAX_SETS
* 2] = {};
592 va
= radv_buffer_get_va(device
->trace_bo
) + 24;
594 for_each_bit(i
, descriptors_state
->valid
) {
595 struct radv_descriptor_set
*set
= descriptors_state
->sets
[i
];
596 data
[i
* 2] = (uint64_t)(uintptr_t)set
;
597 data
[i
* 2 + 1] = (uint64_t)(uintptr_t)set
>> 32;
600 radv_emit_write_data_packet(cmd_buffer
, va
, MAX_SETS
* 2, data
);
603 struct radv_userdata_info
*
604 radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
605 gl_shader_stage stage
,
608 struct radv_shader_variant
*shader
= radv_get_shader(pipeline
, stage
);
609 return &shader
->info
.user_sgprs_locs
.shader_data
[idx
];
613 radv_emit_userdata_address(struct radv_cmd_buffer
*cmd_buffer
,
614 struct radv_pipeline
*pipeline
,
615 gl_shader_stage stage
,
616 int idx
, uint64_t va
)
618 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, idx
);
619 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
620 if (loc
->sgpr_idx
== -1)
623 assert(loc
->num_sgprs
== 1);
625 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
626 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
630 radv_emit_descriptor_pointers(struct radv_cmd_buffer
*cmd_buffer
,
631 struct radv_pipeline
*pipeline
,
632 struct radv_descriptor_state
*descriptors_state
,
633 gl_shader_stage stage
)
635 struct radv_device
*device
= cmd_buffer
->device
;
636 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
637 uint32_t sh_base
= pipeline
->user_data_0
[stage
];
638 struct radv_userdata_locations
*locs
=
639 &pipeline
->shaders
[stage
]->info
.user_sgprs_locs
;
640 unsigned mask
= locs
->descriptor_sets_enabled
;
642 mask
&= descriptors_state
->dirty
& descriptors_state
->valid
;
647 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
649 struct radv_userdata_info
*loc
= &locs
->descriptor_sets
[start
];
650 unsigned sh_offset
= sh_base
+ loc
->sgpr_idx
* 4;
652 radv_emit_shader_pointer_head(cs
, sh_offset
, count
, true);
653 for (int i
= 0; i
< count
; i
++) {
654 struct radv_descriptor_set
*set
=
655 descriptors_state
->sets
[start
+ i
];
657 radv_emit_shader_pointer_body(device
, cs
, set
->va
, true);
663 * Convert the user sample locations to hardware sample locations (the values
664 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
667 radv_convert_user_sample_locs(struct radv_sample_locations_state
*state
,
668 uint32_t x
, uint32_t y
, VkOffset2D
*sample_locs
)
670 uint32_t x_offset
= x
% state
->grid_size
.width
;
671 uint32_t y_offset
= y
% state
->grid_size
.height
;
672 uint32_t num_samples
= (uint32_t)state
->per_pixel
;
673 VkSampleLocationEXT
*user_locs
;
674 uint32_t pixel_offset
;
676 pixel_offset
= (x_offset
+ y_offset
* state
->grid_size
.width
) * num_samples
;
678 assert(pixel_offset
<= MAX_SAMPLE_LOCATIONS
);
679 user_locs
= &state
->locations
[pixel_offset
];
681 for (uint32_t i
= 0; i
< num_samples
; i
++) {
682 float shifted_pos_x
= user_locs
[i
].x
- 0.5;
683 float shifted_pos_y
= user_locs
[i
].y
- 0.5;
685 int32_t scaled_pos_x
= floor(shifted_pos_x
* 16);
686 int32_t scaled_pos_y
= floor(shifted_pos_y
* 16);
688 sample_locs
[i
].x
= CLAMP(scaled_pos_x
, -8, 7);
689 sample_locs
[i
].y
= CLAMP(scaled_pos_y
, -8, 7);
694 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
698 radv_compute_sample_locs_pixel(uint32_t num_samples
, VkOffset2D
*sample_locs
,
699 uint32_t *sample_locs_pixel
)
701 for (uint32_t i
= 0; i
< num_samples
; i
++) {
702 uint32_t sample_reg_idx
= i
/ 4;
703 uint32_t sample_loc_idx
= i
% 4;
704 int32_t pos_x
= sample_locs
[i
].x
;
705 int32_t pos_y
= sample_locs
[i
].y
;
707 uint32_t shift_x
= 8 * sample_loc_idx
;
708 uint32_t shift_y
= shift_x
+ 4;
710 sample_locs_pixel
[sample_reg_idx
] |= (pos_x
& 0xf) << shift_x
;
711 sample_locs_pixel
[sample_reg_idx
] |= (pos_y
& 0xf) << shift_y
;
716 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
720 radv_compute_centroid_priority(struct radv_cmd_buffer
*cmd_buffer
,
721 VkOffset2D
*sample_locs
,
722 uint32_t num_samples
)
724 uint32_t centroid_priorities
[num_samples
];
725 uint32_t sample_mask
= num_samples
- 1;
726 uint32_t distances
[num_samples
];
727 uint64_t centroid_priority
= 0;
729 /* Compute the distances from center for each sample. */
730 for (int i
= 0; i
< num_samples
; i
++) {
731 distances
[i
] = (sample_locs
[i
].x
* sample_locs
[i
].x
) +
732 (sample_locs
[i
].y
* sample_locs
[i
].y
);
735 /* Compute the centroid priorities by looking at the distances array. */
736 for (int i
= 0; i
< num_samples
; i
++) {
737 uint32_t min_idx
= 0;
739 for (int j
= 1; j
< num_samples
; j
++) {
740 if (distances
[j
] < distances
[min_idx
])
744 centroid_priorities
[i
] = min_idx
;
745 distances
[min_idx
] = 0xffffffff;
748 /* Compute the final centroid priority. */
749 for (int i
= 0; i
< 8; i
++) {
751 centroid_priorities
[i
& sample_mask
] << (i
* 4);
754 return centroid_priority
<< 32 | centroid_priority
;
758 * Emit the sample locations that are specified with VK_EXT_sample_locations.
761 radv_emit_sample_locations(struct radv_cmd_buffer
*cmd_buffer
)
763 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
764 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
765 struct radv_sample_locations_state
*sample_location
=
766 &cmd_buffer
->state
.dynamic
.sample_location
;
767 uint32_t num_samples
= (uint32_t)sample_location
->per_pixel
;
768 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
769 uint32_t sample_locs_pixel
[4][2] = {};
770 VkOffset2D sample_locs
[4][8]; /* 8 is the max. sample count supported */
771 uint32_t max_sample_dist
= 0;
772 uint64_t centroid_priority
;
774 if (!cmd_buffer
->state
.dynamic
.sample_location
.count
)
777 /* Convert the user sample locations to hardware sample locations. */
778 radv_convert_user_sample_locs(sample_location
, 0, 0, sample_locs
[0]);
779 radv_convert_user_sample_locs(sample_location
, 1, 0, sample_locs
[1]);
780 radv_convert_user_sample_locs(sample_location
, 0, 1, sample_locs
[2]);
781 radv_convert_user_sample_locs(sample_location
, 1, 1, sample_locs
[3]);
783 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
784 for (uint32_t i
= 0; i
< 4; i
++) {
785 radv_compute_sample_locs_pixel(num_samples
, sample_locs
[i
],
786 sample_locs_pixel
[i
]);
789 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
791 radv_compute_centroid_priority(cmd_buffer
, sample_locs
[0],
794 /* Compute the maximum sample distance from the specified locations. */
795 for (uint32_t i
= 0; i
< num_samples
; i
++) {
796 VkOffset2D offset
= sample_locs
[0][i
];
797 max_sample_dist
= MAX2(max_sample_dist
,
798 MAX2(abs(offset
.x
), abs(offset
.y
)));
801 /* Emit the specified user sample locations. */
802 switch (num_samples
) {
805 radeon_set_context_reg(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_pixel
[0][0]);
806 radeon_set_context_reg(cs
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_pixel
[1][0]);
807 radeon_set_context_reg(cs
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_pixel
[2][0]);
808 radeon_set_context_reg(cs
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_pixel
[3][0]);
811 radeon_set_context_reg(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_pixel
[0][0]);
812 radeon_set_context_reg(cs
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_pixel
[1][0]);
813 radeon_set_context_reg(cs
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_pixel
[2][0]);
814 radeon_set_context_reg(cs
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_pixel
[3][0]);
815 radeon_set_context_reg(cs
, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1
, sample_locs_pixel
[0][1]);
816 radeon_set_context_reg(cs
, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1
, sample_locs_pixel
[1][1]);
817 radeon_set_context_reg(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1
, sample_locs_pixel
[2][1]);
818 radeon_set_context_reg(cs
, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1
, sample_locs_pixel
[3][1]);
821 unreachable("invalid number of samples");
824 /* Emit the maximum sample distance and the centroid priority. */
825 uint32_t pa_sc_aa_config
= ms
->pa_sc_aa_config
;
827 pa_sc_aa_config
&= C_028BE0_MAX_SAMPLE_DIST
;
828 pa_sc_aa_config
|= S_028BE0_MAX_SAMPLE_DIST(max_sample_dist
);
830 radeon_set_context_reg_seq(cs
, R_028BE0_PA_SC_AA_CONFIG
, 1);
831 radeon_emit(cs
, pa_sc_aa_config
);
833 radeon_set_context_reg_seq(cs
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 2);
834 radeon_emit(cs
, centroid_priority
);
835 radeon_emit(cs
, centroid_priority
>> 32);
837 /* GFX9: Flush DFSM when the AA mode changes. */
838 if (cmd_buffer
->device
->dfsm_allowed
) {
839 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
840 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
843 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
847 radv_emit_inline_push_consts(struct radv_cmd_buffer
*cmd_buffer
,
848 struct radv_pipeline
*pipeline
,
849 gl_shader_stage stage
,
850 int idx
, int count
, uint32_t *values
)
852 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, idx
);
853 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
854 if (loc
->sgpr_idx
== -1)
857 assert(loc
->num_sgprs
== count
);
859 radeon_set_sh_reg_seq(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, count
);
860 radeon_emit_array(cmd_buffer
->cs
, values
, count
);
864 radv_update_multisample_state(struct radv_cmd_buffer
*cmd_buffer
,
865 struct radv_pipeline
*pipeline
)
867 int num_samples
= pipeline
->graphics
.ms
.num_samples
;
868 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
869 struct radv_pipeline
*old_pipeline
= cmd_buffer
->state
.emitted_pipeline
;
871 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.needs_sample_positions
)
872 cmd_buffer
->sample_positions_needed
= true;
874 if (old_pipeline
&& num_samples
== old_pipeline
->graphics
.ms
.num_samples
)
877 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028BDC_PA_SC_LINE_CNTL
, 2);
878 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_line_cntl
);
879 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_config
);
881 radeon_set_context_reg(cmd_buffer
->cs
, R_028A48_PA_SC_MODE_CNTL_0
, ms
->pa_sc_mode_cntl_0
);
883 radv_emit_default_sample_locations(cmd_buffer
->cs
, num_samples
);
885 /* GFX9: Flush DFSM when the AA mode changes. */
886 if (cmd_buffer
->device
->dfsm_allowed
) {
887 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
888 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
891 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
895 radv_update_binning_state(struct radv_cmd_buffer
*cmd_buffer
,
896 struct radv_pipeline
*pipeline
)
898 const struct radv_pipeline
*old_pipeline
= cmd_buffer
->state
.emitted_pipeline
;
901 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX9
)
905 old_pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
== pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
&&
906 old_pipeline
->graphics
.binning
.db_dfsm_control
== pipeline
->graphics
.binning
.db_dfsm_control
)
909 bool binning_flush
= false;
910 if (cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_VEGA12
||
911 cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_VEGA20
||
912 cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_RAVEN2
||
913 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
914 binning_flush
= !old_pipeline
||
915 G_028C44_BINNING_MODE(old_pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
) !=
916 G_028C44_BINNING_MODE(pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
);
919 radeon_set_context_reg(cmd_buffer
->cs
, R_028C44_PA_SC_BINNER_CNTL_0
,
920 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
|
921 S_028C44_FLUSH_ON_BINNING_TRANSITION(!!binning_flush
));
923 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
924 radeon_set_context_reg(cmd_buffer
->cs
, R_028038_DB_DFSM_CONTROL
,
925 pipeline
->graphics
.binning
.db_dfsm_control
);
927 radeon_set_context_reg(cmd_buffer
->cs
, R_028060_DB_DFSM_CONTROL
,
928 pipeline
->graphics
.binning
.db_dfsm_control
);
931 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
936 radv_emit_shader_prefetch(struct radv_cmd_buffer
*cmd_buffer
,
937 struct radv_shader_variant
*shader
)
944 va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
946 si_cp_dma_prefetch(cmd_buffer
, va
, shader
->code_size
);
950 radv_emit_prefetch_L2(struct radv_cmd_buffer
*cmd_buffer
,
951 struct radv_pipeline
*pipeline
,
952 bool vertex_stage_only
)
954 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
955 uint32_t mask
= state
->prefetch_L2_mask
;
957 if (vertex_stage_only
) {
958 /* Fast prefetch path for starting draws as soon as possible.
960 mask
= state
->prefetch_L2_mask
& (RADV_PREFETCH_VS
|
961 RADV_PREFETCH_VBO_DESCRIPTORS
);
964 if (mask
& RADV_PREFETCH_VS
)
965 radv_emit_shader_prefetch(cmd_buffer
,
966 pipeline
->shaders
[MESA_SHADER_VERTEX
]);
968 if (mask
& RADV_PREFETCH_VBO_DESCRIPTORS
)
969 si_cp_dma_prefetch(cmd_buffer
, state
->vb_va
, state
->vb_size
);
971 if (mask
& RADV_PREFETCH_TCS
)
972 radv_emit_shader_prefetch(cmd_buffer
,
973 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]);
975 if (mask
& RADV_PREFETCH_TES
)
976 radv_emit_shader_prefetch(cmd_buffer
,
977 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]);
979 if (mask
& RADV_PREFETCH_GS
) {
980 radv_emit_shader_prefetch(cmd_buffer
,
981 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]);
982 if (radv_pipeline_has_gs_copy_shader(pipeline
))
983 radv_emit_shader_prefetch(cmd_buffer
, pipeline
->gs_copy_shader
);
986 if (mask
& RADV_PREFETCH_PS
)
987 radv_emit_shader_prefetch(cmd_buffer
,
988 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
990 state
->prefetch_L2_mask
&= ~mask
;
994 radv_emit_rbplus_state(struct radv_cmd_buffer
*cmd_buffer
)
996 if (!cmd_buffer
->device
->physical_device
->rad_info
.rbplus_allowed
)
999 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1000 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1002 unsigned sx_ps_downconvert
= 0;
1003 unsigned sx_blend_opt_epsilon
= 0;
1004 unsigned sx_blend_opt_control
= 0;
1006 if (!cmd_buffer
->state
.attachments
|| !subpass
)
1009 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1010 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
1011 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
1012 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
1016 int idx
= subpass
->color_attachments
[i
].attachment
;
1017 struct radv_color_buffer_info
*cb
= &cmd_buffer
->state
.attachments
[idx
].cb
;
1019 unsigned format
= G_028C70_FORMAT(cb
->cb_color_info
);
1020 unsigned swap
= G_028C70_COMP_SWAP(cb
->cb_color_info
);
1021 uint32_t spi_format
= (pipeline
->graphics
.col_format
>> (i
* 4)) & 0xf;
1022 uint32_t colormask
= (pipeline
->graphics
.cb_target_mask
>> (i
* 4)) & 0xf;
1024 bool has_alpha
, has_rgb
;
1026 /* Set if RGB and A are present. */
1027 has_alpha
= !G_028C74_FORCE_DST_ALPHA_1(cb
->cb_color_attrib
);
1029 if (format
== V_028C70_COLOR_8
||
1030 format
== V_028C70_COLOR_16
||
1031 format
== V_028C70_COLOR_32
)
1032 has_rgb
= !has_alpha
;
1036 /* Check the colormask and export format. */
1037 if (!(colormask
& 0x7))
1039 if (!(colormask
& 0x8))
1042 if (spi_format
== V_028714_SPI_SHADER_ZERO
) {
1047 /* Disable value checking for disabled channels. */
1049 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
1051 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
1053 /* Enable down-conversion for 32bpp and smaller formats. */
1055 case V_028C70_COLOR_8
:
1056 case V_028C70_COLOR_8_8
:
1057 case V_028C70_COLOR_8_8_8_8
:
1058 /* For 1 and 2-channel formats, use the superset thereof. */
1059 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
||
1060 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
1061 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
1062 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_8_8_8_8
<< (i
* 4);
1063 sx_blend_opt_epsilon
|= V_028758_8BIT_FORMAT
<< (i
* 4);
1067 case V_028C70_COLOR_5_6_5
:
1068 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1069 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_5_6_5
<< (i
* 4);
1070 sx_blend_opt_epsilon
|= V_028758_6BIT_FORMAT
<< (i
* 4);
1074 case V_028C70_COLOR_1_5_5_5
:
1075 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1076 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_1_5_5_5
<< (i
* 4);
1077 sx_blend_opt_epsilon
|= V_028758_5BIT_FORMAT
<< (i
* 4);
1081 case V_028C70_COLOR_4_4_4_4
:
1082 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1083 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_4_4_4_4
<< (i
* 4);
1084 sx_blend_opt_epsilon
|= V_028758_4BIT_FORMAT
<< (i
* 4);
1088 case V_028C70_COLOR_32
:
1089 if (swap
== V_028C70_SWAP_STD
&&
1090 spi_format
== V_028714_SPI_SHADER_32_R
)
1091 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
1092 else if (swap
== V_028C70_SWAP_ALT_REV
&&
1093 spi_format
== V_028714_SPI_SHADER_32_AR
)
1094 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_A
<< (i
* 4);
1097 case V_028C70_COLOR_16
:
1098 case V_028C70_COLOR_16_16
:
1099 /* For 1-channel formats, use the superset thereof. */
1100 if (spi_format
== V_028714_SPI_SHADER_UNORM16_ABGR
||
1101 spi_format
== V_028714_SPI_SHADER_SNORM16_ABGR
||
1102 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
1103 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
1104 if (swap
== V_028C70_SWAP_STD
||
1105 swap
== V_028C70_SWAP_STD_REV
)
1106 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_GR
<< (i
* 4);
1108 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_AR
<< (i
* 4);
1112 case V_028C70_COLOR_10_11_11
:
1113 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1114 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_10_11_11
<< (i
* 4);
1115 sx_blend_opt_epsilon
|= V_028758_11BIT_FORMAT
<< (i
* 4);
1119 case V_028C70_COLOR_2_10_10_10
:
1120 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1121 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_2_10_10_10
<< (i
* 4);
1122 sx_blend_opt_epsilon
|= V_028758_10BIT_FORMAT
<< (i
* 4);
1128 for (unsigned i
= subpass
->color_count
; i
< 8; ++i
) {
1129 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
1130 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
1132 /* TODO: avoid redundantly setting context registers */
1133 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
1134 radeon_emit(cmd_buffer
->cs
, sx_ps_downconvert
);
1135 radeon_emit(cmd_buffer
->cs
, sx_blend_opt_epsilon
);
1136 radeon_emit(cmd_buffer
->cs
, sx_blend_opt_control
);
1138 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1142 radv_emit_graphics_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
1144 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1146 if (!pipeline
|| cmd_buffer
->state
.emitted_pipeline
== pipeline
)
1149 radv_update_multisample_state(cmd_buffer
, pipeline
);
1150 radv_update_binning_state(cmd_buffer
, pipeline
);
1152 cmd_buffer
->scratch_size_per_wave_needed
= MAX2(cmd_buffer
->scratch_size_per_wave_needed
,
1153 pipeline
->scratch_bytes_per_wave
);
1154 cmd_buffer
->scratch_waves_wanted
= MAX2(cmd_buffer
->scratch_waves_wanted
,
1155 pipeline
->max_waves
);
1157 if (!cmd_buffer
->state
.emitted_pipeline
||
1158 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
!=
1159 pipeline
->graphics
.can_use_guardband
)
1160 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
1162 radeon_emit_array(cmd_buffer
->cs
, pipeline
->cs
.buf
, pipeline
->cs
.cdw
);
1164 if (!cmd_buffer
->state
.emitted_pipeline
||
1165 cmd_buffer
->state
.emitted_pipeline
->ctx_cs
.cdw
!= pipeline
->ctx_cs
.cdw
||
1166 cmd_buffer
->state
.emitted_pipeline
->ctx_cs_hash
!= pipeline
->ctx_cs_hash
||
1167 memcmp(cmd_buffer
->state
.emitted_pipeline
->ctx_cs
.buf
,
1168 pipeline
->ctx_cs
.buf
, pipeline
->ctx_cs
.cdw
* 4)) {
1169 radeon_emit_array(cmd_buffer
->cs
, pipeline
->ctx_cs
.buf
, pipeline
->ctx_cs
.cdw
);
1170 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1173 for (unsigned i
= 0; i
< MESA_SHADER_COMPUTE
; i
++) {
1174 if (!pipeline
->shaders
[i
])
1177 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
1178 pipeline
->shaders
[i
]->bo
);
1181 if (radv_pipeline_has_gs_copy_shader(pipeline
))
1182 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
1183 pipeline
->gs_copy_shader
->bo
);
1185 if (unlikely(cmd_buffer
->device
->trace_bo
))
1186 radv_save_pipeline(cmd_buffer
, pipeline
, RING_GFX
);
1188 cmd_buffer
->state
.emitted_pipeline
= pipeline
;
1190 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_PIPELINE
;
1194 radv_emit_viewport(struct radv_cmd_buffer
*cmd_buffer
)
1196 si_write_viewport(cmd_buffer
->cs
, 0, cmd_buffer
->state
.dynamic
.viewport
.count
,
1197 cmd_buffer
->state
.dynamic
.viewport
.viewports
);
1201 radv_emit_scissor(struct radv_cmd_buffer
*cmd_buffer
)
1203 uint32_t count
= cmd_buffer
->state
.dynamic
.scissor
.count
;
1205 si_write_scissors(cmd_buffer
->cs
, 0, count
,
1206 cmd_buffer
->state
.dynamic
.scissor
.scissors
,
1207 cmd_buffer
->state
.dynamic
.viewport
.viewports
,
1208 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
);
1210 cmd_buffer
->state
.context_roll_without_scissor_emitted
= false;
1214 radv_emit_discard_rectangle(struct radv_cmd_buffer
*cmd_buffer
)
1216 if (!cmd_buffer
->state
.dynamic
.discard_rectangle
.count
)
1219 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028210_PA_SC_CLIPRECT_0_TL
,
1220 cmd_buffer
->state
.dynamic
.discard_rectangle
.count
* 2);
1221 for (unsigned i
= 0; i
< cmd_buffer
->state
.dynamic
.discard_rectangle
.count
; ++i
) {
1222 VkRect2D rect
= cmd_buffer
->state
.dynamic
.discard_rectangle
.rectangles
[i
];
1223 radeon_emit(cmd_buffer
->cs
, S_028210_TL_X(rect
.offset
.x
) | S_028210_TL_Y(rect
.offset
.y
));
1224 radeon_emit(cmd_buffer
->cs
, S_028214_BR_X(rect
.offset
.x
+ rect
.extent
.width
) |
1225 S_028214_BR_Y(rect
.offset
.y
+ rect
.extent
.height
));
1230 radv_emit_line_width(struct radv_cmd_buffer
*cmd_buffer
)
1232 unsigned width
= cmd_buffer
->state
.dynamic
.line_width
* 8;
1234 radeon_set_context_reg(cmd_buffer
->cs
, R_028A08_PA_SU_LINE_CNTL
,
1235 S_028A08_WIDTH(CLAMP(width
, 0, 0xFFF)));
1239 radv_emit_blend_constants(struct radv_cmd_buffer
*cmd_buffer
)
1241 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1243 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028414_CB_BLEND_RED
, 4);
1244 radeon_emit_array(cmd_buffer
->cs
, (uint32_t *)d
->blend_constants
, 4);
1248 radv_emit_stencil(struct radv_cmd_buffer
*cmd_buffer
)
1250 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1252 radeon_set_context_reg_seq(cmd_buffer
->cs
,
1253 R_028430_DB_STENCILREFMASK
, 2);
1254 radeon_emit(cmd_buffer
->cs
,
1255 S_028430_STENCILTESTVAL(d
->stencil_reference
.front
) |
1256 S_028430_STENCILMASK(d
->stencil_compare_mask
.front
) |
1257 S_028430_STENCILWRITEMASK(d
->stencil_write_mask
.front
) |
1258 S_028430_STENCILOPVAL(1));
1259 radeon_emit(cmd_buffer
->cs
,
1260 S_028434_STENCILTESTVAL_BF(d
->stencil_reference
.back
) |
1261 S_028434_STENCILMASK_BF(d
->stencil_compare_mask
.back
) |
1262 S_028434_STENCILWRITEMASK_BF(d
->stencil_write_mask
.back
) |
1263 S_028434_STENCILOPVAL_BF(1));
1267 radv_emit_depth_bounds(struct radv_cmd_buffer
*cmd_buffer
)
1269 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1271 radeon_set_context_reg(cmd_buffer
->cs
, R_028020_DB_DEPTH_BOUNDS_MIN
,
1272 fui(d
->depth_bounds
.min
));
1273 radeon_set_context_reg(cmd_buffer
->cs
, R_028024_DB_DEPTH_BOUNDS_MAX
,
1274 fui(d
->depth_bounds
.max
));
1278 radv_emit_depth_bias(struct radv_cmd_buffer
*cmd_buffer
)
1280 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1281 unsigned slope
= fui(d
->depth_bias
.slope
* 16.0f
);
1282 unsigned bias
= fui(d
->depth_bias
.bias
* cmd_buffer
->state
.offset_scale
);
1285 radeon_set_context_reg_seq(cmd_buffer
->cs
,
1286 R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, 5);
1287 radeon_emit(cmd_buffer
->cs
, fui(d
->depth_bias
.clamp
)); /* CLAMP */
1288 radeon_emit(cmd_buffer
->cs
, slope
); /* FRONT SCALE */
1289 radeon_emit(cmd_buffer
->cs
, bias
); /* FRONT OFFSET */
1290 radeon_emit(cmd_buffer
->cs
, slope
); /* BACK SCALE */
1291 radeon_emit(cmd_buffer
->cs
, bias
); /* BACK OFFSET */
1295 radv_emit_fb_color_state(struct radv_cmd_buffer
*cmd_buffer
,
1297 struct radv_color_buffer_info
*cb
,
1298 struct radv_image_view
*iview
,
1299 VkImageLayout layout
,
1300 bool in_render_loop
)
1302 bool is_vi
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX8
;
1303 uint32_t cb_color_info
= cb
->cb_color_info
;
1304 struct radv_image
*image
= iview
->image
;
1306 if (!radv_layout_dcc_compressed(cmd_buffer
->device
, image
, layout
, in_render_loop
,
1307 radv_image_queue_family_mask(image
,
1308 cmd_buffer
->queue_family_index
,
1309 cmd_buffer
->queue_family_index
))) {
1310 cb_color_info
&= C_028C70_DCC_ENABLE
;
1313 if (radv_image_is_tc_compat_cmask(image
) &&
1314 (radv_is_fmask_decompress_pipeline(cmd_buffer
) ||
1315 radv_is_dcc_decompress_pipeline(cmd_buffer
))) {
1316 /* If this bit is set, the FMASK decompression operation
1317 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1319 cb_color_info
&= C_028C70_FMASK_COMPRESS_1FRAG_ONLY
;
1322 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
1323 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1324 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1325 radeon_emit(cmd_buffer
->cs
, 0);
1326 radeon_emit(cmd_buffer
->cs
, 0);
1327 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1328 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1329 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1330 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1331 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1332 radeon_emit(cmd_buffer
->cs
, 0);
1333 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1334 radeon_emit(cmd_buffer
->cs
, 0);
1336 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, 1);
1337 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
);
1339 radeon_set_context_reg(cmd_buffer
->cs
, R_028E40_CB_COLOR0_BASE_EXT
+ index
* 4,
1340 cb
->cb_color_base
>> 32);
1341 radeon_set_context_reg(cmd_buffer
->cs
, R_028E60_CB_COLOR0_CMASK_BASE_EXT
+ index
* 4,
1342 cb
->cb_color_cmask
>> 32);
1343 radeon_set_context_reg(cmd_buffer
->cs
, R_028E80_CB_COLOR0_FMASK_BASE_EXT
+ index
* 4,
1344 cb
->cb_color_fmask
>> 32);
1345 radeon_set_context_reg(cmd_buffer
->cs
, R_028EA0_CB_COLOR0_DCC_BASE_EXT
+ index
* 4,
1346 cb
->cb_dcc_base
>> 32);
1347 radeon_set_context_reg(cmd_buffer
->cs
, R_028EC0_CB_COLOR0_ATTRIB2
+ index
* 4,
1348 cb
->cb_color_attrib2
);
1349 radeon_set_context_reg(cmd_buffer
->cs
, R_028EE0_CB_COLOR0_ATTRIB3
+ index
* 4,
1350 cb
->cb_color_attrib3
);
1351 } else if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
1352 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1353 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1354 radeon_emit(cmd_buffer
->cs
, S_028C64_BASE_256B(cb
->cb_color_base
>> 32));
1355 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib2
);
1356 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1357 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1358 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1359 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1360 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1361 radeon_emit(cmd_buffer
->cs
, S_028C80_BASE_256B(cb
->cb_color_cmask
>> 32));
1362 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1363 radeon_emit(cmd_buffer
->cs
, S_028C88_BASE_256B(cb
->cb_color_fmask
>> 32));
1365 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, 2);
1366 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
);
1367 radeon_emit(cmd_buffer
->cs
, S_028C98_BASE_256B(cb
->cb_dcc_base
>> 32));
1369 radeon_set_context_reg(cmd_buffer
->cs
, R_0287A0_CB_MRT0_EPITCH
+ index
* 4,
1372 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1373 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1374 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_pitch
);
1375 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_slice
);
1376 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1377 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1378 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1379 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1380 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1381 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask_slice
);
1382 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1383 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask_slice
);
1385 if (is_vi
) { /* DCC BASE */
1386 radeon_set_context_reg(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, cb
->cb_dcc_base
);
1390 if (radv_dcc_enabled(image
, iview
->base_mip
)) {
1391 /* Drawing with DCC enabled also compresses colorbuffers. */
1392 VkImageSubresourceRange range
= {
1393 .aspectMask
= iview
->aspect_mask
,
1394 .baseMipLevel
= iview
->base_mip
,
1395 .levelCount
= iview
->level_count
,
1396 .baseArrayLayer
= iview
->base_layer
,
1397 .layerCount
= iview
->layer_count
,
1400 radv_update_dcc_metadata(cmd_buffer
, image
, &range
, true);
1405 radv_update_zrange_precision(struct radv_cmd_buffer
*cmd_buffer
,
1406 struct radv_ds_buffer_info
*ds
,
1407 const struct radv_image_view
*iview
,
1408 VkImageLayout layout
,
1409 bool in_render_loop
, bool requires_cond_exec
)
1411 const struct radv_image
*image
= iview
->image
;
1412 uint32_t db_z_info
= ds
->db_z_info
;
1413 uint32_t db_z_info_reg
;
1415 if (!cmd_buffer
->device
->physical_device
->rad_info
.has_tc_compat_zrange_bug
||
1416 !radv_image_is_tc_compat_htile(image
))
1419 if (!radv_layout_has_htile(image
, layout
, in_render_loop
,
1420 radv_image_queue_family_mask(image
,
1421 cmd_buffer
->queue_family_index
,
1422 cmd_buffer
->queue_family_index
))) {
1423 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
1426 db_z_info
&= C_028040_ZRANGE_PRECISION
;
1428 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
1429 db_z_info_reg
= R_028038_DB_Z_INFO
;
1431 db_z_info_reg
= R_028040_DB_Z_INFO
;
1434 /* When we don't know the last fast clear value we need to emit a
1435 * conditional packet that will eventually skip the following
1436 * SET_CONTEXT_REG packet.
1438 if (requires_cond_exec
) {
1439 uint64_t va
= radv_get_tc_compat_zrange_va(image
, iview
->base_mip
);
1441 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_COND_EXEC
, 3, 0));
1442 radeon_emit(cmd_buffer
->cs
, va
);
1443 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1444 radeon_emit(cmd_buffer
->cs
, 0);
1445 radeon_emit(cmd_buffer
->cs
, 3); /* SET_CONTEXT_REG size */
1448 radeon_set_context_reg(cmd_buffer
->cs
, db_z_info_reg
, db_z_info
);
1452 radv_emit_fb_ds_state(struct radv_cmd_buffer
*cmd_buffer
,
1453 struct radv_ds_buffer_info
*ds
,
1454 struct radv_image_view
*iview
,
1455 VkImageLayout layout
,
1456 bool in_render_loop
)
1458 const struct radv_image
*image
= iview
->image
;
1459 uint32_t db_z_info
= ds
->db_z_info
;
1460 uint32_t db_stencil_info
= ds
->db_stencil_info
;
1462 if (!radv_layout_has_htile(image
, layout
, in_render_loop
,
1463 radv_image_queue_family_mask(image
,
1464 cmd_buffer
->queue_family_index
,
1465 cmd_buffer
->queue_family_index
))) {
1466 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
1467 db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
1470 radeon_set_context_reg(cmd_buffer
->cs
, R_028008_DB_DEPTH_VIEW
, ds
->db_depth_view
);
1471 radeon_set_context_reg(cmd_buffer
->cs
, R_028ABC_DB_HTILE_SURFACE
, ds
->db_htile_surface
);
1473 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
1474 radeon_set_context_reg(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, ds
->db_htile_data_base
);
1475 radeon_set_context_reg(cmd_buffer
->cs
, R_02801C_DB_DEPTH_SIZE_XY
, ds
->db_depth_size
);
1477 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_02803C_DB_DEPTH_INFO
, 7);
1478 radeon_emit(cmd_buffer
->cs
, S_02803C_RESOURCE_LEVEL(1));
1479 radeon_emit(cmd_buffer
->cs
, db_z_info
);
1480 radeon_emit(cmd_buffer
->cs
, db_stencil_info
);
1481 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
);
1482 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
);
1483 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
);
1484 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
);
1486 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028068_DB_Z_READ_BASE_HI
, 5);
1487 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
>> 32);
1488 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
>> 32);
1489 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
>> 32);
1490 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
>> 32);
1491 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
>> 32);
1492 } else if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
1493 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
1494 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
);
1495 radeon_emit(cmd_buffer
->cs
, S_028018_BASE_HI(ds
->db_htile_data_base
>> 32));
1496 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
);
1498 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 10);
1499 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* DB_Z_INFO */
1500 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* DB_STENCIL_INFO */
1501 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* DB_Z_READ_BASE */
1502 radeon_emit(cmd_buffer
->cs
, S_028044_BASE_HI(ds
->db_z_read_base
>> 32)); /* DB_Z_READ_BASE_HI */
1503 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* DB_STENCIL_READ_BASE */
1504 radeon_emit(cmd_buffer
->cs
, S_02804C_BASE_HI(ds
->db_stencil_read_base
>> 32)); /* DB_STENCIL_READ_BASE_HI */
1505 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* DB_Z_WRITE_BASE */
1506 radeon_emit(cmd_buffer
->cs
, S_028054_BASE_HI(ds
->db_z_write_base
>> 32)); /* DB_Z_WRITE_BASE_HI */
1507 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* DB_STENCIL_WRITE_BASE */
1508 radeon_emit(cmd_buffer
->cs
, S_02805C_BASE_HI(ds
->db_stencil_write_base
>> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1510 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028068_DB_Z_INFO2
, 2);
1511 radeon_emit(cmd_buffer
->cs
, ds
->db_z_info2
);
1512 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_info2
);
1514 radeon_set_context_reg(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, ds
->db_htile_data_base
);
1516 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_02803C_DB_DEPTH_INFO
, 9);
1517 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_info
); /* R_02803C_DB_DEPTH_INFO */
1518 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* R_028040_DB_Z_INFO */
1519 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* R_028044_DB_STENCIL_INFO */
1520 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* R_028048_DB_Z_READ_BASE */
1521 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* R_02804C_DB_STENCIL_READ_BASE */
1522 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* R_028050_DB_Z_WRITE_BASE */
1523 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* R_028054_DB_STENCIL_WRITE_BASE */
1524 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
); /* R_028058_DB_DEPTH_SIZE */
1525 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_slice
); /* R_02805C_DB_DEPTH_SLICE */
1529 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1530 radv_update_zrange_precision(cmd_buffer
, ds
, iview
, layout
,
1531 in_render_loop
, true);
1533 radeon_set_context_reg(cmd_buffer
->cs
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1534 ds
->pa_su_poly_offset_db_fmt_cntl
);
1538 * Update the fast clear depth/stencil values if the image is bound as a
1539 * depth/stencil buffer.
1542 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer
*cmd_buffer
,
1543 const struct radv_image_view
*iview
,
1544 VkClearDepthStencilValue ds_clear_value
,
1545 VkImageAspectFlags aspects
)
1547 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1548 const struct radv_image
*image
= iview
->image
;
1549 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1552 if (!cmd_buffer
->state
.attachments
|| !subpass
)
1555 if (!subpass
->depth_stencil_attachment
)
1558 att_idx
= subpass
->depth_stencil_attachment
->attachment
;
1559 if (cmd_buffer
->state
.attachments
[att_idx
].iview
->image
!= image
)
1562 if (aspects
== (VK_IMAGE_ASPECT_DEPTH_BIT
|
1563 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
1564 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 2);
1565 radeon_emit(cs
, ds_clear_value
.stencil
);
1566 radeon_emit(cs
, fui(ds_clear_value
.depth
));
1567 } else if (aspects
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
1568 radeon_set_context_reg_seq(cs
, R_02802C_DB_DEPTH_CLEAR
, 1);
1569 radeon_emit(cs
, fui(ds_clear_value
.depth
));
1571 assert(aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
1572 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 1);
1573 radeon_emit(cs
, ds_clear_value
.stencil
);
1576 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1577 * only needed when clearing Z to 0.0.
1579 if ((aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
1580 ds_clear_value
.depth
== 0.0) {
1581 VkImageLayout layout
= subpass
->depth_stencil_attachment
->layout
;
1582 bool in_render_loop
= subpass
->depth_stencil_attachment
->in_render_loop
;
1584 radv_update_zrange_precision(cmd_buffer
, &cmd_buffer
->state
.attachments
[att_idx
].ds
,
1585 iview
, layout
, in_render_loop
, false);
1588 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1592 * Set the clear depth/stencil values to the image's metadata.
1595 radv_set_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1596 struct radv_image
*image
,
1597 const VkImageSubresourceRange
*range
,
1598 VkClearDepthStencilValue ds_clear_value
,
1599 VkImageAspectFlags aspects
)
1601 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1602 uint64_t va
= radv_get_ds_clear_value_va(image
, range
->baseMipLevel
);
1603 uint32_t level_count
= radv_get_levelCount(image
, range
);
1605 if (aspects
== (VK_IMAGE_ASPECT_DEPTH_BIT
|
1606 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
1607 /* Use the fastest way when both aspects are used. */
1608 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + 2 * level_count
, cmd_buffer
->state
.predicating
));
1609 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
1610 S_370_WR_CONFIRM(1) |
1611 S_370_ENGINE_SEL(V_370_PFP
));
1612 radeon_emit(cs
, va
);
1613 radeon_emit(cs
, va
>> 32);
1615 for (uint32_t l
= 0; l
< level_count
; l
++) {
1616 radeon_emit(cs
, ds_clear_value
.stencil
);
1617 radeon_emit(cs
, fui(ds_clear_value
.depth
));
1620 /* Otherwise we need one WRITE_DATA packet per level. */
1621 for (uint32_t l
= 0; l
< level_count
; l
++) {
1622 uint64_t va
= radv_get_ds_clear_value_va(image
, range
->baseMipLevel
+ l
);
1625 if (aspects
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
1626 value
= fui(ds_clear_value
.depth
);
1629 assert(aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
1630 value
= ds_clear_value
.stencil
;
1633 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, cmd_buffer
->state
.predicating
));
1634 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
1635 S_370_WR_CONFIRM(1) |
1636 S_370_ENGINE_SEL(V_370_PFP
));
1637 radeon_emit(cs
, va
);
1638 radeon_emit(cs
, va
>> 32);
1639 radeon_emit(cs
, value
);
1645 * Update the TC-compat metadata value for this image.
1648 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1649 struct radv_image
*image
,
1650 const VkImageSubresourceRange
*range
,
1653 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1655 if (!cmd_buffer
->device
->physical_device
->rad_info
.has_tc_compat_zrange_bug
)
1658 uint64_t va
= radv_get_tc_compat_zrange_va(image
, range
->baseMipLevel
);
1659 uint32_t level_count
= radv_get_levelCount(image
, range
);
1661 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + level_count
, cmd_buffer
->state
.predicating
));
1662 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
1663 S_370_WR_CONFIRM(1) |
1664 S_370_ENGINE_SEL(V_370_PFP
));
1665 radeon_emit(cs
, va
);
1666 radeon_emit(cs
, va
>> 32);
1668 for (uint32_t l
= 0; l
< level_count
; l
++)
1669 radeon_emit(cs
, value
);
1673 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1674 const struct radv_image_view
*iview
,
1675 VkClearDepthStencilValue ds_clear_value
)
1677 VkImageSubresourceRange range
= {
1678 .aspectMask
= iview
->aspect_mask
,
1679 .baseMipLevel
= iview
->base_mip
,
1680 .levelCount
= iview
->level_count
,
1681 .baseArrayLayer
= iview
->base_layer
,
1682 .layerCount
= iview
->layer_count
,
1686 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1687 * depth clear value is 0.0f.
1689 cond_val
= ds_clear_value
.depth
== 0.0f
? UINT_MAX
: 0;
1691 radv_set_tc_compat_zrange_metadata(cmd_buffer
, iview
->image
, &range
,
1696 * Update the clear depth/stencil values for this image.
1699 radv_update_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1700 const struct radv_image_view
*iview
,
1701 VkClearDepthStencilValue ds_clear_value
,
1702 VkImageAspectFlags aspects
)
1704 VkImageSubresourceRange range
= {
1705 .aspectMask
= iview
->aspect_mask
,
1706 .baseMipLevel
= iview
->base_mip
,
1707 .levelCount
= iview
->level_count
,
1708 .baseArrayLayer
= iview
->base_layer
,
1709 .layerCount
= iview
->layer_count
,
1711 struct radv_image
*image
= iview
->image
;
1713 assert(radv_image_has_htile(image
));
1715 radv_set_ds_clear_metadata(cmd_buffer
, iview
->image
, &range
,
1716 ds_clear_value
, aspects
);
1718 if (radv_image_is_tc_compat_htile(image
) &&
1719 (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
1720 radv_update_tc_compat_zrange_metadata(cmd_buffer
, iview
,
1724 radv_update_bound_fast_clear_ds(cmd_buffer
, iview
, ds_clear_value
,
1729 * Load the clear depth/stencil values from the image's metadata.
1732 radv_load_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1733 const struct radv_image_view
*iview
)
1735 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1736 const struct radv_image
*image
= iview
->image
;
1737 VkImageAspectFlags aspects
= vk_format_aspects(image
->vk_format
);
1738 uint64_t va
= radv_get_ds_clear_value_va(image
, iview
->base_mip
);
1739 unsigned reg_offset
= 0, reg_count
= 0;
1741 if (!radv_image_has_htile(image
))
1744 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1750 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1753 uint32_t reg
= R_028028_DB_STENCIL_CLEAR
+ 4 * reg_offset
;
1755 if (cmd_buffer
->device
->physical_device
->rad_info
.has_load_ctx_reg_pkt
) {
1756 radeon_emit(cs
, PKT3(PKT3_LOAD_CONTEXT_REG
, 3, 0));
1757 radeon_emit(cs
, va
);
1758 radeon_emit(cs
, va
>> 32);
1759 radeon_emit(cs
, (reg
- SI_CONTEXT_REG_OFFSET
) >> 2);
1760 radeon_emit(cs
, reg_count
);
1762 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
1763 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
1764 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1765 (reg_count
== 2 ? COPY_DATA_COUNT_SEL
: 0));
1766 radeon_emit(cs
, va
);
1767 radeon_emit(cs
, va
>> 32);
1768 radeon_emit(cs
, reg
>> 2);
1771 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
1777 * With DCC some colors don't require CMASK elimination before being
1778 * used as a texture. This sets a predicate value to determine if the
1779 * cmask eliminate is required.
1782 radv_update_fce_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1783 struct radv_image
*image
,
1784 const VkImageSubresourceRange
*range
, bool value
)
1786 uint64_t pred_val
= value
;
1787 uint64_t va
= radv_image_get_fce_pred_va(image
, range
->baseMipLevel
);
1788 uint32_t level_count
= radv_get_levelCount(image
, range
);
1789 uint32_t count
= 2 * level_count
;
1791 assert(radv_dcc_enabled(image
, range
->baseMipLevel
));
1793 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, 0));
1794 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM
) |
1795 S_370_WR_CONFIRM(1) |
1796 S_370_ENGINE_SEL(V_370_PFP
));
1797 radeon_emit(cmd_buffer
->cs
, va
);
1798 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1800 for (uint32_t l
= 0; l
< level_count
; l
++) {
1801 radeon_emit(cmd_buffer
->cs
, pred_val
);
1802 radeon_emit(cmd_buffer
->cs
, pred_val
>> 32);
1807 * Update the DCC predicate to reflect the compression state.
1810 radv_update_dcc_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1811 struct radv_image
*image
,
1812 const VkImageSubresourceRange
*range
, bool value
)
1814 uint64_t pred_val
= value
;
1815 uint64_t va
= radv_image_get_dcc_pred_va(image
, range
->baseMipLevel
);
1816 uint32_t level_count
= radv_get_levelCount(image
, range
);
1817 uint32_t count
= 2 * level_count
;
1819 assert(radv_dcc_enabled(image
, range
->baseMipLevel
));
1821 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, 0));
1822 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM
) |
1823 S_370_WR_CONFIRM(1) |
1824 S_370_ENGINE_SEL(V_370_PFP
));
1825 radeon_emit(cmd_buffer
->cs
, va
);
1826 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1828 for (uint32_t l
= 0; l
< level_count
; l
++) {
1829 radeon_emit(cmd_buffer
->cs
, pred_val
);
1830 radeon_emit(cmd_buffer
->cs
, pred_val
>> 32);
1835 * Update the fast clear color values if the image is bound as a color buffer.
1838 radv_update_bound_fast_clear_color(struct radv_cmd_buffer
*cmd_buffer
,
1839 struct radv_image
*image
,
1841 uint32_t color_values
[2])
1843 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1844 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1847 if (!cmd_buffer
->state
.attachments
|| !subpass
)
1850 att_idx
= subpass
->color_attachments
[cb_idx
].attachment
;
1851 if (att_idx
== VK_ATTACHMENT_UNUSED
)
1854 if (cmd_buffer
->state
.attachments
[att_idx
].iview
->image
!= image
)
1857 radeon_set_context_reg_seq(cs
, R_028C8C_CB_COLOR0_CLEAR_WORD0
+ cb_idx
* 0x3c, 2);
1858 radeon_emit(cs
, color_values
[0]);
1859 radeon_emit(cs
, color_values
[1]);
1861 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1865 * Set the clear color values to the image's metadata.
1868 radv_set_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1869 struct radv_image
*image
,
1870 const VkImageSubresourceRange
*range
,
1871 uint32_t color_values
[2])
1873 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1874 uint64_t va
= radv_image_get_fast_clear_va(image
, range
->baseMipLevel
);
1875 uint32_t level_count
= radv_get_levelCount(image
, range
);
1876 uint32_t count
= 2 * level_count
;
1878 assert(radv_image_has_cmask(image
) ||
1879 radv_dcc_enabled(image
, range
->baseMipLevel
));
1881 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, cmd_buffer
->state
.predicating
));
1882 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
1883 S_370_WR_CONFIRM(1) |
1884 S_370_ENGINE_SEL(V_370_PFP
));
1885 radeon_emit(cs
, va
);
1886 radeon_emit(cs
, va
>> 32);
1888 for (uint32_t l
= 0; l
< level_count
; l
++) {
1889 radeon_emit(cs
, color_values
[0]);
1890 radeon_emit(cs
, color_values
[1]);
1895 * Update the clear color values for this image.
1898 radv_update_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1899 const struct radv_image_view
*iview
,
1901 uint32_t color_values
[2])
1903 struct radv_image
*image
= iview
->image
;
1904 VkImageSubresourceRange range
= {
1905 .aspectMask
= iview
->aspect_mask
,
1906 .baseMipLevel
= iview
->base_mip
,
1907 .levelCount
= iview
->level_count
,
1908 .baseArrayLayer
= iview
->base_layer
,
1909 .layerCount
= iview
->layer_count
,
1912 assert(radv_image_has_cmask(image
) ||
1913 radv_dcc_enabled(image
, iview
->base_mip
));
1915 radv_set_color_clear_metadata(cmd_buffer
, image
, &range
, color_values
);
1917 radv_update_bound_fast_clear_color(cmd_buffer
, image
, cb_idx
,
1922 * Load the clear color values from the image's metadata.
1925 radv_load_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1926 struct radv_image_view
*iview
,
1929 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1930 struct radv_image
*image
= iview
->image
;
1931 uint64_t va
= radv_image_get_fast_clear_va(image
, iview
->base_mip
);
1933 if (!radv_image_has_cmask(image
) &&
1934 !radv_dcc_enabled(image
, iview
->base_mip
))
1937 uint32_t reg
= R_028C8C_CB_COLOR0_CLEAR_WORD0
+ cb_idx
* 0x3c;
1939 if (cmd_buffer
->device
->physical_device
->rad_info
.has_load_ctx_reg_pkt
) {
1940 radeon_emit(cs
, PKT3(PKT3_LOAD_CONTEXT_REG
, 3, cmd_buffer
->state
.predicating
));
1941 radeon_emit(cs
, va
);
1942 radeon_emit(cs
, va
>> 32);
1943 radeon_emit(cs
, (reg
- SI_CONTEXT_REG_OFFSET
) >> 2);
1946 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, cmd_buffer
->state
.predicating
));
1947 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
1948 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1949 COPY_DATA_COUNT_SEL
);
1950 radeon_emit(cs
, va
);
1951 radeon_emit(cs
, va
>> 32);
1952 radeon_emit(cs
, reg
>> 2);
1955 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, cmd_buffer
->state
.predicating
));
1961 radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer
)
1964 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1965 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1967 /* this may happen for inherited secondary recording */
1971 for (i
= 0; i
< 8; ++i
) {
1972 if (i
>= subpass
->color_count
|| subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
1973 radeon_set_context_reg(cmd_buffer
->cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
1974 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
1978 int idx
= subpass
->color_attachments
[i
].attachment
;
1979 struct radv_image_view
*iview
= cmd_buffer
->state
.attachments
[idx
].iview
;
1980 VkImageLayout layout
= subpass
->color_attachments
[i
].layout
;
1981 bool in_render_loop
= subpass
->color_attachments
[i
].in_render_loop
;
1983 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, iview
->bo
);
1985 assert(iview
->aspect_mask
& (VK_IMAGE_ASPECT_COLOR_BIT
| VK_IMAGE_ASPECT_PLANE_0_BIT
|
1986 VK_IMAGE_ASPECT_PLANE_1_BIT
| VK_IMAGE_ASPECT_PLANE_2_BIT
));
1987 radv_emit_fb_color_state(cmd_buffer
, i
, &cmd_buffer
->state
.attachments
[idx
].cb
, iview
, layout
, in_render_loop
);
1989 radv_load_color_clear_metadata(cmd_buffer
, iview
, i
);
1992 if (subpass
->depth_stencil_attachment
) {
1993 int idx
= subpass
->depth_stencil_attachment
->attachment
;
1994 VkImageLayout layout
= subpass
->depth_stencil_attachment
->layout
;
1995 bool in_render_loop
= subpass
->depth_stencil_attachment
->in_render_loop
;
1996 struct radv_image_view
*iview
= cmd_buffer
->state
.attachments
[idx
].iview
;
1997 struct radv_image
*image
= iview
->image
;
1998 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, cmd_buffer
->state
.attachments
[idx
].iview
->bo
);
1999 ASSERTED
uint32_t queue_mask
= radv_image_queue_family_mask(image
,
2000 cmd_buffer
->queue_family_index
,
2001 cmd_buffer
->queue_family_index
);
2002 /* We currently don't support writing decompressed HTILE */
2003 assert(radv_layout_has_htile(image
, layout
, in_render_loop
, queue_mask
) ==
2004 radv_layout_is_htile_compressed(image
, layout
, in_render_loop
, queue_mask
));
2006 radv_emit_fb_ds_state(cmd_buffer
, &cmd_buffer
->state
.attachments
[idx
].ds
, iview
, layout
, in_render_loop
);
2008 if (cmd_buffer
->state
.attachments
[idx
].ds
.offset_scale
!= cmd_buffer
->state
.offset_scale
) {
2009 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
2010 cmd_buffer
->state
.offset_scale
= cmd_buffer
->state
.attachments
[idx
].ds
.offset_scale
;
2012 radv_load_ds_clear_metadata(cmd_buffer
, iview
);
2014 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
)
2015 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 2);
2017 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028040_DB_Z_INFO
, 2);
2019 radeon_emit(cmd_buffer
->cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
2020 radeon_emit(cmd_buffer
->cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
2022 radeon_set_context_reg(cmd_buffer
->cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
2023 S_028208_BR_X(framebuffer
->width
) |
2024 S_028208_BR_Y(framebuffer
->height
));
2026 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX8
) {
2027 bool disable_constant_encode
=
2028 cmd_buffer
->device
->physical_device
->rad_info
.has_dcc_constant_encode
;
2029 enum chip_class chip_class
=
2030 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
;
2031 uint8_t watermark
= chip_class
>= GFX10
? 6 : 4;
2033 radeon_set_context_reg(cmd_buffer
->cs
, R_028424_CB_DCC_CONTROL
,
2034 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class
<= GFX9
) |
2035 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark
) |
2036 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode
));
2039 if (cmd_buffer
->device
->dfsm_allowed
) {
2040 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2041 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
2044 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_FRAMEBUFFER
;
2048 radv_emit_index_buffer(struct radv_cmd_buffer
*cmd_buffer
)
2050 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
2051 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2053 if (state
->index_type
!= state
->last_index_type
) {
2054 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2055 radeon_set_uconfig_reg_idx(cmd_buffer
->device
->physical_device
,
2056 cs
, R_03090C_VGT_INDEX_TYPE
,
2057 2, state
->index_type
);
2059 radeon_emit(cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
2060 radeon_emit(cs
, state
->index_type
);
2063 state
->last_index_type
= state
->index_type
;
2066 radeon_emit(cs
, PKT3(PKT3_INDEX_BASE
, 1, 0));
2067 radeon_emit(cs
, state
->index_va
);
2068 radeon_emit(cs
, state
->index_va
>> 32);
2070 radeon_emit(cs
, PKT3(PKT3_INDEX_BUFFER_SIZE
, 0, 0));
2071 radeon_emit(cs
, state
->max_index_count
);
2073 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_INDEX_BUFFER
;
2076 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
)
2078 bool has_perfect_queries
= cmd_buffer
->state
.perfect_occlusion_queries_enabled
;
2079 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
2080 uint32_t pa_sc_mode_cntl_1
=
2081 pipeline
? pipeline
->graphics
.ms
.pa_sc_mode_cntl_1
: 0;
2082 uint32_t db_count_control
;
2084 if(!cmd_buffer
->state
.active_occlusion_queries
) {
2085 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2086 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1
) &&
2087 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
&&
2088 has_perfect_queries
) {
2089 /* Re-enable out-of-order rasterization if the
2090 * bound pipeline supports it and if it's has
2091 * been disabled before starting any perfect
2092 * occlusion queries.
2094 radeon_set_context_reg(cmd_buffer
->cs
,
2095 R_028A4C_PA_SC_MODE_CNTL_1
,
2099 db_count_control
= S_028004_ZPASS_INCREMENT_DISABLE(1);
2101 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
2102 uint32_t sample_rate
= subpass
? util_logbase2(subpass
->max_sample_count
) : 0;
2103 bool gfx10_perfect
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&& has_perfect_queries
;
2105 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2107 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries
) |
2108 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect
) |
2109 S_028004_SAMPLE_RATE(sample_rate
) |
2110 S_028004_ZPASS_ENABLE(1) |
2111 S_028004_SLICE_EVEN_ENABLE(1) |
2112 S_028004_SLICE_ODD_ENABLE(1);
2114 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1
) &&
2115 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
&&
2116 has_perfect_queries
) {
2117 /* If the bound pipeline has enabled
2118 * out-of-order rasterization, we should
2119 * disable it before starting any perfect
2120 * occlusion queries.
2122 pa_sc_mode_cntl_1
&= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE
;
2124 radeon_set_context_reg(cmd_buffer
->cs
,
2125 R_028A4C_PA_SC_MODE_CNTL_1
,
2129 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(1) |
2130 S_028004_SAMPLE_RATE(sample_rate
);
2134 radeon_set_context_reg(cmd_buffer
->cs
, R_028004_DB_COUNT_CONTROL
, db_count_control
);
2136 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
2140 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
)
2142 uint32_t states
= cmd_buffer
->state
.dirty
& cmd_buffer
->state
.emitted_pipeline
->graphics
.needed_dynamic_state
;
2144 if (states
& (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
))
2145 radv_emit_viewport(cmd_buffer
);
2147 if (states
& (RADV_CMD_DIRTY_DYNAMIC_SCISSOR
| RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
) &&
2148 !cmd_buffer
->device
->physical_device
->rad_info
.has_gfx9_scissor_bug
)
2149 radv_emit_scissor(cmd_buffer
);
2151 if (states
& RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
)
2152 radv_emit_line_width(cmd_buffer
);
2154 if (states
& RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
)
2155 radv_emit_blend_constants(cmd_buffer
);
2157 if (states
& (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
|
2158 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
|
2159 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
))
2160 radv_emit_stencil(cmd_buffer
);
2162 if (states
& RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
)
2163 radv_emit_depth_bounds(cmd_buffer
);
2165 if (states
& RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
)
2166 radv_emit_depth_bias(cmd_buffer
);
2168 if (states
& RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
)
2169 radv_emit_discard_rectangle(cmd_buffer
);
2171 if (states
& RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS
)
2172 radv_emit_sample_locations(cmd_buffer
);
2174 cmd_buffer
->state
.dirty
&= ~states
;
2178 radv_flush_push_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
2179 VkPipelineBindPoint bind_point
)
2181 struct radv_descriptor_state
*descriptors_state
=
2182 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2183 struct radv_descriptor_set
*set
= &descriptors_state
->push_set
.set
;
2186 if (!radv_cmd_buffer_upload_data(cmd_buffer
, set
->size
, 32,
2191 set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2192 set
->va
+= bo_offset
;
2196 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer
*cmd_buffer
,
2197 VkPipelineBindPoint bind_point
)
2199 struct radv_descriptor_state
*descriptors_state
=
2200 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2201 uint32_t size
= MAX_SETS
* 4;
2205 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
,
2206 256, &offset
, &ptr
))
2209 for (unsigned i
= 0; i
< MAX_SETS
; i
++) {
2210 uint32_t *uptr
= ((uint32_t *)ptr
) + i
;
2211 uint64_t set_va
= 0;
2212 struct radv_descriptor_set
*set
= descriptors_state
->sets
[i
];
2213 if (descriptors_state
->valid
& (1u << i
))
2215 uptr
[0] = set_va
& 0xffffffff;
2218 uint64_t va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2221 if (cmd_buffer
->state
.pipeline
) {
2222 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_VERTEX
])
2223 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
2224 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2226 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_FRAGMENT
])
2227 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_FRAGMENT
,
2228 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2230 if (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
))
2231 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
2232 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2234 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
2235 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_CTRL
,
2236 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2238 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
2239 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_EVAL
,
2240 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2243 if (cmd_buffer
->state
.compute_pipeline
)
2244 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
, MESA_SHADER_COMPUTE
,
2245 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2249 radv_flush_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
2250 VkShaderStageFlags stages
)
2252 VkPipelineBindPoint bind_point
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
?
2253 VK_PIPELINE_BIND_POINT_COMPUTE
:
2254 VK_PIPELINE_BIND_POINT_GRAPHICS
;
2255 struct radv_descriptor_state
*descriptors_state
=
2256 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2257 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2258 bool flush_indirect_descriptors
;
2260 if (!descriptors_state
->dirty
)
2263 if (descriptors_state
->push_dirty
)
2264 radv_flush_push_descriptors(cmd_buffer
, bind_point
);
2266 flush_indirect_descriptors
=
2267 (bind_point
== VK_PIPELINE_BIND_POINT_GRAPHICS
&&
2268 state
->pipeline
&& state
->pipeline
->need_indirect_descriptor_sets
) ||
2269 (bind_point
== VK_PIPELINE_BIND_POINT_COMPUTE
&&
2270 state
->compute_pipeline
&& state
->compute_pipeline
->need_indirect_descriptor_sets
);
2272 if (flush_indirect_descriptors
)
2273 radv_flush_indirect_descriptor_sets(cmd_buffer
, bind_point
);
2275 ASSERTED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
2277 MAX_SETS
* MESA_SHADER_STAGES
* 4);
2279 if (cmd_buffer
->state
.pipeline
) {
2280 radv_foreach_stage(stage
, stages
) {
2281 if (!cmd_buffer
->state
.pipeline
->shaders
[stage
])
2284 radv_emit_descriptor_pointers(cmd_buffer
,
2285 cmd_buffer
->state
.pipeline
,
2286 descriptors_state
, stage
);
2290 if (cmd_buffer
->state
.compute_pipeline
&&
2291 (stages
& VK_SHADER_STAGE_COMPUTE_BIT
)) {
2292 radv_emit_descriptor_pointers(cmd_buffer
,
2293 cmd_buffer
->state
.compute_pipeline
,
2295 MESA_SHADER_COMPUTE
);
2298 descriptors_state
->dirty
= 0;
2299 descriptors_state
->push_dirty
= false;
2301 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2303 if (unlikely(cmd_buffer
->device
->trace_bo
))
2304 radv_save_descriptors(cmd_buffer
, bind_point
);
2308 radv_flush_constants(struct radv_cmd_buffer
*cmd_buffer
,
2309 VkShaderStageFlags stages
)
2311 struct radv_pipeline
*pipeline
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
2312 ? cmd_buffer
->state
.compute_pipeline
2313 : cmd_buffer
->state
.pipeline
;
2314 VkPipelineBindPoint bind_point
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
?
2315 VK_PIPELINE_BIND_POINT_COMPUTE
:
2316 VK_PIPELINE_BIND_POINT_GRAPHICS
;
2317 struct radv_descriptor_state
*descriptors_state
=
2318 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2319 struct radv_pipeline_layout
*layout
= pipeline
->layout
;
2320 struct radv_shader_variant
*shader
, *prev_shader
;
2321 bool need_push_constants
= false;
2326 stages
&= cmd_buffer
->push_constant_stages
;
2328 (!layout
->push_constant_size
&& !layout
->dynamic_offset_count
))
2331 radv_foreach_stage(stage
, stages
) {
2332 shader
= radv_get_shader(pipeline
, stage
);
2336 need_push_constants
|= shader
->info
.loads_push_constants
;
2337 need_push_constants
|= shader
->info
.loads_dynamic_offsets
;
2339 uint8_t base
= shader
->info
.base_inline_push_consts
;
2340 uint8_t count
= shader
->info
.num_inline_push_consts
;
2342 radv_emit_inline_push_consts(cmd_buffer
, pipeline
, stage
,
2343 AC_UD_INLINE_PUSH_CONSTANTS
,
2345 (uint32_t *)&cmd_buffer
->push_constants
[base
* 4]);
2348 if (need_push_constants
) {
2349 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, layout
->push_constant_size
+
2350 16 * layout
->dynamic_offset_count
,
2351 256, &offset
, &ptr
))
2354 memcpy(ptr
, cmd_buffer
->push_constants
, layout
->push_constant_size
);
2355 memcpy((char*)ptr
+ layout
->push_constant_size
,
2356 descriptors_state
->dynamic_buffers
,
2357 16 * layout
->dynamic_offset_count
);
2359 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2362 ASSERTED
unsigned cdw_max
=
2363 radeon_check_space(cmd_buffer
->device
->ws
,
2364 cmd_buffer
->cs
, MESA_SHADER_STAGES
* 4);
2367 radv_foreach_stage(stage
, stages
) {
2368 shader
= radv_get_shader(pipeline
, stage
);
2370 /* Avoid redundantly emitting the address for merged stages. */
2371 if (shader
&& shader
!= prev_shader
) {
2372 radv_emit_userdata_address(cmd_buffer
, pipeline
, stage
,
2373 AC_UD_PUSH_CONSTANTS
, va
);
2375 prev_shader
= shader
;
2378 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2381 cmd_buffer
->push_constant_stages
&= ~stages
;
2385 radv_flush_vertex_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
2386 bool pipeline_is_dirty
)
2388 if ((pipeline_is_dirty
||
2389 (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_VERTEX_BUFFER
)) &&
2390 cmd_buffer
->state
.pipeline
->num_vertex_bindings
&&
2391 radv_get_shader(cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
)->info
.vs
.has_vertex_buffers
) {
2395 uint32_t count
= cmd_buffer
->state
.pipeline
->num_vertex_bindings
;
2398 /* allocate some descriptor state for vertex buffers */
2399 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, count
* 16, 256,
2400 &vb_offset
, &vb_ptr
))
2403 for (i
= 0; i
< count
; i
++) {
2404 uint32_t *desc
= &((uint32_t *)vb_ptr
)[i
* 4];
2406 struct radv_buffer
*buffer
= cmd_buffer
->vertex_bindings
[i
].buffer
;
2407 uint32_t stride
= cmd_buffer
->state
.pipeline
->binding_stride
[i
];
2408 unsigned num_records
;
2413 va
= radv_buffer_get_va(buffer
->bo
);
2415 offset
= cmd_buffer
->vertex_bindings
[i
].offset
;
2416 va
+= offset
+ buffer
->offset
;
2418 num_records
= buffer
->size
- offset
;
2419 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
!= GFX8
&& stride
)
2420 num_records
/= stride
;
2423 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) | S_008F04_STRIDE(stride
);
2424 desc
[2] = num_records
;
2425 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2426 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2427 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2428 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
2430 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2431 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT
) |
2432 S_008F0C_OOB_SELECT(1) |
2433 S_008F0C_RESOURCE_LEVEL(1);
2435 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT
) |
2436 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2440 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2443 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
2444 AC_UD_VS_VERTEX_BUFFERS
, va
);
2446 cmd_buffer
->state
.vb_va
= va
;
2447 cmd_buffer
->state
.vb_size
= count
* 16;
2448 cmd_buffer
->state
.prefetch_L2_mask
|= RADV_PREFETCH_VBO_DESCRIPTORS
;
2450 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_VERTEX_BUFFER
;
2454 radv_emit_streamout_buffers(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
)
2456 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
2457 struct radv_userdata_info
*loc
;
2460 for (unsigned stage
= 0; stage
< MESA_SHADER_STAGES
; ++stage
) {
2461 if (!radv_get_shader(pipeline
, stage
))
2464 loc
= radv_lookup_user_sgpr(pipeline
, stage
,
2465 AC_UD_STREAMOUT_BUFFERS
);
2466 if (loc
->sgpr_idx
== -1)
2469 base_reg
= pipeline
->user_data_0
[stage
];
2471 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
2472 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
2475 if (radv_pipeline_has_gs_copy_shader(pipeline
)) {
2476 loc
= &pipeline
->gs_copy_shader
->info
.user_sgprs_locs
.shader_data
[AC_UD_STREAMOUT_BUFFERS
];
2477 if (loc
->sgpr_idx
!= -1) {
2478 base_reg
= R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2480 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
2481 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
2487 radv_flush_streamout_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
2489 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_STREAMOUT_BUFFER
) {
2490 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
2491 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
2496 /* Allocate some descriptor state for streamout buffers. */
2497 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
,
2498 MAX_SO_BUFFERS
* 16, 256,
2499 &so_offset
, &so_ptr
))
2502 for (uint32_t i
= 0; i
< MAX_SO_BUFFERS
; i
++) {
2503 struct radv_buffer
*buffer
= sb
[i
].buffer
;
2504 uint32_t *desc
= &((uint32_t *)so_ptr
)[i
* 4];
2506 if (!(so
->enabled_mask
& (1 << i
)))
2509 va
= radv_buffer_get_va(buffer
->bo
) + buffer
->offset
;
2513 /* Set the descriptor.
2515 * On GFX8, the format must be non-INVALID, otherwise
2516 * the buffer will be considered not bound and store
2517 * instructions will be no-ops.
2519 uint32_t size
= 0xffffffff;
2521 /* Compute the correct buffer size for NGG streamout
2522 * because it's used to determine the max emit per
2525 if (cmd_buffer
->device
->physical_device
->use_ngg_streamout
)
2526 size
= buffer
->size
- sb
[i
].offset
;
2529 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
2531 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2532 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2533 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2534 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
2536 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2537 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2538 S_008F0C_OOB_SELECT(3) |
2539 S_008F0C_RESOURCE_LEVEL(1);
2541 desc
[3] |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2545 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2548 radv_emit_streamout_buffers(cmd_buffer
, va
);
2551 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER
;
2555 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer
*cmd_buffer
, bool pipeline_is_dirty
)
2557 radv_flush_vertex_descriptors(cmd_buffer
, pipeline_is_dirty
);
2558 radv_flush_streamout_descriptors(cmd_buffer
);
2559 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
2560 radv_flush_constants(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
2563 struct radv_draw_info
{
2565 * Number of vertices.
2570 * Index of the first vertex.
2572 int32_t vertex_offset
;
2575 * First instance id.
2577 uint32_t first_instance
;
2580 * Number of instances.
2582 uint32_t instance_count
;
2585 * First index (indexed draws only).
2587 uint32_t first_index
;
2590 * Whether it's an indexed draw.
2595 * Indirect draw parameters resource.
2597 struct radv_buffer
*indirect
;
2598 uint64_t indirect_offset
;
2602 * Draw count parameters resource.
2604 struct radv_buffer
*count_buffer
;
2605 uint64_t count_buffer_offset
;
2608 * Stream output parameters resource.
2610 struct radv_buffer
*strmout_buffer
;
2611 uint64_t strmout_buffer_offset
;
2615 radv_get_primitive_reset_index(struct radv_cmd_buffer
*cmd_buffer
)
2617 switch (cmd_buffer
->state
.index_type
) {
2618 case V_028A7C_VGT_INDEX_8
:
2620 case V_028A7C_VGT_INDEX_16
:
2622 case V_028A7C_VGT_INDEX_32
:
2625 unreachable("invalid index type");
2630 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
2631 bool instanced_draw
, bool indirect_draw
,
2632 bool count_from_stream_output
,
2633 uint32_t draw_vertex_count
)
2635 struct radeon_info
*info
= &cmd_buffer
->device
->physical_device
->rad_info
;
2636 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2637 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
2638 unsigned ia_multi_vgt_param
;
2640 ia_multi_vgt_param
=
2641 si_get_ia_multi_vgt_param(cmd_buffer
, instanced_draw
,
2643 count_from_stream_output
,
2646 if (state
->last_ia_multi_vgt_param
!= ia_multi_vgt_param
) {
2647 if (info
->chip_class
== GFX9
) {
2648 radeon_set_uconfig_reg_idx(cmd_buffer
->device
->physical_device
,
2650 R_030960_IA_MULTI_VGT_PARAM
,
2651 4, ia_multi_vgt_param
);
2652 } else if (info
->chip_class
>= GFX7
) {
2653 radeon_set_context_reg_idx(cs
,
2654 R_028AA8_IA_MULTI_VGT_PARAM
,
2655 1, ia_multi_vgt_param
);
2657 radeon_set_context_reg(cs
, R_028AA8_IA_MULTI_VGT_PARAM
,
2658 ia_multi_vgt_param
);
2660 state
->last_ia_multi_vgt_param
= ia_multi_vgt_param
;
2665 radv_emit_draw_registers(struct radv_cmd_buffer
*cmd_buffer
,
2666 const struct radv_draw_info
*draw_info
)
2668 struct radeon_info
*info
= &cmd_buffer
->device
->physical_device
->rad_info
;
2669 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2670 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
2671 int32_t primitive_reset_en
;
2674 if (info
->chip_class
< GFX10
) {
2675 si_emit_ia_multi_vgt_param(cmd_buffer
, draw_info
->instance_count
> 1,
2676 draw_info
->indirect
,
2677 !!draw_info
->strmout_buffer
,
2678 draw_info
->indirect
? 0 : draw_info
->count
);
2681 /* Primitive restart. */
2682 primitive_reset_en
=
2683 draw_info
->indexed
&& state
->pipeline
->graphics
.prim_restart_enable
;
2685 if (primitive_reset_en
!= state
->last_primitive_reset_en
) {
2686 state
->last_primitive_reset_en
= primitive_reset_en
;
2687 if (info
->chip_class
>= GFX9
) {
2688 radeon_set_uconfig_reg(cs
,
2689 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN
,
2690 primitive_reset_en
);
2692 radeon_set_context_reg(cs
,
2693 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
,
2694 primitive_reset_en
);
2698 if (primitive_reset_en
) {
2699 uint32_t primitive_reset_index
=
2700 radv_get_primitive_reset_index(cmd_buffer
);
2702 if (primitive_reset_index
!= state
->last_primitive_reset_index
) {
2703 radeon_set_context_reg(cs
,
2704 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
,
2705 primitive_reset_index
);
2706 state
->last_primitive_reset_index
= primitive_reset_index
;
2710 if (draw_info
->strmout_buffer
) {
2711 uint64_t va
= radv_buffer_get_va(draw_info
->strmout_buffer
->bo
);
2713 va
+= draw_info
->strmout_buffer
->offset
+
2714 draw_info
->strmout_buffer_offset
;
2716 radeon_set_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
,
2719 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
2720 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
2721 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
2722 COPY_DATA_WR_CONFIRM
);
2723 radeon_emit(cs
, va
);
2724 radeon_emit(cs
, va
>> 32);
2725 radeon_emit(cs
, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2);
2726 radeon_emit(cs
, 0); /* unused */
2728 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, draw_info
->strmout_buffer
->bo
);
2732 static void radv_stage_flush(struct radv_cmd_buffer
*cmd_buffer
,
2733 VkPipelineStageFlags src_stage_mask
)
2735 if (src_stage_mask
& (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT
|
2736 VK_PIPELINE_STAGE_TRANSFER_BIT
|
2737 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
2738 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
2739 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
;
2742 if (src_stage_mask
& (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT
|
2743 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT
|
2744 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT
|
2745 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
|
2746 VK_PIPELINE_STAGE_TRANSFER_BIT
|
2747 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
2748 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT
|
2749 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
2750 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
;
2751 } else if (src_stage_mask
& (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
2752 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
|
2753 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT
|
2754 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT
|
2755 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT
|
2756 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT
|
2757 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT
)) {
2758 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VS_PARTIAL_FLUSH
;
2762 static enum radv_cmd_flush_bits
2763 radv_src_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
2764 VkAccessFlags src_flags
,
2765 struct radv_image
*image
)
2767 bool flush_CB_meta
= true, flush_DB_meta
= true;
2768 enum radv_cmd_flush_bits flush_bits
= 0;
2772 if (!radv_image_has_CB_metadata(image
))
2773 flush_CB_meta
= false;
2774 if (!radv_image_has_htile(image
))
2775 flush_DB_meta
= false;
2778 for_each_bit(b
, src_flags
) {
2779 switch ((VkAccessFlagBits
)(1 << b
)) {
2780 case VK_ACCESS_SHADER_WRITE_BIT
:
2781 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT
:
2782 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT
:
2783 flush_bits
|= RADV_CMD_FLAG_WB_L2
;
2785 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
2786 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
;
2788 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2790 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
2791 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
;
2793 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2795 case VK_ACCESS_TRANSFER_WRITE_BIT
:
2796 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
2797 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
2798 RADV_CMD_FLAG_INV_L2
;
2801 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2803 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2812 static enum radv_cmd_flush_bits
2813 radv_dst_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
2814 VkAccessFlags dst_flags
,
2815 struct radv_image
*image
)
2817 bool flush_CB_meta
= true, flush_DB_meta
= true;
2818 enum radv_cmd_flush_bits flush_bits
= 0;
2819 bool flush_CB
= true, flush_DB
= true;
2820 bool image_is_coherent
= false;
2824 if (!(image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
)) {
2829 if (!radv_image_has_CB_metadata(image
))
2830 flush_CB_meta
= false;
2831 if (!radv_image_has_htile(image
))
2832 flush_DB_meta
= false;
2834 /* TODO: implement shader coherent for GFX10 */
2836 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
2837 if (image
->info
.samples
== 1 &&
2838 (image
->usage
& (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
|
2839 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
)) &&
2840 !vk_format_is_stencil(image
->vk_format
)) {
2841 /* Single-sample color and single-sample depth
2842 * (not stencil) are coherent with shaders on
2845 image_is_coherent
= true;
2850 for_each_bit(b
, dst_flags
) {
2851 switch ((VkAccessFlagBits
)(1 << b
)) {
2852 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
2853 case VK_ACCESS_INDEX_READ_BIT
:
2854 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT
:
2856 case VK_ACCESS_UNIFORM_READ_BIT
:
2857 flush_bits
|= RADV_CMD_FLAG_INV_VCACHE
| RADV_CMD_FLAG_INV_SCACHE
;
2859 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
2860 case VK_ACCESS_TRANSFER_READ_BIT
:
2861 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
2862 flush_bits
|= RADV_CMD_FLAG_INV_VCACHE
|
2863 RADV_CMD_FLAG_INV_L2
;
2865 case VK_ACCESS_SHADER_READ_BIT
:
2866 flush_bits
|= RADV_CMD_FLAG_INV_VCACHE
;
2867 /* Unlike LLVM, ACO uses SMEM for SSBOs and we have to
2868 * invalidate the scalar cache. */
2869 if (cmd_buffer
->device
->physical_device
->use_aco
&&
2870 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX8
)
2871 flush_bits
|= RADV_CMD_FLAG_INV_SCACHE
;
2873 if (!image_is_coherent
)
2874 flush_bits
|= RADV_CMD_FLAG_INV_L2
;
2876 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
:
2878 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
;
2880 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2882 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT
:
2884 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
;
2886 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2895 void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
,
2896 const struct radv_subpass_barrier
*barrier
)
2898 cmd_buffer
->state
.flush_bits
|= radv_src_access_flush(cmd_buffer
, barrier
->src_access_mask
,
2900 radv_stage_flush(cmd_buffer
, barrier
->src_stage_mask
);
2901 cmd_buffer
->state
.flush_bits
|= radv_dst_access_flush(cmd_buffer
, barrier
->dst_access_mask
,
2906 radv_get_subpass_id(struct radv_cmd_buffer
*cmd_buffer
)
2908 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2909 uint32_t subpass_id
= state
->subpass
- state
->pass
->subpasses
;
2911 /* The id of this subpass shouldn't exceed the number of subpasses in
2912 * this render pass minus 1.
2914 assert(subpass_id
< state
->pass
->subpass_count
);
2918 static struct radv_sample_locations_state
*
2919 radv_get_attachment_sample_locations(struct radv_cmd_buffer
*cmd_buffer
,
2923 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2924 uint32_t subpass_id
= radv_get_subpass_id(cmd_buffer
);
2925 struct radv_image_view
*view
= state
->attachments
[att_idx
].iview
;
2927 if (view
->image
->info
.samples
== 1)
2930 if (state
->pass
->attachments
[att_idx
].first_subpass_idx
== subpass_id
) {
2931 /* Return the initial sample locations if this is the initial
2932 * layout transition of the given subpass attachemnt.
2934 if (state
->attachments
[att_idx
].sample_location
.count
> 0)
2935 return &state
->attachments
[att_idx
].sample_location
;
2937 /* Otherwise return the subpass sample locations if defined. */
2938 if (state
->subpass_sample_locs
) {
2939 /* Because the driver sets the current subpass before
2940 * initial layout transitions, we should use the sample
2941 * locations from the previous subpass to avoid an
2942 * off-by-one problem. Otherwise, use the sample
2943 * locations for the current subpass for final layout
2949 for (uint32_t i
= 0; i
< state
->num_subpass_sample_locs
; i
++) {
2950 if (state
->subpass_sample_locs
[i
].subpass_idx
== subpass_id
)
2951 return &state
->subpass_sample_locs
[i
].sample_location
;
2959 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
2960 struct radv_subpass_attachment att
,
2963 unsigned idx
= att
.attachment
;
2964 struct radv_image_view
*view
= cmd_buffer
->state
.attachments
[idx
].iview
;
2965 struct radv_sample_locations_state
*sample_locs
;
2966 VkImageSubresourceRange range
;
2967 range
.aspectMask
= view
->aspect_mask
;
2968 range
.baseMipLevel
= view
->base_mip
;
2969 range
.levelCount
= 1;
2970 range
.baseArrayLayer
= view
->base_layer
;
2971 range
.layerCount
= cmd_buffer
->state
.framebuffer
->layers
;
2973 if (cmd_buffer
->state
.subpass
->view_mask
) {
2974 /* If the current subpass uses multiview, the driver might have
2975 * performed a fast color/depth clear to the whole image
2976 * (including all layers). To make sure the driver will
2977 * decompress the image correctly (if needed), we have to
2978 * account for the "real" number of layers. If the view mask is
2979 * sparse, this will decompress more layers than needed.
2981 range
.layerCount
= util_last_bit(cmd_buffer
->state
.subpass
->view_mask
);
2984 /* Get the subpass sample locations for the given attachment, if NULL
2985 * is returned the driver will use the default HW locations.
2987 sample_locs
= radv_get_attachment_sample_locations(cmd_buffer
, idx
,
2990 radv_handle_image_transition(cmd_buffer
,
2992 cmd_buffer
->state
.attachments
[idx
].current_layout
,
2993 cmd_buffer
->state
.attachments
[idx
].current_in_render_loop
,
2994 att
.layout
, att
.in_render_loop
,
2995 0, 0, &range
, sample_locs
);
2997 cmd_buffer
->state
.attachments
[idx
].current_layout
= att
.layout
;
2998 cmd_buffer
->state
.attachments
[idx
].current_in_render_loop
= att
.in_render_loop
;
3004 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
3005 const struct radv_subpass
*subpass
)
3007 cmd_buffer
->state
.subpass
= subpass
;
3009 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_FRAMEBUFFER
;
3013 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer
*cmd_buffer
,
3014 struct radv_render_pass
*pass
,
3015 const VkRenderPassBeginInfo
*info
)
3017 const struct VkRenderPassSampleLocationsBeginInfoEXT
*sample_locs
=
3018 vk_find_struct_const(info
->pNext
,
3019 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT
);
3020 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3023 state
->subpass_sample_locs
= NULL
;
3027 for (uint32_t i
= 0; i
< sample_locs
->attachmentInitialSampleLocationsCount
; i
++) {
3028 const VkAttachmentSampleLocationsEXT
*att_sample_locs
=
3029 &sample_locs
->pAttachmentInitialSampleLocations
[i
];
3030 uint32_t att_idx
= att_sample_locs
->attachmentIndex
;
3031 struct radv_image
*image
= cmd_buffer
->state
.attachments
[att_idx
].iview
->image
;
3033 assert(vk_format_is_depth_or_stencil(image
->vk_format
));
3035 /* From the Vulkan spec 1.1.108:
3037 * "If the image referenced by the framebuffer attachment at
3038 * index attachmentIndex was not created with
3039 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
3040 * then the values specified in sampleLocationsInfo are
3043 if (!(image
->flags
& VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
))
3046 const VkSampleLocationsInfoEXT
*sample_locs_info
=
3047 &att_sample_locs
->sampleLocationsInfo
;
3049 state
->attachments
[att_idx
].sample_location
.per_pixel
=
3050 sample_locs_info
->sampleLocationsPerPixel
;
3051 state
->attachments
[att_idx
].sample_location
.grid_size
=
3052 sample_locs_info
->sampleLocationGridSize
;
3053 state
->attachments
[att_idx
].sample_location
.count
=
3054 sample_locs_info
->sampleLocationsCount
;
3055 typed_memcpy(&state
->attachments
[att_idx
].sample_location
.locations
[0],
3056 sample_locs_info
->pSampleLocations
,
3057 sample_locs_info
->sampleLocationsCount
);
3060 state
->subpass_sample_locs
= vk_alloc(&cmd_buffer
->pool
->alloc
,
3061 sample_locs
->postSubpassSampleLocationsCount
*
3062 sizeof(state
->subpass_sample_locs
[0]),
3063 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3064 if (state
->subpass_sample_locs
== NULL
) {
3065 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
3066 return cmd_buffer
->record_result
;
3069 state
->num_subpass_sample_locs
= sample_locs
->postSubpassSampleLocationsCount
;
3071 for (uint32_t i
= 0; i
< sample_locs
->postSubpassSampleLocationsCount
; i
++) {
3072 const VkSubpassSampleLocationsEXT
*subpass_sample_locs_info
=
3073 &sample_locs
->pPostSubpassSampleLocations
[i
];
3074 const VkSampleLocationsInfoEXT
*sample_locs_info
=
3075 &subpass_sample_locs_info
->sampleLocationsInfo
;
3077 state
->subpass_sample_locs
[i
].subpass_idx
=
3078 subpass_sample_locs_info
->subpassIndex
;
3079 state
->subpass_sample_locs
[i
].sample_location
.per_pixel
=
3080 sample_locs_info
->sampleLocationsPerPixel
;
3081 state
->subpass_sample_locs
[i
].sample_location
.grid_size
=
3082 sample_locs_info
->sampleLocationGridSize
;
3083 state
->subpass_sample_locs
[i
].sample_location
.count
=
3084 sample_locs_info
->sampleLocationsCount
;
3085 typed_memcpy(&state
->subpass_sample_locs
[i
].sample_location
.locations
[0],
3086 sample_locs_info
->pSampleLocations
,
3087 sample_locs_info
->sampleLocationsCount
);
3094 radv_cmd_state_setup_attachments(struct radv_cmd_buffer
*cmd_buffer
,
3095 struct radv_render_pass
*pass
,
3096 const VkRenderPassBeginInfo
*info
)
3098 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3099 const struct VkRenderPassAttachmentBeginInfoKHR
*attachment_info
= NULL
;
3102 attachment_info
= vk_find_struct_const(info
->pNext
,
3103 RENDER_PASS_ATTACHMENT_BEGIN_INFO_KHR
);
3107 if (pass
->attachment_count
== 0) {
3108 state
->attachments
= NULL
;
3112 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
3113 pass
->attachment_count
*
3114 sizeof(state
->attachments
[0]),
3115 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3116 if (state
->attachments
== NULL
) {
3117 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
3118 return cmd_buffer
->record_result
;
3121 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
3122 struct radv_render_pass_attachment
*att
= &pass
->attachments
[i
];
3123 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
3124 VkImageAspectFlags clear_aspects
= 0;
3126 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
3127 /* color attachment */
3128 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
3129 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
3132 /* depthstencil attachment */
3133 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
3134 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
3135 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
3136 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
3137 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_DONT_CARE
)
3138 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
3140 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
3141 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
3142 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
3146 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
3147 state
->attachments
[i
].cleared_views
= 0;
3148 if (clear_aspects
&& info
) {
3149 assert(info
->clearValueCount
> i
);
3150 state
->attachments
[i
].clear_value
= info
->pClearValues
[i
];
3153 state
->attachments
[i
].current_layout
= att
->initial_layout
;
3154 state
->attachments
[i
].sample_location
.count
= 0;
3156 struct radv_image_view
*iview
;
3157 if (attachment_info
&& attachment_info
->attachmentCount
> i
) {
3158 iview
= radv_image_view_from_handle(attachment_info
->pAttachments
[i
]);
3160 iview
= state
->framebuffer
->attachments
[i
];
3163 state
->attachments
[i
].iview
= iview
;
3164 if (iview
->aspect_mask
& (VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3165 radv_initialise_ds_surface(cmd_buffer
->device
, &state
->attachments
[i
].ds
, iview
);
3167 radv_initialise_color_surface(cmd_buffer
->device
, &state
->attachments
[i
].cb
, iview
);
3174 VkResult
radv_AllocateCommandBuffers(
3176 const VkCommandBufferAllocateInfo
*pAllocateInfo
,
3177 VkCommandBuffer
*pCommandBuffers
)
3179 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3180 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
3182 VkResult result
= VK_SUCCESS
;
3185 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
3187 if (!list_is_empty(&pool
->free_cmd_buffers
)) {
3188 struct radv_cmd_buffer
*cmd_buffer
= list_first_entry(&pool
->free_cmd_buffers
, struct radv_cmd_buffer
, pool_link
);
3190 list_del(&cmd_buffer
->pool_link
);
3191 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
3193 result
= radv_reset_cmd_buffer(cmd_buffer
);
3194 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
3195 cmd_buffer
->level
= pAllocateInfo
->level
;
3197 pCommandBuffers
[i
] = radv_cmd_buffer_to_handle(cmd_buffer
);
3199 result
= radv_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
3200 &pCommandBuffers
[i
]);
3202 if (result
!= VK_SUCCESS
)
3206 if (result
!= VK_SUCCESS
) {
3207 radv_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
,
3208 i
, pCommandBuffers
);
3210 /* From the Vulkan 1.0.66 spec:
3212 * "vkAllocateCommandBuffers can be used to create multiple
3213 * command buffers. If the creation of any of those command
3214 * buffers fails, the implementation must destroy all
3215 * successfully created command buffer objects from this
3216 * command, set all entries of the pCommandBuffers array to
3217 * NULL and return the error."
3219 memset(pCommandBuffers
, 0,
3220 sizeof(*pCommandBuffers
) * pAllocateInfo
->commandBufferCount
);
3226 void radv_FreeCommandBuffers(
3228 VkCommandPool commandPool
,
3229 uint32_t commandBufferCount
,
3230 const VkCommandBuffer
*pCommandBuffers
)
3232 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
3233 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
3236 if (cmd_buffer
->pool
) {
3237 list_del(&cmd_buffer
->pool_link
);
3238 list_addtail(&cmd_buffer
->pool_link
, &cmd_buffer
->pool
->free_cmd_buffers
);
3240 radv_cmd_buffer_destroy(cmd_buffer
);
3246 VkResult
radv_ResetCommandBuffer(
3247 VkCommandBuffer commandBuffer
,
3248 VkCommandBufferResetFlags flags
)
3250 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3251 return radv_reset_cmd_buffer(cmd_buffer
);
3254 VkResult
radv_BeginCommandBuffer(
3255 VkCommandBuffer commandBuffer
,
3256 const VkCommandBufferBeginInfo
*pBeginInfo
)
3258 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3259 VkResult result
= VK_SUCCESS
;
3261 if (cmd_buffer
->status
!= RADV_CMD_BUFFER_STATUS_INITIAL
) {
3262 /* If the command buffer has already been resetted with
3263 * vkResetCommandBuffer, no need to do it again.
3265 result
= radv_reset_cmd_buffer(cmd_buffer
);
3266 if (result
!= VK_SUCCESS
)
3270 memset(&cmd_buffer
->state
, 0, sizeof(cmd_buffer
->state
));
3271 cmd_buffer
->state
.last_primitive_reset_en
= -1;
3272 cmd_buffer
->state
.last_index_type
= -1;
3273 cmd_buffer
->state
.last_num_instances
= -1;
3274 cmd_buffer
->state
.last_vertex_offset
= -1;
3275 cmd_buffer
->state
.last_first_instance
= -1;
3276 cmd_buffer
->state
.predication_type
= -1;
3277 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
3279 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
&&
3280 (pBeginInfo
->flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
)) {
3281 assert(pBeginInfo
->pInheritanceInfo
);
3282 cmd_buffer
->state
.framebuffer
= radv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
3283 cmd_buffer
->state
.pass
= radv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
3285 struct radv_subpass
*subpass
=
3286 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
3288 if (cmd_buffer
->state
.framebuffer
) {
3289 result
= radv_cmd_state_setup_attachments(cmd_buffer
, cmd_buffer
->state
.pass
, NULL
);
3290 if (result
!= VK_SUCCESS
)
3294 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
);
3297 if (unlikely(cmd_buffer
->device
->trace_bo
)) {
3298 struct radv_device
*device
= cmd_buffer
->device
;
3300 radv_cs_add_buffer(device
->ws
, cmd_buffer
->cs
,
3303 radv_cmd_buffer_trace_emit(cmd_buffer
);
3306 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_RECORDING
;
3311 void radv_CmdBindVertexBuffers(
3312 VkCommandBuffer commandBuffer
,
3313 uint32_t firstBinding
,
3314 uint32_t bindingCount
,
3315 const VkBuffer
* pBuffers
,
3316 const VkDeviceSize
* pOffsets
)
3318 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3319 struct radv_vertex_binding
*vb
= cmd_buffer
->vertex_bindings
;
3320 bool changed
= false;
3322 /* We have to defer setting up vertex buffer since we need the buffer
3323 * stride from the pipeline. */
3325 assert(firstBinding
+ bindingCount
<= MAX_VBS
);
3326 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
3327 uint32_t idx
= firstBinding
+ i
;
3330 (vb
[idx
].buffer
!= radv_buffer_from_handle(pBuffers
[i
]) ||
3331 vb
[idx
].offset
!= pOffsets
[i
])) {
3335 vb
[idx
].buffer
= radv_buffer_from_handle(pBuffers
[i
]);
3336 vb
[idx
].offset
= pOffsets
[i
];
3338 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
3339 vb
[idx
].buffer
->bo
);
3343 /* No state changes. */
3347 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_VERTEX_BUFFER
;
3351 vk_to_index_type(VkIndexType type
)
3354 case VK_INDEX_TYPE_UINT8_EXT
:
3355 return V_028A7C_VGT_INDEX_8
;
3356 case VK_INDEX_TYPE_UINT16
:
3357 return V_028A7C_VGT_INDEX_16
;
3358 case VK_INDEX_TYPE_UINT32
:
3359 return V_028A7C_VGT_INDEX_32
;
3361 unreachable("invalid index type");
3366 radv_get_vgt_index_size(uint32_t type
)
3369 case V_028A7C_VGT_INDEX_8
:
3371 case V_028A7C_VGT_INDEX_16
:
3373 case V_028A7C_VGT_INDEX_32
:
3376 unreachable("invalid index type");
3380 void radv_CmdBindIndexBuffer(
3381 VkCommandBuffer commandBuffer
,
3383 VkDeviceSize offset
,
3384 VkIndexType indexType
)
3386 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3387 RADV_FROM_HANDLE(radv_buffer
, index_buffer
, buffer
);
3389 if (cmd_buffer
->state
.index_buffer
== index_buffer
&&
3390 cmd_buffer
->state
.index_offset
== offset
&&
3391 cmd_buffer
->state
.index_type
== indexType
) {
3392 /* No state changes. */
3396 cmd_buffer
->state
.index_buffer
= index_buffer
;
3397 cmd_buffer
->state
.index_offset
= offset
;
3398 cmd_buffer
->state
.index_type
= vk_to_index_type(indexType
);
3399 cmd_buffer
->state
.index_va
= radv_buffer_get_va(index_buffer
->bo
);
3400 cmd_buffer
->state
.index_va
+= index_buffer
->offset
+ offset
;
3402 int index_size
= radv_get_vgt_index_size(vk_to_index_type(indexType
));
3403 cmd_buffer
->state
.max_index_count
= (index_buffer
->size
- offset
) / index_size
;
3404 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
3405 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, index_buffer
->bo
);
3410 radv_bind_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
3411 VkPipelineBindPoint bind_point
,
3412 struct radv_descriptor_set
*set
, unsigned idx
)
3414 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
3416 radv_set_descriptor_set(cmd_buffer
, bind_point
, set
, idx
);
3419 assert(!(set
->layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
));
3421 if (!cmd_buffer
->device
->use_global_bo_list
) {
3422 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
)
3423 if (set
->descriptors
[j
])
3424 radv_cs_add_buffer(ws
, cmd_buffer
->cs
, set
->descriptors
[j
]);
3428 radv_cs_add_buffer(ws
, cmd_buffer
->cs
, set
->bo
);
3431 void radv_CmdBindDescriptorSets(
3432 VkCommandBuffer commandBuffer
,
3433 VkPipelineBindPoint pipelineBindPoint
,
3434 VkPipelineLayout _layout
,
3436 uint32_t descriptorSetCount
,
3437 const VkDescriptorSet
* pDescriptorSets
,
3438 uint32_t dynamicOffsetCount
,
3439 const uint32_t* pDynamicOffsets
)
3441 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3442 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
3443 unsigned dyn_idx
= 0;
3445 const bool no_dynamic_bounds
= cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_NO_DYNAMIC_BOUNDS
;
3446 struct radv_descriptor_state
*descriptors_state
=
3447 radv_get_descriptors_state(cmd_buffer
, pipelineBindPoint
);
3449 for (unsigned i
= 0; i
< descriptorSetCount
; ++i
) {
3450 unsigned idx
= i
+ firstSet
;
3451 RADV_FROM_HANDLE(radv_descriptor_set
, set
, pDescriptorSets
[i
]);
3453 /* If the set is already bound we only need to update the
3454 * (potentially changed) dynamic offsets. */
3455 if (descriptors_state
->sets
[idx
] != set
||
3456 !(descriptors_state
->valid
& (1u << idx
))) {
3457 radv_bind_descriptor_set(cmd_buffer
, pipelineBindPoint
, set
, idx
);
3460 for(unsigned j
= 0; j
< set
->layout
->dynamic_offset_count
; ++j
, ++dyn_idx
) {
3461 unsigned idx
= j
+ layout
->set
[i
+ firstSet
].dynamic_offset_start
;
3462 uint32_t *dst
= descriptors_state
->dynamic_buffers
+ idx
* 4;
3463 assert(dyn_idx
< dynamicOffsetCount
);
3465 struct radv_descriptor_range
*range
= set
->dynamic_descriptors
+ j
;
3466 uint64_t va
= range
->va
+ pDynamicOffsets
[dyn_idx
];
3468 dst
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
3469 dst
[2] = no_dynamic_bounds
? 0xffffffffu
: range
->size
;
3470 dst
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3471 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3472 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3473 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3475 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3476 dst
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3477 S_008F0C_OOB_SELECT(3) |
3478 S_008F0C_RESOURCE_LEVEL(1);
3480 dst
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3481 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3484 cmd_buffer
->push_constant_stages
|=
3485 set
->layout
->dynamic_shader_stages
;
3490 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
3491 struct radv_descriptor_set
*set
,
3492 struct radv_descriptor_set_layout
*layout
,
3493 VkPipelineBindPoint bind_point
)
3495 struct radv_descriptor_state
*descriptors_state
=
3496 radv_get_descriptors_state(cmd_buffer
, bind_point
);
3497 set
->size
= layout
->size
;
3498 set
->layout
= layout
;
3500 if (descriptors_state
->push_set
.capacity
< set
->size
) {
3501 size_t new_size
= MAX2(set
->size
, 1024);
3502 new_size
= MAX2(new_size
, 2 * descriptors_state
->push_set
.capacity
);
3503 new_size
= MIN2(new_size
, 96 * MAX_PUSH_DESCRIPTORS
);
3505 free(set
->mapped_ptr
);
3506 set
->mapped_ptr
= malloc(new_size
);
3508 if (!set
->mapped_ptr
) {
3509 descriptors_state
->push_set
.capacity
= 0;
3510 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
3514 descriptors_state
->push_set
.capacity
= new_size
;
3520 void radv_meta_push_descriptor_set(
3521 struct radv_cmd_buffer
* cmd_buffer
,
3522 VkPipelineBindPoint pipelineBindPoint
,
3523 VkPipelineLayout _layout
,
3525 uint32_t descriptorWriteCount
,
3526 const VkWriteDescriptorSet
* pDescriptorWrites
)
3528 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
3529 struct radv_descriptor_set
*push_set
= &cmd_buffer
->meta_push_descriptors
;
3533 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
3535 push_set
->size
= layout
->set
[set
].layout
->size
;
3536 push_set
->layout
= layout
->set
[set
].layout
;
3538 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, push_set
->size
, 32,
3540 (void**) &push_set
->mapped_ptr
))
3543 push_set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
3544 push_set
->va
+= bo_offset
;
3546 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
3547 radv_descriptor_set_to_handle(push_set
),
3548 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
3550 radv_set_descriptor_set(cmd_buffer
, pipelineBindPoint
, push_set
, set
);
3553 void radv_CmdPushDescriptorSetKHR(
3554 VkCommandBuffer commandBuffer
,
3555 VkPipelineBindPoint pipelineBindPoint
,
3556 VkPipelineLayout _layout
,
3558 uint32_t descriptorWriteCount
,
3559 const VkWriteDescriptorSet
* pDescriptorWrites
)
3561 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3562 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
3563 struct radv_descriptor_state
*descriptors_state
=
3564 radv_get_descriptors_state(cmd_buffer
, pipelineBindPoint
);
3565 struct radv_descriptor_set
*push_set
= &descriptors_state
->push_set
.set
;
3567 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
3569 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
,
3570 layout
->set
[set
].layout
,
3574 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3575 * because it is invalid, according to Vulkan spec.
3577 for (int i
= 0; i
< descriptorWriteCount
; i
++) {
3578 ASSERTED
const VkWriteDescriptorSet
*writeset
= &pDescriptorWrites
[i
];
3579 assert(writeset
->descriptorType
!= VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
);
3582 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
3583 radv_descriptor_set_to_handle(push_set
),
3584 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
3586 radv_set_descriptor_set(cmd_buffer
, pipelineBindPoint
, push_set
, set
);
3587 descriptors_state
->push_dirty
= true;
3590 void radv_CmdPushDescriptorSetWithTemplateKHR(
3591 VkCommandBuffer commandBuffer
,
3592 VkDescriptorUpdateTemplate descriptorUpdateTemplate
,
3593 VkPipelineLayout _layout
,
3597 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3598 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
3599 RADV_FROM_HANDLE(radv_descriptor_update_template
, templ
, descriptorUpdateTemplate
);
3600 struct radv_descriptor_state
*descriptors_state
=
3601 radv_get_descriptors_state(cmd_buffer
, templ
->bind_point
);
3602 struct radv_descriptor_set
*push_set
= &descriptors_state
->push_set
.set
;
3604 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
3606 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
,
3607 layout
->set
[set
].layout
,
3611 radv_update_descriptor_set_with_template(cmd_buffer
->device
, cmd_buffer
, push_set
,
3612 descriptorUpdateTemplate
, pData
);
3614 radv_set_descriptor_set(cmd_buffer
, templ
->bind_point
, push_set
, set
);
3615 descriptors_state
->push_dirty
= true;
3618 void radv_CmdPushConstants(VkCommandBuffer commandBuffer
,
3619 VkPipelineLayout layout
,
3620 VkShaderStageFlags stageFlags
,
3623 const void* pValues
)
3625 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3626 memcpy(cmd_buffer
->push_constants
+ offset
, pValues
, size
);
3627 cmd_buffer
->push_constant_stages
|= stageFlags
;
3630 VkResult
radv_EndCommandBuffer(
3631 VkCommandBuffer commandBuffer
)
3633 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3635 if (cmd_buffer
->queue_family_index
!= RADV_QUEUE_TRANSFER
) {
3636 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX6
)
3637 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
| RADV_CMD_FLAG_WB_L2
;
3639 /* Make sure to sync all pending active queries at the end of
3642 cmd_buffer
->state
.flush_bits
|= cmd_buffer
->active_query_flush_bits
;
3644 /* Since NGG streamout uses GDS, we need to make GDS idle when
3645 * we leave the IB, otherwise another process might overwrite
3646 * it while our shaders are busy.
3648 if (cmd_buffer
->gds_needed
)
3649 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
;
3651 si_emit_cache_flush(cmd_buffer
);
3654 /* Make sure CP DMA is idle at the end of IBs because the kernel
3655 * doesn't wait for it.
3657 si_cp_dma_wait_for_idle(cmd_buffer
);
3659 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
3660 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.subpass_sample_locs
);
3662 if (!cmd_buffer
->device
->ws
->cs_finalize(cmd_buffer
->cs
))
3663 return vk_error(cmd_buffer
->device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
3665 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_EXECUTABLE
;
3667 return cmd_buffer
->record_result
;
3671 radv_emit_compute_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
3673 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
3675 if (!pipeline
|| pipeline
== cmd_buffer
->state
.emitted_compute_pipeline
)
3678 assert(!pipeline
->ctx_cs
.cdw
);
3680 cmd_buffer
->state
.emitted_compute_pipeline
= pipeline
;
3682 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, pipeline
->cs
.cdw
);
3683 radeon_emit_array(cmd_buffer
->cs
, pipeline
->cs
.buf
, pipeline
->cs
.cdw
);
3685 cmd_buffer
->compute_scratch_size_per_wave_needed
= MAX2(cmd_buffer
->compute_scratch_size_per_wave_needed
,
3686 pipeline
->scratch_bytes_per_wave
);
3687 cmd_buffer
->compute_scratch_waves_wanted
= MAX2(cmd_buffer
->compute_scratch_waves_wanted
,
3688 pipeline
->max_waves
);
3690 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
3691 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->bo
);
3693 if (unlikely(cmd_buffer
->device
->trace_bo
))
3694 radv_save_pipeline(cmd_buffer
, pipeline
, RING_COMPUTE
);
3697 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer
*cmd_buffer
,
3698 VkPipelineBindPoint bind_point
)
3700 struct radv_descriptor_state
*descriptors_state
=
3701 radv_get_descriptors_state(cmd_buffer
, bind_point
);
3703 descriptors_state
->dirty
|= descriptors_state
->valid
;
3706 void radv_CmdBindPipeline(
3707 VkCommandBuffer commandBuffer
,
3708 VkPipelineBindPoint pipelineBindPoint
,
3709 VkPipeline _pipeline
)
3711 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3712 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
3714 switch (pipelineBindPoint
) {
3715 case VK_PIPELINE_BIND_POINT_COMPUTE
:
3716 if (cmd_buffer
->state
.compute_pipeline
== pipeline
)
3718 radv_mark_descriptor_sets_dirty(cmd_buffer
, pipelineBindPoint
);
3720 cmd_buffer
->state
.compute_pipeline
= pipeline
;
3721 cmd_buffer
->push_constant_stages
|= VK_SHADER_STAGE_COMPUTE_BIT
;
3723 case VK_PIPELINE_BIND_POINT_GRAPHICS
:
3724 if (cmd_buffer
->state
.pipeline
== pipeline
)
3726 radv_mark_descriptor_sets_dirty(cmd_buffer
, pipelineBindPoint
);
3728 cmd_buffer
->state
.pipeline
= pipeline
;
3732 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
;
3733 cmd_buffer
->push_constant_stages
|= pipeline
->active_stages
;
3735 /* the new vertex shader might not have the same user regs */
3736 cmd_buffer
->state
.last_first_instance
= -1;
3737 cmd_buffer
->state
.last_vertex_offset
= -1;
3739 /* Prefetch all pipeline shaders at first draw time. */
3740 cmd_buffer
->state
.prefetch_L2_mask
|= RADV_PREFETCH_SHADERS
;
3742 if ((cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_NAVI10
||
3743 cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_NAVI12
||
3744 cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_NAVI14
) &&
3745 cmd_buffer
->state
.emitted_pipeline
&&
3746 radv_pipeline_has_ngg(cmd_buffer
->state
.emitted_pipeline
) &&
3747 !radv_pipeline_has_ngg(cmd_buffer
->state
.pipeline
)) {
3748 /* Transitioning from NGG to legacy GS requires
3749 * VGT_FLUSH on Navi10-14. VGT_FLUSH is also emitted
3750 * at the beginning of IBs when legacy GS ring pointers
3753 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VGT_FLUSH
;
3756 radv_bind_dynamic_state(cmd_buffer
, &pipeline
->dynamic_state
);
3757 radv_bind_streamout_state(cmd_buffer
, pipeline
);
3759 if (pipeline
->graphics
.esgs_ring_size
> cmd_buffer
->esgs_ring_size_needed
)
3760 cmd_buffer
->esgs_ring_size_needed
= pipeline
->graphics
.esgs_ring_size
;
3761 if (pipeline
->graphics
.gsvs_ring_size
> cmd_buffer
->gsvs_ring_size_needed
)
3762 cmd_buffer
->gsvs_ring_size_needed
= pipeline
->graphics
.gsvs_ring_size
;
3764 if (radv_pipeline_has_tess(pipeline
))
3765 cmd_buffer
->tess_rings_needed
= true;
3768 assert(!"invalid bind point");
3773 void radv_CmdSetViewport(
3774 VkCommandBuffer commandBuffer
,
3775 uint32_t firstViewport
,
3776 uint32_t viewportCount
,
3777 const VkViewport
* pViewports
)
3779 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3780 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3781 ASSERTED
const uint32_t total_count
= firstViewport
+ viewportCount
;
3783 assert(firstViewport
< MAX_VIEWPORTS
);
3784 assert(total_count
>= 1 && total_count
<= MAX_VIEWPORTS
);
3786 if (!memcmp(state
->dynamic
.viewport
.viewports
+ firstViewport
,
3787 pViewports
, viewportCount
* sizeof(*pViewports
))) {
3791 memcpy(state
->dynamic
.viewport
.viewports
+ firstViewport
, pViewports
,
3792 viewportCount
* sizeof(*pViewports
));
3794 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
3797 void radv_CmdSetScissor(
3798 VkCommandBuffer commandBuffer
,
3799 uint32_t firstScissor
,
3800 uint32_t scissorCount
,
3801 const VkRect2D
* pScissors
)
3803 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3804 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3805 ASSERTED
const uint32_t total_count
= firstScissor
+ scissorCount
;
3807 assert(firstScissor
< MAX_SCISSORS
);
3808 assert(total_count
>= 1 && total_count
<= MAX_SCISSORS
);
3810 if (!memcmp(state
->dynamic
.scissor
.scissors
+ firstScissor
, pScissors
,
3811 scissorCount
* sizeof(*pScissors
))) {
3815 memcpy(state
->dynamic
.scissor
.scissors
+ firstScissor
, pScissors
,
3816 scissorCount
* sizeof(*pScissors
));
3818 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
3821 void radv_CmdSetLineWidth(
3822 VkCommandBuffer commandBuffer
,
3825 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3827 if (cmd_buffer
->state
.dynamic
.line_width
== lineWidth
)
3830 cmd_buffer
->state
.dynamic
.line_width
= lineWidth
;
3831 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
3834 void radv_CmdSetDepthBias(
3835 VkCommandBuffer commandBuffer
,
3836 float depthBiasConstantFactor
,
3837 float depthBiasClamp
,
3838 float depthBiasSlopeFactor
)
3840 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3841 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3843 if (state
->dynamic
.depth_bias
.bias
== depthBiasConstantFactor
&&
3844 state
->dynamic
.depth_bias
.clamp
== depthBiasClamp
&&
3845 state
->dynamic
.depth_bias
.slope
== depthBiasSlopeFactor
) {
3849 state
->dynamic
.depth_bias
.bias
= depthBiasConstantFactor
;
3850 state
->dynamic
.depth_bias
.clamp
= depthBiasClamp
;
3851 state
->dynamic
.depth_bias
.slope
= depthBiasSlopeFactor
;
3853 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
3856 void radv_CmdSetBlendConstants(
3857 VkCommandBuffer commandBuffer
,
3858 const float blendConstants
[4])
3860 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3861 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3863 if (!memcmp(state
->dynamic
.blend_constants
, blendConstants
, sizeof(float) * 4))
3866 memcpy(state
->dynamic
.blend_constants
, blendConstants
, sizeof(float) * 4);
3868 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
3871 void radv_CmdSetDepthBounds(
3872 VkCommandBuffer commandBuffer
,
3873 float minDepthBounds
,
3874 float maxDepthBounds
)
3876 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3877 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3879 if (state
->dynamic
.depth_bounds
.min
== minDepthBounds
&&
3880 state
->dynamic
.depth_bounds
.max
== maxDepthBounds
) {
3884 state
->dynamic
.depth_bounds
.min
= minDepthBounds
;
3885 state
->dynamic
.depth_bounds
.max
= maxDepthBounds
;
3887 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
3890 void radv_CmdSetStencilCompareMask(
3891 VkCommandBuffer commandBuffer
,
3892 VkStencilFaceFlags faceMask
,
3893 uint32_t compareMask
)
3895 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3896 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3897 bool front_same
= state
->dynamic
.stencil_compare_mask
.front
== compareMask
;
3898 bool back_same
= state
->dynamic
.stencil_compare_mask
.back
== compareMask
;
3900 if ((!(faceMask
& VK_STENCIL_FACE_FRONT_BIT
) || front_same
) &&
3901 (!(faceMask
& VK_STENCIL_FACE_BACK_BIT
) || back_same
)) {
3905 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
3906 state
->dynamic
.stencil_compare_mask
.front
= compareMask
;
3907 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
3908 state
->dynamic
.stencil_compare_mask
.back
= compareMask
;
3910 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
3913 void radv_CmdSetStencilWriteMask(
3914 VkCommandBuffer commandBuffer
,
3915 VkStencilFaceFlags faceMask
,
3918 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3919 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3920 bool front_same
= state
->dynamic
.stencil_write_mask
.front
== writeMask
;
3921 bool back_same
= state
->dynamic
.stencil_write_mask
.back
== writeMask
;
3923 if ((!(faceMask
& VK_STENCIL_FACE_FRONT_BIT
) || front_same
) &&
3924 (!(faceMask
& VK_STENCIL_FACE_BACK_BIT
) || back_same
)) {
3928 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
3929 state
->dynamic
.stencil_write_mask
.front
= writeMask
;
3930 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
3931 state
->dynamic
.stencil_write_mask
.back
= writeMask
;
3933 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
3936 void radv_CmdSetStencilReference(
3937 VkCommandBuffer commandBuffer
,
3938 VkStencilFaceFlags faceMask
,
3941 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3942 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3943 bool front_same
= state
->dynamic
.stencil_reference
.front
== reference
;
3944 bool back_same
= state
->dynamic
.stencil_reference
.back
== reference
;
3946 if ((!(faceMask
& VK_STENCIL_FACE_FRONT_BIT
) || front_same
) &&
3947 (!(faceMask
& VK_STENCIL_FACE_BACK_BIT
) || back_same
)) {
3951 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
3952 cmd_buffer
->state
.dynamic
.stencil_reference
.front
= reference
;
3953 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
3954 cmd_buffer
->state
.dynamic
.stencil_reference
.back
= reference
;
3956 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
3959 void radv_CmdSetDiscardRectangleEXT(
3960 VkCommandBuffer commandBuffer
,
3961 uint32_t firstDiscardRectangle
,
3962 uint32_t discardRectangleCount
,
3963 const VkRect2D
* pDiscardRectangles
)
3965 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3966 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3967 ASSERTED
const uint32_t total_count
= firstDiscardRectangle
+ discardRectangleCount
;
3969 assert(firstDiscardRectangle
< MAX_DISCARD_RECTANGLES
);
3970 assert(total_count
>= 1 && total_count
<= MAX_DISCARD_RECTANGLES
);
3972 if (!memcmp(state
->dynamic
.discard_rectangle
.rectangles
+ firstDiscardRectangle
,
3973 pDiscardRectangles
, discardRectangleCount
* sizeof(*pDiscardRectangles
))) {
3977 typed_memcpy(&state
->dynamic
.discard_rectangle
.rectangles
[firstDiscardRectangle
],
3978 pDiscardRectangles
, discardRectangleCount
);
3980 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
;
3983 void radv_CmdSetSampleLocationsEXT(
3984 VkCommandBuffer commandBuffer
,
3985 const VkSampleLocationsInfoEXT
* pSampleLocationsInfo
)
3987 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3988 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3990 assert(pSampleLocationsInfo
->sampleLocationsCount
<= MAX_SAMPLE_LOCATIONS
);
3992 state
->dynamic
.sample_location
.per_pixel
= pSampleLocationsInfo
->sampleLocationsPerPixel
;
3993 state
->dynamic
.sample_location
.grid_size
= pSampleLocationsInfo
->sampleLocationGridSize
;
3994 state
->dynamic
.sample_location
.count
= pSampleLocationsInfo
->sampleLocationsCount
;
3995 typed_memcpy(&state
->dynamic
.sample_location
.locations
[0],
3996 pSampleLocationsInfo
->pSampleLocations
,
3997 pSampleLocationsInfo
->sampleLocationsCount
);
3999 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS
;
4002 void radv_CmdExecuteCommands(
4003 VkCommandBuffer commandBuffer
,
4004 uint32_t commandBufferCount
,
4005 const VkCommandBuffer
* pCmdBuffers
)
4007 RADV_FROM_HANDLE(radv_cmd_buffer
, primary
, commandBuffer
);
4009 assert(commandBufferCount
> 0);
4011 /* Emit pending flushes on primary prior to executing secondary */
4012 si_emit_cache_flush(primary
);
4014 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
4015 RADV_FROM_HANDLE(radv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
4017 primary
->scratch_size_per_wave_needed
= MAX2(primary
->scratch_size_per_wave_needed
,
4018 secondary
->scratch_size_per_wave_needed
);
4019 primary
->scratch_waves_wanted
= MAX2(primary
->scratch_waves_wanted
,
4020 secondary
->scratch_waves_wanted
);
4021 primary
->compute_scratch_size_per_wave_needed
= MAX2(primary
->compute_scratch_size_per_wave_needed
,
4022 secondary
->compute_scratch_size_per_wave_needed
);
4023 primary
->compute_scratch_waves_wanted
= MAX2(primary
->compute_scratch_waves_wanted
,
4024 secondary
->compute_scratch_waves_wanted
);
4026 if (secondary
->esgs_ring_size_needed
> primary
->esgs_ring_size_needed
)
4027 primary
->esgs_ring_size_needed
= secondary
->esgs_ring_size_needed
;
4028 if (secondary
->gsvs_ring_size_needed
> primary
->gsvs_ring_size_needed
)
4029 primary
->gsvs_ring_size_needed
= secondary
->gsvs_ring_size_needed
;
4030 if (secondary
->tess_rings_needed
)
4031 primary
->tess_rings_needed
= true;
4032 if (secondary
->sample_positions_needed
)
4033 primary
->sample_positions_needed
= true;
4035 if (!secondary
->state
.framebuffer
&&
4036 (primary
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
)) {
4037 /* Emit the framebuffer state from primary if secondary
4038 * has been recorded without a framebuffer, otherwise
4039 * fast color/depth clears can't work.
4041 radv_emit_framebuffer_state(primary
);
4044 primary
->device
->ws
->cs_execute_secondary(primary
->cs
, secondary
->cs
);
4047 /* When the secondary command buffer is compute only we don't
4048 * need to re-emit the current graphics pipeline.
4050 if (secondary
->state
.emitted_pipeline
) {
4051 primary
->state
.emitted_pipeline
=
4052 secondary
->state
.emitted_pipeline
;
4055 /* When the secondary command buffer is graphics only we don't
4056 * need to re-emit the current compute pipeline.
4058 if (secondary
->state
.emitted_compute_pipeline
) {
4059 primary
->state
.emitted_compute_pipeline
=
4060 secondary
->state
.emitted_compute_pipeline
;
4063 /* Only re-emit the draw packets when needed. */
4064 if (secondary
->state
.last_primitive_reset_en
!= -1) {
4065 primary
->state
.last_primitive_reset_en
=
4066 secondary
->state
.last_primitive_reset_en
;
4069 if (secondary
->state
.last_primitive_reset_index
) {
4070 primary
->state
.last_primitive_reset_index
=
4071 secondary
->state
.last_primitive_reset_index
;
4074 if (secondary
->state
.last_ia_multi_vgt_param
) {
4075 primary
->state
.last_ia_multi_vgt_param
=
4076 secondary
->state
.last_ia_multi_vgt_param
;
4079 primary
->state
.last_first_instance
= secondary
->state
.last_first_instance
;
4080 primary
->state
.last_num_instances
= secondary
->state
.last_num_instances
;
4081 primary
->state
.last_vertex_offset
= secondary
->state
.last_vertex_offset
;
4083 if (secondary
->state
.last_index_type
!= -1) {
4084 primary
->state
.last_index_type
=
4085 secondary
->state
.last_index_type
;
4089 /* After executing commands from secondary buffers we have to dirty
4092 primary
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
|
4093 RADV_CMD_DIRTY_INDEX_BUFFER
|
4094 RADV_CMD_DIRTY_DYNAMIC_ALL
;
4095 radv_mark_descriptor_sets_dirty(primary
, VK_PIPELINE_BIND_POINT_GRAPHICS
);
4096 radv_mark_descriptor_sets_dirty(primary
, VK_PIPELINE_BIND_POINT_COMPUTE
);
4099 VkResult
radv_CreateCommandPool(
4101 const VkCommandPoolCreateInfo
* pCreateInfo
,
4102 const VkAllocationCallbacks
* pAllocator
,
4103 VkCommandPool
* pCmdPool
)
4105 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4106 struct radv_cmd_pool
*pool
;
4108 pool
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pool
), 8,
4109 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4111 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4114 pool
->alloc
= *pAllocator
;
4116 pool
->alloc
= device
->alloc
;
4118 list_inithead(&pool
->cmd_buffers
);
4119 list_inithead(&pool
->free_cmd_buffers
);
4121 pool
->queue_family_index
= pCreateInfo
->queueFamilyIndex
;
4123 *pCmdPool
= radv_cmd_pool_to_handle(pool
);
4129 void radv_DestroyCommandPool(
4131 VkCommandPool commandPool
,
4132 const VkAllocationCallbacks
* pAllocator
)
4134 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4135 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
4140 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
4141 &pool
->cmd_buffers
, pool_link
) {
4142 radv_cmd_buffer_destroy(cmd_buffer
);
4145 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
4146 &pool
->free_cmd_buffers
, pool_link
) {
4147 radv_cmd_buffer_destroy(cmd_buffer
);
4150 vk_free2(&device
->alloc
, pAllocator
, pool
);
4153 VkResult
radv_ResetCommandPool(
4155 VkCommandPool commandPool
,
4156 VkCommandPoolResetFlags flags
)
4158 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
4161 list_for_each_entry(struct radv_cmd_buffer
, cmd_buffer
,
4162 &pool
->cmd_buffers
, pool_link
) {
4163 result
= radv_reset_cmd_buffer(cmd_buffer
);
4164 if (result
!= VK_SUCCESS
)
4171 void radv_TrimCommandPool(
4173 VkCommandPool commandPool
,
4174 VkCommandPoolTrimFlags flags
)
4176 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
4181 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
4182 &pool
->free_cmd_buffers
, pool_link
) {
4183 radv_cmd_buffer_destroy(cmd_buffer
);
4188 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer
*cmd_buffer
,
4189 uint32_t subpass_id
)
4191 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4192 struct radv_subpass
*subpass
= &state
->pass
->subpasses
[subpass_id
];
4194 ASSERTED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
4195 cmd_buffer
->cs
, 4096);
4197 radv_subpass_barrier(cmd_buffer
, &subpass
->start_barrier
);
4199 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
);
4201 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4202 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4203 if (a
== VK_ATTACHMENT_UNUSED
)
4206 radv_handle_subpass_image_transition(cmd_buffer
,
4207 subpass
->attachments
[i
],
4211 radv_cmd_buffer_clear_subpass(cmd_buffer
);
4213 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4217 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer
*cmd_buffer
)
4219 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4220 const struct radv_subpass
*subpass
= state
->subpass
;
4221 uint32_t subpass_id
= radv_get_subpass_id(cmd_buffer
);
4223 radv_cmd_buffer_resolve_subpass(cmd_buffer
);
4225 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4226 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4227 if (a
== VK_ATTACHMENT_UNUSED
)
4230 if (state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
4233 VkImageLayout layout
= state
->pass
->attachments
[a
].final_layout
;
4234 struct radv_subpass_attachment att
= { a
, layout
};
4235 radv_handle_subpass_image_transition(cmd_buffer
, att
, false);
4239 void radv_CmdBeginRenderPass(
4240 VkCommandBuffer commandBuffer
,
4241 const VkRenderPassBeginInfo
* pRenderPassBegin
,
4242 VkSubpassContents contents
)
4244 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4245 RADV_FROM_HANDLE(radv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
4246 RADV_FROM_HANDLE(radv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
4249 cmd_buffer
->state
.framebuffer
= framebuffer
;
4250 cmd_buffer
->state
.pass
= pass
;
4251 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
4253 result
= radv_cmd_state_setup_attachments(cmd_buffer
, pass
, pRenderPassBegin
);
4254 if (result
!= VK_SUCCESS
)
4257 result
= radv_cmd_state_setup_sample_locations(cmd_buffer
, pass
, pRenderPassBegin
);
4258 if (result
!= VK_SUCCESS
)
4261 radv_cmd_buffer_begin_subpass(cmd_buffer
, 0);
4264 void radv_CmdBeginRenderPass2KHR(
4265 VkCommandBuffer commandBuffer
,
4266 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
4267 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
)
4269 radv_CmdBeginRenderPass(commandBuffer
, pRenderPassBeginInfo
,
4270 pSubpassBeginInfo
->contents
);
4273 void radv_CmdNextSubpass(
4274 VkCommandBuffer commandBuffer
,
4275 VkSubpassContents contents
)
4277 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4279 uint32_t prev_subpass
= radv_get_subpass_id(cmd_buffer
);
4280 radv_cmd_buffer_end_subpass(cmd_buffer
);
4281 radv_cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
4284 void radv_CmdNextSubpass2KHR(
4285 VkCommandBuffer commandBuffer
,
4286 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
,
4287 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
4289 radv_CmdNextSubpass(commandBuffer
, pSubpassBeginInfo
->contents
);
4292 static void radv_emit_view_index(struct radv_cmd_buffer
*cmd_buffer
, unsigned index
)
4294 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
4295 for (unsigned stage
= 0; stage
< MESA_SHADER_STAGES
; ++stage
) {
4296 if (!radv_get_shader(pipeline
, stage
))
4299 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, AC_UD_VIEW_INDEX
);
4300 if (loc
->sgpr_idx
== -1)
4302 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
4303 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
4306 if (radv_pipeline_has_gs_copy_shader(pipeline
)) {
4307 struct radv_userdata_info
*loc
= &pipeline
->gs_copy_shader
->info
.user_sgprs_locs
.shader_data
[AC_UD_VIEW_INDEX
];
4308 if (loc
->sgpr_idx
!= -1) {
4309 uint32_t base_reg
= R_00B130_SPI_SHADER_USER_DATA_VS_0
;
4310 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
4316 radv_cs_emit_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
4317 uint32_t vertex_count
,
4320 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, cmd_buffer
->state
.predicating
));
4321 radeon_emit(cmd_buffer
->cs
, vertex_count
);
4322 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
4323 S_0287F0_USE_OPAQUE(use_opaque
));
4327 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer
*cmd_buffer
,
4329 uint32_t index_count
)
4331 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_2
, 4, cmd_buffer
->state
.predicating
));
4332 radeon_emit(cmd_buffer
->cs
, cmd_buffer
->state
.max_index_count
);
4333 radeon_emit(cmd_buffer
->cs
, index_va
);
4334 radeon_emit(cmd_buffer
->cs
, index_va
>> 32);
4335 radeon_emit(cmd_buffer
->cs
, index_count
);
4336 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_DMA
);
4340 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
4342 uint32_t draw_count
,
4346 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4347 unsigned di_src_sel
= indexed
? V_0287F0_DI_SRC_SEL_DMA
4348 : V_0287F0_DI_SRC_SEL_AUTO_INDEX
;
4349 bool draw_id_enable
= radv_get_shader(cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
)->info
.vs
.needs_draw_id
;
4350 uint32_t base_reg
= cmd_buffer
->state
.pipeline
->graphics
.vtx_base_sgpr
;
4351 bool predicating
= cmd_buffer
->state
.predicating
;
4354 /* just reset draw state for vertex data */
4355 cmd_buffer
->state
.last_first_instance
= -1;
4356 cmd_buffer
->state
.last_num_instances
= -1;
4357 cmd_buffer
->state
.last_vertex_offset
= -1;
4359 if (draw_count
== 1 && !count_va
&& !draw_id_enable
) {
4360 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT
:
4361 PKT3_DRAW_INDIRECT
, 3, predicating
));
4363 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
4364 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
4365 radeon_emit(cs
, di_src_sel
);
4367 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT_MULTI
:
4368 PKT3_DRAW_INDIRECT_MULTI
,
4371 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
4372 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
4373 radeon_emit(cs
, (((base_reg
+ 8) - SI_SH_REG_OFFSET
) >> 2) |
4374 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable
) |
4375 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va
));
4376 radeon_emit(cs
, draw_count
); /* count */
4377 radeon_emit(cs
, count_va
); /* count_addr */
4378 radeon_emit(cs
, count_va
>> 32);
4379 radeon_emit(cs
, stride
); /* stride */
4380 radeon_emit(cs
, di_src_sel
);
4385 radv_emit_draw_packets(struct radv_cmd_buffer
*cmd_buffer
,
4386 const struct radv_draw_info
*info
)
4388 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4389 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
4390 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4392 if (info
->indirect
) {
4393 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
4394 uint64_t count_va
= 0;
4396 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
4398 radv_cs_add_buffer(ws
, cs
, info
->indirect
->bo
);
4400 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0));
4402 radeon_emit(cs
, va
);
4403 radeon_emit(cs
, va
>> 32);
4405 if (info
->count_buffer
) {
4406 count_va
= radv_buffer_get_va(info
->count_buffer
->bo
);
4407 count_va
+= info
->count_buffer
->offset
+
4408 info
->count_buffer_offset
;
4410 radv_cs_add_buffer(ws
, cs
, info
->count_buffer
->bo
);
4413 if (!state
->subpass
->view_mask
) {
4414 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
4421 for_each_bit(i
, state
->subpass
->view_mask
) {
4422 radv_emit_view_index(cmd_buffer
, i
);
4424 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
4432 assert(state
->pipeline
->graphics
.vtx_base_sgpr
);
4434 if (info
->vertex_offset
!= state
->last_vertex_offset
||
4435 info
->first_instance
!= state
->last_first_instance
) {
4436 radeon_set_sh_reg_seq(cs
, state
->pipeline
->graphics
.vtx_base_sgpr
,
4437 state
->pipeline
->graphics
.vtx_emit_num
);
4439 radeon_emit(cs
, info
->vertex_offset
);
4440 radeon_emit(cs
, info
->first_instance
);
4441 if (state
->pipeline
->graphics
.vtx_emit_num
== 3)
4443 state
->last_first_instance
= info
->first_instance
;
4444 state
->last_vertex_offset
= info
->vertex_offset
;
4447 if (state
->last_num_instances
!= info
->instance_count
) {
4448 radeon_emit(cs
, PKT3(PKT3_NUM_INSTANCES
, 0, false));
4449 radeon_emit(cs
, info
->instance_count
);
4450 state
->last_num_instances
= info
->instance_count
;
4453 if (info
->indexed
) {
4454 int index_size
= radv_get_vgt_index_size(state
->index_type
);
4457 /* Skip draw calls with 0-sized index buffers. They
4458 * cause a hang on some chips, like Navi10-14.
4460 if (!cmd_buffer
->state
.max_index_count
)
4463 index_va
= state
->index_va
;
4464 index_va
+= info
->first_index
* index_size
;
4466 if (!state
->subpass
->view_mask
) {
4467 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
4472 for_each_bit(i
, state
->subpass
->view_mask
) {
4473 radv_emit_view_index(cmd_buffer
, i
);
4475 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
4481 if (!state
->subpass
->view_mask
) {
4482 radv_cs_emit_draw_packet(cmd_buffer
,
4484 !!info
->strmout_buffer
);
4487 for_each_bit(i
, state
->subpass
->view_mask
) {
4488 radv_emit_view_index(cmd_buffer
, i
);
4490 radv_cs_emit_draw_packet(cmd_buffer
,
4492 !!info
->strmout_buffer
);
4500 * Vega and raven have a bug which triggers if there are multiple context
4501 * register contexts active at the same time with different scissor values.
4503 * There are two possible workarounds:
4504 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
4505 * there is only ever 1 active set of scissor values at the same time.
4507 * 2) Whenever the hardware switches contexts we have to set the scissor
4508 * registers again even if it is a noop. That way the new context gets
4509 * the correct scissor values.
4511 * This implements option 2. radv_need_late_scissor_emission needs to
4512 * return true on affected HW if radv_emit_all_graphics_states sets
4513 * any context registers.
4515 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer
*cmd_buffer
,
4516 const struct radv_draw_info
*info
)
4518 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4520 if (!cmd_buffer
->device
->physical_device
->rad_info
.has_gfx9_scissor_bug
)
4523 if (cmd_buffer
->state
.context_roll_without_scissor_emitted
|| info
->strmout_buffer
)
4526 uint32_t used_states
= cmd_buffer
->state
.pipeline
->graphics
.needed_dynamic_state
| ~RADV_CMD_DIRTY_DYNAMIC_ALL
;
4528 /* Index, vertex and streamout buffers don't change context regs, and
4529 * pipeline is already handled.
4531 used_states
&= ~(RADV_CMD_DIRTY_INDEX_BUFFER
|
4532 RADV_CMD_DIRTY_VERTEX_BUFFER
|
4533 RADV_CMD_DIRTY_STREAMOUT_BUFFER
|
4534 RADV_CMD_DIRTY_PIPELINE
);
4536 if (cmd_buffer
->state
.dirty
& used_states
)
4539 uint32_t primitive_reset_index
=
4540 radv_get_primitive_reset_index(cmd_buffer
);
4542 if (info
->indexed
&& state
->pipeline
->graphics
.prim_restart_enable
&&
4543 primitive_reset_index
!= state
->last_primitive_reset_index
)
4550 radv_emit_all_graphics_states(struct radv_cmd_buffer
*cmd_buffer
,
4551 const struct radv_draw_info
*info
)
4553 bool late_scissor_emission
;
4555 if ((cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
) ||
4556 cmd_buffer
->state
.emitted_pipeline
!= cmd_buffer
->state
.pipeline
)
4557 radv_emit_rbplus_state(cmd_buffer
);
4559 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
)
4560 radv_emit_graphics_pipeline(cmd_buffer
);
4562 /* This should be before the cmd_buffer->state.dirty is cleared
4563 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4564 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4565 late_scissor_emission
=
4566 radv_need_late_scissor_emission(cmd_buffer
, info
);
4568 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
)
4569 radv_emit_framebuffer_state(cmd_buffer
);
4571 if (info
->indexed
) {
4572 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_INDEX_BUFFER
)
4573 radv_emit_index_buffer(cmd_buffer
);
4575 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4576 * so the state must be re-emitted before the next indexed
4579 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4580 cmd_buffer
->state
.last_index_type
= -1;
4581 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
4585 radv_cmd_buffer_flush_dynamic_state(cmd_buffer
);
4587 radv_emit_draw_registers(cmd_buffer
, info
);
4589 if (late_scissor_emission
)
4590 radv_emit_scissor(cmd_buffer
);
4594 radv_draw(struct radv_cmd_buffer
*cmd_buffer
,
4595 const struct radv_draw_info
*info
)
4597 struct radeon_info
*rad_info
=
4598 &cmd_buffer
->device
->physical_device
->rad_info
;
4600 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
4601 bool pipeline_is_dirty
=
4602 (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
) &&
4603 cmd_buffer
->state
.pipeline
!= cmd_buffer
->state
.emitted_pipeline
;
4605 ASSERTED
unsigned cdw_max
=
4606 radeon_check_space(cmd_buffer
->device
->ws
,
4607 cmd_buffer
->cs
, 4096);
4609 if (likely(!info
->indirect
)) {
4610 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4611 * no workaround for indirect draws, but we can at least skip
4614 if (unlikely(!info
->instance_count
))
4617 /* Handle count == 0. */
4618 if (unlikely(!info
->count
&& !info
->strmout_buffer
))
4622 /* Use optimal packet order based on whether we need to sync the
4625 if (cmd_buffer
->state
.flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4626 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4627 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
4628 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)) {
4629 /* If we have to wait for idle, set all states first, so that
4630 * all SET packets are processed in parallel with previous draw
4631 * calls. Then upload descriptors, set shader pointers, and
4632 * draw, and prefetch at the end. This ensures that the time
4633 * the CUs are idle is very short. (there are only SET_SH
4634 * packets between the wait and the draw)
4636 radv_emit_all_graphics_states(cmd_buffer
, info
);
4637 si_emit_cache_flush(cmd_buffer
);
4638 /* <-- CUs are idle here --> */
4640 radv_upload_graphics_shader_descriptors(cmd_buffer
, pipeline_is_dirty
);
4642 radv_emit_draw_packets(cmd_buffer
, info
);
4643 /* <-- CUs are busy here --> */
4645 /* Start prefetches after the draw has been started. Both will
4646 * run in parallel, but starting the draw first is more
4649 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
4650 radv_emit_prefetch_L2(cmd_buffer
,
4651 cmd_buffer
->state
.pipeline
, false);
4654 /* If we don't wait for idle, start prefetches first, then set
4655 * states, and draw at the end.
4657 si_emit_cache_flush(cmd_buffer
);
4659 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
4660 /* Only prefetch the vertex shader and VBO descriptors
4661 * in order to start the draw as soon as possible.
4663 radv_emit_prefetch_L2(cmd_buffer
,
4664 cmd_buffer
->state
.pipeline
, true);
4667 radv_upload_graphics_shader_descriptors(cmd_buffer
, pipeline_is_dirty
);
4669 radv_emit_all_graphics_states(cmd_buffer
, info
);
4670 radv_emit_draw_packets(cmd_buffer
, info
);
4672 /* Prefetch the remaining shaders after the draw has been
4675 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
4676 radv_emit_prefetch_L2(cmd_buffer
,
4677 cmd_buffer
->state
.pipeline
, false);
4681 /* Workaround for a VGT hang when streamout is enabled.
4682 * It must be done after drawing.
4684 if (cmd_buffer
->state
.streamout
.streamout_enabled
&&
4685 (rad_info
->family
== CHIP_HAWAII
||
4686 rad_info
->family
== CHIP_TONGA
||
4687 rad_info
->family
== CHIP_FIJI
)) {
4688 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC
;
4691 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4692 radv_cmd_buffer_after_draw(cmd_buffer
, RADV_CMD_FLAG_PS_PARTIAL_FLUSH
);
4696 VkCommandBuffer commandBuffer
,
4697 uint32_t vertexCount
,
4698 uint32_t instanceCount
,
4699 uint32_t firstVertex
,
4700 uint32_t firstInstance
)
4702 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4703 struct radv_draw_info info
= {};
4705 info
.count
= vertexCount
;
4706 info
.instance_count
= instanceCount
;
4707 info
.first_instance
= firstInstance
;
4708 info
.vertex_offset
= firstVertex
;
4710 radv_draw(cmd_buffer
, &info
);
4713 void radv_CmdDrawIndexed(
4714 VkCommandBuffer commandBuffer
,
4715 uint32_t indexCount
,
4716 uint32_t instanceCount
,
4717 uint32_t firstIndex
,
4718 int32_t vertexOffset
,
4719 uint32_t firstInstance
)
4721 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4722 struct radv_draw_info info
= {};
4724 info
.indexed
= true;
4725 info
.count
= indexCount
;
4726 info
.instance_count
= instanceCount
;
4727 info
.first_index
= firstIndex
;
4728 info
.vertex_offset
= vertexOffset
;
4729 info
.first_instance
= firstInstance
;
4731 radv_draw(cmd_buffer
, &info
);
4734 void radv_CmdDrawIndirect(
4735 VkCommandBuffer commandBuffer
,
4737 VkDeviceSize offset
,
4741 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4742 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4743 struct radv_draw_info info
= {};
4745 info
.count
= drawCount
;
4746 info
.indirect
= buffer
;
4747 info
.indirect_offset
= offset
;
4748 info
.stride
= stride
;
4750 radv_draw(cmd_buffer
, &info
);
4753 void radv_CmdDrawIndexedIndirect(
4754 VkCommandBuffer commandBuffer
,
4756 VkDeviceSize offset
,
4760 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4761 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4762 struct radv_draw_info info
= {};
4764 info
.indexed
= true;
4765 info
.count
= drawCount
;
4766 info
.indirect
= buffer
;
4767 info
.indirect_offset
= offset
;
4768 info
.stride
= stride
;
4770 radv_draw(cmd_buffer
, &info
);
4773 void radv_CmdDrawIndirectCountKHR(
4774 VkCommandBuffer commandBuffer
,
4776 VkDeviceSize offset
,
4777 VkBuffer _countBuffer
,
4778 VkDeviceSize countBufferOffset
,
4779 uint32_t maxDrawCount
,
4782 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4783 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4784 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
4785 struct radv_draw_info info
= {};
4787 info
.count
= maxDrawCount
;
4788 info
.indirect
= buffer
;
4789 info
.indirect_offset
= offset
;
4790 info
.count_buffer
= count_buffer
;
4791 info
.count_buffer_offset
= countBufferOffset
;
4792 info
.stride
= stride
;
4794 radv_draw(cmd_buffer
, &info
);
4797 void radv_CmdDrawIndexedIndirectCountKHR(
4798 VkCommandBuffer commandBuffer
,
4800 VkDeviceSize offset
,
4801 VkBuffer _countBuffer
,
4802 VkDeviceSize countBufferOffset
,
4803 uint32_t maxDrawCount
,
4806 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4807 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4808 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
4809 struct radv_draw_info info
= {};
4811 info
.indexed
= true;
4812 info
.count
= maxDrawCount
;
4813 info
.indirect
= buffer
;
4814 info
.indirect_offset
= offset
;
4815 info
.count_buffer
= count_buffer
;
4816 info
.count_buffer_offset
= countBufferOffset
;
4817 info
.stride
= stride
;
4819 radv_draw(cmd_buffer
, &info
);
4822 struct radv_dispatch_info
{
4824 * Determine the layout of the grid (in block units) to be used.
4829 * A starting offset for the grid. If unaligned is set, the offset
4830 * must still be aligned.
4832 uint32_t offsets
[3];
4834 * Whether it's an unaligned compute dispatch.
4839 * Indirect compute parameters resource.
4841 struct radv_buffer
*indirect
;
4842 uint64_t indirect_offset
;
4846 radv_emit_dispatch_packets(struct radv_cmd_buffer
*cmd_buffer
,
4847 const struct radv_dispatch_info
*info
)
4849 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
4850 struct radv_shader_variant
*compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
4851 unsigned dispatch_initiator
= cmd_buffer
->device
->dispatch_initiator
;
4852 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
4853 bool predicating
= cmd_buffer
->state
.predicating
;
4854 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4855 struct radv_userdata_info
*loc
;
4857 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_COMPUTE
,
4858 AC_UD_CS_GRID_SIZE
);
4860 ASSERTED
unsigned cdw_max
= radeon_check_space(ws
, cs
, 25);
4862 if (compute_shader
->info
.wave_size
== 32) {
4863 assert(cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
);
4864 dispatch_initiator
|= S_00B800_CS_W32_EN(1);
4867 if (info
->indirect
) {
4868 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
4870 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
4872 radv_cs_add_buffer(ws
, cs
, info
->indirect
->bo
);
4874 if (loc
->sgpr_idx
!= -1) {
4875 for (unsigned i
= 0; i
< 3; ++i
) {
4876 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
4877 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
4878 COPY_DATA_DST_SEL(COPY_DATA_REG
));
4879 radeon_emit(cs
, (va
+ 4 * i
));
4880 radeon_emit(cs
, (va
+ 4 * i
) >> 32);
4881 radeon_emit(cs
, ((R_00B900_COMPUTE_USER_DATA_0
4882 + loc
->sgpr_idx
* 4) >> 2) + i
);
4887 if (radv_cmd_buffer_uses_mec(cmd_buffer
)) {
4888 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 2, predicating
) |
4889 PKT3_SHADER_TYPE_S(1));
4890 radeon_emit(cs
, va
);
4891 radeon_emit(cs
, va
>> 32);
4892 radeon_emit(cs
, dispatch_initiator
);
4894 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0) |
4895 PKT3_SHADER_TYPE_S(1));
4897 radeon_emit(cs
, va
);
4898 radeon_emit(cs
, va
>> 32);
4900 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 1, predicating
) |
4901 PKT3_SHADER_TYPE_S(1));
4903 radeon_emit(cs
, dispatch_initiator
);
4906 unsigned blocks
[3] = { info
->blocks
[0], info
->blocks
[1], info
->blocks
[2] };
4907 unsigned offsets
[3] = { info
->offsets
[0], info
->offsets
[1], info
->offsets
[2] };
4909 if (info
->unaligned
) {
4910 unsigned *cs_block_size
= compute_shader
->info
.cs
.block_size
;
4911 unsigned remainder
[3];
4913 /* If aligned, these should be an entire block size,
4916 remainder
[0] = blocks
[0] + cs_block_size
[0] -
4917 align_u32_npot(blocks
[0], cs_block_size
[0]);
4918 remainder
[1] = blocks
[1] + cs_block_size
[1] -
4919 align_u32_npot(blocks
[1], cs_block_size
[1]);
4920 remainder
[2] = blocks
[2] + cs_block_size
[2] -
4921 align_u32_npot(blocks
[2], cs_block_size
[2]);
4923 blocks
[0] = round_up_u32(blocks
[0], cs_block_size
[0]);
4924 blocks
[1] = round_up_u32(blocks
[1], cs_block_size
[1]);
4925 blocks
[2] = round_up_u32(blocks
[2], cs_block_size
[2]);
4927 for(unsigned i
= 0; i
< 3; ++i
) {
4928 assert(offsets
[i
] % cs_block_size
[i
] == 0);
4929 offsets
[i
] /= cs_block_size
[i
];
4932 radeon_set_sh_reg_seq(cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
4934 S_00B81C_NUM_THREAD_FULL(cs_block_size
[0]) |
4935 S_00B81C_NUM_THREAD_PARTIAL(remainder
[0]));
4937 S_00B81C_NUM_THREAD_FULL(cs_block_size
[1]) |
4938 S_00B81C_NUM_THREAD_PARTIAL(remainder
[1]));
4940 S_00B81C_NUM_THREAD_FULL(cs_block_size
[2]) |
4941 S_00B81C_NUM_THREAD_PARTIAL(remainder
[2]));
4943 dispatch_initiator
|= S_00B800_PARTIAL_TG_EN(1);
4946 if (loc
->sgpr_idx
!= -1) {
4947 assert(loc
->num_sgprs
== 3);
4949 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
+
4950 loc
->sgpr_idx
* 4, 3);
4951 radeon_emit(cs
, blocks
[0]);
4952 radeon_emit(cs
, blocks
[1]);
4953 radeon_emit(cs
, blocks
[2]);
4956 if (offsets
[0] || offsets
[1] || offsets
[2]) {
4957 radeon_set_sh_reg_seq(cs
, R_00B810_COMPUTE_START_X
, 3);
4958 radeon_emit(cs
, offsets
[0]);
4959 radeon_emit(cs
, offsets
[1]);
4960 radeon_emit(cs
, offsets
[2]);
4962 /* The blocks in the packet are not counts but end values. */
4963 for (unsigned i
= 0; i
< 3; ++i
)
4964 blocks
[i
] += offsets
[i
];
4966 dispatch_initiator
|= S_00B800_FORCE_START_AT_000(1);
4969 radeon_emit(cs
, PKT3(PKT3_DISPATCH_DIRECT
, 3, predicating
) |
4970 PKT3_SHADER_TYPE_S(1));
4971 radeon_emit(cs
, blocks
[0]);
4972 radeon_emit(cs
, blocks
[1]);
4973 radeon_emit(cs
, blocks
[2]);
4974 radeon_emit(cs
, dispatch_initiator
);
4977 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4981 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
4983 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
4984 radv_flush_constants(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
4988 radv_dispatch(struct radv_cmd_buffer
*cmd_buffer
,
4989 const struct radv_dispatch_info
*info
)
4991 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
4993 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
4994 bool pipeline_is_dirty
= pipeline
&&
4995 pipeline
!= cmd_buffer
->state
.emitted_compute_pipeline
;
4997 if (cmd_buffer
->state
.flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4998 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4999 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
5000 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)) {
5001 /* If we have to wait for idle, set all states first, so that
5002 * all SET packets are processed in parallel with previous draw
5003 * calls. Then upload descriptors, set shader pointers, and
5004 * dispatch, and prefetch at the end. This ensures that the
5005 * time the CUs are idle is very short. (there are only SET_SH
5006 * packets between the wait and the draw)
5008 radv_emit_compute_pipeline(cmd_buffer
);
5009 si_emit_cache_flush(cmd_buffer
);
5010 /* <-- CUs are idle here --> */
5012 radv_upload_compute_shader_descriptors(cmd_buffer
);
5014 radv_emit_dispatch_packets(cmd_buffer
, info
);
5015 /* <-- CUs are busy here --> */
5017 /* Start prefetches after the dispatch has been started. Both
5018 * will run in parallel, but starting the dispatch first is
5021 if (has_prefetch
&& pipeline_is_dirty
) {
5022 radv_emit_shader_prefetch(cmd_buffer
,
5023 pipeline
->shaders
[MESA_SHADER_COMPUTE
]);
5026 /* If we don't wait for idle, start prefetches first, then set
5027 * states, and dispatch at the end.
5029 si_emit_cache_flush(cmd_buffer
);
5031 if (has_prefetch
&& pipeline_is_dirty
) {
5032 radv_emit_shader_prefetch(cmd_buffer
,
5033 pipeline
->shaders
[MESA_SHADER_COMPUTE
]);
5036 radv_upload_compute_shader_descriptors(cmd_buffer
);
5038 radv_emit_compute_pipeline(cmd_buffer
);
5039 radv_emit_dispatch_packets(cmd_buffer
, info
);
5042 radv_cmd_buffer_after_draw(cmd_buffer
, RADV_CMD_FLAG_CS_PARTIAL_FLUSH
);
5045 void radv_CmdDispatchBase(
5046 VkCommandBuffer commandBuffer
,
5054 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5055 struct radv_dispatch_info info
= {};
5061 info
.offsets
[0] = base_x
;
5062 info
.offsets
[1] = base_y
;
5063 info
.offsets
[2] = base_z
;
5064 radv_dispatch(cmd_buffer
, &info
);
5067 void radv_CmdDispatch(
5068 VkCommandBuffer commandBuffer
,
5073 radv_CmdDispatchBase(commandBuffer
, 0, 0, 0, x
, y
, z
);
5076 void radv_CmdDispatchIndirect(
5077 VkCommandBuffer commandBuffer
,
5079 VkDeviceSize offset
)
5081 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5082 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
5083 struct radv_dispatch_info info
= {};
5085 info
.indirect
= buffer
;
5086 info
.indirect_offset
= offset
;
5088 radv_dispatch(cmd_buffer
, &info
);
5091 void radv_unaligned_dispatch(
5092 struct radv_cmd_buffer
*cmd_buffer
,
5097 struct radv_dispatch_info info
= {};
5104 radv_dispatch(cmd_buffer
, &info
);
5107 void radv_CmdEndRenderPass(
5108 VkCommandBuffer commandBuffer
)
5110 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5112 radv_subpass_barrier(cmd_buffer
, &cmd_buffer
->state
.pass
->end_barrier
);
5114 radv_cmd_buffer_end_subpass(cmd_buffer
);
5116 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
5117 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.subpass_sample_locs
);
5119 cmd_buffer
->state
.pass
= NULL
;
5120 cmd_buffer
->state
.subpass
= NULL
;
5121 cmd_buffer
->state
.attachments
= NULL
;
5122 cmd_buffer
->state
.framebuffer
= NULL
;
5123 cmd_buffer
->state
.subpass_sample_locs
= NULL
;
5126 void radv_CmdEndRenderPass2KHR(
5127 VkCommandBuffer commandBuffer
,
5128 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
5130 radv_CmdEndRenderPass(commandBuffer
);
5134 * For HTILE we have the following interesting clear words:
5135 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
5136 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
5137 * 0xfffffff0: Clear depth to 1.0
5138 * 0x00000000: Clear depth to 0.0
5140 static void radv_initialize_htile(struct radv_cmd_buffer
*cmd_buffer
,
5141 struct radv_image
*image
,
5142 const VkImageSubresourceRange
*range
,
5143 uint32_t clear_word
)
5145 assert(range
->baseMipLevel
== 0);
5146 assert(range
->levelCount
== 1 || range
->levelCount
== VK_REMAINING_ARRAY_LAYERS
);
5147 VkImageAspectFlags aspects
= VK_IMAGE_ASPECT_DEPTH_BIT
;
5148 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
5149 VkClearDepthStencilValue value
= {};
5151 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
5152 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
5154 state
->flush_bits
|= radv_clear_htile(cmd_buffer
, image
, range
, clear_word
);
5156 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
5158 if (vk_format_is_stencil(image
->vk_format
))
5159 aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
5161 radv_set_ds_clear_metadata(cmd_buffer
, image
, range
, value
, aspects
);
5163 if (radv_image_is_tc_compat_htile(image
)) {
5164 /* Initialize the TC-compat metada value to 0 because by
5165 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
5166 * need have to conditionally update its value when performing
5167 * a fast depth clear.
5169 radv_set_tc_compat_zrange_metadata(cmd_buffer
, image
, range
, 0);
5173 static void radv_handle_depth_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
5174 struct radv_image
*image
,
5175 VkImageLayout src_layout
,
5176 bool src_render_loop
,
5177 VkImageLayout dst_layout
,
5178 bool dst_render_loop
,
5179 unsigned src_queue_mask
,
5180 unsigned dst_queue_mask
,
5181 const VkImageSubresourceRange
*range
,
5182 struct radv_sample_locations_state
*sample_locs
)
5184 if (!radv_image_has_htile(image
))
5187 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
5188 uint32_t clear_value
= vk_format_is_stencil(image
->vk_format
) ? 0xfffff30f : 0xfffc000f;
5190 if (radv_layout_is_htile_compressed(image
, dst_layout
, dst_render_loop
,
5195 radv_initialize_htile(cmd_buffer
, image
, range
, clear_value
);
5196 } else if (!radv_layout_is_htile_compressed(image
, src_layout
, src_render_loop
, src_queue_mask
) &&
5197 radv_layout_is_htile_compressed(image
, dst_layout
, dst_render_loop
, dst_queue_mask
)) {
5198 uint32_t clear_value
= vk_format_is_stencil(image
->vk_format
) ? 0xfffff30f : 0xfffc000f;
5199 radv_initialize_htile(cmd_buffer
, image
, range
, clear_value
);
5200 } else if (radv_layout_is_htile_compressed(image
, src_layout
, src_render_loop
, src_queue_mask
) &&
5201 !radv_layout_is_htile_compressed(image
, dst_layout
, dst_render_loop
, dst_queue_mask
)) {
5202 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
5203 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
5205 radv_decompress_depth_image_inplace(cmd_buffer
, image
, range
,
5208 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
5209 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
5213 static void radv_initialise_cmask(struct radv_cmd_buffer
*cmd_buffer
,
5214 struct radv_image
*image
,
5215 const VkImageSubresourceRange
*range
,
5218 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
5220 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
5221 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5223 state
->flush_bits
|= radv_clear_cmask(cmd_buffer
, image
, range
, value
);
5225 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5228 void radv_initialize_fmask(struct radv_cmd_buffer
*cmd_buffer
,
5229 struct radv_image
*image
,
5230 const VkImageSubresourceRange
*range
)
5232 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
5233 static const uint32_t fmask_clear_values
[4] = {
5239 uint32_t log2_samples
= util_logbase2(image
->info
.samples
);
5240 uint32_t value
= fmask_clear_values
[log2_samples
];
5242 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
5243 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5245 state
->flush_bits
|= radv_clear_fmask(cmd_buffer
, image
, range
, value
);
5247 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5250 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
5251 struct radv_image
*image
,
5252 const VkImageSubresourceRange
*range
, uint32_t value
)
5254 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
5257 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
5258 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5260 state
->flush_bits
|= radv_clear_dcc(cmd_buffer
, image
, range
, value
);
5262 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX8
) {
5263 /* When DCC is enabled with mipmaps, some levels might not
5264 * support fast clears and we have to initialize them as "fully
5267 /* Compute the size of all fast clearable DCC levels. */
5268 for (unsigned i
= 0; i
< image
->planes
[0].surface
.num_dcc_levels
; i
++) {
5269 struct legacy_surf_level
*surf_level
=
5270 &image
->planes
[0].surface
.u
.legacy
.level
[i
];
5271 unsigned dcc_fast_clear_size
=
5272 surf_level
->dcc_slice_fast_clear_size
* image
->info
.array_size
;
5274 if (!dcc_fast_clear_size
)
5277 size
= surf_level
->dcc_offset
+ dcc_fast_clear_size
;
5280 /* Initialize the mipmap levels without DCC. */
5281 if (size
!= image
->planes
[0].surface
.dcc_size
) {
5282 state
->flush_bits
|=
5283 radv_fill_buffer(cmd_buffer
, image
->bo
,
5284 image
->offset
+ image
->dcc_offset
+ size
,
5285 image
->planes
[0].surface
.dcc_size
- size
,
5290 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
5291 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5295 * Initialize DCC/FMASK/CMASK metadata for a color image.
5297 static void radv_init_color_image_metadata(struct radv_cmd_buffer
*cmd_buffer
,
5298 struct radv_image
*image
,
5299 VkImageLayout src_layout
,
5300 bool src_render_loop
,
5301 VkImageLayout dst_layout
,
5302 bool dst_render_loop
,
5303 unsigned src_queue_mask
,
5304 unsigned dst_queue_mask
,
5305 const VkImageSubresourceRange
*range
)
5307 if (radv_image_has_cmask(image
)) {
5308 uint32_t value
= 0xffffffffu
; /* Fully expanded mode. */
5310 /* TODO: clarify this. */
5311 if (radv_image_has_fmask(image
)) {
5312 value
= 0xccccccccu
;
5315 radv_initialise_cmask(cmd_buffer
, image
, range
, value
);
5318 if (radv_image_has_fmask(image
)) {
5319 radv_initialize_fmask(cmd_buffer
, image
, range
);
5322 if (radv_dcc_enabled(image
, range
->baseMipLevel
)) {
5323 uint32_t value
= 0xffffffffu
; /* Fully expanded mode. */
5324 bool need_decompress_pass
= false;
5326 if (radv_layout_dcc_compressed(cmd_buffer
->device
, image
, dst_layout
,
5329 value
= 0x20202020u
;
5330 need_decompress_pass
= true;
5333 radv_initialize_dcc(cmd_buffer
, image
, range
, value
);
5335 radv_update_fce_metadata(cmd_buffer
, image
, range
,
5336 need_decompress_pass
);
5339 if (radv_image_has_cmask(image
) ||
5340 radv_dcc_enabled(image
, range
->baseMipLevel
)) {
5341 uint32_t color_values
[2] = {};
5342 radv_set_color_clear_metadata(cmd_buffer
, image
, range
,
5348 * Handle color image transitions for DCC/FMASK/CMASK.
5350 static void radv_handle_color_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
5351 struct radv_image
*image
,
5352 VkImageLayout src_layout
,
5353 bool src_render_loop
,
5354 VkImageLayout dst_layout
,
5355 bool dst_render_loop
,
5356 unsigned src_queue_mask
,
5357 unsigned dst_queue_mask
,
5358 const VkImageSubresourceRange
*range
)
5360 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
5361 radv_init_color_image_metadata(cmd_buffer
, image
,
5362 src_layout
, src_render_loop
,
5363 dst_layout
, dst_render_loop
,
5364 src_queue_mask
, dst_queue_mask
,
5369 if (radv_dcc_enabled(image
, range
->baseMipLevel
)) {
5370 if (src_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
5371 radv_initialize_dcc(cmd_buffer
, image
, range
, 0xffffffffu
);
5372 } else if (radv_layout_dcc_compressed(cmd_buffer
->device
, image
, src_layout
, src_render_loop
, src_queue_mask
) &&
5373 !radv_layout_dcc_compressed(cmd_buffer
->device
, image
, dst_layout
, dst_render_loop
, dst_queue_mask
)) {
5374 radv_decompress_dcc(cmd_buffer
, image
, range
);
5375 } else if (radv_layout_can_fast_clear(image
, src_layout
, src_render_loop
, src_queue_mask
) &&
5376 !radv_layout_can_fast_clear(image
, dst_layout
, dst_render_loop
, dst_queue_mask
)) {
5377 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
5379 } else if (radv_image_has_cmask(image
) || radv_image_has_fmask(image
)) {
5380 bool fce_eliminate
= false, fmask_expand
= false;
5382 if (radv_layout_can_fast_clear(image
, src_layout
, src_render_loop
, src_queue_mask
) &&
5383 !radv_layout_can_fast_clear(image
, dst_layout
, dst_render_loop
, dst_queue_mask
)) {
5384 fce_eliminate
= true;
5387 if (radv_image_has_fmask(image
)) {
5388 if (src_layout
!= VK_IMAGE_LAYOUT_GENERAL
&&
5389 dst_layout
== VK_IMAGE_LAYOUT_GENERAL
) {
5390 /* A FMASK decompress is required before doing
5391 * a MSAA decompress using FMASK.
5393 fmask_expand
= true;
5397 if (fce_eliminate
|| fmask_expand
)
5398 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
5401 radv_expand_fmask_image_inplace(cmd_buffer
, image
, range
);
5405 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
5406 struct radv_image
*image
,
5407 VkImageLayout src_layout
,
5408 bool src_render_loop
,
5409 VkImageLayout dst_layout
,
5410 bool dst_render_loop
,
5411 uint32_t src_family
,
5412 uint32_t dst_family
,
5413 const VkImageSubresourceRange
*range
,
5414 struct radv_sample_locations_state
*sample_locs
)
5416 if (image
->exclusive
&& src_family
!= dst_family
) {
5417 /* This is an acquire or a release operation and there will be
5418 * a corresponding release/acquire. Do the transition in the
5419 * most flexible queue. */
5421 assert(src_family
== cmd_buffer
->queue_family_index
||
5422 dst_family
== cmd_buffer
->queue_family_index
);
5424 if (src_family
== VK_QUEUE_FAMILY_EXTERNAL
||
5425 src_family
== VK_QUEUE_FAMILY_FOREIGN_EXT
)
5428 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_TRANSFER
)
5431 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
5432 (src_family
== RADV_QUEUE_GENERAL
||
5433 dst_family
== RADV_QUEUE_GENERAL
))
5437 if (src_layout
== dst_layout
)
5440 unsigned src_queue_mask
=
5441 radv_image_queue_family_mask(image
, src_family
,
5442 cmd_buffer
->queue_family_index
);
5443 unsigned dst_queue_mask
=
5444 radv_image_queue_family_mask(image
, dst_family
,
5445 cmd_buffer
->queue_family_index
);
5447 if (vk_format_is_depth(image
->vk_format
)) {
5448 radv_handle_depth_image_transition(cmd_buffer
, image
,
5449 src_layout
, src_render_loop
,
5450 dst_layout
, dst_render_loop
,
5451 src_queue_mask
, dst_queue_mask
,
5452 range
, sample_locs
);
5454 radv_handle_color_image_transition(cmd_buffer
, image
,
5455 src_layout
, src_render_loop
,
5456 dst_layout
, dst_render_loop
,
5457 src_queue_mask
, dst_queue_mask
,
5462 struct radv_barrier_info
{
5463 uint32_t eventCount
;
5464 const VkEvent
*pEvents
;
5465 VkPipelineStageFlags srcStageMask
;
5466 VkPipelineStageFlags dstStageMask
;
5470 radv_barrier(struct radv_cmd_buffer
*cmd_buffer
,
5471 uint32_t memoryBarrierCount
,
5472 const VkMemoryBarrier
*pMemoryBarriers
,
5473 uint32_t bufferMemoryBarrierCount
,
5474 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
5475 uint32_t imageMemoryBarrierCount
,
5476 const VkImageMemoryBarrier
*pImageMemoryBarriers
,
5477 const struct radv_barrier_info
*info
)
5479 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5480 enum radv_cmd_flush_bits src_flush_bits
= 0;
5481 enum radv_cmd_flush_bits dst_flush_bits
= 0;
5483 for (unsigned i
= 0; i
< info
->eventCount
; ++i
) {
5484 RADV_FROM_HANDLE(radv_event
, event
, info
->pEvents
[i
]);
5485 uint64_t va
= radv_buffer_get_va(event
->bo
);
5487 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, event
->bo
);
5489 ASSERTED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 7);
5491 radv_cp_wait_mem(cs
, WAIT_REG_MEM_EQUAL
, va
, 1, 0xffffffff);
5492 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
5495 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
5496 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pMemoryBarriers
[i
].srcAccessMask
,
5498 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pMemoryBarriers
[i
].dstAccessMask
,
5502 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
5503 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].srcAccessMask
,
5505 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].dstAccessMask
,
5509 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
5510 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
5512 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].srcAccessMask
,
5514 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].dstAccessMask
,
5518 /* The Vulkan spec 1.1.98 says:
5520 * "An execution dependency with only
5521 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
5522 * will only prevent that stage from executing in subsequently
5523 * submitted commands. As this stage does not perform any actual
5524 * execution, this is not observable - in effect, it does not delay
5525 * processing of subsequent commands. Similarly an execution dependency
5526 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
5527 * will effectively not wait for any prior commands to complete."
5529 if (info
->dstStageMask
!= VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
)
5530 radv_stage_flush(cmd_buffer
, info
->srcStageMask
);
5531 cmd_buffer
->state
.flush_bits
|= src_flush_bits
;
5533 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
5534 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
5536 const struct VkSampleLocationsInfoEXT
*sample_locs_info
=
5537 vk_find_struct_const(pImageMemoryBarriers
[i
].pNext
,
5538 SAMPLE_LOCATIONS_INFO_EXT
);
5539 struct radv_sample_locations_state sample_locations
= {};
5541 if (sample_locs_info
) {
5542 assert(image
->flags
& VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
);
5543 sample_locations
.per_pixel
= sample_locs_info
->sampleLocationsPerPixel
;
5544 sample_locations
.grid_size
= sample_locs_info
->sampleLocationGridSize
;
5545 sample_locations
.count
= sample_locs_info
->sampleLocationsCount
;
5546 typed_memcpy(&sample_locations
.locations
[0],
5547 sample_locs_info
->pSampleLocations
,
5548 sample_locs_info
->sampleLocationsCount
);
5551 radv_handle_image_transition(cmd_buffer
, image
,
5552 pImageMemoryBarriers
[i
].oldLayout
,
5553 false, /* Outside of a renderpass we are never in a renderloop */
5554 pImageMemoryBarriers
[i
].newLayout
,
5555 false, /* Outside of a renderpass we are never in a renderloop */
5556 pImageMemoryBarriers
[i
].srcQueueFamilyIndex
,
5557 pImageMemoryBarriers
[i
].dstQueueFamilyIndex
,
5558 &pImageMemoryBarriers
[i
].subresourceRange
,
5559 sample_locs_info
? &sample_locations
: NULL
);
5562 /* Make sure CP DMA is idle because the driver might have performed a
5563 * DMA operation for copying or filling buffers/images.
5565 if (info
->srcStageMask
& (VK_PIPELINE_STAGE_TRANSFER_BIT
|
5566 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
))
5567 si_cp_dma_wait_for_idle(cmd_buffer
);
5569 cmd_buffer
->state
.flush_bits
|= dst_flush_bits
;
5572 void radv_CmdPipelineBarrier(
5573 VkCommandBuffer commandBuffer
,
5574 VkPipelineStageFlags srcStageMask
,
5575 VkPipelineStageFlags destStageMask
,
5577 uint32_t memoryBarrierCount
,
5578 const VkMemoryBarrier
* pMemoryBarriers
,
5579 uint32_t bufferMemoryBarrierCount
,
5580 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
5581 uint32_t imageMemoryBarrierCount
,
5582 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
5584 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5585 struct radv_barrier_info info
;
5587 info
.eventCount
= 0;
5588 info
.pEvents
= NULL
;
5589 info
.srcStageMask
= srcStageMask
;
5590 info
.dstStageMask
= destStageMask
;
5592 radv_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
5593 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
5594 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
5598 static void write_event(struct radv_cmd_buffer
*cmd_buffer
,
5599 struct radv_event
*event
,
5600 VkPipelineStageFlags stageMask
,
5603 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5604 uint64_t va
= radv_buffer_get_va(event
->bo
);
5606 si_emit_cache_flush(cmd_buffer
);
5608 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, event
->bo
);
5610 ASSERTED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 21);
5612 /* Flags that only require a top-of-pipe event. */
5613 VkPipelineStageFlags top_of_pipe_flags
=
5614 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
;
5616 /* Flags that only require a post-index-fetch event. */
5617 VkPipelineStageFlags post_index_fetch_flags
=
5619 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
5620 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
;
5622 /* Make sure CP DMA is idle because the driver might have performed a
5623 * DMA operation for copying or filling buffers/images.
5625 if (stageMask
& (VK_PIPELINE_STAGE_TRANSFER_BIT
|
5626 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
))
5627 si_cp_dma_wait_for_idle(cmd_buffer
);
5629 /* TODO: Emit EOS events for syncing PS/CS stages. */
5631 if (!(stageMask
& ~top_of_pipe_flags
)) {
5632 /* Just need to sync the PFP engine. */
5633 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
5634 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
5635 S_370_WR_CONFIRM(1) |
5636 S_370_ENGINE_SEL(V_370_PFP
));
5637 radeon_emit(cs
, va
);
5638 radeon_emit(cs
, va
>> 32);
5639 radeon_emit(cs
, value
);
5640 } else if (!(stageMask
& ~post_index_fetch_flags
)) {
5641 /* Sync ME because PFP reads index and indirect buffers. */
5642 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
5643 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
5644 S_370_WR_CONFIRM(1) |
5645 S_370_ENGINE_SEL(V_370_ME
));
5646 radeon_emit(cs
, va
);
5647 radeon_emit(cs
, va
>> 32);
5648 radeon_emit(cs
, value
);
5650 /* Otherwise, sync all prior GPU work using an EOP event. */
5651 si_cs_emit_write_event_eop(cs
,
5652 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
5653 radv_cmd_buffer_uses_mec(cmd_buffer
),
5654 V_028A90_BOTTOM_OF_PIPE_TS
, 0,
5656 EOP_DATA_SEL_VALUE_32BIT
, va
, value
,
5657 cmd_buffer
->gfx9_eop_bug_va
);
5660 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
5663 void radv_CmdSetEvent(VkCommandBuffer commandBuffer
,
5665 VkPipelineStageFlags stageMask
)
5667 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5668 RADV_FROM_HANDLE(radv_event
, event
, _event
);
5670 write_event(cmd_buffer
, event
, stageMask
, 1);
5673 void radv_CmdResetEvent(VkCommandBuffer commandBuffer
,
5675 VkPipelineStageFlags stageMask
)
5677 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5678 RADV_FROM_HANDLE(radv_event
, event
, _event
);
5680 write_event(cmd_buffer
, event
, stageMask
, 0);
5683 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer
,
5684 uint32_t eventCount
,
5685 const VkEvent
* pEvents
,
5686 VkPipelineStageFlags srcStageMask
,
5687 VkPipelineStageFlags dstStageMask
,
5688 uint32_t memoryBarrierCount
,
5689 const VkMemoryBarrier
* pMemoryBarriers
,
5690 uint32_t bufferMemoryBarrierCount
,
5691 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
5692 uint32_t imageMemoryBarrierCount
,
5693 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
5695 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5696 struct radv_barrier_info info
;
5698 info
.eventCount
= eventCount
;
5699 info
.pEvents
= pEvents
;
5700 info
.srcStageMask
= 0;
5702 radv_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
5703 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
5704 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
5708 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer
,
5709 uint32_t deviceMask
)
5714 /* VK_EXT_conditional_rendering */
5715 void radv_CmdBeginConditionalRenderingEXT(
5716 VkCommandBuffer commandBuffer
,
5717 const VkConditionalRenderingBeginInfoEXT
* pConditionalRenderingBegin
)
5719 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5720 RADV_FROM_HANDLE(radv_buffer
, buffer
, pConditionalRenderingBegin
->buffer
);
5721 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5722 bool draw_visible
= true;
5723 uint64_t pred_value
= 0;
5724 uint64_t va
, new_va
;
5725 unsigned pred_offset
;
5727 va
= radv_buffer_get_va(buffer
->bo
) + pConditionalRenderingBegin
->offset
;
5729 /* By default, if the 32-bit value at offset in buffer memory is zero,
5730 * then the rendering commands are discarded, otherwise they are
5731 * executed as normal. If the inverted flag is set, all commands are
5732 * discarded if the value is non zero.
5734 if (pConditionalRenderingBegin
->flags
&
5735 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT
) {
5736 draw_visible
= false;
5739 si_emit_cache_flush(cmd_buffer
);
5741 /* From the Vulkan spec 1.1.107:
5743 * "If the 32-bit value at offset in buffer memory is zero, then the
5744 * rendering commands are discarded, otherwise they are executed as
5745 * normal. If the value of the predicate in buffer memory changes while
5746 * conditional rendering is active, the rendering commands may be
5747 * discarded in an implementation-dependent way. Some implementations
5748 * may latch the value of the predicate upon beginning conditional
5749 * rendering while others may read it before every rendering command."
5751 * But, the AMD hardware treats the predicate as a 64-bit value which
5752 * means we need a workaround in the driver. Luckily, it's not required
5753 * to support if the value changes when predication is active.
5755 * The workaround is as follows:
5756 * 1) allocate a 64-value in the upload BO and initialize it to 0
5757 * 2) copy the 32-bit predicate value to the upload BO
5758 * 3) use the new allocated VA address for predication
5760 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
5761 * in ME (+ sync PFP) instead of PFP.
5763 radv_cmd_buffer_upload_data(cmd_buffer
, 8, 16, &pred_value
, &pred_offset
);
5765 new_va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
) + pred_offset
;
5767 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
5768 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
5769 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM
) |
5770 COPY_DATA_WR_CONFIRM
);
5771 radeon_emit(cs
, va
);
5772 radeon_emit(cs
, va
>> 32);
5773 radeon_emit(cs
, new_va
);
5774 radeon_emit(cs
, new_va
>> 32);
5776 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
5779 /* Enable predication for this command buffer. */
5780 si_emit_set_predication_state(cmd_buffer
, draw_visible
, new_va
);
5781 cmd_buffer
->state
.predicating
= true;
5783 /* Store conditional rendering user info. */
5784 cmd_buffer
->state
.predication_type
= draw_visible
;
5785 cmd_buffer
->state
.predication_va
= new_va
;
5788 void radv_CmdEndConditionalRenderingEXT(
5789 VkCommandBuffer commandBuffer
)
5791 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5793 /* Disable predication for this command buffer. */
5794 si_emit_set_predication_state(cmd_buffer
, false, 0);
5795 cmd_buffer
->state
.predicating
= false;
5797 /* Reset conditional rendering user info. */
5798 cmd_buffer
->state
.predication_type
= -1;
5799 cmd_buffer
->state
.predication_va
= 0;
5802 /* VK_EXT_transform_feedback */
5803 void radv_CmdBindTransformFeedbackBuffersEXT(
5804 VkCommandBuffer commandBuffer
,
5805 uint32_t firstBinding
,
5806 uint32_t bindingCount
,
5807 const VkBuffer
* pBuffers
,
5808 const VkDeviceSize
* pOffsets
,
5809 const VkDeviceSize
* pSizes
)
5811 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5812 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
5813 uint8_t enabled_mask
= 0;
5815 assert(firstBinding
+ bindingCount
<= MAX_SO_BUFFERS
);
5816 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
5817 uint32_t idx
= firstBinding
+ i
;
5819 sb
[idx
].buffer
= radv_buffer_from_handle(pBuffers
[i
]);
5820 sb
[idx
].offset
= pOffsets
[i
];
5821 sb
[idx
].size
= pSizes
[i
];
5823 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
5824 sb
[idx
].buffer
->bo
);
5826 enabled_mask
|= 1 << idx
;
5829 cmd_buffer
->state
.streamout
.enabled_mask
|= enabled_mask
;
5831 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_STREAMOUT_BUFFER
;
5835 radv_emit_streamout_enable(struct radv_cmd_buffer
*cmd_buffer
)
5837 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
5838 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5840 radeon_set_context_reg_seq(cs
, R_028B94_VGT_STRMOUT_CONFIG
, 2);
5842 S_028B94_STREAMOUT_0_EN(so
->streamout_enabled
) |
5843 S_028B94_RAST_STREAM(0) |
5844 S_028B94_STREAMOUT_1_EN(so
->streamout_enabled
) |
5845 S_028B94_STREAMOUT_2_EN(so
->streamout_enabled
) |
5846 S_028B94_STREAMOUT_3_EN(so
->streamout_enabled
));
5847 radeon_emit(cs
, so
->hw_enabled_mask
&
5848 so
->enabled_stream_buffers_mask
);
5850 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
5854 radv_set_streamout_enable(struct radv_cmd_buffer
*cmd_buffer
, bool enable
)
5856 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
5857 bool old_streamout_enabled
= so
->streamout_enabled
;
5858 uint32_t old_hw_enabled_mask
= so
->hw_enabled_mask
;
5860 so
->streamout_enabled
= enable
;
5862 so
->hw_enabled_mask
= so
->enabled_mask
|
5863 (so
->enabled_mask
<< 4) |
5864 (so
->enabled_mask
<< 8) |
5865 (so
->enabled_mask
<< 12);
5867 if (!cmd_buffer
->device
->physical_device
->use_ngg_streamout
&&
5868 ((old_streamout_enabled
!= so
->streamout_enabled
) ||
5869 (old_hw_enabled_mask
!= so
->hw_enabled_mask
)))
5870 radv_emit_streamout_enable(cmd_buffer
);
5872 if (cmd_buffer
->device
->physical_device
->use_ngg_streamout
)
5873 cmd_buffer
->gds_needed
= true;
5876 static void radv_flush_vgt_streamout(struct radv_cmd_buffer
*cmd_buffer
)
5878 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5879 unsigned reg_strmout_cntl
;
5881 /* The register is at different places on different ASICs. */
5882 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
5883 reg_strmout_cntl
= R_0300FC_CP_STRMOUT_CNTL
;
5884 radeon_set_uconfig_reg(cs
, reg_strmout_cntl
, 0);
5886 reg_strmout_cntl
= R_0084FC_CP_STRMOUT_CNTL
;
5887 radeon_set_config_reg(cs
, reg_strmout_cntl
, 0);
5890 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
5891 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH
) | EVENT_INDEX(0));
5893 radeon_emit(cs
, PKT3(PKT3_WAIT_REG_MEM
, 5, 0));
5894 radeon_emit(cs
, WAIT_REG_MEM_EQUAL
); /* wait until the register is equal to the reference value */
5895 radeon_emit(cs
, reg_strmout_cntl
>> 2); /* register */
5897 radeon_emit(cs
, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
5898 radeon_emit(cs
, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
5899 radeon_emit(cs
, 4); /* poll interval */
5903 radv_emit_streamout_begin(struct radv_cmd_buffer
*cmd_buffer
,
5904 uint32_t firstCounterBuffer
,
5905 uint32_t counterBufferCount
,
5906 const VkBuffer
*pCounterBuffers
,
5907 const VkDeviceSize
*pCounterBufferOffsets
)
5910 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
5911 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
5912 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5915 radv_flush_vgt_streamout(cmd_buffer
);
5917 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
5918 for_each_bit(i
, so
->enabled_mask
) {
5919 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
5920 if (counter_buffer_idx
>= 0 && counter_buffer_idx
>= counterBufferCount
)
5921 counter_buffer_idx
= -1;
5923 /* AMD GCN binds streamout buffers as shader resources.
5924 * VGT only counts primitives and tells the shader through
5927 radeon_set_context_reg_seq(cs
, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0
+ 16*i
, 2);
5928 radeon_emit(cs
, sb
[i
].size
>> 2); /* BUFFER_SIZE (in DW) */
5929 radeon_emit(cs
, so
->stride_in_dw
[i
]); /* VTX_STRIDE (in DW) */
5931 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
5933 if (counter_buffer_idx
>= 0 && pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
]) {
5934 /* The array of counter buffers is optional. */
5935 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
5936 uint64_t va
= radv_buffer_get_va(buffer
->bo
);
5938 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
5941 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
5942 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
5943 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5944 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM
)); /* control */
5945 radeon_emit(cs
, 0); /* unused */
5946 radeon_emit(cs
, 0); /* unused */
5947 radeon_emit(cs
, va
); /* src address lo */
5948 radeon_emit(cs
, va
>> 32); /* src address hi */
5950 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, buffer
->bo
);
5952 /* Start from the beginning. */
5953 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
5954 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
5955 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5956 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET
)); /* control */
5957 radeon_emit(cs
, 0); /* unused */
5958 radeon_emit(cs
, 0); /* unused */
5959 radeon_emit(cs
, 0); /* unused */
5960 radeon_emit(cs
, 0); /* unused */
5964 radv_set_streamout_enable(cmd_buffer
, true);
5968 gfx10_emit_streamout_begin(struct radv_cmd_buffer
*cmd_buffer
,
5969 uint32_t firstCounterBuffer
,
5970 uint32_t counterBufferCount
,
5971 const VkBuffer
*pCounterBuffers
,
5972 const VkDeviceSize
*pCounterBufferOffsets
)
5974 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
5975 unsigned last_target
= util_last_bit(so
->enabled_mask
) - 1;
5976 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5979 assert(cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
);
5980 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
5982 /* Sync because the next streamout operation will overwrite GDS and we
5983 * have to make sure it's idle.
5984 * TODO: Improve by tracking if there is a streamout operation in
5987 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VS_PARTIAL_FLUSH
;
5988 si_emit_cache_flush(cmd_buffer
);
5990 for_each_bit(i
, so
->enabled_mask
) {
5991 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
5992 if (counter_buffer_idx
>= 0 && counter_buffer_idx
>= counterBufferCount
)
5993 counter_buffer_idx
= -1;
5995 bool append
= counter_buffer_idx
>= 0 &&
5996 pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
];
6000 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
6002 va
+= radv_buffer_get_va(buffer
->bo
);
6003 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
6005 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, buffer
->bo
);
6008 radeon_emit(cs
, PKT3(PKT3_DMA_DATA
, 5, 0));
6009 radeon_emit(cs
, S_411_SRC_SEL(append
? V_411_SRC_ADDR_TC_L2
: V_411_DATA
) |
6010 S_411_DST_SEL(V_411_GDS
) |
6011 S_411_CP_SYNC(i
== last_target
));
6012 radeon_emit(cs
, va
);
6013 radeon_emit(cs
, va
>> 32);
6014 radeon_emit(cs
, 4 * i
); /* destination in GDS */
6016 radeon_emit(cs
, S_414_BYTE_COUNT_GFX9(4) |
6017 S_414_DISABLE_WR_CONFIRM_GFX9(i
!= last_target
));
6020 radv_set_streamout_enable(cmd_buffer
, true);
6023 void radv_CmdBeginTransformFeedbackEXT(
6024 VkCommandBuffer commandBuffer
,
6025 uint32_t firstCounterBuffer
,
6026 uint32_t counterBufferCount
,
6027 const VkBuffer
* pCounterBuffers
,
6028 const VkDeviceSize
* pCounterBufferOffsets
)
6030 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
6032 if (cmd_buffer
->device
->physical_device
->use_ngg_streamout
) {
6033 gfx10_emit_streamout_begin(cmd_buffer
,
6034 firstCounterBuffer
, counterBufferCount
,
6035 pCounterBuffers
, pCounterBufferOffsets
);
6037 radv_emit_streamout_begin(cmd_buffer
,
6038 firstCounterBuffer
, counterBufferCount
,
6039 pCounterBuffers
, pCounterBufferOffsets
);
6044 radv_emit_streamout_end(struct radv_cmd_buffer
*cmd_buffer
,
6045 uint32_t firstCounterBuffer
,
6046 uint32_t counterBufferCount
,
6047 const VkBuffer
*pCounterBuffers
,
6048 const VkDeviceSize
*pCounterBufferOffsets
)
6050 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
6051 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
6054 radv_flush_vgt_streamout(cmd_buffer
);
6056 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
6057 for_each_bit(i
, so
->enabled_mask
) {
6058 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
6059 if (counter_buffer_idx
>= 0 && counter_buffer_idx
>= counterBufferCount
)
6060 counter_buffer_idx
= -1;
6062 if (counter_buffer_idx
>= 0 && pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
]) {
6063 /* The array of counters buffer is optional. */
6064 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
6065 uint64_t va
= radv_buffer_get_va(buffer
->bo
);
6067 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
6069 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
6070 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
6071 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6072 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE
) |
6073 STRMOUT_STORE_BUFFER_FILLED_SIZE
); /* control */
6074 radeon_emit(cs
, va
); /* dst address lo */
6075 radeon_emit(cs
, va
>> 32); /* dst address hi */
6076 radeon_emit(cs
, 0); /* unused */
6077 radeon_emit(cs
, 0); /* unused */
6079 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, buffer
->bo
);
6082 /* Deactivate transform feedback by zeroing the buffer size.
6083 * The counters (primitives generated, primitives emitted) may
6084 * be enabled even if there is not buffer bound. This ensures
6085 * that the primitives-emitted query won't increment.
6087 radeon_set_context_reg(cs
, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0
+ 16*i
, 0);
6089 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
6092 radv_set_streamout_enable(cmd_buffer
, false);
6096 gfx10_emit_streamout_end(struct radv_cmd_buffer
*cmd_buffer
,
6097 uint32_t firstCounterBuffer
,
6098 uint32_t counterBufferCount
,
6099 const VkBuffer
*pCounterBuffers
,
6100 const VkDeviceSize
*pCounterBufferOffsets
)
6102 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
6103 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
6106 assert(cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
);
6107 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
6109 for_each_bit(i
, so
->enabled_mask
) {
6110 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
6111 if (counter_buffer_idx
>= 0 && counter_buffer_idx
>= counterBufferCount
)
6112 counter_buffer_idx
= -1;
6114 if (counter_buffer_idx
>= 0 && pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
]) {
6115 /* The array of counters buffer is optional. */
6116 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
6117 uint64_t va
= radv_buffer_get_va(buffer
->bo
);
6119 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
6121 si_cs_emit_write_event_eop(cs
,
6122 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
6123 radv_cmd_buffer_uses_mec(cmd_buffer
),
6124 V_028A90_PS_DONE
, 0,
6127 va
, EOP_DATA_GDS(i
, 1), 0);
6129 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, buffer
->bo
);
6133 radv_set_streamout_enable(cmd_buffer
, false);
6136 void radv_CmdEndTransformFeedbackEXT(
6137 VkCommandBuffer commandBuffer
,
6138 uint32_t firstCounterBuffer
,
6139 uint32_t counterBufferCount
,
6140 const VkBuffer
* pCounterBuffers
,
6141 const VkDeviceSize
* pCounterBufferOffsets
)
6143 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
6145 if (cmd_buffer
->device
->physical_device
->use_ngg_streamout
) {
6146 gfx10_emit_streamout_end(cmd_buffer
,
6147 firstCounterBuffer
, counterBufferCount
,
6148 pCounterBuffers
, pCounterBufferOffsets
);
6150 radv_emit_streamout_end(cmd_buffer
,
6151 firstCounterBuffer
, counterBufferCount
,
6152 pCounterBuffers
, pCounterBufferOffsets
);
6156 void radv_CmdDrawIndirectByteCountEXT(
6157 VkCommandBuffer commandBuffer
,
6158 uint32_t instanceCount
,
6159 uint32_t firstInstance
,
6160 VkBuffer _counterBuffer
,
6161 VkDeviceSize counterBufferOffset
,
6162 uint32_t counterOffset
,
6163 uint32_t vertexStride
)
6165 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
6166 RADV_FROM_HANDLE(radv_buffer
, counterBuffer
, _counterBuffer
);
6167 struct radv_draw_info info
= {};
6169 info
.instance_count
= instanceCount
;
6170 info
.first_instance
= firstInstance
;
6171 info
.strmout_buffer
= counterBuffer
;
6172 info
.strmout_buffer_offset
= counterBufferOffset
;
6173 info
.stride
= vertexStride
;
6175 radv_draw(cmd_buffer
, &info
);
6178 /* VK_AMD_buffer_marker */
6179 void radv_CmdWriteBufferMarkerAMD(
6180 VkCommandBuffer commandBuffer
,
6181 VkPipelineStageFlagBits pipelineStage
,
6183 VkDeviceSize dstOffset
,
6186 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
6187 RADV_FROM_HANDLE(radv_buffer
, buffer
, dstBuffer
);
6188 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
6189 uint64_t va
= radv_buffer_get_va(buffer
->bo
) + dstOffset
;
6191 si_emit_cache_flush(cmd_buffer
);
6193 ASSERTED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 12);
6195 if (!(pipelineStage
& ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
)) {
6196 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
6197 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_IMM
) |
6198 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM
) |
6199 COPY_DATA_WR_CONFIRM
);
6200 radeon_emit(cs
, marker
);
6202 radeon_emit(cs
, va
);
6203 radeon_emit(cs
, va
>> 32);
6205 si_cs_emit_write_event_eop(cs
,
6206 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
6207 radv_cmd_buffer_uses_mec(cmd_buffer
),
6208 V_028A90_BOTTOM_OF_PIPE_TS
, 0,
6210 EOP_DATA_SEL_VALUE_32BIT
,
6212 cmd_buffer
->gfx9_eop_bug_va
);
6215 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);