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radv: fix optional pSizes parameter when binding streamout buffers
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 bool src_render_loop,
58 VkImageLayout dst_layout,
59 bool dst_render_loop,
60 uint32_t src_family,
61 uint32_t dst_family,
62 const VkImageSubresourceRange *range,
63 struct radv_sample_locations_state *sample_locs);
64
65 const struct radv_dynamic_state default_dynamic_state = {
66 .viewport = {
67 .count = 0,
68 },
69 .scissor = {
70 .count = 0,
71 },
72 .line_width = 1.0f,
73 .depth_bias = {
74 .bias = 0.0f,
75 .clamp = 0.0f,
76 .slope = 0.0f,
77 },
78 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
79 .depth_bounds = {
80 .min = 0.0f,
81 .max = 1.0f,
82 },
83 .stencil_compare_mask = {
84 .front = ~0u,
85 .back = ~0u,
86 },
87 .stencil_write_mask = {
88 .front = ~0u,
89 .back = ~0u,
90 },
91 .stencil_reference = {
92 .front = 0u,
93 .back = 0u,
94 },
95 .line_stipple = {
96 .factor = 0u,
97 .pattern = 0u,
98 },
99 };
100
101 static void
102 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
103 const struct radv_dynamic_state *src)
104 {
105 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
106 uint32_t copy_mask = src->mask;
107 uint32_t dest_mask = 0;
108
109 /* Make sure to copy the number of viewports/scissors because they can
110 * only be specified at pipeline creation time.
111 */
112 dest->viewport.count = src->viewport.count;
113 dest->scissor.count = src->scissor.count;
114 dest->discard_rectangle.count = src->discard_rectangle.count;
115 dest->sample_location.count = src->sample_location.count;
116
117 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
118 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
119 src->viewport.count * sizeof(VkViewport))) {
120 typed_memcpy(dest->viewport.viewports,
121 src->viewport.viewports,
122 src->viewport.count);
123 dest_mask |= RADV_DYNAMIC_VIEWPORT;
124 }
125 }
126
127 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
128 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
129 src->scissor.count * sizeof(VkRect2D))) {
130 typed_memcpy(dest->scissor.scissors,
131 src->scissor.scissors, src->scissor.count);
132 dest_mask |= RADV_DYNAMIC_SCISSOR;
133 }
134 }
135
136 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
137 if (dest->line_width != src->line_width) {
138 dest->line_width = src->line_width;
139 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
140 }
141 }
142
143 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
144 if (memcmp(&dest->depth_bias, &src->depth_bias,
145 sizeof(src->depth_bias))) {
146 dest->depth_bias = src->depth_bias;
147 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
148 }
149 }
150
151 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
152 if (memcmp(&dest->blend_constants, &src->blend_constants,
153 sizeof(src->blend_constants))) {
154 typed_memcpy(dest->blend_constants,
155 src->blend_constants, 4);
156 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
157 }
158 }
159
160 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
161 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
162 sizeof(src->depth_bounds))) {
163 dest->depth_bounds = src->depth_bounds;
164 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
165 }
166 }
167
168 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
169 if (memcmp(&dest->stencil_compare_mask,
170 &src->stencil_compare_mask,
171 sizeof(src->stencil_compare_mask))) {
172 dest->stencil_compare_mask = src->stencil_compare_mask;
173 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
174 }
175 }
176
177 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
178 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
179 sizeof(src->stencil_write_mask))) {
180 dest->stencil_write_mask = src->stencil_write_mask;
181 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
182 }
183 }
184
185 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
186 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
187 sizeof(src->stencil_reference))) {
188 dest->stencil_reference = src->stencil_reference;
189 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
190 }
191 }
192
193 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
194 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
195 src->discard_rectangle.count * sizeof(VkRect2D))) {
196 typed_memcpy(dest->discard_rectangle.rectangles,
197 src->discard_rectangle.rectangles,
198 src->discard_rectangle.count);
199 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
200 }
201 }
202
203 if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
204 if (dest->sample_location.per_pixel != src->sample_location.per_pixel ||
205 dest->sample_location.grid_size.width != src->sample_location.grid_size.width ||
206 dest->sample_location.grid_size.height != src->sample_location.grid_size.height ||
207 memcmp(&dest->sample_location.locations,
208 &src->sample_location.locations,
209 src->sample_location.count * sizeof(VkSampleLocationEXT))) {
210 dest->sample_location.per_pixel = src->sample_location.per_pixel;
211 dest->sample_location.grid_size = src->sample_location.grid_size;
212 typed_memcpy(dest->sample_location.locations,
213 src->sample_location.locations,
214 src->sample_location.count);
215 dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
216 }
217 }
218
219 if (copy_mask & RADV_DYNAMIC_LINE_STIPPLE) {
220 if (memcmp(&dest->line_stipple, &src->line_stipple,
221 sizeof(src->line_stipple))) {
222 dest->line_stipple = src->line_stipple;
223 dest_mask |= RADV_DYNAMIC_LINE_STIPPLE;
224 }
225 }
226
227 cmd_buffer->state.dirty |= dest_mask;
228 }
229
230 static void
231 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
232 struct radv_pipeline *pipeline)
233 {
234 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
235 struct radv_shader_info *info;
236
237 if (!pipeline->streamout_shader ||
238 cmd_buffer->device->physical_device->use_ngg_streamout)
239 return;
240
241 info = &pipeline->streamout_shader->info;
242 for (int i = 0; i < MAX_SO_BUFFERS; i++)
243 so->stride_in_dw[i] = info->so.strides[i];
244
245 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
246 }
247
248 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
249 {
250 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
251 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
252 }
253
254 enum ring_type radv_queue_family_to_ring(int f) {
255 switch (f) {
256 case RADV_QUEUE_GENERAL:
257 return RING_GFX;
258 case RADV_QUEUE_COMPUTE:
259 return RING_COMPUTE;
260 case RADV_QUEUE_TRANSFER:
261 return RING_DMA;
262 default:
263 unreachable("Unknown queue family");
264 }
265 }
266
267 static VkResult radv_create_cmd_buffer(
268 struct radv_device * device,
269 struct radv_cmd_pool * pool,
270 VkCommandBufferLevel level,
271 VkCommandBuffer* pCommandBuffer)
272 {
273 struct radv_cmd_buffer *cmd_buffer;
274 unsigned ring;
275 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
276 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
277 if (cmd_buffer == NULL)
278 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
279
280 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
281 cmd_buffer->device = device;
282 cmd_buffer->pool = pool;
283 cmd_buffer->level = level;
284
285 if (pool) {
286 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
287 cmd_buffer->queue_family_index = pool->queue_family_index;
288
289 } else {
290 /* Init the pool_link so we can safely call list_del when we destroy
291 * the command buffer
292 */
293 list_inithead(&cmd_buffer->pool_link);
294 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
295 }
296
297 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
298
299 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
300 if (!cmd_buffer->cs) {
301 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
302 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
303 }
304
305 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
306
307 list_inithead(&cmd_buffer->upload.list);
308
309 return VK_SUCCESS;
310 }
311
312 static void
313 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
314 {
315 list_del(&cmd_buffer->pool_link);
316
317 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
318 &cmd_buffer->upload.list, list) {
319 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
320 list_del(&up->list);
321 free(up);
322 }
323
324 if (cmd_buffer->upload.upload_bo)
325 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
326 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
327
328 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
329 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
330
331 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
332 }
333
334 static VkResult
335 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
336 {
337 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
338
339 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
340 &cmd_buffer->upload.list, list) {
341 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
342 list_del(&up->list);
343 free(up);
344 }
345
346 cmd_buffer->push_constant_stages = 0;
347 cmd_buffer->scratch_size_per_wave_needed = 0;
348 cmd_buffer->scratch_waves_wanted = 0;
349 cmd_buffer->compute_scratch_size_per_wave_needed = 0;
350 cmd_buffer->compute_scratch_waves_wanted = 0;
351 cmd_buffer->esgs_ring_size_needed = 0;
352 cmd_buffer->gsvs_ring_size_needed = 0;
353 cmd_buffer->tess_rings_needed = false;
354 cmd_buffer->gds_needed = false;
355 cmd_buffer->gds_oa_needed = false;
356 cmd_buffer->sample_positions_needed = false;
357
358 if (cmd_buffer->upload.upload_bo)
359 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
360 cmd_buffer->upload.upload_bo);
361 cmd_buffer->upload.offset = 0;
362
363 cmd_buffer->record_result = VK_SUCCESS;
364
365 memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
366
367 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
368 cmd_buffer->descriptors[i].dirty = 0;
369 cmd_buffer->descriptors[i].valid = 0;
370 cmd_buffer->descriptors[i].push_dirty = false;
371 }
372
373 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
374 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
375 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
376 unsigned fence_offset, eop_bug_offset;
377 void *fence_ptr;
378
379 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
380 &fence_ptr);
381
382 cmd_buffer->gfx9_fence_va =
383 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
384 cmd_buffer->gfx9_fence_va += fence_offset;
385
386 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
387 /* Allocate a buffer for the EOP bug on GFX9. */
388 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
389 &eop_bug_offset, &fence_ptr);
390 cmd_buffer->gfx9_eop_bug_va =
391 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
392 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
393 }
394 }
395
396 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
397
398 return cmd_buffer->record_result;
399 }
400
401 static bool
402 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
403 uint64_t min_needed)
404 {
405 uint64_t new_size;
406 struct radeon_winsys_bo *bo;
407 struct radv_cmd_buffer_upload *upload;
408 struct radv_device *device = cmd_buffer->device;
409
410 new_size = MAX2(min_needed, 16 * 1024);
411 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
412
413 bo = device->ws->buffer_create(device->ws,
414 new_size, 4096,
415 RADEON_DOMAIN_GTT,
416 RADEON_FLAG_CPU_ACCESS|
417 RADEON_FLAG_NO_INTERPROCESS_SHARING |
418 RADEON_FLAG_32BIT,
419 RADV_BO_PRIORITY_UPLOAD_BUFFER);
420
421 if (!bo) {
422 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
423 return false;
424 }
425
426 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
427 if (cmd_buffer->upload.upload_bo) {
428 upload = malloc(sizeof(*upload));
429
430 if (!upload) {
431 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
432 device->ws->buffer_destroy(bo);
433 return false;
434 }
435
436 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
437 list_add(&upload->list, &cmd_buffer->upload.list);
438 }
439
440 cmd_buffer->upload.upload_bo = bo;
441 cmd_buffer->upload.size = new_size;
442 cmd_buffer->upload.offset = 0;
443 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
444
445 if (!cmd_buffer->upload.map) {
446 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
447 return false;
448 }
449
450 return true;
451 }
452
453 bool
454 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
455 unsigned size,
456 unsigned alignment,
457 unsigned *out_offset,
458 void **ptr)
459 {
460 assert(util_is_power_of_two_nonzero(alignment));
461
462 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
463 if (offset + size > cmd_buffer->upload.size) {
464 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
465 return false;
466 offset = 0;
467 }
468
469 *out_offset = offset;
470 *ptr = cmd_buffer->upload.map + offset;
471
472 cmd_buffer->upload.offset = offset + size;
473 return true;
474 }
475
476 bool
477 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
478 unsigned size, unsigned alignment,
479 const void *data, unsigned *out_offset)
480 {
481 uint8_t *ptr;
482
483 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
484 out_offset, (void **)&ptr))
485 return false;
486
487 if (ptr)
488 memcpy(ptr, data, size);
489
490 return true;
491 }
492
493 static void
494 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
495 unsigned count, const uint32_t *data)
496 {
497 struct radeon_cmdbuf *cs = cmd_buffer->cs;
498
499 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
500
501 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
502 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
503 S_370_WR_CONFIRM(1) |
504 S_370_ENGINE_SEL(V_370_ME));
505 radeon_emit(cs, va);
506 radeon_emit(cs, va >> 32);
507 radeon_emit_array(cs, data, count);
508 }
509
510 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
511 {
512 struct radv_device *device = cmd_buffer->device;
513 struct radeon_cmdbuf *cs = cmd_buffer->cs;
514 uint64_t va;
515
516 va = radv_buffer_get_va(device->trace_bo);
517 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
518 va += 4;
519
520 ++cmd_buffer->state.trace_id;
521 radv_emit_write_data_packet(cmd_buffer, va, 1,
522 &cmd_buffer->state.trace_id);
523
524 radeon_check_space(cmd_buffer->device->ws, cs, 2);
525
526 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
527 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
528 }
529
530 static void
531 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
532 enum radv_cmd_flush_bits flags)
533 {
534 if (unlikely(cmd_buffer->device->thread_trace_bo)) {
535 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
536 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_THREAD_TRACE_MARKER) | EVENT_INDEX(0));
537 }
538
539 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
540 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
541 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
542
543 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
544
545 /* Force wait for graphics or compute engines to be idle. */
546 si_cs_emit_cache_flush(cmd_buffer->cs,
547 cmd_buffer->device->physical_device->rad_info.chip_class,
548 &cmd_buffer->gfx9_fence_idx,
549 cmd_buffer->gfx9_fence_va,
550 radv_cmd_buffer_uses_mec(cmd_buffer),
551 flags, cmd_buffer->gfx9_eop_bug_va);
552 }
553
554 if (unlikely(cmd_buffer->device->trace_bo))
555 radv_cmd_buffer_trace_emit(cmd_buffer);
556 }
557
558 static void
559 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
560 struct radv_pipeline *pipeline, enum ring_type ring)
561 {
562 struct radv_device *device = cmd_buffer->device;
563 uint32_t data[2];
564 uint64_t va;
565
566 va = radv_buffer_get_va(device->trace_bo);
567
568 switch (ring) {
569 case RING_GFX:
570 va += 8;
571 break;
572 case RING_COMPUTE:
573 va += 16;
574 break;
575 default:
576 assert(!"invalid ring type");
577 }
578
579 uint64_t pipeline_address = (uintptr_t)pipeline;
580 data[0] = pipeline_address;
581 data[1] = pipeline_address >> 32;
582
583 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
584 }
585
586 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
587 VkPipelineBindPoint bind_point,
588 struct radv_descriptor_set *set,
589 unsigned idx)
590 {
591 struct radv_descriptor_state *descriptors_state =
592 radv_get_descriptors_state(cmd_buffer, bind_point);
593
594 descriptors_state->sets[idx] = set;
595
596 descriptors_state->valid |= (1u << idx); /* active descriptors */
597 descriptors_state->dirty |= (1u << idx);
598 }
599
600 static void
601 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
602 VkPipelineBindPoint bind_point)
603 {
604 struct radv_descriptor_state *descriptors_state =
605 radv_get_descriptors_state(cmd_buffer, bind_point);
606 struct radv_device *device = cmd_buffer->device;
607 uint32_t data[MAX_SETS * 2] = {};
608 uint64_t va;
609 unsigned i;
610 va = radv_buffer_get_va(device->trace_bo) + 24;
611
612 for_each_bit(i, descriptors_state->valid) {
613 struct radv_descriptor_set *set = descriptors_state->sets[i];
614 data[i * 2] = (uint64_t)(uintptr_t)set;
615 data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
616 }
617
618 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
619 }
620
621 struct radv_userdata_info *
622 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
623 gl_shader_stage stage,
624 int idx)
625 {
626 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
627 return &shader->info.user_sgprs_locs.shader_data[idx];
628 }
629
630 static void
631 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
632 struct radv_pipeline *pipeline,
633 gl_shader_stage stage,
634 int idx, uint64_t va)
635 {
636 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
637 uint32_t base_reg = pipeline->user_data_0[stage];
638 if (loc->sgpr_idx == -1)
639 return;
640
641 assert(loc->num_sgprs == 1);
642
643 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
644 base_reg + loc->sgpr_idx * 4, va, false);
645 }
646
647 static void
648 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
649 struct radv_pipeline *pipeline,
650 struct radv_descriptor_state *descriptors_state,
651 gl_shader_stage stage)
652 {
653 struct radv_device *device = cmd_buffer->device;
654 struct radeon_cmdbuf *cs = cmd_buffer->cs;
655 uint32_t sh_base = pipeline->user_data_0[stage];
656 struct radv_userdata_locations *locs =
657 &pipeline->shaders[stage]->info.user_sgprs_locs;
658 unsigned mask = locs->descriptor_sets_enabled;
659
660 mask &= descriptors_state->dirty & descriptors_state->valid;
661
662 while (mask) {
663 int start, count;
664
665 u_bit_scan_consecutive_range(&mask, &start, &count);
666
667 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
668 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
669
670 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
671 for (int i = 0; i < count; i++) {
672 struct radv_descriptor_set *set =
673 descriptors_state->sets[start + i];
674
675 radv_emit_shader_pointer_body(device, cs, set->va, true);
676 }
677 }
678 }
679
680 /**
681 * Convert the user sample locations to hardware sample locations (the values
682 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
683 */
684 static void
685 radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
686 uint32_t x, uint32_t y, VkOffset2D *sample_locs)
687 {
688 uint32_t x_offset = x % state->grid_size.width;
689 uint32_t y_offset = y % state->grid_size.height;
690 uint32_t num_samples = (uint32_t)state->per_pixel;
691 VkSampleLocationEXT *user_locs;
692 uint32_t pixel_offset;
693
694 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
695
696 assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
697 user_locs = &state->locations[pixel_offset];
698
699 for (uint32_t i = 0; i < num_samples; i++) {
700 float shifted_pos_x = user_locs[i].x - 0.5;
701 float shifted_pos_y = user_locs[i].y - 0.5;
702
703 int32_t scaled_pos_x = floor(shifted_pos_x * 16);
704 int32_t scaled_pos_y = floor(shifted_pos_y * 16);
705
706 sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
707 sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
708 }
709 }
710
711 /**
712 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
713 * locations.
714 */
715 static void
716 radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
717 uint32_t *sample_locs_pixel)
718 {
719 for (uint32_t i = 0; i < num_samples; i++) {
720 uint32_t sample_reg_idx = i / 4;
721 uint32_t sample_loc_idx = i % 4;
722 int32_t pos_x = sample_locs[i].x;
723 int32_t pos_y = sample_locs[i].y;
724
725 uint32_t shift_x = 8 * sample_loc_idx;
726 uint32_t shift_y = shift_x + 4;
727
728 sample_locs_pixel[sample_reg_idx] |= (pos_x & 0xf) << shift_x;
729 sample_locs_pixel[sample_reg_idx] |= (pos_y & 0xf) << shift_y;
730 }
731 }
732
733 /**
734 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
735 * sample locations.
736 */
737 static uint64_t
738 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer,
739 VkOffset2D *sample_locs,
740 uint32_t num_samples)
741 {
742 uint32_t centroid_priorities[num_samples];
743 uint32_t sample_mask = num_samples - 1;
744 uint32_t distances[num_samples];
745 uint64_t centroid_priority = 0;
746
747 /* Compute the distances from center for each sample. */
748 for (int i = 0; i < num_samples; i++) {
749 distances[i] = (sample_locs[i].x * sample_locs[i].x) +
750 (sample_locs[i].y * sample_locs[i].y);
751 }
752
753 /* Compute the centroid priorities by looking at the distances array. */
754 for (int i = 0; i < num_samples; i++) {
755 uint32_t min_idx = 0;
756
757 for (int j = 1; j < num_samples; j++) {
758 if (distances[j] < distances[min_idx])
759 min_idx = j;
760 }
761
762 centroid_priorities[i] = min_idx;
763 distances[min_idx] = 0xffffffff;
764 }
765
766 /* Compute the final centroid priority. */
767 for (int i = 0; i < 8; i++) {
768 centroid_priority |=
769 centroid_priorities[i & sample_mask] << (i * 4);
770 }
771
772 return centroid_priority << 32 | centroid_priority;
773 }
774
775 /**
776 * Emit the sample locations that are specified with VK_EXT_sample_locations.
777 */
778 static void
779 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
780 {
781 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
782 struct radv_multisample_state *ms = &pipeline->graphics.ms;
783 struct radv_sample_locations_state *sample_location =
784 &cmd_buffer->state.dynamic.sample_location;
785 uint32_t num_samples = (uint32_t)sample_location->per_pixel;
786 struct radeon_cmdbuf *cs = cmd_buffer->cs;
787 uint32_t sample_locs_pixel[4][2] = {};
788 VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
789 uint32_t max_sample_dist = 0;
790 uint64_t centroid_priority;
791
792 if (!cmd_buffer->state.dynamic.sample_location.count)
793 return;
794
795 /* Convert the user sample locations to hardware sample locations. */
796 radv_convert_user_sample_locs(sample_location, 0, 0, sample_locs[0]);
797 radv_convert_user_sample_locs(sample_location, 1, 0, sample_locs[1]);
798 radv_convert_user_sample_locs(sample_location, 0, 1, sample_locs[2]);
799 radv_convert_user_sample_locs(sample_location, 1, 1, sample_locs[3]);
800
801 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
802 for (uint32_t i = 0; i < 4; i++) {
803 radv_compute_sample_locs_pixel(num_samples, sample_locs[i],
804 sample_locs_pixel[i]);
805 }
806
807 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
808 centroid_priority =
809 radv_compute_centroid_priority(cmd_buffer, sample_locs[0],
810 num_samples);
811
812 /* Compute the maximum sample distance from the specified locations. */
813 for (uint32_t i = 0; i < num_samples; i++) {
814 VkOffset2D offset = sample_locs[0][i];
815 max_sample_dist = MAX2(max_sample_dist,
816 MAX2(abs(offset.x), abs(offset.y)));
817 }
818
819 /* Emit the specified user sample locations. */
820 switch (num_samples) {
821 case 2:
822 case 4:
823 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
824 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
825 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
826 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
827 break;
828 case 8:
829 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
830 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
831 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
832 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
833 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs_pixel[0][1]);
834 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs_pixel[1][1]);
835 radeon_set_context_reg(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs_pixel[2][1]);
836 radeon_set_context_reg(cs, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs_pixel[3][1]);
837 break;
838 default:
839 unreachable("invalid number of samples");
840 }
841
842 /* Emit the maximum sample distance and the centroid priority. */
843 uint32_t pa_sc_aa_config = ms->pa_sc_aa_config;
844
845 pa_sc_aa_config &= C_028BE0_MAX_SAMPLE_DIST;
846 pa_sc_aa_config |= S_028BE0_MAX_SAMPLE_DIST(max_sample_dist);
847
848 radeon_set_context_reg_seq(cs, R_028BE0_PA_SC_AA_CONFIG, 1);
849 radeon_emit(cs, pa_sc_aa_config);
850
851 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
852 radeon_emit(cs, centroid_priority);
853 radeon_emit(cs, centroid_priority >> 32);
854
855 /* GFX9: Flush DFSM when the AA mode changes. */
856 if (cmd_buffer->device->dfsm_allowed) {
857 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
858 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
859 }
860
861 cmd_buffer->state.context_roll_without_scissor_emitted = true;
862 }
863
864 static void
865 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
866 struct radv_pipeline *pipeline,
867 gl_shader_stage stage,
868 int idx, int count, uint32_t *values)
869 {
870 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
871 uint32_t base_reg = pipeline->user_data_0[stage];
872 if (loc->sgpr_idx == -1)
873 return;
874
875 assert(loc->num_sgprs == count);
876
877 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
878 radeon_emit_array(cmd_buffer->cs, values, count);
879 }
880
881 static void
882 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
883 struct radv_pipeline *pipeline)
884 {
885 int num_samples = pipeline->graphics.ms.num_samples;
886 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
887
888 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.needs_sample_positions)
889 cmd_buffer->sample_positions_needed = true;
890
891 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
892 return;
893
894 radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
895
896 cmd_buffer->state.context_roll_without_scissor_emitted = true;
897 }
898
899 static void
900 radv_update_binning_state(struct radv_cmd_buffer *cmd_buffer,
901 struct radv_pipeline *pipeline)
902 {
903 const struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
904
905
906 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
907 return;
908
909 if (old_pipeline &&
910 old_pipeline->graphics.binning.pa_sc_binner_cntl_0 == pipeline->graphics.binning.pa_sc_binner_cntl_0 &&
911 old_pipeline->graphics.binning.db_dfsm_control == pipeline->graphics.binning.db_dfsm_control)
912 return;
913
914 bool binning_flush = false;
915 if (cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA12 ||
916 cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA20 ||
917 cmd_buffer->device->physical_device->rad_info.family == CHIP_RAVEN2 ||
918 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
919 binning_flush = !old_pipeline ||
920 G_028C44_BINNING_MODE(old_pipeline->graphics.binning.pa_sc_binner_cntl_0) !=
921 G_028C44_BINNING_MODE(pipeline->graphics.binning.pa_sc_binner_cntl_0);
922 }
923
924 radeon_set_context_reg(cmd_buffer->cs, R_028C44_PA_SC_BINNER_CNTL_0,
925 pipeline->graphics.binning.pa_sc_binner_cntl_0 |
926 S_028C44_FLUSH_ON_BINNING_TRANSITION(!!binning_flush));
927
928 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
929 radeon_set_context_reg(cmd_buffer->cs, R_028038_DB_DFSM_CONTROL,
930 pipeline->graphics.binning.db_dfsm_control);
931 } else {
932 radeon_set_context_reg(cmd_buffer->cs, R_028060_DB_DFSM_CONTROL,
933 pipeline->graphics.binning.db_dfsm_control);
934 }
935
936 cmd_buffer->state.context_roll_without_scissor_emitted = true;
937 }
938
939
940 static void
941 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
942 struct radv_shader_variant *shader)
943 {
944 uint64_t va;
945
946 if (!shader)
947 return;
948
949 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
950
951 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
952 }
953
954 static void
955 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
956 struct radv_pipeline *pipeline,
957 bool vertex_stage_only)
958 {
959 struct radv_cmd_state *state = &cmd_buffer->state;
960 uint32_t mask = state->prefetch_L2_mask;
961
962 if (vertex_stage_only) {
963 /* Fast prefetch path for starting draws as soon as possible.
964 */
965 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
966 RADV_PREFETCH_VBO_DESCRIPTORS);
967 }
968
969 if (mask & RADV_PREFETCH_VS)
970 radv_emit_shader_prefetch(cmd_buffer,
971 pipeline->shaders[MESA_SHADER_VERTEX]);
972
973 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
974 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
975
976 if (mask & RADV_PREFETCH_TCS)
977 radv_emit_shader_prefetch(cmd_buffer,
978 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
979
980 if (mask & RADV_PREFETCH_TES)
981 radv_emit_shader_prefetch(cmd_buffer,
982 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
983
984 if (mask & RADV_PREFETCH_GS) {
985 radv_emit_shader_prefetch(cmd_buffer,
986 pipeline->shaders[MESA_SHADER_GEOMETRY]);
987 if (radv_pipeline_has_gs_copy_shader(pipeline))
988 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
989 }
990
991 if (mask & RADV_PREFETCH_PS)
992 radv_emit_shader_prefetch(cmd_buffer,
993 pipeline->shaders[MESA_SHADER_FRAGMENT]);
994
995 state->prefetch_L2_mask &= ~mask;
996 }
997
998 static void
999 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
1000 {
1001 if (!cmd_buffer->device->physical_device->rad_info.rbplus_allowed)
1002 return;
1003
1004 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1005 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1006
1007 unsigned sx_ps_downconvert = 0;
1008 unsigned sx_blend_opt_epsilon = 0;
1009 unsigned sx_blend_opt_control = 0;
1010
1011 if (!cmd_buffer->state.attachments || !subpass)
1012 return;
1013
1014 for (unsigned i = 0; i < subpass->color_count; ++i) {
1015 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1016 /* We don't set the DISABLE bits, because the HW can't have holes,
1017 * so the SPI color format is set to 32-bit 1-component. */
1018 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1019 continue;
1020 }
1021
1022 int idx = subpass->color_attachments[i].attachment;
1023 struct radv_color_buffer_info *cb = &cmd_buffer->state.attachments[idx].cb;
1024
1025 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
1026 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
1027 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
1028 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
1029
1030 bool has_alpha, has_rgb;
1031
1032 /* Set if RGB and A are present. */
1033 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
1034
1035 if (format == V_028C70_COLOR_8 ||
1036 format == V_028C70_COLOR_16 ||
1037 format == V_028C70_COLOR_32)
1038 has_rgb = !has_alpha;
1039 else
1040 has_rgb = true;
1041
1042 /* Check the colormask and export format. */
1043 if (!(colormask & 0x7))
1044 has_rgb = false;
1045 if (!(colormask & 0x8))
1046 has_alpha = false;
1047
1048 if (spi_format == V_028714_SPI_SHADER_ZERO) {
1049 has_rgb = false;
1050 has_alpha = false;
1051 }
1052
1053 /* Disable value checking for disabled channels. */
1054 if (!has_rgb)
1055 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1056 if (!has_alpha)
1057 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1058
1059 /* Enable down-conversion for 32bpp and smaller formats. */
1060 switch (format) {
1061 case V_028C70_COLOR_8:
1062 case V_028C70_COLOR_8_8:
1063 case V_028C70_COLOR_8_8_8_8:
1064 /* For 1 and 2-channel formats, use the superset thereof. */
1065 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
1066 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1067 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1068 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
1069 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
1070 }
1071 break;
1072
1073 case V_028C70_COLOR_5_6_5:
1074 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1075 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
1076 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
1077 }
1078 break;
1079
1080 case V_028C70_COLOR_1_5_5_5:
1081 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1082 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
1083 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
1084 }
1085 break;
1086
1087 case V_028C70_COLOR_4_4_4_4:
1088 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1089 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
1090 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
1091 }
1092 break;
1093
1094 case V_028C70_COLOR_32:
1095 if (swap == V_028C70_SWAP_STD &&
1096 spi_format == V_028714_SPI_SHADER_32_R)
1097 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1098 else if (swap == V_028C70_SWAP_ALT_REV &&
1099 spi_format == V_028714_SPI_SHADER_32_AR)
1100 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
1101 break;
1102
1103 case V_028C70_COLOR_16:
1104 case V_028C70_COLOR_16_16:
1105 /* For 1-channel formats, use the superset thereof. */
1106 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
1107 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
1108 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1109 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1110 if (swap == V_028C70_SWAP_STD ||
1111 swap == V_028C70_SWAP_STD_REV)
1112 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
1113 else
1114 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
1115 }
1116 break;
1117
1118 case V_028C70_COLOR_10_11_11:
1119 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1120 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
1121 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
1122 }
1123 break;
1124
1125 case V_028C70_COLOR_2_10_10_10:
1126 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1127 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
1128 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
1129 }
1130 break;
1131 }
1132 }
1133
1134 /* Do not set the DISABLE bits for the unused attachments, as that
1135 * breaks dual source blending in SkQP and does not seem to improve
1136 * performance. */
1137
1138 if (sx_ps_downconvert == cmd_buffer->state.last_sx_ps_downconvert &&
1139 sx_blend_opt_epsilon == cmd_buffer->state.last_sx_blend_opt_epsilon &&
1140 sx_blend_opt_control == cmd_buffer->state.last_sx_blend_opt_control)
1141 return;
1142
1143 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
1144 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
1145 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
1146 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
1147
1148 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1149
1150 cmd_buffer->state.last_sx_ps_downconvert = sx_ps_downconvert;
1151 cmd_buffer->state.last_sx_blend_opt_epsilon = sx_blend_opt_epsilon;
1152 cmd_buffer->state.last_sx_blend_opt_control = sx_blend_opt_control;
1153 }
1154
1155 static void
1156 radv_emit_batch_break_on_new_ps(struct radv_cmd_buffer *cmd_buffer)
1157 {
1158 if (!cmd_buffer->device->pbb_allowed)
1159 return;
1160
1161 struct radv_binning_settings settings =
1162 radv_get_binning_settings(cmd_buffer->device->physical_device);
1163 bool break_for_new_ps =
1164 (!cmd_buffer->state.emitted_pipeline ||
1165 cmd_buffer->state.emitted_pipeline->shaders[MESA_SHADER_FRAGMENT] !=
1166 cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT]) &&
1167 (settings.context_states_per_bin > 1 ||
1168 settings.persistent_states_per_bin > 1);
1169 bool break_for_new_cb_target_mask =
1170 (!cmd_buffer->state.emitted_pipeline ||
1171 cmd_buffer->state.emitted_pipeline->graphics.cb_target_mask !=
1172 cmd_buffer->state.pipeline->graphics.cb_target_mask) &&
1173 settings.context_states_per_bin > 1;
1174
1175 if (!break_for_new_ps && !break_for_new_cb_target_mask)
1176 return;
1177
1178 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1179 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1180 }
1181
1182 static void
1183 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1184 {
1185 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1186
1187 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1188 return;
1189
1190 radv_update_multisample_state(cmd_buffer, pipeline);
1191 radv_update_binning_state(cmd_buffer, pipeline);
1192
1193 cmd_buffer->scratch_size_per_wave_needed = MAX2(cmd_buffer->scratch_size_per_wave_needed,
1194 pipeline->scratch_bytes_per_wave);
1195 cmd_buffer->scratch_waves_wanted = MAX2(cmd_buffer->scratch_waves_wanted,
1196 pipeline->max_waves);
1197
1198 if (!cmd_buffer->state.emitted_pipeline ||
1199 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1200 pipeline->graphics.can_use_guardband)
1201 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1202
1203 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
1204
1205 if (!cmd_buffer->state.emitted_pipeline ||
1206 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
1207 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
1208 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
1209 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
1210 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
1211 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1212 }
1213
1214 radv_emit_batch_break_on_new_ps(cmd_buffer);
1215
1216 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
1217 if (!pipeline->shaders[i])
1218 continue;
1219
1220 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1221 pipeline->shaders[i]->bo);
1222 }
1223
1224 if (radv_pipeline_has_gs_copy_shader(pipeline))
1225 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1226 pipeline->gs_copy_shader->bo);
1227
1228 if (unlikely(cmd_buffer->device->trace_bo))
1229 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1230
1231 cmd_buffer->state.emitted_pipeline = pipeline;
1232
1233 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1234 }
1235
1236 static void
1237 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1238 {
1239 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1240 cmd_buffer->state.dynamic.viewport.viewports);
1241 }
1242
1243 static void
1244 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1245 {
1246 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1247
1248 si_write_scissors(cmd_buffer->cs, 0, count,
1249 cmd_buffer->state.dynamic.scissor.scissors,
1250 cmd_buffer->state.dynamic.viewport.viewports,
1251 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1252
1253 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1254 }
1255
1256 static void
1257 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1258 {
1259 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1260 return;
1261
1262 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1263 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1264 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1265 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1266 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1267 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1268 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1269 }
1270 }
1271
1272 static void
1273 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1274 {
1275 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1276
1277 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1278 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1279 }
1280
1281 static void
1282 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1283 {
1284 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1285
1286 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1287 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1288 }
1289
1290 static void
1291 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1292 {
1293 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1294
1295 radeon_set_context_reg_seq(cmd_buffer->cs,
1296 R_028430_DB_STENCILREFMASK, 2);
1297 radeon_emit(cmd_buffer->cs,
1298 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1299 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1300 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1301 S_028430_STENCILOPVAL(1));
1302 radeon_emit(cmd_buffer->cs,
1303 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1304 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1305 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1306 S_028434_STENCILOPVAL_BF(1));
1307 }
1308
1309 static void
1310 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1311 {
1312 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1313
1314 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1315 fui(d->depth_bounds.min));
1316 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1317 fui(d->depth_bounds.max));
1318 }
1319
1320 static void
1321 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1322 {
1323 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1324 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1325 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1326
1327
1328 radeon_set_context_reg_seq(cmd_buffer->cs,
1329 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1330 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1331 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1332 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1333 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1334 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1335 }
1336
1337 static void
1338 radv_emit_line_stipple(struct radv_cmd_buffer *cmd_buffer)
1339 {
1340 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1341 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1342 uint32_t auto_reset_cntl = 1;
1343
1344 if (pipeline->graphics.topology == VK_PRIMITIVE_TOPOLOGY_LINE_STRIP)
1345 auto_reset_cntl = 2;
1346
1347 radeon_set_context_reg(cmd_buffer->cs, R_028A0C_PA_SC_LINE_STIPPLE,
1348 S_028A0C_LINE_PATTERN(d->line_stipple.pattern) |
1349 S_028A0C_REPEAT_COUNT(d->line_stipple.factor - 1) |
1350 S_028A0C_AUTO_RESET_CNTL(auto_reset_cntl));
1351 }
1352
1353 static void
1354 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1355 int index,
1356 struct radv_color_buffer_info *cb,
1357 struct radv_image_view *iview,
1358 VkImageLayout layout,
1359 bool in_render_loop)
1360 {
1361 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
1362 uint32_t cb_color_info = cb->cb_color_info;
1363 struct radv_image *image = iview->image;
1364
1365 if (!radv_layout_dcc_compressed(cmd_buffer->device, image, layout, in_render_loop,
1366 radv_image_queue_family_mask(image,
1367 cmd_buffer->queue_family_index,
1368 cmd_buffer->queue_family_index))) {
1369 cb_color_info &= C_028C70_DCC_ENABLE;
1370 }
1371
1372 if (radv_image_is_tc_compat_cmask(image) &&
1373 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1374 radv_is_dcc_decompress_pipeline(cmd_buffer))) {
1375 /* If this bit is set, the FMASK decompression operation
1376 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1377 */
1378 cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
1379 }
1380
1381 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1382 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1383 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1384 radeon_emit(cmd_buffer->cs, 0);
1385 radeon_emit(cmd_buffer->cs, 0);
1386 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1387 radeon_emit(cmd_buffer->cs, cb_color_info);
1388 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1389 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1390 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1391 radeon_emit(cmd_buffer->cs, 0);
1392 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1393 radeon_emit(cmd_buffer->cs, 0);
1394
1395 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 1);
1396 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1397
1398 radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4,
1399 cb->cb_color_base >> 32);
1400 radeon_set_context_reg(cmd_buffer->cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + index * 4,
1401 cb->cb_color_cmask >> 32);
1402 radeon_set_context_reg(cmd_buffer->cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + index * 4,
1403 cb->cb_color_fmask >> 32);
1404 radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4,
1405 cb->cb_dcc_base >> 32);
1406 radeon_set_context_reg(cmd_buffer->cs, R_028EC0_CB_COLOR0_ATTRIB2 + index * 4,
1407 cb->cb_color_attrib2);
1408 radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4,
1409 cb->cb_color_attrib3);
1410 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1411 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1412 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1413 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1414 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1415 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1416 radeon_emit(cmd_buffer->cs, cb_color_info);
1417 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1418 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1419 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1420 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1421 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1422 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1423
1424 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1425 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1426 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1427
1428 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1429 cb->cb_mrt_epitch);
1430 } else {
1431 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1432 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1433 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1434 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1435 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1436 radeon_emit(cmd_buffer->cs, cb_color_info);
1437 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1438 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1439 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1440 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1441 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1442 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1443
1444 if (is_vi) { /* DCC BASE */
1445 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1446 }
1447 }
1448
1449 if (radv_dcc_enabled(image, iview->base_mip)) {
1450 /* Drawing with DCC enabled also compresses colorbuffers. */
1451 VkImageSubresourceRange range = {
1452 .aspectMask = iview->aspect_mask,
1453 .baseMipLevel = iview->base_mip,
1454 .levelCount = iview->level_count,
1455 .baseArrayLayer = iview->base_layer,
1456 .layerCount = iview->layer_count,
1457 };
1458
1459 radv_update_dcc_metadata(cmd_buffer, image, &range, true);
1460 }
1461 }
1462
1463 static void
1464 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1465 struct radv_ds_buffer_info *ds,
1466 const struct radv_image_view *iview,
1467 VkImageLayout layout,
1468 bool in_render_loop, bool requires_cond_exec)
1469 {
1470 const struct radv_image *image = iview->image;
1471 uint32_t db_z_info = ds->db_z_info;
1472 uint32_t db_z_info_reg;
1473
1474 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug ||
1475 !radv_image_is_tc_compat_htile(image))
1476 return;
1477
1478 if (!radv_layout_has_htile(image, layout, in_render_loop,
1479 radv_image_queue_family_mask(image,
1480 cmd_buffer->queue_family_index,
1481 cmd_buffer->queue_family_index))) {
1482 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1483 }
1484
1485 db_z_info &= C_028040_ZRANGE_PRECISION;
1486
1487 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1488 db_z_info_reg = R_028038_DB_Z_INFO;
1489 } else {
1490 db_z_info_reg = R_028040_DB_Z_INFO;
1491 }
1492
1493 /* When we don't know the last fast clear value we need to emit a
1494 * conditional packet that will eventually skip the following
1495 * SET_CONTEXT_REG packet.
1496 */
1497 if (requires_cond_exec) {
1498 uint64_t va = radv_get_tc_compat_zrange_va(image, iview->base_mip);
1499
1500 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1501 radeon_emit(cmd_buffer->cs, va);
1502 radeon_emit(cmd_buffer->cs, va >> 32);
1503 radeon_emit(cmd_buffer->cs, 0);
1504 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1505 }
1506
1507 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1508 }
1509
1510 static void
1511 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1512 struct radv_ds_buffer_info *ds,
1513 struct radv_image_view *iview,
1514 VkImageLayout layout,
1515 bool in_render_loop)
1516 {
1517 const struct radv_image *image = iview->image;
1518 uint32_t db_z_info = ds->db_z_info;
1519 uint32_t db_stencil_info = ds->db_stencil_info;
1520
1521 if (!radv_layout_has_htile(image, layout, in_render_loop,
1522 radv_image_queue_family_mask(image,
1523 cmd_buffer->queue_family_index,
1524 cmd_buffer->queue_family_index))) {
1525 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1526 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1527 }
1528
1529 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1530 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1531
1532 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1533 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1534 radeon_set_context_reg(cmd_buffer->cs, R_02801C_DB_DEPTH_SIZE_XY, ds->db_depth_size);
1535
1536 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 7);
1537 radeon_emit(cmd_buffer->cs, S_02803C_RESOURCE_LEVEL(1));
1538 radeon_emit(cmd_buffer->cs, db_z_info);
1539 radeon_emit(cmd_buffer->cs, db_stencil_info);
1540 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1541 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1542 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1543 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1544
1545 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_READ_BASE_HI, 5);
1546 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1547 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1548 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1549 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1550 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1551 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1552 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1553 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1554 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1555 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1556
1557 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1558 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1559 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1560 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1561 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1562 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1563 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1564 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1565 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1566 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1567 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1568
1569 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1570 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1571 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1572 } else {
1573 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1574
1575 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1576 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1577 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1578 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1579 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1580 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1581 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1582 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1583 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1584 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1585
1586 }
1587
1588 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1589 radv_update_zrange_precision(cmd_buffer, ds, iview, layout,
1590 in_render_loop, true);
1591
1592 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1593 ds->pa_su_poly_offset_db_fmt_cntl);
1594 }
1595
1596 /**
1597 * Update the fast clear depth/stencil values if the image is bound as a
1598 * depth/stencil buffer.
1599 */
1600 static void
1601 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1602 const struct radv_image_view *iview,
1603 VkClearDepthStencilValue ds_clear_value,
1604 VkImageAspectFlags aspects)
1605 {
1606 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1607 const struct radv_image *image = iview->image;
1608 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1609 uint32_t att_idx;
1610
1611 if (!cmd_buffer->state.attachments || !subpass)
1612 return;
1613
1614 if (!subpass->depth_stencil_attachment)
1615 return;
1616
1617 att_idx = subpass->depth_stencil_attachment->attachment;
1618 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1619 return;
1620
1621 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1622 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1623 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1624 radeon_emit(cs, ds_clear_value.stencil);
1625 radeon_emit(cs, fui(ds_clear_value.depth));
1626 } else if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1627 radeon_set_context_reg_seq(cs, R_02802C_DB_DEPTH_CLEAR, 1);
1628 radeon_emit(cs, fui(ds_clear_value.depth));
1629 } else {
1630 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1631 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 1);
1632 radeon_emit(cs, ds_clear_value.stencil);
1633 }
1634
1635 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1636 * only needed when clearing Z to 0.0.
1637 */
1638 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1639 ds_clear_value.depth == 0.0) {
1640 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1641 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
1642
1643 radv_update_zrange_precision(cmd_buffer, &cmd_buffer->state.attachments[att_idx].ds,
1644 iview, layout, in_render_loop, false);
1645 }
1646
1647 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1648 }
1649
1650 /**
1651 * Set the clear depth/stencil values to the image's metadata.
1652 */
1653 static void
1654 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1655 struct radv_image *image,
1656 const VkImageSubresourceRange *range,
1657 VkClearDepthStencilValue ds_clear_value,
1658 VkImageAspectFlags aspects)
1659 {
1660 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1661 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel);
1662 uint32_t level_count = radv_get_levelCount(image, range);
1663
1664 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1665 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1666 /* Use the fastest way when both aspects are used. */
1667 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + 2 * level_count, cmd_buffer->state.predicating));
1668 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1669 S_370_WR_CONFIRM(1) |
1670 S_370_ENGINE_SEL(V_370_PFP));
1671 radeon_emit(cs, va);
1672 radeon_emit(cs, va >> 32);
1673
1674 for (uint32_t l = 0; l < level_count; l++) {
1675 radeon_emit(cs, ds_clear_value.stencil);
1676 radeon_emit(cs, fui(ds_clear_value.depth));
1677 }
1678 } else {
1679 /* Otherwise we need one WRITE_DATA packet per level. */
1680 for (uint32_t l = 0; l < level_count; l++) {
1681 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel + l);
1682 unsigned value;
1683
1684 if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1685 value = fui(ds_clear_value.depth);
1686 va += 4;
1687 } else {
1688 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1689 value = ds_clear_value.stencil;
1690 }
1691
1692 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1693 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1694 S_370_WR_CONFIRM(1) |
1695 S_370_ENGINE_SEL(V_370_PFP));
1696 radeon_emit(cs, va);
1697 radeon_emit(cs, va >> 32);
1698 radeon_emit(cs, value);
1699 }
1700 }
1701 }
1702
1703 /**
1704 * Update the TC-compat metadata value for this image.
1705 */
1706 static void
1707 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1708 struct radv_image *image,
1709 const VkImageSubresourceRange *range,
1710 uint32_t value)
1711 {
1712 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1713
1714 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug)
1715 return;
1716
1717 uint64_t va = radv_get_tc_compat_zrange_va(image, range->baseMipLevel);
1718 uint32_t level_count = radv_get_levelCount(image, range);
1719
1720 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + level_count, cmd_buffer->state.predicating));
1721 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1722 S_370_WR_CONFIRM(1) |
1723 S_370_ENGINE_SEL(V_370_PFP));
1724 radeon_emit(cs, va);
1725 radeon_emit(cs, va >> 32);
1726
1727 for (uint32_t l = 0; l < level_count; l++)
1728 radeon_emit(cs, value);
1729 }
1730
1731 static void
1732 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1733 const struct radv_image_view *iview,
1734 VkClearDepthStencilValue ds_clear_value)
1735 {
1736 VkImageSubresourceRange range = {
1737 .aspectMask = iview->aspect_mask,
1738 .baseMipLevel = iview->base_mip,
1739 .levelCount = iview->level_count,
1740 .baseArrayLayer = iview->base_layer,
1741 .layerCount = iview->layer_count,
1742 };
1743 uint32_t cond_val;
1744
1745 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1746 * depth clear value is 0.0f.
1747 */
1748 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1749
1750 radv_set_tc_compat_zrange_metadata(cmd_buffer, iview->image, &range,
1751 cond_val);
1752 }
1753
1754 /**
1755 * Update the clear depth/stencil values for this image.
1756 */
1757 void
1758 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1759 const struct radv_image_view *iview,
1760 VkClearDepthStencilValue ds_clear_value,
1761 VkImageAspectFlags aspects)
1762 {
1763 VkImageSubresourceRange range = {
1764 .aspectMask = iview->aspect_mask,
1765 .baseMipLevel = iview->base_mip,
1766 .levelCount = iview->level_count,
1767 .baseArrayLayer = iview->base_layer,
1768 .layerCount = iview->layer_count,
1769 };
1770 struct radv_image *image = iview->image;
1771
1772 assert(radv_image_has_htile(image));
1773
1774 radv_set_ds_clear_metadata(cmd_buffer, iview->image, &range,
1775 ds_clear_value, aspects);
1776
1777 if (radv_image_is_tc_compat_htile(image) &&
1778 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1779 radv_update_tc_compat_zrange_metadata(cmd_buffer, iview,
1780 ds_clear_value);
1781 }
1782
1783 radv_update_bound_fast_clear_ds(cmd_buffer, iview, ds_clear_value,
1784 aspects);
1785 }
1786
1787 /**
1788 * Load the clear depth/stencil values from the image's metadata.
1789 */
1790 static void
1791 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1792 const struct radv_image_view *iview)
1793 {
1794 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1795 const struct radv_image *image = iview->image;
1796 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1797 uint64_t va = radv_get_ds_clear_value_va(image, iview->base_mip);
1798 unsigned reg_offset = 0, reg_count = 0;
1799
1800 if (!radv_image_has_htile(image))
1801 return;
1802
1803 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1804 ++reg_count;
1805 } else {
1806 ++reg_offset;
1807 va += 4;
1808 }
1809 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1810 ++reg_count;
1811
1812 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1813
1814 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
1815 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1816 radeon_emit(cs, va);
1817 radeon_emit(cs, va >> 32);
1818 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1819 radeon_emit(cs, reg_count);
1820 } else {
1821 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1822 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1823 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1824 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1825 radeon_emit(cs, va);
1826 radeon_emit(cs, va >> 32);
1827 radeon_emit(cs, reg >> 2);
1828 radeon_emit(cs, 0);
1829
1830 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1831 radeon_emit(cs, 0);
1832 }
1833 }
1834
1835 /*
1836 * With DCC some colors don't require CMASK elimination before being
1837 * used as a texture. This sets a predicate value to determine if the
1838 * cmask eliminate is required.
1839 */
1840 void
1841 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1842 struct radv_image *image,
1843 const VkImageSubresourceRange *range, bool value)
1844 {
1845 uint64_t pred_val = value;
1846 uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
1847 uint32_t level_count = radv_get_levelCount(image, range);
1848 uint32_t count = 2 * level_count;
1849
1850 assert(radv_dcc_enabled(image, range->baseMipLevel));
1851
1852 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1853 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1854 S_370_WR_CONFIRM(1) |
1855 S_370_ENGINE_SEL(V_370_PFP));
1856 radeon_emit(cmd_buffer->cs, va);
1857 radeon_emit(cmd_buffer->cs, va >> 32);
1858
1859 for (uint32_t l = 0; l < level_count; l++) {
1860 radeon_emit(cmd_buffer->cs, pred_val);
1861 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1862 }
1863 }
1864
1865 /**
1866 * Update the DCC predicate to reflect the compression state.
1867 */
1868 void
1869 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1870 struct radv_image *image,
1871 const VkImageSubresourceRange *range, bool value)
1872 {
1873 uint64_t pred_val = value;
1874 uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
1875 uint32_t level_count = radv_get_levelCount(image, range);
1876 uint32_t count = 2 * level_count;
1877
1878 assert(radv_dcc_enabled(image, range->baseMipLevel));
1879
1880 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1881 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1882 S_370_WR_CONFIRM(1) |
1883 S_370_ENGINE_SEL(V_370_PFP));
1884 radeon_emit(cmd_buffer->cs, va);
1885 radeon_emit(cmd_buffer->cs, va >> 32);
1886
1887 for (uint32_t l = 0; l < level_count; l++) {
1888 radeon_emit(cmd_buffer->cs, pred_val);
1889 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1890 }
1891 }
1892
1893 /**
1894 * Update the fast clear color values if the image is bound as a color buffer.
1895 */
1896 static void
1897 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1898 struct radv_image *image,
1899 int cb_idx,
1900 uint32_t color_values[2])
1901 {
1902 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1903 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1904 uint32_t att_idx;
1905
1906 if (!cmd_buffer->state.attachments || !subpass)
1907 return;
1908
1909 att_idx = subpass->color_attachments[cb_idx].attachment;
1910 if (att_idx == VK_ATTACHMENT_UNUSED)
1911 return;
1912
1913 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1914 return;
1915
1916 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1917 radeon_emit(cs, color_values[0]);
1918 radeon_emit(cs, color_values[1]);
1919
1920 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1921 }
1922
1923 /**
1924 * Set the clear color values to the image's metadata.
1925 */
1926 static void
1927 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1928 struct radv_image *image,
1929 const VkImageSubresourceRange *range,
1930 uint32_t color_values[2])
1931 {
1932 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1933 uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
1934 uint32_t level_count = radv_get_levelCount(image, range);
1935 uint32_t count = 2 * level_count;
1936
1937 assert(radv_image_has_cmask(image) ||
1938 radv_dcc_enabled(image, range->baseMipLevel));
1939
1940 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
1941 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1942 S_370_WR_CONFIRM(1) |
1943 S_370_ENGINE_SEL(V_370_PFP));
1944 radeon_emit(cs, va);
1945 radeon_emit(cs, va >> 32);
1946
1947 for (uint32_t l = 0; l < level_count; l++) {
1948 radeon_emit(cs, color_values[0]);
1949 radeon_emit(cs, color_values[1]);
1950 }
1951 }
1952
1953 /**
1954 * Update the clear color values for this image.
1955 */
1956 void
1957 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1958 const struct radv_image_view *iview,
1959 int cb_idx,
1960 uint32_t color_values[2])
1961 {
1962 struct radv_image *image = iview->image;
1963 VkImageSubresourceRange range = {
1964 .aspectMask = iview->aspect_mask,
1965 .baseMipLevel = iview->base_mip,
1966 .levelCount = iview->level_count,
1967 .baseArrayLayer = iview->base_layer,
1968 .layerCount = iview->layer_count,
1969 };
1970
1971 assert(radv_image_has_cmask(image) ||
1972 radv_dcc_enabled(image, iview->base_mip));
1973
1974 radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
1975
1976 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1977 color_values);
1978 }
1979
1980 /**
1981 * Load the clear color values from the image's metadata.
1982 */
1983 static void
1984 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1985 struct radv_image_view *iview,
1986 int cb_idx)
1987 {
1988 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1989 struct radv_image *image = iview->image;
1990 uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
1991
1992 if (!radv_image_has_cmask(image) &&
1993 !radv_dcc_enabled(image, iview->base_mip))
1994 return;
1995
1996 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1997
1998 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
1999 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
2000 radeon_emit(cs, va);
2001 radeon_emit(cs, va >> 32);
2002 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
2003 radeon_emit(cs, 2);
2004 } else {
2005 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
2006 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2007 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2008 COPY_DATA_COUNT_SEL);
2009 radeon_emit(cs, va);
2010 radeon_emit(cs, va >> 32);
2011 radeon_emit(cs, reg >> 2);
2012 radeon_emit(cs, 0);
2013
2014 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
2015 radeon_emit(cs, 0);
2016 }
2017 }
2018
2019 static void
2020 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
2021 {
2022 int i;
2023 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
2024 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2025
2026 /* this may happen for inherited secondary recording */
2027 if (!framebuffer)
2028 return;
2029
2030 for (i = 0; i < 8; ++i) {
2031 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
2032 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2033 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2034 continue;
2035 }
2036
2037 int idx = subpass->color_attachments[i].attachment;
2038 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
2039 VkImageLayout layout = subpass->color_attachments[i].layout;
2040 bool in_render_loop = subpass->color_attachments[i].in_render_loop;
2041
2042 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, iview->bo);
2043
2044 assert(iview->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
2045 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
2046 radv_emit_fb_color_state(cmd_buffer, i, &cmd_buffer->state.attachments[idx].cb, iview, layout, in_render_loop);
2047
2048 radv_load_color_clear_metadata(cmd_buffer, iview, i);
2049 }
2050
2051 if (subpass->depth_stencil_attachment) {
2052 int idx = subpass->depth_stencil_attachment->attachment;
2053 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
2054 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
2055 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
2056 struct radv_image *image = iview->image;
2057 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, cmd_buffer->state.attachments[idx].iview->bo);
2058 ASSERTED uint32_t queue_mask = radv_image_queue_family_mask(image,
2059 cmd_buffer->queue_family_index,
2060 cmd_buffer->queue_family_index);
2061 /* We currently don't support writing decompressed HTILE */
2062 assert(radv_layout_has_htile(image, layout, in_render_loop, queue_mask) ==
2063 radv_layout_is_htile_compressed(image, layout, in_render_loop, queue_mask));
2064
2065 radv_emit_fb_ds_state(cmd_buffer, &cmd_buffer->state.attachments[idx].ds, iview, layout, in_render_loop);
2066
2067 if (cmd_buffer->state.attachments[idx].ds.offset_scale != cmd_buffer->state.offset_scale) {
2068 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2069 cmd_buffer->state.offset_scale = cmd_buffer->state.attachments[idx].ds.offset_scale;
2070 }
2071 radv_load_ds_clear_metadata(cmd_buffer, iview);
2072 } else {
2073 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9)
2074 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
2075 else
2076 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
2077
2078 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
2079 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
2080 }
2081 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2082 S_028208_BR_X(framebuffer->width) |
2083 S_028208_BR_Y(framebuffer->height));
2084
2085 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
2086 bool disable_constant_encode =
2087 cmd_buffer->device->physical_device->rad_info.has_dcc_constant_encode;
2088 enum chip_class chip_class =
2089 cmd_buffer->device->physical_device->rad_info.chip_class;
2090 uint8_t watermark = chip_class >= GFX10 ? 6 : 4;
2091
2092 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
2093 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class <= GFX9) |
2094 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
2095 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
2096 }
2097
2098 if (cmd_buffer->device->dfsm_allowed) {
2099 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2100 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
2101 }
2102
2103 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
2104 }
2105
2106 static void
2107 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer, bool indirect)
2108 {
2109 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2110 struct radv_cmd_state *state = &cmd_buffer->state;
2111
2112 if (state->index_type != state->last_index_type) {
2113 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2114 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2115 cs, R_03090C_VGT_INDEX_TYPE,
2116 2, state->index_type);
2117 } else {
2118 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2119 radeon_emit(cs, state->index_type);
2120 }
2121
2122 state->last_index_type = state->index_type;
2123 }
2124
2125 /* For the direct indexed draws we use DRAW_INDEX_2, which includes
2126 * the index_va and max_index_count already. */
2127 if (!indirect)
2128 return;
2129
2130 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2131 radeon_emit(cs, state->index_va);
2132 radeon_emit(cs, state->index_va >> 32);
2133
2134 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2135 radeon_emit(cs, state->max_index_count);
2136
2137 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
2138 }
2139
2140 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
2141 {
2142 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
2143 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2144 uint32_t pa_sc_mode_cntl_1 =
2145 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
2146 uint32_t db_count_control;
2147
2148 if(!cmd_buffer->state.active_occlusion_queries) {
2149 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2150 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2151 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2152 has_perfect_queries) {
2153 /* Re-enable out-of-order rasterization if the
2154 * bound pipeline supports it and if it's has
2155 * been disabled before starting any perfect
2156 * occlusion queries.
2157 */
2158 radeon_set_context_reg(cmd_buffer->cs,
2159 R_028A4C_PA_SC_MODE_CNTL_1,
2160 pa_sc_mode_cntl_1);
2161 }
2162 }
2163 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
2164 } else {
2165 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2166 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
2167 bool gfx10_perfect = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10 && has_perfect_queries;
2168
2169 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2170 db_count_control =
2171 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
2172 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
2173 S_028004_SAMPLE_RATE(sample_rate) |
2174 S_028004_ZPASS_ENABLE(1) |
2175 S_028004_SLICE_EVEN_ENABLE(1) |
2176 S_028004_SLICE_ODD_ENABLE(1);
2177
2178 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2179 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2180 has_perfect_queries) {
2181 /* If the bound pipeline has enabled
2182 * out-of-order rasterization, we should
2183 * disable it before starting any perfect
2184 * occlusion queries.
2185 */
2186 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
2187
2188 radeon_set_context_reg(cmd_buffer->cs,
2189 R_028A4C_PA_SC_MODE_CNTL_1,
2190 pa_sc_mode_cntl_1);
2191 }
2192 } else {
2193 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
2194 S_028004_SAMPLE_RATE(sample_rate);
2195 }
2196 }
2197
2198 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
2199
2200 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2201 }
2202
2203 static void
2204 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
2205 {
2206 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
2207
2208 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
2209 radv_emit_viewport(cmd_buffer);
2210
2211 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
2212 !cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
2213 radv_emit_scissor(cmd_buffer);
2214
2215 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
2216 radv_emit_line_width(cmd_buffer);
2217
2218 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
2219 radv_emit_blend_constants(cmd_buffer);
2220
2221 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
2222 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
2223 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
2224 radv_emit_stencil(cmd_buffer);
2225
2226 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
2227 radv_emit_depth_bounds(cmd_buffer);
2228
2229 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
2230 radv_emit_depth_bias(cmd_buffer);
2231
2232 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
2233 radv_emit_discard_rectangle(cmd_buffer);
2234
2235 if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)
2236 radv_emit_sample_locations(cmd_buffer);
2237
2238 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE)
2239 radv_emit_line_stipple(cmd_buffer);
2240
2241 cmd_buffer->state.dirty &= ~states;
2242 }
2243
2244 static void
2245 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
2246 VkPipelineBindPoint bind_point)
2247 {
2248 struct radv_descriptor_state *descriptors_state =
2249 radv_get_descriptors_state(cmd_buffer, bind_point);
2250 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
2251 unsigned bo_offset;
2252
2253 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
2254 set->mapped_ptr,
2255 &bo_offset))
2256 return;
2257
2258 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2259 set->va += bo_offset;
2260 }
2261
2262 static void
2263 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
2264 VkPipelineBindPoint bind_point)
2265 {
2266 struct radv_descriptor_state *descriptors_state =
2267 radv_get_descriptors_state(cmd_buffer, bind_point);
2268 uint32_t size = MAX_SETS * 4;
2269 uint32_t offset;
2270 void *ptr;
2271
2272 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
2273 256, &offset, &ptr))
2274 return;
2275
2276 for (unsigned i = 0; i < MAX_SETS; i++) {
2277 uint32_t *uptr = ((uint32_t *)ptr) + i;
2278 uint64_t set_va = 0;
2279 struct radv_descriptor_set *set = descriptors_state->sets[i];
2280 if (descriptors_state->valid & (1u << i))
2281 set_va = set->va;
2282 uptr[0] = set_va & 0xffffffff;
2283 }
2284
2285 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2286 va += offset;
2287
2288 if (cmd_buffer->state.pipeline) {
2289 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
2290 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2291 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2292
2293 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
2294 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
2295 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2296
2297 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
2298 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2299 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2300
2301 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2302 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
2303 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2304
2305 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2306 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
2307 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2308 }
2309
2310 if (cmd_buffer->state.compute_pipeline)
2311 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
2312 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2313 }
2314
2315 static void
2316 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
2317 VkShaderStageFlags stages)
2318 {
2319 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2320 VK_PIPELINE_BIND_POINT_COMPUTE :
2321 VK_PIPELINE_BIND_POINT_GRAPHICS;
2322 struct radv_descriptor_state *descriptors_state =
2323 radv_get_descriptors_state(cmd_buffer, bind_point);
2324 struct radv_cmd_state *state = &cmd_buffer->state;
2325 bool flush_indirect_descriptors;
2326
2327 if (!descriptors_state->dirty)
2328 return;
2329
2330 if (descriptors_state->push_dirty)
2331 radv_flush_push_descriptors(cmd_buffer, bind_point);
2332
2333 flush_indirect_descriptors =
2334 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
2335 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
2336 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
2337 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
2338
2339 if (flush_indirect_descriptors)
2340 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
2341
2342 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2343 cmd_buffer->cs,
2344 MAX_SETS * MESA_SHADER_STAGES * 4);
2345
2346 if (cmd_buffer->state.pipeline) {
2347 radv_foreach_stage(stage, stages) {
2348 if (!cmd_buffer->state.pipeline->shaders[stage])
2349 continue;
2350
2351 radv_emit_descriptor_pointers(cmd_buffer,
2352 cmd_buffer->state.pipeline,
2353 descriptors_state, stage);
2354 }
2355 }
2356
2357 if (cmd_buffer->state.compute_pipeline &&
2358 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
2359 radv_emit_descriptor_pointers(cmd_buffer,
2360 cmd_buffer->state.compute_pipeline,
2361 descriptors_state,
2362 MESA_SHADER_COMPUTE);
2363 }
2364
2365 descriptors_state->dirty = 0;
2366 descriptors_state->push_dirty = false;
2367
2368 assert(cmd_buffer->cs->cdw <= cdw_max);
2369
2370 if (unlikely(cmd_buffer->device->trace_bo))
2371 radv_save_descriptors(cmd_buffer, bind_point);
2372 }
2373
2374 static void
2375 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
2376 VkShaderStageFlags stages)
2377 {
2378 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
2379 ? cmd_buffer->state.compute_pipeline
2380 : cmd_buffer->state.pipeline;
2381 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2382 VK_PIPELINE_BIND_POINT_COMPUTE :
2383 VK_PIPELINE_BIND_POINT_GRAPHICS;
2384 struct radv_descriptor_state *descriptors_state =
2385 radv_get_descriptors_state(cmd_buffer, bind_point);
2386 struct radv_pipeline_layout *layout = pipeline->layout;
2387 struct radv_shader_variant *shader, *prev_shader;
2388 bool need_push_constants = false;
2389 unsigned offset;
2390 void *ptr;
2391 uint64_t va;
2392
2393 stages &= cmd_buffer->push_constant_stages;
2394 if (!stages ||
2395 (!layout->push_constant_size && !layout->dynamic_offset_count))
2396 return;
2397
2398 radv_foreach_stage(stage, stages) {
2399 shader = radv_get_shader(pipeline, stage);
2400 if (!shader)
2401 continue;
2402
2403 need_push_constants |= shader->info.loads_push_constants;
2404 need_push_constants |= shader->info.loads_dynamic_offsets;
2405
2406 uint8_t base = shader->info.base_inline_push_consts;
2407 uint8_t count = shader->info.num_inline_push_consts;
2408
2409 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
2410 AC_UD_INLINE_PUSH_CONSTANTS,
2411 count,
2412 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
2413 }
2414
2415 if (need_push_constants) {
2416 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
2417 16 * layout->dynamic_offset_count,
2418 256, &offset, &ptr))
2419 return;
2420
2421 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
2422 memcpy((char*)ptr + layout->push_constant_size,
2423 descriptors_state->dynamic_buffers,
2424 16 * layout->dynamic_offset_count);
2425
2426 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2427 va += offset;
2428
2429 ASSERTED unsigned cdw_max =
2430 radeon_check_space(cmd_buffer->device->ws,
2431 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
2432
2433 prev_shader = NULL;
2434 radv_foreach_stage(stage, stages) {
2435 shader = radv_get_shader(pipeline, stage);
2436
2437 /* Avoid redundantly emitting the address for merged stages. */
2438 if (shader && shader != prev_shader) {
2439 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
2440 AC_UD_PUSH_CONSTANTS, va);
2441
2442 prev_shader = shader;
2443 }
2444 }
2445 assert(cmd_buffer->cs->cdw <= cdw_max);
2446 }
2447
2448 cmd_buffer->push_constant_stages &= ~stages;
2449 }
2450
2451 static void
2452 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
2453 bool pipeline_is_dirty)
2454 {
2455 if ((pipeline_is_dirty ||
2456 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
2457 cmd_buffer->state.pipeline->num_vertex_bindings &&
2458 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.has_vertex_buffers) {
2459 unsigned vb_offset;
2460 void *vb_ptr;
2461 uint32_t i = 0;
2462 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
2463 uint64_t va;
2464
2465 /* allocate some descriptor state for vertex buffers */
2466 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2467 &vb_offset, &vb_ptr))
2468 return;
2469
2470 for (i = 0; i < count; i++) {
2471 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2472 uint32_t offset;
2473 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2474 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[i];
2475 unsigned num_records;
2476
2477 if (!buffer)
2478 continue;
2479
2480 va = radv_buffer_get_va(buffer->bo);
2481
2482 offset = cmd_buffer->vertex_bindings[i].offset;
2483 va += offset + buffer->offset;
2484
2485 num_records = buffer->size - offset;
2486 if (cmd_buffer->device->physical_device->rad_info.chip_class != GFX8 && stride)
2487 num_records /= stride;
2488
2489 desc[0] = va;
2490 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2491 desc[2] = num_records;
2492 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2493 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2494 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2495 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2496
2497 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2498 /* OOB_SELECT chooses the out-of-bounds check:
2499 * - 1: index >= NUM_RECORDS (Structured)
2500 * - 3: offset >= NUM_RECORDS (Raw)
2501 */
2502 int oob_select = stride ? V_008F0C_OOB_SELECT_STRUCTURED : V_008F0C_OOB_SELECT_RAW;
2503
2504 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT) |
2505 S_008F0C_OOB_SELECT(oob_select) |
2506 S_008F0C_RESOURCE_LEVEL(1);
2507 } else {
2508 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2509 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2510 }
2511 }
2512
2513 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2514 va += vb_offset;
2515
2516 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2517 AC_UD_VS_VERTEX_BUFFERS, va);
2518
2519 cmd_buffer->state.vb_va = va;
2520 cmd_buffer->state.vb_size = count * 16;
2521 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2522 }
2523 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2524 }
2525
2526 static void
2527 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2528 {
2529 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2530 struct radv_userdata_info *loc;
2531 uint32_t base_reg;
2532
2533 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2534 if (!radv_get_shader(pipeline, stage))
2535 continue;
2536
2537 loc = radv_lookup_user_sgpr(pipeline, stage,
2538 AC_UD_STREAMOUT_BUFFERS);
2539 if (loc->sgpr_idx == -1)
2540 continue;
2541
2542 base_reg = pipeline->user_data_0[stage];
2543
2544 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2545 base_reg + loc->sgpr_idx * 4, va, false);
2546 }
2547
2548 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
2549 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2550 if (loc->sgpr_idx != -1) {
2551 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2552
2553 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2554 base_reg + loc->sgpr_idx * 4, va, false);
2555 }
2556 }
2557 }
2558
2559 static void
2560 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2561 {
2562 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2563 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2564 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2565 unsigned so_offset;
2566 void *so_ptr;
2567 uint64_t va;
2568
2569 /* Allocate some descriptor state for streamout buffers. */
2570 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2571 MAX_SO_BUFFERS * 16, 256,
2572 &so_offset, &so_ptr))
2573 return;
2574
2575 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2576 struct radv_buffer *buffer = sb[i].buffer;
2577 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2578
2579 if (!(so->enabled_mask & (1 << i)))
2580 continue;
2581
2582 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2583
2584 va += sb[i].offset;
2585
2586 /* Set the descriptor.
2587 *
2588 * On GFX8, the format must be non-INVALID, otherwise
2589 * the buffer will be considered not bound and store
2590 * instructions will be no-ops.
2591 */
2592 uint32_t size = 0xffffffff;
2593
2594 /* Compute the correct buffer size for NGG streamout
2595 * because it's used to determine the max emit per
2596 * buffer.
2597 */
2598 if (cmd_buffer->device->physical_device->use_ngg_streamout)
2599 size = buffer->size - sb[i].offset;
2600
2601 desc[0] = va;
2602 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2603 desc[2] = size;
2604 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2605 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2606 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2607 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2608
2609 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2610 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2611 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
2612 S_008F0C_RESOURCE_LEVEL(1);
2613 } else {
2614 desc[3] |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2615 }
2616 }
2617
2618 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2619 va += so_offset;
2620
2621 radv_emit_streamout_buffers(cmd_buffer, va);
2622 }
2623
2624 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2625 }
2626
2627 static void
2628 radv_flush_ngg_gs_state(struct radv_cmd_buffer *cmd_buffer)
2629 {
2630 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2631 struct radv_userdata_info *loc;
2632 uint32_t ngg_gs_state = 0;
2633 uint32_t base_reg;
2634
2635 if (!radv_pipeline_has_gs(pipeline) ||
2636 !radv_pipeline_has_ngg(pipeline))
2637 return;
2638
2639 /* By default NGG GS queries are disabled but they are enabled if the
2640 * command buffer has active GDS queries or if it's a secondary command
2641 * buffer that inherits the number of generated primitives.
2642 */
2643 if (cmd_buffer->state.active_pipeline_gds_queries ||
2644 (cmd_buffer->state.inherited_pipeline_statistics & VK_QUERY_PIPELINE_STATISTIC_GEOMETRY_SHADER_PRIMITIVES_BIT))
2645 ngg_gs_state = 1;
2646
2647 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_GEOMETRY,
2648 AC_UD_NGG_GS_STATE);
2649 base_reg = pipeline->user_data_0[MESA_SHADER_GEOMETRY];
2650 assert(loc->sgpr_idx != -1);
2651
2652 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
2653 ngg_gs_state);
2654 }
2655
2656 static void
2657 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2658 {
2659 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2660 radv_flush_streamout_descriptors(cmd_buffer);
2661 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2662 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2663 radv_flush_ngg_gs_state(cmd_buffer);
2664 }
2665
2666 struct radv_draw_info {
2667 /**
2668 * Number of vertices.
2669 */
2670 uint32_t count;
2671
2672 /**
2673 * Index of the first vertex.
2674 */
2675 int32_t vertex_offset;
2676
2677 /**
2678 * First instance id.
2679 */
2680 uint32_t first_instance;
2681
2682 /**
2683 * Number of instances.
2684 */
2685 uint32_t instance_count;
2686
2687 /**
2688 * First index (indexed draws only).
2689 */
2690 uint32_t first_index;
2691
2692 /**
2693 * Whether it's an indexed draw.
2694 */
2695 bool indexed;
2696
2697 /**
2698 * Indirect draw parameters resource.
2699 */
2700 struct radv_buffer *indirect;
2701 uint64_t indirect_offset;
2702 uint32_t stride;
2703
2704 /**
2705 * Draw count parameters resource.
2706 */
2707 struct radv_buffer *count_buffer;
2708 uint64_t count_buffer_offset;
2709
2710 /**
2711 * Stream output parameters resource.
2712 */
2713 struct radv_buffer *strmout_buffer;
2714 uint64_t strmout_buffer_offset;
2715 };
2716
2717 static uint32_t
2718 radv_get_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
2719 {
2720 switch (cmd_buffer->state.index_type) {
2721 case V_028A7C_VGT_INDEX_8:
2722 return 0xffu;
2723 case V_028A7C_VGT_INDEX_16:
2724 return 0xffffu;
2725 case V_028A7C_VGT_INDEX_32:
2726 return 0xffffffffu;
2727 default:
2728 unreachable("invalid index type");
2729 }
2730 }
2731
2732 static void
2733 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
2734 bool instanced_draw, bool indirect_draw,
2735 bool count_from_stream_output,
2736 uint32_t draw_vertex_count)
2737 {
2738 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2739 struct radv_cmd_state *state = &cmd_buffer->state;
2740 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2741 unsigned ia_multi_vgt_param;
2742
2743 ia_multi_vgt_param =
2744 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
2745 indirect_draw,
2746 count_from_stream_output,
2747 draw_vertex_count);
2748
2749 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2750 if (info->chip_class == GFX9) {
2751 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2752 cs,
2753 R_030960_IA_MULTI_VGT_PARAM,
2754 4, ia_multi_vgt_param);
2755 } else if (info->chip_class >= GFX7) {
2756 radeon_set_context_reg_idx(cs,
2757 R_028AA8_IA_MULTI_VGT_PARAM,
2758 1, ia_multi_vgt_param);
2759 } else {
2760 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2761 ia_multi_vgt_param);
2762 }
2763 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2764 }
2765 }
2766
2767 static void
2768 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2769 const struct radv_draw_info *draw_info)
2770 {
2771 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2772 struct radv_cmd_state *state = &cmd_buffer->state;
2773 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2774 int32_t primitive_reset_en;
2775
2776 /* Draw state. */
2777 if (info->chip_class < GFX10) {
2778 si_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2779 draw_info->indirect,
2780 !!draw_info->strmout_buffer,
2781 draw_info->indirect ? 0 : draw_info->count);
2782 }
2783
2784 /* Primitive restart. */
2785 primitive_reset_en =
2786 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2787
2788 if (primitive_reset_en != state->last_primitive_reset_en) {
2789 state->last_primitive_reset_en = primitive_reset_en;
2790 if (info->chip_class >= GFX9) {
2791 radeon_set_uconfig_reg(cs,
2792 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2793 primitive_reset_en);
2794 } else {
2795 radeon_set_context_reg(cs,
2796 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2797 primitive_reset_en);
2798 }
2799 }
2800
2801 if (primitive_reset_en) {
2802 uint32_t primitive_reset_index =
2803 radv_get_primitive_reset_index(cmd_buffer);
2804
2805 if (primitive_reset_index != state->last_primitive_reset_index) {
2806 radeon_set_context_reg(cs,
2807 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2808 primitive_reset_index);
2809 state->last_primitive_reset_index = primitive_reset_index;
2810 }
2811 }
2812
2813 if (draw_info->strmout_buffer) {
2814 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2815
2816 va += draw_info->strmout_buffer->offset +
2817 draw_info->strmout_buffer_offset;
2818
2819 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2820 draw_info->stride);
2821
2822 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2823 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2824 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2825 COPY_DATA_WR_CONFIRM);
2826 radeon_emit(cs, va);
2827 radeon_emit(cs, va >> 32);
2828 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2829 radeon_emit(cs, 0); /* unused */
2830
2831 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2832 }
2833 }
2834
2835 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2836 VkPipelineStageFlags src_stage_mask)
2837 {
2838 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2839 VK_PIPELINE_STAGE_TRANSFER_BIT |
2840 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2841 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2842 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2843 }
2844
2845 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2846 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2847 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2848 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2849 VK_PIPELINE_STAGE_TRANSFER_BIT |
2850 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2851 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2852 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2853 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2854 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2855 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2856 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2857 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2858 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2859 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2860 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2861 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2862 }
2863 }
2864
2865 static enum radv_cmd_flush_bits
2866 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2867 VkAccessFlags src_flags,
2868 struct radv_image *image)
2869 {
2870 bool flush_CB_meta = true, flush_DB_meta = true;
2871 enum radv_cmd_flush_bits flush_bits = 0;
2872 uint32_t b;
2873
2874 if (image) {
2875 if (!radv_image_has_CB_metadata(image))
2876 flush_CB_meta = false;
2877 if (!radv_image_has_htile(image))
2878 flush_DB_meta = false;
2879 }
2880
2881 for_each_bit(b, src_flags) {
2882 switch ((VkAccessFlagBits)(1 << b)) {
2883 case VK_ACCESS_SHADER_WRITE_BIT:
2884 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2885 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2886 flush_bits |= RADV_CMD_FLAG_WB_L2;
2887 break;
2888 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2889 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2890 if (flush_CB_meta)
2891 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2892 break;
2893 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2894 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2895 if (flush_DB_meta)
2896 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2897 break;
2898 case VK_ACCESS_TRANSFER_WRITE_BIT:
2899 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2900 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2901 RADV_CMD_FLAG_INV_L2;
2902
2903 if (flush_CB_meta)
2904 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2905 if (flush_DB_meta)
2906 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2907 break;
2908 default:
2909 break;
2910 }
2911 }
2912 return flush_bits;
2913 }
2914
2915 static enum radv_cmd_flush_bits
2916 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2917 VkAccessFlags dst_flags,
2918 struct radv_image *image)
2919 {
2920 bool flush_CB_meta = true, flush_DB_meta = true;
2921 enum radv_cmd_flush_bits flush_bits = 0;
2922 bool flush_CB = true, flush_DB = true;
2923 bool image_is_coherent = false;
2924 uint32_t b;
2925
2926 if (image) {
2927 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2928 flush_CB = false;
2929 flush_DB = false;
2930 }
2931
2932 if (!radv_image_has_CB_metadata(image))
2933 flush_CB_meta = false;
2934 if (!radv_image_has_htile(image))
2935 flush_DB_meta = false;
2936
2937 /* TODO: implement shader coherent for GFX10 */
2938
2939 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
2940 if (image->info.samples == 1 &&
2941 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2942 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2943 !vk_format_is_stencil(image->vk_format)) {
2944 /* Single-sample color and single-sample depth
2945 * (not stencil) are coherent with shaders on
2946 * GFX9.
2947 */
2948 image_is_coherent = true;
2949 }
2950 }
2951 }
2952
2953 for_each_bit(b, dst_flags) {
2954 switch ((VkAccessFlagBits)(1 << b)) {
2955 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2956 case VK_ACCESS_INDEX_READ_BIT:
2957 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2958 break;
2959 case VK_ACCESS_UNIFORM_READ_BIT:
2960 flush_bits |= RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_SCACHE;
2961 break;
2962 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2963 case VK_ACCESS_TRANSFER_READ_BIT:
2964 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2965 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
2966 RADV_CMD_FLAG_INV_L2;
2967 break;
2968 case VK_ACCESS_SHADER_READ_BIT:
2969 flush_bits |= RADV_CMD_FLAG_INV_VCACHE;
2970 /* Unlike LLVM, ACO uses SMEM for SSBOs and we have to
2971 * invalidate the scalar cache. */
2972 if (cmd_buffer->device->physical_device->use_aco &&
2973 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8)
2974 flush_bits |= RADV_CMD_FLAG_INV_SCACHE;
2975
2976 if (!image_is_coherent)
2977 flush_bits |= RADV_CMD_FLAG_INV_L2;
2978 break;
2979 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2980 if (flush_CB)
2981 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2982 if (flush_CB_meta)
2983 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2984 break;
2985 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2986 if (flush_DB)
2987 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2988 if (flush_DB_meta)
2989 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2990 break;
2991 default:
2992 break;
2993 }
2994 }
2995 return flush_bits;
2996 }
2997
2998 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2999 const struct radv_subpass_barrier *barrier)
3000 {
3001 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
3002 NULL);
3003 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
3004 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
3005 NULL);
3006 }
3007
3008 uint32_t
3009 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
3010 {
3011 struct radv_cmd_state *state = &cmd_buffer->state;
3012 uint32_t subpass_id = state->subpass - state->pass->subpasses;
3013
3014 /* The id of this subpass shouldn't exceed the number of subpasses in
3015 * this render pass minus 1.
3016 */
3017 assert(subpass_id < state->pass->subpass_count);
3018 return subpass_id;
3019 }
3020
3021 static struct radv_sample_locations_state *
3022 radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer,
3023 uint32_t att_idx,
3024 bool begin_subpass)
3025 {
3026 struct radv_cmd_state *state = &cmd_buffer->state;
3027 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
3028 struct radv_image_view *view = state->attachments[att_idx].iview;
3029
3030 if (view->image->info.samples == 1)
3031 return NULL;
3032
3033 if (state->pass->attachments[att_idx].first_subpass_idx == subpass_id) {
3034 /* Return the initial sample locations if this is the initial
3035 * layout transition of the given subpass attachemnt.
3036 */
3037 if (state->attachments[att_idx].sample_location.count > 0)
3038 return &state->attachments[att_idx].sample_location;
3039 } else {
3040 /* Otherwise return the subpass sample locations if defined. */
3041 if (state->subpass_sample_locs) {
3042 /* Because the driver sets the current subpass before
3043 * initial layout transitions, we should use the sample
3044 * locations from the previous subpass to avoid an
3045 * off-by-one problem. Otherwise, use the sample
3046 * locations for the current subpass for final layout
3047 * transitions.
3048 */
3049 if (begin_subpass)
3050 subpass_id--;
3051
3052 for (uint32_t i = 0; i < state->num_subpass_sample_locs; i++) {
3053 if (state->subpass_sample_locs[i].subpass_idx == subpass_id)
3054 return &state->subpass_sample_locs[i].sample_location;
3055 }
3056 }
3057 }
3058
3059 return NULL;
3060 }
3061
3062 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
3063 struct radv_subpass_attachment att,
3064 bool begin_subpass)
3065 {
3066 unsigned idx = att.attachment;
3067 struct radv_image_view *view = cmd_buffer->state.attachments[idx].iview;
3068 struct radv_sample_locations_state *sample_locs;
3069 VkImageSubresourceRange range;
3070 range.aspectMask = view->aspect_mask;
3071 range.baseMipLevel = view->base_mip;
3072 range.levelCount = 1;
3073 range.baseArrayLayer = view->base_layer;
3074 range.layerCount = cmd_buffer->state.framebuffer->layers;
3075
3076 if (cmd_buffer->state.subpass->view_mask) {
3077 /* If the current subpass uses multiview, the driver might have
3078 * performed a fast color/depth clear to the whole image
3079 * (including all layers). To make sure the driver will
3080 * decompress the image correctly (if needed), we have to
3081 * account for the "real" number of layers. If the view mask is
3082 * sparse, this will decompress more layers than needed.
3083 */
3084 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
3085 }
3086
3087 /* Get the subpass sample locations for the given attachment, if NULL
3088 * is returned the driver will use the default HW locations.
3089 */
3090 sample_locs = radv_get_attachment_sample_locations(cmd_buffer, idx,
3091 begin_subpass);
3092
3093 /* Determine if the subpass uses separate depth/stencil layouts. */
3094 bool uses_separate_depth_stencil_layouts = false;
3095 if ((cmd_buffer->state.attachments[idx].current_layout !=
3096 cmd_buffer->state.attachments[idx].current_stencil_layout) ||
3097 (att.layout != att.stencil_layout)) {
3098 uses_separate_depth_stencil_layouts = true;
3099 }
3100
3101 /* For separate layouts, perform depth and stencil transitions
3102 * separately.
3103 */
3104 if (uses_separate_depth_stencil_layouts &&
3105 (range.aspectMask == (VK_IMAGE_ASPECT_DEPTH_BIT |
3106 VK_IMAGE_ASPECT_STENCIL_BIT))) {
3107 /* Depth-only transitions. */
3108 range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3109 radv_handle_image_transition(cmd_buffer,
3110 view->image,
3111 cmd_buffer->state.attachments[idx].current_layout,
3112 cmd_buffer->state.attachments[idx].current_in_render_loop,
3113 att.layout, att.in_render_loop,
3114 0, 0, &range, sample_locs);
3115
3116 /* Stencil-only transitions. */
3117 range.aspectMask = VK_IMAGE_ASPECT_STENCIL_BIT;
3118 radv_handle_image_transition(cmd_buffer,
3119 view->image,
3120 cmd_buffer->state.attachments[idx].current_stencil_layout,
3121 cmd_buffer->state.attachments[idx].current_in_render_loop,
3122 att.stencil_layout, att.in_render_loop,
3123 0, 0, &range, sample_locs);
3124 } else {
3125 radv_handle_image_transition(cmd_buffer,
3126 view->image,
3127 cmd_buffer->state.attachments[idx].current_layout,
3128 cmd_buffer->state.attachments[idx].current_in_render_loop,
3129 att.layout, att.in_render_loop,
3130 0, 0, &range, sample_locs);
3131 }
3132
3133 cmd_buffer->state.attachments[idx].current_layout = att.layout;
3134 cmd_buffer->state.attachments[idx].current_stencil_layout = att.stencil_layout;
3135 cmd_buffer->state.attachments[idx].current_in_render_loop = att.in_render_loop;
3136
3137
3138 }
3139
3140 void
3141 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
3142 const struct radv_subpass *subpass)
3143 {
3144 cmd_buffer->state.subpass = subpass;
3145
3146 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
3147 }
3148
3149 static VkResult
3150 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
3151 struct radv_render_pass *pass,
3152 const VkRenderPassBeginInfo *info)
3153 {
3154 const struct VkRenderPassSampleLocationsBeginInfoEXT *sample_locs =
3155 vk_find_struct_const(info->pNext,
3156 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT);
3157 struct radv_cmd_state *state = &cmd_buffer->state;
3158
3159 if (!sample_locs) {
3160 state->subpass_sample_locs = NULL;
3161 return VK_SUCCESS;
3162 }
3163
3164 for (uint32_t i = 0; i < sample_locs->attachmentInitialSampleLocationsCount; i++) {
3165 const VkAttachmentSampleLocationsEXT *att_sample_locs =
3166 &sample_locs->pAttachmentInitialSampleLocations[i];
3167 uint32_t att_idx = att_sample_locs->attachmentIndex;
3168 struct radv_image *image = cmd_buffer->state.attachments[att_idx].iview->image;
3169
3170 assert(vk_format_is_depth_or_stencil(image->vk_format));
3171
3172 /* From the Vulkan spec 1.1.108:
3173 *
3174 * "If the image referenced by the framebuffer attachment at
3175 * index attachmentIndex was not created with
3176 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
3177 * then the values specified in sampleLocationsInfo are
3178 * ignored."
3179 */
3180 if (!(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT))
3181 continue;
3182
3183 const VkSampleLocationsInfoEXT *sample_locs_info =
3184 &att_sample_locs->sampleLocationsInfo;
3185
3186 state->attachments[att_idx].sample_location.per_pixel =
3187 sample_locs_info->sampleLocationsPerPixel;
3188 state->attachments[att_idx].sample_location.grid_size =
3189 sample_locs_info->sampleLocationGridSize;
3190 state->attachments[att_idx].sample_location.count =
3191 sample_locs_info->sampleLocationsCount;
3192 typed_memcpy(&state->attachments[att_idx].sample_location.locations[0],
3193 sample_locs_info->pSampleLocations,
3194 sample_locs_info->sampleLocationsCount);
3195 }
3196
3197 state->subpass_sample_locs = vk_alloc(&cmd_buffer->pool->alloc,
3198 sample_locs->postSubpassSampleLocationsCount *
3199 sizeof(state->subpass_sample_locs[0]),
3200 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3201 if (state->subpass_sample_locs == NULL) {
3202 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3203 return cmd_buffer->record_result;
3204 }
3205
3206 state->num_subpass_sample_locs = sample_locs->postSubpassSampleLocationsCount;
3207
3208 for (uint32_t i = 0; i < sample_locs->postSubpassSampleLocationsCount; i++) {
3209 const VkSubpassSampleLocationsEXT *subpass_sample_locs_info =
3210 &sample_locs->pPostSubpassSampleLocations[i];
3211 const VkSampleLocationsInfoEXT *sample_locs_info =
3212 &subpass_sample_locs_info->sampleLocationsInfo;
3213
3214 state->subpass_sample_locs[i].subpass_idx =
3215 subpass_sample_locs_info->subpassIndex;
3216 state->subpass_sample_locs[i].sample_location.per_pixel =
3217 sample_locs_info->sampleLocationsPerPixel;
3218 state->subpass_sample_locs[i].sample_location.grid_size =
3219 sample_locs_info->sampleLocationGridSize;
3220 state->subpass_sample_locs[i].sample_location.count =
3221 sample_locs_info->sampleLocationsCount;
3222 typed_memcpy(&state->subpass_sample_locs[i].sample_location.locations[0],
3223 sample_locs_info->pSampleLocations,
3224 sample_locs_info->sampleLocationsCount);
3225 }
3226
3227 return VK_SUCCESS;
3228 }
3229
3230 static VkResult
3231 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
3232 struct radv_render_pass *pass,
3233 const VkRenderPassBeginInfo *info)
3234 {
3235 struct radv_cmd_state *state = &cmd_buffer->state;
3236 const struct VkRenderPassAttachmentBeginInfo *attachment_info = NULL;
3237
3238 if (info) {
3239 attachment_info = vk_find_struct_const(info->pNext,
3240 RENDER_PASS_ATTACHMENT_BEGIN_INFO);
3241 }
3242
3243
3244 if (pass->attachment_count == 0) {
3245 state->attachments = NULL;
3246 return VK_SUCCESS;
3247 }
3248
3249 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
3250 pass->attachment_count *
3251 sizeof(state->attachments[0]),
3252 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3253 if (state->attachments == NULL) {
3254 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3255 return cmd_buffer->record_result;
3256 }
3257
3258 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
3259 struct radv_render_pass_attachment *att = &pass->attachments[i];
3260 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
3261 VkImageAspectFlags clear_aspects = 0;
3262
3263 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
3264 /* color attachment */
3265 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3266 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
3267 }
3268 } else {
3269 /* depthstencil attachment */
3270 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
3271 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3272 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
3273 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3274 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
3275 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3276 }
3277 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3278 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3279 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3280 }
3281 }
3282
3283 state->attachments[i].pending_clear_aspects = clear_aspects;
3284 state->attachments[i].cleared_views = 0;
3285 if (clear_aspects && info) {
3286 assert(info->clearValueCount > i);
3287 state->attachments[i].clear_value = info->pClearValues[i];
3288 }
3289
3290 state->attachments[i].current_layout = att->initial_layout;
3291 state->attachments[i].current_stencil_layout = att->stencil_initial_layout;
3292 state->attachments[i].sample_location.count = 0;
3293
3294 struct radv_image_view *iview;
3295 if (attachment_info && attachment_info->attachmentCount > i) {
3296 iview = radv_image_view_from_handle(attachment_info->pAttachments[i]);
3297 } else {
3298 iview = state->framebuffer->attachments[i];
3299 }
3300
3301 state->attachments[i].iview = iview;
3302 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3303 radv_initialise_ds_surface(cmd_buffer->device, &state->attachments[i].ds, iview);
3304 } else {
3305 radv_initialise_color_surface(cmd_buffer->device, &state->attachments[i].cb, iview);
3306 }
3307 }
3308
3309 return VK_SUCCESS;
3310 }
3311
3312 VkResult radv_AllocateCommandBuffers(
3313 VkDevice _device,
3314 const VkCommandBufferAllocateInfo *pAllocateInfo,
3315 VkCommandBuffer *pCommandBuffers)
3316 {
3317 RADV_FROM_HANDLE(radv_device, device, _device);
3318 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
3319
3320 VkResult result = VK_SUCCESS;
3321 uint32_t i;
3322
3323 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
3324
3325 if (!list_is_empty(&pool->free_cmd_buffers)) {
3326 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
3327
3328 list_del(&cmd_buffer->pool_link);
3329 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
3330
3331 result = radv_reset_cmd_buffer(cmd_buffer);
3332 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
3333 cmd_buffer->level = pAllocateInfo->level;
3334
3335 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
3336 } else {
3337 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
3338 &pCommandBuffers[i]);
3339 }
3340 if (result != VK_SUCCESS)
3341 break;
3342 }
3343
3344 if (result != VK_SUCCESS) {
3345 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
3346 i, pCommandBuffers);
3347
3348 /* From the Vulkan 1.0.66 spec:
3349 *
3350 * "vkAllocateCommandBuffers can be used to create multiple
3351 * command buffers. If the creation of any of those command
3352 * buffers fails, the implementation must destroy all
3353 * successfully created command buffer objects from this
3354 * command, set all entries of the pCommandBuffers array to
3355 * NULL and return the error."
3356 */
3357 memset(pCommandBuffers, 0,
3358 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
3359 }
3360
3361 return result;
3362 }
3363
3364 void radv_FreeCommandBuffers(
3365 VkDevice device,
3366 VkCommandPool commandPool,
3367 uint32_t commandBufferCount,
3368 const VkCommandBuffer *pCommandBuffers)
3369 {
3370 for (uint32_t i = 0; i < commandBufferCount; i++) {
3371 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
3372
3373 if (cmd_buffer) {
3374 if (cmd_buffer->pool) {
3375 list_del(&cmd_buffer->pool_link);
3376 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
3377 } else
3378 radv_cmd_buffer_destroy(cmd_buffer);
3379
3380 }
3381 }
3382 }
3383
3384 VkResult radv_ResetCommandBuffer(
3385 VkCommandBuffer commandBuffer,
3386 VkCommandBufferResetFlags flags)
3387 {
3388 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3389 return radv_reset_cmd_buffer(cmd_buffer);
3390 }
3391
3392 VkResult radv_BeginCommandBuffer(
3393 VkCommandBuffer commandBuffer,
3394 const VkCommandBufferBeginInfo *pBeginInfo)
3395 {
3396 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3397 VkResult result = VK_SUCCESS;
3398
3399 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
3400 /* If the command buffer has already been resetted with
3401 * vkResetCommandBuffer, no need to do it again.
3402 */
3403 result = radv_reset_cmd_buffer(cmd_buffer);
3404 if (result != VK_SUCCESS)
3405 return result;
3406 }
3407
3408 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
3409 cmd_buffer->state.last_primitive_reset_en = -1;
3410 cmd_buffer->state.last_index_type = -1;
3411 cmd_buffer->state.last_num_instances = -1;
3412 cmd_buffer->state.last_vertex_offset = -1;
3413 cmd_buffer->state.last_first_instance = -1;
3414 cmd_buffer->state.predication_type = -1;
3415 cmd_buffer->state.last_sx_ps_downconvert = -1;
3416 cmd_buffer->state.last_sx_blend_opt_epsilon = -1;
3417 cmd_buffer->state.last_sx_blend_opt_control = -1;
3418 cmd_buffer->usage_flags = pBeginInfo->flags;
3419
3420 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
3421 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
3422 assert(pBeginInfo->pInheritanceInfo);
3423 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
3424 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
3425
3426 struct radv_subpass *subpass =
3427 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
3428
3429 if (cmd_buffer->state.framebuffer) {
3430 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
3431 if (result != VK_SUCCESS)
3432 return result;
3433 }
3434
3435 cmd_buffer->state.inherited_pipeline_statistics =
3436 pBeginInfo->pInheritanceInfo->pipelineStatistics;
3437
3438 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3439 }
3440
3441 if (unlikely(cmd_buffer->device->trace_bo))
3442 radv_cmd_buffer_trace_emit(cmd_buffer);
3443
3444 radv_describe_begin_cmd_buffer(cmd_buffer);
3445
3446 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
3447
3448 return result;
3449 }
3450
3451 void radv_CmdBindVertexBuffers(
3452 VkCommandBuffer commandBuffer,
3453 uint32_t firstBinding,
3454 uint32_t bindingCount,
3455 const VkBuffer* pBuffers,
3456 const VkDeviceSize* pOffsets)
3457 {
3458 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3459 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
3460 bool changed = false;
3461
3462 /* We have to defer setting up vertex buffer since we need the buffer
3463 * stride from the pipeline. */
3464
3465 assert(firstBinding + bindingCount <= MAX_VBS);
3466 for (uint32_t i = 0; i < bindingCount; i++) {
3467 uint32_t idx = firstBinding + i;
3468
3469 if (!changed &&
3470 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
3471 vb[idx].offset != pOffsets[i])) {
3472 changed = true;
3473 }
3474
3475 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
3476 vb[idx].offset = pOffsets[i];
3477
3478 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3479 vb[idx].buffer->bo);
3480 }
3481
3482 if (!changed) {
3483 /* No state changes. */
3484 return;
3485 }
3486
3487 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
3488 }
3489
3490 static uint32_t
3491 vk_to_index_type(VkIndexType type)
3492 {
3493 switch (type) {
3494 case VK_INDEX_TYPE_UINT8_EXT:
3495 return V_028A7C_VGT_INDEX_8;
3496 case VK_INDEX_TYPE_UINT16:
3497 return V_028A7C_VGT_INDEX_16;
3498 case VK_INDEX_TYPE_UINT32:
3499 return V_028A7C_VGT_INDEX_32;
3500 default:
3501 unreachable("invalid index type");
3502 }
3503 }
3504
3505 static uint32_t
3506 radv_get_vgt_index_size(uint32_t type)
3507 {
3508 switch (type) {
3509 case V_028A7C_VGT_INDEX_8:
3510 return 1;
3511 case V_028A7C_VGT_INDEX_16:
3512 return 2;
3513 case V_028A7C_VGT_INDEX_32:
3514 return 4;
3515 default:
3516 unreachable("invalid index type");
3517 }
3518 }
3519
3520 void radv_CmdBindIndexBuffer(
3521 VkCommandBuffer commandBuffer,
3522 VkBuffer buffer,
3523 VkDeviceSize offset,
3524 VkIndexType indexType)
3525 {
3526 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3527 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
3528
3529 if (cmd_buffer->state.index_buffer == index_buffer &&
3530 cmd_buffer->state.index_offset == offset &&
3531 cmd_buffer->state.index_type == indexType) {
3532 /* No state changes. */
3533 return;
3534 }
3535
3536 cmd_buffer->state.index_buffer = index_buffer;
3537 cmd_buffer->state.index_offset = offset;
3538 cmd_buffer->state.index_type = vk_to_index_type(indexType);
3539 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
3540 cmd_buffer->state.index_va += index_buffer->offset + offset;
3541
3542 int index_size = radv_get_vgt_index_size(vk_to_index_type(indexType));
3543 cmd_buffer->state.max_index_count = (index_buffer->size - offset) / index_size;
3544 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3545 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
3546 }
3547
3548
3549 static void
3550 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3551 VkPipelineBindPoint bind_point,
3552 struct radv_descriptor_set *set, unsigned idx)
3553 {
3554 struct radeon_winsys *ws = cmd_buffer->device->ws;
3555
3556 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
3557
3558 assert(set);
3559 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
3560
3561 if (!cmd_buffer->device->use_global_bo_list) {
3562 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3563 if (set->descriptors[j])
3564 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
3565 }
3566
3567 if(set->bo)
3568 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
3569 }
3570
3571 void radv_CmdBindDescriptorSets(
3572 VkCommandBuffer commandBuffer,
3573 VkPipelineBindPoint pipelineBindPoint,
3574 VkPipelineLayout _layout,
3575 uint32_t firstSet,
3576 uint32_t descriptorSetCount,
3577 const VkDescriptorSet* pDescriptorSets,
3578 uint32_t dynamicOffsetCount,
3579 const uint32_t* pDynamicOffsets)
3580 {
3581 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3582 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3583 unsigned dyn_idx = 0;
3584
3585 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
3586 struct radv_descriptor_state *descriptors_state =
3587 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3588
3589 for (unsigned i = 0; i < descriptorSetCount; ++i) {
3590 unsigned idx = i + firstSet;
3591 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
3592
3593 /* If the set is already bound we only need to update the
3594 * (potentially changed) dynamic offsets. */
3595 if (descriptors_state->sets[idx] != set ||
3596 !(descriptors_state->valid & (1u << idx))) {
3597 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
3598 }
3599
3600 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
3601 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
3602 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
3603 assert(dyn_idx < dynamicOffsetCount);
3604
3605 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
3606 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
3607 dst[0] = va;
3608 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
3609 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
3610 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3611 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3612 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3613 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3614
3615 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
3616 dst[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3617 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3618 S_008F0C_RESOURCE_LEVEL(1);
3619 } else {
3620 dst[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3621 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3622 }
3623
3624 cmd_buffer->push_constant_stages |=
3625 set->layout->dynamic_shader_stages;
3626 }
3627 }
3628 }
3629
3630 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3631 struct radv_descriptor_set *set,
3632 struct radv_descriptor_set_layout *layout,
3633 VkPipelineBindPoint bind_point)
3634 {
3635 struct radv_descriptor_state *descriptors_state =
3636 radv_get_descriptors_state(cmd_buffer, bind_point);
3637 set->size = layout->size;
3638 set->layout = layout;
3639
3640 if (descriptors_state->push_set.capacity < set->size) {
3641 size_t new_size = MAX2(set->size, 1024);
3642 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
3643 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
3644
3645 free(set->mapped_ptr);
3646 set->mapped_ptr = malloc(new_size);
3647
3648 if (!set->mapped_ptr) {
3649 descriptors_state->push_set.capacity = 0;
3650 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3651 return false;
3652 }
3653
3654 descriptors_state->push_set.capacity = new_size;
3655 }
3656
3657 return true;
3658 }
3659
3660 void radv_meta_push_descriptor_set(
3661 struct radv_cmd_buffer* cmd_buffer,
3662 VkPipelineBindPoint pipelineBindPoint,
3663 VkPipelineLayout _layout,
3664 uint32_t set,
3665 uint32_t descriptorWriteCount,
3666 const VkWriteDescriptorSet* pDescriptorWrites)
3667 {
3668 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3669 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
3670 unsigned bo_offset;
3671
3672 assert(set == 0);
3673 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3674
3675 push_set->size = layout->set[set].layout->size;
3676 push_set->layout = layout->set[set].layout;
3677
3678 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
3679 &bo_offset,
3680 (void**) &push_set->mapped_ptr))
3681 return;
3682
3683 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
3684 push_set->va += bo_offset;
3685
3686 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3687 radv_descriptor_set_to_handle(push_set),
3688 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3689
3690 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3691 }
3692
3693 void radv_CmdPushDescriptorSetKHR(
3694 VkCommandBuffer commandBuffer,
3695 VkPipelineBindPoint pipelineBindPoint,
3696 VkPipelineLayout _layout,
3697 uint32_t set,
3698 uint32_t descriptorWriteCount,
3699 const VkWriteDescriptorSet* pDescriptorWrites)
3700 {
3701 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3702 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3703 struct radv_descriptor_state *descriptors_state =
3704 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3705 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3706
3707 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3708
3709 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3710 layout->set[set].layout,
3711 pipelineBindPoint))
3712 return;
3713
3714 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3715 * because it is invalid, according to Vulkan spec.
3716 */
3717 for (int i = 0; i < descriptorWriteCount; i++) {
3718 ASSERTED const VkWriteDescriptorSet *writeset = &pDescriptorWrites[i];
3719 assert(writeset->descriptorType != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT);
3720 }
3721
3722 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3723 radv_descriptor_set_to_handle(push_set),
3724 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3725
3726 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3727 descriptors_state->push_dirty = true;
3728 }
3729
3730 void radv_CmdPushDescriptorSetWithTemplateKHR(
3731 VkCommandBuffer commandBuffer,
3732 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
3733 VkPipelineLayout _layout,
3734 uint32_t set,
3735 const void* pData)
3736 {
3737 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3738 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3739 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
3740 struct radv_descriptor_state *descriptors_state =
3741 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
3742 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3743
3744 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3745
3746 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3747 layout->set[set].layout,
3748 templ->bind_point))
3749 return;
3750
3751 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
3752 descriptorUpdateTemplate, pData);
3753
3754 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
3755 descriptors_state->push_dirty = true;
3756 }
3757
3758 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
3759 VkPipelineLayout layout,
3760 VkShaderStageFlags stageFlags,
3761 uint32_t offset,
3762 uint32_t size,
3763 const void* pValues)
3764 {
3765 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3766 memcpy(cmd_buffer->push_constants + offset, pValues, size);
3767 cmd_buffer->push_constant_stages |= stageFlags;
3768 }
3769
3770 VkResult radv_EndCommandBuffer(
3771 VkCommandBuffer commandBuffer)
3772 {
3773 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3774
3775 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
3776 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6)
3777 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WB_L2;
3778
3779 /* Make sure to sync all pending active queries at the end of
3780 * command buffer.
3781 */
3782 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
3783
3784 /* Since NGG streamout uses GDS, we need to make GDS idle when
3785 * we leave the IB, otherwise another process might overwrite
3786 * it while our shaders are busy.
3787 */
3788 if (cmd_buffer->gds_needed)
3789 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
3790
3791 si_emit_cache_flush(cmd_buffer);
3792 }
3793
3794 /* Make sure CP DMA is idle at the end of IBs because the kernel
3795 * doesn't wait for it.
3796 */
3797 si_cp_dma_wait_for_idle(cmd_buffer);
3798
3799 radv_describe_end_cmd_buffer(cmd_buffer);
3800
3801 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3802 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
3803
3804 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
3805 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3806
3807 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
3808
3809 return cmd_buffer->record_result;
3810 }
3811
3812 static void
3813 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
3814 {
3815 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3816
3817 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
3818 return;
3819
3820 assert(!pipeline->ctx_cs.cdw);
3821
3822 cmd_buffer->state.emitted_compute_pipeline = pipeline;
3823
3824 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
3825 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
3826
3827 cmd_buffer->compute_scratch_size_per_wave_needed = MAX2(cmd_buffer->compute_scratch_size_per_wave_needed,
3828 pipeline->scratch_bytes_per_wave);
3829 cmd_buffer->compute_scratch_waves_wanted = MAX2(cmd_buffer->compute_scratch_waves_wanted,
3830 pipeline->max_waves);
3831
3832 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3833 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
3834
3835 if (unlikely(cmd_buffer->device->trace_bo))
3836 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
3837 }
3838
3839 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
3840 VkPipelineBindPoint bind_point)
3841 {
3842 struct radv_descriptor_state *descriptors_state =
3843 radv_get_descriptors_state(cmd_buffer, bind_point);
3844
3845 descriptors_state->dirty |= descriptors_state->valid;
3846 }
3847
3848 void radv_CmdBindPipeline(
3849 VkCommandBuffer commandBuffer,
3850 VkPipelineBindPoint pipelineBindPoint,
3851 VkPipeline _pipeline)
3852 {
3853 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3854 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
3855
3856 switch (pipelineBindPoint) {
3857 case VK_PIPELINE_BIND_POINT_COMPUTE:
3858 if (cmd_buffer->state.compute_pipeline == pipeline)
3859 return;
3860 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3861
3862 cmd_buffer->state.compute_pipeline = pipeline;
3863 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
3864 break;
3865 case VK_PIPELINE_BIND_POINT_GRAPHICS:
3866 if (cmd_buffer->state.pipeline == pipeline)
3867 return;
3868 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3869
3870 cmd_buffer->state.pipeline = pipeline;
3871 if (!pipeline)
3872 break;
3873
3874 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
3875 cmd_buffer->push_constant_stages |= pipeline->active_stages;
3876
3877 /* the new vertex shader might not have the same user regs */
3878 cmd_buffer->state.last_first_instance = -1;
3879 cmd_buffer->state.last_vertex_offset = -1;
3880
3881 /* Prefetch all pipeline shaders at first draw time. */
3882 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
3883
3884 if ((cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI10 ||
3885 cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI12 ||
3886 cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI14) &&
3887 cmd_buffer->state.emitted_pipeline &&
3888 radv_pipeline_has_ngg(cmd_buffer->state.emitted_pipeline) &&
3889 !radv_pipeline_has_ngg(cmd_buffer->state.pipeline)) {
3890 /* Transitioning from NGG to legacy GS requires
3891 * VGT_FLUSH on Navi10-14. VGT_FLUSH is also emitted
3892 * at the beginning of IBs when legacy GS ring pointers
3893 * are set.
3894 */
3895 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
3896 }
3897
3898 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
3899 radv_bind_streamout_state(cmd_buffer, pipeline);
3900
3901 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
3902 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
3903 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
3904 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
3905
3906 if (radv_pipeline_has_tess(pipeline))
3907 cmd_buffer->tess_rings_needed = true;
3908 break;
3909 default:
3910 assert(!"invalid bind point");
3911 break;
3912 }
3913 }
3914
3915 void radv_CmdSetViewport(
3916 VkCommandBuffer commandBuffer,
3917 uint32_t firstViewport,
3918 uint32_t viewportCount,
3919 const VkViewport* pViewports)
3920 {
3921 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3922 struct radv_cmd_state *state = &cmd_buffer->state;
3923 ASSERTED const uint32_t total_count = firstViewport + viewportCount;
3924
3925 assert(firstViewport < MAX_VIEWPORTS);
3926 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
3927
3928 if (!memcmp(state->dynamic.viewport.viewports + firstViewport,
3929 pViewports, viewportCount * sizeof(*pViewports))) {
3930 return;
3931 }
3932
3933 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
3934 viewportCount * sizeof(*pViewports));
3935
3936 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
3937 }
3938
3939 void radv_CmdSetScissor(
3940 VkCommandBuffer commandBuffer,
3941 uint32_t firstScissor,
3942 uint32_t scissorCount,
3943 const VkRect2D* pScissors)
3944 {
3945 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3946 struct radv_cmd_state *state = &cmd_buffer->state;
3947 ASSERTED const uint32_t total_count = firstScissor + scissorCount;
3948
3949 assert(firstScissor < MAX_SCISSORS);
3950 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
3951
3952 if (!memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
3953 scissorCount * sizeof(*pScissors))) {
3954 return;
3955 }
3956
3957 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
3958 scissorCount * sizeof(*pScissors));
3959
3960 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
3961 }
3962
3963 void radv_CmdSetLineWidth(
3964 VkCommandBuffer commandBuffer,
3965 float lineWidth)
3966 {
3967 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3968
3969 if (cmd_buffer->state.dynamic.line_width == lineWidth)
3970 return;
3971
3972 cmd_buffer->state.dynamic.line_width = lineWidth;
3973 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
3974 }
3975
3976 void radv_CmdSetDepthBias(
3977 VkCommandBuffer commandBuffer,
3978 float depthBiasConstantFactor,
3979 float depthBiasClamp,
3980 float depthBiasSlopeFactor)
3981 {
3982 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3983 struct radv_cmd_state *state = &cmd_buffer->state;
3984
3985 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
3986 state->dynamic.depth_bias.clamp == depthBiasClamp &&
3987 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
3988 return;
3989 }
3990
3991 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
3992 state->dynamic.depth_bias.clamp = depthBiasClamp;
3993 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
3994
3995 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
3996 }
3997
3998 void radv_CmdSetBlendConstants(
3999 VkCommandBuffer commandBuffer,
4000 const float blendConstants[4])
4001 {
4002 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4003 struct radv_cmd_state *state = &cmd_buffer->state;
4004
4005 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
4006 return;
4007
4008 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
4009
4010 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
4011 }
4012
4013 void radv_CmdSetDepthBounds(
4014 VkCommandBuffer commandBuffer,
4015 float minDepthBounds,
4016 float maxDepthBounds)
4017 {
4018 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4019 struct radv_cmd_state *state = &cmd_buffer->state;
4020
4021 if (state->dynamic.depth_bounds.min == minDepthBounds &&
4022 state->dynamic.depth_bounds.max == maxDepthBounds) {
4023 return;
4024 }
4025
4026 state->dynamic.depth_bounds.min = minDepthBounds;
4027 state->dynamic.depth_bounds.max = maxDepthBounds;
4028
4029 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
4030 }
4031
4032 void radv_CmdSetStencilCompareMask(
4033 VkCommandBuffer commandBuffer,
4034 VkStencilFaceFlags faceMask,
4035 uint32_t compareMask)
4036 {
4037 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4038 struct radv_cmd_state *state = &cmd_buffer->state;
4039 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
4040 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
4041
4042 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4043 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4044 return;
4045 }
4046
4047 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4048 state->dynamic.stencil_compare_mask.front = compareMask;
4049 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4050 state->dynamic.stencil_compare_mask.back = compareMask;
4051
4052 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
4053 }
4054
4055 void radv_CmdSetStencilWriteMask(
4056 VkCommandBuffer commandBuffer,
4057 VkStencilFaceFlags faceMask,
4058 uint32_t writeMask)
4059 {
4060 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4061 struct radv_cmd_state *state = &cmd_buffer->state;
4062 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
4063 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
4064
4065 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4066 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4067 return;
4068 }
4069
4070 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4071 state->dynamic.stencil_write_mask.front = writeMask;
4072 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4073 state->dynamic.stencil_write_mask.back = writeMask;
4074
4075 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
4076 }
4077
4078 void radv_CmdSetStencilReference(
4079 VkCommandBuffer commandBuffer,
4080 VkStencilFaceFlags faceMask,
4081 uint32_t reference)
4082 {
4083 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4084 struct radv_cmd_state *state = &cmd_buffer->state;
4085 bool front_same = state->dynamic.stencil_reference.front == reference;
4086 bool back_same = state->dynamic.stencil_reference.back == reference;
4087
4088 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4089 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4090 return;
4091 }
4092
4093 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4094 cmd_buffer->state.dynamic.stencil_reference.front = reference;
4095 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4096 cmd_buffer->state.dynamic.stencil_reference.back = reference;
4097
4098 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
4099 }
4100
4101 void radv_CmdSetDiscardRectangleEXT(
4102 VkCommandBuffer commandBuffer,
4103 uint32_t firstDiscardRectangle,
4104 uint32_t discardRectangleCount,
4105 const VkRect2D* pDiscardRectangles)
4106 {
4107 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4108 struct radv_cmd_state *state = &cmd_buffer->state;
4109 ASSERTED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
4110
4111 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
4112 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
4113
4114 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
4115 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
4116 return;
4117 }
4118
4119 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
4120 pDiscardRectangles, discardRectangleCount);
4121
4122 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
4123 }
4124
4125 void radv_CmdSetSampleLocationsEXT(
4126 VkCommandBuffer commandBuffer,
4127 const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
4128 {
4129 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4130 struct radv_cmd_state *state = &cmd_buffer->state;
4131
4132 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
4133
4134 state->dynamic.sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
4135 state->dynamic.sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
4136 state->dynamic.sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
4137 typed_memcpy(&state->dynamic.sample_location.locations[0],
4138 pSampleLocationsInfo->pSampleLocations,
4139 pSampleLocationsInfo->sampleLocationsCount);
4140
4141 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS;
4142 }
4143
4144 void radv_CmdSetLineStippleEXT(
4145 VkCommandBuffer commandBuffer,
4146 uint32_t lineStippleFactor,
4147 uint16_t lineStipplePattern)
4148 {
4149 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4150 struct radv_cmd_state *state = &cmd_buffer->state;
4151
4152 state->dynamic.line_stipple.factor = lineStippleFactor;
4153 state->dynamic.line_stipple.pattern = lineStipplePattern;
4154
4155 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE;
4156 }
4157
4158 void radv_CmdExecuteCommands(
4159 VkCommandBuffer commandBuffer,
4160 uint32_t commandBufferCount,
4161 const VkCommandBuffer* pCmdBuffers)
4162 {
4163 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
4164
4165 assert(commandBufferCount > 0);
4166
4167 /* Emit pending flushes on primary prior to executing secondary */
4168 si_emit_cache_flush(primary);
4169
4170 for (uint32_t i = 0; i < commandBufferCount; i++) {
4171 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
4172
4173 primary->scratch_size_per_wave_needed = MAX2(primary->scratch_size_per_wave_needed,
4174 secondary->scratch_size_per_wave_needed);
4175 primary->scratch_waves_wanted = MAX2(primary->scratch_waves_wanted,
4176 secondary->scratch_waves_wanted);
4177 primary->compute_scratch_size_per_wave_needed = MAX2(primary->compute_scratch_size_per_wave_needed,
4178 secondary->compute_scratch_size_per_wave_needed);
4179 primary->compute_scratch_waves_wanted = MAX2(primary->compute_scratch_waves_wanted,
4180 secondary->compute_scratch_waves_wanted);
4181
4182 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
4183 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
4184 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
4185 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
4186 if (secondary->tess_rings_needed)
4187 primary->tess_rings_needed = true;
4188 if (secondary->sample_positions_needed)
4189 primary->sample_positions_needed = true;
4190 if (secondary->gds_needed)
4191 primary->gds_needed = true;
4192
4193 if (!secondary->state.framebuffer &&
4194 (primary->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)) {
4195 /* Emit the framebuffer state from primary if secondary
4196 * has been recorded without a framebuffer, otherwise
4197 * fast color/depth clears can't work.
4198 */
4199 radv_emit_framebuffer_state(primary);
4200 }
4201
4202 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
4203
4204
4205 /* When the secondary command buffer is compute only we don't
4206 * need to re-emit the current graphics pipeline.
4207 */
4208 if (secondary->state.emitted_pipeline) {
4209 primary->state.emitted_pipeline =
4210 secondary->state.emitted_pipeline;
4211 }
4212
4213 /* When the secondary command buffer is graphics only we don't
4214 * need to re-emit the current compute pipeline.
4215 */
4216 if (secondary->state.emitted_compute_pipeline) {
4217 primary->state.emitted_compute_pipeline =
4218 secondary->state.emitted_compute_pipeline;
4219 }
4220
4221 /* Only re-emit the draw packets when needed. */
4222 if (secondary->state.last_primitive_reset_en != -1) {
4223 primary->state.last_primitive_reset_en =
4224 secondary->state.last_primitive_reset_en;
4225 }
4226
4227 if (secondary->state.last_primitive_reset_index) {
4228 primary->state.last_primitive_reset_index =
4229 secondary->state.last_primitive_reset_index;
4230 }
4231
4232 if (secondary->state.last_ia_multi_vgt_param) {
4233 primary->state.last_ia_multi_vgt_param =
4234 secondary->state.last_ia_multi_vgt_param;
4235 }
4236
4237 primary->state.last_first_instance = secondary->state.last_first_instance;
4238 primary->state.last_num_instances = secondary->state.last_num_instances;
4239 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
4240 primary->state.last_sx_ps_downconvert = secondary->state.last_sx_ps_downconvert;
4241 primary->state.last_sx_blend_opt_epsilon = secondary->state.last_sx_blend_opt_epsilon;
4242 primary->state.last_sx_blend_opt_control = secondary->state.last_sx_blend_opt_control;
4243
4244 if (secondary->state.last_index_type != -1) {
4245 primary->state.last_index_type =
4246 secondary->state.last_index_type;
4247 }
4248 }
4249
4250 /* After executing commands from secondary buffers we have to dirty
4251 * some states.
4252 */
4253 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
4254 RADV_CMD_DIRTY_INDEX_BUFFER |
4255 RADV_CMD_DIRTY_DYNAMIC_ALL;
4256 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
4257 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
4258 }
4259
4260 VkResult radv_CreateCommandPool(
4261 VkDevice _device,
4262 const VkCommandPoolCreateInfo* pCreateInfo,
4263 const VkAllocationCallbacks* pAllocator,
4264 VkCommandPool* pCmdPool)
4265 {
4266 RADV_FROM_HANDLE(radv_device, device, _device);
4267 struct radv_cmd_pool *pool;
4268
4269 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
4270 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4271 if (pool == NULL)
4272 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4273
4274 if (pAllocator)
4275 pool->alloc = *pAllocator;
4276 else
4277 pool->alloc = device->alloc;
4278
4279 list_inithead(&pool->cmd_buffers);
4280 list_inithead(&pool->free_cmd_buffers);
4281
4282 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
4283
4284 *pCmdPool = radv_cmd_pool_to_handle(pool);
4285
4286 return VK_SUCCESS;
4287
4288 }
4289
4290 void radv_DestroyCommandPool(
4291 VkDevice _device,
4292 VkCommandPool commandPool,
4293 const VkAllocationCallbacks* pAllocator)
4294 {
4295 RADV_FROM_HANDLE(radv_device, device, _device);
4296 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4297
4298 if (!pool)
4299 return;
4300
4301 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4302 &pool->cmd_buffers, pool_link) {
4303 radv_cmd_buffer_destroy(cmd_buffer);
4304 }
4305
4306 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4307 &pool->free_cmd_buffers, pool_link) {
4308 radv_cmd_buffer_destroy(cmd_buffer);
4309 }
4310
4311 vk_free2(&device->alloc, pAllocator, pool);
4312 }
4313
4314 VkResult radv_ResetCommandPool(
4315 VkDevice device,
4316 VkCommandPool commandPool,
4317 VkCommandPoolResetFlags flags)
4318 {
4319 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4320 VkResult result;
4321
4322 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
4323 &pool->cmd_buffers, pool_link) {
4324 result = radv_reset_cmd_buffer(cmd_buffer);
4325 if (result != VK_SUCCESS)
4326 return result;
4327 }
4328
4329 return VK_SUCCESS;
4330 }
4331
4332 void radv_TrimCommandPool(
4333 VkDevice device,
4334 VkCommandPool commandPool,
4335 VkCommandPoolTrimFlags flags)
4336 {
4337 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4338
4339 if (!pool)
4340 return;
4341
4342 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4343 &pool->free_cmd_buffers, pool_link) {
4344 radv_cmd_buffer_destroy(cmd_buffer);
4345 }
4346 }
4347
4348 static void
4349 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
4350 uint32_t subpass_id)
4351 {
4352 struct radv_cmd_state *state = &cmd_buffer->state;
4353 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
4354
4355 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
4356 cmd_buffer->cs, 4096);
4357
4358 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
4359
4360 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
4361
4362 radv_describe_barrier_start(cmd_buffer, RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC);
4363
4364 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4365 const uint32_t a = subpass->attachments[i].attachment;
4366 if (a == VK_ATTACHMENT_UNUSED)
4367 continue;
4368
4369 radv_handle_subpass_image_transition(cmd_buffer,
4370 subpass->attachments[i],
4371 true);
4372 }
4373
4374 radv_describe_barrier_end(cmd_buffer);
4375
4376 radv_cmd_buffer_clear_subpass(cmd_buffer);
4377
4378 assert(cmd_buffer->cs->cdw <= cdw_max);
4379 }
4380
4381 static void
4382 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
4383 {
4384 struct radv_cmd_state *state = &cmd_buffer->state;
4385 const struct radv_subpass *subpass = state->subpass;
4386 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
4387
4388 radv_cmd_buffer_resolve_subpass(cmd_buffer);
4389
4390 radv_describe_barrier_start(cmd_buffer, RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC);
4391
4392 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4393 const uint32_t a = subpass->attachments[i].attachment;
4394 if (a == VK_ATTACHMENT_UNUSED)
4395 continue;
4396
4397 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
4398 continue;
4399
4400 VkImageLayout layout = state->pass->attachments[a].final_layout;
4401 VkImageLayout stencil_layout = state->pass->attachments[a].stencil_final_layout;
4402 struct radv_subpass_attachment att = { a, layout, stencil_layout };
4403 radv_handle_subpass_image_transition(cmd_buffer, att, false);
4404 }
4405
4406 radv_describe_barrier_end(cmd_buffer);
4407 }
4408
4409 void
4410 radv_cmd_buffer_begin_render_pass(struct radv_cmd_buffer *cmd_buffer,
4411 const VkRenderPassBeginInfo *pRenderPassBegin)
4412 {
4413 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
4414 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
4415 VkResult result;
4416
4417 cmd_buffer->state.framebuffer = framebuffer;
4418 cmd_buffer->state.pass = pass;
4419 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
4420
4421 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
4422 if (result != VK_SUCCESS)
4423 return;
4424
4425 result = radv_cmd_state_setup_sample_locations(cmd_buffer, pass, pRenderPassBegin);
4426 if (result != VK_SUCCESS)
4427 return;
4428 }
4429
4430 void radv_CmdBeginRenderPass(
4431 VkCommandBuffer commandBuffer,
4432 const VkRenderPassBeginInfo* pRenderPassBegin,
4433 VkSubpassContents contents)
4434 {
4435 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4436
4437 radv_cmd_buffer_begin_render_pass(cmd_buffer, pRenderPassBegin);
4438
4439 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
4440 }
4441
4442 void radv_CmdBeginRenderPass2(
4443 VkCommandBuffer commandBuffer,
4444 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
4445 const VkSubpassBeginInfo* pSubpassBeginInfo)
4446 {
4447 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
4448 pSubpassBeginInfo->contents);
4449 }
4450
4451 void radv_CmdNextSubpass(
4452 VkCommandBuffer commandBuffer,
4453 VkSubpassContents contents)
4454 {
4455 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4456
4457 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
4458 radv_cmd_buffer_end_subpass(cmd_buffer);
4459 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
4460 }
4461
4462 void radv_CmdNextSubpass2(
4463 VkCommandBuffer commandBuffer,
4464 const VkSubpassBeginInfo* pSubpassBeginInfo,
4465 const VkSubpassEndInfo* pSubpassEndInfo)
4466 {
4467 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
4468 }
4469
4470 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
4471 {
4472 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
4473 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
4474 if (!radv_get_shader(pipeline, stage))
4475 continue;
4476
4477 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
4478 if (loc->sgpr_idx == -1)
4479 continue;
4480 uint32_t base_reg = pipeline->user_data_0[stage];
4481 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4482
4483 }
4484 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
4485 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
4486 if (loc->sgpr_idx != -1) {
4487 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
4488 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4489 }
4490 }
4491 }
4492
4493 static void
4494 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4495 uint32_t vertex_count,
4496 bool use_opaque)
4497 {
4498 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
4499 radeon_emit(cmd_buffer->cs, vertex_count);
4500 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
4501 S_0287F0_USE_OPAQUE(use_opaque));
4502 }
4503
4504 static void
4505 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
4506 uint64_t index_va,
4507 uint32_t index_count)
4508 {
4509 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
4510 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
4511 radeon_emit(cmd_buffer->cs, index_va);
4512 radeon_emit(cmd_buffer->cs, index_va >> 32);
4513 radeon_emit(cmd_buffer->cs, index_count);
4514 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
4515 }
4516
4517 static void
4518 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4519 bool indexed,
4520 uint32_t draw_count,
4521 uint64_t count_va,
4522 uint32_t stride)
4523 {
4524 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4525 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
4526 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
4527 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id;
4528 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
4529 bool predicating = cmd_buffer->state.predicating;
4530 assert(base_reg);
4531
4532 /* just reset draw state for vertex data */
4533 cmd_buffer->state.last_first_instance = -1;
4534 cmd_buffer->state.last_num_instances = -1;
4535 cmd_buffer->state.last_vertex_offset = -1;
4536
4537 if (draw_count == 1 && !count_va && !draw_id_enable) {
4538 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
4539 PKT3_DRAW_INDIRECT, 3, predicating));
4540 radeon_emit(cs, 0);
4541 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4542 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4543 radeon_emit(cs, di_src_sel);
4544 } else {
4545 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
4546 PKT3_DRAW_INDIRECT_MULTI,
4547 8, predicating));
4548 radeon_emit(cs, 0);
4549 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4550 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4551 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
4552 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
4553 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
4554 radeon_emit(cs, draw_count); /* count */
4555 radeon_emit(cs, count_va); /* count_addr */
4556 radeon_emit(cs, count_va >> 32);
4557 radeon_emit(cs, stride); /* stride */
4558 radeon_emit(cs, di_src_sel);
4559 }
4560 }
4561
4562 static void
4563 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
4564 const struct radv_draw_info *info)
4565 {
4566 struct radv_cmd_state *state = &cmd_buffer->state;
4567 struct radeon_winsys *ws = cmd_buffer->device->ws;
4568 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4569
4570 if (info->indirect) {
4571 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4572 uint64_t count_va = 0;
4573
4574 va += info->indirect->offset + info->indirect_offset;
4575
4576 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4577
4578 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
4579 radeon_emit(cs, 1);
4580 radeon_emit(cs, va);
4581 radeon_emit(cs, va >> 32);
4582
4583 if (info->count_buffer) {
4584 count_va = radv_buffer_get_va(info->count_buffer->bo);
4585 count_va += info->count_buffer->offset +
4586 info->count_buffer_offset;
4587
4588 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
4589 }
4590
4591 if (!state->subpass->view_mask) {
4592 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4593 info->indexed,
4594 info->count,
4595 count_va,
4596 info->stride);
4597 } else {
4598 unsigned i;
4599 for_each_bit(i, state->subpass->view_mask) {
4600 radv_emit_view_index(cmd_buffer, i);
4601
4602 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4603 info->indexed,
4604 info->count,
4605 count_va,
4606 info->stride);
4607 }
4608 }
4609 } else {
4610 assert(state->pipeline->graphics.vtx_base_sgpr);
4611
4612 if (info->vertex_offset != state->last_vertex_offset ||
4613 info->first_instance != state->last_first_instance) {
4614 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
4615 state->pipeline->graphics.vtx_emit_num);
4616
4617 radeon_emit(cs, info->vertex_offset);
4618 radeon_emit(cs, info->first_instance);
4619 if (state->pipeline->graphics.vtx_emit_num == 3)
4620 radeon_emit(cs, 0);
4621 state->last_first_instance = info->first_instance;
4622 state->last_vertex_offset = info->vertex_offset;
4623 }
4624
4625 if (state->last_num_instances != info->instance_count) {
4626 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
4627 radeon_emit(cs, info->instance_count);
4628 state->last_num_instances = info->instance_count;
4629 }
4630
4631 if (info->indexed) {
4632 int index_size = radv_get_vgt_index_size(state->index_type);
4633 uint64_t index_va;
4634
4635 /* Skip draw calls with 0-sized index buffers. They
4636 * cause a hang on some chips, like Navi10-14.
4637 */
4638 if (!cmd_buffer->state.max_index_count)
4639 return;
4640
4641 index_va = state->index_va;
4642 index_va += info->first_index * index_size;
4643
4644 if (!state->subpass->view_mask) {
4645 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4646 index_va,
4647 info->count);
4648 } else {
4649 unsigned i;
4650 for_each_bit(i, state->subpass->view_mask) {
4651 radv_emit_view_index(cmd_buffer, i);
4652
4653 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4654 index_va,
4655 info->count);
4656 }
4657 }
4658 } else {
4659 if (!state->subpass->view_mask) {
4660 radv_cs_emit_draw_packet(cmd_buffer,
4661 info->count,
4662 !!info->strmout_buffer);
4663 } else {
4664 unsigned i;
4665 for_each_bit(i, state->subpass->view_mask) {
4666 radv_emit_view_index(cmd_buffer, i);
4667
4668 radv_cs_emit_draw_packet(cmd_buffer,
4669 info->count,
4670 !!info->strmout_buffer);
4671 }
4672 }
4673 }
4674 }
4675 }
4676
4677 /*
4678 * Vega and raven have a bug which triggers if there are multiple context
4679 * register contexts active at the same time with different scissor values.
4680 *
4681 * There are two possible workarounds:
4682 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
4683 * there is only ever 1 active set of scissor values at the same time.
4684 *
4685 * 2) Whenever the hardware switches contexts we have to set the scissor
4686 * registers again even if it is a noop. That way the new context gets
4687 * the correct scissor values.
4688 *
4689 * This implements option 2. radv_need_late_scissor_emission needs to
4690 * return true on affected HW if radv_emit_all_graphics_states sets
4691 * any context registers.
4692 */
4693 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
4694 const struct radv_draw_info *info)
4695 {
4696 struct radv_cmd_state *state = &cmd_buffer->state;
4697
4698 if (!cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
4699 return false;
4700
4701 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
4702 return true;
4703
4704 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
4705
4706 /* Index, vertex and streamout buffers don't change context regs, and
4707 * pipeline is already handled.
4708 */
4709 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
4710 RADV_CMD_DIRTY_VERTEX_BUFFER |
4711 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
4712 RADV_CMD_DIRTY_PIPELINE);
4713
4714 if (cmd_buffer->state.dirty & used_states)
4715 return true;
4716
4717 uint32_t primitive_reset_index =
4718 radv_get_primitive_reset_index(cmd_buffer);
4719
4720 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
4721 primitive_reset_index != state->last_primitive_reset_index)
4722 return true;
4723
4724 return false;
4725 }
4726
4727 static void
4728 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
4729 const struct radv_draw_info *info)
4730 {
4731 bool late_scissor_emission;
4732
4733 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
4734 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
4735 radv_emit_rbplus_state(cmd_buffer);
4736
4737 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
4738 radv_emit_graphics_pipeline(cmd_buffer);
4739
4740 /* This should be before the cmd_buffer->state.dirty is cleared
4741 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4742 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4743 late_scissor_emission =
4744 radv_need_late_scissor_emission(cmd_buffer, info);
4745
4746 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
4747 radv_emit_framebuffer_state(cmd_buffer);
4748
4749 if (info->indexed) {
4750 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
4751 radv_emit_index_buffer(cmd_buffer, info->indirect);
4752 } else {
4753 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4754 * so the state must be re-emitted before the next indexed
4755 * draw.
4756 */
4757 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
4758 cmd_buffer->state.last_index_type = -1;
4759 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
4760 }
4761 }
4762
4763 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
4764
4765 radv_emit_draw_registers(cmd_buffer, info);
4766
4767 if (late_scissor_emission)
4768 radv_emit_scissor(cmd_buffer);
4769 }
4770
4771 static void
4772 radv_draw(struct radv_cmd_buffer *cmd_buffer,
4773 const struct radv_draw_info *info)
4774 {
4775 struct radeon_info *rad_info =
4776 &cmd_buffer->device->physical_device->rad_info;
4777 bool has_prefetch =
4778 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4779 bool pipeline_is_dirty =
4780 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
4781 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
4782
4783 ASSERTED unsigned cdw_max =
4784 radeon_check_space(cmd_buffer->device->ws,
4785 cmd_buffer->cs, 4096);
4786
4787 if (likely(!info->indirect)) {
4788 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4789 * no workaround for indirect draws, but we can at least skip
4790 * direct draws.
4791 */
4792 if (unlikely(!info->instance_count))
4793 return;
4794
4795 /* Handle count == 0. */
4796 if (unlikely(!info->count && !info->strmout_buffer))
4797 return;
4798 }
4799
4800 radv_describe_draw(cmd_buffer);
4801
4802 /* Use optimal packet order based on whether we need to sync the
4803 * pipeline.
4804 */
4805 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4806 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4807 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4808 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4809 /* If we have to wait for idle, set all states first, so that
4810 * all SET packets are processed in parallel with previous draw
4811 * calls. Then upload descriptors, set shader pointers, and
4812 * draw, and prefetch at the end. This ensures that the time
4813 * the CUs are idle is very short. (there are only SET_SH
4814 * packets between the wait and the draw)
4815 */
4816 radv_emit_all_graphics_states(cmd_buffer, info);
4817 si_emit_cache_flush(cmd_buffer);
4818 /* <-- CUs are idle here --> */
4819
4820 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4821
4822 radv_emit_draw_packets(cmd_buffer, info);
4823 /* <-- CUs are busy here --> */
4824
4825 /* Start prefetches after the draw has been started. Both will
4826 * run in parallel, but starting the draw first is more
4827 * important.
4828 */
4829 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4830 radv_emit_prefetch_L2(cmd_buffer,
4831 cmd_buffer->state.pipeline, false);
4832 }
4833 } else {
4834 /* If we don't wait for idle, start prefetches first, then set
4835 * states, and draw at the end.
4836 */
4837 si_emit_cache_flush(cmd_buffer);
4838
4839 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4840 /* Only prefetch the vertex shader and VBO descriptors
4841 * in order to start the draw as soon as possible.
4842 */
4843 radv_emit_prefetch_L2(cmd_buffer,
4844 cmd_buffer->state.pipeline, true);
4845 }
4846
4847 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4848
4849 radv_emit_all_graphics_states(cmd_buffer, info);
4850 radv_emit_draw_packets(cmd_buffer, info);
4851
4852 /* Prefetch the remaining shaders after the draw has been
4853 * started.
4854 */
4855 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4856 radv_emit_prefetch_L2(cmd_buffer,
4857 cmd_buffer->state.pipeline, false);
4858 }
4859 }
4860
4861 /* Workaround for a VGT hang when streamout is enabled.
4862 * It must be done after drawing.
4863 */
4864 if (cmd_buffer->state.streamout.streamout_enabled &&
4865 (rad_info->family == CHIP_HAWAII ||
4866 rad_info->family == CHIP_TONGA ||
4867 rad_info->family == CHIP_FIJI)) {
4868 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
4869 }
4870
4871 assert(cmd_buffer->cs->cdw <= cdw_max);
4872 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
4873 }
4874
4875 void radv_CmdDraw(
4876 VkCommandBuffer commandBuffer,
4877 uint32_t vertexCount,
4878 uint32_t instanceCount,
4879 uint32_t firstVertex,
4880 uint32_t firstInstance)
4881 {
4882 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4883 struct radv_draw_info info = {};
4884
4885 info.count = vertexCount;
4886 info.instance_count = instanceCount;
4887 info.first_instance = firstInstance;
4888 info.vertex_offset = firstVertex;
4889
4890 radv_draw(cmd_buffer, &info);
4891 }
4892
4893 void radv_CmdDrawIndexed(
4894 VkCommandBuffer commandBuffer,
4895 uint32_t indexCount,
4896 uint32_t instanceCount,
4897 uint32_t firstIndex,
4898 int32_t vertexOffset,
4899 uint32_t firstInstance)
4900 {
4901 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4902 struct radv_draw_info info = {};
4903
4904 info.indexed = true;
4905 info.count = indexCount;
4906 info.instance_count = instanceCount;
4907 info.first_index = firstIndex;
4908 info.vertex_offset = vertexOffset;
4909 info.first_instance = firstInstance;
4910
4911 radv_draw(cmd_buffer, &info);
4912 }
4913
4914 void radv_CmdDrawIndirect(
4915 VkCommandBuffer commandBuffer,
4916 VkBuffer _buffer,
4917 VkDeviceSize offset,
4918 uint32_t drawCount,
4919 uint32_t stride)
4920 {
4921 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4922 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4923 struct radv_draw_info info = {};
4924
4925 info.count = drawCount;
4926 info.indirect = buffer;
4927 info.indirect_offset = offset;
4928 info.stride = stride;
4929
4930 radv_draw(cmd_buffer, &info);
4931 }
4932
4933 void radv_CmdDrawIndexedIndirect(
4934 VkCommandBuffer commandBuffer,
4935 VkBuffer _buffer,
4936 VkDeviceSize offset,
4937 uint32_t drawCount,
4938 uint32_t stride)
4939 {
4940 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4941 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4942 struct radv_draw_info info = {};
4943
4944 info.indexed = true;
4945 info.count = drawCount;
4946 info.indirect = buffer;
4947 info.indirect_offset = offset;
4948 info.stride = stride;
4949
4950 radv_draw(cmd_buffer, &info);
4951 }
4952
4953 void radv_CmdDrawIndirectCount(
4954 VkCommandBuffer commandBuffer,
4955 VkBuffer _buffer,
4956 VkDeviceSize offset,
4957 VkBuffer _countBuffer,
4958 VkDeviceSize countBufferOffset,
4959 uint32_t maxDrawCount,
4960 uint32_t stride)
4961 {
4962 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4963 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4964 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4965 struct radv_draw_info info = {};
4966
4967 info.count = maxDrawCount;
4968 info.indirect = buffer;
4969 info.indirect_offset = offset;
4970 info.count_buffer = count_buffer;
4971 info.count_buffer_offset = countBufferOffset;
4972 info.stride = stride;
4973
4974 radv_draw(cmd_buffer, &info);
4975 }
4976
4977 void radv_CmdDrawIndexedIndirectCount(
4978 VkCommandBuffer commandBuffer,
4979 VkBuffer _buffer,
4980 VkDeviceSize offset,
4981 VkBuffer _countBuffer,
4982 VkDeviceSize countBufferOffset,
4983 uint32_t maxDrawCount,
4984 uint32_t stride)
4985 {
4986 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4987 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4988 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4989 struct radv_draw_info info = {};
4990
4991 info.indexed = true;
4992 info.count = maxDrawCount;
4993 info.indirect = buffer;
4994 info.indirect_offset = offset;
4995 info.count_buffer = count_buffer;
4996 info.count_buffer_offset = countBufferOffset;
4997 info.stride = stride;
4998
4999 radv_draw(cmd_buffer, &info);
5000 }
5001
5002 struct radv_dispatch_info {
5003 /**
5004 * Determine the layout of the grid (in block units) to be used.
5005 */
5006 uint32_t blocks[3];
5007
5008 /**
5009 * A starting offset for the grid. If unaligned is set, the offset
5010 * must still be aligned.
5011 */
5012 uint32_t offsets[3];
5013 /**
5014 * Whether it's an unaligned compute dispatch.
5015 */
5016 bool unaligned;
5017
5018 /**
5019 * Indirect compute parameters resource.
5020 */
5021 struct radv_buffer *indirect;
5022 uint64_t indirect_offset;
5023 };
5024
5025 static void
5026 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
5027 const struct radv_dispatch_info *info)
5028 {
5029 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
5030 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
5031 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
5032 struct radeon_winsys *ws = cmd_buffer->device->ws;
5033 bool predicating = cmd_buffer->state.predicating;
5034 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5035 struct radv_userdata_info *loc;
5036
5037 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
5038 AC_UD_CS_GRID_SIZE);
5039
5040 ASSERTED unsigned cdw_max = radeon_check_space(ws, cs, 25);
5041
5042 if (compute_shader->info.wave_size == 32) {
5043 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
5044 dispatch_initiator |= S_00B800_CS_W32_EN(1);
5045 }
5046
5047 if (info->indirect) {
5048 uint64_t va = radv_buffer_get_va(info->indirect->bo);
5049
5050 va += info->indirect->offset + info->indirect_offset;
5051
5052 radv_cs_add_buffer(ws, cs, info->indirect->bo);
5053
5054 if (loc->sgpr_idx != -1) {
5055 for (unsigned i = 0; i < 3; ++i) {
5056 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5057 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5058 COPY_DATA_DST_SEL(COPY_DATA_REG));
5059 radeon_emit(cs, (va + 4 * i));
5060 radeon_emit(cs, (va + 4 * i) >> 32);
5061 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
5062 + loc->sgpr_idx * 4) >> 2) + i);
5063 radeon_emit(cs, 0);
5064 }
5065 }
5066
5067 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
5068 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
5069 PKT3_SHADER_TYPE_S(1));
5070 radeon_emit(cs, va);
5071 radeon_emit(cs, va >> 32);
5072 radeon_emit(cs, dispatch_initiator);
5073 } else {
5074 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
5075 PKT3_SHADER_TYPE_S(1));
5076 radeon_emit(cs, 1);
5077 radeon_emit(cs, va);
5078 radeon_emit(cs, va >> 32);
5079
5080 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
5081 PKT3_SHADER_TYPE_S(1));
5082 radeon_emit(cs, 0);
5083 radeon_emit(cs, dispatch_initiator);
5084 }
5085 } else {
5086 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
5087 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
5088
5089 if (info->unaligned) {
5090 unsigned *cs_block_size = compute_shader->info.cs.block_size;
5091 unsigned remainder[3];
5092
5093 /* If aligned, these should be an entire block size,
5094 * not 0.
5095 */
5096 remainder[0] = blocks[0] + cs_block_size[0] -
5097 align_u32_npot(blocks[0], cs_block_size[0]);
5098 remainder[1] = blocks[1] + cs_block_size[1] -
5099 align_u32_npot(blocks[1], cs_block_size[1]);
5100 remainder[2] = blocks[2] + cs_block_size[2] -
5101 align_u32_npot(blocks[2], cs_block_size[2]);
5102
5103 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
5104 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
5105 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
5106
5107 for(unsigned i = 0; i < 3; ++i) {
5108 assert(offsets[i] % cs_block_size[i] == 0);
5109 offsets[i] /= cs_block_size[i];
5110 }
5111
5112 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
5113 radeon_emit(cs,
5114 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
5115 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
5116 radeon_emit(cs,
5117 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
5118 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
5119 radeon_emit(cs,
5120 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
5121 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
5122
5123 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
5124 }
5125
5126 if (loc->sgpr_idx != -1) {
5127 assert(loc->num_sgprs == 3);
5128
5129 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
5130 loc->sgpr_idx * 4, 3);
5131 radeon_emit(cs, blocks[0]);
5132 radeon_emit(cs, blocks[1]);
5133 radeon_emit(cs, blocks[2]);
5134 }
5135
5136 if (offsets[0] || offsets[1] || offsets[2]) {
5137 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
5138 radeon_emit(cs, offsets[0]);
5139 radeon_emit(cs, offsets[1]);
5140 radeon_emit(cs, offsets[2]);
5141
5142 /* The blocks in the packet are not counts but end values. */
5143 for (unsigned i = 0; i < 3; ++i)
5144 blocks[i] += offsets[i];
5145 } else {
5146 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
5147 }
5148
5149 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
5150 PKT3_SHADER_TYPE_S(1));
5151 radeon_emit(cs, blocks[0]);
5152 radeon_emit(cs, blocks[1]);
5153 radeon_emit(cs, blocks[2]);
5154 radeon_emit(cs, dispatch_initiator);
5155 }
5156
5157 assert(cmd_buffer->cs->cdw <= cdw_max);
5158 }
5159
5160 static void
5161 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
5162 {
5163 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
5164 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
5165 }
5166
5167 static void
5168 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
5169 const struct radv_dispatch_info *info)
5170 {
5171 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
5172 bool has_prefetch =
5173 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
5174 bool pipeline_is_dirty = pipeline &&
5175 pipeline != cmd_buffer->state.emitted_compute_pipeline;
5176
5177 radv_describe_dispatch(cmd_buffer, 8, 8, 8);
5178
5179 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5180 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5181 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
5182 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
5183 /* If we have to wait for idle, set all states first, so that
5184 * all SET packets are processed in parallel with previous draw
5185 * calls. Then upload descriptors, set shader pointers, and
5186 * dispatch, and prefetch at the end. This ensures that the
5187 * time the CUs are idle is very short. (there are only SET_SH
5188 * packets between the wait and the draw)
5189 */
5190 radv_emit_compute_pipeline(cmd_buffer);
5191 si_emit_cache_flush(cmd_buffer);
5192 /* <-- CUs are idle here --> */
5193
5194 radv_upload_compute_shader_descriptors(cmd_buffer);
5195
5196 radv_emit_dispatch_packets(cmd_buffer, info);
5197 /* <-- CUs are busy here --> */
5198
5199 /* Start prefetches after the dispatch has been started. Both
5200 * will run in parallel, but starting the dispatch first is
5201 * more important.
5202 */
5203 if (has_prefetch && pipeline_is_dirty) {
5204 radv_emit_shader_prefetch(cmd_buffer,
5205 pipeline->shaders[MESA_SHADER_COMPUTE]);
5206 }
5207 } else {
5208 /* If we don't wait for idle, start prefetches first, then set
5209 * states, and dispatch at the end.
5210 */
5211 si_emit_cache_flush(cmd_buffer);
5212
5213 if (has_prefetch && pipeline_is_dirty) {
5214 radv_emit_shader_prefetch(cmd_buffer,
5215 pipeline->shaders[MESA_SHADER_COMPUTE]);
5216 }
5217
5218 radv_upload_compute_shader_descriptors(cmd_buffer);
5219
5220 radv_emit_compute_pipeline(cmd_buffer);
5221 radv_emit_dispatch_packets(cmd_buffer, info);
5222 }
5223
5224 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
5225 }
5226
5227 void radv_CmdDispatchBase(
5228 VkCommandBuffer commandBuffer,
5229 uint32_t base_x,
5230 uint32_t base_y,
5231 uint32_t base_z,
5232 uint32_t x,
5233 uint32_t y,
5234 uint32_t z)
5235 {
5236 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5237 struct radv_dispatch_info info = {};
5238
5239 info.blocks[0] = x;
5240 info.blocks[1] = y;
5241 info.blocks[2] = z;
5242
5243 info.offsets[0] = base_x;
5244 info.offsets[1] = base_y;
5245 info.offsets[2] = base_z;
5246 radv_dispatch(cmd_buffer, &info);
5247 }
5248
5249 void radv_CmdDispatch(
5250 VkCommandBuffer commandBuffer,
5251 uint32_t x,
5252 uint32_t y,
5253 uint32_t z)
5254 {
5255 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
5256 }
5257
5258 void radv_CmdDispatchIndirect(
5259 VkCommandBuffer commandBuffer,
5260 VkBuffer _buffer,
5261 VkDeviceSize offset)
5262 {
5263 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5264 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5265 struct radv_dispatch_info info = {};
5266
5267 info.indirect = buffer;
5268 info.indirect_offset = offset;
5269
5270 radv_dispatch(cmd_buffer, &info);
5271 }
5272
5273 void radv_unaligned_dispatch(
5274 struct radv_cmd_buffer *cmd_buffer,
5275 uint32_t x,
5276 uint32_t y,
5277 uint32_t z)
5278 {
5279 struct radv_dispatch_info info = {};
5280
5281 info.blocks[0] = x;
5282 info.blocks[1] = y;
5283 info.blocks[2] = z;
5284 info.unaligned = 1;
5285
5286 radv_dispatch(cmd_buffer, &info);
5287 }
5288
5289 void
5290 radv_cmd_buffer_end_render_pass(struct radv_cmd_buffer *cmd_buffer)
5291 {
5292 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
5293 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
5294
5295 cmd_buffer->state.pass = NULL;
5296 cmd_buffer->state.subpass = NULL;
5297 cmd_buffer->state.attachments = NULL;
5298 cmd_buffer->state.framebuffer = NULL;
5299 cmd_buffer->state.subpass_sample_locs = NULL;
5300 }
5301
5302 void radv_CmdEndRenderPass(
5303 VkCommandBuffer commandBuffer)
5304 {
5305 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5306
5307 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
5308
5309 radv_cmd_buffer_end_subpass(cmd_buffer);
5310
5311 radv_cmd_buffer_end_render_pass(cmd_buffer);
5312 }
5313
5314 void radv_CmdEndRenderPass2(
5315 VkCommandBuffer commandBuffer,
5316 const VkSubpassEndInfo* pSubpassEndInfo)
5317 {
5318 radv_CmdEndRenderPass(commandBuffer);
5319 }
5320
5321 /*
5322 * For HTILE we have the following interesting clear words:
5323 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
5324 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
5325 * 0xfffffff0: Clear depth to 1.0
5326 * 0x00000000: Clear depth to 0.0
5327 */
5328 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
5329 struct radv_image *image,
5330 const VkImageSubresourceRange *range)
5331 {
5332 assert(range->baseMipLevel == 0);
5333 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
5334 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
5335 struct radv_cmd_state *state = &cmd_buffer->state;
5336 uint32_t htile_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
5337 VkClearDepthStencilValue value = {};
5338 struct radv_barrier_data barrier = {};
5339
5340 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5341 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5342
5343 barrier.layout_transitions.init_mask_ram = 1;
5344 radv_describe_layout_transition(cmd_buffer, &barrier);
5345
5346 state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, htile_value);
5347
5348 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5349
5350 if (vk_format_is_stencil(image->vk_format))
5351 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
5352
5353 radv_set_ds_clear_metadata(cmd_buffer, image, range, value, aspects);
5354
5355 if (radv_image_is_tc_compat_htile(image)) {
5356 /* Initialize the TC-compat metada value to 0 because by
5357 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
5358 * need have to conditionally update its value when performing
5359 * a fast depth clear.
5360 */
5361 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, range, 0);
5362 }
5363 }
5364
5365 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
5366 struct radv_image *image,
5367 VkImageLayout src_layout,
5368 bool src_render_loop,
5369 VkImageLayout dst_layout,
5370 bool dst_render_loop,
5371 unsigned src_queue_mask,
5372 unsigned dst_queue_mask,
5373 const VkImageSubresourceRange *range,
5374 struct radv_sample_locations_state *sample_locs)
5375 {
5376 if (!radv_image_has_htile(image))
5377 return;
5378
5379 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5380 radv_initialize_htile(cmd_buffer, image, range);
5381 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5382 radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5383 radv_initialize_htile(cmd_buffer, image, range);
5384 } else if (radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5385 !radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5386 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5387 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5388
5389 radv_decompress_depth_image_inplace(cmd_buffer, image, range,
5390 sample_locs);
5391
5392 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5393 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5394 }
5395 }
5396
5397 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
5398 struct radv_image *image,
5399 const VkImageSubresourceRange *range,
5400 uint32_t value)
5401 {
5402 struct radv_cmd_state *state = &cmd_buffer->state;
5403 struct radv_barrier_data barrier = {};
5404
5405 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5406 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5407
5408 barrier.layout_transitions.init_mask_ram = 1;
5409 radv_describe_layout_transition(cmd_buffer, &barrier);
5410
5411 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, range, value);
5412
5413 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5414 }
5415
5416 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
5417 struct radv_image *image,
5418 const VkImageSubresourceRange *range)
5419 {
5420 struct radv_cmd_state *state = &cmd_buffer->state;
5421 static const uint32_t fmask_clear_values[4] = {
5422 0x00000000,
5423 0x02020202,
5424 0xE4E4E4E4,
5425 0x76543210
5426 };
5427 uint32_t log2_samples = util_logbase2(image->info.samples);
5428 uint32_t value = fmask_clear_values[log2_samples];
5429 struct radv_barrier_data barrier = {};
5430
5431 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5432 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5433
5434 barrier.layout_transitions.init_mask_ram = 1;
5435 radv_describe_layout_transition(cmd_buffer, &barrier);
5436
5437 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, range, value);
5438
5439 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5440 }
5441
5442 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
5443 struct radv_image *image,
5444 const VkImageSubresourceRange *range, uint32_t value)
5445 {
5446 struct radv_cmd_state *state = &cmd_buffer->state;
5447 struct radv_barrier_data barrier = {};
5448 unsigned size = 0;
5449
5450 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5451 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5452
5453 barrier.layout_transitions.init_mask_ram = 1;
5454 radv_describe_layout_transition(cmd_buffer, &barrier);
5455
5456 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
5457
5458 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) {
5459 /* When DCC is enabled with mipmaps, some levels might not
5460 * support fast clears and we have to initialize them as "fully
5461 * expanded".
5462 */
5463 /* Compute the size of all fast clearable DCC levels. */
5464 for (unsigned i = 0; i < image->planes[0].surface.num_dcc_levels; i++) {
5465 struct legacy_surf_level *surf_level =
5466 &image->planes[0].surface.u.legacy.level[i];
5467 unsigned dcc_fast_clear_size =
5468 surf_level->dcc_slice_fast_clear_size * image->info.array_size;
5469
5470 if (!dcc_fast_clear_size)
5471 break;
5472
5473 size = surf_level->dcc_offset + dcc_fast_clear_size;
5474 }
5475
5476 /* Initialize the mipmap levels without DCC. */
5477 if (size != image->planes[0].surface.dcc_size) {
5478 state->flush_bits |=
5479 radv_fill_buffer(cmd_buffer, image->bo,
5480 image->offset + image->dcc_offset + size,
5481 image->planes[0].surface.dcc_size - size,
5482 0xffffffff);
5483 }
5484 }
5485
5486 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5487 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5488 }
5489
5490 /**
5491 * Initialize DCC/FMASK/CMASK metadata for a color image.
5492 */
5493 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
5494 struct radv_image *image,
5495 VkImageLayout src_layout,
5496 bool src_render_loop,
5497 VkImageLayout dst_layout,
5498 bool dst_render_loop,
5499 unsigned src_queue_mask,
5500 unsigned dst_queue_mask,
5501 const VkImageSubresourceRange *range)
5502 {
5503 if (radv_image_has_cmask(image)) {
5504 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5505
5506 /* TODO: clarify this. */
5507 if (radv_image_has_fmask(image)) {
5508 value = 0xccccccccu;
5509 }
5510
5511 radv_initialise_cmask(cmd_buffer, image, range, value);
5512 }
5513
5514 if (radv_image_has_fmask(image)) {
5515 radv_initialize_fmask(cmd_buffer, image, range);
5516 }
5517
5518 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5519 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5520 bool need_decompress_pass = false;
5521
5522 if (radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout,
5523 dst_render_loop,
5524 dst_queue_mask)) {
5525 value = 0x20202020u;
5526 need_decompress_pass = true;
5527 }
5528
5529 radv_initialize_dcc(cmd_buffer, image, range, value);
5530
5531 radv_update_fce_metadata(cmd_buffer, image, range,
5532 need_decompress_pass);
5533 }
5534
5535 if (radv_image_has_cmask(image) ||
5536 radv_dcc_enabled(image, range->baseMipLevel)) {
5537 uint32_t color_values[2] = {};
5538 radv_set_color_clear_metadata(cmd_buffer, image, range,
5539 color_values);
5540 }
5541 }
5542
5543 /**
5544 * Handle color image transitions for DCC/FMASK/CMASK.
5545 */
5546 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
5547 struct radv_image *image,
5548 VkImageLayout src_layout,
5549 bool src_render_loop,
5550 VkImageLayout dst_layout,
5551 bool dst_render_loop,
5552 unsigned src_queue_mask,
5553 unsigned dst_queue_mask,
5554 const VkImageSubresourceRange *range)
5555 {
5556 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5557 radv_init_color_image_metadata(cmd_buffer, image,
5558 src_layout, src_render_loop,
5559 dst_layout, dst_render_loop,
5560 src_queue_mask, dst_queue_mask,
5561 range);
5562 return;
5563 }
5564
5565 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5566 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
5567 radv_initialize_dcc(cmd_buffer, image, range, 0xffffffffu);
5568 } else if (radv_layout_dcc_compressed(cmd_buffer->device, image, src_layout, src_render_loop, src_queue_mask) &&
5569 !radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout, dst_render_loop, dst_queue_mask)) {
5570 radv_decompress_dcc(cmd_buffer, image, range);
5571 } else if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
5572 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5573 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5574 }
5575 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
5576 bool fce_eliminate = false, fmask_expand = false;
5577
5578 if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
5579 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5580 fce_eliminate = true;
5581 }
5582
5583 if (radv_image_has_fmask(image)) {
5584 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
5585 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
5586 /* A FMASK decompress is required before doing
5587 * a MSAA decompress using FMASK.
5588 */
5589 fmask_expand = true;
5590 }
5591 }
5592
5593 if (fce_eliminate || fmask_expand)
5594 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5595
5596 if (fmask_expand) {
5597 struct radv_barrier_data barrier = {};
5598 barrier.layout_transitions.fmask_color_expand = 1;
5599 radv_describe_layout_transition(cmd_buffer, &barrier);
5600
5601 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
5602 }
5603 }
5604 }
5605
5606 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
5607 struct radv_image *image,
5608 VkImageLayout src_layout,
5609 bool src_render_loop,
5610 VkImageLayout dst_layout,
5611 bool dst_render_loop,
5612 uint32_t src_family,
5613 uint32_t dst_family,
5614 const VkImageSubresourceRange *range,
5615 struct radv_sample_locations_state *sample_locs)
5616 {
5617 if (image->exclusive && src_family != dst_family) {
5618 /* This is an acquire or a release operation and there will be
5619 * a corresponding release/acquire. Do the transition in the
5620 * most flexible queue. */
5621
5622 assert(src_family == cmd_buffer->queue_family_index ||
5623 dst_family == cmd_buffer->queue_family_index);
5624
5625 if (src_family == VK_QUEUE_FAMILY_EXTERNAL ||
5626 src_family == VK_QUEUE_FAMILY_FOREIGN_EXT)
5627 return;
5628
5629 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
5630 return;
5631
5632 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
5633 (src_family == RADV_QUEUE_GENERAL ||
5634 dst_family == RADV_QUEUE_GENERAL))
5635 return;
5636 }
5637
5638 if (src_layout == dst_layout)
5639 return;
5640
5641 unsigned src_queue_mask =
5642 radv_image_queue_family_mask(image, src_family,
5643 cmd_buffer->queue_family_index);
5644 unsigned dst_queue_mask =
5645 radv_image_queue_family_mask(image, dst_family,
5646 cmd_buffer->queue_family_index);
5647
5648 if (vk_format_is_depth(image->vk_format)) {
5649 radv_handle_depth_image_transition(cmd_buffer, image,
5650 src_layout, src_render_loop,
5651 dst_layout, dst_render_loop,
5652 src_queue_mask, dst_queue_mask,
5653 range, sample_locs);
5654 } else {
5655 radv_handle_color_image_transition(cmd_buffer, image,
5656 src_layout, src_render_loop,
5657 dst_layout, dst_render_loop,
5658 src_queue_mask, dst_queue_mask,
5659 range);
5660 }
5661 }
5662
5663 struct radv_barrier_info {
5664 enum rgp_barrier_reason reason;
5665 uint32_t eventCount;
5666 const VkEvent *pEvents;
5667 VkPipelineStageFlags srcStageMask;
5668 VkPipelineStageFlags dstStageMask;
5669 };
5670
5671 static void
5672 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
5673 uint32_t memoryBarrierCount,
5674 const VkMemoryBarrier *pMemoryBarriers,
5675 uint32_t bufferMemoryBarrierCount,
5676 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
5677 uint32_t imageMemoryBarrierCount,
5678 const VkImageMemoryBarrier *pImageMemoryBarriers,
5679 const struct radv_barrier_info *info)
5680 {
5681 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5682 enum radv_cmd_flush_bits src_flush_bits = 0;
5683 enum radv_cmd_flush_bits dst_flush_bits = 0;
5684
5685 radv_describe_barrier_start(cmd_buffer, info->reason);
5686
5687 for (unsigned i = 0; i < info->eventCount; ++i) {
5688 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
5689 uint64_t va = radv_buffer_get_va(event->bo);
5690
5691 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5692
5693 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
5694
5695 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
5696 assert(cmd_buffer->cs->cdw <= cdw_max);
5697 }
5698
5699 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
5700 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
5701 NULL);
5702 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
5703 NULL);
5704 }
5705
5706 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
5707 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
5708 NULL);
5709 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
5710 NULL);
5711 }
5712
5713 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5714 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5715
5716 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
5717 image);
5718 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
5719 image);
5720 }
5721
5722 /* The Vulkan spec 1.1.98 says:
5723 *
5724 * "An execution dependency with only
5725 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
5726 * will only prevent that stage from executing in subsequently
5727 * submitted commands. As this stage does not perform any actual
5728 * execution, this is not observable - in effect, it does not delay
5729 * processing of subsequent commands. Similarly an execution dependency
5730 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
5731 * will effectively not wait for any prior commands to complete."
5732 */
5733 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
5734 radv_stage_flush(cmd_buffer, info->srcStageMask);
5735 cmd_buffer->state.flush_bits |= src_flush_bits;
5736
5737 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5738 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5739
5740 const struct VkSampleLocationsInfoEXT *sample_locs_info =
5741 vk_find_struct_const(pImageMemoryBarriers[i].pNext,
5742 SAMPLE_LOCATIONS_INFO_EXT);
5743 struct radv_sample_locations_state sample_locations = {};
5744
5745 if (sample_locs_info) {
5746 assert(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
5747 sample_locations.per_pixel = sample_locs_info->sampleLocationsPerPixel;
5748 sample_locations.grid_size = sample_locs_info->sampleLocationGridSize;
5749 sample_locations.count = sample_locs_info->sampleLocationsCount;
5750 typed_memcpy(&sample_locations.locations[0],
5751 sample_locs_info->pSampleLocations,
5752 sample_locs_info->sampleLocationsCount);
5753 }
5754
5755 radv_handle_image_transition(cmd_buffer, image,
5756 pImageMemoryBarriers[i].oldLayout,
5757 false, /* Outside of a renderpass we are never in a renderloop */
5758 pImageMemoryBarriers[i].newLayout,
5759 false, /* Outside of a renderpass we are never in a renderloop */
5760 pImageMemoryBarriers[i].srcQueueFamilyIndex,
5761 pImageMemoryBarriers[i].dstQueueFamilyIndex,
5762 &pImageMemoryBarriers[i].subresourceRange,
5763 sample_locs_info ? &sample_locations : NULL);
5764 }
5765
5766 /* Make sure CP DMA is idle because the driver might have performed a
5767 * DMA operation for copying or filling buffers/images.
5768 */
5769 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5770 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5771 si_cp_dma_wait_for_idle(cmd_buffer);
5772
5773 cmd_buffer->state.flush_bits |= dst_flush_bits;
5774
5775 radv_describe_barrier_end(cmd_buffer);
5776 }
5777
5778 void radv_CmdPipelineBarrier(
5779 VkCommandBuffer commandBuffer,
5780 VkPipelineStageFlags srcStageMask,
5781 VkPipelineStageFlags destStageMask,
5782 VkBool32 byRegion,
5783 uint32_t memoryBarrierCount,
5784 const VkMemoryBarrier* pMemoryBarriers,
5785 uint32_t bufferMemoryBarrierCount,
5786 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5787 uint32_t imageMemoryBarrierCount,
5788 const VkImageMemoryBarrier* pImageMemoryBarriers)
5789 {
5790 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5791 struct radv_barrier_info info;
5792
5793 info.reason = RGP_BARRIER_EXTERNAL_CMD_PIPELINE_BARRIER;
5794 info.eventCount = 0;
5795 info.pEvents = NULL;
5796 info.srcStageMask = srcStageMask;
5797 info.dstStageMask = destStageMask;
5798
5799 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5800 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5801 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5802 }
5803
5804
5805 static void write_event(struct radv_cmd_buffer *cmd_buffer,
5806 struct radv_event *event,
5807 VkPipelineStageFlags stageMask,
5808 unsigned value)
5809 {
5810 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5811 uint64_t va = radv_buffer_get_va(event->bo);
5812
5813 si_emit_cache_flush(cmd_buffer);
5814
5815 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5816
5817 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 21);
5818
5819 /* Flags that only require a top-of-pipe event. */
5820 VkPipelineStageFlags top_of_pipe_flags =
5821 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
5822
5823 /* Flags that only require a post-index-fetch event. */
5824 VkPipelineStageFlags post_index_fetch_flags =
5825 top_of_pipe_flags |
5826 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
5827 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
5828
5829 /* Make sure CP DMA is idle because the driver might have performed a
5830 * DMA operation for copying or filling buffers/images.
5831 */
5832 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5833 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5834 si_cp_dma_wait_for_idle(cmd_buffer);
5835
5836 /* TODO: Emit EOS events for syncing PS/CS stages. */
5837
5838 if (!(stageMask & ~top_of_pipe_flags)) {
5839 /* Just need to sync the PFP engine. */
5840 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5841 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5842 S_370_WR_CONFIRM(1) |
5843 S_370_ENGINE_SEL(V_370_PFP));
5844 radeon_emit(cs, va);
5845 radeon_emit(cs, va >> 32);
5846 radeon_emit(cs, value);
5847 } else if (!(stageMask & ~post_index_fetch_flags)) {
5848 /* Sync ME because PFP reads index and indirect buffers. */
5849 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5850 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5851 S_370_WR_CONFIRM(1) |
5852 S_370_ENGINE_SEL(V_370_ME));
5853 radeon_emit(cs, va);
5854 radeon_emit(cs, va >> 32);
5855 radeon_emit(cs, value);
5856 } else {
5857 /* Otherwise, sync all prior GPU work using an EOP event. */
5858 si_cs_emit_write_event_eop(cs,
5859 cmd_buffer->device->physical_device->rad_info.chip_class,
5860 radv_cmd_buffer_uses_mec(cmd_buffer),
5861 V_028A90_BOTTOM_OF_PIPE_TS, 0,
5862 EOP_DST_SEL_MEM,
5863 EOP_DATA_SEL_VALUE_32BIT, va, value,
5864 cmd_buffer->gfx9_eop_bug_va);
5865 }
5866
5867 assert(cmd_buffer->cs->cdw <= cdw_max);
5868 }
5869
5870 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
5871 VkEvent _event,
5872 VkPipelineStageFlags stageMask)
5873 {
5874 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5875 RADV_FROM_HANDLE(radv_event, event, _event);
5876
5877 write_event(cmd_buffer, event, stageMask, 1);
5878 }
5879
5880 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
5881 VkEvent _event,
5882 VkPipelineStageFlags stageMask)
5883 {
5884 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5885 RADV_FROM_HANDLE(radv_event, event, _event);
5886
5887 write_event(cmd_buffer, event, stageMask, 0);
5888 }
5889
5890 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
5891 uint32_t eventCount,
5892 const VkEvent* pEvents,
5893 VkPipelineStageFlags srcStageMask,
5894 VkPipelineStageFlags dstStageMask,
5895 uint32_t memoryBarrierCount,
5896 const VkMemoryBarrier* pMemoryBarriers,
5897 uint32_t bufferMemoryBarrierCount,
5898 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5899 uint32_t imageMemoryBarrierCount,
5900 const VkImageMemoryBarrier* pImageMemoryBarriers)
5901 {
5902 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5903 struct radv_barrier_info info;
5904
5905 info.reason = RGP_BARRIER_EXTERNAL_CMD_WAIT_EVENTS;
5906 info.eventCount = eventCount;
5907 info.pEvents = pEvents;
5908 info.srcStageMask = 0;
5909
5910 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5911 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5912 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5913 }
5914
5915
5916 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
5917 uint32_t deviceMask)
5918 {
5919 /* No-op */
5920 }
5921
5922 /* VK_EXT_conditional_rendering */
5923 void radv_CmdBeginConditionalRenderingEXT(
5924 VkCommandBuffer commandBuffer,
5925 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
5926 {
5927 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5928 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
5929 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5930 bool draw_visible = true;
5931 uint64_t pred_value = 0;
5932 uint64_t va, new_va;
5933 unsigned pred_offset;
5934
5935 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
5936
5937 /* By default, if the 32-bit value at offset in buffer memory is zero,
5938 * then the rendering commands are discarded, otherwise they are
5939 * executed as normal. If the inverted flag is set, all commands are
5940 * discarded if the value is non zero.
5941 */
5942 if (pConditionalRenderingBegin->flags &
5943 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
5944 draw_visible = false;
5945 }
5946
5947 si_emit_cache_flush(cmd_buffer);
5948
5949 /* From the Vulkan spec 1.1.107:
5950 *
5951 * "If the 32-bit value at offset in buffer memory is zero, then the
5952 * rendering commands are discarded, otherwise they are executed as
5953 * normal. If the value of the predicate in buffer memory changes while
5954 * conditional rendering is active, the rendering commands may be
5955 * discarded in an implementation-dependent way. Some implementations
5956 * may latch the value of the predicate upon beginning conditional
5957 * rendering while others may read it before every rendering command."
5958 *
5959 * But, the AMD hardware treats the predicate as a 64-bit value which
5960 * means we need a workaround in the driver. Luckily, it's not required
5961 * to support if the value changes when predication is active.
5962 *
5963 * The workaround is as follows:
5964 * 1) allocate a 64-value in the upload BO and initialize it to 0
5965 * 2) copy the 32-bit predicate value to the upload BO
5966 * 3) use the new allocated VA address for predication
5967 *
5968 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
5969 * in ME (+ sync PFP) instead of PFP.
5970 */
5971 radv_cmd_buffer_upload_data(cmd_buffer, 8, 16, &pred_value, &pred_offset);
5972
5973 new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
5974
5975 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5976 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5977 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
5978 COPY_DATA_WR_CONFIRM);
5979 radeon_emit(cs, va);
5980 radeon_emit(cs, va >> 32);
5981 radeon_emit(cs, new_va);
5982 radeon_emit(cs, new_va >> 32);
5983
5984 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
5985 radeon_emit(cs, 0);
5986
5987 /* Enable predication for this command buffer. */
5988 si_emit_set_predication_state(cmd_buffer, draw_visible, new_va);
5989 cmd_buffer->state.predicating = true;
5990
5991 /* Store conditional rendering user info. */
5992 cmd_buffer->state.predication_type = draw_visible;
5993 cmd_buffer->state.predication_va = new_va;
5994 }
5995
5996 void radv_CmdEndConditionalRenderingEXT(
5997 VkCommandBuffer commandBuffer)
5998 {
5999 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6000
6001 /* Disable predication for this command buffer. */
6002 si_emit_set_predication_state(cmd_buffer, false, 0);
6003 cmd_buffer->state.predicating = false;
6004
6005 /* Reset conditional rendering user info. */
6006 cmd_buffer->state.predication_type = -1;
6007 cmd_buffer->state.predication_va = 0;
6008 }
6009
6010 /* VK_EXT_transform_feedback */
6011 void radv_CmdBindTransformFeedbackBuffersEXT(
6012 VkCommandBuffer commandBuffer,
6013 uint32_t firstBinding,
6014 uint32_t bindingCount,
6015 const VkBuffer* pBuffers,
6016 const VkDeviceSize* pOffsets,
6017 const VkDeviceSize* pSizes)
6018 {
6019 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6020 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
6021 uint8_t enabled_mask = 0;
6022
6023 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
6024 for (uint32_t i = 0; i < bindingCount; i++) {
6025 uint32_t idx = firstBinding + i;
6026
6027 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
6028 sb[idx].offset = pOffsets[i];
6029
6030 if (!pSizes || pSizes[i] == VK_WHOLE_SIZE) {
6031 sb[idx].size = sb[idx].buffer->size - sb[idx].offset;
6032 } else {
6033 sb[idx].size = pSizes[i];
6034 }
6035
6036 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
6037 sb[idx].buffer->bo);
6038
6039 enabled_mask |= 1 << idx;
6040 }
6041
6042 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
6043
6044 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
6045 }
6046
6047 static void
6048 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
6049 {
6050 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6051 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6052
6053 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
6054 radeon_emit(cs,
6055 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
6056 S_028B94_RAST_STREAM(0) |
6057 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
6058 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
6059 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
6060 radeon_emit(cs, so->hw_enabled_mask &
6061 so->enabled_stream_buffers_mask);
6062
6063 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6064 }
6065
6066 static void
6067 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
6068 {
6069 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6070 bool old_streamout_enabled = so->streamout_enabled;
6071 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
6072
6073 so->streamout_enabled = enable;
6074
6075 so->hw_enabled_mask = so->enabled_mask |
6076 (so->enabled_mask << 4) |
6077 (so->enabled_mask << 8) |
6078 (so->enabled_mask << 12);
6079
6080 if (!cmd_buffer->device->physical_device->use_ngg_streamout &&
6081 ((old_streamout_enabled != so->streamout_enabled) ||
6082 (old_hw_enabled_mask != so->hw_enabled_mask)))
6083 radv_emit_streamout_enable(cmd_buffer);
6084
6085 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6086 cmd_buffer->gds_needed = true;
6087 cmd_buffer->gds_oa_needed = true;
6088 }
6089 }
6090
6091 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
6092 {
6093 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6094 unsigned reg_strmout_cntl;
6095
6096 /* The register is at different places on different ASICs. */
6097 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
6098 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
6099 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
6100 } else {
6101 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
6102 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
6103 }
6104
6105 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
6106 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
6107
6108 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
6109 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
6110 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
6111 radeon_emit(cs, 0);
6112 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
6113 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
6114 radeon_emit(cs, 4); /* poll interval */
6115 }
6116
6117 static void
6118 radv_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
6119 uint32_t firstCounterBuffer,
6120 uint32_t counterBufferCount,
6121 const VkBuffer *pCounterBuffers,
6122 const VkDeviceSize *pCounterBufferOffsets)
6123
6124 {
6125 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
6126 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6127 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6128 uint32_t i;
6129
6130 radv_flush_vgt_streamout(cmd_buffer);
6131
6132 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6133 for_each_bit(i, so->enabled_mask) {
6134 int32_t counter_buffer_idx = i - firstCounterBuffer;
6135 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6136 counter_buffer_idx = -1;
6137
6138 /* AMD GCN binds streamout buffers as shader resources.
6139 * VGT only counts primitives and tells the shader through
6140 * SGPRs what to do.
6141 */
6142 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
6143 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
6144 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
6145
6146 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6147
6148 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6149 /* The array of counter buffers is optional. */
6150 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6151 uint64_t va = radv_buffer_get_va(buffer->bo);
6152
6153 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6154
6155 /* Append */
6156 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6157 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6158 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6159 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
6160 radeon_emit(cs, 0); /* unused */
6161 radeon_emit(cs, 0); /* unused */
6162 radeon_emit(cs, va); /* src address lo */
6163 radeon_emit(cs, va >> 32); /* src address hi */
6164
6165 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6166 } else {
6167 /* Start from the beginning. */
6168 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6169 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6170 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6171 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
6172 radeon_emit(cs, 0); /* unused */
6173 radeon_emit(cs, 0); /* unused */
6174 radeon_emit(cs, 0); /* unused */
6175 radeon_emit(cs, 0); /* unused */
6176 }
6177 }
6178
6179 radv_set_streamout_enable(cmd_buffer, true);
6180 }
6181
6182 static void
6183 gfx10_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
6184 uint32_t firstCounterBuffer,
6185 uint32_t counterBufferCount,
6186 const VkBuffer *pCounterBuffers,
6187 const VkDeviceSize *pCounterBufferOffsets)
6188 {
6189 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6190 unsigned last_target = util_last_bit(so->enabled_mask) - 1;
6191 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6192 uint32_t i;
6193
6194 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6195 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6196
6197 /* Sync because the next streamout operation will overwrite GDS and we
6198 * have to make sure it's idle.
6199 * TODO: Improve by tracking if there is a streamout operation in
6200 * flight.
6201 */
6202 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
6203 si_emit_cache_flush(cmd_buffer);
6204
6205 for_each_bit(i, so->enabled_mask) {
6206 int32_t counter_buffer_idx = i - firstCounterBuffer;
6207 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6208 counter_buffer_idx = -1;
6209
6210 bool append = counter_buffer_idx >= 0 &&
6211 pCounterBuffers && pCounterBuffers[counter_buffer_idx];
6212 uint64_t va = 0;
6213
6214 if (append) {
6215 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6216
6217 va += radv_buffer_get_va(buffer->bo);
6218 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6219
6220 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6221 }
6222
6223 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
6224 radeon_emit(cs, S_411_SRC_SEL(append ? V_411_SRC_ADDR_TC_L2 : V_411_DATA) |
6225 S_411_DST_SEL(V_411_GDS) |
6226 S_411_CP_SYNC(i == last_target));
6227 radeon_emit(cs, va);
6228 radeon_emit(cs, va >> 32);
6229 radeon_emit(cs, 4 * i); /* destination in GDS */
6230 radeon_emit(cs, 0);
6231 radeon_emit(cs, S_414_BYTE_COUNT_GFX9(4) |
6232 S_414_DISABLE_WR_CONFIRM_GFX9(i != last_target));
6233 }
6234
6235 radv_set_streamout_enable(cmd_buffer, true);
6236 }
6237
6238 void radv_CmdBeginTransformFeedbackEXT(
6239 VkCommandBuffer commandBuffer,
6240 uint32_t firstCounterBuffer,
6241 uint32_t counterBufferCount,
6242 const VkBuffer* pCounterBuffers,
6243 const VkDeviceSize* pCounterBufferOffsets)
6244 {
6245 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6246
6247 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6248 gfx10_emit_streamout_begin(cmd_buffer,
6249 firstCounterBuffer, counterBufferCount,
6250 pCounterBuffers, pCounterBufferOffsets);
6251 } else {
6252 radv_emit_streamout_begin(cmd_buffer,
6253 firstCounterBuffer, counterBufferCount,
6254 pCounterBuffers, pCounterBufferOffsets);
6255 }
6256 }
6257
6258 static void
6259 radv_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6260 uint32_t firstCounterBuffer,
6261 uint32_t counterBufferCount,
6262 const VkBuffer *pCounterBuffers,
6263 const VkDeviceSize *pCounterBufferOffsets)
6264 {
6265 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6266 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6267 uint32_t i;
6268
6269 radv_flush_vgt_streamout(cmd_buffer);
6270
6271 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6272 for_each_bit(i, so->enabled_mask) {
6273 int32_t counter_buffer_idx = i - firstCounterBuffer;
6274 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6275 counter_buffer_idx = -1;
6276
6277 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6278 /* The array of counters buffer is optional. */
6279 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6280 uint64_t va = radv_buffer_get_va(buffer->bo);
6281
6282 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6283
6284 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6285 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6286 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6287 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
6288 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
6289 radeon_emit(cs, va); /* dst address lo */
6290 radeon_emit(cs, va >> 32); /* dst address hi */
6291 radeon_emit(cs, 0); /* unused */
6292 radeon_emit(cs, 0); /* unused */
6293
6294 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6295 }
6296
6297 /* Deactivate transform feedback by zeroing the buffer size.
6298 * The counters (primitives generated, primitives emitted) may
6299 * be enabled even if there is not buffer bound. This ensures
6300 * that the primitives-emitted query won't increment.
6301 */
6302 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
6303
6304 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6305 }
6306
6307 radv_set_streamout_enable(cmd_buffer, false);
6308 }
6309
6310 static void
6311 gfx10_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6312 uint32_t firstCounterBuffer,
6313 uint32_t counterBufferCount,
6314 const VkBuffer *pCounterBuffers,
6315 const VkDeviceSize *pCounterBufferOffsets)
6316 {
6317 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6318 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6319 uint32_t i;
6320
6321 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6322 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6323
6324 for_each_bit(i, so->enabled_mask) {
6325 int32_t counter_buffer_idx = i - firstCounterBuffer;
6326 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6327 counter_buffer_idx = -1;
6328
6329 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6330 /* The array of counters buffer is optional. */
6331 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6332 uint64_t va = radv_buffer_get_va(buffer->bo);
6333
6334 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6335
6336 si_cs_emit_write_event_eop(cs,
6337 cmd_buffer->device->physical_device->rad_info.chip_class,
6338 radv_cmd_buffer_uses_mec(cmd_buffer),
6339 V_028A90_PS_DONE, 0,
6340 EOP_DST_SEL_TC_L2,
6341 EOP_DATA_SEL_GDS,
6342 va, EOP_DATA_GDS(i, 1), 0);
6343
6344 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6345 }
6346 }
6347
6348 radv_set_streamout_enable(cmd_buffer, false);
6349 }
6350
6351 void radv_CmdEndTransformFeedbackEXT(
6352 VkCommandBuffer commandBuffer,
6353 uint32_t firstCounterBuffer,
6354 uint32_t counterBufferCount,
6355 const VkBuffer* pCounterBuffers,
6356 const VkDeviceSize* pCounterBufferOffsets)
6357 {
6358 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6359
6360 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6361 gfx10_emit_streamout_end(cmd_buffer,
6362 firstCounterBuffer, counterBufferCount,
6363 pCounterBuffers, pCounterBufferOffsets);
6364 } else {
6365 radv_emit_streamout_end(cmd_buffer,
6366 firstCounterBuffer, counterBufferCount,
6367 pCounterBuffers, pCounterBufferOffsets);
6368 }
6369 }
6370
6371 void radv_CmdDrawIndirectByteCountEXT(
6372 VkCommandBuffer commandBuffer,
6373 uint32_t instanceCount,
6374 uint32_t firstInstance,
6375 VkBuffer _counterBuffer,
6376 VkDeviceSize counterBufferOffset,
6377 uint32_t counterOffset,
6378 uint32_t vertexStride)
6379 {
6380 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6381 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
6382 struct radv_draw_info info = {};
6383
6384 info.instance_count = instanceCount;
6385 info.first_instance = firstInstance;
6386 info.strmout_buffer = counterBuffer;
6387 info.strmout_buffer_offset = counterBufferOffset;
6388 info.stride = vertexStride;
6389
6390 radv_draw(cmd_buffer, &info);
6391 }
6392
6393 /* VK_AMD_buffer_marker */
6394 void radv_CmdWriteBufferMarkerAMD(
6395 VkCommandBuffer commandBuffer,
6396 VkPipelineStageFlagBits pipelineStage,
6397 VkBuffer dstBuffer,
6398 VkDeviceSize dstOffset,
6399 uint32_t marker)
6400 {
6401 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6402 RADV_FROM_HANDLE(radv_buffer, buffer, dstBuffer);
6403 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6404 uint64_t va = radv_buffer_get_va(buffer->bo) + dstOffset;
6405
6406 si_emit_cache_flush(cmd_buffer);
6407
6408 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 12);
6409
6410 if (!(pipelineStage & ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT)) {
6411 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
6412 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
6413 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
6414 COPY_DATA_WR_CONFIRM);
6415 radeon_emit(cs, marker);
6416 radeon_emit(cs, 0);
6417 radeon_emit(cs, va);
6418 radeon_emit(cs, va >> 32);
6419 } else {
6420 si_cs_emit_write_event_eop(cs,
6421 cmd_buffer->device->physical_device->rad_info.chip_class,
6422 radv_cmd_buffer_uses_mec(cmd_buffer),
6423 V_028A90_BOTTOM_OF_PIPE_TS, 0,
6424 EOP_DST_SEL_MEM,
6425 EOP_DATA_SEL_VALUE_32BIT,
6426 va, marker,
6427 cmd_buffer->gfx9_eop_bug_va);
6428 }
6429
6430 assert(cmd_buffer->cs->cdw <= cdw_max);
6431 }