projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: destroy the base object if VkAllocateCommandBuffers() failed
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 bool src_render_loop,
58 VkImageLayout dst_layout,
59 bool dst_render_loop,
60 uint32_t src_family,
61 uint32_t dst_family,
62 const VkImageSubresourceRange *range,
63 struct radv_sample_locations_state *sample_locs);
64
65 const struct radv_dynamic_state default_dynamic_state = {
66 .viewport = {
67 .count = 0,
68 },
69 .scissor = {
70 .count = 0,
71 },
72 .line_width = 1.0f,
73 .depth_bias = {
74 .bias = 0.0f,
75 .clamp = 0.0f,
76 .slope = 0.0f,
77 },
78 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
79 .depth_bounds = {
80 .min = 0.0f,
81 .max = 1.0f,
82 },
83 .stencil_compare_mask = {
84 .front = ~0u,
85 .back = ~0u,
86 },
87 .stencil_write_mask = {
88 .front = ~0u,
89 .back = ~0u,
90 },
91 .stencil_reference = {
92 .front = 0u,
93 .back = 0u,
94 },
95 .line_stipple = {
96 .factor = 0u,
97 .pattern = 0u,
98 },
99 .cull_mode = 0u,
100 .front_face = 0u,
101 .primitive_topology = 0u,
102 };
103
104 static void
105 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
106 const struct radv_dynamic_state *src)
107 {
108 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
109 uint32_t copy_mask = src->mask;
110 uint32_t dest_mask = 0;
111
112 dest->discard_rectangle.count = src->discard_rectangle.count;
113 dest->sample_location.count = src->sample_location.count;
114
115 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
116 if (dest->viewport.count != src->viewport.count) {
117 dest->viewport.count = src->viewport.count;
118 dest_mask |= RADV_DYNAMIC_VIEWPORT;
119 }
120
121 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
122 src->viewport.count * sizeof(VkViewport))) {
123 typed_memcpy(dest->viewport.viewports,
124 src->viewport.viewports,
125 src->viewport.count);
126 dest_mask |= RADV_DYNAMIC_VIEWPORT;
127 }
128 }
129
130 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
131 if (dest->scissor.count != src->scissor.count) {
132 dest->scissor.count = src->scissor.count;
133 dest_mask |= RADV_DYNAMIC_SCISSOR;
134 }
135
136 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
137 src->scissor.count * sizeof(VkRect2D))) {
138 typed_memcpy(dest->scissor.scissors,
139 src->scissor.scissors, src->scissor.count);
140 dest_mask |= RADV_DYNAMIC_SCISSOR;
141 }
142 }
143
144 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
145 if (dest->line_width != src->line_width) {
146 dest->line_width = src->line_width;
147 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
148 }
149 }
150
151 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
152 if (memcmp(&dest->depth_bias, &src->depth_bias,
153 sizeof(src->depth_bias))) {
154 dest->depth_bias = src->depth_bias;
155 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
156 }
157 }
158
159 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
160 if (memcmp(&dest->blend_constants, &src->blend_constants,
161 sizeof(src->blend_constants))) {
162 typed_memcpy(dest->blend_constants,
163 src->blend_constants, 4);
164 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
165 }
166 }
167
168 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
169 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
170 sizeof(src->depth_bounds))) {
171 dest->depth_bounds = src->depth_bounds;
172 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
173 }
174 }
175
176 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
177 if (memcmp(&dest->stencil_compare_mask,
178 &src->stencil_compare_mask,
179 sizeof(src->stencil_compare_mask))) {
180 dest->stencil_compare_mask = src->stencil_compare_mask;
181 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
182 }
183 }
184
185 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
186 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
187 sizeof(src->stencil_write_mask))) {
188 dest->stencil_write_mask = src->stencil_write_mask;
189 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
190 }
191 }
192
193 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
194 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
195 sizeof(src->stencil_reference))) {
196 dest->stencil_reference = src->stencil_reference;
197 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
198 }
199 }
200
201 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
202 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
203 src->discard_rectangle.count * sizeof(VkRect2D))) {
204 typed_memcpy(dest->discard_rectangle.rectangles,
205 src->discard_rectangle.rectangles,
206 src->discard_rectangle.count);
207 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
208 }
209 }
210
211 if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
212 if (dest->sample_location.per_pixel != src->sample_location.per_pixel ||
213 dest->sample_location.grid_size.width != src->sample_location.grid_size.width ||
214 dest->sample_location.grid_size.height != src->sample_location.grid_size.height ||
215 memcmp(&dest->sample_location.locations,
216 &src->sample_location.locations,
217 src->sample_location.count * sizeof(VkSampleLocationEXT))) {
218 dest->sample_location.per_pixel = src->sample_location.per_pixel;
219 dest->sample_location.grid_size = src->sample_location.grid_size;
220 typed_memcpy(dest->sample_location.locations,
221 src->sample_location.locations,
222 src->sample_location.count);
223 dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
224 }
225 }
226
227 if (copy_mask & RADV_DYNAMIC_LINE_STIPPLE) {
228 if (memcmp(&dest->line_stipple, &src->line_stipple,
229 sizeof(src->line_stipple))) {
230 dest->line_stipple = src->line_stipple;
231 dest_mask |= RADV_DYNAMIC_LINE_STIPPLE;
232 }
233 }
234
235 if (copy_mask & RADV_DYNAMIC_CULL_MODE) {
236 if (dest->cull_mode != src->cull_mode) {
237 dest->cull_mode = src->cull_mode;
238 dest_mask |= RADV_DYNAMIC_CULL_MODE;
239 }
240 }
241
242 if (copy_mask & RADV_DYNAMIC_FRONT_FACE) {
243 if (dest->front_face != src->front_face) {
244 dest->front_face = src->front_face;
245 dest_mask |= RADV_DYNAMIC_FRONT_FACE;
246 }
247 }
248
249 if (copy_mask & RADV_DYNAMIC_PRIMITIVE_TOPOLOGY) {
250 if (dest->primitive_topology != src->primitive_topology) {
251 dest->primitive_topology = src->primitive_topology;
252 dest_mask |= RADV_DYNAMIC_PRIMITIVE_TOPOLOGY;
253 }
254 }
255
256 if (copy_mask & RADV_DYNAMIC_DEPTH_TEST_ENABLE) {
257 if (dest->depth_test_enable != src->depth_test_enable) {
258 dest->depth_test_enable = src->depth_test_enable;
259 dest_mask |= RADV_DYNAMIC_DEPTH_TEST_ENABLE;
260 }
261 }
262
263 if (copy_mask & RADV_DYNAMIC_DEPTH_WRITE_ENABLE) {
264 if (dest->depth_write_enable != src->depth_write_enable) {
265 dest->depth_write_enable = src->depth_write_enable;
266 dest_mask |= RADV_DYNAMIC_DEPTH_WRITE_ENABLE;
267 }
268 }
269
270 if (copy_mask & RADV_DYNAMIC_DEPTH_COMPARE_OP) {
271 if (dest->depth_compare_op != src->depth_compare_op) {
272 dest->depth_compare_op = src->depth_compare_op;
273 dest_mask |= RADV_DYNAMIC_DEPTH_COMPARE_OP;
274 }
275 }
276
277 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE) {
278 if (dest->depth_bounds_test_enable != src->depth_bounds_test_enable) {
279 dest->depth_bounds_test_enable = src->depth_bounds_test_enable;
280 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE;
281 }
282 }
283
284 if (copy_mask & RADV_DYNAMIC_STENCIL_TEST_ENABLE) {
285 if (dest->stencil_test_enable != src->stencil_test_enable) {
286 dest->stencil_test_enable = src->stencil_test_enable;
287 dest_mask |= RADV_DYNAMIC_STENCIL_TEST_ENABLE;
288 }
289 }
290
291 if (copy_mask & RADV_DYNAMIC_STENCIL_OP) {
292 if (memcmp(&dest->stencil_op, &src->stencil_op,
293 sizeof(src->stencil_op))) {
294 dest->stencil_op = src->stencil_op;
295 dest_mask |= RADV_DYNAMIC_STENCIL_OP;
296 }
297 }
298
299 cmd_buffer->state.dirty |= dest_mask;
300 }
301
302 static void
303 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
304 struct radv_pipeline *pipeline)
305 {
306 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
307 struct radv_shader_info *info;
308
309 if (!pipeline->streamout_shader ||
310 cmd_buffer->device->physical_device->use_ngg_streamout)
311 return;
312
313 info = &pipeline->streamout_shader->info;
314 for (int i = 0; i < MAX_SO_BUFFERS; i++)
315 so->stride_in_dw[i] = info->so.strides[i];
316
317 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
318 }
319
320 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
321 {
322 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
323 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
324 }
325
326 enum ring_type radv_queue_family_to_ring(int f) {
327 switch (f) {
328 case RADV_QUEUE_GENERAL:
329 return RING_GFX;
330 case RADV_QUEUE_COMPUTE:
331 return RING_COMPUTE;
332 case RADV_QUEUE_TRANSFER:
333 return RING_DMA;
334 default:
335 unreachable("Unknown queue family");
336 }
337 }
338
339 static void
340 radv_destroy_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
341 {
342 list_del(&cmd_buffer->pool_link);
343
344 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
345 &cmd_buffer->upload.list, list) {
346 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
347 list_del(&up->list);
348 free(up);
349 }
350
351 if (cmd_buffer->upload.upload_bo)
352 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
353
354 if (cmd_buffer->cs)
355 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
356
357 for (unsigned i = 0; i < MAX_BIND_POINTS; i++)
358 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
359
360 vk_object_base_finish(&cmd_buffer->base);
361 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
362 }
363
364 static VkResult radv_create_cmd_buffer(
365 struct radv_device * device,
366 struct radv_cmd_pool * pool,
367 VkCommandBufferLevel level,
368 VkCommandBuffer* pCommandBuffer)
369 {
370 struct radv_cmd_buffer *cmd_buffer;
371 unsigned ring;
372 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
373 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
374 if (cmd_buffer == NULL)
375 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
376
377 vk_object_base_init(&device->vk, &cmd_buffer->base,
378 VK_OBJECT_TYPE_COMMAND_BUFFER);
379
380 cmd_buffer->device = device;
381 cmd_buffer->pool = pool;
382 cmd_buffer->level = level;
383
384 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
385 cmd_buffer->queue_family_index = pool->queue_family_index;
386
387 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
388
389 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
390 if (!cmd_buffer->cs) {
391 radv_destroy_cmd_buffer(cmd_buffer);
392 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
393 }
394
395 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
396
397 list_inithead(&cmd_buffer->upload.list);
398
399 return VK_SUCCESS;
400 }
401
402 static VkResult
403 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
404 {
405 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
406
407 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
408 &cmd_buffer->upload.list, list) {
409 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
410 list_del(&up->list);
411 free(up);
412 }
413
414 cmd_buffer->push_constant_stages = 0;
415 cmd_buffer->scratch_size_per_wave_needed = 0;
416 cmd_buffer->scratch_waves_wanted = 0;
417 cmd_buffer->compute_scratch_size_per_wave_needed = 0;
418 cmd_buffer->compute_scratch_waves_wanted = 0;
419 cmd_buffer->esgs_ring_size_needed = 0;
420 cmd_buffer->gsvs_ring_size_needed = 0;
421 cmd_buffer->tess_rings_needed = false;
422 cmd_buffer->gds_needed = false;
423 cmd_buffer->gds_oa_needed = false;
424 cmd_buffer->sample_positions_needed = false;
425
426 if (cmd_buffer->upload.upload_bo)
427 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
428 cmd_buffer->upload.upload_bo);
429 cmd_buffer->upload.offset = 0;
430
431 cmd_buffer->record_result = VK_SUCCESS;
432
433 memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
434
435 for (unsigned i = 0; i < MAX_BIND_POINTS; i++) {
436 cmd_buffer->descriptors[i].dirty = 0;
437 cmd_buffer->descriptors[i].valid = 0;
438 cmd_buffer->descriptors[i].push_dirty = false;
439 }
440
441 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
442 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
443 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
444 unsigned fence_offset, eop_bug_offset;
445 void *fence_ptr;
446
447 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
448 &fence_ptr);
449
450 cmd_buffer->gfx9_fence_va =
451 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
452 cmd_buffer->gfx9_fence_va += fence_offset;
453
454 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
455 /* Allocate a buffer for the EOP bug on GFX9. */
456 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
457 &eop_bug_offset, &fence_ptr);
458 cmd_buffer->gfx9_eop_bug_va =
459 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
460 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
461 }
462 }
463
464 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
465
466 return cmd_buffer->record_result;
467 }
468
469 static bool
470 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
471 uint64_t min_needed)
472 {
473 uint64_t new_size;
474 struct radeon_winsys_bo *bo;
475 struct radv_cmd_buffer_upload *upload;
476 struct radv_device *device = cmd_buffer->device;
477
478 new_size = MAX2(min_needed, 16 * 1024);
479 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
480
481 bo = device->ws->buffer_create(device->ws,
482 new_size, 4096,
483 RADEON_DOMAIN_GTT,
484 RADEON_FLAG_CPU_ACCESS|
485 RADEON_FLAG_NO_INTERPROCESS_SHARING |
486 RADEON_FLAG_32BIT,
487 RADV_BO_PRIORITY_UPLOAD_BUFFER);
488
489 if (!bo) {
490 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
491 return false;
492 }
493
494 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
495 if (cmd_buffer->upload.upload_bo) {
496 upload = malloc(sizeof(*upload));
497
498 if (!upload) {
499 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
500 device->ws->buffer_destroy(bo);
501 return false;
502 }
503
504 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
505 list_add(&upload->list, &cmd_buffer->upload.list);
506 }
507
508 cmd_buffer->upload.upload_bo = bo;
509 cmd_buffer->upload.size = new_size;
510 cmd_buffer->upload.offset = 0;
511 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
512
513 if (!cmd_buffer->upload.map) {
514 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
515 return false;
516 }
517
518 return true;
519 }
520
521 bool
522 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
523 unsigned size,
524 unsigned alignment,
525 unsigned *out_offset,
526 void **ptr)
527 {
528 assert(util_is_power_of_two_nonzero(alignment));
529
530 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
531 if (offset + size > cmd_buffer->upload.size) {
532 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
533 return false;
534 offset = 0;
535 }
536
537 *out_offset = offset;
538 *ptr = cmd_buffer->upload.map + offset;
539
540 cmd_buffer->upload.offset = offset + size;
541 return true;
542 }
543
544 bool
545 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
546 unsigned size, unsigned alignment,
547 const void *data, unsigned *out_offset)
548 {
549 uint8_t *ptr;
550
551 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
552 out_offset, (void **)&ptr))
553 return false;
554
555 if (ptr)
556 memcpy(ptr, data, size);
557
558 return true;
559 }
560
561 static void
562 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
563 unsigned count, const uint32_t *data)
564 {
565 struct radeon_cmdbuf *cs = cmd_buffer->cs;
566
567 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
568
569 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
570 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
571 S_370_WR_CONFIRM(1) |
572 S_370_ENGINE_SEL(V_370_ME));
573 radeon_emit(cs, va);
574 radeon_emit(cs, va >> 32);
575 radeon_emit_array(cs, data, count);
576 }
577
578 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
579 {
580 struct radv_device *device = cmd_buffer->device;
581 struct radeon_cmdbuf *cs = cmd_buffer->cs;
582 uint64_t va;
583
584 va = radv_buffer_get_va(device->trace_bo);
585 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
586 va += 4;
587
588 ++cmd_buffer->state.trace_id;
589 radv_emit_write_data_packet(cmd_buffer, va, 1,
590 &cmd_buffer->state.trace_id);
591
592 radeon_check_space(cmd_buffer->device->ws, cs, 2);
593
594 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
595 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
596 }
597
598 static void
599 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
600 enum radv_cmd_flush_bits flags)
601 {
602 if (unlikely(cmd_buffer->device->thread_trace_bo)) {
603 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
604 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_THREAD_TRACE_MARKER) | EVENT_INDEX(0));
605 }
606
607 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
608 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
609 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
610
611 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
612
613 /* Force wait for graphics or compute engines to be idle. */
614 si_cs_emit_cache_flush(cmd_buffer->cs,
615 cmd_buffer->device->physical_device->rad_info.chip_class,
616 &cmd_buffer->gfx9_fence_idx,
617 cmd_buffer->gfx9_fence_va,
618 radv_cmd_buffer_uses_mec(cmd_buffer),
619 flags, cmd_buffer->gfx9_eop_bug_va);
620 }
621
622 if (unlikely(cmd_buffer->device->trace_bo))
623 radv_cmd_buffer_trace_emit(cmd_buffer);
624 }
625
626 static void
627 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
628 struct radv_pipeline *pipeline, enum ring_type ring)
629 {
630 struct radv_device *device = cmd_buffer->device;
631 uint32_t data[2];
632 uint64_t va;
633
634 va = radv_buffer_get_va(device->trace_bo);
635
636 switch (ring) {
637 case RING_GFX:
638 va += 8;
639 break;
640 case RING_COMPUTE:
641 va += 16;
642 break;
643 default:
644 assert(!"invalid ring type");
645 }
646
647 uint64_t pipeline_address = (uintptr_t)pipeline;
648 data[0] = pipeline_address;
649 data[1] = pipeline_address >> 32;
650
651 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
652 }
653
654 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
655 VkPipelineBindPoint bind_point,
656 struct radv_descriptor_set *set,
657 unsigned idx)
658 {
659 struct radv_descriptor_state *descriptors_state =
660 radv_get_descriptors_state(cmd_buffer, bind_point);
661
662 descriptors_state->sets[idx] = set;
663
664 descriptors_state->valid |= (1u << idx); /* active descriptors */
665 descriptors_state->dirty |= (1u << idx);
666 }
667
668 static void
669 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
670 VkPipelineBindPoint bind_point)
671 {
672 struct radv_descriptor_state *descriptors_state =
673 radv_get_descriptors_state(cmd_buffer, bind_point);
674 struct radv_device *device = cmd_buffer->device;
675 uint32_t data[MAX_SETS * 2] = {};
676 uint64_t va;
677 unsigned i;
678 va = radv_buffer_get_va(device->trace_bo) + 24;
679
680 for_each_bit(i, descriptors_state->valid) {
681 struct radv_descriptor_set *set = descriptors_state->sets[i];
682 data[i * 2] = (uint64_t)(uintptr_t)set;
683 data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
684 }
685
686 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
687 }
688
689 struct radv_userdata_info *
690 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
691 gl_shader_stage stage,
692 int idx)
693 {
694 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
695 return &shader->info.user_sgprs_locs.shader_data[idx];
696 }
697
698 static void
699 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
700 struct radv_pipeline *pipeline,
701 gl_shader_stage stage,
702 int idx, uint64_t va)
703 {
704 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
705 uint32_t base_reg = pipeline->user_data_0[stage];
706 if (loc->sgpr_idx == -1)
707 return;
708
709 assert(loc->num_sgprs == 1);
710
711 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
712 base_reg + loc->sgpr_idx * 4, va, false);
713 }
714
715 static void
716 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
717 struct radv_pipeline *pipeline,
718 struct radv_descriptor_state *descriptors_state,
719 gl_shader_stage stage)
720 {
721 struct radv_device *device = cmd_buffer->device;
722 struct radeon_cmdbuf *cs = cmd_buffer->cs;
723 uint32_t sh_base = pipeline->user_data_0[stage];
724 struct radv_userdata_locations *locs =
725 &pipeline->shaders[stage]->info.user_sgprs_locs;
726 unsigned mask = locs->descriptor_sets_enabled;
727
728 mask &= descriptors_state->dirty & descriptors_state->valid;
729
730 while (mask) {
731 int start, count;
732
733 u_bit_scan_consecutive_range(&mask, &start, &count);
734
735 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
736 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
737
738 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
739 for (int i = 0; i < count; i++) {
740 struct radv_descriptor_set *set =
741 descriptors_state->sets[start + i];
742
743 radv_emit_shader_pointer_body(device, cs, set->va, true);
744 }
745 }
746 }
747
748 /**
749 * Convert the user sample locations to hardware sample locations (the values
750 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
751 */
752 static void
753 radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
754 uint32_t x, uint32_t y, VkOffset2D *sample_locs)
755 {
756 uint32_t x_offset = x % state->grid_size.width;
757 uint32_t y_offset = y % state->grid_size.height;
758 uint32_t num_samples = (uint32_t)state->per_pixel;
759 VkSampleLocationEXT *user_locs;
760 uint32_t pixel_offset;
761
762 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
763
764 assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
765 user_locs = &state->locations[pixel_offset];
766
767 for (uint32_t i = 0; i < num_samples; i++) {
768 float shifted_pos_x = user_locs[i].x - 0.5;
769 float shifted_pos_y = user_locs[i].y - 0.5;
770
771 int32_t scaled_pos_x = floorf(shifted_pos_x * 16);
772 int32_t scaled_pos_y = floorf(shifted_pos_y * 16);
773
774 sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
775 sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
776 }
777 }
778
779 /**
780 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
781 * locations.
782 */
783 static void
784 radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
785 uint32_t *sample_locs_pixel)
786 {
787 for (uint32_t i = 0; i < num_samples; i++) {
788 uint32_t sample_reg_idx = i / 4;
789 uint32_t sample_loc_idx = i % 4;
790 int32_t pos_x = sample_locs[i].x;
791 int32_t pos_y = sample_locs[i].y;
792
793 uint32_t shift_x = 8 * sample_loc_idx;
794 uint32_t shift_y = shift_x + 4;
795
796 sample_locs_pixel[sample_reg_idx] |= (pos_x & 0xf) << shift_x;
797 sample_locs_pixel[sample_reg_idx] |= (pos_y & 0xf) << shift_y;
798 }
799 }
800
801 /**
802 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
803 * sample locations.
804 */
805 static uint64_t
806 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer,
807 VkOffset2D *sample_locs,
808 uint32_t num_samples)
809 {
810 uint32_t centroid_priorities[num_samples];
811 uint32_t sample_mask = num_samples - 1;
812 uint32_t distances[num_samples];
813 uint64_t centroid_priority = 0;
814
815 /* Compute the distances from center for each sample. */
816 for (int i = 0; i < num_samples; i++) {
817 distances[i] = (sample_locs[i].x * sample_locs[i].x) +
818 (sample_locs[i].y * sample_locs[i].y);
819 }
820
821 /* Compute the centroid priorities by looking at the distances array. */
822 for (int i = 0; i < num_samples; i++) {
823 uint32_t min_idx = 0;
824
825 for (int j = 1; j < num_samples; j++) {
826 if (distances[j] < distances[min_idx])
827 min_idx = j;
828 }
829
830 centroid_priorities[i] = min_idx;
831 distances[min_idx] = 0xffffffff;
832 }
833
834 /* Compute the final centroid priority. */
835 for (int i = 0; i < 8; i++) {
836 centroid_priority |=
837 centroid_priorities[i & sample_mask] << (i * 4);
838 }
839
840 return centroid_priority << 32 | centroid_priority;
841 }
842
843 /**
844 * Emit the sample locations that are specified with VK_EXT_sample_locations.
845 */
846 static void
847 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
848 {
849 struct radv_sample_locations_state *sample_location =
850 &cmd_buffer->state.dynamic.sample_location;
851 uint32_t num_samples = (uint32_t)sample_location->per_pixel;
852 struct radeon_cmdbuf *cs = cmd_buffer->cs;
853 uint32_t sample_locs_pixel[4][2] = {};
854 VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
855 uint32_t max_sample_dist = 0;
856 uint64_t centroid_priority;
857
858 if (!cmd_buffer->state.dynamic.sample_location.count)
859 return;
860
861 /* Convert the user sample locations to hardware sample locations. */
862 radv_convert_user_sample_locs(sample_location, 0, 0, sample_locs[0]);
863 radv_convert_user_sample_locs(sample_location, 1, 0, sample_locs[1]);
864 radv_convert_user_sample_locs(sample_location, 0, 1, sample_locs[2]);
865 radv_convert_user_sample_locs(sample_location, 1, 1, sample_locs[3]);
866
867 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
868 for (uint32_t i = 0; i < 4; i++) {
869 radv_compute_sample_locs_pixel(num_samples, sample_locs[i],
870 sample_locs_pixel[i]);
871 }
872
873 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
874 centroid_priority =
875 radv_compute_centroid_priority(cmd_buffer, sample_locs[0],
876 num_samples);
877
878 /* Compute the maximum sample distance from the specified locations. */
879 for (unsigned i = 0; i < 4; ++i) {
880 for (uint32_t j = 0; j < num_samples; j++) {
881 VkOffset2D offset = sample_locs[i][j];
882 max_sample_dist = MAX2(max_sample_dist,
883 MAX2(abs(offset.x), abs(offset.y)));
884 }
885 }
886
887 /* Emit the specified user sample locations. */
888 switch (num_samples) {
889 case 2:
890 case 4:
891 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
892 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
893 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
894 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
895 break;
896 case 8:
897 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
898 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
899 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
900 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
901 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs_pixel[0][1]);
902 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs_pixel[1][1]);
903 radeon_set_context_reg(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs_pixel[2][1]);
904 radeon_set_context_reg(cs, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs_pixel[3][1]);
905 break;
906 default:
907 unreachable("invalid number of samples");
908 }
909
910 /* Emit the maximum sample distance and the centroid priority. */
911 radeon_set_context_reg_rmw(cs, R_028BE0_PA_SC_AA_CONFIG,
912 S_028BE0_MAX_SAMPLE_DIST(max_sample_dist),
913 ~C_028BE0_MAX_SAMPLE_DIST);
914
915 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
916 radeon_emit(cs, centroid_priority);
917 radeon_emit(cs, centroid_priority >> 32);
918
919 /* GFX9: Flush DFSM when the AA mode changes. */
920 if (cmd_buffer->device->dfsm_allowed) {
921 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
922 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
923 }
924
925 cmd_buffer->state.context_roll_without_scissor_emitted = true;
926 }
927
928 static void
929 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
930 struct radv_pipeline *pipeline,
931 gl_shader_stage stage,
932 int idx, int count, uint32_t *values)
933 {
934 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
935 uint32_t base_reg = pipeline->user_data_0[stage];
936 if (loc->sgpr_idx == -1)
937 return;
938
939 assert(loc->num_sgprs == count);
940
941 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
942 radeon_emit_array(cmd_buffer->cs, values, count);
943 }
944
945 static void
946 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
947 struct radv_pipeline *pipeline)
948 {
949 int num_samples = pipeline->graphics.ms.num_samples;
950 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
951
952 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.needs_sample_positions)
953 cmd_buffer->sample_positions_needed = true;
954
955 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
956 return;
957
958 radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
959
960 cmd_buffer->state.context_roll_without_scissor_emitted = true;
961 }
962
963 static void
964 radv_update_binning_state(struct radv_cmd_buffer *cmd_buffer,
965 struct radv_pipeline *pipeline)
966 {
967 const struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
968
969
970 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
971 return;
972
973 if (old_pipeline &&
974 old_pipeline->graphics.binning.pa_sc_binner_cntl_0 == pipeline->graphics.binning.pa_sc_binner_cntl_0 &&
975 old_pipeline->graphics.binning.db_dfsm_control == pipeline->graphics.binning.db_dfsm_control)
976 return;
977
978 bool binning_flush = false;
979 if (cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA12 ||
980 cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA20 ||
981 cmd_buffer->device->physical_device->rad_info.family == CHIP_RAVEN2 ||
982 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
983 binning_flush = !old_pipeline ||
984 G_028C44_BINNING_MODE(old_pipeline->graphics.binning.pa_sc_binner_cntl_0) !=
985 G_028C44_BINNING_MODE(pipeline->graphics.binning.pa_sc_binner_cntl_0);
986 }
987
988 radeon_set_context_reg(cmd_buffer->cs, R_028C44_PA_SC_BINNER_CNTL_0,
989 pipeline->graphics.binning.pa_sc_binner_cntl_0 |
990 S_028C44_FLUSH_ON_BINNING_TRANSITION(!!binning_flush));
991
992 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
993 radeon_set_context_reg(cmd_buffer->cs, R_028038_DB_DFSM_CONTROL,
994 pipeline->graphics.binning.db_dfsm_control);
995 } else {
996 radeon_set_context_reg(cmd_buffer->cs, R_028060_DB_DFSM_CONTROL,
997 pipeline->graphics.binning.db_dfsm_control);
998 }
999
1000 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1001 }
1002
1003
1004 static void
1005 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
1006 struct radv_shader_variant *shader)
1007 {
1008 uint64_t va;
1009
1010 if (!shader)
1011 return;
1012
1013 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
1014
1015 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
1016 }
1017
1018 static void
1019 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
1020 struct radv_pipeline *pipeline,
1021 bool vertex_stage_only)
1022 {
1023 struct radv_cmd_state *state = &cmd_buffer->state;
1024 uint32_t mask = state->prefetch_L2_mask;
1025
1026 if (vertex_stage_only) {
1027 /* Fast prefetch path for starting draws as soon as possible.
1028 */
1029 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
1030 RADV_PREFETCH_VBO_DESCRIPTORS);
1031 }
1032
1033 if (mask & RADV_PREFETCH_VS)
1034 radv_emit_shader_prefetch(cmd_buffer,
1035 pipeline->shaders[MESA_SHADER_VERTEX]);
1036
1037 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
1038 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
1039
1040 if (mask & RADV_PREFETCH_TCS)
1041 radv_emit_shader_prefetch(cmd_buffer,
1042 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
1043
1044 if (mask & RADV_PREFETCH_TES)
1045 radv_emit_shader_prefetch(cmd_buffer,
1046 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
1047
1048 if (mask & RADV_PREFETCH_GS) {
1049 radv_emit_shader_prefetch(cmd_buffer,
1050 pipeline->shaders[MESA_SHADER_GEOMETRY]);
1051 if (radv_pipeline_has_gs_copy_shader(pipeline))
1052 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
1053 }
1054
1055 if (mask & RADV_PREFETCH_PS)
1056 radv_emit_shader_prefetch(cmd_buffer,
1057 pipeline->shaders[MESA_SHADER_FRAGMENT]);
1058
1059 state->prefetch_L2_mask &= ~mask;
1060 }
1061
1062 static void
1063 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
1064 {
1065 if (!cmd_buffer->device->physical_device->rad_info.rbplus_allowed)
1066 return;
1067
1068 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1069 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1070
1071 unsigned sx_ps_downconvert = 0;
1072 unsigned sx_blend_opt_epsilon = 0;
1073 unsigned sx_blend_opt_control = 0;
1074
1075 if (!cmd_buffer->state.attachments || !subpass)
1076 return;
1077
1078 for (unsigned i = 0; i < subpass->color_count; ++i) {
1079 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1080 /* We don't set the DISABLE bits, because the HW can't have holes,
1081 * so the SPI color format is set to 32-bit 1-component. */
1082 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1083 continue;
1084 }
1085
1086 int idx = subpass->color_attachments[i].attachment;
1087 struct radv_color_buffer_info *cb = &cmd_buffer->state.attachments[idx].cb;
1088
1089 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
1090 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
1091 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
1092 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
1093
1094 bool has_alpha, has_rgb;
1095
1096 /* Set if RGB and A are present. */
1097 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
1098
1099 if (format == V_028C70_COLOR_8 ||
1100 format == V_028C70_COLOR_16 ||
1101 format == V_028C70_COLOR_32)
1102 has_rgb = !has_alpha;
1103 else
1104 has_rgb = true;
1105
1106 /* Check the colormask and export format. */
1107 if (!(colormask & 0x7))
1108 has_rgb = false;
1109 if (!(colormask & 0x8))
1110 has_alpha = false;
1111
1112 if (spi_format == V_028714_SPI_SHADER_ZERO) {
1113 has_rgb = false;
1114 has_alpha = false;
1115 }
1116
1117 /* Disable value checking for disabled channels. */
1118 if (!has_rgb)
1119 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1120 if (!has_alpha)
1121 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1122
1123 /* Enable down-conversion for 32bpp and smaller formats. */
1124 switch (format) {
1125 case V_028C70_COLOR_8:
1126 case V_028C70_COLOR_8_8:
1127 case V_028C70_COLOR_8_8_8_8:
1128 /* For 1 and 2-channel formats, use the superset thereof. */
1129 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
1130 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1131 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1132 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
1133 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
1134 }
1135 break;
1136
1137 case V_028C70_COLOR_5_6_5:
1138 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1139 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
1140 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
1141 }
1142 break;
1143
1144 case V_028C70_COLOR_1_5_5_5:
1145 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1146 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
1147 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
1148 }
1149 break;
1150
1151 case V_028C70_COLOR_4_4_4_4:
1152 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1153 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
1154 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
1155 }
1156 break;
1157
1158 case V_028C70_COLOR_32:
1159 if (swap == V_028C70_SWAP_STD &&
1160 spi_format == V_028714_SPI_SHADER_32_R)
1161 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1162 else if (swap == V_028C70_SWAP_ALT_REV &&
1163 spi_format == V_028714_SPI_SHADER_32_AR)
1164 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
1165 break;
1166
1167 case V_028C70_COLOR_16:
1168 case V_028C70_COLOR_16_16:
1169 /* For 1-channel formats, use the superset thereof. */
1170 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
1171 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
1172 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1173 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1174 if (swap == V_028C70_SWAP_STD ||
1175 swap == V_028C70_SWAP_STD_REV)
1176 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
1177 else
1178 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
1179 }
1180 break;
1181
1182 case V_028C70_COLOR_10_11_11:
1183 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1184 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
1185 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
1186 }
1187 break;
1188
1189 case V_028C70_COLOR_2_10_10_10:
1190 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1191 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
1192 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
1193 }
1194 break;
1195 }
1196 }
1197
1198 /* Do not set the DISABLE bits for the unused attachments, as that
1199 * breaks dual source blending in SkQP and does not seem to improve
1200 * performance. */
1201
1202 if (sx_ps_downconvert == cmd_buffer->state.last_sx_ps_downconvert &&
1203 sx_blend_opt_epsilon == cmd_buffer->state.last_sx_blend_opt_epsilon &&
1204 sx_blend_opt_control == cmd_buffer->state.last_sx_blend_opt_control)
1205 return;
1206
1207 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
1208 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
1209 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
1210 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
1211
1212 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1213
1214 cmd_buffer->state.last_sx_ps_downconvert = sx_ps_downconvert;
1215 cmd_buffer->state.last_sx_blend_opt_epsilon = sx_blend_opt_epsilon;
1216 cmd_buffer->state.last_sx_blend_opt_control = sx_blend_opt_control;
1217 }
1218
1219 static void
1220 radv_emit_batch_break_on_new_ps(struct radv_cmd_buffer *cmd_buffer)
1221 {
1222 if (!cmd_buffer->device->pbb_allowed)
1223 return;
1224
1225 struct radv_binning_settings settings =
1226 radv_get_binning_settings(cmd_buffer->device->physical_device);
1227 bool break_for_new_ps =
1228 (!cmd_buffer->state.emitted_pipeline ||
1229 cmd_buffer->state.emitted_pipeline->shaders[MESA_SHADER_FRAGMENT] !=
1230 cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT]) &&
1231 (settings.context_states_per_bin > 1 ||
1232 settings.persistent_states_per_bin > 1);
1233 bool break_for_new_cb_target_mask =
1234 (!cmd_buffer->state.emitted_pipeline ||
1235 cmd_buffer->state.emitted_pipeline->graphics.cb_target_mask !=
1236 cmd_buffer->state.pipeline->graphics.cb_target_mask) &&
1237 settings.context_states_per_bin > 1;
1238
1239 if (!break_for_new_ps && !break_for_new_cb_target_mask)
1240 return;
1241
1242 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1243 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1244 }
1245
1246 static void
1247 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1248 {
1249 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1250
1251 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1252 return;
1253
1254 radv_update_multisample_state(cmd_buffer, pipeline);
1255 radv_update_binning_state(cmd_buffer, pipeline);
1256
1257 cmd_buffer->scratch_size_per_wave_needed = MAX2(cmd_buffer->scratch_size_per_wave_needed,
1258 pipeline->scratch_bytes_per_wave);
1259 cmd_buffer->scratch_waves_wanted = MAX2(cmd_buffer->scratch_waves_wanted,
1260 pipeline->max_waves);
1261
1262 if (!cmd_buffer->state.emitted_pipeline ||
1263 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1264 pipeline->graphics.can_use_guardband)
1265 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1266
1267 if (!cmd_buffer->state.emitted_pipeline ||
1268 cmd_buffer->state.emitted_pipeline->graphics.pa_su_sc_mode_cntl !=
1269 pipeline->graphics.pa_su_sc_mode_cntl)
1270 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_CULL_MODE |
1271 RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE;
1272
1273 if (!cmd_buffer->state.emitted_pipeline)
1274 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY;
1275
1276 if (!cmd_buffer->state.emitted_pipeline ||
1277 cmd_buffer->state.emitted_pipeline->graphics.db_depth_control !=
1278 pipeline->graphics.db_depth_control)
1279 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE |
1280 RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE |
1281 RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP |
1282 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE |
1283 RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE |
1284 RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP;
1285
1286 if (!cmd_buffer->state.emitted_pipeline)
1287 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP;
1288
1289 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
1290
1291 if (!cmd_buffer->state.emitted_pipeline ||
1292 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
1293 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
1294 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
1295 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
1296 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
1297 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1298 }
1299
1300 radv_emit_batch_break_on_new_ps(cmd_buffer);
1301
1302 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
1303 if (!pipeline->shaders[i])
1304 continue;
1305
1306 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1307 pipeline->shaders[i]->bo);
1308 }
1309
1310 if (radv_pipeline_has_gs_copy_shader(pipeline))
1311 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1312 pipeline->gs_copy_shader->bo);
1313
1314 if (unlikely(cmd_buffer->device->trace_bo))
1315 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1316
1317 cmd_buffer->state.emitted_pipeline = pipeline;
1318
1319 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1320 }
1321
1322 static void
1323 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1324 {
1325 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1326 cmd_buffer->state.dynamic.viewport.viewports);
1327 }
1328
1329 static void
1330 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1331 {
1332 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1333
1334 si_write_scissors(cmd_buffer->cs, 0, count,
1335 cmd_buffer->state.dynamic.scissor.scissors,
1336 cmd_buffer->state.dynamic.viewport.viewports,
1337 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1338
1339 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1340 }
1341
1342 static void
1343 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1344 {
1345 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1346 return;
1347
1348 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1349 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1350 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1351 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1352 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1353 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1354 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1355 }
1356 }
1357
1358 static void
1359 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1360 {
1361 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1362
1363 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1364 S_028A08_WIDTH(CLAMP(width, 0, 0xFFFF)));
1365 }
1366
1367 static void
1368 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1369 {
1370 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1371
1372 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1373 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1374 }
1375
1376 static void
1377 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1378 {
1379 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1380
1381 radeon_set_context_reg_seq(cmd_buffer->cs,
1382 R_028430_DB_STENCILREFMASK, 2);
1383 radeon_emit(cmd_buffer->cs,
1384 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1385 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1386 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1387 S_028430_STENCILOPVAL(1));
1388 radeon_emit(cmd_buffer->cs,
1389 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1390 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1391 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1392 S_028434_STENCILOPVAL_BF(1));
1393 }
1394
1395 static void
1396 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1397 {
1398 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1399
1400 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1401 fui(d->depth_bounds.min));
1402 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1403 fui(d->depth_bounds.max));
1404 }
1405
1406 static void
1407 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1408 {
1409 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1410 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1411 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1412
1413
1414 radeon_set_context_reg_seq(cmd_buffer->cs,
1415 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1416 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1417 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1418 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1419 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1420 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1421 }
1422
1423 static void
1424 radv_emit_line_stipple(struct radv_cmd_buffer *cmd_buffer)
1425 {
1426 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1427 uint32_t auto_reset_cntl = 1;
1428
1429 if (d->primitive_topology == V_008958_DI_PT_LINESTRIP)
1430 auto_reset_cntl = 2;
1431
1432 radeon_set_context_reg(cmd_buffer->cs, R_028A0C_PA_SC_LINE_STIPPLE,
1433 S_028A0C_LINE_PATTERN(d->line_stipple.pattern) |
1434 S_028A0C_REPEAT_COUNT(d->line_stipple.factor - 1) |
1435 S_028A0C_AUTO_RESET_CNTL(auto_reset_cntl));
1436 }
1437
1438 static void
1439 radv_emit_culling(struct radv_cmd_buffer *cmd_buffer, uint32_t states)
1440 {
1441 unsigned pa_su_sc_mode_cntl = cmd_buffer->state.pipeline->graphics.pa_su_sc_mode_cntl;
1442 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1443
1444 if (states & RADV_CMD_DIRTY_DYNAMIC_CULL_MODE) {
1445 pa_su_sc_mode_cntl &= C_028814_CULL_FRONT;
1446 pa_su_sc_mode_cntl |= S_028814_CULL_FRONT(!!(d->cull_mode & VK_CULL_MODE_FRONT_BIT));
1447
1448 pa_su_sc_mode_cntl &= C_028814_CULL_BACK;
1449 pa_su_sc_mode_cntl |= S_028814_CULL_BACK(!!(d->cull_mode & VK_CULL_MODE_BACK_BIT));
1450 }
1451
1452 if (states & RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE) {
1453 pa_su_sc_mode_cntl &= C_028814_FACE;
1454 pa_su_sc_mode_cntl |= S_028814_FACE(d->front_face);
1455 }
1456
1457 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
1458 pa_su_sc_mode_cntl);
1459 }
1460
1461 static void
1462 radv_emit_primitive_topology(struct radv_cmd_buffer *cmd_buffer)
1463 {
1464 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1465
1466 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1467 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
1468 cmd_buffer->cs,
1469 R_030908_VGT_PRIMITIVE_TYPE, 1,
1470 d->primitive_topology);
1471 } else {
1472 radeon_set_config_reg(cmd_buffer->cs,
1473 R_008958_VGT_PRIMITIVE_TYPE,
1474 d->primitive_topology);
1475 }
1476 }
1477
1478 static void
1479 radv_emit_depth_control(struct radv_cmd_buffer *cmd_buffer, uint32_t states)
1480 {
1481 unsigned db_depth_control = cmd_buffer->state.pipeline->graphics.db_depth_control;
1482 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1483
1484 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE) {
1485 db_depth_control &= C_028800_Z_ENABLE;
1486 db_depth_control |= S_028800_Z_ENABLE(d->depth_test_enable ? 1 : 0);
1487 }
1488
1489 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE) {
1490 db_depth_control &= C_028800_Z_WRITE_ENABLE;
1491 db_depth_control |= S_028800_Z_WRITE_ENABLE(d->depth_write_enable ? 1 : 0);
1492 }
1493
1494 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP) {
1495 db_depth_control &= C_028800_ZFUNC;
1496 db_depth_control |= S_028800_ZFUNC(d->depth_compare_op);
1497 }
1498
1499 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE) {
1500 db_depth_control &= C_028800_DEPTH_BOUNDS_ENABLE;
1501 db_depth_control |= S_028800_DEPTH_BOUNDS_ENABLE(d->depth_bounds_test_enable ? 1 : 0);
1502 }
1503
1504 if (states & RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE) {
1505 db_depth_control &= C_028800_STENCIL_ENABLE;
1506 db_depth_control |= S_028800_STENCIL_ENABLE(d->stencil_test_enable ? 1 : 0);
1507
1508 db_depth_control &= C_028800_BACKFACE_ENABLE;
1509 db_depth_control |= S_028800_BACKFACE_ENABLE(d->stencil_test_enable ? 1 : 0);
1510 }
1511
1512 if (states & RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP) {
1513 db_depth_control &= C_028800_STENCILFUNC;
1514 db_depth_control |= S_028800_STENCILFUNC(d->stencil_op.front.compare_op);
1515
1516 db_depth_control &= C_028800_STENCILFUNC_BF;
1517 db_depth_control |= S_028800_STENCILFUNC_BF(d->stencil_op.back.compare_op);
1518 }
1519
1520 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL,
1521 db_depth_control);
1522 }
1523
1524 static void
1525 radv_emit_stencil_control(struct radv_cmd_buffer *cmd_buffer)
1526 {
1527 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1528
1529 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL,
1530 S_02842C_STENCILFAIL(si_translate_stencil_op(d->stencil_op.front.fail_op)) |
1531 S_02842C_STENCILZPASS(si_translate_stencil_op(d->stencil_op.front.pass_op)) |
1532 S_02842C_STENCILZFAIL(si_translate_stencil_op(d->stencil_op.front.depth_fail_op)) |
1533 S_02842C_STENCILFAIL_BF(si_translate_stencil_op(d->stencil_op.back.fail_op)) |
1534 S_02842C_STENCILZPASS_BF(si_translate_stencil_op(d->stencil_op.back.pass_op)) |
1535 S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(d->stencil_op.back.depth_fail_op)));
1536 }
1537
1538 static void
1539 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1540 int index,
1541 struct radv_color_buffer_info *cb,
1542 struct radv_image_view *iview,
1543 VkImageLayout layout,
1544 bool in_render_loop)
1545 {
1546 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
1547 uint32_t cb_color_info = cb->cb_color_info;
1548 struct radv_image *image = iview->image;
1549
1550 if (!radv_layout_dcc_compressed(cmd_buffer->device, image, layout, in_render_loop,
1551 radv_image_queue_family_mask(image,
1552 cmd_buffer->queue_family_index,
1553 cmd_buffer->queue_family_index))) {
1554 cb_color_info &= C_028C70_DCC_ENABLE;
1555 }
1556
1557 if (!radv_layout_can_fast_clear(image, layout, in_render_loop,
1558 radv_image_queue_family_mask(image,
1559 cmd_buffer->queue_family_index,
1560 cmd_buffer->queue_family_index))) {
1561 cb_color_info &= C_028C70_COMPRESSION;
1562 }
1563
1564 if (radv_image_is_tc_compat_cmask(image) &&
1565 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1566 radv_is_dcc_decompress_pipeline(cmd_buffer))) {
1567 /* If this bit is set, the FMASK decompression operation
1568 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1569 */
1570 cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
1571 }
1572
1573 if (radv_image_has_fmask(image) &&
1574 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1575 radv_is_hw_resolve_pipeline(cmd_buffer))) {
1576 /* Make sure FMASK is enabled if it has been cleared because:
1577 *
1578 * 1) it's required for FMASK_DECOMPRESS operations to avoid
1579 * GPU hangs
1580 * 2) it's necessary for CB_RESOLVE which can read compressed
1581 * FMASK data anyways.
1582 */
1583 cb_color_info |= S_028C70_COMPRESSION(1);
1584 }
1585
1586 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1587 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1588 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1589 radeon_emit(cmd_buffer->cs, 0);
1590 radeon_emit(cmd_buffer->cs, 0);
1591 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1592 radeon_emit(cmd_buffer->cs, cb_color_info);
1593 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1594 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1595 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1596 radeon_emit(cmd_buffer->cs, 0);
1597 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1598 radeon_emit(cmd_buffer->cs, 0);
1599
1600 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 1);
1601 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1602
1603 radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4,
1604 cb->cb_color_base >> 32);
1605 radeon_set_context_reg(cmd_buffer->cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + index * 4,
1606 cb->cb_color_cmask >> 32);
1607 radeon_set_context_reg(cmd_buffer->cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + index * 4,
1608 cb->cb_color_fmask >> 32);
1609 radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4,
1610 cb->cb_dcc_base >> 32);
1611 radeon_set_context_reg(cmd_buffer->cs, R_028EC0_CB_COLOR0_ATTRIB2 + index * 4,
1612 cb->cb_color_attrib2);
1613 radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4,
1614 cb->cb_color_attrib3);
1615 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1616 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1617 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1618 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1619 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1620 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1621 radeon_emit(cmd_buffer->cs, cb_color_info);
1622 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1623 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1624 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1625 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1626 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1627 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1628
1629 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1630 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1631 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1632
1633 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1634 cb->cb_mrt_epitch);
1635 } else {
1636 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1637 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1638 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1639 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1640 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1641 radeon_emit(cmd_buffer->cs, cb_color_info);
1642 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1643 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1644 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1645 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1646 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1647 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1648
1649 if (is_vi) { /* DCC BASE */
1650 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1651 }
1652 }
1653
1654 if (radv_dcc_enabled(image, iview->base_mip)) {
1655 /* Drawing with DCC enabled also compresses colorbuffers. */
1656 VkImageSubresourceRange range = {
1657 .aspectMask = iview->aspect_mask,
1658 .baseMipLevel = iview->base_mip,
1659 .levelCount = iview->level_count,
1660 .baseArrayLayer = iview->base_layer,
1661 .layerCount = iview->layer_count,
1662 };
1663
1664 radv_update_dcc_metadata(cmd_buffer, image, &range, true);
1665 }
1666 }
1667
1668 static void
1669 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1670 struct radv_ds_buffer_info *ds,
1671 const struct radv_image_view *iview,
1672 VkImageLayout layout,
1673 bool in_render_loop, bool requires_cond_exec)
1674 {
1675 const struct radv_image *image = iview->image;
1676 uint32_t db_z_info = ds->db_z_info;
1677 uint32_t db_z_info_reg;
1678
1679 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug ||
1680 !radv_image_is_tc_compat_htile(image))
1681 return;
1682
1683 if (!radv_layout_is_htile_compressed(image, layout, in_render_loop,
1684 radv_image_queue_family_mask(image,
1685 cmd_buffer->queue_family_index,
1686 cmd_buffer->queue_family_index))) {
1687 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1688 }
1689
1690 db_z_info &= C_028040_ZRANGE_PRECISION;
1691
1692 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1693 db_z_info_reg = R_028038_DB_Z_INFO;
1694 } else {
1695 db_z_info_reg = R_028040_DB_Z_INFO;
1696 }
1697
1698 /* When we don't know the last fast clear value we need to emit a
1699 * conditional packet that will eventually skip the following
1700 * SET_CONTEXT_REG packet.
1701 */
1702 if (requires_cond_exec) {
1703 uint64_t va = radv_get_tc_compat_zrange_va(image, iview->base_mip);
1704
1705 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1706 radeon_emit(cmd_buffer->cs, va);
1707 radeon_emit(cmd_buffer->cs, va >> 32);
1708 radeon_emit(cmd_buffer->cs, 0);
1709 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1710 }
1711
1712 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1713 }
1714
1715 static void
1716 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1717 struct radv_ds_buffer_info *ds,
1718 struct radv_image_view *iview,
1719 VkImageLayout layout,
1720 bool in_render_loop)
1721 {
1722 const struct radv_image *image = iview->image;
1723 uint32_t db_z_info = ds->db_z_info;
1724 uint32_t db_stencil_info = ds->db_stencil_info;
1725
1726 if (!radv_layout_is_htile_compressed(image, layout, in_render_loop,
1727 radv_image_queue_family_mask(image,
1728 cmd_buffer->queue_family_index,
1729 cmd_buffer->queue_family_index))) {
1730 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1731 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1732 }
1733
1734 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1735 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1736
1737 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1738 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1739 radeon_set_context_reg(cmd_buffer->cs, R_02801C_DB_DEPTH_SIZE_XY, ds->db_depth_size);
1740
1741 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 7);
1742 radeon_emit(cmd_buffer->cs, S_02803C_RESOURCE_LEVEL(1));
1743 radeon_emit(cmd_buffer->cs, db_z_info);
1744 radeon_emit(cmd_buffer->cs, db_stencil_info);
1745 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1746 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1747 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1748 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1749
1750 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_READ_BASE_HI, 5);
1751 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1752 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1753 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1754 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1755 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1756 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1757 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1758 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1759 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1760 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1761
1762 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1763 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1764 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1765 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1766 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1767 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1768 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1769 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1770 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1771 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1772 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1773
1774 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1775 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1776 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1777 } else {
1778 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1779
1780 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1781 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1782 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1783 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1784 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1785 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1786 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1787 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1788 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1789 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1790
1791 }
1792
1793 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1794 radv_update_zrange_precision(cmd_buffer, ds, iview, layout,
1795 in_render_loop, true);
1796
1797 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1798 ds->pa_su_poly_offset_db_fmt_cntl);
1799 }
1800
1801 /**
1802 * Update the fast clear depth/stencil values if the image is bound as a
1803 * depth/stencil buffer.
1804 */
1805 static void
1806 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1807 const struct radv_image_view *iview,
1808 VkClearDepthStencilValue ds_clear_value,
1809 VkImageAspectFlags aspects)
1810 {
1811 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1812 const struct radv_image *image = iview->image;
1813 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1814 uint32_t att_idx;
1815
1816 if (!cmd_buffer->state.attachments || !subpass)
1817 return;
1818
1819 if (!subpass->depth_stencil_attachment)
1820 return;
1821
1822 att_idx = subpass->depth_stencil_attachment->attachment;
1823 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1824 return;
1825
1826 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1827 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1828 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1829 radeon_emit(cs, ds_clear_value.stencil);
1830 radeon_emit(cs, fui(ds_clear_value.depth));
1831 } else if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1832 radeon_set_context_reg_seq(cs, R_02802C_DB_DEPTH_CLEAR, 1);
1833 radeon_emit(cs, fui(ds_clear_value.depth));
1834 } else {
1835 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1836 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 1);
1837 radeon_emit(cs, ds_clear_value.stencil);
1838 }
1839
1840 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1841 * only needed when clearing Z to 0.0.
1842 */
1843 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1844 ds_clear_value.depth == 0.0) {
1845 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1846 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
1847
1848 radv_update_zrange_precision(cmd_buffer, &cmd_buffer->state.attachments[att_idx].ds,
1849 iview, layout, in_render_loop, false);
1850 }
1851
1852 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1853 }
1854
1855 /**
1856 * Set the clear depth/stencil values to the image's metadata.
1857 */
1858 static void
1859 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1860 struct radv_image *image,
1861 const VkImageSubresourceRange *range,
1862 VkClearDepthStencilValue ds_clear_value,
1863 VkImageAspectFlags aspects)
1864 {
1865 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1866 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel);
1867 uint32_t level_count = radv_get_levelCount(image, range);
1868
1869 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1870 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1871 /* Use the fastest way when both aspects are used. */
1872 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + 2 * level_count, cmd_buffer->state.predicating));
1873 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1874 S_370_WR_CONFIRM(1) |
1875 S_370_ENGINE_SEL(V_370_PFP));
1876 radeon_emit(cs, va);
1877 radeon_emit(cs, va >> 32);
1878
1879 for (uint32_t l = 0; l < level_count; l++) {
1880 radeon_emit(cs, ds_clear_value.stencil);
1881 radeon_emit(cs, fui(ds_clear_value.depth));
1882 }
1883 } else {
1884 /* Otherwise we need one WRITE_DATA packet per level. */
1885 for (uint32_t l = 0; l < level_count; l++) {
1886 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel + l);
1887 unsigned value;
1888
1889 if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1890 value = fui(ds_clear_value.depth);
1891 va += 4;
1892 } else {
1893 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1894 value = ds_clear_value.stencil;
1895 }
1896
1897 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1898 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1899 S_370_WR_CONFIRM(1) |
1900 S_370_ENGINE_SEL(V_370_PFP));
1901 radeon_emit(cs, va);
1902 radeon_emit(cs, va >> 32);
1903 radeon_emit(cs, value);
1904 }
1905 }
1906 }
1907
1908 /**
1909 * Update the TC-compat metadata value for this image.
1910 */
1911 static void
1912 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1913 struct radv_image *image,
1914 const VkImageSubresourceRange *range,
1915 uint32_t value)
1916 {
1917 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1918
1919 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug)
1920 return;
1921
1922 uint64_t va = radv_get_tc_compat_zrange_va(image, range->baseMipLevel);
1923 uint32_t level_count = radv_get_levelCount(image, range);
1924
1925 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + level_count, cmd_buffer->state.predicating));
1926 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1927 S_370_WR_CONFIRM(1) |
1928 S_370_ENGINE_SEL(V_370_PFP));
1929 radeon_emit(cs, va);
1930 radeon_emit(cs, va >> 32);
1931
1932 for (uint32_t l = 0; l < level_count; l++)
1933 radeon_emit(cs, value);
1934 }
1935
1936 static void
1937 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1938 const struct radv_image_view *iview,
1939 VkClearDepthStencilValue ds_clear_value)
1940 {
1941 VkImageSubresourceRange range = {
1942 .aspectMask = iview->aspect_mask,
1943 .baseMipLevel = iview->base_mip,
1944 .levelCount = iview->level_count,
1945 .baseArrayLayer = iview->base_layer,
1946 .layerCount = iview->layer_count,
1947 };
1948 uint32_t cond_val;
1949
1950 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1951 * depth clear value is 0.0f.
1952 */
1953 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1954
1955 radv_set_tc_compat_zrange_metadata(cmd_buffer, iview->image, &range,
1956 cond_val);
1957 }
1958
1959 /**
1960 * Update the clear depth/stencil values for this image.
1961 */
1962 void
1963 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1964 const struct radv_image_view *iview,
1965 VkClearDepthStencilValue ds_clear_value,
1966 VkImageAspectFlags aspects)
1967 {
1968 VkImageSubresourceRange range = {
1969 .aspectMask = iview->aspect_mask,
1970 .baseMipLevel = iview->base_mip,
1971 .levelCount = iview->level_count,
1972 .baseArrayLayer = iview->base_layer,
1973 .layerCount = iview->layer_count,
1974 };
1975 struct radv_image *image = iview->image;
1976
1977 assert(radv_image_has_htile(image));
1978
1979 radv_set_ds_clear_metadata(cmd_buffer, iview->image, &range,
1980 ds_clear_value, aspects);
1981
1982 if (radv_image_is_tc_compat_htile(image) &&
1983 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1984 radv_update_tc_compat_zrange_metadata(cmd_buffer, iview,
1985 ds_clear_value);
1986 }
1987
1988 radv_update_bound_fast_clear_ds(cmd_buffer, iview, ds_clear_value,
1989 aspects);
1990 }
1991
1992 /**
1993 * Load the clear depth/stencil values from the image's metadata.
1994 */
1995 static void
1996 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1997 const struct radv_image_view *iview)
1998 {
1999 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2000 const struct radv_image *image = iview->image;
2001 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
2002 uint64_t va = radv_get_ds_clear_value_va(image, iview->base_mip);
2003 unsigned reg_offset = 0, reg_count = 0;
2004
2005 if (!radv_image_has_htile(image))
2006 return;
2007
2008 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
2009 ++reg_count;
2010 } else {
2011 ++reg_offset;
2012 va += 4;
2013 }
2014 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
2015 ++reg_count;
2016
2017 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
2018
2019 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
2020 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG_INDEX, 3, 0));
2021 radeon_emit(cs, va);
2022 radeon_emit(cs, va >> 32);
2023 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
2024 radeon_emit(cs, reg_count);
2025 } else {
2026 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2027 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2028 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2029 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
2030 radeon_emit(cs, va);
2031 radeon_emit(cs, va >> 32);
2032 radeon_emit(cs, reg >> 2);
2033 radeon_emit(cs, 0);
2034
2035 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
2036 radeon_emit(cs, 0);
2037 }
2038 }
2039
2040 /*
2041 * With DCC some colors don't require CMASK elimination before being
2042 * used as a texture. This sets a predicate value to determine if the
2043 * cmask eliminate is required.
2044 */
2045 void
2046 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
2047 struct radv_image *image,
2048 const VkImageSubresourceRange *range, bool value)
2049 {
2050 uint64_t pred_val = value;
2051 uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
2052 uint32_t level_count = radv_get_levelCount(image, range);
2053 uint32_t count = 2 * level_count;
2054
2055 assert(radv_dcc_enabled(image, range->baseMipLevel));
2056
2057 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
2058 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
2059 S_370_WR_CONFIRM(1) |
2060 S_370_ENGINE_SEL(V_370_PFP));
2061 radeon_emit(cmd_buffer->cs, va);
2062 radeon_emit(cmd_buffer->cs, va >> 32);
2063
2064 for (uint32_t l = 0; l < level_count; l++) {
2065 radeon_emit(cmd_buffer->cs, pred_val);
2066 radeon_emit(cmd_buffer->cs, pred_val >> 32);
2067 }
2068 }
2069
2070 /**
2071 * Update the DCC predicate to reflect the compression state.
2072 */
2073 void
2074 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
2075 struct radv_image *image,
2076 const VkImageSubresourceRange *range, bool value)
2077 {
2078 uint64_t pred_val = value;
2079 uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
2080 uint32_t level_count = radv_get_levelCount(image, range);
2081 uint32_t count = 2 * level_count;
2082
2083 assert(radv_dcc_enabled(image, range->baseMipLevel));
2084
2085 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
2086 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
2087 S_370_WR_CONFIRM(1) |
2088 S_370_ENGINE_SEL(V_370_PFP));
2089 radeon_emit(cmd_buffer->cs, va);
2090 radeon_emit(cmd_buffer->cs, va >> 32);
2091
2092 for (uint32_t l = 0; l < level_count; l++) {
2093 radeon_emit(cmd_buffer->cs, pred_val);
2094 radeon_emit(cmd_buffer->cs, pred_val >> 32);
2095 }
2096 }
2097
2098 /**
2099 * Update the fast clear color values if the image is bound as a color buffer.
2100 */
2101 static void
2102 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
2103 struct radv_image *image,
2104 int cb_idx,
2105 uint32_t color_values[2])
2106 {
2107 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2108 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2109 uint32_t att_idx;
2110
2111 if (!cmd_buffer->state.attachments || !subpass)
2112 return;
2113
2114 att_idx = subpass->color_attachments[cb_idx].attachment;
2115 if (att_idx == VK_ATTACHMENT_UNUSED)
2116 return;
2117
2118 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
2119 return;
2120
2121 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
2122 radeon_emit(cs, color_values[0]);
2123 radeon_emit(cs, color_values[1]);
2124
2125 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2126 }
2127
2128 /**
2129 * Set the clear color values to the image's metadata.
2130 */
2131 static void
2132 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
2133 struct radv_image *image,
2134 const VkImageSubresourceRange *range,
2135 uint32_t color_values[2])
2136 {
2137 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2138 uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
2139 uint32_t level_count = radv_get_levelCount(image, range);
2140 uint32_t count = 2 * level_count;
2141
2142 assert(radv_image_has_cmask(image) ||
2143 radv_dcc_enabled(image, range->baseMipLevel));
2144
2145 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
2146 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
2147 S_370_WR_CONFIRM(1) |
2148 S_370_ENGINE_SEL(V_370_PFP));
2149 radeon_emit(cs, va);
2150 radeon_emit(cs, va >> 32);
2151
2152 for (uint32_t l = 0; l < level_count; l++) {
2153 radeon_emit(cs, color_values[0]);
2154 radeon_emit(cs, color_values[1]);
2155 }
2156 }
2157
2158 /**
2159 * Update the clear color values for this image.
2160 */
2161 void
2162 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
2163 const struct radv_image_view *iview,
2164 int cb_idx,
2165 uint32_t color_values[2])
2166 {
2167 struct radv_image *image = iview->image;
2168 VkImageSubresourceRange range = {
2169 .aspectMask = iview->aspect_mask,
2170 .baseMipLevel = iview->base_mip,
2171 .levelCount = iview->level_count,
2172 .baseArrayLayer = iview->base_layer,
2173 .layerCount = iview->layer_count,
2174 };
2175
2176 assert(radv_image_has_cmask(image) ||
2177 radv_dcc_enabled(image, iview->base_mip));
2178
2179 radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
2180
2181 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
2182 color_values);
2183 }
2184
2185 /**
2186 * Load the clear color values from the image's metadata.
2187 */
2188 static void
2189 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
2190 struct radv_image_view *iview,
2191 int cb_idx)
2192 {
2193 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2194 struct radv_image *image = iview->image;
2195 uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
2196
2197 if (!radv_image_has_cmask(image) &&
2198 !radv_dcc_enabled(image, iview->base_mip))
2199 return;
2200
2201 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
2202
2203 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
2204 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG_INDEX, 3, cmd_buffer->state.predicating));
2205 radeon_emit(cs, va);
2206 radeon_emit(cs, va >> 32);
2207 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
2208 radeon_emit(cs, 2);
2209 } else {
2210 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
2211 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2212 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2213 COPY_DATA_COUNT_SEL);
2214 radeon_emit(cs, va);
2215 radeon_emit(cs, va >> 32);
2216 radeon_emit(cs, reg >> 2);
2217 radeon_emit(cs, 0);
2218
2219 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
2220 radeon_emit(cs, 0);
2221 }
2222 }
2223
2224 static void
2225 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
2226 {
2227 int i;
2228 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
2229 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2230
2231 /* this may happen for inherited secondary recording */
2232 if (!framebuffer)
2233 return;
2234
2235 for (i = 0; i < 8; ++i) {
2236 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
2237 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2238 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2239 continue;
2240 }
2241
2242 int idx = subpass->color_attachments[i].attachment;
2243 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
2244 VkImageLayout layout = subpass->color_attachments[i].layout;
2245 bool in_render_loop = subpass->color_attachments[i].in_render_loop;
2246
2247 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, iview->bo);
2248
2249 assert(iview->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
2250 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
2251 radv_emit_fb_color_state(cmd_buffer, i, &cmd_buffer->state.attachments[idx].cb, iview, layout, in_render_loop);
2252
2253 radv_load_color_clear_metadata(cmd_buffer, iview, i);
2254 }
2255
2256 if (subpass->depth_stencil_attachment) {
2257 int idx = subpass->depth_stencil_attachment->attachment;
2258 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
2259 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
2260 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
2261 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, cmd_buffer->state.attachments[idx].iview->bo);
2262
2263 radv_emit_fb_ds_state(cmd_buffer, &cmd_buffer->state.attachments[idx].ds, iview, layout, in_render_loop);
2264
2265 if (cmd_buffer->state.attachments[idx].ds.offset_scale != cmd_buffer->state.offset_scale) {
2266 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2267 cmd_buffer->state.offset_scale = cmd_buffer->state.attachments[idx].ds.offset_scale;
2268 }
2269 radv_load_ds_clear_metadata(cmd_buffer, iview);
2270 } else {
2271 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9)
2272 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
2273 else
2274 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
2275
2276 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
2277 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
2278 }
2279 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2280 S_028208_BR_X(framebuffer->width) |
2281 S_028208_BR_Y(framebuffer->height));
2282
2283 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
2284 bool disable_constant_encode =
2285 cmd_buffer->device->physical_device->rad_info.has_dcc_constant_encode;
2286 enum chip_class chip_class =
2287 cmd_buffer->device->physical_device->rad_info.chip_class;
2288 uint8_t watermark = chip_class >= GFX10 ? 6 : 4;
2289
2290 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
2291 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class <= GFX9) |
2292 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
2293 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
2294 }
2295
2296 if (cmd_buffer->device->dfsm_allowed) {
2297 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2298 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
2299 }
2300
2301 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
2302 }
2303
2304 static void
2305 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer, bool indirect)
2306 {
2307 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2308 struct radv_cmd_state *state = &cmd_buffer->state;
2309
2310 if (state->index_type != state->last_index_type) {
2311 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2312 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2313 cs, R_03090C_VGT_INDEX_TYPE,
2314 2, state->index_type);
2315 } else {
2316 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2317 radeon_emit(cs, state->index_type);
2318 }
2319
2320 state->last_index_type = state->index_type;
2321 }
2322
2323 /* For the direct indexed draws we use DRAW_INDEX_2, which includes
2324 * the index_va and max_index_count already. */
2325 if (!indirect)
2326 return;
2327
2328 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2329 radeon_emit(cs, state->index_va);
2330 radeon_emit(cs, state->index_va >> 32);
2331
2332 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2333 radeon_emit(cs, state->max_index_count);
2334
2335 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
2336 }
2337
2338 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
2339 {
2340 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
2341 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2342 uint32_t pa_sc_mode_cntl_1 =
2343 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
2344 uint32_t db_count_control;
2345
2346 if(!cmd_buffer->state.active_occlusion_queries) {
2347 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2348 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2349 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2350 has_perfect_queries) {
2351 /* Re-enable out-of-order rasterization if the
2352 * bound pipeline supports it and if it's has
2353 * been disabled before starting any perfect
2354 * occlusion queries.
2355 */
2356 radeon_set_context_reg(cmd_buffer->cs,
2357 R_028A4C_PA_SC_MODE_CNTL_1,
2358 pa_sc_mode_cntl_1);
2359 }
2360 }
2361 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
2362 } else {
2363 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2364 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
2365 bool gfx10_perfect = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10 && has_perfect_queries;
2366
2367 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2368 /* Always enable PERFECT_ZPASS_COUNTS due to issues with partially
2369 * covered tiles, discards, and early depth testing. For more details,
2370 * see https://gitlab.freedesktop.org/mesa/mesa/-/issues/3218 */
2371 db_count_control =
2372 S_028004_PERFECT_ZPASS_COUNTS(1) |
2373 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
2374 S_028004_SAMPLE_RATE(sample_rate) |
2375 S_028004_ZPASS_ENABLE(1) |
2376 S_028004_SLICE_EVEN_ENABLE(1) |
2377 S_028004_SLICE_ODD_ENABLE(1);
2378
2379 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2380 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2381 has_perfect_queries) {
2382 /* If the bound pipeline has enabled
2383 * out-of-order rasterization, we should
2384 * disable it before starting any perfect
2385 * occlusion queries.
2386 */
2387 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
2388
2389 radeon_set_context_reg(cmd_buffer->cs,
2390 R_028A4C_PA_SC_MODE_CNTL_1,
2391 pa_sc_mode_cntl_1);
2392 }
2393 } else {
2394 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
2395 S_028004_SAMPLE_RATE(sample_rate);
2396 }
2397 }
2398
2399 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
2400
2401 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2402 }
2403
2404 static void
2405 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
2406 {
2407 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
2408
2409 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
2410 radv_emit_viewport(cmd_buffer);
2411
2412 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
2413 !cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
2414 radv_emit_scissor(cmd_buffer);
2415
2416 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
2417 radv_emit_line_width(cmd_buffer);
2418
2419 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
2420 radv_emit_blend_constants(cmd_buffer);
2421
2422 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
2423 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
2424 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
2425 radv_emit_stencil(cmd_buffer);
2426
2427 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
2428 radv_emit_depth_bounds(cmd_buffer);
2429
2430 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
2431 radv_emit_depth_bias(cmd_buffer);
2432
2433 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
2434 radv_emit_discard_rectangle(cmd_buffer);
2435
2436 if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)
2437 radv_emit_sample_locations(cmd_buffer);
2438
2439 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE)
2440 radv_emit_line_stipple(cmd_buffer);
2441
2442 if (states & (RADV_CMD_DIRTY_DYNAMIC_CULL_MODE |
2443 RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE))
2444 radv_emit_culling(cmd_buffer, states);
2445
2446 if (states & RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY)
2447 radv_emit_primitive_topology(cmd_buffer);
2448
2449 if (states & (RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE |
2450 RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE |
2451 RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP |
2452 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE |
2453 RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE |
2454 RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP))
2455 radv_emit_depth_control(cmd_buffer, states);
2456
2457 if (states & RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP)
2458 radv_emit_stencil_control(cmd_buffer);
2459
2460 cmd_buffer->state.dirty &= ~states;
2461 }
2462
2463 static void
2464 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
2465 VkPipelineBindPoint bind_point)
2466 {
2467 struct radv_descriptor_state *descriptors_state =
2468 radv_get_descriptors_state(cmd_buffer, bind_point);
2469 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
2470 unsigned bo_offset;
2471
2472 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
2473 set->mapped_ptr,
2474 &bo_offset))
2475 return;
2476
2477 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2478 set->va += bo_offset;
2479 }
2480
2481 static void
2482 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
2483 VkPipelineBindPoint bind_point)
2484 {
2485 struct radv_descriptor_state *descriptors_state =
2486 radv_get_descriptors_state(cmd_buffer, bind_point);
2487 uint32_t size = MAX_SETS * 4;
2488 uint32_t offset;
2489 void *ptr;
2490
2491 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
2492 256, &offset, &ptr))
2493 return;
2494
2495 for (unsigned i = 0; i < MAX_SETS; i++) {
2496 uint32_t *uptr = ((uint32_t *)ptr) + i;
2497 uint64_t set_va = 0;
2498 struct radv_descriptor_set *set = descriptors_state->sets[i];
2499 if (descriptors_state->valid & (1u << i))
2500 set_va = set->va;
2501 uptr[0] = set_va & 0xffffffff;
2502 }
2503
2504 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2505 va += offset;
2506
2507 if (cmd_buffer->state.pipeline) {
2508 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
2509 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2510 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2511
2512 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
2513 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
2514 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2515
2516 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
2517 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2518 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2519
2520 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2521 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
2522 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2523
2524 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2525 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
2526 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2527 }
2528
2529 if (cmd_buffer->state.compute_pipeline)
2530 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
2531 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2532 }
2533
2534 static void
2535 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
2536 VkShaderStageFlags stages)
2537 {
2538 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2539 VK_PIPELINE_BIND_POINT_COMPUTE :
2540 VK_PIPELINE_BIND_POINT_GRAPHICS;
2541 struct radv_descriptor_state *descriptors_state =
2542 radv_get_descriptors_state(cmd_buffer, bind_point);
2543 struct radv_cmd_state *state = &cmd_buffer->state;
2544 bool flush_indirect_descriptors;
2545
2546 if (!descriptors_state->dirty)
2547 return;
2548
2549 if (descriptors_state->push_dirty)
2550 radv_flush_push_descriptors(cmd_buffer, bind_point);
2551
2552 flush_indirect_descriptors =
2553 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
2554 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
2555 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
2556 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
2557
2558 if (flush_indirect_descriptors)
2559 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
2560
2561 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2562 cmd_buffer->cs,
2563 MAX_SETS * MESA_SHADER_STAGES * 4);
2564
2565 if (cmd_buffer->state.pipeline) {
2566 radv_foreach_stage(stage, stages) {
2567 if (!cmd_buffer->state.pipeline->shaders[stage])
2568 continue;
2569
2570 radv_emit_descriptor_pointers(cmd_buffer,
2571 cmd_buffer->state.pipeline,
2572 descriptors_state, stage);
2573 }
2574 }
2575
2576 if (cmd_buffer->state.compute_pipeline &&
2577 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
2578 radv_emit_descriptor_pointers(cmd_buffer,
2579 cmd_buffer->state.compute_pipeline,
2580 descriptors_state,
2581 MESA_SHADER_COMPUTE);
2582 }
2583
2584 descriptors_state->dirty = 0;
2585 descriptors_state->push_dirty = false;
2586
2587 assert(cmd_buffer->cs->cdw <= cdw_max);
2588
2589 if (unlikely(cmd_buffer->device->trace_bo))
2590 radv_save_descriptors(cmd_buffer, bind_point);
2591 }
2592
2593 static void
2594 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
2595 VkShaderStageFlags stages)
2596 {
2597 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
2598 ? cmd_buffer->state.compute_pipeline
2599 : cmd_buffer->state.pipeline;
2600 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2601 VK_PIPELINE_BIND_POINT_COMPUTE :
2602 VK_PIPELINE_BIND_POINT_GRAPHICS;
2603 struct radv_descriptor_state *descriptors_state =
2604 radv_get_descriptors_state(cmd_buffer, bind_point);
2605 struct radv_pipeline_layout *layout = pipeline->layout;
2606 struct radv_shader_variant *shader, *prev_shader;
2607 bool need_push_constants = false;
2608 unsigned offset;
2609 void *ptr;
2610 uint64_t va;
2611
2612 stages &= cmd_buffer->push_constant_stages;
2613 if (!stages ||
2614 (!layout->push_constant_size && !layout->dynamic_offset_count))
2615 return;
2616
2617 radv_foreach_stage(stage, stages) {
2618 shader = radv_get_shader(pipeline, stage);
2619 if (!shader)
2620 continue;
2621
2622 need_push_constants |= shader->info.loads_push_constants;
2623 need_push_constants |= shader->info.loads_dynamic_offsets;
2624
2625 uint8_t base = shader->info.base_inline_push_consts;
2626 uint8_t count = shader->info.num_inline_push_consts;
2627
2628 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
2629 AC_UD_INLINE_PUSH_CONSTANTS,
2630 count,
2631 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
2632 }
2633
2634 if (need_push_constants) {
2635 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
2636 16 * layout->dynamic_offset_count,
2637 256, &offset, &ptr))
2638 return;
2639
2640 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
2641 memcpy((char*)ptr + layout->push_constant_size,
2642 descriptors_state->dynamic_buffers,
2643 16 * layout->dynamic_offset_count);
2644
2645 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2646 va += offset;
2647
2648 ASSERTED unsigned cdw_max =
2649 radeon_check_space(cmd_buffer->device->ws,
2650 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
2651
2652 prev_shader = NULL;
2653 radv_foreach_stage(stage, stages) {
2654 shader = radv_get_shader(pipeline, stage);
2655
2656 /* Avoid redundantly emitting the address for merged stages. */
2657 if (shader && shader != prev_shader) {
2658 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
2659 AC_UD_PUSH_CONSTANTS, va);
2660
2661 prev_shader = shader;
2662 }
2663 }
2664 assert(cmd_buffer->cs->cdw <= cdw_max);
2665 }
2666
2667 cmd_buffer->push_constant_stages &= ~stages;
2668 }
2669
2670 static void
2671 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
2672 bool pipeline_is_dirty)
2673 {
2674 if ((pipeline_is_dirty ||
2675 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
2676 cmd_buffer->state.pipeline->num_vertex_bindings &&
2677 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.has_vertex_buffers) {
2678 unsigned vb_offset;
2679 void *vb_ptr;
2680 uint32_t i = 0;
2681 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
2682 uint64_t va;
2683
2684 /* allocate some descriptor state for vertex buffers */
2685 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2686 &vb_offset, &vb_ptr))
2687 return;
2688
2689 for (i = 0; i < count; i++) {
2690 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2691 uint32_t offset;
2692 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2693 unsigned num_records;
2694 unsigned stride;
2695
2696 if (!buffer)
2697 continue;
2698
2699 va = radv_buffer_get_va(buffer->bo);
2700
2701 offset = cmd_buffer->vertex_bindings[i].offset;
2702 va += offset + buffer->offset;
2703
2704 if (cmd_buffer->vertex_bindings[i].size) {
2705 num_records = cmd_buffer->vertex_bindings[i].size;
2706 } else {
2707 num_records = buffer->size - offset;
2708 }
2709
2710 if (cmd_buffer->state.pipeline->graphics.uses_dynamic_stride) {
2711 stride = cmd_buffer->vertex_bindings[i].stride;
2712 } else {
2713 stride = cmd_buffer->state.pipeline->binding_stride[i];
2714 }
2715
2716 if (cmd_buffer->device->physical_device->rad_info.chip_class != GFX8 && stride)
2717 num_records /= stride;
2718
2719 desc[0] = va;
2720 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2721 desc[2] = num_records;
2722 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2723 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2724 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2725 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2726
2727 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2728 /* OOB_SELECT chooses the out-of-bounds check:
2729 * - 1: index >= NUM_RECORDS (Structured)
2730 * - 3: offset >= NUM_RECORDS (Raw)
2731 */
2732 int oob_select = stride ? V_008F0C_OOB_SELECT_STRUCTURED : V_008F0C_OOB_SELECT_RAW;
2733
2734 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT) |
2735 S_008F0C_OOB_SELECT(oob_select) |
2736 S_008F0C_RESOURCE_LEVEL(1);
2737 } else {
2738 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2739 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2740 }
2741 }
2742
2743 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2744 va += vb_offset;
2745
2746 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2747 AC_UD_VS_VERTEX_BUFFERS, va);
2748
2749 cmd_buffer->state.vb_va = va;
2750 cmd_buffer->state.vb_size = count * 16;
2751 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2752 }
2753 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2754 }
2755
2756 static void
2757 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2758 {
2759 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2760 struct radv_userdata_info *loc;
2761 uint32_t base_reg;
2762
2763 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2764 if (!radv_get_shader(pipeline, stage))
2765 continue;
2766
2767 loc = radv_lookup_user_sgpr(pipeline, stage,
2768 AC_UD_STREAMOUT_BUFFERS);
2769 if (loc->sgpr_idx == -1)
2770 continue;
2771
2772 base_reg = pipeline->user_data_0[stage];
2773
2774 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2775 base_reg + loc->sgpr_idx * 4, va, false);
2776 }
2777
2778 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
2779 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2780 if (loc->sgpr_idx != -1) {
2781 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2782
2783 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2784 base_reg + loc->sgpr_idx * 4, va, false);
2785 }
2786 }
2787 }
2788
2789 static void
2790 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2791 {
2792 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2793 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2794 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2795 unsigned so_offset;
2796 void *so_ptr;
2797 uint64_t va;
2798
2799 /* Allocate some descriptor state for streamout buffers. */
2800 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2801 MAX_SO_BUFFERS * 16, 256,
2802 &so_offset, &so_ptr))
2803 return;
2804
2805 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2806 struct radv_buffer *buffer = sb[i].buffer;
2807 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2808
2809 if (!(so->enabled_mask & (1 << i)))
2810 continue;
2811
2812 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2813
2814 va += sb[i].offset;
2815
2816 /* Set the descriptor.
2817 *
2818 * On GFX8, the format must be non-INVALID, otherwise
2819 * the buffer will be considered not bound and store
2820 * instructions will be no-ops.
2821 */
2822 uint32_t size = 0xffffffff;
2823
2824 /* Compute the correct buffer size for NGG streamout
2825 * because it's used to determine the max emit per
2826 * buffer.
2827 */
2828 if (cmd_buffer->device->physical_device->use_ngg_streamout)
2829 size = buffer->size - sb[i].offset;
2830
2831 desc[0] = va;
2832 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2833 desc[2] = size;
2834 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2835 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2836 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2837 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2838
2839 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2840 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2841 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
2842 S_008F0C_RESOURCE_LEVEL(1);
2843 } else {
2844 desc[3] |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2845 }
2846 }
2847
2848 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2849 va += so_offset;
2850
2851 radv_emit_streamout_buffers(cmd_buffer, va);
2852 }
2853
2854 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2855 }
2856
2857 static void
2858 radv_flush_ngg_gs_state(struct radv_cmd_buffer *cmd_buffer)
2859 {
2860 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2861 struct radv_userdata_info *loc;
2862 uint32_t ngg_gs_state = 0;
2863 uint32_t base_reg;
2864
2865 if (!radv_pipeline_has_gs(pipeline) ||
2866 !radv_pipeline_has_ngg(pipeline))
2867 return;
2868
2869 /* By default NGG GS queries are disabled but they are enabled if the
2870 * command buffer has active GDS queries or if it's a secondary command
2871 * buffer that inherits the number of generated primitives.
2872 */
2873 if (cmd_buffer->state.active_pipeline_gds_queries ||
2874 (cmd_buffer->state.inherited_pipeline_statistics & VK_QUERY_PIPELINE_STATISTIC_GEOMETRY_SHADER_PRIMITIVES_BIT))
2875 ngg_gs_state = 1;
2876
2877 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_GEOMETRY,
2878 AC_UD_NGG_GS_STATE);
2879 base_reg = pipeline->user_data_0[MESA_SHADER_GEOMETRY];
2880 assert(loc->sgpr_idx != -1);
2881
2882 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
2883 ngg_gs_state);
2884 }
2885
2886 static void
2887 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2888 {
2889 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2890 radv_flush_streamout_descriptors(cmd_buffer);
2891 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2892 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2893 radv_flush_ngg_gs_state(cmd_buffer);
2894 }
2895
2896 struct radv_draw_info {
2897 /**
2898 * Number of vertices.
2899 */
2900 uint32_t count;
2901
2902 /**
2903 * Index of the first vertex.
2904 */
2905 int32_t vertex_offset;
2906
2907 /**
2908 * First instance id.
2909 */
2910 uint32_t first_instance;
2911
2912 /**
2913 * Number of instances.
2914 */
2915 uint32_t instance_count;
2916
2917 /**
2918 * First index (indexed draws only).
2919 */
2920 uint32_t first_index;
2921
2922 /**
2923 * Whether it's an indexed draw.
2924 */
2925 bool indexed;
2926
2927 /**
2928 * Indirect draw parameters resource.
2929 */
2930 struct radv_buffer *indirect;
2931 uint64_t indirect_offset;
2932 uint32_t stride;
2933
2934 /**
2935 * Draw count parameters resource.
2936 */
2937 struct radv_buffer *count_buffer;
2938 uint64_t count_buffer_offset;
2939
2940 /**
2941 * Stream output parameters resource.
2942 */
2943 struct radv_buffer *strmout_buffer;
2944 uint64_t strmout_buffer_offset;
2945 };
2946
2947 static uint32_t
2948 radv_get_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
2949 {
2950 switch (cmd_buffer->state.index_type) {
2951 case V_028A7C_VGT_INDEX_8:
2952 return 0xffu;
2953 case V_028A7C_VGT_INDEX_16:
2954 return 0xffffu;
2955 case V_028A7C_VGT_INDEX_32:
2956 return 0xffffffffu;
2957 default:
2958 unreachable("invalid index type");
2959 }
2960 }
2961
2962 static void
2963 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
2964 bool instanced_draw, bool indirect_draw,
2965 bool count_from_stream_output,
2966 uint32_t draw_vertex_count)
2967 {
2968 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2969 struct radv_cmd_state *state = &cmd_buffer->state;
2970 unsigned topology = state->dynamic.primitive_topology;
2971 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2972 unsigned ia_multi_vgt_param;
2973
2974 ia_multi_vgt_param =
2975 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
2976 indirect_draw,
2977 count_from_stream_output,
2978 draw_vertex_count,
2979 topology);
2980
2981 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2982 if (info->chip_class == GFX9) {
2983 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2984 cs,
2985 R_030960_IA_MULTI_VGT_PARAM,
2986 4, ia_multi_vgt_param);
2987 } else if (info->chip_class >= GFX7) {
2988 radeon_set_context_reg_idx(cs,
2989 R_028AA8_IA_MULTI_VGT_PARAM,
2990 1, ia_multi_vgt_param);
2991 } else {
2992 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2993 ia_multi_vgt_param);
2994 }
2995 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2996 }
2997 }
2998
2999 static void
3000 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
3001 const struct radv_draw_info *draw_info)
3002 {
3003 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
3004 struct radv_cmd_state *state = &cmd_buffer->state;
3005 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3006 int32_t primitive_reset_en;
3007
3008 /* Draw state. */
3009 if (info->chip_class < GFX10) {
3010 si_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
3011 draw_info->indirect,
3012 !!draw_info->strmout_buffer,
3013 draw_info->indirect ? 0 : draw_info->count);
3014 }
3015
3016 /* Primitive restart. */
3017 primitive_reset_en =
3018 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
3019
3020 if (primitive_reset_en != state->last_primitive_reset_en) {
3021 state->last_primitive_reset_en = primitive_reset_en;
3022 if (info->chip_class >= GFX9) {
3023 radeon_set_uconfig_reg(cs,
3024 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
3025 primitive_reset_en);
3026 } else {
3027 radeon_set_context_reg(cs,
3028 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
3029 primitive_reset_en);
3030 }
3031 }
3032
3033 if (primitive_reset_en) {
3034 uint32_t primitive_reset_index =
3035 radv_get_primitive_reset_index(cmd_buffer);
3036
3037 if (primitive_reset_index != state->last_primitive_reset_index) {
3038 radeon_set_context_reg(cs,
3039 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
3040 primitive_reset_index);
3041 state->last_primitive_reset_index = primitive_reset_index;
3042 }
3043 }
3044
3045 if (draw_info->strmout_buffer) {
3046 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
3047
3048 va += draw_info->strmout_buffer->offset +
3049 draw_info->strmout_buffer_offset;
3050
3051 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
3052 draw_info->stride);
3053
3054 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3055 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
3056 COPY_DATA_DST_SEL(COPY_DATA_REG) |
3057 COPY_DATA_WR_CONFIRM);
3058 radeon_emit(cs, va);
3059 radeon_emit(cs, va >> 32);
3060 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
3061 radeon_emit(cs, 0); /* unused */
3062
3063 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
3064 }
3065 }
3066
3067 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
3068 VkPipelineStageFlags src_stage_mask)
3069 {
3070 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
3071 VK_PIPELINE_STAGE_TRANSFER_BIT |
3072 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
3073 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
3074 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
3075 }
3076
3077 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
3078 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
3079 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
3080 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
3081 VK_PIPELINE_STAGE_TRANSFER_BIT |
3082 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
3083 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
3084 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
3085 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
3086 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
3087 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
3088 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
3089 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
3090 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
3091 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
3092 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
3093 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
3094 }
3095 }
3096
3097 static enum radv_cmd_flush_bits
3098 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
3099 VkAccessFlags src_flags,
3100 struct radv_image *image)
3101 {
3102 bool flush_CB_meta = true, flush_DB_meta = true;
3103 enum radv_cmd_flush_bits flush_bits = 0;
3104 uint32_t b;
3105
3106 if (image) {
3107 if (!radv_image_has_CB_metadata(image))
3108 flush_CB_meta = false;
3109 if (!radv_image_has_htile(image))
3110 flush_DB_meta = false;
3111 }
3112
3113 for_each_bit(b, src_flags) {
3114 switch ((VkAccessFlagBits)(1 << b)) {
3115 case VK_ACCESS_SHADER_WRITE_BIT:
3116 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
3117 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
3118 flush_bits |= RADV_CMD_FLAG_WB_L2;
3119 break;
3120 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
3121 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
3122 if (flush_CB_meta)
3123 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3124 break;
3125 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
3126 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
3127 if (flush_DB_meta)
3128 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3129 break;
3130 case VK_ACCESS_TRANSFER_WRITE_BIT:
3131 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3132 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3133 RADV_CMD_FLAG_INV_L2;
3134
3135 if (flush_CB_meta)
3136 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3137 if (flush_DB_meta)
3138 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3139 break;
3140 case VK_ACCESS_MEMORY_WRITE_BIT:
3141 flush_bits |= RADV_CMD_FLAG_INV_L2 |
3142 RADV_CMD_FLAG_WB_L2 |
3143 RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3144 RADV_CMD_FLAG_FLUSH_AND_INV_DB;
3145
3146 if (flush_CB_meta)
3147 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3148 if (flush_DB_meta)
3149 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3150 break;
3151 default:
3152 break;
3153 }
3154 }
3155 return flush_bits;
3156 }
3157
3158 static enum radv_cmd_flush_bits
3159 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
3160 VkAccessFlags dst_flags,
3161 struct radv_image *image)
3162 {
3163 bool flush_CB_meta = true, flush_DB_meta = true;
3164 enum radv_cmd_flush_bits flush_bits = 0;
3165 bool flush_CB = true, flush_DB = true;
3166 bool image_is_coherent = false;
3167 uint32_t b;
3168
3169 if (image) {
3170 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
3171 flush_CB = false;
3172 flush_DB = false;
3173 }
3174
3175 if (!radv_image_has_CB_metadata(image))
3176 flush_CB_meta = false;
3177 if (!radv_image_has_htile(image))
3178 flush_DB_meta = false;
3179
3180 /* TODO: implement shader coherent for GFX10 */
3181
3182 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
3183 if (image->info.samples == 1 &&
3184 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
3185 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
3186 !vk_format_is_stencil(image->vk_format)) {
3187 /* Single-sample color and single-sample depth
3188 * (not stencil) are coherent with shaders on
3189 * GFX9.
3190 */
3191 image_is_coherent = true;
3192 }
3193 }
3194 }
3195
3196 for_each_bit(b, dst_flags) {
3197 switch ((VkAccessFlagBits)(1 << b)) {
3198 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
3199 case VK_ACCESS_INDEX_READ_BIT:
3200 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
3201 break;
3202 case VK_ACCESS_UNIFORM_READ_BIT:
3203 flush_bits |= RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_SCACHE;
3204 break;
3205 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
3206 case VK_ACCESS_TRANSFER_READ_BIT:
3207 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
3208 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
3209 RADV_CMD_FLAG_INV_L2;
3210 break;
3211 case VK_ACCESS_SHADER_READ_BIT:
3212 flush_bits |= RADV_CMD_FLAG_INV_VCACHE;
3213 /* Unlike LLVM, ACO uses SMEM for SSBOs and we have to
3214 * invalidate the scalar cache. */
3215 if (!cmd_buffer->device->physical_device->use_llvm)
3216 flush_bits |= RADV_CMD_FLAG_INV_SCACHE;
3217
3218 if (!image_is_coherent)
3219 flush_bits |= RADV_CMD_FLAG_INV_L2;
3220 break;
3221 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
3222 if (flush_CB)
3223 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
3224 if (flush_CB_meta)
3225 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3226 break;
3227 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
3228 if (flush_DB)
3229 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
3230 if (flush_DB_meta)
3231 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3232 break;
3233 case VK_ACCESS_MEMORY_READ_BIT:
3234 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
3235 RADV_CMD_FLAG_INV_SCACHE |
3236 RADV_CMD_FLAG_INV_L2;
3237 if (flush_CB)
3238 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
3239 if (flush_CB_meta)
3240 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3241 if (flush_DB)
3242 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
3243 if (flush_DB_meta)
3244 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3245 break;
3246 default:
3247 break;
3248 }
3249 }
3250 return flush_bits;
3251 }
3252
3253 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
3254 const struct radv_subpass_barrier *barrier)
3255 {
3256 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
3257 NULL);
3258 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
3259 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
3260 NULL);
3261 }
3262
3263 uint32_t
3264 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
3265 {
3266 struct radv_cmd_state *state = &cmd_buffer->state;
3267 uint32_t subpass_id = state->subpass - state->pass->subpasses;
3268
3269 /* The id of this subpass shouldn't exceed the number of subpasses in
3270 * this render pass minus 1.
3271 */
3272 assert(subpass_id < state->pass->subpass_count);
3273 return subpass_id;
3274 }
3275
3276 static struct radv_sample_locations_state *
3277 radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer,
3278 uint32_t att_idx,
3279 bool begin_subpass)
3280 {
3281 struct radv_cmd_state *state = &cmd_buffer->state;
3282 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
3283 struct radv_image_view *view = state->attachments[att_idx].iview;
3284
3285 if (view->image->info.samples == 1)
3286 return NULL;
3287
3288 if (state->pass->attachments[att_idx].first_subpass_idx == subpass_id) {
3289 /* Return the initial sample locations if this is the initial
3290 * layout transition of the given subpass attachemnt.
3291 */
3292 if (state->attachments[att_idx].sample_location.count > 0)
3293 return &state->attachments[att_idx].sample_location;
3294 } else {
3295 /* Otherwise return the subpass sample locations if defined. */
3296 if (state->subpass_sample_locs) {
3297 /* Because the driver sets the current subpass before
3298 * initial layout transitions, we should use the sample
3299 * locations from the previous subpass to avoid an
3300 * off-by-one problem. Otherwise, use the sample
3301 * locations for the current subpass for final layout
3302 * transitions.
3303 */
3304 if (begin_subpass)
3305 subpass_id--;
3306
3307 for (uint32_t i = 0; i < state->num_subpass_sample_locs; i++) {
3308 if (state->subpass_sample_locs[i].subpass_idx == subpass_id)
3309 return &state->subpass_sample_locs[i].sample_location;
3310 }
3311 }
3312 }
3313
3314 return NULL;
3315 }
3316
3317 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
3318 struct radv_subpass_attachment att,
3319 bool begin_subpass)
3320 {
3321 unsigned idx = att.attachment;
3322 struct radv_image_view *view = cmd_buffer->state.attachments[idx].iview;
3323 struct radv_sample_locations_state *sample_locs;
3324 VkImageSubresourceRange range;
3325 range.aspectMask = view->aspect_mask;
3326 range.baseMipLevel = view->base_mip;
3327 range.levelCount = 1;
3328 range.baseArrayLayer = view->base_layer;
3329 range.layerCount = cmd_buffer->state.framebuffer->layers;
3330
3331 if (cmd_buffer->state.subpass->view_mask) {
3332 /* If the current subpass uses multiview, the driver might have
3333 * performed a fast color/depth clear to the whole image
3334 * (including all layers). To make sure the driver will
3335 * decompress the image correctly (if needed), we have to
3336 * account for the "real" number of layers. If the view mask is
3337 * sparse, this will decompress more layers than needed.
3338 */
3339 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
3340 }
3341
3342 /* Get the subpass sample locations for the given attachment, if NULL
3343 * is returned the driver will use the default HW locations.
3344 */
3345 sample_locs = radv_get_attachment_sample_locations(cmd_buffer, idx,
3346 begin_subpass);
3347
3348 /* Determine if the subpass uses separate depth/stencil layouts. */
3349 bool uses_separate_depth_stencil_layouts = false;
3350 if ((cmd_buffer->state.attachments[idx].current_layout !=
3351 cmd_buffer->state.attachments[idx].current_stencil_layout) ||
3352 (att.layout != att.stencil_layout)) {
3353 uses_separate_depth_stencil_layouts = true;
3354 }
3355
3356 /* For separate layouts, perform depth and stencil transitions
3357 * separately.
3358 */
3359 if (uses_separate_depth_stencil_layouts &&
3360 (range.aspectMask == (VK_IMAGE_ASPECT_DEPTH_BIT |
3361 VK_IMAGE_ASPECT_STENCIL_BIT))) {
3362 /* Depth-only transitions. */
3363 range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3364 radv_handle_image_transition(cmd_buffer,
3365 view->image,
3366 cmd_buffer->state.attachments[idx].current_layout,
3367 cmd_buffer->state.attachments[idx].current_in_render_loop,
3368 att.layout, att.in_render_loop,
3369 0, 0, &range, sample_locs);
3370
3371 /* Stencil-only transitions. */
3372 range.aspectMask = VK_IMAGE_ASPECT_STENCIL_BIT;
3373 radv_handle_image_transition(cmd_buffer,
3374 view->image,
3375 cmd_buffer->state.attachments[idx].current_stencil_layout,
3376 cmd_buffer->state.attachments[idx].current_in_render_loop,
3377 att.stencil_layout, att.in_render_loop,
3378 0, 0, &range, sample_locs);
3379 } else {
3380 radv_handle_image_transition(cmd_buffer,
3381 view->image,
3382 cmd_buffer->state.attachments[idx].current_layout,
3383 cmd_buffer->state.attachments[idx].current_in_render_loop,
3384 att.layout, att.in_render_loop,
3385 0, 0, &range, sample_locs);
3386 }
3387
3388 cmd_buffer->state.attachments[idx].current_layout = att.layout;
3389 cmd_buffer->state.attachments[idx].current_stencil_layout = att.stencil_layout;
3390 cmd_buffer->state.attachments[idx].current_in_render_loop = att.in_render_loop;
3391
3392
3393 }
3394
3395 void
3396 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
3397 const struct radv_subpass *subpass)
3398 {
3399 cmd_buffer->state.subpass = subpass;
3400
3401 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
3402 }
3403
3404 static VkResult
3405 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
3406 struct radv_render_pass *pass,
3407 const VkRenderPassBeginInfo *info)
3408 {
3409 const struct VkRenderPassSampleLocationsBeginInfoEXT *sample_locs =
3410 vk_find_struct_const(info->pNext,
3411 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT);
3412 struct radv_cmd_state *state = &cmd_buffer->state;
3413
3414 if (!sample_locs) {
3415 state->subpass_sample_locs = NULL;
3416 return VK_SUCCESS;
3417 }
3418
3419 for (uint32_t i = 0; i < sample_locs->attachmentInitialSampleLocationsCount; i++) {
3420 const VkAttachmentSampleLocationsEXT *att_sample_locs =
3421 &sample_locs->pAttachmentInitialSampleLocations[i];
3422 uint32_t att_idx = att_sample_locs->attachmentIndex;
3423 struct radv_image *image = cmd_buffer->state.attachments[att_idx].iview->image;
3424
3425 assert(vk_format_is_depth_or_stencil(image->vk_format));
3426
3427 /* From the Vulkan spec 1.1.108:
3428 *
3429 * "If the image referenced by the framebuffer attachment at
3430 * index attachmentIndex was not created with
3431 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
3432 * then the values specified in sampleLocationsInfo are
3433 * ignored."
3434 */
3435 if (!(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT))
3436 continue;
3437
3438 const VkSampleLocationsInfoEXT *sample_locs_info =
3439 &att_sample_locs->sampleLocationsInfo;
3440
3441 state->attachments[att_idx].sample_location.per_pixel =
3442 sample_locs_info->sampleLocationsPerPixel;
3443 state->attachments[att_idx].sample_location.grid_size =
3444 sample_locs_info->sampleLocationGridSize;
3445 state->attachments[att_idx].sample_location.count =
3446 sample_locs_info->sampleLocationsCount;
3447 typed_memcpy(&state->attachments[att_idx].sample_location.locations[0],
3448 sample_locs_info->pSampleLocations,
3449 sample_locs_info->sampleLocationsCount);
3450 }
3451
3452 state->subpass_sample_locs = vk_alloc(&cmd_buffer->pool->alloc,
3453 sample_locs->postSubpassSampleLocationsCount *
3454 sizeof(state->subpass_sample_locs[0]),
3455 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3456 if (state->subpass_sample_locs == NULL) {
3457 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3458 return cmd_buffer->record_result;
3459 }
3460
3461 state->num_subpass_sample_locs = sample_locs->postSubpassSampleLocationsCount;
3462
3463 for (uint32_t i = 0; i < sample_locs->postSubpassSampleLocationsCount; i++) {
3464 const VkSubpassSampleLocationsEXT *subpass_sample_locs_info =
3465 &sample_locs->pPostSubpassSampleLocations[i];
3466 const VkSampleLocationsInfoEXT *sample_locs_info =
3467 &subpass_sample_locs_info->sampleLocationsInfo;
3468
3469 state->subpass_sample_locs[i].subpass_idx =
3470 subpass_sample_locs_info->subpassIndex;
3471 state->subpass_sample_locs[i].sample_location.per_pixel =
3472 sample_locs_info->sampleLocationsPerPixel;
3473 state->subpass_sample_locs[i].sample_location.grid_size =
3474 sample_locs_info->sampleLocationGridSize;
3475 state->subpass_sample_locs[i].sample_location.count =
3476 sample_locs_info->sampleLocationsCount;
3477 typed_memcpy(&state->subpass_sample_locs[i].sample_location.locations[0],
3478 sample_locs_info->pSampleLocations,
3479 sample_locs_info->sampleLocationsCount);
3480 }
3481
3482 return VK_SUCCESS;
3483 }
3484
3485 static VkResult
3486 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
3487 struct radv_render_pass *pass,
3488 const VkRenderPassBeginInfo *info)
3489 {
3490 struct radv_cmd_state *state = &cmd_buffer->state;
3491 const struct VkRenderPassAttachmentBeginInfo *attachment_info = NULL;
3492
3493 if (info) {
3494 attachment_info = vk_find_struct_const(info->pNext,
3495 RENDER_PASS_ATTACHMENT_BEGIN_INFO);
3496 }
3497
3498
3499 if (pass->attachment_count == 0) {
3500 state->attachments = NULL;
3501 return VK_SUCCESS;
3502 }
3503
3504 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
3505 pass->attachment_count *
3506 sizeof(state->attachments[0]),
3507 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3508 if (state->attachments == NULL) {
3509 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3510 return cmd_buffer->record_result;
3511 }
3512
3513 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
3514 struct radv_render_pass_attachment *att = &pass->attachments[i];
3515 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
3516 VkImageAspectFlags clear_aspects = 0;
3517
3518 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
3519 /* color attachment */
3520 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3521 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
3522 }
3523 } else {
3524 /* depthstencil attachment */
3525 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
3526 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3527 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
3528 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3529 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
3530 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3531 }
3532 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3533 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3534 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3535 }
3536 }
3537
3538 state->attachments[i].pending_clear_aspects = clear_aspects;
3539 state->attachments[i].cleared_views = 0;
3540 if (clear_aspects && info) {
3541 assert(info->clearValueCount > i);
3542 state->attachments[i].clear_value = info->pClearValues[i];
3543 }
3544
3545 state->attachments[i].current_layout = att->initial_layout;
3546 state->attachments[i].current_stencil_layout = att->stencil_initial_layout;
3547 state->attachments[i].sample_location.count = 0;
3548
3549 struct radv_image_view *iview;
3550 if (attachment_info && attachment_info->attachmentCount > i) {
3551 iview = radv_image_view_from_handle(attachment_info->pAttachments[i]);
3552 } else {
3553 iview = state->framebuffer->attachments[i];
3554 }
3555
3556 state->attachments[i].iview = iview;
3557 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3558 radv_initialise_ds_surface(cmd_buffer->device, &state->attachments[i].ds, iview);
3559 } else {
3560 radv_initialise_color_surface(cmd_buffer->device, &state->attachments[i].cb, iview);
3561 }
3562 }
3563
3564 return VK_SUCCESS;
3565 }
3566
3567 VkResult radv_AllocateCommandBuffers(
3568 VkDevice _device,
3569 const VkCommandBufferAllocateInfo *pAllocateInfo,
3570 VkCommandBuffer *pCommandBuffers)
3571 {
3572 RADV_FROM_HANDLE(radv_device, device, _device);
3573 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
3574
3575 VkResult result = VK_SUCCESS;
3576 uint32_t i;
3577
3578 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
3579
3580 if (!list_is_empty(&pool->free_cmd_buffers)) {
3581 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
3582
3583 list_del(&cmd_buffer->pool_link);
3584 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
3585
3586 result = radv_reset_cmd_buffer(cmd_buffer);
3587 cmd_buffer->level = pAllocateInfo->level;
3588
3589 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
3590 } else {
3591 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
3592 &pCommandBuffers[i]);
3593 }
3594 if (result != VK_SUCCESS)
3595 break;
3596 }
3597
3598 if (result != VK_SUCCESS) {
3599 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
3600 i, pCommandBuffers);
3601
3602 /* From the Vulkan 1.0.66 spec:
3603 *
3604 * "vkAllocateCommandBuffers can be used to create multiple
3605 * command buffers. If the creation of any of those command
3606 * buffers fails, the implementation must destroy all
3607 * successfully created command buffer objects from this
3608 * command, set all entries of the pCommandBuffers array to
3609 * NULL and return the error."
3610 */
3611 memset(pCommandBuffers, 0,
3612 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
3613 }
3614
3615 return result;
3616 }
3617
3618 void radv_FreeCommandBuffers(
3619 VkDevice device,
3620 VkCommandPool commandPool,
3621 uint32_t commandBufferCount,
3622 const VkCommandBuffer *pCommandBuffers)
3623 {
3624 for (uint32_t i = 0; i < commandBufferCount; i++) {
3625 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
3626
3627 if (cmd_buffer) {
3628 if (cmd_buffer->pool) {
3629 list_del(&cmd_buffer->pool_link);
3630 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
3631 } else
3632 radv_destroy_cmd_buffer(cmd_buffer);
3633
3634 }
3635 }
3636 }
3637
3638 VkResult radv_ResetCommandBuffer(
3639 VkCommandBuffer commandBuffer,
3640 VkCommandBufferResetFlags flags)
3641 {
3642 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3643 return radv_reset_cmd_buffer(cmd_buffer);
3644 }
3645
3646 VkResult radv_BeginCommandBuffer(
3647 VkCommandBuffer commandBuffer,
3648 const VkCommandBufferBeginInfo *pBeginInfo)
3649 {
3650 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3651 VkResult result = VK_SUCCESS;
3652
3653 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
3654 /* If the command buffer has already been resetted with
3655 * vkResetCommandBuffer, no need to do it again.
3656 */
3657 result = radv_reset_cmd_buffer(cmd_buffer);
3658 if (result != VK_SUCCESS)
3659 return result;
3660 }
3661
3662 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
3663 cmd_buffer->state.last_primitive_reset_en = -1;
3664 cmd_buffer->state.last_index_type = -1;
3665 cmd_buffer->state.last_num_instances = -1;
3666 cmd_buffer->state.last_vertex_offset = -1;
3667 cmd_buffer->state.last_first_instance = -1;
3668 cmd_buffer->state.predication_type = -1;
3669 cmd_buffer->state.last_sx_ps_downconvert = -1;
3670 cmd_buffer->state.last_sx_blend_opt_epsilon = -1;
3671 cmd_buffer->state.last_sx_blend_opt_control = -1;
3672 cmd_buffer->usage_flags = pBeginInfo->flags;
3673
3674 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
3675 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
3676 assert(pBeginInfo->pInheritanceInfo);
3677 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
3678 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
3679
3680 struct radv_subpass *subpass =
3681 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
3682
3683 if (cmd_buffer->state.framebuffer) {
3684 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
3685 if (result != VK_SUCCESS)
3686 return result;
3687 }
3688
3689 cmd_buffer->state.inherited_pipeline_statistics =
3690 pBeginInfo->pInheritanceInfo->pipelineStatistics;
3691
3692 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3693 }
3694
3695 if (unlikely(cmd_buffer->device->trace_bo))
3696 radv_cmd_buffer_trace_emit(cmd_buffer);
3697
3698 radv_describe_begin_cmd_buffer(cmd_buffer);
3699
3700 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
3701
3702 return result;
3703 }
3704
3705 void radv_CmdBindVertexBuffers(
3706 VkCommandBuffer commandBuffer,
3707 uint32_t firstBinding,
3708 uint32_t bindingCount,
3709 const VkBuffer* pBuffers,
3710 const VkDeviceSize* pOffsets)
3711 {
3712 radv_CmdBindVertexBuffers2EXT(commandBuffer, firstBinding,
3713 bindingCount, pBuffers, pOffsets,
3714 NULL, NULL);
3715 }
3716
3717 void radv_CmdBindVertexBuffers2EXT(
3718 VkCommandBuffer commandBuffer,
3719 uint32_t firstBinding,
3720 uint32_t bindingCount,
3721 const VkBuffer* pBuffers,
3722 const VkDeviceSize* pOffsets,
3723 const VkDeviceSize* pSizes,
3724 const VkDeviceSize* pStrides)
3725 {
3726 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3727 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
3728 bool changed = false;
3729
3730 /* We have to defer setting up vertex buffer since we need the buffer
3731 * stride from the pipeline. */
3732
3733 assert(firstBinding + bindingCount <= MAX_VBS);
3734 for (uint32_t i = 0; i < bindingCount; i++) {
3735 RADV_FROM_HANDLE(radv_buffer, buffer, pBuffers[i]);
3736 uint32_t idx = firstBinding + i;
3737 VkDeviceSize size = pSizes ? pSizes[i] : 0;
3738 VkDeviceSize stride = pStrides ? pStrides[i] : 0;
3739
3740 /* pSizes and pStrides are optional. */
3741 if (!changed &&
3742 (vb[idx].buffer != buffer ||
3743 vb[idx].offset != pOffsets[i] ||
3744 vb[idx].size != size ||
3745 vb[idx].stride != stride)) {
3746 changed = true;
3747 }
3748
3749 vb[idx].buffer = buffer;
3750 vb[idx].offset = pOffsets[i];
3751 vb[idx].size = size;
3752 vb[idx].stride = stride;
3753
3754 if (buffer) {
3755 radv_cs_add_buffer(cmd_buffer->device->ws,
3756 cmd_buffer->cs, vb[idx].buffer->bo);
3757 }
3758 }
3759
3760 if (!changed) {
3761 /* No state changes. */
3762 return;
3763 }
3764
3765 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
3766 }
3767
3768 static uint32_t
3769 vk_to_index_type(VkIndexType type)
3770 {
3771 switch (type) {
3772 case VK_INDEX_TYPE_UINT8_EXT:
3773 return V_028A7C_VGT_INDEX_8;
3774 case VK_INDEX_TYPE_UINT16:
3775 return V_028A7C_VGT_INDEX_16;
3776 case VK_INDEX_TYPE_UINT32:
3777 return V_028A7C_VGT_INDEX_32;
3778 default:
3779 unreachable("invalid index type");
3780 }
3781 }
3782
3783 static uint32_t
3784 radv_get_vgt_index_size(uint32_t type)
3785 {
3786 switch (type) {
3787 case V_028A7C_VGT_INDEX_8:
3788 return 1;
3789 case V_028A7C_VGT_INDEX_16:
3790 return 2;
3791 case V_028A7C_VGT_INDEX_32:
3792 return 4;
3793 default:
3794 unreachable("invalid index type");
3795 }
3796 }
3797
3798 void radv_CmdBindIndexBuffer(
3799 VkCommandBuffer commandBuffer,
3800 VkBuffer buffer,
3801 VkDeviceSize offset,
3802 VkIndexType indexType)
3803 {
3804 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3805 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
3806
3807 if (cmd_buffer->state.index_buffer == index_buffer &&
3808 cmd_buffer->state.index_offset == offset &&
3809 cmd_buffer->state.index_type == indexType) {
3810 /* No state changes. */
3811 return;
3812 }
3813
3814 cmd_buffer->state.index_buffer = index_buffer;
3815 cmd_buffer->state.index_offset = offset;
3816 cmd_buffer->state.index_type = vk_to_index_type(indexType);
3817 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
3818 cmd_buffer->state.index_va += index_buffer->offset + offset;
3819
3820 int index_size = radv_get_vgt_index_size(vk_to_index_type(indexType));
3821 cmd_buffer->state.max_index_count = (index_buffer->size - offset) / index_size;
3822 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3823 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
3824 }
3825
3826
3827 static void
3828 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3829 VkPipelineBindPoint bind_point,
3830 struct radv_descriptor_set *set, unsigned idx)
3831 {
3832 struct radeon_winsys *ws = cmd_buffer->device->ws;
3833
3834 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
3835
3836 assert(set);
3837 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
3838
3839 if (!cmd_buffer->device->use_global_bo_list) {
3840 for (unsigned j = 0; j < set->buffer_count; ++j)
3841 if (set->descriptors[j])
3842 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
3843 }
3844
3845 if(set->bo)
3846 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
3847 }
3848
3849 void radv_CmdBindDescriptorSets(
3850 VkCommandBuffer commandBuffer,
3851 VkPipelineBindPoint pipelineBindPoint,
3852 VkPipelineLayout _layout,
3853 uint32_t firstSet,
3854 uint32_t descriptorSetCount,
3855 const VkDescriptorSet* pDescriptorSets,
3856 uint32_t dynamicOffsetCount,
3857 const uint32_t* pDynamicOffsets)
3858 {
3859 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3860 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3861 unsigned dyn_idx = 0;
3862
3863 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
3864 struct radv_descriptor_state *descriptors_state =
3865 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3866
3867 for (unsigned i = 0; i < descriptorSetCount; ++i) {
3868 unsigned idx = i + firstSet;
3869 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
3870
3871 /* If the set is already bound we only need to update the
3872 * (potentially changed) dynamic offsets. */
3873 if (descriptors_state->sets[idx] != set ||
3874 !(descriptors_state->valid & (1u << idx))) {
3875 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
3876 }
3877
3878 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
3879 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
3880 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
3881 assert(dyn_idx < dynamicOffsetCount);
3882
3883 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
3884 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
3885 dst[0] = va;
3886 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
3887 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
3888 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3889 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3890 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3891 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3892
3893 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
3894 dst[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3895 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3896 S_008F0C_RESOURCE_LEVEL(1);
3897 } else {
3898 dst[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3899 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3900 }
3901
3902 cmd_buffer->push_constant_stages |=
3903 set->layout->dynamic_shader_stages;
3904 }
3905 }
3906 }
3907
3908 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3909 struct radv_descriptor_set *set,
3910 struct radv_descriptor_set_layout *layout,
3911 VkPipelineBindPoint bind_point)
3912 {
3913 struct radv_descriptor_state *descriptors_state =
3914 radv_get_descriptors_state(cmd_buffer, bind_point);
3915 set->size = layout->size;
3916 set->layout = layout;
3917
3918 if (descriptors_state->push_set.capacity < set->size) {
3919 size_t new_size = MAX2(set->size, 1024);
3920 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
3921 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
3922
3923 free(set->mapped_ptr);
3924 set->mapped_ptr = malloc(new_size);
3925
3926 if (!set->mapped_ptr) {
3927 descriptors_state->push_set.capacity = 0;
3928 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3929 return false;
3930 }
3931
3932 descriptors_state->push_set.capacity = new_size;
3933 }
3934
3935 return true;
3936 }
3937
3938 void radv_meta_push_descriptor_set(
3939 struct radv_cmd_buffer* cmd_buffer,
3940 VkPipelineBindPoint pipelineBindPoint,
3941 VkPipelineLayout _layout,
3942 uint32_t set,
3943 uint32_t descriptorWriteCount,
3944 const VkWriteDescriptorSet* pDescriptorWrites)
3945 {
3946 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3947 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
3948 unsigned bo_offset;
3949
3950 assert(set == 0);
3951 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3952
3953 push_set->size = layout->set[set].layout->size;
3954 push_set->layout = layout->set[set].layout;
3955
3956 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
3957 &bo_offset,
3958 (void**) &push_set->mapped_ptr))
3959 return;
3960
3961 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
3962 push_set->va += bo_offset;
3963
3964 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3965 radv_descriptor_set_to_handle(push_set),
3966 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3967
3968 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3969 }
3970
3971 void radv_CmdPushDescriptorSetKHR(
3972 VkCommandBuffer commandBuffer,
3973 VkPipelineBindPoint pipelineBindPoint,
3974 VkPipelineLayout _layout,
3975 uint32_t set,
3976 uint32_t descriptorWriteCount,
3977 const VkWriteDescriptorSet* pDescriptorWrites)
3978 {
3979 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3980 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3981 struct radv_descriptor_state *descriptors_state =
3982 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3983 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3984
3985 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3986
3987 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3988 layout->set[set].layout,
3989 pipelineBindPoint))
3990 return;
3991
3992 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3993 * because it is invalid, according to Vulkan spec.
3994 */
3995 for (int i = 0; i < descriptorWriteCount; i++) {
3996 ASSERTED const VkWriteDescriptorSet *writeset = &pDescriptorWrites[i];
3997 assert(writeset->descriptorType != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT);
3998 }
3999
4000 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
4001 radv_descriptor_set_to_handle(push_set),
4002 descriptorWriteCount, pDescriptorWrites, 0, NULL);
4003
4004 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
4005 descriptors_state->push_dirty = true;
4006 }
4007
4008 void radv_CmdPushDescriptorSetWithTemplateKHR(
4009 VkCommandBuffer commandBuffer,
4010 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
4011 VkPipelineLayout _layout,
4012 uint32_t set,
4013 const void* pData)
4014 {
4015 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4016 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
4017 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
4018 struct radv_descriptor_state *descriptors_state =
4019 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
4020 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
4021
4022 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
4023
4024 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
4025 layout->set[set].layout,
4026 templ->bind_point))
4027 return;
4028
4029 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
4030 descriptorUpdateTemplate, pData);
4031
4032 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
4033 descriptors_state->push_dirty = true;
4034 }
4035
4036 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
4037 VkPipelineLayout layout,
4038 VkShaderStageFlags stageFlags,
4039 uint32_t offset,
4040 uint32_t size,
4041 const void* pValues)
4042 {
4043 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4044 memcpy(cmd_buffer->push_constants + offset, pValues, size);
4045 cmd_buffer->push_constant_stages |= stageFlags;
4046 }
4047
4048 VkResult radv_EndCommandBuffer(
4049 VkCommandBuffer commandBuffer)
4050 {
4051 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4052
4053 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
4054 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6)
4055 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WB_L2;
4056
4057 /* Make sure to sync all pending active queries at the end of
4058 * command buffer.
4059 */
4060 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
4061
4062 /* Since NGG streamout uses GDS, we need to make GDS idle when
4063 * we leave the IB, otherwise another process might overwrite
4064 * it while our shaders are busy.
4065 */
4066 if (cmd_buffer->gds_needed)
4067 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
4068
4069 si_emit_cache_flush(cmd_buffer);
4070 }
4071
4072 /* Make sure CP DMA is idle at the end of IBs because the kernel
4073 * doesn't wait for it.
4074 */
4075 si_cp_dma_wait_for_idle(cmd_buffer);
4076
4077 radv_describe_end_cmd_buffer(cmd_buffer);
4078
4079 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
4080 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
4081
4082 VkResult result = cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs);
4083 if (result != VK_SUCCESS)
4084 return vk_error(cmd_buffer->device->instance, result);
4085
4086 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
4087
4088 return cmd_buffer->record_result;
4089 }
4090
4091 static void
4092 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
4093 {
4094 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4095
4096 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
4097 return;
4098
4099 assert(!pipeline->ctx_cs.cdw);
4100
4101 cmd_buffer->state.emitted_compute_pipeline = pipeline;
4102
4103 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
4104 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
4105
4106 cmd_buffer->compute_scratch_size_per_wave_needed = MAX2(cmd_buffer->compute_scratch_size_per_wave_needed,
4107 pipeline->scratch_bytes_per_wave);
4108 cmd_buffer->compute_scratch_waves_wanted = MAX2(cmd_buffer->compute_scratch_waves_wanted,
4109 pipeline->max_waves);
4110
4111 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
4112 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
4113
4114 if (unlikely(cmd_buffer->device->trace_bo))
4115 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
4116 }
4117
4118 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
4119 VkPipelineBindPoint bind_point)
4120 {
4121 struct radv_descriptor_state *descriptors_state =
4122 radv_get_descriptors_state(cmd_buffer, bind_point);
4123
4124 descriptors_state->dirty |= descriptors_state->valid;
4125 }
4126
4127 void radv_CmdBindPipeline(
4128 VkCommandBuffer commandBuffer,
4129 VkPipelineBindPoint pipelineBindPoint,
4130 VkPipeline _pipeline)
4131 {
4132 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4133 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
4134
4135 switch (pipelineBindPoint) {
4136 case VK_PIPELINE_BIND_POINT_COMPUTE:
4137 if (cmd_buffer->state.compute_pipeline == pipeline)
4138 return;
4139 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
4140
4141 cmd_buffer->state.compute_pipeline = pipeline;
4142 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
4143 break;
4144 case VK_PIPELINE_BIND_POINT_GRAPHICS:
4145 if (cmd_buffer->state.pipeline == pipeline)
4146 return;
4147 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
4148
4149 cmd_buffer->state.pipeline = pipeline;
4150 if (!pipeline)
4151 break;
4152
4153 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
4154 cmd_buffer->push_constant_stages |= pipeline->active_stages;
4155
4156 /* the new vertex shader might not have the same user regs */
4157 cmd_buffer->state.last_first_instance = -1;
4158 cmd_buffer->state.last_vertex_offset = -1;
4159
4160 /* Prefetch all pipeline shaders at first draw time. */
4161 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
4162
4163 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX10 &&
4164 cmd_buffer->state.emitted_pipeline &&
4165 radv_pipeline_has_ngg(cmd_buffer->state.emitted_pipeline) &&
4166 !radv_pipeline_has_ngg(cmd_buffer->state.pipeline)) {
4167 /* Transitioning from NGG to legacy GS requires
4168 * VGT_FLUSH on Navi10-14. VGT_FLUSH is also emitted
4169 * at the beginning of IBs when legacy GS ring pointers
4170 * are set.
4171 */
4172 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
4173 }
4174
4175 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
4176 radv_bind_streamout_state(cmd_buffer, pipeline);
4177
4178 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
4179 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
4180 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
4181 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
4182
4183 if (radv_pipeline_has_tess(pipeline))
4184 cmd_buffer->tess_rings_needed = true;
4185 break;
4186 default:
4187 assert(!"invalid bind point");
4188 break;
4189 }
4190 }
4191
4192 void radv_CmdSetViewport(
4193 VkCommandBuffer commandBuffer,
4194 uint32_t firstViewport,
4195 uint32_t viewportCount,
4196 const VkViewport* pViewports)
4197 {
4198 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4199 struct radv_cmd_state *state = &cmd_buffer->state;
4200 ASSERTED const uint32_t total_count = firstViewport + viewportCount;
4201
4202 assert(firstViewport < MAX_VIEWPORTS);
4203 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
4204
4205 if (total_count <= state->dynamic.viewport.count &&
4206 !memcmp(state->dynamic.viewport.viewports + firstViewport,
4207 pViewports, viewportCount * sizeof(*pViewports))) {
4208 return;
4209 }
4210
4211 if (state->dynamic.viewport.count < total_count)
4212 state->dynamic.viewport.count = total_count;
4213
4214 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
4215 viewportCount * sizeof(*pViewports));
4216
4217 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
4218 }
4219
4220 void radv_CmdSetScissor(
4221 VkCommandBuffer commandBuffer,
4222 uint32_t firstScissor,
4223 uint32_t scissorCount,
4224 const VkRect2D* pScissors)
4225 {
4226 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4227 struct radv_cmd_state *state = &cmd_buffer->state;
4228 ASSERTED const uint32_t total_count = firstScissor + scissorCount;
4229
4230 assert(firstScissor < MAX_SCISSORS);
4231 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
4232
4233 if (total_count <= state->dynamic.scissor.count &&
4234 !memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
4235 scissorCount * sizeof(*pScissors))) {
4236 return;
4237 }
4238
4239 if (state->dynamic.scissor.count < total_count)
4240 state->dynamic.scissor.count = total_count;
4241
4242 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
4243 scissorCount * sizeof(*pScissors));
4244
4245 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
4246 }
4247
4248 void radv_CmdSetLineWidth(
4249 VkCommandBuffer commandBuffer,
4250 float lineWidth)
4251 {
4252 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4253
4254 if (cmd_buffer->state.dynamic.line_width == lineWidth)
4255 return;
4256
4257 cmd_buffer->state.dynamic.line_width = lineWidth;
4258 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
4259 }
4260
4261 void radv_CmdSetDepthBias(
4262 VkCommandBuffer commandBuffer,
4263 float depthBiasConstantFactor,
4264 float depthBiasClamp,
4265 float depthBiasSlopeFactor)
4266 {
4267 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4268 struct radv_cmd_state *state = &cmd_buffer->state;
4269
4270 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
4271 state->dynamic.depth_bias.clamp == depthBiasClamp &&
4272 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
4273 return;
4274 }
4275
4276 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
4277 state->dynamic.depth_bias.clamp = depthBiasClamp;
4278 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
4279
4280 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
4281 }
4282
4283 void radv_CmdSetBlendConstants(
4284 VkCommandBuffer commandBuffer,
4285 const float blendConstants[4])
4286 {
4287 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4288 struct radv_cmd_state *state = &cmd_buffer->state;
4289
4290 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
4291 return;
4292
4293 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
4294
4295 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
4296 }
4297
4298 void radv_CmdSetDepthBounds(
4299 VkCommandBuffer commandBuffer,
4300 float minDepthBounds,
4301 float maxDepthBounds)
4302 {
4303 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4304 struct radv_cmd_state *state = &cmd_buffer->state;
4305
4306 if (state->dynamic.depth_bounds.min == minDepthBounds &&
4307 state->dynamic.depth_bounds.max == maxDepthBounds) {
4308 return;
4309 }
4310
4311 state->dynamic.depth_bounds.min = minDepthBounds;
4312 state->dynamic.depth_bounds.max = maxDepthBounds;
4313
4314 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
4315 }
4316
4317 void radv_CmdSetStencilCompareMask(
4318 VkCommandBuffer commandBuffer,
4319 VkStencilFaceFlags faceMask,
4320 uint32_t compareMask)
4321 {
4322 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4323 struct radv_cmd_state *state = &cmd_buffer->state;
4324 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
4325 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
4326
4327 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4328 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4329 return;
4330 }
4331
4332 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4333 state->dynamic.stencil_compare_mask.front = compareMask;
4334 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4335 state->dynamic.stencil_compare_mask.back = compareMask;
4336
4337 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
4338 }
4339
4340 void radv_CmdSetStencilWriteMask(
4341 VkCommandBuffer commandBuffer,
4342 VkStencilFaceFlags faceMask,
4343 uint32_t writeMask)
4344 {
4345 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4346 struct radv_cmd_state *state = &cmd_buffer->state;
4347 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
4348 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
4349
4350 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4351 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4352 return;
4353 }
4354
4355 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4356 state->dynamic.stencil_write_mask.front = writeMask;
4357 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4358 state->dynamic.stencil_write_mask.back = writeMask;
4359
4360 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
4361 }
4362
4363 void radv_CmdSetStencilReference(
4364 VkCommandBuffer commandBuffer,
4365 VkStencilFaceFlags faceMask,
4366 uint32_t reference)
4367 {
4368 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4369 struct radv_cmd_state *state = &cmd_buffer->state;
4370 bool front_same = state->dynamic.stencil_reference.front == reference;
4371 bool back_same = state->dynamic.stencil_reference.back == reference;
4372
4373 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4374 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4375 return;
4376 }
4377
4378 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4379 cmd_buffer->state.dynamic.stencil_reference.front = reference;
4380 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4381 cmd_buffer->state.dynamic.stencil_reference.back = reference;
4382
4383 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
4384 }
4385
4386 void radv_CmdSetDiscardRectangleEXT(
4387 VkCommandBuffer commandBuffer,
4388 uint32_t firstDiscardRectangle,
4389 uint32_t discardRectangleCount,
4390 const VkRect2D* pDiscardRectangles)
4391 {
4392 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4393 struct radv_cmd_state *state = &cmd_buffer->state;
4394 ASSERTED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
4395
4396 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
4397 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
4398
4399 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
4400 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
4401 return;
4402 }
4403
4404 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
4405 pDiscardRectangles, discardRectangleCount);
4406
4407 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
4408 }
4409
4410 void radv_CmdSetSampleLocationsEXT(
4411 VkCommandBuffer commandBuffer,
4412 const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
4413 {
4414 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4415 struct radv_cmd_state *state = &cmd_buffer->state;
4416
4417 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
4418
4419 state->dynamic.sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
4420 state->dynamic.sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
4421 state->dynamic.sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
4422 typed_memcpy(&state->dynamic.sample_location.locations[0],
4423 pSampleLocationsInfo->pSampleLocations,
4424 pSampleLocationsInfo->sampleLocationsCount);
4425
4426 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS;
4427 }
4428
4429 void radv_CmdSetLineStippleEXT(
4430 VkCommandBuffer commandBuffer,
4431 uint32_t lineStippleFactor,
4432 uint16_t lineStipplePattern)
4433 {
4434 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4435 struct radv_cmd_state *state = &cmd_buffer->state;
4436
4437 state->dynamic.line_stipple.factor = lineStippleFactor;
4438 state->dynamic.line_stipple.pattern = lineStipplePattern;
4439
4440 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE;
4441 }
4442
4443 void radv_CmdSetCullModeEXT(
4444 VkCommandBuffer commandBuffer,
4445 VkCullModeFlags cullMode)
4446 {
4447 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4448 struct radv_cmd_state *state = &cmd_buffer->state;
4449
4450 if (state->dynamic.cull_mode == cullMode)
4451 return;
4452
4453 state->dynamic.cull_mode = cullMode;
4454
4455 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_CULL_MODE;
4456 }
4457
4458 void radv_CmdSetFrontFaceEXT(
4459 VkCommandBuffer commandBuffer,
4460 VkFrontFace frontFace)
4461 {
4462 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4463 struct radv_cmd_state *state = &cmd_buffer->state;
4464
4465 if (state->dynamic.front_face == frontFace)
4466 return;
4467
4468 state->dynamic.front_face = frontFace;
4469
4470 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE;
4471 }
4472
4473 void radv_CmdSetPrimitiveTopologyEXT(
4474 VkCommandBuffer commandBuffer,
4475 VkPrimitiveTopology primitiveTopology)
4476 {
4477 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4478 struct radv_cmd_state *state = &cmd_buffer->state;
4479 unsigned primitive_topology = si_translate_prim(primitiveTopology);
4480
4481 if (state->dynamic.primitive_topology == primitive_topology)
4482 return;
4483
4484 state->dynamic.primitive_topology = primitive_topology;
4485
4486 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY;
4487 }
4488
4489 void radv_CmdSetViewportWithCountEXT(
4490 VkCommandBuffer commandBuffer,
4491 uint32_t viewportCount,
4492 const VkViewport* pViewports)
4493 {
4494 radv_CmdSetViewport(commandBuffer, 0, viewportCount, pViewports);
4495 }
4496
4497 void radv_CmdSetScissorWithCountEXT(
4498 VkCommandBuffer commandBuffer,
4499 uint32_t scissorCount,
4500 const VkRect2D* pScissors)
4501 {
4502 radv_CmdSetScissor(commandBuffer, 0, scissorCount, pScissors);
4503 }
4504
4505 void radv_CmdSetDepthTestEnableEXT(
4506 VkCommandBuffer commandBuffer,
4507 VkBool32 depthTestEnable)
4508
4509 {
4510 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4511 struct radv_cmd_state *state = &cmd_buffer->state;
4512
4513 if (state->dynamic.depth_test_enable == depthTestEnable)
4514 return;
4515
4516 state->dynamic.depth_test_enable = depthTestEnable;
4517
4518 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE;
4519 }
4520
4521 void radv_CmdSetDepthWriteEnableEXT(
4522 VkCommandBuffer commandBuffer,
4523 VkBool32 depthWriteEnable)
4524 {
4525 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4526 struct radv_cmd_state *state = &cmd_buffer->state;
4527
4528 if (state->dynamic.depth_write_enable == depthWriteEnable)
4529 return;
4530
4531 state->dynamic.depth_write_enable = depthWriteEnable;
4532
4533 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE;
4534 }
4535
4536 void radv_CmdSetDepthCompareOpEXT(
4537 VkCommandBuffer commandBuffer,
4538 VkCompareOp depthCompareOp)
4539 {
4540 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4541 struct radv_cmd_state *state = &cmd_buffer->state;
4542
4543 if (state->dynamic.depth_compare_op == depthCompareOp)
4544 return;
4545
4546 state->dynamic.depth_compare_op = depthCompareOp;
4547
4548 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP;
4549 }
4550
4551 void radv_CmdSetDepthBoundsTestEnableEXT(
4552 VkCommandBuffer commandBuffer,
4553 VkBool32 depthBoundsTestEnable)
4554 {
4555 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4556 struct radv_cmd_state *state = &cmd_buffer->state;
4557
4558 if (state->dynamic.depth_bounds_test_enable == depthBoundsTestEnable)
4559 return;
4560
4561 state->dynamic.depth_bounds_test_enable = depthBoundsTestEnable;
4562
4563 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE;
4564 }
4565
4566 void radv_CmdSetStencilTestEnableEXT(
4567 VkCommandBuffer commandBuffer,
4568 VkBool32 stencilTestEnable)
4569 {
4570 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4571 struct radv_cmd_state *state = &cmd_buffer->state;
4572
4573 if (state->dynamic.stencil_test_enable == stencilTestEnable)
4574 return;
4575
4576 state->dynamic.stencil_test_enable = stencilTestEnable;
4577
4578 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE;
4579 }
4580
4581 void radv_CmdSetStencilOpEXT(
4582 VkCommandBuffer commandBuffer,
4583 VkStencilFaceFlags faceMask,
4584 VkStencilOp failOp,
4585 VkStencilOp passOp,
4586 VkStencilOp depthFailOp,
4587 VkCompareOp compareOp)
4588 {
4589 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4590 struct radv_cmd_state *state = &cmd_buffer->state;
4591 bool front_same =
4592 state->dynamic.stencil_op.front.fail_op == failOp &&
4593 state->dynamic.stencil_op.front.pass_op == passOp &&
4594 state->dynamic.stencil_op.front.depth_fail_op == depthFailOp &&
4595 state->dynamic.stencil_op.front.compare_op == compareOp;
4596 bool back_same =
4597 state->dynamic.stencil_op.back.fail_op == failOp &&
4598 state->dynamic.stencil_op.back.pass_op == passOp &&
4599 state->dynamic.stencil_op.back.depth_fail_op == depthFailOp &&
4600 state->dynamic.stencil_op.back.compare_op == compareOp;
4601
4602 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4603 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same))
4604 return;
4605
4606 if (faceMask & VK_STENCIL_FACE_FRONT_BIT) {
4607 state->dynamic.stencil_op.front.fail_op = failOp;
4608 state->dynamic.stencil_op.front.pass_op = passOp;
4609 state->dynamic.stencil_op.front.depth_fail_op = depthFailOp;
4610 state->dynamic.stencil_op.front.compare_op = compareOp;
4611 }
4612
4613 if (faceMask & VK_STENCIL_FACE_BACK_BIT) {
4614 state->dynamic.stencil_op.back.fail_op = failOp;
4615 state->dynamic.stencil_op.back.pass_op = passOp;
4616 state->dynamic.stencil_op.back.depth_fail_op = depthFailOp;
4617 state->dynamic.stencil_op.back.compare_op = compareOp;
4618 }
4619
4620 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP;
4621 }
4622
4623 void radv_CmdExecuteCommands(
4624 VkCommandBuffer commandBuffer,
4625 uint32_t commandBufferCount,
4626 const VkCommandBuffer* pCmdBuffers)
4627 {
4628 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
4629
4630 assert(commandBufferCount > 0);
4631
4632 /* Emit pending flushes on primary prior to executing secondary */
4633 si_emit_cache_flush(primary);
4634
4635 for (uint32_t i = 0; i < commandBufferCount; i++) {
4636 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
4637
4638 primary->scratch_size_per_wave_needed = MAX2(primary->scratch_size_per_wave_needed,
4639 secondary->scratch_size_per_wave_needed);
4640 primary->scratch_waves_wanted = MAX2(primary->scratch_waves_wanted,
4641 secondary->scratch_waves_wanted);
4642 primary->compute_scratch_size_per_wave_needed = MAX2(primary->compute_scratch_size_per_wave_needed,
4643 secondary->compute_scratch_size_per_wave_needed);
4644 primary->compute_scratch_waves_wanted = MAX2(primary->compute_scratch_waves_wanted,
4645 secondary->compute_scratch_waves_wanted);
4646
4647 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
4648 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
4649 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
4650 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
4651 if (secondary->tess_rings_needed)
4652 primary->tess_rings_needed = true;
4653 if (secondary->sample_positions_needed)
4654 primary->sample_positions_needed = true;
4655 if (secondary->gds_needed)
4656 primary->gds_needed = true;
4657
4658 if (!secondary->state.framebuffer &&
4659 (primary->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)) {
4660 /* Emit the framebuffer state from primary if secondary
4661 * has been recorded without a framebuffer, otherwise
4662 * fast color/depth clears can't work.
4663 */
4664 radv_emit_framebuffer_state(primary);
4665 }
4666
4667 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
4668
4669
4670 /* When the secondary command buffer is compute only we don't
4671 * need to re-emit the current graphics pipeline.
4672 */
4673 if (secondary->state.emitted_pipeline) {
4674 primary->state.emitted_pipeline =
4675 secondary->state.emitted_pipeline;
4676 }
4677
4678 /* When the secondary command buffer is graphics only we don't
4679 * need to re-emit the current compute pipeline.
4680 */
4681 if (secondary->state.emitted_compute_pipeline) {
4682 primary->state.emitted_compute_pipeline =
4683 secondary->state.emitted_compute_pipeline;
4684 }
4685
4686 /* Only re-emit the draw packets when needed. */
4687 if (secondary->state.last_primitive_reset_en != -1) {
4688 primary->state.last_primitive_reset_en =
4689 secondary->state.last_primitive_reset_en;
4690 }
4691
4692 if (secondary->state.last_primitive_reset_index) {
4693 primary->state.last_primitive_reset_index =
4694 secondary->state.last_primitive_reset_index;
4695 }
4696
4697 if (secondary->state.last_ia_multi_vgt_param) {
4698 primary->state.last_ia_multi_vgt_param =
4699 secondary->state.last_ia_multi_vgt_param;
4700 }
4701
4702 primary->state.last_first_instance = secondary->state.last_first_instance;
4703 primary->state.last_num_instances = secondary->state.last_num_instances;
4704 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
4705 primary->state.last_sx_ps_downconvert = secondary->state.last_sx_ps_downconvert;
4706 primary->state.last_sx_blend_opt_epsilon = secondary->state.last_sx_blend_opt_epsilon;
4707 primary->state.last_sx_blend_opt_control = secondary->state.last_sx_blend_opt_control;
4708
4709 if (secondary->state.last_index_type != -1) {
4710 primary->state.last_index_type =
4711 secondary->state.last_index_type;
4712 }
4713 }
4714
4715 /* After executing commands from secondary buffers we have to dirty
4716 * some states.
4717 */
4718 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
4719 RADV_CMD_DIRTY_INDEX_BUFFER |
4720 RADV_CMD_DIRTY_DYNAMIC_ALL;
4721 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
4722 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
4723 }
4724
4725 VkResult radv_CreateCommandPool(
4726 VkDevice _device,
4727 const VkCommandPoolCreateInfo* pCreateInfo,
4728 const VkAllocationCallbacks* pAllocator,
4729 VkCommandPool* pCmdPool)
4730 {
4731 RADV_FROM_HANDLE(radv_device, device, _device);
4732 struct radv_cmd_pool *pool;
4733
4734 pool = vk_alloc2(&device->vk.alloc, pAllocator, sizeof(*pool), 8,
4735 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4736 if (pool == NULL)
4737 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4738
4739 vk_object_base_init(&device->vk, &pool->base,
4740 VK_OBJECT_TYPE_COMMAND_POOL);
4741
4742 if (pAllocator)
4743 pool->alloc = *pAllocator;
4744 else
4745 pool->alloc = device->vk.alloc;
4746
4747 list_inithead(&pool->cmd_buffers);
4748 list_inithead(&pool->free_cmd_buffers);
4749
4750 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
4751
4752 *pCmdPool = radv_cmd_pool_to_handle(pool);
4753
4754 return VK_SUCCESS;
4755
4756 }
4757
4758 void radv_DestroyCommandPool(
4759 VkDevice _device,
4760 VkCommandPool commandPool,
4761 const VkAllocationCallbacks* pAllocator)
4762 {
4763 RADV_FROM_HANDLE(radv_device, device, _device);
4764 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4765
4766 if (!pool)
4767 return;
4768
4769 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4770 &pool->cmd_buffers, pool_link) {
4771 radv_destroy_cmd_buffer(cmd_buffer);
4772 }
4773
4774 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4775 &pool->free_cmd_buffers, pool_link) {
4776 radv_destroy_cmd_buffer(cmd_buffer);
4777 }
4778
4779 vk_object_base_finish(&pool->base);
4780 vk_free2(&device->vk.alloc, pAllocator, pool);
4781 }
4782
4783 VkResult radv_ResetCommandPool(
4784 VkDevice device,
4785 VkCommandPool commandPool,
4786 VkCommandPoolResetFlags flags)
4787 {
4788 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4789 VkResult result;
4790
4791 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
4792 &pool->cmd_buffers, pool_link) {
4793 result = radv_reset_cmd_buffer(cmd_buffer);
4794 if (result != VK_SUCCESS)
4795 return result;
4796 }
4797
4798 return VK_SUCCESS;
4799 }
4800
4801 void radv_TrimCommandPool(
4802 VkDevice device,
4803 VkCommandPool commandPool,
4804 VkCommandPoolTrimFlags flags)
4805 {
4806 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4807
4808 if (!pool)
4809 return;
4810
4811 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4812 &pool->free_cmd_buffers, pool_link) {
4813 radv_destroy_cmd_buffer(cmd_buffer);
4814 }
4815 }
4816
4817 static void
4818 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
4819 uint32_t subpass_id)
4820 {
4821 struct radv_cmd_state *state = &cmd_buffer->state;
4822 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
4823
4824 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
4825 cmd_buffer->cs, 4096);
4826
4827 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
4828
4829 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
4830
4831 radv_describe_barrier_start(cmd_buffer, RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC);
4832
4833 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4834 const uint32_t a = subpass->attachments[i].attachment;
4835 if (a == VK_ATTACHMENT_UNUSED)
4836 continue;
4837
4838 radv_handle_subpass_image_transition(cmd_buffer,
4839 subpass->attachments[i],
4840 true);
4841 }
4842
4843 radv_describe_barrier_end(cmd_buffer);
4844
4845 radv_cmd_buffer_clear_subpass(cmd_buffer);
4846
4847 assert(cmd_buffer->cs->cdw <= cdw_max);
4848 }
4849
4850 static void
4851 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
4852 {
4853 struct radv_cmd_state *state = &cmd_buffer->state;
4854 const struct radv_subpass *subpass = state->subpass;
4855 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
4856
4857 radv_cmd_buffer_resolve_subpass(cmd_buffer);
4858
4859 radv_describe_barrier_start(cmd_buffer, RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC);
4860
4861 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4862 const uint32_t a = subpass->attachments[i].attachment;
4863 if (a == VK_ATTACHMENT_UNUSED)
4864 continue;
4865
4866 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
4867 continue;
4868
4869 VkImageLayout layout = state->pass->attachments[a].final_layout;
4870 VkImageLayout stencil_layout = state->pass->attachments[a].stencil_final_layout;
4871 struct radv_subpass_attachment att = { a, layout, stencil_layout };
4872 radv_handle_subpass_image_transition(cmd_buffer, att, false);
4873 }
4874
4875 radv_describe_barrier_end(cmd_buffer);
4876 }
4877
4878 void
4879 radv_cmd_buffer_begin_render_pass(struct radv_cmd_buffer *cmd_buffer,
4880 const VkRenderPassBeginInfo *pRenderPassBegin)
4881 {
4882 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
4883 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
4884 VkResult result;
4885
4886 cmd_buffer->state.framebuffer = framebuffer;
4887 cmd_buffer->state.pass = pass;
4888 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
4889
4890 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
4891 if (result != VK_SUCCESS)
4892 return;
4893
4894 result = radv_cmd_state_setup_sample_locations(cmd_buffer, pass, pRenderPassBegin);
4895 if (result != VK_SUCCESS)
4896 return;
4897 }
4898
4899 void radv_CmdBeginRenderPass(
4900 VkCommandBuffer commandBuffer,
4901 const VkRenderPassBeginInfo* pRenderPassBegin,
4902 VkSubpassContents contents)
4903 {
4904 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4905
4906 radv_cmd_buffer_begin_render_pass(cmd_buffer, pRenderPassBegin);
4907
4908 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
4909 }
4910
4911 void radv_CmdBeginRenderPass2(
4912 VkCommandBuffer commandBuffer,
4913 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
4914 const VkSubpassBeginInfo* pSubpassBeginInfo)
4915 {
4916 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
4917 pSubpassBeginInfo->contents);
4918 }
4919
4920 void radv_CmdNextSubpass(
4921 VkCommandBuffer commandBuffer,
4922 VkSubpassContents contents)
4923 {
4924 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4925
4926 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
4927 radv_cmd_buffer_end_subpass(cmd_buffer);
4928 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
4929 }
4930
4931 void radv_CmdNextSubpass2(
4932 VkCommandBuffer commandBuffer,
4933 const VkSubpassBeginInfo* pSubpassBeginInfo,
4934 const VkSubpassEndInfo* pSubpassEndInfo)
4935 {
4936 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
4937 }
4938
4939 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
4940 {
4941 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
4942 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
4943 if (!radv_get_shader(pipeline, stage))
4944 continue;
4945
4946 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
4947 if (loc->sgpr_idx == -1)
4948 continue;
4949 uint32_t base_reg = pipeline->user_data_0[stage];
4950 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4951
4952 }
4953 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
4954 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
4955 if (loc->sgpr_idx != -1) {
4956 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
4957 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4958 }
4959 }
4960 }
4961
4962 static void
4963 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4964 uint32_t vertex_count,
4965 bool use_opaque)
4966 {
4967 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
4968 radeon_emit(cmd_buffer->cs, vertex_count);
4969 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
4970 S_0287F0_USE_OPAQUE(use_opaque));
4971 }
4972
4973 static void
4974 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
4975 uint64_t index_va,
4976 uint32_t index_count)
4977 {
4978 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
4979 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
4980 radeon_emit(cmd_buffer->cs, index_va);
4981 radeon_emit(cmd_buffer->cs, index_va >> 32);
4982 radeon_emit(cmd_buffer->cs, index_count);
4983 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
4984 }
4985
4986 static void
4987 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4988 bool indexed,
4989 uint32_t draw_count,
4990 uint64_t count_va,
4991 uint32_t stride)
4992 {
4993 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4994 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
4995 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
4996 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id;
4997 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
4998 bool predicating = cmd_buffer->state.predicating;
4999 assert(base_reg);
5000
5001 /* just reset draw state for vertex data */
5002 cmd_buffer->state.last_first_instance = -1;
5003 cmd_buffer->state.last_num_instances = -1;
5004 cmd_buffer->state.last_vertex_offset = -1;
5005
5006 if (draw_count == 1 && !count_va && !draw_id_enable) {
5007 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
5008 PKT3_DRAW_INDIRECT, 3, predicating));
5009 radeon_emit(cs, 0);
5010 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
5011 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
5012 radeon_emit(cs, di_src_sel);
5013 } else {
5014 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
5015 PKT3_DRAW_INDIRECT_MULTI,
5016 8, predicating));
5017 radeon_emit(cs, 0);
5018 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
5019 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
5020 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
5021 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
5022 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
5023 radeon_emit(cs, draw_count); /* count */
5024 radeon_emit(cs, count_va); /* count_addr */
5025 radeon_emit(cs, count_va >> 32);
5026 radeon_emit(cs, stride); /* stride */
5027 radeon_emit(cs, di_src_sel);
5028 }
5029 }
5030
5031 static void
5032 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
5033 const struct radv_draw_info *info)
5034 {
5035 struct radv_cmd_state *state = &cmd_buffer->state;
5036 struct radeon_winsys *ws = cmd_buffer->device->ws;
5037 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5038
5039 if (info->indirect) {
5040 uint64_t va = radv_buffer_get_va(info->indirect->bo);
5041 uint64_t count_va = 0;
5042
5043 va += info->indirect->offset + info->indirect_offset;
5044
5045 radv_cs_add_buffer(ws, cs, info->indirect->bo);
5046
5047 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
5048 radeon_emit(cs, 1);
5049 radeon_emit(cs, va);
5050 radeon_emit(cs, va >> 32);
5051
5052 if (info->count_buffer) {
5053 count_va = radv_buffer_get_va(info->count_buffer->bo);
5054 count_va += info->count_buffer->offset +
5055 info->count_buffer_offset;
5056
5057 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
5058 }
5059
5060 if (!state->subpass->view_mask) {
5061 radv_cs_emit_indirect_draw_packet(cmd_buffer,
5062 info->indexed,
5063 info->count,
5064 count_va,
5065 info->stride);
5066 } else {
5067 unsigned i;
5068 for_each_bit(i, state->subpass->view_mask) {
5069 radv_emit_view_index(cmd_buffer, i);
5070
5071 radv_cs_emit_indirect_draw_packet(cmd_buffer,
5072 info->indexed,
5073 info->count,
5074 count_va,
5075 info->stride);
5076 }
5077 }
5078 } else {
5079 assert(state->pipeline->graphics.vtx_base_sgpr);
5080
5081 if (info->vertex_offset != state->last_vertex_offset ||
5082 info->first_instance != state->last_first_instance) {
5083 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
5084 state->pipeline->graphics.vtx_emit_num);
5085
5086 radeon_emit(cs, info->vertex_offset);
5087 radeon_emit(cs, info->first_instance);
5088 if (state->pipeline->graphics.vtx_emit_num == 3)
5089 radeon_emit(cs, 0);
5090 state->last_first_instance = info->first_instance;
5091 state->last_vertex_offset = info->vertex_offset;
5092 }
5093
5094 if (state->last_num_instances != info->instance_count) {
5095 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
5096 radeon_emit(cs, info->instance_count);
5097 state->last_num_instances = info->instance_count;
5098 }
5099
5100 if (info->indexed) {
5101 int index_size = radv_get_vgt_index_size(state->index_type);
5102 uint64_t index_va;
5103
5104 /* Skip draw calls with 0-sized index buffers. They
5105 * cause a hang on some chips, like Navi10-14.
5106 */
5107 if (!cmd_buffer->state.max_index_count)
5108 return;
5109
5110 index_va = state->index_va;
5111 index_va += info->first_index * index_size;
5112
5113 if (!state->subpass->view_mask) {
5114 radv_cs_emit_draw_indexed_packet(cmd_buffer,
5115 index_va,
5116 info->count);
5117 } else {
5118 unsigned i;
5119 for_each_bit(i, state->subpass->view_mask) {
5120 radv_emit_view_index(cmd_buffer, i);
5121
5122 radv_cs_emit_draw_indexed_packet(cmd_buffer,
5123 index_va,
5124 info->count);
5125 }
5126 }
5127 } else {
5128 if (!state->subpass->view_mask) {
5129 radv_cs_emit_draw_packet(cmd_buffer,
5130 info->count,
5131 !!info->strmout_buffer);
5132 } else {
5133 unsigned i;
5134 for_each_bit(i, state->subpass->view_mask) {
5135 radv_emit_view_index(cmd_buffer, i);
5136
5137 radv_cs_emit_draw_packet(cmd_buffer,
5138 info->count,
5139 !!info->strmout_buffer);
5140 }
5141 }
5142 }
5143 }
5144 }
5145
5146 /*
5147 * Vega and raven have a bug which triggers if there are multiple context
5148 * register contexts active at the same time with different scissor values.
5149 *
5150 * There are two possible workarounds:
5151 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
5152 * there is only ever 1 active set of scissor values at the same time.
5153 *
5154 * 2) Whenever the hardware switches contexts we have to set the scissor
5155 * registers again even if it is a noop. That way the new context gets
5156 * the correct scissor values.
5157 *
5158 * This implements option 2. radv_need_late_scissor_emission needs to
5159 * return true on affected HW if radv_emit_all_graphics_states sets
5160 * any context registers.
5161 */
5162 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
5163 const struct radv_draw_info *info)
5164 {
5165 struct radv_cmd_state *state = &cmd_buffer->state;
5166
5167 if (!cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
5168 return false;
5169
5170 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
5171 return true;
5172
5173 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
5174
5175 /* Index, vertex and streamout buffers don't change context regs, and
5176 * pipeline is already handled.
5177 */
5178 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
5179 RADV_CMD_DIRTY_VERTEX_BUFFER |
5180 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
5181 RADV_CMD_DIRTY_PIPELINE);
5182
5183 if (cmd_buffer->state.dirty & used_states)
5184 return true;
5185
5186 uint32_t primitive_reset_index =
5187 radv_get_primitive_reset_index(cmd_buffer);
5188
5189 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
5190 primitive_reset_index != state->last_primitive_reset_index)
5191 return true;
5192
5193 return false;
5194 }
5195
5196 static void
5197 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
5198 const struct radv_draw_info *info)
5199 {
5200 bool late_scissor_emission;
5201
5202 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
5203 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
5204 radv_emit_rbplus_state(cmd_buffer);
5205
5206 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
5207 radv_emit_graphics_pipeline(cmd_buffer);
5208
5209 /* This should be before the cmd_buffer->state.dirty is cleared
5210 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
5211 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
5212 late_scissor_emission =
5213 radv_need_late_scissor_emission(cmd_buffer, info);
5214
5215 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
5216 radv_emit_framebuffer_state(cmd_buffer);
5217
5218 if (info->indexed) {
5219 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
5220 radv_emit_index_buffer(cmd_buffer, info->indirect);
5221 } else {
5222 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
5223 * so the state must be re-emitted before the next indexed
5224 * draw.
5225 */
5226 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
5227 cmd_buffer->state.last_index_type = -1;
5228 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
5229 }
5230 }
5231
5232 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
5233
5234 radv_emit_draw_registers(cmd_buffer, info);
5235
5236 if (late_scissor_emission)
5237 radv_emit_scissor(cmd_buffer);
5238 }
5239
5240 static void
5241 radv_draw(struct radv_cmd_buffer *cmd_buffer,
5242 const struct radv_draw_info *info)
5243 {
5244 struct radeon_info *rad_info =
5245 &cmd_buffer->device->physical_device->rad_info;
5246 bool has_prefetch =
5247 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
5248 bool pipeline_is_dirty =
5249 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
5250 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
5251
5252 ASSERTED unsigned cdw_max =
5253 radeon_check_space(cmd_buffer->device->ws,
5254 cmd_buffer->cs, 4096);
5255
5256 if (likely(!info->indirect)) {
5257 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
5258 * no workaround for indirect draws, but we can at least skip
5259 * direct draws.
5260 */
5261 if (unlikely(!info->instance_count))
5262 return;
5263
5264 /* Handle count == 0. */
5265 if (unlikely(!info->count && !info->strmout_buffer))
5266 return;
5267 }
5268
5269 radv_describe_draw(cmd_buffer);
5270
5271 /* Use optimal packet order based on whether we need to sync the
5272 * pipeline.
5273 */
5274 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5275 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5276 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
5277 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
5278 /* If we have to wait for idle, set all states first, so that
5279 * all SET packets are processed in parallel with previous draw
5280 * calls. Then upload descriptors, set shader pointers, and
5281 * draw, and prefetch at the end. This ensures that the time
5282 * the CUs are idle is very short. (there are only SET_SH
5283 * packets between the wait and the draw)
5284 */
5285 radv_emit_all_graphics_states(cmd_buffer, info);
5286 si_emit_cache_flush(cmd_buffer);
5287 /* <-- CUs are idle here --> */
5288
5289 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
5290
5291 radv_emit_draw_packets(cmd_buffer, info);
5292 /* <-- CUs are busy here --> */
5293
5294 /* Start prefetches after the draw has been started. Both will
5295 * run in parallel, but starting the draw first is more
5296 * important.
5297 */
5298 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
5299 radv_emit_prefetch_L2(cmd_buffer,
5300 cmd_buffer->state.pipeline, false);
5301 }
5302 } else {
5303 /* If we don't wait for idle, start prefetches first, then set
5304 * states, and draw at the end.
5305 */
5306 si_emit_cache_flush(cmd_buffer);
5307
5308 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
5309 /* Only prefetch the vertex shader and VBO descriptors
5310 * in order to start the draw as soon as possible.
5311 */
5312 radv_emit_prefetch_L2(cmd_buffer,
5313 cmd_buffer->state.pipeline, true);
5314 }
5315
5316 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
5317
5318 radv_emit_all_graphics_states(cmd_buffer, info);
5319 radv_emit_draw_packets(cmd_buffer, info);
5320
5321 /* Prefetch the remaining shaders after the draw has been
5322 * started.
5323 */
5324 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
5325 radv_emit_prefetch_L2(cmd_buffer,
5326 cmd_buffer->state.pipeline, false);
5327 }
5328 }
5329
5330 /* Workaround for a VGT hang when streamout is enabled.
5331 * It must be done after drawing.
5332 */
5333 if (cmd_buffer->state.streamout.streamout_enabled &&
5334 (rad_info->family == CHIP_HAWAII ||
5335 rad_info->family == CHIP_TONGA ||
5336 rad_info->family == CHIP_FIJI)) {
5337 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
5338 }
5339
5340 assert(cmd_buffer->cs->cdw <= cdw_max);
5341 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
5342 }
5343
5344 void radv_CmdDraw(
5345 VkCommandBuffer commandBuffer,
5346 uint32_t vertexCount,
5347 uint32_t instanceCount,
5348 uint32_t firstVertex,
5349 uint32_t firstInstance)
5350 {
5351 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5352 struct radv_draw_info info = {};
5353
5354 info.count = vertexCount;
5355 info.instance_count = instanceCount;
5356 info.first_instance = firstInstance;
5357 info.vertex_offset = firstVertex;
5358
5359 radv_draw(cmd_buffer, &info);
5360 }
5361
5362 void radv_CmdDrawIndexed(
5363 VkCommandBuffer commandBuffer,
5364 uint32_t indexCount,
5365 uint32_t instanceCount,
5366 uint32_t firstIndex,
5367 int32_t vertexOffset,
5368 uint32_t firstInstance)
5369 {
5370 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5371 struct radv_draw_info info = {};
5372
5373 info.indexed = true;
5374 info.count = indexCount;
5375 info.instance_count = instanceCount;
5376 info.first_index = firstIndex;
5377 info.vertex_offset = vertexOffset;
5378 info.first_instance = firstInstance;
5379
5380 radv_draw(cmd_buffer, &info);
5381 }
5382
5383 void radv_CmdDrawIndirect(
5384 VkCommandBuffer commandBuffer,
5385 VkBuffer _buffer,
5386 VkDeviceSize offset,
5387 uint32_t drawCount,
5388 uint32_t stride)
5389 {
5390 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5391 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5392 struct radv_draw_info info = {};
5393
5394 info.count = drawCount;
5395 info.indirect = buffer;
5396 info.indirect_offset = offset;
5397 info.stride = stride;
5398
5399 radv_draw(cmd_buffer, &info);
5400 }
5401
5402 void radv_CmdDrawIndexedIndirect(
5403 VkCommandBuffer commandBuffer,
5404 VkBuffer _buffer,
5405 VkDeviceSize offset,
5406 uint32_t drawCount,
5407 uint32_t stride)
5408 {
5409 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5410 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5411 struct radv_draw_info info = {};
5412
5413 info.indexed = true;
5414 info.count = drawCount;
5415 info.indirect = buffer;
5416 info.indirect_offset = offset;
5417 info.stride = stride;
5418
5419 radv_draw(cmd_buffer, &info);
5420 }
5421
5422 void radv_CmdDrawIndirectCount(
5423 VkCommandBuffer commandBuffer,
5424 VkBuffer _buffer,
5425 VkDeviceSize offset,
5426 VkBuffer _countBuffer,
5427 VkDeviceSize countBufferOffset,
5428 uint32_t maxDrawCount,
5429 uint32_t stride)
5430 {
5431 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5432 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5433 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
5434 struct radv_draw_info info = {};
5435
5436 info.count = maxDrawCount;
5437 info.indirect = buffer;
5438 info.indirect_offset = offset;
5439 info.count_buffer = count_buffer;
5440 info.count_buffer_offset = countBufferOffset;
5441 info.stride = stride;
5442
5443 radv_draw(cmd_buffer, &info);
5444 }
5445
5446 void radv_CmdDrawIndexedIndirectCount(
5447 VkCommandBuffer commandBuffer,
5448 VkBuffer _buffer,
5449 VkDeviceSize offset,
5450 VkBuffer _countBuffer,
5451 VkDeviceSize countBufferOffset,
5452 uint32_t maxDrawCount,
5453 uint32_t stride)
5454 {
5455 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5456 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5457 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
5458 struct radv_draw_info info = {};
5459
5460 info.indexed = true;
5461 info.count = maxDrawCount;
5462 info.indirect = buffer;
5463 info.indirect_offset = offset;
5464 info.count_buffer = count_buffer;
5465 info.count_buffer_offset = countBufferOffset;
5466 info.stride = stride;
5467
5468 radv_draw(cmd_buffer, &info);
5469 }
5470
5471 struct radv_dispatch_info {
5472 /**
5473 * Determine the layout of the grid (in block units) to be used.
5474 */
5475 uint32_t blocks[3];
5476
5477 /**
5478 * A starting offset for the grid. If unaligned is set, the offset
5479 * must still be aligned.
5480 */
5481 uint32_t offsets[3];
5482 /**
5483 * Whether it's an unaligned compute dispatch.
5484 */
5485 bool unaligned;
5486
5487 /**
5488 * Indirect compute parameters resource.
5489 */
5490 struct radv_buffer *indirect;
5491 uint64_t indirect_offset;
5492 };
5493
5494 static void
5495 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
5496 const struct radv_dispatch_info *info)
5497 {
5498 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
5499 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
5500 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
5501 struct radeon_winsys *ws = cmd_buffer->device->ws;
5502 bool predicating = cmd_buffer->state.predicating;
5503 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5504 struct radv_userdata_info *loc;
5505
5506 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
5507 AC_UD_CS_GRID_SIZE);
5508
5509 ASSERTED unsigned cdw_max = radeon_check_space(ws, cs, 25);
5510
5511 if (compute_shader->info.wave_size == 32) {
5512 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
5513 dispatch_initiator |= S_00B800_CS_W32_EN(1);
5514 }
5515
5516 if (info->indirect) {
5517 uint64_t va = radv_buffer_get_va(info->indirect->bo);
5518
5519 va += info->indirect->offset + info->indirect_offset;
5520
5521 radv_cs_add_buffer(ws, cs, info->indirect->bo);
5522
5523 if (loc->sgpr_idx != -1) {
5524 for (unsigned i = 0; i < 3; ++i) {
5525 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5526 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5527 COPY_DATA_DST_SEL(COPY_DATA_REG));
5528 radeon_emit(cs, (va + 4 * i));
5529 radeon_emit(cs, (va + 4 * i) >> 32);
5530 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
5531 + loc->sgpr_idx * 4) >> 2) + i);
5532 radeon_emit(cs, 0);
5533 }
5534 }
5535
5536 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
5537 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
5538 PKT3_SHADER_TYPE_S(1));
5539 radeon_emit(cs, va);
5540 radeon_emit(cs, va >> 32);
5541 radeon_emit(cs, dispatch_initiator);
5542 } else {
5543 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
5544 PKT3_SHADER_TYPE_S(1));
5545 radeon_emit(cs, 1);
5546 radeon_emit(cs, va);
5547 radeon_emit(cs, va >> 32);
5548
5549 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
5550 PKT3_SHADER_TYPE_S(1));
5551 radeon_emit(cs, 0);
5552 radeon_emit(cs, dispatch_initiator);
5553 }
5554 } else {
5555 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
5556 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
5557
5558 if (info->unaligned) {
5559 unsigned *cs_block_size = compute_shader->info.cs.block_size;
5560 unsigned remainder[3];
5561
5562 /* If aligned, these should be an entire block size,
5563 * not 0.
5564 */
5565 remainder[0] = blocks[0] + cs_block_size[0] -
5566 align_u32_npot(blocks[0], cs_block_size[0]);
5567 remainder[1] = blocks[1] + cs_block_size[1] -
5568 align_u32_npot(blocks[1], cs_block_size[1]);
5569 remainder[2] = blocks[2] + cs_block_size[2] -
5570 align_u32_npot(blocks[2], cs_block_size[2]);
5571
5572 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
5573 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
5574 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
5575
5576 for(unsigned i = 0; i < 3; ++i) {
5577 assert(offsets[i] % cs_block_size[i] == 0);
5578 offsets[i] /= cs_block_size[i];
5579 }
5580
5581 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
5582 radeon_emit(cs,
5583 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
5584 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
5585 radeon_emit(cs,
5586 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
5587 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
5588 radeon_emit(cs,
5589 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
5590 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
5591
5592 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
5593 }
5594
5595 if (loc->sgpr_idx != -1) {
5596 assert(loc->num_sgprs == 3);
5597
5598 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
5599 loc->sgpr_idx * 4, 3);
5600 radeon_emit(cs, blocks[0]);
5601 radeon_emit(cs, blocks[1]);
5602 radeon_emit(cs, blocks[2]);
5603 }
5604
5605 if (offsets[0] || offsets[1] || offsets[2]) {
5606 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
5607 radeon_emit(cs, offsets[0]);
5608 radeon_emit(cs, offsets[1]);
5609 radeon_emit(cs, offsets[2]);
5610
5611 /* The blocks in the packet are not counts but end values. */
5612 for (unsigned i = 0; i < 3; ++i)
5613 blocks[i] += offsets[i];
5614 } else {
5615 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
5616 }
5617
5618 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
5619 PKT3_SHADER_TYPE_S(1));
5620 radeon_emit(cs, blocks[0]);
5621 radeon_emit(cs, blocks[1]);
5622 radeon_emit(cs, blocks[2]);
5623 radeon_emit(cs, dispatch_initiator);
5624 }
5625
5626 assert(cmd_buffer->cs->cdw <= cdw_max);
5627 }
5628
5629 static void
5630 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
5631 {
5632 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
5633 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
5634 }
5635
5636 static void
5637 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
5638 const struct radv_dispatch_info *info)
5639 {
5640 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
5641 bool has_prefetch =
5642 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
5643 bool pipeline_is_dirty = pipeline &&
5644 pipeline != cmd_buffer->state.emitted_compute_pipeline;
5645
5646 radv_describe_dispatch(cmd_buffer, 8, 8, 8);
5647
5648 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5649 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5650 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
5651 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
5652 /* If we have to wait for idle, set all states first, so that
5653 * all SET packets are processed in parallel with previous draw
5654 * calls. Then upload descriptors, set shader pointers, and
5655 * dispatch, and prefetch at the end. This ensures that the
5656 * time the CUs are idle is very short. (there are only SET_SH
5657 * packets between the wait and the draw)
5658 */
5659 radv_emit_compute_pipeline(cmd_buffer);
5660 si_emit_cache_flush(cmd_buffer);
5661 /* <-- CUs are idle here --> */
5662
5663 radv_upload_compute_shader_descriptors(cmd_buffer);
5664
5665 radv_emit_dispatch_packets(cmd_buffer, info);
5666 /* <-- CUs are busy here --> */
5667
5668 /* Start prefetches after the dispatch has been started. Both
5669 * will run in parallel, but starting the dispatch first is
5670 * more important.
5671 */
5672 if (has_prefetch && pipeline_is_dirty) {
5673 radv_emit_shader_prefetch(cmd_buffer,
5674 pipeline->shaders[MESA_SHADER_COMPUTE]);
5675 }
5676 } else {
5677 /* If we don't wait for idle, start prefetches first, then set
5678 * states, and dispatch at the end.
5679 */
5680 si_emit_cache_flush(cmd_buffer);
5681
5682 if (has_prefetch && pipeline_is_dirty) {
5683 radv_emit_shader_prefetch(cmd_buffer,
5684 pipeline->shaders[MESA_SHADER_COMPUTE]);
5685 }
5686
5687 radv_upload_compute_shader_descriptors(cmd_buffer);
5688
5689 radv_emit_compute_pipeline(cmd_buffer);
5690 radv_emit_dispatch_packets(cmd_buffer, info);
5691 }
5692
5693 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
5694 }
5695
5696 void radv_CmdDispatchBase(
5697 VkCommandBuffer commandBuffer,
5698 uint32_t base_x,
5699 uint32_t base_y,
5700 uint32_t base_z,
5701 uint32_t x,
5702 uint32_t y,
5703 uint32_t z)
5704 {
5705 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5706 struct radv_dispatch_info info = {};
5707
5708 info.blocks[0] = x;
5709 info.blocks[1] = y;
5710 info.blocks[2] = z;
5711
5712 info.offsets[0] = base_x;
5713 info.offsets[1] = base_y;
5714 info.offsets[2] = base_z;
5715 radv_dispatch(cmd_buffer, &info);
5716 }
5717
5718 void radv_CmdDispatch(
5719 VkCommandBuffer commandBuffer,
5720 uint32_t x,
5721 uint32_t y,
5722 uint32_t z)
5723 {
5724 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
5725 }
5726
5727 void radv_CmdDispatchIndirect(
5728 VkCommandBuffer commandBuffer,
5729 VkBuffer _buffer,
5730 VkDeviceSize offset)
5731 {
5732 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5733 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5734 struct radv_dispatch_info info = {};
5735
5736 info.indirect = buffer;
5737 info.indirect_offset = offset;
5738
5739 radv_dispatch(cmd_buffer, &info);
5740 }
5741
5742 void radv_unaligned_dispatch(
5743 struct radv_cmd_buffer *cmd_buffer,
5744 uint32_t x,
5745 uint32_t y,
5746 uint32_t z)
5747 {
5748 struct radv_dispatch_info info = {};
5749
5750 info.blocks[0] = x;
5751 info.blocks[1] = y;
5752 info.blocks[2] = z;
5753 info.unaligned = 1;
5754
5755 radv_dispatch(cmd_buffer, &info);
5756 }
5757
5758 void
5759 radv_cmd_buffer_end_render_pass(struct radv_cmd_buffer *cmd_buffer)
5760 {
5761 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
5762 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
5763
5764 cmd_buffer->state.pass = NULL;
5765 cmd_buffer->state.subpass = NULL;
5766 cmd_buffer->state.attachments = NULL;
5767 cmd_buffer->state.framebuffer = NULL;
5768 cmd_buffer->state.subpass_sample_locs = NULL;
5769 }
5770
5771 void radv_CmdEndRenderPass(
5772 VkCommandBuffer commandBuffer)
5773 {
5774 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5775
5776 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
5777
5778 radv_cmd_buffer_end_subpass(cmd_buffer);
5779
5780 radv_cmd_buffer_end_render_pass(cmd_buffer);
5781 }
5782
5783 void radv_CmdEndRenderPass2(
5784 VkCommandBuffer commandBuffer,
5785 const VkSubpassEndInfo* pSubpassEndInfo)
5786 {
5787 radv_CmdEndRenderPass(commandBuffer);
5788 }
5789
5790 /*
5791 * For HTILE we have the following interesting clear words:
5792 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
5793 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
5794 * 0xfffffff0: Clear depth to 1.0
5795 * 0x00000000: Clear depth to 0.0
5796 */
5797 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
5798 struct radv_image *image,
5799 const VkImageSubresourceRange *range)
5800 {
5801 assert(range->baseMipLevel == 0);
5802 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
5803 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
5804 struct radv_cmd_state *state = &cmd_buffer->state;
5805 uint32_t htile_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
5806 VkClearDepthStencilValue value = {};
5807 struct radv_barrier_data barrier = {};
5808
5809 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5810 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5811
5812 barrier.layout_transitions.init_mask_ram = 1;
5813 radv_describe_layout_transition(cmd_buffer, &barrier);
5814
5815 state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, htile_value);
5816
5817 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5818
5819 if (vk_format_is_stencil(image->vk_format))
5820 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
5821
5822 radv_set_ds_clear_metadata(cmd_buffer, image, range, value, aspects);
5823
5824 if (radv_image_is_tc_compat_htile(image)) {
5825 /* Initialize the TC-compat metada value to 0 because by
5826 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
5827 * need have to conditionally update its value when performing
5828 * a fast depth clear.
5829 */
5830 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, range, 0);
5831 }
5832 }
5833
5834 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
5835 struct radv_image *image,
5836 VkImageLayout src_layout,
5837 bool src_render_loop,
5838 VkImageLayout dst_layout,
5839 bool dst_render_loop,
5840 unsigned src_queue_mask,
5841 unsigned dst_queue_mask,
5842 const VkImageSubresourceRange *range,
5843 struct radv_sample_locations_state *sample_locs)
5844 {
5845 if (!radv_image_has_htile(image))
5846 return;
5847
5848 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5849 radv_initialize_htile(cmd_buffer, image, range);
5850 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5851 radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5852 radv_initialize_htile(cmd_buffer, image, range);
5853 } else if (radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5854 !radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5855 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5856 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5857
5858 radv_decompress_depth_stencil(cmd_buffer, image, range,
5859 sample_locs);
5860
5861 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5862 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5863 }
5864 }
5865
5866 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
5867 struct radv_image *image,
5868 const VkImageSubresourceRange *range,
5869 uint32_t value)
5870 {
5871 struct radv_cmd_state *state = &cmd_buffer->state;
5872 struct radv_barrier_data barrier = {};
5873
5874 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5875 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5876
5877 barrier.layout_transitions.init_mask_ram = 1;
5878 radv_describe_layout_transition(cmd_buffer, &barrier);
5879
5880 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, range, value);
5881
5882 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5883 }
5884
5885 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
5886 struct radv_image *image,
5887 const VkImageSubresourceRange *range)
5888 {
5889 struct radv_cmd_state *state = &cmd_buffer->state;
5890 static const uint32_t fmask_clear_values[4] = {
5891 0x00000000,
5892 0x02020202,
5893 0xE4E4E4E4,
5894 0x76543210
5895 };
5896 uint32_t log2_samples = util_logbase2(image->info.samples);
5897 uint32_t value = fmask_clear_values[log2_samples];
5898 struct radv_barrier_data barrier = {};
5899
5900 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5901 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5902
5903 barrier.layout_transitions.init_mask_ram = 1;
5904 radv_describe_layout_transition(cmd_buffer, &barrier);
5905
5906 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, range, value);
5907
5908 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5909 }
5910
5911 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
5912 struct radv_image *image,
5913 const VkImageSubresourceRange *range, uint32_t value)
5914 {
5915 struct radv_cmd_state *state = &cmd_buffer->state;
5916 struct radv_barrier_data barrier = {};
5917 unsigned size = 0;
5918
5919 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5920 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5921
5922 barrier.layout_transitions.init_mask_ram = 1;
5923 radv_describe_layout_transition(cmd_buffer, &barrier);
5924
5925 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
5926
5927 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) {
5928 /* When DCC is enabled with mipmaps, some levels might not
5929 * support fast clears and we have to initialize them as "fully
5930 * expanded".
5931 */
5932 /* Compute the size of all fast clearable DCC levels. */
5933 for (unsigned i = 0; i < image->planes[0].surface.num_dcc_levels; i++) {
5934 struct legacy_surf_level *surf_level =
5935 &image->planes[0].surface.u.legacy.level[i];
5936 unsigned dcc_fast_clear_size =
5937 surf_level->dcc_slice_fast_clear_size * image->info.array_size;
5938
5939 if (!dcc_fast_clear_size)
5940 break;
5941
5942 size = surf_level->dcc_offset + dcc_fast_clear_size;
5943 }
5944
5945 /* Initialize the mipmap levels without DCC. */
5946 if (size != image->planes[0].surface.dcc_size) {
5947 state->flush_bits |=
5948 radv_fill_buffer(cmd_buffer, image->bo,
5949 image->offset + image->planes[0].surface.dcc_offset + size,
5950 image->planes[0].surface.dcc_size - size,
5951 0xffffffff);
5952 }
5953 }
5954
5955 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5956 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5957 }
5958
5959 /**
5960 * Initialize DCC/FMASK/CMASK metadata for a color image.
5961 */
5962 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
5963 struct radv_image *image,
5964 VkImageLayout src_layout,
5965 bool src_render_loop,
5966 VkImageLayout dst_layout,
5967 bool dst_render_loop,
5968 unsigned src_queue_mask,
5969 unsigned dst_queue_mask,
5970 const VkImageSubresourceRange *range)
5971 {
5972 if (radv_image_has_cmask(image)) {
5973 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5974
5975 /* TODO: clarify this. */
5976 if (radv_image_has_fmask(image)) {
5977 value = 0xccccccccu;
5978 }
5979
5980 radv_initialise_cmask(cmd_buffer, image, range, value);
5981 }
5982
5983 if (radv_image_has_fmask(image)) {
5984 radv_initialize_fmask(cmd_buffer, image, range);
5985 }
5986
5987 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5988 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5989 bool need_decompress_pass = false;
5990
5991 if (radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout,
5992 dst_render_loop,
5993 dst_queue_mask)) {
5994 value = 0x20202020u;
5995 need_decompress_pass = true;
5996 }
5997
5998 radv_initialize_dcc(cmd_buffer, image, range, value);
5999
6000 radv_update_fce_metadata(cmd_buffer, image, range,
6001 need_decompress_pass);
6002 }
6003
6004 if (radv_image_has_cmask(image) ||
6005 radv_dcc_enabled(image, range->baseMipLevel)) {
6006 uint32_t color_values[2] = {};
6007 radv_set_color_clear_metadata(cmd_buffer, image, range,
6008 color_values);
6009 }
6010 }
6011
6012 /**
6013 * Handle color image transitions for DCC/FMASK/CMASK.
6014 */
6015 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
6016 struct radv_image *image,
6017 VkImageLayout src_layout,
6018 bool src_render_loop,
6019 VkImageLayout dst_layout,
6020 bool dst_render_loop,
6021 unsigned src_queue_mask,
6022 unsigned dst_queue_mask,
6023 const VkImageSubresourceRange *range)
6024 {
6025 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
6026 radv_init_color_image_metadata(cmd_buffer, image,
6027 src_layout, src_render_loop,
6028 dst_layout, dst_render_loop,
6029 src_queue_mask, dst_queue_mask,
6030 range);
6031 return;
6032 }
6033
6034 if (radv_dcc_enabled(image, range->baseMipLevel)) {
6035 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
6036 radv_initialize_dcc(cmd_buffer, image, range, 0xffffffffu);
6037 } else if (radv_layout_dcc_compressed(cmd_buffer->device, image, src_layout, src_render_loop, src_queue_mask) &&
6038 !radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout, dst_render_loop, dst_queue_mask)) {
6039 radv_decompress_dcc(cmd_buffer, image, range);
6040 } else if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
6041 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
6042 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
6043 }
6044 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
6045 bool fce_eliminate = false, fmask_expand = false;
6046
6047 if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
6048 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
6049 fce_eliminate = true;
6050 }
6051
6052 if (radv_image_has_fmask(image)) {
6053 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
6054 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
6055 /* A FMASK decompress is required before doing
6056 * a MSAA decompress using FMASK.
6057 */
6058 fmask_expand = true;
6059 }
6060 }
6061
6062 if (fce_eliminate || fmask_expand)
6063 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
6064
6065 if (fmask_expand) {
6066 struct radv_barrier_data barrier = {};
6067 barrier.layout_transitions.fmask_color_expand = 1;
6068 radv_describe_layout_transition(cmd_buffer, &barrier);
6069
6070 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
6071 }
6072 }
6073 }
6074
6075 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
6076 struct radv_image *image,
6077 VkImageLayout src_layout,
6078 bool src_render_loop,
6079 VkImageLayout dst_layout,
6080 bool dst_render_loop,
6081 uint32_t src_family,
6082 uint32_t dst_family,
6083 const VkImageSubresourceRange *range,
6084 struct radv_sample_locations_state *sample_locs)
6085 {
6086 if (image->exclusive && src_family != dst_family) {
6087 /* This is an acquire or a release operation and there will be
6088 * a corresponding release/acquire. Do the transition in the
6089 * most flexible queue. */
6090
6091 assert(src_family == cmd_buffer->queue_family_index ||
6092 dst_family == cmd_buffer->queue_family_index);
6093
6094 if (src_family == VK_QUEUE_FAMILY_EXTERNAL ||
6095 src_family == VK_QUEUE_FAMILY_FOREIGN_EXT)
6096 return;
6097
6098 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
6099 return;
6100
6101 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
6102 (src_family == RADV_QUEUE_GENERAL ||
6103 dst_family == RADV_QUEUE_GENERAL))
6104 return;
6105 }
6106
6107 if (src_layout == dst_layout)
6108 return;
6109
6110 unsigned src_queue_mask =
6111 radv_image_queue_family_mask(image, src_family,
6112 cmd_buffer->queue_family_index);
6113 unsigned dst_queue_mask =
6114 radv_image_queue_family_mask(image, dst_family,
6115 cmd_buffer->queue_family_index);
6116
6117 if (vk_format_is_depth(image->vk_format)) {
6118 radv_handle_depth_image_transition(cmd_buffer, image,
6119 src_layout, src_render_loop,
6120 dst_layout, dst_render_loop,
6121 src_queue_mask, dst_queue_mask,
6122 range, sample_locs);
6123 } else {
6124 radv_handle_color_image_transition(cmd_buffer, image,
6125 src_layout, src_render_loop,
6126 dst_layout, dst_render_loop,
6127 src_queue_mask, dst_queue_mask,
6128 range);
6129 }
6130 }
6131
6132 struct radv_barrier_info {
6133 enum rgp_barrier_reason reason;
6134 uint32_t eventCount;
6135 const VkEvent *pEvents;
6136 VkPipelineStageFlags srcStageMask;
6137 VkPipelineStageFlags dstStageMask;
6138 };
6139
6140 static void
6141 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
6142 uint32_t memoryBarrierCount,
6143 const VkMemoryBarrier *pMemoryBarriers,
6144 uint32_t bufferMemoryBarrierCount,
6145 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
6146 uint32_t imageMemoryBarrierCount,
6147 const VkImageMemoryBarrier *pImageMemoryBarriers,
6148 const struct radv_barrier_info *info)
6149 {
6150 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6151 enum radv_cmd_flush_bits src_flush_bits = 0;
6152 enum radv_cmd_flush_bits dst_flush_bits = 0;
6153
6154 radv_describe_barrier_start(cmd_buffer, info->reason);
6155
6156 for (unsigned i = 0; i < info->eventCount; ++i) {
6157 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
6158 uint64_t va = radv_buffer_get_va(event->bo);
6159
6160 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
6161
6162 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
6163
6164 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
6165 assert(cmd_buffer->cs->cdw <= cdw_max);
6166 }
6167
6168 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
6169 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
6170 NULL);
6171 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
6172 NULL);
6173 }
6174
6175 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
6176 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
6177 NULL);
6178 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
6179 NULL);
6180 }
6181
6182 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
6183 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
6184
6185 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
6186 image);
6187 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
6188 image);
6189 }
6190
6191 /* The Vulkan spec 1.1.98 says:
6192 *
6193 * "An execution dependency with only
6194 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
6195 * will only prevent that stage from executing in subsequently
6196 * submitted commands. As this stage does not perform any actual
6197 * execution, this is not observable - in effect, it does not delay
6198 * processing of subsequent commands. Similarly an execution dependency
6199 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
6200 * will effectively not wait for any prior commands to complete."
6201 */
6202 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
6203 radv_stage_flush(cmd_buffer, info->srcStageMask);
6204 cmd_buffer->state.flush_bits |= src_flush_bits;
6205
6206 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
6207 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
6208
6209 const struct VkSampleLocationsInfoEXT *sample_locs_info =
6210 vk_find_struct_const(pImageMemoryBarriers[i].pNext,
6211 SAMPLE_LOCATIONS_INFO_EXT);
6212 struct radv_sample_locations_state sample_locations = {};
6213
6214 if (sample_locs_info) {
6215 assert(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
6216 sample_locations.per_pixel = sample_locs_info->sampleLocationsPerPixel;
6217 sample_locations.grid_size = sample_locs_info->sampleLocationGridSize;
6218 sample_locations.count = sample_locs_info->sampleLocationsCount;
6219 typed_memcpy(&sample_locations.locations[0],
6220 sample_locs_info->pSampleLocations,
6221 sample_locs_info->sampleLocationsCount);
6222 }
6223
6224 radv_handle_image_transition(cmd_buffer, image,
6225 pImageMemoryBarriers[i].oldLayout,
6226 false, /* Outside of a renderpass we are never in a renderloop */
6227 pImageMemoryBarriers[i].newLayout,
6228 false, /* Outside of a renderpass we are never in a renderloop */
6229 pImageMemoryBarriers[i].srcQueueFamilyIndex,
6230 pImageMemoryBarriers[i].dstQueueFamilyIndex,
6231 &pImageMemoryBarriers[i].subresourceRange,
6232 sample_locs_info ? &sample_locations : NULL);
6233 }
6234
6235 /* Make sure CP DMA is idle because the driver might have performed a
6236 * DMA operation for copying or filling buffers/images.
6237 */
6238 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
6239 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
6240 si_cp_dma_wait_for_idle(cmd_buffer);
6241
6242 cmd_buffer->state.flush_bits |= dst_flush_bits;
6243
6244 radv_describe_barrier_end(cmd_buffer);
6245 }
6246
6247 void radv_CmdPipelineBarrier(
6248 VkCommandBuffer commandBuffer,
6249 VkPipelineStageFlags srcStageMask,
6250 VkPipelineStageFlags destStageMask,
6251 VkBool32 byRegion,
6252 uint32_t memoryBarrierCount,
6253 const VkMemoryBarrier* pMemoryBarriers,
6254 uint32_t bufferMemoryBarrierCount,
6255 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
6256 uint32_t imageMemoryBarrierCount,
6257 const VkImageMemoryBarrier* pImageMemoryBarriers)
6258 {
6259 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6260 struct radv_barrier_info info;
6261
6262 info.reason = RGP_BARRIER_EXTERNAL_CMD_PIPELINE_BARRIER;
6263 info.eventCount = 0;
6264 info.pEvents = NULL;
6265 info.srcStageMask = srcStageMask;
6266 info.dstStageMask = destStageMask;
6267
6268 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
6269 bufferMemoryBarrierCount, pBufferMemoryBarriers,
6270 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
6271 }
6272
6273
6274 static void write_event(struct radv_cmd_buffer *cmd_buffer,
6275 struct radv_event *event,
6276 VkPipelineStageFlags stageMask,
6277 unsigned value)
6278 {
6279 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6280 uint64_t va = radv_buffer_get_va(event->bo);
6281
6282 si_emit_cache_flush(cmd_buffer);
6283
6284 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
6285
6286 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 21);
6287
6288 /* Flags that only require a top-of-pipe event. */
6289 VkPipelineStageFlags top_of_pipe_flags =
6290 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
6291
6292 /* Flags that only require a post-index-fetch event. */
6293 VkPipelineStageFlags post_index_fetch_flags =
6294 top_of_pipe_flags |
6295 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
6296 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
6297
6298 /* Make sure CP DMA is idle because the driver might have performed a
6299 * DMA operation for copying or filling buffers/images.
6300 */
6301 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
6302 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
6303 si_cp_dma_wait_for_idle(cmd_buffer);
6304
6305 /* TODO: Emit EOS events for syncing PS/CS stages. */
6306
6307 if (!(stageMask & ~top_of_pipe_flags)) {
6308 /* Just need to sync the PFP engine. */
6309 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
6310 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
6311 S_370_WR_CONFIRM(1) |
6312 S_370_ENGINE_SEL(V_370_PFP));
6313 radeon_emit(cs, va);
6314 radeon_emit(cs, va >> 32);
6315 radeon_emit(cs, value);
6316 } else if (!(stageMask & ~post_index_fetch_flags)) {
6317 /* Sync ME because PFP reads index and indirect buffers. */
6318 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
6319 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
6320 S_370_WR_CONFIRM(1) |
6321 S_370_ENGINE_SEL(V_370_ME));
6322 radeon_emit(cs, va);
6323 radeon_emit(cs, va >> 32);
6324 radeon_emit(cs, value);
6325 } else {
6326 /* Otherwise, sync all prior GPU work using an EOP event. */
6327 si_cs_emit_write_event_eop(cs,
6328 cmd_buffer->device->physical_device->rad_info.chip_class,
6329 radv_cmd_buffer_uses_mec(cmd_buffer),
6330 V_028A90_BOTTOM_OF_PIPE_TS, 0,
6331 EOP_DST_SEL_MEM,
6332 EOP_DATA_SEL_VALUE_32BIT, va, value,
6333 cmd_buffer->gfx9_eop_bug_va);
6334 }
6335
6336 assert(cmd_buffer->cs->cdw <= cdw_max);
6337 }
6338
6339 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
6340 VkEvent _event,
6341 VkPipelineStageFlags stageMask)
6342 {
6343 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6344 RADV_FROM_HANDLE(radv_event, event, _event);
6345
6346 write_event(cmd_buffer, event, stageMask, 1);
6347 }
6348
6349 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
6350 VkEvent _event,
6351 VkPipelineStageFlags stageMask)
6352 {
6353 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6354 RADV_FROM_HANDLE(radv_event, event, _event);
6355
6356 write_event(cmd_buffer, event, stageMask, 0);
6357 }
6358
6359 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
6360 uint32_t eventCount,
6361 const VkEvent* pEvents,
6362 VkPipelineStageFlags srcStageMask,
6363 VkPipelineStageFlags dstStageMask,
6364 uint32_t memoryBarrierCount,
6365 const VkMemoryBarrier* pMemoryBarriers,
6366 uint32_t bufferMemoryBarrierCount,
6367 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
6368 uint32_t imageMemoryBarrierCount,
6369 const VkImageMemoryBarrier* pImageMemoryBarriers)
6370 {
6371 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6372 struct radv_barrier_info info;
6373
6374 info.reason = RGP_BARRIER_EXTERNAL_CMD_WAIT_EVENTS;
6375 info.eventCount = eventCount;
6376 info.pEvents = pEvents;
6377 info.srcStageMask = 0;
6378
6379 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
6380 bufferMemoryBarrierCount, pBufferMemoryBarriers,
6381 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
6382 }
6383
6384
6385 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
6386 uint32_t deviceMask)
6387 {
6388 /* No-op */
6389 }
6390
6391 /* VK_EXT_conditional_rendering */
6392 void radv_CmdBeginConditionalRenderingEXT(
6393 VkCommandBuffer commandBuffer,
6394 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
6395 {
6396 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6397 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
6398 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6399 bool draw_visible = true;
6400 uint64_t pred_value = 0;
6401 uint64_t va, new_va;
6402 unsigned pred_offset;
6403
6404 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
6405
6406 /* By default, if the 32-bit value at offset in buffer memory is zero,
6407 * then the rendering commands are discarded, otherwise they are
6408 * executed as normal. If the inverted flag is set, all commands are
6409 * discarded if the value is non zero.
6410 */
6411 if (pConditionalRenderingBegin->flags &
6412 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
6413 draw_visible = false;
6414 }
6415
6416 si_emit_cache_flush(cmd_buffer);
6417
6418 /* From the Vulkan spec 1.1.107:
6419 *
6420 * "If the 32-bit value at offset in buffer memory is zero, then the
6421 * rendering commands are discarded, otherwise they are executed as
6422 * normal. If the value of the predicate in buffer memory changes while
6423 * conditional rendering is active, the rendering commands may be
6424 * discarded in an implementation-dependent way. Some implementations
6425 * may latch the value of the predicate upon beginning conditional
6426 * rendering while others may read it before every rendering command."
6427 *
6428 * But, the AMD hardware treats the predicate as a 64-bit value which
6429 * means we need a workaround in the driver. Luckily, it's not required
6430 * to support if the value changes when predication is active.
6431 *
6432 * The workaround is as follows:
6433 * 1) allocate a 64-value in the upload BO and initialize it to 0
6434 * 2) copy the 32-bit predicate value to the upload BO
6435 * 3) use the new allocated VA address for predication
6436 *
6437 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
6438 * in ME (+ sync PFP) instead of PFP.
6439 */
6440 radv_cmd_buffer_upload_data(cmd_buffer, 8, 16, &pred_value, &pred_offset);
6441
6442 new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
6443
6444 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
6445 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
6446 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
6447 COPY_DATA_WR_CONFIRM);
6448 radeon_emit(cs, va);
6449 radeon_emit(cs, va >> 32);
6450 radeon_emit(cs, new_va);
6451 radeon_emit(cs, new_va >> 32);
6452
6453 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
6454 radeon_emit(cs, 0);
6455
6456 /* Enable predication for this command buffer. */
6457 si_emit_set_predication_state(cmd_buffer, draw_visible, new_va);
6458 cmd_buffer->state.predicating = true;
6459
6460 /* Store conditional rendering user info. */
6461 cmd_buffer->state.predication_type = draw_visible;
6462 cmd_buffer->state.predication_va = new_va;
6463 }
6464
6465 void radv_CmdEndConditionalRenderingEXT(
6466 VkCommandBuffer commandBuffer)
6467 {
6468 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6469
6470 /* Disable predication for this command buffer. */
6471 si_emit_set_predication_state(cmd_buffer, false, 0);
6472 cmd_buffer->state.predicating = false;
6473
6474 /* Reset conditional rendering user info. */
6475 cmd_buffer->state.predication_type = -1;
6476 cmd_buffer->state.predication_va = 0;
6477 }
6478
6479 /* VK_EXT_transform_feedback */
6480 void radv_CmdBindTransformFeedbackBuffersEXT(
6481 VkCommandBuffer commandBuffer,
6482 uint32_t firstBinding,
6483 uint32_t bindingCount,
6484 const VkBuffer* pBuffers,
6485 const VkDeviceSize* pOffsets,
6486 const VkDeviceSize* pSizes)
6487 {
6488 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6489 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
6490 uint8_t enabled_mask = 0;
6491
6492 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
6493 for (uint32_t i = 0; i < bindingCount; i++) {
6494 uint32_t idx = firstBinding + i;
6495
6496 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
6497 sb[idx].offset = pOffsets[i];
6498
6499 if (!pSizes || pSizes[i] == VK_WHOLE_SIZE) {
6500 sb[idx].size = sb[idx].buffer->size - sb[idx].offset;
6501 } else {
6502 sb[idx].size = pSizes[i];
6503 }
6504
6505 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
6506 sb[idx].buffer->bo);
6507
6508 enabled_mask |= 1 << idx;
6509 }
6510
6511 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
6512
6513 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
6514 }
6515
6516 static void
6517 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
6518 {
6519 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6520 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6521
6522 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
6523 radeon_emit(cs,
6524 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
6525 S_028B94_RAST_STREAM(0) |
6526 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
6527 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
6528 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
6529 radeon_emit(cs, so->hw_enabled_mask &
6530 so->enabled_stream_buffers_mask);
6531
6532 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6533 }
6534
6535 static void
6536 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
6537 {
6538 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6539 bool old_streamout_enabled = so->streamout_enabled;
6540 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
6541
6542 so->streamout_enabled = enable;
6543
6544 so->hw_enabled_mask = so->enabled_mask |
6545 (so->enabled_mask << 4) |
6546 (so->enabled_mask << 8) |
6547 (so->enabled_mask << 12);
6548
6549 if (!cmd_buffer->device->physical_device->use_ngg_streamout &&
6550 ((old_streamout_enabled != so->streamout_enabled) ||
6551 (old_hw_enabled_mask != so->hw_enabled_mask)))
6552 radv_emit_streamout_enable(cmd_buffer);
6553
6554 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6555 cmd_buffer->gds_needed = true;
6556 cmd_buffer->gds_oa_needed = true;
6557 }
6558 }
6559
6560 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
6561 {
6562 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6563 unsigned reg_strmout_cntl;
6564
6565 /* The register is at different places on different ASICs. */
6566 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
6567 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
6568 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
6569 } else {
6570 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
6571 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
6572 }
6573
6574 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
6575 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
6576
6577 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
6578 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
6579 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
6580 radeon_emit(cs, 0);
6581 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
6582 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
6583 radeon_emit(cs, 4); /* poll interval */
6584 }
6585
6586 static void
6587 radv_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
6588 uint32_t firstCounterBuffer,
6589 uint32_t counterBufferCount,
6590 const VkBuffer *pCounterBuffers,
6591 const VkDeviceSize *pCounterBufferOffsets)
6592
6593 {
6594 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
6595 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6596 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6597 uint32_t i;
6598
6599 radv_flush_vgt_streamout(cmd_buffer);
6600
6601 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6602 for_each_bit(i, so->enabled_mask) {
6603 int32_t counter_buffer_idx = i - firstCounterBuffer;
6604 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6605 counter_buffer_idx = -1;
6606
6607 /* AMD GCN binds streamout buffers as shader resources.
6608 * VGT only counts primitives and tells the shader through
6609 * SGPRs what to do.
6610 */
6611 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
6612 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
6613 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
6614
6615 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6616
6617 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6618 /* The array of counter buffers is optional. */
6619 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6620 uint64_t va = radv_buffer_get_va(buffer->bo);
6621
6622 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6623
6624 /* Append */
6625 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6626 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6627 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6628 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
6629 radeon_emit(cs, 0); /* unused */
6630 radeon_emit(cs, 0); /* unused */
6631 radeon_emit(cs, va); /* src address lo */
6632 radeon_emit(cs, va >> 32); /* src address hi */
6633
6634 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6635 } else {
6636 /* Start from the beginning. */
6637 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6638 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6639 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6640 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
6641 radeon_emit(cs, 0); /* unused */
6642 radeon_emit(cs, 0); /* unused */
6643 radeon_emit(cs, 0); /* unused */
6644 radeon_emit(cs, 0); /* unused */
6645 }
6646 }
6647
6648 radv_set_streamout_enable(cmd_buffer, true);
6649 }
6650
6651 static void
6652 gfx10_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
6653 uint32_t firstCounterBuffer,
6654 uint32_t counterBufferCount,
6655 const VkBuffer *pCounterBuffers,
6656 const VkDeviceSize *pCounterBufferOffsets)
6657 {
6658 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6659 unsigned last_target = util_last_bit(so->enabled_mask) - 1;
6660 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6661 uint32_t i;
6662
6663 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6664 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6665
6666 /* Sync because the next streamout operation will overwrite GDS and we
6667 * have to make sure it's idle.
6668 * TODO: Improve by tracking if there is a streamout operation in
6669 * flight.
6670 */
6671 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
6672 si_emit_cache_flush(cmd_buffer);
6673
6674 for_each_bit(i, so->enabled_mask) {
6675 int32_t counter_buffer_idx = i - firstCounterBuffer;
6676 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6677 counter_buffer_idx = -1;
6678
6679 bool append = counter_buffer_idx >= 0 &&
6680 pCounterBuffers && pCounterBuffers[counter_buffer_idx];
6681 uint64_t va = 0;
6682
6683 if (append) {
6684 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6685
6686 va += radv_buffer_get_va(buffer->bo);
6687 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6688
6689 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6690 }
6691
6692 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
6693 radeon_emit(cs, S_411_SRC_SEL(append ? V_411_SRC_ADDR_TC_L2 : V_411_DATA) |
6694 S_411_DST_SEL(V_411_GDS) |
6695 S_411_CP_SYNC(i == last_target));
6696 radeon_emit(cs, va);
6697 radeon_emit(cs, va >> 32);
6698 radeon_emit(cs, 4 * i); /* destination in GDS */
6699 radeon_emit(cs, 0);
6700 radeon_emit(cs, S_414_BYTE_COUNT_GFX9(4) |
6701 S_414_DISABLE_WR_CONFIRM_GFX9(i != last_target));
6702 }
6703
6704 radv_set_streamout_enable(cmd_buffer, true);
6705 }
6706
6707 void radv_CmdBeginTransformFeedbackEXT(
6708 VkCommandBuffer commandBuffer,
6709 uint32_t firstCounterBuffer,
6710 uint32_t counterBufferCount,
6711 const VkBuffer* pCounterBuffers,
6712 const VkDeviceSize* pCounterBufferOffsets)
6713 {
6714 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6715
6716 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6717 gfx10_emit_streamout_begin(cmd_buffer,
6718 firstCounterBuffer, counterBufferCount,
6719 pCounterBuffers, pCounterBufferOffsets);
6720 } else {
6721 radv_emit_streamout_begin(cmd_buffer,
6722 firstCounterBuffer, counterBufferCount,
6723 pCounterBuffers, pCounterBufferOffsets);
6724 }
6725 }
6726
6727 static void
6728 radv_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6729 uint32_t firstCounterBuffer,
6730 uint32_t counterBufferCount,
6731 const VkBuffer *pCounterBuffers,
6732 const VkDeviceSize *pCounterBufferOffsets)
6733 {
6734 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6735 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6736 uint32_t i;
6737
6738 radv_flush_vgt_streamout(cmd_buffer);
6739
6740 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6741 for_each_bit(i, so->enabled_mask) {
6742 int32_t counter_buffer_idx = i - firstCounterBuffer;
6743 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6744 counter_buffer_idx = -1;
6745
6746 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6747 /* The array of counters buffer is optional. */
6748 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6749 uint64_t va = radv_buffer_get_va(buffer->bo);
6750
6751 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6752
6753 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6754 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6755 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6756 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
6757 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
6758 radeon_emit(cs, va); /* dst address lo */
6759 radeon_emit(cs, va >> 32); /* dst address hi */
6760 radeon_emit(cs, 0); /* unused */
6761 radeon_emit(cs, 0); /* unused */
6762
6763 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6764 }
6765
6766 /* Deactivate transform feedback by zeroing the buffer size.
6767 * The counters (primitives generated, primitives emitted) may
6768 * be enabled even if there is not buffer bound. This ensures
6769 * that the primitives-emitted query won't increment.
6770 */
6771 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
6772
6773 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6774 }
6775
6776 radv_set_streamout_enable(cmd_buffer, false);
6777 }
6778
6779 static void
6780 gfx10_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6781 uint32_t firstCounterBuffer,
6782 uint32_t counterBufferCount,
6783 const VkBuffer *pCounterBuffers,
6784 const VkDeviceSize *pCounterBufferOffsets)
6785 {
6786 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6787 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6788 uint32_t i;
6789
6790 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6791 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6792
6793 for_each_bit(i, so->enabled_mask) {
6794 int32_t counter_buffer_idx = i - firstCounterBuffer;
6795 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6796 counter_buffer_idx = -1;
6797
6798 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6799 /* The array of counters buffer is optional. */
6800 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6801 uint64_t va = radv_buffer_get_va(buffer->bo);
6802
6803 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6804
6805 si_cs_emit_write_event_eop(cs,
6806 cmd_buffer->device->physical_device->rad_info.chip_class,
6807 radv_cmd_buffer_uses_mec(cmd_buffer),
6808 V_028A90_PS_DONE, 0,
6809 EOP_DST_SEL_TC_L2,
6810 EOP_DATA_SEL_GDS,
6811 va, EOP_DATA_GDS(i, 1), 0);
6812
6813 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6814 }
6815 }
6816
6817 radv_set_streamout_enable(cmd_buffer, false);
6818 }
6819
6820 void radv_CmdEndTransformFeedbackEXT(
6821 VkCommandBuffer commandBuffer,
6822 uint32_t firstCounterBuffer,
6823 uint32_t counterBufferCount,
6824 const VkBuffer* pCounterBuffers,
6825 const VkDeviceSize* pCounterBufferOffsets)
6826 {
6827 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6828
6829 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6830 gfx10_emit_streamout_end(cmd_buffer,
6831 firstCounterBuffer, counterBufferCount,
6832 pCounterBuffers, pCounterBufferOffsets);
6833 } else {
6834 radv_emit_streamout_end(cmd_buffer,
6835 firstCounterBuffer, counterBufferCount,
6836 pCounterBuffers, pCounterBufferOffsets);
6837 }
6838 }
6839
6840 void radv_CmdDrawIndirectByteCountEXT(
6841 VkCommandBuffer commandBuffer,
6842 uint32_t instanceCount,
6843 uint32_t firstInstance,
6844 VkBuffer _counterBuffer,
6845 VkDeviceSize counterBufferOffset,
6846 uint32_t counterOffset,
6847 uint32_t vertexStride)
6848 {
6849 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6850 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
6851 struct radv_draw_info info = {};
6852
6853 info.instance_count = instanceCount;
6854 info.first_instance = firstInstance;
6855 info.strmout_buffer = counterBuffer;
6856 info.strmout_buffer_offset = counterBufferOffset;
6857 info.stride = vertexStride;
6858
6859 radv_draw(cmd_buffer, &info);
6860 }
6861
6862 /* VK_AMD_buffer_marker */
6863 void radv_CmdWriteBufferMarkerAMD(
6864 VkCommandBuffer commandBuffer,
6865 VkPipelineStageFlagBits pipelineStage,
6866 VkBuffer dstBuffer,
6867 VkDeviceSize dstOffset,
6868 uint32_t marker)
6869 {
6870 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6871 RADV_FROM_HANDLE(radv_buffer, buffer, dstBuffer);
6872 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6873 uint64_t va = radv_buffer_get_va(buffer->bo) + dstOffset;
6874
6875 si_emit_cache_flush(cmd_buffer);
6876
6877 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 12);
6878
6879 if (!(pipelineStage & ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT)) {
6880 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
6881 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
6882 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
6883 COPY_DATA_WR_CONFIRM);
6884 radeon_emit(cs, marker);
6885 radeon_emit(cs, 0);
6886 radeon_emit(cs, va);
6887 radeon_emit(cs, va >> 32);
6888 } else {
6889 si_cs_emit_write_event_eop(cs,
6890 cmd_buffer->device->physical_device->rad_info.chip_class,
6891 radv_cmd_buffer_uses_mec(cmd_buffer),
6892 V_028A90_BOTTOM_OF_PIPE_TS, 0,
6893 EOP_DST_SEL_MEM,
6894 EOP_DATA_SEL_VALUE_32BIT,
6895 va, marker,
6896 cmd_buffer->gfx9_eop_bug_va);
6897 }
6898
6899 assert(cmd_buffer->cs->cdw <= cdw_max);
6900 }