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radv: add support for dynamic cull mode and front face
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 bool src_render_loop,
58 VkImageLayout dst_layout,
59 bool dst_render_loop,
60 uint32_t src_family,
61 uint32_t dst_family,
62 const VkImageSubresourceRange *range,
63 struct radv_sample_locations_state *sample_locs);
64
65 const struct radv_dynamic_state default_dynamic_state = {
66 .viewport = {
67 .count = 0,
68 },
69 .scissor = {
70 .count = 0,
71 },
72 .line_width = 1.0f,
73 .depth_bias = {
74 .bias = 0.0f,
75 .clamp = 0.0f,
76 .slope = 0.0f,
77 },
78 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
79 .depth_bounds = {
80 .min = 0.0f,
81 .max = 1.0f,
82 },
83 .stencil_compare_mask = {
84 .front = ~0u,
85 .back = ~0u,
86 },
87 .stencil_write_mask = {
88 .front = ~0u,
89 .back = ~0u,
90 },
91 .stencil_reference = {
92 .front = 0u,
93 .back = 0u,
94 },
95 .line_stipple = {
96 .factor = 0u,
97 .pattern = 0u,
98 },
99 .cull_mode = 0u,
100 .front_face = 0u,
101 };
102
103 static void
104 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
105 const struct radv_dynamic_state *src)
106 {
107 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
108 uint32_t copy_mask = src->mask;
109 uint32_t dest_mask = 0;
110
111 dest->discard_rectangle.count = src->discard_rectangle.count;
112 dest->sample_location.count = src->sample_location.count;
113
114 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
115 dest->viewport.count = src->viewport.count;
116 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
117 src->viewport.count * sizeof(VkViewport))) {
118 typed_memcpy(dest->viewport.viewports,
119 src->viewport.viewports,
120 src->viewport.count);
121 dest_mask |= RADV_DYNAMIC_VIEWPORT;
122 }
123 }
124
125 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
126 dest->scissor.count = src->scissor.count;
127 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
128 src->scissor.count * sizeof(VkRect2D))) {
129 typed_memcpy(dest->scissor.scissors,
130 src->scissor.scissors, src->scissor.count);
131 dest_mask |= RADV_DYNAMIC_SCISSOR;
132 }
133 }
134
135 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
136 if (dest->line_width != src->line_width) {
137 dest->line_width = src->line_width;
138 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
139 }
140 }
141
142 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
143 if (memcmp(&dest->depth_bias, &src->depth_bias,
144 sizeof(src->depth_bias))) {
145 dest->depth_bias = src->depth_bias;
146 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
147 }
148 }
149
150 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
151 if (memcmp(&dest->blend_constants, &src->blend_constants,
152 sizeof(src->blend_constants))) {
153 typed_memcpy(dest->blend_constants,
154 src->blend_constants, 4);
155 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
156 }
157 }
158
159 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
160 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
161 sizeof(src->depth_bounds))) {
162 dest->depth_bounds = src->depth_bounds;
163 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
164 }
165 }
166
167 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
168 if (memcmp(&dest->stencil_compare_mask,
169 &src->stencil_compare_mask,
170 sizeof(src->stencil_compare_mask))) {
171 dest->stencil_compare_mask = src->stencil_compare_mask;
172 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
173 }
174 }
175
176 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
177 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
178 sizeof(src->stencil_write_mask))) {
179 dest->stencil_write_mask = src->stencil_write_mask;
180 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
181 }
182 }
183
184 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
185 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
186 sizeof(src->stencil_reference))) {
187 dest->stencil_reference = src->stencil_reference;
188 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
189 }
190 }
191
192 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
193 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
194 src->discard_rectangle.count * sizeof(VkRect2D))) {
195 typed_memcpy(dest->discard_rectangle.rectangles,
196 src->discard_rectangle.rectangles,
197 src->discard_rectangle.count);
198 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
199 }
200 }
201
202 if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
203 if (dest->sample_location.per_pixel != src->sample_location.per_pixel ||
204 dest->sample_location.grid_size.width != src->sample_location.grid_size.width ||
205 dest->sample_location.grid_size.height != src->sample_location.grid_size.height ||
206 memcmp(&dest->sample_location.locations,
207 &src->sample_location.locations,
208 src->sample_location.count * sizeof(VkSampleLocationEXT))) {
209 dest->sample_location.per_pixel = src->sample_location.per_pixel;
210 dest->sample_location.grid_size = src->sample_location.grid_size;
211 typed_memcpy(dest->sample_location.locations,
212 src->sample_location.locations,
213 src->sample_location.count);
214 dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
215 }
216 }
217
218 if (copy_mask & RADV_DYNAMIC_LINE_STIPPLE) {
219 if (memcmp(&dest->line_stipple, &src->line_stipple,
220 sizeof(src->line_stipple))) {
221 dest->line_stipple = src->line_stipple;
222 dest_mask |= RADV_DYNAMIC_LINE_STIPPLE;
223 }
224 }
225
226 if (copy_mask & RADV_DYNAMIC_CULL_MODE) {
227 if (dest->cull_mode != src->cull_mode) {
228 dest->cull_mode = src->cull_mode;
229 dest_mask |= RADV_DYNAMIC_CULL_MODE;
230 }
231 }
232
233 if (copy_mask & RADV_DYNAMIC_FRONT_FACE) {
234 if (dest->front_face != src->front_face) {
235 dest->front_face = src->front_face;
236 dest_mask |= RADV_DYNAMIC_FRONT_FACE;
237 }
238 }
239
240 cmd_buffer->state.dirty |= dest_mask;
241 }
242
243 static void
244 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
245 struct radv_pipeline *pipeline)
246 {
247 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
248 struct radv_shader_info *info;
249
250 if (!pipeline->streamout_shader ||
251 cmd_buffer->device->physical_device->use_ngg_streamout)
252 return;
253
254 info = &pipeline->streamout_shader->info;
255 for (int i = 0; i < MAX_SO_BUFFERS; i++)
256 so->stride_in_dw[i] = info->so.strides[i];
257
258 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
259 }
260
261 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
262 {
263 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
264 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
265 }
266
267 enum ring_type radv_queue_family_to_ring(int f) {
268 switch (f) {
269 case RADV_QUEUE_GENERAL:
270 return RING_GFX;
271 case RADV_QUEUE_COMPUTE:
272 return RING_COMPUTE;
273 case RADV_QUEUE_TRANSFER:
274 return RING_DMA;
275 default:
276 unreachable("Unknown queue family");
277 }
278 }
279
280 static VkResult radv_create_cmd_buffer(
281 struct radv_device * device,
282 struct radv_cmd_pool * pool,
283 VkCommandBufferLevel level,
284 VkCommandBuffer* pCommandBuffer)
285 {
286 struct radv_cmd_buffer *cmd_buffer;
287 unsigned ring;
288 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
289 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
290 if (cmd_buffer == NULL)
291 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
292
293 vk_object_base_init(&device->vk, &cmd_buffer->base,
294 VK_OBJECT_TYPE_COMMAND_BUFFER);
295
296 cmd_buffer->device = device;
297 cmd_buffer->pool = pool;
298 cmd_buffer->level = level;
299
300 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
301 cmd_buffer->queue_family_index = pool->queue_family_index;
302
303 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
304
305 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
306 if (!cmd_buffer->cs) {
307 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
308 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
309 }
310
311 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
312
313 list_inithead(&cmd_buffer->upload.list);
314
315 return VK_SUCCESS;
316 }
317
318 static void
319 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
320 {
321 list_del(&cmd_buffer->pool_link);
322
323 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
324 &cmd_buffer->upload.list, list) {
325 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
326 list_del(&up->list);
327 free(up);
328 }
329
330 if (cmd_buffer->upload.upload_bo)
331 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
332 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
333
334 for (unsigned i = 0; i < MAX_BIND_POINTS; i++)
335 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
336
337 vk_object_base_finish(&cmd_buffer->base);
338
339 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
340 }
341
342 static VkResult
343 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
344 {
345 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
346
347 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
348 &cmd_buffer->upload.list, list) {
349 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
350 list_del(&up->list);
351 free(up);
352 }
353
354 cmd_buffer->push_constant_stages = 0;
355 cmd_buffer->scratch_size_per_wave_needed = 0;
356 cmd_buffer->scratch_waves_wanted = 0;
357 cmd_buffer->compute_scratch_size_per_wave_needed = 0;
358 cmd_buffer->compute_scratch_waves_wanted = 0;
359 cmd_buffer->esgs_ring_size_needed = 0;
360 cmd_buffer->gsvs_ring_size_needed = 0;
361 cmd_buffer->tess_rings_needed = false;
362 cmd_buffer->gds_needed = false;
363 cmd_buffer->gds_oa_needed = false;
364 cmd_buffer->sample_positions_needed = false;
365
366 if (cmd_buffer->upload.upload_bo)
367 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
368 cmd_buffer->upload.upload_bo);
369 cmd_buffer->upload.offset = 0;
370
371 cmd_buffer->record_result = VK_SUCCESS;
372
373 memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
374
375 for (unsigned i = 0; i < MAX_BIND_POINTS; i++) {
376 cmd_buffer->descriptors[i].dirty = 0;
377 cmd_buffer->descriptors[i].valid = 0;
378 cmd_buffer->descriptors[i].push_dirty = false;
379 }
380
381 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
382 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
383 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
384 unsigned fence_offset, eop_bug_offset;
385 void *fence_ptr;
386
387 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
388 &fence_ptr);
389
390 cmd_buffer->gfx9_fence_va =
391 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
392 cmd_buffer->gfx9_fence_va += fence_offset;
393
394 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
395 /* Allocate a buffer for the EOP bug on GFX9. */
396 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
397 &eop_bug_offset, &fence_ptr);
398 cmd_buffer->gfx9_eop_bug_va =
399 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
400 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
401 }
402 }
403
404 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
405
406 return cmd_buffer->record_result;
407 }
408
409 static bool
410 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
411 uint64_t min_needed)
412 {
413 uint64_t new_size;
414 struct radeon_winsys_bo *bo;
415 struct radv_cmd_buffer_upload *upload;
416 struct radv_device *device = cmd_buffer->device;
417
418 new_size = MAX2(min_needed, 16 * 1024);
419 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
420
421 bo = device->ws->buffer_create(device->ws,
422 new_size, 4096,
423 RADEON_DOMAIN_GTT,
424 RADEON_FLAG_CPU_ACCESS|
425 RADEON_FLAG_NO_INTERPROCESS_SHARING |
426 RADEON_FLAG_32BIT,
427 RADV_BO_PRIORITY_UPLOAD_BUFFER);
428
429 if (!bo) {
430 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
431 return false;
432 }
433
434 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
435 if (cmd_buffer->upload.upload_bo) {
436 upload = malloc(sizeof(*upload));
437
438 if (!upload) {
439 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
440 device->ws->buffer_destroy(bo);
441 return false;
442 }
443
444 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
445 list_add(&upload->list, &cmd_buffer->upload.list);
446 }
447
448 cmd_buffer->upload.upload_bo = bo;
449 cmd_buffer->upload.size = new_size;
450 cmd_buffer->upload.offset = 0;
451 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
452
453 if (!cmd_buffer->upload.map) {
454 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
455 return false;
456 }
457
458 return true;
459 }
460
461 bool
462 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
463 unsigned size,
464 unsigned alignment,
465 unsigned *out_offset,
466 void **ptr)
467 {
468 assert(util_is_power_of_two_nonzero(alignment));
469
470 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
471 if (offset + size > cmd_buffer->upload.size) {
472 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
473 return false;
474 offset = 0;
475 }
476
477 *out_offset = offset;
478 *ptr = cmd_buffer->upload.map + offset;
479
480 cmd_buffer->upload.offset = offset + size;
481 return true;
482 }
483
484 bool
485 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
486 unsigned size, unsigned alignment,
487 const void *data, unsigned *out_offset)
488 {
489 uint8_t *ptr;
490
491 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
492 out_offset, (void **)&ptr))
493 return false;
494
495 if (ptr)
496 memcpy(ptr, data, size);
497
498 return true;
499 }
500
501 static void
502 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
503 unsigned count, const uint32_t *data)
504 {
505 struct radeon_cmdbuf *cs = cmd_buffer->cs;
506
507 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
508
509 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
510 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
511 S_370_WR_CONFIRM(1) |
512 S_370_ENGINE_SEL(V_370_ME));
513 radeon_emit(cs, va);
514 radeon_emit(cs, va >> 32);
515 radeon_emit_array(cs, data, count);
516 }
517
518 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
519 {
520 struct radv_device *device = cmd_buffer->device;
521 struct radeon_cmdbuf *cs = cmd_buffer->cs;
522 uint64_t va;
523
524 va = radv_buffer_get_va(device->trace_bo);
525 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
526 va += 4;
527
528 ++cmd_buffer->state.trace_id;
529 radv_emit_write_data_packet(cmd_buffer, va, 1,
530 &cmd_buffer->state.trace_id);
531
532 radeon_check_space(cmd_buffer->device->ws, cs, 2);
533
534 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
535 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
536 }
537
538 static void
539 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
540 enum radv_cmd_flush_bits flags)
541 {
542 if (unlikely(cmd_buffer->device->thread_trace_bo)) {
543 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
544 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_THREAD_TRACE_MARKER) | EVENT_INDEX(0));
545 }
546
547 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
548 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
549 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
550
551 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
552
553 /* Force wait for graphics or compute engines to be idle. */
554 si_cs_emit_cache_flush(cmd_buffer->cs,
555 cmd_buffer->device->physical_device->rad_info.chip_class,
556 &cmd_buffer->gfx9_fence_idx,
557 cmd_buffer->gfx9_fence_va,
558 radv_cmd_buffer_uses_mec(cmd_buffer),
559 flags, cmd_buffer->gfx9_eop_bug_va);
560 }
561
562 if (unlikely(cmd_buffer->device->trace_bo))
563 radv_cmd_buffer_trace_emit(cmd_buffer);
564 }
565
566 static void
567 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
568 struct radv_pipeline *pipeline, enum ring_type ring)
569 {
570 struct radv_device *device = cmd_buffer->device;
571 uint32_t data[2];
572 uint64_t va;
573
574 va = radv_buffer_get_va(device->trace_bo);
575
576 switch (ring) {
577 case RING_GFX:
578 va += 8;
579 break;
580 case RING_COMPUTE:
581 va += 16;
582 break;
583 default:
584 assert(!"invalid ring type");
585 }
586
587 uint64_t pipeline_address = (uintptr_t)pipeline;
588 data[0] = pipeline_address;
589 data[1] = pipeline_address >> 32;
590
591 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
592 }
593
594 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
595 VkPipelineBindPoint bind_point,
596 struct radv_descriptor_set *set,
597 unsigned idx)
598 {
599 struct radv_descriptor_state *descriptors_state =
600 radv_get_descriptors_state(cmd_buffer, bind_point);
601
602 descriptors_state->sets[idx] = set;
603
604 descriptors_state->valid |= (1u << idx); /* active descriptors */
605 descriptors_state->dirty |= (1u << idx);
606 }
607
608 static void
609 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
610 VkPipelineBindPoint bind_point)
611 {
612 struct radv_descriptor_state *descriptors_state =
613 radv_get_descriptors_state(cmd_buffer, bind_point);
614 struct radv_device *device = cmd_buffer->device;
615 uint32_t data[MAX_SETS * 2] = {};
616 uint64_t va;
617 unsigned i;
618 va = radv_buffer_get_va(device->trace_bo) + 24;
619
620 for_each_bit(i, descriptors_state->valid) {
621 struct radv_descriptor_set *set = descriptors_state->sets[i];
622 data[i * 2] = (uint64_t)(uintptr_t)set;
623 data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
624 }
625
626 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
627 }
628
629 struct radv_userdata_info *
630 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
631 gl_shader_stage stage,
632 int idx)
633 {
634 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
635 return &shader->info.user_sgprs_locs.shader_data[idx];
636 }
637
638 static void
639 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
640 struct radv_pipeline *pipeline,
641 gl_shader_stage stage,
642 int idx, uint64_t va)
643 {
644 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
645 uint32_t base_reg = pipeline->user_data_0[stage];
646 if (loc->sgpr_idx == -1)
647 return;
648
649 assert(loc->num_sgprs == 1);
650
651 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
652 base_reg + loc->sgpr_idx * 4, va, false);
653 }
654
655 static void
656 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
657 struct radv_pipeline *pipeline,
658 struct radv_descriptor_state *descriptors_state,
659 gl_shader_stage stage)
660 {
661 struct radv_device *device = cmd_buffer->device;
662 struct radeon_cmdbuf *cs = cmd_buffer->cs;
663 uint32_t sh_base = pipeline->user_data_0[stage];
664 struct radv_userdata_locations *locs =
665 &pipeline->shaders[stage]->info.user_sgprs_locs;
666 unsigned mask = locs->descriptor_sets_enabled;
667
668 mask &= descriptors_state->dirty & descriptors_state->valid;
669
670 while (mask) {
671 int start, count;
672
673 u_bit_scan_consecutive_range(&mask, &start, &count);
674
675 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
676 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
677
678 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
679 for (int i = 0; i < count; i++) {
680 struct radv_descriptor_set *set =
681 descriptors_state->sets[start + i];
682
683 radv_emit_shader_pointer_body(device, cs, set->va, true);
684 }
685 }
686 }
687
688 /**
689 * Convert the user sample locations to hardware sample locations (the values
690 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
691 */
692 static void
693 radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
694 uint32_t x, uint32_t y, VkOffset2D *sample_locs)
695 {
696 uint32_t x_offset = x % state->grid_size.width;
697 uint32_t y_offset = y % state->grid_size.height;
698 uint32_t num_samples = (uint32_t)state->per_pixel;
699 VkSampleLocationEXT *user_locs;
700 uint32_t pixel_offset;
701
702 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
703
704 assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
705 user_locs = &state->locations[pixel_offset];
706
707 for (uint32_t i = 0; i < num_samples; i++) {
708 float shifted_pos_x = user_locs[i].x - 0.5;
709 float shifted_pos_y = user_locs[i].y - 0.5;
710
711 int32_t scaled_pos_x = floorf(shifted_pos_x * 16);
712 int32_t scaled_pos_y = floorf(shifted_pos_y * 16);
713
714 sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
715 sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
716 }
717 }
718
719 /**
720 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
721 * locations.
722 */
723 static void
724 radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
725 uint32_t *sample_locs_pixel)
726 {
727 for (uint32_t i = 0; i < num_samples; i++) {
728 uint32_t sample_reg_idx = i / 4;
729 uint32_t sample_loc_idx = i % 4;
730 int32_t pos_x = sample_locs[i].x;
731 int32_t pos_y = sample_locs[i].y;
732
733 uint32_t shift_x = 8 * sample_loc_idx;
734 uint32_t shift_y = shift_x + 4;
735
736 sample_locs_pixel[sample_reg_idx] |= (pos_x & 0xf) << shift_x;
737 sample_locs_pixel[sample_reg_idx] |= (pos_y & 0xf) << shift_y;
738 }
739 }
740
741 /**
742 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
743 * sample locations.
744 */
745 static uint64_t
746 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer,
747 VkOffset2D *sample_locs,
748 uint32_t num_samples)
749 {
750 uint32_t centroid_priorities[num_samples];
751 uint32_t sample_mask = num_samples - 1;
752 uint32_t distances[num_samples];
753 uint64_t centroid_priority = 0;
754
755 /* Compute the distances from center for each sample. */
756 for (int i = 0; i < num_samples; i++) {
757 distances[i] = (sample_locs[i].x * sample_locs[i].x) +
758 (sample_locs[i].y * sample_locs[i].y);
759 }
760
761 /* Compute the centroid priorities by looking at the distances array. */
762 for (int i = 0; i < num_samples; i++) {
763 uint32_t min_idx = 0;
764
765 for (int j = 1; j < num_samples; j++) {
766 if (distances[j] < distances[min_idx])
767 min_idx = j;
768 }
769
770 centroid_priorities[i] = min_idx;
771 distances[min_idx] = 0xffffffff;
772 }
773
774 /* Compute the final centroid priority. */
775 for (int i = 0; i < 8; i++) {
776 centroid_priority |=
777 centroid_priorities[i & sample_mask] << (i * 4);
778 }
779
780 return centroid_priority << 32 | centroid_priority;
781 }
782
783 /**
784 * Emit the sample locations that are specified with VK_EXT_sample_locations.
785 */
786 static void
787 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
788 {
789 struct radv_sample_locations_state *sample_location =
790 &cmd_buffer->state.dynamic.sample_location;
791 uint32_t num_samples = (uint32_t)sample_location->per_pixel;
792 struct radeon_cmdbuf *cs = cmd_buffer->cs;
793 uint32_t sample_locs_pixel[4][2] = {};
794 VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
795 uint32_t max_sample_dist = 0;
796 uint64_t centroid_priority;
797
798 if (!cmd_buffer->state.dynamic.sample_location.count)
799 return;
800
801 /* Convert the user sample locations to hardware sample locations. */
802 radv_convert_user_sample_locs(sample_location, 0, 0, sample_locs[0]);
803 radv_convert_user_sample_locs(sample_location, 1, 0, sample_locs[1]);
804 radv_convert_user_sample_locs(sample_location, 0, 1, sample_locs[2]);
805 radv_convert_user_sample_locs(sample_location, 1, 1, sample_locs[3]);
806
807 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
808 for (uint32_t i = 0; i < 4; i++) {
809 radv_compute_sample_locs_pixel(num_samples, sample_locs[i],
810 sample_locs_pixel[i]);
811 }
812
813 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
814 centroid_priority =
815 radv_compute_centroid_priority(cmd_buffer, sample_locs[0],
816 num_samples);
817
818 /* Compute the maximum sample distance from the specified locations. */
819 for (unsigned i = 0; i < 4; ++i) {
820 for (uint32_t j = 0; j < num_samples; j++) {
821 VkOffset2D offset = sample_locs[i][j];
822 max_sample_dist = MAX2(max_sample_dist,
823 MAX2(abs(offset.x), abs(offset.y)));
824 }
825 }
826
827 /* Emit the specified user sample locations. */
828 switch (num_samples) {
829 case 2:
830 case 4:
831 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
832 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
833 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
834 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
835 break;
836 case 8:
837 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
838 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
839 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
840 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
841 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs_pixel[0][1]);
842 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs_pixel[1][1]);
843 radeon_set_context_reg(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs_pixel[2][1]);
844 radeon_set_context_reg(cs, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs_pixel[3][1]);
845 break;
846 default:
847 unreachable("invalid number of samples");
848 }
849
850 /* Emit the maximum sample distance and the centroid priority. */
851 radeon_set_context_reg_rmw(cs, R_028BE0_PA_SC_AA_CONFIG,
852 S_028BE0_MAX_SAMPLE_DIST(max_sample_dist),
853 ~C_028BE0_MAX_SAMPLE_DIST);
854
855 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
856 radeon_emit(cs, centroid_priority);
857 radeon_emit(cs, centroid_priority >> 32);
858
859 /* GFX9: Flush DFSM when the AA mode changes. */
860 if (cmd_buffer->device->dfsm_allowed) {
861 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
862 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
863 }
864
865 cmd_buffer->state.context_roll_without_scissor_emitted = true;
866 }
867
868 static void
869 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
870 struct radv_pipeline *pipeline,
871 gl_shader_stage stage,
872 int idx, int count, uint32_t *values)
873 {
874 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
875 uint32_t base_reg = pipeline->user_data_0[stage];
876 if (loc->sgpr_idx == -1)
877 return;
878
879 assert(loc->num_sgprs == count);
880
881 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
882 radeon_emit_array(cmd_buffer->cs, values, count);
883 }
884
885 static void
886 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
887 struct radv_pipeline *pipeline)
888 {
889 int num_samples = pipeline->graphics.ms.num_samples;
890 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
891
892 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.needs_sample_positions)
893 cmd_buffer->sample_positions_needed = true;
894
895 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
896 return;
897
898 radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
899
900 cmd_buffer->state.context_roll_without_scissor_emitted = true;
901 }
902
903 static void
904 radv_update_binning_state(struct radv_cmd_buffer *cmd_buffer,
905 struct radv_pipeline *pipeline)
906 {
907 const struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
908
909
910 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
911 return;
912
913 if (old_pipeline &&
914 old_pipeline->graphics.binning.pa_sc_binner_cntl_0 == pipeline->graphics.binning.pa_sc_binner_cntl_0 &&
915 old_pipeline->graphics.binning.db_dfsm_control == pipeline->graphics.binning.db_dfsm_control)
916 return;
917
918 bool binning_flush = false;
919 if (cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA12 ||
920 cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA20 ||
921 cmd_buffer->device->physical_device->rad_info.family == CHIP_RAVEN2 ||
922 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
923 binning_flush = !old_pipeline ||
924 G_028C44_BINNING_MODE(old_pipeline->graphics.binning.pa_sc_binner_cntl_0) !=
925 G_028C44_BINNING_MODE(pipeline->graphics.binning.pa_sc_binner_cntl_0);
926 }
927
928 radeon_set_context_reg(cmd_buffer->cs, R_028C44_PA_SC_BINNER_CNTL_0,
929 pipeline->graphics.binning.pa_sc_binner_cntl_0 |
930 S_028C44_FLUSH_ON_BINNING_TRANSITION(!!binning_flush));
931
932 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
933 radeon_set_context_reg(cmd_buffer->cs, R_028038_DB_DFSM_CONTROL,
934 pipeline->graphics.binning.db_dfsm_control);
935 } else {
936 radeon_set_context_reg(cmd_buffer->cs, R_028060_DB_DFSM_CONTROL,
937 pipeline->graphics.binning.db_dfsm_control);
938 }
939
940 cmd_buffer->state.context_roll_without_scissor_emitted = true;
941 }
942
943
944 static void
945 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
946 struct radv_shader_variant *shader)
947 {
948 uint64_t va;
949
950 if (!shader)
951 return;
952
953 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
954
955 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
956 }
957
958 static void
959 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
960 struct radv_pipeline *pipeline,
961 bool vertex_stage_only)
962 {
963 struct radv_cmd_state *state = &cmd_buffer->state;
964 uint32_t mask = state->prefetch_L2_mask;
965
966 if (vertex_stage_only) {
967 /* Fast prefetch path for starting draws as soon as possible.
968 */
969 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
970 RADV_PREFETCH_VBO_DESCRIPTORS);
971 }
972
973 if (mask & RADV_PREFETCH_VS)
974 radv_emit_shader_prefetch(cmd_buffer,
975 pipeline->shaders[MESA_SHADER_VERTEX]);
976
977 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
978 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
979
980 if (mask & RADV_PREFETCH_TCS)
981 radv_emit_shader_prefetch(cmd_buffer,
982 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
983
984 if (mask & RADV_PREFETCH_TES)
985 radv_emit_shader_prefetch(cmd_buffer,
986 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
987
988 if (mask & RADV_PREFETCH_GS) {
989 radv_emit_shader_prefetch(cmd_buffer,
990 pipeline->shaders[MESA_SHADER_GEOMETRY]);
991 if (radv_pipeline_has_gs_copy_shader(pipeline))
992 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
993 }
994
995 if (mask & RADV_PREFETCH_PS)
996 radv_emit_shader_prefetch(cmd_buffer,
997 pipeline->shaders[MESA_SHADER_FRAGMENT]);
998
999 state->prefetch_L2_mask &= ~mask;
1000 }
1001
1002 static void
1003 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
1004 {
1005 if (!cmd_buffer->device->physical_device->rad_info.rbplus_allowed)
1006 return;
1007
1008 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1009 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1010
1011 unsigned sx_ps_downconvert = 0;
1012 unsigned sx_blend_opt_epsilon = 0;
1013 unsigned sx_blend_opt_control = 0;
1014
1015 if (!cmd_buffer->state.attachments || !subpass)
1016 return;
1017
1018 for (unsigned i = 0; i < subpass->color_count; ++i) {
1019 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1020 /* We don't set the DISABLE bits, because the HW can't have holes,
1021 * so the SPI color format is set to 32-bit 1-component. */
1022 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1023 continue;
1024 }
1025
1026 int idx = subpass->color_attachments[i].attachment;
1027 struct radv_color_buffer_info *cb = &cmd_buffer->state.attachments[idx].cb;
1028
1029 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
1030 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
1031 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
1032 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
1033
1034 bool has_alpha, has_rgb;
1035
1036 /* Set if RGB and A are present. */
1037 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
1038
1039 if (format == V_028C70_COLOR_8 ||
1040 format == V_028C70_COLOR_16 ||
1041 format == V_028C70_COLOR_32)
1042 has_rgb = !has_alpha;
1043 else
1044 has_rgb = true;
1045
1046 /* Check the colormask and export format. */
1047 if (!(colormask & 0x7))
1048 has_rgb = false;
1049 if (!(colormask & 0x8))
1050 has_alpha = false;
1051
1052 if (spi_format == V_028714_SPI_SHADER_ZERO) {
1053 has_rgb = false;
1054 has_alpha = false;
1055 }
1056
1057 /* Disable value checking for disabled channels. */
1058 if (!has_rgb)
1059 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1060 if (!has_alpha)
1061 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1062
1063 /* Enable down-conversion for 32bpp and smaller formats. */
1064 switch (format) {
1065 case V_028C70_COLOR_8:
1066 case V_028C70_COLOR_8_8:
1067 case V_028C70_COLOR_8_8_8_8:
1068 /* For 1 and 2-channel formats, use the superset thereof. */
1069 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
1070 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1071 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1072 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
1073 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
1074 }
1075 break;
1076
1077 case V_028C70_COLOR_5_6_5:
1078 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1079 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
1080 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
1081 }
1082 break;
1083
1084 case V_028C70_COLOR_1_5_5_5:
1085 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1086 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
1087 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
1088 }
1089 break;
1090
1091 case V_028C70_COLOR_4_4_4_4:
1092 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1093 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
1094 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
1095 }
1096 break;
1097
1098 case V_028C70_COLOR_32:
1099 if (swap == V_028C70_SWAP_STD &&
1100 spi_format == V_028714_SPI_SHADER_32_R)
1101 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1102 else if (swap == V_028C70_SWAP_ALT_REV &&
1103 spi_format == V_028714_SPI_SHADER_32_AR)
1104 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
1105 break;
1106
1107 case V_028C70_COLOR_16:
1108 case V_028C70_COLOR_16_16:
1109 /* For 1-channel formats, use the superset thereof. */
1110 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
1111 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
1112 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1113 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1114 if (swap == V_028C70_SWAP_STD ||
1115 swap == V_028C70_SWAP_STD_REV)
1116 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
1117 else
1118 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
1119 }
1120 break;
1121
1122 case V_028C70_COLOR_10_11_11:
1123 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1124 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
1125 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
1126 }
1127 break;
1128
1129 case V_028C70_COLOR_2_10_10_10:
1130 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1131 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
1132 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
1133 }
1134 break;
1135 }
1136 }
1137
1138 /* Do not set the DISABLE bits for the unused attachments, as that
1139 * breaks dual source blending in SkQP and does not seem to improve
1140 * performance. */
1141
1142 if (sx_ps_downconvert == cmd_buffer->state.last_sx_ps_downconvert &&
1143 sx_blend_opt_epsilon == cmd_buffer->state.last_sx_blend_opt_epsilon &&
1144 sx_blend_opt_control == cmd_buffer->state.last_sx_blend_opt_control)
1145 return;
1146
1147 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
1148 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
1149 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
1150 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
1151
1152 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1153
1154 cmd_buffer->state.last_sx_ps_downconvert = sx_ps_downconvert;
1155 cmd_buffer->state.last_sx_blend_opt_epsilon = sx_blend_opt_epsilon;
1156 cmd_buffer->state.last_sx_blend_opt_control = sx_blend_opt_control;
1157 }
1158
1159 static void
1160 radv_emit_batch_break_on_new_ps(struct radv_cmd_buffer *cmd_buffer)
1161 {
1162 if (!cmd_buffer->device->pbb_allowed)
1163 return;
1164
1165 struct radv_binning_settings settings =
1166 radv_get_binning_settings(cmd_buffer->device->physical_device);
1167 bool break_for_new_ps =
1168 (!cmd_buffer->state.emitted_pipeline ||
1169 cmd_buffer->state.emitted_pipeline->shaders[MESA_SHADER_FRAGMENT] !=
1170 cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT]) &&
1171 (settings.context_states_per_bin > 1 ||
1172 settings.persistent_states_per_bin > 1);
1173 bool break_for_new_cb_target_mask =
1174 (!cmd_buffer->state.emitted_pipeline ||
1175 cmd_buffer->state.emitted_pipeline->graphics.cb_target_mask !=
1176 cmd_buffer->state.pipeline->graphics.cb_target_mask) &&
1177 settings.context_states_per_bin > 1;
1178
1179 if (!break_for_new_ps && !break_for_new_cb_target_mask)
1180 return;
1181
1182 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1183 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1184 }
1185
1186 static void
1187 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1188 {
1189 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1190
1191 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1192 return;
1193
1194 radv_update_multisample_state(cmd_buffer, pipeline);
1195 radv_update_binning_state(cmd_buffer, pipeline);
1196
1197 cmd_buffer->scratch_size_per_wave_needed = MAX2(cmd_buffer->scratch_size_per_wave_needed,
1198 pipeline->scratch_bytes_per_wave);
1199 cmd_buffer->scratch_waves_wanted = MAX2(cmd_buffer->scratch_waves_wanted,
1200 pipeline->max_waves);
1201
1202 if (!cmd_buffer->state.emitted_pipeline ||
1203 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1204 pipeline->graphics.can_use_guardband)
1205 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1206
1207 if (!cmd_buffer->state.emitted_pipeline ||
1208 cmd_buffer->state.emitted_pipeline->graphics.pa_su_sc_mode_cntl !=
1209 pipeline->graphics.pa_su_sc_mode_cntl)
1210 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_CULL_MODE |
1211 RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE;
1212
1213 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
1214
1215 if (!cmd_buffer->state.emitted_pipeline ||
1216 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
1217 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
1218 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
1219 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
1220 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
1221 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1222 }
1223
1224 radv_emit_batch_break_on_new_ps(cmd_buffer);
1225
1226 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
1227 if (!pipeline->shaders[i])
1228 continue;
1229
1230 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1231 pipeline->shaders[i]->bo);
1232 }
1233
1234 if (radv_pipeline_has_gs_copy_shader(pipeline))
1235 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1236 pipeline->gs_copy_shader->bo);
1237
1238 if (unlikely(cmd_buffer->device->trace_bo))
1239 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1240
1241 cmd_buffer->state.emitted_pipeline = pipeline;
1242
1243 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1244 }
1245
1246 static void
1247 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1248 {
1249 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1250 cmd_buffer->state.dynamic.viewport.viewports);
1251 }
1252
1253 static void
1254 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1255 {
1256 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1257
1258 si_write_scissors(cmd_buffer->cs, 0, count,
1259 cmd_buffer->state.dynamic.scissor.scissors,
1260 cmd_buffer->state.dynamic.viewport.viewports,
1261 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1262
1263 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1264 }
1265
1266 static void
1267 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1268 {
1269 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1270 return;
1271
1272 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1273 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1274 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1275 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1276 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1277 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1278 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1279 }
1280 }
1281
1282 static void
1283 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1284 {
1285 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1286
1287 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1288 S_028A08_WIDTH(CLAMP(width, 0, 0xFFFF)));
1289 }
1290
1291 static void
1292 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1293 {
1294 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1295
1296 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1297 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1298 }
1299
1300 static void
1301 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1302 {
1303 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1304
1305 radeon_set_context_reg_seq(cmd_buffer->cs,
1306 R_028430_DB_STENCILREFMASK, 2);
1307 radeon_emit(cmd_buffer->cs,
1308 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1309 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1310 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1311 S_028430_STENCILOPVAL(1));
1312 radeon_emit(cmd_buffer->cs,
1313 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1314 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1315 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1316 S_028434_STENCILOPVAL_BF(1));
1317 }
1318
1319 static void
1320 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1321 {
1322 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1323
1324 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1325 fui(d->depth_bounds.min));
1326 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1327 fui(d->depth_bounds.max));
1328 }
1329
1330 static void
1331 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1332 {
1333 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1334 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1335 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1336
1337
1338 radeon_set_context_reg_seq(cmd_buffer->cs,
1339 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1340 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1341 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1342 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1343 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1344 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1345 }
1346
1347 static void
1348 radv_emit_line_stipple(struct radv_cmd_buffer *cmd_buffer)
1349 {
1350 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1351 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1352 uint32_t auto_reset_cntl = 1;
1353
1354 if (pipeline->graphics.topology == V_008958_DI_PT_LINESTRIP)
1355 auto_reset_cntl = 2;
1356
1357 radeon_set_context_reg(cmd_buffer->cs, R_028A0C_PA_SC_LINE_STIPPLE,
1358 S_028A0C_LINE_PATTERN(d->line_stipple.pattern) |
1359 S_028A0C_REPEAT_COUNT(d->line_stipple.factor - 1) |
1360 S_028A0C_AUTO_RESET_CNTL(auto_reset_cntl));
1361 }
1362
1363 static void
1364 radv_emit_culling(struct radv_cmd_buffer *cmd_buffer, uint32_t states)
1365 {
1366 unsigned pa_su_sc_mode_cntl = cmd_buffer->state.pipeline->graphics.pa_su_sc_mode_cntl;
1367 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1368
1369 if (states & RADV_CMD_DIRTY_DYNAMIC_CULL_MODE) {
1370 pa_su_sc_mode_cntl &= C_028814_CULL_FRONT;
1371 pa_su_sc_mode_cntl |= S_028814_CULL_FRONT(!!(d->cull_mode & VK_CULL_MODE_FRONT_BIT));
1372
1373 pa_su_sc_mode_cntl &= C_028814_CULL_BACK;
1374 pa_su_sc_mode_cntl |= S_028814_CULL_BACK(!!(d->cull_mode & VK_CULL_MODE_BACK_BIT));
1375 }
1376
1377 if (states & RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE) {
1378 pa_su_sc_mode_cntl &= C_028814_FACE;
1379 pa_su_sc_mode_cntl |= S_028814_FACE(d->front_face);
1380 }
1381
1382 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
1383 pa_su_sc_mode_cntl);
1384 }
1385
1386 static void
1387 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1388 int index,
1389 struct radv_color_buffer_info *cb,
1390 struct radv_image_view *iview,
1391 VkImageLayout layout,
1392 bool in_render_loop)
1393 {
1394 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
1395 uint32_t cb_color_info = cb->cb_color_info;
1396 struct radv_image *image = iview->image;
1397
1398 if (!radv_layout_dcc_compressed(cmd_buffer->device, image, layout, in_render_loop,
1399 radv_image_queue_family_mask(image,
1400 cmd_buffer->queue_family_index,
1401 cmd_buffer->queue_family_index))) {
1402 cb_color_info &= C_028C70_DCC_ENABLE;
1403 }
1404
1405 if (!radv_layout_can_fast_clear(image, layout, in_render_loop,
1406 radv_image_queue_family_mask(image,
1407 cmd_buffer->queue_family_index,
1408 cmd_buffer->queue_family_index))) {
1409 cb_color_info &= C_028C70_COMPRESSION;
1410 }
1411
1412 if (radv_image_is_tc_compat_cmask(image) &&
1413 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1414 radv_is_dcc_decompress_pipeline(cmd_buffer))) {
1415 /* If this bit is set, the FMASK decompression operation
1416 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1417 */
1418 cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
1419 }
1420
1421 if (radv_image_has_fmask(image) &&
1422 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1423 radv_is_hw_resolve_pipeline(cmd_buffer))) {
1424 /* Make sure FMASK is enabled if it has been cleared because:
1425 *
1426 * 1) it's required for FMASK_DECOMPRESS operations to avoid
1427 * GPU hangs
1428 * 2) it's necessary for CB_RESOLVE which can read compressed
1429 * FMASK data anyways.
1430 */
1431 cb_color_info |= S_028C70_COMPRESSION(1);
1432 }
1433
1434 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1435 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1436 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1437 radeon_emit(cmd_buffer->cs, 0);
1438 radeon_emit(cmd_buffer->cs, 0);
1439 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1440 radeon_emit(cmd_buffer->cs, cb_color_info);
1441 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1442 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1443 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1444 radeon_emit(cmd_buffer->cs, 0);
1445 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1446 radeon_emit(cmd_buffer->cs, 0);
1447
1448 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 1);
1449 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1450
1451 radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4,
1452 cb->cb_color_base >> 32);
1453 radeon_set_context_reg(cmd_buffer->cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + index * 4,
1454 cb->cb_color_cmask >> 32);
1455 radeon_set_context_reg(cmd_buffer->cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + index * 4,
1456 cb->cb_color_fmask >> 32);
1457 radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4,
1458 cb->cb_dcc_base >> 32);
1459 radeon_set_context_reg(cmd_buffer->cs, R_028EC0_CB_COLOR0_ATTRIB2 + index * 4,
1460 cb->cb_color_attrib2);
1461 radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4,
1462 cb->cb_color_attrib3);
1463 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1464 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1465 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1466 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1467 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1468 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1469 radeon_emit(cmd_buffer->cs, cb_color_info);
1470 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1471 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1472 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1473 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1474 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1475 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1476
1477 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1478 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1479 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1480
1481 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1482 cb->cb_mrt_epitch);
1483 } else {
1484 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1485 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1486 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1487 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1488 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1489 radeon_emit(cmd_buffer->cs, cb_color_info);
1490 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1491 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1492 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1493 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1494 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1495 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1496
1497 if (is_vi) { /* DCC BASE */
1498 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1499 }
1500 }
1501
1502 if (radv_dcc_enabled(image, iview->base_mip)) {
1503 /* Drawing with DCC enabled also compresses colorbuffers. */
1504 VkImageSubresourceRange range = {
1505 .aspectMask = iview->aspect_mask,
1506 .baseMipLevel = iview->base_mip,
1507 .levelCount = iview->level_count,
1508 .baseArrayLayer = iview->base_layer,
1509 .layerCount = iview->layer_count,
1510 };
1511
1512 radv_update_dcc_metadata(cmd_buffer, image, &range, true);
1513 }
1514 }
1515
1516 static void
1517 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1518 struct radv_ds_buffer_info *ds,
1519 const struct radv_image_view *iview,
1520 VkImageLayout layout,
1521 bool in_render_loop, bool requires_cond_exec)
1522 {
1523 const struct radv_image *image = iview->image;
1524 uint32_t db_z_info = ds->db_z_info;
1525 uint32_t db_z_info_reg;
1526
1527 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug ||
1528 !radv_image_is_tc_compat_htile(image))
1529 return;
1530
1531 if (!radv_layout_is_htile_compressed(image, layout, in_render_loop,
1532 radv_image_queue_family_mask(image,
1533 cmd_buffer->queue_family_index,
1534 cmd_buffer->queue_family_index))) {
1535 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1536 }
1537
1538 db_z_info &= C_028040_ZRANGE_PRECISION;
1539
1540 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1541 db_z_info_reg = R_028038_DB_Z_INFO;
1542 } else {
1543 db_z_info_reg = R_028040_DB_Z_INFO;
1544 }
1545
1546 /* When we don't know the last fast clear value we need to emit a
1547 * conditional packet that will eventually skip the following
1548 * SET_CONTEXT_REG packet.
1549 */
1550 if (requires_cond_exec) {
1551 uint64_t va = radv_get_tc_compat_zrange_va(image, iview->base_mip);
1552
1553 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1554 radeon_emit(cmd_buffer->cs, va);
1555 radeon_emit(cmd_buffer->cs, va >> 32);
1556 radeon_emit(cmd_buffer->cs, 0);
1557 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1558 }
1559
1560 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1561 }
1562
1563 static void
1564 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1565 struct radv_ds_buffer_info *ds,
1566 struct radv_image_view *iview,
1567 VkImageLayout layout,
1568 bool in_render_loop)
1569 {
1570 const struct radv_image *image = iview->image;
1571 uint32_t db_z_info = ds->db_z_info;
1572 uint32_t db_stencil_info = ds->db_stencil_info;
1573
1574 if (!radv_layout_is_htile_compressed(image, layout, in_render_loop,
1575 radv_image_queue_family_mask(image,
1576 cmd_buffer->queue_family_index,
1577 cmd_buffer->queue_family_index))) {
1578 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1579 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1580 }
1581
1582 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1583 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1584
1585 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1586 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1587 radeon_set_context_reg(cmd_buffer->cs, R_02801C_DB_DEPTH_SIZE_XY, ds->db_depth_size);
1588
1589 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 7);
1590 radeon_emit(cmd_buffer->cs, S_02803C_RESOURCE_LEVEL(1));
1591 radeon_emit(cmd_buffer->cs, db_z_info);
1592 radeon_emit(cmd_buffer->cs, db_stencil_info);
1593 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1594 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1595 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1596 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1597
1598 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_READ_BASE_HI, 5);
1599 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1600 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1601 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1602 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1603 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1604 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1605 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1606 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1607 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1608 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1609
1610 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1611 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1612 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1613 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1614 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1615 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1616 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1617 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1618 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1619 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1620 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1621
1622 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1623 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1624 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1625 } else {
1626 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1627
1628 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1629 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1630 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1631 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1632 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1633 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1634 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1635 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1636 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1637 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1638
1639 }
1640
1641 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1642 radv_update_zrange_precision(cmd_buffer, ds, iview, layout,
1643 in_render_loop, true);
1644
1645 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1646 ds->pa_su_poly_offset_db_fmt_cntl);
1647 }
1648
1649 /**
1650 * Update the fast clear depth/stencil values if the image is bound as a
1651 * depth/stencil buffer.
1652 */
1653 static void
1654 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1655 const struct radv_image_view *iview,
1656 VkClearDepthStencilValue ds_clear_value,
1657 VkImageAspectFlags aspects)
1658 {
1659 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1660 const struct radv_image *image = iview->image;
1661 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1662 uint32_t att_idx;
1663
1664 if (!cmd_buffer->state.attachments || !subpass)
1665 return;
1666
1667 if (!subpass->depth_stencil_attachment)
1668 return;
1669
1670 att_idx = subpass->depth_stencil_attachment->attachment;
1671 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1672 return;
1673
1674 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1675 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1676 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1677 radeon_emit(cs, ds_clear_value.stencil);
1678 radeon_emit(cs, fui(ds_clear_value.depth));
1679 } else if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1680 radeon_set_context_reg_seq(cs, R_02802C_DB_DEPTH_CLEAR, 1);
1681 radeon_emit(cs, fui(ds_clear_value.depth));
1682 } else {
1683 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1684 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 1);
1685 radeon_emit(cs, ds_clear_value.stencil);
1686 }
1687
1688 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1689 * only needed when clearing Z to 0.0.
1690 */
1691 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1692 ds_clear_value.depth == 0.0) {
1693 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1694 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
1695
1696 radv_update_zrange_precision(cmd_buffer, &cmd_buffer->state.attachments[att_idx].ds,
1697 iview, layout, in_render_loop, false);
1698 }
1699
1700 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1701 }
1702
1703 /**
1704 * Set the clear depth/stencil values to the image's metadata.
1705 */
1706 static void
1707 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1708 struct radv_image *image,
1709 const VkImageSubresourceRange *range,
1710 VkClearDepthStencilValue ds_clear_value,
1711 VkImageAspectFlags aspects)
1712 {
1713 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1714 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel);
1715 uint32_t level_count = radv_get_levelCount(image, range);
1716
1717 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1718 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1719 /* Use the fastest way when both aspects are used. */
1720 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + 2 * level_count, cmd_buffer->state.predicating));
1721 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1722 S_370_WR_CONFIRM(1) |
1723 S_370_ENGINE_SEL(V_370_PFP));
1724 radeon_emit(cs, va);
1725 radeon_emit(cs, va >> 32);
1726
1727 for (uint32_t l = 0; l < level_count; l++) {
1728 radeon_emit(cs, ds_clear_value.stencil);
1729 radeon_emit(cs, fui(ds_clear_value.depth));
1730 }
1731 } else {
1732 /* Otherwise we need one WRITE_DATA packet per level. */
1733 for (uint32_t l = 0; l < level_count; l++) {
1734 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel + l);
1735 unsigned value;
1736
1737 if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1738 value = fui(ds_clear_value.depth);
1739 va += 4;
1740 } else {
1741 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1742 value = ds_clear_value.stencil;
1743 }
1744
1745 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1746 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1747 S_370_WR_CONFIRM(1) |
1748 S_370_ENGINE_SEL(V_370_PFP));
1749 radeon_emit(cs, va);
1750 radeon_emit(cs, va >> 32);
1751 radeon_emit(cs, value);
1752 }
1753 }
1754 }
1755
1756 /**
1757 * Update the TC-compat metadata value for this image.
1758 */
1759 static void
1760 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1761 struct radv_image *image,
1762 const VkImageSubresourceRange *range,
1763 uint32_t value)
1764 {
1765 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1766
1767 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug)
1768 return;
1769
1770 uint64_t va = radv_get_tc_compat_zrange_va(image, range->baseMipLevel);
1771 uint32_t level_count = radv_get_levelCount(image, range);
1772
1773 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + level_count, cmd_buffer->state.predicating));
1774 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1775 S_370_WR_CONFIRM(1) |
1776 S_370_ENGINE_SEL(V_370_PFP));
1777 radeon_emit(cs, va);
1778 radeon_emit(cs, va >> 32);
1779
1780 for (uint32_t l = 0; l < level_count; l++)
1781 radeon_emit(cs, value);
1782 }
1783
1784 static void
1785 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1786 const struct radv_image_view *iview,
1787 VkClearDepthStencilValue ds_clear_value)
1788 {
1789 VkImageSubresourceRange range = {
1790 .aspectMask = iview->aspect_mask,
1791 .baseMipLevel = iview->base_mip,
1792 .levelCount = iview->level_count,
1793 .baseArrayLayer = iview->base_layer,
1794 .layerCount = iview->layer_count,
1795 };
1796 uint32_t cond_val;
1797
1798 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1799 * depth clear value is 0.0f.
1800 */
1801 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1802
1803 radv_set_tc_compat_zrange_metadata(cmd_buffer, iview->image, &range,
1804 cond_val);
1805 }
1806
1807 /**
1808 * Update the clear depth/stencil values for this image.
1809 */
1810 void
1811 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1812 const struct radv_image_view *iview,
1813 VkClearDepthStencilValue ds_clear_value,
1814 VkImageAspectFlags aspects)
1815 {
1816 VkImageSubresourceRange range = {
1817 .aspectMask = iview->aspect_mask,
1818 .baseMipLevel = iview->base_mip,
1819 .levelCount = iview->level_count,
1820 .baseArrayLayer = iview->base_layer,
1821 .layerCount = iview->layer_count,
1822 };
1823 struct radv_image *image = iview->image;
1824
1825 assert(radv_image_has_htile(image));
1826
1827 radv_set_ds_clear_metadata(cmd_buffer, iview->image, &range,
1828 ds_clear_value, aspects);
1829
1830 if (radv_image_is_tc_compat_htile(image) &&
1831 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1832 radv_update_tc_compat_zrange_metadata(cmd_buffer, iview,
1833 ds_clear_value);
1834 }
1835
1836 radv_update_bound_fast_clear_ds(cmd_buffer, iview, ds_clear_value,
1837 aspects);
1838 }
1839
1840 /**
1841 * Load the clear depth/stencil values from the image's metadata.
1842 */
1843 static void
1844 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1845 const struct radv_image_view *iview)
1846 {
1847 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1848 const struct radv_image *image = iview->image;
1849 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1850 uint64_t va = radv_get_ds_clear_value_va(image, iview->base_mip);
1851 unsigned reg_offset = 0, reg_count = 0;
1852
1853 if (!radv_image_has_htile(image))
1854 return;
1855
1856 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1857 ++reg_count;
1858 } else {
1859 ++reg_offset;
1860 va += 4;
1861 }
1862 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1863 ++reg_count;
1864
1865 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1866
1867 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
1868 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG_INDEX, 3, 0));
1869 radeon_emit(cs, va);
1870 radeon_emit(cs, va >> 32);
1871 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1872 radeon_emit(cs, reg_count);
1873 } else {
1874 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1875 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1876 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1877 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1878 radeon_emit(cs, va);
1879 radeon_emit(cs, va >> 32);
1880 radeon_emit(cs, reg >> 2);
1881 radeon_emit(cs, 0);
1882
1883 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1884 radeon_emit(cs, 0);
1885 }
1886 }
1887
1888 /*
1889 * With DCC some colors don't require CMASK elimination before being
1890 * used as a texture. This sets a predicate value to determine if the
1891 * cmask eliminate is required.
1892 */
1893 void
1894 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1895 struct radv_image *image,
1896 const VkImageSubresourceRange *range, bool value)
1897 {
1898 uint64_t pred_val = value;
1899 uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
1900 uint32_t level_count = radv_get_levelCount(image, range);
1901 uint32_t count = 2 * level_count;
1902
1903 assert(radv_dcc_enabled(image, range->baseMipLevel));
1904
1905 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1906 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1907 S_370_WR_CONFIRM(1) |
1908 S_370_ENGINE_SEL(V_370_PFP));
1909 radeon_emit(cmd_buffer->cs, va);
1910 radeon_emit(cmd_buffer->cs, va >> 32);
1911
1912 for (uint32_t l = 0; l < level_count; l++) {
1913 radeon_emit(cmd_buffer->cs, pred_val);
1914 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1915 }
1916 }
1917
1918 /**
1919 * Update the DCC predicate to reflect the compression state.
1920 */
1921 void
1922 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1923 struct radv_image *image,
1924 const VkImageSubresourceRange *range, bool value)
1925 {
1926 uint64_t pred_val = value;
1927 uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
1928 uint32_t level_count = radv_get_levelCount(image, range);
1929 uint32_t count = 2 * level_count;
1930
1931 assert(radv_dcc_enabled(image, range->baseMipLevel));
1932
1933 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1934 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1935 S_370_WR_CONFIRM(1) |
1936 S_370_ENGINE_SEL(V_370_PFP));
1937 radeon_emit(cmd_buffer->cs, va);
1938 radeon_emit(cmd_buffer->cs, va >> 32);
1939
1940 for (uint32_t l = 0; l < level_count; l++) {
1941 radeon_emit(cmd_buffer->cs, pred_val);
1942 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1943 }
1944 }
1945
1946 /**
1947 * Update the fast clear color values if the image is bound as a color buffer.
1948 */
1949 static void
1950 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1951 struct radv_image *image,
1952 int cb_idx,
1953 uint32_t color_values[2])
1954 {
1955 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1956 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1957 uint32_t att_idx;
1958
1959 if (!cmd_buffer->state.attachments || !subpass)
1960 return;
1961
1962 att_idx = subpass->color_attachments[cb_idx].attachment;
1963 if (att_idx == VK_ATTACHMENT_UNUSED)
1964 return;
1965
1966 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1967 return;
1968
1969 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1970 radeon_emit(cs, color_values[0]);
1971 radeon_emit(cs, color_values[1]);
1972
1973 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1974 }
1975
1976 /**
1977 * Set the clear color values to the image's metadata.
1978 */
1979 static void
1980 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1981 struct radv_image *image,
1982 const VkImageSubresourceRange *range,
1983 uint32_t color_values[2])
1984 {
1985 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1986 uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
1987 uint32_t level_count = radv_get_levelCount(image, range);
1988 uint32_t count = 2 * level_count;
1989
1990 assert(radv_image_has_cmask(image) ||
1991 radv_dcc_enabled(image, range->baseMipLevel));
1992
1993 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
1994 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1995 S_370_WR_CONFIRM(1) |
1996 S_370_ENGINE_SEL(V_370_PFP));
1997 radeon_emit(cs, va);
1998 radeon_emit(cs, va >> 32);
1999
2000 for (uint32_t l = 0; l < level_count; l++) {
2001 radeon_emit(cs, color_values[0]);
2002 radeon_emit(cs, color_values[1]);
2003 }
2004 }
2005
2006 /**
2007 * Update the clear color values for this image.
2008 */
2009 void
2010 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
2011 const struct radv_image_view *iview,
2012 int cb_idx,
2013 uint32_t color_values[2])
2014 {
2015 struct radv_image *image = iview->image;
2016 VkImageSubresourceRange range = {
2017 .aspectMask = iview->aspect_mask,
2018 .baseMipLevel = iview->base_mip,
2019 .levelCount = iview->level_count,
2020 .baseArrayLayer = iview->base_layer,
2021 .layerCount = iview->layer_count,
2022 };
2023
2024 assert(radv_image_has_cmask(image) ||
2025 radv_dcc_enabled(image, iview->base_mip));
2026
2027 radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
2028
2029 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
2030 color_values);
2031 }
2032
2033 /**
2034 * Load the clear color values from the image's metadata.
2035 */
2036 static void
2037 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
2038 struct radv_image_view *iview,
2039 int cb_idx)
2040 {
2041 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2042 struct radv_image *image = iview->image;
2043 uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
2044
2045 if (!radv_image_has_cmask(image) &&
2046 !radv_dcc_enabled(image, iview->base_mip))
2047 return;
2048
2049 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
2050
2051 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
2052 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG_INDEX, 3, cmd_buffer->state.predicating));
2053 radeon_emit(cs, va);
2054 radeon_emit(cs, va >> 32);
2055 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
2056 radeon_emit(cs, 2);
2057 } else {
2058 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
2059 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2060 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2061 COPY_DATA_COUNT_SEL);
2062 radeon_emit(cs, va);
2063 radeon_emit(cs, va >> 32);
2064 radeon_emit(cs, reg >> 2);
2065 radeon_emit(cs, 0);
2066
2067 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
2068 radeon_emit(cs, 0);
2069 }
2070 }
2071
2072 static void
2073 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
2074 {
2075 int i;
2076 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
2077 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2078
2079 /* this may happen for inherited secondary recording */
2080 if (!framebuffer)
2081 return;
2082
2083 for (i = 0; i < 8; ++i) {
2084 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
2085 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2086 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2087 continue;
2088 }
2089
2090 int idx = subpass->color_attachments[i].attachment;
2091 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
2092 VkImageLayout layout = subpass->color_attachments[i].layout;
2093 bool in_render_loop = subpass->color_attachments[i].in_render_loop;
2094
2095 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, iview->bo);
2096
2097 assert(iview->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
2098 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
2099 radv_emit_fb_color_state(cmd_buffer, i, &cmd_buffer->state.attachments[idx].cb, iview, layout, in_render_loop);
2100
2101 radv_load_color_clear_metadata(cmd_buffer, iview, i);
2102 }
2103
2104 if (subpass->depth_stencil_attachment) {
2105 int idx = subpass->depth_stencil_attachment->attachment;
2106 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
2107 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
2108 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
2109 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, cmd_buffer->state.attachments[idx].iview->bo);
2110
2111 radv_emit_fb_ds_state(cmd_buffer, &cmd_buffer->state.attachments[idx].ds, iview, layout, in_render_loop);
2112
2113 if (cmd_buffer->state.attachments[idx].ds.offset_scale != cmd_buffer->state.offset_scale) {
2114 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2115 cmd_buffer->state.offset_scale = cmd_buffer->state.attachments[idx].ds.offset_scale;
2116 }
2117 radv_load_ds_clear_metadata(cmd_buffer, iview);
2118 } else {
2119 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9)
2120 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
2121 else
2122 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
2123
2124 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
2125 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
2126 }
2127 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2128 S_028208_BR_X(framebuffer->width) |
2129 S_028208_BR_Y(framebuffer->height));
2130
2131 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
2132 bool disable_constant_encode =
2133 cmd_buffer->device->physical_device->rad_info.has_dcc_constant_encode;
2134 enum chip_class chip_class =
2135 cmd_buffer->device->physical_device->rad_info.chip_class;
2136 uint8_t watermark = chip_class >= GFX10 ? 6 : 4;
2137
2138 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
2139 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class <= GFX9) |
2140 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
2141 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
2142 }
2143
2144 if (cmd_buffer->device->dfsm_allowed) {
2145 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2146 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
2147 }
2148
2149 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
2150 }
2151
2152 static void
2153 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer, bool indirect)
2154 {
2155 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2156 struct radv_cmd_state *state = &cmd_buffer->state;
2157
2158 if (state->index_type != state->last_index_type) {
2159 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2160 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2161 cs, R_03090C_VGT_INDEX_TYPE,
2162 2, state->index_type);
2163 } else {
2164 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2165 radeon_emit(cs, state->index_type);
2166 }
2167
2168 state->last_index_type = state->index_type;
2169 }
2170
2171 /* For the direct indexed draws we use DRAW_INDEX_2, which includes
2172 * the index_va and max_index_count already. */
2173 if (!indirect)
2174 return;
2175
2176 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2177 radeon_emit(cs, state->index_va);
2178 radeon_emit(cs, state->index_va >> 32);
2179
2180 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2181 radeon_emit(cs, state->max_index_count);
2182
2183 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
2184 }
2185
2186 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
2187 {
2188 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
2189 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2190 uint32_t pa_sc_mode_cntl_1 =
2191 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
2192 uint32_t db_count_control;
2193
2194 if(!cmd_buffer->state.active_occlusion_queries) {
2195 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2196 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2197 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2198 has_perfect_queries) {
2199 /* Re-enable out-of-order rasterization if the
2200 * bound pipeline supports it and if it's has
2201 * been disabled before starting any perfect
2202 * occlusion queries.
2203 */
2204 radeon_set_context_reg(cmd_buffer->cs,
2205 R_028A4C_PA_SC_MODE_CNTL_1,
2206 pa_sc_mode_cntl_1);
2207 }
2208 }
2209 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
2210 } else {
2211 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2212 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
2213 bool gfx10_perfect = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10 && has_perfect_queries;
2214
2215 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2216 /* Always enable PERFECT_ZPASS_COUNTS due to issues with partially
2217 * covered tiles, discards, and early depth testing. For more details,
2218 * see https://gitlab.freedesktop.org/mesa/mesa/-/issues/3218 */
2219 db_count_control =
2220 S_028004_PERFECT_ZPASS_COUNTS(1) |
2221 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
2222 S_028004_SAMPLE_RATE(sample_rate) |
2223 S_028004_ZPASS_ENABLE(1) |
2224 S_028004_SLICE_EVEN_ENABLE(1) |
2225 S_028004_SLICE_ODD_ENABLE(1);
2226
2227 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2228 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2229 has_perfect_queries) {
2230 /* If the bound pipeline has enabled
2231 * out-of-order rasterization, we should
2232 * disable it before starting any perfect
2233 * occlusion queries.
2234 */
2235 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
2236
2237 radeon_set_context_reg(cmd_buffer->cs,
2238 R_028A4C_PA_SC_MODE_CNTL_1,
2239 pa_sc_mode_cntl_1);
2240 }
2241 } else {
2242 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
2243 S_028004_SAMPLE_RATE(sample_rate);
2244 }
2245 }
2246
2247 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
2248
2249 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2250 }
2251
2252 static void
2253 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
2254 {
2255 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
2256
2257 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
2258 radv_emit_viewport(cmd_buffer);
2259
2260 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
2261 !cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
2262 radv_emit_scissor(cmd_buffer);
2263
2264 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
2265 radv_emit_line_width(cmd_buffer);
2266
2267 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
2268 radv_emit_blend_constants(cmd_buffer);
2269
2270 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
2271 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
2272 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
2273 radv_emit_stencil(cmd_buffer);
2274
2275 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
2276 radv_emit_depth_bounds(cmd_buffer);
2277
2278 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
2279 radv_emit_depth_bias(cmd_buffer);
2280
2281 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
2282 radv_emit_discard_rectangle(cmd_buffer);
2283
2284 if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)
2285 radv_emit_sample_locations(cmd_buffer);
2286
2287 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE)
2288 radv_emit_line_stipple(cmd_buffer);
2289
2290 if (states & (RADV_CMD_DIRTY_DYNAMIC_CULL_MODE |
2291 RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE))
2292 radv_emit_culling(cmd_buffer, states);
2293
2294 cmd_buffer->state.dirty &= ~states;
2295 }
2296
2297 static void
2298 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
2299 VkPipelineBindPoint bind_point)
2300 {
2301 struct radv_descriptor_state *descriptors_state =
2302 radv_get_descriptors_state(cmd_buffer, bind_point);
2303 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
2304 unsigned bo_offset;
2305
2306 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
2307 set->mapped_ptr,
2308 &bo_offset))
2309 return;
2310
2311 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2312 set->va += bo_offset;
2313 }
2314
2315 static void
2316 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
2317 VkPipelineBindPoint bind_point)
2318 {
2319 struct radv_descriptor_state *descriptors_state =
2320 radv_get_descriptors_state(cmd_buffer, bind_point);
2321 uint32_t size = MAX_SETS * 4;
2322 uint32_t offset;
2323 void *ptr;
2324
2325 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
2326 256, &offset, &ptr))
2327 return;
2328
2329 for (unsigned i = 0; i < MAX_SETS; i++) {
2330 uint32_t *uptr = ((uint32_t *)ptr) + i;
2331 uint64_t set_va = 0;
2332 struct radv_descriptor_set *set = descriptors_state->sets[i];
2333 if (descriptors_state->valid & (1u << i))
2334 set_va = set->va;
2335 uptr[0] = set_va & 0xffffffff;
2336 }
2337
2338 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2339 va += offset;
2340
2341 if (cmd_buffer->state.pipeline) {
2342 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
2343 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2344 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2345
2346 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
2347 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
2348 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2349
2350 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
2351 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2352 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2353
2354 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2355 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
2356 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2357
2358 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2359 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
2360 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2361 }
2362
2363 if (cmd_buffer->state.compute_pipeline)
2364 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
2365 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2366 }
2367
2368 static void
2369 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
2370 VkShaderStageFlags stages)
2371 {
2372 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2373 VK_PIPELINE_BIND_POINT_COMPUTE :
2374 VK_PIPELINE_BIND_POINT_GRAPHICS;
2375 struct radv_descriptor_state *descriptors_state =
2376 radv_get_descriptors_state(cmd_buffer, bind_point);
2377 struct radv_cmd_state *state = &cmd_buffer->state;
2378 bool flush_indirect_descriptors;
2379
2380 if (!descriptors_state->dirty)
2381 return;
2382
2383 if (descriptors_state->push_dirty)
2384 radv_flush_push_descriptors(cmd_buffer, bind_point);
2385
2386 flush_indirect_descriptors =
2387 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
2388 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
2389 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
2390 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
2391
2392 if (flush_indirect_descriptors)
2393 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
2394
2395 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2396 cmd_buffer->cs,
2397 MAX_SETS * MESA_SHADER_STAGES * 4);
2398
2399 if (cmd_buffer->state.pipeline) {
2400 radv_foreach_stage(stage, stages) {
2401 if (!cmd_buffer->state.pipeline->shaders[stage])
2402 continue;
2403
2404 radv_emit_descriptor_pointers(cmd_buffer,
2405 cmd_buffer->state.pipeline,
2406 descriptors_state, stage);
2407 }
2408 }
2409
2410 if (cmd_buffer->state.compute_pipeline &&
2411 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
2412 radv_emit_descriptor_pointers(cmd_buffer,
2413 cmd_buffer->state.compute_pipeline,
2414 descriptors_state,
2415 MESA_SHADER_COMPUTE);
2416 }
2417
2418 descriptors_state->dirty = 0;
2419 descriptors_state->push_dirty = false;
2420
2421 assert(cmd_buffer->cs->cdw <= cdw_max);
2422
2423 if (unlikely(cmd_buffer->device->trace_bo))
2424 radv_save_descriptors(cmd_buffer, bind_point);
2425 }
2426
2427 static void
2428 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
2429 VkShaderStageFlags stages)
2430 {
2431 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
2432 ? cmd_buffer->state.compute_pipeline
2433 : cmd_buffer->state.pipeline;
2434 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2435 VK_PIPELINE_BIND_POINT_COMPUTE :
2436 VK_PIPELINE_BIND_POINT_GRAPHICS;
2437 struct radv_descriptor_state *descriptors_state =
2438 radv_get_descriptors_state(cmd_buffer, bind_point);
2439 struct radv_pipeline_layout *layout = pipeline->layout;
2440 struct radv_shader_variant *shader, *prev_shader;
2441 bool need_push_constants = false;
2442 unsigned offset;
2443 void *ptr;
2444 uint64_t va;
2445
2446 stages &= cmd_buffer->push_constant_stages;
2447 if (!stages ||
2448 (!layout->push_constant_size && !layout->dynamic_offset_count))
2449 return;
2450
2451 radv_foreach_stage(stage, stages) {
2452 shader = radv_get_shader(pipeline, stage);
2453 if (!shader)
2454 continue;
2455
2456 need_push_constants |= shader->info.loads_push_constants;
2457 need_push_constants |= shader->info.loads_dynamic_offsets;
2458
2459 uint8_t base = shader->info.base_inline_push_consts;
2460 uint8_t count = shader->info.num_inline_push_consts;
2461
2462 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
2463 AC_UD_INLINE_PUSH_CONSTANTS,
2464 count,
2465 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
2466 }
2467
2468 if (need_push_constants) {
2469 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
2470 16 * layout->dynamic_offset_count,
2471 256, &offset, &ptr))
2472 return;
2473
2474 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
2475 memcpy((char*)ptr + layout->push_constant_size,
2476 descriptors_state->dynamic_buffers,
2477 16 * layout->dynamic_offset_count);
2478
2479 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2480 va += offset;
2481
2482 ASSERTED unsigned cdw_max =
2483 radeon_check_space(cmd_buffer->device->ws,
2484 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
2485
2486 prev_shader = NULL;
2487 radv_foreach_stage(stage, stages) {
2488 shader = radv_get_shader(pipeline, stage);
2489
2490 /* Avoid redundantly emitting the address for merged stages. */
2491 if (shader && shader != prev_shader) {
2492 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
2493 AC_UD_PUSH_CONSTANTS, va);
2494
2495 prev_shader = shader;
2496 }
2497 }
2498 assert(cmd_buffer->cs->cdw <= cdw_max);
2499 }
2500
2501 cmd_buffer->push_constant_stages &= ~stages;
2502 }
2503
2504 static void
2505 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
2506 bool pipeline_is_dirty)
2507 {
2508 if ((pipeline_is_dirty ||
2509 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
2510 cmd_buffer->state.pipeline->num_vertex_bindings &&
2511 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.has_vertex_buffers) {
2512 unsigned vb_offset;
2513 void *vb_ptr;
2514 uint32_t i = 0;
2515 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
2516 uint64_t va;
2517
2518 /* allocate some descriptor state for vertex buffers */
2519 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2520 &vb_offset, &vb_ptr))
2521 return;
2522
2523 for (i = 0; i < count; i++) {
2524 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2525 uint32_t offset;
2526 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2527 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[i];
2528 unsigned num_records;
2529
2530 if (!buffer)
2531 continue;
2532
2533 va = radv_buffer_get_va(buffer->bo);
2534
2535 offset = cmd_buffer->vertex_bindings[i].offset;
2536 va += offset + buffer->offset;
2537
2538 num_records = buffer->size - offset;
2539 if (cmd_buffer->device->physical_device->rad_info.chip_class != GFX8 && stride)
2540 num_records /= stride;
2541
2542 desc[0] = va;
2543 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2544 desc[2] = num_records;
2545 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2546 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2547 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2548 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2549
2550 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2551 /* OOB_SELECT chooses the out-of-bounds check:
2552 * - 1: index >= NUM_RECORDS (Structured)
2553 * - 3: offset >= NUM_RECORDS (Raw)
2554 */
2555 int oob_select = stride ? V_008F0C_OOB_SELECT_STRUCTURED : V_008F0C_OOB_SELECT_RAW;
2556
2557 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT) |
2558 S_008F0C_OOB_SELECT(oob_select) |
2559 S_008F0C_RESOURCE_LEVEL(1);
2560 } else {
2561 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2562 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2563 }
2564 }
2565
2566 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2567 va += vb_offset;
2568
2569 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2570 AC_UD_VS_VERTEX_BUFFERS, va);
2571
2572 cmd_buffer->state.vb_va = va;
2573 cmd_buffer->state.vb_size = count * 16;
2574 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2575 }
2576 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2577 }
2578
2579 static void
2580 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2581 {
2582 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2583 struct radv_userdata_info *loc;
2584 uint32_t base_reg;
2585
2586 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2587 if (!radv_get_shader(pipeline, stage))
2588 continue;
2589
2590 loc = radv_lookup_user_sgpr(pipeline, stage,
2591 AC_UD_STREAMOUT_BUFFERS);
2592 if (loc->sgpr_idx == -1)
2593 continue;
2594
2595 base_reg = pipeline->user_data_0[stage];
2596
2597 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2598 base_reg + loc->sgpr_idx * 4, va, false);
2599 }
2600
2601 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
2602 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2603 if (loc->sgpr_idx != -1) {
2604 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2605
2606 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2607 base_reg + loc->sgpr_idx * 4, va, false);
2608 }
2609 }
2610 }
2611
2612 static void
2613 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2614 {
2615 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2616 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2617 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2618 unsigned so_offset;
2619 void *so_ptr;
2620 uint64_t va;
2621
2622 /* Allocate some descriptor state for streamout buffers. */
2623 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2624 MAX_SO_BUFFERS * 16, 256,
2625 &so_offset, &so_ptr))
2626 return;
2627
2628 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2629 struct radv_buffer *buffer = sb[i].buffer;
2630 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2631
2632 if (!(so->enabled_mask & (1 << i)))
2633 continue;
2634
2635 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2636
2637 va += sb[i].offset;
2638
2639 /* Set the descriptor.
2640 *
2641 * On GFX8, the format must be non-INVALID, otherwise
2642 * the buffer will be considered not bound and store
2643 * instructions will be no-ops.
2644 */
2645 uint32_t size = 0xffffffff;
2646
2647 /* Compute the correct buffer size for NGG streamout
2648 * because it's used to determine the max emit per
2649 * buffer.
2650 */
2651 if (cmd_buffer->device->physical_device->use_ngg_streamout)
2652 size = buffer->size - sb[i].offset;
2653
2654 desc[0] = va;
2655 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2656 desc[2] = size;
2657 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2658 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2659 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2660 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2661
2662 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2663 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2664 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
2665 S_008F0C_RESOURCE_LEVEL(1);
2666 } else {
2667 desc[3] |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2668 }
2669 }
2670
2671 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2672 va += so_offset;
2673
2674 radv_emit_streamout_buffers(cmd_buffer, va);
2675 }
2676
2677 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2678 }
2679
2680 static void
2681 radv_flush_ngg_gs_state(struct radv_cmd_buffer *cmd_buffer)
2682 {
2683 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2684 struct radv_userdata_info *loc;
2685 uint32_t ngg_gs_state = 0;
2686 uint32_t base_reg;
2687
2688 if (!radv_pipeline_has_gs(pipeline) ||
2689 !radv_pipeline_has_ngg(pipeline))
2690 return;
2691
2692 /* By default NGG GS queries are disabled but they are enabled if the
2693 * command buffer has active GDS queries or if it's a secondary command
2694 * buffer that inherits the number of generated primitives.
2695 */
2696 if (cmd_buffer->state.active_pipeline_gds_queries ||
2697 (cmd_buffer->state.inherited_pipeline_statistics & VK_QUERY_PIPELINE_STATISTIC_GEOMETRY_SHADER_PRIMITIVES_BIT))
2698 ngg_gs_state = 1;
2699
2700 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_GEOMETRY,
2701 AC_UD_NGG_GS_STATE);
2702 base_reg = pipeline->user_data_0[MESA_SHADER_GEOMETRY];
2703 assert(loc->sgpr_idx != -1);
2704
2705 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
2706 ngg_gs_state);
2707 }
2708
2709 static void
2710 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2711 {
2712 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2713 radv_flush_streamout_descriptors(cmd_buffer);
2714 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2715 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2716 radv_flush_ngg_gs_state(cmd_buffer);
2717 }
2718
2719 struct radv_draw_info {
2720 /**
2721 * Number of vertices.
2722 */
2723 uint32_t count;
2724
2725 /**
2726 * Index of the first vertex.
2727 */
2728 int32_t vertex_offset;
2729
2730 /**
2731 * First instance id.
2732 */
2733 uint32_t first_instance;
2734
2735 /**
2736 * Number of instances.
2737 */
2738 uint32_t instance_count;
2739
2740 /**
2741 * First index (indexed draws only).
2742 */
2743 uint32_t first_index;
2744
2745 /**
2746 * Whether it's an indexed draw.
2747 */
2748 bool indexed;
2749
2750 /**
2751 * Indirect draw parameters resource.
2752 */
2753 struct radv_buffer *indirect;
2754 uint64_t indirect_offset;
2755 uint32_t stride;
2756
2757 /**
2758 * Draw count parameters resource.
2759 */
2760 struct radv_buffer *count_buffer;
2761 uint64_t count_buffer_offset;
2762
2763 /**
2764 * Stream output parameters resource.
2765 */
2766 struct radv_buffer *strmout_buffer;
2767 uint64_t strmout_buffer_offset;
2768 };
2769
2770 static uint32_t
2771 radv_get_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
2772 {
2773 switch (cmd_buffer->state.index_type) {
2774 case V_028A7C_VGT_INDEX_8:
2775 return 0xffu;
2776 case V_028A7C_VGT_INDEX_16:
2777 return 0xffffu;
2778 case V_028A7C_VGT_INDEX_32:
2779 return 0xffffffffu;
2780 default:
2781 unreachable("invalid index type");
2782 }
2783 }
2784
2785 static void
2786 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
2787 bool instanced_draw, bool indirect_draw,
2788 bool count_from_stream_output,
2789 uint32_t draw_vertex_count)
2790 {
2791 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2792 struct radv_cmd_state *state = &cmd_buffer->state;
2793 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2794 unsigned ia_multi_vgt_param;
2795
2796 ia_multi_vgt_param =
2797 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
2798 indirect_draw,
2799 count_from_stream_output,
2800 draw_vertex_count);
2801
2802 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2803 if (info->chip_class == GFX9) {
2804 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2805 cs,
2806 R_030960_IA_MULTI_VGT_PARAM,
2807 4, ia_multi_vgt_param);
2808 } else if (info->chip_class >= GFX7) {
2809 radeon_set_context_reg_idx(cs,
2810 R_028AA8_IA_MULTI_VGT_PARAM,
2811 1, ia_multi_vgt_param);
2812 } else {
2813 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2814 ia_multi_vgt_param);
2815 }
2816 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2817 }
2818 }
2819
2820 static void
2821 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2822 const struct radv_draw_info *draw_info)
2823 {
2824 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2825 struct radv_cmd_state *state = &cmd_buffer->state;
2826 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2827 int32_t primitive_reset_en;
2828
2829 /* Draw state. */
2830 if (info->chip_class < GFX10) {
2831 si_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2832 draw_info->indirect,
2833 !!draw_info->strmout_buffer,
2834 draw_info->indirect ? 0 : draw_info->count);
2835 }
2836
2837 /* Primitive restart. */
2838 primitive_reset_en =
2839 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2840
2841 if (primitive_reset_en != state->last_primitive_reset_en) {
2842 state->last_primitive_reset_en = primitive_reset_en;
2843 if (info->chip_class >= GFX9) {
2844 radeon_set_uconfig_reg(cs,
2845 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2846 primitive_reset_en);
2847 } else {
2848 radeon_set_context_reg(cs,
2849 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2850 primitive_reset_en);
2851 }
2852 }
2853
2854 if (primitive_reset_en) {
2855 uint32_t primitive_reset_index =
2856 radv_get_primitive_reset_index(cmd_buffer);
2857
2858 if (primitive_reset_index != state->last_primitive_reset_index) {
2859 radeon_set_context_reg(cs,
2860 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2861 primitive_reset_index);
2862 state->last_primitive_reset_index = primitive_reset_index;
2863 }
2864 }
2865
2866 if (draw_info->strmout_buffer) {
2867 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2868
2869 va += draw_info->strmout_buffer->offset +
2870 draw_info->strmout_buffer_offset;
2871
2872 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2873 draw_info->stride);
2874
2875 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2876 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2877 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2878 COPY_DATA_WR_CONFIRM);
2879 radeon_emit(cs, va);
2880 radeon_emit(cs, va >> 32);
2881 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2882 radeon_emit(cs, 0); /* unused */
2883
2884 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2885 }
2886 }
2887
2888 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2889 VkPipelineStageFlags src_stage_mask)
2890 {
2891 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2892 VK_PIPELINE_STAGE_TRANSFER_BIT |
2893 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2894 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2895 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2896 }
2897
2898 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2899 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2900 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2901 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2902 VK_PIPELINE_STAGE_TRANSFER_BIT |
2903 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2904 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2905 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2906 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2907 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2908 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2909 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2910 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2911 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2912 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2913 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2914 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2915 }
2916 }
2917
2918 static enum radv_cmd_flush_bits
2919 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2920 VkAccessFlags src_flags,
2921 struct radv_image *image)
2922 {
2923 bool flush_CB_meta = true, flush_DB_meta = true;
2924 enum radv_cmd_flush_bits flush_bits = 0;
2925 uint32_t b;
2926
2927 if (image) {
2928 if (!radv_image_has_CB_metadata(image))
2929 flush_CB_meta = false;
2930 if (!radv_image_has_htile(image))
2931 flush_DB_meta = false;
2932 }
2933
2934 for_each_bit(b, src_flags) {
2935 switch ((VkAccessFlagBits)(1 << b)) {
2936 case VK_ACCESS_SHADER_WRITE_BIT:
2937 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2938 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2939 flush_bits |= RADV_CMD_FLAG_WB_L2;
2940 break;
2941 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2942 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2943 if (flush_CB_meta)
2944 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2945 break;
2946 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2947 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2948 if (flush_DB_meta)
2949 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2950 break;
2951 case VK_ACCESS_TRANSFER_WRITE_BIT:
2952 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2953 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2954 RADV_CMD_FLAG_INV_L2;
2955
2956 if (flush_CB_meta)
2957 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2958 if (flush_DB_meta)
2959 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2960 break;
2961 case VK_ACCESS_MEMORY_WRITE_BIT:
2962 flush_bits |= RADV_CMD_FLAG_INV_L2 |
2963 RADV_CMD_FLAG_WB_L2 |
2964 RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2965 RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2966
2967 if (flush_CB_meta)
2968 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2969 if (flush_DB_meta)
2970 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2971 break;
2972 default:
2973 break;
2974 }
2975 }
2976 return flush_bits;
2977 }
2978
2979 static enum radv_cmd_flush_bits
2980 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2981 VkAccessFlags dst_flags,
2982 struct radv_image *image)
2983 {
2984 bool flush_CB_meta = true, flush_DB_meta = true;
2985 enum radv_cmd_flush_bits flush_bits = 0;
2986 bool flush_CB = true, flush_DB = true;
2987 bool image_is_coherent = false;
2988 uint32_t b;
2989
2990 if (image) {
2991 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2992 flush_CB = false;
2993 flush_DB = false;
2994 }
2995
2996 if (!radv_image_has_CB_metadata(image))
2997 flush_CB_meta = false;
2998 if (!radv_image_has_htile(image))
2999 flush_DB_meta = false;
3000
3001 /* TODO: implement shader coherent for GFX10 */
3002
3003 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
3004 if (image->info.samples == 1 &&
3005 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
3006 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
3007 !vk_format_is_stencil(image->vk_format)) {
3008 /* Single-sample color and single-sample depth
3009 * (not stencil) are coherent with shaders on
3010 * GFX9.
3011 */
3012 image_is_coherent = true;
3013 }
3014 }
3015 }
3016
3017 for_each_bit(b, dst_flags) {
3018 switch ((VkAccessFlagBits)(1 << b)) {
3019 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
3020 case VK_ACCESS_INDEX_READ_BIT:
3021 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
3022 break;
3023 case VK_ACCESS_UNIFORM_READ_BIT:
3024 flush_bits |= RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_SCACHE;
3025 break;
3026 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
3027 case VK_ACCESS_TRANSFER_READ_BIT:
3028 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
3029 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
3030 RADV_CMD_FLAG_INV_L2;
3031 break;
3032 case VK_ACCESS_SHADER_READ_BIT:
3033 flush_bits |= RADV_CMD_FLAG_INV_VCACHE;
3034 /* Unlike LLVM, ACO uses SMEM for SSBOs and we have to
3035 * invalidate the scalar cache. */
3036 if (!cmd_buffer->device->physical_device->use_llvm)
3037 flush_bits |= RADV_CMD_FLAG_INV_SCACHE;
3038
3039 if (!image_is_coherent)
3040 flush_bits |= RADV_CMD_FLAG_INV_L2;
3041 break;
3042 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
3043 if (flush_CB)
3044 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
3045 if (flush_CB_meta)
3046 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3047 break;
3048 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
3049 if (flush_DB)
3050 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
3051 if (flush_DB_meta)
3052 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3053 break;
3054 case VK_ACCESS_MEMORY_READ_BIT:
3055 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
3056 RADV_CMD_FLAG_INV_SCACHE |
3057 RADV_CMD_FLAG_INV_L2;
3058 if (flush_CB)
3059 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
3060 if (flush_CB_meta)
3061 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3062 if (flush_DB)
3063 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
3064 if (flush_DB_meta)
3065 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3066 break;
3067 default:
3068 break;
3069 }
3070 }
3071 return flush_bits;
3072 }
3073
3074 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
3075 const struct radv_subpass_barrier *barrier)
3076 {
3077 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
3078 NULL);
3079 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
3080 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
3081 NULL);
3082 }
3083
3084 uint32_t
3085 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
3086 {
3087 struct radv_cmd_state *state = &cmd_buffer->state;
3088 uint32_t subpass_id = state->subpass - state->pass->subpasses;
3089
3090 /* The id of this subpass shouldn't exceed the number of subpasses in
3091 * this render pass minus 1.
3092 */
3093 assert(subpass_id < state->pass->subpass_count);
3094 return subpass_id;
3095 }
3096
3097 static struct radv_sample_locations_state *
3098 radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer,
3099 uint32_t att_idx,
3100 bool begin_subpass)
3101 {
3102 struct radv_cmd_state *state = &cmd_buffer->state;
3103 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
3104 struct radv_image_view *view = state->attachments[att_idx].iview;
3105
3106 if (view->image->info.samples == 1)
3107 return NULL;
3108
3109 if (state->pass->attachments[att_idx].first_subpass_idx == subpass_id) {
3110 /* Return the initial sample locations if this is the initial
3111 * layout transition of the given subpass attachemnt.
3112 */
3113 if (state->attachments[att_idx].sample_location.count > 0)
3114 return &state->attachments[att_idx].sample_location;
3115 } else {
3116 /* Otherwise return the subpass sample locations if defined. */
3117 if (state->subpass_sample_locs) {
3118 /* Because the driver sets the current subpass before
3119 * initial layout transitions, we should use the sample
3120 * locations from the previous subpass to avoid an
3121 * off-by-one problem. Otherwise, use the sample
3122 * locations for the current subpass for final layout
3123 * transitions.
3124 */
3125 if (begin_subpass)
3126 subpass_id--;
3127
3128 for (uint32_t i = 0; i < state->num_subpass_sample_locs; i++) {
3129 if (state->subpass_sample_locs[i].subpass_idx == subpass_id)
3130 return &state->subpass_sample_locs[i].sample_location;
3131 }
3132 }
3133 }
3134
3135 return NULL;
3136 }
3137
3138 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
3139 struct radv_subpass_attachment att,
3140 bool begin_subpass)
3141 {
3142 unsigned idx = att.attachment;
3143 struct radv_image_view *view = cmd_buffer->state.attachments[idx].iview;
3144 struct radv_sample_locations_state *sample_locs;
3145 VkImageSubresourceRange range;
3146 range.aspectMask = view->aspect_mask;
3147 range.baseMipLevel = view->base_mip;
3148 range.levelCount = 1;
3149 range.baseArrayLayer = view->base_layer;
3150 range.layerCount = cmd_buffer->state.framebuffer->layers;
3151
3152 if (cmd_buffer->state.subpass->view_mask) {
3153 /* If the current subpass uses multiview, the driver might have
3154 * performed a fast color/depth clear to the whole image
3155 * (including all layers). To make sure the driver will
3156 * decompress the image correctly (if needed), we have to
3157 * account for the "real" number of layers. If the view mask is
3158 * sparse, this will decompress more layers than needed.
3159 */
3160 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
3161 }
3162
3163 /* Get the subpass sample locations for the given attachment, if NULL
3164 * is returned the driver will use the default HW locations.
3165 */
3166 sample_locs = radv_get_attachment_sample_locations(cmd_buffer, idx,
3167 begin_subpass);
3168
3169 /* Determine if the subpass uses separate depth/stencil layouts. */
3170 bool uses_separate_depth_stencil_layouts = false;
3171 if ((cmd_buffer->state.attachments[idx].current_layout !=
3172 cmd_buffer->state.attachments[idx].current_stencil_layout) ||
3173 (att.layout != att.stencil_layout)) {
3174 uses_separate_depth_stencil_layouts = true;
3175 }
3176
3177 /* For separate layouts, perform depth and stencil transitions
3178 * separately.
3179 */
3180 if (uses_separate_depth_stencil_layouts &&
3181 (range.aspectMask == (VK_IMAGE_ASPECT_DEPTH_BIT |
3182 VK_IMAGE_ASPECT_STENCIL_BIT))) {
3183 /* Depth-only transitions. */
3184 range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3185 radv_handle_image_transition(cmd_buffer,
3186 view->image,
3187 cmd_buffer->state.attachments[idx].current_layout,
3188 cmd_buffer->state.attachments[idx].current_in_render_loop,
3189 att.layout, att.in_render_loop,
3190 0, 0, &range, sample_locs);
3191
3192 /* Stencil-only transitions. */
3193 range.aspectMask = VK_IMAGE_ASPECT_STENCIL_BIT;
3194 radv_handle_image_transition(cmd_buffer,
3195 view->image,
3196 cmd_buffer->state.attachments[idx].current_stencil_layout,
3197 cmd_buffer->state.attachments[idx].current_in_render_loop,
3198 att.stencil_layout, att.in_render_loop,
3199 0, 0, &range, sample_locs);
3200 } else {
3201 radv_handle_image_transition(cmd_buffer,
3202 view->image,
3203 cmd_buffer->state.attachments[idx].current_layout,
3204 cmd_buffer->state.attachments[idx].current_in_render_loop,
3205 att.layout, att.in_render_loop,
3206 0, 0, &range, sample_locs);
3207 }
3208
3209 cmd_buffer->state.attachments[idx].current_layout = att.layout;
3210 cmd_buffer->state.attachments[idx].current_stencil_layout = att.stencil_layout;
3211 cmd_buffer->state.attachments[idx].current_in_render_loop = att.in_render_loop;
3212
3213
3214 }
3215
3216 void
3217 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
3218 const struct radv_subpass *subpass)
3219 {
3220 cmd_buffer->state.subpass = subpass;
3221
3222 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
3223 }
3224
3225 static VkResult
3226 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
3227 struct radv_render_pass *pass,
3228 const VkRenderPassBeginInfo *info)
3229 {
3230 const struct VkRenderPassSampleLocationsBeginInfoEXT *sample_locs =
3231 vk_find_struct_const(info->pNext,
3232 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT);
3233 struct radv_cmd_state *state = &cmd_buffer->state;
3234
3235 if (!sample_locs) {
3236 state->subpass_sample_locs = NULL;
3237 return VK_SUCCESS;
3238 }
3239
3240 for (uint32_t i = 0; i < sample_locs->attachmentInitialSampleLocationsCount; i++) {
3241 const VkAttachmentSampleLocationsEXT *att_sample_locs =
3242 &sample_locs->pAttachmentInitialSampleLocations[i];
3243 uint32_t att_idx = att_sample_locs->attachmentIndex;
3244 struct radv_image *image = cmd_buffer->state.attachments[att_idx].iview->image;
3245
3246 assert(vk_format_is_depth_or_stencil(image->vk_format));
3247
3248 /* From the Vulkan spec 1.1.108:
3249 *
3250 * "If the image referenced by the framebuffer attachment at
3251 * index attachmentIndex was not created with
3252 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
3253 * then the values specified in sampleLocationsInfo are
3254 * ignored."
3255 */
3256 if (!(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT))
3257 continue;
3258
3259 const VkSampleLocationsInfoEXT *sample_locs_info =
3260 &att_sample_locs->sampleLocationsInfo;
3261
3262 state->attachments[att_idx].sample_location.per_pixel =
3263 sample_locs_info->sampleLocationsPerPixel;
3264 state->attachments[att_idx].sample_location.grid_size =
3265 sample_locs_info->sampleLocationGridSize;
3266 state->attachments[att_idx].sample_location.count =
3267 sample_locs_info->sampleLocationsCount;
3268 typed_memcpy(&state->attachments[att_idx].sample_location.locations[0],
3269 sample_locs_info->pSampleLocations,
3270 sample_locs_info->sampleLocationsCount);
3271 }
3272
3273 state->subpass_sample_locs = vk_alloc(&cmd_buffer->pool->alloc,
3274 sample_locs->postSubpassSampleLocationsCount *
3275 sizeof(state->subpass_sample_locs[0]),
3276 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3277 if (state->subpass_sample_locs == NULL) {
3278 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3279 return cmd_buffer->record_result;
3280 }
3281
3282 state->num_subpass_sample_locs = sample_locs->postSubpassSampleLocationsCount;
3283
3284 for (uint32_t i = 0; i < sample_locs->postSubpassSampleLocationsCount; i++) {
3285 const VkSubpassSampleLocationsEXT *subpass_sample_locs_info =
3286 &sample_locs->pPostSubpassSampleLocations[i];
3287 const VkSampleLocationsInfoEXT *sample_locs_info =
3288 &subpass_sample_locs_info->sampleLocationsInfo;
3289
3290 state->subpass_sample_locs[i].subpass_idx =
3291 subpass_sample_locs_info->subpassIndex;
3292 state->subpass_sample_locs[i].sample_location.per_pixel =
3293 sample_locs_info->sampleLocationsPerPixel;
3294 state->subpass_sample_locs[i].sample_location.grid_size =
3295 sample_locs_info->sampleLocationGridSize;
3296 state->subpass_sample_locs[i].sample_location.count =
3297 sample_locs_info->sampleLocationsCount;
3298 typed_memcpy(&state->subpass_sample_locs[i].sample_location.locations[0],
3299 sample_locs_info->pSampleLocations,
3300 sample_locs_info->sampleLocationsCount);
3301 }
3302
3303 return VK_SUCCESS;
3304 }
3305
3306 static VkResult
3307 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
3308 struct radv_render_pass *pass,
3309 const VkRenderPassBeginInfo *info)
3310 {
3311 struct radv_cmd_state *state = &cmd_buffer->state;
3312 const struct VkRenderPassAttachmentBeginInfo *attachment_info = NULL;
3313
3314 if (info) {
3315 attachment_info = vk_find_struct_const(info->pNext,
3316 RENDER_PASS_ATTACHMENT_BEGIN_INFO);
3317 }
3318
3319
3320 if (pass->attachment_count == 0) {
3321 state->attachments = NULL;
3322 return VK_SUCCESS;
3323 }
3324
3325 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
3326 pass->attachment_count *
3327 sizeof(state->attachments[0]),
3328 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3329 if (state->attachments == NULL) {
3330 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3331 return cmd_buffer->record_result;
3332 }
3333
3334 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
3335 struct radv_render_pass_attachment *att = &pass->attachments[i];
3336 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
3337 VkImageAspectFlags clear_aspects = 0;
3338
3339 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
3340 /* color attachment */
3341 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3342 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
3343 }
3344 } else {
3345 /* depthstencil attachment */
3346 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
3347 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3348 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
3349 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3350 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
3351 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3352 }
3353 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3354 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3355 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3356 }
3357 }
3358
3359 state->attachments[i].pending_clear_aspects = clear_aspects;
3360 state->attachments[i].cleared_views = 0;
3361 if (clear_aspects && info) {
3362 assert(info->clearValueCount > i);
3363 state->attachments[i].clear_value = info->pClearValues[i];
3364 }
3365
3366 state->attachments[i].current_layout = att->initial_layout;
3367 state->attachments[i].current_stencil_layout = att->stencil_initial_layout;
3368 state->attachments[i].sample_location.count = 0;
3369
3370 struct radv_image_view *iview;
3371 if (attachment_info && attachment_info->attachmentCount > i) {
3372 iview = radv_image_view_from_handle(attachment_info->pAttachments[i]);
3373 } else {
3374 iview = state->framebuffer->attachments[i];
3375 }
3376
3377 state->attachments[i].iview = iview;
3378 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3379 radv_initialise_ds_surface(cmd_buffer->device, &state->attachments[i].ds, iview);
3380 } else {
3381 radv_initialise_color_surface(cmd_buffer->device, &state->attachments[i].cb, iview);
3382 }
3383 }
3384
3385 return VK_SUCCESS;
3386 }
3387
3388 VkResult radv_AllocateCommandBuffers(
3389 VkDevice _device,
3390 const VkCommandBufferAllocateInfo *pAllocateInfo,
3391 VkCommandBuffer *pCommandBuffers)
3392 {
3393 RADV_FROM_HANDLE(radv_device, device, _device);
3394 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
3395
3396 VkResult result = VK_SUCCESS;
3397 uint32_t i;
3398
3399 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
3400
3401 if (!list_is_empty(&pool->free_cmd_buffers)) {
3402 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
3403
3404 list_del(&cmd_buffer->pool_link);
3405 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
3406
3407 result = radv_reset_cmd_buffer(cmd_buffer);
3408 cmd_buffer->level = pAllocateInfo->level;
3409
3410 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
3411 } else {
3412 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
3413 &pCommandBuffers[i]);
3414 }
3415 if (result != VK_SUCCESS)
3416 break;
3417 }
3418
3419 if (result != VK_SUCCESS) {
3420 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
3421 i, pCommandBuffers);
3422
3423 /* From the Vulkan 1.0.66 spec:
3424 *
3425 * "vkAllocateCommandBuffers can be used to create multiple
3426 * command buffers. If the creation of any of those command
3427 * buffers fails, the implementation must destroy all
3428 * successfully created command buffer objects from this
3429 * command, set all entries of the pCommandBuffers array to
3430 * NULL and return the error."
3431 */
3432 memset(pCommandBuffers, 0,
3433 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
3434 }
3435
3436 return result;
3437 }
3438
3439 void radv_FreeCommandBuffers(
3440 VkDevice device,
3441 VkCommandPool commandPool,
3442 uint32_t commandBufferCount,
3443 const VkCommandBuffer *pCommandBuffers)
3444 {
3445 for (uint32_t i = 0; i < commandBufferCount; i++) {
3446 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
3447
3448 if (cmd_buffer) {
3449 if (cmd_buffer->pool) {
3450 list_del(&cmd_buffer->pool_link);
3451 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
3452 } else
3453 radv_cmd_buffer_destroy(cmd_buffer);
3454
3455 }
3456 }
3457 }
3458
3459 VkResult radv_ResetCommandBuffer(
3460 VkCommandBuffer commandBuffer,
3461 VkCommandBufferResetFlags flags)
3462 {
3463 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3464 return radv_reset_cmd_buffer(cmd_buffer);
3465 }
3466
3467 VkResult radv_BeginCommandBuffer(
3468 VkCommandBuffer commandBuffer,
3469 const VkCommandBufferBeginInfo *pBeginInfo)
3470 {
3471 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3472 VkResult result = VK_SUCCESS;
3473
3474 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
3475 /* If the command buffer has already been resetted with
3476 * vkResetCommandBuffer, no need to do it again.
3477 */
3478 result = radv_reset_cmd_buffer(cmd_buffer);
3479 if (result != VK_SUCCESS)
3480 return result;
3481 }
3482
3483 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
3484 cmd_buffer->state.last_primitive_reset_en = -1;
3485 cmd_buffer->state.last_index_type = -1;
3486 cmd_buffer->state.last_num_instances = -1;
3487 cmd_buffer->state.last_vertex_offset = -1;
3488 cmd_buffer->state.last_first_instance = -1;
3489 cmd_buffer->state.predication_type = -1;
3490 cmd_buffer->state.last_sx_ps_downconvert = -1;
3491 cmd_buffer->state.last_sx_blend_opt_epsilon = -1;
3492 cmd_buffer->state.last_sx_blend_opt_control = -1;
3493 cmd_buffer->usage_flags = pBeginInfo->flags;
3494
3495 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
3496 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
3497 assert(pBeginInfo->pInheritanceInfo);
3498 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
3499 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
3500
3501 struct radv_subpass *subpass =
3502 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
3503
3504 if (cmd_buffer->state.framebuffer) {
3505 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
3506 if (result != VK_SUCCESS)
3507 return result;
3508 }
3509
3510 cmd_buffer->state.inherited_pipeline_statistics =
3511 pBeginInfo->pInheritanceInfo->pipelineStatistics;
3512
3513 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3514 }
3515
3516 if (unlikely(cmd_buffer->device->trace_bo))
3517 radv_cmd_buffer_trace_emit(cmd_buffer);
3518
3519 radv_describe_begin_cmd_buffer(cmd_buffer);
3520
3521 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
3522
3523 return result;
3524 }
3525
3526 void radv_CmdBindVertexBuffers(
3527 VkCommandBuffer commandBuffer,
3528 uint32_t firstBinding,
3529 uint32_t bindingCount,
3530 const VkBuffer* pBuffers,
3531 const VkDeviceSize* pOffsets)
3532 {
3533 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3534 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
3535 bool changed = false;
3536
3537 /* We have to defer setting up vertex buffer since we need the buffer
3538 * stride from the pipeline. */
3539
3540 assert(firstBinding + bindingCount <= MAX_VBS);
3541 for (uint32_t i = 0; i < bindingCount; i++) {
3542 RADV_FROM_HANDLE(radv_buffer, buffer, pBuffers[i]);
3543 uint32_t idx = firstBinding + i;
3544
3545 if (!changed &&
3546 (vb[idx].buffer != buffer ||
3547 vb[idx].offset != pOffsets[i])) {
3548 changed = true;
3549 }
3550
3551 vb[idx].buffer = buffer;
3552 vb[idx].offset = pOffsets[i];
3553
3554 if (buffer) {
3555 radv_cs_add_buffer(cmd_buffer->device->ws,
3556 cmd_buffer->cs, vb[idx].buffer->bo);
3557 }
3558 }
3559
3560 if (!changed) {
3561 /* No state changes. */
3562 return;
3563 }
3564
3565 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
3566 }
3567
3568 static uint32_t
3569 vk_to_index_type(VkIndexType type)
3570 {
3571 switch (type) {
3572 case VK_INDEX_TYPE_UINT8_EXT:
3573 return V_028A7C_VGT_INDEX_8;
3574 case VK_INDEX_TYPE_UINT16:
3575 return V_028A7C_VGT_INDEX_16;
3576 case VK_INDEX_TYPE_UINT32:
3577 return V_028A7C_VGT_INDEX_32;
3578 default:
3579 unreachable("invalid index type");
3580 }
3581 }
3582
3583 static uint32_t
3584 radv_get_vgt_index_size(uint32_t type)
3585 {
3586 switch (type) {
3587 case V_028A7C_VGT_INDEX_8:
3588 return 1;
3589 case V_028A7C_VGT_INDEX_16:
3590 return 2;
3591 case V_028A7C_VGT_INDEX_32:
3592 return 4;
3593 default:
3594 unreachable("invalid index type");
3595 }
3596 }
3597
3598 void radv_CmdBindIndexBuffer(
3599 VkCommandBuffer commandBuffer,
3600 VkBuffer buffer,
3601 VkDeviceSize offset,
3602 VkIndexType indexType)
3603 {
3604 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3605 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
3606
3607 if (cmd_buffer->state.index_buffer == index_buffer &&
3608 cmd_buffer->state.index_offset == offset &&
3609 cmd_buffer->state.index_type == indexType) {
3610 /* No state changes. */
3611 return;
3612 }
3613
3614 cmd_buffer->state.index_buffer = index_buffer;
3615 cmd_buffer->state.index_offset = offset;
3616 cmd_buffer->state.index_type = vk_to_index_type(indexType);
3617 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
3618 cmd_buffer->state.index_va += index_buffer->offset + offset;
3619
3620 int index_size = radv_get_vgt_index_size(vk_to_index_type(indexType));
3621 cmd_buffer->state.max_index_count = (index_buffer->size - offset) / index_size;
3622 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3623 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
3624 }
3625
3626
3627 static void
3628 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3629 VkPipelineBindPoint bind_point,
3630 struct radv_descriptor_set *set, unsigned idx)
3631 {
3632 struct radeon_winsys *ws = cmd_buffer->device->ws;
3633
3634 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
3635
3636 assert(set);
3637 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
3638
3639 if (!cmd_buffer->device->use_global_bo_list) {
3640 for (unsigned j = 0; j < set->buffer_count; ++j)
3641 if (set->descriptors[j])
3642 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
3643 }
3644
3645 if(set->bo)
3646 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
3647 }
3648
3649 void radv_CmdBindDescriptorSets(
3650 VkCommandBuffer commandBuffer,
3651 VkPipelineBindPoint pipelineBindPoint,
3652 VkPipelineLayout _layout,
3653 uint32_t firstSet,
3654 uint32_t descriptorSetCount,
3655 const VkDescriptorSet* pDescriptorSets,
3656 uint32_t dynamicOffsetCount,
3657 const uint32_t* pDynamicOffsets)
3658 {
3659 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3660 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3661 unsigned dyn_idx = 0;
3662
3663 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
3664 struct radv_descriptor_state *descriptors_state =
3665 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3666
3667 for (unsigned i = 0; i < descriptorSetCount; ++i) {
3668 unsigned idx = i + firstSet;
3669 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
3670
3671 /* If the set is already bound we only need to update the
3672 * (potentially changed) dynamic offsets. */
3673 if (descriptors_state->sets[idx] != set ||
3674 !(descriptors_state->valid & (1u << idx))) {
3675 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
3676 }
3677
3678 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
3679 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
3680 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
3681 assert(dyn_idx < dynamicOffsetCount);
3682
3683 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
3684 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
3685 dst[0] = va;
3686 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
3687 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
3688 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3689 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3690 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3691 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3692
3693 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
3694 dst[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3695 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3696 S_008F0C_RESOURCE_LEVEL(1);
3697 } else {
3698 dst[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3699 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3700 }
3701
3702 cmd_buffer->push_constant_stages |=
3703 set->layout->dynamic_shader_stages;
3704 }
3705 }
3706 }
3707
3708 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3709 struct radv_descriptor_set *set,
3710 struct radv_descriptor_set_layout *layout,
3711 VkPipelineBindPoint bind_point)
3712 {
3713 struct radv_descriptor_state *descriptors_state =
3714 radv_get_descriptors_state(cmd_buffer, bind_point);
3715 set->size = layout->size;
3716 set->layout = layout;
3717
3718 if (descriptors_state->push_set.capacity < set->size) {
3719 size_t new_size = MAX2(set->size, 1024);
3720 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
3721 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
3722
3723 free(set->mapped_ptr);
3724 set->mapped_ptr = malloc(new_size);
3725
3726 if (!set->mapped_ptr) {
3727 descriptors_state->push_set.capacity = 0;
3728 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3729 return false;
3730 }
3731
3732 descriptors_state->push_set.capacity = new_size;
3733 }
3734
3735 return true;
3736 }
3737
3738 void radv_meta_push_descriptor_set(
3739 struct radv_cmd_buffer* cmd_buffer,
3740 VkPipelineBindPoint pipelineBindPoint,
3741 VkPipelineLayout _layout,
3742 uint32_t set,
3743 uint32_t descriptorWriteCount,
3744 const VkWriteDescriptorSet* pDescriptorWrites)
3745 {
3746 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3747 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
3748 unsigned bo_offset;
3749
3750 assert(set == 0);
3751 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3752
3753 push_set->size = layout->set[set].layout->size;
3754 push_set->layout = layout->set[set].layout;
3755
3756 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
3757 &bo_offset,
3758 (void**) &push_set->mapped_ptr))
3759 return;
3760
3761 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
3762 push_set->va += bo_offset;
3763
3764 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3765 radv_descriptor_set_to_handle(push_set),
3766 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3767
3768 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3769 }
3770
3771 void radv_CmdPushDescriptorSetKHR(
3772 VkCommandBuffer commandBuffer,
3773 VkPipelineBindPoint pipelineBindPoint,
3774 VkPipelineLayout _layout,
3775 uint32_t set,
3776 uint32_t descriptorWriteCount,
3777 const VkWriteDescriptorSet* pDescriptorWrites)
3778 {
3779 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3780 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3781 struct radv_descriptor_state *descriptors_state =
3782 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3783 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3784
3785 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3786
3787 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3788 layout->set[set].layout,
3789 pipelineBindPoint))
3790 return;
3791
3792 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3793 * because it is invalid, according to Vulkan spec.
3794 */
3795 for (int i = 0; i < descriptorWriteCount; i++) {
3796 ASSERTED const VkWriteDescriptorSet *writeset = &pDescriptorWrites[i];
3797 assert(writeset->descriptorType != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT);
3798 }
3799
3800 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3801 radv_descriptor_set_to_handle(push_set),
3802 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3803
3804 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3805 descriptors_state->push_dirty = true;
3806 }
3807
3808 void radv_CmdPushDescriptorSetWithTemplateKHR(
3809 VkCommandBuffer commandBuffer,
3810 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
3811 VkPipelineLayout _layout,
3812 uint32_t set,
3813 const void* pData)
3814 {
3815 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3816 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3817 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
3818 struct radv_descriptor_state *descriptors_state =
3819 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
3820 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3821
3822 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3823
3824 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3825 layout->set[set].layout,
3826 templ->bind_point))
3827 return;
3828
3829 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
3830 descriptorUpdateTemplate, pData);
3831
3832 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
3833 descriptors_state->push_dirty = true;
3834 }
3835
3836 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
3837 VkPipelineLayout layout,
3838 VkShaderStageFlags stageFlags,
3839 uint32_t offset,
3840 uint32_t size,
3841 const void* pValues)
3842 {
3843 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3844 memcpy(cmd_buffer->push_constants + offset, pValues, size);
3845 cmd_buffer->push_constant_stages |= stageFlags;
3846 }
3847
3848 VkResult radv_EndCommandBuffer(
3849 VkCommandBuffer commandBuffer)
3850 {
3851 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3852
3853 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
3854 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6)
3855 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WB_L2;
3856
3857 /* Make sure to sync all pending active queries at the end of
3858 * command buffer.
3859 */
3860 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
3861
3862 /* Since NGG streamout uses GDS, we need to make GDS idle when
3863 * we leave the IB, otherwise another process might overwrite
3864 * it while our shaders are busy.
3865 */
3866 if (cmd_buffer->gds_needed)
3867 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
3868
3869 si_emit_cache_flush(cmd_buffer);
3870 }
3871
3872 /* Make sure CP DMA is idle at the end of IBs because the kernel
3873 * doesn't wait for it.
3874 */
3875 si_cp_dma_wait_for_idle(cmd_buffer);
3876
3877 radv_describe_end_cmd_buffer(cmd_buffer);
3878
3879 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3880 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
3881
3882 VkResult result = cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs);
3883 if (result != VK_SUCCESS)
3884 return vk_error(cmd_buffer->device->instance, result);
3885
3886 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
3887
3888 return cmd_buffer->record_result;
3889 }
3890
3891 static void
3892 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
3893 {
3894 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3895
3896 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
3897 return;
3898
3899 assert(!pipeline->ctx_cs.cdw);
3900
3901 cmd_buffer->state.emitted_compute_pipeline = pipeline;
3902
3903 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
3904 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
3905
3906 cmd_buffer->compute_scratch_size_per_wave_needed = MAX2(cmd_buffer->compute_scratch_size_per_wave_needed,
3907 pipeline->scratch_bytes_per_wave);
3908 cmd_buffer->compute_scratch_waves_wanted = MAX2(cmd_buffer->compute_scratch_waves_wanted,
3909 pipeline->max_waves);
3910
3911 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3912 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
3913
3914 if (unlikely(cmd_buffer->device->trace_bo))
3915 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
3916 }
3917
3918 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
3919 VkPipelineBindPoint bind_point)
3920 {
3921 struct radv_descriptor_state *descriptors_state =
3922 radv_get_descriptors_state(cmd_buffer, bind_point);
3923
3924 descriptors_state->dirty |= descriptors_state->valid;
3925 }
3926
3927 void radv_CmdBindPipeline(
3928 VkCommandBuffer commandBuffer,
3929 VkPipelineBindPoint pipelineBindPoint,
3930 VkPipeline _pipeline)
3931 {
3932 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3933 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
3934
3935 switch (pipelineBindPoint) {
3936 case VK_PIPELINE_BIND_POINT_COMPUTE:
3937 if (cmd_buffer->state.compute_pipeline == pipeline)
3938 return;
3939 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3940
3941 cmd_buffer->state.compute_pipeline = pipeline;
3942 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
3943 break;
3944 case VK_PIPELINE_BIND_POINT_GRAPHICS:
3945 if (cmd_buffer->state.pipeline == pipeline)
3946 return;
3947 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3948
3949 cmd_buffer->state.pipeline = pipeline;
3950 if (!pipeline)
3951 break;
3952
3953 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
3954 cmd_buffer->push_constant_stages |= pipeline->active_stages;
3955
3956 /* the new vertex shader might not have the same user regs */
3957 cmd_buffer->state.last_first_instance = -1;
3958 cmd_buffer->state.last_vertex_offset = -1;
3959
3960 /* Prefetch all pipeline shaders at first draw time. */
3961 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
3962
3963 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX10 &&
3964 cmd_buffer->state.emitted_pipeline &&
3965 radv_pipeline_has_ngg(cmd_buffer->state.emitted_pipeline) &&
3966 !radv_pipeline_has_ngg(cmd_buffer->state.pipeline)) {
3967 /* Transitioning from NGG to legacy GS requires
3968 * VGT_FLUSH on Navi10-14. VGT_FLUSH is also emitted
3969 * at the beginning of IBs when legacy GS ring pointers
3970 * are set.
3971 */
3972 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
3973 }
3974
3975 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
3976 radv_bind_streamout_state(cmd_buffer, pipeline);
3977
3978 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
3979 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
3980 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
3981 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
3982
3983 if (radv_pipeline_has_tess(pipeline))
3984 cmd_buffer->tess_rings_needed = true;
3985 break;
3986 default:
3987 assert(!"invalid bind point");
3988 break;
3989 }
3990 }
3991
3992 void radv_CmdSetViewport(
3993 VkCommandBuffer commandBuffer,
3994 uint32_t firstViewport,
3995 uint32_t viewportCount,
3996 const VkViewport* pViewports)
3997 {
3998 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3999 struct radv_cmd_state *state = &cmd_buffer->state;
4000 ASSERTED const uint32_t total_count = firstViewport + viewportCount;
4001
4002 assert(firstViewport < MAX_VIEWPORTS);
4003 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
4004
4005 if (total_count <= state->dynamic.viewport.count &&
4006 !memcmp(state->dynamic.viewport.viewports + firstViewport,
4007 pViewports, viewportCount * sizeof(*pViewports))) {
4008 return;
4009 }
4010
4011 if (state->dynamic.viewport.count < total_count)
4012 state->dynamic.viewport.count = total_count;
4013
4014 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
4015 viewportCount * sizeof(*pViewports));
4016
4017 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
4018 }
4019
4020 void radv_CmdSetScissor(
4021 VkCommandBuffer commandBuffer,
4022 uint32_t firstScissor,
4023 uint32_t scissorCount,
4024 const VkRect2D* pScissors)
4025 {
4026 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4027 struct radv_cmd_state *state = &cmd_buffer->state;
4028 ASSERTED const uint32_t total_count = firstScissor + scissorCount;
4029
4030 assert(firstScissor < MAX_SCISSORS);
4031 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
4032
4033 if (total_count <= state->dynamic.scissor.count &&
4034 !memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
4035 scissorCount * sizeof(*pScissors))) {
4036 return;
4037 }
4038
4039 if (state->dynamic.scissor.count < total_count)
4040 state->dynamic.scissor.count = total_count;
4041
4042 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
4043 scissorCount * sizeof(*pScissors));
4044
4045 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
4046 }
4047
4048 void radv_CmdSetLineWidth(
4049 VkCommandBuffer commandBuffer,
4050 float lineWidth)
4051 {
4052 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4053
4054 if (cmd_buffer->state.dynamic.line_width == lineWidth)
4055 return;
4056
4057 cmd_buffer->state.dynamic.line_width = lineWidth;
4058 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
4059 }
4060
4061 void radv_CmdSetDepthBias(
4062 VkCommandBuffer commandBuffer,
4063 float depthBiasConstantFactor,
4064 float depthBiasClamp,
4065 float depthBiasSlopeFactor)
4066 {
4067 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4068 struct radv_cmd_state *state = &cmd_buffer->state;
4069
4070 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
4071 state->dynamic.depth_bias.clamp == depthBiasClamp &&
4072 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
4073 return;
4074 }
4075
4076 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
4077 state->dynamic.depth_bias.clamp = depthBiasClamp;
4078 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
4079
4080 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
4081 }
4082
4083 void radv_CmdSetBlendConstants(
4084 VkCommandBuffer commandBuffer,
4085 const float blendConstants[4])
4086 {
4087 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4088 struct radv_cmd_state *state = &cmd_buffer->state;
4089
4090 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
4091 return;
4092
4093 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
4094
4095 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
4096 }
4097
4098 void radv_CmdSetDepthBounds(
4099 VkCommandBuffer commandBuffer,
4100 float minDepthBounds,
4101 float maxDepthBounds)
4102 {
4103 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4104 struct radv_cmd_state *state = &cmd_buffer->state;
4105
4106 if (state->dynamic.depth_bounds.min == minDepthBounds &&
4107 state->dynamic.depth_bounds.max == maxDepthBounds) {
4108 return;
4109 }
4110
4111 state->dynamic.depth_bounds.min = minDepthBounds;
4112 state->dynamic.depth_bounds.max = maxDepthBounds;
4113
4114 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
4115 }
4116
4117 void radv_CmdSetStencilCompareMask(
4118 VkCommandBuffer commandBuffer,
4119 VkStencilFaceFlags faceMask,
4120 uint32_t compareMask)
4121 {
4122 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4123 struct radv_cmd_state *state = &cmd_buffer->state;
4124 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
4125 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
4126
4127 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4128 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4129 return;
4130 }
4131
4132 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4133 state->dynamic.stencil_compare_mask.front = compareMask;
4134 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4135 state->dynamic.stencil_compare_mask.back = compareMask;
4136
4137 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
4138 }
4139
4140 void radv_CmdSetStencilWriteMask(
4141 VkCommandBuffer commandBuffer,
4142 VkStencilFaceFlags faceMask,
4143 uint32_t writeMask)
4144 {
4145 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4146 struct radv_cmd_state *state = &cmd_buffer->state;
4147 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
4148 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
4149
4150 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4151 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4152 return;
4153 }
4154
4155 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4156 state->dynamic.stencil_write_mask.front = writeMask;
4157 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4158 state->dynamic.stencil_write_mask.back = writeMask;
4159
4160 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
4161 }
4162
4163 void radv_CmdSetStencilReference(
4164 VkCommandBuffer commandBuffer,
4165 VkStencilFaceFlags faceMask,
4166 uint32_t reference)
4167 {
4168 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4169 struct radv_cmd_state *state = &cmd_buffer->state;
4170 bool front_same = state->dynamic.stencil_reference.front == reference;
4171 bool back_same = state->dynamic.stencil_reference.back == reference;
4172
4173 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4174 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4175 return;
4176 }
4177
4178 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4179 cmd_buffer->state.dynamic.stencil_reference.front = reference;
4180 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4181 cmd_buffer->state.dynamic.stencil_reference.back = reference;
4182
4183 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
4184 }
4185
4186 void radv_CmdSetDiscardRectangleEXT(
4187 VkCommandBuffer commandBuffer,
4188 uint32_t firstDiscardRectangle,
4189 uint32_t discardRectangleCount,
4190 const VkRect2D* pDiscardRectangles)
4191 {
4192 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4193 struct radv_cmd_state *state = &cmd_buffer->state;
4194 ASSERTED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
4195
4196 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
4197 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
4198
4199 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
4200 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
4201 return;
4202 }
4203
4204 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
4205 pDiscardRectangles, discardRectangleCount);
4206
4207 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
4208 }
4209
4210 void radv_CmdSetSampleLocationsEXT(
4211 VkCommandBuffer commandBuffer,
4212 const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
4213 {
4214 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4215 struct radv_cmd_state *state = &cmd_buffer->state;
4216
4217 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
4218
4219 state->dynamic.sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
4220 state->dynamic.sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
4221 state->dynamic.sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
4222 typed_memcpy(&state->dynamic.sample_location.locations[0],
4223 pSampleLocationsInfo->pSampleLocations,
4224 pSampleLocationsInfo->sampleLocationsCount);
4225
4226 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS;
4227 }
4228
4229 void radv_CmdSetLineStippleEXT(
4230 VkCommandBuffer commandBuffer,
4231 uint32_t lineStippleFactor,
4232 uint16_t lineStipplePattern)
4233 {
4234 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4235 struct radv_cmd_state *state = &cmd_buffer->state;
4236
4237 state->dynamic.line_stipple.factor = lineStippleFactor;
4238 state->dynamic.line_stipple.pattern = lineStipplePattern;
4239
4240 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE;
4241 }
4242
4243 void radv_CmdSetCullModeEXT(
4244 VkCommandBuffer commandBuffer,
4245 VkCullModeFlags cullMode)
4246 {
4247 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4248 struct radv_cmd_state *state = &cmd_buffer->state;
4249
4250 if (state->dynamic.cull_mode == cullMode)
4251 return;
4252
4253 state->dynamic.cull_mode = cullMode;
4254
4255 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_CULL_MODE;
4256 }
4257
4258 void radv_CmdSetFrontFaceEXT(
4259 VkCommandBuffer commandBuffer,
4260 VkFrontFace frontFace)
4261 {
4262 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4263 struct radv_cmd_state *state = &cmd_buffer->state;
4264
4265 if (state->dynamic.front_face == frontFace)
4266 return;
4267
4268 state->dynamic.front_face = frontFace;
4269
4270 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE;
4271 }
4272
4273 void radv_CmdExecuteCommands(
4274 VkCommandBuffer commandBuffer,
4275 uint32_t commandBufferCount,
4276 const VkCommandBuffer* pCmdBuffers)
4277 {
4278 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
4279
4280 assert(commandBufferCount > 0);
4281
4282 /* Emit pending flushes on primary prior to executing secondary */
4283 si_emit_cache_flush(primary);
4284
4285 for (uint32_t i = 0; i < commandBufferCount; i++) {
4286 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
4287
4288 primary->scratch_size_per_wave_needed = MAX2(primary->scratch_size_per_wave_needed,
4289 secondary->scratch_size_per_wave_needed);
4290 primary->scratch_waves_wanted = MAX2(primary->scratch_waves_wanted,
4291 secondary->scratch_waves_wanted);
4292 primary->compute_scratch_size_per_wave_needed = MAX2(primary->compute_scratch_size_per_wave_needed,
4293 secondary->compute_scratch_size_per_wave_needed);
4294 primary->compute_scratch_waves_wanted = MAX2(primary->compute_scratch_waves_wanted,
4295 secondary->compute_scratch_waves_wanted);
4296
4297 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
4298 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
4299 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
4300 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
4301 if (secondary->tess_rings_needed)
4302 primary->tess_rings_needed = true;
4303 if (secondary->sample_positions_needed)
4304 primary->sample_positions_needed = true;
4305 if (secondary->gds_needed)
4306 primary->gds_needed = true;
4307
4308 if (!secondary->state.framebuffer &&
4309 (primary->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)) {
4310 /* Emit the framebuffer state from primary if secondary
4311 * has been recorded without a framebuffer, otherwise
4312 * fast color/depth clears can't work.
4313 */
4314 radv_emit_framebuffer_state(primary);
4315 }
4316
4317 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
4318
4319
4320 /* When the secondary command buffer is compute only we don't
4321 * need to re-emit the current graphics pipeline.
4322 */
4323 if (secondary->state.emitted_pipeline) {
4324 primary->state.emitted_pipeline =
4325 secondary->state.emitted_pipeline;
4326 }
4327
4328 /* When the secondary command buffer is graphics only we don't
4329 * need to re-emit the current compute pipeline.
4330 */
4331 if (secondary->state.emitted_compute_pipeline) {
4332 primary->state.emitted_compute_pipeline =
4333 secondary->state.emitted_compute_pipeline;
4334 }
4335
4336 /* Only re-emit the draw packets when needed. */
4337 if (secondary->state.last_primitive_reset_en != -1) {
4338 primary->state.last_primitive_reset_en =
4339 secondary->state.last_primitive_reset_en;
4340 }
4341
4342 if (secondary->state.last_primitive_reset_index) {
4343 primary->state.last_primitive_reset_index =
4344 secondary->state.last_primitive_reset_index;
4345 }
4346
4347 if (secondary->state.last_ia_multi_vgt_param) {
4348 primary->state.last_ia_multi_vgt_param =
4349 secondary->state.last_ia_multi_vgt_param;
4350 }
4351
4352 primary->state.last_first_instance = secondary->state.last_first_instance;
4353 primary->state.last_num_instances = secondary->state.last_num_instances;
4354 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
4355 primary->state.last_sx_ps_downconvert = secondary->state.last_sx_ps_downconvert;
4356 primary->state.last_sx_blend_opt_epsilon = secondary->state.last_sx_blend_opt_epsilon;
4357 primary->state.last_sx_blend_opt_control = secondary->state.last_sx_blend_opt_control;
4358
4359 if (secondary->state.last_index_type != -1) {
4360 primary->state.last_index_type =
4361 secondary->state.last_index_type;
4362 }
4363 }
4364
4365 /* After executing commands from secondary buffers we have to dirty
4366 * some states.
4367 */
4368 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
4369 RADV_CMD_DIRTY_INDEX_BUFFER |
4370 RADV_CMD_DIRTY_DYNAMIC_ALL;
4371 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
4372 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
4373 }
4374
4375 VkResult radv_CreateCommandPool(
4376 VkDevice _device,
4377 const VkCommandPoolCreateInfo* pCreateInfo,
4378 const VkAllocationCallbacks* pAllocator,
4379 VkCommandPool* pCmdPool)
4380 {
4381 RADV_FROM_HANDLE(radv_device, device, _device);
4382 struct radv_cmd_pool *pool;
4383
4384 pool = vk_alloc2(&device->vk.alloc, pAllocator, sizeof(*pool), 8,
4385 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4386 if (pool == NULL)
4387 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4388
4389 vk_object_base_init(&device->vk, &pool->base,
4390 VK_OBJECT_TYPE_COMMAND_POOL);
4391
4392 if (pAllocator)
4393 pool->alloc = *pAllocator;
4394 else
4395 pool->alloc = device->vk.alloc;
4396
4397 list_inithead(&pool->cmd_buffers);
4398 list_inithead(&pool->free_cmd_buffers);
4399
4400 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
4401
4402 *pCmdPool = radv_cmd_pool_to_handle(pool);
4403
4404 return VK_SUCCESS;
4405
4406 }
4407
4408 void radv_DestroyCommandPool(
4409 VkDevice _device,
4410 VkCommandPool commandPool,
4411 const VkAllocationCallbacks* pAllocator)
4412 {
4413 RADV_FROM_HANDLE(radv_device, device, _device);
4414 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4415
4416 if (!pool)
4417 return;
4418
4419 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4420 &pool->cmd_buffers, pool_link) {
4421 radv_cmd_buffer_destroy(cmd_buffer);
4422 }
4423
4424 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4425 &pool->free_cmd_buffers, pool_link) {
4426 radv_cmd_buffer_destroy(cmd_buffer);
4427 }
4428
4429 vk_object_base_finish(&pool->base);
4430 vk_free2(&device->vk.alloc, pAllocator, pool);
4431 }
4432
4433 VkResult radv_ResetCommandPool(
4434 VkDevice device,
4435 VkCommandPool commandPool,
4436 VkCommandPoolResetFlags flags)
4437 {
4438 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4439 VkResult result;
4440
4441 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
4442 &pool->cmd_buffers, pool_link) {
4443 result = radv_reset_cmd_buffer(cmd_buffer);
4444 if (result != VK_SUCCESS)
4445 return result;
4446 }
4447
4448 return VK_SUCCESS;
4449 }
4450
4451 void radv_TrimCommandPool(
4452 VkDevice device,
4453 VkCommandPool commandPool,
4454 VkCommandPoolTrimFlags flags)
4455 {
4456 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4457
4458 if (!pool)
4459 return;
4460
4461 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4462 &pool->free_cmd_buffers, pool_link) {
4463 radv_cmd_buffer_destroy(cmd_buffer);
4464 }
4465 }
4466
4467 static void
4468 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
4469 uint32_t subpass_id)
4470 {
4471 struct radv_cmd_state *state = &cmd_buffer->state;
4472 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
4473
4474 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
4475 cmd_buffer->cs, 4096);
4476
4477 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
4478
4479 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
4480
4481 radv_describe_barrier_start(cmd_buffer, RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC);
4482
4483 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4484 const uint32_t a = subpass->attachments[i].attachment;
4485 if (a == VK_ATTACHMENT_UNUSED)
4486 continue;
4487
4488 radv_handle_subpass_image_transition(cmd_buffer,
4489 subpass->attachments[i],
4490 true);
4491 }
4492
4493 radv_describe_barrier_end(cmd_buffer);
4494
4495 radv_cmd_buffer_clear_subpass(cmd_buffer);
4496
4497 assert(cmd_buffer->cs->cdw <= cdw_max);
4498 }
4499
4500 static void
4501 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
4502 {
4503 struct radv_cmd_state *state = &cmd_buffer->state;
4504 const struct radv_subpass *subpass = state->subpass;
4505 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
4506
4507 radv_cmd_buffer_resolve_subpass(cmd_buffer);
4508
4509 radv_describe_barrier_start(cmd_buffer, RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC);
4510
4511 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4512 const uint32_t a = subpass->attachments[i].attachment;
4513 if (a == VK_ATTACHMENT_UNUSED)
4514 continue;
4515
4516 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
4517 continue;
4518
4519 VkImageLayout layout = state->pass->attachments[a].final_layout;
4520 VkImageLayout stencil_layout = state->pass->attachments[a].stencil_final_layout;
4521 struct radv_subpass_attachment att = { a, layout, stencil_layout };
4522 radv_handle_subpass_image_transition(cmd_buffer, att, false);
4523 }
4524
4525 radv_describe_barrier_end(cmd_buffer);
4526 }
4527
4528 void
4529 radv_cmd_buffer_begin_render_pass(struct radv_cmd_buffer *cmd_buffer,
4530 const VkRenderPassBeginInfo *pRenderPassBegin)
4531 {
4532 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
4533 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
4534 VkResult result;
4535
4536 cmd_buffer->state.framebuffer = framebuffer;
4537 cmd_buffer->state.pass = pass;
4538 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
4539
4540 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
4541 if (result != VK_SUCCESS)
4542 return;
4543
4544 result = radv_cmd_state_setup_sample_locations(cmd_buffer, pass, pRenderPassBegin);
4545 if (result != VK_SUCCESS)
4546 return;
4547 }
4548
4549 void radv_CmdBeginRenderPass(
4550 VkCommandBuffer commandBuffer,
4551 const VkRenderPassBeginInfo* pRenderPassBegin,
4552 VkSubpassContents contents)
4553 {
4554 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4555
4556 radv_cmd_buffer_begin_render_pass(cmd_buffer, pRenderPassBegin);
4557
4558 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
4559 }
4560
4561 void radv_CmdBeginRenderPass2(
4562 VkCommandBuffer commandBuffer,
4563 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
4564 const VkSubpassBeginInfo* pSubpassBeginInfo)
4565 {
4566 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
4567 pSubpassBeginInfo->contents);
4568 }
4569
4570 void radv_CmdNextSubpass(
4571 VkCommandBuffer commandBuffer,
4572 VkSubpassContents contents)
4573 {
4574 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4575
4576 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
4577 radv_cmd_buffer_end_subpass(cmd_buffer);
4578 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
4579 }
4580
4581 void radv_CmdNextSubpass2(
4582 VkCommandBuffer commandBuffer,
4583 const VkSubpassBeginInfo* pSubpassBeginInfo,
4584 const VkSubpassEndInfo* pSubpassEndInfo)
4585 {
4586 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
4587 }
4588
4589 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
4590 {
4591 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
4592 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
4593 if (!radv_get_shader(pipeline, stage))
4594 continue;
4595
4596 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
4597 if (loc->sgpr_idx == -1)
4598 continue;
4599 uint32_t base_reg = pipeline->user_data_0[stage];
4600 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4601
4602 }
4603 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
4604 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
4605 if (loc->sgpr_idx != -1) {
4606 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
4607 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4608 }
4609 }
4610 }
4611
4612 static void
4613 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4614 uint32_t vertex_count,
4615 bool use_opaque)
4616 {
4617 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
4618 radeon_emit(cmd_buffer->cs, vertex_count);
4619 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
4620 S_0287F0_USE_OPAQUE(use_opaque));
4621 }
4622
4623 static void
4624 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
4625 uint64_t index_va,
4626 uint32_t index_count)
4627 {
4628 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
4629 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
4630 radeon_emit(cmd_buffer->cs, index_va);
4631 radeon_emit(cmd_buffer->cs, index_va >> 32);
4632 radeon_emit(cmd_buffer->cs, index_count);
4633 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
4634 }
4635
4636 static void
4637 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4638 bool indexed,
4639 uint32_t draw_count,
4640 uint64_t count_va,
4641 uint32_t stride)
4642 {
4643 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4644 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
4645 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
4646 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id;
4647 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
4648 bool predicating = cmd_buffer->state.predicating;
4649 assert(base_reg);
4650
4651 /* just reset draw state for vertex data */
4652 cmd_buffer->state.last_first_instance = -1;
4653 cmd_buffer->state.last_num_instances = -1;
4654 cmd_buffer->state.last_vertex_offset = -1;
4655
4656 if (draw_count == 1 && !count_va && !draw_id_enable) {
4657 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
4658 PKT3_DRAW_INDIRECT, 3, predicating));
4659 radeon_emit(cs, 0);
4660 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4661 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4662 radeon_emit(cs, di_src_sel);
4663 } else {
4664 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
4665 PKT3_DRAW_INDIRECT_MULTI,
4666 8, predicating));
4667 radeon_emit(cs, 0);
4668 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4669 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4670 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
4671 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
4672 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
4673 radeon_emit(cs, draw_count); /* count */
4674 radeon_emit(cs, count_va); /* count_addr */
4675 radeon_emit(cs, count_va >> 32);
4676 radeon_emit(cs, stride); /* stride */
4677 radeon_emit(cs, di_src_sel);
4678 }
4679 }
4680
4681 static void
4682 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
4683 const struct radv_draw_info *info)
4684 {
4685 struct radv_cmd_state *state = &cmd_buffer->state;
4686 struct radeon_winsys *ws = cmd_buffer->device->ws;
4687 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4688
4689 if (info->indirect) {
4690 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4691 uint64_t count_va = 0;
4692
4693 va += info->indirect->offset + info->indirect_offset;
4694
4695 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4696
4697 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
4698 radeon_emit(cs, 1);
4699 radeon_emit(cs, va);
4700 radeon_emit(cs, va >> 32);
4701
4702 if (info->count_buffer) {
4703 count_va = radv_buffer_get_va(info->count_buffer->bo);
4704 count_va += info->count_buffer->offset +
4705 info->count_buffer_offset;
4706
4707 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
4708 }
4709
4710 if (!state->subpass->view_mask) {
4711 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4712 info->indexed,
4713 info->count,
4714 count_va,
4715 info->stride);
4716 } else {
4717 unsigned i;
4718 for_each_bit(i, state->subpass->view_mask) {
4719 radv_emit_view_index(cmd_buffer, i);
4720
4721 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4722 info->indexed,
4723 info->count,
4724 count_va,
4725 info->stride);
4726 }
4727 }
4728 } else {
4729 assert(state->pipeline->graphics.vtx_base_sgpr);
4730
4731 if (info->vertex_offset != state->last_vertex_offset ||
4732 info->first_instance != state->last_first_instance) {
4733 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
4734 state->pipeline->graphics.vtx_emit_num);
4735
4736 radeon_emit(cs, info->vertex_offset);
4737 radeon_emit(cs, info->first_instance);
4738 if (state->pipeline->graphics.vtx_emit_num == 3)
4739 radeon_emit(cs, 0);
4740 state->last_first_instance = info->first_instance;
4741 state->last_vertex_offset = info->vertex_offset;
4742 }
4743
4744 if (state->last_num_instances != info->instance_count) {
4745 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
4746 radeon_emit(cs, info->instance_count);
4747 state->last_num_instances = info->instance_count;
4748 }
4749
4750 if (info->indexed) {
4751 int index_size = radv_get_vgt_index_size(state->index_type);
4752 uint64_t index_va;
4753
4754 /* Skip draw calls with 0-sized index buffers. They
4755 * cause a hang on some chips, like Navi10-14.
4756 */
4757 if (!cmd_buffer->state.max_index_count)
4758 return;
4759
4760 index_va = state->index_va;
4761 index_va += info->first_index * index_size;
4762
4763 if (!state->subpass->view_mask) {
4764 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4765 index_va,
4766 info->count);
4767 } else {
4768 unsigned i;
4769 for_each_bit(i, state->subpass->view_mask) {
4770 radv_emit_view_index(cmd_buffer, i);
4771
4772 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4773 index_va,
4774 info->count);
4775 }
4776 }
4777 } else {
4778 if (!state->subpass->view_mask) {
4779 radv_cs_emit_draw_packet(cmd_buffer,
4780 info->count,
4781 !!info->strmout_buffer);
4782 } else {
4783 unsigned i;
4784 for_each_bit(i, state->subpass->view_mask) {
4785 radv_emit_view_index(cmd_buffer, i);
4786
4787 radv_cs_emit_draw_packet(cmd_buffer,
4788 info->count,
4789 !!info->strmout_buffer);
4790 }
4791 }
4792 }
4793 }
4794 }
4795
4796 /*
4797 * Vega and raven have a bug which triggers if there are multiple context
4798 * register contexts active at the same time with different scissor values.
4799 *
4800 * There are two possible workarounds:
4801 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
4802 * there is only ever 1 active set of scissor values at the same time.
4803 *
4804 * 2) Whenever the hardware switches contexts we have to set the scissor
4805 * registers again even if it is a noop. That way the new context gets
4806 * the correct scissor values.
4807 *
4808 * This implements option 2. radv_need_late_scissor_emission needs to
4809 * return true on affected HW if radv_emit_all_graphics_states sets
4810 * any context registers.
4811 */
4812 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
4813 const struct radv_draw_info *info)
4814 {
4815 struct radv_cmd_state *state = &cmd_buffer->state;
4816
4817 if (!cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
4818 return false;
4819
4820 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
4821 return true;
4822
4823 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
4824
4825 /* Index, vertex and streamout buffers don't change context regs, and
4826 * pipeline is already handled.
4827 */
4828 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
4829 RADV_CMD_DIRTY_VERTEX_BUFFER |
4830 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
4831 RADV_CMD_DIRTY_PIPELINE);
4832
4833 if (cmd_buffer->state.dirty & used_states)
4834 return true;
4835
4836 uint32_t primitive_reset_index =
4837 radv_get_primitive_reset_index(cmd_buffer);
4838
4839 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
4840 primitive_reset_index != state->last_primitive_reset_index)
4841 return true;
4842
4843 return false;
4844 }
4845
4846 static void
4847 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
4848 const struct radv_draw_info *info)
4849 {
4850 bool late_scissor_emission;
4851
4852 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
4853 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
4854 radv_emit_rbplus_state(cmd_buffer);
4855
4856 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
4857 radv_emit_graphics_pipeline(cmd_buffer);
4858
4859 /* This should be before the cmd_buffer->state.dirty is cleared
4860 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4861 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4862 late_scissor_emission =
4863 radv_need_late_scissor_emission(cmd_buffer, info);
4864
4865 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
4866 radv_emit_framebuffer_state(cmd_buffer);
4867
4868 if (info->indexed) {
4869 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
4870 radv_emit_index_buffer(cmd_buffer, info->indirect);
4871 } else {
4872 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4873 * so the state must be re-emitted before the next indexed
4874 * draw.
4875 */
4876 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
4877 cmd_buffer->state.last_index_type = -1;
4878 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
4879 }
4880 }
4881
4882 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
4883
4884 radv_emit_draw_registers(cmd_buffer, info);
4885
4886 if (late_scissor_emission)
4887 radv_emit_scissor(cmd_buffer);
4888 }
4889
4890 static void
4891 radv_draw(struct radv_cmd_buffer *cmd_buffer,
4892 const struct radv_draw_info *info)
4893 {
4894 struct radeon_info *rad_info =
4895 &cmd_buffer->device->physical_device->rad_info;
4896 bool has_prefetch =
4897 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4898 bool pipeline_is_dirty =
4899 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
4900 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
4901
4902 ASSERTED unsigned cdw_max =
4903 radeon_check_space(cmd_buffer->device->ws,
4904 cmd_buffer->cs, 4096);
4905
4906 if (likely(!info->indirect)) {
4907 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4908 * no workaround for indirect draws, but we can at least skip
4909 * direct draws.
4910 */
4911 if (unlikely(!info->instance_count))
4912 return;
4913
4914 /* Handle count == 0. */
4915 if (unlikely(!info->count && !info->strmout_buffer))
4916 return;
4917 }
4918
4919 radv_describe_draw(cmd_buffer);
4920
4921 /* Use optimal packet order based on whether we need to sync the
4922 * pipeline.
4923 */
4924 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4925 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4926 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4927 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4928 /* If we have to wait for idle, set all states first, so that
4929 * all SET packets are processed in parallel with previous draw
4930 * calls. Then upload descriptors, set shader pointers, and
4931 * draw, and prefetch at the end. This ensures that the time
4932 * the CUs are idle is very short. (there are only SET_SH
4933 * packets between the wait and the draw)
4934 */
4935 radv_emit_all_graphics_states(cmd_buffer, info);
4936 si_emit_cache_flush(cmd_buffer);
4937 /* <-- CUs are idle here --> */
4938
4939 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4940
4941 radv_emit_draw_packets(cmd_buffer, info);
4942 /* <-- CUs are busy here --> */
4943
4944 /* Start prefetches after the draw has been started. Both will
4945 * run in parallel, but starting the draw first is more
4946 * important.
4947 */
4948 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4949 radv_emit_prefetch_L2(cmd_buffer,
4950 cmd_buffer->state.pipeline, false);
4951 }
4952 } else {
4953 /* If we don't wait for idle, start prefetches first, then set
4954 * states, and draw at the end.
4955 */
4956 si_emit_cache_flush(cmd_buffer);
4957
4958 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4959 /* Only prefetch the vertex shader and VBO descriptors
4960 * in order to start the draw as soon as possible.
4961 */
4962 radv_emit_prefetch_L2(cmd_buffer,
4963 cmd_buffer->state.pipeline, true);
4964 }
4965
4966 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4967
4968 radv_emit_all_graphics_states(cmd_buffer, info);
4969 radv_emit_draw_packets(cmd_buffer, info);
4970
4971 /* Prefetch the remaining shaders after the draw has been
4972 * started.
4973 */
4974 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4975 radv_emit_prefetch_L2(cmd_buffer,
4976 cmd_buffer->state.pipeline, false);
4977 }
4978 }
4979
4980 /* Workaround for a VGT hang when streamout is enabled.
4981 * It must be done after drawing.
4982 */
4983 if (cmd_buffer->state.streamout.streamout_enabled &&
4984 (rad_info->family == CHIP_HAWAII ||
4985 rad_info->family == CHIP_TONGA ||
4986 rad_info->family == CHIP_FIJI)) {
4987 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
4988 }
4989
4990 assert(cmd_buffer->cs->cdw <= cdw_max);
4991 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
4992 }
4993
4994 void radv_CmdDraw(
4995 VkCommandBuffer commandBuffer,
4996 uint32_t vertexCount,
4997 uint32_t instanceCount,
4998 uint32_t firstVertex,
4999 uint32_t firstInstance)
5000 {
5001 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5002 struct radv_draw_info info = {};
5003
5004 info.count = vertexCount;
5005 info.instance_count = instanceCount;
5006 info.first_instance = firstInstance;
5007 info.vertex_offset = firstVertex;
5008
5009 radv_draw(cmd_buffer, &info);
5010 }
5011
5012 void radv_CmdDrawIndexed(
5013 VkCommandBuffer commandBuffer,
5014 uint32_t indexCount,
5015 uint32_t instanceCount,
5016 uint32_t firstIndex,
5017 int32_t vertexOffset,
5018 uint32_t firstInstance)
5019 {
5020 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5021 struct radv_draw_info info = {};
5022
5023 info.indexed = true;
5024 info.count = indexCount;
5025 info.instance_count = instanceCount;
5026 info.first_index = firstIndex;
5027 info.vertex_offset = vertexOffset;
5028 info.first_instance = firstInstance;
5029
5030 radv_draw(cmd_buffer, &info);
5031 }
5032
5033 void radv_CmdDrawIndirect(
5034 VkCommandBuffer commandBuffer,
5035 VkBuffer _buffer,
5036 VkDeviceSize offset,
5037 uint32_t drawCount,
5038 uint32_t stride)
5039 {
5040 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5041 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5042 struct radv_draw_info info = {};
5043
5044 info.count = drawCount;
5045 info.indirect = buffer;
5046 info.indirect_offset = offset;
5047 info.stride = stride;
5048
5049 radv_draw(cmd_buffer, &info);
5050 }
5051
5052 void radv_CmdDrawIndexedIndirect(
5053 VkCommandBuffer commandBuffer,
5054 VkBuffer _buffer,
5055 VkDeviceSize offset,
5056 uint32_t drawCount,
5057 uint32_t stride)
5058 {
5059 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5060 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5061 struct radv_draw_info info = {};
5062
5063 info.indexed = true;
5064 info.count = drawCount;
5065 info.indirect = buffer;
5066 info.indirect_offset = offset;
5067 info.stride = stride;
5068
5069 radv_draw(cmd_buffer, &info);
5070 }
5071
5072 void radv_CmdDrawIndirectCount(
5073 VkCommandBuffer commandBuffer,
5074 VkBuffer _buffer,
5075 VkDeviceSize offset,
5076 VkBuffer _countBuffer,
5077 VkDeviceSize countBufferOffset,
5078 uint32_t maxDrawCount,
5079 uint32_t stride)
5080 {
5081 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5082 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5083 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
5084 struct radv_draw_info info = {};
5085
5086 info.count = maxDrawCount;
5087 info.indirect = buffer;
5088 info.indirect_offset = offset;
5089 info.count_buffer = count_buffer;
5090 info.count_buffer_offset = countBufferOffset;
5091 info.stride = stride;
5092
5093 radv_draw(cmd_buffer, &info);
5094 }
5095
5096 void radv_CmdDrawIndexedIndirectCount(
5097 VkCommandBuffer commandBuffer,
5098 VkBuffer _buffer,
5099 VkDeviceSize offset,
5100 VkBuffer _countBuffer,
5101 VkDeviceSize countBufferOffset,
5102 uint32_t maxDrawCount,
5103 uint32_t stride)
5104 {
5105 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5106 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5107 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
5108 struct radv_draw_info info = {};
5109
5110 info.indexed = true;
5111 info.count = maxDrawCount;
5112 info.indirect = buffer;
5113 info.indirect_offset = offset;
5114 info.count_buffer = count_buffer;
5115 info.count_buffer_offset = countBufferOffset;
5116 info.stride = stride;
5117
5118 radv_draw(cmd_buffer, &info);
5119 }
5120
5121 struct radv_dispatch_info {
5122 /**
5123 * Determine the layout of the grid (in block units) to be used.
5124 */
5125 uint32_t blocks[3];
5126
5127 /**
5128 * A starting offset for the grid. If unaligned is set, the offset
5129 * must still be aligned.
5130 */
5131 uint32_t offsets[3];
5132 /**
5133 * Whether it's an unaligned compute dispatch.
5134 */
5135 bool unaligned;
5136
5137 /**
5138 * Indirect compute parameters resource.
5139 */
5140 struct radv_buffer *indirect;
5141 uint64_t indirect_offset;
5142 };
5143
5144 static void
5145 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
5146 const struct radv_dispatch_info *info)
5147 {
5148 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
5149 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
5150 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
5151 struct radeon_winsys *ws = cmd_buffer->device->ws;
5152 bool predicating = cmd_buffer->state.predicating;
5153 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5154 struct radv_userdata_info *loc;
5155
5156 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
5157 AC_UD_CS_GRID_SIZE);
5158
5159 ASSERTED unsigned cdw_max = radeon_check_space(ws, cs, 25);
5160
5161 if (compute_shader->info.wave_size == 32) {
5162 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
5163 dispatch_initiator |= S_00B800_CS_W32_EN(1);
5164 }
5165
5166 if (info->indirect) {
5167 uint64_t va = radv_buffer_get_va(info->indirect->bo);
5168
5169 va += info->indirect->offset + info->indirect_offset;
5170
5171 radv_cs_add_buffer(ws, cs, info->indirect->bo);
5172
5173 if (loc->sgpr_idx != -1) {
5174 for (unsigned i = 0; i < 3; ++i) {
5175 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5176 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5177 COPY_DATA_DST_SEL(COPY_DATA_REG));
5178 radeon_emit(cs, (va + 4 * i));
5179 radeon_emit(cs, (va + 4 * i) >> 32);
5180 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
5181 + loc->sgpr_idx * 4) >> 2) + i);
5182 radeon_emit(cs, 0);
5183 }
5184 }
5185
5186 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
5187 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
5188 PKT3_SHADER_TYPE_S(1));
5189 radeon_emit(cs, va);
5190 radeon_emit(cs, va >> 32);
5191 radeon_emit(cs, dispatch_initiator);
5192 } else {
5193 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
5194 PKT3_SHADER_TYPE_S(1));
5195 radeon_emit(cs, 1);
5196 radeon_emit(cs, va);
5197 radeon_emit(cs, va >> 32);
5198
5199 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
5200 PKT3_SHADER_TYPE_S(1));
5201 radeon_emit(cs, 0);
5202 radeon_emit(cs, dispatch_initiator);
5203 }
5204 } else {
5205 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
5206 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
5207
5208 if (info->unaligned) {
5209 unsigned *cs_block_size = compute_shader->info.cs.block_size;
5210 unsigned remainder[3];
5211
5212 /* If aligned, these should be an entire block size,
5213 * not 0.
5214 */
5215 remainder[0] = blocks[0] + cs_block_size[0] -
5216 align_u32_npot(blocks[0], cs_block_size[0]);
5217 remainder[1] = blocks[1] + cs_block_size[1] -
5218 align_u32_npot(blocks[1], cs_block_size[1]);
5219 remainder[2] = blocks[2] + cs_block_size[2] -
5220 align_u32_npot(blocks[2], cs_block_size[2]);
5221
5222 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
5223 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
5224 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
5225
5226 for(unsigned i = 0; i < 3; ++i) {
5227 assert(offsets[i] % cs_block_size[i] == 0);
5228 offsets[i] /= cs_block_size[i];
5229 }
5230
5231 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
5232 radeon_emit(cs,
5233 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
5234 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
5235 radeon_emit(cs,
5236 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
5237 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
5238 radeon_emit(cs,
5239 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
5240 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
5241
5242 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
5243 }
5244
5245 if (loc->sgpr_idx != -1) {
5246 assert(loc->num_sgprs == 3);
5247
5248 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
5249 loc->sgpr_idx * 4, 3);
5250 radeon_emit(cs, blocks[0]);
5251 radeon_emit(cs, blocks[1]);
5252 radeon_emit(cs, blocks[2]);
5253 }
5254
5255 if (offsets[0] || offsets[1] || offsets[2]) {
5256 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
5257 radeon_emit(cs, offsets[0]);
5258 radeon_emit(cs, offsets[1]);
5259 radeon_emit(cs, offsets[2]);
5260
5261 /* The blocks in the packet are not counts but end values. */
5262 for (unsigned i = 0; i < 3; ++i)
5263 blocks[i] += offsets[i];
5264 } else {
5265 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
5266 }
5267
5268 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
5269 PKT3_SHADER_TYPE_S(1));
5270 radeon_emit(cs, blocks[0]);
5271 radeon_emit(cs, blocks[1]);
5272 radeon_emit(cs, blocks[2]);
5273 radeon_emit(cs, dispatch_initiator);
5274 }
5275
5276 assert(cmd_buffer->cs->cdw <= cdw_max);
5277 }
5278
5279 static void
5280 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
5281 {
5282 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
5283 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
5284 }
5285
5286 static void
5287 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
5288 const struct radv_dispatch_info *info)
5289 {
5290 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
5291 bool has_prefetch =
5292 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
5293 bool pipeline_is_dirty = pipeline &&
5294 pipeline != cmd_buffer->state.emitted_compute_pipeline;
5295
5296 radv_describe_dispatch(cmd_buffer, 8, 8, 8);
5297
5298 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5299 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5300 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
5301 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
5302 /* If we have to wait for idle, set all states first, so that
5303 * all SET packets are processed in parallel with previous draw
5304 * calls. Then upload descriptors, set shader pointers, and
5305 * dispatch, and prefetch at the end. This ensures that the
5306 * time the CUs are idle is very short. (there are only SET_SH
5307 * packets between the wait and the draw)
5308 */
5309 radv_emit_compute_pipeline(cmd_buffer);
5310 si_emit_cache_flush(cmd_buffer);
5311 /* <-- CUs are idle here --> */
5312
5313 radv_upload_compute_shader_descriptors(cmd_buffer);
5314
5315 radv_emit_dispatch_packets(cmd_buffer, info);
5316 /* <-- CUs are busy here --> */
5317
5318 /* Start prefetches after the dispatch has been started. Both
5319 * will run in parallel, but starting the dispatch first is
5320 * more important.
5321 */
5322 if (has_prefetch && pipeline_is_dirty) {
5323 radv_emit_shader_prefetch(cmd_buffer,
5324 pipeline->shaders[MESA_SHADER_COMPUTE]);
5325 }
5326 } else {
5327 /* If we don't wait for idle, start prefetches first, then set
5328 * states, and dispatch at the end.
5329 */
5330 si_emit_cache_flush(cmd_buffer);
5331
5332 if (has_prefetch && pipeline_is_dirty) {
5333 radv_emit_shader_prefetch(cmd_buffer,
5334 pipeline->shaders[MESA_SHADER_COMPUTE]);
5335 }
5336
5337 radv_upload_compute_shader_descriptors(cmd_buffer);
5338
5339 radv_emit_compute_pipeline(cmd_buffer);
5340 radv_emit_dispatch_packets(cmd_buffer, info);
5341 }
5342
5343 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
5344 }
5345
5346 void radv_CmdDispatchBase(
5347 VkCommandBuffer commandBuffer,
5348 uint32_t base_x,
5349 uint32_t base_y,
5350 uint32_t base_z,
5351 uint32_t x,
5352 uint32_t y,
5353 uint32_t z)
5354 {
5355 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5356 struct radv_dispatch_info info = {};
5357
5358 info.blocks[0] = x;
5359 info.blocks[1] = y;
5360 info.blocks[2] = z;
5361
5362 info.offsets[0] = base_x;
5363 info.offsets[1] = base_y;
5364 info.offsets[2] = base_z;
5365 radv_dispatch(cmd_buffer, &info);
5366 }
5367
5368 void radv_CmdDispatch(
5369 VkCommandBuffer commandBuffer,
5370 uint32_t x,
5371 uint32_t y,
5372 uint32_t z)
5373 {
5374 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
5375 }
5376
5377 void radv_CmdDispatchIndirect(
5378 VkCommandBuffer commandBuffer,
5379 VkBuffer _buffer,
5380 VkDeviceSize offset)
5381 {
5382 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5383 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5384 struct radv_dispatch_info info = {};
5385
5386 info.indirect = buffer;
5387 info.indirect_offset = offset;
5388
5389 radv_dispatch(cmd_buffer, &info);
5390 }
5391
5392 void radv_unaligned_dispatch(
5393 struct radv_cmd_buffer *cmd_buffer,
5394 uint32_t x,
5395 uint32_t y,
5396 uint32_t z)
5397 {
5398 struct radv_dispatch_info info = {};
5399
5400 info.blocks[0] = x;
5401 info.blocks[1] = y;
5402 info.blocks[2] = z;
5403 info.unaligned = 1;
5404
5405 radv_dispatch(cmd_buffer, &info);
5406 }
5407
5408 void
5409 radv_cmd_buffer_end_render_pass(struct radv_cmd_buffer *cmd_buffer)
5410 {
5411 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
5412 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
5413
5414 cmd_buffer->state.pass = NULL;
5415 cmd_buffer->state.subpass = NULL;
5416 cmd_buffer->state.attachments = NULL;
5417 cmd_buffer->state.framebuffer = NULL;
5418 cmd_buffer->state.subpass_sample_locs = NULL;
5419 }
5420
5421 void radv_CmdEndRenderPass(
5422 VkCommandBuffer commandBuffer)
5423 {
5424 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5425
5426 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
5427
5428 radv_cmd_buffer_end_subpass(cmd_buffer);
5429
5430 radv_cmd_buffer_end_render_pass(cmd_buffer);
5431 }
5432
5433 void radv_CmdEndRenderPass2(
5434 VkCommandBuffer commandBuffer,
5435 const VkSubpassEndInfo* pSubpassEndInfo)
5436 {
5437 radv_CmdEndRenderPass(commandBuffer);
5438 }
5439
5440 /*
5441 * For HTILE we have the following interesting clear words:
5442 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
5443 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
5444 * 0xfffffff0: Clear depth to 1.0
5445 * 0x00000000: Clear depth to 0.0
5446 */
5447 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
5448 struct radv_image *image,
5449 const VkImageSubresourceRange *range)
5450 {
5451 assert(range->baseMipLevel == 0);
5452 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
5453 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
5454 struct radv_cmd_state *state = &cmd_buffer->state;
5455 uint32_t htile_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
5456 VkClearDepthStencilValue value = {};
5457 struct radv_barrier_data barrier = {};
5458
5459 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5460 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5461
5462 barrier.layout_transitions.init_mask_ram = 1;
5463 radv_describe_layout_transition(cmd_buffer, &barrier);
5464
5465 state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, htile_value);
5466
5467 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5468
5469 if (vk_format_is_stencil(image->vk_format))
5470 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
5471
5472 radv_set_ds_clear_metadata(cmd_buffer, image, range, value, aspects);
5473
5474 if (radv_image_is_tc_compat_htile(image)) {
5475 /* Initialize the TC-compat metada value to 0 because by
5476 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
5477 * need have to conditionally update its value when performing
5478 * a fast depth clear.
5479 */
5480 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, range, 0);
5481 }
5482 }
5483
5484 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
5485 struct radv_image *image,
5486 VkImageLayout src_layout,
5487 bool src_render_loop,
5488 VkImageLayout dst_layout,
5489 bool dst_render_loop,
5490 unsigned src_queue_mask,
5491 unsigned dst_queue_mask,
5492 const VkImageSubresourceRange *range,
5493 struct radv_sample_locations_state *sample_locs)
5494 {
5495 if (!radv_image_has_htile(image))
5496 return;
5497
5498 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5499 radv_initialize_htile(cmd_buffer, image, range);
5500 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5501 radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5502 radv_initialize_htile(cmd_buffer, image, range);
5503 } else if (radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5504 !radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5505 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5506 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5507
5508 radv_decompress_depth_stencil(cmd_buffer, image, range,
5509 sample_locs);
5510
5511 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5512 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5513 }
5514 }
5515
5516 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
5517 struct radv_image *image,
5518 const VkImageSubresourceRange *range,
5519 uint32_t value)
5520 {
5521 struct radv_cmd_state *state = &cmd_buffer->state;
5522 struct radv_barrier_data barrier = {};
5523
5524 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5525 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5526
5527 barrier.layout_transitions.init_mask_ram = 1;
5528 radv_describe_layout_transition(cmd_buffer, &barrier);
5529
5530 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, range, value);
5531
5532 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5533 }
5534
5535 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
5536 struct radv_image *image,
5537 const VkImageSubresourceRange *range)
5538 {
5539 struct radv_cmd_state *state = &cmd_buffer->state;
5540 static const uint32_t fmask_clear_values[4] = {
5541 0x00000000,
5542 0x02020202,
5543 0xE4E4E4E4,
5544 0x76543210
5545 };
5546 uint32_t log2_samples = util_logbase2(image->info.samples);
5547 uint32_t value = fmask_clear_values[log2_samples];
5548 struct radv_barrier_data barrier = {};
5549
5550 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5551 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5552
5553 barrier.layout_transitions.init_mask_ram = 1;
5554 radv_describe_layout_transition(cmd_buffer, &barrier);
5555
5556 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, range, value);
5557
5558 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5559 }
5560
5561 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
5562 struct radv_image *image,
5563 const VkImageSubresourceRange *range, uint32_t value)
5564 {
5565 struct radv_cmd_state *state = &cmd_buffer->state;
5566 struct radv_barrier_data barrier = {};
5567 unsigned size = 0;
5568
5569 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5570 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5571
5572 barrier.layout_transitions.init_mask_ram = 1;
5573 radv_describe_layout_transition(cmd_buffer, &barrier);
5574
5575 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
5576
5577 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) {
5578 /* When DCC is enabled with mipmaps, some levels might not
5579 * support fast clears and we have to initialize them as "fully
5580 * expanded".
5581 */
5582 /* Compute the size of all fast clearable DCC levels. */
5583 for (unsigned i = 0; i < image->planes[0].surface.num_dcc_levels; i++) {
5584 struct legacy_surf_level *surf_level =
5585 &image->planes[0].surface.u.legacy.level[i];
5586 unsigned dcc_fast_clear_size =
5587 surf_level->dcc_slice_fast_clear_size * image->info.array_size;
5588
5589 if (!dcc_fast_clear_size)
5590 break;
5591
5592 size = surf_level->dcc_offset + dcc_fast_clear_size;
5593 }
5594
5595 /* Initialize the mipmap levels without DCC. */
5596 if (size != image->planes[0].surface.dcc_size) {
5597 state->flush_bits |=
5598 radv_fill_buffer(cmd_buffer, image->bo,
5599 image->offset + image->planes[0].surface.dcc_offset + size,
5600 image->planes[0].surface.dcc_size - size,
5601 0xffffffff);
5602 }
5603 }
5604
5605 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5606 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5607 }
5608
5609 /**
5610 * Initialize DCC/FMASK/CMASK metadata for a color image.
5611 */
5612 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
5613 struct radv_image *image,
5614 VkImageLayout src_layout,
5615 bool src_render_loop,
5616 VkImageLayout dst_layout,
5617 bool dst_render_loop,
5618 unsigned src_queue_mask,
5619 unsigned dst_queue_mask,
5620 const VkImageSubresourceRange *range)
5621 {
5622 if (radv_image_has_cmask(image)) {
5623 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5624
5625 /* TODO: clarify this. */
5626 if (radv_image_has_fmask(image)) {
5627 value = 0xccccccccu;
5628 }
5629
5630 radv_initialise_cmask(cmd_buffer, image, range, value);
5631 }
5632
5633 if (radv_image_has_fmask(image)) {
5634 radv_initialize_fmask(cmd_buffer, image, range);
5635 }
5636
5637 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5638 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5639 bool need_decompress_pass = false;
5640
5641 if (radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout,
5642 dst_render_loop,
5643 dst_queue_mask)) {
5644 value = 0x20202020u;
5645 need_decompress_pass = true;
5646 }
5647
5648 radv_initialize_dcc(cmd_buffer, image, range, value);
5649
5650 radv_update_fce_metadata(cmd_buffer, image, range,
5651 need_decompress_pass);
5652 }
5653
5654 if (radv_image_has_cmask(image) ||
5655 radv_dcc_enabled(image, range->baseMipLevel)) {
5656 uint32_t color_values[2] = {};
5657 radv_set_color_clear_metadata(cmd_buffer, image, range,
5658 color_values);
5659 }
5660 }
5661
5662 /**
5663 * Handle color image transitions for DCC/FMASK/CMASK.
5664 */
5665 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
5666 struct radv_image *image,
5667 VkImageLayout src_layout,
5668 bool src_render_loop,
5669 VkImageLayout dst_layout,
5670 bool dst_render_loop,
5671 unsigned src_queue_mask,
5672 unsigned dst_queue_mask,
5673 const VkImageSubresourceRange *range)
5674 {
5675 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5676 radv_init_color_image_metadata(cmd_buffer, image,
5677 src_layout, src_render_loop,
5678 dst_layout, dst_render_loop,
5679 src_queue_mask, dst_queue_mask,
5680 range);
5681 return;
5682 }
5683
5684 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5685 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
5686 radv_initialize_dcc(cmd_buffer, image, range, 0xffffffffu);
5687 } else if (radv_layout_dcc_compressed(cmd_buffer->device, image, src_layout, src_render_loop, src_queue_mask) &&
5688 !radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout, dst_render_loop, dst_queue_mask)) {
5689 radv_decompress_dcc(cmd_buffer, image, range);
5690 } else if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
5691 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5692 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5693 }
5694 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
5695 bool fce_eliminate = false, fmask_expand = false;
5696
5697 if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
5698 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5699 fce_eliminate = true;
5700 }
5701
5702 if (radv_image_has_fmask(image)) {
5703 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
5704 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
5705 /* A FMASK decompress is required before doing
5706 * a MSAA decompress using FMASK.
5707 */
5708 fmask_expand = true;
5709 }
5710 }
5711
5712 if (fce_eliminate || fmask_expand)
5713 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5714
5715 if (fmask_expand) {
5716 struct radv_barrier_data barrier = {};
5717 barrier.layout_transitions.fmask_color_expand = 1;
5718 radv_describe_layout_transition(cmd_buffer, &barrier);
5719
5720 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
5721 }
5722 }
5723 }
5724
5725 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
5726 struct radv_image *image,
5727 VkImageLayout src_layout,
5728 bool src_render_loop,
5729 VkImageLayout dst_layout,
5730 bool dst_render_loop,
5731 uint32_t src_family,
5732 uint32_t dst_family,
5733 const VkImageSubresourceRange *range,
5734 struct radv_sample_locations_state *sample_locs)
5735 {
5736 if (image->exclusive && src_family != dst_family) {
5737 /* This is an acquire or a release operation and there will be
5738 * a corresponding release/acquire. Do the transition in the
5739 * most flexible queue. */
5740
5741 assert(src_family == cmd_buffer->queue_family_index ||
5742 dst_family == cmd_buffer->queue_family_index);
5743
5744 if (src_family == VK_QUEUE_FAMILY_EXTERNAL ||
5745 src_family == VK_QUEUE_FAMILY_FOREIGN_EXT)
5746 return;
5747
5748 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
5749 return;
5750
5751 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
5752 (src_family == RADV_QUEUE_GENERAL ||
5753 dst_family == RADV_QUEUE_GENERAL))
5754 return;
5755 }
5756
5757 if (src_layout == dst_layout)
5758 return;
5759
5760 unsigned src_queue_mask =
5761 radv_image_queue_family_mask(image, src_family,
5762 cmd_buffer->queue_family_index);
5763 unsigned dst_queue_mask =
5764 radv_image_queue_family_mask(image, dst_family,
5765 cmd_buffer->queue_family_index);
5766
5767 if (vk_format_is_depth(image->vk_format)) {
5768 radv_handle_depth_image_transition(cmd_buffer, image,
5769 src_layout, src_render_loop,
5770 dst_layout, dst_render_loop,
5771 src_queue_mask, dst_queue_mask,
5772 range, sample_locs);
5773 } else {
5774 radv_handle_color_image_transition(cmd_buffer, image,
5775 src_layout, src_render_loop,
5776 dst_layout, dst_render_loop,
5777 src_queue_mask, dst_queue_mask,
5778 range);
5779 }
5780 }
5781
5782 struct radv_barrier_info {
5783 enum rgp_barrier_reason reason;
5784 uint32_t eventCount;
5785 const VkEvent *pEvents;
5786 VkPipelineStageFlags srcStageMask;
5787 VkPipelineStageFlags dstStageMask;
5788 };
5789
5790 static void
5791 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
5792 uint32_t memoryBarrierCount,
5793 const VkMemoryBarrier *pMemoryBarriers,
5794 uint32_t bufferMemoryBarrierCount,
5795 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
5796 uint32_t imageMemoryBarrierCount,
5797 const VkImageMemoryBarrier *pImageMemoryBarriers,
5798 const struct radv_barrier_info *info)
5799 {
5800 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5801 enum radv_cmd_flush_bits src_flush_bits = 0;
5802 enum radv_cmd_flush_bits dst_flush_bits = 0;
5803
5804 radv_describe_barrier_start(cmd_buffer, info->reason);
5805
5806 for (unsigned i = 0; i < info->eventCount; ++i) {
5807 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
5808 uint64_t va = radv_buffer_get_va(event->bo);
5809
5810 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5811
5812 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
5813
5814 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
5815 assert(cmd_buffer->cs->cdw <= cdw_max);
5816 }
5817
5818 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
5819 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
5820 NULL);
5821 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
5822 NULL);
5823 }
5824
5825 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
5826 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
5827 NULL);
5828 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
5829 NULL);
5830 }
5831
5832 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5833 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5834
5835 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
5836 image);
5837 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
5838 image);
5839 }
5840
5841 /* The Vulkan spec 1.1.98 says:
5842 *
5843 * "An execution dependency with only
5844 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
5845 * will only prevent that stage from executing in subsequently
5846 * submitted commands. As this stage does not perform any actual
5847 * execution, this is not observable - in effect, it does not delay
5848 * processing of subsequent commands. Similarly an execution dependency
5849 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
5850 * will effectively not wait for any prior commands to complete."
5851 */
5852 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
5853 radv_stage_flush(cmd_buffer, info->srcStageMask);
5854 cmd_buffer->state.flush_bits |= src_flush_bits;
5855
5856 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5857 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5858
5859 const struct VkSampleLocationsInfoEXT *sample_locs_info =
5860 vk_find_struct_const(pImageMemoryBarriers[i].pNext,
5861 SAMPLE_LOCATIONS_INFO_EXT);
5862 struct radv_sample_locations_state sample_locations = {};
5863
5864 if (sample_locs_info) {
5865 assert(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
5866 sample_locations.per_pixel = sample_locs_info->sampleLocationsPerPixel;
5867 sample_locations.grid_size = sample_locs_info->sampleLocationGridSize;
5868 sample_locations.count = sample_locs_info->sampleLocationsCount;
5869 typed_memcpy(&sample_locations.locations[0],
5870 sample_locs_info->pSampleLocations,
5871 sample_locs_info->sampleLocationsCount);
5872 }
5873
5874 radv_handle_image_transition(cmd_buffer, image,
5875 pImageMemoryBarriers[i].oldLayout,
5876 false, /* Outside of a renderpass we are never in a renderloop */
5877 pImageMemoryBarriers[i].newLayout,
5878 false, /* Outside of a renderpass we are never in a renderloop */
5879 pImageMemoryBarriers[i].srcQueueFamilyIndex,
5880 pImageMemoryBarriers[i].dstQueueFamilyIndex,
5881 &pImageMemoryBarriers[i].subresourceRange,
5882 sample_locs_info ? &sample_locations : NULL);
5883 }
5884
5885 /* Make sure CP DMA is idle because the driver might have performed a
5886 * DMA operation for copying or filling buffers/images.
5887 */
5888 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5889 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5890 si_cp_dma_wait_for_idle(cmd_buffer);
5891
5892 cmd_buffer->state.flush_bits |= dst_flush_bits;
5893
5894 radv_describe_barrier_end(cmd_buffer);
5895 }
5896
5897 void radv_CmdPipelineBarrier(
5898 VkCommandBuffer commandBuffer,
5899 VkPipelineStageFlags srcStageMask,
5900 VkPipelineStageFlags destStageMask,
5901 VkBool32 byRegion,
5902 uint32_t memoryBarrierCount,
5903 const VkMemoryBarrier* pMemoryBarriers,
5904 uint32_t bufferMemoryBarrierCount,
5905 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5906 uint32_t imageMemoryBarrierCount,
5907 const VkImageMemoryBarrier* pImageMemoryBarriers)
5908 {
5909 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5910 struct radv_barrier_info info;
5911
5912 info.reason = RGP_BARRIER_EXTERNAL_CMD_PIPELINE_BARRIER;
5913 info.eventCount = 0;
5914 info.pEvents = NULL;
5915 info.srcStageMask = srcStageMask;
5916 info.dstStageMask = destStageMask;
5917
5918 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5919 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5920 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5921 }
5922
5923
5924 static void write_event(struct radv_cmd_buffer *cmd_buffer,
5925 struct radv_event *event,
5926 VkPipelineStageFlags stageMask,
5927 unsigned value)
5928 {
5929 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5930 uint64_t va = radv_buffer_get_va(event->bo);
5931
5932 si_emit_cache_flush(cmd_buffer);
5933
5934 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5935
5936 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 21);
5937
5938 /* Flags that only require a top-of-pipe event. */
5939 VkPipelineStageFlags top_of_pipe_flags =
5940 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
5941
5942 /* Flags that only require a post-index-fetch event. */
5943 VkPipelineStageFlags post_index_fetch_flags =
5944 top_of_pipe_flags |
5945 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
5946 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
5947
5948 /* Make sure CP DMA is idle because the driver might have performed a
5949 * DMA operation for copying or filling buffers/images.
5950 */
5951 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5952 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5953 si_cp_dma_wait_for_idle(cmd_buffer);
5954
5955 /* TODO: Emit EOS events for syncing PS/CS stages. */
5956
5957 if (!(stageMask & ~top_of_pipe_flags)) {
5958 /* Just need to sync the PFP engine. */
5959 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5960 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5961 S_370_WR_CONFIRM(1) |
5962 S_370_ENGINE_SEL(V_370_PFP));
5963 radeon_emit(cs, va);
5964 radeon_emit(cs, va >> 32);
5965 radeon_emit(cs, value);
5966 } else if (!(stageMask & ~post_index_fetch_flags)) {
5967 /* Sync ME because PFP reads index and indirect buffers. */
5968 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5969 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5970 S_370_WR_CONFIRM(1) |
5971 S_370_ENGINE_SEL(V_370_ME));
5972 radeon_emit(cs, va);
5973 radeon_emit(cs, va >> 32);
5974 radeon_emit(cs, value);
5975 } else {
5976 /* Otherwise, sync all prior GPU work using an EOP event. */
5977 si_cs_emit_write_event_eop(cs,
5978 cmd_buffer->device->physical_device->rad_info.chip_class,
5979 radv_cmd_buffer_uses_mec(cmd_buffer),
5980 V_028A90_BOTTOM_OF_PIPE_TS, 0,
5981 EOP_DST_SEL_MEM,
5982 EOP_DATA_SEL_VALUE_32BIT, va, value,
5983 cmd_buffer->gfx9_eop_bug_va);
5984 }
5985
5986 assert(cmd_buffer->cs->cdw <= cdw_max);
5987 }
5988
5989 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
5990 VkEvent _event,
5991 VkPipelineStageFlags stageMask)
5992 {
5993 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5994 RADV_FROM_HANDLE(radv_event, event, _event);
5995
5996 write_event(cmd_buffer, event, stageMask, 1);
5997 }
5998
5999 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
6000 VkEvent _event,
6001 VkPipelineStageFlags stageMask)
6002 {
6003 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6004 RADV_FROM_HANDLE(radv_event, event, _event);
6005
6006 write_event(cmd_buffer, event, stageMask, 0);
6007 }
6008
6009 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
6010 uint32_t eventCount,
6011 const VkEvent* pEvents,
6012 VkPipelineStageFlags srcStageMask,
6013 VkPipelineStageFlags dstStageMask,
6014 uint32_t memoryBarrierCount,
6015 const VkMemoryBarrier* pMemoryBarriers,
6016 uint32_t bufferMemoryBarrierCount,
6017 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
6018 uint32_t imageMemoryBarrierCount,
6019 const VkImageMemoryBarrier* pImageMemoryBarriers)
6020 {
6021 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6022 struct radv_barrier_info info;
6023
6024 info.reason = RGP_BARRIER_EXTERNAL_CMD_WAIT_EVENTS;
6025 info.eventCount = eventCount;
6026 info.pEvents = pEvents;
6027 info.srcStageMask = 0;
6028
6029 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
6030 bufferMemoryBarrierCount, pBufferMemoryBarriers,
6031 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
6032 }
6033
6034
6035 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
6036 uint32_t deviceMask)
6037 {
6038 /* No-op */
6039 }
6040
6041 /* VK_EXT_conditional_rendering */
6042 void radv_CmdBeginConditionalRenderingEXT(
6043 VkCommandBuffer commandBuffer,
6044 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
6045 {
6046 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6047 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
6048 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6049 bool draw_visible = true;
6050 uint64_t pred_value = 0;
6051 uint64_t va, new_va;
6052 unsigned pred_offset;
6053
6054 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
6055
6056 /* By default, if the 32-bit value at offset in buffer memory is zero,
6057 * then the rendering commands are discarded, otherwise they are
6058 * executed as normal. If the inverted flag is set, all commands are
6059 * discarded if the value is non zero.
6060 */
6061 if (pConditionalRenderingBegin->flags &
6062 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
6063 draw_visible = false;
6064 }
6065
6066 si_emit_cache_flush(cmd_buffer);
6067
6068 /* From the Vulkan spec 1.1.107:
6069 *
6070 * "If the 32-bit value at offset in buffer memory is zero, then the
6071 * rendering commands are discarded, otherwise they are executed as
6072 * normal. If the value of the predicate in buffer memory changes while
6073 * conditional rendering is active, the rendering commands may be
6074 * discarded in an implementation-dependent way. Some implementations
6075 * may latch the value of the predicate upon beginning conditional
6076 * rendering while others may read it before every rendering command."
6077 *
6078 * But, the AMD hardware treats the predicate as a 64-bit value which
6079 * means we need a workaround in the driver. Luckily, it's not required
6080 * to support if the value changes when predication is active.
6081 *
6082 * The workaround is as follows:
6083 * 1) allocate a 64-value in the upload BO and initialize it to 0
6084 * 2) copy the 32-bit predicate value to the upload BO
6085 * 3) use the new allocated VA address for predication
6086 *
6087 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
6088 * in ME (+ sync PFP) instead of PFP.
6089 */
6090 radv_cmd_buffer_upload_data(cmd_buffer, 8, 16, &pred_value, &pred_offset);
6091
6092 new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
6093
6094 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
6095 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
6096 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
6097 COPY_DATA_WR_CONFIRM);
6098 radeon_emit(cs, va);
6099 radeon_emit(cs, va >> 32);
6100 radeon_emit(cs, new_va);
6101 radeon_emit(cs, new_va >> 32);
6102
6103 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
6104 radeon_emit(cs, 0);
6105
6106 /* Enable predication for this command buffer. */
6107 si_emit_set_predication_state(cmd_buffer, draw_visible, new_va);
6108 cmd_buffer->state.predicating = true;
6109
6110 /* Store conditional rendering user info. */
6111 cmd_buffer->state.predication_type = draw_visible;
6112 cmd_buffer->state.predication_va = new_va;
6113 }
6114
6115 void radv_CmdEndConditionalRenderingEXT(
6116 VkCommandBuffer commandBuffer)
6117 {
6118 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6119
6120 /* Disable predication for this command buffer. */
6121 si_emit_set_predication_state(cmd_buffer, false, 0);
6122 cmd_buffer->state.predicating = false;
6123
6124 /* Reset conditional rendering user info. */
6125 cmd_buffer->state.predication_type = -1;
6126 cmd_buffer->state.predication_va = 0;
6127 }
6128
6129 /* VK_EXT_transform_feedback */
6130 void radv_CmdBindTransformFeedbackBuffersEXT(
6131 VkCommandBuffer commandBuffer,
6132 uint32_t firstBinding,
6133 uint32_t bindingCount,
6134 const VkBuffer* pBuffers,
6135 const VkDeviceSize* pOffsets,
6136 const VkDeviceSize* pSizes)
6137 {
6138 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6139 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
6140 uint8_t enabled_mask = 0;
6141
6142 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
6143 for (uint32_t i = 0; i < bindingCount; i++) {
6144 uint32_t idx = firstBinding + i;
6145
6146 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
6147 sb[idx].offset = pOffsets[i];
6148
6149 if (!pSizes || pSizes[i] == VK_WHOLE_SIZE) {
6150 sb[idx].size = sb[idx].buffer->size - sb[idx].offset;
6151 } else {
6152 sb[idx].size = pSizes[i];
6153 }
6154
6155 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
6156 sb[idx].buffer->bo);
6157
6158 enabled_mask |= 1 << idx;
6159 }
6160
6161 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
6162
6163 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
6164 }
6165
6166 static void
6167 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
6168 {
6169 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6170 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6171
6172 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
6173 radeon_emit(cs,
6174 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
6175 S_028B94_RAST_STREAM(0) |
6176 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
6177 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
6178 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
6179 radeon_emit(cs, so->hw_enabled_mask &
6180 so->enabled_stream_buffers_mask);
6181
6182 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6183 }
6184
6185 static void
6186 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
6187 {
6188 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6189 bool old_streamout_enabled = so->streamout_enabled;
6190 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
6191
6192 so->streamout_enabled = enable;
6193
6194 so->hw_enabled_mask = so->enabled_mask |
6195 (so->enabled_mask << 4) |
6196 (so->enabled_mask << 8) |
6197 (so->enabled_mask << 12);
6198
6199 if (!cmd_buffer->device->physical_device->use_ngg_streamout &&
6200 ((old_streamout_enabled != so->streamout_enabled) ||
6201 (old_hw_enabled_mask != so->hw_enabled_mask)))
6202 radv_emit_streamout_enable(cmd_buffer);
6203
6204 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6205 cmd_buffer->gds_needed = true;
6206 cmd_buffer->gds_oa_needed = true;
6207 }
6208 }
6209
6210 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
6211 {
6212 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6213 unsigned reg_strmout_cntl;
6214
6215 /* The register is at different places on different ASICs. */
6216 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
6217 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
6218 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
6219 } else {
6220 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
6221 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
6222 }
6223
6224 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
6225 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
6226
6227 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
6228 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
6229 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
6230 radeon_emit(cs, 0);
6231 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
6232 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
6233 radeon_emit(cs, 4); /* poll interval */
6234 }
6235
6236 static void
6237 radv_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
6238 uint32_t firstCounterBuffer,
6239 uint32_t counterBufferCount,
6240 const VkBuffer *pCounterBuffers,
6241 const VkDeviceSize *pCounterBufferOffsets)
6242
6243 {
6244 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
6245 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6246 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6247 uint32_t i;
6248
6249 radv_flush_vgt_streamout(cmd_buffer);
6250
6251 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6252 for_each_bit(i, so->enabled_mask) {
6253 int32_t counter_buffer_idx = i - firstCounterBuffer;
6254 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6255 counter_buffer_idx = -1;
6256
6257 /* AMD GCN binds streamout buffers as shader resources.
6258 * VGT only counts primitives and tells the shader through
6259 * SGPRs what to do.
6260 */
6261 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
6262 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
6263 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
6264
6265 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6266
6267 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6268 /* The array of counter buffers is optional. */
6269 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6270 uint64_t va = radv_buffer_get_va(buffer->bo);
6271
6272 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6273
6274 /* Append */
6275 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6276 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6277 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6278 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
6279 radeon_emit(cs, 0); /* unused */
6280 radeon_emit(cs, 0); /* unused */
6281 radeon_emit(cs, va); /* src address lo */
6282 radeon_emit(cs, va >> 32); /* src address hi */
6283
6284 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6285 } else {
6286 /* Start from the beginning. */
6287 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6288 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6289 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6290 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
6291 radeon_emit(cs, 0); /* unused */
6292 radeon_emit(cs, 0); /* unused */
6293 radeon_emit(cs, 0); /* unused */
6294 radeon_emit(cs, 0); /* unused */
6295 }
6296 }
6297
6298 radv_set_streamout_enable(cmd_buffer, true);
6299 }
6300
6301 static void
6302 gfx10_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
6303 uint32_t firstCounterBuffer,
6304 uint32_t counterBufferCount,
6305 const VkBuffer *pCounterBuffers,
6306 const VkDeviceSize *pCounterBufferOffsets)
6307 {
6308 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6309 unsigned last_target = util_last_bit(so->enabled_mask) - 1;
6310 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6311 uint32_t i;
6312
6313 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6314 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6315
6316 /* Sync because the next streamout operation will overwrite GDS and we
6317 * have to make sure it's idle.
6318 * TODO: Improve by tracking if there is a streamout operation in
6319 * flight.
6320 */
6321 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
6322 si_emit_cache_flush(cmd_buffer);
6323
6324 for_each_bit(i, so->enabled_mask) {
6325 int32_t counter_buffer_idx = i - firstCounterBuffer;
6326 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6327 counter_buffer_idx = -1;
6328
6329 bool append = counter_buffer_idx >= 0 &&
6330 pCounterBuffers && pCounterBuffers[counter_buffer_idx];
6331 uint64_t va = 0;
6332
6333 if (append) {
6334 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6335
6336 va += radv_buffer_get_va(buffer->bo);
6337 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6338
6339 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6340 }
6341
6342 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
6343 radeon_emit(cs, S_411_SRC_SEL(append ? V_411_SRC_ADDR_TC_L2 : V_411_DATA) |
6344 S_411_DST_SEL(V_411_GDS) |
6345 S_411_CP_SYNC(i == last_target));
6346 radeon_emit(cs, va);
6347 radeon_emit(cs, va >> 32);
6348 radeon_emit(cs, 4 * i); /* destination in GDS */
6349 radeon_emit(cs, 0);
6350 radeon_emit(cs, S_414_BYTE_COUNT_GFX9(4) |
6351 S_414_DISABLE_WR_CONFIRM_GFX9(i != last_target));
6352 }
6353
6354 radv_set_streamout_enable(cmd_buffer, true);
6355 }
6356
6357 void radv_CmdBeginTransformFeedbackEXT(
6358 VkCommandBuffer commandBuffer,
6359 uint32_t firstCounterBuffer,
6360 uint32_t counterBufferCount,
6361 const VkBuffer* pCounterBuffers,
6362 const VkDeviceSize* pCounterBufferOffsets)
6363 {
6364 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6365
6366 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6367 gfx10_emit_streamout_begin(cmd_buffer,
6368 firstCounterBuffer, counterBufferCount,
6369 pCounterBuffers, pCounterBufferOffsets);
6370 } else {
6371 radv_emit_streamout_begin(cmd_buffer,
6372 firstCounterBuffer, counterBufferCount,
6373 pCounterBuffers, pCounterBufferOffsets);
6374 }
6375 }
6376
6377 static void
6378 radv_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6379 uint32_t firstCounterBuffer,
6380 uint32_t counterBufferCount,
6381 const VkBuffer *pCounterBuffers,
6382 const VkDeviceSize *pCounterBufferOffsets)
6383 {
6384 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6385 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6386 uint32_t i;
6387
6388 radv_flush_vgt_streamout(cmd_buffer);
6389
6390 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6391 for_each_bit(i, so->enabled_mask) {
6392 int32_t counter_buffer_idx = i - firstCounterBuffer;
6393 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6394 counter_buffer_idx = -1;
6395
6396 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6397 /* The array of counters buffer is optional. */
6398 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6399 uint64_t va = radv_buffer_get_va(buffer->bo);
6400
6401 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6402
6403 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6404 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6405 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6406 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
6407 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
6408 radeon_emit(cs, va); /* dst address lo */
6409 radeon_emit(cs, va >> 32); /* dst address hi */
6410 radeon_emit(cs, 0); /* unused */
6411 radeon_emit(cs, 0); /* unused */
6412
6413 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6414 }
6415
6416 /* Deactivate transform feedback by zeroing the buffer size.
6417 * The counters (primitives generated, primitives emitted) may
6418 * be enabled even if there is not buffer bound. This ensures
6419 * that the primitives-emitted query won't increment.
6420 */
6421 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
6422
6423 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6424 }
6425
6426 radv_set_streamout_enable(cmd_buffer, false);
6427 }
6428
6429 static void
6430 gfx10_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6431 uint32_t firstCounterBuffer,
6432 uint32_t counterBufferCount,
6433 const VkBuffer *pCounterBuffers,
6434 const VkDeviceSize *pCounterBufferOffsets)
6435 {
6436 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6437 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6438 uint32_t i;
6439
6440 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6441 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6442
6443 for_each_bit(i, so->enabled_mask) {
6444 int32_t counter_buffer_idx = i - firstCounterBuffer;
6445 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6446 counter_buffer_idx = -1;
6447
6448 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6449 /* The array of counters buffer is optional. */
6450 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6451 uint64_t va = radv_buffer_get_va(buffer->bo);
6452
6453 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6454
6455 si_cs_emit_write_event_eop(cs,
6456 cmd_buffer->device->physical_device->rad_info.chip_class,
6457 radv_cmd_buffer_uses_mec(cmd_buffer),
6458 V_028A90_PS_DONE, 0,
6459 EOP_DST_SEL_TC_L2,
6460 EOP_DATA_SEL_GDS,
6461 va, EOP_DATA_GDS(i, 1), 0);
6462
6463 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6464 }
6465 }
6466
6467 radv_set_streamout_enable(cmd_buffer, false);
6468 }
6469
6470 void radv_CmdEndTransformFeedbackEXT(
6471 VkCommandBuffer commandBuffer,
6472 uint32_t firstCounterBuffer,
6473 uint32_t counterBufferCount,
6474 const VkBuffer* pCounterBuffers,
6475 const VkDeviceSize* pCounterBufferOffsets)
6476 {
6477 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6478
6479 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6480 gfx10_emit_streamout_end(cmd_buffer,
6481 firstCounterBuffer, counterBufferCount,
6482 pCounterBuffers, pCounterBufferOffsets);
6483 } else {
6484 radv_emit_streamout_end(cmd_buffer,
6485 firstCounterBuffer, counterBufferCount,
6486 pCounterBuffers, pCounterBufferOffsets);
6487 }
6488 }
6489
6490 void radv_CmdDrawIndirectByteCountEXT(
6491 VkCommandBuffer commandBuffer,
6492 uint32_t instanceCount,
6493 uint32_t firstInstance,
6494 VkBuffer _counterBuffer,
6495 VkDeviceSize counterBufferOffset,
6496 uint32_t counterOffset,
6497 uint32_t vertexStride)
6498 {
6499 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6500 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
6501 struct radv_draw_info info = {};
6502
6503 info.instance_count = instanceCount;
6504 info.first_instance = firstInstance;
6505 info.strmout_buffer = counterBuffer;
6506 info.strmout_buffer_offset = counterBufferOffset;
6507 info.stride = vertexStride;
6508
6509 radv_draw(cmd_buffer, &info);
6510 }
6511
6512 /* VK_AMD_buffer_marker */
6513 void radv_CmdWriteBufferMarkerAMD(
6514 VkCommandBuffer commandBuffer,
6515 VkPipelineStageFlagBits pipelineStage,
6516 VkBuffer dstBuffer,
6517 VkDeviceSize dstOffset,
6518 uint32_t marker)
6519 {
6520 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6521 RADV_FROM_HANDLE(radv_buffer, buffer, dstBuffer);
6522 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6523 uint64_t va = radv_buffer_get_va(buffer->bo) + dstOffset;
6524
6525 si_emit_cache_flush(cmd_buffer);
6526
6527 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 12);
6528
6529 if (!(pipelineStage & ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT)) {
6530 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
6531 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
6532 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
6533 COPY_DATA_WR_CONFIRM);
6534 radeon_emit(cs, marker);
6535 radeon_emit(cs, 0);
6536 radeon_emit(cs, va);
6537 radeon_emit(cs, va >> 32);
6538 } else {
6539 si_cs_emit_write_event_eop(cs,
6540 cmd_buffer->device->physical_device->rad_info.chip_class,
6541 radv_cmd_buffer_uses_mec(cmd_buffer),
6542 V_028A90_BOTTOM_OF_PIPE_TS, 0,
6543 EOP_DST_SEL_MEM,
6544 EOP_DATA_SEL_VALUE_32BIT,
6545 va, marker,
6546 cmd_buffer->gfx9_eop_bug_va);
6547 }
6548
6549 assert(cmd_buffer->cs->cdw <= cdw_max);
6550 }