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radv: implement VK_EXT_line_rasterization
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 bool src_render_loop,
58 VkImageLayout dst_layout,
59 bool dst_render_loop,
60 uint32_t src_family,
61 uint32_t dst_family,
62 const VkImageSubresourceRange *range,
63 struct radv_sample_locations_state *sample_locs);
64
65 const struct radv_dynamic_state default_dynamic_state = {
66 .viewport = {
67 .count = 0,
68 },
69 .scissor = {
70 .count = 0,
71 },
72 .line_width = 1.0f,
73 .depth_bias = {
74 .bias = 0.0f,
75 .clamp = 0.0f,
76 .slope = 0.0f,
77 },
78 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
79 .depth_bounds = {
80 .min = 0.0f,
81 .max = 1.0f,
82 },
83 .stencil_compare_mask = {
84 .front = ~0u,
85 .back = ~0u,
86 },
87 .stencil_write_mask = {
88 .front = ~0u,
89 .back = ~0u,
90 },
91 .stencil_reference = {
92 .front = 0u,
93 .back = 0u,
94 },
95 .line_stipple = {
96 .factor = 0u,
97 .pattern = 0u,
98 },
99 };
100
101 static void
102 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
103 const struct radv_dynamic_state *src)
104 {
105 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
106 uint32_t copy_mask = src->mask;
107 uint32_t dest_mask = 0;
108
109 /* Make sure to copy the number of viewports/scissors because they can
110 * only be specified at pipeline creation time.
111 */
112 dest->viewport.count = src->viewport.count;
113 dest->scissor.count = src->scissor.count;
114 dest->discard_rectangle.count = src->discard_rectangle.count;
115 dest->sample_location.count = src->sample_location.count;
116
117 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
118 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
119 src->viewport.count * sizeof(VkViewport))) {
120 typed_memcpy(dest->viewport.viewports,
121 src->viewport.viewports,
122 src->viewport.count);
123 dest_mask |= RADV_DYNAMIC_VIEWPORT;
124 }
125 }
126
127 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
128 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
129 src->scissor.count * sizeof(VkRect2D))) {
130 typed_memcpy(dest->scissor.scissors,
131 src->scissor.scissors, src->scissor.count);
132 dest_mask |= RADV_DYNAMIC_SCISSOR;
133 }
134 }
135
136 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
137 if (dest->line_width != src->line_width) {
138 dest->line_width = src->line_width;
139 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
140 }
141 }
142
143 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
144 if (memcmp(&dest->depth_bias, &src->depth_bias,
145 sizeof(src->depth_bias))) {
146 dest->depth_bias = src->depth_bias;
147 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
148 }
149 }
150
151 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
152 if (memcmp(&dest->blend_constants, &src->blend_constants,
153 sizeof(src->blend_constants))) {
154 typed_memcpy(dest->blend_constants,
155 src->blend_constants, 4);
156 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
157 }
158 }
159
160 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
161 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
162 sizeof(src->depth_bounds))) {
163 dest->depth_bounds = src->depth_bounds;
164 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
165 }
166 }
167
168 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
169 if (memcmp(&dest->stencil_compare_mask,
170 &src->stencil_compare_mask,
171 sizeof(src->stencil_compare_mask))) {
172 dest->stencil_compare_mask = src->stencil_compare_mask;
173 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
174 }
175 }
176
177 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
178 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
179 sizeof(src->stencil_write_mask))) {
180 dest->stencil_write_mask = src->stencil_write_mask;
181 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
182 }
183 }
184
185 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
186 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
187 sizeof(src->stencil_reference))) {
188 dest->stencil_reference = src->stencil_reference;
189 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
190 }
191 }
192
193 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
194 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
195 src->discard_rectangle.count * sizeof(VkRect2D))) {
196 typed_memcpy(dest->discard_rectangle.rectangles,
197 src->discard_rectangle.rectangles,
198 src->discard_rectangle.count);
199 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
200 }
201 }
202
203 if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
204 if (dest->sample_location.per_pixel != src->sample_location.per_pixel ||
205 dest->sample_location.grid_size.width != src->sample_location.grid_size.width ||
206 dest->sample_location.grid_size.height != src->sample_location.grid_size.height ||
207 memcmp(&dest->sample_location.locations,
208 &src->sample_location.locations,
209 src->sample_location.count * sizeof(VkSampleLocationEXT))) {
210 dest->sample_location.per_pixel = src->sample_location.per_pixel;
211 dest->sample_location.grid_size = src->sample_location.grid_size;
212 typed_memcpy(dest->sample_location.locations,
213 src->sample_location.locations,
214 src->sample_location.count);
215 dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
216 }
217 }
218
219 if (copy_mask & RADV_DYNAMIC_LINE_STIPPLE) {
220 if (memcmp(&dest->line_stipple, &src->line_stipple,
221 sizeof(src->line_stipple))) {
222 dest->line_stipple = src->line_stipple;
223 dest_mask |= RADV_DYNAMIC_LINE_STIPPLE;
224 }
225 }
226
227 cmd_buffer->state.dirty |= dest_mask;
228 }
229
230 static void
231 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
232 struct radv_pipeline *pipeline)
233 {
234 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
235 struct radv_shader_info *info;
236
237 if (!pipeline->streamout_shader ||
238 cmd_buffer->device->physical_device->use_ngg_streamout)
239 return;
240
241 info = &pipeline->streamout_shader->info;
242 for (int i = 0; i < MAX_SO_BUFFERS; i++)
243 so->stride_in_dw[i] = info->so.strides[i];
244
245 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
246 }
247
248 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
249 {
250 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
251 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
252 }
253
254 enum ring_type radv_queue_family_to_ring(int f) {
255 switch (f) {
256 case RADV_QUEUE_GENERAL:
257 return RING_GFX;
258 case RADV_QUEUE_COMPUTE:
259 return RING_COMPUTE;
260 case RADV_QUEUE_TRANSFER:
261 return RING_DMA;
262 default:
263 unreachable("Unknown queue family");
264 }
265 }
266
267 static VkResult radv_create_cmd_buffer(
268 struct radv_device * device,
269 struct radv_cmd_pool * pool,
270 VkCommandBufferLevel level,
271 VkCommandBuffer* pCommandBuffer)
272 {
273 struct radv_cmd_buffer *cmd_buffer;
274 unsigned ring;
275 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
276 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
277 if (cmd_buffer == NULL)
278 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
279
280 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
281 cmd_buffer->device = device;
282 cmd_buffer->pool = pool;
283 cmd_buffer->level = level;
284
285 if (pool) {
286 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
287 cmd_buffer->queue_family_index = pool->queue_family_index;
288
289 } else {
290 /* Init the pool_link so we can safely call list_del when we destroy
291 * the command buffer
292 */
293 list_inithead(&cmd_buffer->pool_link);
294 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
295 }
296
297 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
298
299 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
300 if (!cmd_buffer->cs) {
301 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
302 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
303 }
304
305 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
306
307 list_inithead(&cmd_buffer->upload.list);
308
309 return VK_SUCCESS;
310 }
311
312 static void
313 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
314 {
315 list_del(&cmd_buffer->pool_link);
316
317 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
318 &cmd_buffer->upload.list, list) {
319 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
320 list_del(&up->list);
321 free(up);
322 }
323
324 if (cmd_buffer->upload.upload_bo)
325 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
326 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
327
328 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
329 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
330
331 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
332 }
333
334 static VkResult
335 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
336 {
337 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
338
339 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
340 &cmd_buffer->upload.list, list) {
341 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
342 list_del(&up->list);
343 free(up);
344 }
345
346 cmd_buffer->push_constant_stages = 0;
347 cmd_buffer->scratch_size_per_wave_needed = 0;
348 cmd_buffer->scratch_waves_wanted = 0;
349 cmd_buffer->compute_scratch_size_per_wave_needed = 0;
350 cmd_buffer->compute_scratch_waves_wanted = 0;
351 cmd_buffer->esgs_ring_size_needed = 0;
352 cmd_buffer->gsvs_ring_size_needed = 0;
353 cmd_buffer->tess_rings_needed = false;
354 cmd_buffer->gds_needed = false;
355 cmd_buffer->gds_oa_needed = false;
356 cmd_buffer->sample_positions_needed = false;
357
358 if (cmd_buffer->upload.upload_bo)
359 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
360 cmd_buffer->upload.upload_bo);
361 cmd_buffer->upload.offset = 0;
362
363 cmd_buffer->record_result = VK_SUCCESS;
364
365 memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
366
367 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
368 cmd_buffer->descriptors[i].dirty = 0;
369 cmd_buffer->descriptors[i].valid = 0;
370 cmd_buffer->descriptors[i].push_dirty = false;
371 }
372
373 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
374 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
375 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
376 unsigned fence_offset, eop_bug_offset;
377 void *fence_ptr;
378
379 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
380 &fence_ptr);
381
382 cmd_buffer->gfx9_fence_va =
383 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
384 cmd_buffer->gfx9_fence_va += fence_offset;
385
386 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
387 /* Allocate a buffer for the EOP bug on GFX9. */
388 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
389 &eop_bug_offset, &fence_ptr);
390 cmd_buffer->gfx9_eop_bug_va =
391 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
392 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
393 }
394 }
395
396 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
397
398 return cmd_buffer->record_result;
399 }
400
401 static bool
402 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
403 uint64_t min_needed)
404 {
405 uint64_t new_size;
406 struct radeon_winsys_bo *bo;
407 struct radv_cmd_buffer_upload *upload;
408 struct radv_device *device = cmd_buffer->device;
409
410 new_size = MAX2(min_needed, 16 * 1024);
411 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
412
413 bo = device->ws->buffer_create(device->ws,
414 new_size, 4096,
415 RADEON_DOMAIN_GTT,
416 RADEON_FLAG_CPU_ACCESS|
417 RADEON_FLAG_NO_INTERPROCESS_SHARING |
418 RADEON_FLAG_32BIT,
419 RADV_BO_PRIORITY_UPLOAD_BUFFER);
420
421 if (!bo) {
422 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
423 return false;
424 }
425
426 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
427 if (cmd_buffer->upload.upload_bo) {
428 upload = malloc(sizeof(*upload));
429
430 if (!upload) {
431 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
432 device->ws->buffer_destroy(bo);
433 return false;
434 }
435
436 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
437 list_add(&upload->list, &cmd_buffer->upload.list);
438 }
439
440 cmd_buffer->upload.upload_bo = bo;
441 cmd_buffer->upload.size = new_size;
442 cmd_buffer->upload.offset = 0;
443 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
444
445 if (!cmd_buffer->upload.map) {
446 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
447 return false;
448 }
449
450 return true;
451 }
452
453 bool
454 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
455 unsigned size,
456 unsigned alignment,
457 unsigned *out_offset,
458 void **ptr)
459 {
460 assert(util_is_power_of_two_nonzero(alignment));
461
462 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
463 if (offset + size > cmd_buffer->upload.size) {
464 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
465 return false;
466 offset = 0;
467 }
468
469 *out_offset = offset;
470 *ptr = cmd_buffer->upload.map + offset;
471
472 cmd_buffer->upload.offset = offset + size;
473 return true;
474 }
475
476 bool
477 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
478 unsigned size, unsigned alignment,
479 const void *data, unsigned *out_offset)
480 {
481 uint8_t *ptr;
482
483 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
484 out_offset, (void **)&ptr))
485 return false;
486
487 if (ptr)
488 memcpy(ptr, data, size);
489
490 return true;
491 }
492
493 static void
494 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
495 unsigned count, const uint32_t *data)
496 {
497 struct radeon_cmdbuf *cs = cmd_buffer->cs;
498
499 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
500
501 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
502 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
503 S_370_WR_CONFIRM(1) |
504 S_370_ENGINE_SEL(V_370_ME));
505 radeon_emit(cs, va);
506 radeon_emit(cs, va >> 32);
507 radeon_emit_array(cs, data, count);
508 }
509
510 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
511 {
512 struct radv_device *device = cmd_buffer->device;
513 struct radeon_cmdbuf *cs = cmd_buffer->cs;
514 uint64_t va;
515
516 va = radv_buffer_get_va(device->trace_bo);
517 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
518 va += 4;
519
520 ++cmd_buffer->state.trace_id;
521 radv_emit_write_data_packet(cmd_buffer, va, 1,
522 &cmd_buffer->state.trace_id);
523
524 radeon_check_space(cmd_buffer->device->ws, cs, 2);
525
526 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
527 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
528 }
529
530 static void
531 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
532 enum radv_cmd_flush_bits flags)
533 {
534 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
535 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
536 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
537
538 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
539
540 /* Force wait for graphics or compute engines to be idle. */
541 si_cs_emit_cache_flush(cmd_buffer->cs,
542 cmd_buffer->device->physical_device->rad_info.chip_class,
543 &cmd_buffer->gfx9_fence_idx,
544 cmd_buffer->gfx9_fence_va,
545 radv_cmd_buffer_uses_mec(cmd_buffer),
546 flags, cmd_buffer->gfx9_eop_bug_va);
547 }
548
549 if (unlikely(cmd_buffer->device->trace_bo))
550 radv_cmd_buffer_trace_emit(cmd_buffer);
551 }
552
553 static void
554 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
555 struct radv_pipeline *pipeline, enum ring_type ring)
556 {
557 struct radv_device *device = cmd_buffer->device;
558 uint32_t data[2];
559 uint64_t va;
560
561 va = radv_buffer_get_va(device->trace_bo);
562
563 switch (ring) {
564 case RING_GFX:
565 va += 8;
566 break;
567 case RING_COMPUTE:
568 va += 16;
569 break;
570 default:
571 assert(!"invalid ring type");
572 }
573
574 uint64_t pipeline_address = (uintptr_t)pipeline;
575 data[0] = pipeline_address;
576 data[1] = pipeline_address >> 32;
577
578 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
579 }
580
581 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
582 VkPipelineBindPoint bind_point,
583 struct radv_descriptor_set *set,
584 unsigned idx)
585 {
586 struct radv_descriptor_state *descriptors_state =
587 radv_get_descriptors_state(cmd_buffer, bind_point);
588
589 descriptors_state->sets[idx] = set;
590
591 descriptors_state->valid |= (1u << idx); /* active descriptors */
592 descriptors_state->dirty |= (1u << idx);
593 }
594
595 static void
596 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
597 VkPipelineBindPoint bind_point)
598 {
599 struct radv_descriptor_state *descriptors_state =
600 radv_get_descriptors_state(cmd_buffer, bind_point);
601 struct radv_device *device = cmd_buffer->device;
602 uint32_t data[MAX_SETS * 2] = {};
603 uint64_t va;
604 unsigned i;
605 va = radv_buffer_get_va(device->trace_bo) + 24;
606
607 for_each_bit(i, descriptors_state->valid) {
608 struct radv_descriptor_set *set = descriptors_state->sets[i];
609 data[i * 2] = (uint64_t)(uintptr_t)set;
610 data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
611 }
612
613 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
614 }
615
616 struct radv_userdata_info *
617 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
618 gl_shader_stage stage,
619 int idx)
620 {
621 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
622 return &shader->info.user_sgprs_locs.shader_data[idx];
623 }
624
625 static void
626 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
627 struct radv_pipeline *pipeline,
628 gl_shader_stage stage,
629 int idx, uint64_t va)
630 {
631 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
632 uint32_t base_reg = pipeline->user_data_0[stage];
633 if (loc->sgpr_idx == -1)
634 return;
635
636 assert(loc->num_sgprs == 1);
637
638 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
639 base_reg + loc->sgpr_idx * 4, va, false);
640 }
641
642 static void
643 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
644 struct radv_pipeline *pipeline,
645 struct radv_descriptor_state *descriptors_state,
646 gl_shader_stage stage)
647 {
648 struct radv_device *device = cmd_buffer->device;
649 struct radeon_cmdbuf *cs = cmd_buffer->cs;
650 uint32_t sh_base = pipeline->user_data_0[stage];
651 struct radv_userdata_locations *locs =
652 &pipeline->shaders[stage]->info.user_sgprs_locs;
653 unsigned mask = locs->descriptor_sets_enabled;
654
655 mask &= descriptors_state->dirty & descriptors_state->valid;
656
657 while (mask) {
658 int start, count;
659
660 u_bit_scan_consecutive_range(&mask, &start, &count);
661
662 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
663 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
664
665 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
666 for (int i = 0; i < count; i++) {
667 struct radv_descriptor_set *set =
668 descriptors_state->sets[start + i];
669
670 radv_emit_shader_pointer_body(device, cs, set->va, true);
671 }
672 }
673 }
674
675 /**
676 * Convert the user sample locations to hardware sample locations (the values
677 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
678 */
679 static void
680 radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
681 uint32_t x, uint32_t y, VkOffset2D *sample_locs)
682 {
683 uint32_t x_offset = x % state->grid_size.width;
684 uint32_t y_offset = y % state->grid_size.height;
685 uint32_t num_samples = (uint32_t)state->per_pixel;
686 VkSampleLocationEXT *user_locs;
687 uint32_t pixel_offset;
688
689 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
690
691 assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
692 user_locs = &state->locations[pixel_offset];
693
694 for (uint32_t i = 0; i < num_samples; i++) {
695 float shifted_pos_x = user_locs[i].x - 0.5;
696 float shifted_pos_y = user_locs[i].y - 0.5;
697
698 int32_t scaled_pos_x = floor(shifted_pos_x * 16);
699 int32_t scaled_pos_y = floor(shifted_pos_y * 16);
700
701 sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
702 sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
703 }
704 }
705
706 /**
707 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
708 * locations.
709 */
710 static void
711 radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
712 uint32_t *sample_locs_pixel)
713 {
714 for (uint32_t i = 0; i < num_samples; i++) {
715 uint32_t sample_reg_idx = i / 4;
716 uint32_t sample_loc_idx = i % 4;
717 int32_t pos_x = sample_locs[i].x;
718 int32_t pos_y = sample_locs[i].y;
719
720 uint32_t shift_x = 8 * sample_loc_idx;
721 uint32_t shift_y = shift_x + 4;
722
723 sample_locs_pixel[sample_reg_idx] |= (pos_x & 0xf) << shift_x;
724 sample_locs_pixel[sample_reg_idx] |= (pos_y & 0xf) << shift_y;
725 }
726 }
727
728 /**
729 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
730 * sample locations.
731 */
732 static uint64_t
733 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer,
734 VkOffset2D *sample_locs,
735 uint32_t num_samples)
736 {
737 uint32_t centroid_priorities[num_samples];
738 uint32_t sample_mask = num_samples - 1;
739 uint32_t distances[num_samples];
740 uint64_t centroid_priority = 0;
741
742 /* Compute the distances from center for each sample. */
743 for (int i = 0; i < num_samples; i++) {
744 distances[i] = (sample_locs[i].x * sample_locs[i].x) +
745 (sample_locs[i].y * sample_locs[i].y);
746 }
747
748 /* Compute the centroid priorities by looking at the distances array. */
749 for (int i = 0; i < num_samples; i++) {
750 uint32_t min_idx = 0;
751
752 for (int j = 1; j < num_samples; j++) {
753 if (distances[j] < distances[min_idx])
754 min_idx = j;
755 }
756
757 centroid_priorities[i] = min_idx;
758 distances[min_idx] = 0xffffffff;
759 }
760
761 /* Compute the final centroid priority. */
762 for (int i = 0; i < 8; i++) {
763 centroid_priority |=
764 centroid_priorities[i & sample_mask] << (i * 4);
765 }
766
767 return centroid_priority << 32 | centroid_priority;
768 }
769
770 /**
771 * Emit the sample locations that are specified with VK_EXT_sample_locations.
772 */
773 static void
774 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
775 {
776 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
777 struct radv_multisample_state *ms = &pipeline->graphics.ms;
778 struct radv_sample_locations_state *sample_location =
779 &cmd_buffer->state.dynamic.sample_location;
780 uint32_t num_samples = (uint32_t)sample_location->per_pixel;
781 struct radeon_cmdbuf *cs = cmd_buffer->cs;
782 uint32_t sample_locs_pixel[4][2] = {};
783 VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
784 uint32_t max_sample_dist = 0;
785 uint64_t centroid_priority;
786
787 if (!cmd_buffer->state.dynamic.sample_location.count)
788 return;
789
790 /* Convert the user sample locations to hardware sample locations. */
791 radv_convert_user_sample_locs(sample_location, 0, 0, sample_locs[0]);
792 radv_convert_user_sample_locs(sample_location, 1, 0, sample_locs[1]);
793 radv_convert_user_sample_locs(sample_location, 0, 1, sample_locs[2]);
794 radv_convert_user_sample_locs(sample_location, 1, 1, sample_locs[3]);
795
796 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
797 for (uint32_t i = 0; i < 4; i++) {
798 radv_compute_sample_locs_pixel(num_samples, sample_locs[i],
799 sample_locs_pixel[i]);
800 }
801
802 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
803 centroid_priority =
804 radv_compute_centroid_priority(cmd_buffer, sample_locs[0],
805 num_samples);
806
807 /* Compute the maximum sample distance from the specified locations. */
808 for (uint32_t i = 0; i < num_samples; i++) {
809 VkOffset2D offset = sample_locs[0][i];
810 max_sample_dist = MAX2(max_sample_dist,
811 MAX2(abs(offset.x), abs(offset.y)));
812 }
813
814 /* Emit the specified user sample locations. */
815 switch (num_samples) {
816 case 2:
817 case 4:
818 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
819 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
820 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
821 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
822 break;
823 case 8:
824 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
825 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
826 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
827 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
828 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs_pixel[0][1]);
829 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs_pixel[1][1]);
830 radeon_set_context_reg(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs_pixel[2][1]);
831 radeon_set_context_reg(cs, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs_pixel[3][1]);
832 break;
833 default:
834 unreachable("invalid number of samples");
835 }
836
837 /* Emit the maximum sample distance and the centroid priority. */
838 uint32_t pa_sc_aa_config = ms->pa_sc_aa_config;
839
840 pa_sc_aa_config &= C_028BE0_MAX_SAMPLE_DIST;
841 pa_sc_aa_config |= S_028BE0_MAX_SAMPLE_DIST(max_sample_dist);
842
843 radeon_set_context_reg_seq(cs, R_028BE0_PA_SC_AA_CONFIG, 1);
844 radeon_emit(cs, pa_sc_aa_config);
845
846 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
847 radeon_emit(cs, centroid_priority);
848 radeon_emit(cs, centroid_priority >> 32);
849
850 /* GFX9: Flush DFSM when the AA mode changes. */
851 if (cmd_buffer->device->dfsm_allowed) {
852 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
853 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
854 }
855
856 cmd_buffer->state.context_roll_without_scissor_emitted = true;
857 }
858
859 static void
860 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
861 struct radv_pipeline *pipeline,
862 gl_shader_stage stage,
863 int idx, int count, uint32_t *values)
864 {
865 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
866 uint32_t base_reg = pipeline->user_data_0[stage];
867 if (loc->sgpr_idx == -1)
868 return;
869
870 assert(loc->num_sgprs == count);
871
872 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
873 radeon_emit_array(cmd_buffer->cs, values, count);
874 }
875
876 static void
877 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
878 struct radv_pipeline *pipeline)
879 {
880 int num_samples = pipeline->graphics.ms.num_samples;
881 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
882
883 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.needs_sample_positions)
884 cmd_buffer->sample_positions_needed = true;
885
886 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
887 return;
888
889 radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
890
891 cmd_buffer->state.context_roll_without_scissor_emitted = true;
892 }
893
894 static void
895 radv_update_binning_state(struct radv_cmd_buffer *cmd_buffer,
896 struct radv_pipeline *pipeline)
897 {
898 const struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
899
900
901 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
902 return;
903
904 if (old_pipeline &&
905 old_pipeline->graphics.binning.pa_sc_binner_cntl_0 == pipeline->graphics.binning.pa_sc_binner_cntl_0 &&
906 old_pipeline->graphics.binning.db_dfsm_control == pipeline->graphics.binning.db_dfsm_control)
907 return;
908
909 bool binning_flush = false;
910 if (cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA12 ||
911 cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA20 ||
912 cmd_buffer->device->physical_device->rad_info.family == CHIP_RAVEN2 ||
913 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
914 binning_flush = !old_pipeline ||
915 G_028C44_BINNING_MODE(old_pipeline->graphics.binning.pa_sc_binner_cntl_0) !=
916 G_028C44_BINNING_MODE(pipeline->graphics.binning.pa_sc_binner_cntl_0);
917 }
918
919 radeon_set_context_reg(cmd_buffer->cs, R_028C44_PA_SC_BINNER_CNTL_0,
920 pipeline->graphics.binning.pa_sc_binner_cntl_0 |
921 S_028C44_FLUSH_ON_BINNING_TRANSITION(!!binning_flush));
922
923 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
924 radeon_set_context_reg(cmd_buffer->cs, R_028038_DB_DFSM_CONTROL,
925 pipeline->graphics.binning.db_dfsm_control);
926 } else {
927 radeon_set_context_reg(cmd_buffer->cs, R_028060_DB_DFSM_CONTROL,
928 pipeline->graphics.binning.db_dfsm_control);
929 }
930
931 cmd_buffer->state.context_roll_without_scissor_emitted = true;
932 }
933
934
935 static void
936 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
937 struct radv_shader_variant *shader)
938 {
939 uint64_t va;
940
941 if (!shader)
942 return;
943
944 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
945
946 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
947 }
948
949 static void
950 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
951 struct radv_pipeline *pipeline,
952 bool vertex_stage_only)
953 {
954 struct radv_cmd_state *state = &cmd_buffer->state;
955 uint32_t mask = state->prefetch_L2_mask;
956
957 if (vertex_stage_only) {
958 /* Fast prefetch path for starting draws as soon as possible.
959 */
960 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
961 RADV_PREFETCH_VBO_DESCRIPTORS);
962 }
963
964 if (mask & RADV_PREFETCH_VS)
965 radv_emit_shader_prefetch(cmd_buffer,
966 pipeline->shaders[MESA_SHADER_VERTEX]);
967
968 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
969 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
970
971 if (mask & RADV_PREFETCH_TCS)
972 radv_emit_shader_prefetch(cmd_buffer,
973 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
974
975 if (mask & RADV_PREFETCH_TES)
976 radv_emit_shader_prefetch(cmd_buffer,
977 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
978
979 if (mask & RADV_PREFETCH_GS) {
980 radv_emit_shader_prefetch(cmd_buffer,
981 pipeline->shaders[MESA_SHADER_GEOMETRY]);
982 if (radv_pipeline_has_gs_copy_shader(pipeline))
983 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
984 }
985
986 if (mask & RADV_PREFETCH_PS)
987 radv_emit_shader_prefetch(cmd_buffer,
988 pipeline->shaders[MESA_SHADER_FRAGMENT]);
989
990 state->prefetch_L2_mask &= ~mask;
991 }
992
993 static void
994 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
995 {
996 if (!cmd_buffer->device->physical_device->rad_info.rbplus_allowed)
997 return;
998
999 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1000 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1001
1002 unsigned sx_ps_downconvert = 0;
1003 unsigned sx_blend_opt_epsilon = 0;
1004 unsigned sx_blend_opt_control = 0;
1005
1006 if (!cmd_buffer->state.attachments || !subpass)
1007 return;
1008
1009 for (unsigned i = 0; i < subpass->color_count; ++i) {
1010 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1011 /* We don't set the DISABLE bits, because the HW can't have holes,
1012 * so the SPI color format is set to 32-bit 1-component. */
1013 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1014 continue;
1015 }
1016
1017 int idx = subpass->color_attachments[i].attachment;
1018 struct radv_color_buffer_info *cb = &cmd_buffer->state.attachments[idx].cb;
1019
1020 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
1021 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
1022 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
1023 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
1024
1025 bool has_alpha, has_rgb;
1026
1027 /* Set if RGB and A are present. */
1028 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
1029
1030 if (format == V_028C70_COLOR_8 ||
1031 format == V_028C70_COLOR_16 ||
1032 format == V_028C70_COLOR_32)
1033 has_rgb = !has_alpha;
1034 else
1035 has_rgb = true;
1036
1037 /* Check the colormask and export format. */
1038 if (!(colormask & 0x7))
1039 has_rgb = false;
1040 if (!(colormask & 0x8))
1041 has_alpha = false;
1042
1043 if (spi_format == V_028714_SPI_SHADER_ZERO) {
1044 has_rgb = false;
1045 has_alpha = false;
1046 }
1047
1048 /* Disable value checking for disabled channels. */
1049 if (!has_rgb)
1050 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1051 if (!has_alpha)
1052 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1053
1054 /* Enable down-conversion for 32bpp and smaller formats. */
1055 switch (format) {
1056 case V_028C70_COLOR_8:
1057 case V_028C70_COLOR_8_8:
1058 case V_028C70_COLOR_8_8_8_8:
1059 /* For 1 and 2-channel formats, use the superset thereof. */
1060 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
1061 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1062 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1063 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
1064 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
1065 }
1066 break;
1067
1068 case V_028C70_COLOR_5_6_5:
1069 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1070 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
1071 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
1072 }
1073 break;
1074
1075 case V_028C70_COLOR_1_5_5_5:
1076 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1077 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
1078 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
1079 }
1080 break;
1081
1082 case V_028C70_COLOR_4_4_4_4:
1083 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1084 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
1085 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
1086 }
1087 break;
1088
1089 case V_028C70_COLOR_32:
1090 if (swap == V_028C70_SWAP_STD &&
1091 spi_format == V_028714_SPI_SHADER_32_R)
1092 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1093 else if (swap == V_028C70_SWAP_ALT_REV &&
1094 spi_format == V_028714_SPI_SHADER_32_AR)
1095 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
1096 break;
1097
1098 case V_028C70_COLOR_16:
1099 case V_028C70_COLOR_16_16:
1100 /* For 1-channel formats, use the superset thereof. */
1101 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
1102 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
1103 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1104 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1105 if (swap == V_028C70_SWAP_STD ||
1106 swap == V_028C70_SWAP_STD_REV)
1107 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
1108 else
1109 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
1110 }
1111 break;
1112
1113 case V_028C70_COLOR_10_11_11:
1114 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1115 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
1116 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
1117 }
1118 break;
1119
1120 case V_028C70_COLOR_2_10_10_10:
1121 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1122 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
1123 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
1124 }
1125 break;
1126 }
1127 }
1128
1129 /* Do not set the DISABLE bits for the unused attachments, as that
1130 * breaks dual source blending in SkQP and does not seem to improve
1131 * performance. */
1132
1133 if (sx_ps_downconvert == cmd_buffer->state.last_sx_ps_downconvert &&
1134 sx_blend_opt_epsilon == cmd_buffer->state.last_sx_blend_opt_epsilon &&
1135 sx_blend_opt_control == cmd_buffer->state.last_sx_blend_opt_control)
1136 return;
1137
1138 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
1139 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
1140 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
1141 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
1142
1143 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1144
1145 cmd_buffer->state.last_sx_ps_downconvert = sx_ps_downconvert;
1146 cmd_buffer->state.last_sx_blend_opt_epsilon = sx_blend_opt_epsilon;
1147 cmd_buffer->state.last_sx_blend_opt_control = sx_blend_opt_control;
1148 }
1149
1150 static void
1151 radv_emit_batch_break_on_new_ps(struct radv_cmd_buffer *cmd_buffer)
1152 {
1153 if (!cmd_buffer->device->pbb_allowed)
1154 return;
1155
1156 struct radv_binning_settings settings =
1157 radv_get_binning_settings(cmd_buffer->device->physical_device);
1158 bool break_for_new_ps =
1159 (!cmd_buffer->state.emitted_pipeline ||
1160 cmd_buffer->state.emitted_pipeline->shaders[MESA_SHADER_FRAGMENT] !=
1161 cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT]) &&
1162 (settings.context_states_per_bin > 1 ||
1163 settings.persistent_states_per_bin > 1);
1164 bool break_for_new_cb_target_mask =
1165 (!cmd_buffer->state.emitted_pipeline ||
1166 cmd_buffer->state.emitted_pipeline->graphics.cb_target_mask !=
1167 cmd_buffer->state.pipeline->graphics.cb_target_mask) &&
1168 settings.context_states_per_bin > 1;
1169
1170 if (!break_for_new_ps && !break_for_new_cb_target_mask)
1171 return;
1172
1173 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1174 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1175 }
1176
1177 static void
1178 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1179 {
1180 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1181
1182 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1183 return;
1184
1185 radv_update_multisample_state(cmd_buffer, pipeline);
1186 radv_update_binning_state(cmd_buffer, pipeline);
1187
1188 cmd_buffer->scratch_size_per_wave_needed = MAX2(cmd_buffer->scratch_size_per_wave_needed,
1189 pipeline->scratch_bytes_per_wave);
1190 cmd_buffer->scratch_waves_wanted = MAX2(cmd_buffer->scratch_waves_wanted,
1191 pipeline->max_waves);
1192
1193 if (!cmd_buffer->state.emitted_pipeline ||
1194 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1195 pipeline->graphics.can_use_guardband)
1196 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1197
1198 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
1199
1200 if (!cmd_buffer->state.emitted_pipeline ||
1201 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
1202 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
1203 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
1204 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
1205 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
1206 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1207 }
1208
1209 radv_emit_batch_break_on_new_ps(cmd_buffer);
1210
1211 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
1212 if (!pipeline->shaders[i])
1213 continue;
1214
1215 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1216 pipeline->shaders[i]->bo);
1217 }
1218
1219 if (radv_pipeline_has_gs_copy_shader(pipeline))
1220 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1221 pipeline->gs_copy_shader->bo);
1222
1223 if (unlikely(cmd_buffer->device->trace_bo))
1224 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1225
1226 cmd_buffer->state.emitted_pipeline = pipeline;
1227
1228 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1229 }
1230
1231 static void
1232 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1233 {
1234 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1235 cmd_buffer->state.dynamic.viewport.viewports);
1236 }
1237
1238 static void
1239 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1240 {
1241 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1242
1243 si_write_scissors(cmd_buffer->cs, 0, count,
1244 cmd_buffer->state.dynamic.scissor.scissors,
1245 cmd_buffer->state.dynamic.viewport.viewports,
1246 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1247
1248 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1249 }
1250
1251 static void
1252 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1253 {
1254 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1255 return;
1256
1257 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1258 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1259 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1260 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1261 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1262 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1263 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1264 }
1265 }
1266
1267 static void
1268 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1269 {
1270 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1271
1272 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1273 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1274 }
1275
1276 static void
1277 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1278 {
1279 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1280
1281 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1282 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1283 }
1284
1285 static void
1286 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1287 {
1288 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1289
1290 radeon_set_context_reg_seq(cmd_buffer->cs,
1291 R_028430_DB_STENCILREFMASK, 2);
1292 radeon_emit(cmd_buffer->cs,
1293 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1294 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1295 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1296 S_028430_STENCILOPVAL(1));
1297 radeon_emit(cmd_buffer->cs,
1298 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1299 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1300 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1301 S_028434_STENCILOPVAL_BF(1));
1302 }
1303
1304 static void
1305 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1306 {
1307 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1308
1309 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1310 fui(d->depth_bounds.min));
1311 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1312 fui(d->depth_bounds.max));
1313 }
1314
1315 static void
1316 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1317 {
1318 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1319 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1320 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1321
1322
1323 radeon_set_context_reg_seq(cmd_buffer->cs,
1324 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1325 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1326 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1327 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1328 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1329 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1330 }
1331
1332 static void
1333 radv_emit_line_stipple(struct radv_cmd_buffer *cmd_buffer)
1334 {
1335 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1336 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1337 uint32_t auto_reset_cntl = 1;
1338
1339 if (pipeline->graphics.topology == VK_PRIMITIVE_TOPOLOGY_LINE_STRIP)
1340 auto_reset_cntl = 2;
1341
1342 radeon_set_context_reg(cmd_buffer->cs, R_028A0C_PA_SC_LINE_STIPPLE,
1343 S_028A0C_LINE_PATTERN(d->line_stipple.pattern) |
1344 S_028A0C_REPEAT_COUNT(d->line_stipple.factor - 1) |
1345 S_028A0C_AUTO_RESET_CNTL(auto_reset_cntl));
1346 }
1347
1348 static void
1349 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1350 int index,
1351 struct radv_color_buffer_info *cb,
1352 struct radv_image_view *iview,
1353 VkImageLayout layout,
1354 bool in_render_loop)
1355 {
1356 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
1357 uint32_t cb_color_info = cb->cb_color_info;
1358 struct radv_image *image = iview->image;
1359
1360 if (!radv_layout_dcc_compressed(cmd_buffer->device, image, layout, in_render_loop,
1361 radv_image_queue_family_mask(image,
1362 cmd_buffer->queue_family_index,
1363 cmd_buffer->queue_family_index))) {
1364 cb_color_info &= C_028C70_DCC_ENABLE;
1365 }
1366
1367 if (radv_image_is_tc_compat_cmask(image) &&
1368 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1369 radv_is_dcc_decompress_pipeline(cmd_buffer))) {
1370 /* If this bit is set, the FMASK decompression operation
1371 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1372 */
1373 cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
1374 }
1375
1376 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1377 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1378 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1379 radeon_emit(cmd_buffer->cs, 0);
1380 radeon_emit(cmd_buffer->cs, 0);
1381 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1382 radeon_emit(cmd_buffer->cs, cb_color_info);
1383 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1384 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1385 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1386 radeon_emit(cmd_buffer->cs, 0);
1387 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1388 radeon_emit(cmd_buffer->cs, 0);
1389
1390 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 1);
1391 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1392
1393 radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4,
1394 cb->cb_color_base >> 32);
1395 radeon_set_context_reg(cmd_buffer->cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + index * 4,
1396 cb->cb_color_cmask >> 32);
1397 radeon_set_context_reg(cmd_buffer->cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + index * 4,
1398 cb->cb_color_fmask >> 32);
1399 radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4,
1400 cb->cb_dcc_base >> 32);
1401 radeon_set_context_reg(cmd_buffer->cs, R_028EC0_CB_COLOR0_ATTRIB2 + index * 4,
1402 cb->cb_color_attrib2);
1403 radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4,
1404 cb->cb_color_attrib3);
1405 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1406 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1407 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1408 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1409 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1410 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1411 radeon_emit(cmd_buffer->cs, cb_color_info);
1412 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1413 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1414 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1415 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1416 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1417 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1418
1419 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1420 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1421 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1422
1423 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1424 cb->cb_mrt_epitch);
1425 } else {
1426 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1427 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1428 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1429 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1430 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1431 radeon_emit(cmd_buffer->cs, cb_color_info);
1432 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1433 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1434 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1435 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1436 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1437 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1438
1439 if (is_vi) { /* DCC BASE */
1440 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1441 }
1442 }
1443
1444 if (radv_dcc_enabled(image, iview->base_mip)) {
1445 /* Drawing with DCC enabled also compresses colorbuffers. */
1446 VkImageSubresourceRange range = {
1447 .aspectMask = iview->aspect_mask,
1448 .baseMipLevel = iview->base_mip,
1449 .levelCount = iview->level_count,
1450 .baseArrayLayer = iview->base_layer,
1451 .layerCount = iview->layer_count,
1452 };
1453
1454 radv_update_dcc_metadata(cmd_buffer, image, &range, true);
1455 }
1456 }
1457
1458 static void
1459 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1460 struct radv_ds_buffer_info *ds,
1461 const struct radv_image_view *iview,
1462 VkImageLayout layout,
1463 bool in_render_loop, bool requires_cond_exec)
1464 {
1465 const struct radv_image *image = iview->image;
1466 uint32_t db_z_info = ds->db_z_info;
1467 uint32_t db_z_info_reg;
1468
1469 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug ||
1470 !radv_image_is_tc_compat_htile(image))
1471 return;
1472
1473 if (!radv_layout_has_htile(image, layout, in_render_loop,
1474 radv_image_queue_family_mask(image,
1475 cmd_buffer->queue_family_index,
1476 cmd_buffer->queue_family_index))) {
1477 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1478 }
1479
1480 db_z_info &= C_028040_ZRANGE_PRECISION;
1481
1482 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1483 db_z_info_reg = R_028038_DB_Z_INFO;
1484 } else {
1485 db_z_info_reg = R_028040_DB_Z_INFO;
1486 }
1487
1488 /* When we don't know the last fast clear value we need to emit a
1489 * conditional packet that will eventually skip the following
1490 * SET_CONTEXT_REG packet.
1491 */
1492 if (requires_cond_exec) {
1493 uint64_t va = radv_get_tc_compat_zrange_va(image, iview->base_mip);
1494
1495 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1496 radeon_emit(cmd_buffer->cs, va);
1497 radeon_emit(cmd_buffer->cs, va >> 32);
1498 radeon_emit(cmd_buffer->cs, 0);
1499 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1500 }
1501
1502 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1503 }
1504
1505 static void
1506 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1507 struct radv_ds_buffer_info *ds,
1508 struct radv_image_view *iview,
1509 VkImageLayout layout,
1510 bool in_render_loop)
1511 {
1512 const struct radv_image *image = iview->image;
1513 uint32_t db_z_info = ds->db_z_info;
1514 uint32_t db_stencil_info = ds->db_stencil_info;
1515
1516 if (!radv_layout_has_htile(image, layout, in_render_loop,
1517 radv_image_queue_family_mask(image,
1518 cmd_buffer->queue_family_index,
1519 cmd_buffer->queue_family_index))) {
1520 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1521 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1522 }
1523
1524 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1525 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1526
1527 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1528 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1529 radeon_set_context_reg(cmd_buffer->cs, R_02801C_DB_DEPTH_SIZE_XY, ds->db_depth_size);
1530
1531 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 7);
1532 radeon_emit(cmd_buffer->cs, S_02803C_RESOURCE_LEVEL(1));
1533 radeon_emit(cmd_buffer->cs, db_z_info);
1534 radeon_emit(cmd_buffer->cs, db_stencil_info);
1535 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1536 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1537 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1538 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1539
1540 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_READ_BASE_HI, 5);
1541 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1542 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1543 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1544 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1545 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1546 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1547 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1548 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1549 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1550 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1551
1552 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1553 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1554 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1555 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1556 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1557 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1558 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1559 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1560 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1561 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1562 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1563
1564 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1565 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1566 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1567 } else {
1568 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1569
1570 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1571 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1572 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1573 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1574 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1575 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1576 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1577 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1578 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1579 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1580
1581 }
1582
1583 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1584 radv_update_zrange_precision(cmd_buffer, ds, iview, layout,
1585 in_render_loop, true);
1586
1587 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1588 ds->pa_su_poly_offset_db_fmt_cntl);
1589 }
1590
1591 /**
1592 * Update the fast clear depth/stencil values if the image is bound as a
1593 * depth/stencil buffer.
1594 */
1595 static void
1596 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1597 const struct radv_image_view *iview,
1598 VkClearDepthStencilValue ds_clear_value,
1599 VkImageAspectFlags aspects)
1600 {
1601 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1602 const struct radv_image *image = iview->image;
1603 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1604 uint32_t att_idx;
1605
1606 if (!cmd_buffer->state.attachments || !subpass)
1607 return;
1608
1609 if (!subpass->depth_stencil_attachment)
1610 return;
1611
1612 att_idx = subpass->depth_stencil_attachment->attachment;
1613 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1614 return;
1615
1616 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1617 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1618 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1619 radeon_emit(cs, ds_clear_value.stencil);
1620 radeon_emit(cs, fui(ds_clear_value.depth));
1621 } else if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1622 radeon_set_context_reg_seq(cs, R_02802C_DB_DEPTH_CLEAR, 1);
1623 radeon_emit(cs, fui(ds_clear_value.depth));
1624 } else {
1625 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1626 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 1);
1627 radeon_emit(cs, ds_clear_value.stencil);
1628 }
1629
1630 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1631 * only needed when clearing Z to 0.0.
1632 */
1633 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1634 ds_clear_value.depth == 0.0) {
1635 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1636 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
1637
1638 radv_update_zrange_precision(cmd_buffer, &cmd_buffer->state.attachments[att_idx].ds,
1639 iview, layout, in_render_loop, false);
1640 }
1641
1642 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1643 }
1644
1645 /**
1646 * Set the clear depth/stencil values to the image's metadata.
1647 */
1648 static void
1649 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1650 struct radv_image *image,
1651 const VkImageSubresourceRange *range,
1652 VkClearDepthStencilValue ds_clear_value,
1653 VkImageAspectFlags aspects)
1654 {
1655 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1656 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel);
1657 uint32_t level_count = radv_get_levelCount(image, range);
1658
1659 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1660 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1661 /* Use the fastest way when both aspects are used. */
1662 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + 2 * level_count, cmd_buffer->state.predicating));
1663 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1664 S_370_WR_CONFIRM(1) |
1665 S_370_ENGINE_SEL(V_370_PFP));
1666 radeon_emit(cs, va);
1667 radeon_emit(cs, va >> 32);
1668
1669 for (uint32_t l = 0; l < level_count; l++) {
1670 radeon_emit(cs, ds_clear_value.stencil);
1671 radeon_emit(cs, fui(ds_clear_value.depth));
1672 }
1673 } else {
1674 /* Otherwise we need one WRITE_DATA packet per level. */
1675 for (uint32_t l = 0; l < level_count; l++) {
1676 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel + l);
1677 unsigned value;
1678
1679 if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1680 value = fui(ds_clear_value.depth);
1681 va += 4;
1682 } else {
1683 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1684 value = ds_clear_value.stencil;
1685 }
1686
1687 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1688 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1689 S_370_WR_CONFIRM(1) |
1690 S_370_ENGINE_SEL(V_370_PFP));
1691 radeon_emit(cs, va);
1692 radeon_emit(cs, va >> 32);
1693 radeon_emit(cs, value);
1694 }
1695 }
1696 }
1697
1698 /**
1699 * Update the TC-compat metadata value for this image.
1700 */
1701 static void
1702 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1703 struct radv_image *image,
1704 const VkImageSubresourceRange *range,
1705 uint32_t value)
1706 {
1707 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1708
1709 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug)
1710 return;
1711
1712 uint64_t va = radv_get_tc_compat_zrange_va(image, range->baseMipLevel);
1713 uint32_t level_count = radv_get_levelCount(image, range);
1714
1715 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + level_count, cmd_buffer->state.predicating));
1716 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1717 S_370_WR_CONFIRM(1) |
1718 S_370_ENGINE_SEL(V_370_PFP));
1719 radeon_emit(cs, va);
1720 radeon_emit(cs, va >> 32);
1721
1722 for (uint32_t l = 0; l < level_count; l++)
1723 radeon_emit(cs, value);
1724 }
1725
1726 static void
1727 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1728 const struct radv_image_view *iview,
1729 VkClearDepthStencilValue ds_clear_value)
1730 {
1731 VkImageSubresourceRange range = {
1732 .aspectMask = iview->aspect_mask,
1733 .baseMipLevel = iview->base_mip,
1734 .levelCount = iview->level_count,
1735 .baseArrayLayer = iview->base_layer,
1736 .layerCount = iview->layer_count,
1737 };
1738 uint32_t cond_val;
1739
1740 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1741 * depth clear value is 0.0f.
1742 */
1743 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1744
1745 radv_set_tc_compat_zrange_metadata(cmd_buffer, iview->image, &range,
1746 cond_val);
1747 }
1748
1749 /**
1750 * Update the clear depth/stencil values for this image.
1751 */
1752 void
1753 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1754 const struct radv_image_view *iview,
1755 VkClearDepthStencilValue ds_clear_value,
1756 VkImageAspectFlags aspects)
1757 {
1758 VkImageSubresourceRange range = {
1759 .aspectMask = iview->aspect_mask,
1760 .baseMipLevel = iview->base_mip,
1761 .levelCount = iview->level_count,
1762 .baseArrayLayer = iview->base_layer,
1763 .layerCount = iview->layer_count,
1764 };
1765 struct radv_image *image = iview->image;
1766
1767 assert(radv_image_has_htile(image));
1768
1769 radv_set_ds_clear_metadata(cmd_buffer, iview->image, &range,
1770 ds_clear_value, aspects);
1771
1772 if (radv_image_is_tc_compat_htile(image) &&
1773 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1774 radv_update_tc_compat_zrange_metadata(cmd_buffer, iview,
1775 ds_clear_value);
1776 }
1777
1778 radv_update_bound_fast_clear_ds(cmd_buffer, iview, ds_clear_value,
1779 aspects);
1780 }
1781
1782 /**
1783 * Load the clear depth/stencil values from the image's metadata.
1784 */
1785 static void
1786 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1787 const struct radv_image_view *iview)
1788 {
1789 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1790 const struct radv_image *image = iview->image;
1791 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1792 uint64_t va = radv_get_ds_clear_value_va(image, iview->base_mip);
1793 unsigned reg_offset = 0, reg_count = 0;
1794
1795 if (!radv_image_has_htile(image))
1796 return;
1797
1798 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1799 ++reg_count;
1800 } else {
1801 ++reg_offset;
1802 va += 4;
1803 }
1804 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1805 ++reg_count;
1806
1807 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1808
1809 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
1810 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1811 radeon_emit(cs, va);
1812 radeon_emit(cs, va >> 32);
1813 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1814 radeon_emit(cs, reg_count);
1815 } else {
1816 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1817 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1818 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1819 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1820 radeon_emit(cs, va);
1821 radeon_emit(cs, va >> 32);
1822 radeon_emit(cs, reg >> 2);
1823 radeon_emit(cs, 0);
1824
1825 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1826 radeon_emit(cs, 0);
1827 }
1828 }
1829
1830 /*
1831 * With DCC some colors don't require CMASK elimination before being
1832 * used as a texture. This sets a predicate value to determine if the
1833 * cmask eliminate is required.
1834 */
1835 void
1836 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1837 struct radv_image *image,
1838 const VkImageSubresourceRange *range, bool value)
1839 {
1840 uint64_t pred_val = value;
1841 uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
1842 uint32_t level_count = radv_get_levelCount(image, range);
1843 uint32_t count = 2 * level_count;
1844
1845 assert(radv_dcc_enabled(image, range->baseMipLevel));
1846
1847 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1848 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1849 S_370_WR_CONFIRM(1) |
1850 S_370_ENGINE_SEL(V_370_PFP));
1851 radeon_emit(cmd_buffer->cs, va);
1852 radeon_emit(cmd_buffer->cs, va >> 32);
1853
1854 for (uint32_t l = 0; l < level_count; l++) {
1855 radeon_emit(cmd_buffer->cs, pred_val);
1856 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1857 }
1858 }
1859
1860 /**
1861 * Update the DCC predicate to reflect the compression state.
1862 */
1863 void
1864 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1865 struct radv_image *image,
1866 const VkImageSubresourceRange *range, bool value)
1867 {
1868 uint64_t pred_val = value;
1869 uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
1870 uint32_t level_count = radv_get_levelCount(image, range);
1871 uint32_t count = 2 * level_count;
1872
1873 assert(radv_dcc_enabled(image, range->baseMipLevel));
1874
1875 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1876 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1877 S_370_WR_CONFIRM(1) |
1878 S_370_ENGINE_SEL(V_370_PFP));
1879 radeon_emit(cmd_buffer->cs, va);
1880 radeon_emit(cmd_buffer->cs, va >> 32);
1881
1882 for (uint32_t l = 0; l < level_count; l++) {
1883 radeon_emit(cmd_buffer->cs, pred_val);
1884 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1885 }
1886 }
1887
1888 /**
1889 * Update the fast clear color values if the image is bound as a color buffer.
1890 */
1891 static void
1892 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1893 struct radv_image *image,
1894 int cb_idx,
1895 uint32_t color_values[2])
1896 {
1897 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1898 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1899 uint32_t att_idx;
1900
1901 if (!cmd_buffer->state.attachments || !subpass)
1902 return;
1903
1904 att_idx = subpass->color_attachments[cb_idx].attachment;
1905 if (att_idx == VK_ATTACHMENT_UNUSED)
1906 return;
1907
1908 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1909 return;
1910
1911 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1912 radeon_emit(cs, color_values[0]);
1913 radeon_emit(cs, color_values[1]);
1914
1915 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1916 }
1917
1918 /**
1919 * Set the clear color values to the image's metadata.
1920 */
1921 static void
1922 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1923 struct radv_image *image,
1924 const VkImageSubresourceRange *range,
1925 uint32_t color_values[2])
1926 {
1927 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1928 uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
1929 uint32_t level_count = radv_get_levelCount(image, range);
1930 uint32_t count = 2 * level_count;
1931
1932 assert(radv_image_has_cmask(image) ||
1933 radv_dcc_enabled(image, range->baseMipLevel));
1934
1935 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
1936 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1937 S_370_WR_CONFIRM(1) |
1938 S_370_ENGINE_SEL(V_370_PFP));
1939 radeon_emit(cs, va);
1940 radeon_emit(cs, va >> 32);
1941
1942 for (uint32_t l = 0; l < level_count; l++) {
1943 radeon_emit(cs, color_values[0]);
1944 radeon_emit(cs, color_values[1]);
1945 }
1946 }
1947
1948 /**
1949 * Update the clear color values for this image.
1950 */
1951 void
1952 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1953 const struct radv_image_view *iview,
1954 int cb_idx,
1955 uint32_t color_values[2])
1956 {
1957 struct radv_image *image = iview->image;
1958 VkImageSubresourceRange range = {
1959 .aspectMask = iview->aspect_mask,
1960 .baseMipLevel = iview->base_mip,
1961 .levelCount = iview->level_count,
1962 .baseArrayLayer = iview->base_layer,
1963 .layerCount = iview->layer_count,
1964 };
1965
1966 assert(radv_image_has_cmask(image) ||
1967 radv_dcc_enabled(image, iview->base_mip));
1968
1969 radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
1970
1971 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1972 color_values);
1973 }
1974
1975 /**
1976 * Load the clear color values from the image's metadata.
1977 */
1978 static void
1979 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1980 struct radv_image_view *iview,
1981 int cb_idx)
1982 {
1983 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1984 struct radv_image *image = iview->image;
1985 uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
1986
1987 if (!radv_image_has_cmask(image) &&
1988 !radv_dcc_enabled(image, iview->base_mip))
1989 return;
1990
1991 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1992
1993 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
1994 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1995 radeon_emit(cs, va);
1996 radeon_emit(cs, va >> 32);
1997 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1998 radeon_emit(cs, 2);
1999 } else {
2000 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
2001 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2002 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2003 COPY_DATA_COUNT_SEL);
2004 radeon_emit(cs, va);
2005 radeon_emit(cs, va >> 32);
2006 radeon_emit(cs, reg >> 2);
2007 radeon_emit(cs, 0);
2008
2009 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
2010 radeon_emit(cs, 0);
2011 }
2012 }
2013
2014 static void
2015 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
2016 {
2017 int i;
2018 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
2019 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2020
2021 /* this may happen for inherited secondary recording */
2022 if (!framebuffer)
2023 return;
2024
2025 for (i = 0; i < 8; ++i) {
2026 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
2027 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2028 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2029 continue;
2030 }
2031
2032 int idx = subpass->color_attachments[i].attachment;
2033 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
2034 VkImageLayout layout = subpass->color_attachments[i].layout;
2035 bool in_render_loop = subpass->color_attachments[i].in_render_loop;
2036
2037 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, iview->bo);
2038
2039 assert(iview->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
2040 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
2041 radv_emit_fb_color_state(cmd_buffer, i, &cmd_buffer->state.attachments[idx].cb, iview, layout, in_render_loop);
2042
2043 radv_load_color_clear_metadata(cmd_buffer, iview, i);
2044 }
2045
2046 if (subpass->depth_stencil_attachment) {
2047 int idx = subpass->depth_stencil_attachment->attachment;
2048 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
2049 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
2050 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
2051 struct radv_image *image = iview->image;
2052 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, cmd_buffer->state.attachments[idx].iview->bo);
2053 ASSERTED uint32_t queue_mask = radv_image_queue_family_mask(image,
2054 cmd_buffer->queue_family_index,
2055 cmd_buffer->queue_family_index);
2056 /* We currently don't support writing decompressed HTILE */
2057 assert(radv_layout_has_htile(image, layout, in_render_loop, queue_mask) ==
2058 radv_layout_is_htile_compressed(image, layout, in_render_loop, queue_mask));
2059
2060 radv_emit_fb_ds_state(cmd_buffer, &cmd_buffer->state.attachments[idx].ds, iview, layout, in_render_loop);
2061
2062 if (cmd_buffer->state.attachments[idx].ds.offset_scale != cmd_buffer->state.offset_scale) {
2063 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2064 cmd_buffer->state.offset_scale = cmd_buffer->state.attachments[idx].ds.offset_scale;
2065 }
2066 radv_load_ds_clear_metadata(cmd_buffer, iview);
2067 } else {
2068 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9)
2069 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
2070 else
2071 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
2072
2073 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
2074 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
2075 }
2076 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2077 S_028208_BR_X(framebuffer->width) |
2078 S_028208_BR_Y(framebuffer->height));
2079
2080 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
2081 bool disable_constant_encode =
2082 cmd_buffer->device->physical_device->rad_info.has_dcc_constant_encode;
2083 enum chip_class chip_class =
2084 cmd_buffer->device->physical_device->rad_info.chip_class;
2085 uint8_t watermark = chip_class >= GFX10 ? 6 : 4;
2086
2087 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
2088 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class <= GFX9) |
2089 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
2090 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
2091 }
2092
2093 if (cmd_buffer->device->dfsm_allowed) {
2094 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2095 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
2096 }
2097
2098 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
2099 }
2100
2101 static void
2102 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer, bool indirect)
2103 {
2104 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2105 struct radv_cmd_state *state = &cmd_buffer->state;
2106
2107 if (state->index_type != state->last_index_type) {
2108 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2109 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2110 cs, R_03090C_VGT_INDEX_TYPE,
2111 2, state->index_type);
2112 } else {
2113 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2114 radeon_emit(cs, state->index_type);
2115 }
2116
2117 state->last_index_type = state->index_type;
2118 }
2119
2120 /* For the direct indexed draws we use DRAW_INDEX_2, which includes
2121 * the index_va and max_index_count already. */
2122 if (!indirect)
2123 return;
2124
2125 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2126 radeon_emit(cs, state->index_va);
2127 radeon_emit(cs, state->index_va >> 32);
2128
2129 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2130 radeon_emit(cs, state->max_index_count);
2131
2132 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
2133 }
2134
2135 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
2136 {
2137 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
2138 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2139 uint32_t pa_sc_mode_cntl_1 =
2140 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
2141 uint32_t db_count_control;
2142
2143 if(!cmd_buffer->state.active_occlusion_queries) {
2144 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2145 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2146 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2147 has_perfect_queries) {
2148 /* Re-enable out-of-order rasterization if the
2149 * bound pipeline supports it and if it's has
2150 * been disabled before starting any perfect
2151 * occlusion queries.
2152 */
2153 radeon_set_context_reg(cmd_buffer->cs,
2154 R_028A4C_PA_SC_MODE_CNTL_1,
2155 pa_sc_mode_cntl_1);
2156 }
2157 }
2158 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
2159 } else {
2160 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2161 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
2162 bool gfx10_perfect = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10 && has_perfect_queries;
2163
2164 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2165 db_count_control =
2166 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
2167 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
2168 S_028004_SAMPLE_RATE(sample_rate) |
2169 S_028004_ZPASS_ENABLE(1) |
2170 S_028004_SLICE_EVEN_ENABLE(1) |
2171 S_028004_SLICE_ODD_ENABLE(1);
2172
2173 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2174 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2175 has_perfect_queries) {
2176 /* If the bound pipeline has enabled
2177 * out-of-order rasterization, we should
2178 * disable it before starting any perfect
2179 * occlusion queries.
2180 */
2181 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
2182
2183 radeon_set_context_reg(cmd_buffer->cs,
2184 R_028A4C_PA_SC_MODE_CNTL_1,
2185 pa_sc_mode_cntl_1);
2186 }
2187 } else {
2188 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
2189 S_028004_SAMPLE_RATE(sample_rate);
2190 }
2191 }
2192
2193 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
2194
2195 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2196 }
2197
2198 static void
2199 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
2200 {
2201 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
2202
2203 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
2204 radv_emit_viewport(cmd_buffer);
2205
2206 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
2207 !cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
2208 radv_emit_scissor(cmd_buffer);
2209
2210 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
2211 radv_emit_line_width(cmd_buffer);
2212
2213 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
2214 radv_emit_blend_constants(cmd_buffer);
2215
2216 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
2217 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
2218 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
2219 radv_emit_stencil(cmd_buffer);
2220
2221 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
2222 radv_emit_depth_bounds(cmd_buffer);
2223
2224 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
2225 radv_emit_depth_bias(cmd_buffer);
2226
2227 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
2228 radv_emit_discard_rectangle(cmd_buffer);
2229
2230 if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)
2231 radv_emit_sample_locations(cmd_buffer);
2232
2233 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE)
2234 radv_emit_line_stipple(cmd_buffer);
2235
2236 cmd_buffer->state.dirty &= ~states;
2237 }
2238
2239 static void
2240 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
2241 VkPipelineBindPoint bind_point)
2242 {
2243 struct radv_descriptor_state *descriptors_state =
2244 radv_get_descriptors_state(cmd_buffer, bind_point);
2245 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
2246 unsigned bo_offset;
2247
2248 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
2249 set->mapped_ptr,
2250 &bo_offset))
2251 return;
2252
2253 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2254 set->va += bo_offset;
2255 }
2256
2257 static void
2258 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
2259 VkPipelineBindPoint bind_point)
2260 {
2261 struct radv_descriptor_state *descriptors_state =
2262 radv_get_descriptors_state(cmd_buffer, bind_point);
2263 uint32_t size = MAX_SETS * 4;
2264 uint32_t offset;
2265 void *ptr;
2266
2267 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
2268 256, &offset, &ptr))
2269 return;
2270
2271 for (unsigned i = 0; i < MAX_SETS; i++) {
2272 uint32_t *uptr = ((uint32_t *)ptr) + i;
2273 uint64_t set_va = 0;
2274 struct radv_descriptor_set *set = descriptors_state->sets[i];
2275 if (descriptors_state->valid & (1u << i))
2276 set_va = set->va;
2277 uptr[0] = set_va & 0xffffffff;
2278 }
2279
2280 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2281 va += offset;
2282
2283 if (cmd_buffer->state.pipeline) {
2284 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
2285 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2286 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2287
2288 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
2289 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
2290 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2291
2292 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
2293 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2294 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2295
2296 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2297 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
2298 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2299
2300 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2301 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
2302 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2303 }
2304
2305 if (cmd_buffer->state.compute_pipeline)
2306 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
2307 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2308 }
2309
2310 static void
2311 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
2312 VkShaderStageFlags stages)
2313 {
2314 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2315 VK_PIPELINE_BIND_POINT_COMPUTE :
2316 VK_PIPELINE_BIND_POINT_GRAPHICS;
2317 struct radv_descriptor_state *descriptors_state =
2318 radv_get_descriptors_state(cmd_buffer, bind_point);
2319 struct radv_cmd_state *state = &cmd_buffer->state;
2320 bool flush_indirect_descriptors;
2321
2322 if (!descriptors_state->dirty)
2323 return;
2324
2325 if (descriptors_state->push_dirty)
2326 radv_flush_push_descriptors(cmd_buffer, bind_point);
2327
2328 flush_indirect_descriptors =
2329 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
2330 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
2331 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
2332 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
2333
2334 if (flush_indirect_descriptors)
2335 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
2336
2337 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2338 cmd_buffer->cs,
2339 MAX_SETS * MESA_SHADER_STAGES * 4);
2340
2341 if (cmd_buffer->state.pipeline) {
2342 radv_foreach_stage(stage, stages) {
2343 if (!cmd_buffer->state.pipeline->shaders[stage])
2344 continue;
2345
2346 radv_emit_descriptor_pointers(cmd_buffer,
2347 cmd_buffer->state.pipeline,
2348 descriptors_state, stage);
2349 }
2350 }
2351
2352 if (cmd_buffer->state.compute_pipeline &&
2353 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
2354 radv_emit_descriptor_pointers(cmd_buffer,
2355 cmd_buffer->state.compute_pipeline,
2356 descriptors_state,
2357 MESA_SHADER_COMPUTE);
2358 }
2359
2360 descriptors_state->dirty = 0;
2361 descriptors_state->push_dirty = false;
2362
2363 assert(cmd_buffer->cs->cdw <= cdw_max);
2364
2365 if (unlikely(cmd_buffer->device->trace_bo))
2366 radv_save_descriptors(cmd_buffer, bind_point);
2367 }
2368
2369 static void
2370 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
2371 VkShaderStageFlags stages)
2372 {
2373 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
2374 ? cmd_buffer->state.compute_pipeline
2375 : cmd_buffer->state.pipeline;
2376 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2377 VK_PIPELINE_BIND_POINT_COMPUTE :
2378 VK_PIPELINE_BIND_POINT_GRAPHICS;
2379 struct radv_descriptor_state *descriptors_state =
2380 radv_get_descriptors_state(cmd_buffer, bind_point);
2381 struct radv_pipeline_layout *layout = pipeline->layout;
2382 struct radv_shader_variant *shader, *prev_shader;
2383 bool need_push_constants = false;
2384 unsigned offset;
2385 void *ptr;
2386 uint64_t va;
2387
2388 stages &= cmd_buffer->push_constant_stages;
2389 if (!stages ||
2390 (!layout->push_constant_size && !layout->dynamic_offset_count))
2391 return;
2392
2393 radv_foreach_stage(stage, stages) {
2394 shader = radv_get_shader(pipeline, stage);
2395 if (!shader)
2396 continue;
2397
2398 need_push_constants |= shader->info.loads_push_constants;
2399 need_push_constants |= shader->info.loads_dynamic_offsets;
2400
2401 uint8_t base = shader->info.base_inline_push_consts;
2402 uint8_t count = shader->info.num_inline_push_consts;
2403
2404 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
2405 AC_UD_INLINE_PUSH_CONSTANTS,
2406 count,
2407 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
2408 }
2409
2410 if (need_push_constants) {
2411 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
2412 16 * layout->dynamic_offset_count,
2413 256, &offset, &ptr))
2414 return;
2415
2416 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
2417 memcpy((char*)ptr + layout->push_constant_size,
2418 descriptors_state->dynamic_buffers,
2419 16 * layout->dynamic_offset_count);
2420
2421 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2422 va += offset;
2423
2424 ASSERTED unsigned cdw_max =
2425 radeon_check_space(cmd_buffer->device->ws,
2426 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
2427
2428 prev_shader = NULL;
2429 radv_foreach_stage(stage, stages) {
2430 shader = radv_get_shader(pipeline, stage);
2431
2432 /* Avoid redundantly emitting the address for merged stages. */
2433 if (shader && shader != prev_shader) {
2434 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
2435 AC_UD_PUSH_CONSTANTS, va);
2436
2437 prev_shader = shader;
2438 }
2439 }
2440 assert(cmd_buffer->cs->cdw <= cdw_max);
2441 }
2442
2443 cmd_buffer->push_constant_stages &= ~stages;
2444 }
2445
2446 static void
2447 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
2448 bool pipeline_is_dirty)
2449 {
2450 if ((pipeline_is_dirty ||
2451 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
2452 cmd_buffer->state.pipeline->num_vertex_bindings &&
2453 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.has_vertex_buffers) {
2454 unsigned vb_offset;
2455 void *vb_ptr;
2456 uint32_t i = 0;
2457 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
2458 uint64_t va;
2459
2460 /* allocate some descriptor state for vertex buffers */
2461 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2462 &vb_offset, &vb_ptr))
2463 return;
2464
2465 for (i = 0; i < count; i++) {
2466 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2467 uint32_t offset;
2468 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2469 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[i];
2470 unsigned num_records;
2471
2472 if (!buffer)
2473 continue;
2474
2475 va = radv_buffer_get_va(buffer->bo);
2476
2477 offset = cmd_buffer->vertex_bindings[i].offset;
2478 va += offset + buffer->offset;
2479
2480 num_records = buffer->size - offset;
2481 if (cmd_buffer->device->physical_device->rad_info.chip_class != GFX8 && stride)
2482 num_records /= stride;
2483
2484 desc[0] = va;
2485 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2486 desc[2] = num_records;
2487 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2488 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2489 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2490 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2491
2492 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2493 /* OOB_SELECT chooses the out-of-bounds check:
2494 * - 1: index >= NUM_RECORDS (Structured)
2495 * - 3: offset >= NUM_RECORDS (Raw)
2496 */
2497 int oob_select = stride ? V_008F0C_OOB_SELECT_STRUCTURED : V_008F0C_OOB_SELECT_RAW;
2498
2499 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT) |
2500 S_008F0C_OOB_SELECT(oob_select) |
2501 S_008F0C_RESOURCE_LEVEL(1);
2502 } else {
2503 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2504 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2505 }
2506 }
2507
2508 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2509 va += vb_offset;
2510
2511 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2512 AC_UD_VS_VERTEX_BUFFERS, va);
2513
2514 cmd_buffer->state.vb_va = va;
2515 cmd_buffer->state.vb_size = count * 16;
2516 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2517 }
2518 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2519 }
2520
2521 static void
2522 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2523 {
2524 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2525 struct radv_userdata_info *loc;
2526 uint32_t base_reg;
2527
2528 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2529 if (!radv_get_shader(pipeline, stage))
2530 continue;
2531
2532 loc = radv_lookup_user_sgpr(pipeline, stage,
2533 AC_UD_STREAMOUT_BUFFERS);
2534 if (loc->sgpr_idx == -1)
2535 continue;
2536
2537 base_reg = pipeline->user_data_0[stage];
2538
2539 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2540 base_reg + loc->sgpr_idx * 4, va, false);
2541 }
2542
2543 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
2544 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2545 if (loc->sgpr_idx != -1) {
2546 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2547
2548 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2549 base_reg + loc->sgpr_idx * 4, va, false);
2550 }
2551 }
2552 }
2553
2554 static void
2555 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2556 {
2557 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2558 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2559 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2560 unsigned so_offset;
2561 void *so_ptr;
2562 uint64_t va;
2563
2564 /* Allocate some descriptor state for streamout buffers. */
2565 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2566 MAX_SO_BUFFERS * 16, 256,
2567 &so_offset, &so_ptr))
2568 return;
2569
2570 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2571 struct radv_buffer *buffer = sb[i].buffer;
2572 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2573
2574 if (!(so->enabled_mask & (1 << i)))
2575 continue;
2576
2577 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2578
2579 va += sb[i].offset;
2580
2581 /* Set the descriptor.
2582 *
2583 * On GFX8, the format must be non-INVALID, otherwise
2584 * the buffer will be considered not bound and store
2585 * instructions will be no-ops.
2586 */
2587 uint32_t size = 0xffffffff;
2588
2589 /* Compute the correct buffer size for NGG streamout
2590 * because it's used to determine the max emit per
2591 * buffer.
2592 */
2593 if (cmd_buffer->device->physical_device->use_ngg_streamout)
2594 size = buffer->size - sb[i].offset;
2595
2596 desc[0] = va;
2597 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2598 desc[2] = size;
2599 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2600 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2601 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2602 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2603
2604 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2605 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2606 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
2607 S_008F0C_RESOURCE_LEVEL(1);
2608 } else {
2609 desc[3] |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2610 }
2611 }
2612
2613 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2614 va += so_offset;
2615
2616 radv_emit_streamout_buffers(cmd_buffer, va);
2617 }
2618
2619 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2620 }
2621
2622 static void
2623 radv_flush_ngg_gs_state(struct radv_cmd_buffer *cmd_buffer)
2624 {
2625 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2626 struct radv_userdata_info *loc;
2627 uint32_t ngg_gs_state = 0;
2628 uint32_t base_reg;
2629
2630 if (!radv_pipeline_has_gs(pipeline) ||
2631 !radv_pipeline_has_ngg(pipeline))
2632 return;
2633
2634 /* By default NGG GS queries are disabled but they are enabled if the
2635 * command buffer has active GDS queries or if it's a secondary command
2636 * buffer that inherits the number of generated primitives.
2637 */
2638 if (cmd_buffer->state.active_pipeline_gds_queries ||
2639 (cmd_buffer->state.inherited_pipeline_statistics & VK_QUERY_PIPELINE_STATISTIC_GEOMETRY_SHADER_PRIMITIVES_BIT))
2640 ngg_gs_state = 1;
2641
2642 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_GEOMETRY,
2643 AC_UD_NGG_GS_STATE);
2644 base_reg = pipeline->user_data_0[MESA_SHADER_GEOMETRY];
2645 assert(loc->sgpr_idx != -1);
2646
2647 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
2648 ngg_gs_state);
2649 }
2650
2651 static void
2652 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2653 {
2654 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2655 radv_flush_streamout_descriptors(cmd_buffer);
2656 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2657 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2658 radv_flush_ngg_gs_state(cmd_buffer);
2659 }
2660
2661 struct radv_draw_info {
2662 /**
2663 * Number of vertices.
2664 */
2665 uint32_t count;
2666
2667 /**
2668 * Index of the first vertex.
2669 */
2670 int32_t vertex_offset;
2671
2672 /**
2673 * First instance id.
2674 */
2675 uint32_t first_instance;
2676
2677 /**
2678 * Number of instances.
2679 */
2680 uint32_t instance_count;
2681
2682 /**
2683 * First index (indexed draws only).
2684 */
2685 uint32_t first_index;
2686
2687 /**
2688 * Whether it's an indexed draw.
2689 */
2690 bool indexed;
2691
2692 /**
2693 * Indirect draw parameters resource.
2694 */
2695 struct radv_buffer *indirect;
2696 uint64_t indirect_offset;
2697 uint32_t stride;
2698
2699 /**
2700 * Draw count parameters resource.
2701 */
2702 struct radv_buffer *count_buffer;
2703 uint64_t count_buffer_offset;
2704
2705 /**
2706 * Stream output parameters resource.
2707 */
2708 struct radv_buffer *strmout_buffer;
2709 uint64_t strmout_buffer_offset;
2710 };
2711
2712 static uint32_t
2713 radv_get_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
2714 {
2715 switch (cmd_buffer->state.index_type) {
2716 case V_028A7C_VGT_INDEX_8:
2717 return 0xffu;
2718 case V_028A7C_VGT_INDEX_16:
2719 return 0xffffu;
2720 case V_028A7C_VGT_INDEX_32:
2721 return 0xffffffffu;
2722 default:
2723 unreachable("invalid index type");
2724 }
2725 }
2726
2727 static void
2728 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
2729 bool instanced_draw, bool indirect_draw,
2730 bool count_from_stream_output,
2731 uint32_t draw_vertex_count)
2732 {
2733 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2734 struct radv_cmd_state *state = &cmd_buffer->state;
2735 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2736 unsigned ia_multi_vgt_param;
2737
2738 ia_multi_vgt_param =
2739 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
2740 indirect_draw,
2741 count_from_stream_output,
2742 draw_vertex_count);
2743
2744 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2745 if (info->chip_class == GFX9) {
2746 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2747 cs,
2748 R_030960_IA_MULTI_VGT_PARAM,
2749 4, ia_multi_vgt_param);
2750 } else if (info->chip_class >= GFX7) {
2751 radeon_set_context_reg_idx(cs,
2752 R_028AA8_IA_MULTI_VGT_PARAM,
2753 1, ia_multi_vgt_param);
2754 } else {
2755 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2756 ia_multi_vgt_param);
2757 }
2758 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2759 }
2760 }
2761
2762 static void
2763 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2764 const struct radv_draw_info *draw_info)
2765 {
2766 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2767 struct radv_cmd_state *state = &cmd_buffer->state;
2768 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2769 int32_t primitive_reset_en;
2770
2771 /* Draw state. */
2772 if (info->chip_class < GFX10) {
2773 si_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2774 draw_info->indirect,
2775 !!draw_info->strmout_buffer,
2776 draw_info->indirect ? 0 : draw_info->count);
2777 }
2778
2779 /* Primitive restart. */
2780 primitive_reset_en =
2781 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2782
2783 if (primitive_reset_en != state->last_primitive_reset_en) {
2784 state->last_primitive_reset_en = primitive_reset_en;
2785 if (info->chip_class >= GFX9) {
2786 radeon_set_uconfig_reg(cs,
2787 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2788 primitive_reset_en);
2789 } else {
2790 radeon_set_context_reg(cs,
2791 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2792 primitive_reset_en);
2793 }
2794 }
2795
2796 if (primitive_reset_en) {
2797 uint32_t primitive_reset_index =
2798 radv_get_primitive_reset_index(cmd_buffer);
2799
2800 if (primitive_reset_index != state->last_primitive_reset_index) {
2801 radeon_set_context_reg(cs,
2802 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2803 primitive_reset_index);
2804 state->last_primitive_reset_index = primitive_reset_index;
2805 }
2806 }
2807
2808 if (draw_info->strmout_buffer) {
2809 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2810
2811 va += draw_info->strmout_buffer->offset +
2812 draw_info->strmout_buffer_offset;
2813
2814 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2815 draw_info->stride);
2816
2817 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2818 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2819 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2820 COPY_DATA_WR_CONFIRM);
2821 radeon_emit(cs, va);
2822 radeon_emit(cs, va >> 32);
2823 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2824 radeon_emit(cs, 0); /* unused */
2825
2826 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2827 }
2828 }
2829
2830 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2831 VkPipelineStageFlags src_stage_mask)
2832 {
2833 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2834 VK_PIPELINE_STAGE_TRANSFER_BIT |
2835 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2836 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2837 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2838 }
2839
2840 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2841 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2842 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2843 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2844 VK_PIPELINE_STAGE_TRANSFER_BIT |
2845 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2846 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2847 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2848 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2849 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2850 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2851 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2852 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2853 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2854 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2855 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2856 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2857 }
2858 }
2859
2860 static enum radv_cmd_flush_bits
2861 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2862 VkAccessFlags src_flags,
2863 struct radv_image *image)
2864 {
2865 bool flush_CB_meta = true, flush_DB_meta = true;
2866 enum radv_cmd_flush_bits flush_bits = 0;
2867 uint32_t b;
2868
2869 if (image) {
2870 if (!radv_image_has_CB_metadata(image))
2871 flush_CB_meta = false;
2872 if (!radv_image_has_htile(image))
2873 flush_DB_meta = false;
2874 }
2875
2876 for_each_bit(b, src_flags) {
2877 switch ((VkAccessFlagBits)(1 << b)) {
2878 case VK_ACCESS_SHADER_WRITE_BIT:
2879 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2880 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2881 flush_bits |= RADV_CMD_FLAG_WB_L2;
2882 break;
2883 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2884 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2885 if (flush_CB_meta)
2886 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2887 break;
2888 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2889 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2890 if (flush_DB_meta)
2891 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2892 break;
2893 case VK_ACCESS_TRANSFER_WRITE_BIT:
2894 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2895 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2896 RADV_CMD_FLAG_INV_L2;
2897
2898 if (flush_CB_meta)
2899 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2900 if (flush_DB_meta)
2901 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2902 break;
2903 default:
2904 break;
2905 }
2906 }
2907 return flush_bits;
2908 }
2909
2910 static enum radv_cmd_flush_bits
2911 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2912 VkAccessFlags dst_flags,
2913 struct radv_image *image)
2914 {
2915 bool flush_CB_meta = true, flush_DB_meta = true;
2916 enum radv_cmd_flush_bits flush_bits = 0;
2917 bool flush_CB = true, flush_DB = true;
2918 bool image_is_coherent = false;
2919 uint32_t b;
2920
2921 if (image) {
2922 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2923 flush_CB = false;
2924 flush_DB = false;
2925 }
2926
2927 if (!radv_image_has_CB_metadata(image))
2928 flush_CB_meta = false;
2929 if (!radv_image_has_htile(image))
2930 flush_DB_meta = false;
2931
2932 /* TODO: implement shader coherent for GFX10 */
2933
2934 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
2935 if (image->info.samples == 1 &&
2936 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2937 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2938 !vk_format_is_stencil(image->vk_format)) {
2939 /* Single-sample color and single-sample depth
2940 * (not stencil) are coherent with shaders on
2941 * GFX9.
2942 */
2943 image_is_coherent = true;
2944 }
2945 }
2946 }
2947
2948 for_each_bit(b, dst_flags) {
2949 switch ((VkAccessFlagBits)(1 << b)) {
2950 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2951 case VK_ACCESS_INDEX_READ_BIT:
2952 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2953 break;
2954 case VK_ACCESS_UNIFORM_READ_BIT:
2955 flush_bits |= RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_SCACHE;
2956 break;
2957 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2958 case VK_ACCESS_TRANSFER_READ_BIT:
2959 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2960 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
2961 RADV_CMD_FLAG_INV_L2;
2962 break;
2963 case VK_ACCESS_SHADER_READ_BIT:
2964 flush_bits |= RADV_CMD_FLAG_INV_VCACHE;
2965 /* Unlike LLVM, ACO uses SMEM for SSBOs and we have to
2966 * invalidate the scalar cache. */
2967 if (cmd_buffer->device->physical_device->use_aco &&
2968 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8)
2969 flush_bits |= RADV_CMD_FLAG_INV_SCACHE;
2970
2971 if (!image_is_coherent)
2972 flush_bits |= RADV_CMD_FLAG_INV_L2;
2973 break;
2974 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2975 if (flush_CB)
2976 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2977 if (flush_CB_meta)
2978 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2979 break;
2980 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2981 if (flush_DB)
2982 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2983 if (flush_DB_meta)
2984 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2985 break;
2986 default:
2987 break;
2988 }
2989 }
2990 return flush_bits;
2991 }
2992
2993 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2994 const struct radv_subpass_barrier *barrier)
2995 {
2996 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2997 NULL);
2998 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2999 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
3000 NULL);
3001 }
3002
3003 uint32_t
3004 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
3005 {
3006 struct radv_cmd_state *state = &cmd_buffer->state;
3007 uint32_t subpass_id = state->subpass - state->pass->subpasses;
3008
3009 /* The id of this subpass shouldn't exceed the number of subpasses in
3010 * this render pass minus 1.
3011 */
3012 assert(subpass_id < state->pass->subpass_count);
3013 return subpass_id;
3014 }
3015
3016 static struct radv_sample_locations_state *
3017 radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer,
3018 uint32_t att_idx,
3019 bool begin_subpass)
3020 {
3021 struct radv_cmd_state *state = &cmd_buffer->state;
3022 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
3023 struct radv_image_view *view = state->attachments[att_idx].iview;
3024
3025 if (view->image->info.samples == 1)
3026 return NULL;
3027
3028 if (state->pass->attachments[att_idx].first_subpass_idx == subpass_id) {
3029 /* Return the initial sample locations if this is the initial
3030 * layout transition of the given subpass attachemnt.
3031 */
3032 if (state->attachments[att_idx].sample_location.count > 0)
3033 return &state->attachments[att_idx].sample_location;
3034 } else {
3035 /* Otherwise return the subpass sample locations if defined. */
3036 if (state->subpass_sample_locs) {
3037 /* Because the driver sets the current subpass before
3038 * initial layout transitions, we should use the sample
3039 * locations from the previous subpass to avoid an
3040 * off-by-one problem. Otherwise, use the sample
3041 * locations for the current subpass for final layout
3042 * transitions.
3043 */
3044 if (begin_subpass)
3045 subpass_id--;
3046
3047 for (uint32_t i = 0; i < state->num_subpass_sample_locs; i++) {
3048 if (state->subpass_sample_locs[i].subpass_idx == subpass_id)
3049 return &state->subpass_sample_locs[i].sample_location;
3050 }
3051 }
3052 }
3053
3054 return NULL;
3055 }
3056
3057 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
3058 struct radv_subpass_attachment att,
3059 bool begin_subpass)
3060 {
3061 unsigned idx = att.attachment;
3062 struct radv_image_view *view = cmd_buffer->state.attachments[idx].iview;
3063 struct radv_sample_locations_state *sample_locs;
3064 VkImageSubresourceRange range;
3065 range.aspectMask = view->aspect_mask;
3066 range.baseMipLevel = view->base_mip;
3067 range.levelCount = 1;
3068 range.baseArrayLayer = view->base_layer;
3069 range.layerCount = cmd_buffer->state.framebuffer->layers;
3070
3071 if (cmd_buffer->state.subpass->view_mask) {
3072 /* If the current subpass uses multiview, the driver might have
3073 * performed a fast color/depth clear to the whole image
3074 * (including all layers). To make sure the driver will
3075 * decompress the image correctly (if needed), we have to
3076 * account for the "real" number of layers. If the view mask is
3077 * sparse, this will decompress more layers than needed.
3078 */
3079 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
3080 }
3081
3082 /* Get the subpass sample locations for the given attachment, if NULL
3083 * is returned the driver will use the default HW locations.
3084 */
3085 sample_locs = radv_get_attachment_sample_locations(cmd_buffer, idx,
3086 begin_subpass);
3087
3088 /* Determine if the subpass uses separate depth/stencil layouts. */
3089 bool uses_separate_depth_stencil_layouts = false;
3090 if ((cmd_buffer->state.attachments[idx].current_layout !=
3091 cmd_buffer->state.attachments[idx].current_stencil_layout) ||
3092 (att.layout != att.stencil_layout)) {
3093 uses_separate_depth_stencil_layouts = true;
3094 }
3095
3096 /* For separate layouts, perform depth and stencil transitions
3097 * separately.
3098 */
3099 if (uses_separate_depth_stencil_layouts &&
3100 (range.aspectMask == (VK_IMAGE_ASPECT_DEPTH_BIT |
3101 VK_IMAGE_ASPECT_STENCIL_BIT))) {
3102 /* Depth-only transitions. */
3103 range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3104 radv_handle_image_transition(cmd_buffer,
3105 view->image,
3106 cmd_buffer->state.attachments[idx].current_layout,
3107 cmd_buffer->state.attachments[idx].current_in_render_loop,
3108 att.layout, att.in_render_loop,
3109 0, 0, &range, sample_locs);
3110
3111 /* Stencil-only transitions. */
3112 range.aspectMask = VK_IMAGE_ASPECT_STENCIL_BIT;
3113 radv_handle_image_transition(cmd_buffer,
3114 view->image,
3115 cmd_buffer->state.attachments[idx].current_stencil_layout,
3116 cmd_buffer->state.attachments[idx].current_in_render_loop,
3117 att.stencil_layout, att.in_render_loop,
3118 0, 0, &range, sample_locs);
3119 } else {
3120 radv_handle_image_transition(cmd_buffer,
3121 view->image,
3122 cmd_buffer->state.attachments[idx].current_layout,
3123 cmd_buffer->state.attachments[idx].current_in_render_loop,
3124 att.layout, att.in_render_loop,
3125 0, 0, &range, sample_locs);
3126 }
3127
3128 cmd_buffer->state.attachments[idx].current_layout = att.layout;
3129 cmd_buffer->state.attachments[idx].current_stencil_layout = att.stencil_layout;
3130 cmd_buffer->state.attachments[idx].current_in_render_loop = att.in_render_loop;
3131
3132
3133 }
3134
3135 void
3136 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
3137 const struct radv_subpass *subpass)
3138 {
3139 cmd_buffer->state.subpass = subpass;
3140
3141 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
3142 }
3143
3144 static VkResult
3145 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
3146 struct radv_render_pass *pass,
3147 const VkRenderPassBeginInfo *info)
3148 {
3149 const struct VkRenderPassSampleLocationsBeginInfoEXT *sample_locs =
3150 vk_find_struct_const(info->pNext,
3151 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT);
3152 struct radv_cmd_state *state = &cmd_buffer->state;
3153
3154 if (!sample_locs) {
3155 state->subpass_sample_locs = NULL;
3156 return VK_SUCCESS;
3157 }
3158
3159 for (uint32_t i = 0; i < sample_locs->attachmentInitialSampleLocationsCount; i++) {
3160 const VkAttachmentSampleLocationsEXT *att_sample_locs =
3161 &sample_locs->pAttachmentInitialSampleLocations[i];
3162 uint32_t att_idx = att_sample_locs->attachmentIndex;
3163 struct radv_image *image = cmd_buffer->state.attachments[att_idx].iview->image;
3164
3165 assert(vk_format_is_depth_or_stencil(image->vk_format));
3166
3167 /* From the Vulkan spec 1.1.108:
3168 *
3169 * "If the image referenced by the framebuffer attachment at
3170 * index attachmentIndex was not created with
3171 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
3172 * then the values specified in sampleLocationsInfo are
3173 * ignored."
3174 */
3175 if (!(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT))
3176 continue;
3177
3178 const VkSampleLocationsInfoEXT *sample_locs_info =
3179 &att_sample_locs->sampleLocationsInfo;
3180
3181 state->attachments[att_idx].sample_location.per_pixel =
3182 sample_locs_info->sampleLocationsPerPixel;
3183 state->attachments[att_idx].sample_location.grid_size =
3184 sample_locs_info->sampleLocationGridSize;
3185 state->attachments[att_idx].sample_location.count =
3186 sample_locs_info->sampleLocationsCount;
3187 typed_memcpy(&state->attachments[att_idx].sample_location.locations[0],
3188 sample_locs_info->pSampleLocations,
3189 sample_locs_info->sampleLocationsCount);
3190 }
3191
3192 state->subpass_sample_locs = vk_alloc(&cmd_buffer->pool->alloc,
3193 sample_locs->postSubpassSampleLocationsCount *
3194 sizeof(state->subpass_sample_locs[0]),
3195 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3196 if (state->subpass_sample_locs == NULL) {
3197 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3198 return cmd_buffer->record_result;
3199 }
3200
3201 state->num_subpass_sample_locs = sample_locs->postSubpassSampleLocationsCount;
3202
3203 for (uint32_t i = 0; i < sample_locs->postSubpassSampleLocationsCount; i++) {
3204 const VkSubpassSampleLocationsEXT *subpass_sample_locs_info =
3205 &sample_locs->pPostSubpassSampleLocations[i];
3206 const VkSampleLocationsInfoEXT *sample_locs_info =
3207 &subpass_sample_locs_info->sampleLocationsInfo;
3208
3209 state->subpass_sample_locs[i].subpass_idx =
3210 subpass_sample_locs_info->subpassIndex;
3211 state->subpass_sample_locs[i].sample_location.per_pixel =
3212 sample_locs_info->sampleLocationsPerPixel;
3213 state->subpass_sample_locs[i].sample_location.grid_size =
3214 sample_locs_info->sampleLocationGridSize;
3215 state->subpass_sample_locs[i].sample_location.count =
3216 sample_locs_info->sampleLocationsCount;
3217 typed_memcpy(&state->subpass_sample_locs[i].sample_location.locations[0],
3218 sample_locs_info->pSampleLocations,
3219 sample_locs_info->sampleLocationsCount);
3220 }
3221
3222 return VK_SUCCESS;
3223 }
3224
3225 static VkResult
3226 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
3227 struct radv_render_pass *pass,
3228 const VkRenderPassBeginInfo *info)
3229 {
3230 struct radv_cmd_state *state = &cmd_buffer->state;
3231 const struct VkRenderPassAttachmentBeginInfo *attachment_info = NULL;
3232
3233 if (info) {
3234 attachment_info = vk_find_struct_const(info->pNext,
3235 RENDER_PASS_ATTACHMENT_BEGIN_INFO);
3236 }
3237
3238
3239 if (pass->attachment_count == 0) {
3240 state->attachments = NULL;
3241 return VK_SUCCESS;
3242 }
3243
3244 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
3245 pass->attachment_count *
3246 sizeof(state->attachments[0]),
3247 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3248 if (state->attachments == NULL) {
3249 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3250 return cmd_buffer->record_result;
3251 }
3252
3253 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
3254 struct radv_render_pass_attachment *att = &pass->attachments[i];
3255 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
3256 VkImageAspectFlags clear_aspects = 0;
3257
3258 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
3259 /* color attachment */
3260 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3261 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
3262 }
3263 } else {
3264 /* depthstencil attachment */
3265 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
3266 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3267 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
3268 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3269 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
3270 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3271 }
3272 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3273 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3274 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3275 }
3276 }
3277
3278 state->attachments[i].pending_clear_aspects = clear_aspects;
3279 state->attachments[i].cleared_views = 0;
3280 if (clear_aspects && info) {
3281 assert(info->clearValueCount > i);
3282 state->attachments[i].clear_value = info->pClearValues[i];
3283 }
3284
3285 state->attachments[i].current_layout = att->initial_layout;
3286 state->attachments[i].current_stencil_layout = att->stencil_initial_layout;
3287 state->attachments[i].sample_location.count = 0;
3288
3289 struct radv_image_view *iview;
3290 if (attachment_info && attachment_info->attachmentCount > i) {
3291 iview = radv_image_view_from_handle(attachment_info->pAttachments[i]);
3292 } else {
3293 iview = state->framebuffer->attachments[i];
3294 }
3295
3296 state->attachments[i].iview = iview;
3297 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3298 radv_initialise_ds_surface(cmd_buffer->device, &state->attachments[i].ds, iview);
3299 } else {
3300 radv_initialise_color_surface(cmd_buffer->device, &state->attachments[i].cb, iview);
3301 }
3302 }
3303
3304 return VK_SUCCESS;
3305 }
3306
3307 VkResult radv_AllocateCommandBuffers(
3308 VkDevice _device,
3309 const VkCommandBufferAllocateInfo *pAllocateInfo,
3310 VkCommandBuffer *pCommandBuffers)
3311 {
3312 RADV_FROM_HANDLE(radv_device, device, _device);
3313 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
3314
3315 VkResult result = VK_SUCCESS;
3316 uint32_t i;
3317
3318 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
3319
3320 if (!list_is_empty(&pool->free_cmd_buffers)) {
3321 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
3322
3323 list_del(&cmd_buffer->pool_link);
3324 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
3325
3326 result = radv_reset_cmd_buffer(cmd_buffer);
3327 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
3328 cmd_buffer->level = pAllocateInfo->level;
3329
3330 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
3331 } else {
3332 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
3333 &pCommandBuffers[i]);
3334 }
3335 if (result != VK_SUCCESS)
3336 break;
3337 }
3338
3339 if (result != VK_SUCCESS) {
3340 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
3341 i, pCommandBuffers);
3342
3343 /* From the Vulkan 1.0.66 spec:
3344 *
3345 * "vkAllocateCommandBuffers can be used to create multiple
3346 * command buffers. If the creation of any of those command
3347 * buffers fails, the implementation must destroy all
3348 * successfully created command buffer objects from this
3349 * command, set all entries of the pCommandBuffers array to
3350 * NULL and return the error."
3351 */
3352 memset(pCommandBuffers, 0,
3353 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
3354 }
3355
3356 return result;
3357 }
3358
3359 void radv_FreeCommandBuffers(
3360 VkDevice device,
3361 VkCommandPool commandPool,
3362 uint32_t commandBufferCount,
3363 const VkCommandBuffer *pCommandBuffers)
3364 {
3365 for (uint32_t i = 0; i < commandBufferCount; i++) {
3366 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
3367
3368 if (cmd_buffer) {
3369 if (cmd_buffer->pool) {
3370 list_del(&cmd_buffer->pool_link);
3371 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
3372 } else
3373 radv_cmd_buffer_destroy(cmd_buffer);
3374
3375 }
3376 }
3377 }
3378
3379 VkResult radv_ResetCommandBuffer(
3380 VkCommandBuffer commandBuffer,
3381 VkCommandBufferResetFlags flags)
3382 {
3383 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3384 return radv_reset_cmd_buffer(cmd_buffer);
3385 }
3386
3387 VkResult radv_BeginCommandBuffer(
3388 VkCommandBuffer commandBuffer,
3389 const VkCommandBufferBeginInfo *pBeginInfo)
3390 {
3391 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3392 VkResult result = VK_SUCCESS;
3393
3394 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
3395 /* If the command buffer has already been resetted with
3396 * vkResetCommandBuffer, no need to do it again.
3397 */
3398 result = radv_reset_cmd_buffer(cmd_buffer);
3399 if (result != VK_SUCCESS)
3400 return result;
3401 }
3402
3403 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
3404 cmd_buffer->state.last_primitive_reset_en = -1;
3405 cmd_buffer->state.last_index_type = -1;
3406 cmd_buffer->state.last_num_instances = -1;
3407 cmd_buffer->state.last_vertex_offset = -1;
3408 cmd_buffer->state.last_first_instance = -1;
3409 cmd_buffer->state.predication_type = -1;
3410 cmd_buffer->state.last_sx_ps_downconvert = -1;
3411 cmd_buffer->state.last_sx_blend_opt_epsilon = -1;
3412 cmd_buffer->state.last_sx_blend_opt_control = -1;
3413 cmd_buffer->usage_flags = pBeginInfo->flags;
3414
3415 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
3416 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
3417 assert(pBeginInfo->pInheritanceInfo);
3418 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
3419 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
3420
3421 struct radv_subpass *subpass =
3422 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
3423
3424 if (cmd_buffer->state.framebuffer) {
3425 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
3426 if (result != VK_SUCCESS)
3427 return result;
3428 }
3429
3430 cmd_buffer->state.inherited_pipeline_statistics =
3431 pBeginInfo->pInheritanceInfo->pipelineStatistics;
3432
3433 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3434 }
3435
3436 if (unlikely(cmd_buffer->device->trace_bo)) {
3437 struct radv_device *device = cmd_buffer->device;
3438
3439 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
3440 device->trace_bo);
3441
3442 radv_cmd_buffer_trace_emit(cmd_buffer);
3443 }
3444
3445 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
3446
3447 return result;
3448 }
3449
3450 void radv_CmdBindVertexBuffers(
3451 VkCommandBuffer commandBuffer,
3452 uint32_t firstBinding,
3453 uint32_t bindingCount,
3454 const VkBuffer* pBuffers,
3455 const VkDeviceSize* pOffsets)
3456 {
3457 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3458 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
3459 bool changed = false;
3460
3461 /* We have to defer setting up vertex buffer since we need the buffer
3462 * stride from the pipeline. */
3463
3464 assert(firstBinding + bindingCount <= MAX_VBS);
3465 for (uint32_t i = 0; i < bindingCount; i++) {
3466 uint32_t idx = firstBinding + i;
3467
3468 if (!changed &&
3469 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
3470 vb[idx].offset != pOffsets[i])) {
3471 changed = true;
3472 }
3473
3474 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
3475 vb[idx].offset = pOffsets[i];
3476
3477 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3478 vb[idx].buffer->bo);
3479 }
3480
3481 if (!changed) {
3482 /* No state changes. */
3483 return;
3484 }
3485
3486 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
3487 }
3488
3489 static uint32_t
3490 vk_to_index_type(VkIndexType type)
3491 {
3492 switch (type) {
3493 case VK_INDEX_TYPE_UINT8_EXT:
3494 return V_028A7C_VGT_INDEX_8;
3495 case VK_INDEX_TYPE_UINT16:
3496 return V_028A7C_VGT_INDEX_16;
3497 case VK_INDEX_TYPE_UINT32:
3498 return V_028A7C_VGT_INDEX_32;
3499 default:
3500 unreachable("invalid index type");
3501 }
3502 }
3503
3504 static uint32_t
3505 radv_get_vgt_index_size(uint32_t type)
3506 {
3507 switch (type) {
3508 case V_028A7C_VGT_INDEX_8:
3509 return 1;
3510 case V_028A7C_VGT_INDEX_16:
3511 return 2;
3512 case V_028A7C_VGT_INDEX_32:
3513 return 4;
3514 default:
3515 unreachable("invalid index type");
3516 }
3517 }
3518
3519 void radv_CmdBindIndexBuffer(
3520 VkCommandBuffer commandBuffer,
3521 VkBuffer buffer,
3522 VkDeviceSize offset,
3523 VkIndexType indexType)
3524 {
3525 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3526 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
3527
3528 if (cmd_buffer->state.index_buffer == index_buffer &&
3529 cmd_buffer->state.index_offset == offset &&
3530 cmd_buffer->state.index_type == indexType) {
3531 /* No state changes. */
3532 return;
3533 }
3534
3535 cmd_buffer->state.index_buffer = index_buffer;
3536 cmd_buffer->state.index_offset = offset;
3537 cmd_buffer->state.index_type = vk_to_index_type(indexType);
3538 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
3539 cmd_buffer->state.index_va += index_buffer->offset + offset;
3540
3541 int index_size = radv_get_vgt_index_size(vk_to_index_type(indexType));
3542 cmd_buffer->state.max_index_count = (index_buffer->size - offset) / index_size;
3543 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3544 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
3545 }
3546
3547
3548 static void
3549 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3550 VkPipelineBindPoint bind_point,
3551 struct radv_descriptor_set *set, unsigned idx)
3552 {
3553 struct radeon_winsys *ws = cmd_buffer->device->ws;
3554
3555 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
3556
3557 assert(set);
3558 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
3559
3560 if (!cmd_buffer->device->use_global_bo_list) {
3561 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3562 if (set->descriptors[j])
3563 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
3564 }
3565
3566 if(set->bo)
3567 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
3568 }
3569
3570 void radv_CmdBindDescriptorSets(
3571 VkCommandBuffer commandBuffer,
3572 VkPipelineBindPoint pipelineBindPoint,
3573 VkPipelineLayout _layout,
3574 uint32_t firstSet,
3575 uint32_t descriptorSetCount,
3576 const VkDescriptorSet* pDescriptorSets,
3577 uint32_t dynamicOffsetCount,
3578 const uint32_t* pDynamicOffsets)
3579 {
3580 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3581 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3582 unsigned dyn_idx = 0;
3583
3584 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
3585 struct radv_descriptor_state *descriptors_state =
3586 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3587
3588 for (unsigned i = 0; i < descriptorSetCount; ++i) {
3589 unsigned idx = i + firstSet;
3590 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
3591
3592 /* If the set is already bound we only need to update the
3593 * (potentially changed) dynamic offsets. */
3594 if (descriptors_state->sets[idx] != set ||
3595 !(descriptors_state->valid & (1u << idx))) {
3596 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
3597 }
3598
3599 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
3600 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
3601 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
3602 assert(dyn_idx < dynamicOffsetCount);
3603
3604 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
3605 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
3606 dst[0] = va;
3607 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
3608 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
3609 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3610 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3611 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3612 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3613
3614 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
3615 dst[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3616 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3617 S_008F0C_RESOURCE_LEVEL(1);
3618 } else {
3619 dst[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3620 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3621 }
3622
3623 cmd_buffer->push_constant_stages |=
3624 set->layout->dynamic_shader_stages;
3625 }
3626 }
3627 }
3628
3629 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3630 struct radv_descriptor_set *set,
3631 struct radv_descriptor_set_layout *layout,
3632 VkPipelineBindPoint bind_point)
3633 {
3634 struct radv_descriptor_state *descriptors_state =
3635 radv_get_descriptors_state(cmd_buffer, bind_point);
3636 set->size = layout->size;
3637 set->layout = layout;
3638
3639 if (descriptors_state->push_set.capacity < set->size) {
3640 size_t new_size = MAX2(set->size, 1024);
3641 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
3642 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
3643
3644 free(set->mapped_ptr);
3645 set->mapped_ptr = malloc(new_size);
3646
3647 if (!set->mapped_ptr) {
3648 descriptors_state->push_set.capacity = 0;
3649 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3650 return false;
3651 }
3652
3653 descriptors_state->push_set.capacity = new_size;
3654 }
3655
3656 return true;
3657 }
3658
3659 void radv_meta_push_descriptor_set(
3660 struct radv_cmd_buffer* cmd_buffer,
3661 VkPipelineBindPoint pipelineBindPoint,
3662 VkPipelineLayout _layout,
3663 uint32_t set,
3664 uint32_t descriptorWriteCount,
3665 const VkWriteDescriptorSet* pDescriptorWrites)
3666 {
3667 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3668 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
3669 unsigned bo_offset;
3670
3671 assert(set == 0);
3672 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3673
3674 push_set->size = layout->set[set].layout->size;
3675 push_set->layout = layout->set[set].layout;
3676
3677 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
3678 &bo_offset,
3679 (void**) &push_set->mapped_ptr))
3680 return;
3681
3682 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
3683 push_set->va += bo_offset;
3684
3685 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3686 radv_descriptor_set_to_handle(push_set),
3687 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3688
3689 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3690 }
3691
3692 void radv_CmdPushDescriptorSetKHR(
3693 VkCommandBuffer commandBuffer,
3694 VkPipelineBindPoint pipelineBindPoint,
3695 VkPipelineLayout _layout,
3696 uint32_t set,
3697 uint32_t descriptorWriteCount,
3698 const VkWriteDescriptorSet* pDescriptorWrites)
3699 {
3700 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3701 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3702 struct radv_descriptor_state *descriptors_state =
3703 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3704 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3705
3706 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3707
3708 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3709 layout->set[set].layout,
3710 pipelineBindPoint))
3711 return;
3712
3713 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3714 * because it is invalid, according to Vulkan spec.
3715 */
3716 for (int i = 0; i < descriptorWriteCount; i++) {
3717 ASSERTED const VkWriteDescriptorSet *writeset = &pDescriptorWrites[i];
3718 assert(writeset->descriptorType != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT);
3719 }
3720
3721 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3722 radv_descriptor_set_to_handle(push_set),
3723 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3724
3725 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3726 descriptors_state->push_dirty = true;
3727 }
3728
3729 void radv_CmdPushDescriptorSetWithTemplateKHR(
3730 VkCommandBuffer commandBuffer,
3731 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
3732 VkPipelineLayout _layout,
3733 uint32_t set,
3734 const void* pData)
3735 {
3736 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3737 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3738 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
3739 struct radv_descriptor_state *descriptors_state =
3740 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
3741 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3742
3743 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3744
3745 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3746 layout->set[set].layout,
3747 templ->bind_point))
3748 return;
3749
3750 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
3751 descriptorUpdateTemplate, pData);
3752
3753 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
3754 descriptors_state->push_dirty = true;
3755 }
3756
3757 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
3758 VkPipelineLayout layout,
3759 VkShaderStageFlags stageFlags,
3760 uint32_t offset,
3761 uint32_t size,
3762 const void* pValues)
3763 {
3764 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3765 memcpy(cmd_buffer->push_constants + offset, pValues, size);
3766 cmd_buffer->push_constant_stages |= stageFlags;
3767 }
3768
3769 VkResult radv_EndCommandBuffer(
3770 VkCommandBuffer commandBuffer)
3771 {
3772 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3773
3774 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
3775 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6)
3776 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WB_L2;
3777
3778 /* Make sure to sync all pending active queries at the end of
3779 * command buffer.
3780 */
3781 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
3782
3783 /* Since NGG streamout uses GDS, we need to make GDS idle when
3784 * we leave the IB, otherwise another process might overwrite
3785 * it while our shaders are busy.
3786 */
3787 if (cmd_buffer->gds_needed)
3788 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
3789
3790 si_emit_cache_flush(cmd_buffer);
3791 }
3792
3793 /* Make sure CP DMA is idle at the end of IBs because the kernel
3794 * doesn't wait for it.
3795 */
3796 si_cp_dma_wait_for_idle(cmd_buffer);
3797
3798 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3799 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
3800
3801 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
3802 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3803
3804 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
3805
3806 return cmd_buffer->record_result;
3807 }
3808
3809 static void
3810 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
3811 {
3812 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3813
3814 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
3815 return;
3816
3817 assert(!pipeline->ctx_cs.cdw);
3818
3819 cmd_buffer->state.emitted_compute_pipeline = pipeline;
3820
3821 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
3822 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
3823
3824 cmd_buffer->compute_scratch_size_per_wave_needed = MAX2(cmd_buffer->compute_scratch_size_per_wave_needed,
3825 pipeline->scratch_bytes_per_wave);
3826 cmd_buffer->compute_scratch_waves_wanted = MAX2(cmd_buffer->compute_scratch_waves_wanted,
3827 pipeline->max_waves);
3828
3829 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3830 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
3831
3832 if (unlikely(cmd_buffer->device->trace_bo))
3833 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
3834 }
3835
3836 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
3837 VkPipelineBindPoint bind_point)
3838 {
3839 struct radv_descriptor_state *descriptors_state =
3840 radv_get_descriptors_state(cmd_buffer, bind_point);
3841
3842 descriptors_state->dirty |= descriptors_state->valid;
3843 }
3844
3845 void radv_CmdBindPipeline(
3846 VkCommandBuffer commandBuffer,
3847 VkPipelineBindPoint pipelineBindPoint,
3848 VkPipeline _pipeline)
3849 {
3850 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3851 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
3852
3853 switch (pipelineBindPoint) {
3854 case VK_PIPELINE_BIND_POINT_COMPUTE:
3855 if (cmd_buffer->state.compute_pipeline == pipeline)
3856 return;
3857 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3858
3859 cmd_buffer->state.compute_pipeline = pipeline;
3860 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
3861 break;
3862 case VK_PIPELINE_BIND_POINT_GRAPHICS:
3863 if (cmd_buffer->state.pipeline == pipeline)
3864 return;
3865 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3866
3867 cmd_buffer->state.pipeline = pipeline;
3868 if (!pipeline)
3869 break;
3870
3871 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
3872 cmd_buffer->push_constant_stages |= pipeline->active_stages;
3873
3874 /* the new vertex shader might not have the same user regs */
3875 cmd_buffer->state.last_first_instance = -1;
3876 cmd_buffer->state.last_vertex_offset = -1;
3877
3878 /* Prefetch all pipeline shaders at first draw time. */
3879 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
3880
3881 if ((cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI10 ||
3882 cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI12 ||
3883 cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI14) &&
3884 cmd_buffer->state.emitted_pipeline &&
3885 radv_pipeline_has_ngg(cmd_buffer->state.emitted_pipeline) &&
3886 !radv_pipeline_has_ngg(cmd_buffer->state.pipeline)) {
3887 /* Transitioning from NGG to legacy GS requires
3888 * VGT_FLUSH on Navi10-14. VGT_FLUSH is also emitted
3889 * at the beginning of IBs when legacy GS ring pointers
3890 * are set.
3891 */
3892 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
3893 }
3894
3895 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
3896 radv_bind_streamout_state(cmd_buffer, pipeline);
3897
3898 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
3899 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
3900 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
3901 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
3902
3903 if (radv_pipeline_has_tess(pipeline))
3904 cmd_buffer->tess_rings_needed = true;
3905 break;
3906 default:
3907 assert(!"invalid bind point");
3908 break;
3909 }
3910 }
3911
3912 void radv_CmdSetViewport(
3913 VkCommandBuffer commandBuffer,
3914 uint32_t firstViewport,
3915 uint32_t viewportCount,
3916 const VkViewport* pViewports)
3917 {
3918 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3919 struct radv_cmd_state *state = &cmd_buffer->state;
3920 ASSERTED const uint32_t total_count = firstViewport + viewportCount;
3921
3922 assert(firstViewport < MAX_VIEWPORTS);
3923 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
3924
3925 if (!memcmp(state->dynamic.viewport.viewports + firstViewport,
3926 pViewports, viewportCount * sizeof(*pViewports))) {
3927 return;
3928 }
3929
3930 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
3931 viewportCount * sizeof(*pViewports));
3932
3933 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
3934 }
3935
3936 void radv_CmdSetScissor(
3937 VkCommandBuffer commandBuffer,
3938 uint32_t firstScissor,
3939 uint32_t scissorCount,
3940 const VkRect2D* pScissors)
3941 {
3942 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3943 struct radv_cmd_state *state = &cmd_buffer->state;
3944 ASSERTED const uint32_t total_count = firstScissor + scissorCount;
3945
3946 assert(firstScissor < MAX_SCISSORS);
3947 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
3948
3949 if (!memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
3950 scissorCount * sizeof(*pScissors))) {
3951 return;
3952 }
3953
3954 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
3955 scissorCount * sizeof(*pScissors));
3956
3957 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
3958 }
3959
3960 void radv_CmdSetLineWidth(
3961 VkCommandBuffer commandBuffer,
3962 float lineWidth)
3963 {
3964 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3965
3966 if (cmd_buffer->state.dynamic.line_width == lineWidth)
3967 return;
3968
3969 cmd_buffer->state.dynamic.line_width = lineWidth;
3970 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
3971 }
3972
3973 void radv_CmdSetDepthBias(
3974 VkCommandBuffer commandBuffer,
3975 float depthBiasConstantFactor,
3976 float depthBiasClamp,
3977 float depthBiasSlopeFactor)
3978 {
3979 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3980 struct radv_cmd_state *state = &cmd_buffer->state;
3981
3982 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
3983 state->dynamic.depth_bias.clamp == depthBiasClamp &&
3984 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
3985 return;
3986 }
3987
3988 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
3989 state->dynamic.depth_bias.clamp = depthBiasClamp;
3990 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
3991
3992 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
3993 }
3994
3995 void radv_CmdSetBlendConstants(
3996 VkCommandBuffer commandBuffer,
3997 const float blendConstants[4])
3998 {
3999 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4000 struct radv_cmd_state *state = &cmd_buffer->state;
4001
4002 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
4003 return;
4004
4005 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
4006
4007 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
4008 }
4009
4010 void radv_CmdSetDepthBounds(
4011 VkCommandBuffer commandBuffer,
4012 float minDepthBounds,
4013 float maxDepthBounds)
4014 {
4015 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4016 struct radv_cmd_state *state = &cmd_buffer->state;
4017
4018 if (state->dynamic.depth_bounds.min == minDepthBounds &&
4019 state->dynamic.depth_bounds.max == maxDepthBounds) {
4020 return;
4021 }
4022
4023 state->dynamic.depth_bounds.min = minDepthBounds;
4024 state->dynamic.depth_bounds.max = maxDepthBounds;
4025
4026 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
4027 }
4028
4029 void radv_CmdSetStencilCompareMask(
4030 VkCommandBuffer commandBuffer,
4031 VkStencilFaceFlags faceMask,
4032 uint32_t compareMask)
4033 {
4034 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4035 struct radv_cmd_state *state = &cmd_buffer->state;
4036 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
4037 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
4038
4039 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4040 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4041 return;
4042 }
4043
4044 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4045 state->dynamic.stencil_compare_mask.front = compareMask;
4046 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4047 state->dynamic.stencil_compare_mask.back = compareMask;
4048
4049 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
4050 }
4051
4052 void radv_CmdSetStencilWriteMask(
4053 VkCommandBuffer commandBuffer,
4054 VkStencilFaceFlags faceMask,
4055 uint32_t writeMask)
4056 {
4057 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4058 struct radv_cmd_state *state = &cmd_buffer->state;
4059 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
4060 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
4061
4062 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4063 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4064 return;
4065 }
4066
4067 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4068 state->dynamic.stencil_write_mask.front = writeMask;
4069 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4070 state->dynamic.stencil_write_mask.back = writeMask;
4071
4072 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
4073 }
4074
4075 void radv_CmdSetStencilReference(
4076 VkCommandBuffer commandBuffer,
4077 VkStencilFaceFlags faceMask,
4078 uint32_t reference)
4079 {
4080 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4081 struct radv_cmd_state *state = &cmd_buffer->state;
4082 bool front_same = state->dynamic.stencil_reference.front == reference;
4083 bool back_same = state->dynamic.stencil_reference.back == reference;
4084
4085 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4086 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4087 return;
4088 }
4089
4090 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4091 cmd_buffer->state.dynamic.stencil_reference.front = reference;
4092 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4093 cmd_buffer->state.dynamic.stencil_reference.back = reference;
4094
4095 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
4096 }
4097
4098 void radv_CmdSetDiscardRectangleEXT(
4099 VkCommandBuffer commandBuffer,
4100 uint32_t firstDiscardRectangle,
4101 uint32_t discardRectangleCount,
4102 const VkRect2D* pDiscardRectangles)
4103 {
4104 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4105 struct radv_cmd_state *state = &cmd_buffer->state;
4106 ASSERTED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
4107
4108 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
4109 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
4110
4111 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
4112 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
4113 return;
4114 }
4115
4116 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
4117 pDiscardRectangles, discardRectangleCount);
4118
4119 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
4120 }
4121
4122 void radv_CmdSetSampleLocationsEXT(
4123 VkCommandBuffer commandBuffer,
4124 const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
4125 {
4126 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4127 struct radv_cmd_state *state = &cmd_buffer->state;
4128
4129 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
4130
4131 state->dynamic.sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
4132 state->dynamic.sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
4133 state->dynamic.sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
4134 typed_memcpy(&state->dynamic.sample_location.locations[0],
4135 pSampleLocationsInfo->pSampleLocations,
4136 pSampleLocationsInfo->sampleLocationsCount);
4137
4138 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS;
4139 }
4140
4141 void radv_CmdSetLineStippleEXT(
4142 VkCommandBuffer commandBuffer,
4143 uint32_t lineStippleFactor,
4144 uint16_t lineStipplePattern)
4145 {
4146 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4147 struct radv_cmd_state *state = &cmd_buffer->state;
4148
4149 state->dynamic.line_stipple.factor = lineStippleFactor;
4150 state->dynamic.line_stipple.pattern = lineStipplePattern;
4151
4152 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE;
4153 }
4154
4155 void radv_CmdExecuteCommands(
4156 VkCommandBuffer commandBuffer,
4157 uint32_t commandBufferCount,
4158 const VkCommandBuffer* pCmdBuffers)
4159 {
4160 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
4161
4162 assert(commandBufferCount > 0);
4163
4164 /* Emit pending flushes on primary prior to executing secondary */
4165 si_emit_cache_flush(primary);
4166
4167 for (uint32_t i = 0; i < commandBufferCount; i++) {
4168 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
4169
4170 primary->scratch_size_per_wave_needed = MAX2(primary->scratch_size_per_wave_needed,
4171 secondary->scratch_size_per_wave_needed);
4172 primary->scratch_waves_wanted = MAX2(primary->scratch_waves_wanted,
4173 secondary->scratch_waves_wanted);
4174 primary->compute_scratch_size_per_wave_needed = MAX2(primary->compute_scratch_size_per_wave_needed,
4175 secondary->compute_scratch_size_per_wave_needed);
4176 primary->compute_scratch_waves_wanted = MAX2(primary->compute_scratch_waves_wanted,
4177 secondary->compute_scratch_waves_wanted);
4178
4179 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
4180 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
4181 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
4182 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
4183 if (secondary->tess_rings_needed)
4184 primary->tess_rings_needed = true;
4185 if (secondary->sample_positions_needed)
4186 primary->sample_positions_needed = true;
4187 if (secondary->gds_needed)
4188 primary->gds_needed = true;
4189
4190 if (!secondary->state.framebuffer &&
4191 (primary->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)) {
4192 /* Emit the framebuffer state from primary if secondary
4193 * has been recorded without a framebuffer, otherwise
4194 * fast color/depth clears can't work.
4195 */
4196 radv_emit_framebuffer_state(primary);
4197 }
4198
4199 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
4200
4201
4202 /* When the secondary command buffer is compute only we don't
4203 * need to re-emit the current graphics pipeline.
4204 */
4205 if (secondary->state.emitted_pipeline) {
4206 primary->state.emitted_pipeline =
4207 secondary->state.emitted_pipeline;
4208 }
4209
4210 /* When the secondary command buffer is graphics only we don't
4211 * need to re-emit the current compute pipeline.
4212 */
4213 if (secondary->state.emitted_compute_pipeline) {
4214 primary->state.emitted_compute_pipeline =
4215 secondary->state.emitted_compute_pipeline;
4216 }
4217
4218 /* Only re-emit the draw packets when needed. */
4219 if (secondary->state.last_primitive_reset_en != -1) {
4220 primary->state.last_primitive_reset_en =
4221 secondary->state.last_primitive_reset_en;
4222 }
4223
4224 if (secondary->state.last_primitive_reset_index) {
4225 primary->state.last_primitive_reset_index =
4226 secondary->state.last_primitive_reset_index;
4227 }
4228
4229 if (secondary->state.last_ia_multi_vgt_param) {
4230 primary->state.last_ia_multi_vgt_param =
4231 secondary->state.last_ia_multi_vgt_param;
4232 }
4233
4234 primary->state.last_first_instance = secondary->state.last_first_instance;
4235 primary->state.last_num_instances = secondary->state.last_num_instances;
4236 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
4237 primary->state.last_sx_ps_downconvert = secondary->state.last_sx_ps_downconvert;
4238 primary->state.last_sx_blend_opt_epsilon = secondary->state.last_sx_blend_opt_epsilon;
4239 primary->state.last_sx_blend_opt_control = secondary->state.last_sx_blend_opt_control;
4240
4241 if (secondary->state.last_index_type != -1) {
4242 primary->state.last_index_type =
4243 secondary->state.last_index_type;
4244 }
4245 }
4246
4247 /* After executing commands from secondary buffers we have to dirty
4248 * some states.
4249 */
4250 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
4251 RADV_CMD_DIRTY_INDEX_BUFFER |
4252 RADV_CMD_DIRTY_DYNAMIC_ALL;
4253 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
4254 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
4255 }
4256
4257 VkResult radv_CreateCommandPool(
4258 VkDevice _device,
4259 const VkCommandPoolCreateInfo* pCreateInfo,
4260 const VkAllocationCallbacks* pAllocator,
4261 VkCommandPool* pCmdPool)
4262 {
4263 RADV_FROM_HANDLE(radv_device, device, _device);
4264 struct radv_cmd_pool *pool;
4265
4266 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
4267 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4268 if (pool == NULL)
4269 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4270
4271 if (pAllocator)
4272 pool->alloc = *pAllocator;
4273 else
4274 pool->alloc = device->alloc;
4275
4276 list_inithead(&pool->cmd_buffers);
4277 list_inithead(&pool->free_cmd_buffers);
4278
4279 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
4280
4281 *pCmdPool = radv_cmd_pool_to_handle(pool);
4282
4283 return VK_SUCCESS;
4284
4285 }
4286
4287 void radv_DestroyCommandPool(
4288 VkDevice _device,
4289 VkCommandPool commandPool,
4290 const VkAllocationCallbacks* pAllocator)
4291 {
4292 RADV_FROM_HANDLE(radv_device, device, _device);
4293 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4294
4295 if (!pool)
4296 return;
4297
4298 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4299 &pool->cmd_buffers, pool_link) {
4300 radv_cmd_buffer_destroy(cmd_buffer);
4301 }
4302
4303 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4304 &pool->free_cmd_buffers, pool_link) {
4305 radv_cmd_buffer_destroy(cmd_buffer);
4306 }
4307
4308 vk_free2(&device->alloc, pAllocator, pool);
4309 }
4310
4311 VkResult radv_ResetCommandPool(
4312 VkDevice device,
4313 VkCommandPool commandPool,
4314 VkCommandPoolResetFlags flags)
4315 {
4316 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4317 VkResult result;
4318
4319 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
4320 &pool->cmd_buffers, pool_link) {
4321 result = radv_reset_cmd_buffer(cmd_buffer);
4322 if (result != VK_SUCCESS)
4323 return result;
4324 }
4325
4326 return VK_SUCCESS;
4327 }
4328
4329 void radv_TrimCommandPool(
4330 VkDevice device,
4331 VkCommandPool commandPool,
4332 VkCommandPoolTrimFlags flags)
4333 {
4334 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4335
4336 if (!pool)
4337 return;
4338
4339 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4340 &pool->free_cmd_buffers, pool_link) {
4341 radv_cmd_buffer_destroy(cmd_buffer);
4342 }
4343 }
4344
4345 static void
4346 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
4347 uint32_t subpass_id)
4348 {
4349 struct radv_cmd_state *state = &cmd_buffer->state;
4350 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
4351
4352 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
4353 cmd_buffer->cs, 4096);
4354
4355 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
4356
4357 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
4358
4359 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4360 const uint32_t a = subpass->attachments[i].attachment;
4361 if (a == VK_ATTACHMENT_UNUSED)
4362 continue;
4363
4364 radv_handle_subpass_image_transition(cmd_buffer,
4365 subpass->attachments[i],
4366 true);
4367 }
4368
4369 radv_cmd_buffer_clear_subpass(cmd_buffer);
4370
4371 assert(cmd_buffer->cs->cdw <= cdw_max);
4372 }
4373
4374 static void
4375 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
4376 {
4377 struct radv_cmd_state *state = &cmd_buffer->state;
4378 const struct radv_subpass *subpass = state->subpass;
4379 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
4380
4381 radv_cmd_buffer_resolve_subpass(cmd_buffer);
4382
4383 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4384 const uint32_t a = subpass->attachments[i].attachment;
4385 if (a == VK_ATTACHMENT_UNUSED)
4386 continue;
4387
4388 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
4389 continue;
4390
4391 VkImageLayout layout = state->pass->attachments[a].final_layout;
4392 VkImageLayout stencil_layout = state->pass->attachments[a].stencil_final_layout;
4393 struct radv_subpass_attachment att = { a, layout, stencil_layout };
4394 radv_handle_subpass_image_transition(cmd_buffer, att, false);
4395 }
4396 }
4397
4398 void radv_CmdBeginRenderPass(
4399 VkCommandBuffer commandBuffer,
4400 const VkRenderPassBeginInfo* pRenderPassBegin,
4401 VkSubpassContents contents)
4402 {
4403 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4404 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
4405 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
4406 VkResult result;
4407
4408 cmd_buffer->state.framebuffer = framebuffer;
4409 cmd_buffer->state.pass = pass;
4410 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
4411
4412 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
4413 if (result != VK_SUCCESS)
4414 return;
4415
4416 result = radv_cmd_state_setup_sample_locations(cmd_buffer, pass, pRenderPassBegin);
4417 if (result != VK_SUCCESS)
4418 return;
4419
4420 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
4421 }
4422
4423 void radv_CmdBeginRenderPass2(
4424 VkCommandBuffer commandBuffer,
4425 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
4426 const VkSubpassBeginInfo* pSubpassBeginInfo)
4427 {
4428 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
4429 pSubpassBeginInfo->contents);
4430 }
4431
4432 void radv_CmdNextSubpass(
4433 VkCommandBuffer commandBuffer,
4434 VkSubpassContents contents)
4435 {
4436 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4437
4438 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
4439 radv_cmd_buffer_end_subpass(cmd_buffer);
4440 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
4441 }
4442
4443 void radv_CmdNextSubpass2(
4444 VkCommandBuffer commandBuffer,
4445 const VkSubpassBeginInfo* pSubpassBeginInfo,
4446 const VkSubpassEndInfo* pSubpassEndInfo)
4447 {
4448 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
4449 }
4450
4451 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
4452 {
4453 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
4454 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
4455 if (!radv_get_shader(pipeline, stage))
4456 continue;
4457
4458 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
4459 if (loc->sgpr_idx == -1)
4460 continue;
4461 uint32_t base_reg = pipeline->user_data_0[stage];
4462 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4463
4464 }
4465 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
4466 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
4467 if (loc->sgpr_idx != -1) {
4468 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
4469 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4470 }
4471 }
4472 }
4473
4474 static void
4475 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4476 uint32_t vertex_count,
4477 bool use_opaque)
4478 {
4479 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
4480 radeon_emit(cmd_buffer->cs, vertex_count);
4481 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
4482 S_0287F0_USE_OPAQUE(use_opaque));
4483 }
4484
4485 static void
4486 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
4487 uint64_t index_va,
4488 uint32_t index_count)
4489 {
4490 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
4491 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
4492 radeon_emit(cmd_buffer->cs, index_va);
4493 radeon_emit(cmd_buffer->cs, index_va >> 32);
4494 radeon_emit(cmd_buffer->cs, index_count);
4495 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
4496 }
4497
4498 static void
4499 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4500 bool indexed,
4501 uint32_t draw_count,
4502 uint64_t count_va,
4503 uint32_t stride)
4504 {
4505 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4506 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
4507 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
4508 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id;
4509 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
4510 bool predicating = cmd_buffer->state.predicating;
4511 assert(base_reg);
4512
4513 /* just reset draw state for vertex data */
4514 cmd_buffer->state.last_first_instance = -1;
4515 cmd_buffer->state.last_num_instances = -1;
4516 cmd_buffer->state.last_vertex_offset = -1;
4517
4518 if (draw_count == 1 && !count_va && !draw_id_enable) {
4519 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
4520 PKT3_DRAW_INDIRECT, 3, predicating));
4521 radeon_emit(cs, 0);
4522 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4523 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4524 radeon_emit(cs, di_src_sel);
4525 } else {
4526 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
4527 PKT3_DRAW_INDIRECT_MULTI,
4528 8, predicating));
4529 radeon_emit(cs, 0);
4530 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4531 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4532 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
4533 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
4534 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
4535 radeon_emit(cs, draw_count); /* count */
4536 radeon_emit(cs, count_va); /* count_addr */
4537 radeon_emit(cs, count_va >> 32);
4538 radeon_emit(cs, stride); /* stride */
4539 radeon_emit(cs, di_src_sel);
4540 }
4541 }
4542
4543 static void
4544 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
4545 const struct radv_draw_info *info)
4546 {
4547 struct radv_cmd_state *state = &cmd_buffer->state;
4548 struct radeon_winsys *ws = cmd_buffer->device->ws;
4549 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4550
4551 if (info->indirect) {
4552 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4553 uint64_t count_va = 0;
4554
4555 va += info->indirect->offset + info->indirect_offset;
4556
4557 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4558
4559 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
4560 radeon_emit(cs, 1);
4561 radeon_emit(cs, va);
4562 radeon_emit(cs, va >> 32);
4563
4564 if (info->count_buffer) {
4565 count_va = radv_buffer_get_va(info->count_buffer->bo);
4566 count_va += info->count_buffer->offset +
4567 info->count_buffer_offset;
4568
4569 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
4570 }
4571
4572 if (!state->subpass->view_mask) {
4573 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4574 info->indexed,
4575 info->count,
4576 count_va,
4577 info->stride);
4578 } else {
4579 unsigned i;
4580 for_each_bit(i, state->subpass->view_mask) {
4581 radv_emit_view_index(cmd_buffer, i);
4582
4583 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4584 info->indexed,
4585 info->count,
4586 count_va,
4587 info->stride);
4588 }
4589 }
4590 } else {
4591 assert(state->pipeline->graphics.vtx_base_sgpr);
4592
4593 if (info->vertex_offset != state->last_vertex_offset ||
4594 info->first_instance != state->last_first_instance) {
4595 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
4596 state->pipeline->graphics.vtx_emit_num);
4597
4598 radeon_emit(cs, info->vertex_offset);
4599 radeon_emit(cs, info->first_instance);
4600 if (state->pipeline->graphics.vtx_emit_num == 3)
4601 radeon_emit(cs, 0);
4602 state->last_first_instance = info->first_instance;
4603 state->last_vertex_offset = info->vertex_offset;
4604 }
4605
4606 if (state->last_num_instances != info->instance_count) {
4607 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
4608 radeon_emit(cs, info->instance_count);
4609 state->last_num_instances = info->instance_count;
4610 }
4611
4612 if (info->indexed) {
4613 int index_size = radv_get_vgt_index_size(state->index_type);
4614 uint64_t index_va;
4615
4616 /* Skip draw calls with 0-sized index buffers. They
4617 * cause a hang on some chips, like Navi10-14.
4618 */
4619 if (!cmd_buffer->state.max_index_count)
4620 return;
4621
4622 index_va = state->index_va;
4623 index_va += info->first_index * index_size;
4624
4625 if (!state->subpass->view_mask) {
4626 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4627 index_va,
4628 info->count);
4629 } else {
4630 unsigned i;
4631 for_each_bit(i, state->subpass->view_mask) {
4632 radv_emit_view_index(cmd_buffer, i);
4633
4634 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4635 index_va,
4636 info->count);
4637 }
4638 }
4639 } else {
4640 if (!state->subpass->view_mask) {
4641 radv_cs_emit_draw_packet(cmd_buffer,
4642 info->count,
4643 !!info->strmout_buffer);
4644 } else {
4645 unsigned i;
4646 for_each_bit(i, state->subpass->view_mask) {
4647 radv_emit_view_index(cmd_buffer, i);
4648
4649 radv_cs_emit_draw_packet(cmd_buffer,
4650 info->count,
4651 !!info->strmout_buffer);
4652 }
4653 }
4654 }
4655 }
4656 }
4657
4658 /*
4659 * Vega and raven have a bug which triggers if there are multiple context
4660 * register contexts active at the same time with different scissor values.
4661 *
4662 * There are two possible workarounds:
4663 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
4664 * there is only ever 1 active set of scissor values at the same time.
4665 *
4666 * 2) Whenever the hardware switches contexts we have to set the scissor
4667 * registers again even if it is a noop. That way the new context gets
4668 * the correct scissor values.
4669 *
4670 * This implements option 2. radv_need_late_scissor_emission needs to
4671 * return true on affected HW if radv_emit_all_graphics_states sets
4672 * any context registers.
4673 */
4674 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
4675 const struct radv_draw_info *info)
4676 {
4677 struct radv_cmd_state *state = &cmd_buffer->state;
4678
4679 if (!cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
4680 return false;
4681
4682 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
4683 return true;
4684
4685 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
4686
4687 /* Index, vertex and streamout buffers don't change context regs, and
4688 * pipeline is already handled.
4689 */
4690 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
4691 RADV_CMD_DIRTY_VERTEX_BUFFER |
4692 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
4693 RADV_CMD_DIRTY_PIPELINE);
4694
4695 if (cmd_buffer->state.dirty & used_states)
4696 return true;
4697
4698 uint32_t primitive_reset_index =
4699 radv_get_primitive_reset_index(cmd_buffer);
4700
4701 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
4702 primitive_reset_index != state->last_primitive_reset_index)
4703 return true;
4704
4705 return false;
4706 }
4707
4708 static void
4709 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
4710 const struct radv_draw_info *info)
4711 {
4712 bool late_scissor_emission;
4713
4714 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
4715 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
4716 radv_emit_rbplus_state(cmd_buffer);
4717
4718 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
4719 radv_emit_graphics_pipeline(cmd_buffer);
4720
4721 /* This should be before the cmd_buffer->state.dirty is cleared
4722 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4723 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4724 late_scissor_emission =
4725 radv_need_late_scissor_emission(cmd_buffer, info);
4726
4727 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
4728 radv_emit_framebuffer_state(cmd_buffer);
4729
4730 if (info->indexed) {
4731 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
4732 radv_emit_index_buffer(cmd_buffer, info->indirect);
4733 } else {
4734 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4735 * so the state must be re-emitted before the next indexed
4736 * draw.
4737 */
4738 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
4739 cmd_buffer->state.last_index_type = -1;
4740 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
4741 }
4742 }
4743
4744 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
4745
4746 radv_emit_draw_registers(cmd_buffer, info);
4747
4748 if (late_scissor_emission)
4749 radv_emit_scissor(cmd_buffer);
4750 }
4751
4752 static void
4753 radv_draw(struct radv_cmd_buffer *cmd_buffer,
4754 const struct radv_draw_info *info)
4755 {
4756 struct radeon_info *rad_info =
4757 &cmd_buffer->device->physical_device->rad_info;
4758 bool has_prefetch =
4759 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4760 bool pipeline_is_dirty =
4761 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
4762 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
4763
4764 ASSERTED unsigned cdw_max =
4765 radeon_check_space(cmd_buffer->device->ws,
4766 cmd_buffer->cs, 4096);
4767
4768 if (likely(!info->indirect)) {
4769 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4770 * no workaround for indirect draws, but we can at least skip
4771 * direct draws.
4772 */
4773 if (unlikely(!info->instance_count))
4774 return;
4775
4776 /* Handle count == 0. */
4777 if (unlikely(!info->count && !info->strmout_buffer))
4778 return;
4779 }
4780
4781 /* Use optimal packet order based on whether we need to sync the
4782 * pipeline.
4783 */
4784 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4785 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4786 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4787 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4788 /* If we have to wait for idle, set all states first, so that
4789 * all SET packets are processed in parallel with previous draw
4790 * calls. Then upload descriptors, set shader pointers, and
4791 * draw, and prefetch at the end. This ensures that the time
4792 * the CUs are idle is very short. (there are only SET_SH
4793 * packets between the wait and the draw)
4794 */
4795 radv_emit_all_graphics_states(cmd_buffer, info);
4796 si_emit_cache_flush(cmd_buffer);
4797 /* <-- CUs are idle here --> */
4798
4799 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4800
4801 radv_emit_draw_packets(cmd_buffer, info);
4802 /* <-- CUs are busy here --> */
4803
4804 /* Start prefetches after the draw has been started. Both will
4805 * run in parallel, but starting the draw first is more
4806 * important.
4807 */
4808 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4809 radv_emit_prefetch_L2(cmd_buffer,
4810 cmd_buffer->state.pipeline, false);
4811 }
4812 } else {
4813 /* If we don't wait for idle, start prefetches first, then set
4814 * states, and draw at the end.
4815 */
4816 si_emit_cache_flush(cmd_buffer);
4817
4818 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4819 /* Only prefetch the vertex shader and VBO descriptors
4820 * in order to start the draw as soon as possible.
4821 */
4822 radv_emit_prefetch_L2(cmd_buffer,
4823 cmd_buffer->state.pipeline, true);
4824 }
4825
4826 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4827
4828 radv_emit_all_graphics_states(cmd_buffer, info);
4829 radv_emit_draw_packets(cmd_buffer, info);
4830
4831 /* Prefetch the remaining shaders after the draw has been
4832 * started.
4833 */
4834 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4835 radv_emit_prefetch_L2(cmd_buffer,
4836 cmd_buffer->state.pipeline, false);
4837 }
4838 }
4839
4840 /* Workaround for a VGT hang when streamout is enabled.
4841 * It must be done after drawing.
4842 */
4843 if (cmd_buffer->state.streamout.streamout_enabled &&
4844 (rad_info->family == CHIP_HAWAII ||
4845 rad_info->family == CHIP_TONGA ||
4846 rad_info->family == CHIP_FIJI)) {
4847 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
4848 }
4849
4850 assert(cmd_buffer->cs->cdw <= cdw_max);
4851 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
4852 }
4853
4854 void radv_CmdDraw(
4855 VkCommandBuffer commandBuffer,
4856 uint32_t vertexCount,
4857 uint32_t instanceCount,
4858 uint32_t firstVertex,
4859 uint32_t firstInstance)
4860 {
4861 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4862 struct radv_draw_info info = {};
4863
4864 info.count = vertexCount;
4865 info.instance_count = instanceCount;
4866 info.first_instance = firstInstance;
4867 info.vertex_offset = firstVertex;
4868
4869 radv_draw(cmd_buffer, &info);
4870 }
4871
4872 void radv_CmdDrawIndexed(
4873 VkCommandBuffer commandBuffer,
4874 uint32_t indexCount,
4875 uint32_t instanceCount,
4876 uint32_t firstIndex,
4877 int32_t vertexOffset,
4878 uint32_t firstInstance)
4879 {
4880 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4881 struct radv_draw_info info = {};
4882
4883 info.indexed = true;
4884 info.count = indexCount;
4885 info.instance_count = instanceCount;
4886 info.first_index = firstIndex;
4887 info.vertex_offset = vertexOffset;
4888 info.first_instance = firstInstance;
4889
4890 radv_draw(cmd_buffer, &info);
4891 }
4892
4893 void radv_CmdDrawIndirect(
4894 VkCommandBuffer commandBuffer,
4895 VkBuffer _buffer,
4896 VkDeviceSize offset,
4897 uint32_t drawCount,
4898 uint32_t stride)
4899 {
4900 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4901 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4902 struct radv_draw_info info = {};
4903
4904 info.count = drawCount;
4905 info.indirect = buffer;
4906 info.indirect_offset = offset;
4907 info.stride = stride;
4908
4909 radv_draw(cmd_buffer, &info);
4910 }
4911
4912 void radv_CmdDrawIndexedIndirect(
4913 VkCommandBuffer commandBuffer,
4914 VkBuffer _buffer,
4915 VkDeviceSize offset,
4916 uint32_t drawCount,
4917 uint32_t stride)
4918 {
4919 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4920 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4921 struct radv_draw_info info = {};
4922
4923 info.indexed = true;
4924 info.count = drawCount;
4925 info.indirect = buffer;
4926 info.indirect_offset = offset;
4927 info.stride = stride;
4928
4929 radv_draw(cmd_buffer, &info);
4930 }
4931
4932 void radv_CmdDrawIndirectCount(
4933 VkCommandBuffer commandBuffer,
4934 VkBuffer _buffer,
4935 VkDeviceSize offset,
4936 VkBuffer _countBuffer,
4937 VkDeviceSize countBufferOffset,
4938 uint32_t maxDrawCount,
4939 uint32_t stride)
4940 {
4941 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4942 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4943 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4944 struct radv_draw_info info = {};
4945
4946 info.count = maxDrawCount;
4947 info.indirect = buffer;
4948 info.indirect_offset = offset;
4949 info.count_buffer = count_buffer;
4950 info.count_buffer_offset = countBufferOffset;
4951 info.stride = stride;
4952
4953 radv_draw(cmd_buffer, &info);
4954 }
4955
4956 void radv_CmdDrawIndexedIndirectCount(
4957 VkCommandBuffer commandBuffer,
4958 VkBuffer _buffer,
4959 VkDeviceSize offset,
4960 VkBuffer _countBuffer,
4961 VkDeviceSize countBufferOffset,
4962 uint32_t maxDrawCount,
4963 uint32_t stride)
4964 {
4965 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4966 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4967 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4968 struct radv_draw_info info = {};
4969
4970 info.indexed = true;
4971 info.count = maxDrawCount;
4972 info.indirect = buffer;
4973 info.indirect_offset = offset;
4974 info.count_buffer = count_buffer;
4975 info.count_buffer_offset = countBufferOffset;
4976 info.stride = stride;
4977
4978 radv_draw(cmd_buffer, &info);
4979 }
4980
4981 struct radv_dispatch_info {
4982 /**
4983 * Determine the layout of the grid (in block units) to be used.
4984 */
4985 uint32_t blocks[3];
4986
4987 /**
4988 * A starting offset for the grid. If unaligned is set, the offset
4989 * must still be aligned.
4990 */
4991 uint32_t offsets[3];
4992 /**
4993 * Whether it's an unaligned compute dispatch.
4994 */
4995 bool unaligned;
4996
4997 /**
4998 * Indirect compute parameters resource.
4999 */
5000 struct radv_buffer *indirect;
5001 uint64_t indirect_offset;
5002 };
5003
5004 static void
5005 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
5006 const struct radv_dispatch_info *info)
5007 {
5008 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
5009 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
5010 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
5011 struct radeon_winsys *ws = cmd_buffer->device->ws;
5012 bool predicating = cmd_buffer->state.predicating;
5013 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5014 struct radv_userdata_info *loc;
5015
5016 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
5017 AC_UD_CS_GRID_SIZE);
5018
5019 ASSERTED unsigned cdw_max = radeon_check_space(ws, cs, 25);
5020
5021 if (compute_shader->info.wave_size == 32) {
5022 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
5023 dispatch_initiator |= S_00B800_CS_W32_EN(1);
5024 }
5025
5026 if (info->indirect) {
5027 uint64_t va = radv_buffer_get_va(info->indirect->bo);
5028
5029 va += info->indirect->offset + info->indirect_offset;
5030
5031 radv_cs_add_buffer(ws, cs, info->indirect->bo);
5032
5033 if (loc->sgpr_idx != -1) {
5034 for (unsigned i = 0; i < 3; ++i) {
5035 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5036 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5037 COPY_DATA_DST_SEL(COPY_DATA_REG));
5038 radeon_emit(cs, (va + 4 * i));
5039 radeon_emit(cs, (va + 4 * i) >> 32);
5040 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
5041 + loc->sgpr_idx * 4) >> 2) + i);
5042 radeon_emit(cs, 0);
5043 }
5044 }
5045
5046 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
5047 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
5048 PKT3_SHADER_TYPE_S(1));
5049 radeon_emit(cs, va);
5050 radeon_emit(cs, va >> 32);
5051 radeon_emit(cs, dispatch_initiator);
5052 } else {
5053 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
5054 PKT3_SHADER_TYPE_S(1));
5055 radeon_emit(cs, 1);
5056 radeon_emit(cs, va);
5057 radeon_emit(cs, va >> 32);
5058
5059 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
5060 PKT3_SHADER_TYPE_S(1));
5061 radeon_emit(cs, 0);
5062 radeon_emit(cs, dispatch_initiator);
5063 }
5064 } else {
5065 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
5066 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
5067
5068 if (info->unaligned) {
5069 unsigned *cs_block_size = compute_shader->info.cs.block_size;
5070 unsigned remainder[3];
5071
5072 /* If aligned, these should be an entire block size,
5073 * not 0.
5074 */
5075 remainder[0] = blocks[0] + cs_block_size[0] -
5076 align_u32_npot(blocks[0], cs_block_size[0]);
5077 remainder[1] = blocks[1] + cs_block_size[1] -
5078 align_u32_npot(blocks[1], cs_block_size[1]);
5079 remainder[2] = blocks[2] + cs_block_size[2] -
5080 align_u32_npot(blocks[2], cs_block_size[2]);
5081
5082 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
5083 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
5084 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
5085
5086 for(unsigned i = 0; i < 3; ++i) {
5087 assert(offsets[i] % cs_block_size[i] == 0);
5088 offsets[i] /= cs_block_size[i];
5089 }
5090
5091 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
5092 radeon_emit(cs,
5093 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
5094 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
5095 radeon_emit(cs,
5096 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
5097 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
5098 radeon_emit(cs,
5099 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
5100 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
5101
5102 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
5103 }
5104
5105 if (loc->sgpr_idx != -1) {
5106 assert(loc->num_sgprs == 3);
5107
5108 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
5109 loc->sgpr_idx * 4, 3);
5110 radeon_emit(cs, blocks[0]);
5111 radeon_emit(cs, blocks[1]);
5112 radeon_emit(cs, blocks[2]);
5113 }
5114
5115 if (offsets[0] || offsets[1] || offsets[2]) {
5116 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
5117 radeon_emit(cs, offsets[0]);
5118 radeon_emit(cs, offsets[1]);
5119 radeon_emit(cs, offsets[2]);
5120
5121 /* The blocks in the packet are not counts but end values. */
5122 for (unsigned i = 0; i < 3; ++i)
5123 blocks[i] += offsets[i];
5124 } else {
5125 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
5126 }
5127
5128 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
5129 PKT3_SHADER_TYPE_S(1));
5130 radeon_emit(cs, blocks[0]);
5131 radeon_emit(cs, blocks[1]);
5132 radeon_emit(cs, blocks[2]);
5133 radeon_emit(cs, dispatch_initiator);
5134 }
5135
5136 assert(cmd_buffer->cs->cdw <= cdw_max);
5137 }
5138
5139 static void
5140 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
5141 {
5142 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
5143 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
5144 }
5145
5146 static void
5147 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
5148 const struct radv_dispatch_info *info)
5149 {
5150 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
5151 bool has_prefetch =
5152 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
5153 bool pipeline_is_dirty = pipeline &&
5154 pipeline != cmd_buffer->state.emitted_compute_pipeline;
5155
5156 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5157 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5158 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
5159 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
5160 /* If we have to wait for idle, set all states first, so that
5161 * all SET packets are processed in parallel with previous draw
5162 * calls. Then upload descriptors, set shader pointers, and
5163 * dispatch, and prefetch at the end. This ensures that the
5164 * time the CUs are idle is very short. (there are only SET_SH
5165 * packets between the wait and the draw)
5166 */
5167 radv_emit_compute_pipeline(cmd_buffer);
5168 si_emit_cache_flush(cmd_buffer);
5169 /* <-- CUs are idle here --> */
5170
5171 radv_upload_compute_shader_descriptors(cmd_buffer);
5172
5173 radv_emit_dispatch_packets(cmd_buffer, info);
5174 /* <-- CUs are busy here --> */
5175
5176 /* Start prefetches after the dispatch has been started. Both
5177 * will run in parallel, but starting the dispatch first is
5178 * more important.
5179 */
5180 if (has_prefetch && pipeline_is_dirty) {
5181 radv_emit_shader_prefetch(cmd_buffer,
5182 pipeline->shaders[MESA_SHADER_COMPUTE]);
5183 }
5184 } else {
5185 /* If we don't wait for idle, start prefetches first, then set
5186 * states, and dispatch at the end.
5187 */
5188 si_emit_cache_flush(cmd_buffer);
5189
5190 if (has_prefetch && pipeline_is_dirty) {
5191 radv_emit_shader_prefetch(cmd_buffer,
5192 pipeline->shaders[MESA_SHADER_COMPUTE]);
5193 }
5194
5195 radv_upload_compute_shader_descriptors(cmd_buffer);
5196
5197 radv_emit_compute_pipeline(cmd_buffer);
5198 radv_emit_dispatch_packets(cmd_buffer, info);
5199 }
5200
5201 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
5202 }
5203
5204 void radv_CmdDispatchBase(
5205 VkCommandBuffer commandBuffer,
5206 uint32_t base_x,
5207 uint32_t base_y,
5208 uint32_t base_z,
5209 uint32_t x,
5210 uint32_t y,
5211 uint32_t z)
5212 {
5213 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5214 struct radv_dispatch_info info = {};
5215
5216 info.blocks[0] = x;
5217 info.blocks[1] = y;
5218 info.blocks[2] = z;
5219
5220 info.offsets[0] = base_x;
5221 info.offsets[1] = base_y;
5222 info.offsets[2] = base_z;
5223 radv_dispatch(cmd_buffer, &info);
5224 }
5225
5226 void radv_CmdDispatch(
5227 VkCommandBuffer commandBuffer,
5228 uint32_t x,
5229 uint32_t y,
5230 uint32_t z)
5231 {
5232 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
5233 }
5234
5235 void radv_CmdDispatchIndirect(
5236 VkCommandBuffer commandBuffer,
5237 VkBuffer _buffer,
5238 VkDeviceSize offset)
5239 {
5240 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5241 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5242 struct radv_dispatch_info info = {};
5243
5244 info.indirect = buffer;
5245 info.indirect_offset = offset;
5246
5247 radv_dispatch(cmd_buffer, &info);
5248 }
5249
5250 void radv_unaligned_dispatch(
5251 struct radv_cmd_buffer *cmd_buffer,
5252 uint32_t x,
5253 uint32_t y,
5254 uint32_t z)
5255 {
5256 struct radv_dispatch_info info = {};
5257
5258 info.blocks[0] = x;
5259 info.blocks[1] = y;
5260 info.blocks[2] = z;
5261 info.unaligned = 1;
5262
5263 radv_dispatch(cmd_buffer, &info);
5264 }
5265
5266 void radv_CmdEndRenderPass(
5267 VkCommandBuffer commandBuffer)
5268 {
5269 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5270
5271 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
5272
5273 radv_cmd_buffer_end_subpass(cmd_buffer);
5274
5275 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
5276 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
5277
5278 cmd_buffer->state.pass = NULL;
5279 cmd_buffer->state.subpass = NULL;
5280 cmd_buffer->state.attachments = NULL;
5281 cmd_buffer->state.framebuffer = NULL;
5282 cmd_buffer->state.subpass_sample_locs = NULL;
5283 }
5284
5285 void radv_CmdEndRenderPass2(
5286 VkCommandBuffer commandBuffer,
5287 const VkSubpassEndInfo* pSubpassEndInfo)
5288 {
5289 radv_CmdEndRenderPass(commandBuffer);
5290 }
5291
5292 /*
5293 * For HTILE we have the following interesting clear words:
5294 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
5295 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
5296 * 0xfffffff0: Clear depth to 1.0
5297 * 0x00000000: Clear depth to 0.0
5298 */
5299 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
5300 struct radv_image *image,
5301 const VkImageSubresourceRange *range)
5302 {
5303 assert(range->baseMipLevel == 0);
5304 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
5305 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
5306 struct radv_cmd_state *state = &cmd_buffer->state;
5307 uint32_t htile_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
5308 VkClearDepthStencilValue value = {};
5309
5310 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5311 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5312
5313 state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, htile_value);
5314
5315 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5316
5317 if (vk_format_is_stencil(image->vk_format))
5318 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
5319
5320 radv_set_ds_clear_metadata(cmd_buffer, image, range, value, aspects);
5321
5322 if (radv_image_is_tc_compat_htile(image)) {
5323 /* Initialize the TC-compat metada value to 0 because by
5324 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
5325 * need have to conditionally update its value when performing
5326 * a fast depth clear.
5327 */
5328 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, range, 0);
5329 }
5330 }
5331
5332 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
5333 struct radv_image *image,
5334 VkImageLayout src_layout,
5335 bool src_render_loop,
5336 VkImageLayout dst_layout,
5337 bool dst_render_loop,
5338 unsigned src_queue_mask,
5339 unsigned dst_queue_mask,
5340 const VkImageSubresourceRange *range,
5341 struct radv_sample_locations_state *sample_locs)
5342 {
5343 if (!radv_image_has_htile(image))
5344 return;
5345
5346 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5347 radv_initialize_htile(cmd_buffer, image, range);
5348 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5349 radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5350 radv_initialize_htile(cmd_buffer, image, range);
5351 } else if (radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5352 !radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5353 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5354 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5355
5356 radv_decompress_depth_image_inplace(cmd_buffer, image, range,
5357 sample_locs);
5358
5359 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5360 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5361 }
5362 }
5363
5364 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
5365 struct radv_image *image,
5366 const VkImageSubresourceRange *range,
5367 uint32_t value)
5368 {
5369 struct radv_cmd_state *state = &cmd_buffer->state;
5370
5371 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5372 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5373
5374 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, range, value);
5375
5376 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5377 }
5378
5379 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
5380 struct radv_image *image,
5381 const VkImageSubresourceRange *range)
5382 {
5383 struct radv_cmd_state *state = &cmd_buffer->state;
5384 static const uint32_t fmask_clear_values[4] = {
5385 0x00000000,
5386 0x02020202,
5387 0xE4E4E4E4,
5388 0x76543210
5389 };
5390 uint32_t log2_samples = util_logbase2(image->info.samples);
5391 uint32_t value = fmask_clear_values[log2_samples];
5392
5393 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5394 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5395
5396 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, range, value);
5397
5398 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5399 }
5400
5401 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
5402 struct radv_image *image,
5403 const VkImageSubresourceRange *range, uint32_t value)
5404 {
5405 struct radv_cmd_state *state = &cmd_buffer->state;
5406 unsigned size = 0;
5407
5408 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5409 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5410
5411 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
5412
5413 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) {
5414 /* When DCC is enabled with mipmaps, some levels might not
5415 * support fast clears and we have to initialize them as "fully
5416 * expanded".
5417 */
5418 /* Compute the size of all fast clearable DCC levels. */
5419 for (unsigned i = 0; i < image->planes[0].surface.num_dcc_levels; i++) {
5420 struct legacy_surf_level *surf_level =
5421 &image->planes[0].surface.u.legacy.level[i];
5422 unsigned dcc_fast_clear_size =
5423 surf_level->dcc_slice_fast_clear_size * image->info.array_size;
5424
5425 if (!dcc_fast_clear_size)
5426 break;
5427
5428 size = surf_level->dcc_offset + dcc_fast_clear_size;
5429 }
5430
5431 /* Initialize the mipmap levels without DCC. */
5432 if (size != image->planes[0].surface.dcc_size) {
5433 state->flush_bits |=
5434 radv_fill_buffer(cmd_buffer, image->bo,
5435 image->offset + image->dcc_offset + size,
5436 image->planes[0].surface.dcc_size - size,
5437 0xffffffff);
5438 }
5439 }
5440
5441 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5442 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5443 }
5444
5445 /**
5446 * Initialize DCC/FMASK/CMASK metadata for a color image.
5447 */
5448 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
5449 struct radv_image *image,
5450 VkImageLayout src_layout,
5451 bool src_render_loop,
5452 VkImageLayout dst_layout,
5453 bool dst_render_loop,
5454 unsigned src_queue_mask,
5455 unsigned dst_queue_mask,
5456 const VkImageSubresourceRange *range)
5457 {
5458 if (radv_image_has_cmask(image)) {
5459 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5460
5461 /* TODO: clarify this. */
5462 if (radv_image_has_fmask(image)) {
5463 value = 0xccccccccu;
5464 }
5465
5466 radv_initialise_cmask(cmd_buffer, image, range, value);
5467 }
5468
5469 if (radv_image_has_fmask(image)) {
5470 radv_initialize_fmask(cmd_buffer, image, range);
5471 }
5472
5473 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5474 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5475 bool need_decompress_pass = false;
5476
5477 if (radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout,
5478 dst_render_loop,
5479 dst_queue_mask)) {
5480 value = 0x20202020u;
5481 need_decompress_pass = true;
5482 }
5483
5484 radv_initialize_dcc(cmd_buffer, image, range, value);
5485
5486 radv_update_fce_metadata(cmd_buffer, image, range,
5487 need_decompress_pass);
5488 }
5489
5490 if (radv_image_has_cmask(image) ||
5491 radv_dcc_enabled(image, range->baseMipLevel)) {
5492 uint32_t color_values[2] = {};
5493 radv_set_color_clear_metadata(cmd_buffer, image, range,
5494 color_values);
5495 }
5496 }
5497
5498 /**
5499 * Handle color image transitions for DCC/FMASK/CMASK.
5500 */
5501 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
5502 struct radv_image *image,
5503 VkImageLayout src_layout,
5504 bool src_render_loop,
5505 VkImageLayout dst_layout,
5506 bool dst_render_loop,
5507 unsigned src_queue_mask,
5508 unsigned dst_queue_mask,
5509 const VkImageSubresourceRange *range)
5510 {
5511 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5512 radv_init_color_image_metadata(cmd_buffer, image,
5513 src_layout, src_render_loop,
5514 dst_layout, dst_render_loop,
5515 src_queue_mask, dst_queue_mask,
5516 range);
5517 return;
5518 }
5519
5520 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5521 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
5522 radv_initialize_dcc(cmd_buffer, image, range, 0xffffffffu);
5523 } else if (radv_layout_dcc_compressed(cmd_buffer->device, image, src_layout, src_render_loop, src_queue_mask) &&
5524 !radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout, dst_render_loop, dst_queue_mask)) {
5525 radv_decompress_dcc(cmd_buffer, image, range);
5526 } else if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
5527 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5528 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5529 }
5530 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
5531 bool fce_eliminate = false, fmask_expand = false;
5532
5533 if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
5534 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5535 fce_eliminate = true;
5536 }
5537
5538 if (radv_image_has_fmask(image)) {
5539 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
5540 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
5541 /* A FMASK decompress is required before doing
5542 * a MSAA decompress using FMASK.
5543 */
5544 fmask_expand = true;
5545 }
5546 }
5547
5548 if (fce_eliminate || fmask_expand)
5549 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5550
5551 if (fmask_expand)
5552 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
5553 }
5554 }
5555
5556 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
5557 struct radv_image *image,
5558 VkImageLayout src_layout,
5559 bool src_render_loop,
5560 VkImageLayout dst_layout,
5561 bool dst_render_loop,
5562 uint32_t src_family,
5563 uint32_t dst_family,
5564 const VkImageSubresourceRange *range,
5565 struct radv_sample_locations_state *sample_locs)
5566 {
5567 if (image->exclusive && src_family != dst_family) {
5568 /* This is an acquire or a release operation and there will be
5569 * a corresponding release/acquire. Do the transition in the
5570 * most flexible queue. */
5571
5572 assert(src_family == cmd_buffer->queue_family_index ||
5573 dst_family == cmd_buffer->queue_family_index);
5574
5575 if (src_family == VK_QUEUE_FAMILY_EXTERNAL ||
5576 src_family == VK_QUEUE_FAMILY_FOREIGN_EXT)
5577 return;
5578
5579 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
5580 return;
5581
5582 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
5583 (src_family == RADV_QUEUE_GENERAL ||
5584 dst_family == RADV_QUEUE_GENERAL))
5585 return;
5586 }
5587
5588 if (src_layout == dst_layout)
5589 return;
5590
5591 unsigned src_queue_mask =
5592 radv_image_queue_family_mask(image, src_family,
5593 cmd_buffer->queue_family_index);
5594 unsigned dst_queue_mask =
5595 radv_image_queue_family_mask(image, dst_family,
5596 cmd_buffer->queue_family_index);
5597
5598 if (vk_format_is_depth(image->vk_format)) {
5599 radv_handle_depth_image_transition(cmd_buffer, image,
5600 src_layout, src_render_loop,
5601 dst_layout, dst_render_loop,
5602 src_queue_mask, dst_queue_mask,
5603 range, sample_locs);
5604 } else {
5605 radv_handle_color_image_transition(cmd_buffer, image,
5606 src_layout, src_render_loop,
5607 dst_layout, dst_render_loop,
5608 src_queue_mask, dst_queue_mask,
5609 range);
5610 }
5611 }
5612
5613 struct radv_barrier_info {
5614 uint32_t eventCount;
5615 const VkEvent *pEvents;
5616 VkPipelineStageFlags srcStageMask;
5617 VkPipelineStageFlags dstStageMask;
5618 };
5619
5620 static void
5621 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
5622 uint32_t memoryBarrierCount,
5623 const VkMemoryBarrier *pMemoryBarriers,
5624 uint32_t bufferMemoryBarrierCount,
5625 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
5626 uint32_t imageMemoryBarrierCount,
5627 const VkImageMemoryBarrier *pImageMemoryBarriers,
5628 const struct radv_barrier_info *info)
5629 {
5630 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5631 enum radv_cmd_flush_bits src_flush_bits = 0;
5632 enum radv_cmd_flush_bits dst_flush_bits = 0;
5633
5634 for (unsigned i = 0; i < info->eventCount; ++i) {
5635 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
5636 uint64_t va = radv_buffer_get_va(event->bo);
5637
5638 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5639
5640 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
5641
5642 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
5643 assert(cmd_buffer->cs->cdw <= cdw_max);
5644 }
5645
5646 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
5647 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
5648 NULL);
5649 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
5650 NULL);
5651 }
5652
5653 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
5654 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
5655 NULL);
5656 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
5657 NULL);
5658 }
5659
5660 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5661 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5662
5663 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
5664 image);
5665 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
5666 image);
5667 }
5668
5669 /* The Vulkan spec 1.1.98 says:
5670 *
5671 * "An execution dependency with only
5672 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
5673 * will only prevent that stage from executing in subsequently
5674 * submitted commands. As this stage does not perform any actual
5675 * execution, this is not observable - in effect, it does not delay
5676 * processing of subsequent commands. Similarly an execution dependency
5677 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
5678 * will effectively not wait for any prior commands to complete."
5679 */
5680 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
5681 radv_stage_flush(cmd_buffer, info->srcStageMask);
5682 cmd_buffer->state.flush_bits |= src_flush_bits;
5683
5684 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5685 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5686
5687 const struct VkSampleLocationsInfoEXT *sample_locs_info =
5688 vk_find_struct_const(pImageMemoryBarriers[i].pNext,
5689 SAMPLE_LOCATIONS_INFO_EXT);
5690 struct radv_sample_locations_state sample_locations = {};
5691
5692 if (sample_locs_info) {
5693 assert(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
5694 sample_locations.per_pixel = sample_locs_info->sampleLocationsPerPixel;
5695 sample_locations.grid_size = sample_locs_info->sampleLocationGridSize;
5696 sample_locations.count = sample_locs_info->sampleLocationsCount;
5697 typed_memcpy(&sample_locations.locations[0],
5698 sample_locs_info->pSampleLocations,
5699 sample_locs_info->sampleLocationsCount);
5700 }
5701
5702 radv_handle_image_transition(cmd_buffer, image,
5703 pImageMemoryBarriers[i].oldLayout,
5704 false, /* Outside of a renderpass we are never in a renderloop */
5705 pImageMemoryBarriers[i].newLayout,
5706 false, /* Outside of a renderpass we are never in a renderloop */
5707 pImageMemoryBarriers[i].srcQueueFamilyIndex,
5708 pImageMemoryBarriers[i].dstQueueFamilyIndex,
5709 &pImageMemoryBarriers[i].subresourceRange,
5710 sample_locs_info ? &sample_locations : NULL);
5711 }
5712
5713 /* Make sure CP DMA is idle because the driver might have performed a
5714 * DMA operation for copying or filling buffers/images.
5715 */
5716 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5717 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5718 si_cp_dma_wait_for_idle(cmd_buffer);
5719
5720 cmd_buffer->state.flush_bits |= dst_flush_bits;
5721 }
5722
5723 void radv_CmdPipelineBarrier(
5724 VkCommandBuffer commandBuffer,
5725 VkPipelineStageFlags srcStageMask,
5726 VkPipelineStageFlags destStageMask,
5727 VkBool32 byRegion,
5728 uint32_t memoryBarrierCount,
5729 const VkMemoryBarrier* pMemoryBarriers,
5730 uint32_t bufferMemoryBarrierCount,
5731 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5732 uint32_t imageMemoryBarrierCount,
5733 const VkImageMemoryBarrier* pImageMemoryBarriers)
5734 {
5735 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5736 struct radv_barrier_info info;
5737
5738 info.eventCount = 0;
5739 info.pEvents = NULL;
5740 info.srcStageMask = srcStageMask;
5741 info.dstStageMask = destStageMask;
5742
5743 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5744 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5745 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5746 }
5747
5748
5749 static void write_event(struct radv_cmd_buffer *cmd_buffer,
5750 struct radv_event *event,
5751 VkPipelineStageFlags stageMask,
5752 unsigned value)
5753 {
5754 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5755 uint64_t va = radv_buffer_get_va(event->bo);
5756
5757 si_emit_cache_flush(cmd_buffer);
5758
5759 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5760
5761 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 21);
5762
5763 /* Flags that only require a top-of-pipe event. */
5764 VkPipelineStageFlags top_of_pipe_flags =
5765 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
5766
5767 /* Flags that only require a post-index-fetch event. */
5768 VkPipelineStageFlags post_index_fetch_flags =
5769 top_of_pipe_flags |
5770 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
5771 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
5772
5773 /* Make sure CP DMA is idle because the driver might have performed a
5774 * DMA operation for copying or filling buffers/images.
5775 */
5776 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5777 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5778 si_cp_dma_wait_for_idle(cmd_buffer);
5779
5780 /* TODO: Emit EOS events for syncing PS/CS stages. */
5781
5782 if (!(stageMask & ~top_of_pipe_flags)) {
5783 /* Just need to sync the PFP engine. */
5784 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5785 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5786 S_370_WR_CONFIRM(1) |
5787 S_370_ENGINE_SEL(V_370_PFP));
5788 radeon_emit(cs, va);
5789 radeon_emit(cs, va >> 32);
5790 radeon_emit(cs, value);
5791 } else if (!(stageMask & ~post_index_fetch_flags)) {
5792 /* Sync ME because PFP reads index and indirect buffers. */
5793 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5794 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5795 S_370_WR_CONFIRM(1) |
5796 S_370_ENGINE_SEL(V_370_ME));
5797 radeon_emit(cs, va);
5798 radeon_emit(cs, va >> 32);
5799 radeon_emit(cs, value);
5800 } else {
5801 /* Otherwise, sync all prior GPU work using an EOP event. */
5802 si_cs_emit_write_event_eop(cs,
5803 cmd_buffer->device->physical_device->rad_info.chip_class,
5804 radv_cmd_buffer_uses_mec(cmd_buffer),
5805 V_028A90_BOTTOM_OF_PIPE_TS, 0,
5806 EOP_DST_SEL_MEM,
5807 EOP_DATA_SEL_VALUE_32BIT, va, value,
5808 cmd_buffer->gfx9_eop_bug_va);
5809 }
5810
5811 assert(cmd_buffer->cs->cdw <= cdw_max);
5812 }
5813
5814 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
5815 VkEvent _event,
5816 VkPipelineStageFlags stageMask)
5817 {
5818 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5819 RADV_FROM_HANDLE(radv_event, event, _event);
5820
5821 write_event(cmd_buffer, event, stageMask, 1);
5822 }
5823
5824 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
5825 VkEvent _event,
5826 VkPipelineStageFlags stageMask)
5827 {
5828 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5829 RADV_FROM_HANDLE(radv_event, event, _event);
5830
5831 write_event(cmd_buffer, event, stageMask, 0);
5832 }
5833
5834 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
5835 uint32_t eventCount,
5836 const VkEvent* pEvents,
5837 VkPipelineStageFlags srcStageMask,
5838 VkPipelineStageFlags dstStageMask,
5839 uint32_t memoryBarrierCount,
5840 const VkMemoryBarrier* pMemoryBarriers,
5841 uint32_t bufferMemoryBarrierCount,
5842 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5843 uint32_t imageMemoryBarrierCount,
5844 const VkImageMemoryBarrier* pImageMemoryBarriers)
5845 {
5846 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5847 struct radv_barrier_info info;
5848
5849 info.eventCount = eventCount;
5850 info.pEvents = pEvents;
5851 info.srcStageMask = 0;
5852
5853 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5854 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5855 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5856 }
5857
5858
5859 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
5860 uint32_t deviceMask)
5861 {
5862 /* No-op */
5863 }
5864
5865 /* VK_EXT_conditional_rendering */
5866 void radv_CmdBeginConditionalRenderingEXT(
5867 VkCommandBuffer commandBuffer,
5868 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
5869 {
5870 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5871 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
5872 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5873 bool draw_visible = true;
5874 uint64_t pred_value = 0;
5875 uint64_t va, new_va;
5876 unsigned pred_offset;
5877
5878 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
5879
5880 /* By default, if the 32-bit value at offset in buffer memory is zero,
5881 * then the rendering commands are discarded, otherwise they are
5882 * executed as normal. If the inverted flag is set, all commands are
5883 * discarded if the value is non zero.
5884 */
5885 if (pConditionalRenderingBegin->flags &
5886 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
5887 draw_visible = false;
5888 }
5889
5890 si_emit_cache_flush(cmd_buffer);
5891
5892 /* From the Vulkan spec 1.1.107:
5893 *
5894 * "If the 32-bit value at offset in buffer memory is zero, then the
5895 * rendering commands are discarded, otherwise they are executed as
5896 * normal. If the value of the predicate in buffer memory changes while
5897 * conditional rendering is active, the rendering commands may be
5898 * discarded in an implementation-dependent way. Some implementations
5899 * may latch the value of the predicate upon beginning conditional
5900 * rendering while others may read it before every rendering command."
5901 *
5902 * But, the AMD hardware treats the predicate as a 64-bit value which
5903 * means we need a workaround in the driver. Luckily, it's not required
5904 * to support if the value changes when predication is active.
5905 *
5906 * The workaround is as follows:
5907 * 1) allocate a 64-value in the upload BO and initialize it to 0
5908 * 2) copy the 32-bit predicate value to the upload BO
5909 * 3) use the new allocated VA address for predication
5910 *
5911 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
5912 * in ME (+ sync PFP) instead of PFP.
5913 */
5914 radv_cmd_buffer_upload_data(cmd_buffer, 8, 16, &pred_value, &pred_offset);
5915
5916 new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
5917
5918 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5919 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5920 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
5921 COPY_DATA_WR_CONFIRM);
5922 radeon_emit(cs, va);
5923 radeon_emit(cs, va >> 32);
5924 radeon_emit(cs, new_va);
5925 radeon_emit(cs, new_va >> 32);
5926
5927 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
5928 radeon_emit(cs, 0);
5929
5930 /* Enable predication for this command buffer. */
5931 si_emit_set_predication_state(cmd_buffer, draw_visible, new_va);
5932 cmd_buffer->state.predicating = true;
5933
5934 /* Store conditional rendering user info. */
5935 cmd_buffer->state.predication_type = draw_visible;
5936 cmd_buffer->state.predication_va = new_va;
5937 }
5938
5939 void radv_CmdEndConditionalRenderingEXT(
5940 VkCommandBuffer commandBuffer)
5941 {
5942 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5943
5944 /* Disable predication for this command buffer. */
5945 si_emit_set_predication_state(cmd_buffer, false, 0);
5946 cmd_buffer->state.predicating = false;
5947
5948 /* Reset conditional rendering user info. */
5949 cmd_buffer->state.predication_type = -1;
5950 cmd_buffer->state.predication_va = 0;
5951 }
5952
5953 /* VK_EXT_transform_feedback */
5954 void radv_CmdBindTransformFeedbackBuffersEXT(
5955 VkCommandBuffer commandBuffer,
5956 uint32_t firstBinding,
5957 uint32_t bindingCount,
5958 const VkBuffer* pBuffers,
5959 const VkDeviceSize* pOffsets,
5960 const VkDeviceSize* pSizes)
5961 {
5962 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5963 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5964 uint8_t enabled_mask = 0;
5965
5966 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
5967 for (uint32_t i = 0; i < bindingCount; i++) {
5968 uint32_t idx = firstBinding + i;
5969
5970 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
5971 sb[idx].offset = pOffsets[i];
5972 sb[idx].size = pSizes[i];
5973
5974 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
5975 sb[idx].buffer->bo);
5976
5977 enabled_mask |= 1 << idx;
5978 }
5979
5980 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
5981
5982 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
5983 }
5984
5985 static void
5986 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
5987 {
5988 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5989 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5990
5991 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
5992 radeon_emit(cs,
5993 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
5994 S_028B94_RAST_STREAM(0) |
5995 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
5996 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
5997 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
5998 radeon_emit(cs, so->hw_enabled_mask &
5999 so->enabled_stream_buffers_mask);
6000
6001 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6002 }
6003
6004 static void
6005 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
6006 {
6007 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6008 bool old_streamout_enabled = so->streamout_enabled;
6009 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
6010
6011 so->streamout_enabled = enable;
6012
6013 so->hw_enabled_mask = so->enabled_mask |
6014 (so->enabled_mask << 4) |
6015 (so->enabled_mask << 8) |
6016 (so->enabled_mask << 12);
6017
6018 if (!cmd_buffer->device->physical_device->use_ngg_streamout &&
6019 ((old_streamout_enabled != so->streamout_enabled) ||
6020 (old_hw_enabled_mask != so->hw_enabled_mask)))
6021 radv_emit_streamout_enable(cmd_buffer);
6022
6023 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6024 cmd_buffer->gds_needed = true;
6025 cmd_buffer->gds_oa_needed = true;
6026 }
6027 }
6028
6029 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
6030 {
6031 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6032 unsigned reg_strmout_cntl;
6033
6034 /* The register is at different places on different ASICs. */
6035 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
6036 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
6037 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
6038 } else {
6039 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
6040 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
6041 }
6042
6043 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
6044 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
6045
6046 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
6047 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
6048 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
6049 radeon_emit(cs, 0);
6050 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
6051 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
6052 radeon_emit(cs, 4); /* poll interval */
6053 }
6054
6055 static void
6056 radv_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
6057 uint32_t firstCounterBuffer,
6058 uint32_t counterBufferCount,
6059 const VkBuffer *pCounterBuffers,
6060 const VkDeviceSize *pCounterBufferOffsets)
6061
6062 {
6063 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
6064 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6065 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6066 uint32_t i;
6067
6068 radv_flush_vgt_streamout(cmd_buffer);
6069
6070 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6071 for_each_bit(i, so->enabled_mask) {
6072 int32_t counter_buffer_idx = i - firstCounterBuffer;
6073 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6074 counter_buffer_idx = -1;
6075
6076 /* AMD GCN binds streamout buffers as shader resources.
6077 * VGT only counts primitives and tells the shader through
6078 * SGPRs what to do.
6079 */
6080 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
6081 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
6082 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
6083
6084 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6085
6086 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6087 /* The array of counter buffers is optional. */
6088 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6089 uint64_t va = radv_buffer_get_va(buffer->bo);
6090
6091 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6092
6093 /* Append */
6094 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6095 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6096 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6097 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
6098 radeon_emit(cs, 0); /* unused */
6099 radeon_emit(cs, 0); /* unused */
6100 radeon_emit(cs, va); /* src address lo */
6101 radeon_emit(cs, va >> 32); /* src address hi */
6102
6103 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6104 } else {
6105 /* Start from the beginning. */
6106 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6107 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6108 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6109 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
6110 radeon_emit(cs, 0); /* unused */
6111 radeon_emit(cs, 0); /* unused */
6112 radeon_emit(cs, 0); /* unused */
6113 radeon_emit(cs, 0); /* unused */
6114 }
6115 }
6116
6117 radv_set_streamout_enable(cmd_buffer, true);
6118 }
6119
6120 static void
6121 gfx10_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
6122 uint32_t firstCounterBuffer,
6123 uint32_t counterBufferCount,
6124 const VkBuffer *pCounterBuffers,
6125 const VkDeviceSize *pCounterBufferOffsets)
6126 {
6127 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6128 unsigned last_target = util_last_bit(so->enabled_mask) - 1;
6129 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6130 uint32_t i;
6131
6132 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6133 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6134
6135 /* Sync because the next streamout operation will overwrite GDS and we
6136 * have to make sure it's idle.
6137 * TODO: Improve by tracking if there is a streamout operation in
6138 * flight.
6139 */
6140 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
6141 si_emit_cache_flush(cmd_buffer);
6142
6143 for_each_bit(i, so->enabled_mask) {
6144 int32_t counter_buffer_idx = i - firstCounterBuffer;
6145 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6146 counter_buffer_idx = -1;
6147
6148 bool append = counter_buffer_idx >= 0 &&
6149 pCounterBuffers && pCounterBuffers[counter_buffer_idx];
6150 uint64_t va = 0;
6151
6152 if (append) {
6153 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6154
6155 va += radv_buffer_get_va(buffer->bo);
6156 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6157
6158 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6159 }
6160
6161 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
6162 radeon_emit(cs, S_411_SRC_SEL(append ? V_411_SRC_ADDR_TC_L2 : V_411_DATA) |
6163 S_411_DST_SEL(V_411_GDS) |
6164 S_411_CP_SYNC(i == last_target));
6165 radeon_emit(cs, va);
6166 radeon_emit(cs, va >> 32);
6167 radeon_emit(cs, 4 * i); /* destination in GDS */
6168 radeon_emit(cs, 0);
6169 radeon_emit(cs, S_414_BYTE_COUNT_GFX9(4) |
6170 S_414_DISABLE_WR_CONFIRM_GFX9(i != last_target));
6171 }
6172
6173 radv_set_streamout_enable(cmd_buffer, true);
6174 }
6175
6176 void radv_CmdBeginTransformFeedbackEXT(
6177 VkCommandBuffer commandBuffer,
6178 uint32_t firstCounterBuffer,
6179 uint32_t counterBufferCount,
6180 const VkBuffer* pCounterBuffers,
6181 const VkDeviceSize* pCounterBufferOffsets)
6182 {
6183 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6184
6185 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6186 gfx10_emit_streamout_begin(cmd_buffer,
6187 firstCounterBuffer, counterBufferCount,
6188 pCounterBuffers, pCounterBufferOffsets);
6189 } else {
6190 radv_emit_streamout_begin(cmd_buffer,
6191 firstCounterBuffer, counterBufferCount,
6192 pCounterBuffers, pCounterBufferOffsets);
6193 }
6194 }
6195
6196 static void
6197 radv_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6198 uint32_t firstCounterBuffer,
6199 uint32_t counterBufferCount,
6200 const VkBuffer *pCounterBuffers,
6201 const VkDeviceSize *pCounterBufferOffsets)
6202 {
6203 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6204 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6205 uint32_t i;
6206
6207 radv_flush_vgt_streamout(cmd_buffer);
6208
6209 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6210 for_each_bit(i, so->enabled_mask) {
6211 int32_t counter_buffer_idx = i - firstCounterBuffer;
6212 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6213 counter_buffer_idx = -1;
6214
6215 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6216 /* The array of counters buffer is optional. */
6217 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6218 uint64_t va = radv_buffer_get_va(buffer->bo);
6219
6220 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6221
6222 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6223 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6224 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6225 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
6226 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
6227 radeon_emit(cs, va); /* dst address lo */
6228 radeon_emit(cs, va >> 32); /* dst address hi */
6229 radeon_emit(cs, 0); /* unused */
6230 radeon_emit(cs, 0); /* unused */
6231
6232 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6233 }
6234
6235 /* Deactivate transform feedback by zeroing the buffer size.
6236 * The counters (primitives generated, primitives emitted) may
6237 * be enabled even if there is not buffer bound. This ensures
6238 * that the primitives-emitted query won't increment.
6239 */
6240 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
6241
6242 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6243 }
6244
6245 radv_set_streamout_enable(cmd_buffer, false);
6246 }
6247
6248 static void
6249 gfx10_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6250 uint32_t firstCounterBuffer,
6251 uint32_t counterBufferCount,
6252 const VkBuffer *pCounterBuffers,
6253 const VkDeviceSize *pCounterBufferOffsets)
6254 {
6255 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6256 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6257 uint32_t i;
6258
6259 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6260 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6261
6262 for_each_bit(i, so->enabled_mask) {
6263 int32_t counter_buffer_idx = i - firstCounterBuffer;
6264 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6265 counter_buffer_idx = -1;
6266
6267 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6268 /* The array of counters buffer is optional. */
6269 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6270 uint64_t va = radv_buffer_get_va(buffer->bo);
6271
6272 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6273
6274 si_cs_emit_write_event_eop(cs,
6275 cmd_buffer->device->physical_device->rad_info.chip_class,
6276 radv_cmd_buffer_uses_mec(cmd_buffer),
6277 V_028A90_PS_DONE, 0,
6278 EOP_DST_SEL_TC_L2,
6279 EOP_DATA_SEL_GDS,
6280 va, EOP_DATA_GDS(i, 1), 0);
6281
6282 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6283 }
6284 }
6285
6286 radv_set_streamout_enable(cmd_buffer, false);
6287 }
6288
6289 void radv_CmdEndTransformFeedbackEXT(
6290 VkCommandBuffer commandBuffer,
6291 uint32_t firstCounterBuffer,
6292 uint32_t counterBufferCount,
6293 const VkBuffer* pCounterBuffers,
6294 const VkDeviceSize* pCounterBufferOffsets)
6295 {
6296 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6297
6298 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6299 gfx10_emit_streamout_end(cmd_buffer,
6300 firstCounterBuffer, counterBufferCount,
6301 pCounterBuffers, pCounterBufferOffsets);
6302 } else {
6303 radv_emit_streamout_end(cmd_buffer,
6304 firstCounterBuffer, counterBufferCount,
6305 pCounterBuffers, pCounterBufferOffsets);
6306 }
6307 }
6308
6309 void radv_CmdDrawIndirectByteCountEXT(
6310 VkCommandBuffer commandBuffer,
6311 uint32_t instanceCount,
6312 uint32_t firstInstance,
6313 VkBuffer _counterBuffer,
6314 VkDeviceSize counterBufferOffset,
6315 uint32_t counterOffset,
6316 uint32_t vertexStride)
6317 {
6318 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6319 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
6320 struct radv_draw_info info = {};
6321
6322 info.instance_count = instanceCount;
6323 info.first_instance = firstInstance;
6324 info.strmout_buffer = counterBuffer;
6325 info.strmout_buffer_offset = counterBufferOffset;
6326 info.stride = vertexStride;
6327
6328 radv_draw(cmd_buffer, &info);
6329 }
6330
6331 /* VK_AMD_buffer_marker */
6332 void radv_CmdWriteBufferMarkerAMD(
6333 VkCommandBuffer commandBuffer,
6334 VkPipelineStageFlagBits pipelineStage,
6335 VkBuffer dstBuffer,
6336 VkDeviceSize dstOffset,
6337 uint32_t marker)
6338 {
6339 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6340 RADV_FROM_HANDLE(radv_buffer, buffer, dstBuffer);
6341 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6342 uint64_t va = radv_buffer_get_va(buffer->bo) + dstOffset;
6343
6344 si_emit_cache_flush(cmd_buffer);
6345
6346 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 12);
6347
6348 if (!(pipelineStage & ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT)) {
6349 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
6350 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
6351 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
6352 COPY_DATA_WR_CONFIRM);
6353 radeon_emit(cs, marker);
6354 radeon_emit(cs, 0);
6355 radeon_emit(cs, va);
6356 radeon_emit(cs, va >> 32);
6357 } else {
6358 si_cs_emit_write_event_eop(cs,
6359 cmd_buffer->device->physical_device->rad_info.chip_class,
6360 radv_cmd_buffer_uses_mec(cmd_buffer),
6361 V_028A90_BOTTOM_OF_PIPE_TS, 0,
6362 EOP_DST_SEL_MEM,
6363 EOP_DATA_SEL_VALUE_32BIT,
6364 va, marker,
6365 cmd_buffer->gfx9_eop_bug_va);
6366 }
6367
6368 assert(cmd_buffer->cs->cdw <= cdw_max);
6369 }