2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
33 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
41 RADV_PREFETCH_VBO_DESCRIPTORS
= (1 << 0),
42 RADV_PREFETCH_VS
= (1 << 1),
43 RADV_PREFETCH_TCS
= (1 << 2),
44 RADV_PREFETCH_TES
= (1 << 3),
45 RADV_PREFETCH_GS
= (1 << 4),
46 RADV_PREFETCH_PS
= (1 << 5),
47 RADV_PREFETCH_SHADERS
= (RADV_PREFETCH_VS
|
54 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
55 struct radv_image
*image
,
56 VkImageLayout src_layout
,
58 VkImageLayout dst_layout
,
62 const VkImageSubresourceRange
*range
,
63 struct radv_sample_locations_state
*sample_locs
);
65 const struct radv_dynamic_state default_dynamic_state
= {
78 .blend_constants
= { 0.0f
, 0.0f
, 0.0f
, 0.0f
},
83 .stencil_compare_mask
= {
87 .stencil_write_mask
= {
91 .stencil_reference
= {
98 radv_bind_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
,
99 const struct radv_dynamic_state
*src
)
101 struct radv_dynamic_state
*dest
= &cmd_buffer
->state
.dynamic
;
102 uint32_t copy_mask
= src
->mask
;
103 uint32_t dest_mask
= 0;
105 /* Make sure to copy the number of viewports/scissors because they can
106 * only be specified at pipeline creation time.
108 dest
->viewport
.count
= src
->viewport
.count
;
109 dest
->scissor
.count
= src
->scissor
.count
;
110 dest
->discard_rectangle
.count
= src
->discard_rectangle
.count
;
111 dest
->sample_location
.count
= src
->sample_location
.count
;
113 if (copy_mask
& RADV_DYNAMIC_VIEWPORT
) {
114 if (memcmp(&dest
->viewport
.viewports
, &src
->viewport
.viewports
,
115 src
->viewport
.count
* sizeof(VkViewport
))) {
116 typed_memcpy(dest
->viewport
.viewports
,
117 src
->viewport
.viewports
,
118 src
->viewport
.count
);
119 dest_mask
|= RADV_DYNAMIC_VIEWPORT
;
123 if (copy_mask
& RADV_DYNAMIC_SCISSOR
) {
124 if (memcmp(&dest
->scissor
.scissors
, &src
->scissor
.scissors
,
125 src
->scissor
.count
* sizeof(VkRect2D
))) {
126 typed_memcpy(dest
->scissor
.scissors
,
127 src
->scissor
.scissors
, src
->scissor
.count
);
128 dest_mask
|= RADV_DYNAMIC_SCISSOR
;
132 if (copy_mask
& RADV_DYNAMIC_LINE_WIDTH
) {
133 if (dest
->line_width
!= src
->line_width
) {
134 dest
->line_width
= src
->line_width
;
135 dest_mask
|= RADV_DYNAMIC_LINE_WIDTH
;
139 if (copy_mask
& RADV_DYNAMIC_DEPTH_BIAS
) {
140 if (memcmp(&dest
->depth_bias
, &src
->depth_bias
,
141 sizeof(src
->depth_bias
))) {
142 dest
->depth_bias
= src
->depth_bias
;
143 dest_mask
|= RADV_DYNAMIC_DEPTH_BIAS
;
147 if (copy_mask
& RADV_DYNAMIC_BLEND_CONSTANTS
) {
148 if (memcmp(&dest
->blend_constants
, &src
->blend_constants
,
149 sizeof(src
->blend_constants
))) {
150 typed_memcpy(dest
->blend_constants
,
151 src
->blend_constants
, 4);
152 dest_mask
|= RADV_DYNAMIC_BLEND_CONSTANTS
;
156 if (copy_mask
& RADV_DYNAMIC_DEPTH_BOUNDS
) {
157 if (memcmp(&dest
->depth_bounds
, &src
->depth_bounds
,
158 sizeof(src
->depth_bounds
))) {
159 dest
->depth_bounds
= src
->depth_bounds
;
160 dest_mask
|= RADV_DYNAMIC_DEPTH_BOUNDS
;
164 if (copy_mask
& RADV_DYNAMIC_STENCIL_COMPARE_MASK
) {
165 if (memcmp(&dest
->stencil_compare_mask
,
166 &src
->stencil_compare_mask
,
167 sizeof(src
->stencil_compare_mask
))) {
168 dest
->stencil_compare_mask
= src
->stencil_compare_mask
;
169 dest_mask
|= RADV_DYNAMIC_STENCIL_COMPARE_MASK
;
173 if (copy_mask
& RADV_DYNAMIC_STENCIL_WRITE_MASK
) {
174 if (memcmp(&dest
->stencil_write_mask
, &src
->stencil_write_mask
,
175 sizeof(src
->stencil_write_mask
))) {
176 dest
->stencil_write_mask
= src
->stencil_write_mask
;
177 dest_mask
|= RADV_DYNAMIC_STENCIL_WRITE_MASK
;
181 if (copy_mask
& RADV_DYNAMIC_STENCIL_REFERENCE
) {
182 if (memcmp(&dest
->stencil_reference
, &src
->stencil_reference
,
183 sizeof(src
->stencil_reference
))) {
184 dest
->stencil_reference
= src
->stencil_reference
;
185 dest_mask
|= RADV_DYNAMIC_STENCIL_REFERENCE
;
189 if (copy_mask
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
190 if (memcmp(&dest
->discard_rectangle
.rectangles
, &src
->discard_rectangle
.rectangles
,
191 src
->discard_rectangle
.count
* sizeof(VkRect2D
))) {
192 typed_memcpy(dest
->discard_rectangle
.rectangles
,
193 src
->discard_rectangle
.rectangles
,
194 src
->discard_rectangle
.count
);
195 dest_mask
|= RADV_DYNAMIC_DISCARD_RECTANGLE
;
199 if (copy_mask
& RADV_DYNAMIC_SAMPLE_LOCATIONS
) {
200 if (dest
->sample_location
.per_pixel
!= src
->sample_location
.per_pixel
||
201 dest
->sample_location
.grid_size
.width
!= src
->sample_location
.grid_size
.width
||
202 dest
->sample_location
.grid_size
.height
!= src
->sample_location
.grid_size
.height
||
203 memcmp(&dest
->sample_location
.locations
,
204 &src
->sample_location
.locations
,
205 src
->sample_location
.count
* sizeof(VkSampleLocationEXT
))) {
206 dest
->sample_location
.per_pixel
= src
->sample_location
.per_pixel
;
207 dest
->sample_location
.grid_size
= src
->sample_location
.grid_size
;
208 typed_memcpy(dest
->sample_location
.locations
,
209 src
->sample_location
.locations
,
210 src
->sample_location
.count
);
211 dest_mask
|= RADV_DYNAMIC_SAMPLE_LOCATIONS
;
215 cmd_buffer
->state
.dirty
|= dest_mask
;
219 radv_bind_streamout_state(struct radv_cmd_buffer
*cmd_buffer
,
220 struct radv_pipeline
*pipeline
)
222 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
223 struct radv_shader_info
*info
;
225 if (!pipeline
->streamout_shader
||
226 cmd_buffer
->device
->physical_device
->use_ngg_streamout
)
229 info
= &pipeline
->streamout_shader
->info
;
230 for (int i
= 0; i
< MAX_SO_BUFFERS
; i
++)
231 so
->stride_in_dw
[i
] = info
->so
.strides
[i
];
233 so
->enabled_stream_buffers_mask
= info
->so
.enabled_stream_buffers_mask
;
236 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
)
238 return cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
239 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
242 enum ring_type
radv_queue_family_to_ring(int f
) {
244 case RADV_QUEUE_GENERAL
:
246 case RADV_QUEUE_COMPUTE
:
248 case RADV_QUEUE_TRANSFER
:
251 unreachable("Unknown queue family");
255 static VkResult
radv_create_cmd_buffer(
256 struct radv_device
* device
,
257 struct radv_cmd_pool
* pool
,
258 VkCommandBufferLevel level
,
259 VkCommandBuffer
* pCommandBuffer
)
261 struct radv_cmd_buffer
*cmd_buffer
;
263 cmd_buffer
= vk_zalloc(&pool
->alloc
, sizeof(*cmd_buffer
), 8,
264 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
265 if (cmd_buffer
== NULL
)
266 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
268 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
269 cmd_buffer
->device
= device
;
270 cmd_buffer
->pool
= pool
;
271 cmd_buffer
->level
= level
;
274 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
275 cmd_buffer
->queue_family_index
= pool
->queue_family_index
;
278 /* Init the pool_link so we can safely call list_del when we destroy
281 list_inithead(&cmd_buffer
->pool_link
);
282 cmd_buffer
->queue_family_index
= RADV_QUEUE_GENERAL
;
285 ring
= radv_queue_family_to_ring(cmd_buffer
->queue_family_index
);
287 cmd_buffer
->cs
= device
->ws
->cs_create(device
->ws
, ring
);
288 if (!cmd_buffer
->cs
) {
289 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
290 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
293 *pCommandBuffer
= radv_cmd_buffer_to_handle(cmd_buffer
);
295 list_inithead(&cmd_buffer
->upload
.list
);
301 radv_cmd_buffer_destroy(struct radv_cmd_buffer
*cmd_buffer
)
303 list_del(&cmd_buffer
->pool_link
);
305 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
306 &cmd_buffer
->upload
.list
, list
) {
307 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
312 if (cmd_buffer
->upload
.upload_bo
)
313 cmd_buffer
->device
->ws
->buffer_destroy(cmd_buffer
->upload
.upload_bo
);
314 cmd_buffer
->device
->ws
->cs_destroy(cmd_buffer
->cs
);
316 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++)
317 free(cmd_buffer
->descriptors
[i
].push_set
.set
.mapped_ptr
);
319 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
323 radv_reset_cmd_buffer(struct radv_cmd_buffer
*cmd_buffer
)
325 cmd_buffer
->device
->ws
->cs_reset(cmd_buffer
->cs
);
327 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
328 &cmd_buffer
->upload
.list
, list
) {
329 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
334 cmd_buffer
->push_constant_stages
= 0;
335 cmd_buffer
->scratch_size_needed
= 0;
336 cmd_buffer
->compute_scratch_size_needed
= 0;
337 cmd_buffer
->esgs_ring_size_needed
= 0;
338 cmd_buffer
->gsvs_ring_size_needed
= 0;
339 cmd_buffer
->tess_rings_needed
= false;
340 cmd_buffer
->gds_needed
= false;
341 cmd_buffer
->sample_positions_needed
= false;
343 if (cmd_buffer
->upload
.upload_bo
)
344 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
345 cmd_buffer
->upload
.upload_bo
);
346 cmd_buffer
->upload
.offset
= 0;
348 cmd_buffer
->record_result
= VK_SUCCESS
;
350 memset(cmd_buffer
->vertex_bindings
, 0, sizeof(cmd_buffer
->vertex_bindings
));
352 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++) {
353 cmd_buffer
->descriptors
[i
].dirty
= 0;
354 cmd_buffer
->descriptors
[i
].valid
= 0;
355 cmd_buffer
->descriptors
[i
].push_dirty
= false;
358 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
359 cmd_buffer
->queue_family_index
== RADV_QUEUE_GENERAL
) {
360 unsigned num_db
= cmd_buffer
->device
->physical_device
->rad_info
.num_render_backends
;
361 unsigned fence_offset
, eop_bug_offset
;
364 radv_cmd_buffer_upload_alloc(cmd_buffer
, 8, 8, &fence_offset
,
367 cmd_buffer
->gfx9_fence_va
=
368 radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
369 cmd_buffer
->gfx9_fence_va
+= fence_offset
;
371 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
372 /* Allocate a buffer for the EOP bug on GFX9. */
373 radv_cmd_buffer_upload_alloc(cmd_buffer
, 16 * num_db
, 8,
374 &eop_bug_offset
, &fence_ptr
);
375 cmd_buffer
->gfx9_eop_bug_va
=
376 radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
377 cmd_buffer
->gfx9_eop_bug_va
+= eop_bug_offset
;
381 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_INITIAL
;
383 return cmd_buffer
->record_result
;
387 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer
*cmd_buffer
,
391 struct radeon_winsys_bo
*bo
;
392 struct radv_cmd_buffer_upload
*upload
;
393 struct radv_device
*device
= cmd_buffer
->device
;
395 new_size
= MAX2(min_needed
, 16 * 1024);
396 new_size
= MAX2(new_size
, 2 * cmd_buffer
->upload
.size
);
398 bo
= device
->ws
->buffer_create(device
->ws
,
401 RADEON_FLAG_CPU_ACCESS
|
402 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
404 RADV_BO_PRIORITY_UPLOAD_BUFFER
);
407 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
411 radv_cs_add_buffer(device
->ws
, cmd_buffer
->cs
, bo
);
412 if (cmd_buffer
->upload
.upload_bo
) {
413 upload
= malloc(sizeof(*upload
));
416 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
417 device
->ws
->buffer_destroy(bo
);
421 memcpy(upload
, &cmd_buffer
->upload
, sizeof(*upload
));
422 list_add(&upload
->list
, &cmd_buffer
->upload
.list
);
425 cmd_buffer
->upload
.upload_bo
= bo
;
426 cmd_buffer
->upload
.size
= new_size
;
427 cmd_buffer
->upload
.offset
= 0;
428 cmd_buffer
->upload
.map
= device
->ws
->buffer_map(cmd_buffer
->upload
.upload_bo
);
430 if (!cmd_buffer
->upload
.map
) {
431 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
439 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
442 unsigned *out_offset
,
445 assert(util_is_power_of_two_nonzero(alignment
));
447 uint64_t offset
= align(cmd_buffer
->upload
.offset
, alignment
);
448 if (offset
+ size
> cmd_buffer
->upload
.size
) {
449 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer
, size
))
454 *out_offset
= offset
;
455 *ptr
= cmd_buffer
->upload
.map
+ offset
;
457 cmd_buffer
->upload
.offset
= offset
+ size
;
462 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
463 unsigned size
, unsigned alignment
,
464 const void *data
, unsigned *out_offset
)
468 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
, alignment
,
469 out_offset
, (void **)&ptr
))
473 memcpy(ptr
, data
, size
);
479 radv_emit_write_data_packet(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
480 unsigned count
, const uint32_t *data
)
482 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
484 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 4 + count
);
486 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, 0));
487 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
488 S_370_WR_CONFIRM(1) |
489 S_370_ENGINE_SEL(V_370_ME
));
491 radeon_emit(cs
, va
>> 32);
492 radeon_emit_array(cs
, data
, count
);
495 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
)
497 struct radv_device
*device
= cmd_buffer
->device
;
498 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
501 va
= radv_buffer_get_va(device
->trace_bo
);
502 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
)
505 ++cmd_buffer
->state
.trace_id
;
506 radv_emit_write_data_packet(cmd_buffer
, va
, 1,
507 &cmd_buffer
->state
.trace_id
);
509 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 2);
511 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
512 radeon_emit(cs
, AC_ENCODE_TRACE_POINT(cmd_buffer
->state
.trace_id
));
516 radv_cmd_buffer_after_draw(struct radv_cmd_buffer
*cmd_buffer
,
517 enum radv_cmd_flush_bits flags
)
519 if (cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_SYNC_SHADERS
) {
520 assert(flags
& (RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
521 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
));
523 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 4);
525 /* Force wait for graphics or compute engines to be idle. */
526 si_cs_emit_cache_flush(cmd_buffer
->cs
,
527 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
528 &cmd_buffer
->gfx9_fence_idx
,
529 cmd_buffer
->gfx9_fence_va
,
530 radv_cmd_buffer_uses_mec(cmd_buffer
),
531 flags
, cmd_buffer
->gfx9_eop_bug_va
);
534 if (unlikely(cmd_buffer
->device
->trace_bo
))
535 radv_cmd_buffer_trace_emit(cmd_buffer
);
539 radv_save_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
540 struct radv_pipeline
*pipeline
, enum ring_type ring
)
542 struct radv_device
*device
= cmd_buffer
->device
;
546 va
= radv_buffer_get_va(device
->trace_bo
);
556 assert(!"invalid ring type");
559 data
[0] = (uintptr_t)pipeline
;
560 data
[1] = (uintptr_t)pipeline
>> 32;
562 radv_emit_write_data_packet(cmd_buffer
, va
, 2, data
);
565 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
566 VkPipelineBindPoint bind_point
,
567 struct radv_descriptor_set
*set
,
570 struct radv_descriptor_state
*descriptors_state
=
571 radv_get_descriptors_state(cmd_buffer
, bind_point
);
573 descriptors_state
->sets
[idx
] = set
;
575 descriptors_state
->valid
|= (1u << idx
); /* active descriptors */
576 descriptors_state
->dirty
|= (1u << idx
);
580 radv_save_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
581 VkPipelineBindPoint bind_point
)
583 struct radv_descriptor_state
*descriptors_state
=
584 radv_get_descriptors_state(cmd_buffer
, bind_point
);
585 struct radv_device
*device
= cmd_buffer
->device
;
586 uint32_t data
[MAX_SETS
* 2] = {};
589 va
= radv_buffer_get_va(device
->trace_bo
) + 24;
591 for_each_bit(i
, descriptors_state
->valid
) {
592 struct radv_descriptor_set
*set
= descriptors_state
->sets
[i
];
593 data
[i
* 2] = (uint64_t)(uintptr_t)set
;
594 data
[i
* 2 + 1] = (uint64_t)(uintptr_t)set
>> 32;
597 radv_emit_write_data_packet(cmd_buffer
, va
, MAX_SETS
* 2, data
);
600 struct radv_userdata_info
*
601 radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
602 gl_shader_stage stage
,
605 struct radv_shader_variant
*shader
= radv_get_shader(pipeline
, stage
);
606 return &shader
->info
.user_sgprs_locs
.shader_data
[idx
];
610 radv_emit_userdata_address(struct radv_cmd_buffer
*cmd_buffer
,
611 struct radv_pipeline
*pipeline
,
612 gl_shader_stage stage
,
613 int idx
, uint64_t va
)
615 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, idx
);
616 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
617 if (loc
->sgpr_idx
== -1)
620 assert(loc
->num_sgprs
== 1);
622 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
623 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
627 radv_emit_descriptor_pointers(struct radv_cmd_buffer
*cmd_buffer
,
628 struct radv_pipeline
*pipeline
,
629 struct radv_descriptor_state
*descriptors_state
,
630 gl_shader_stage stage
)
632 struct radv_device
*device
= cmd_buffer
->device
;
633 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
634 uint32_t sh_base
= pipeline
->user_data_0
[stage
];
635 struct radv_userdata_locations
*locs
=
636 &pipeline
->shaders
[stage
]->info
.user_sgprs_locs
;
637 unsigned mask
= locs
->descriptor_sets_enabled
;
639 mask
&= descriptors_state
->dirty
& descriptors_state
->valid
;
644 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
646 struct radv_userdata_info
*loc
= &locs
->descriptor_sets
[start
];
647 unsigned sh_offset
= sh_base
+ loc
->sgpr_idx
* 4;
649 radv_emit_shader_pointer_head(cs
, sh_offset
, count
, true);
650 for (int i
= 0; i
< count
; i
++) {
651 struct radv_descriptor_set
*set
=
652 descriptors_state
->sets
[start
+ i
];
654 radv_emit_shader_pointer_body(device
, cs
, set
->va
, true);
660 * Convert the user sample locations to hardware sample locations (the values
661 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
664 radv_convert_user_sample_locs(struct radv_sample_locations_state
*state
,
665 uint32_t x
, uint32_t y
, VkOffset2D
*sample_locs
)
667 uint32_t x_offset
= x
% state
->grid_size
.width
;
668 uint32_t y_offset
= y
% state
->grid_size
.height
;
669 uint32_t num_samples
= (uint32_t)state
->per_pixel
;
670 VkSampleLocationEXT
*user_locs
;
671 uint32_t pixel_offset
;
673 pixel_offset
= (x_offset
+ y_offset
* state
->grid_size
.width
) * num_samples
;
675 assert(pixel_offset
<= MAX_SAMPLE_LOCATIONS
);
676 user_locs
= &state
->locations
[pixel_offset
];
678 for (uint32_t i
= 0; i
< num_samples
; i
++) {
679 float shifted_pos_x
= user_locs
[i
].x
- 0.5;
680 float shifted_pos_y
= user_locs
[i
].y
- 0.5;
682 int32_t scaled_pos_x
= floor(shifted_pos_x
* 16);
683 int32_t scaled_pos_y
= floor(shifted_pos_y
* 16);
685 sample_locs
[i
].x
= CLAMP(scaled_pos_x
, -8, 7);
686 sample_locs
[i
].y
= CLAMP(scaled_pos_y
, -8, 7);
691 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
695 radv_compute_sample_locs_pixel(uint32_t num_samples
, VkOffset2D
*sample_locs
,
696 uint32_t *sample_locs_pixel
)
698 for (uint32_t i
= 0; i
< num_samples
; i
++) {
699 uint32_t sample_reg_idx
= i
/ 4;
700 uint32_t sample_loc_idx
= i
% 4;
701 int32_t pos_x
= sample_locs
[i
].x
;
702 int32_t pos_y
= sample_locs
[i
].y
;
704 uint32_t shift_x
= 8 * sample_loc_idx
;
705 uint32_t shift_y
= shift_x
+ 4;
707 sample_locs_pixel
[sample_reg_idx
] |= (pos_x
& 0xf) << shift_x
;
708 sample_locs_pixel
[sample_reg_idx
] |= (pos_y
& 0xf) << shift_y
;
713 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
717 radv_compute_centroid_priority(struct radv_cmd_buffer
*cmd_buffer
,
718 VkOffset2D
*sample_locs
,
719 uint32_t num_samples
)
721 uint32_t centroid_priorities
[num_samples
];
722 uint32_t sample_mask
= num_samples
- 1;
723 uint32_t distances
[num_samples
];
724 uint64_t centroid_priority
= 0;
726 /* Compute the distances from center for each sample. */
727 for (int i
= 0; i
< num_samples
; i
++) {
728 distances
[i
] = (sample_locs
[i
].x
* sample_locs
[i
].x
) +
729 (sample_locs
[i
].y
* sample_locs
[i
].y
);
732 /* Compute the centroid priorities by looking at the distances array. */
733 for (int i
= 0; i
< num_samples
; i
++) {
734 uint32_t min_idx
= 0;
736 for (int j
= 1; j
< num_samples
; j
++) {
737 if (distances
[j
] < distances
[min_idx
])
741 centroid_priorities
[i
] = min_idx
;
742 distances
[min_idx
] = 0xffffffff;
745 /* Compute the final centroid priority. */
746 for (int i
= 0; i
< 8; i
++) {
748 centroid_priorities
[i
& sample_mask
] << (i
* 4);
751 return centroid_priority
<< 32 | centroid_priority
;
755 * Emit the sample locations that are specified with VK_EXT_sample_locations.
758 radv_emit_sample_locations(struct radv_cmd_buffer
*cmd_buffer
)
760 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
761 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
762 struct radv_sample_locations_state
*sample_location
=
763 &cmd_buffer
->state
.dynamic
.sample_location
;
764 uint32_t num_samples
= (uint32_t)sample_location
->per_pixel
;
765 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
766 uint32_t sample_locs_pixel
[4][2] = {};
767 VkOffset2D sample_locs
[4][8]; /* 8 is the max. sample count supported */
768 uint32_t max_sample_dist
= 0;
769 uint64_t centroid_priority
;
771 if (!cmd_buffer
->state
.dynamic
.sample_location
.count
)
774 /* Convert the user sample locations to hardware sample locations. */
775 radv_convert_user_sample_locs(sample_location
, 0, 0, sample_locs
[0]);
776 radv_convert_user_sample_locs(sample_location
, 1, 0, sample_locs
[1]);
777 radv_convert_user_sample_locs(sample_location
, 0, 1, sample_locs
[2]);
778 radv_convert_user_sample_locs(sample_location
, 1, 1, sample_locs
[3]);
780 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
781 for (uint32_t i
= 0; i
< 4; i
++) {
782 radv_compute_sample_locs_pixel(num_samples
, sample_locs
[i
],
783 sample_locs_pixel
[i
]);
786 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
788 radv_compute_centroid_priority(cmd_buffer
, sample_locs
[0],
791 /* Compute the maximum sample distance from the specified locations. */
792 for (uint32_t i
= 0; i
< num_samples
; i
++) {
793 VkOffset2D offset
= sample_locs
[0][i
];
794 max_sample_dist
= MAX2(max_sample_dist
,
795 MAX2(abs(offset
.x
), abs(offset
.y
)));
798 /* Emit the specified user sample locations. */
799 switch (num_samples
) {
802 radeon_set_context_reg(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_pixel
[0][0]);
803 radeon_set_context_reg(cs
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_pixel
[1][0]);
804 radeon_set_context_reg(cs
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_pixel
[2][0]);
805 radeon_set_context_reg(cs
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_pixel
[3][0]);
808 radeon_set_context_reg(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_pixel
[0][0]);
809 radeon_set_context_reg(cs
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_pixel
[1][0]);
810 radeon_set_context_reg(cs
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_pixel
[2][0]);
811 radeon_set_context_reg(cs
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_pixel
[3][0]);
812 radeon_set_context_reg(cs
, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1
, sample_locs_pixel
[0][1]);
813 radeon_set_context_reg(cs
, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1
, sample_locs_pixel
[1][1]);
814 radeon_set_context_reg(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1
, sample_locs_pixel
[2][1]);
815 radeon_set_context_reg(cs
, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1
, sample_locs_pixel
[3][1]);
818 unreachable("invalid number of samples");
821 /* Emit the maximum sample distance and the centroid priority. */
822 uint32_t pa_sc_aa_config
= ms
->pa_sc_aa_config
;
824 pa_sc_aa_config
&= C_028BE0_MAX_SAMPLE_DIST
;
825 pa_sc_aa_config
|= S_028BE0_MAX_SAMPLE_DIST(max_sample_dist
);
827 radeon_set_context_reg_seq(cs
, R_028BE0_PA_SC_AA_CONFIG
, 1);
828 radeon_emit(cs
, pa_sc_aa_config
);
830 radeon_set_context_reg_seq(cs
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 2);
831 radeon_emit(cs
, centroid_priority
);
832 radeon_emit(cs
, centroid_priority
>> 32);
834 /* GFX9: Flush DFSM when the AA mode changes. */
835 if (cmd_buffer
->device
->dfsm_allowed
) {
836 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
837 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
840 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
844 radv_emit_inline_push_consts(struct radv_cmd_buffer
*cmd_buffer
,
845 struct radv_pipeline
*pipeline
,
846 gl_shader_stage stage
,
847 int idx
, int count
, uint32_t *values
)
849 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, idx
);
850 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
851 if (loc
->sgpr_idx
== -1)
854 assert(loc
->num_sgprs
== count
);
856 radeon_set_sh_reg_seq(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, count
);
857 radeon_emit_array(cmd_buffer
->cs
, values
, count
);
861 radv_update_multisample_state(struct radv_cmd_buffer
*cmd_buffer
,
862 struct radv_pipeline
*pipeline
)
864 int num_samples
= pipeline
->graphics
.ms
.num_samples
;
865 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
866 struct radv_pipeline
*old_pipeline
= cmd_buffer
->state
.emitted_pipeline
;
868 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.needs_sample_positions
)
869 cmd_buffer
->sample_positions_needed
= true;
871 if (old_pipeline
&& num_samples
== old_pipeline
->graphics
.ms
.num_samples
)
874 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028BDC_PA_SC_LINE_CNTL
, 2);
875 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_line_cntl
);
876 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_config
);
878 radeon_set_context_reg(cmd_buffer
->cs
, R_028A48_PA_SC_MODE_CNTL_0
, ms
->pa_sc_mode_cntl_0
);
880 radv_emit_default_sample_locations(cmd_buffer
->cs
, num_samples
);
882 /* GFX9: Flush DFSM when the AA mode changes. */
883 if (cmd_buffer
->device
->dfsm_allowed
) {
884 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
885 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
888 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
892 radv_update_binning_state(struct radv_cmd_buffer
*cmd_buffer
,
893 struct radv_pipeline
*pipeline
)
895 const struct radv_pipeline
*old_pipeline
= cmd_buffer
->state
.emitted_pipeline
;
898 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX9
)
902 old_pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
== pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
&&
903 old_pipeline
->graphics
.binning
.db_dfsm_control
== pipeline
->graphics
.binning
.db_dfsm_control
)
906 bool binning_flush
= false;
907 if (cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_VEGA12
||
908 cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_VEGA20
||
909 cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_RAVEN2
||
910 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
911 binning_flush
= !old_pipeline
||
912 G_028C44_BINNING_MODE(old_pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
) !=
913 G_028C44_BINNING_MODE(pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
);
916 radeon_set_context_reg(cmd_buffer
->cs
, R_028C44_PA_SC_BINNER_CNTL_0
,
917 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
|
918 S_028C44_FLUSH_ON_BINNING_TRANSITION(!!binning_flush
));
920 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
921 radeon_set_context_reg(cmd_buffer
->cs
, R_028038_DB_DFSM_CONTROL
,
922 pipeline
->graphics
.binning
.db_dfsm_control
);
924 radeon_set_context_reg(cmd_buffer
->cs
, R_028060_DB_DFSM_CONTROL
,
925 pipeline
->graphics
.binning
.db_dfsm_control
);
928 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
933 radv_emit_shader_prefetch(struct radv_cmd_buffer
*cmd_buffer
,
934 struct radv_shader_variant
*shader
)
941 va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
943 si_cp_dma_prefetch(cmd_buffer
, va
, shader
->code_size
);
947 radv_emit_prefetch_L2(struct radv_cmd_buffer
*cmd_buffer
,
948 struct radv_pipeline
*pipeline
,
949 bool vertex_stage_only
)
951 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
952 uint32_t mask
= state
->prefetch_L2_mask
;
954 if (vertex_stage_only
) {
955 /* Fast prefetch path for starting draws as soon as possible.
957 mask
= state
->prefetch_L2_mask
& (RADV_PREFETCH_VS
|
958 RADV_PREFETCH_VBO_DESCRIPTORS
);
961 if (mask
& RADV_PREFETCH_VS
)
962 radv_emit_shader_prefetch(cmd_buffer
,
963 pipeline
->shaders
[MESA_SHADER_VERTEX
]);
965 if (mask
& RADV_PREFETCH_VBO_DESCRIPTORS
)
966 si_cp_dma_prefetch(cmd_buffer
, state
->vb_va
, state
->vb_size
);
968 if (mask
& RADV_PREFETCH_TCS
)
969 radv_emit_shader_prefetch(cmd_buffer
,
970 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]);
972 if (mask
& RADV_PREFETCH_TES
)
973 radv_emit_shader_prefetch(cmd_buffer
,
974 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]);
976 if (mask
& RADV_PREFETCH_GS
) {
977 radv_emit_shader_prefetch(cmd_buffer
,
978 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]);
979 if (radv_pipeline_has_gs_copy_shader(pipeline
))
980 radv_emit_shader_prefetch(cmd_buffer
, pipeline
->gs_copy_shader
);
983 if (mask
& RADV_PREFETCH_PS
)
984 radv_emit_shader_prefetch(cmd_buffer
,
985 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
987 state
->prefetch_L2_mask
&= ~mask
;
991 radv_emit_rbplus_state(struct radv_cmd_buffer
*cmd_buffer
)
993 if (!cmd_buffer
->device
->physical_device
->rad_info
.rbplus_allowed
)
996 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
997 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
999 unsigned sx_ps_downconvert
= 0;
1000 unsigned sx_blend_opt_epsilon
= 0;
1001 unsigned sx_blend_opt_control
= 0;
1003 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1004 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
1005 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
1006 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
1010 int idx
= subpass
->color_attachments
[i
].attachment
;
1011 struct radv_color_buffer_info
*cb
= &cmd_buffer
->state
.attachments
[idx
].cb
;
1013 unsigned format
= G_028C70_FORMAT(cb
->cb_color_info
);
1014 unsigned swap
= G_028C70_COMP_SWAP(cb
->cb_color_info
);
1015 uint32_t spi_format
= (pipeline
->graphics
.col_format
>> (i
* 4)) & 0xf;
1016 uint32_t colormask
= (pipeline
->graphics
.cb_target_mask
>> (i
* 4)) & 0xf;
1018 bool has_alpha
, has_rgb
;
1020 /* Set if RGB and A are present. */
1021 has_alpha
= !G_028C74_FORCE_DST_ALPHA_1(cb
->cb_color_attrib
);
1023 if (format
== V_028C70_COLOR_8
||
1024 format
== V_028C70_COLOR_16
||
1025 format
== V_028C70_COLOR_32
)
1026 has_rgb
= !has_alpha
;
1030 /* Check the colormask and export format. */
1031 if (!(colormask
& 0x7))
1033 if (!(colormask
& 0x8))
1036 if (spi_format
== V_028714_SPI_SHADER_ZERO
) {
1041 /* Disable value checking for disabled channels. */
1043 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
1045 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
1047 /* Enable down-conversion for 32bpp and smaller formats. */
1049 case V_028C70_COLOR_8
:
1050 case V_028C70_COLOR_8_8
:
1051 case V_028C70_COLOR_8_8_8_8
:
1052 /* For 1 and 2-channel formats, use the superset thereof. */
1053 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
||
1054 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
1055 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
1056 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_8_8_8_8
<< (i
* 4);
1057 sx_blend_opt_epsilon
|= V_028758_8BIT_FORMAT
<< (i
* 4);
1061 case V_028C70_COLOR_5_6_5
:
1062 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1063 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_5_6_5
<< (i
* 4);
1064 sx_blend_opt_epsilon
|= V_028758_6BIT_FORMAT
<< (i
* 4);
1068 case V_028C70_COLOR_1_5_5_5
:
1069 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1070 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_1_5_5_5
<< (i
* 4);
1071 sx_blend_opt_epsilon
|= V_028758_5BIT_FORMAT
<< (i
* 4);
1075 case V_028C70_COLOR_4_4_4_4
:
1076 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1077 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_4_4_4_4
<< (i
* 4);
1078 sx_blend_opt_epsilon
|= V_028758_4BIT_FORMAT
<< (i
* 4);
1082 case V_028C70_COLOR_32
:
1083 if (swap
== V_028C70_SWAP_STD
&&
1084 spi_format
== V_028714_SPI_SHADER_32_R
)
1085 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
1086 else if (swap
== V_028C70_SWAP_ALT_REV
&&
1087 spi_format
== V_028714_SPI_SHADER_32_AR
)
1088 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_A
<< (i
* 4);
1091 case V_028C70_COLOR_16
:
1092 case V_028C70_COLOR_16_16
:
1093 /* For 1-channel formats, use the superset thereof. */
1094 if (spi_format
== V_028714_SPI_SHADER_UNORM16_ABGR
||
1095 spi_format
== V_028714_SPI_SHADER_SNORM16_ABGR
||
1096 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
1097 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
1098 if (swap
== V_028C70_SWAP_STD
||
1099 swap
== V_028C70_SWAP_STD_REV
)
1100 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_GR
<< (i
* 4);
1102 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_AR
<< (i
* 4);
1106 case V_028C70_COLOR_10_11_11
:
1107 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1108 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_10_11_11
<< (i
* 4);
1109 sx_blend_opt_epsilon
|= V_028758_11BIT_FORMAT
<< (i
* 4);
1113 case V_028C70_COLOR_2_10_10_10
:
1114 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1115 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_2_10_10_10
<< (i
* 4);
1116 sx_blend_opt_epsilon
|= V_028758_10BIT_FORMAT
<< (i
* 4);
1122 for (unsigned i
= subpass
->color_count
; i
< 8; ++i
) {
1123 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
1124 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
1126 /* TODO: avoid redundantly setting context registers */
1127 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
1128 radeon_emit(cmd_buffer
->cs
, sx_ps_downconvert
);
1129 radeon_emit(cmd_buffer
->cs
, sx_blend_opt_epsilon
);
1130 radeon_emit(cmd_buffer
->cs
, sx_blend_opt_control
);
1132 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1136 radv_emit_graphics_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
1138 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1140 if (!pipeline
|| cmd_buffer
->state
.emitted_pipeline
== pipeline
)
1143 radv_update_multisample_state(cmd_buffer
, pipeline
);
1144 radv_update_binning_state(cmd_buffer
, pipeline
);
1146 cmd_buffer
->scratch_size_needed
=
1147 MAX2(cmd_buffer
->scratch_size_needed
,
1148 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
1150 if (!cmd_buffer
->state
.emitted_pipeline
||
1151 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
!=
1152 pipeline
->graphics
.can_use_guardband
)
1153 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
1155 radeon_emit_array(cmd_buffer
->cs
, pipeline
->cs
.buf
, pipeline
->cs
.cdw
);
1157 if (!cmd_buffer
->state
.emitted_pipeline
||
1158 cmd_buffer
->state
.emitted_pipeline
->ctx_cs
.cdw
!= pipeline
->ctx_cs
.cdw
||
1159 cmd_buffer
->state
.emitted_pipeline
->ctx_cs_hash
!= pipeline
->ctx_cs_hash
||
1160 memcmp(cmd_buffer
->state
.emitted_pipeline
->ctx_cs
.buf
,
1161 pipeline
->ctx_cs
.buf
, pipeline
->ctx_cs
.cdw
* 4)) {
1162 radeon_emit_array(cmd_buffer
->cs
, pipeline
->ctx_cs
.buf
, pipeline
->ctx_cs
.cdw
);
1163 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1166 for (unsigned i
= 0; i
< MESA_SHADER_COMPUTE
; i
++) {
1167 if (!pipeline
->shaders
[i
])
1170 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
1171 pipeline
->shaders
[i
]->bo
);
1174 if (radv_pipeline_has_gs_copy_shader(pipeline
))
1175 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
1176 pipeline
->gs_copy_shader
->bo
);
1178 if (unlikely(cmd_buffer
->device
->trace_bo
))
1179 radv_save_pipeline(cmd_buffer
, pipeline
, RING_GFX
);
1181 cmd_buffer
->state
.emitted_pipeline
= pipeline
;
1183 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_PIPELINE
;
1187 radv_emit_viewport(struct radv_cmd_buffer
*cmd_buffer
)
1189 si_write_viewport(cmd_buffer
->cs
, 0, cmd_buffer
->state
.dynamic
.viewport
.count
,
1190 cmd_buffer
->state
.dynamic
.viewport
.viewports
);
1194 radv_emit_scissor(struct radv_cmd_buffer
*cmd_buffer
)
1196 uint32_t count
= cmd_buffer
->state
.dynamic
.scissor
.count
;
1198 si_write_scissors(cmd_buffer
->cs
, 0, count
,
1199 cmd_buffer
->state
.dynamic
.scissor
.scissors
,
1200 cmd_buffer
->state
.dynamic
.viewport
.viewports
,
1201 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
);
1203 cmd_buffer
->state
.context_roll_without_scissor_emitted
= false;
1207 radv_emit_discard_rectangle(struct radv_cmd_buffer
*cmd_buffer
)
1209 if (!cmd_buffer
->state
.dynamic
.discard_rectangle
.count
)
1212 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028210_PA_SC_CLIPRECT_0_TL
,
1213 cmd_buffer
->state
.dynamic
.discard_rectangle
.count
* 2);
1214 for (unsigned i
= 0; i
< cmd_buffer
->state
.dynamic
.discard_rectangle
.count
; ++i
) {
1215 VkRect2D rect
= cmd_buffer
->state
.dynamic
.discard_rectangle
.rectangles
[i
];
1216 radeon_emit(cmd_buffer
->cs
, S_028210_TL_X(rect
.offset
.x
) | S_028210_TL_Y(rect
.offset
.y
));
1217 radeon_emit(cmd_buffer
->cs
, S_028214_BR_X(rect
.offset
.x
+ rect
.extent
.width
) |
1218 S_028214_BR_Y(rect
.offset
.y
+ rect
.extent
.height
));
1223 radv_emit_line_width(struct radv_cmd_buffer
*cmd_buffer
)
1225 unsigned width
= cmd_buffer
->state
.dynamic
.line_width
* 8;
1227 radeon_set_context_reg(cmd_buffer
->cs
, R_028A08_PA_SU_LINE_CNTL
,
1228 S_028A08_WIDTH(CLAMP(width
, 0, 0xFFF)));
1232 radv_emit_blend_constants(struct radv_cmd_buffer
*cmd_buffer
)
1234 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1236 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028414_CB_BLEND_RED
, 4);
1237 radeon_emit_array(cmd_buffer
->cs
, (uint32_t *)d
->blend_constants
, 4);
1241 radv_emit_stencil(struct radv_cmd_buffer
*cmd_buffer
)
1243 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1245 radeon_set_context_reg_seq(cmd_buffer
->cs
,
1246 R_028430_DB_STENCILREFMASK
, 2);
1247 radeon_emit(cmd_buffer
->cs
,
1248 S_028430_STENCILTESTVAL(d
->stencil_reference
.front
) |
1249 S_028430_STENCILMASK(d
->stencil_compare_mask
.front
) |
1250 S_028430_STENCILWRITEMASK(d
->stencil_write_mask
.front
) |
1251 S_028430_STENCILOPVAL(1));
1252 radeon_emit(cmd_buffer
->cs
,
1253 S_028434_STENCILTESTVAL_BF(d
->stencil_reference
.back
) |
1254 S_028434_STENCILMASK_BF(d
->stencil_compare_mask
.back
) |
1255 S_028434_STENCILWRITEMASK_BF(d
->stencil_write_mask
.back
) |
1256 S_028434_STENCILOPVAL_BF(1));
1260 radv_emit_depth_bounds(struct radv_cmd_buffer
*cmd_buffer
)
1262 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1264 radeon_set_context_reg(cmd_buffer
->cs
, R_028020_DB_DEPTH_BOUNDS_MIN
,
1265 fui(d
->depth_bounds
.min
));
1266 radeon_set_context_reg(cmd_buffer
->cs
, R_028024_DB_DEPTH_BOUNDS_MAX
,
1267 fui(d
->depth_bounds
.max
));
1271 radv_emit_depth_bias(struct radv_cmd_buffer
*cmd_buffer
)
1273 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1274 unsigned slope
= fui(d
->depth_bias
.slope
* 16.0f
);
1275 unsigned bias
= fui(d
->depth_bias
.bias
* cmd_buffer
->state
.offset_scale
);
1278 radeon_set_context_reg_seq(cmd_buffer
->cs
,
1279 R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, 5);
1280 radeon_emit(cmd_buffer
->cs
, fui(d
->depth_bias
.clamp
)); /* CLAMP */
1281 radeon_emit(cmd_buffer
->cs
, slope
); /* FRONT SCALE */
1282 radeon_emit(cmd_buffer
->cs
, bias
); /* FRONT OFFSET */
1283 radeon_emit(cmd_buffer
->cs
, slope
); /* BACK SCALE */
1284 radeon_emit(cmd_buffer
->cs
, bias
); /* BACK OFFSET */
1288 radv_emit_fb_color_state(struct radv_cmd_buffer
*cmd_buffer
,
1290 struct radv_color_buffer_info
*cb
,
1291 struct radv_image_view
*iview
,
1292 VkImageLayout layout
,
1293 bool in_render_loop
)
1295 bool is_vi
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX8
;
1296 uint32_t cb_color_info
= cb
->cb_color_info
;
1297 struct radv_image
*image
= iview
->image
;
1299 if (!radv_layout_dcc_compressed(cmd_buffer
->device
, image
, layout
, in_render_loop
,
1300 radv_image_queue_family_mask(image
,
1301 cmd_buffer
->queue_family_index
,
1302 cmd_buffer
->queue_family_index
))) {
1303 cb_color_info
&= C_028C70_DCC_ENABLE
;
1306 if (radv_image_is_tc_compat_cmask(image
) &&
1307 (radv_is_fmask_decompress_pipeline(cmd_buffer
) ||
1308 radv_is_dcc_decompress_pipeline(cmd_buffer
))) {
1309 /* If this bit is set, the FMASK decompression operation
1310 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1312 cb_color_info
&= C_028C70_FMASK_COMPRESS_1FRAG_ONLY
;
1315 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
1316 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1317 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1318 radeon_emit(cmd_buffer
->cs
, 0);
1319 radeon_emit(cmd_buffer
->cs
, 0);
1320 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1321 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1322 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1323 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1324 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1325 radeon_emit(cmd_buffer
->cs
, 0);
1326 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1327 radeon_emit(cmd_buffer
->cs
, 0);
1329 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, 1);
1330 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
);
1332 radeon_set_context_reg(cmd_buffer
->cs
, R_028E40_CB_COLOR0_BASE_EXT
+ index
* 4,
1333 cb
->cb_color_base
>> 32);
1334 radeon_set_context_reg(cmd_buffer
->cs
, R_028E60_CB_COLOR0_CMASK_BASE_EXT
+ index
* 4,
1335 cb
->cb_color_cmask
>> 32);
1336 radeon_set_context_reg(cmd_buffer
->cs
, R_028E80_CB_COLOR0_FMASK_BASE_EXT
+ index
* 4,
1337 cb
->cb_color_fmask
>> 32);
1338 radeon_set_context_reg(cmd_buffer
->cs
, R_028EA0_CB_COLOR0_DCC_BASE_EXT
+ index
* 4,
1339 cb
->cb_dcc_base
>> 32);
1340 radeon_set_context_reg(cmd_buffer
->cs
, R_028EC0_CB_COLOR0_ATTRIB2
+ index
* 4,
1341 cb
->cb_color_attrib2
);
1342 radeon_set_context_reg(cmd_buffer
->cs
, R_028EE0_CB_COLOR0_ATTRIB3
+ index
* 4,
1343 cb
->cb_color_attrib3
);
1344 } else if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
1345 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1346 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1347 radeon_emit(cmd_buffer
->cs
, S_028C64_BASE_256B(cb
->cb_color_base
>> 32));
1348 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib2
);
1349 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1350 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1351 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1352 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1353 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1354 radeon_emit(cmd_buffer
->cs
, S_028C80_BASE_256B(cb
->cb_color_cmask
>> 32));
1355 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1356 radeon_emit(cmd_buffer
->cs
, S_028C88_BASE_256B(cb
->cb_color_fmask
>> 32));
1358 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, 2);
1359 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
);
1360 radeon_emit(cmd_buffer
->cs
, S_028C98_BASE_256B(cb
->cb_dcc_base
>> 32));
1362 radeon_set_context_reg(cmd_buffer
->cs
, R_0287A0_CB_MRT0_EPITCH
+ index
* 4,
1365 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1366 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1367 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_pitch
);
1368 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_slice
);
1369 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1370 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1371 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1372 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1373 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1374 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask_slice
);
1375 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1376 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask_slice
);
1378 if (is_vi
) { /* DCC BASE */
1379 radeon_set_context_reg(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, cb
->cb_dcc_base
);
1383 if (radv_dcc_enabled(image
, iview
->base_mip
)) {
1384 /* Drawing with DCC enabled also compresses colorbuffers. */
1385 VkImageSubresourceRange range
= {
1386 .aspectMask
= iview
->aspect_mask
,
1387 .baseMipLevel
= iview
->base_mip
,
1388 .levelCount
= iview
->level_count
,
1389 .baseArrayLayer
= iview
->base_layer
,
1390 .layerCount
= iview
->layer_count
,
1393 radv_update_dcc_metadata(cmd_buffer
, image
, &range
, true);
1398 radv_update_zrange_precision(struct radv_cmd_buffer
*cmd_buffer
,
1399 struct radv_ds_buffer_info
*ds
,
1400 const struct radv_image_view
*iview
,
1401 VkImageLayout layout
,
1402 bool in_render_loop
, bool requires_cond_exec
)
1404 const struct radv_image
*image
= iview
->image
;
1405 uint32_t db_z_info
= ds
->db_z_info
;
1406 uint32_t db_z_info_reg
;
1408 if (!cmd_buffer
->device
->physical_device
->rad_info
.has_tc_compat_zrange_bug
||
1409 !radv_image_is_tc_compat_htile(image
))
1412 if (!radv_layout_has_htile(image
, layout
, in_render_loop
,
1413 radv_image_queue_family_mask(image
,
1414 cmd_buffer
->queue_family_index
,
1415 cmd_buffer
->queue_family_index
))) {
1416 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
1419 db_z_info
&= C_028040_ZRANGE_PRECISION
;
1421 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
1422 db_z_info_reg
= R_028038_DB_Z_INFO
;
1424 db_z_info_reg
= R_028040_DB_Z_INFO
;
1427 /* When we don't know the last fast clear value we need to emit a
1428 * conditional packet that will eventually skip the following
1429 * SET_CONTEXT_REG packet.
1431 if (requires_cond_exec
) {
1432 uint64_t va
= radv_get_tc_compat_zrange_va(image
, iview
->base_mip
);
1434 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_COND_EXEC
, 3, 0));
1435 radeon_emit(cmd_buffer
->cs
, va
);
1436 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1437 radeon_emit(cmd_buffer
->cs
, 0);
1438 radeon_emit(cmd_buffer
->cs
, 3); /* SET_CONTEXT_REG size */
1441 radeon_set_context_reg(cmd_buffer
->cs
, db_z_info_reg
, db_z_info
);
1445 radv_emit_fb_ds_state(struct radv_cmd_buffer
*cmd_buffer
,
1446 struct radv_ds_buffer_info
*ds
,
1447 struct radv_image_view
*iview
,
1448 VkImageLayout layout
,
1449 bool in_render_loop
)
1451 const struct radv_image
*image
= iview
->image
;
1452 uint32_t db_z_info
= ds
->db_z_info
;
1453 uint32_t db_stencil_info
= ds
->db_stencil_info
;
1455 if (!radv_layout_has_htile(image
, layout
, in_render_loop
,
1456 radv_image_queue_family_mask(image
,
1457 cmd_buffer
->queue_family_index
,
1458 cmd_buffer
->queue_family_index
))) {
1459 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
1460 db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
1463 radeon_set_context_reg(cmd_buffer
->cs
, R_028008_DB_DEPTH_VIEW
, ds
->db_depth_view
);
1464 radeon_set_context_reg(cmd_buffer
->cs
, R_028ABC_DB_HTILE_SURFACE
, ds
->db_htile_surface
);
1466 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
1467 radeon_set_context_reg(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, ds
->db_htile_data_base
);
1468 radeon_set_context_reg(cmd_buffer
->cs
, R_02801C_DB_DEPTH_SIZE_XY
, ds
->db_depth_size
);
1470 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_02803C_DB_DEPTH_INFO
, 7);
1471 radeon_emit(cmd_buffer
->cs
, S_02803C_RESOURCE_LEVEL(1));
1472 radeon_emit(cmd_buffer
->cs
, db_z_info
);
1473 radeon_emit(cmd_buffer
->cs
, db_stencil_info
);
1474 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
);
1475 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
);
1476 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
);
1477 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
);
1479 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028068_DB_Z_READ_BASE_HI
, 5);
1480 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
>> 32);
1481 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
>> 32);
1482 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
>> 32);
1483 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
>> 32);
1484 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
>> 32);
1485 } else if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
1486 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
1487 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
);
1488 radeon_emit(cmd_buffer
->cs
, S_028018_BASE_HI(ds
->db_htile_data_base
>> 32));
1489 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
);
1491 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 10);
1492 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* DB_Z_INFO */
1493 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* DB_STENCIL_INFO */
1494 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* DB_Z_READ_BASE */
1495 radeon_emit(cmd_buffer
->cs
, S_028044_BASE_HI(ds
->db_z_read_base
>> 32)); /* DB_Z_READ_BASE_HI */
1496 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* DB_STENCIL_READ_BASE */
1497 radeon_emit(cmd_buffer
->cs
, S_02804C_BASE_HI(ds
->db_stencil_read_base
>> 32)); /* DB_STENCIL_READ_BASE_HI */
1498 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* DB_Z_WRITE_BASE */
1499 radeon_emit(cmd_buffer
->cs
, S_028054_BASE_HI(ds
->db_z_write_base
>> 32)); /* DB_Z_WRITE_BASE_HI */
1500 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* DB_STENCIL_WRITE_BASE */
1501 radeon_emit(cmd_buffer
->cs
, S_02805C_BASE_HI(ds
->db_stencil_write_base
>> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1503 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028068_DB_Z_INFO2
, 2);
1504 radeon_emit(cmd_buffer
->cs
, ds
->db_z_info2
);
1505 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_info2
);
1507 radeon_set_context_reg(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, ds
->db_htile_data_base
);
1509 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_02803C_DB_DEPTH_INFO
, 9);
1510 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_info
); /* R_02803C_DB_DEPTH_INFO */
1511 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* R_028040_DB_Z_INFO */
1512 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* R_028044_DB_STENCIL_INFO */
1513 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* R_028048_DB_Z_READ_BASE */
1514 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* R_02804C_DB_STENCIL_READ_BASE */
1515 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* R_028050_DB_Z_WRITE_BASE */
1516 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* R_028054_DB_STENCIL_WRITE_BASE */
1517 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
); /* R_028058_DB_DEPTH_SIZE */
1518 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_slice
); /* R_02805C_DB_DEPTH_SLICE */
1522 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1523 radv_update_zrange_precision(cmd_buffer
, ds
, iview
, layout
,
1524 in_render_loop
, true);
1526 radeon_set_context_reg(cmd_buffer
->cs
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1527 ds
->pa_su_poly_offset_db_fmt_cntl
);
1531 * Update the fast clear depth/stencil values if the image is bound as a
1532 * depth/stencil buffer.
1535 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer
*cmd_buffer
,
1536 const struct radv_image_view
*iview
,
1537 VkClearDepthStencilValue ds_clear_value
,
1538 VkImageAspectFlags aspects
)
1540 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1541 const struct radv_image
*image
= iview
->image
;
1542 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1545 if (!cmd_buffer
->state
.attachments
|| !subpass
)
1548 if (!subpass
->depth_stencil_attachment
)
1551 att_idx
= subpass
->depth_stencil_attachment
->attachment
;
1552 if (cmd_buffer
->state
.attachments
[att_idx
].iview
->image
!= image
)
1555 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 2);
1556 radeon_emit(cs
, ds_clear_value
.stencil
);
1557 radeon_emit(cs
, fui(ds_clear_value
.depth
));
1559 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1560 * only needed when clearing Z to 0.0.
1562 if ((aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
1563 ds_clear_value
.depth
== 0.0) {
1564 VkImageLayout layout
= subpass
->depth_stencil_attachment
->layout
;
1565 bool in_render_loop
= subpass
->depth_stencil_attachment
->in_render_loop
;
1567 radv_update_zrange_precision(cmd_buffer
, &cmd_buffer
->state
.attachments
[att_idx
].ds
,
1568 iview
, layout
, in_render_loop
, false);
1571 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1575 * Set the clear depth/stencil values to the image's metadata.
1578 radv_set_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1579 struct radv_image
*image
,
1580 const VkImageSubresourceRange
*range
,
1581 VkClearDepthStencilValue ds_clear_value
,
1582 VkImageAspectFlags aspects
)
1584 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1585 uint64_t va
= radv_get_ds_clear_value_va(image
, range
->baseMipLevel
);
1586 uint32_t level_count
= radv_get_levelCount(image
, range
);
1588 if (aspects
== (VK_IMAGE_ASPECT_DEPTH_BIT
|
1589 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
1590 /* Use the fastest way when both aspects are used. */
1591 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + 2 * level_count
, cmd_buffer
->state
.predicating
));
1592 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
1593 S_370_WR_CONFIRM(1) |
1594 S_370_ENGINE_SEL(V_370_PFP
));
1595 radeon_emit(cs
, va
);
1596 radeon_emit(cs
, va
>> 32);
1598 for (uint32_t l
= 0; l
< level_count
; l
++) {
1599 radeon_emit(cs
, ds_clear_value
.stencil
);
1600 radeon_emit(cs
, fui(ds_clear_value
.depth
));
1603 /* Otherwise we need one WRITE_DATA packet per level. */
1604 for (uint32_t l
= 0; l
< level_count
; l
++) {
1605 uint64_t va
= radv_get_ds_clear_value_va(image
, range
->baseMipLevel
+ l
);
1608 if (aspects
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
1609 value
= fui(ds_clear_value
.depth
);
1612 assert(aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
1613 value
= ds_clear_value
.stencil
;
1616 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, cmd_buffer
->state
.predicating
));
1617 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
1618 S_370_WR_CONFIRM(1) |
1619 S_370_ENGINE_SEL(V_370_PFP
));
1620 radeon_emit(cs
, va
);
1621 radeon_emit(cs
, va
>> 32);
1622 radeon_emit(cs
, value
);
1628 * Update the TC-compat metadata value for this image.
1631 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1632 struct radv_image
*image
,
1633 const VkImageSubresourceRange
*range
,
1636 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1638 if (!cmd_buffer
->device
->physical_device
->rad_info
.has_tc_compat_zrange_bug
)
1641 uint64_t va
= radv_get_tc_compat_zrange_va(image
, range
->baseMipLevel
);
1642 uint32_t level_count
= radv_get_levelCount(image
, range
);
1644 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + level_count
, cmd_buffer
->state
.predicating
));
1645 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
1646 S_370_WR_CONFIRM(1) |
1647 S_370_ENGINE_SEL(V_370_PFP
));
1648 radeon_emit(cs
, va
);
1649 radeon_emit(cs
, va
>> 32);
1651 for (uint32_t l
= 0; l
< level_count
; l
++)
1652 radeon_emit(cs
, value
);
1656 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1657 const struct radv_image_view
*iview
,
1658 VkClearDepthStencilValue ds_clear_value
)
1660 VkImageSubresourceRange range
= {
1661 .aspectMask
= iview
->aspect_mask
,
1662 .baseMipLevel
= iview
->base_mip
,
1663 .levelCount
= iview
->level_count
,
1664 .baseArrayLayer
= iview
->base_layer
,
1665 .layerCount
= iview
->layer_count
,
1669 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1670 * depth clear value is 0.0f.
1672 cond_val
= ds_clear_value
.depth
== 0.0f
? UINT_MAX
: 0;
1674 radv_set_tc_compat_zrange_metadata(cmd_buffer
, iview
->image
, &range
,
1679 * Update the clear depth/stencil values for this image.
1682 radv_update_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1683 const struct radv_image_view
*iview
,
1684 VkClearDepthStencilValue ds_clear_value
,
1685 VkImageAspectFlags aspects
)
1687 VkImageSubresourceRange range
= {
1688 .aspectMask
= iview
->aspect_mask
,
1689 .baseMipLevel
= iview
->base_mip
,
1690 .levelCount
= iview
->level_count
,
1691 .baseArrayLayer
= iview
->base_layer
,
1692 .layerCount
= iview
->layer_count
,
1694 struct radv_image
*image
= iview
->image
;
1696 assert(radv_image_has_htile(image
));
1698 radv_set_ds_clear_metadata(cmd_buffer
, iview
->image
, &range
,
1699 ds_clear_value
, aspects
);
1701 if (radv_image_is_tc_compat_htile(image
) &&
1702 (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
1703 radv_update_tc_compat_zrange_metadata(cmd_buffer
, iview
,
1707 radv_update_bound_fast_clear_ds(cmd_buffer
, iview
, ds_clear_value
,
1712 * Load the clear depth/stencil values from the image's metadata.
1715 radv_load_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1716 const struct radv_image_view
*iview
)
1718 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1719 const struct radv_image
*image
= iview
->image
;
1720 VkImageAspectFlags aspects
= vk_format_aspects(image
->vk_format
);
1721 uint64_t va
= radv_get_ds_clear_value_va(image
, iview
->base_mip
);
1722 unsigned reg_offset
= 0, reg_count
= 0;
1724 if (!radv_image_has_htile(image
))
1727 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1733 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1736 uint32_t reg
= R_028028_DB_STENCIL_CLEAR
+ 4 * reg_offset
;
1738 if (cmd_buffer
->device
->physical_device
->rad_info
.has_load_ctx_reg_pkt
) {
1739 radeon_emit(cs
, PKT3(PKT3_LOAD_CONTEXT_REG
, 3, 0));
1740 radeon_emit(cs
, va
);
1741 radeon_emit(cs
, va
>> 32);
1742 radeon_emit(cs
, (reg
- SI_CONTEXT_REG_OFFSET
) >> 2);
1743 radeon_emit(cs
, reg_count
);
1745 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
1746 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
1747 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1748 (reg_count
== 2 ? COPY_DATA_COUNT_SEL
: 0));
1749 radeon_emit(cs
, va
);
1750 radeon_emit(cs
, va
>> 32);
1751 radeon_emit(cs
, reg
>> 2);
1754 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
1760 * With DCC some colors don't require CMASK elimination before being
1761 * used as a texture. This sets a predicate value to determine if the
1762 * cmask eliminate is required.
1765 radv_update_fce_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1766 struct radv_image
*image
,
1767 const VkImageSubresourceRange
*range
, bool value
)
1769 uint64_t pred_val
= value
;
1770 uint64_t va
= radv_image_get_fce_pred_va(image
, range
->baseMipLevel
);
1771 uint32_t level_count
= radv_get_levelCount(image
, range
);
1772 uint32_t count
= 2 * level_count
;
1774 assert(radv_dcc_enabled(image
, range
->baseMipLevel
));
1776 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, 0));
1777 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM
) |
1778 S_370_WR_CONFIRM(1) |
1779 S_370_ENGINE_SEL(V_370_PFP
));
1780 radeon_emit(cmd_buffer
->cs
, va
);
1781 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1783 for (uint32_t l
= 0; l
< level_count
; l
++) {
1784 radeon_emit(cmd_buffer
->cs
, pred_val
);
1785 radeon_emit(cmd_buffer
->cs
, pred_val
>> 32);
1790 * Update the DCC predicate to reflect the compression state.
1793 radv_update_dcc_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1794 struct radv_image
*image
,
1795 const VkImageSubresourceRange
*range
, bool value
)
1797 uint64_t pred_val
= value
;
1798 uint64_t va
= radv_image_get_dcc_pred_va(image
, range
->baseMipLevel
);
1799 uint32_t level_count
= radv_get_levelCount(image
, range
);
1800 uint32_t count
= 2 * level_count
;
1802 assert(radv_dcc_enabled(image
, range
->baseMipLevel
));
1804 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, 0));
1805 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM
) |
1806 S_370_WR_CONFIRM(1) |
1807 S_370_ENGINE_SEL(V_370_PFP
));
1808 radeon_emit(cmd_buffer
->cs
, va
);
1809 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1811 for (uint32_t l
= 0; l
< level_count
; l
++) {
1812 radeon_emit(cmd_buffer
->cs
, pred_val
);
1813 radeon_emit(cmd_buffer
->cs
, pred_val
>> 32);
1818 * Update the fast clear color values if the image is bound as a color buffer.
1821 radv_update_bound_fast_clear_color(struct radv_cmd_buffer
*cmd_buffer
,
1822 struct radv_image
*image
,
1824 uint32_t color_values
[2])
1826 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1827 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1830 if (!cmd_buffer
->state
.attachments
|| !subpass
)
1833 att_idx
= subpass
->color_attachments
[cb_idx
].attachment
;
1834 if (att_idx
== VK_ATTACHMENT_UNUSED
)
1837 if (cmd_buffer
->state
.attachments
[att_idx
].iview
->image
!= image
)
1840 radeon_set_context_reg_seq(cs
, R_028C8C_CB_COLOR0_CLEAR_WORD0
+ cb_idx
* 0x3c, 2);
1841 radeon_emit(cs
, color_values
[0]);
1842 radeon_emit(cs
, color_values
[1]);
1844 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1848 * Set the clear color values to the image's metadata.
1851 radv_set_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1852 struct radv_image
*image
,
1853 const VkImageSubresourceRange
*range
,
1854 uint32_t color_values
[2])
1856 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1857 uint64_t va
= radv_image_get_fast_clear_va(image
, range
->baseMipLevel
);
1858 uint32_t level_count
= radv_get_levelCount(image
, range
);
1859 uint32_t count
= 2 * level_count
;
1861 assert(radv_image_has_cmask(image
) ||
1862 radv_dcc_enabled(image
, range
->baseMipLevel
));
1864 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, cmd_buffer
->state
.predicating
));
1865 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
1866 S_370_WR_CONFIRM(1) |
1867 S_370_ENGINE_SEL(V_370_PFP
));
1868 radeon_emit(cs
, va
);
1869 radeon_emit(cs
, va
>> 32);
1871 for (uint32_t l
= 0; l
< level_count
; l
++) {
1872 radeon_emit(cs
, color_values
[0]);
1873 radeon_emit(cs
, color_values
[1]);
1878 * Update the clear color values for this image.
1881 radv_update_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1882 const struct radv_image_view
*iview
,
1884 uint32_t color_values
[2])
1886 struct radv_image
*image
= iview
->image
;
1887 VkImageSubresourceRange range
= {
1888 .aspectMask
= iview
->aspect_mask
,
1889 .baseMipLevel
= iview
->base_mip
,
1890 .levelCount
= iview
->level_count
,
1891 .baseArrayLayer
= iview
->base_layer
,
1892 .layerCount
= iview
->layer_count
,
1895 assert(radv_image_has_cmask(image
) ||
1896 radv_dcc_enabled(image
, iview
->base_mip
));
1898 radv_set_color_clear_metadata(cmd_buffer
, image
, &range
, color_values
);
1900 radv_update_bound_fast_clear_color(cmd_buffer
, image
, cb_idx
,
1905 * Load the clear color values from the image's metadata.
1908 radv_load_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1909 struct radv_image_view
*iview
,
1912 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1913 struct radv_image
*image
= iview
->image
;
1914 uint64_t va
= radv_image_get_fast_clear_va(image
, iview
->base_mip
);
1916 if (!radv_image_has_cmask(image
) &&
1917 !radv_dcc_enabled(image
, iview
->base_mip
))
1920 uint32_t reg
= R_028C8C_CB_COLOR0_CLEAR_WORD0
+ cb_idx
* 0x3c;
1922 if (cmd_buffer
->device
->physical_device
->rad_info
.has_load_ctx_reg_pkt
) {
1923 radeon_emit(cs
, PKT3(PKT3_LOAD_CONTEXT_REG
, 3, cmd_buffer
->state
.predicating
));
1924 radeon_emit(cs
, va
);
1925 radeon_emit(cs
, va
>> 32);
1926 radeon_emit(cs
, (reg
- SI_CONTEXT_REG_OFFSET
) >> 2);
1929 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, cmd_buffer
->state
.predicating
));
1930 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
1931 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1932 COPY_DATA_COUNT_SEL
);
1933 radeon_emit(cs
, va
);
1934 radeon_emit(cs
, va
>> 32);
1935 radeon_emit(cs
, reg
>> 2);
1938 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, cmd_buffer
->state
.predicating
));
1944 radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer
)
1947 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1948 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1950 /* this may happen for inherited secondary recording */
1954 for (i
= 0; i
< 8; ++i
) {
1955 if (i
>= subpass
->color_count
|| subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
1956 radeon_set_context_reg(cmd_buffer
->cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
1957 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
1961 int idx
= subpass
->color_attachments
[i
].attachment
;
1962 struct radv_image_view
*iview
= cmd_buffer
->state
.attachments
[idx
].iview
;
1963 VkImageLayout layout
= subpass
->color_attachments
[i
].layout
;
1964 bool in_render_loop
= subpass
->color_attachments
[i
].in_render_loop
;
1966 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, iview
->bo
);
1968 assert(iview
->aspect_mask
& (VK_IMAGE_ASPECT_COLOR_BIT
| VK_IMAGE_ASPECT_PLANE_0_BIT
|
1969 VK_IMAGE_ASPECT_PLANE_1_BIT
| VK_IMAGE_ASPECT_PLANE_2_BIT
));
1970 radv_emit_fb_color_state(cmd_buffer
, i
, &cmd_buffer
->state
.attachments
[idx
].cb
, iview
, layout
, in_render_loop
);
1972 radv_load_color_clear_metadata(cmd_buffer
, iview
, i
);
1975 if (subpass
->depth_stencil_attachment
) {
1976 int idx
= subpass
->depth_stencil_attachment
->attachment
;
1977 VkImageLayout layout
= subpass
->depth_stencil_attachment
->layout
;
1978 bool in_render_loop
= subpass
->depth_stencil_attachment
->in_render_loop
;
1979 struct radv_image_view
*iview
= cmd_buffer
->state
.attachments
[idx
].iview
;
1980 struct radv_image
*image
= iview
->image
;
1981 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, cmd_buffer
->state
.attachments
[idx
].iview
->bo
);
1982 ASSERTED
uint32_t queue_mask
= radv_image_queue_family_mask(image
,
1983 cmd_buffer
->queue_family_index
,
1984 cmd_buffer
->queue_family_index
);
1985 /* We currently don't support writing decompressed HTILE */
1986 assert(radv_layout_has_htile(image
, layout
, in_render_loop
, queue_mask
) ==
1987 radv_layout_is_htile_compressed(image
, layout
, in_render_loop
, queue_mask
));
1989 radv_emit_fb_ds_state(cmd_buffer
, &cmd_buffer
->state
.attachments
[idx
].ds
, iview
, layout
, in_render_loop
);
1991 if (cmd_buffer
->state
.attachments
[idx
].ds
.offset_scale
!= cmd_buffer
->state
.offset_scale
) {
1992 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
1993 cmd_buffer
->state
.offset_scale
= cmd_buffer
->state
.attachments
[idx
].ds
.offset_scale
;
1995 radv_load_ds_clear_metadata(cmd_buffer
, iview
);
1997 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
)
1998 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 2);
2000 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028040_DB_Z_INFO
, 2);
2002 radeon_emit(cmd_buffer
->cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
2003 radeon_emit(cmd_buffer
->cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
2005 radeon_set_context_reg(cmd_buffer
->cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
2006 S_028208_BR_X(framebuffer
->width
) |
2007 S_028208_BR_Y(framebuffer
->height
));
2009 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX8
) {
2010 bool disable_constant_encode
=
2011 cmd_buffer
->device
->physical_device
->rad_info
.has_dcc_constant_encode
;
2012 enum chip_class chip_class
=
2013 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
;
2014 uint8_t watermark
= chip_class
>= GFX10
? 6 : 4;
2016 radeon_set_context_reg(cmd_buffer
->cs
, R_028424_CB_DCC_CONTROL
,
2017 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class
<= GFX9
) |
2018 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark
) |
2019 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode
));
2022 if (cmd_buffer
->device
->dfsm_allowed
) {
2023 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2024 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
2027 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_FRAMEBUFFER
;
2031 radv_emit_index_buffer(struct radv_cmd_buffer
*cmd_buffer
)
2033 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
2034 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2036 if (state
->index_type
!= state
->last_index_type
) {
2037 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2038 radeon_set_uconfig_reg_idx(cmd_buffer
->device
->physical_device
,
2039 cs
, R_03090C_VGT_INDEX_TYPE
,
2040 2, state
->index_type
);
2042 radeon_emit(cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
2043 radeon_emit(cs
, state
->index_type
);
2046 state
->last_index_type
= state
->index_type
;
2049 radeon_emit(cs
, PKT3(PKT3_INDEX_BASE
, 1, 0));
2050 radeon_emit(cs
, state
->index_va
);
2051 radeon_emit(cs
, state
->index_va
>> 32);
2053 radeon_emit(cs
, PKT3(PKT3_INDEX_BUFFER_SIZE
, 0, 0));
2054 radeon_emit(cs
, state
->max_index_count
);
2056 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_INDEX_BUFFER
;
2059 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
)
2061 bool has_perfect_queries
= cmd_buffer
->state
.perfect_occlusion_queries_enabled
;
2062 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
2063 uint32_t pa_sc_mode_cntl_1
=
2064 pipeline
? pipeline
->graphics
.ms
.pa_sc_mode_cntl_1
: 0;
2065 uint32_t db_count_control
;
2067 if(!cmd_buffer
->state
.active_occlusion_queries
) {
2068 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2069 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1
) &&
2070 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
&&
2071 has_perfect_queries
) {
2072 /* Re-enable out-of-order rasterization if the
2073 * bound pipeline supports it and if it's has
2074 * been disabled before starting any perfect
2075 * occlusion queries.
2077 radeon_set_context_reg(cmd_buffer
->cs
,
2078 R_028A4C_PA_SC_MODE_CNTL_1
,
2082 db_count_control
= S_028004_ZPASS_INCREMENT_DISABLE(1);
2084 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
2085 uint32_t sample_rate
= subpass
? util_logbase2(subpass
->max_sample_count
) : 0;
2086 bool gfx10_perfect
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&& has_perfect_queries
;
2088 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2090 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries
) |
2091 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect
) |
2092 S_028004_SAMPLE_RATE(sample_rate
) |
2093 S_028004_ZPASS_ENABLE(1) |
2094 S_028004_SLICE_EVEN_ENABLE(1) |
2095 S_028004_SLICE_ODD_ENABLE(1);
2097 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1
) &&
2098 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
&&
2099 has_perfect_queries
) {
2100 /* If the bound pipeline has enabled
2101 * out-of-order rasterization, we should
2102 * disable it before starting any perfect
2103 * occlusion queries.
2105 pa_sc_mode_cntl_1
&= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE
;
2107 radeon_set_context_reg(cmd_buffer
->cs
,
2108 R_028A4C_PA_SC_MODE_CNTL_1
,
2112 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(1) |
2113 S_028004_SAMPLE_RATE(sample_rate
);
2117 radeon_set_context_reg(cmd_buffer
->cs
, R_028004_DB_COUNT_CONTROL
, db_count_control
);
2119 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
2123 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
)
2125 uint32_t states
= cmd_buffer
->state
.dirty
& cmd_buffer
->state
.emitted_pipeline
->graphics
.needed_dynamic_state
;
2127 if (states
& (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
))
2128 radv_emit_viewport(cmd_buffer
);
2130 if (states
& (RADV_CMD_DIRTY_DYNAMIC_SCISSOR
| RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
) &&
2131 !cmd_buffer
->device
->physical_device
->rad_info
.has_gfx9_scissor_bug
)
2132 radv_emit_scissor(cmd_buffer
);
2134 if (states
& RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
)
2135 radv_emit_line_width(cmd_buffer
);
2137 if (states
& RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
)
2138 radv_emit_blend_constants(cmd_buffer
);
2140 if (states
& (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
|
2141 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
|
2142 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
))
2143 radv_emit_stencil(cmd_buffer
);
2145 if (states
& RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
)
2146 radv_emit_depth_bounds(cmd_buffer
);
2148 if (states
& RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
)
2149 radv_emit_depth_bias(cmd_buffer
);
2151 if (states
& RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
)
2152 radv_emit_discard_rectangle(cmd_buffer
);
2154 if (states
& RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS
)
2155 radv_emit_sample_locations(cmd_buffer
);
2157 cmd_buffer
->state
.dirty
&= ~states
;
2161 radv_flush_push_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
2162 VkPipelineBindPoint bind_point
)
2164 struct radv_descriptor_state
*descriptors_state
=
2165 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2166 struct radv_descriptor_set
*set
= &descriptors_state
->push_set
.set
;
2169 if (!radv_cmd_buffer_upload_data(cmd_buffer
, set
->size
, 32,
2174 set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2175 set
->va
+= bo_offset
;
2179 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer
*cmd_buffer
,
2180 VkPipelineBindPoint bind_point
)
2182 struct radv_descriptor_state
*descriptors_state
=
2183 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2184 uint32_t size
= MAX_SETS
* 4;
2188 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
,
2189 256, &offset
, &ptr
))
2192 for (unsigned i
= 0; i
< MAX_SETS
; i
++) {
2193 uint32_t *uptr
= ((uint32_t *)ptr
) + i
;
2194 uint64_t set_va
= 0;
2195 struct radv_descriptor_set
*set
= descriptors_state
->sets
[i
];
2196 if (descriptors_state
->valid
& (1u << i
))
2198 uptr
[0] = set_va
& 0xffffffff;
2201 uint64_t va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2204 if (cmd_buffer
->state
.pipeline
) {
2205 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_VERTEX
])
2206 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
2207 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2209 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_FRAGMENT
])
2210 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_FRAGMENT
,
2211 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2213 if (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
))
2214 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
2215 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2217 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
2218 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_CTRL
,
2219 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2221 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
2222 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_EVAL
,
2223 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2226 if (cmd_buffer
->state
.compute_pipeline
)
2227 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
, MESA_SHADER_COMPUTE
,
2228 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2232 radv_flush_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
2233 VkShaderStageFlags stages
)
2235 VkPipelineBindPoint bind_point
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
?
2236 VK_PIPELINE_BIND_POINT_COMPUTE
:
2237 VK_PIPELINE_BIND_POINT_GRAPHICS
;
2238 struct radv_descriptor_state
*descriptors_state
=
2239 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2240 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2241 bool flush_indirect_descriptors
;
2243 if (!descriptors_state
->dirty
)
2246 if (descriptors_state
->push_dirty
)
2247 radv_flush_push_descriptors(cmd_buffer
, bind_point
);
2249 flush_indirect_descriptors
=
2250 (bind_point
== VK_PIPELINE_BIND_POINT_GRAPHICS
&&
2251 state
->pipeline
&& state
->pipeline
->need_indirect_descriptor_sets
) ||
2252 (bind_point
== VK_PIPELINE_BIND_POINT_COMPUTE
&&
2253 state
->compute_pipeline
&& state
->compute_pipeline
->need_indirect_descriptor_sets
);
2255 if (flush_indirect_descriptors
)
2256 radv_flush_indirect_descriptor_sets(cmd_buffer
, bind_point
);
2258 ASSERTED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
2260 MAX_SETS
* MESA_SHADER_STAGES
* 4);
2262 if (cmd_buffer
->state
.pipeline
) {
2263 radv_foreach_stage(stage
, stages
) {
2264 if (!cmd_buffer
->state
.pipeline
->shaders
[stage
])
2267 radv_emit_descriptor_pointers(cmd_buffer
,
2268 cmd_buffer
->state
.pipeline
,
2269 descriptors_state
, stage
);
2273 if (cmd_buffer
->state
.compute_pipeline
&&
2274 (stages
& VK_SHADER_STAGE_COMPUTE_BIT
)) {
2275 radv_emit_descriptor_pointers(cmd_buffer
,
2276 cmd_buffer
->state
.compute_pipeline
,
2278 MESA_SHADER_COMPUTE
);
2281 descriptors_state
->dirty
= 0;
2282 descriptors_state
->push_dirty
= false;
2284 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2286 if (unlikely(cmd_buffer
->device
->trace_bo
))
2287 radv_save_descriptors(cmd_buffer
, bind_point
);
2291 radv_flush_constants(struct radv_cmd_buffer
*cmd_buffer
,
2292 VkShaderStageFlags stages
)
2294 struct radv_pipeline
*pipeline
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
2295 ? cmd_buffer
->state
.compute_pipeline
2296 : cmd_buffer
->state
.pipeline
;
2297 VkPipelineBindPoint bind_point
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
?
2298 VK_PIPELINE_BIND_POINT_COMPUTE
:
2299 VK_PIPELINE_BIND_POINT_GRAPHICS
;
2300 struct radv_descriptor_state
*descriptors_state
=
2301 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2302 struct radv_pipeline_layout
*layout
= pipeline
->layout
;
2303 struct radv_shader_variant
*shader
, *prev_shader
;
2304 bool need_push_constants
= false;
2309 stages
&= cmd_buffer
->push_constant_stages
;
2311 (!layout
->push_constant_size
&& !layout
->dynamic_offset_count
))
2314 radv_foreach_stage(stage
, stages
) {
2315 if (!pipeline
->shaders
[stage
])
2318 need_push_constants
|= pipeline
->shaders
[stage
]->info
.loads_push_constants
;
2319 need_push_constants
|= pipeline
->shaders
[stage
]->info
.loads_dynamic_offsets
;
2321 uint8_t base
= pipeline
->shaders
[stage
]->info
.base_inline_push_consts
;
2322 uint8_t count
= pipeline
->shaders
[stage
]->info
.num_inline_push_consts
;
2324 radv_emit_inline_push_consts(cmd_buffer
, pipeline
, stage
,
2325 AC_UD_INLINE_PUSH_CONSTANTS
,
2327 (uint32_t *)&cmd_buffer
->push_constants
[base
* 4]);
2330 if (need_push_constants
) {
2331 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, layout
->push_constant_size
+
2332 16 * layout
->dynamic_offset_count
,
2333 256, &offset
, &ptr
))
2336 memcpy(ptr
, cmd_buffer
->push_constants
, layout
->push_constant_size
);
2337 memcpy((char*)ptr
+ layout
->push_constant_size
,
2338 descriptors_state
->dynamic_buffers
,
2339 16 * layout
->dynamic_offset_count
);
2341 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2344 ASSERTED
unsigned cdw_max
=
2345 radeon_check_space(cmd_buffer
->device
->ws
,
2346 cmd_buffer
->cs
, MESA_SHADER_STAGES
* 4);
2349 radv_foreach_stage(stage
, stages
) {
2350 shader
= radv_get_shader(pipeline
, stage
);
2352 /* Avoid redundantly emitting the address for merged stages. */
2353 if (shader
&& shader
!= prev_shader
) {
2354 radv_emit_userdata_address(cmd_buffer
, pipeline
, stage
,
2355 AC_UD_PUSH_CONSTANTS
, va
);
2357 prev_shader
= shader
;
2360 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2363 cmd_buffer
->push_constant_stages
&= ~stages
;
2367 radv_flush_vertex_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
2368 bool pipeline_is_dirty
)
2370 if ((pipeline_is_dirty
||
2371 (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_VERTEX_BUFFER
)) &&
2372 cmd_buffer
->state
.pipeline
->num_vertex_bindings
&&
2373 radv_get_shader(cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
)->info
.vs
.has_vertex_buffers
) {
2374 struct radv_vertex_elements_info
*velems
= &cmd_buffer
->state
.pipeline
->vertex_elements
;
2378 uint32_t count
= cmd_buffer
->state
.pipeline
->num_vertex_bindings
;
2381 /* allocate some descriptor state for vertex buffers */
2382 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, count
* 16, 256,
2383 &vb_offset
, &vb_ptr
))
2386 for (i
= 0; i
< count
; i
++) {
2387 uint32_t *desc
= &((uint32_t *)vb_ptr
)[i
* 4];
2389 struct radv_buffer
*buffer
= cmd_buffer
->vertex_bindings
[i
].buffer
;
2390 uint32_t stride
= cmd_buffer
->state
.pipeline
->binding_stride
[i
];
2395 va
= radv_buffer_get_va(buffer
->bo
);
2397 offset
= cmd_buffer
->vertex_bindings
[i
].offset
;
2398 va
+= offset
+ buffer
->offset
;
2400 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) | S_008F04_STRIDE(stride
);
2401 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
<= GFX7
&& stride
)
2402 desc
[2] = (buffer
->size
- offset
- velems
->format_size
[i
]) / stride
+ 1;
2404 desc
[2] = buffer
->size
- offset
;
2405 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2406 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2407 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2408 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
2410 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2411 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT
) |
2412 S_008F0C_OOB_SELECT(1) |
2413 S_008F0C_RESOURCE_LEVEL(1);
2415 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT
) |
2416 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2420 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2423 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
2424 AC_UD_VS_VERTEX_BUFFERS
, va
);
2426 cmd_buffer
->state
.vb_va
= va
;
2427 cmd_buffer
->state
.vb_size
= count
* 16;
2428 cmd_buffer
->state
.prefetch_L2_mask
|= RADV_PREFETCH_VBO_DESCRIPTORS
;
2430 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_VERTEX_BUFFER
;
2434 radv_emit_streamout_buffers(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
)
2436 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
2437 struct radv_userdata_info
*loc
;
2440 for (unsigned stage
= 0; stage
< MESA_SHADER_STAGES
; ++stage
) {
2441 if (!radv_get_shader(pipeline
, stage
))
2444 loc
= radv_lookup_user_sgpr(pipeline
, stage
,
2445 AC_UD_STREAMOUT_BUFFERS
);
2446 if (loc
->sgpr_idx
== -1)
2449 base_reg
= pipeline
->user_data_0
[stage
];
2451 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
2452 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
2455 if (radv_pipeline_has_gs_copy_shader(pipeline
)) {
2456 loc
= &pipeline
->gs_copy_shader
->info
.user_sgprs_locs
.shader_data
[AC_UD_STREAMOUT_BUFFERS
];
2457 if (loc
->sgpr_idx
!= -1) {
2458 base_reg
= R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2460 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
2461 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
2467 radv_flush_streamout_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
2469 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_STREAMOUT_BUFFER
) {
2470 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
2471 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
2476 /* Allocate some descriptor state for streamout buffers. */
2477 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
,
2478 MAX_SO_BUFFERS
* 16, 256,
2479 &so_offset
, &so_ptr
))
2482 for (uint32_t i
= 0; i
< MAX_SO_BUFFERS
; i
++) {
2483 struct radv_buffer
*buffer
= sb
[i
].buffer
;
2484 uint32_t *desc
= &((uint32_t *)so_ptr
)[i
* 4];
2486 if (!(so
->enabled_mask
& (1 << i
)))
2489 va
= radv_buffer_get_va(buffer
->bo
) + buffer
->offset
;
2493 /* Set the descriptor.
2495 * On GFX8, the format must be non-INVALID, otherwise
2496 * the buffer will be considered not bound and store
2497 * instructions will be no-ops.
2499 uint32_t size
= 0xffffffff;
2501 /* Compute the correct buffer size for NGG streamout
2502 * because it's used to determine the max emit per
2505 if (cmd_buffer
->device
->physical_device
->use_ngg_streamout
)
2506 size
= buffer
->size
- sb
[i
].offset
;
2509 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
2511 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2512 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2513 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2514 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
2516 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2517 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2518 S_008F0C_OOB_SELECT(3) |
2519 S_008F0C_RESOURCE_LEVEL(1);
2521 desc
[3] |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2525 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2528 radv_emit_streamout_buffers(cmd_buffer
, va
);
2531 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER
;
2535 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer
*cmd_buffer
, bool pipeline_is_dirty
)
2537 radv_flush_vertex_descriptors(cmd_buffer
, pipeline_is_dirty
);
2538 radv_flush_streamout_descriptors(cmd_buffer
);
2539 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
2540 radv_flush_constants(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
2543 struct radv_draw_info
{
2545 * Number of vertices.
2550 * Index of the first vertex.
2552 int32_t vertex_offset
;
2555 * First instance id.
2557 uint32_t first_instance
;
2560 * Number of instances.
2562 uint32_t instance_count
;
2565 * First index (indexed draws only).
2567 uint32_t first_index
;
2570 * Whether it's an indexed draw.
2575 * Indirect draw parameters resource.
2577 struct radv_buffer
*indirect
;
2578 uint64_t indirect_offset
;
2582 * Draw count parameters resource.
2584 struct radv_buffer
*count_buffer
;
2585 uint64_t count_buffer_offset
;
2588 * Stream output parameters resource.
2590 struct radv_buffer
*strmout_buffer
;
2591 uint64_t strmout_buffer_offset
;
2595 radv_get_primitive_reset_index(struct radv_cmd_buffer
*cmd_buffer
)
2597 switch (cmd_buffer
->state
.index_type
) {
2598 case V_028A7C_VGT_INDEX_8
:
2600 case V_028A7C_VGT_INDEX_16
:
2602 case V_028A7C_VGT_INDEX_32
:
2605 unreachable("invalid index type");
2610 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
2611 bool instanced_draw
, bool indirect_draw
,
2612 bool count_from_stream_output
,
2613 uint32_t draw_vertex_count
)
2615 struct radeon_info
*info
= &cmd_buffer
->device
->physical_device
->rad_info
;
2616 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2617 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
2618 unsigned ia_multi_vgt_param
;
2620 ia_multi_vgt_param
=
2621 si_get_ia_multi_vgt_param(cmd_buffer
, instanced_draw
,
2623 count_from_stream_output
,
2626 if (state
->last_ia_multi_vgt_param
!= ia_multi_vgt_param
) {
2627 if (info
->chip_class
== GFX9
) {
2628 radeon_set_uconfig_reg_idx(cmd_buffer
->device
->physical_device
,
2630 R_030960_IA_MULTI_VGT_PARAM
,
2631 4, ia_multi_vgt_param
);
2632 } else if (info
->chip_class
>= GFX7
) {
2633 radeon_set_context_reg_idx(cs
,
2634 R_028AA8_IA_MULTI_VGT_PARAM
,
2635 1, ia_multi_vgt_param
);
2637 radeon_set_context_reg(cs
, R_028AA8_IA_MULTI_VGT_PARAM
,
2638 ia_multi_vgt_param
);
2640 state
->last_ia_multi_vgt_param
= ia_multi_vgt_param
;
2645 radv_emit_draw_registers(struct radv_cmd_buffer
*cmd_buffer
,
2646 const struct radv_draw_info
*draw_info
)
2648 struct radeon_info
*info
= &cmd_buffer
->device
->physical_device
->rad_info
;
2649 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2650 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
2651 int32_t primitive_reset_en
;
2654 if (info
->chip_class
< GFX10
) {
2655 si_emit_ia_multi_vgt_param(cmd_buffer
, draw_info
->instance_count
> 1,
2656 draw_info
->indirect
,
2657 !!draw_info
->strmout_buffer
,
2658 draw_info
->indirect
? 0 : draw_info
->count
);
2661 /* Primitive restart. */
2662 primitive_reset_en
=
2663 draw_info
->indexed
&& state
->pipeline
->graphics
.prim_restart_enable
;
2665 if (primitive_reset_en
!= state
->last_primitive_reset_en
) {
2666 state
->last_primitive_reset_en
= primitive_reset_en
;
2667 if (info
->chip_class
>= GFX9
) {
2668 radeon_set_uconfig_reg(cs
,
2669 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN
,
2670 primitive_reset_en
);
2672 radeon_set_context_reg(cs
,
2673 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
,
2674 primitive_reset_en
);
2678 if (primitive_reset_en
) {
2679 uint32_t primitive_reset_index
=
2680 radv_get_primitive_reset_index(cmd_buffer
);
2682 if (primitive_reset_index
!= state
->last_primitive_reset_index
) {
2683 radeon_set_context_reg(cs
,
2684 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
,
2685 primitive_reset_index
);
2686 state
->last_primitive_reset_index
= primitive_reset_index
;
2690 if (draw_info
->strmout_buffer
) {
2691 uint64_t va
= radv_buffer_get_va(draw_info
->strmout_buffer
->bo
);
2693 va
+= draw_info
->strmout_buffer
->offset
+
2694 draw_info
->strmout_buffer_offset
;
2696 radeon_set_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
,
2699 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
2700 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
2701 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
2702 COPY_DATA_WR_CONFIRM
);
2703 radeon_emit(cs
, va
);
2704 radeon_emit(cs
, va
>> 32);
2705 radeon_emit(cs
, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2);
2706 radeon_emit(cs
, 0); /* unused */
2708 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, draw_info
->strmout_buffer
->bo
);
2712 static void radv_stage_flush(struct radv_cmd_buffer
*cmd_buffer
,
2713 VkPipelineStageFlags src_stage_mask
)
2715 if (src_stage_mask
& (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT
|
2716 VK_PIPELINE_STAGE_TRANSFER_BIT
|
2717 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
2718 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
2719 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
;
2722 if (src_stage_mask
& (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT
|
2723 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT
|
2724 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT
|
2725 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
|
2726 VK_PIPELINE_STAGE_TRANSFER_BIT
|
2727 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
2728 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT
|
2729 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
2730 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
;
2731 } else if (src_stage_mask
& (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
2732 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
|
2733 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT
|
2734 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT
|
2735 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT
|
2736 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT
|
2737 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT
)) {
2738 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VS_PARTIAL_FLUSH
;
2742 static enum radv_cmd_flush_bits
2743 radv_src_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
2744 VkAccessFlags src_flags
,
2745 struct radv_image
*image
)
2747 bool flush_CB_meta
= true, flush_DB_meta
= true;
2748 enum radv_cmd_flush_bits flush_bits
= 0;
2752 if (!radv_image_has_CB_metadata(image
))
2753 flush_CB_meta
= false;
2754 if (!radv_image_has_htile(image
))
2755 flush_DB_meta
= false;
2758 for_each_bit(b
, src_flags
) {
2759 switch ((VkAccessFlagBits
)(1 << b
)) {
2760 case VK_ACCESS_SHADER_WRITE_BIT
:
2761 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT
:
2762 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT
:
2763 flush_bits
|= RADV_CMD_FLAG_WB_L2
;
2765 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
2766 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
;
2768 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2770 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
2771 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
;
2773 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2775 case VK_ACCESS_TRANSFER_WRITE_BIT
:
2776 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
2777 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
2778 RADV_CMD_FLAG_INV_L2
;
2781 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2783 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2792 static enum radv_cmd_flush_bits
2793 radv_dst_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
2794 VkAccessFlags dst_flags
,
2795 struct radv_image
*image
)
2797 bool flush_CB_meta
= true, flush_DB_meta
= true;
2798 enum radv_cmd_flush_bits flush_bits
= 0;
2799 bool flush_CB
= true, flush_DB
= true;
2800 bool image_is_coherent
= false;
2804 if (!(image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
)) {
2809 if (!radv_image_has_CB_metadata(image
))
2810 flush_CB_meta
= false;
2811 if (!radv_image_has_htile(image
))
2812 flush_DB_meta
= false;
2814 /* TODO: implement shader coherent for GFX10 */
2816 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
2817 if (image
->info
.samples
== 1 &&
2818 (image
->usage
& (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
|
2819 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
)) &&
2820 !vk_format_is_stencil(image
->vk_format
)) {
2821 /* Single-sample color and single-sample depth
2822 * (not stencil) are coherent with shaders on
2825 image_is_coherent
= true;
2830 for_each_bit(b
, dst_flags
) {
2831 switch ((VkAccessFlagBits
)(1 << b
)) {
2832 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
2833 case VK_ACCESS_INDEX_READ_BIT
:
2834 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT
:
2836 case VK_ACCESS_UNIFORM_READ_BIT
:
2837 flush_bits
|= RADV_CMD_FLAG_INV_VCACHE
| RADV_CMD_FLAG_INV_SCACHE
;
2839 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
2840 case VK_ACCESS_TRANSFER_READ_BIT
:
2841 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
2842 flush_bits
|= RADV_CMD_FLAG_INV_VCACHE
|
2843 RADV_CMD_FLAG_INV_L2
;
2845 case VK_ACCESS_SHADER_READ_BIT
:
2846 flush_bits
|= RADV_CMD_FLAG_INV_VCACHE
;
2847 /* Unlike LLVM, ACO uses SMEM for SSBOs and we have to
2848 * invalidate the scalar cache. */
2849 if (cmd_buffer
->device
->physical_device
->use_aco
)
2850 flush_bits
|= RADV_CMD_FLAG_INV_SCACHE
;
2852 if (!image_is_coherent
)
2853 flush_bits
|= RADV_CMD_FLAG_INV_L2
;
2855 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
:
2857 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
;
2859 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2861 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT
:
2863 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
;
2865 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2874 void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
,
2875 const struct radv_subpass_barrier
*barrier
)
2877 cmd_buffer
->state
.flush_bits
|= radv_src_access_flush(cmd_buffer
, barrier
->src_access_mask
,
2879 radv_stage_flush(cmd_buffer
, barrier
->src_stage_mask
);
2880 cmd_buffer
->state
.flush_bits
|= radv_dst_access_flush(cmd_buffer
, barrier
->dst_access_mask
,
2885 radv_get_subpass_id(struct radv_cmd_buffer
*cmd_buffer
)
2887 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2888 uint32_t subpass_id
= state
->subpass
- state
->pass
->subpasses
;
2890 /* The id of this subpass shouldn't exceed the number of subpasses in
2891 * this render pass minus 1.
2893 assert(subpass_id
< state
->pass
->subpass_count
);
2897 static struct radv_sample_locations_state
*
2898 radv_get_attachment_sample_locations(struct radv_cmd_buffer
*cmd_buffer
,
2902 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2903 uint32_t subpass_id
= radv_get_subpass_id(cmd_buffer
);
2904 struct radv_image_view
*view
= state
->attachments
[att_idx
].iview
;
2906 if (view
->image
->info
.samples
== 1)
2909 if (state
->pass
->attachments
[att_idx
].first_subpass_idx
== subpass_id
) {
2910 /* Return the initial sample locations if this is the initial
2911 * layout transition of the given subpass attachemnt.
2913 if (state
->attachments
[att_idx
].sample_location
.count
> 0)
2914 return &state
->attachments
[att_idx
].sample_location
;
2916 /* Otherwise return the subpass sample locations if defined. */
2917 if (state
->subpass_sample_locs
) {
2918 /* Because the driver sets the current subpass before
2919 * initial layout transitions, we should use the sample
2920 * locations from the previous subpass to avoid an
2921 * off-by-one problem. Otherwise, use the sample
2922 * locations for the current subpass for final layout
2928 for (uint32_t i
= 0; i
< state
->num_subpass_sample_locs
; i
++) {
2929 if (state
->subpass_sample_locs
[i
].subpass_idx
== subpass_id
)
2930 return &state
->subpass_sample_locs
[i
].sample_location
;
2938 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
2939 struct radv_subpass_attachment att
,
2942 unsigned idx
= att
.attachment
;
2943 struct radv_image_view
*view
= cmd_buffer
->state
.attachments
[idx
].iview
;
2944 struct radv_sample_locations_state
*sample_locs
;
2945 VkImageSubresourceRange range
;
2946 range
.aspectMask
= 0;
2947 range
.baseMipLevel
= view
->base_mip
;
2948 range
.levelCount
= 1;
2949 range
.baseArrayLayer
= view
->base_layer
;
2950 range
.layerCount
= cmd_buffer
->state
.framebuffer
->layers
;
2952 if (cmd_buffer
->state
.subpass
->view_mask
) {
2953 /* If the current subpass uses multiview, the driver might have
2954 * performed a fast color/depth clear to the whole image
2955 * (including all layers). To make sure the driver will
2956 * decompress the image correctly (if needed), we have to
2957 * account for the "real" number of layers. If the view mask is
2958 * sparse, this will decompress more layers than needed.
2960 range
.layerCount
= util_last_bit(cmd_buffer
->state
.subpass
->view_mask
);
2963 /* Get the subpass sample locations for the given attachment, if NULL
2964 * is returned the driver will use the default HW locations.
2966 sample_locs
= radv_get_attachment_sample_locations(cmd_buffer
, idx
,
2969 radv_handle_image_transition(cmd_buffer
,
2971 cmd_buffer
->state
.attachments
[idx
].current_layout
,
2972 cmd_buffer
->state
.attachments
[idx
].current_in_render_loop
,
2973 att
.layout
, att
.in_render_loop
,
2974 0, 0, &range
, sample_locs
);
2976 cmd_buffer
->state
.attachments
[idx
].current_layout
= att
.layout
;
2977 cmd_buffer
->state
.attachments
[idx
].current_in_render_loop
= att
.in_render_loop
;
2983 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
2984 const struct radv_subpass
*subpass
)
2986 cmd_buffer
->state
.subpass
= subpass
;
2988 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_FRAMEBUFFER
;
2992 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer
*cmd_buffer
,
2993 struct radv_render_pass
*pass
,
2994 const VkRenderPassBeginInfo
*info
)
2996 const struct VkRenderPassSampleLocationsBeginInfoEXT
*sample_locs
=
2997 vk_find_struct_const(info
->pNext
,
2998 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT
);
2999 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3002 state
->subpass_sample_locs
= NULL
;
3006 for (uint32_t i
= 0; i
< sample_locs
->attachmentInitialSampleLocationsCount
; i
++) {
3007 const VkAttachmentSampleLocationsEXT
*att_sample_locs
=
3008 &sample_locs
->pAttachmentInitialSampleLocations
[i
];
3009 uint32_t att_idx
= att_sample_locs
->attachmentIndex
;
3010 struct radv_image
*image
= cmd_buffer
->state
.attachments
[att_idx
].iview
->image
;
3012 assert(vk_format_is_depth_or_stencil(image
->vk_format
));
3014 /* From the Vulkan spec 1.1.108:
3016 * "If the image referenced by the framebuffer attachment at
3017 * index attachmentIndex was not created with
3018 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
3019 * then the values specified in sampleLocationsInfo are
3022 if (!(image
->flags
& VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
))
3025 const VkSampleLocationsInfoEXT
*sample_locs_info
=
3026 &att_sample_locs
->sampleLocationsInfo
;
3028 state
->attachments
[att_idx
].sample_location
.per_pixel
=
3029 sample_locs_info
->sampleLocationsPerPixel
;
3030 state
->attachments
[att_idx
].sample_location
.grid_size
=
3031 sample_locs_info
->sampleLocationGridSize
;
3032 state
->attachments
[att_idx
].sample_location
.count
=
3033 sample_locs_info
->sampleLocationsCount
;
3034 typed_memcpy(&state
->attachments
[att_idx
].sample_location
.locations
[0],
3035 sample_locs_info
->pSampleLocations
,
3036 sample_locs_info
->sampleLocationsCount
);
3039 state
->subpass_sample_locs
= vk_alloc(&cmd_buffer
->pool
->alloc
,
3040 sample_locs
->postSubpassSampleLocationsCount
*
3041 sizeof(state
->subpass_sample_locs
[0]),
3042 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3043 if (state
->subpass_sample_locs
== NULL
) {
3044 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
3045 return cmd_buffer
->record_result
;
3048 state
->num_subpass_sample_locs
= sample_locs
->postSubpassSampleLocationsCount
;
3050 for (uint32_t i
= 0; i
< sample_locs
->postSubpassSampleLocationsCount
; i
++) {
3051 const VkSubpassSampleLocationsEXT
*subpass_sample_locs_info
=
3052 &sample_locs
->pPostSubpassSampleLocations
[i
];
3053 const VkSampleLocationsInfoEXT
*sample_locs_info
=
3054 &subpass_sample_locs_info
->sampleLocationsInfo
;
3056 state
->subpass_sample_locs
[i
].subpass_idx
=
3057 subpass_sample_locs_info
->subpassIndex
;
3058 state
->subpass_sample_locs
[i
].sample_location
.per_pixel
=
3059 sample_locs_info
->sampleLocationsPerPixel
;
3060 state
->subpass_sample_locs
[i
].sample_location
.grid_size
=
3061 sample_locs_info
->sampleLocationGridSize
;
3062 state
->subpass_sample_locs
[i
].sample_location
.count
=
3063 sample_locs_info
->sampleLocationsCount
;
3064 typed_memcpy(&state
->subpass_sample_locs
[i
].sample_location
.locations
[0],
3065 sample_locs_info
->pSampleLocations
,
3066 sample_locs_info
->sampleLocationsCount
);
3073 radv_cmd_state_setup_attachments(struct radv_cmd_buffer
*cmd_buffer
,
3074 struct radv_render_pass
*pass
,
3075 const VkRenderPassBeginInfo
*info
)
3077 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3078 const struct VkRenderPassAttachmentBeginInfoKHR
*attachment_info
= NULL
;
3081 attachment_info
= vk_find_struct_const(info
->pNext
,
3082 RENDER_PASS_ATTACHMENT_BEGIN_INFO_KHR
);
3086 if (pass
->attachment_count
== 0) {
3087 state
->attachments
= NULL
;
3091 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
3092 pass
->attachment_count
*
3093 sizeof(state
->attachments
[0]),
3094 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3095 if (state
->attachments
== NULL
) {
3096 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
3097 return cmd_buffer
->record_result
;
3100 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
3101 struct radv_render_pass_attachment
*att
= &pass
->attachments
[i
];
3102 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
3103 VkImageAspectFlags clear_aspects
= 0;
3105 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
3106 /* color attachment */
3107 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
3108 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
3111 /* depthstencil attachment */
3112 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
3113 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
3114 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
3115 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
3116 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_DONT_CARE
)
3117 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
3119 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
3120 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
3121 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
3125 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
3126 state
->attachments
[i
].cleared_views
= 0;
3127 if (clear_aspects
&& info
) {
3128 assert(info
->clearValueCount
> i
);
3129 state
->attachments
[i
].clear_value
= info
->pClearValues
[i
];
3132 state
->attachments
[i
].current_layout
= att
->initial_layout
;
3133 state
->attachments
[i
].sample_location
.count
= 0;
3135 struct radv_image_view
*iview
;
3136 if (attachment_info
&& attachment_info
->attachmentCount
> i
) {
3137 iview
= radv_image_view_from_handle(attachment_info
->pAttachments
[i
]);
3139 iview
= state
->framebuffer
->attachments
[i
];
3142 state
->attachments
[i
].iview
= iview
;
3143 if (iview
->aspect_mask
& (VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3144 radv_initialise_ds_surface(cmd_buffer
->device
, &state
->attachments
[i
].ds
, iview
);
3146 radv_initialise_color_surface(cmd_buffer
->device
, &state
->attachments
[i
].cb
, iview
);
3153 VkResult
radv_AllocateCommandBuffers(
3155 const VkCommandBufferAllocateInfo
*pAllocateInfo
,
3156 VkCommandBuffer
*pCommandBuffers
)
3158 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3159 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
3161 VkResult result
= VK_SUCCESS
;
3164 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
3166 if (!list_empty(&pool
->free_cmd_buffers
)) {
3167 struct radv_cmd_buffer
*cmd_buffer
= list_first_entry(&pool
->free_cmd_buffers
, struct radv_cmd_buffer
, pool_link
);
3169 list_del(&cmd_buffer
->pool_link
);
3170 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
3172 result
= radv_reset_cmd_buffer(cmd_buffer
);
3173 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
3174 cmd_buffer
->level
= pAllocateInfo
->level
;
3176 pCommandBuffers
[i
] = radv_cmd_buffer_to_handle(cmd_buffer
);
3178 result
= radv_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
3179 &pCommandBuffers
[i
]);
3181 if (result
!= VK_SUCCESS
)
3185 if (result
!= VK_SUCCESS
) {
3186 radv_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
,
3187 i
, pCommandBuffers
);
3189 /* From the Vulkan 1.0.66 spec:
3191 * "vkAllocateCommandBuffers can be used to create multiple
3192 * command buffers. If the creation of any of those command
3193 * buffers fails, the implementation must destroy all
3194 * successfully created command buffer objects from this
3195 * command, set all entries of the pCommandBuffers array to
3196 * NULL and return the error."
3198 memset(pCommandBuffers
, 0,
3199 sizeof(*pCommandBuffers
) * pAllocateInfo
->commandBufferCount
);
3205 void radv_FreeCommandBuffers(
3207 VkCommandPool commandPool
,
3208 uint32_t commandBufferCount
,
3209 const VkCommandBuffer
*pCommandBuffers
)
3211 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
3212 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
3215 if (cmd_buffer
->pool
) {
3216 list_del(&cmd_buffer
->pool_link
);
3217 list_addtail(&cmd_buffer
->pool_link
, &cmd_buffer
->pool
->free_cmd_buffers
);
3219 radv_cmd_buffer_destroy(cmd_buffer
);
3225 VkResult
radv_ResetCommandBuffer(
3226 VkCommandBuffer commandBuffer
,
3227 VkCommandBufferResetFlags flags
)
3229 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3230 return radv_reset_cmd_buffer(cmd_buffer
);
3233 VkResult
radv_BeginCommandBuffer(
3234 VkCommandBuffer commandBuffer
,
3235 const VkCommandBufferBeginInfo
*pBeginInfo
)
3237 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3238 VkResult result
= VK_SUCCESS
;
3240 if (cmd_buffer
->status
!= RADV_CMD_BUFFER_STATUS_INITIAL
) {
3241 /* If the command buffer has already been resetted with
3242 * vkResetCommandBuffer, no need to do it again.
3244 result
= radv_reset_cmd_buffer(cmd_buffer
);
3245 if (result
!= VK_SUCCESS
)
3249 memset(&cmd_buffer
->state
, 0, sizeof(cmd_buffer
->state
));
3250 cmd_buffer
->state
.last_primitive_reset_en
= -1;
3251 cmd_buffer
->state
.last_index_type
= -1;
3252 cmd_buffer
->state
.last_num_instances
= -1;
3253 cmd_buffer
->state
.last_vertex_offset
= -1;
3254 cmd_buffer
->state
.last_first_instance
= -1;
3255 cmd_buffer
->state
.predication_type
= -1;
3256 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
3258 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
&&
3259 (pBeginInfo
->flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
)) {
3260 assert(pBeginInfo
->pInheritanceInfo
);
3261 cmd_buffer
->state
.framebuffer
= radv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
3262 cmd_buffer
->state
.pass
= radv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
3264 struct radv_subpass
*subpass
=
3265 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
3267 if (cmd_buffer
->state
.framebuffer
) {
3268 result
= radv_cmd_state_setup_attachments(cmd_buffer
, cmd_buffer
->state
.pass
, NULL
);
3269 if (result
!= VK_SUCCESS
)
3273 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
);
3276 if (unlikely(cmd_buffer
->device
->trace_bo
)) {
3277 struct radv_device
*device
= cmd_buffer
->device
;
3279 radv_cs_add_buffer(device
->ws
, cmd_buffer
->cs
,
3282 radv_cmd_buffer_trace_emit(cmd_buffer
);
3285 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_RECORDING
;
3290 void radv_CmdBindVertexBuffers(
3291 VkCommandBuffer commandBuffer
,
3292 uint32_t firstBinding
,
3293 uint32_t bindingCount
,
3294 const VkBuffer
* pBuffers
,
3295 const VkDeviceSize
* pOffsets
)
3297 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3298 struct radv_vertex_binding
*vb
= cmd_buffer
->vertex_bindings
;
3299 bool changed
= false;
3301 /* We have to defer setting up vertex buffer since we need the buffer
3302 * stride from the pipeline. */
3304 assert(firstBinding
+ bindingCount
<= MAX_VBS
);
3305 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
3306 uint32_t idx
= firstBinding
+ i
;
3309 (vb
[idx
].buffer
!= radv_buffer_from_handle(pBuffers
[i
]) ||
3310 vb
[idx
].offset
!= pOffsets
[i
])) {
3314 vb
[idx
].buffer
= radv_buffer_from_handle(pBuffers
[i
]);
3315 vb
[idx
].offset
= pOffsets
[i
];
3317 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
3318 vb
[idx
].buffer
->bo
);
3322 /* No state changes. */
3326 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_VERTEX_BUFFER
;
3330 vk_to_index_type(VkIndexType type
)
3333 case VK_INDEX_TYPE_UINT8_EXT
:
3334 return V_028A7C_VGT_INDEX_8
;
3335 case VK_INDEX_TYPE_UINT16
:
3336 return V_028A7C_VGT_INDEX_16
;
3337 case VK_INDEX_TYPE_UINT32
:
3338 return V_028A7C_VGT_INDEX_32
;
3340 unreachable("invalid index type");
3345 radv_get_vgt_index_size(uint32_t type
)
3348 case V_028A7C_VGT_INDEX_8
:
3350 case V_028A7C_VGT_INDEX_16
:
3352 case V_028A7C_VGT_INDEX_32
:
3355 unreachable("invalid index type");
3359 void radv_CmdBindIndexBuffer(
3360 VkCommandBuffer commandBuffer
,
3362 VkDeviceSize offset
,
3363 VkIndexType indexType
)
3365 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3366 RADV_FROM_HANDLE(radv_buffer
, index_buffer
, buffer
);
3368 if (cmd_buffer
->state
.index_buffer
== index_buffer
&&
3369 cmd_buffer
->state
.index_offset
== offset
&&
3370 cmd_buffer
->state
.index_type
== indexType
) {
3371 /* No state changes. */
3375 cmd_buffer
->state
.index_buffer
= index_buffer
;
3376 cmd_buffer
->state
.index_offset
= offset
;
3377 cmd_buffer
->state
.index_type
= vk_to_index_type(indexType
);
3378 cmd_buffer
->state
.index_va
= radv_buffer_get_va(index_buffer
->bo
);
3379 cmd_buffer
->state
.index_va
+= index_buffer
->offset
+ offset
;
3381 int index_size
= radv_get_vgt_index_size(vk_to_index_type(indexType
));
3382 cmd_buffer
->state
.max_index_count
= (index_buffer
->size
- offset
) / index_size
;
3383 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
3384 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, index_buffer
->bo
);
3389 radv_bind_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
3390 VkPipelineBindPoint bind_point
,
3391 struct radv_descriptor_set
*set
, unsigned idx
)
3393 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
3395 radv_set_descriptor_set(cmd_buffer
, bind_point
, set
, idx
);
3398 assert(!(set
->layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
));
3400 if (!cmd_buffer
->device
->use_global_bo_list
) {
3401 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
)
3402 if (set
->descriptors
[j
])
3403 radv_cs_add_buffer(ws
, cmd_buffer
->cs
, set
->descriptors
[j
]);
3407 radv_cs_add_buffer(ws
, cmd_buffer
->cs
, set
->bo
);
3410 void radv_CmdBindDescriptorSets(
3411 VkCommandBuffer commandBuffer
,
3412 VkPipelineBindPoint pipelineBindPoint
,
3413 VkPipelineLayout _layout
,
3415 uint32_t descriptorSetCount
,
3416 const VkDescriptorSet
* pDescriptorSets
,
3417 uint32_t dynamicOffsetCount
,
3418 const uint32_t* pDynamicOffsets
)
3420 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3421 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
3422 unsigned dyn_idx
= 0;
3424 const bool no_dynamic_bounds
= cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_NO_DYNAMIC_BOUNDS
;
3425 struct radv_descriptor_state
*descriptors_state
=
3426 radv_get_descriptors_state(cmd_buffer
, pipelineBindPoint
);
3428 for (unsigned i
= 0; i
< descriptorSetCount
; ++i
) {
3429 unsigned idx
= i
+ firstSet
;
3430 RADV_FROM_HANDLE(radv_descriptor_set
, set
, pDescriptorSets
[i
]);
3432 /* If the set is already bound we only need to update the
3433 * (potentially changed) dynamic offsets. */
3434 if (descriptors_state
->sets
[idx
] != set
||
3435 !(descriptors_state
->valid
& (1u << idx
))) {
3436 radv_bind_descriptor_set(cmd_buffer
, pipelineBindPoint
, set
, idx
);
3439 for(unsigned j
= 0; j
< set
->layout
->dynamic_offset_count
; ++j
, ++dyn_idx
) {
3440 unsigned idx
= j
+ layout
->set
[i
+ firstSet
].dynamic_offset_start
;
3441 uint32_t *dst
= descriptors_state
->dynamic_buffers
+ idx
* 4;
3442 assert(dyn_idx
< dynamicOffsetCount
);
3444 struct radv_descriptor_range
*range
= set
->dynamic_descriptors
+ j
;
3445 uint64_t va
= range
->va
+ pDynamicOffsets
[dyn_idx
];
3447 dst
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
3448 dst
[2] = no_dynamic_bounds
? 0xffffffffu
: range
->size
;
3449 dst
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3450 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3451 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3452 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3454 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3455 dst
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3456 S_008F0C_OOB_SELECT(3) |
3457 S_008F0C_RESOURCE_LEVEL(1);
3459 dst
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3460 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3463 cmd_buffer
->push_constant_stages
|=
3464 set
->layout
->dynamic_shader_stages
;
3469 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
3470 struct radv_descriptor_set
*set
,
3471 struct radv_descriptor_set_layout
*layout
,
3472 VkPipelineBindPoint bind_point
)
3474 struct radv_descriptor_state
*descriptors_state
=
3475 radv_get_descriptors_state(cmd_buffer
, bind_point
);
3476 set
->size
= layout
->size
;
3477 set
->layout
= layout
;
3479 if (descriptors_state
->push_set
.capacity
< set
->size
) {
3480 size_t new_size
= MAX2(set
->size
, 1024);
3481 new_size
= MAX2(new_size
, 2 * descriptors_state
->push_set
.capacity
);
3482 new_size
= MIN2(new_size
, 96 * MAX_PUSH_DESCRIPTORS
);
3484 free(set
->mapped_ptr
);
3485 set
->mapped_ptr
= malloc(new_size
);
3487 if (!set
->mapped_ptr
) {
3488 descriptors_state
->push_set
.capacity
= 0;
3489 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
3493 descriptors_state
->push_set
.capacity
= new_size
;
3499 void radv_meta_push_descriptor_set(
3500 struct radv_cmd_buffer
* cmd_buffer
,
3501 VkPipelineBindPoint pipelineBindPoint
,
3502 VkPipelineLayout _layout
,
3504 uint32_t descriptorWriteCount
,
3505 const VkWriteDescriptorSet
* pDescriptorWrites
)
3507 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
3508 struct radv_descriptor_set
*push_set
= &cmd_buffer
->meta_push_descriptors
;
3512 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
3514 push_set
->size
= layout
->set
[set
].layout
->size
;
3515 push_set
->layout
= layout
->set
[set
].layout
;
3517 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, push_set
->size
, 32,
3519 (void**) &push_set
->mapped_ptr
))
3522 push_set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
3523 push_set
->va
+= bo_offset
;
3525 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
3526 radv_descriptor_set_to_handle(push_set
),
3527 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
3529 radv_set_descriptor_set(cmd_buffer
, pipelineBindPoint
, push_set
, set
);
3532 void radv_CmdPushDescriptorSetKHR(
3533 VkCommandBuffer commandBuffer
,
3534 VkPipelineBindPoint pipelineBindPoint
,
3535 VkPipelineLayout _layout
,
3537 uint32_t descriptorWriteCount
,
3538 const VkWriteDescriptorSet
* pDescriptorWrites
)
3540 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3541 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
3542 struct radv_descriptor_state
*descriptors_state
=
3543 radv_get_descriptors_state(cmd_buffer
, pipelineBindPoint
);
3544 struct radv_descriptor_set
*push_set
= &descriptors_state
->push_set
.set
;
3546 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
3548 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
,
3549 layout
->set
[set
].layout
,
3553 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3554 * because it is invalid, according to Vulkan spec.
3556 for (int i
= 0; i
< descriptorWriteCount
; i
++) {
3557 ASSERTED
const VkWriteDescriptorSet
*writeset
= &pDescriptorWrites
[i
];
3558 assert(writeset
->descriptorType
!= VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
);
3561 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
3562 radv_descriptor_set_to_handle(push_set
),
3563 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
3565 radv_set_descriptor_set(cmd_buffer
, pipelineBindPoint
, push_set
, set
);
3566 descriptors_state
->push_dirty
= true;
3569 void radv_CmdPushDescriptorSetWithTemplateKHR(
3570 VkCommandBuffer commandBuffer
,
3571 VkDescriptorUpdateTemplate descriptorUpdateTemplate
,
3572 VkPipelineLayout _layout
,
3576 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3577 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
3578 RADV_FROM_HANDLE(radv_descriptor_update_template
, templ
, descriptorUpdateTemplate
);
3579 struct radv_descriptor_state
*descriptors_state
=
3580 radv_get_descriptors_state(cmd_buffer
, templ
->bind_point
);
3581 struct radv_descriptor_set
*push_set
= &descriptors_state
->push_set
.set
;
3583 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
3585 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
,
3586 layout
->set
[set
].layout
,
3590 radv_update_descriptor_set_with_template(cmd_buffer
->device
, cmd_buffer
, push_set
,
3591 descriptorUpdateTemplate
, pData
);
3593 radv_set_descriptor_set(cmd_buffer
, templ
->bind_point
, push_set
, set
);
3594 descriptors_state
->push_dirty
= true;
3597 void radv_CmdPushConstants(VkCommandBuffer commandBuffer
,
3598 VkPipelineLayout layout
,
3599 VkShaderStageFlags stageFlags
,
3602 const void* pValues
)
3604 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3605 memcpy(cmd_buffer
->push_constants
+ offset
, pValues
, size
);
3606 cmd_buffer
->push_constant_stages
|= stageFlags
;
3609 VkResult
radv_EndCommandBuffer(
3610 VkCommandBuffer commandBuffer
)
3612 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3614 if (cmd_buffer
->queue_family_index
!= RADV_QUEUE_TRANSFER
) {
3615 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX6
)
3616 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
| RADV_CMD_FLAG_WB_L2
;
3618 /* Make sure to sync all pending active queries at the end of
3621 cmd_buffer
->state
.flush_bits
|= cmd_buffer
->active_query_flush_bits
;
3623 /* Since NGG streamout uses GDS, we need to make GDS idle when
3624 * we leave the IB, otherwise another process might overwrite
3625 * it while our shaders are busy.
3627 if (cmd_buffer
->gds_needed
)
3628 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
;
3630 si_emit_cache_flush(cmd_buffer
);
3633 /* Make sure CP DMA is idle at the end of IBs because the kernel
3634 * doesn't wait for it.
3636 si_cp_dma_wait_for_idle(cmd_buffer
);
3638 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
3639 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.subpass_sample_locs
);
3641 if (!cmd_buffer
->device
->ws
->cs_finalize(cmd_buffer
->cs
))
3642 return vk_error(cmd_buffer
->device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
3644 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_EXECUTABLE
;
3646 return cmd_buffer
->record_result
;
3650 radv_emit_compute_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
3652 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
3654 if (!pipeline
|| pipeline
== cmd_buffer
->state
.emitted_compute_pipeline
)
3657 assert(!pipeline
->ctx_cs
.cdw
);
3659 cmd_buffer
->state
.emitted_compute_pipeline
= pipeline
;
3661 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, pipeline
->cs
.cdw
);
3662 radeon_emit_array(cmd_buffer
->cs
, pipeline
->cs
.buf
, pipeline
->cs
.cdw
);
3664 cmd_buffer
->compute_scratch_size_needed
=
3665 MAX2(cmd_buffer
->compute_scratch_size_needed
,
3666 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
3668 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
3669 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->bo
);
3671 if (unlikely(cmd_buffer
->device
->trace_bo
))
3672 radv_save_pipeline(cmd_buffer
, pipeline
, RING_COMPUTE
);
3675 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer
*cmd_buffer
,
3676 VkPipelineBindPoint bind_point
)
3678 struct radv_descriptor_state
*descriptors_state
=
3679 radv_get_descriptors_state(cmd_buffer
, bind_point
);
3681 descriptors_state
->dirty
|= descriptors_state
->valid
;
3684 void radv_CmdBindPipeline(
3685 VkCommandBuffer commandBuffer
,
3686 VkPipelineBindPoint pipelineBindPoint
,
3687 VkPipeline _pipeline
)
3689 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3690 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
3692 switch (pipelineBindPoint
) {
3693 case VK_PIPELINE_BIND_POINT_COMPUTE
:
3694 if (cmd_buffer
->state
.compute_pipeline
== pipeline
)
3696 radv_mark_descriptor_sets_dirty(cmd_buffer
, pipelineBindPoint
);
3698 cmd_buffer
->state
.compute_pipeline
= pipeline
;
3699 cmd_buffer
->push_constant_stages
|= VK_SHADER_STAGE_COMPUTE_BIT
;
3701 case VK_PIPELINE_BIND_POINT_GRAPHICS
:
3702 if (cmd_buffer
->state
.pipeline
== pipeline
)
3704 radv_mark_descriptor_sets_dirty(cmd_buffer
, pipelineBindPoint
);
3706 cmd_buffer
->state
.pipeline
= pipeline
;
3710 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
;
3711 cmd_buffer
->push_constant_stages
|= pipeline
->active_stages
;
3713 /* the new vertex shader might not have the same user regs */
3714 cmd_buffer
->state
.last_first_instance
= -1;
3715 cmd_buffer
->state
.last_vertex_offset
= -1;
3717 /* Prefetch all pipeline shaders at first draw time. */
3718 cmd_buffer
->state
.prefetch_L2_mask
|= RADV_PREFETCH_SHADERS
;
3720 if ((cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_NAVI10
||
3721 cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_NAVI12
||
3722 cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_NAVI14
) &&
3723 cmd_buffer
->state
.emitted_pipeline
&&
3724 radv_pipeline_has_ngg(cmd_buffer
->state
.emitted_pipeline
) &&
3725 !radv_pipeline_has_ngg(cmd_buffer
->state
.pipeline
)) {
3726 /* Transitioning from NGG to legacy GS requires
3727 * VGT_FLUSH on Navi10-14. VGT_FLUSH is also emitted
3728 * at the beginning of IBs when legacy GS ring pointers
3731 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VGT_FLUSH
;
3734 radv_bind_dynamic_state(cmd_buffer
, &pipeline
->dynamic_state
);
3735 radv_bind_streamout_state(cmd_buffer
, pipeline
);
3737 if (pipeline
->graphics
.esgs_ring_size
> cmd_buffer
->esgs_ring_size_needed
)
3738 cmd_buffer
->esgs_ring_size_needed
= pipeline
->graphics
.esgs_ring_size
;
3739 if (pipeline
->graphics
.gsvs_ring_size
> cmd_buffer
->gsvs_ring_size_needed
)
3740 cmd_buffer
->gsvs_ring_size_needed
= pipeline
->graphics
.gsvs_ring_size
;
3742 if (radv_pipeline_has_tess(pipeline
))
3743 cmd_buffer
->tess_rings_needed
= true;
3746 assert(!"invalid bind point");
3751 void radv_CmdSetViewport(
3752 VkCommandBuffer commandBuffer
,
3753 uint32_t firstViewport
,
3754 uint32_t viewportCount
,
3755 const VkViewport
* pViewports
)
3757 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3758 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3759 ASSERTED
const uint32_t total_count
= firstViewport
+ viewportCount
;
3761 assert(firstViewport
< MAX_VIEWPORTS
);
3762 assert(total_count
>= 1 && total_count
<= MAX_VIEWPORTS
);
3764 if (!memcmp(state
->dynamic
.viewport
.viewports
+ firstViewport
,
3765 pViewports
, viewportCount
* sizeof(*pViewports
))) {
3769 memcpy(state
->dynamic
.viewport
.viewports
+ firstViewport
, pViewports
,
3770 viewportCount
* sizeof(*pViewports
));
3772 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
3775 void radv_CmdSetScissor(
3776 VkCommandBuffer commandBuffer
,
3777 uint32_t firstScissor
,
3778 uint32_t scissorCount
,
3779 const VkRect2D
* pScissors
)
3781 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3782 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3783 ASSERTED
const uint32_t total_count
= firstScissor
+ scissorCount
;
3785 assert(firstScissor
< MAX_SCISSORS
);
3786 assert(total_count
>= 1 && total_count
<= MAX_SCISSORS
);
3788 if (!memcmp(state
->dynamic
.scissor
.scissors
+ firstScissor
, pScissors
,
3789 scissorCount
* sizeof(*pScissors
))) {
3793 memcpy(state
->dynamic
.scissor
.scissors
+ firstScissor
, pScissors
,
3794 scissorCount
* sizeof(*pScissors
));
3796 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
3799 void radv_CmdSetLineWidth(
3800 VkCommandBuffer commandBuffer
,
3803 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3805 if (cmd_buffer
->state
.dynamic
.line_width
== lineWidth
)
3808 cmd_buffer
->state
.dynamic
.line_width
= lineWidth
;
3809 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
3812 void radv_CmdSetDepthBias(
3813 VkCommandBuffer commandBuffer
,
3814 float depthBiasConstantFactor
,
3815 float depthBiasClamp
,
3816 float depthBiasSlopeFactor
)
3818 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3819 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3821 if (state
->dynamic
.depth_bias
.bias
== depthBiasConstantFactor
&&
3822 state
->dynamic
.depth_bias
.clamp
== depthBiasClamp
&&
3823 state
->dynamic
.depth_bias
.slope
== depthBiasSlopeFactor
) {
3827 state
->dynamic
.depth_bias
.bias
= depthBiasConstantFactor
;
3828 state
->dynamic
.depth_bias
.clamp
= depthBiasClamp
;
3829 state
->dynamic
.depth_bias
.slope
= depthBiasSlopeFactor
;
3831 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
3834 void radv_CmdSetBlendConstants(
3835 VkCommandBuffer commandBuffer
,
3836 const float blendConstants
[4])
3838 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3839 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3841 if (!memcmp(state
->dynamic
.blend_constants
, blendConstants
, sizeof(float) * 4))
3844 memcpy(state
->dynamic
.blend_constants
, blendConstants
, sizeof(float) * 4);
3846 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
3849 void radv_CmdSetDepthBounds(
3850 VkCommandBuffer commandBuffer
,
3851 float minDepthBounds
,
3852 float maxDepthBounds
)
3854 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3855 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3857 if (state
->dynamic
.depth_bounds
.min
== minDepthBounds
&&
3858 state
->dynamic
.depth_bounds
.max
== maxDepthBounds
) {
3862 state
->dynamic
.depth_bounds
.min
= minDepthBounds
;
3863 state
->dynamic
.depth_bounds
.max
= maxDepthBounds
;
3865 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
3868 void radv_CmdSetStencilCompareMask(
3869 VkCommandBuffer commandBuffer
,
3870 VkStencilFaceFlags faceMask
,
3871 uint32_t compareMask
)
3873 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3874 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3875 bool front_same
= state
->dynamic
.stencil_compare_mask
.front
== compareMask
;
3876 bool back_same
= state
->dynamic
.stencil_compare_mask
.back
== compareMask
;
3878 if ((!(faceMask
& VK_STENCIL_FACE_FRONT_BIT
) || front_same
) &&
3879 (!(faceMask
& VK_STENCIL_FACE_BACK_BIT
) || back_same
)) {
3883 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
3884 state
->dynamic
.stencil_compare_mask
.front
= compareMask
;
3885 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
3886 state
->dynamic
.stencil_compare_mask
.back
= compareMask
;
3888 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
3891 void radv_CmdSetStencilWriteMask(
3892 VkCommandBuffer commandBuffer
,
3893 VkStencilFaceFlags faceMask
,
3896 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3897 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3898 bool front_same
= state
->dynamic
.stencil_write_mask
.front
== writeMask
;
3899 bool back_same
= state
->dynamic
.stencil_write_mask
.back
== writeMask
;
3901 if ((!(faceMask
& VK_STENCIL_FACE_FRONT_BIT
) || front_same
) &&
3902 (!(faceMask
& VK_STENCIL_FACE_BACK_BIT
) || back_same
)) {
3906 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
3907 state
->dynamic
.stencil_write_mask
.front
= writeMask
;
3908 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
3909 state
->dynamic
.stencil_write_mask
.back
= writeMask
;
3911 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
3914 void radv_CmdSetStencilReference(
3915 VkCommandBuffer commandBuffer
,
3916 VkStencilFaceFlags faceMask
,
3919 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3920 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3921 bool front_same
= state
->dynamic
.stencil_reference
.front
== reference
;
3922 bool back_same
= state
->dynamic
.stencil_reference
.back
== reference
;
3924 if ((!(faceMask
& VK_STENCIL_FACE_FRONT_BIT
) || front_same
) &&
3925 (!(faceMask
& VK_STENCIL_FACE_BACK_BIT
) || back_same
)) {
3929 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
3930 cmd_buffer
->state
.dynamic
.stencil_reference
.front
= reference
;
3931 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
3932 cmd_buffer
->state
.dynamic
.stencil_reference
.back
= reference
;
3934 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
3937 void radv_CmdSetDiscardRectangleEXT(
3938 VkCommandBuffer commandBuffer
,
3939 uint32_t firstDiscardRectangle
,
3940 uint32_t discardRectangleCount
,
3941 const VkRect2D
* pDiscardRectangles
)
3943 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3944 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3945 ASSERTED
const uint32_t total_count
= firstDiscardRectangle
+ discardRectangleCount
;
3947 assert(firstDiscardRectangle
< MAX_DISCARD_RECTANGLES
);
3948 assert(total_count
>= 1 && total_count
<= MAX_DISCARD_RECTANGLES
);
3950 if (!memcmp(state
->dynamic
.discard_rectangle
.rectangles
+ firstDiscardRectangle
,
3951 pDiscardRectangles
, discardRectangleCount
* sizeof(*pDiscardRectangles
))) {
3955 typed_memcpy(&state
->dynamic
.discard_rectangle
.rectangles
[firstDiscardRectangle
],
3956 pDiscardRectangles
, discardRectangleCount
);
3958 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
;
3961 void radv_CmdSetSampleLocationsEXT(
3962 VkCommandBuffer commandBuffer
,
3963 const VkSampleLocationsInfoEXT
* pSampleLocationsInfo
)
3965 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3966 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3968 assert(pSampleLocationsInfo
->sampleLocationsCount
<= MAX_SAMPLE_LOCATIONS
);
3970 state
->dynamic
.sample_location
.per_pixel
= pSampleLocationsInfo
->sampleLocationsPerPixel
;
3971 state
->dynamic
.sample_location
.grid_size
= pSampleLocationsInfo
->sampleLocationGridSize
;
3972 state
->dynamic
.sample_location
.count
= pSampleLocationsInfo
->sampleLocationsCount
;
3973 typed_memcpy(&state
->dynamic
.sample_location
.locations
[0],
3974 pSampleLocationsInfo
->pSampleLocations
,
3975 pSampleLocationsInfo
->sampleLocationsCount
);
3977 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS
;
3980 void radv_CmdExecuteCommands(
3981 VkCommandBuffer commandBuffer
,
3982 uint32_t commandBufferCount
,
3983 const VkCommandBuffer
* pCmdBuffers
)
3985 RADV_FROM_HANDLE(radv_cmd_buffer
, primary
, commandBuffer
);
3987 assert(commandBufferCount
> 0);
3989 /* Emit pending flushes on primary prior to executing secondary */
3990 si_emit_cache_flush(primary
);
3992 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
3993 RADV_FROM_HANDLE(radv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
3995 primary
->scratch_size_needed
= MAX2(primary
->scratch_size_needed
,
3996 secondary
->scratch_size_needed
);
3997 primary
->compute_scratch_size_needed
= MAX2(primary
->compute_scratch_size_needed
,
3998 secondary
->compute_scratch_size_needed
);
4000 if (secondary
->esgs_ring_size_needed
> primary
->esgs_ring_size_needed
)
4001 primary
->esgs_ring_size_needed
= secondary
->esgs_ring_size_needed
;
4002 if (secondary
->gsvs_ring_size_needed
> primary
->gsvs_ring_size_needed
)
4003 primary
->gsvs_ring_size_needed
= secondary
->gsvs_ring_size_needed
;
4004 if (secondary
->tess_rings_needed
)
4005 primary
->tess_rings_needed
= true;
4006 if (secondary
->sample_positions_needed
)
4007 primary
->sample_positions_needed
= true;
4009 if (!secondary
->state
.framebuffer
&&
4010 (primary
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
)) {
4011 /* Emit the framebuffer state from primary if secondary
4012 * has been recorded without a framebuffer, otherwise
4013 * fast color/depth clears can't work.
4015 radv_emit_framebuffer_state(primary
);
4018 primary
->device
->ws
->cs_execute_secondary(primary
->cs
, secondary
->cs
);
4021 /* When the secondary command buffer is compute only we don't
4022 * need to re-emit the current graphics pipeline.
4024 if (secondary
->state
.emitted_pipeline
) {
4025 primary
->state
.emitted_pipeline
=
4026 secondary
->state
.emitted_pipeline
;
4029 /* When the secondary command buffer is graphics only we don't
4030 * need to re-emit the current compute pipeline.
4032 if (secondary
->state
.emitted_compute_pipeline
) {
4033 primary
->state
.emitted_compute_pipeline
=
4034 secondary
->state
.emitted_compute_pipeline
;
4037 /* Only re-emit the draw packets when needed. */
4038 if (secondary
->state
.last_primitive_reset_en
!= -1) {
4039 primary
->state
.last_primitive_reset_en
=
4040 secondary
->state
.last_primitive_reset_en
;
4043 if (secondary
->state
.last_primitive_reset_index
) {
4044 primary
->state
.last_primitive_reset_index
=
4045 secondary
->state
.last_primitive_reset_index
;
4048 if (secondary
->state
.last_ia_multi_vgt_param
) {
4049 primary
->state
.last_ia_multi_vgt_param
=
4050 secondary
->state
.last_ia_multi_vgt_param
;
4053 primary
->state
.last_first_instance
= secondary
->state
.last_first_instance
;
4054 primary
->state
.last_num_instances
= secondary
->state
.last_num_instances
;
4055 primary
->state
.last_vertex_offset
= secondary
->state
.last_vertex_offset
;
4057 if (secondary
->state
.last_index_type
!= -1) {
4058 primary
->state
.last_index_type
=
4059 secondary
->state
.last_index_type
;
4063 /* After executing commands from secondary buffers we have to dirty
4066 primary
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
|
4067 RADV_CMD_DIRTY_INDEX_BUFFER
|
4068 RADV_CMD_DIRTY_DYNAMIC_ALL
;
4069 radv_mark_descriptor_sets_dirty(primary
, VK_PIPELINE_BIND_POINT_GRAPHICS
);
4070 radv_mark_descriptor_sets_dirty(primary
, VK_PIPELINE_BIND_POINT_COMPUTE
);
4073 VkResult
radv_CreateCommandPool(
4075 const VkCommandPoolCreateInfo
* pCreateInfo
,
4076 const VkAllocationCallbacks
* pAllocator
,
4077 VkCommandPool
* pCmdPool
)
4079 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4080 struct radv_cmd_pool
*pool
;
4082 pool
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pool
), 8,
4083 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4085 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4088 pool
->alloc
= *pAllocator
;
4090 pool
->alloc
= device
->alloc
;
4092 list_inithead(&pool
->cmd_buffers
);
4093 list_inithead(&pool
->free_cmd_buffers
);
4095 pool
->queue_family_index
= pCreateInfo
->queueFamilyIndex
;
4097 *pCmdPool
= radv_cmd_pool_to_handle(pool
);
4103 void radv_DestroyCommandPool(
4105 VkCommandPool commandPool
,
4106 const VkAllocationCallbacks
* pAllocator
)
4108 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4109 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
4114 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
4115 &pool
->cmd_buffers
, pool_link
) {
4116 radv_cmd_buffer_destroy(cmd_buffer
);
4119 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
4120 &pool
->free_cmd_buffers
, pool_link
) {
4121 radv_cmd_buffer_destroy(cmd_buffer
);
4124 vk_free2(&device
->alloc
, pAllocator
, pool
);
4127 VkResult
radv_ResetCommandPool(
4129 VkCommandPool commandPool
,
4130 VkCommandPoolResetFlags flags
)
4132 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
4135 list_for_each_entry(struct radv_cmd_buffer
, cmd_buffer
,
4136 &pool
->cmd_buffers
, pool_link
) {
4137 result
= radv_reset_cmd_buffer(cmd_buffer
);
4138 if (result
!= VK_SUCCESS
)
4145 void radv_TrimCommandPool(
4147 VkCommandPool commandPool
,
4148 VkCommandPoolTrimFlags flags
)
4150 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
4155 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
4156 &pool
->free_cmd_buffers
, pool_link
) {
4157 radv_cmd_buffer_destroy(cmd_buffer
);
4162 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer
*cmd_buffer
,
4163 uint32_t subpass_id
)
4165 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4166 struct radv_subpass
*subpass
= &state
->pass
->subpasses
[subpass_id
];
4168 ASSERTED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
4169 cmd_buffer
->cs
, 4096);
4171 radv_subpass_barrier(cmd_buffer
, &subpass
->start_barrier
);
4173 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
);
4175 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4176 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4177 if (a
== VK_ATTACHMENT_UNUSED
)
4180 radv_handle_subpass_image_transition(cmd_buffer
,
4181 subpass
->attachments
[i
],
4185 radv_cmd_buffer_clear_subpass(cmd_buffer
);
4187 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4191 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer
*cmd_buffer
)
4193 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4194 const struct radv_subpass
*subpass
= state
->subpass
;
4195 uint32_t subpass_id
= radv_get_subpass_id(cmd_buffer
);
4197 radv_cmd_buffer_resolve_subpass(cmd_buffer
);
4199 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4200 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4201 if (a
== VK_ATTACHMENT_UNUSED
)
4204 if (state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
4207 VkImageLayout layout
= state
->pass
->attachments
[a
].final_layout
;
4208 struct radv_subpass_attachment att
= { a
, layout
};
4209 radv_handle_subpass_image_transition(cmd_buffer
, att
, false);
4213 void radv_CmdBeginRenderPass(
4214 VkCommandBuffer commandBuffer
,
4215 const VkRenderPassBeginInfo
* pRenderPassBegin
,
4216 VkSubpassContents contents
)
4218 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4219 RADV_FROM_HANDLE(radv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
4220 RADV_FROM_HANDLE(radv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
4223 cmd_buffer
->state
.framebuffer
= framebuffer
;
4224 cmd_buffer
->state
.pass
= pass
;
4225 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
4227 result
= radv_cmd_state_setup_attachments(cmd_buffer
, pass
, pRenderPassBegin
);
4228 if (result
!= VK_SUCCESS
)
4231 result
= radv_cmd_state_setup_sample_locations(cmd_buffer
, pass
, pRenderPassBegin
);
4232 if (result
!= VK_SUCCESS
)
4235 radv_cmd_buffer_begin_subpass(cmd_buffer
, 0);
4238 void radv_CmdBeginRenderPass2KHR(
4239 VkCommandBuffer commandBuffer
,
4240 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
4241 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
)
4243 radv_CmdBeginRenderPass(commandBuffer
, pRenderPassBeginInfo
,
4244 pSubpassBeginInfo
->contents
);
4247 void radv_CmdNextSubpass(
4248 VkCommandBuffer commandBuffer
,
4249 VkSubpassContents contents
)
4251 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4253 uint32_t prev_subpass
= radv_get_subpass_id(cmd_buffer
);
4254 radv_cmd_buffer_end_subpass(cmd_buffer
);
4255 radv_cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
4258 void radv_CmdNextSubpass2KHR(
4259 VkCommandBuffer commandBuffer
,
4260 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
,
4261 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
4263 radv_CmdNextSubpass(commandBuffer
, pSubpassBeginInfo
->contents
);
4266 static void radv_emit_view_index(struct radv_cmd_buffer
*cmd_buffer
, unsigned index
)
4268 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
4269 for (unsigned stage
= 0; stage
< MESA_SHADER_STAGES
; ++stage
) {
4270 if (!radv_get_shader(pipeline
, stage
))
4273 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, AC_UD_VIEW_INDEX
);
4274 if (loc
->sgpr_idx
== -1)
4276 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
4277 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
4280 if (radv_pipeline_has_gs_copy_shader(pipeline
)) {
4281 struct radv_userdata_info
*loc
= &pipeline
->gs_copy_shader
->info
.user_sgprs_locs
.shader_data
[AC_UD_VIEW_INDEX
];
4282 if (loc
->sgpr_idx
!= -1) {
4283 uint32_t base_reg
= R_00B130_SPI_SHADER_USER_DATA_VS_0
;
4284 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
4290 radv_cs_emit_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
4291 uint32_t vertex_count
,
4294 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, cmd_buffer
->state
.predicating
));
4295 radeon_emit(cmd_buffer
->cs
, vertex_count
);
4296 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
4297 S_0287F0_USE_OPAQUE(use_opaque
));
4301 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer
*cmd_buffer
,
4303 uint32_t index_count
)
4305 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_2
, 4, cmd_buffer
->state
.predicating
));
4306 radeon_emit(cmd_buffer
->cs
, cmd_buffer
->state
.max_index_count
);
4307 radeon_emit(cmd_buffer
->cs
, index_va
);
4308 radeon_emit(cmd_buffer
->cs
, index_va
>> 32);
4309 radeon_emit(cmd_buffer
->cs
, index_count
);
4310 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_DMA
);
4314 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
4316 uint32_t draw_count
,
4320 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4321 unsigned di_src_sel
= indexed
? V_0287F0_DI_SRC_SEL_DMA
4322 : V_0287F0_DI_SRC_SEL_AUTO_INDEX
;
4323 bool draw_id_enable
= radv_get_shader(cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
)->info
.vs
.needs_draw_id
;
4324 uint32_t base_reg
= cmd_buffer
->state
.pipeline
->graphics
.vtx_base_sgpr
;
4325 bool predicating
= cmd_buffer
->state
.predicating
;
4328 /* just reset draw state for vertex data */
4329 cmd_buffer
->state
.last_first_instance
= -1;
4330 cmd_buffer
->state
.last_num_instances
= -1;
4331 cmd_buffer
->state
.last_vertex_offset
= -1;
4333 if (draw_count
== 1 && !count_va
&& !draw_id_enable
) {
4334 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT
:
4335 PKT3_DRAW_INDIRECT
, 3, predicating
));
4337 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
4338 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
4339 radeon_emit(cs
, di_src_sel
);
4341 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT_MULTI
:
4342 PKT3_DRAW_INDIRECT_MULTI
,
4345 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
4346 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
4347 radeon_emit(cs
, (((base_reg
+ 8) - SI_SH_REG_OFFSET
) >> 2) |
4348 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable
) |
4349 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va
));
4350 radeon_emit(cs
, draw_count
); /* count */
4351 radeon_emit(cs
, count_va
); /* count_addr */
4352 radeon_emit(cs
, count_va
>> 32);
4353 radeon_emit(cs
, stride
); /* stride */
4354 radeon_emit(cs
, di_src_sel
);
4359 radv_emit_draw_packets(struct radv_cmd_buffer
*cmd_buffer
,
4360 const struct radv_draw_info
*info
)
4362 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4363 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
4364 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4366 if (info
->indirect
) {
4367 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
4368 uint64_t count_va
= 0;
4370 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
4372 radv_cs_add_buffer(ws
, cs
, info
->indirect
->bo
);
4374 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0));
4376 radeon_emit(cs
, va
);
4377 radeon_emit(cs
, va
>> 32);
4379 if (info
->count_buffer
) {
4380 count_va
= radv_buffer_get_va(info
->count_buffer
->bo
);
4381 count_va
+= info
->count_buffer
->offset
+
4382 info
->count_buffer_offset
;
4384 radv_cs_add_buffer(ws
, cs
, info
->count_buffer
->bo
);
4387 if (!state
->subpass
->view_mask
) {
4388 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
4395 for_each_bit(i
, state
->subpass
->view_mask
) {
4396 radv_emit_view_index(cmd_buffer
, i
);
4398 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
4406 assert(state
->pipeline
->graphics
.vtx_base_sgpr
);
4408 if (info
->vertex_offset
!= state
->last_vertex_offset
||
4409 info
->first_instance
!= state
->last_first_instance
) {
4410 radeon_set_sh_reg_seq(cs
, state
->pipeline
->graphics
.vtx_base_sgpr
,
4411 state
->pipeline
->graphics
.vtx_emit_num
);
4413 radeon_emit(cs
, info
->vertex_offset
);
4414 radeon_emit(cs
, info
->first_instance
);
4415 if (state
->pipeline
->graphics
.vtx_emit_num
== 3)
4417 state
->last_first_instance
= info
->first_instance
;
4418 state
->last_vertex_offset
= info
->vertex_offset
;
4421 if (state
->last_num_instances
!= info
->instance_count
) {
4422 radeon_emit(cs
, PKT3(PKT3_NUM_INSTANCES
, 0, false));
4423 radeon_emit(cs
, info
->instance_count
);
4424 state
->last_num_instances
= info
->instance_count
;
4427 if (info
->indexed
) {
4428 int index_size
= radv_get_vgt_index_size(state
->index_type
);
4431 /* Skip draw calls with 0-sized index buffers. They
4432 * cause a hang on some chips, like Navi10-14.
4434 if (!cmd_buffer
->state
.max_index_count
)
4437 index_va
= state
->index_va
;
4438 index_va
+= info
->first_index
* index_size
;
4440 if (!state
->subpass
->view_mask
) {
4441 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
4446 for_each_bit(i
, state
->subpass
->view_mask
) {
4447 radv_emit_view_index(cmd_buffer
, i
);
4449 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
4455 if (!state
->subpass
->view_mask
) {
4456 radv_cs_emit_draw_packet(cmd_buffer
,
4458 !!info
->strmout_buffer
);
4461 for_each_bit(i
, state
->subpass
->view_mask
) {
4462 radv_emit_view_index(cmd_buffer
, i
);
4464 radv_cs_emit_draw_packet(cmd_buffer
,
4466 !!info
->strmout_buffer
);
4474 * Vega and raven have a bug which triggers if there are multiple context
4475 * register contexts active at the same time with different scissor values.
4477 * There are two possible workarounds:
4478 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
4479 * there is only ever 1 active set of scissor values at the same time.
4481 * 2) Whenever the hardware switches contexts we have to set the scissor
4482 * registers again even if it is a noop. That way the new context gets
4483 * the correct scissor values.
4485 * This implements option 2. radv_need_late_scissor_emission needs to
4486 * return true on affected HW if radv_emit_all_graphics_states sets
4487 * any context registers.
4489 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer
*cmd_buffer
,
4490 const struct radv_draw_info
*info
)
4492 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4494 if (!cmd_buffer
->device
->physical_device
->rad_info
.has_gfx9_scissor_bug
)
4497 if (cmd_buffer
->state
.context_roll_without_scissor_emitted
|| info
->strmout_buffer
)
4500 uint32_t used_states
= cmd_buffer
->state
.pipeline
->graphics
.needed_dynamic_state
| ~RADV_CMD_DIRTY_DYNAMIC_ALL
;
4502 /* Index, vertex and streamout buffers don't change context regs, and
4503 * pipeline is already handled.
4505 used_states
&= ~(RADV_CMD_DIRTY_INDEX_BUFFER
|
4506 RADV_CMD_DIRTY_VERTEX_BUFFER
|
4507 RADV_CMD_DIRTY_STREAMOUT_BUFFER
|
4508 RADV_CMD_DIRTY_PIPELINE
);
4510 if (cmd_buffer
->state
.dirty
& used_states
)
4513 uint32_t primitive_reset_index
=
4514 radv_get_primitive_reset_index(cmd_buffer
);
4516 if (info
->indexed
&& state
->pipeline
->graphics
.prim_restart_enable
&&
4517 primitive_reset_index
!= state
->last_primitive_reset_index
)
4524 radv_emit_all_graphics_states(struct radv_cmd_buffer
*cmd_buffer
,
4525 const struct radv_draw_info
*info
)
4527 bool late_scissor_emission
;
4529 if ((cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
) ||
4530 cmd_buffer
->state
.emitted_pipeline
!= cmd_buffer
->state
.pipeline
)
4531 radv_emit_rbplus_state(cmd_buffer
);
4533 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
)
4534 radv_emit_graphics_pipeline(cmd_buffer
);
4536 /* This should be before the cmd_buffer->state.dirty is cleared
4537 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4538 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4539 late_scissor_emission
=
4540 radv_need_late_scissor_emission(cmd_buffer
, info
);
4542 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
)
4543 radv_emit_framebuffer_state(cmd_buffer
);
4545 if (info
->indexed
) {
4546 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_INDEX_BUFFER
)
4547 radv_emit_index_buffer(cmd_buffer
);
4549 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4550 * so the state must be re-emitted before the next indexed
4553 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4554 cmd_buffer
->state
.last_index_type
= -1;
4555 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
4559 radv_cmd_buffer_flush_dynamic_state(cmd_buffer
);
4561 radv_emit_draw_registers(cmd_buffer
, info
);
4563 if (late_scissor_emission
)
4564 radv_emit_scissor(cmd_buffer
);
4568 radv_draw(struct radv_cmd_buffer
*cmd_buffer
,
4569 const struct radv_draw_info
*info
)
4571 struct radeon_info
*rad_info
=
4572 &cmd_buffer
->device
->physical_device
->rad_info
;
4574 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
4575 bool pipeline_is_dirty
=
4576 (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
) &&
4577 cmd_buffer
->state
.pipeline
!= cmd_buffer
->state
.emitted_pipeline
;
4579 ASSERTED
unsigned cdw_max
=
4580 radeon_check_space(cmd_buffer
->device
->ws
,
4581 cmd_buffer
->cs
, 4096);
4583 if (likely(!info
->indirect
)) {
4584 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4585 * no workaround for indirect draws, but we can at least skip
4588 if (unlikely(!info
->instance_count
))
4591 /* Handle count == 0. */
4592 if (unlikely(!info
->count
&& !info
->strmout_buffer
))
4596 /* Use optimal packet order based on whether we need to sync the
4599 if (cmd_buffer
->state
.flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4600 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4601 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
4602 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)) {
4603 /* If we have to wait for idle, set all states first, so that
4604 * all SET packets are processed in parallel with previous draw
4605 * calls. Then upload descriptors, set shader pointers, and
4606 * draw, and prefetch at the end. This ensures that the time
4607 * the CUs are idle is very short. (there are only SET_SH
4608 * packets between the wait and the draw)
4610 radv_emit_all_graphics_states(cmd_buffer
, info
);
4611 si_emit_cache_flush(cmd_buffer
);
4612 /* <-- CUs are idle here --> */
4614 radv_upload_graphics_shader_descriptors(cmd_buffer
, pipeline_is_dirty
);
4616 radv_emit_draw_packets(cmd_buffer
, info
);
4617 /* <-- CUs are busy here --> */
4619 /* Start prefetches after the draw has been started. Both will
4620 * run in parallel, but starting the draw first is more
4623 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
4624 radv_emit_prefetch_L2(cmd_buffer
,
4625 cmd_buffer
->state
.pipeline
, false);
4628 /* If we don't wait for idle, start prefetches first, then set
4629 * states, and draw at the end.
4631 si_emit_cache_flush(cmd_buffer
);
4633 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
4634 /* Only prefetch the vertex shader and VBO descriptors
4635 * in order to start the draw as soon as possible.
4637 radv_emit_prefetch_L2(cmd_buffer
,
4638 cmd_buffer
->state
.pipeline
, true);
4641 radv_upload_graphics_shader_descriptors(cmd_buffer
, pipeline_is_dirty
);
4643 radv_emit_all_graphics_states(cmd_buffer
, info
);
4644 radv_emit_draw_packets(cmd_buffer
, info
);
4646 /* Prefetch the remaining shaders after the draw has been
4649 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
4650 radv_emit_prefetch_L2(cmd_buffer
,
4651 cmd_buffer
->state
.pipeline
, false);
4655 /* Workaround for a VGT hang when streamout is enabled.
4656 * It must be done after drawing.
4658 if (cmd_buffer
->state
.streamout
.streamout_enabled
&&
4659 (rad_info
->family
== CHIP_HAWAII
||
4660 rad_info
->family
== CHIP_TONGA
||
4661 rad_info
->family
== CHIP_FIJI
)) {
4662 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC
;
4665 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4666 radv_cmd_buffer_after_draw(cmd_buffer
, RADV_CMD_FLAG_PS_PARTIAL_FLUSH
);
4670 VkCommandBuffer commandBuffer
,
4671 uint32_t vertexCount
,
4672 uint32_t instanceCount
,
4673 uint32_t firstVertex
,
4674 uint32_t firstInstance
)
4676 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4677 struct radv_draw_info info
= {};
4679 info
.count
= vertexCount
;
4680 info
.instance_count
= instanceCount
;
4681 info
.first_instance
= firstInstance
;
4682 info
.vertex_offset
= firstVertex
;
4684 radv_draw(cmd_buffer
, &info
);
4687 void radv_CmdDrawIndexed(
4688 VkCommandBuffer commandBuffer
,
4689 uint32_t indexCount
,
4690 uint32_t instanceCount
,
4691 uint32_t firstIndex
,
4692 int32_t vertexOffset
,
4693 uint32_t firstInstance
)
4695 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4696 struct radv_draw_info info
= {};
4698 info
.indexed
= true;
4699 info
.count
= indexCount
;
4700 info
.instance_count
= instanceCount
;
4701 info
.first_index
= firstIndex
;
4702 info
.vertex_offset
= vertexOffset
;
4703 info
.first_instance
= firstInstance
;
4705 radv_draw(cmd_buffer
, &info
);
4708 void radv_CmdDrawIndirect(
4709 VkCommandBuffer commandBuffer
,
4711 VkDeviceSize offset
,
4715 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4716 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4717 struct radv_draw_info info
= {};
4719 info
.count
= drawCount
;
4720 info
.indirect
= buffer
;
4721 info
.indirect_offset
= offset
;
4722 info
.stride
= stride
;
4724 radv_draw(cmd_buffer
, &info
);
4727 void radv_CmdDrawIndexedIndirect(
4728 VkCommandBuffer commandBuffer
,
4730 VkDeviceSize offset
,
4734 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4735 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4736 struct radv_draw_info info
= {};
4738 info
.indexed
= true;
4739 info
.count
= drawCount
;
4740 info
.indirect
= buffer
;
4741 info
.indirect_offset
= offset
;
4742 info
.stride
= stride
;
4744 radv_draw(cmd_buffer
, &info
);
4747 void radv_CmdDrawIndirectCountKHR(
4748 VkCommandBuffer commandBuffer
,
4750 VkDeviceSize offset
,
4751 VkBuffer _countBuffer
,
4752 VkDeviceSize countBufferOffset
,
4753 uint32_t maxDrawCount
,
4756 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4757 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4758 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
4759 struct radv_draw_info info
= {};
4761 info
.count
= maxDrawCount
;
4762 info
.indirect
= buffer
;
4763 info
.indirect_offset
= offset
;
4764 info
.count_buffer
= count_buffer
;
4765 info
.count_buffer_offset
= countBufferOffset
;
4766 info
.stride
= stride
;
4768 radv_draw(cmd_buffer
, &info
);
4771 void radv_CmdDrawIndexedIndirectCountKHR(
4772 VkCommandBuffer commandBuffer
,
4774 VkDeviceSize offset
,
4775 VkBuffer _countBuffer
,
4776 VkDeviceSize countBufferOffset
,
4777 uint32_t maxDrawCount
,
4780 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4781 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4782 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
4783 struct radv_draw_info info
= {};
4785 info
.indexed
= true;
4786 info
.count
= maxDrawCount
;
4787 info
.indirect
= buffer
;
4788 info
.indirect_offset
= offset
;
4789 info
.count_buffer
= count_buffer
;
4790 info
.count_buffer_offset
= countBufferOffset
;
4791 info
.stride
= stride
;
4793 radv_draw(cmd_buffer
, &info
);
4796 struct radv_dispatch_info
{
4798 * Determine the layout of the grid (in block units) to be used.
4803 * A starting offset for the grid. If unaligned is set, the offset
4804 * must still be aligned.
4806 uint32_t offsets
[3];
4808 * Whether it's an unaligned compute dispatch.
4813 * Indirect compute parameters resource.
4815 struct radv_buffer
*indirect
;
4816 uint64_t indirect_offset
;
4820 radv_emit_dispatch_packets(struct radv_cmd_buffer
*cmd_buffer
,
4821 const struct radv_dispatch_info
*info
)
4823 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
4824 struct radv_shader_variant
*compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
4825 unsigned dispatch_initiator
= cmd_buffer
->device
->dispatch_initiator
;
4826 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
4827 bool predicating
= cmd_buffer
->state
.predicating
;
4828 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4829 struct radv_userdata_info
*loc
;
4831 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_COMPUTE
,
4832 AC_UD_CS_GRID_SIZE
);
4834 ASSERTED
unsigned cdw_max
= radeon_check_space(ws
, cs
, 25);
4836 if (info
->indirect
) {
4837 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
4839 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
4841 radv_cs_add_buffer(ws
, cs
, info
->indirect
->bo
);
4843 if (loc
->sgpr_idx
!= -1) {
4844 for (unsigned i
= 0; i
< 3; ++i
) {
4845 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
4846 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
4847 COPY_DATA_DST_SEL(COPY_DATA_REG
));
4848 radeon_emit(cs
, (va
+ 4 * i
));
4849 radeon_emit(cs
, (va
+ 4 * i
) >> 32);
4850 radeon_emit(cs
, ((R_00B900_COMPUTE_USER_DATA_0
4851 + loc
->sgpr_idx
* 4) >> 2) + i
);
4856 if (radv_cmd_buffer_uses_mec(cmd_buffer
)) {
4857 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 2, predicating
) |
4858 PKT3_SHADER_TYPE_S(1));
4859 radeon_emit(cs
, va
);
4860 radeon_emit(cs
, va
>> 32);
4861 radeon_emit(cs
, dispatch_initiator
);
4863 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0) |
4864 PKT3_SHADER_TYPE_S(1));
4866 radeon_emit(cs
, va
);
4867 radeon_emit(cs
, va
>> 32);
4869 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 1, predicating
) |
4870 PKT3_SHADER_TYPE_S(1));
4872 radeon_emit(cs
, dispatch_initiator
);
4875 unsigned blocks
[3] = { info
->blocks
[0], info
->blocks
[1], info
->blocks
[2] };
4876 unsigned offsets
[3] = { info
->offsets
[0], info
->offsets
[1], info
->offsets
[2] };
4878 if (info
->unaligned
) {
4879 unsigned *cs_block_size
= compute_shader
->info
.cs
.block_size
;
4880 unsigned remainder
[3];
4882 /* If aligned, these should be an entire block size,
4885 remainder
[0] = blocks
[0] + cs_block_size
[0] -
4886 align_u32_npot(blocks
[0], cs_block_size
[0]);
4887 remainder
[1] = blocks
[1] + cs_block_size
[1] -
4888 align_u32_npot(blocks
[1], cs_block_size
[1]);
4889 remainder
[2] = blocks
[2] + cs_block_size
[2] -
4890 align_u32_npot(blocks
[2], cs_block_size
[2]);
4892 blocks
[0] = round_up_u32(blocks
[0], cs_block_size
[0]);
4893 blocks
[1] = round_up_u32(blocks
[1], cs_block_size
[1]);
4894 blocks
[2] = round_up_u32(blocks
[2], cs_block_size
[2]);
4896 for(unsigned i
= 0; i
< 3; ++i
) {
4897 assert(offsets
[i
] % cs_block_size
[i
] == 0);
4898 offsets
[i
] /= cs_block_size
[i
];
4901 radeon_set_sh_reg_seq(cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
4903 S_00B81C_NUM_THREAD_FULL(cs_block_size
[0]) |
4904 S_00B81C_NUM_THREAD_PARTIAL(remainder
[0]));
4906 S_00B81C_NUM_THREAD_FULL(cs_block_size
[1]) |
4907 S_00B81C_NUM_THREAD_PARTIAL(remainder
[1]));
4909 S_00B81C_NUM_THREAD_FULL(cs_block_size
[2]) |
4910 S_00B81C_NUM_THREAD_PARTIAL(remainder
[2]));
4912 dispatch_initiator
|= S_00B800_PARTIAL_TG_EN(1);
4915 if (loc
->sgpr_idx
!= -1) {
4916 assert(loc
->num_sgprs
== 3);
4918 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
+
4919 loc
->sgpr_idx
* 4, 3);
4920 radeon_emit(cs
, blocks
[0]);
4921 radeon_emit(cs
, blocks
[1]);
4922 radeon_emit(cs
, blocks
[2]);
4925 if (offsets
[0] || offsets
[1] || offsets
[2]) {
4926 radeon_set_sh_reg_seq(cs
, R_00B810_COMPUTE_START_X
, 3);
4927 radeon_emit(cs
, offsets
[0]);
4928 radeon_emit(cs
, offsets
[1]);
4929 radeon_emit(cs
, offsets
[2]);
4931 /* The blocks in the packet are not counts but end values. */
4932 for (unsigned i
= 0; i
< 3; ++i
)
4933 blocks
[i
] += offsets
[i
];
4935 dispatch_initiator
|= S_00B800_FORCE_START_AT_000(1);
4938 radeon_emit(cs
, PKT3(PKT3_DISPATCH_DIRECT
, 3, predicating
) |
4939 PKT3_SHADER_TYPE_S(1));
4940 radeon_emit(cs
, blocks
[0]);
4941 radeon_emit(cs
, blocks
[1]);
4942 radeon_emit(cs
, blocks
[2]);
4943 radeon_emit(cs
, dispatch_initiator
);
4946 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4950 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
4952 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
4953 radv_flush_constants(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
4957 radv_dispatch(struct radv_cmd_buffer
*cmd_buffer
,
4958 const struct radv_dispatch_info
*info
)
4960 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
4962 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
4963 bool pipeline_is_dirty
= pipeline
&&
4964 pipeline
!= cmd_buffer
->state
.emitted_compute_pipeline
;
4966 if (cmd_buffer
->state
.flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4967 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4968 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
4969 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)) {
4970 /* If we have to wait for idle, set all states first, so that
4971 * all SET packets are processed in parallel with previous draw
4972 * calls. Then upload descriptors, set shader pointers, and
4973 * dispatch, and prefetch at the end. This ensures that the
4974 * time the CUs are idle is very short. (there are only SET_SH
4975 * packets between the wait and the draw)
4977 radv_emit_compute_pipeline(cmd_buffer
);
4978 si_emit_cache_flush(cmd_buffer
);
4979 /* <-- CUs are idle here --> */
4981 radv_upload_compute_shader_descriptors(cmd_buffer
);
4983 radv_emit_dispatch_packets(cmd_buffer
, info
);
4984 /* <-- CUs are busy here --> */
4986 /* Start prefetches after the dispatch has been started. Both
4987 * will run in parallel, but starting the dispatch first is
4990 if (has_prefetch
&& pipeline_is_dirty
) {
4991 radv_emit_shader_prefetch(cmd_buffer
,
4992 pipeline
->shaders
[MESA_SHADER_COMPUTE
]);
4995 /* If we don't wait for idle, start prefetches first, then set
4996 * states, and dispatch at the end.
4998 si_emit_cache_flush(cmd_buffer
);
5000 if (has_prefetch
&& pipeline_is_dirty
) {
5001 radv_emit_shader_prefetch(cmd_buffer
,
5002 pipeline
->shaders
[MESA_SHADER_COMPUTE
]);
5005 radv_upload_compute_shader_descriptors(cmd_buffer
);
5007 radv_emit_compute_pipeline(cmd_buffer
);
5008 radv_emit_dispatch_packets(cmd_buffer
, info
);
5011 radv_cmd_buffer_after_draw(cmd_buffer
, RADV_CMD_FLAG_CS_PARTIAL_FLUSH
);
5014 void radv_CmdDispatchBase(
5015 VkCommandBuffer commandBuffer
,
5023 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5024 struct radv_dispatch_info info
= {};
5030 info
.offsets
[0] = base_x
;
5031 info
.offsets
[1] = base_y
;
5032 info
.offsets
[2] = base_z
;
5033 radv_dispatch(cmd_buffer
, &info
);
5036 void radv_CmdDispatch(
5037 VkCommandBuffer commandBuffer
,
5042 radv_CmdDispatchBase(commandBuffer
, 0, 0, 0, x
, y
, z
);
5045 void radv_CmdDispatchIndirect(
5046 VkCommandBuffer commandBuffer
,
5048 VkDeviceSize offset
)
5050 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5051 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
5052 struct radv_dispatch_info info
= {};
5054 info
.indirect
= buffer
;
5055 info
.indirect_offset
= offset
;
5057 radv_dispatch(cmd_buffer
, &info
);
5060 void radv_unaligned_dispatch(
5061 struct radv_cmd_buffer
*cmd_buffer
,
5066 struct radv_dispatch_info info
= {};
5073 radv_dispatch(cmd_buffer
, &info
);
5076 void radv_CmdEndRenderPass(
5077 VkCommandBuffer commandBuffer
)
5079 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5081 radv_subpass_barrier(cmd_buffer
, &cmd_buffer
->state
.pass
->end_barrier
);
5083 radv_cmd_buffer_end_subpass(cmd_buffer
);
5085 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
5086 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.subpass_sample_locs
);
5088 cmd_buffer
->state
.pass
= NULL
;
5089 cmd_buffer
->state
.subpass
= NULL
;
5090 cmd_buffer
->state
.attachments
= NULL
;
5091 cmd_buffer
->state
.framebuffer
= NULL
;
5092 cmd_buffer
->state
.subpass_sample_locs
= NULL
;
5095 void radv_CmdEndRenderPass2KHR(
5096 VkCommandBuffer commandBuffer
,
5097 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
5099 radv_CmdEndRenderPass(commandBuffer
);
5103 * For HTILE we have the following interesting clear words:
5104 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
5105 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
5106 * 0xfffffff0: Clear depth to 1.0
5107 * 0x00000000: Clear depth to 0.0
5109 static void radv_initialize_htile(struct radv_cmd_buffer
*cmd_buffer
,
5110 struct radv_image
*image
,
5111 const VkImageSubresourceRange
*range
,
5112 uint32_t clear_word
)
5114 assert(range
->baseMipLevel
== 0);
5115 assert(range
->levelCount
== 1 || range
->levelCount
== VK_REMAINING_ARRAY_LAYERS
);
5116 VkImageAspectFlags aspects
= VK_IMAGE_ASPECT_DEPTH_BIT
;
5117 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
5118 VkClearDepthStencilValue value
= {};
5120 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
5121 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
5123 state
->flush_bits
|= radv_clear_htile(cmd_buffer
, image
, range
, clear_word
);
5125 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
5127 if (vk_format_is_stencil(image
->vk_format
))
5128 aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
5130 radv_set_ds_clear_metadata(cmd_buffer
, image
, range
, value
, aspects
);
5132 if (radv_image_is_tc_compat_htile(image
)) {
5133 /* Initialize the TC-compat metada value to 0 because by
5134 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
5135 * need have to conditionally update its value when performing
5136 * a fast depth clear.
5138 radv_set_tc_compat_zrange_metadata(cmd_buffer
, image
, range
, 0);
5142 static void radv_handle_depth_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
5143 struct radv_image
*image
,
5144 VkImageLayout src_layout
,
5145 bool src_render_loop
,
5146 VkImageLayout dst_layout
,
5147 bool dst_render_loop
,
5148 unsigned src_queue_mask
,
5149 unsigned dst_queue_mask
,
5150 const VkImageSubresourceRange
*range
,
5151 struct radv_sample_locations_state
*sample_locs
)
5153 if (!radv_image_has_htile(image
))
5156 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
5157 uint32_t clear_value
= vk_format_is_stencil(image
->vk_format
) ? 0xfffff30f : 0xfffc000f;
5159 if (radv_layout_is_htile_compressed(image
, dst_layout
, dst_render_loop
,
5164 radv_initialize_htile(cmd_buffer
, image
, range
, clear_value
);
5165 } else if (!radv_layout_is_htile_compressed(image
, src_layout
, src_render_loop
, src_queue_mask
) &&
5166 radv_layout_is_htile_compressed(image
, dst_layout
, dst_render_loop
, dst_queue_mask
)) {
5167 uint32_t clear_value
= vk_format_is_stencil(image
->vk_format
) ? 0xfffff30f : 0xfffc000f;
5168 radv_initialize_htile(cmd_buffer
, image
, range
, clear_value
);
5169 } else if (radv_layout_is_htile_compressed(image
, src_layout
, src_render_loop
, src_queue_mask
) &&
5170 !radv_layout_is_htile_compressed(image
, dst_layout
, dst_render_loop
, dst_queue_mask
)) {
5171 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
5172 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
5174 radv_decompress_depth_image_inplace(cmd_buffer
, image
, range
,
5177 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
5178 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
5182 static void radv_initialise_cmask(struct radv_cmd_buffer
*cmd_buffer
,
5183 struct radv_image
*image
,
5184 const VkImageSubresourceRange
*range
,
5187 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
5189 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
5190 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5192 state
->flush_bits
|= radv_clear_cmask(cmd_buffer
, image
, range
, value
);
5194 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5197 void radv_initialize_fmask(struct radv_cmd_buffer
*cmd_buffer
,
5198 struct radv_image
*image
,
5199 const VkImageSubresourceRange
*range
)
5201 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
5202 static const uint32_t fmask_clear_values
[4] = {
5208 uint32_t log2_samples
= util_logbase2(image
->info
.samples
);
5209 uint32_t value
= fmask_clear_values
[log2_samples
];
5211 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
5212 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5214 state
->flush_bits
|= radv_clear_fmask(cmd_buffer
, image
, range
, value
);
5216 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5219 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
5220 struct radv_image
*image
,
5221 const VkImageSubresourceRange
*range
, uint32_t value
)
5223 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
5226 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
5227 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5229 state
->flush_bits
|= radv_clear_dcc(cmd_buffer
, image
, range
, value
);
5231 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX8
) {
5232 /* When DCC is enabled with mipmaps, some levels might not
5233 * support fast clears and we have to initialize them as "fully
5236 /* Compute the size of all fast clearable DCC levels. */
5237 for (unsigned i
= 0; i
< image
->planes
[0].surface
.num_dcc_levels
; i
++) {
5238 struct legacy_surf_level
*surf_level
=
5239 &image
->planes
[0].surface
.u
.legacy
.level
[i
];
5240 unsigned dcc_fast_clear_size
=
5241 surf_level
->dcc_slice_fast_clear_size
* image
->info
.array_size
;
5243 if (!dcc_fast_clear_size
)
5246 size
= surf_level
->dcc_offset
+ dcc_fast_clear_size
;
5249 /* Initialize the mipmap levels without DCC. */
5250 if (size
!= image
->planes
[0].surface
.dcc_size
) {
5251 state
->flush_bits
|=
5252 radv_fill_buffer(cmd_buffer
, image
->bo
,
5253 image
->offset
+ image
->dcc_offset
+ size
,
5254 image
->planes
[0].surface
.dcc_size
- size
,
5259 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
5260 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5264 * Initialize DCC/FMASK/CMASK metadata for a color image.
5266 static void radv_init_color_image_metadata(struct radv_cmd_buffer
*cmd_buffer
,
5267 struct radv_image
*image
,
5268 VkImageLayout src_layout
,
5269 bool src_render_loop
,
5270 VkImageLayout dst_layout
,
5271 bool dst_render_loop
,
5272 unsigned src_queue_mask
,
5273 unsigned dst_queue_mask
,
5274 const VkImageSubresourceRange
*range
)
5276 if (radv_image_has_cmask(image
)) {
5277 uint32_t value
= 0xffffffffu
; /* Fully expanded mode. */
5279 /* TODO: clarify this. */
5280 if (radv_image_has_fmask(image
)) {
5281 value
= 0xccccccccu
;
5284 radv_initialise_cmask(cmd_buffer
, image
, range
, value
);
5287 if (radv_image_has_fmask(image
)) {
5288 radv_initialize_fmask(cmd_buffer
, image
, range
);
5291 if (radv_dcc_enabled(image
, range
->baseMipLevel
)) {
5292 uint32_t value
= 0xffffffffu
; /* Fully expanded mode. */
5293 bool need_decompress_pass
= false;
5295 if (radv_layout_dcc_compressed(cmd_buffer
->device
, image
, dst_layout
,
5298 value
= 0x20202020u
;
5299 need_decompress_pass
= true;
5302 radv_initialize_dcc(cmd_buffer
, image
, range
, value
);
5304 radv_update_fce_metadata(cmd_buffer
, image
, range
,
5305 need_decompress_pass
);
5308 if (radv_image_has_cmask(image
) ||
5309 radv_dcc_enabled(image
, range
->baseMipLevel
)) {
5310 uint32_t color_values
[2] = {};
5311 radv_set_color_clear_metadata(cmd_buffer
, image
, range
,
5317 * Handle color image transitions for DCC/FMASK/CMASK.
5319 static void radv_handle_color_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
5320 struct radv_image
*image
,
5321 VkImageLayout src_layout
,
5322 bool src_render_loop
,
5323 VkImageLayout dst_layout
,
5324 bool dst_render_loop
,
5325 unsigned src_queue_mask
,
5326 unsigned dst_queue_mask
,
5327 const VkImageSubresourceRange
*range
)
5329 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
5330 radv_init_color_image_metadata(cmd_buffer
, image
,
5331 src_layout
, src_render_loop
,
5332 dst_layout
, dst_render_loop
,
5333 src_queue_mask
, dst_queue_mask
,
5338 if (radv_dcc_enabled(image
, range
->baseMipLevel
)) {
5339 if (src_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
5340 radv_initialize_dcc(cmd_buffer
, image
, range
, 0xffffffffu
);
5341 } else if (radv_layout_dcc_compressed(cmd_buffer
->device
, image
, src_layout
, src_render_loop
, src_queue_mask
) &&
5342 !radv_layout_dcc_compressed(cmd_buffer
->device
, image
, dst_layout
, dst_render_loop
, dst_queue_mask
)) {
5343 radv_decompress_dcc(cmd_buffer
, image
, range
);
5344 } else if (radv_layout_can_fast_clear(image
, src_layout
, src_render_loop
, src_queue_mask
) &&
5345 !radv_layout_can_fast_clear(image
, dst_layout
, dst_render_loop
, dst_queue_mask
)) {
5346 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
5348 } else if (radv_image_has_cmask(image
) || radv_image_has_fmask(image
)) {
5349 bool fce_eliminate
= false, fmask_expand
= false;
5351 if (radv_layout_can_fast_clear(image
, src_layout
, src_render_loop
, src_queue_mask
) &&
5352 !radv_layout_can_fast_clear(image
, dst_layout
, dst_render_loop
, dst_queue_mask
)) {
5353 fce_eliminate
= true;
5356 if (radv_image_has_fmask(image
)) {
5357 if (src_layout
!= VK_IMAGE_LAYOUT_GENERAL
&&
5358 dst_layout
== VK_IMAGE_LAYOUT_GENERAL
) {
5359 /* A FMASK decompress is required before doing
5360 * a MSAA decompress using FMASK.
5362 fmask_expand
= true;
5366 if (fce_eliminate
|| fmask_expand
)
5367 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
5370 radv_expand_fmask_image_inplace(cmd_buffer
, image
, range
);
5374 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
5375 struct radv_image
*image
,
5376 VkImageLayout src_layout
,
5377 bool src_render_loop
,
5378 VkImageLayout dst_layout
,
5379 bool dst_render_loop
,
5380 uint32_t src_family
,
5381 uint32_t dst_family
,
5382 const VkImageSubresourceRange
*range
,
5383 struct radv_sample_locations_state
*sample_locs
)
5385 if (image
->exclusive
&& src_family
!= dst_family
) {
5386 /* This is an acquire or a release operation and there will be
5387 * a corresponding release/acquire. Do the transition in the
5388 * most flexible queue. */
5390 assert(src_family
== cmd_buffer
->queue_family_index
||
5391 dst_family
== cmd_buffer
->queue_family_index
);
5393 if (src_family
== VK_QUEUE_FAMILY_EXTERNAL
||
5394 src_family
== VK_QUEUE_FAMILY_FOREIGN_EXT
)
5397 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_TRANSFER
)
5400 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
5401 (src_family
== RADV_QUEUE_GENERAL
||
5402 dst_family
== RADV_QUEUE_GENERAL
))
5406 if (src_layout
== dst_layout
)
5409 unsigned src_queue_mask
=
5410 radv_image_queue_family_mask(image
, src_family
,
5411 cmd_buffer
->queue_family_index
);
5412 unsigned dst_queue_mask
=
5413 radv_image_queue_family_mask(image
, dst_family
,
5414 cmd_buffer
->queue_family_index
);
5416 if (vk_format_is_depth(image
->vk_format
)) {
5417 radv_handle_depth_image_transition(cmd_buffer
, image
,
5418 src_layout
, src_render_loop
,
5419 dst_layout
, dst_render_loop
,
5420 src_queue_mask
, dst_queue_mask
,
5421 range
, sample_locs
);
5423 radv_handle_color_image_transition(cmd_buffer
, image
,
5424 src_layout
, src_render_loop
,
5425 dst_layout
, dst_render_loop
,
5426 src_queue_mask
, dst_queue_mask
,
5431 struct radv_barrier_info
{
5432 uint32_t eventCount
;
5433 const VkEvent
*pEvents
;
5434 VkPipelineStageFlags srcStageMask
;
5435 VkPipelineStageFlags dstStageMask
;
5439 radv_barrier(struct radv_cmd_buffer
*cmd_buffer
,
5440 uint32_t memoryBarrierCount
,
5441 const VkMemoryBarrier
*pMemoryBarriers
,
5442 uint32_t bufferMemoryBarrierCount
,
5443 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
5444 uint32_t imageMemoryBarrierCount
,
5445 const VkImageMemoryBarrier
*pImageMemoryBarriers
,
5446 const struct radv_barrier_info
*info
)
5448 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5449 enum radv_cmd_flush_bits src_flush_bits
= 0;
5450 enum radv_cmd_flush_bits dst_flush_bits
= 0;
5452 for (unsigned i
= 0; i
< info
->eventCount
; ++i
) {
5453 RADV_FROM_HANDLE(radv_event
, event
, info
->pEvents
[i
]);
5454 uint64_t va
= radv_buffer_get_va(event
->bo
);
5456 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, event
->bo
);
5458 ASSERTED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 7);
5460 radv_cp_wait_mem(cs
, WAIT_REG_MEM_EQUAL
, va
, 1, 0xffffffff);
5461 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
5464 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
5465 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pMemoryBarriers
[i
].srcAccessMask
,
5467 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pMemoryBarriers
[i
].dstAccessMask
,
5471 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
5472 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].srcAccessMask
,
5474 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].dstAccessMask
,
5478 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
5479 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
5481 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].srcAccessMask
,
5483 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].dstAccessMask
,
5487 /* The Vulkan spec 1.1.98 says:
5489 * "An execution dependency with only
5490 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
5491 * will only prevent that stage from executing in subsequently
5492 * submitted commands. As this stage does not perform any actual
5493 * execution, this is not observable - in effect, it does not delay
5494 * processing of subsequent commands. Similarly an execution dependency
5495 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
5496 * will effectively not wait for any prior commands to complete."
5498 if (info
->dstStageMask
!= VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
)
5499 radv_stage_flush(cmd_buffer
, info
->srcStageMask
);
5500 cmd_buffer
->state
.flush_bits
|= src_flush_bits
;
5502 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
5503 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
5505 const struct VkSampleLocationsInfoEXT
*sample_locs_info
=
5506 vk_find_struct_const(pImageMemoryBarriers
[i
].pNext
,
5507 SAMPLE_LOCATIONS_INFO_EXT
);
5508 struct radv_sample_locations_state sample_locations
= {};
5510 if (sample_locs_info
) {
5511 assert(image
->flags
& VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
);
5512 sample_locations
.per_pixel
= sample_locs_info
->sampleLocationsPerPixel
;
5513 sample_locations
.grid_size
= sample_locs_info
->sampleLocationGridSize
;
5514 sample_locations
.count
= sample_locs_info
->sampleLocationsCount
;
5515 typed_memcpy(&sample_locations
.locations
[0],
5516 sample_locs_info
->pSampleLocations
,
5517 sample_locs_info
->sampleLocationsCount
);
5520 radv_handle_image_transition(cmd_buffer
, image
,
5521 pImageMemoryBarriers
[i
].oldLayout
,
5522 false, /* Outside of a renderpass we are never in a renderloop */
5523 pImageMemoryBarriers
[i
].newLayout
,
5524 false, /* Outside of a renderpass we are never in a renderloop */
5525 pImageMemoryBarriers
[i
].srcQueueFamilyIndex
,
5526 pImageMemoryBarriers
[i
].dstQueueFamilyIndex
,
5527 &pImageMemoryBarriers
[i
].subresourceRange
,
5528 sample_locs_info
? &sample_locations
: NULL
);
5531 /* Make sure CP DMA is idle because the driver might have performed a
5532 * DMA operation for copying or filling buffers/images.
5534 if (info
->srcStageMask
& (VK_PIPELINE_STAGE_TRANSFER_BIT
|
5535 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
))
5536 si_cp_dma_wait_for_idle(cmd_buffer
);
5538 cmd_buffer
->state
.flush_bits
|= dst_flush_bits
;
5541 void radv_CmdPipelineBarrier(
5542 VkCommandBuffer commandBuffer
,
5543 VkPipelineStageFlags srcStageMask
,
5544 VkPipelineStageFlags destStageMask
,
5546 uint32_t memoryBarrierCount
,
5547 const VkMemoryBarrier
* pMemoryBarriers
,
5548 uint32_t bufferMemoryBarrierCount
,
5549 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
5550 uint32_t imageMemoryBarrierCount
,
5551 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
5553 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5554 struct radv_barrier_info info
;
5556 info
.eventCount
= 0;
5557 info
.pEvents
= NULL
;
5558 info
.srcStageMask
= srcStageMask
;
5559 info
.dstStageMask
= destStageMask
;
5561 radv_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
5562 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
5563 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
5567 static void write_event(struct radv_cmd_buffer
*cmd_buffer
,
5568 struct radv_event
*event
,
5569 VkPipelineStageFlags stageMask
,
5572 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5573 uint64_t va
= radv_buffer_get_va(event
->bo
);
5575 si_emit_cache_flush(cmd_buffer
);
5577 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, event
->bo
);
5579 ASSERTED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 21);
5581 /* Flags that only require a top-of-pipe event. */
5582 VkPipelineStageFlags top_of_pipe_flags
=
5583 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
;
5585 /* Flags that only require a post-index-fetch event. */
5586 VkPipelineStageFlags post_index_fetch_flags
=
5588 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
5589 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
;
5591 /* Make sure CP DMA is idle because the driver might have performed a
5592 * DMA operation for copying or filling buffers/images.
5594 if (stageMask
& (VK_PIPELINE_STAGE_TRANSFER_BIT
|
5595 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
))
5596 si_cp_dma_wait_for_idle(cmd_buffer
);
5598 /* TODO: Emit EOS events for syncing PS/CS stages. */
5600 if (!(stageMask
& ~top_of_pipe_flags
)) {
5601 /* Just need to sync the PFP engine. */
5602 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
5603 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
5604 S_370_WR_CONFIRM(1) |
5605 S_370_ENGINE_SEL(V_370_PFP
));
5606 radeon_emit(cs
, va
);
5607 radeon_emit(cs
, va
>> 32);
5608 radeon_emit(cs
, value
);
5609 } else if (!(stageMask
& ~post_index_fetch_flags
)) {
5610 /* Sync ME because PFP reads index and indirect buffers. */
5611 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
5612 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
5613 S_370_WR_CONFIRM(1) |
5614 S_370_ENGINE_SEL(V_370_ME
));
5615 radeon_emit(cs
, va
);
5616 radeon_emit(cs
, va
>> 32);
5617 radeon_emit(cs
, value
);
5619 /* Otherwise, sync all prior GPU work using an EOP event. */
5620 si_cs_emit_write_event_eop(cs
,
5621 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
5622 radv_cmd_buffer_uses_mec(cmd_buffer
),
5623 V_028A90_BOTTOM_OF_PIPE_TS
, 0,
5625 EOP_DATA_SEL_VALUE_32BIT
, va
, value
,
5626 cmd_buffer
->gfx9_eop_bug_va
);
5629 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
5632 void radv_CmdSetEvent(VkCommandBuffer commandBuffer
,
5634 VkPipelineStageFlags stageMask
)
5636 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5637 RADV_FROM_HANDLE(radv_event
, event
, _event
);
5639 write_event(cmd_buffer
, event
, stageMask
, 1);
5642 void radv_CmdResetEvent(VkCommandBuffer commandBuffer
,
5644 VkPipelineStageFlags stageMask
)
5646 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5647 RADV_FROM_HANDLE(radv_event
, event
, _event
);
5649 write_event(cmd_buffer
, event
, stageMask
, 0);
5652 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer
,
5653 uint32_t eventCount
,
5654 const VkEvent
* pEvents
,
5655 VkPipelineStageFlags srcStageMask
,
5656 VkPipelineStageFlags dstStageMask
,
5657 uint32_t memoryBarrierCount
,
5658 const VkMemoryBarrier
* pMemoryBarriers
,
5659 uint32_t bufferMemoryBarrierCount
,
5660 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
5661 uint32_t imageMemoryBarrierCount
,
5662 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
5664 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5665 struct radv_barrier_info info
;
5667 info
.eventCount
= eventCount
;
5668 info
.pEvents
= pEvents
;
5669 info
.srcStageMask
= 0;
5671 radv_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
5672 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
5673 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
5677 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer
,
5678 uint32_t deviceMask
)
5683 /* VK_EXT_conditional_rendering */
5684 void radv_CmdBeginConditionalRenderingEXT(
5685 VkCommandBuffer commandBuffer
,
5686 const VkConditionalRenderingBeginInfoEXT
* pConditionalRenderingBegin
)
5688 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5689 RADV_FROM_HANDLE(radv_buffer
, buffer
, pConditionalRenderingBegin
->buffer
);
5690 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5691 bool draw_visible
= true;
5692 uint64_t pred_value
= 0;
5693 uint64_t va
, new_va
;
5694 unsigned pred_offset
;
5696 va
= radv_buffer_get_va(buffer
->bo
) + pConditionalRenderingBegin
->offset
;
5698 /* By default, if the 32-bit value at offset in buffer memory is zero,
5699 * then the rendering commands are discarded, otherwise they are
5700 * executed as normal. If the inverted flag is set, all commands are
5701 * discarded if the value is non zero.
5703 if (pConditionalRenderingBegin
->flags
&
5704 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT
) {
5705 draw_visible
= false;
5708 si_emit_cache_flush(cmd_buffer
);
5710 /* From the Vulkan spec 1.1.107:
5712 * "If the 32-bit value at offset in buffer memory is zero, then the
5713 * rendering commands are discarded, otherwise they are executed as
5714 * normal. If the value of the predicate in buffer memory changes while
5715 * conditional rendering is active, the rendering commands may be
5716 * discarded in an implementation-dependent way. Some implementations
5717 * may latch the value of the predicate upon beginning conditional
5718 * rendering while others may read it before every rendering command."
5720 * But, the AMD hardware treats the predicate as a 64-bit value which
5721 * means we need a workaround in the driver. Luckily, it's not required
5722 * to support if the value changes when predication is active.
5724 * The workaround is as follows:
5725 * 1) allocate a 64-value in the upload BO and initialize it to 0
5726 * 2) copy the 32-bit predicate value to the upload BO
5727 * 3) use the new allocated VA address for predication
5729 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
5730 * in ME (+ sync PFP) instead of PFP.
5732 radv_cmd_buffer_upload_data(cmd_buffer
, 8, 16, &pred_value
, &pred_offset
);
5734 new_va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
) + pred_offset
;
5736 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
5737 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
5738 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM
) |
5739 COPY_DATA_WR_CONFIRM
);
5740 radeon_emit(cs
, va
);
5741 radeon_emit(cs
, va
>> 32);
5742 radeon_emit(cs
, new_va
);
5743 radeon_emit(cs
, new_va
>> 32);
5745 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
5748 /* Enable predication for this command buffer. */
5749 si_emit_set_predication_state(cmd_buffer
, draw_visible
, new_va
);
5750 cmd_buffer
->state
.predicating
= true;
5752 /* Store conditional rendering user info. */
5753 cmd_buffer
->state
.predication_type
= draw_visible
;
5754 cmd_buffer
->state
.predication_va
= new_va
;
5757 void radv_CmdEndConditionalRenderingEXT(
5758 VkCommandBuffer commandBuffer
)
5760 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5762 /* Disable predication for this command buffer. */
5763 si_emit_set_predication_state(cmd_buffer
, false, 0);
5764 cmd_buffer
->state
.predicating
= false;
5766 /* Reset conditional rendering user info. */
5767 cmd_buffer
->state
.predication_type
= -1;
5768 cmd_buffer
->state
.predication_va
= 0;
5771 /* VK_EXT_transform_feedback */
5772 void radv_CmdBindTransformFeedbackBuffersEXT(
5773 VkCommandBuffer commandBuffer
,
5774 uint32_t firstBinding
,
5775 uint32_t bindingCount
,
5776 const VkBuffer
* pBuffers
,
5777 const VkDeviceSize
* pOffsets
,
5778 const VkDeviceSize
* pSizes
)
5780 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5781 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
5782 uint8_t enabled_mask
= 0;
5784 assert(firstBinding
+ bindingCount
<= MAX_SO_BUFFERS
);
5785 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
5786 uint32_t idx
= firstBinding
+ i
;
5788 sb
[idx
].buffer
= radv_buffer_from_handle(pBuffers
[i
]);
5789 sb
[idx
].offset
= pOffsets
[i
];
5790 sb
[idx
].size
= pSizes
[i
];
5792 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
5793 sb
[idx
].buffer
->bo
);
5795 enabled_mask
|= 1 << idx
;
5798 cmd_buffer
->state
.streamout
.enabled_mask
|= enabled_mask
;
5800 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_STREAMOUT_BUFFER
;
5804 radv_emit_streamout_enable(struct radv_cmd_buffer
*cmd_buffer
)
5806 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
5807 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5809 radeon_set_context_reg_seq(cs
, R_028B94_VGT_STRMOUT_CONFIG
, 2);
5811 S_028B94_STREAMOUT_0_EN(so
->streamout_enabled
) |
5812 S_028B94_RAST_STREAM(0) |
5813 S_028B94_STREAMOUT_1_EN(so
->streamout_enabled
) |
5814 S_028B94_STREAMOUT_2_EN(so
->streamout_enabled
) |
5815 S_028B94_STREAMOUT_3_EN(so
->streamout_enabled
));
5816 radeon_emit(cs
, so
->hw_enabled_mask
&
5817 so
->enabled_stream_buffers_mask
);
5819 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
5823 radv_set_streamout_enable(struct radv_cmd_buffer
*cmd_buffer
, bool enable
)
5825 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
5826 bool old_streamout_enabled
= so
->streamout_enabled
;
5827 uint32_t old_hw_enabled_mask
= so
->hw_enabled_mask
;
5829 so
->streamout_enabled
= enable
;
5831 so
->hw_enabled_mask
= so
->enabled_mask
|
5832 (so
->enabled_mask
<< 4) |
5833 (so
->enabled_mask
<< 8) |
5834 (so
->enabled_mask
<< 12);
5836 if (!cmd_buffer
->device
->physical_device
->use_ngg_streamout
&&
5837 ((old_streamout_enabled
!= so
->streamout_enabled
) ||
5838 (old_hw_enabled_mask
!= so
->hw_enabled_mask
)))
5839 radv_emit_streamout_enable(cmd_buffer
);
5841 if (cmd_buffer
->device
->physical_device
->use_ngg_streamout
)
5842 cmd_buffer
->gds_needed
= true;
5845 static void radv_flush_vgt_streamout(struct radv_cmd_buffer
*cmd_buffer
)
5847 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5848 unsigned reg_strmout_cntl
;
5850 /* The register is at different places on different ASICs. */
5851 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
5852 reg_strmout_cntl
= R_0300FC_CP_STRMOUT_CNTL
;
5853 radeon_set_uconfig_reg(cs
, reg_strmout_cntl
, 0);
5855 reg_strmout_cntl
= R_0084FC_CP_STRMOUT_CNTL
;
5856 radeon_set_config_reg(cs
, reg_strmout_cntl
, 0);
5859 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
5860 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH
) | EVENT_INDEX(0));
5862 radeon_emit(cs
, PKT3(PKT3_WAIT_REG_MEM
, 5, 0));
5863 radeon_emit(cs
, WAIT_REG_MEM_EQUAL
); /* wait until the register is equal to the reference value */
5864 radeon_emit(cs
, reg_strmout_cntl
>> 2); /* register */
5866 radeon_emit(cs
, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
5867 radeon_emit(cs
, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
5868 radeon_emit(cs
, 4); /* poll interval */
5872 radv_emit_streamout_begin(struct radv_cmd_buffer
*cmd_buffer
,
5873 uint32_t firstCounterBuffer
,
5874 uint32_t counterBufferCount
,
5875 const VkBuffer
*pCounterBuffers
,
5876 const VkDeviceSize
*pCounterBufferOffsets
)
5879 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
5880 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
5881 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5884 radv_flush_vgt_streamout(cmd_buffer
);
5886 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
5887 for_each_bit(i
, so
->enabled_mask
) {
5888 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
5889 if (counter_buffer_idx
>= 0 && counter_buffer_idx
>= counterBufferCount
)
5890 counter_buffer_idx
= -1;
5892 /* AMD GCN binds streamout buffers as shader resources.
5893 * VGT only counts primitives and tells the shader through
5896 radeon_set_context_reg_seq(cs
, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0
+ 16*i
, 2);
5897 radeon_emit(cs
, sb
[i
].size
>> 2); /* BUFFER_SIZE (in DW) */
5898 radeon_emit(cs
, so
->stride_in_dw
[i
]); /* VTX_STRIDE (in DW) */
5900 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
5902 if (counter_buffer_idx
>= 0 && pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
]) {
5903 /* The array of counter buffers is optional. */
5904 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
5905 uint64_t va
= radv_buffer_get_va(buffer
->bo
);
5907 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
5910 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
5911 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
5912 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5913 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM
)); /* control */
5914 radeon_emit(cs
, 0); /* unused */
5915 radeon_emit(cs
, 0); /* unused */
5916 radeon_emit(cs
, va
); /* src address lo */
5917 radeon_emit(cs
, va
>> 32); /* src address hi */
5919 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, buffer
->bo
);
5921 /* Start from the beginning. */
5922 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
5923 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
5924 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5925 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET
)); /* control */
5926 radeon_emit(cs
, 0); /* unused */
5927 radeon_emit(cs
, 0); /* unused */
5928 radeon_emit(cs
, 0); /* unused */
5929 radeon_emit(cs
, 0); /* unused */
5933 radv_set_streamout_enable(cmd_buffer
, true);
5937 gfx10_emit_streamout_begin(struct radv_cmd_buffer
*cmd_buffer
,
5938 uint32_t firstCounterBuffer
,
5939 uint32_t counterBufferCount
,
5940 const VkBuffer
*pCounterBuffers
,
5941 const VkDeviceSize
*pCounterBufferOffsets
)
5943 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
5944 unsigned last_target
= util_last_bit(so
->enabled_mask
) - 1;
5945 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5948 assert(cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
);
5949 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
5951 /* Sync because the next streamout operation will overwrite GDS and we
5952 * have to make sure it's idle.
5953 * TODO: Improve by tracking if there is a streamout operation in
5956 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VS_PARTIAL_FLUSH
;
5957 si_emit_cache_flush(cmd_buffer
);
5959 for_each_bit(i
, so
->enabled_mask
) {
5960 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
5961 if (counter_buffer_idx
>= 0 && counter_buffer_idx
>= counterBufferCount
)
5962 counter_buffer_idx
= -1;
5964 bool append
= counter_buffer_idx
>= 0 &&
5965 pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
];
5969 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
5971 va
+= radv_buffer_get_va(buffer
->bo
);
5972 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
5974 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, buffer
->bo
);
5977 radeon_emit(cs
, PKT3(PKT3_DMA_DATA
, 5, 0));
5978 radeon_emit(cs
, S_411_SRC_SEL(append
? V_411_SRC_ADDR_TC_L2
: V_411_DATA
) |
5979 S_411_DST_SEL(V_411_GDS
) |
5980 S_411_CP_SYNC(i
== last_target
));
5981 radeon_emit(cs
, va
);
5982 radeon_emit(cs
, va
>> 32);
5983 radeon_emit(cs
, 4 * i
); /* destination in GDS */
5985 radeon_emit(cs
, S_414_BYTE_COUNT_GFX9(4) |
5986 S_414_DISABLE_WR_CONFIRM_GFX9(i
!= last_target
));
5989 radv_set_streamout_enable(cmd_buffer
, true);
5992 void radv_CmdBeginTransformFeedbackEXT(
5993 VkCommandBuffer commandBuffer
,
5994 uint32_t firstCounterBuffer
,
5995 uint32_t counterBufferCount
,
5996 const VkBuffer
* pCounterBuffers
,
5997 const VkDeviceSize
* pCounterBufferOffsets
)
5999 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
6001 if (cmd_buffer
->device
->physical_device
->use_ngg_streamout
) {
6002 gfx10_emit_streamout_begin(cmd_buffer
,
6003 firstCounterBuffer
, counterBufferCount
,
6004 pCounterBuffers
, pCounterBufferOffsets
);
6006 radv_emit_streamout_begin(cmd_buffer
,
6007 firstCounterBuffer
, counterBufferCount
,
6008 pCounterBuffers
, pCounterBufferOffsets
);
6013 radv_emit_streamout_end(struct radv_cmd_buffer
*cmd_buffer
,
6014 uint32_t firstCounterBuffer
,
6015 uint32_t counterBufferCount
,
6016 const VkBuffer
*pCounterBuffers
,
6017 const VkDeviceSize
*pCounterBufferOffsets
)
6019 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
6020 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
6023 radv_flush_vgt_streamout(cmd_buffer
);
6025 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
6026 for_each_bit(i
, so
->enabled_mask
) {
6027 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
6028 if (counter_buffer_idx
>= 0 && counter_buffer_idx
>= counterBufferCount
)
6029 counter_buffer_idx
= -1;
6031 if (counter_buffer_idx
>= 0 && pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
]) {
6032 /* The array of counters buffer is optional. */
6033 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
6034 uint64_t va
= radv_buffer_get_va(buffer
->bo
);
6036 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
6038 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
6039 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
6040 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6041 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE
) |
6042 STRMOUT_STORE_BUFFER_FILLED_SIZE
); /* control */
6043 radeon_emit(cs
, va
); /* dst address lo */
6044 radeon_emit(cs
, va
>> 32); /* dst address hi */
6045 radeon_emit(cs
, 0); /* unused */
6046 radeon_emit(cs
, 0); /* unused */
6048 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, buffer
->bo
);
6051 /* Deactivate transform feedback by zeroing the buffer size.
6052 * The counters (primitives generated, primitives emitted) may
6053 * be enabled even if there is not buffer bound. This ensures
6054 * that the primitives-emitted query won't increment.
6056 radeon_set_context_reg(cs
, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0
+ 16*i
, 0);
6058 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
6061 radv_set_streamout_enable(cmd_buffer
, false);
6065 gfx10_emit_streamout_end(struct radv_cmd_buffer
*cmd_buffer
,
6066 uint32_t firstCounterBuffer
,
6067 uint32_t counterBufferCount
,
6068 const VkBuffer
*pCounterBuffers
,
6069 const VkDeviceSize
*pCounterBufferOffsets
)
6071 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
6072 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
6075 assert(cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
);
6076 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
6078 for_each_bit(i
, so
->enabled_mask
) {
6079 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
6080 if (counter_buffer_idx
>= 0 && counter_buffer_idx
>= counterBufferCount
)
6081 counter_buffer_idx
= -1;
6083 if (counter_buffer_idx
>= 0 && pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
]) {
6084 /* The array of counters buffer is optional. */
6085 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
6086 uint64_t va
= radv_buffer_get_va(buffer
->bo
);
6088 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
6090 si_cs_emit_write_event_eop(cs
,
6091 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
6092 radv_cmd_buffer_uses_mec(cmd_buffer
),
6093 V_028A90_PS_DONE
, 0,
6096 va
, EOP_DATA_GDS(i
, 1), 0);
6098 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, buffer
->bo
);
6102 radv_set_streamout_enable(cmd_buffer
, false);
6105 void radv_CmdEndTransformFeedbackEXT(
6106 VkCommandBuffer commandBuffer
,
6107 uint32_t firstCounterBuffer
,
6108 uint32_t counterBufferCount
,
6109 const VkBuffer
* pCounterBuffers
,
6110 const VkDeviceSize
* pCounterBufferOffsets
)
6112 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
6114 if (cmd_buffer
->device
->physical_device
->use_ngg_streamout
) {
6115 gfx10_emit_streamout_end(cmd_buffer
,
6116 firstCounterBuffer
, counterBufferCount
,
6117 pCounterBuffers
, pCounterBufferOffsets
);
6119 radv_emit_streamout_end(cmd_buffer
,
6120 firstCounterBuffer
, counterBufferCount
,
6121 pCounterBuffers
, pCounterBufferOffsets
);
6125 void radv_CmdDrawIndirectByteCountEXT(
6126 VkCommandBuffer commandBuffer
,
6127 uint32_t instanceCount
,
6128 uint32_t firstInstance
,
6129 VkBuffer _counterBuffer
,
6130 VkDeviceSize counterBufferOffset
,
6131 uint32_t counterOffset
,
6132 uint32_t vertexStride
)
6134 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
6135 RADV_FROM_HANDLE(radv_buffer
, counterBuffer
, _counterBuffer
);
6136 struct radv_draw_info info
= {};
6138 info
.instance_count
= instanceCount
;
6139 info
.first_instance
= firstInstance
;
6140 info
.strmout_buffer
= counterBuffer
;
6141 info
.strmout_buffer_offset
= counterBufferOffset
;
6142 info
.stride
= vertexStride
;
6144 radv_draw(cmd_buffer
, &info
);
6147 /* VK_AMD_buffer_marker */
6148 void radv_CmdWriteBufferMarkerAMD(
6149 VkCommandBuffer commandBuffer
,
6150 VkPipelineStageFlagBits pipelineStage
,
6152 VkDeviceSize dstOffset
,
6155 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
6156 RADV_FROM_HANDLE(radv_buffer
, buffer
, dstBuffer
);
6157 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
6158 uint64_t va
= radv_buffer_get_va(buffer
->bo
) + dstOffset
;
6160 si_emit_cache_flush(cmd_buffer
);
6162 if (!(pipelineStage
& ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
)) {
6163 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
6164 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_IMM
) |
6165 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM
) |
6166 COPY_DATA_WR_CONFIRM
);
6167 radeon_emit(cs
, marker
);
6169 radeon_emit(cs
, va
);
6170 radeon_emit(cs
, va
>> 32);
6172 si_cs_emit_write_event_eop(cs
,
6173 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
6174 radv_cmd_buffer_uses_mec(cmd_buffer
),
6175 V_028A90_BOTTOM_OF_PIPE_TS
, 0,
6177 EOP_DATA_SEL_VALUE_32BIT
,
6179 cmd_buffer
->gfx9_eop_bug_va
);