2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
33 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
41 RADV_PREFETCH_VBO_DESCRIPTORS
= (1 << 0),
42 RADV_PREFETCH_VS
= (1 << 1),
43 RADV_PREFETCH_TCS
= (1 << 2),
44 RADV_PREFETCH_TES
= (1 << 3),
45 RADV_PREFETCH_GS
= (1 << 4),
46 RADV_PREFETCH_PS
= (1 << 5),
47 RADV_PREFETCH_SHADERS
= (RADV_PREFETCH_VS
|
54 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
55 struct radv_image
*image
,
56 VkImageLayout src_layout
,
58 VkImageLayout dst_layout
,
62 const VkImageSubresourceRange
*range
,
63 struct radv_sample_locations_state
*sample_locs
);
65 const struct radv_dynamic_state default_dynamic_state
= {
78 .blend_constants
= { 0.0f
, 0.0f
, 0.0f
, 0.0f
},
83 .stencil_compare_mask
= {
87 .stencil_write_mask
= {
91 .stencil_reference
= {
98 radv_bind_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
,
99 const struct radv_dynamic_state
*src
)
101 struct radv_dynamic_state
*dest
= &cmd_buffer
->state
.dynamic
;
102 uint32_t copy_mask
= src
->mask
;
103 uint32_t dest_mask
= 0;
105 /* Make sure to copy the number of viewports/scissors because they can
106 * only be specified at pipeline creation time.
108 dest
->viewport
.count
= src
->viewport
.count
;
109 dest
->scissor
.count
= src
->scissor
.count
;
110 dest
->discard_rectangle
.count
= src
->discard_rectangle
.count
;
111 dest
->sample_location
.count
= src
->sample_location
.count
;
113 if (copy_mask
& RADV_DYNAMIC_VIEWPORT
) {
114 if (memcmp(&dest
->viewport
.viewports
, &src
->viewport
.viewports
,
115 src
->viewport
.count
* sizeof(VkViewport
))) {
116 typed_memcpy(dest
->viewport
.viewports
,
117 src
->viewport
.viewports
,
118 src
->viewport
.count
);
119 dest_mask
|= RADV_DYNAMIC_VIEWPORT
;
123 if (copy_mask
& RADV_DYNAMIC_SCISSOR
) {
124 if (memcmp(&dest
->scissor
.scissors
, &src
->scissor
.scissors
,
125 src
->scissor
.count
* sizeof(VkRect2D
))) {
126 typed_memcpy(dest
->scissor
.scissors
,
127 src
->scissor
.scissors
, src
->scissor
.count
);
128 dest_mask
|= RADV_DYNAMIC_SCISSOR
;
132 if (copy_mask
& RADV_DYNAMIC_LINE_WIDTH
) {
133 if (dest
->line_width
!= src
->line_width
) {
134 dest
->line_width
= src
->line_width
;
135 dest_mask
|= RADV_DYNAMIC_LINE_WIDTH
;
139 if (copy_mask
& RADV_DYNAMIC_DEPTH_BIAS
) {
140 if (memcmp(&dest
->depth_bias
, &src
->depth_bias
,
141 sizeof(src
->depth_bias
))) {
142 dest
->depth_bias
= src
->depth_bias
;
143 dest_mask
|= RADV_DYNAMIC_DEPTH_BIAS
;
147 if (copy_mask
& RADV_DYNAMIC_BLEND_CONSTANTS
) {
148 if (memcmp(&dest
->blend_constants
, &src
->blend_constants
,
149 sizeof(src
->blend_constants
))) {
150 typed_memcpy(dest
->blend_constants
,
151 src
->blend_constants
, 4);
152 dest_mask
|= RADV_DYNAMIC_BLEND_CONSTANTS
;
156 if (copy_mask
& RADV_DYNAMIC_DEPTH_BOUNDS
) {
157 if (memcmp(&dest
->depth_bounds
, &src
->depth_bounds
,
158 sizeof(src
->depth_bounds
))) {
159 dest
->depth_bounds
= src
->depth_bounds
;
160 dest_mask
|= RADV_DYNAMIC_DEPTH_BOUNDS
;
164 if (copy_mask
& RADV_DYNAMIC_STENCIL_COMPARE_MASK
) {
165 if (memcmp(&dest
->stencil_compare_mask
,
166 &src
->stencil_compare_mask
,
167 sizeof(src
->stencil_compare_mask
))) {
168 dest
->stencil_compare_mask
= src
->stencil_compare_mask
;
169 dest_mask
|= RADV_DYNAMIC_STENCIL_COMPARE_MASK
;
173 if (copy_mask
& RADV_DYNAMIC_STENCIL_WRITE_MASK
) {
174 if (memcmp(&dest
->stencil_write_mask
, &src
->stencil_write_mask
,
175 sizeof(src
->stencil_write_mask
))) {
176 dest
->stencil_write_mask
= src
->stencil_write_mask
;
177 dest_mask
|= RADV_DYNAMIC_STENCIL_WRITE_MASK
;
181 if (copy_mask
& RADV_DYNAMIC_STENCIL_REFERENCE
) {
182 if (memcmp(&dest
->stencil_reference
, &src
->stencil_reference
,
183 sizeof(src
->stencil_reference
))) {
184 dest
->stencil_reference
= src
->stencil_reference
;
185 dest_mask
|= RADV_DYNAMIC_STENCIL_REFERENCE
;
189 if (copy_mask
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
190 if (memcmp(&dest
->discard_rectangle
.rectangles
, &src
->discard_rectangle
.rectangles
,
191 src
->discard_rectangle
.count
* sizeof(VkRect2D
))) {
192 typed_memcpy(dest
->discard_rectangle
.rectangles
,
193 src
->discard_rectangle
.rectangles
,
194 src
->discard_rectangle
.count
);
195 dest_mask
|= RADV_DYNAMIC_DISCARD_RECTANGLE
;
199 if (copy_mask
& RADV_DYNAMIC_SAMPLE_LOCATIONS
) {
200 if (dest
->sample_location
.per_pixel
!= src
->sample_location
.per_pixel
||
201 dest
->sample_location
.grid_size
.width
!= src
->sample_location
.grid_size
.width
||
202 dest
->sample_location
.grid_size
.height
!= src
->sample_location
.grid_size
.height
||
203 memcmp(&dest
->sample_location
.locations
,
204 &src
->sample_location
.locations
,
205 src
->sample_location
.count
* sizeof(VkSampleLocationEXT
))) {
206 dest
->sample_location
.per_pixel
= src
->sample_location
.per_pixel
;
207 dest
->sample_location
.grid_size
= src
->sample_location
.grid_size
;
208 typed_memcpy(dest
->sample_location
.locations
,
209 src
->sample_location
.locations
,
210 src
->sample_location
.count
);
211 dest_mask
|= RADV_DYNAMIC_SAMPLE_LOCATIONS
;
215 cmd_buffer
->state
.dirty
|= dest_mask
;
219 radv_bind_streamout_state(struct radv_cmd_buffer
*cmd_buffer
,
220 struct radv_pipeline
*pipeline
)
222 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
223 struct radv_shader_info
*info
;
225 if (!pipeline
->streamout_shader
||
226 cmd_buffer
->device
->physical_device
->use_ngg_streamout
)
229 info
= &pipeline
->streamout_shader
->info
;
230 for (int i
= 0; i
< MAX_SO_BUFFERS
; i
++)
231 so
->stride_in_dw
[i
] = info
->so
.strides
[i
];
233 so
->enabled_stream_buffers_mask
= info
->so
.enabled_stream_buffers_mask
;
236 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
)
238 return cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
239 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
242 enum ring_type
radv_queue_family_to_ring(int f
) {
244 case RADV_QUEUE_GENERAL
:
246 case RADV_QUEUE_COMPUTE
:
248 case RADV_QUEUE_TRANSFER
:
251 unreachable("Unknown queue family");
255 static VkResult
radv_create_cmd_buffer(
256 struct radv_device
* device
,
257 struct radv_cmd_pool
* pool
,
258 VkCommandBufferLevel level
,
259 VkCommandBuffer
* pCommandBuffer
)
261 struct radv_cmd_buffer
*cmd_buffer
;
263 cmd_buffer
= vk_zalloc(&pool
->alloc
, sizeof(*cmd_buffer
), 8,
264 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
265 if (cmd_buffer
== NULL
)
266 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
268 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
269 cmd_buffer
->device
= device
;
270 cmd_buffer
->pool
= pool
;
271 cmd_buffer
->level
= level
;
274 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
275 cmd_buffer
->queue_family_index
= pool
->queue_family_index
;
278 /* Init the pool_link so we can safely call list_del when we destroy
281 list_inithead(&cmd_buffer
->pool_link
);
282 cmd_buffer
->queue_family_index
= RADV_QUEUE_GENERAL
;
285 ring
= radv_queue_family_to_ring(cmd_buffer
->queue_family_index
);
287 cmd_buffer
->cs
= device
->ws
->cs_create(device
->ws
, ring
);
288 if (!cmd_buffer
->cs
) {
289 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
290 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
293 *pCommandBuffer
= radv_cmd_buffer_to_handle(cmd_buffer
);
295 list_inithead(&cmd_buffer
->upload
.list
);
301 radv_cmd_buffer_destroy(struct radv_cmd_buffer
*cmd_buffer
)
303 list_del(&cmd_buffer
->pool_link
);
305 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
306 &cmd_buffer
->upload
.list
, list
) {
307 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
312 if (cmd_buffer
->upload
.upload_bo
)
313 cmd_buffer
->device
->ws
->buffer_destroy(cmd_buffer
->upload
.upload_bo
);
314 cmd_buffer
->device
->ws
->cs_destroy(cmd_buffer
->cs
);
316 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++)
317 free(cmd_buffer
->descriptors
[i
].push_set
.set
.mapped_ptr
);
319 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
323 radv_reset_cmd_buffer(struct radv_cmd_buffer
*cmd_buffer
)
325 cmd_buffer
->device
->ws
->cs_reset(cmd_buffer
->cs
);
327 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
328 &cmd_buffer
->upload
.list
, list
) {
329 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
334 cmd_buffer
->push_constant_stages
= 0;
335 cmd_buffer
->scratch_size_needed
= 0;
336 cmd_buffer
->compute_scratch_size_needed
= 0;
337 cmd_buffer
->esgs_ring_size_needed
= 0;
338 cmd_buffer
->gsvs_ring_size_needed
= 0;
339 cmd_buffer
->tess_rings_needed
= false;
340 cmd_buffer
->gds_needed
= false;
341 cmd_buffer
->sample_positions_needed
= false;
343 if (cmd_buffer
->upload
.upload_bo
)
344 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
345 cmd_buffer
->upload
.upload_bo
);
346 cmd_buffer
->upload
.offset
= 0;
348 cmd_buffer
->record_result
= VK_SUCCESS
;
350 memset(cmd_buffer
->vertex_bindings
, 0, sizeof(cmd_buffer
->vertex_bindings
));
352 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++) {
353 cmd_buffer
->descriptors
[i
].dirty
= 0;
354 cmd_buffer
->descriptors
[i
].valid
= 0;
355 cmd_buffer
->descriptors
[i
].push_dirty
= false;
358 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
359 cmd_buffer
->queue_family_index
== RADV_QUEUE_GENERAL
) {
360 unsigned num_db
= cmd_buffer
->device
->physical_device
->rad_info
.num_render_backends
;
361 unsigned fence_offset
, eop_bug_offset
;
364 radv_cmd_buffer_upload_alloc(cmd_buffer
, 8, 8, &fence_offset
,
367 cmd_buffer
->gfx9_fence_va
=
368 radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
369 cmd_buffer
->gfx9_fence_va
+= fence_offset
;
371 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
372 /* Allocate a buffer for the EOP bug on GFX9. */
373 radv_cmd_buffer_upload_alloc(cmd_buffer
, 16 * num_db
, 8,
374 &eop_bug_offset
, &fence_ptr
);
375 cmd_buffer
->gfx9_eop_bug_va
=
376 radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
377 cmd_buffer
->gfx9_eop_bug_va
+= eop_bug_offset
;
381 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_INITIAL
;
383 return cmd_buffer
->record_result
;
387 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer
*cmd_buffer
,
391 struct radeon_winsys_bo
*bo
;
392 struct radv_cmd_buffer_upload
*upload
;
393 struct radv_device
*device
= cmd_buffer
->device
;
395 new_size
= MAX2(min_needed
, 16 * 1024);
396 new_size
= MAX2(new_size
, 2 * cmd_buffer
->upload
.size
);
398 bo
= device
->ws
->buffer_create(device
->ws
,
401 RADEON_FLAG_CPU_ACCESS
|
402 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
404 RADV_BO_PRIORITY_UPLOAD_BUFFER
);
407 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
411 radv_cs_add_buffer(device
->ws
, cmd_buffer
->cs
, bo
);
412 if (cmd_buffer
->upload
.upload_bo
) {
413 upload
= malloc(sizeof(*upload
));
416 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
417 device
->ws
->buffer_destroy(bo
);
421 memcpy(upload
, &cmd_buffer
->upload
, sizeof(*upload
));
422 list_add(&upload
->list
, &cmd_buffer
->upload
.list
);
425 cmd_buffer
->upload
.upload_bo
= bo
;
426 cmd_buffer
->upload
.size
= new_size
;
427 cmd_buffer
->upload
.offset
= 0;
428 cmd_buffer
->upload
.map
= device
->ws
->buffer_map(cmd_buffer
->upload
.upload_bo
);
430 if (!cmd_buffer
->upload
.map
) {
431 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
439 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
442 unsigned *out_offset
,
445 assert(util_is_power_of_two_nonzero(alignment
));
447 uint64_t offset
= align(cmd_buffer
->upload
.offset
, alignment
);
448 if (offset
+ size
> cmd_buffer
->upload
.size
) {
449 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer
, size
))
454 *out_offset
= offset
;
455 *ptr
= cmd_buffer
->upload
.map
+ offset
;
457 cmd_buffer
->upload
.offset
= offset
+ size
;
462 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
463 unsigned size
, unsigned alignment
,
464 const void *data
, unsigned *out_offset
)
468 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
, alignment
,
469 out_offset
, (void **)&ptr
))
473 memcpy(ptr
, data
, size
);
479 radv_emit_write_data_packet(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
480 unsigned count
, const uint32_t *data
)
482 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
484 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 4 + count
);
486 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, 0));
487 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
488 S_370_WR_CONFIRM(1) |
489 S_370_ENGINE_SEL(V_370_ME
));
491 radeon_emit(cs
, va
>> 32);
492 radeon_emit_array(cs
, data
, count
);
495 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
)
497 struct radv_device
*device
= cmd_buffer
->device
;
498 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
501 va
= radv_buffer_get_va(device
->trace_bo
);
502 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
)
505 ++cmd_buffer
->state
.trace_id
;
506 radv_emit_write_data_packet(cmd_buffer
, va
, 1,
507 &cmd_buffer
->state
.trace_id
);
509 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 2);
511 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
512 radeon_emit(cs
, AC_ENCODE_TRACE_POINT(cmd_buffer
->state
.trace_id
));
516 radv_cmd_buffer_after_draw(struct radv_cmd_buffer
*cmd_buffer
,
517 enum radv_cmd_flush_bits flags
)
519 if (cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_SYNC_SHADERS
) {
520 assert(flags
& (RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
521 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
));
523 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 4);
525 /* Force wait for graphics or compute engines to be idle. */
526 si_cs_emit_cache_flush(cmd_buffer
->cs
,
527 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
528 &cmd_buffer
->gfx9_fence_idx
,
529 cmd_buffer
->gfx9_fence_va
,
530 radv_cmd_buffer_uses_mec(cmd_buffer
),
531 flags
, cmd_buffer
->gfx9_eop_bug_va
);
534 if (unlikely(cmd_buffer
->device
->trace_bo
))
535 radv_cmd_buffer_trace_emit(cmd_buffer
);
539 radv_save_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
540 struct radv_pipeline
*pipeline
, enum ring_type ring
)
542 struct radv_device
*device
= cmd_buffer
->device
;
546 va
= radv_buffer_get_va(device
->trace_bo
);
556 assert(!"invalid ring type");
559 data
[0] = (uintptr_t)pipeline
;
560 data
[1] = (uintptr_t)pipeline
>> 32;
562 radv_emit_write_data_packet(cmd_buffer
, va
, 2, data
);
565 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
566 VkPipelineBindPoint bind_point
,
567 struct radv_descriptor_set
*set
,
570 struct radv_descriptor_state
*descriptors_state
=
571 radv_get_descriptors_state(cmd_buffer
, bind_point
);
573 descriptors_state
->sets
[idx
] = set
;
575 descriptors_state
->valid
|= (1u << idx
); /* active descriptors */
576 descriptors_state
->dirty
|= (1u << idx
);
580 radv_save_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
581 VkPipelineBindPoint bind_point
)
583 struct radv_descriptor_state
*descriptors_state
=
584 radv_get_descriptors_state(cmd_buffer
, bind_point
);
585 struct radv_device
*device
= cmd_buffer
->device
;
586 uint32_t data
[MAX_SETS
* 2] = {};
589 va
= radv_buffer_get_va(device
->trace_bo
) + 24;
591 for_each_bit(i
, descriptors_state
->valid
) {
592 struct radv_descriptor_set
*set
= descriptors_state
->sets
[i
];
593 data
[i
* 2] = (uint64_t)(uintptr_t)set
;
594 data
[i
* 2 + 1] = (uint64_t)(uintptr_t)set
>> 32;
597 radv_emit_write_data_packet(cmd_buffer
, va
, MAX_SETS
* 2, data
);
600 struct radv_userdata_info
*
601 radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
602 gl_shader_stage stage
,
605 struct radv_shader_variant
*shader
= radv_get_shader(pipeline
, stage
);
606 return &shader
->info
.user_sgprs_locs
.shader_data
[idx
];
610 radv_emit_userdata_address(struct radv_cmd_buffer
*cmd_buffer
,
611 struct radv_pipeline
*pipeline
,
612 gl_shader_stage stage
,
613 int idx
, uint64_t va
)
615 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, idx
);
616 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
617 if (loc
->sgpr_idx
== -1)
620 assert(loc
->num_sgprs
== 1);
622 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
623 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
627 radv_emit_descriptor_pointers(struct radv_cmd_buffer
*cmd_buffer
,
628 struct radv_pipeline
*pipeline
,
629 struct radv_descriptor_state
*descriptors_state
,
630 gl_shader_stage stage
)
632 struct radv_device
*device
= cmd_buffer
->device
;
633 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
634 uint32_t sh_base
= pipeline
->user_data_0
[stage
];
635 struct radv_userdata_locations
*locs
=
636 &pipeline
->shaders
[stage
]->info
.user_sgprs_locs
;
637 unsigned mask
= locs
->descriptor_sets_enabled
;
639 mask
&= descriptors_state
->dirty
& descriptors_state
->valid
;
644 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
646 struct radv_userdata_info
*loc
= &locs
->descriptor_sets
[start
];
647 unsigned sh_offset
= sh_base
+ loc
->sgpr_idx
* 4;
649 radv_emit_shader_pointer_head(cs
, sh_offset
, count
, true);
650 for (int i
= 0; i
< count
; i
++) {
651 struct radv_descriptor_set
*set
=
652 descriptors_state
->sets
[start
+ i
];
654 radv_emit_shader_pointer_body(device
, cs
, set
->va
, true);
660 * Convert the user sample locations to hardware sample locations (the values
661 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
664 radv_convert_user_sample_locs(struct radv_sample_locations_state
*state
,
665 uint32_t x
, uint32_t y
, VkOffset2D
*sample_locs
)
667 uint32_t x_offset
= x
% state
->grid_size
.width
;
668 uint32_t y_offset
= y
% state
->grid_size
.height
;
669 uint32_t num_samples
= (uint32_t)state
->per_pixel
;
670 VkSampleLocationEXT
*user_locs
;
671 uint32_t pixel_offset
;
673 pixel_offset
= (x_offset
+ y_offset
* state
->grid_size
.width
) * num_samples
;
675 assert(pixel_offset
<= MAX_SAMPLE_LOCATIONS
);
676 user_locs
= &state
->locations
[pixel_offset
];
678 for (uint32_t i
= 0; i
< num_samples
; i
++) {
679 float shifted_pos_x
= user_locs
[i
].x
- 0.5;
680 float shifted_pos_y
= user_locs
[i
].y
- 0.5;
682 int32_t scaled_pos_x
= floor(shifted_pos_x
* 16);
683 int32_t scaled_pos_y
= floor(shifted_pos_y
* 16);
685 sample_locs
[i
].x
= CLAMP(scaled_pos_x
, -8, 7);
686 sample_locs
[i
].y
= CLAMP(scaled_pos_y
, -8, 7);
691 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
695 radv_compute_sample_locs_pixel(uint32_t num_samples
, VkOffset2D
*sample_locs
,
696 uint32_t *sample_locs_pixel
)
698 for (uint32_t i
= 0; i
< num_samples
; i
++) {
699 uint32_t sample_reg_idx
= i
/ 4;
700 uint32_t sample_loc_idx
= i
% 4;
701 int32_t pos_x
= sample_locs
[i
].x
;
702 int32_t pos_y
= sample_locs
[i
].y
;
704 uint32_t shift_x
= 8 * sample_loc_idx
;
705 uint32_t shift_y
= shift_x
+ 4;
707 sample_locs_pixel
[sample_reg_idx
] |= (pos_x
& 0xf) << shift_x
;
708 sample_locs_pixel
[sample_reg_idx
] |= (pos_y
& 0xf) << shift_y
;
713 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
717 radv_compute_centroid_priority(struct radv_cmd_buffer
*cmd_buffer
,
718 VkOffset2D
*sample_locs
,
719 uint32_t num_samples
)
721 uint32_t centroid_priorities
[num_samples
];
722 uint32_t sample_mask
= num_samples
- 1;
723 uint32_t distances
[num_samples
];
724 uint64_t centroid_priority
= 0;
726 /* Compute the distances from center for each sample. */
727 for (int i
= 0; i
< num_samples
; i
++) {
728 distances
[i
] = (sample_locs
[i
].x
* sample_locs
[i
].x
) +
729 (sample_locs
[i
].y
* sample_locs
[i
].y
);
732 /* Compute the centroid priorities by looking at the distances array. */
733 for (int i
= 0; i
< num_samples
; i
++) {
734 uint32_t min_idx
= 0;
736 for (int j
= 1; j
< num_samples
; j
++) {
737 if (distances
[j
] < distances
[min_idx
])
741 centroid_priorities
[i
] = min_idx
;
742 distances
[min_idx
] = 0xffffffff;
745 /* Compute the final centroid priority. */
746 for (int i
= 0; i
< 8; i
++) {
748 centroid_priorities
[i
& sample_mask
] << (i
* 4);
751 return centroid_priority
<< 32 | centroid_priority
;
755 * Emit the sample locations that are specified with VK_EXT_sample_locations.
758 radv_emit_sample_locations(struct radv_cmd_buffer
*cmd_buffer
)
760 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
761 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
762 struct radv_sample_locations_state
*sample_location
=
763 &cmd_buffer
->state
.dynamic
.sample_location
;
764 uint32_t num_samples
= (uint32_t)sample_location
->per_pixel
;
765 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
766 uint32_t sample_locs_pixel
[4][2] = {};
767 VkOffset2D sample_locs
[4][8]; /* 8 is the max. sample count supported */
768 uint32_t max_sample_dist
= 0;
769 uint64_t centroid_priority
;
771 if (!cmd_buffer
->state
.dynamic
.sample_location
.count
)
774 /* Convert the user sample locations to hardware sample locations. */
775 radv_convert_user_sample_locs(sample_location
, 0, 0, sample_locs
[0]);
776 radv_convert_user_sample_locs(sample_location
, 1, 0, sample_locs
[1]);
777 radv_convert_user_sample_locs(sample_location
, 0, 1, sample_locs
[2]);
778 radv_convert_user_sample_locs(sample_location
, 1, 1, sample_locs
[3]);
780 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
781 for (uint32_t i
= 0; i
< 4; i
++) {
782 radv_compute_sample_locs_pixel(num_samples
, sample_locs
[i
],
783 sample_locs_pixel
[i
]);
786 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
788 radv_compute_centroid_priority(cmd_buffer
, sample_locs
[0],
791 /* Compute the maximum sample distance from the specified locations. */
792 for (uint32_t i
= 0; i
< num_samples
; i
++) {
793 VkOffset2D offset
= sample_locs
[0][i
];
794 max_sample_dist
= MAX2(max_sample_dist
,
795 MAX2(abs(offset
.x
), abs(offset
.y
)));
798 /* Emit the specified user sample locations. */
799 switch (num_samples
) {
802 radeon_set_context_reg(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_pixel
[0][0]);
803 radeon_set_context_reg(cs
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_pixel
[1][0]);
804 radeon_set_context_reg(cs
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_pixel
[2][0]);
805 radeon_set_context_reg(cs
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_pixel
[3][0]);
808 radeon_set_context_reg(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_pixel
[0][0]);
809 radeon_set_context_reg(cs
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_pixel
[1][0]);
810 radeon_set_context_reg(cs
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_pixel
[2][0]);
811 radeon_set_context_reg(cs
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_pixel
[3][0]);
812 radeon_set_context_reg(cs
, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1
, sample_locs_pixel
[0][1]);
813 radeon_set_context_reg(cs
, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1
, sample_locs_pixel
[1][1]);
814 radeon_set_context_reg(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1
, sample_locs_pixel
[2][1]);
815 radeon_set_context_reg(cs
, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1
, sample_locs_pixel
[3][1]);
818 unreachable("invalid number of samples");
821 /* Emit the maximum sample distance and the centroid priority. */
822 uint32_t pa_sc_aa_config
= ms
->pa_sc_aa_config
;
824 pa_sc_aa_config
&= C_028BE0_MAX_SAMPLE_DIST
;
825 pa_sc_aa_config
|= S_028BE0_MAX_SAMPLE_DIST(max_sample_dist
);
827 radeon_set_context_reg_seq(cs
, R_028BE0_PA_SC_AA_CONFIG
, 1);
828 radeon_emit(cs
, pa_sc_aa_config
);
830 radeon_set_context_reg_seq(cs
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 2);
831 radeon_emit(cs
, centroid_priority
);
832 radeon_emit(cs
, centroid_priority
>> 32);
834 /* GFX9: Flush DFSM when the AA mode changes. */
835 if (cmd_buffer
->device
->dfsm_allowed
) {
836 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
837 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
840 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
844 radv_emit_inline_push_consts(struct radv_cmd_buffer
*cmd_buffer
,
845 struct radv_pipeline
*pipeline
,
846 gl_shader_stage stage
,
847 int idx
, int count
, uint32_t *values
)
849 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, idx
);
850 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
851 if (loc
->sgpr_idx
== -1)
854 assert(loc
->num_sgprs
== count
);
856 radeon_set_sh_reg_seq(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, count
);
857 radeon_emit_array(cmd_buffer
->cs
, values
, count
);
861 radv_update_multisample_state(struct radv_cmd_buffer
*cmd_buffer
,
862 struct radv_pipeline
*pipeline
)
864 int num_samples
= pipeline
->graphics
.ms
.num_samples
;
865 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
866 struct radv_pipeline
*old_pipeline
= cmd_buffer
->state
.emitted_pipeline
;
868 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.needs_sample_positions
)
869 cmd_buffer
->sample_positions_needed
= true;
871 if (old_pipeline
&& num_samples
== old_pipeline
->graphics
.ms
.num_samples
)
874 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028BDC_PA_SC_LINE_CNTL
, 2);
875 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_line_cntl
);
876 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_config
);
878 radeon_set_context_reg(cmd_buffer
->cs
, R_028A48_PA_SC_MODE_CNTL_0
, ms
->pa_sc_mode_cntl_0
);
880 radv_emit_default_sample_locations(cmd_buffer
->cs
, num_samples
);
882 /* GFX9: Flush DFSM when the AA mode changes. */
883 if (cmd_buffer
->device
->dfsm_allowed
) {
884 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
885 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
888 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
892 radv_update_binning_state(struct radv_cmd_buffer
*cmd_buffer
,
893 struct radv_pipeline
*pipeline
)
895 const struct radv_pipeline
*old_pipeline
= cmd_buffer
->state
.emitted_pipeline
;
898 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX9
)
902 old_pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
== pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
&&
903 old_pipeline
->graphics
.binning
.db_dfsm_control
== pipeline
->graphics
.binning
.db_dfsm_control
)
906 bool binning_flush
= false;
907 if (cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_VEGA12
||
908 cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_VEGA20
||
909 cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_RAVEN2
||
910 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
911 binning_flush
= !old_pipeline
||
912 G_028C44_BINNING_MODE(old_pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
) !=
913 G_028C44_BINNING_MODE(pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
);
916 radeon_set_context_reg(cmd_buffer
->cs
, R_028C44_PA_SC_BINNER_CNTL_0
,
917 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
|
918 S_028C44_FLUSH_ON_BINNING_TRANSITION(!!binning_flush
));
920 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
921 radeon_set_context_reg(cmd_buffer
->cs
, R_028038_DB_DFSM_CONTROL
,
922 pipeline
->graphics
.binning
.db_dfsm_control
);
924 radeon_set_context_reg(cmd_buffer
->cs
, R_028060_DB_DFSM_CONTROL
,
925 pipeline
->graphics
.binning
.db_dfsm_control
);
928 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
933 radv_emit_shader_prefetch(struct radv_cmd_buffer
*cmd_buffer
,
934 struct radv_shader_variant
*shader
)
941 va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
943 si_cp_dma_prefetch(cmd_buffer
, va
, shader
->code_size
);
947 radv_emit_prefetch_L2(struct radv_cmd_buffer
*cmd_buffer
,
948 struct radv_pipeline
*pipeline
,
949 bool vertex_stage_only
)
951 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
952 uint32_t mask
= state
->prefetch_L2_mask
;
954 if (vertex_stage_only
) {
955 /* Fast prefetch path for starting draws as soon as possible.
957 mask
= state
->prefetch_L2_mask
& (RADV_PREFETCH_VS
|
958 RADV_PREFETCH_VBO_DESCRIPTORS
);
961 if (mask
& RADV_PREFETCH_VS
)
962 radv_emit_shader_prefetch(cmd_buffer
,
963 pipeline
->shaders
[MESA_SHADER_VERTEX
]);
965 if (mask
& RADV_PREFETCH_VBO_DESCRIPTORS
)
966 si_cp_dma_prefetch(cmd_buffer
, state
->vb_va
, state
->vb_size
);
968 if (mask
& RADV_PREFETCH_TCS
)
969 radv_emit_shader_prefetch(cmd_buffer
,
970 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]);
972 if (mask
& RADV_PREFETCH_TES
)
973 radv_emit_shader_prefetch(cmd_buffer
,
974 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]);
976 if (mask
& RADV_PREFETCH_GS
) {
977 radv_emit_shader_prefetch(cmd_buffer
,
978 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]);
979 if (radv_pipeline_has_gs_copy_shader(pipeline
))
980 radv_emit_shader_prefetch(cmd_buffer
, pipeline
->gs_copy_shader
);
983 if (mask
& RADV_PREFETCH_PS
)
984 radv_emit_shader_prefetch(cmd_buffer
,
985 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
987 state
->prefetch_L2_mask
&= ~mask
;
991 radv_emit_rbplus_state(struct radv_cmd_buffer
*cmd_buffer
)
993 if (!cmd_buffer
->device
->physical_device
->rad_info
.rbplus_allowed
)
996 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
997 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
999 unsigned sx_ps_downconvert
= 0;
1000 unsigned sx_blend_opt_epsilon
= 0;
1001 unsigned sx_blend_opt_control
= 0;
1003 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1004 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
1005 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
1006 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
1010 int idx
= subpass
->color_attachments
[i
].attachment
;
1011 struct radv_color_buffer_info
*cb
= &cmd_buffer
->state
.attachments
[idx
].cb
;
1013 unsigned format
= G_028C70_FORMAT(cb
->cb_color_info
);
1014 unsigned swap
= G_028C70_COMP_SWAP(cb
->cb_color_info
);
1015 uint32_t spi_format
= (pipeline
->graphics
.col_format
>> (i
* 4)) & 0xf;
1016 uint32_t colormask
= (pipeline
->graphics
.cb_target_mask
>> (i
* 4)) & 0xf;
1018 bool has_alpha
, has_rgb
;
1020 /* Set if RGB and A are present. */
1021 has_alpha
= !G_028C74_FORCE_DST_ALPHA_1(cb
->cb_color_attrib
);
1023 if (format
== V_028C70_COLOR_8
||
1024 format
== V_028C70_COLOR_16
||
1025 format
== V_028C70_COLOR_32
)
1026 has_rgb
= !has_alpha
;
1030 /* Check the colormask and export format. */
1031 if (!(colormask
& 0x7))
1033 if (!(colormask
& 0x8))
1036 if (spi_format
== V_028714_SPI_SHADER_ZERO
) {
1041 /* Disable value checking for disabled channels. */
1043 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
1045 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
1047 /* Enable down-conversion for 32bpp and smaller formats. */
1049 case V_028C70_COLOR_8
:
1050 case V_028C70_COLOR_8_8
:
1051 case V_028C70_COLOR_8_8_8_8
:
1052 /* For 1 and 2-channel formats, use the superset thereof. */
1053 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
||
1054 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
1055 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
1056 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_8_8_8_8
<< (i
* 4);
1057 sx_blend_opt_epsilon
|= V_028758_8BIT_FORMAT
<< (i
* 4);
1061 case V_028C70_COLOR_5_6_5
:
1062 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1063 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_5_6_5
<< (i
* 4);
1064 sx_blend_opt_epsilon
|= V_028758_6BIT_FORMAT
<< (i
* 4);
1068 case V_028C70_COLOR_1_5_5_5
:
1069 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1070 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_1_5_5_5
<< (i
* 4);
1071 sx_blend_opt_epsilon
|= V_028758_5BIT_FORMAT
<< (i
* 4);
1075 case V_028C70_COLOR_4_4_4_4
:
1076 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1077 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_4_4_4_4
<< (i
* 4);
1078 sx_blend_opt_epsilon
|= V_028758_4BIT_FORMAT
<< (i
* 4);
1082 case V_028C70_COLOR_32
:
1083 if (swap
== V_028C70_SWAP_STD
&&
1084 spi_format
== V_028714_SPI_SHADER_32_R
)
1085 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
1086 else if (swap
== V_028C70_SWAP_ALT_REV
&&
1087 spi_format
== V_028714_SPI_SHADER_32_AR
)
1088 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_A
<< (i
* 4);
1091 case V_028C70_COLOR_16
:
1092 case V_028C70_COLOR_16_16
:
1093 /* For 1-channel formats, use the superset thereof. */
1094 if (spi_format
== V_028714_SPI_SHADER_UNORM16_ABGR
||
1095 spi_format
== V_028714_SPI_SHADER_SNORM16_ABGR
||
1096 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
1097 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
1098 if (swap
== V_028C70_SWAP_STD
||
1099 swap
== V_028C70_SWAP_STD_REV
)
1100 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_GR
<< (i
* 4);
1102 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_AR
<< (i
* 4);
1106 case V_028C70_COLOR_10_11_11
:
1107 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1108 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_10_11_11
<< (i
* 4);
1109 sx_blend_opt_epsilon
|= V_028758_11BIT_FORMAT
<< (i
* 4);
1113 case V_028C70_COLOR_2_10_10_10
:
1114 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1115 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_2_10_10_10
<< (i
* 4);
1116 sx_blend_opt_epsilon
|= V_028758_10BIT_FORMAT
<< (i
* 4);
1122 for (unsigned i
= subpass
->color_count
; i
< 8; ++i
) {
1123 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
1124 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
1126 /* TODO: avoid redundantly setting context registers */
1127 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
1128 radeon_emit(cmd_buffer
->cs
, sx_ps_downconvert
);
1129 radeon_emit(cmd_buffer
->cs
, sx_blend_opt_epsilon
);
1130 radeon_emit(cmd_buffer
->cs
, sx_blend_opt_control
);
1132 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1136 radv_emit_graphics_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
1138 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1140 if (!pipeline
|| cmd_buffer
->state
.emitted_pipeline
== pipeline
)
1143 radv_update_multisample_state(cmd_buffer
, pipeline
);
1144 radv_update_binning_state(cmd_buffer
, pipeline
);
1146 cmd_buffer
->scratch_size_needed
=
1147 MAX2(cmd_buffer
->scratch_size_needed
,
1148 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
1150 if (!cmd_buffer
->state
.emitted_pipeline
||
1151 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
!=
1152 pipeline
->graphics
.can_use_guardband
)
1153 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
1155 radeon_emit_array(cmd_buffer
->cs
, pipeline
->cs
.buf
, pipeline
->cs
.cdw
);
1157 if (!cmd_buffer
->state
.emitted_pipeline
||
1158 cmd_buffer
->state
.emitted_pipeline
->ctx_cs
.cdw
!= pipeline
->ctx_cs
.cdw
||
1159 cmd_buffer
->state
.emitted_pipeline
->ctx_cs_hash
!= pipeline
->ctx_cs_hash
||
1160 memcmp(cmd_buffer
->state
.emitted_pipeline
->ctx_cs
.buf
,
1161 pipeline
->ctx_cs
.buf
, pipeline
->ctx_cs
.cdw
* 4)) {
1162 radeon_emit_array(cmd_buffer
->cs
, pipeline
->ctx_cs
.buf
, pipeline
->ctx_cs
.cdw
);
1163 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1166 for (unsigned i
= 0; i
< MESA_SHADER_COMPUTE
; i
++) {
1167 if (!pipeline
->shaders
[i
])
1170 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
1171 pipeline
->shaders
[i
]->bo
);
1174 if (radv_pipeline_has_gs_copy_shader(pipeline
))
1175 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
1176 pipeline
->gs_copy_shader
->bo
);
1178 if (unlikely(cmd_buffer
->device
->trace_bo
))
1179 radv_save_pipeline(cmd_buffer
, pipeline
, RING_GFX
);
1181 cmd_buffer
->state
.emitted_pipeline
= pipeline
;
1183 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_PIPELINE
;
1187 radv_emit_viewport(struct radv_cmd_buffer
*cmd_buffer
)
1189 si_write_viewport(cmd_buffer
->cs
, 0, cmd_buffer
->state
.dynamic
.viewport
.count
,
1190 cmd_buffer
->state
.dynamic
.viewport
.viewports
);
1194 radv_emit_scissor(struct radv_cmd_buffer
*cmd_buffer
)
1196 uint32_t count
= cmd_buffer
->state
.dynamic
.scissor
.count
;
1198 si_write_scissors(cmd_buffer
->cs
, 0, count
,
1199 cmd_buffer
->state
.dynamic
.scissor
.scissors
,
1200 cmd_buffer
->state
.dynamic
.viewport
.viewports
,
1201 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
);
1203 cmd_buffer
->state
.context_roll_without_scissor_emitted
= false;
1207 radv_emit_discard_rectangle(struct radv_cmd_buffer
*cmd_buffer
)
1209 if (!cmd_buffer
->state
.dynamic
.discard_rectangle
.count
)
1212 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028210_PA_SC_CLIPRECT_0_TL
,
1213 cmd_buffer
->state
.dynamic
.discard_rectangle
.count
* 2);
1214 for (unsigned i
= 0; i
< cmd_buffer
->state
.dynamic
.discard_rectangle
.count
; ++i
) {
1215 VkRect2D rect
= cmd_buffer
->state
.dynamic
.discard_rectangle
.rectangles
[i
];
1216 radeon_emit(cmd_buffer
->cs
, S_028210_TL_X(rect
.offset
.x
) | S_028210_TL_Y(rect
.offset
.y
));
1217 radeon_emit(cmd_buffer
->cs
, S_028214_BR_X(rect
.offset
.x
+ rect
.extent
.width
) |
1218 S_028214_BR_Y(rect
.offset
.y
+ rect
.extent
.height
));
1223 radv_emit_line_width(struct radv_cmd_buffer
*cmd_buffer
)
1225 unsigned width
= cmd_buffer
->state
.dynamic
.line_width
* 8;
1227 radeon_set_context_reg(cmd_buffer
->cs
, R_028A08_PA_SU_LINE_CNTL
,
1228 S_028A08_WIDTH(CLAMP(width
, 0, 0xFFF)));
1232 radv_emit_blend_constants(struct radv_cmd_buffer
*cmd_buffer
)
1234 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1236 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028414_CB_BLEND_RED
, 4);
1237 radeon_emit_array(cmd_buffer
->cs
, (uint32_t *)d
->blend_constants
, 4);
1241 radv_emit_stencil(struct radv_cmd_buffer
*cmd_buffer
)
1243 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1245 radeon_set_context_reg_seq(cmd_buffer
->cs
,
1246 R_028430_DB_STENCILREFMASK
, 2);
1247 radeon_emit(cmd_buffer
->cs
,
1248 S_028430_STENCILTESTVAL(d
->stencil_reference
.front
) |
1249 S_028430_STENCILMASK(d
->stencil_compare_mask
.front
) |
1250 S_028430_STENCILWRITEMASK(d
->stencil_write_mask
.front
) |
1251 S_028430_STENCILOPVAL(1));
1252 radeon_emit(cmd_buffer
->cs
,
1253 S_028434_STENCILTESTVAL_BF(d
->stencil_reference
.back
) |
1254 S_028434_STENCILMASK_BF(d
->stencil_compare_mask
.back
) |
1255 S_028434_STENCILWRITEMASK_BF(d
->stencil_write_mask
.back
) |
1256 S_028434_STENCILOPVAL_BF(1));
1260 radv_emit_depth_bounds(struct radv_cmd_buffer
*cmd_buffer
)
1262 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1264 radeon_set_context_reg(cmd_buffer
->cs
, R_028020_DB_DEPTH_BOUNDS_MIN
,
1265 fui(d
->depth_bounds
.min
));
1266 radeon_set_context_reg(cmd_buffer
->cs
, R_028024_DB_DEPTH_BOUNDS_MAX
,
1267 fui(d
->depth_bounds
.max
));
1271 radv_emit_depth_bias(struct radv_cmd_buffer
*cmd_buffer
)
1273 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1274 unsigned slope
= fui(d
->depth_bias
.slope
* 16.0f
);
1275 unsigned bias
= fui(d
->depth_bias
.bias
* cmd_buffer
->state
.offset_scale
);
1278 radeon_set_context_reg_seq(cmd_buffer
->cs
,
1279 R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, 5);
1280 radeon_emit(cmd_buffer
->cs
, fui(d
->depth_bias
.clamp
)); /* CLAMP */
1281 radeon_emit(cmd_buffer
->cs
, slope
); /* FRONT SCALE */
1282 radeon_emit(cmd_buffer
->cs
, bias
); /* FRONT OFFSET */
1283 radeon_emit(cmd_buffer
->cs
, slope
); /* BACK SCALE */
1284 radeon_emit(cmd_buffer
->cs
, bias
); /* BACK OFFSET */
1288 radv_emit_fb_color_state(struct radv_cmd_buffer
*cmd_buffer
,
1290 struct radv_color_buffer_info
*cb
,
1291 struct radv_image_view
*iview
,
1292 VkImageLayout layout
,
1293 bool in_render_loop
)
1295 bool is_vi
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX8
;
1296 uint32_t cb_color_info
= cb
->cb_color_info
;
1297 struct radv_image
*image
= iview
->image
;
1299 if (!radv_layout_dcc_compressed(cmd_buffer
->device
, image
, layout
, in_render_loop
,
1300 radv_image_queue_family_mask(image
,
1301 cmd_buffer
->queue_family_index
,
1302 cmd_buffer
->queue_family_index
))) {
1303 cb_color_info
&= C_028C70_DCC_ENABLE
;
1306 if (radv_image_is_tc_compat_cmask(image
) &&
1307 (radv_is_fmask_decompress_pipeline(cmd_buffer
) ||
1308 radv_is_dcc_decompress_pipeline(cmd_buffer
))) {
1309 /* If this bit is set, the FMASK decompression operation
1310 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1312 cb_color_info
&= C_028C70_FMASK_COMPRESS_1FRAG_ONLY
;
1315 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
1316 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1317 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1318 radeon_emit(cmd_buffer
->cs
, 0);
1319 radeon_emit(cmd_buffer
->cs
, 0);
1320 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1321 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1322 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1323 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1324 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1325 radeon_emit(cmd_buffer
->cs
, 0);
1326 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1327 radeon_emit(cmd_buffer
->cs
, 0);
1329 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, 1);
1330 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
);
1332 radeon_set_context_reg(cmd_buffer
->cs
, R_028E40_CB_COLOR0_BASE_EXT
+ index
* 4,
1333 cb
->cb_color_base
>> 32);
1334 radeon_set_context_reg(cmd_buffer
->cs
, R_028E60_CB_COLOR0_CMASK_BASE_EXT
+ index
* 4,
1335 cb
->cb_color_cmask
>> 32);
1336 radeon_set_context_reg(cmd_buffer
->cs
, R_028E80_CB_COLOR0_FMASK_BASE_EXT
+ index
* 4,
1337 cb
->cb_color_fmask
>> 32);
1338 radeon_set_context_reg(cmd_buffer
->cs
, R_028EA0_CB_COLOR0_DCC_BASE_EXT
+ index
* 4,
1339 cb
->cb_dcc_base
>> 32);
1340 radeon_set_context_reg(cmd_buffer
->cs
, R_028EC0_CB_COLOR0_ATTRIB2
+ index
* 4,
1341 cb
->cb_color_attrib2
);
1342 radeon_set_context_reg(cmd_buffer
->cs
, R_028EE0_CB_COLOR0_ATTRIB3
+ index
* 4,
1343 cb
->cb_color_attrib3
);
1344 } else if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
1345 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1346 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1347 radeon_emit(cmd_buffer
->cs
, S_028C64_BASE_256B(cb
->cb_color_base
>> 32));
1348 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib2
);
1349 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1350 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1351 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1352 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1353 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1354 radeon_emit(cmd_buffer
->cs
, S_028C80_BASE_256B(cb
->cb_color_cmask
>> 32));
1355 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1356 radeon_emit(cmd_buffer
->cs
, S_028C88_BASE_256B(cb
->cb_color_fmask
>> 32));
1358 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, 2);
1359 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
);
1360 radeon_emit(cmd_buffer
->cs
, S_028C98_BASE_256B(cb
->cb_dcc_base
>> 32));
1362 radeon_set_context_reg(cmd_buffer
->cs
, R_0287A0_CB_MRT0_EPITCH
+ index
* 4,
1365 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1366 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1367 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_pitch
);
1368 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_slice
);
1369 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1370 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1371 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1372 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1373 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1374 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask_slice
);
1375 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1376 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask_slice
);
1378 if (is_vi
) { /* DCC BASE */
1379 radeon_set_context_reg(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, cb
->cb_dcc_base
);
1383 if (radv_dcc_enabled(image
, iview
->base_mip
)) {
1384 /* Drawing with DCC enabled also compresses colorbuffers. */
1385 VkImageSubresourceRange range
= {
1386 .aspectMask
= iview
->aspect_mask
,
1387 .baseMipLevel
= iview
->base_mip
,
1388 .levelCount
= iview
->level_count
,
1389 .baseArrayLayer
= iview
->base_layer
,
1390 .layerCount
= iview
->layer_count
,
1393 radv_update_dcc_metadata(cmd_buffer
, image
, &range
, true);
1398 radv_update_zrange_precision(struct radv_cmd_buffer
*cmd_buffer
,
1399 struct radv_ds_buffer_info
*ds
,
1400 const struct radv_image_view
*iview
,
1401 VkImageLayout layout
,
1402 bool in_render_loop
, bool requires_cond_exec
)
1404 const struct radv_image
*image
= iview
->image
;
1405 uint32_t db_z_info
= ds
->db_z_info
;
1406 uint32_t db_z_info_reg
;
1408 if (!cmd_buffer
->device
->physical_device
->rad_info
.has_tc_compat_zrange_bug
||
1409 !radv_image_is_tc_compat_htile(image
))
1412 if (!radv_layout_has_htile(image
, layout
, in_render_loop
,
1413 radv_image_queue_family_mask(image
,
1414 cmd_buffer
->queue_family_index
,
1415 cmd_buffer
->queue_family_index
))) {
1416 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
1419 db_z_info
&= C_028040_ZRANGE_PRECISION
;
1421 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
1422 db_z_info_reg
= R_028038_DB_Z_INFO
;
1424 db_z_info_reg
= R_028040_DB_Z_INFO
;
1427 /* When we don't know the last fast clear value we need to emit a
1428 * conditional packet that will eventually skip the following
1429 * SET_CONTEXT_REG packet.
1431 if (requires_cond_exec
) {
1432 uint64_t va
= radv_get_tc_compat_zrange_va(image
, iview
->base_mip
);
1434 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_COND_EXEC
, 3, 0));
1435 radeon_emit(cmd_buffer
->cs
, va
);
1436 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1437 radeon_emit(cmd_buffer
->cs
, 0);
1438 radeon_emit(cmd_buffer
->cs
, 3); /* SET_CONTEXT_REG size */
1441 radeon_set_context_reg(cmd_buffer
->cs
, db_z_info_reg
, db_z_info
);
1445 radv_emit_fb_ds_state(struct radv_cmd_buffer
*cmd_buffer
,
1446 struct radv_ds_buffer_info
*ds
,
1447 struct radv_image_view
*iview
,
1448 VkImageLayout layout
,
1449 bool in_render_loop
)
1451 const struct radv_image
*image
= iview
->image
;
1452 uint32_t db_z_info
= ds
->db_z_info
;
1453 uint32_t db_stencil_info
= ds
->db_stencil_info
;
1455 if (!radv_layout_has_htile(image
, layout
, in_render_loop
,
1456 radv_image_queue_family_mask(image
,
1457 cmd_buffer
->queue_family_index
,
1458 cmd_buffer
->queue_family_index
))) {
1459 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
1460 db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
1463 radeon_set_context_reg(cmd_buffer
->cs
, R_028008_DB_DEPTH_VIEW
, ds
->db_depth_view
);
1464 radeon_set_context_reg(cmd_buffer
->cs
, R_028ABC_DB_HTILE_SURFACE
, ds
->db_htile_surface
);
1466 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
1467 radeon_set_context_reg(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, ds
->db_htile_data_base
);
1468 radeon_set_context_reg(cmd_buffer
->cs
, R_02801C_DB_DEPTH_SIZE_XY
, ds
->db_depth_size
);
1470 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_02803C_DB_DEPTH_INFO
, 7);
1471 radeon_emit(cmd_buffer
->cs
, S_02803C_RESOURCE_LEVEL(1));
1472 radeon_emit(cmd_buffer
->cs
, db_z_info
);
1473 radeon_emit(cmd_buffer
->cs
, db_stencil_info
);
1474 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
);
1475 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
);
1476 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
);
1477 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
);
1479 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028068_DB_Z_READ_BASE_HI
, 5);
1480 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
>> 32);
1481 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
>> 32);
1482 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
>> 32);
1483 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
>> 32);
1484 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
>> 32);
1485 } else if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
1486 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
1487 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
);
1488 radeon_emit(cmd_buffer
->cs
, S_028018_BASE_HI(ds
->db_htile_data_base
>> 32));
1489 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
);
1491 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 10);
1492 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* DB_Z_INFO */
1493 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* DB_STENCIL_INFO */
1494 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* DB_Z_READ_BASE */
1495 radeon_emit(cmd_buffer
->cs
, S_028044_BASE_HI(ds
->db_z_read_base
>> 32)); /* DB_Z_READ_BASE_HI */
1496 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* DB_STENCIL_READ_BASE */
1497 radeon_emit(cmd_buffer
->cs
, S_02804C_BASE_HI(ds
->db_stencil_read_base
>> 32)); /* DB_STENCIL_READ_BASE_HI */
1498 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* DB_Z_WRITE_BASE */
1499 radeon_emit(cmd_buffer
->cs
, S_028054_BASE_HI(ds
->db_z_write_base
>> 32)); /* DB_Z_WRITE_BASE_HI */
1500 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* DB_STENCIL_WRITE_BASE */
1501 radeon_emit(cmd_buffer
->cs
, S_02805C_BASE_HI(ds
->db_stencil_write_base
>> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1503 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028068_DB_Z_INFO2
, 2);
1504 radeon_emit(cmd_buffer
->cs
, ds
->db_z_info2
);
1505 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_info2
);
1507 radeon_set_context_reg(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, ds
->db_htile_data_base
);
1509 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_02803C_DB_DEPTH_INFO
, 9);
1510 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_info
); /* R_02803C_DB_DEPTH_INFO */
1511 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* R_028040_DB_Z_INFO */
1512 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* R_028044_DB_STENCIL_INFO */
1513 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* R_028048_DB_Z_READ_BASE */
1514 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* R_02804C_DB_STENCIL_READ_BASE */
1515 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* R_028050_DB_Z_WRITE_BASE */
1516 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* R_028054_DB_STENCIL_WRITE_BASE */
1517 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
); /* R_028058_DB_DEPTH_SIZE */
1518 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_slice
); /* R_02805C_DB_DEPTH_SLICE */
1522 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1523 radv_update_zrange_precision(cmd_buffer
, ds
, iview
, layout
,
1524 in_render_loop
, true);
1526 radeon_set_context_reg(cmd_buffer
->cs
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1527 ds
->pa_su_poly_offset_db_fmt_cntl
);
1531 * Update the fast clear depth/stencil values if the image is bound as a
1532 * depth/stencil buffer.
1535 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer
*cmd_buffer
,
1536 const struct radv_image_view
*iview
,
1537 VkClearDepthStencilValue ds_clear_value
,
1538 VkImageAspectFlags aspects
)
1540 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1541 const struct radv_image
*image
= iview
->image
;
1542 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1545 if (!cmd_buffer
->state
.attachments
|| !subpass
)
1548 if (!subpass
->depth_stencil_attachment
)
1551 att_idx
= subpass
->depth_stencil_attachment
->attachment
;
1552 if (cmd_buffer
->state
.attachments
[att_idx
].iview
->image
!= image
)
1555 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 2);
1556 radeon_emit(cs
, ds_clear_value
.stencil
);
1557 radeon_emit(cs
, fui(ds_clear_value
.depth
));
1559 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1560 * only needed when clearing Z to 0.0.
1562 if ((aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
1563 ds_clear_value
.depth
== 0.0) {
1564 VkImageLayout layout
= subpass
->depth_stencil_attachment
->layout
;
1565 bool in_render_loop
= subpass
->depth_stencil_attachment
->in_render_loop
;
1567 radv_update_zrange_precision(cmd_buffer
, &cmd_buffer
->state
.attachments
[att_idx
].ds
,
1568 iview
, layout
, in_render_loop
, false);
1571 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1575 * Set the clear depth/stencil values to the image's metadata.
1578 radv_set_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1579 struct radv_image
*image
,
1580 const VkImageSubresourceRange
*range
,
1581 VkClearDepthStencilValue ds_clear_value
,
1582 VkImageAspectFlags aspects
)
1584 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1585 uint64_t va
= radv_get_ds_clear_value_va(image
, range
->baseMipLevel
);
1586 uint32_t level_count
= radv_get_levelCount(image
, range
);
1588 if (aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
1589 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
1590 /* Use the fastest way when both aspects are used. */
1591 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + 2 * level_count
, cmd_buffer
->state
.predicating
));
1592 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
1593 S_370_WR_CONFIRM(1) |
1594 S_370_ENGINE_SEL(V_370_PFP
));
1595 radeon_emit(cs
, va
);
1596 radeon_emit(cs
, va
>> 32);
1598 for (uint32_t l
= 0; l
< level_count
; l
++) {
1599 radeon_emit(cs
, ds_clear_value
.stencil
);
1600 radeon_emit(cs
, fui(ds_clear_value
.depth
));
1603 /* Otherwise we need one WRITE_DATA packet per level. */
1604 for (uint32_t l
= 0; l
< level_count
; l
++) {
1605 uint64_t va
= radv_get_ds_clear_value_va(image
, range
->baseMipLevel
+ l
);
1608 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1609 value
= fui(ds_clear_value
.depth
);
1612 value
= ds_clear_value
.stencil
;
1615 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, cmd_buffer
->state
.predicating
));
1616 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
1617 S_370_WR_CONFIRM(1) |
1618 S_370_ENGINE_SEL(V_370_PFP
));
1619 radeon_emit(cs
, va
);
1620 radeon_emit(cs
, va
>> 32);
1621 radeon_emit(cs
, value
);
1627 * Update the TC-compat metadata value for this image.
1630 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1631 struct radv_image
*image
,
1632 const VkImageSubresourceRange
*range
,
1635 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1637 if (!cmd_buffer
->device
->physical_device
->rad_info
.has_tc_compat_zrange_bug
)
1640 uint64_t va
= radv_get_tc_compat_zrange_va(image
, range
->baseMipLevel
);
1641 uint32_t level_count
= radv_get_levelCount(image
, range
);
1643 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + level_count
, cmd_buffer
->state
.predicating
));
1644 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
1645 S_370_WR_CONFIRM(1) |
1646 S_370_ENGINE_SEL(V_370_PFP
));
1647 radeon_emit(cs
, va
);
1648 radeon_emit(cs
, va
>> 32);
1650 for (uint32_t l
= 0; l
< level_count
; l
++)
1651 radeon_emit(cs
, value
);
1655 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1656 const struct radv_image_view
*iview
,
1657 VkClearDepthStencilValue ds_clear_value
)
1659 VkImageSubresourceRange range
= {
1660 .aspectMask
= iview
->aspect_mask
,
1661 .baseMipLevel
= iview
->base_mip
,
1662 .levelCount
= iview
->level_count
,
1663 .baseArrayLayer
= iview
->base_layer
,
1664 .layerCount
= iview
->layer_count
,
1668 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1669 * depth clear value is 0.0f.
1671 cond_val
= ds_clear_value
.depth
== 0.0f
? UINT_MAX
: 0;
1673 radv_set_tc_compat_zrange_metadata(cmd_buffer
, iview
->image
, &range
,
1678 * Update the clear depth/stencil values for this image.
1681 radv_update_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1682 const struct radv_image_view
*iview
,
1683 VkClearDepthStencilValue ds_clear_value
,
1684 VkImageAspectFlags aspects
)
1686 VkImageSubresourceRange range
= {
1687 .aspectMask
= iview
->aspect_mask
,
1688 .baseMipLevel
= iview
->base_mip
,
1689 .levelCount
= iview
->level_count
,
1690 .baseArrayLayer
= iview
->base_layer
,
1691 .layerCount
= iview
->layer_count
,
1693 struct radv_image
*image
= iview
->image
;
1695 assert(radv_image_has_htile(image
));
1697 radv_set_ds_clear_metadata(cmd_buffer
, iview
->image
, &range
,
1698 ds_clear_value
, aspects
);
1700 if (radv_image_is_tc_compat_htile(image
) &&
1701 (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
1702 radv_update_tc_compat_zrange_metadata(cmd_buffer
, iview
,
1706 radv_update_bound_fast_clear_ds(cmd_buffer
, iview
, ds_clear_value
,
1711 * Load the clear depth/stencil values from the image's metadata.
1714 radv_load_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1715 const struct radv_image_view
*iview
)
1717 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1718 const struct radv_image
*image
= iview
->image
;
1719 VkImageAspectFlags aspects
= vk_format_aspects(image
->vk_format
);
1720 uint64_t va
= radv_get_ds_clear_value_va(image
, iview
->base_mip
);
1721 unsigned reg_offset
= 0, reg_count
= 0;
1723 if (!radv_image_has_htile(image
))
1726 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1732 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1735 uint32_t reg
= R_028028_DB_STENCIL_CLEAR
+ 4 * reg_offset
;
1737 if (cmd_buffer
->device
->physical_device
->rad_info
.has_load_ctx_reg_pkt
) {
1738 radeon_emit(cs
, PKT3(PKT3_LOAD_CONTEXT_REG
, 3, 0));
1739 radeon_emit(cs
, va
);
1740 radeon_emit(cs
, va
>> 32);
1741 radeon_emit(cs
, (reg
- SI_CONTEXT_REG_OFFSET
) >> 2);
1742 radeon_emit(cs
, reg_count
);
1744 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
1745 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
1746 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1747 (reg_count
== 2 ? COPY_DATA_COUNT_SEL
: 0));
1748 radeon_emit(cs
, va
);
1749 radeon_emit(cs
, va
>> 32);
1750 radeon_emit(cs
, reg
>> 2);
1753 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
1759 * With DCC some colors don't require CMASK elimination before being
1760 * used as a texture. This sets a predicate value to determine if the
1761 * cmask eliminate is required.
1764 radv_update_fce_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1765 struct radv_image
*image
,
1766 const VkImageSubresourceRange
*range
, bool value
)
1768 uint64_t pred_val
= value
;
1769 uint64_t va
= radv_image_get_fce_pred_va(image
, range
->baseMipLevel
);
1770 uint32_t level_count
= radv_get_levelCount(image
, range
);
1771 uint32_t count
= 2 * level_count
;
1773 assert(radv_dcc_enabled(image
, range
->baseMipLevel
));
1775 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, 0));
1776 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM
) |
1777 S_370_WR_CONFIRM(1) |
1778 S_370_ENGINE_SEL(V_370_PFP
));
1779 radeon_emit(cmd_buffer
->cs
, va
);
1780 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1782 for (uint32_t l
= 0; l
< level_count
; l
++) {
1783 radeon_emit(cmd_buffer
->cs
, pred_val
);
1784 radeon_emit(cmd_buffer
->cs
, pred_val
>> 32);
1789 * Update the DCC predicate to reflect the compression state.
1792 radv_update_dcc_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1793 struct radv_image
*image
,
1794 const VkImageSubresourceRange
*range
, bool value
)
1796 uint64_t pred_val
= value
;
1797 uint64_t va
= radv_image_get_dcc_pred_va(image
, range
->baseMipLevel
);
1798 uint32_t level_count
= radv_get_levelCount(image
, range
);
1799 uint32_t count
= 2 * level_count
;
1801 assert(radv_dcc_enabled(image
, range
->baseMipLevel
));
1803 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, 0));
1804 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM
) |
1805 S_370_WR_CONFIRM(1) |
1806 S_370_ENGINE_SEL(V_370_PFP
));
1807 radeon_emit(cmd_buffer
->cs
, va
);
1808 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1810 for (uint32_t l
= 0; l
< level_count
; l
++) {
1811 radeon_emit(cmd_buffer
->cs
, pred_val
);
1812 radeon_emit(cmd_buffer
->cs
, pred_val
>> 32);
1817 * Update the fast clear color values if the image is bound as a color buffer.
1820 radv_update_bound_fast_clear_color(struct radv_cmd_buffer
*cmd_buffer
,
1821 struct radv_image
*image
,
1823 uint32_t color_values
[2])
1825 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1826 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1829 if (!cmd_buffer
->state
.attachments
|| !subpass
)
1832 att_idx
= subpass
->color_attachments
[cb_idx
].attachment
;
1833 if (att_idx
== VK_ATTACHMENT_UNUSED
)
1836 if (cmd_buffer
->state
.attachments
[att_idx
].iview
->image
!= image
)
1839 radeon_set_context_reg_seq(cs
, R_028C8C_CB_COLOR0_CLEAR_WORD0
+ cb_idx
* 0x3c, 2);
1840 radeon_emit(cs
, color_values
[0]);
1841 radeon_emit(cs
, color_values
[1]);
1843 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1847 * Set the clear color values to the image's metadata.
1850 radv_set_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1851 struct radv_image
*image
,
1852 const VkImageSubresourceRange
*range
,
1853 uint32_t color_values
[2])
1855 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1856 uint64_t va
= radv_image_get_fast_clear_va(image
, range
->baseMipLevel
);
1857 uint32_t level_count
= radv_get_levelCount(image
, range
);
1858 uint32_t count
= 2 * level_count
;
1860 assert(radv_image_has_cmask(image
) ||
1861 radv_dcc_enabled(image
, range
->baseMipLevel
));
1863 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, cmd_buffer
->state
.predicating
));
1864 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
1865 S_370_WR_CONFIRM(1) |
1866 S_370_ENGINE_SEL(V_370_PFP
));
1867 radeon_emit(cs
, va
);
1868 radeon_emit(cs
, va
>> 32);
1870 for (uint32_t l
= 0; l
< level_count
; l
++) {
1871 radeon_emit(cs
, color_values
[0]);
1872 radeon_emit(cs
, color_values
[1]);
1877 * Update the clear color values for this image.
1880 radv_update_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1881 const struct radv_image_view
*iview
,
1883 uint32_t color_values
[2])
1885 struct radv_image
*image
= iview
->image
;
1886 VkImageSubresourceRange range
= {
1887 .aspectMask
= iview
->aspect_mask
,
1888 .baseMipLevel
= iview
->base_mip
,
1889 .levelCount
= iview
->level_count
,
1890 .baseArrayLayer
= iview
->base_layer
,
1891 .layerCount
= iview
->layer_count
,
1894 assert(radv_image_has_cmask(image
) ||
1895 radv_dcc_enabled(image
, iview
->base_mip
));
1897 radv_set_color_clear_metadata(cmd_buffer
, image
, &range
, color_values
);
1899 radv_update_bound_fast_clear_color(cmd_buffer
, image
, cb_idx
,
1904 * Load the clear color values from the image's metadata.
1907 radv_load_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1908 struct radv_image_view
*iview
,
1911 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1912 struct radv_image
*image
= iview
->image
;
1913 uint64_t va
= radv_image_get_fast_clear_va(image
, iview
->base_mip
);
1915 if (!radv_image_has_cmask(image
) &&
1916 !radv_dcc_enabled(image
, iview
->base_mip
))
1919 uint32_t reg
= R_028C8C_CB_COLOR0_CLEAR_WORD0
+ cb_idx
* 0x3c;
1921 if (cmd_buffer
->device
->physical_device
->rad_info
.has_load_ctx_reg_pkt
) {
1922 radeon_emit(cs
, PKT3(PKT3_LOAD_CONTEXT_REG
, 3, cmd_buffer
->state
.predicating
));
1923 radeon_emit(cs
, va
);
1924 radeon_emit(cs
, va
>> 32);
1925 radeon_emit(cs
, (reg
- SI_CONTEXT_REG_OFFSET
) >> 2);
1928 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, cmd_buffer
->state
.predicating
));
1929 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
1930 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1931 COPY_DATA_COUNT_SEL
);
1932 radeon_emit(cs
, va
);
1933 radeon_emit(cs
, va
>> 32);
1934 radeon_emit(cs
, reg
>> 2);
1937 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, cmd_buffer
->state
.predicating
));
1943 radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer
)
1946 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1947 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1949 /* this may happen for inherited secondary recording */
1953 for (i
= 0; i
< 8; ++i
) {
1954 if (i
>= subpass
->color_count
|| subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
1955 radeon_set_context_reg(cmd_buffer
->cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
1956 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
1960 int idx
= subpass
->color_attachments
[i
].attachment
;
1961 struct radv_image_view
*iview
= cmd_buffer
->state
.attachments
[idx
].iview
;
1962 VkImageLayout layout
= subpass
->color_attachments
[i
].layout
;
1963 bool in_render_loop
= subpass
->color_attachments
[i
].in_render_loop
;
1965 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, iview
->bo
);
1967 assert(iview
->aspect_mask
& (VK_IMAGE_ASPECT_COLOR_BIT
| VK_IMAGE_ASPECT_PLANE_0_BIT
|
1968 VK_IMAGE_ASPECT_PLANE_1_BIT
| VK_IMAGE_ASPECT_PLANE_2_BIT
));
1969 radv_emit_fb_color_state(cmd_buffer
, i
, &cmd_buffer
->state
.attachments
[idx
].cb
, iview
, layout
, in_render_loop
);
1971 radv_load_color_clear_metadata(cmd_buffer
, iview
, i
);
1974 if (subpass
->depth_stencil_attachment
) {
1975 int idx
= subpass
->depth_stencil_attachment
->attachment
;
1976 VkImageLayout layout
= subpass
->depth_stencil_attachment
->layout
;
1977 bool in_render_loop
= subpass
->depth_stencil_attachment
->in_render_loop
;
1978 struct radv_image_view
*iview
= cmd_buffer
->state
.attachments
[idx
].iview
;
1979 struct radv_image
*image
= iview
->image
;
1980 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, cmd_buffer
->state
.attachments
[idx
].iview
->bo
);
1981 ASSERTED
uint32_t queue_mask
= radv_image_queue_family_mask(image
,
1982 cmd_buffer
->queue_family_index
,
1983 cmd_buffer
->queue_family_index
);
1984 /* We currently don't support writing decompressed HTILE */
1985 assert(radv_layout_has_htile(image
, layout
, in_render_loop
, queue_mask
) ==
1986 radv_layout_is_htile_compressed(image
, layout
, in_render_loop
, queue_mask
));
1988 radv_emit_fb_ds_state(cmd_buffer
, &cmd_buffer
->state
.attachments
[idx
].ds
, iview
, layout
, in_render_loop
);
1990 if (cmd_buffer
->state
.attachments
[idx
].ds
.offset_scale
!= cmd_buffer
->state
.offset_scale
) {
1991 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
1992 cmd_buffer
->state
.offset_scale
= cmd_buffer
->state
.attachments
[idx
].ds
.offset_scale
;
1994 radv_load_ds_clear_metadata(cmd_buffer
, iview
);
1996 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
)
1997 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 2);
1999 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028040_DB_Z_INFO
, 2);
2001 radeon_emit(cmd_buffer
->cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
2002 radeon_emit(cmd_buffer
->cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
2004 radeon_set_context_reg(cmd_buffer
->cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
2005 S_028208_BR_X(framebuffer
->width
) |
2006 S_028208_BR_Y(framebuffer
->height
));
2008 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX8
) {
2009 bool disable_constant_encode
=
2010 cmd_buffer
->device
->physical_device
->rad_info
.has_dcc_constant_encode
;
2011 enum chip_class chip_class
=
2012 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
;
2013 uint8_t watermark
= chip_class
>= GFX10
? 6 : 4;
2015 radeon_set_context_reg(cmd_buffer
->cs
, R_028424_CB_DCC_CONTROL
,
2016 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class
<= GFX9
) |
2017 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark
) |
2018 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode
));
2021 if (cmd_buffer
->device
->pbb_allowed
) {
2022 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2023 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
2026 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_FRAMEBUFFER
;
2030 radv_emit_index_buffer(struct radv_cmd_buffer
*cmd_buffer
)
2032 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
2033 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2035 if (state
->index_type
!= state
->last_index_type
) {
2036 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2037 radeon_set_uconfig_reg_idx(cmd_buffer
->device
->physical_device
,
2038 cs
, R_03090C_VGT_INDEX_TYPE
,
2039 2, state
->index_type
);
2041 radeon_emit(cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
2042 radeon_emit(cs
, state
->index_type
);
2045 state
->last_index_type
= state
->index_type
;
2048 radeon_emit(cs
, PKT3(PKT3_INDEX_BASE
, 1, 0));
2049 radeon_emit(cs
, state
->index_va
);
2050 radeon_emit(cs
, state
->index_va
>> 32);
2052 radeon_emit(cs
, PKT3(PKT3_INDEX_BUFFER_SIZE
, 0, 0));
2053 radeon_emit(cs
, state
->max_index_count
);
2055 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_INDEX_BUFFER
;
2058 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
)
2060 bool has_perfect_queries
= cmd_buffer
->state
.perfect_occlusion_queries_enabled
;
2061 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
2062 uint32_t pa_sc_mode_cntl_1
=
2063 pipeline
? pipeline
->graphics
.ms
.pa_sc_mode_cntl_1
: 0;
2064 uint32_t db_count_control
;
2066 if(!cmd_buffer
->state
.active_occlusion_queries
) {
2067 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2068 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1
) &&
2069 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
&&
2070 has_perfect_queries
) {
2071 /* Re-enable out-of-order rasterization if the
2072 * bound pipeline supports it and if it's has
2073 * been disabled before starting any perfect
2074 * occlusion queries.
2076 radeon_set_context_reg(cmd_buffer
->cs
,
2077 R_028A4C_PA_SC_MODE_CNTL_1
,
2081 db_count_control
= S_028004_ZPASS_INCREMENT_DISABLE(1);
2083 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
2084 uint32_t sample_rate
= subpass
? util_logbase2(subpass
->max_sample_count
) : 0;
2085 bool gfx10_perfect
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&& has_perfect_queries
;
2087 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2089 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries
) |
2090 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect
) |
2091 S_028004_SAMPLE_RATE(sample_rate
) |
2092 S_028004_ZPASS_ENABLE(1) |
2093 S_028004_SLICE_EVEN_ENABLE(1) |
2094 S_028004_SLICE_ODD_ENABLE(1);
2096 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1
) &&
2097 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
&&
2098 has_perfect_queries
) {
2099 /* If the bound pipeline has enabled
2100 * out-of-order rasterization, we should
2101 * disable it before starting any perfect
2102 * occlusion queries.
2104 pa_sc_mode_cntl_1
&= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE
;
2106 radeon_set_context_reg(cmd_buffer
->cs
,
2107 R_028A4C_PA_SC_MODE_CNTL_1
,
2111 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(1) |
2112 S_028004_SAMPLE_RATE(sample_rate
);
2116 radeon_set_context_reg(cmd_buffer
->cs
, R_028004_DB_COUNT_CONTROL
, db_count_control
);
2118 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
2122 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
)
2124 uint32_t states
= cmd_buffer
->state
.dirty
& cmd_buffer
->state
.emitted_pipeline
->graphics
.needed_dynamic_state
;
2126 if (states
& (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
))
2127 radv_emit_viewport(cmd_buffer
);
2129 if (states
& (RADV_CMD_DIRTY_DYNAMIC_SCISSOR
| RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
) &&
2130 !cmd_buffer
->device
->physical_device
->rad_info
.has_gfx9_scissor_bug
)
2131 radv_emit_scissor(cmd_buffer
);
2133 if (states
& RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
)
2134 radv_emit_line_width(cmd_buffer
);
2136 if (states
& RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
)
2137 radv_emit_blend_constants(cmd_buffer
);
2139 if (states
& (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
|
2140 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
|
2141 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
))
2142 radv_emit_stencil(cmd_buffer
);
2144 if (states
& RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
)
2145 radv_emit_depth_bounds(cmd_buffer
);
2147 if (states
& RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
)
2148 radv_emit_depth_bias(cmd_buffer
);
2150 if (states
& RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
)
2151 radv_emit_discard_rectangle(cmd_buffer
);
2153 if (states
& RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS
)
2154 radv_emit_sample_locations(cmd_buffer
);
2156 cmd_buffer
->state
.dirty
&= ~states
;
2160 radv_flush_push_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
2161 VkPipelineBindPoint bind_point
)
2163 struct radv_descriptor_state
*descriptors_state
=
2164 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2165 struct radv_descriptor_set
*set
= &descriptors_state
->push_set
.set
;
2168 if (!radv_cmd_buffer_upload_data(cmd_buffer
, set
->size
, 32,
2173 set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2174 set
->va
+= bo_offset
;
2178 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer
*cmd_buffer
,
2179 VkPipelineBindPoint bind_point
)
2181 struct radv_descriptor_state
*descriptors_state
=
2182 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2183 uint32_t size
= MAX_SETS
* 4;
2187 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
,
2188 256, &offset
, &ptr
))
2191 for (unsigned i
= 0; i
< MAX_SETS
; i
++) {
2192 uint32_t *uptr
= ((uint32_t *)ptr
) + i
;
2193 uint64_t set_va
= 0;
2194 struct radv_descriptor_set
*set
= descriptors_state
->sets
[i
];
2195 if (descriptors_state
->valid
& (1u << i
))
2197 uptr
[0] = set_va
& 0xffffffff;
2200 uint64_t va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2203 if (cmd_buffer
->state
.pipeline
) {
2204 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_VERTEX
])
2205 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
2206 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2208 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_FRAGMENT
])
2209 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_FRAGMENT
,
2210 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2212 if (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
))
2213 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
2214 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2216 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
2217 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_CTRL
,
2218 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2220 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
2221 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_EVAL
,
2222 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2225 if (cmd_buffer
->state
.compute_pipeline
)
2226 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
, MESA_SHADER_COMPUTE
,
2227 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2231 radv_flush_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
2232 VkShaderStageFlags stages
)
2234 VkPipelineBindPoint bind_point
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
?
2235 VK_PIPELINE_BIND_POINT_COMPUTE
:
2236 VK_PIPELINE_BIND_POINT_GRAPHICS
;
2237 struct radv_descriptor_state
*descriptors_state
=
2238 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2239 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2240 bool flush_indirect_descriptors
;
2242 if (!descriptors_state
->dirty
)
2245 if (descriptors_state
->push_dirty
)
2246 radv_flush_push_descriptors(cmd_buffer
, bind_point
);
2248 flush_indirect_descriptors
=
2249 (bind_point
== VK_PIPELINE_BIND_POINT_GRAPHICS
&&
2250 state
->pipeline
&& state
->pipeline
->need_indirect_descriptor_sets
) ||
2251 (bind_point
== VK_PIPELINE_BIND_POINT_COMPUTE
&&
2252 state
->compute_pipeline
&& state
->compute_pipeline
->need_indirect_descriptor_sets
);
2254 if (flush_indirect_descriptors
)
2255 radv_flush_indirect_descriptor_sets(cmd_buffer
, bind_point
);
2257 ASSERTED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
2259 MAX_SETS
* MESA_SHADER_STAGES
* 4);
2261 if (cmd_buffer
->state
.pipeline
) {
2262 radv_foreach_stage(stage
, stages
) {
2263 if (!cmd_buffer
->state
.pipeline
->shaders
[stage
])
2266 radv_emit_descriptor_pointers(cmd_buffer
,
2267 cmd_buffer
->state
.pipeline
,
2268 descriptors_state
, stage
);
2272 if (cmd_buffer
->state
.compute_pipeline
&&
2273 (stages
& VK_SHADER_STAGE_COMPUTE_BIT
)) {
2274 radv_emit_descriptor_pointers(cmd_buffer
,
2275 cmd_buffer
->state
.compute_pipeline
,
2277 MESA_SHADER_COMPUTE
);
2280 descriptors_state
->dirty
= 0;
2281 descriptors_state
->push_dirty
= false;
2283 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2285 if (unlikely(cmd_buffer
->device
->trace_bo
))
2286 radv_save_descriptors(cmd_buffer
, bind_point
);
2290 radv_flush_constants(struct radv_cmd_buffer
*cmd_buffer
,
2291 VkShaderStageFlags stages
)
2293 struct radv_pipeline
*pipeline
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
2294 ? cmd_buffer
->state
.compute_pipeline
2295 : cmd_buffer
->state
.pipeline
;
2296 VkPipelineBindPoint bind_point
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
?
2297 VK_PIPELINE_BIND_POINT_COMPUTE
:
2298 VK_PIPELINE_BIND_POINT_GRAPHICS
;
2299 struct radv_descriptor_state
*descriptors_state
=
2300 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2301 struct radv_pipeline_layout
*layout
= pipeline
->layout
;
2302 struct radv_shader_variant
*shader
, *prev_shader
;
2303 bool need_push_constants
= false;
2308 stages
&= cmd_buffer
->push_constant_stages
;
2310 (!layout
->push_constant_size
&& !layout
->dynamic_offset_count
))
2313 radv_foreach_stage(stage
, stages
) {
2314 if (!pipeline
->shaders
[stage
])
2317 need_push_constants
|= pipeline
->shaders
[stage
]->info
.loads_push_constants
;
2318 need_push_constants
|= pipeline
->shaders
[stage
]->info
.loads_dynamic_offsets
;
2320 uint8_t base
= pipeline
->shaders
[stage
]->info
.base_inline_push_consts
;
2321 uint8_t count
= pipeline
->shaders
[stage
]->info
.num_inline_push_consts
;
2323 radv_emit_inline_push_consts(cmd_buffer
, pipeline
, stage
,
2324 AC_UD_INLINE_PUSH_CONSTANTS
,
2326 (uint32_t *)&cmd_buffer
->push_constants
[base
* 4]);
2329 if (need_push_constants
) {
2330 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, layout
->push_constant_size
+
2331 16 * layout
->dynamic_offset_count
,
2332 256, &offset
, &ptr
))
2335 memcpy(ptr
, cmd_buffer
->push_constants
, layout
->push_constant_size
);
2336 memcpy((char*)ptr
+ layout
->push_constant_size
,
2337 descriptors_state
->dynamic_buffers
,
2338 16 * layout
->dynamic_offset_count
);
2340 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2343 ASSERTED
unsigned cdw_max
=
2344 radeon_check_space(cmd_buffer
->device
->ws
,
2345 cmd_buffer
->cs
, MESA_SHADER_STAGES
* 4);
2348 radv_foreach_stage(stage
, stages
) {
2349 shader
= radv_get_shader(pipeline
, stage
);
2351 /* Avoid redundantly emitting the address for merged stages. */
2352 if (shader
&& shader
!= prev_shader
) {
2353 radv_emit_userdata_address(cmd_buffer
, pipeline
, stage
,
2354 AC_UD_PUSH_CONSTANTS
, va
);
2356 prev_shader
= shader
;
2359 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2362 cmd_buffer
->push_constant_stages
&= ~stages
;
2366 radv_flush_vertex_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
2367 bool pipeline_is_dirty
)
2369 if ((pipeline_is_dirty
||
2370 (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_VERTEX_BUFFER
)) &&
2371 cmd_buffer
->state
.pipeline
->num_vertex_bindings
&&
2372 radv_get_shader(cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
)->info
.vs
.has_vertex_buffers
) {
2373 struct radv_vertex_elements_info
*velems
= &cmd_buffer
->state
.pipeline
->vertex_elements
;
2377 uint32_t count
= cmd_buffer
->state
.pipeline
->num_vertex_bindings
;
2380 /* allocate some descriptor state for vertex buffers */
2381 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, count
* 16, 256,
2382 &vb_offset
, &vb_ptr
))
2385 for (i
= 0; i
< count
; i
++) {
2386 uint32_t *desc
= &((uint32_t *)vb_ptr
)[i
* 4];
2388 struct radv_buffer
*buffer
= cmd_buffer
->vertex_bindings
[i
].buffer
;
2389 uint32_t stride
= cmd_buffer
->state
.pipeline
->binding_stride
[i
];
2394 va
= radv_buffer_get_va(buffer
->bo
);
2396 offset
= cmd_buffer
->vertex_bindings
[i
].offset
;
2397 va
+= offset
+ buffer
->offset
;
2399 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) | S_008F04_STRIDE(stride
);
2400 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
<= GFX7
&& stride
)
2401 desc
[2] = (buffer
->size
- offset
- velems
->format_size
[i
]) / stride
+ 1;
2403 desc
[2] = buffer
->size
- offset
;
2404 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2405 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2406 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2407 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
2409 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2410 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT
) |
2411 S_008F0C_OOB_SELECT(1) |
2412 S_008F0C_RESOURCE_LEVEL(1);
2414 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT
) |
2415 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2419 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2422 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
2423 AC_UD_VS_VERTEX_BUFFERS
, va
);
2425 cmd_buffer
->state
.vb_va
= va
;
2426 cmd_buffer
->state
.vb_size
= count
* 16;
2427 cmd_buffer
->state
.prefetch_L2_mask
|= RADV_PREFETCH_VBO_DESCRIPTORS
;
2429 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_VERTEX_BUFFER
;
2433 radv_emit_streamout_buffers(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
)
2435 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
2436 struct radv_userdata_info
*loc
;
2439 for (unsigned stage
= 0; stage
< MESA_SHADER_STAGES
; ++stage
) {
2440 if (!radv_get_shader(pipeline
, stage
))
2443 loc
= radv_lookup_user_sgpr(pipeline
, stage
,
2444 AC_UD_STREAMOUT_BUFFERS
);
2445 if (loc
->sgpr_idx
== -1)
2448 base_reg
= pipeline
->user_data_0
[stage
];
2450 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
2451 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
2454 if (radv_pipeline_has_gs_copy_shader(pipeline
)) {
2455 loc
= &pipeline
->gs_copy_shader
->info
.user_sgprs_locs
.shader_data
[AC_UD_STREAMOUT_BUFFERS
];
2456 if (loc
->sgpr_idx
!= -1) {
2457 base_reg
= R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2459 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
2460 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
2466 radv_flush_streamout_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
2468 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_STREAMOUT_BUFFER
) {
2469 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
2470 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
2475 /* Allocate some descriptor state for streamout buffers. */
2476 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
,
2477 MAX_SO_BUFFERS
* 16, 256,
2478 &so_offset
, &so_ptr
))
2481 for (uint32_t i
= 0; i
< MAX_SO_BUFFERS
; i
++) {
2482 struct radv_buffer
*buffer
= sb
[i
].buffer
;
2483 uint32_t *desc
= &((uint32_t *)so_ptr
)[i
* 4];
2485 if (!(so
->enabled_mask
& (1 << i
)))
2488 va
= radv_buffer_get_va(buffer
->bo
) + buffer
->offset
;
2492 /* Set the descriptor.
2494 * On GFX8, the format must be non-INVALID, otherwise
2495 * the buffer will be considered not bound and store
2496 * instructions will be no-ops.
2498 uint32_t size
= 0xffffffff;
2500 /* Compute the correct buffer size for NGG streamout
2501 * because it's used to determine the max emit per
2504 if (cmd_buffer
->device
->physical_device
->use_ngg_streamout
)
2505 size
= buffer
->size
- sb
[i
].offset
;
2508 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
2510 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2511 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2512 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2513 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
2515 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2516 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2517 S_008F0C_OOB_SELECT(3) |
2518 S_008F0C_RESOURCE_LEVEL(1);
2520 desc
[3] |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2524 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2527 radv_emit_streamout_buffers(cmd_buffer
, va
);
2530 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER
;
2534 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer
*cmd_buffer
, bool pipeline_is_dirty
)
2536 radv_flush_vertex_descriptors(cmd_buffer
, pipeline_is_dirty
);
2537 radv_flush_streamout_descriptors(cmd_buffer
);
2538 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
2539 radv_flush_constants(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
2542 struct radv_draw_info
{
2544 * Number of vertices.
2549 * Index of the first vertex.
2551 int32_t vertex_offset
;
2554 * First instance id.
2556 uint32_t first_instance
;
2559 * Number of instances.
2561 uint32_t instance_count
;
2564 * First index (indexed draws only).
2566 uint32_t first_index
;
2569 * Whether it's an indexed draw.
2574 * Indirect draw parameters resource.
2576 struct radv_buffer
*indirect
;
2577 uint64_t indirect_offset
;
2581 * Draw count parameters resource.
2583 struct radv_buffer
*count_buffer
;
2584 uint64_t count_buffer_offset
;
2587 * Stream output parameters resource.
2589 struct radv_buffer
*strmout_buffer
;
2590 uint64_t strmout_buffer_offset
;
2594 radv_get_primitive_reset_index(struct radv_cmd_buffer
*cmd_buffer
)
2596 switch (cmd_buffer
->state
.index_type
) {
2597 case V_028A7C_VGT_INDEX_8
:
2599 case V_028A7C_VGT_INDEX_16
:
2601 case V_028A7C_VGT_INDEX_32
:
2604 unreachable("invalid index type");
2609 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
2610 bool instanced_draw
, bool indirect_draw
,
2611 bool count_from_stream_output
,
2612 uint32_t draw_vertex_count
)
2614 struct radeon_info
*info
= &cmd_buffer
->device
->physical_device
->rad_info
;
2615 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2616 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
2617 unsigned ia_multi_vgt_param
;
2619 ia_multi_vgt_param
=
2620 si_get_ia_multi_vgt_param(cmd_buffer
, instanced_draw
,
2622 count_from_stream_output
,
2625 if (state
->last_ia_multi_vgt_param
!= ia_multi_vgt_param
) {
2626 if (info
->chip_class
== GFX9
) {
2627 radeon_set_uconfig_reg_idx(cmd_buffer
->device
->physical_device
,
2629 R_030960_IA_MULTI_VGT_PARAM
,
2630 4, ia_multi_vgt_param
);
2631 } else if (info
->chip_class
>= GFX7
) {
2632 radeon_set_context_reg_idx(cs
,
2633 R_028AA8_IA_MULTI_VGT_PARAM
,
2634 1, ia_multi_vgt_param
);
2636 radeon_set_context_reg(cs
, R_028AA8_IA_MULTI_VGT_PARAM
,
2637 ia_multi_vgt_param
);
2639 state
->last_ia_multi_vgt_param
= ia_multi_vgt_param
;
2644 radv_emit_draw_registers(struct radv_cmd_buffer
*cmd_buffer
,
2645 const struct radv_draw_info
*draw_info
)
2647 struct radeon_info
*info
= &cmd_buffer
->device
->physical_device
->rad_info
;
2648 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2649 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
2650 int32_t primitive_reset_en
;
2653 if (info
->chip_class
< GFX10
) {
2654 si_emit_ia_multi_vgt_param(cmd_buffer
, draw_info
->instance_count
> 1,
2655 draw_info
->indirect
,
2656 !!draw_info
->strmout_buffer
,
2657 draw_info
->indirect
? 0 : draw_info
->count
);
2660 /* Primitive restart. */
2661 primitive_reset_en
=
2662 draw_info
->indexed
&& state
->pipeline
->graphics
.prim_restart_enable
;
2664 if (primitive_reset_en
!= state
->last_primitive_reset_en
) {
2665 state
->last_primitive_reset_en
= primitive_reset_en
;
2666 if (info
->chip_class
>= GFX9
) {
2667 radeon_set_uconfig_reg(cs
,
2668 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN
,
2669 primitive_reset_en
);
2671 radeon_set_context_reg(cs
,
2672 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
,
2673 primitive_reset_en
);
2677 if (primitive_reset_en
) {
2678 uint32_t primitive_reset_index
=
2679 radv_get_primitive_reset_index(cmd_buffer
);
2681 if (primitive_reset_index
!= state
->last_primitive_reset_index
) {
2682 radeon_set_context_reg(cs
,
2683 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
,
2684 primitive_reset_index
);
2685 state
->last_primitive_reset_index
= primitive_reset_index
;
2689 if (draw_info
->strmout_buffer
) {
2690 uint64_t va
= radv_buffer_get_va(draw_info
->strmout_buffer
->bo
);
2692 va
+= draw_info
->strmout_buffer
->offset
+
2693 draw_info
->strmout_buffer_offset
;
2695 radeon_set_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
,
2698 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
2699 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
2700 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
2701 COPY_DATA_WR_CONFIRM
);
2702 radeon_emit(cs
, va
);
2703 radeon_emit(cs
, va
>> 32);
2704 radeon_emit(cs
, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2);
2705 radeon_emit(cs
, 0); /* unused */
2707 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, draw_info
->strmout_buffer
->bo
);
2711 static void radv_stage_flush(struct radv_cmd_buffer
*cmd_buffer
,
2712 VkPipelineStageFlags src_stage_mask
)
2714 if (src_stage_mask
& (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT
|
2715 VK_PIPELINE_STAGE_TRANSFER_BIT
|
2716 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
2717 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
2718 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
;
2721 if (src_stage_mask
& (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT
|
2722 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT
|
2723 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT
|
2724 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
|
2725 VK_PIPELINE_STAGE_TRANSFER_BIT
|
2726 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
2727 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT
|
2728 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
2729 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
;
2730 } else if (src_stage_mask
& (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
2731 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
|
2732 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT
|
2733 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT
|
2734 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT
|
2735 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT
|
2736 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT
)) {
2737 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VS_PARTIAL_FLUSH
;
2741 static enum radv_cmd_flush_bits
2742 radv_src_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
2743 VkAccessFlags src_flags
,
2744 struct radv_image
*image
)
2746 bool flush_CB_meta
= true, flush_DB_meta
= true;
2747 enum radv_cmd_flush_bits flush_bits
= 0;
2751 if (!radv_image_has_CB_metadata(image
))
2752 flush_CB_meta
= false;
2753 if (!radv_image_has_htile(image
))
2754 flush_DB_meta
= false;
2757 for_each_bit(b
, src_flags
) {
2758 switch ((VkAccessFlagBits
)(1 << b
)) {
2759 case VK_ACCESS_SHADER_WRITE_BIT
:
2760 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT
:
2761 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT
:
2762 flush_bits
|= RADV_CMD_FLAG_WB_L2
;
2764 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
2765 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
;
2767 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2769 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
2770 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
;
2772 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2774 case VK_ACCESS_TRANSFER_WRITE_BIT
:
2775 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
2776 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
2777 RADV_CMD_FLAG_INV_L2
;
2780 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2782 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2791 static enum radv_cmd_flush_bits
2792 radv_dst_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
2793 VkAccessFlags dst_flags
,
2794 struct radv_image
*image
)
2796 bool flush_CB_meta
= true, flush_DB_meta
= true;
2797 enum radv_cmd_flush_bits flush_bits
= 0;
2798 bool flush_CB
= true, flush_DB
= true;
2799 bool image_is_coherent
= false;
2803 if (!(image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
)) {
2808 if (!radv_image_has_CB_metadata(image
))
2809 flush_CB_meta
= false;
2810 if (!radv_image_has_htile(image
))
2811 flush_DB_meta
= false;
2813 /* TODO: implement shader coherent for GFX10 */
2815 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
2816 if (image
->info
.samples
== 1 &&
2817 (image
->usage
& (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
|
2818 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
)) &&
2819 !vk_format_is_stencil(image
->vk_format
)) {
2820 /* Single-sample color and single-sample depth
2821 * (not stencil) are coherent with shaders on
2824 image_is_coherent
= true;
2829 for_each_bit(b
, dst_flags
) {
2830 switch ((VkAccessFlagBits
)(1 << b
)) {
2831 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
2832 case VK_ACCESS_INDEX_READ_BIT
:
2833 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT
:
2835 case VK_ACCESS_UNIFORM_READ_BIT
:
2836 flush_bits
|= RADV_CMD_FLAG_INV_VCACHE
| RADV_CMD_FLAG_INV_SCACHE
;
2838 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
2839 case VK_ACCESS_TRANSFER_READ_BIT
:
2840 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
2841 flush_bits
|= RADV_CMD_FLAG_INV_VCACHE
|
2842 RADV_CMD_FLAG_INV_L2
;
2844 case VK_ACCESS_SHADER_READ_BIT
:
2845 flush_bits
|= RADV_CMD_FLAG_INV_VCACHE
;
2847 if (!image_is_coherent
)
2848 flush_bits
|= RADV_CMD_FLAG_INV_L2
;
2850 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
:
2852 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
;
2854 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2856 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT
:
2858 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
;
2860 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2869 void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
,
2870 const struct radv_subpass_barrier
*barrier
)
2872 cmd_buffer
->state
.flush_bits
|= radv_src_access_flush(cmd_buffer
, barrier
->src_access_mask
,
2874 radv_stage_flush(cmd_buffer
, barrier
->src_stage_mask
);
2875 cmd_buffer
->state
.flush_bits
|= radv_dst_access_flush(cmd_buffer
, barrier
->dst_access_mask
,
2880 radv_get_subpass_id(struct radv_cmd_buffer
*cmd_buffer
)
2882 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2883 uint32_t subpass_id
= state
->subpass
- state
->pass
->subpasses
;
2885 /* The id of this subpass shouldn't exceed the number of subpasses in
2886 * this render pass minus 1.
2888 assert(subpass_id
< state
->pass
->subpass_count
);
2892 static struct radv_sample_locations_state
*
2893 radv_get_attachment_sample_locations(struct radv_cmd_buffer
*cmd_buffer
,
2897 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2898 uint32_t subpass_id
= radv_get_subpass_id(cmd_buffer
);
2899 struct radv_image_view
*view
= state
->attachments
[att_idx
].iview
;
2901 if (view
->image
->info
.samples
== 1)
2904 if (state
->pass
->attachments
[att_idx
].first_subpass_idx
== subpass_id
) {
2905 /* Return the initial sample locations if this is the initial
2906 * layout transition of the given subpass attachemnt.
2908 if (state
->attachments
[att_idx
].sample_location
.count
> 0)
2909 return &state
->attachments
[att_idx
].sample_location
;
2911 /* Otherwise return the subpass sample locations if defined. */
2912 if (state
->subpass_sample_locs
) {
2913 /* Because the driver sets the current subpass before
2914 * initial layout transitions, we should use the sample
2915 * locations from the previous subpass to avoid an
2916 * off-by-one problem. Otherwise, use the sample
2917 * locations for the current subpass for final layout
2923 for (uint32_t i
= 0; i
< state
->num_subpass_sample_locs
; i
++) {
2924 if (state
->subpass_sample_locs
[i
].subpass_idx
== subpass_id
)
2925 return &state
->subpass_sample_locs
[i
].sample_location
;
2933 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
2934 struct radv_subpass_attachment att
,
2937 unsigned idx
= att
.attachment
;
2938 struct radv_image_view
*view
= cmd_buffer
->state
.attachments
[idx
].iview
;
2939 struct radv_sample_locations_state
*sample_locs
;
2940 VkImageSubresourceRange range
;
2941 range
.aspectMask
= 0;
2942 range
.baseMipLevel
= view
->base_mip
;
2943 range
.levelCount
= 1;
2944 range
.baseArrayLayer
= view
->base_layer
;
2945 range
.layerCount
= cmd_buffer
->state
.framebuffer
->layers
;
2947 if (cmd_buffer
->state
.subpass
->view_mask
) {
2948 /* If the current subpass uses multiview, the driver might have
2949 * performed a fast color/depth clear to the whole image
2950 * (including all layers). To make sure the driver will
2951 * decompress the image correctly (if needed), we have to
2952 * account for the "real" number of layers. If the view mask is
2953 * sparse, this will decompress more layers than needed.
2955 range
.layerCount
= util_last_bit(cmd_buffer
->state
.subpass
->view_mask
);
2958 /* Get the subpass sample locations for the given attachment, if NULL
2959 * is returned the driver will use the default HW locations.
2961 sample_locs
= radv_get_attachment_sample_locations(cmd_buffer
, idx
,
2964 radv_handle_image_transition(cmd_buffer
,
2966 cmd_buffer
->state
.attachments
[idx
].current_layout
,
2967 cmd_buffer
->state
.attachments
[idx
].current_in_render_loop
,
2968 att
.layout
, att
.in_render_loop
,
2969 0, 0, &range
, sample_locs
);
2971 cmd_buffer
->state
.attachments
[idx
].current_layout
= att
.layout
;
2972 cmd_buffer
->state
.attachments
[idx
].current_in_render_loop
= att
.in_render_loop
;
2978 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
2979 const struct radv_subpass
*subpass
)
2981 cmd_buffer
->state
.subpass
= subpass
;
2983 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_FRAMEBUFFER
;
2987 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer
*cmd_buffer
,
2988 struct radv_render_pass
*pass
,
2989 const VkRenderPassBeginInfo
*info
)
2991 const struct VkRenderPassSampleLocationsBeginInfoEXT
*sample_locs
=
2992 vk_find_struct_const(info
->pNext
,
2993 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT
);
2994 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2997 state
->subpass_sample_locs
= NULL
;
3001 for (uint32_t i
= 0; i
< sample_locs
->attachmentInitialSampleLocationsCount
; i
++) {
3002 const VkAttachmentSampleLocationsEXT
*att_sample_locs
=
3003 &sample_locs
->pAttachmentInitialSampleLocations
[i
];
3004 uint32_t att_idx
= att_sample_locs
->attachmentIndex
;
3005 struct radv_image
*image
= cmd_buffer
->state
.attachments
[att_idx
].iview
->image
;
3007 assert(vk_format_is_depth_or_stencil(image
->vk_format
));
3009 /* From the Vulkan spec 1.1.108:
3011 * "If the image referenced by the framebuffer attachment at
3012 * index attachmentIndex was not created with
3013 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
3014 * then the values specified in sampleLocationsInfo are
3017 if (!(image
->flags
& VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
))
3020 const VkSampleLocationsInfoEXT
*sample_locs_info
=
3021 &att_sample_locs
->sampleLocationsInfo
;
3023 state
->attachments
[att_idx
].sample_location
.per_pixel
=
3024 sample_locs_info
->sampleLocationsPerPixel
;
3025 state
->attachments
[att_idx
].sample_location
.grid_size
=
3026 sample_locs_info
->sampleLocationGridSize
;
3027 state
->attachments
[att_idx
].sample_location
.count
=
3028 sample_locs_info
->sampleLocationsCount
;
3029 typed_memcpy(&state
->attachments
[att_idx
].sample_location
.locations
[0],
3030 sample_locs_info
->pSampleLocations
,
3031 sample_locs_info
->sampleLocationsCount
);
3034 state
->subpass_sample_locs
= vk_alloc(&cmd_buffer
->pool
->alloc
,
3035 sample_locs
->postSubpassSampleLocationsCount
*
3036 sizeof(state
->subpass_sample_locs
[0]),
3037 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3038 if (state
->subpass_sample_locs
== NULL
) {
3039 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
3040 return cmd_buffer
->record_result
;
3043 state
->num_subpass_sample_locs
= sample_locs
->postSubpassSampleLocationsCount
;
3045 for (uint32_t i
= 0; i
< sample_locs
->postSubpassSampleLocationsCount
; i
++) {
3046 const VkSubpassSampleLocationsEXT
*subpass_sample_locs_info
=
3047 &sample_locs
->pPostSubpassSampleLocations
[i
];
3048 const VkSampleLocationsInfoEXT
*sample_locs_info
=
3049 &subpass_sample_locs_info
->sampleLocationsInfo
;
3051 state
->subpass_sample_locs
[i
].subpass_idx
=
3052 subpass_sample_locs_info
->subpassIndex
;
3053 state
->subpass_sample_locs
[i
].sample_location
.per_pixel
=
3054 sample_locs_info
->sampleLocationsPerPixel
;
3055 state
->subpass_sample_locs
[i
].sample_location
.grid_size
=
3056 sample_locs_info
->sampleLocationGridSize
;
3057 state
->subpass_sample_locs
[i
].sample_location
.count
=
3058 sample_locs_info
->sampleLocationsCount
;
3059 typed_memcpy(&state
->subpass_sample_locs
[i
].sample_location
.locations
[0],
3060 sample_locs_info
->pSampleLocations
,
3061 sample_locs_info
->sampleLocationsCount
);
3068 radv_cmd_state_setup_attachments(struct radv_cmd_buffer
*cmd_buffer
,
3069 struct radv_render_pass
*pass
,
3070 const VkRenderPassBeginInfo
*info
)
3072 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3073 const struct VkRenderPassAttachmentBeginInfoKHR
*attachment_info
= NULL
;
3076 attachment_info
= vk_find_struct_const(info
->pNext
,
3077 RENDER_PASS_ATTACHMENT_BEGIN_INFO_KHR
);
3081 if (pass
->attachment_count
== 0) {
3082 state
->attachments
= NULL
;
3086 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
3087 pass
->attachment_count
*
3088 sizeof(state
->attachments
[0]),
3089 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3090 if (state
->attachments
== NULL
) {
3091 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
3092 return cmd_buffer
->record_result
;
3095 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
3096 struct radv_render_pass_attachment
*att
= &pass
->attachments
[i
];
3097 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
3098 VkImageAspectFlags clear_aspects
= 0;
3100 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
3101 /* color attachment */
3102 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
3103 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
3106 /* depthstencil attachment */
3107 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
3108 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
3109 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
3110 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
3111 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_DONT_CARE
)
3112 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
3114 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
3115 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
3116 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
3120 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
3121 state
->attachments
[i
].cleared_views
= 0;
3122 if (clear_aspects
&& info
) {
3123 assert(info
->clearValueCount
> i
);
3124 state
->attachments
[i
].clear_value
= info
->pClearValues
[i
];
3127 state
->attachments
[i
].current_layout
= att
->initial_layout
;
3128 state
->attachments
[i
].sample_location
.count
= 0;
3130 struct radv_image_view
*iview
;
3131 if (attachment_info
&& attachment_info
->attachmentCount
> i
) {
3132 iview
= radv_image_view_from_handle(attachment_info
->pAttachments
[i
]);
3134 iview
= state
->framebuffer
->attachments
[i
];
3137 state
->attachments
[i
].iview
= iview
;
3138 if (iview
->aspect_mask
& (VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3139 radv_initialise_ds_surface(cmd_buffer
->device
, &state
->attachments
[i
].ds
, iview
);
3141 radv_initialise_color_surface(cmd_buffer
->device
, &state
->attachments
[i
].cb
, iview
);
3148 VkResult
radv_AllocateCommandBuffers(
3150 const VkCommandBufferAllocateInfo
*pAllocateInfo
,
3151 VkCommandBuffer
*pCommandBuffers
)
3153 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3154 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
3156 VkResult result
= VK_SUCCESS
;
3159 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
3161 if (!list_empty(&pool
->free_cmd_buffers
)) {
3162 struct radv_cmd_buffer
*cmd_buffer
= list_first_entry(&pool
->free_cmd_buffers
, struct radv_cmd_buffer
, pool_link
);
3164 list_del(&cmd_buffer
->pool_link
);
3165 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
3167 result
= radv_reset_cmd_buffer(cmd_buffer
);
3168 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
3169 cmd_buffer
->level
= pAllocateInfo
->level
;
3171 pCommandBuffers
[i
] = radv_cmd_buffer_to_handle(cmd_buffer
);
3173 result
= radv_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
3174 &pCommandBuffers
[i
]);
3176 if (result
!= VK_SUCCESS
)
3180 if (result
!= VK_SUCCESS
) {
3181 radv_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
,
3182 i
, pCommandBuffers
);
3184 /* From the Vulkan 1.0.66 spec:
3186 * "vkAllocateCommandBuffers can be used to create multiple
3187 * command buffers. If the creation of any of those command
3188 * buffers fails, the implementation must destroy all
3189 * successfully created command buffer objects from this
3190 * command, set all entries of the pCommandBuffers array to
3191 * NULL and return the error."
3193 memset(pCommandBuffers
, 0,
3194 sizeof(*pCommandBuffers
) * pAllocateInfo
->commandBufferCount
);
3200 void radv_FreeCommandBuffers(
3202 VkCommandPool commandPool
,
3203 uint32_t commandBufferCount
,
3204 const VkCommandBuffer
*pCommandBuffers
)
3206 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
3207 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
3210 if (cmd_buffer
->pool
) {
3211 list_del(&cmd_buffer
->pool_link
);
3212 list_addtail(&cmd_buffer
->pool_link
, &cmd_buffer
->pool
->free_cmd_buffers
);
3214 radv_cmd_buffer_destroy(cmd_buffer
);
3220 VkResult
radv_ResetCommandBuffer(
3221 VkCommandBuffer commandBuffer
,
3222 VkCommandBufferResetFlags flags
)
3224 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3225 return radv_reset_cmd_buffer(cmd_buffer
);
3228 VkResult
radv_BeginCommandBuffer(
3229 VkCommandBuffer commandBuffer
,
3230 const VkCommandBufferBeginInfo
*pBeginInfo
)
3232 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3233 VkResult result
= VK_SUCCESS
;
3235 if (cmd_buffer
->status
!= RADV_CMD_BUFFER_STATUS_INITIAL
) {
3236 /* If the command buffer has already been resetted with
3237 * vkResetCommandBuffer, no need to do it again.
3239 result
= radv_reset_cmd_buffer(cmd_buffer
);
3240 if (result
!= VK_SUCCESS
)
3244 memset(&cmd_buffer
->state
, 0, sizeof(cmd_buffer
->state
));
3245 cmd_buffer
->state
.last_primitive_reset_en
= -1;
3246 cmd_buffer
->state
.last_index_type
= -1;
3247 cmd_buffer
->state
.last_num_instances
= -1;
3248 cmd_buffer
->state
.last_vertex_offset
= -1;
3249 cmd_buffer
->state
.last_first_instance
= -1;
3250 cmd_buffer
->state
.predication_type
= -1;
3251 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
3253 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
&&
3254 (pBeginInfo
->flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
)) {
3255 assert(pBeginInfo
->pInheritanceInfo
);
3256 cmd_buffer
->state
.framebuffer
= radv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
3257 cmd_buffer
->state
.pass
= radv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
3259 struct radv_subpass
*subpass
=
3260 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
3262 if (cmd_buffer
->state
.framebuffer
) {
3263 result
= radv_cmd_state_setup_attachments(cmd_buffer
, cmd_buffer
->state
.pass
, NULL
);
3264 if (result
!= VK_SUCCESS
)
3268 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
);
3271 if (unlikely(cmd_buffer
->device
->trace_bo
)) {
3272 struct radv_device
*device
= cmd_buffer
->device
;
3274 radv_cs_add_buffer(device
->ws
, cmd_buffer
->cs
,
3277 radv_cmd_buffer_trace_emit(cmd_buffer
);
3280 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_RECORDING
;
3285 void radv_CmdBindVertexBuffers(
3286 VkCommandBuffer commandBuffer
,
3287 uint32_t firstBinding
,
3288 uint32_t bindingCount
,
3289 const VkBuffer
* pBuffers
,
3290 const VkDeviceSize
* pOffsets
)
3292 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3293 struct radv_vertex_binding
*vb
= cmd_buffer
->vertex_bindings
;
3294 bool changed
= false;
3296 /* We have to defer setting up vertex buffer since we need the buffer
3297 * stride from the pipeline. */
3299 assert(firstBinding
+ bindingCount
<= MAX_VBS
);
3300 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
3301 uint32_t idx
= firstBinding
+ i
;
3304 (vb
[idx
].buffer
!= radv_buffer_from_handle(pBuffers
[i
]) ||
3305 vb
[idx
].offset
!= pOffsets
[i
])) {
3309 vb
[idx
].buffer
= radv_buffer_from_handle(pBuffers
[i
]);
3310 vb
[idx
].offset
= pOffsets
[i
];
3312 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
3313 vb
[idx
].buffer
->bo
);
3317 /* No state changes. */
3321 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_VERTEX_BUFFER
;
3325 vk_to_index_type(VkIndexType type
)
3328 case VK_INDEX_TYPE_UINT8_EXT
:
3329 return V_028A7C_VGT_INDEX_8
;
3330 case VK_INDEX_TYPE_UINT16
:
3331 return V_028A7C_VGT_INDEX_16
;
3332 case VK_INDEX_TYPE_UINT32
:
3333 return V_028A7C_VGT_INDEX_32
;
3335 unreachable("invalid index type");
3340 radv_get_vgt_index_size(uint32_t type
)
3343 case V_028A7C_VGT_INDEX_8
:
3345 case V_028A7C_VGT_INDEX_16
:
3347 case V_028A7C_VGT_INDEX_32
:
3350 unreachable("invalid index type");
3354 void radv_CmdBindIndexBuffer(
3355 VkCommandBuffer commandBuffer
,
3357 VkDeviceSize offset
,
3358 VkIndexType indexType
)
3360 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3361 RADV_FROM_HANDLE(radv_buffer
, index_buffer
, buffer
);
3363 if (cmd_buffer
->state
.index_buffer
== index_buffer
&&
3364 cmd_buffer
->state
.index_offset
== offset
&&
3365 cmd_buffer
->state
.index_type
== indexType
) {
3366 /* No state changes. */
3370 cmd_buffer
->state
.index_buffer
= index_buffer
;
3371 cmd_buffer
->state
.index_offset
= offset
;
3372 cmd_buffer
->state
.index_type
= vk_to_index_type(indexType
);
3373 cmd_buffer
->state
.index_va
= radv_buffer_get_va(index_buffer
->bo
);
3374 cmd_buffer
->state
.index_va
+= index_buffer
->offset
+ offset
;
3376 int index_size
= radv_get_vgt_index_size(vk_to_index_type(indexType
));
3377 cmd_buffer
->state
.max_index_count
= (index_buffer
->size
- offset
) / index_size
;
3378 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
3379 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, index_buffer
->bo
);
3384 radv_bind_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
3385 VkPipelineBindPoint bind_point
,
3386 struct radv_descriptor_set
*set
, unsigned idx
)
3388 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
3390 radv_set_descriptor_set(cmd_buffer
, bind_point
, set
, idx
);
3393 assert(!(set
->layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
));
3395 if (!cmd_buffer
->device
->use_global_bo_list
) {
3396 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
)
3397 if (set
->descriptors
[j
])
3398 radv_cs_add_buffer(ws
, cmd_buffer
->cs
, set
->descriptors
[j
]);
3402 radv_cs_add_buffer(ws
, cmd_buffer
->cs
, set
->bo
);
3405 void radv_CmdBindDescriptorSets(
3406 VkCommandBuffer commandBuffer
,
3407 VkPipelineBindPoint pipelineBindPoint
,
3408 VkPipelineLayout _layout
,
3410 uint32_t descriptorSetCount
,
3411 const VkDescriptorSet
* pDescriptorSets
,
3412 uint32_t dynamicOffsetCount
,
3413 const uint32_t* pDynamicOffsets
)
3415 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3416 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
3417 unsigned dyn_idx
= 0;
3419 const bool no_dynamic_bounds
= cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_NO_DYNAMIC_BOUNDS
;
3420 struct radv_descriptor_state
*descriptors_state
=
3421 radv_get_descriptors_state(cmd_buffer
, pipelineBindPoint
);
3423 for (unsigned i
= 0; i
< descriptorSetCount
; ++i
) {
3424 unsigned idx
= i
+ firstSet
;
3425 RADV_FROM_HANDLE(radv_descriptor_set
, set
, pDescriptorSets
[i
]);
3427 /* If the set is already bound we only need to update the
3428 * (potentially changed) dynamic offsets. */
3429 if (descriptors_state
->sets
[idx
] != set
||
3430 !(descriptors_state
->valid
& (1u << idx
))) {
3431 radv_bind_descriptor_set(cmd_buffer
, pipelineBindPoint
, set
, idx
);
3434 for(unsigned j
= 0; j
< set
->layout
->dynamic_offset_count
; ++j
, ++dyn_idx
) {
3435 unsigned idx
= j
+ layout
->set
[i
+ firstSet
].dynamic_offset_start
;
3436 uint32_t *dst
= descriptors_state
->dynamic_buffers
+ idx
* 4;
3437 assert(dyn_idx
< dynamicOffsetCount
);
3439 struct radv_descriptor_range
*range
= set
->dynamic_descriptors
+ j
;
3440 uint64_t va
= range
->va
+ pDynamicOffsets
[dyn_idx
];
3442 dst
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
3443 dst
[2] = no_dynamic_bounds
? 0xffffffffu
: range
->size
;
3444 dst
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3445 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3446 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3447 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3449 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3450 dst
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3451 S_008F0C_OOB_SELECT(3) |
3452 S_008F0C_RESOURCE_LEVEL(1);
3454 dst
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3455 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3458 cmd_buffer
->push_constant_stages
|=
3459 set
->layout
->dynamic_shader_stages
;
3464 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
3465 struct radv_descriptor_set
*set
,
3466 struct radv_descriptor_set_layout
*layout
,
3467 VkPipelineBindPoint bind_point
)
3469 struct radv_descriptor_state
*descriptors_state
=
3470 radv_get_descriptors_state(cmd_buffer
, bind_point
);
3471 set
->size
= layout
->size
;
3472 set
->layout
= layout
;
3474 if (descriptors_state
->push_set
.capacity
< set
->size
) {
3475 size_t new_size
= MAX2(set
->size
, 1024);
3476 new_size
= MAX2(new_size
, 2 * descriptors_state
->push_set
.capacity
);
3477 new_size
= MIN2(new_size
, 96 * MAX_PUSH_DESCRIPTORS
);
3479 free(set
->mapped_ptr
);
3480 set
->mapped_ptr
= malloc(new_size
);
3482 if (!set
->mapped_ptr
) {
3483 descriptors_state
->push_set
.capacity
= 0;
3484 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
3488 descriptors_state
->push_set
.capacity
= new_size
;
3494 void radv_meta_push_descriptor_set(
3495 struct radv_cmd_buffer
* cmd_buffer
,
3496 VkPipelineBindPoint pipelineBindPoint
,
3497 VkPipelineLayout _layout
,
3499 uint32_t descriptorWriteCount
,
3500 const VkWriteDescriptorSet
* pDescriptorWrites
)
3502 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
3503 struct radv_descriptor_set
*push_set
= &cmd_buffer
->meta_push_descriptors
;
3507 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
3509 push_set
->size
= layout
->set
[set
].layout
->size
;
3510 push_set
->layout
= layout
->set
[set
].layout
;
3512 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, push_set
->size
, 32,
3514 (void**) &push_set
->mapped_ptr
))
3517 push_set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
3518 push_set
->va
+= bo_offset
;
3520 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
3521 radv_descriptor_set_to_handle(push_set
),
3522 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
3524 radv_set_descriptor_set(cmd_buffer
, pipelineBindPoint
, push_set
, set
);
3527 void radv_CmdPushDescriptorSetKHR(
3528 VkCommandBuffer commandBuffer
,
3529 VkPipelineBindPoint pipelineBindPoint
,
3530 VkPipelineLayout _layout
,
3532 uint32_t descriptorWriteCount
,
3533 const VkWriteDescriptorSet
* pDescriptorWrites
)
3535 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3536 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
3537 struct radv_descriptor_state
*descriptors_state
=
3538 radv_get_descriptors_state(cmd_buffer
, pipelineBindPoint
);
3539 struct radv_descriptor_set
*push_set
= &descriptors_state
->push_set
.set
;
3541 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
3543 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
,
3544 layout
->set
[set
].layout
,
3548 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3549 * because it is invalid, according to Vulkan spec.
3551 for (int i
= 0; i
< descriptorWriteCount
; i
++) {
3552 ASSERTED
const VkWriteDescriptorSet
*writeset
= &pDescriptorWrites
[i
];
3553 assert(writeset
->descriptorType
!= VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
);
3556 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
3557 radv_descriptor_set_to_handle(push_set
),
3558 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
3560 radv_set_descriptor_set(cmd_buffer
, pipelineBindPoint
, push_set
, set
);
3561 descriptors_state
->push_dirty
= true;
3564 void radv_CmdPushDescriptorSetWithTemplateKHR(
3565 VkCommandBuffer commandBuffer
,
3566 VkDescriptorUpdateTemplate descriptorUpdateTemplate
,
3567 VkPipelineLayout _layout
,
3571 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3572 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
3573 RADV_FROM_HANDLE(radv_descriptor_update_template
, templ
, descriptorUpdateTemplate
);
3574 struct radv_descriptor_state
*descriptors_state
=
3575 radv_get_descriptors_state(cmd_buffer
, templ
->bind_point
);
3576 struct radv_descriptor_set
*push_set
= &descriptors_state
->push_set
.set
;
3578 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
3580 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
,
3581 layout
->set
[set
].layout
,
3585 radv_update_descriptor_set_with_template(cmd_buffer
->device
, cmd_buffer
, push_set
,
3586 descriptorUpdateTemplate
, pData
);
3588 radv_set_descriptor_set(cmd_buffer
, templ
->bind_point
, push_set
, set
);
3589 descriptors_state
->push_dirty
= true;
3592 void radv_CmdPushConstants(VkCommandBuffer commandBuffer
,
3593 VkPipelineLayout layout
,
3594 VkShaderStageFlags stageFlags
,
3597 const void* pValues
)
3599 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3600 memcpy(cmd_buffer
->push_constants
+ offset
, pValues
, size
);
3601 cmd_buffer
->push_constant_stages
|= stageFlags
;
3604 VkResult
radv_EndCommandBuffer(
3605 VkCommandBuffer commandBuffer
)
3607 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3609 if (cmd_buffer
->queue_family_index
!= RADV_QUEUE_TRANSFER
) {
3610 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX6
)
3611 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
| RADV_CMD_FLAG_WB_L2
;
3613 /* Make sure to sync all pending active queries at the end of
3616 cmd_buffer
->state
.flush_bits
|= cmd_buffer
->active_query_flush_bits
;
3618 /* Since NGG streamout uses GDS, we need to make GDS idle when
3619 * we leave the IB, otherwise another process might overwrite
3620 * it while our shaders are busy.
3622 if (cmd_buffer
->gds_needed
)
3623 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
;
3625 si_emit_cache_flush(cmd_buffer
);
3628 /* Make sure CP DMA is idle at the end of IBs because the kernel
3629 * doesn't wait for it.
3631 si_cp_dma_wait_for_idle(cmd_buffer
);
3633 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
3634 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.subpass_sample_locs
);
3636 if (!cmd_buffer
->device
->ws
->cs_finalize(cmd_buffer
->cs
))
3637 return vk_error(cmd_buffer
->device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
3639 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_EXECUTABLE
;
3641 return cmd_buffer
->record_result
;
3645 radv_emit_compute_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
3647 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
3649 if (!pipeline
|| pipeline
== cmd_buffer
->state
.emitted_compute_pipeline
)
3652 assert(!pipeline
->ctx_cs
.cdw
);
3654 cmd_buffer
->state
.emitted_compute_pipeline
= pipeline
;
3656 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, pipeline
->cs
.cdw
);
3657 radeon_emit_array(cmd_buffer
->cs
, pipeline
->cs
.buf
, pipeline
->cs
.cdw
);
3659 cmd_buffer
->compute_scratch_size_needed
=
3660 MAX2(cmd_buffer
->compute_scratch_size_needed
,
3661 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
3663 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
3664 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->bo
);
3666 if (unlikely(cmd_buffer
->device
->trace_bo
))
3667 radv_save_pipeline(cmd_buffer
, pipeline
, RING_COMPUTE
);
3670 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer
*cmd_buffer
,
3671 VkPipelineBindPoint bind_point
)
3673 struct radv_descriptor_state
*descriptors_state
=
3674 radv_get_descriptors_state(cmd_buffer
, bind_point
);
3676 descriptors_state
->dirty
|= descriptors_state
->valid
;
3679 void radv_CmdBindPipeline(
3680 VkCommandBuffer commandBuffer
,
3681 VkPipelineBindPoint pipelineBindPoint
,
3682 VkPipeline _pipeline
)
3684 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3685 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
3687 switch (pipelineBindPoint
) {
3688 case VK_PIPELINE_BIND_POINT_COMPUTE
:
3689 if (cmd_buffer
->state
.compute_pipeline
== pipeline
)
3691 radv_mark_descriptor_sets_dirty(cmd_buffer
, pipelineBindPoint
);
3693 cmd_buffer
->state
.compute_pipeline
= pipeline
;
3694 cmd_buffer
->push_constant_stages
|= VK_SHADER_STAGE_COMPUTE_BIT
;
3696 case VK_PIPELINE_BIND_POINT_GRAPHICS
:
3697 if (cmd_buffer
->state
.pipeline
== pipeline
)
3699 radv_mark_descriptor_sets_dirty(cmd_buffer
, pipelineBindPoint
);
3701 cmd_buffer
->state
.pipeline
= pipeline
;
3705 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
;
3706 cmd_buffer
->push_constant_stages
|= pipeline
->active_stages
;
3708 /* the new vertex shader might not have the same user regs */
3709 cmd_buffer
->state
.last_first_instance
= -1;
3710 cmd_buffer
->state
.last_vertex_offset
= -1;
3712 /* Prefetch all pipeline shaders at first draw time. */
3713 cmd_buffer
->state
.prefetch_L2_mask
|= RADV_PREFETCH_SHADERS
;
3715 if ((cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_NAVI10
||
3716 cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_NAVI12
||
3717 cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_NAVI14
) &&
3718 cmd_buffer
->state
.emitted_pipeline
&&
3719 radv_pipeline_has_ngg(cmd_buffer
->state
.emitted_pipeline
) &&
3720 !radv_pipeline_has_ngg(cmd_buffer
->state
.pipeline
)) {
3721 /* Transitioning from NGG to legacy GS requires
3722 * VGT_FLUSH on Navi10-14. VGT_FLUSH is also emitted
3723 * at the beginning of IBs when legacy GS ring pointers
3726 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VGT_FLUSH
;
3729 radv_bind_dynamic_state(cmd_buffer
, &pipeline
->dynamic_state
);
3730 radv_bind_streamout_state(cmd_buffer
, pipeline
);
3732 if (pipeline
->graphics
.esgs_ring_size
> cmd_buffer
->esgs_ring_size_needed
)
3733 cmd_buffer
->esgs_ring_size_needed
= pipeline
->graphics
.esgs_ring_size
;
3734 if (pipeline
->graphics
.gsvs_ring_size
> cmd_buffer
->gsvs_ring_size_needed
)
3735 cmd_buffer
->gsvs_ring_size_needed
= pipeline
->graphics
.gsvs_ring_size
;
3737 if (radv_pipeline_has_tess(pipeline
))
3738 cmd_buffer
->tess_rings_needed
= true;
3741 assert(!"invalid bind point");
3746 void radv_CmdSetViewport(
3747 VkCommandBuffer commandBuffer
,
3748 uint32_t firstViewport
,
3749 uint32_t viewportCount
,
3750 const VkViewport
* pViewports
)
3752 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3753 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3754 ASSERTED
const uint32_t total_count
= firstViewport
+ viewportCount
;
3756 assert(firstViewport
< MAX_VIEWPORTS
);
3757 assert(total_count
>= 1 && total_count
<= MAX_VIEWPORTS
);
3759 if (!memcmp(state
->dynamic
.viewport
.viewports
+ firstViewport
,
3760 pViewports
, viewportCount
* sizeof(*pViewports
))) {
3764 memcpy(state
->dynamic
.viewport
.viewports
+ firstViewport
, pViewports
,
3765 viewportCount
* sizeof(*pViewports
));
3767 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
3770 void radv_CmdSetScissor(
3771 VkCommandBuffer commandBuffer
,
3772 uint32_t firstScissor
,
3773 uint32_t scissorCount
,
3774 const VkRect2D
* pScissors
)
3776 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3777 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3778 ASSERTED
const uint32_t total_count
= firstScissor
+ scissorCount
;
3780 assert(firstScissor
< MAX_SCISSORS
);
3781 assert(total_count
>= 1 && total_count
<= MAX_SCISSORS
);
3783 if (!memcmp(state
->dynamic
.scissor
.scissors
+ firstScissor
, pScissors
,
3784 scissorCount
* sizeof(*pScissors
))) {
3788 memcpy(state
->dynamic
.scissor
.scissors
+ firstScissor
, pScissors
,
3789 scissorCount
* sizeof(*pScissors
));
3791 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
3794 void radv_CmdSetLineWidth(
3795 VkCommandBuffer commandBuffer
,
3798 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3800 if (cmd_buffer
->state
.dynamic
.line_width
== lineWidth
)
3803 cmd_buffer
->state
.dynamic
.line_width
= lineWidth
;
3804 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
3807 void radv_CmdSetDepthBias(
3808 VkCommandBuffer commandBuffer
,
3809 float depthBiasConstantFactor
,
3810 float depthBiasClamp
,
3811 float depthBiasSlopeFactor
)
3813 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3814 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3816 if (state
->dynamic
.depth_bias
.bias
== depthBiasConstantFactor
&&
3817 state
->dynamic
.depth_bias
.clamp
== depthBiasClamp
&&
3818 state
->dynamic
.depth_bias
.slope
== depthBiasSlopeFactor
) {
3822 state
->dynamic
.depth_bias
.bias
= depthBiasConstantFactor
;
3823 state
->dynamic
.depth_bias
.clamp
= depthBiasClamp
;
3824 state
->dynamic
.depth_bias
.slope
= depthBiasSlopeFactor
;
3826 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
3829 void radv_CmdSetBlendConstants(
3830 VkCommandBuffer commandBuffer
,
3831 const float blendConstants
[4])
3833 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3834 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3836 if (!memcmp(state
->dynamic
.blend_constants
, blendConstants
, sizeof(float) * 4))
3839 memcpy(state
->dynamic
.blend_constants
, blendConstants
, sizeof(float) * 4);
3841 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
3844 void radv_CmdSetDepthBounds(
3845 VkCommandBuffer commandBuffer
,
3846 float minDepthBounds
,
3847 float maxDepthBounds
)
3849 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3850 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3852 if (state
->dynamic
.depth_bounds
.min
== minDepthBounds
&&
3853 state
->dynamic
.depth_bounds
.max
== maxDepthBounds
) {
3857 state
->dynamic
.depth_bounds
.min
= minDepthBounds
;
3858 state
->dynamic
.depth_bounds
.max
= maxDepthBounds
;
3860 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
3863 void radv_CmdSetStencilCompareMask(
3864 VkCommandBuffer commandBuffer
,
3865 VkStencilFaceFlags faceMask
,
3866 uint32_t compareMask
)
3868 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3869 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3870 bool front_same
= state
->dynamic
.stencil_compare_mask
.front
== compareMask
;
3871 bool back_same
= state
->dynamic
.stencil_compare_mask
.back
== compareMask
;
3873 if ((!(faceMask
& VK_STENCIL_FACE_FRONT_BIT
) || front_same
) &&
3874 (!(faceMask
& VK_STENCIL_FACE_BACK_BIT
) || back_same
)) {
3878 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
3879 state
->dynamic
.stencil_compare_mask
.front
= compareMask
;
3880 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
3881 state
->dynamic
.stencil_compare_mask
.back
= compareMask
;
3883 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
3886 void radv_CmdSetStencilWriteMask(
3887 VkCommandBuffer commandBuffer
,
3888 VkStencilFaceFlags faceMask
,
3891 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3892 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3893 bool front_same
= state
->dynamic
.stencil_write_mask
.front
== writeMask
;
3894 bool back_same
= state
->dynamic
.stencil_write_mask
.back
== writeMask
;
3896 if ((!(faceMask
& VK_STENCIL_FACE_FRONT_BIT
) || front_same
) &&
3897 (!(faceMask
& VK_STENCIL_FACE_BACK_BIT
) || back_same
)) {
3901 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
3902 state
->dynamic
.stencil_write_mask
.front
= writeMask
;
3903 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
3904 state
->dynamic
.stencil_write_mask
.back
= writeMask
;
3906 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
3909 void radv_CmdSetStencilReference(
3910 VkCommandBuffer commandBuffer
,
3911 VkStencilFaceFlags faceMask
,
3914 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3915 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3916 bool front_same
= state
->dynamic
.stencil_reference
.front
== reference
;
3917 bool back_same
= state
->dynamic
.stencil_reference
.back
== reference
;
3919 if ((!(faceMask
& VK_STENCIL_FACE_FRONT_BIT
) || front_same
) &&
3920 (!(faceMask
& VK_STENCIL_FACE_BACK_BIT
) || back_same
)) {
3924 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
3925 cmd_buffer
->state
.dynamic
.stencil_reference
.front
= reference
;
3926 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
3927 cmd_buffer
->state
.dynamic
.stencil_reference
.back
= reference
;
3929 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
3932 void radv_CmdSetDiscardRectangleEXT(
3933 VkCommandBuffer commandBuffer
,
3934 uint32_t firstDiscardRectangle
,
3935 uint32_t discardRectangleCount
,
3936 const VkRect2D
* pDiscardRectangles
)
3938 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3939 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3940 ASSERTED
const uint32_t total_count
= firstDiscardRectangle
+ discardRectangleCount
;
3942 assert(firstDiscardRectangle
< MAX_DISCARD_RECTANGLES
);
3943 assert(total_count
>= 1 && total_count
<= MAX_DISCARD_RECTANGLES
);
3945 if (!memcmp(state
->dynamic
.discard_rectangle
.rectangles
+ firstDiscardRectangle
,
3946 pDiscardRectangles
, discardRectangleCount
* sizeof(*pDiscardRectangles
))) {
3950 typed_memcpy(&state
->dynamic
.discard_rectangle
.rectangles
[firstDiscardRectangle
],
3951 pDiscardRectangles
, discardRectangleCount
);
3953 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
;
3956 void radv_CmdSetSampleLocationsEXT(
3957 VkCommandBuffer commandBuffer
,
3958 const VkSampleLocationsInfoEXT
* pSampleLocationsInfo
)
3960 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3961 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3963 assert(pSampleLocationsInfo
->sampleLocationsCount
<= MAX_SAMPLE_LOCATIONS
);
3965 state
->dynamic
.sample_location
.per_pixel
= pSampleLocationsInfo
->sampleLocationsPerPixel
;
3966 state
->dynamic
.sample_location
.grid_size
= pSampleLocationsInfo
->sampleLocationGridSize
;
3967 state
->dynamic
.sample_location
.count
= pSampleLocationsInfo
->sampleLocationsCount
;
3968 typed_memcpy(&state
->dynamic
.sample_location
.locations
[0],
3969 pSampleLocationsInfo
->pSampleLocations
,
3970 pSampleLocationsInfo
->sampleLocationsCount
);
3972 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS
;
3975 void radv_CmdExecuteCommands(
3976 VkCommandBuffer commandBuffer
,
3977 uint32_t commandBufferCount
,
3978 const VkCommandBuffer
* pCmdBuffers
)
3980 RADV_FROM_HANDLE(radv_cmd_buffer
, primary
, commandBuffer
);
3982 assert(commandBufferCount
> 0);
3984 /* Emit pending flushes on primary prior to executing secondary */
3985 si_emit_cache_flush(primary
);
3987 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
3988 RADV_FROM_HANDLE(radv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
3990 primary
->scratch_size_needed
= MAX2(primary
->scratch_size_needed
,
3991 secondary
->scratch_size_needed
);
3992 primary
->compute_scratch_size_needed
= MAX2(primary
->compute_scratch_size_needed
,
3993 secondary
->compute_scratch_size_needed
);
3995 if (secondary
->esgs_ring_size_needed
> primary
->esgs_ring_size_needed
)
3996 primary
->esgs_ring_size_needed
= secondary
->esgs_ring_size_needed
;
3997 if (secondary
->gsvs_ring_size_needed
> primary
->gsvs_ring_size_needed
)
3998 primary
->gsvs_ring_size_needed
= secondary
->gsvs_ring_size_needed
;
3999 if (secondary
->tess_rings_needed
)
4000 primary
->tess_rings_needed
= true;
4001 if (secondary
->sample_positions_needed
)
4002 primary
->sample_positions_needed
= true;
4004 if (!secondary
->state
.framebuffer
&&
4005 (primary
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
)) {
4006 /* Emit the framebuffer state from primary if secondary
4007 * has been recorded without a framebuffer, otherwise
4008 * fast color/depth clears can't work.
4010 radv_emit_framebuffer_state(primary
);
4013 primary
->device
->ws
->cs_execute_secondary(primary
->cs
, secondary
->cs
);
4016 /* When the secondary command buffer is compute only we don't
4017 * need to re-emit the current graphics pipeline.
4019 if (secondary
->state
.emitted_pipeline
) {
4020 primary
->state
.emitted_pipeline
=
4021 secondary
->state
.emitted_pipeline
;
4024 /* When the secondary command buffer is graphics only we don't
4025 * need to re-emit the current compute pipeline.
4027 if (secondary
->state
.emitted_compute_pipeline
) {
4028 primary
->state
.emitted_compute_pipeline
=
4029 secondary
->state
.emitted_compute_pipeline
;
4032 /* Only re-emit the draw packets when needed. */
4033 if (secondary
->state
.last_primitive_reset_en
!= -1) {
4034 primary
->state
.last_primitive_reset_en
=
4035 secondary
->state
.last_primitive_reset_en
;
4038 if (secondary
->state
.last_primitive_reset_index
) {
4039 primary
->state
.last_primitive_reset_index
=
4040 secondary
->state
.last_primitive_reset_index
;
4043 if (secondary
->state
.last_ia_multi_vgt_param
) {
4044 primary
->state
.last_ia_multi_vgt_param
=
4045 secondary
->state
.last_ia_multi_vgt_param
;
4048 primary
->state
.last_first_instance
= secondary
->state
.last_first_instance
;
4049 primary
->state
.last_num_instances
= secondary
->state
.last_num_instances
;
4050 primary
->state
.last_vertex_offset
= secondary
->state
.last_vertex_offset
;
4052 if (secondary
->state
.last_index_type
!= -1) {
4053 primary
->state
.last_index_type
=
4054 secondary
->state
.last_index_type
;
4058 /* After executing commands from secondary buffers we have to dirty
4061 primary
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
|
4062 RADV_CMD_DIRTY_INDEX_BUFFER
|
4063 RADV_CMD_DIRTY_DYNAMIC_ALL
;
4064 radv_mark_descriptor_sets_dirty(primary
, VK_PIPELINE_BIND_POINT_GRAPHICS
);
4065 radv_mark_descriptor_sets_dirty(primary
, VK_PIPELINE_BIND_POINT_COMPUTE
);
4068 VkResult
radv_CreateCommandPool(
4070 const VkCommandPoolCreateInfo
* pCreateInfo
,
4071 const VkAllocationCallbacks
* pAllocator
,
4072 VkCommandPool
* pCmdPool
)
4074 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4075 struct radv_cmd_pool
*pool
;
4077 pool
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pool
), 8,
4078 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4080 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4083 pool
->alloc
= *pAllocator
;
4085 pool
->alloc
= device
->alloc
;
4087 list_inithead(&pool
->cmd_buffers
);
4088 list_inithead(&pool
->free_cmd_buffers
);
4090 pool
->queue_family_index
= pCreateInfo
->queueFamilyIndex
;
4092 *pCmdPool
= radv_cmd_pool_to_handle(pool
);
4098 void radv_DestroyCommandPool(
4100 VkCommandPool commandPool
,
4101 const VkAllocationCallbacks
* pAllocator
)
4103 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4104 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
4109 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
4110 &pool
->cmd_buffers
, pool_link
) {
4111 radv_cmd_buffer_destroy(cmd_buffer
);
4114 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
4115 &pool
->free_cmd_buffers
, pool_link
) {
4116 radv_cmd_buffer_destroy(cmd_buffer
);
4119 vk_free2(&device
->alloc
, pAllocator
, pool
);
4122 VkResult
radv_ResetCommandPool(
4124 VkCommandPool commandPool
,
4125 VkCommandPoolResetFlags flags
)
4127 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
4130 list_for_each_entry(struct radv_cmd_buffer
, cmd_buffer
,
4131 &pool
->cmd_buffers
, pool_link
) {
4132 result
= radv_reset_cmd_buffer(cmd_buffer
);
4133 if (result
!= VK_SUCCESS
)
4140 void radv_TrimCommandPool(
4142 VkCommandPool commandPool
,
4143 VkCommandPoolTrimFlags flags
)
4145 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
4150 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
4151 &pool
->free_cmd_buffers
, pool_link
) {
4152 radv_cmd_buffer_destroy(cmd_buffer
);
4157 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer
*cmd_buffer
,
4158 uint32_t subpass_id
)
4160 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4161 struct radv_subpass
*subpass
= &state
->pass
->subpasses
[subpass_id
];
4163 ASSERTED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
4164 cmd_buffer
->cs
, 4096);
4166 radv_subpass_barrier(cmd_buffer
, &subpass
->start_barrier
);
4168 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
);
4170 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4171 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4172 if (a
== VK_ATTACHMENT_UNUSED
)
4175 radv_handle_subpass_image_transition(cmd_buffer
,
4176 subpass
->attachments
[i
],
4180 radv_cmd_buffer_clear_subpass(cmd_buffer
);
4182 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4186 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer
*cmd_buffer
)
4188 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4189 const struct radv_subpass
*subpass
= state
->subpass
;
4190 uint32_t subpass_id
= radv_get_subpass_id(cmd_buffer
);
4192 radv_cmd_buffer_resolve_subpass(cmd_buffer
);
4194 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4195 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4196 if (a
== VK_ATTACHMENT_UNUSED
)
4199 if (state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
4202 VkImageLayout layout
= state
->pass
->attachments
[a
].final_layout
;
4203 struct radv_subpass_attachment att
= { a
, layout
};
4204 radv_handle_subpass_image_transition(cmd_buffer
, att
, false);
4208 void radv_CmdBeginRenderPass(
4209 VkCommandBuffer commandBuffer
,
4210 const VkRenderPassBeginInfo
* pRenderPassBegin
,
4211 VkSubpassContents contents
)
4213 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4214 RADV_FROM_HANDLE(radv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
4215 RADV_FROM_HANDLE(radv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
4218 cmd_buffer
->state
.framebuffer
= framebuffer
;
4219 cmd_buffer
->state
.pass
= pass
;
4220 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
4222 result
= radv_cmd_state_setup_attachments(cmd_buffer
, pass
, pRenderPassBegin
);
4223 if (result
!= VK_SUCCESS
)
4226 result
= radv_cmd_state_setup_sample_locations(cmd_buffer
, pass
, pRenderPassBegin
);
4227 if (result
!= VK_SUCCESS
)
4230 radv_cmd_buffer_begin_subpass(cmd_buffer
, 0);
4233 void radv_CmdBeginRenderPass2KHR(
4234 VkCommandBuffer commandBuffer
,
4235 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
4236 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
)
4238 radv_CmdBeginRenderPass(commandBuffer
, pRenderPassBeginInfo
,
4239 pSubpassBeginInfo
->contents
);
4242 void radv_CmdNextSubpass(
4243 VkCommandBuffer commandBuffer
,
4244 VkSubpassContents contents
)
4246 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4248 uint32_t prev_subpass
= radv_get_subpass_id(cmd_buffer
);
4249 radv_cmd_buffer_end_subpass(cmd_buffer
);
4250 radv_cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
4253 void radv_CmdNextSubpass2KHR(
4254 VkCommandBuffer commandBuffer
,
4255 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
,
4256 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
4258 radv_CmdNextSubpass(commandBuffer
, pSubpassBeginInfo
->contents
);
4261 static void radv_emit_view_index(struct radv_cmd_buffer
*cmd_buffer
, unsigned index
)
4263 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
4264 for (unsigned stage
= 0; stage
< MESA_SHADER_STAGES
; ++stage
) {
4265 if (!radv_get_shader(pipeline
, stage
))
4268 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, AC_UD_VIEW_INDEX
);
4269 if (loc
->sgpr_idx
== -1)
4271 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
4272 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
4275 if (radv_pipeline_has_gs_copy_shader(pipeline
)) {
4276 struct radv_userdata_info
*loc
= &pipeline
->gs_copy_shader
->info
.user_sgprs_locs
.shader_data
[AC_UD_VIEW_INDEX
];
4277 if (loc
->sgpr_idx
!= -1) {
4278 uint32_t base_reg
= R_00B130_SPI_SHADER_USER_DATA_VS_0
;
4279 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
4285 radv_cs_emit_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
4286 uint32_t vertex_count
,
4289 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, cmd_buffer
->state
.predicating
));
4290 radeon_emit(cmd_buffer
->cs
, vertex_count
);
4291 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
4292 S_0287F0_USE_OPAQUE(use_opaque
));
4296 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer
*cmd_buffer
,
4298 uint32_t index_count
)
4300 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_2
, 4, cmd_buffer
->state
.predicating
));
4301 radeon_emit(cmd_buffer
->cs
, cmd_buffer
->state
.max_index_count
);
4302 radeon_emit(cmd_buffer
->cs
, index_va
);
4303 radeon_emit(cmd_buffer
->cs
, index_va
>> 32);
4304 radeon_emit(cmd_buffer
->cs
, index_count
);
4305 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_DMA
);
4309 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
4311 uint32_t draw_count
,
4315 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4316 unsigned di_src_sel
= indexed
? V_0287F0_DI_SRC_SEL_DMA
4317 : V_0287F0_DI_SRC_SEL_AUTO_INDEX
;
4318 bool draw_id_enable
= radv_get_shader(cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
)->info
.vs
.needs_draw_id
;
4319 uint32_t base_reg
= cmd_buffer
->state
.pipeline
->graphics
.vtx_base_sgpr
;
4320 bool predicating
= cmd_buffer
->state
.predicating
;
4323 /* just reset draw state for vertex data */
4324 cmd_buffer
->state
.last_first_instance
= -1;
4325 cmd_buffer
->state
.last_num_instances
= -1;
4326 cmd_buffer
->state
.last_vertex_offset
= -1;
4328 if (draw_count
== 1 && !count_va
&& !draw_id_enable
) {
4329 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT
:
4330 PKT3_DRAW_INDIRECT
, 3, predicating
));
4332 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
4333 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
4334 radeon_emit(cs
, di_src_sel
);
4336 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT_MULTI
:
4337 PKT3_DRAW_INDIRECT_MULTI
,
4340 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
4341 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
4342 radeon_emit(cs
, (((base_reg
+ 8) - SI_SH_REG_OFFSET
) >> 2) |
4343 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable
) |
4344 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va
));
4345 radeon_emit(cs
, draw_count
); /* count */
4346 radeon_emit(cs
, count_va
); /* count_addr */
4347 radeon_emit(cs
, count_va
>> 32);
4348 radeon_emit(cs
, stride
); /* stride */
4349 radeon_emit(cs
, di_src_sel
);
4354 radv_emit_draw_packets(struct radv_cmd_buffer
*cmd_buffer
,
4355 const struct radv_draw_info
*info
)
4357 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4358 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
4359 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4361 if (info
->indirect
) {
4362 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
4363 uint64_t count_va
= 0;
4365 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
4367 radv_cs_add_buffer(ws
, cs
, info
->indirect
->bo
);
4369 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0));
4371 radeon_emit(cs
, va
);
4372 radeon_emit(cs
, va
>> 32);
4374 if (info
->count_buffer
) {
4375 count_va
= radv_buffer_get_va(info
->count_buffer
->bo
);
4376 count_va
+= info
->count_buffer
->offset
+
4377 info
->count_buffer_offset
;
4379 radv_cs_add_buffer(ws
, cs
, info
->count_buffer
->bo
);
4382 if (!state
->subpass
->view_mask
) {
4383 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
4390 for_each_bit(i
, state
->subpass
->view_mask
) {
4391 radv_emit_view_index(cmd_buffer
, i
);
4393 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
4401 assert(state
->pipeline
->graphics
.vtx_base_sgpr
);
4403 if (info
->vertex_offset
!= state
->last_vertex_offset
||
4404 info
->first_instance
!= state
->last_first_instance
) {
4405 radeon_set_sh_reg_seq(cs
, state
->pipeline
->graphics
.vtx_base_sgpr
,
4406 state
->pipeline
->graphics
.vtx_emit_num
);
4408 radeon_emit(cs
, info
->vertex_offset
);
4409 radeon_emit(cs
, info
->first_instance
);
4410 if (state
->pipeline
->graphics
.vtx_emit_num
== 3)
4412 state
->last_first_instance
= info
->first_instance
;
4413 state
->last_vertex_offset
= info
->vertex_offset
;
4416 if (state
->last_num_instances
!= info
->instance_count
) {
4417 radeon_emit(cs
, PKT3(PKT3_NUM_INSTANCES
, 0, false));
4418 radeon_emit(cs
, info
->instance_count
);
4419 state
->last_num_instances
= info
->instance_count
;
4422 if (info
->indexed
) {
4423 int index_size
= radv_get_vgt_index_size(state
->index_type
);
4426 /* Skip draw calls with 0-sized index buffers. They
4427 * cause a hang on some chips, like Navi10-14.
4429 if (!cmd_buffer
->state
.max_index_count
)
4432 index_va
= state
->index_va
;
4433 index_va
+= info
->first_index
* index_size
;
4435 if (!state
->subpass
->view_mask
) {
4436 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
4441 for_each_bit(i
, state
->subpass
->view_mask
) {
4442 radv_emit_view_index(cmd_buffer
, i
);
4444 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
4450 if (!state
->subpass
->view_mask
) {
4451 radv_cs_emit_draw_packet(cmd_buffer
,
4453 !!info
->strmout_buffer
);
4456 for_each_bit(i
, state
->subpass
->view_mask
) {
4457 radv_emit_view_index(cmd_buffer
, i
);
4459 radv_cs_emit_draw_packet(cmd_buffer
,
4461 !!info
->strmout_buffer
);
4469 * Vega and raven have a bug which triggers if there are multiple context
4470 * register contexts active at the same time with different scissor values.
4472 * There are two possible workarounds:
4473 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
4474 * there is only ever 1 active set of scissor values at the same time.
4476 * 2) Whenever the hardware switches contexts we have to set the scissor
4477 * registers again even if it is a noop. That way the new context gets
4478 * the correct scissor values.
4480 * This implements option 2. radv_need_late_scissor_emission needs to
4481 * return true on affected HW if radv_emit_all_graphics_states sets
4482 * any context registers.
4484 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer
*cmd_buffer
,
4485 const struct radv_draw_info
*info
)
4487 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4489 if (!cmd_buffer
->device
->physical_device
->rad_info
.has_gfx9_scissor_bug
)
4492 if (cmd_buffer
->state
.context_roll_without_scissor_emitted
|| info
->strmout_buffer
)
4495 uint32_t used_states
= cmd_buffer
->state
.pipeline
->graphics
.needed_dynamic_state
| ~RADV_CMD_DIRTY_DYNAMIC_ALL
;
4497 /* Index, vertex and streamout buffers don't change context regs, and
4498 * pipeline is already handled.
4500 used_states
&= ~(RADV_CMD_DIRTY_INDEX_BUFFER
|
4501 RADV_CMD_DIRTY_VERTEX_BUFFER
|
4502 RADV_CMD_DIRTY_STREAMOUT_BUFFER
|
4503 RADV_CMD_DIRTY_PIPELINE
);
4505 if (cmd_buffer
->state
.dirty
& used_states
)
4508 uint32_t primitive_reset_index
=
4509 radv_get_primitive_reset_index(cmd_buffer
);
4511 if (info
->indexed
&& state
->pipeline
->graphics
.prim_restart_enable
&&
4512 primitive_reset_index
!= state
->last_primitive_reset_index
)
4519 radv_emit_all_graphics_states(struct radv_cmd_buffer
*cmd_buffer
,
4520 const struct radv_draw_info
*info
)
4522 bool late_scissor_emission
;
4524 if ((cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
) ||
4525 cmd_buffer
->state
.emitted_pipeline
!= cmd_buffer
->state
.pipeline
)
4526 radv_emit_rbplus_state(cmd_buffer
);
4528 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
)
4529 radv_emit_graphics_pipeline(cmd_buffer
);
4531 /* This should be before the cmd_buffer->state.dirty is cleared
4532 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4533 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4534 late_scissor_emission
=
4535 radv_need_late_scissor_emission(cmd_buffer
, info
);
4537 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
)
4538 radv_emit_framebuffer_state(cmd_buffer
);
4540 if (info
->indexed
) {
4541 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_INDEX_BUFFER
)
4542 radv_emit_index_buffer(cmd_buffer
);
4544 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4545 * so the state must be re-emitted before the next indexed
4548 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4549 cmd_buffer
->state
.last_index_type
= -1;
4550 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
4554 radv_cmd_buffer_flush_dynamic_state(cmd_buffer
);
4556 radv_emit_draw_registers(cmd_buffer
, info
);
4558 if (late_scissor_emission
)
4559 radv_emit_scissor(cmd_buffer
);
4563 radv_draw(struct radv_cmd_buffer
*cmd_buffer
,
4564 const struct radv_draw_info
*info
)
4566 struct radeon_info
*rad_info
=
4567 &cmd_buffer
->device
->physical_device
->rad_info
;
4569 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
4570 bool pipeline_is_dirty
=
4571 (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
) &&
4572 cmd_buffer
->state
.pipeline
!= cmd_buffer
->state
.emitted_pipeline
;
4574 ASSERTED
unsigned cdw_max
=
4575 radeon_check_space(cmd_buffer
->device
->ws
,
4576 cmd_buffer
->cs
, 4096);
4578 if (likely(!info
->indirect
)) {
4579 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4580 * no workaround for indirect draws, but we can at least skip
4583 if (unlikely(!info
->instance_count
))
4586 /* Handle count == 0. */
4587 if (unlikely(!info
->count
&& !info
->strmout_buffer
))
4591 /* Use optimal packet order based on whether we need to sync the
4594 if (cmd_buffer
->state
.flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4595 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4596 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
4597 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)) {
4598 /* If we have to wait for idle, set all states first, so that
4599 * all SET packets are processed in parallel with previous draw
4600 * calls. Then upload descriptors, set shader pointers, and
4601 * draw, and prefetch at the end. This ensures that the time
4602 * the CUs are idle is very short. (there are only SET_SH
4603 * packets between the wait and the draw)
4605 radv_emit_all_graphics_states(cmd_buffer
, info
);
4606 si_emit_cache_flush(cmd_buffer
);
4607 /* <-- CUs are idle here --> */
4609 radv_upload_graphics_shader_descriptors(cmd_buffer
, pipeline_is_dirty
);
4611 radv_emit_draw_packets(cmd_buffer
, info
);
4612 /* <-- CUs are busy here --> */
4614 /* Start prefetches after the draw has been started. Both will
4615 * run in parallel, but starting the draw first is more
4618 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
4619 radv_emit_prefetch_L2(cmd_buffer
,
4620 cmd_buffer
->state
.pipeline
, false);
4623 /* If we don't wait for idle, start prefetches first, then set
4624 * states, and draw at the end.
4626 si_emit_cache_flush(cmd_buffer
);
4628 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
4629 /* Only prefetch the vertex shader and VBO descriptors
4630 * in order to start the draw as soon as possible.
4632 radv_emit_prefetch_L2(cmd_buffer
,
4633 cmd_buffer
->state
.pipeline
, true);
4636 radv_upload_graphics_shader_descriptors(cmd_buffer
, pipeline_is_dirty
);
4638 radv_emit_all_graphics_states(cmd_buffer
, info
);
4639 radv_emit_draw_packets(cmd_buffer
, info
);
4641 /* Prefetch the remaining shaders after the draw has been
4644 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
4645 radv_emit_prefetch_L2(cmd_buffer
,
4646 cmd_buffer
->state
.pipeline
, false);
4650 /* Workaround for a VGT hang when streamout is enabled.
4651 * It must be done after drawing.
4653 if (cmd_buffer
->state
.streamout
.streamout_enabled
&&
4654 (rad_info
->family
== CHIP_HAWAII
||
4655 rad_info
->family
== CHIP_TONGA
||
4656 rad_info
->family
== CHIP_FIJI
)) {
4657 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC
;
4660 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4661 radv_cmd_buffer_after_draw(cmd_buffer
, RADV_CMD_FLAG_PS_PARTIAL_FLUSH
);
4665 VkCommandBuffer commandBuffer
,
4666 uint32_t vertexCount
,
4667 uint32_t instanceCount
,
4668 uint32_t firstVertex
,
4669 uint32_t firstInstance
)
4671 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4672 struct radv_draw_info info
= {};
4674 info
.count
= vertexCount
;
4675 info
.instance_count
= instanceCount
;
4676 info
.first_instance
= firstInstance
;
4677 info
.vertex_offset
= firstVertex
;
4679 radv_draw(cmd_buffer
, &info
);
4682 void radv_CmdDrawIndexed(
4683 VkCommandBuffer commandBuffer
,
4684 uint32_t indexCount
,
4685 uint32_t instanceCount
,
4686 uint32_t firstIndex
,
4687 int32_t vertexOffset
,
4688 uint32_t firstInstance
)
4690 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4691 struct radv_draw_info info
= {};
4693 info
.indexed
= true;
4694 info
.count
= indexCount
;
4695 info
.instance_count
= instanceCount
;
4696 info
.first_index
= firstIndex
;
4697 info
.vertex_offset
= vertexOffset
;
4698 info
.first_instance
= firstInstance
;
4700 radv_draw(cmd_buffer
, &info
);
4703 void radv_CmdDrawIndirect(
4704 VkCommandBuffer commandBuffer
,
4706 VkDeviceSize offset
,
4710 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4711 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4712 struct radv_draw_info info
= {};
4714 info
.count
= drawCount
;
4715 info
.indirect
= buffer
;
4716 info
.indirect_offset
= offset
;
4717 info
.stride
= stride
;
4719 radv_draw(cmd_buffer
, &info
);
4722 void radv_CmdDrawIndexedIndirect(
4723 VkCommandBuffer commandBuffer
,
4725 VkDeviceSize offset
,
4729 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4730 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4731 struct radv_draw_info info
= {};
4733 info
.indexed
= true;
4734 info
.count
= drawCount
;
4735 info
.indirect
= buffer
;
4736 info
.indirect_offset
= offset
;
4737 info
.stride
= stride
;
4739 radv_draw(cmd_buffer
, &info
);
4742 void radv_CmdDrawIndirectCountKHR(
4743 VkCommandBuffer commandBuffer
,
4745 VkDeviceSize offset
,
4746 VkBuffer _countBuffer
,
4747 VkDeviceSize countBufferOffset
,
4748 uint32_t maxDrawCount
,
4751 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4752 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4753 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
4754 struct radv_draw_info info
= {};
4756 info
.count
= maxDrawCount
;
4757 info
.indirect
= buffer
;
4758 info
.indirect_offset
= offset
;
4759 info
.count_buffer
= count_buffer
;
4760 info
.count_buffer_offset
= countBufferOffset
;
4761 info
.stride
= stride
;
4763 radv_draw(cmd_buffer
, &info
);
4766 void radv_CmdDrawIndexedIndirectCountKHR(
4767 VkCommandBuffer commandBuffer
,
4769 VkDeviceSize offset
,
4770 VkBuffer _countBuffer
,
4771 VkDeviceSize countBufferOffset
,
4772 uint32_t maxDrawCount
,
4775 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4776 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4777 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
4778 struct radv_draw_info info
= {};
4780 info
.indexed
= true;
4781 info
.count
= maxDrawCount
;
4782 info
.indirect
= buffer
;
4783 info
.indirect_offset
= offset
;
4784 info
.count_buffer
= count_buffer
;
4785 info
.count_buffer_offset
= countBufferOffset
;
4786 info
.stride
= stride
;
4788 radv_draw(cmd_buffer
, &info
);
4791 struct radv_dispatch_info
{
4793 * Determine the layout of the grid (in block units) to be used.
4798 * A starting offset for the grid. If unaligned is set, the offset
4799 * must still be aligned.
4801 uint32_t offsets
[3];
4803 * Whether it's an unaligned compute dispatch.
4808 * Indirect compute parameters resource.
4810 struct radv_buffer
*indirect
;
4811 uint64_t indirect_offset
;
4815 radv_emit_dispatch_packets(struct radv_cmd_buffer
*cmd_buffer
,
4816 const struct radv_dispatch_info
*info
)
4818 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
4819 struct radv_shader_variant
*compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
4820 unsigned dispatch_initiator
= cmd_buffer
->device
->dispatch_initiator
;
4821 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
4822 bool predicating
= cmd_buffer
->state
.predicating
;
4823 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4824 struct radv_userdata_info
*loc
;
4826 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_COMPUTE
,
4827 AC_UD_CS_GRID_SIZE
);
4829 ASSERTED
unsigned cdw_max
= radeon_check_space(ws
, cs
, 25);
4831 if (info
->indirect
) {
4832 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
4834 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
4836 radv_cs_add_buffer(ws
, cs
, info
->indirect
->bo
);
4838 if (loc
->sgpr_idx
!= -1) {
4839 for (unsigned i
= 0; i
< 3; ++i
) {
4840 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
4841 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
4842 COPY_DATA_DST_SEL(COPY_DATA_REG
));
4843 radeon_emit(cs
, (va
+ 4 * i
));
4844 radeon_emit(cs
, (va
+ 4 * i
) >> 32);
4845 radeon_emit(cs
, ((R_00B900_COMPUTE_USER_DATA_0
4846 + loc
->sgpr_idx
* 4) >> 2) + i
);
4851 if (radv_cmd_buffer_uses_mec(cmd_buffer
)) {
4852 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 2, predicating
) |
4853 PKT3_SHADER_TYPE_S(1));
4854 radeon_emit(cs
, va
);
4855 radeon_emit(cs
, va
>> 32);
4856 radeon_emit(cs
, dispatch_initiator
);
4858 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0) |
4859 PKT3_SHADER_TYPE_S(1));
4861 radeon_emit(cs
, va
);
4862 radeon_emit(cs
, va
>> 32);
4864 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 1, predicating
) |
4865 PKT3_SHADER_TYPE_S(1));
4867 radeon_emit(cs
, dispatch_initiator
);
4870 unsigned blocks
[3] = { info
->blocks
[0], info
->blocks
[1], info
->blocks
[2] };
4871 unsigned offsets
[3] = { info
->offsets
[0], info
->offsets
[1], info
->offsets
[2] };
4873 if (info
->unaligned
) {
4874 unsigned *cs_block_size
= compute_shader
->info
.cs
.block_size
;
4875 unsigned remainder
[3];
4877 /* If aligned, these should be an entire block size,
4880 remainder
[0] = blocks
[0] + cs_block_size
[0] -
4881 align_u32_npot(blocks
[0], cs_block_size
[0]);
4882 remainder
[1] = blocks
[1] + cs_block_size
[1] -
4883 align_u32_npot(blocks
[1], cs_block_size
[1]);
4884 remainder
[2] = blocks
[2] + cs_block_size
[2] -
4885 align_u32_npot(blocks
[2], cs_block_size
[2]);
4887 blocks
[0] = round_up_u32(blocks
[0], cs_block_size
[0]);
4888 blocks
[1] = round_up_u32(blocks
[1], cs_block_size
[1]);
4889 blocks
[2] = round_up_u32(blocks
[2], cs_block_size
[2]);
4891 for(unsigned i
= 0; i
< 3; ++i
) {
4892 assert(offsets
[i
] % cs_block_size
[i
] == 0);
4893 offsets
[i
] /= cs_block_size
[i
];
4896 radeon_set_sh_reg_seq(cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
4898 S_00B81C_NUM_THREAD_FULL(cs_block_size
[0]) |
4899 S_00B81C_NUM_THREAD_PARTIAL(remainder
[0]));
4901 S_00B81C_NUM_THREAD_FULL(cs_block_size
[1]) |
4902 S_00B81C_NUM_THREAD_PARTIAL(remainder
[1]));
4904 S_00B81C_NUM_THREAD_FULL(cs_block_size
[2]) |
4905 S_00B81C_NUM_THREAD_PARTIAL(remainder
[2]));
4907 dispatch_initiator
|= S_00B800_PARTIAL_TG_EN(1);
4910 if (loc
->sgpr_idx
!= -1) {
4911 assert(loc
->num_sgprs
== 3);
4913 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
+
4914 loc
->sgpr_idx
* 4, 3);
4915 radeon_emit(cs
, blocks
[0]);
4916 radeon_emit(cs
, blocks
[1]);
4917 radeon_emit(cs
, blocks
[2]);
4920 if (offsets
[0] || offsets
[1] || offsets
[2]) {
4921 radeon_set_sh_reg_seq(cs
, R_00B810_COMPUTE_START_X
, 3);
4922 radeon_emit(cs
, offsets
[0]);
4923 radeon_emit(cs
, offsets
[1]);
4924 radeon_emit(cs
, offsets
[2]);
4926 /* The blocks in the packet are not counts but end values. */
4927 for (unsigned i
= 0; i
< 3; ++i
)
4928 blocks
[i
] += offsets
[i
];
4930 dispatch_initiator
|= S_00B800_FORCE_START_AT_000(1);
4933 radeon_emit(cs
, PKT3(PKT3_DISPATCH_DIRECT
, 3, predicating
) |
4934 PKT3_SHADER_TYPE_S(1));
4935 radeon_emit(cs
, blocks
[0]);
4936 radeon_emit(cs
, blocks
[1]);
4937 radeon_emit(cs
, blocks
[2]);
4938 radeon_emit(cs
, dispatch_initiator
);
4941 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4945 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
4947 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
4948 radv_flush_constants(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
4952 radv_dispatch(struct radv_cmd_buffer
*cmd_buffer
,
4953 const struct radv_dispatch_info
*info
)
4955 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
4957 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
4958 bool pipeline_is_dirty
= pipeline
&&
4959 pipeline
!= cmd_buffer
->state
.emitted_compute_pipeline
;
4961 if (cmd_buffer
->state
.flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4962 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4963 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
4964 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)) {
4965 /* If we have to wait for idle, set all states first, so that
4966 * all SET packets are processed in parallel with previous draw
4967 * calls. Then upload descriptors, set shader pointers, and
4968 * dispatch, and prefetch at the end. This ensures that the
4969 * time the CUs are idle is very short. (there are only SET_SH
4970 * packets between the wait and the draw)
4972 radv_emit_compute_pipeline(cmd_buffer
);
4973 si_emit_cache_flush(cmd_buffer
);
4974 /* <-- CUs are idle here --> */
4976 radv_upload_compute_shader_descriptors(cmd_buffer
);
4978 radv_emit_dispatch_packets(cmd_buffer
, info
);
4979 /* <-- CUs are busy here --> */
4981 /* Start prefetches after the dispatch has been started. Both
4982 * will run in parallel, but starting the dispatch first is
4985 if (has_prefetch
&& pipeline_is_dirty
) {
4986 radv_emit_shader_prefetch(cmd_buffer
,
4987 pipeline
->shaders
[MESA_SHADER_COMPUTE
]);
4990 /* If we don't wait for idle, start prefetches first, then set
4991 * states, and dispatch at the end.
4993 si_emit_cache_flush(cmd_buffer
);
4995 if (has_prefetch
&& pipeline_is_dirty
) {
4996 radv_emit_shader_prefetch(cmd_buffer
,
4997 pipeline
->shaders
[MESA_SHADER_COMPUTE
]);
5000 radv_upload_compute_shader_descriptors(cmd_buffer
);
5002 radv_emit_compute_pipeline(cmd_buffer
);
5003 radv_emit_dispatch_packets(cmd_buffer
, info
);
5006 radv_cmd_buffer_after_draw(cmd_buffer
, RADV_CMD_FLAG_CS_PARTIAL_FLUSH
);
5009 void radv_CmdDispatchBase(
5010 VkCommandBuffer commandBuffer
,
5018 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5019 struct radv_dispatch_info info
= {};
5025 info
.offsets
[0] = base_x
;
5026 info
.offsets
[1] = base_y
;
5027 info
.offsets
[2] = base_z
;
5028 radv_dispatch(cmd_buffer
, &info
);
5031 void radv_CmdDispatch(
5032 VkCommandBuffer commandBuffer
,
5037 radv_CmdDispatchBase(commandBuffer
, 0, 0, 0, x
, y
, z
);
5040 void radv_CmdDispatchIndirect(
5041 VkCommandBuffer commandBuffer
,
5043 VkDeviceSize offset
)
5045 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5046 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
5047 struct radv_dispatch_info info
= {};
5049 info
.indirect
= buffer
;
5050 info
.indirect_offset
= offset
;
5052 radv_dispatch(cmd_buffer
, &info
);
5055 void radv_unaligned_dispatch(
5056 struct radv_cmd_buffer
*cmd_buffer
,
5061 struct radv_dispatch_info info
= {};
5068 radv_dispatch(cmd_buffer
, &info
);
5071 void radv_CmdEndRenderPass(
5072 VkCommandBuffer commandBuffer
)
5074 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5076 radv_subpass_barrier(cmd_buffer
, &cmd_buffer
->state
.pass
->end_barrier
);
5078 radv_cmd_buffer_end_subpass(cmd_buffer
);
5080 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
5081 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.subpass_sample_locs
);
5083 cmd_buffer
->state
.pass
= NULL
;
5084 cmd_buffer
->state
.subpass
= NULL
;
5085 cmd_buffer
->state
.attachments
= NULL
;
5086 cmd_buffer
->state
.framebuffer
= NULL
;
5087 cmd_buffer
->state
.subpass_sample_locs
= NULL
;
5090 void radv_CmdEndRenderPass2KHR(
5091 VkCommandBuffer commandBuffer
,
5092 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
5094 radv_CmdEndRenderPass(commandBuffer
);
5098 * For HTILE we have the following interesting clear words:
5099 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
5100 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
5101 * 0xfffffff0: Clear depth to 1.0
5102 * 0x00000000: Clear depth to 0.0
5104 static void radv_initialize_htile(struct radv_cmd_buffer
*cmd_buffer
,
5105 struct radv_image
*image
,
5106 const VkImageSubresourceRange
*range
,
5107 uint32_t clear_word
)
5109 assert(range
->baseMipLevel
== 0);
5110 assert(range
->levelCount
== 1 || range
->levelCount
== VK_REMAINING_ARRAY_LAYERS
);
5111 VkImageAspectFlags aspects
= VK_IMAGE_ASPECT_DEPTH_BIT
;
5112 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
5113 VkClearDepthStencilValue value
= {};
5115 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
5116 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
5118 state
->flush_bits
|= radv_clear_htile(cmd_buffer
, image
, range
, clear_word
);
5120 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
5122 if (vk_format_is_stencil(image
->vk_format
))
5123 aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
5125 radv_set_ds_clear_metadata(cmd_buffer
, image
, range
, value
, aspects
);
5127 if (radv_image_is_tc_compat_htile(image
)) {
5128 /* Initialize the TC-compat metada value to 0 because by
5129 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
5130 * need have to conditionally update its value when performing
5131 * a fast depth clear.
5133 radv_set_tc_compat_zrange_metadata(cmd_buffer
, image
, range
, 0);
5137 static void radv_handle_depth_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
5138 struct radv_image
*image
,
5139 VkImageLayout src_layout
,
5140 bool src_render_loop
,
5141 VkImageLayout dst_layout
,
5142 bool dst_render_loop
,
5143 unsigned src_queue_mask
,
5144 unsigned dst_queue_mask
,
5145 const VkImageSubresourceRange
*range
,
5146 struct radv_sample_locations_state
*sample_locs
)
5148 if (!radv_image_has_htile(image
))
5151 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
5152 uint32_t clear_value
= vk_format_is_stencil(image
->vk_format
) ? 0xfffff30f : 0xfffc000f;
5154 if (radv_layout_is_htile_compressed(image
, dst_layout
, dst_render_loop
,
5159 radv_initialize_htile(cmd_buffer
, image
, range
, clear_value
);
5160 } else if (!radv_layout_is_htile_compressed(image
, src_layout
, src_render_loop
, src_queue_mask
) &&
5161 radv_layout_is_htile_compressed(image
, dst_layout
, dst_render_loop
, dst_queue_mask
)) {
5162 uint32_t clear_value
= vk_format_is_stencil(image
->vk_format
) ? 0xfffff30f : 0xfffc000f;
5163 radv_initialize_htile(cmd_buffer
, image
, range
, clear_value
);
5164 } else if (radv_layout_is_htile_compressed(image
, src_layout
, src_render_loop
, src_queue_mask
) &&
5165 !radv_layout_is_htile_compressed(image
, dst_layout
, dst_render_loop
, dst_queue_mask
)) {
5166 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
5167 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
5169 radv_decompress_depth_image_inplace(cmd_buffer
, image
, range
,
5172 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
5173 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
5177 static void radv_initialise_cmask(struct radv_cmd_buffer
*cmd_buffer
,
5178 struct radv_image
*image
,
5179 const VkImageSubresourceRange
*range
,
5182 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
5184 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
5185 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5187 state
->flush_bits
|= radv_clear_cmask(cmd_buffer
, image
, range
, value
);
5189 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5192 void radv_initialize_fmask(struct radv_cmd_buffer
*cmd_buffer
,
5193 struct radv_image
*image
,
5194 const VkImageSubresourceRange
*range
)
5196 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
5197 static const uint32_t fmask_clear_values
[4] = {
5203 uint32_t log2_samples
= util_logbase2(image
->info
.samples
);
5204 uint32_t value
= fmask_clear_values
[log2_samples
];
5206 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
5207 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5209 state
->flush_bits
|= radv_clear_fmask(cmd_buffer
, image
, range
, value
);
5211 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5214 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
5215 struct radv_image
*image
,
5216 const VkImageSubresourceRange
*range
, uint32_t value
)
5218 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
5221 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
5222 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5224 state
->flush_bits
|= radv_clear_dcc(cmd_buffer
, image
, range
, value
);
5226 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX8
) {
5227 /* When DCC is enabled with mipmaps, some levels might not
5228 * support fast clears and we have to initialize them as "fully
5231 /* Compute the size of all fast clearable DCC levels. */
5232 for (unsigned i
= 0; i
< image
->planes
[0].surface
.num_dcc_levels
; i
++) {
5233 struct legacy_surf_level
*surf_level
=
5234 &image
->planes
[0].surface
.u
.legacy
.level
[i
];
5235 unsigned dcc_fast_clear_size
=
5236 surf_level
->dcc_slice_fast_clear_size
* image
->info
.array_size
;
5238 if (!dcc_fast_clear_size
)
5241 size
= surf_level
->dcc_offset
+ dcc_fast_clear_size
;
5244 /* Initialize the mipmap levels without DCC. */
5245 if (size
!= image
->planes
[0].surface
.dcc_size
) {
5246 state
->flush_bits
|=
5247 radv_fill_buffer(cmd_buffer
, image
->bo
,
5248 image
->offset
+ image
->dcc_offset
+ size
,
5249 image
->planes
[0].surface
.dcc_size
- size
,
5254 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
5255 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5259 * Initialize DCC/FMASK/CMASK metadata for a color image.
5261 static void radv_init_color_image_metadata(struct radv_cmd_buffer
*cmd_buffer
,
5262 struct radv_image
*image
,
5263 VkImageLayout src_layout
,
5264 bool src_render_loop
,
5265 VkImageLayout dst_layout
,
5266 bool dst_render_loop
,
5267 unsigned src_queue_mask
,
5268 unsigned dst_queue_mask
,
5269 const VkImageSubresourceRange
*range
)
5271 if (radv_image_has_cmask(image
)) {
5272 uint32_t value
= 0xffffffffu
; /* Fully expanded mode. */
5274 /* TODO: clarify this. */
5275 if (radv_image_has_fmask(image
)) {
5276 value
= 0xccccccccu
;
5279 radv_initialise_cmask(cmd_buffer
, image
, range
, value
);
5282 if (radv_image_has_fmask(image
)) {
5283 radv_initialize_fmask(cmd_buffer
, image
, range
);
5286 if (radv_dcc_enabled(image
, range
->baseMipLevel
)) {
5287 uint32_t value
= 0xffffffffu
; /* Fully expanded mode. */
5288 bool need_decompress_pass
= false;
5290 if (radv_layout_dcc_compressed(cmd_buffer
->device
, image
, dst_layout
,
5293 value
= 0x20202020u
;
5294 need_decompress_pass
= true;
5297 radv_initialize_dcc(cmd_buffer
, image
, range
, value
);
5299 radv_update_fce_metadata(cmd_buffer
, image
, range
,
5300 need_decompress_pass
);
5303 if (radv_image_has_cmask(image
) ||
5304 radv_dcc_enabled(image
, range
->baseMipLevel
)) {
5305 uint32_t color_values
[2] = {};
5306 radv_set_color_clear_metadata(cmd_buffer
, image
, range
,
5312 * Handle color image transitions for DCC/FMASK/CMASK.
5314 static void radv_handle_color_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
5315 struct radv_image
*image
,
5316 VkImageLayout src_layout
,
5317 bool src_render_loop
,
5318 VkImageLayout dst_layout
,
5319 bool dst_render_loop
,
5320 unsigned src_queue_mask
,
5321 unsigned dst_queue_mask
,
5322 const VkImageSubresourceRange
*range
)
5324 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
5325 radv_init_color_image_metadata(cmd_buffer
, image
,
5326 src_layout
, src_render_loop
,
5327 dst_layout
, dst_render_loop
,
5328 src_queue_mask
, dst_queue_mask
,
5333 if (radv_dcc_enabled(image
, range
->baseMipLevel
)) {
5334 if (src_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
5335 radv_initialize_dcc(cmd_buffer
, image
, range
, 0xffffffffu
);
5336 } else if (radv_layout_dcc_compressed(cmd_buffer
->device
, image
, src_layout
, src_render_loop
, src_queue_mask
) &&
5337 !radv_layout_dcc_compressed(cmd_buffer
->device
, image
, dst_layout
, dst_render_loop
, dst_queue_mask
)) {
5338 radv_decompress_dcc(cmd_buffer
, image
, range
);
5339 } else if (radv_layout_can_fast_clear(image
, src_layout
, src_render_loop
, src_queue_mask
) &&
5340 !radv_layout_can_fast_clear(image
, dst_layout
, dst_render_loop
, dst_queue_mask
)) {
5341 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
5343 } else if (radv_image_has_cmask(image
) || radv_image_has_fmask(image
)) {
5344 bool fce_eliminate
= false, fmask_expand
= false;
5346 if (radv_layout_can_fast_clear(image
, src_layout
, src_render_loop
, src_queue_mask
) &&
5347 !radv_layout_can_fast_clear(image
, dst_layout
, dst_render_loop
, dst_queue_mask
)) {
5348 fce_eliminate
= true;
5351 if (radv_image_has_fmask(image
)) {
5352 if (src_layout
!= VK_IMAGE_LAYOUT_GENERAL
&&
5353 dst_layout
== VK_IMAGE_LAYOUT_GENERAL
) {
5354 /* A FMASK decompress is required before doing
5355 * a MSAA decompress using FMASK.
5357 fmask_expand
= true;
5361 if (fce_eliminate
|| fmask_expand
)
5362 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
5365 radv_expand_fmask_image_inplace(cmd_buffer
, image
, range
);
5369 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
5370 struct radv_image
*image
,
5371 VkImageLayout src_layout
,
5372 bool src_render_loop
,
5373 VkImageLayout dst_layout
,
5374 bool dst_render_loop
,
5375 uint32_t src_family
,
5376 uint32_t dst_family
,
5377 const VkImageSubresourceRange
*range
,
5378 struct radv_sample_locations_state
*sample_locs
)
5380 if (image
->exclusive
&& src_family
!= dst_family
) {
5381 /* This is an acquire or a release operation and there will be
5382 * a corresponding release/acquire. Do the transition in the
5383 * most flexible queue. */
5385 assert(src_family
== cmd_buffer
->queue_family_index
||
5386 dst_family
== cmd_buffer
->queue_family_index
);
5388 if (src_family
== VK_QUEUE_FAMILY_EXTERNAL
||
5389 src_family
== VK_QUEUE_FAMILY_FOREIGN_EXT
)
5392 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_TRANSFER
)
5395 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
5396 (src_family
== RADV_QUEUE_GENERAL
||
5397 dst_family
== RADV_QUEUE_GENERAL
))
5401 if (src_layout
== dst_layout
)
5404 unsigned src_queue_mask
=
5405 radv_image_queue_family_mask(image
, src_family
,
5406 cmd_buffer
->queue_family_index
);
5407 unsigned dst_queue_mask
=
5408 radv_image_queue_family_mask(image
, dst_family
,
5409 cmd_buffer
->queue_family_index
);
5411 if (vk_format_is_depth(image
->vk_format
)) {
5412 radv_handle_depth_image_transition(cmd_buffer
, image
,
5413 src_layout
, src_render_loop
,
5414 dst_layout
, dst_render_loop
,
5415 src_queue_mask
, dst_queue_mask
,
5416 range
, sample_locs
);
5418 radv_handle_color_image_transition(cmd_buffer
, image
,
5419 src_layout
, src_render_loop
,
5420 dst_layout
, dst_render_loop
,
5421 src_queue_mask
, dst_queue_mask
,
5426 struct radv_barrier_info
{
5427 uint32_t eventCount
;
5428 const VkEvent
*pEvents
;
5429 VkPipelineStageFlags srcStageMask
;
5430 VkPipelineStageFlags dstStageMask
;
5434 radv_barrier(struct radv_cmd_buffer
*cmd_buffer
,
5435 uint32_t memoryBarrierCount
,
5436 const VkMemoryBarrier
*pMemoryBarriers
,
5437 uint32_t bufferMemoryBarrierCount
,
5438 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
5439 uint32_t imageMemoryBarrierCount
,
5440 const VkImageMemoryBarrier
*pImageMemoryBarriers
,
5441 const struct radv_barrier_info
*info
)
5443 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5444 enum radv_cmd_flush_bits src_flush_bits
= 0;
5445 enum radv_cmd_flush_bits dst_flush_bits
= 0;
5447 for (unsigned i
= 0; i
< info
->eventCount
; ++i
) {
5448 RADV_FROM_HANDLE(radv_event
, event
, info
->pEvents
[i
]);
5449 uint64_t va
= radv_buffer_get_va(event
->bo
);
5451 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, event
->bo
);
5453 ASSERTED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 7);
5455 radv_cp_wait_mem(cs
, WAIT_REG_MEM_EQUAL
, va
, 1, 0xffffffff);
5456 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
5459 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
5460 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pMemoryBarriers
[i
].srcAccessMask
,
5462 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pMemoryBarriers
[i
].dstAccessMask
,
5466 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
5467 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].srcAccessMask
,
5469 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].dstAccessMask
,
5473 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
5474 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
5476 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].srcAccessMask
,
5478 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].dstAccessMask
,
5482 /* The Vulkan spec 1.1.98 says:
5484 * "An execution dependency with only
5485 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
5486 * will only prevent that stage from executing in subsequently
5487 * submitted commands. As this stage does not perform any actual
5488 * execution, this is not observable - in effect, it does not delay
5489 * processing of subsequent commands. Similarly an execution dependency
5490 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
5491 * will effectively not wait for any prior commands to complete."
5493 if (info
->dstStageMask
!= VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
)
5494 radv_stage_flush(cmd_buffer
, info
->srcStageMask
);
5495 cmd_buffer
->state
.flush_bits
|= src_flush_bits
;
5497 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
5498 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
5500 const struct VkSampleLocationsInfoEXT
*sample_locs_info
=
5501 vk_find_struct_const(pImageMemoryBarriers
[i
].pNext
,
5502 SAMPLE_LOCATIONS_INFO_EXT
);
5503 struct radv_sample_locations_state sample_locations
= {};
5505 if (sample_locs_info
) {
5506 assert(image
->flags
& VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
);
5507 sample_locations
.per_pixel
= sample_locs_info
->sampleLocationsPerPixel
;
5508 sample_locations
.grid_size
= sample_locs_info
->sampleLocationGridSize
;
5509 sample_locations
.count
= sample_locs_info
->sampleLocationsCount
;
5510 typed_memcpy(&sample_locations
.locations
[0],
5511 sample_locs_info
->pSampleLocations
,
5512 sample_locs_info
->sampleLocationsCount
);
5515 radv_handle_image_transition(cmd_buffer
, image
,
5516 pImageMemoryBarriers
[i
].oldLayout
,
5517 false, /* Outside of a renderpass we are never in a renderloop */
5518 pImageMemoryBarriers
[i
].newLayout
,
5519 false, /* Outside of a renderpass we are never in a renderloop */
5520 pImageMemoryBarriers
[i
].srcQueueFamilyIndex
,
5521 pImageMemoryBarriers
[i
].dstQueueFamilyIndex
,
5522 &pImageMemoryBarriers
[i
].subresourceRange
,
5523 sample_locs_info
? &sample_locations
: NULL
);
5526 /* Make sure CP DMA is idle because the driver might have performed a
5527 * DMA operation for copying or filling buffers/images.
5529 if (info
->srcStageMask
& (VK_PIPELINE_STAGE_TRANSFER_BIT
|
5530 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
))
5531 si_cp_dma_wait_for_idle(cmd_buffer
);
5533 cmd_buffer
->state
.flush_bits
|= dst_flush_bits
;
5536 void radv_CmdPipelineBarrier(
5537 VkCommandBuffer commandBuffer
,
5538 VkPipelineStageFlags srcStageMask
,
5539 VkPipelineStageFlags destStageMask
,
5541 uint32_t memoryBarrierCount
,
5542 const VkMemoryBarrier
* pMemoryBarriers
,
5543 uint32_t bufferMemoryBarrierCount
,
5544 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
5545 uint32_t imageMemoryBarrierCount
,
5546 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
5548 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5549 struct radv_barrier_info info
;
5551 info
.eventCount
= 0;
5552 info
.pEvents
= NULL
;
5553 info
.srcStageMask
= srcStageMask
;
5554 info
.dstStageMask
= destStageMask
;
5556 radv_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
5557 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
5558 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
5562 static void write_event(struct radv_cmd_buffer
*cmd_buffer
,
5563 struct radv_event
*event
,
5564 VkPipelineStageFlags stageMask
,
5567 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5568 uint64_t va
= radv_buffer_get_va(event
->bo
);
5570 si_emit_cache_flush(cmd_buffer
);
5572 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, event
->bo
);
5574 ASSERTED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 21);
5576 /* Flags that only require a top-of-pipe event. */
5577 VkPipelineStageFlags top_of_pipe_flags
=
5578 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
;
5580 /* Flags that only require a post-index-fetch event. */
5581 VkPipelineStageFlags post_index_fetch_flags
=
5583 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
5584 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
;
5586 /* Make sure CP DMA is idle because the driver might have performed a
5587 * DMA operation for copying or filling buffers/images.
5589 if (stageMask
& (VK_PIPELINE_STAGE_TRANSFER_BIT
|
5590 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
))
5591 si_cp_dma_wait_for_idle(cmd_buffer
);
5593 /* TODO: Emit EOS events for syncing PS/CS stages. */
5595 if (!(stageMask
& ~top_of_pipe_flags
)) {
5596 /* Just need to sync the PFP engine. */
5597 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
5598 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
5599 S_370_WR_CONFIRM(1) |
5600 S_370_ENGINE_SEL(V_370_PFP
));
5601 radeon_emit(cs
, va
);
5602 radeon_emit(cs
, va
>> 32);
5603 radeon_emit(cs
, value
);
5604 } else if (!(stageMask
& ~post_index_fetch_flags
)) {
5605 /* Sync ME because PFP reads index and indirect buffers. */
5606 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
5607 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
5608 S_370_WR_CONFIRM(1) |
5609 S_370_ENGINE_SEL(V_370_ME
));
5610 radeon_emit(cs
, va
);
5611 radeon_emit(cs
, va
>> 32);
5612 radeon_emit(cs
, value
);
5614 /* Otherwise, sync all prior GPU work using an EOP event. */
5615 si_cs_emit_write_event_eop(cs
,
5616 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
5617 radv_cmd_buffer_uses_mec(cmd_buffer
),
5618 V_028A90_BOTTOM_OF_PIPE_TS
, 0,
5620 EOP_DATA_SEL_VALUE_32BIT
, va
, value
,
5621 cmd_buffer
->gfx9_eop_bug_va
);
5624 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
5627 void radv_CmdSetEvent(VkCommandBuffer commandBuffer
,
5629 VkPipelineStageFlags stageMask
)
5631 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5632 RADV_FROM_HANDLE(radv_event
, event
, _event
);
5634 write_event(cmd_buffer
, event
, stageMask
, 1);
5637 void radv_CmdResetEvent(VkCommandBuffer commandBuffer
,
5639 VkPipelineStageFlags stageMask
)
5641 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5642 RADV_FROM_HANDLE(radv_event
, event
, _event
);
5644 write_event(cmd_buffer
, event
, stageMask
, 0);
5647 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer
,
5648 uint32_t eventCount
,
5649 const VkEvent
* pEvents
,
5650 VkPipelineStageFlags srcStageMask
,
5651 VkPipelineStageFlags dstStageMask
,
5652 uint32_t memoryBarrierCount
,
5653 const VkMemoryBarrier
* pMemoryBarriers
,
5654 uint32_t bufferMemoryBarrierCount
,
5655 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
5656 uint32_t imageMemoryBarrierCount
,
5657 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
5659 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5660 struct radv_barrier_info info
;
5662 info
.eventCount
= eventCount
;
5663 info
.pEvents
= pEvents
;
5664 info
.srcStageMask
= 0;
5666 radv_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
5667 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
5668 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
5672 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer
,
5673 uint32_t deviceMask
)
5678 /* VK_EXT_conditional_rendering */
5679 void radv_CmdBeginConditionalRenderingEXT(
5680 VkCommandBuffer commandBuffer
,
5681 const VkConditionalRenderingBeginInfoEXT
* pConditionalRenderingBegin
)
5683 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5684 RADV_FROM_HANDLE(radv_buffer
, buffer
, pConditionalRenderingBegin
->buffer
);
5685 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5686 bool draw_visible
= true;
5687 uint64_t pred_value
= 0;
5688 uint64_t va
, new_va
;
5689 unsigned pred_offset
;
5691 va
= radv_buffer_get_va(buffer
->bo
) + pConditionalRenderingBegin
->offset
;
5693 /* By default, if the 32-bit value at offset in buffer memory is zero,
5694 * then the rendering commands are discarded, otherwise they are
5695 * executed as normal. If the inverted flag is set, all commands are
5696 * discarded if the value is non zero.
5698 if (pConditionalRenderingBegin
->flags
&
5699 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT
) {
5700 draw_visible
= false;
5703 si_emit_cache_flush(cmd_buffer
);
5705 /* From the Vulkan spec 1.1.107:
5707 * "If the 32-bit value at offset in buffer memory is zero, then the
5708 * rendering commands are discarded, otherwise they are executed as
5709 * normal. If the value of the predicate in buffer memory changes while
5710 * conditional rendering is active, the rendering commands may be
5711 * discarded in an implementation-dependent way. Some implementations
5712 * may latch the value of the predicate upon beginning conditional
5713 * rendering while others may read it before every rendering command."
5715 * But, the AMD hardware treats the predicate as a 64-bit value which
5716 * means we need a workaround in the driver. Luckily, it's not required
5717 * to support if the value changes when predication is active.
5719 * The workaround is as follows:
5720 * 1) allocate a 64-value in the upload BO and initialize it to 0
5721 * 2) copy the 32-bit predicate value to the upload BO
5722 * 3) use the new allocated VA address for predication
5724 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
5725 * in ME (+ sync PFP) instead of PFP.
5727 radv_cmd_buffer_upload_data(cmd_buffer
, 8, 16, &pred_value
, &pred_offset
);
5729 new_va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
) + pred_offset
;
5731 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
5732 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
5733 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM
) |
5734 COPY_DATA_WR_CONFIRM
);
5735 radeon_emit(cs
, va
);
5736 radeon_emit(cs
, va
>> 32);
5737 radeon_emit(cs
, new_va
);
5738 radeon_emit(cs
, new_va
>> 32);
5740 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
5743 /* Enable predication for this command buffer. */
5744 si_emit_set_predication_state(cmd_buffer
, draw_visible
, new_va
);
5745 cmd_buffer
->state
.predicating
= true;
5747 /* Store conditional rendering user info. */
5748 cmd_buffer
->state
.predication_type
= draw_visible
;
5749 cmd_buffer
->state
.predication_va
= new_va
;
5752 void radv_CmdEndConditionalRenderingEXT(
5753 VkCommandBuffer commandBuffer
)
5755 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5757 /* Disable predication for this command buffer. */
5758 si_emit_set_predication_state(cmd_buffer
, false, 0);
5759 cmd_buffer
->state
.predicating
= false;
5761 /* Reset conditional rendering user info. */
5762 cmd_buffer
->state
.predication_type
= -1;
5763 cmd_buffer
->state
.predication_va
= 0;
5766 /* VK_EXT_transform_feedback */
5767 void radv_CmdBindTransformFeedbackBuffersEXT(
5768 VkCommandBuffer commandBuffer
,
5769 uint32_t firstBinding
,
5770 uint32_t bindingCount
,
5771 const VkBuffer
* pBuffers
,
5772 const VkDeviceSize
* pOffsets
,
5773 const VkDeviceSize
* pSizes
)
5775 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5776 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
5777 uint8_t enabled_mask
= 0;
5779 assert(firstBinding
+ bindingCount
<= MAX_SO_BUFFERS
);
5780 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
5781 uint32_t idx
= firstBinding
+ i
;
5783 sb
[idx
].buffer
= radv_buffer_from_handle(pBuffers
[i
]);
5784 sb
[idx
].offset
= pOffsets
[i
];
5785 sb
[idx
].size
= pSizes
[i
];
5787 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
5788 sb
[idx
].buffer
->bo
);
5790 enabled_mask
|= 1 << idx
;
5793 cmd_buffer
->state
.streamout
.enabled_mask
|= enabled_mask
;
5795 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_STREAMOUT_BUFFER
;
5799 radv_emit_streamout_enable(struct radv_cmd_buffer
*cmd_buffer
)
5801 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
5802 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5804 radeon_set_context_reg_seq(cs
, R_028B94_VGT_STRMOUT_CONFIG
, 2);
5806 S_028B94_STREAMOUT_0_EN(so
->streamout_enabled
) |
5807 S_028B94_RAST_STREAM(0) |
5808 S_028B94_STREAMOUT_1_EN(so
->streamout_enabled
) |
5809 S_028B94_STREAMOUT_2_EN(so
->streamout_enabled
) |
5810 S_028B94_STREAMOUT_3_EN(so
->streamout_enabled
));
5811 radeon_emit(cs
, so
->hw_enabled_mask
&
5812 so
->enabled_stream_buffers_mask
);
5814 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
5818 radv_set_streamout_enable(struct radv_cmd_buffer
*cmd_buffer
, bool enable
)
5820 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
5821 bool old_streamout_enabled
= so
->streamout_enabled
;
5822 uint32_t old_hw_enabled_mask
= so
->hw_enabled_mask
;
5824 so
->streamout_enabled
= enable
;
5826 so
->hw_enabled_mask
= so
->enabled_mask
|
5827 (so
->enabled_mask
<< 4) |
5828 (so
->enabled_mask
<< 8) |
5829 (so
->enabled_mask
<< 12);
5831 if (!cmd_buffer
->device
->physical_device
->use_ngg_streamout
&&
5832 ((old_streamout_enabled
!= so
->streamout_enabled
) ||
5833 (old_hw_enabled_mask
!= so
->hw_enabled_mask
)))
5834 radv_emit_streamout_enable(cmd_buffer
);
5836 if (cmd_buffer
->device
->physical_device
->use_ngg_streamout
)
5837 cmd_buffer
->gds_needed
= true;
5840 static void radv_flush_vgt_streamout(struct radv_cmd_buffer
*cmd_buffer
)
5842 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5843 unsigned reg_strmout_cntl
;
5845 /* The register is at different places on different ASICs. */
5846 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
5847 reg_strmout_cntl
= R_0300FC_CP_STRMOUT_CNTL
;
5848 radeon_set_uconfig_reg(cs
, reg_strmout_cntl
, 0);
5850 reg_strmout_cntl
= R_0084FC_CP_STRMOUT_CNTL
;
5851 radeon_set_config_reg(cs
, reg_strmout_cntl
, 0);
5854 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
5855 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH
) | EVENT_INDEX(0));
5857 radeon_emit(cs
, PKT3(PKT3_WAIT_REG_MEM
, 5, 0));
5858 radeon_emit(cs
, WAIT_REG_MEM_EQUAL
); /* wait until the register is equal to the reference value */
5859 radeon_emit(cs
, reg_strmout_cntl
>> 2); /* register */
5861 radeon_emit(cs
, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
5862 radeon_emit(cs
, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
5863 radeon_emit(cs
, 4); /* poll interval */
5867 radv_emit_streamout_begin(struct radv_cmd_buffer
*cmd_buffer
,
5868 uint32_t firstCounterBuffer
,
5869 uint32_t counterBufferCount
,
5870 const VkBuffer
*pCounterBuffers
,
5871 const VkDeviceSize
*pCounterBufferOffsets
)
5874 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
5875 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
5876 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5879 radv_flush_vgt_streamout(cmd_buffer
);
5881 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
5882 for_each_bit(i
, so
->enabled_mask
) {
5883 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
5884 if (counter_buffer_idx
>= 0 && counter_buffer_idx
>= counterBufferCount
)
5885 counter_buffer_idx
= -1;
5887 /* AMD GCN binds streamout buffers as shader resources.
5888 * VGT only counts primitives and tells the shader through
5891 radeon_set_context_reg_seq(cs
, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0
+ 16*i
, 2);
5892 radeon_emit(cs
, sb
[i
].size
>> 2); /* BUFFER_SIZE (in DW) */
5893 radeon_emit(cs
, so
->stride_in_dw
[i
]); /* VTX_STRIDE (in DW) */
5895 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
5897 if (counter_buffer_idx
>= 0 && pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
]) {
5898 /* The array of counter buffers is optional. */
5899 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
5900 uint64_t va
= radv_buffer_get_va(buffer
->bo
);
5902 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
5905 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
5906 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
5907 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5908 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM
)); /* control */
5909 radeon_emit(cs
, 0); /* unused */
5910 radeon_emit(cs
, 0); /* unused */
5911 radeon_emit(cs
, va
); /* src address lo */
5912 radeon_emit(cs
, va
>> 32); /* src address hi */
5914 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, buffer
->bo
);
5916 /* Start from the beginning. */
5917 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
5918 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
5919 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5920 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET
)); /* control */
5921 radeon_emit(cs
, 0); /* unused */
5922 radeon_emit(cs
, 0); /* unused */
5923 radeon_emit(cs
, 0); /* unused */
5924 radeon_emit(cs
, 0); /* unused */
5928 radv_set_streamout_enable(cmd_buffer
, true);
5932 gfx10_emit_streamout_begin(struct radv_cmd_buffer
*cmd_buffer
,
5933 uint32_t firstCounterBuffer
,
5934 uint32_t counterBufferCount
,
5935 const VkBuffer
*pCounterBuffers
,
5936 const VkDeviceSize
*pCounterBufferOffsets
)
5938 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
5939 unsigned last_target
= util_last_bit(so
->enabled_mask
) - 1;
5940 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5943 assert(cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
);
5944 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
5946 for_each_bit(i
, so
->enabled_mask
) {
5947 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
5948 if (counter_buffer_idx
>= 0 && counter_buffer_idx
>= counterBufferCount
)
5949 counter_buffer_idx
= -1;
5951 bool append
= counter_buffer_idx
>= 0 &&
5952 pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
];
5956 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
5958 va
+= radv_buffer_get_va(buffer
->bo
);
5959 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
5961 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, buffer
->bo
);
5964 radeon_emit(cs
, PKT3(PKT3_DMA_DATA
, 5, 0));
5965 radeon_emit(cs
, S_411_SRC_SEL(append
? V_411_SRC_ADDR_TC_L2
: V_411_DATA
) |
5966 S_411_DST_SEL(V_411_GDS
) |
5967 S_411_CP_SYNC(i
== last_target
));
5968 radeon_emit(cs
, va
);
5969 radeon_emit(cs
, va
>> 32);
5970 radeon_emit(cs
, 4 * i
); /* destination in GDS */
5972 radeon_emit(cs
, S_414_BYTE_COUNT_GFX9(4) |
5973 S_414_DISABLE_WR_CONFIRM_GFX9(i
!= last_target
));
5976 radv_set_streamout_enable(cmd_buffer
, true);
5979 void radv_CmdBeginTransformFeedbackEXT(
5980 VkCommandBuffer commandBuffer
,
5981 uint32_t firstCounterBuffer
,
5982 uint32_t counterBufferCount
,
5983 const VkBuffer
* pCounterBuffers
,
5984 const VkDeviceSize
* pCounterBufferOffsets
)
5986 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5988 if (cmd_buffer
->device
->physical_device
->use_ngg_streamout
) {
5989 gfx10_emit_streamout_begin(cmd_buffer
,
5990 firstCounterBuffer
, counterBufferCount
,
5991 pCounterBuffers
, pCounterBufferOffsets
);
5993 radv_emit_streamout_begin(cmd_buffer
,
5994 firstCounterBuffer
, counterBufferCount
,
5995 pCounterBuffers
, pCounterBufferOffsets
);
6000 radv_emit_streamout_end(struct radv_cmd_buffer
*cmd_buffer
,
6001 uint32_t firstCounterBuffer
,
6002 uint32_t counterBufferCount
,
6003 const VkBuffer
*pCounterBuffers
,
6004 const VkDeviceSize
*pCounterBufferOffsets
)
6006 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
6007 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
6010 radv_flush_vgt_streamout(cmd_buffer
);
6012 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
6013 for_each_bit(i
, so
->enabled_mask
) {
6014 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
6015 if (counter_buffer_idx
>= 0 && counter_buffer_idx
>= counterBufferCount
)
6016 counter_buffer_idx
= -1;
6018 if (counter_buffer_idx
>= 0 && pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
]) {
6019 /* The array of counters buffer is optional. */
6020 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
6021 uint64_t va
= radv_buffer_get_va(buffer
->bo
);
6023 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
6025 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
6026 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
6027 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6028 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE
) |
6029 STRMOUT_STORE_BUFFER_FILLED_SIZE
); /* control */
6030 radeon_emit(cs
, va
); /* dst address lo */
6031 radeon_emit(cs
, va
>> 32); /* dst address hi */
6032 radeon_emit(cs
, 0); /* unused */
6033 radeon_emit(cs
, 0); /* unused */
6035 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, buffer
->bo
);
6038 /* Deactivate transform feedback by zeroing the buffer size.
6039 * The counters (primitives generated, primitives emitted) may
6040 * be enabled even if there is not buffer bound. This ensures
6041 * that the primitives-emitted query won't increment.
6043 radeon_set_context_reg(cs
, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0
+ 16*i
, 0);
6045 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
6048 radv_set_streamout_enable(cmd_buffer
, false);
6052 gfx10_emit_streamout_end(struct radv_cmd_buffer
*cmd_buffer
,
6053 uint32_t firstCounterBuffer
,
6054 uint32_t counterBufferCount
,
6055 const VkBuffer
*pCounterBuffers
,
6056 const VkDeviceSize
*pCounterBufferOffsets
)
6058 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
6059 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
6062 assert(cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
);
6063 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
6065 for_each_bit(i
, so
->enabled_mask
) {
6066 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
6067 if (counter_buffer_idx
>= 0 && counter_buffer_idx
>= counterBufferCount
)
6068 counter_buffer_idx
= -1;
6070 if (counter_buffer_idx
>= 0 && pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
]) {
6071 /* The array of counters buffer is optional. */
6072 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
6073 uint64_t va
= radv_buffer_get_va(buffer
->bo
);
6075 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
6077 si_cs_emit_write_event_eop(cs
,
6078 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
6079 radv_cmd_buffer_uses_mec(cmd_buffer
),
6080 V_028A90_PS_DONE
, 0,
6083 va
, EOP_DATA_GDS(i
, 1), 0);
6087 radv_set_streamout_enable(cmd_buffer
, false);
6090 void radv_CmdEndTransformFeedbackEXT(
6091 VkCommandBuffer commandBuffer
,
6092 uint32_t firstCounterBuffer
,
6093 uint32_t counterBufferCount
,
6094 const VkBuffer
* pCounterBuffers
,
6095 const VkDeviceSize
* pCounterBufferOffsets
)
6097 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
6099 if (cmd_buffer
->device
->physical_device
->use_ngg_streamout
) {
6100 gfx10_emit_streamout_end(cmd_buffer
,
6101 firstCounterBuffer
, counterBufferCount
,
6102 pCounterBuffers
, pCounterBufferOffsets
);
6104 radv_emit_streamout_end(cmd_buffer
,
6105 firstCounterBuffer
, counterBufferCount
,
6106 pCounterBuffers
, pCounterBufferOffsets
);
6110 void radv_CmdDrawIndirectByteCountEXT(
6111 VkCommandBuffer commandBuffer
,
6112 uint32_t instanceCount
,
6113 uint32_t firstInstance
,
6114 VkBuffer _counterBuffer
,
6115 VkDeviceSize counterBufferOffset
,
6116 uint32_t counterOffset
,
6117 uint32_t vertexStride
)
6119 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
6120 RADV_FROM_HANDLE(radv_buffer
, counterBuffer
, _counterBuffer
);
6121 struct radv_draw_info info
= {};
6123 info
.instance_count
= instanceCount
;
6124 info
.first_instance
= firstInstance
;
6125 info
.strmout_buffer
= counterBuffer
;
6126 info
.strmout_buffer_offset
= counterBufferOffset
;
6127 info
.stride
= vertexStride
;
6129 radv_draw(cmd_buffer
, &info
);
6132 /* VK_AMD_buffer_marker */
6133 void radv_CmdWriteBufferMarkerAMD(
6134 VkCommandBuffer commandBuffer
,
6135 VkPipelineStageFlagBits pipelineStage
,
6137 VkDeviceSize dstOffset
,
6140 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
6141 RADV_FROM_HANDLE(radv_buffer
, buffer
, dstBuffer
);
6142 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
6143 uint64_t va
= radv_buffer_get_va(buffer
->bo
) + dstOffset
;
6145 si_emit_cache_flush(cmd_buffer
);
6147 if (!(pipelineStage
& ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
)) {
6148 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
6149 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_IMM
) |
6150 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM
) |
6151 COPY_DATA_WR_CONFIRM
);
6152 radeon_emit(cs
, marker
);
6154 radeon_emit(cs
, va
);
6155 radeon_emit(cs
, va
>> 32);
6157 si_cs_emit_write_event_eop(cs
,
6158 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
6159 radv_cmd_buffer_uses_mec(cmd_buffer
),
6160 V_028A90_BOTTOM_OF_PIPE_TS
, 0,
6162 EOP_DATA_SEL_VALUE_32BIT
,
6164 cmd_buffer
->gfx9_eop_bug_va
);