2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
33 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
41 RADV_PREFETCH_VBO_DESCRIPTORS
= (1 << 0),
42 RADV_PREFETCH_VS
= (1 << 1),
43 RADV_PREFETCH_TCS
= (1 << 2),
44 RADV_PREFETCH_TES
= (1 << 3),
45 RADV_PREFETCH_GS
= (1 << 4),
46 RADV_PREFETCH_PS
= (1 << 5),
47 RADV_PREFETCH_SHADERS
= (RADV_PREFETCH_VS
|
54 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
55 struct radv_image
*image
,
56 VkImageLayout src_layout
,
57 VkImageLayout dst_layout
,
60 const VkImageSubresourceRange
*range
,
61 struct radv_sample_locations_state
*sample_locs
);
63 const struct radv_dynamic_state default_dynamic_state
= {
76 .blend_constants
= { 0.0f
, 0.0f
, 0.0f
, 0.0f
},
81 .stencil_compare_mask
= {
85 .stencil_write_mask
= {
89 .stencil_reference
= {
96 radv_bind_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
,
97 const struct radv_dynamic_state
*src
)
99 struct radv_dynamic_state
*dest
= &cmd_buffer
->state
.dynamic
;
100 uint32_t copy_mask
= src
->mask
;
101 uint32_t dest_mask
= 0;
103 /* Make sure to copy the number of viewports/scissors because they can
104 * only be specified at pipeline creation time.
106 dest
->viewport
.count
= src
->viewport
.count
;
107 dest
->scissor
.count
= src
->scissor
.count
;
108 dest
->discard_rectangle
.count
= src
->discard_rectangle
.count
;
109 dest
->sample_location
.count
= src
->sample_location
.count
;
111 if (copy_mask
& RADV_DYNAMIC_VIEWPORT
) {
112 if (memcmp(&dest
->viewport
.viewports
, &src
->viewport
.viewports
,
113 src
->viewport
.count
* sizeof(VkViewport
))) {
114 typed_memcpy(dest
->viewport
.viewports
,
115 src
->viewport
.viewports
,
116 src
->viewport
.count
);
117 dest_mask
|= RADV_DYNAMIC_VIEWPORT
;
121 if (copy_mask
& RADV_DYNAMIC_SCISSOR
) {
122 if (memcmp(&dest
->scissor
.scissors
, &src
->scissor
.scissors
,
123 src
->scissor
.count
* sizeof(VkRect2D
))) {
124 typed_memcpy(dest
->scissor
.scissors
,
125 src
->scissor
.scissors
, src
->scissor
.count
);
126 dest_mask
|= RADV_DYNAMIC_SCISSOR
;
130 if (copy_mask
& RADV_DYNAMIC_LINE_WIDTH
) {
131 if (dest
->line_width
!= src
->line_width
) {
132 dest
->line_width
= src
->line_width
;
133 dest_mask
|= RADV_DYNAMIC_LINE_WIDTH
;
137 if (copy_mask
& RADV_DYNAMIC_DEPTH_BIAS
) {
138 if (memcmp(&dest
->depth_bias
, &src
->depth_bias
,
139 sizeof(src
->depth_bias
))) {
140 dest
->depth_bias
= src
->depth_bias
;
141 dest_mask
|= RADV_DYNAMIC_DEPTH_BIAS
;
145 if (copy_mask
& RADV_DYNAMIC_BLEND_CONSTANTS
) {
146 if (memcmp(&dest
->blend_constants
, &src
->blend_constants
,
147 sizeof(src
->blend_constants
))) {
148 typed_memcpy(dest
->blend_constants
,
149 src
->blend_constants
, 4);
150 dest_mask
|= RADV_DYNAMIC_BLEND_CONSTANTS
;
154 if (copy_mask
& RADV_DYNAMIC_DEPTH_BOUNDS
) {
155 if (memcmp(&dest
->depth_bounds
, &src
->depth_bounds
,
156 sizeof(src
->depth_bounds
))) {
157 dest
->depth_bounds
= src
->depth_bounds
;
158 dest_mask
|= RADV_DYNAMIC_DEPTH_BOUNDS
;
162 if (copy_mask
& RADV_DYNAMIC_STENCIL_COMPARE_MASK
) {
163 if (memcmp(&dest
->stencil_compare_mask
,
164 &src
->stencil_compare_mask
,
165 sizeof(src
->stencil_compare_mask
))) {
166 dest
->stencil_compare_mask
= src
->stencil_compare_mask
;
167 dest_mask
|= RADV_DYNAMIC_STENCIL_COMPARE_MASK
;
171 if (copy_mask
& RADV_DYNAMIC_STENCIL_WRITE_MASK
) {
172 if (memcmp(&dest
->stencil_write_mask
, &src
->stencil_write_mask
,
173 sizeof(src
->stencil_write_mask
))) {
174 dest
->stencil_write_mask
= src
->stencil_write_mask
;
175 dest_mask
|= RADV_DYNAMIC_STENCIL_WRITE_MASK
;
179 if (copy_mask
& RADV_DYNAMIC_STENCIL_REFERENCE
) {
180 if (memcmp(&dest
->stencil_reference
, &src
->stencil_reference
,
181 sizeof(src
->stencil_reference
))) {
182 dest
->stencil_reference
= src
->stencil_reference
;
183 dest_mask
|= RADV_DYNAMIC_STENCIL_REFERENCE
;
187 if (copy_mask
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
188 if (memcmp(&dest
->discard_rectangle
.rectangles
, &src
->discard_rectangle
.rectangles
,
189 src
->discard_rectangle
.count
* sizeof(VkRect2D
))) {
190 typed_memcpy(dest
->discard_rectangle
.rectangles
,
191 src
->discard_rectangle
.rectangles
,
192 src
->discard_rectangle
.count
);
193 dest_mask
|= RADV_DYNAMIC_DISCARD_RECTANGLE
;
197 if (copy_mask
& RADV_DYNAMIC_SAMPLE_LOCATIONS
) {
198 if (dest
->sample_location
.per_pixel
!= src
->sample_location
.per_pixel
||
199 dest
->sample_location
.grid_size
.width
!= src
->sample_location
.grid_size
.width
||
200 dest
->sample_location
.grid_size
.height
!= src
->sample_location
.grid_size
.height
||
201 memcmp(&dest
->sample_location
.locations
,
202 &src
->sample_location
.locations
,
203 src
->sample_location
.count
* sizeof(VkSampleLocationEXT
))) {
204 dest
->sample_location
.per_pixel
= src
->sample_location
.per_pixel
;
205 dest
->sample_location
.grid_size
= src
->sample_location
.grid_size
;
206 typed_memcpy(dest
->sample_location
.locations
,
207 src
->sample_location
.locations
,
208 src
->sample_location
.count
);
209 dest_mask
|= RADV_DYNAMIC_SAMPLE_LOCATIONS
;
213 cmd_buffer
->state
.dirty
|= dest_mask
;
217 radv_bind_streamout_state(struct radv_cmd_buffer
*cmd_buffer
,
218 struct radv_pipeline
*pipeline
)
220 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
221 struct radv_shader_info
*info
;
223 if (!pipeline
->streamout_shader
)
226 info
= &pipeline
->streamout_shader
->info
.info
;
227 for (int i
= 0; i
< MAX_SO_BUFFERS
; i
++)
228 so
->stride_in_dw
[i
] = info
->so
.strides
[i
];
230 so
->enabled_stream_buffers_mask
= info
->so
.enabled_stream_buffers_mask
;
233 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
)
235 return cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
236 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
239 enum ring_type
radv_queue_family_to_ring(int f
) {
241 case RADV_QUEUE_GENERAL
:
243 case RADV_QUEUE_COMPUTE
:
245 case RADV_QUEUE_TRANSFER
:
248 unreachable("Unknown queue family");
252 static VkResult
radv_create_cmd_buffer(
253 struct radv_device
* device
,
254 struct radv_cmd_pool
* pool
,
255 VkCommandBufferLevel level
,
256 VkCommandBuffer
* pCommandBuffer
)
258 struct radv_cmd_buffer
*cmd_buffer
;
260 cmd_buffer
= vk_zalloc(&pool
->alloc
, sizeof(*cmd_buffer
), 8,
261 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
262 if (cmd_buffer
== NULL
)
263 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
265 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
266 cmd_buffer
->device
= device
;
267 cmd_buffer
->pool
= pool
;
268 cmd_buffer
->level
= level
;
271 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
272 cmd_buffer
->queue_family_index
= pool
->queue_family_index
;
275 /* Init the pool_link so we can safely call list_del when we destroy
278 list_inithead(&cmd_buffer
->pool_link
);
279 cmd_buffer
->queue_family_index
= RADV_QUEUE_GENERAL
;
282 ring
= radv_queue_family_to_ring(cmd_buffer
->queue_family_index
);
284 cmd_buffer
->cs
= device
->ws
->cs_create(device
->ws
, ring
);
285 if (!cmd_buffer
->cs
) {
286 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
287 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
290 *pCommandBuffer
= radv_cmd_buffer_to_handle(cmd_buffer
);
292 list_inithead(&cmd_buffer
->upload
.list
);
298 radv_cmd_buffer_destroy(struct radv_cmd_buffer
*cmd_buffer
)
300 list_del(&cmd_buffer
->pool_link
);
302 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
303 &cmd_buffer
->upload
.list
, list
) {
304 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
309 if (cmd_buffer
->upload
.upload_bo
)
310 cmd_buffer
->device
->ws
->buffer_destroy(cmd_buffer
->upload
.upload_bo
);
311 cmd_buffer
->device
->ws
->cs_destroy(cmd_buffer
->cs
);
313 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++)
314 free(cmd_buffer
->descriptors
[i
].push_set
.set
.mapped_ptr
);
316 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
320 radv_reset_cmd_buffer(struct radv_cmd_buffer
*cmd_buffer
)
322 cmd_buffer
->device
->ws
->cs_reset(cmd_buffer
->cs
);
324 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
325 &cmd_buffer
->upload
.list
, list
) {
326 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
331 cmd_buffer
->push_constant_stages
= 0;
332 cmd_buffer
->scratch_size_needed
= 0;
333 cmd_buffer
->compute_scratch_size_needed
= 0;
334 cmd_buffer
->esgs_ring_size_needed
= 0;
335 cmd_buffer
->gsvs_ring_size_needed
= 0;
336 cmd_buffer
->tess_rings_needed
= false;
337 cmd_buffer
->sample_positions_needed
= false;
339 if (cmd_buffer
->upload
.upload_bo
)
340 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
341 cmd_buffer
->upload
.upload_bo
);
342 cmd_buffer
->upload
.offset
= 0;
344 cmd_buffer
->record_result
= VK_SUCCESS
;
346 memset(cmd_buffer
->vertex_bindings
, 0, sizeof(cmd_buffer
->vertex_bindings
));
348 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++) {
349 cmd_buffer
->descriptors
[i
].dirty
= 0;
350 cmd_buffer
->descriptors
[i
].valid
= 0;
351 cmd_buffer
->descriptors
[i
].push_dirty
= false;
354 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
355 cmd_buffer
->queue_family_index
== RADV_QUEUE_GENERAL
) {
356 unsigned num_db
= cmd_buffer
->device
->physical_device
->rad_info
.num_render_backends
;
357 unsigned fence_offset
, eop_bug_offset
;
360 radv_cmd_buffer_upload_alloc(cmd_buffer
, 8, 8, &fence_offset
,
363 cmd_buffer
->gfx9_fence_va
=
364 radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
365 cmd_buffer
->gfx9_fence_va
+= fence_offset
;
367 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
368 /* Allocate a buffer for the EOP bug on GFX9. */
369 radv_cmd_buffer_upload_alloc(cmd_buffer
, 16 * num_db
, 8,
370 &eop_bug_offset
, &fence_ptr
);
371 cmd_buffer
->gfx9_eop_bug_va
=
372 radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
373 cmd_buffer
->gfx9_eop_bug_va
+= eop_bug_offset
;
377 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_INITIAL
;
379 return cmd_buffer
->record_result
;
383 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer
*cmd_buffer
,
387 struct radeon_winsys_bo
*bo
;
388 struct radv_cmd_buffer_upload
*upload
;
389 struct radv_device
*device
= cmd_buffer
->device
;
391 new_size
= MAX2(min_needed
, 16 * 1024);
392 new_size
= MAX2(new_size
, 2 * cmd_buffer
->upload
.size
);
394 bo
= device
->ws
->buffer_create(device
->ws
,
397 RADEON_FLAG_CPU_ACCESS
|
398 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
400 RADV_BO_PRIORITY_UPLOAD_BUFFER
);
403 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
407 radv_cs_add_buffer(device
->ws
, cmd_buffer
->cs
, bo
);
408 if (cmd_buffer
->upload
.upload_bo
) {
409 upload
= malloc(sizeof(*upload
));
412 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
413 device
->ws
->buffer_destroy(bo
);
417 memcpy(upload
, &cmd_buffer
->upload
, sizeof(*upload
));
418 list_add(&upload
->list
, &cmd_buffer
->upload
.list
);
421 cmd_buffer
->upload
.upload_bo
= bo
;
422 cmd_buffer
->upload
.size
= new_size
;
423 cmd_buffer
->upload
.offset
= 0;
424 cmd_buffer
->upload
.map
= device
->ws
->buffer_map(cmd_buffer
->upload
.upload_bo
);
426 if (!cmd_buffer
->upload
.map
) {
427 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
435 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
438 unsigned *out_offset
,
441 assert(util_is_power_of_two_nonzero(alignment
));
443 uint64_t offset
= align(cmd_buffer
->upload
.offset
, alignment
);
444 if (offset
+ size
> cmd_buffer
->upload
.size
) {
445 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer
, size
))
450 *out_offset
= offset
;
451 *ptr
= cmd_buffer
->upload
.map
+ offset
;
453 cmd_buffer
->upload
.offset
= offset
+ size
;
458 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
459 unsigned size
, unsigned alignment
,
460 const void *data
, unsigned *out_offset
)
464 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
, alignment
,
465 out_offset
, (void **)&ptr
))
469 memcpy(ptr
, data
, size
);
475 radv_emit_write_data_packet(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
476 unsigned count
, const uint32_t *data
)
478 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
480 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 4 + count
);
482 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, 0));
483 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
484 S_370_WR_CONFIRM(1) |
485 S_370_ENGINE_SEL(V_370_ME
));
487 radeon_emit(cs
, va
>> 32);
488 radeon_emit_array(cs
, data
, count
);
491 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
)
493 struct radv_device
*device
= cmd_buffer
->device
;
494 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
497 va
= radv_buffer_get_va(device
->trace_bo
);
498 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
)
501 ++cmd_buffer
->state
.trace_id
;
502 radv_emit_write_data_packet(cmd_buffer
, va
, 1,
503 &cmd_buffer
->state
.trace_id
);
505 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 2);
507 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
508 radeon_emit(cs
, AC_ENCODE_TRACE_POINT(cmd_buffer
->state
.trace_id
));
512 radv_cmd_buffer_after_draw(struct radv_cmd_buffer
*cmd_buffer
,
513 enum radv_cmd_flush_bits flags
)
515 if (cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_SYNC_SHADERS
) {
516 assert(flags
& (RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
517 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
));
519 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 4);
521 /* Force wait for graphics or compute engines to be idle. */
522 si_cs_emit_cache_flush(cmd_buffer
->cs
,
523 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
524 &cmd_buffer
->gfx9_fence_idx
,
525 cmd_buffer
->gfx9_fence_va
,
526 radv_cmd_buffer_uses_mec(cmd_buffer
),
527 flags
, cmd_buffer
->gfx9_eop_bug_va
);
530 if (unlikely(cmd_buffer
->device
->trace_bo
))
531 radv_cmd_buffer_trace_emit(cmd_buffer
);
535 radv_save_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
536 struct radv_pipeline
*pipeline
, enum ring_type ring
)
538 struct radv_device
*device
= cmd_buffer
->device
;
542 va
= radv_buffer_get_va(device
->trace_bo
);
552 assert(!"invalid ring type");
555 data
[0] = (uintptr_t)pipeline
;
556 data
[1] = (uintptr_t)pipeline
>> 32;
558 radv_emit_write_data_packet(cmd_buffer
, va
, 2, data
);
561 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
562 VkPipelineBindPoint bind_point
,
563 struct radv_descriptor_set
*set
,
566 struct radv_descriptor_state
*descriptors_state
=
567 radv_get_descriptors_state(cmd_buffer
, bind_point
);
569 descriptors_state
->sets
[idx
] = set
;
571 descriptors_state
->valid
|= (1u << idx
); /* active descriptors */
572 descriptors_state
->dirty
|= (1u << idx
);
576 radv_save_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
577 VkPipelineBindPoint bind_point
)
579 struct radv_descriptor_state
*descriptors_state
=
580 radv_get_descriptors_state(cmd_buffer
, bind_point
);
581 struct radv_device
*device
= cmd_buffer
->device
;
582 uint32_t data
[MAX_SETS
* 2] = {};
585 va
= radv_buffer_get_va(device
->trace_bo
) + 24;
587 for_each_bit(i
, descriptors_state
->valid
) {
588 struct radv_descriptor_set
*set
= descriptors_state
->sets
[i
];
589 data
[i
* 2] = (uint64_t)(uintptr_t)set
;
590 data
[i
* 2 + 1] = (uint64_t)(uintptr_t)set
>> 32;
593 radv_emit_write_data_packet(cmd_buffer
, va
, MAX_SETS
* 2, data
);
596 struct radv_userdata_info
*
597 radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
598 gl_shader_stage stage
,
601 struct radv_shader_variant
*shader
= radv_get_shader(pipeline
, stage
);
602 return &shader
->info
.user_sgprs_locs
.shader_data
[idx
];
606 radv_emit_userdata_address(struct radv_cmd_buffer
*cmd_buffer
,
607 struct radv_pipeline
*pipeline
,
608 gl_shader_stage stage
,
609 int idx
, uint64_t va
)
611 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, idx
);
612 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
613 if (loc
->sgpr_idx
== -1)
616 assert(loc
->num_sgprs
== 1);
618 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
619 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
623 radv_emit_descriptor_pointers(struct radv_cmd_buffer
*cmd_buffer
,
624 struct radv_pipeline
*pipeline
,
625 struct radv_descriptor_state
*descriptors_state
,
626 gl_shader_stage stage
)
628 struct radv_device
*device
= cmd_buffer
->device
;
629 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
630 uint32_t sh_base
= pipeline
->user_data_0
[stage
];
631 struct radv_userdata_locations
*locs
=
632 &pipeline
->shaders
[stage
]->info
.user_sgprs_locs
;
633 unsigned mask
= locs
->descriptor_sets_enabled
;
635 mask
&= descriptors_state
->dirty
& descriptors_state
->valid
;
640 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
642 struct radv_userdata_info
*loc
= &locs
->descriptor_sets
[start
];
643 unsigned sh_offset
= sh_base
+ loc
->sgpr_idx
* 4;
645 radv_emit_shader_pointer_head(cs
, sh_offset
, count
, true);
646 for (int i
= 0; i
< count
; i
++) {
647 struct radv_descriptor_set
*set
=
648 descriptors_state
->sets
[start
+ i
];
650 radv_emit_shader_pointer_body(device
, cs
, set
->va
, true);
656 * Convert the user sample locations to hardware sample locations (the values
657 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
660 radv_convert_user_sample_locs(struct radv_sample_locations_state
*state
,
661 uint32_t x
, uint32_t y
, VkOffset2D
*sample_locs
)
663 uint32_t x_offset
= x
% state
->grid_size
.width
;
664 uint32_t y_offset
= y
% state
->grid_size
.height
;
665 uint32_t num_samples
= (uint32_t)state
->per_pixel
;
666 VkSampleLocationEXT
*user_locs
;
667 uint32_t pixel_offset
;
669 pixel_offset
= (x_offset
+ y_offset
* state
->grid_size
.width
) * num_samples
;
671 assert(pixel_offset
<= MAX_SAMPLE_LOCATIONS
);
672 user_locs
= &state
->locations
[pixel_offset
];
674 for (uint32_t i
= 0; i
< num_samples
; i
++) {
675 float shifted_pos_x
= user_locs
[i
].x
- 0.5;
676 float shifted_pos_y
= user_locs
[i
].y
- 0.5;
678 int32_t scaled_pos_x
= floor(shifted_pos_x
* 16);
679 int32_t scaled_pos_y
= floor(shifted_pos_y
* 16);
681 sample_locs
[i
].x
= CLAMP(scaled_pos_x
, -8, 7);
682 sample_locs
[i
].y
= CLAMP(scaled_pos_y
, -8, 7);
687 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
691 radv_compute_sample_locs_pixel(uint32_t num_samples
, VkOffset2D
*sample_locs
,
692 uint32_t *sample_locs_pixel
)
694 for (uint32_t i
= 0; i
< num_samples
; i
++) {
695 uint32_t sample_reg_idx
= i
/ 4;
696 uint32_t sample_loc_idx
= i
% 4;
697 int32_t pos_x
= sample_locs
[i
].x
;
698 int32_t pos_y
= sample_locs
[i
].y
;
700 uint32_t shift_x
= 8 * sample_loc_idx
;
701 uint32_t shift_y
= shift_x
+ 4;
703 sample_locs_pixel
[sample_reg_idx
] |= (pos_x
& 0xf) << shift_x
;
704 sample_locs_pixel
[sample_reg_idx
] |= (pos_y
& 0xf) << shift_y
;
709 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
713 radv_compute_centroid_priority(struct radv_cmd_buffer
*cmd_buffer
,
714 VkOffset2D
*sample_locs
,
715 uint32_t num_samples
)
717 uint32_t centroid_priorities
[num_samples
];
718 uint32_t sample_mask
= num_samples
- 1;
719 uint32_t distances
[num_samples
];
720 uint64_t centroid_priority
= 0;
722 /* Compute the distances from center for each sample. */
723 for (int i
= 0; i
< num_samples
; i
++) {
724 distances
[i
] = (sample_locs
[i
].x
* sample_locs
[i
].x
) +
725 (sample_locs
[i
].y
* sample_locs
[i
].y
);
728 /* Compute the centroid priorities by looking at the distances array. */
729 for (int i
= 0; i
< num_samples
; i
++) {
730 uint32_t min_idx
= 0;
732 for (int j
= 1; j
< num_samples
; j
++) {
733 if (distances
[j
] < distances
[min_idx
])
737 centroid_priorities
[i
] = min_idx
;
738 distances
[min_idx
] = 0xffffffff;
741 /* Compute the final centroid priority. */
742 for (int i
= 0; i
< 8; i
++) {
744 centroid_priorities
[i
& sample_mask
] << (i
* 4);
747 return centroid_priority
<< 32 | centroid_priority
;
751 * Emit the sample locations that are specified with VK_EXT_sample_locations.
754 radv_emit_sample_locations(struct radv_cmd_buffer
*cmd_buffer
)
756 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
757 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
758 struct radv_sample_locations_state
*sample_location
=
759 &cmd_buffer
->state
.dynamic
.sample_location
;
760 uint32_t num_samples
= (uint32_t)sample_location
->per_pixel
;
761 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
762 uint32_t sample_locs_pixel
[4][2] = {};
763 VkOffset2D sample_locs
[4][8]; /* 8 is the max. sample count supported */
764 uint32_t max_sample_dist
= 0;
765 uint64_t centroid_priority
;
767 if (!cmd_buffer
->state
.dynamic
.sample_location
.count
)
770 /* Convert the user sample locations to hardware sample locations. */
771 radv_convert_user_sample_locs(sample_location
, 0, 0, sample_locs
[0]);
772 radv_convert_user_sample_locs(sample_location
, 1, 0, sample_locs
[1]);
773 radv_convert_user_sample_locs(sample_location
, 0, 1, sample_locs
[2]);
774 radv_convert_user_sample_locs(sample_location
, 1, 1, sample_locs
[3]);
776 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
777 for (uint32_t i
= 0; i
< 4; i
++) {
778 radv_compute_sample_locs_pixel(num_samples
, sample_locs
[i
],
779 sample_locs_pixel
[i
]);
782 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
784 radv_compute_centroid_priority(cmd_buffer
, sample_locs
[0],
787 /* Compute the maximum sample distance from the specified locations. */
788 for (uint32_t i
= 0; i
< num_samples
; i
++) {
789 VkOffset2D offset
= sample_locs
[0][i
];
790 max_sample_dist
= MAX2(max_sample_dist
,
791 MAX2(abs(offset
.x
), abs(offset
.y
)));
794 /* Emit the specified user sample locations. */
795 switch (num_samples
) {
798 radeon_set_context_reg(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_pixel
[0][0]);
799 radeon_set_context_reg(cs
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_pixel
[1][0]);
800 radeon_set_context_reg(cs
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_pixel
[2][0]);
801 radeon_set_context_reg(cs
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_pixel
[3][0]);
804 radeon_set_context_reg(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_pixel
[0][0]);
805 radeon_set_context_reg(cs
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_pixel
[1][0]);
806 radeon_set_context_reg(cs
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_pixel
[2][0]);
807 radeon_set_context_reg(cs
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_pixel
[3][0]);
808 radeon_set_context_reg(cs
, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1
, sample_locs_pixel
[0][1]);
809 radeon_set_context_reg(cs
, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1
, sample_locs_pixel
[1][1]);
810 radeon_set_context_reg(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1
, sample_locs_pixel
[2][1]);
811 radeon_set_context_reg(cs
, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1
, sample_locs_pixel
[3][1]);
814 unreachable("invalid number of samples");
817 /* Emit the maximum sample distance and the centroid priority. */
818 uint32_t pa_sc_aa_config
= ms
->pa_sc_aa_config
;
820 pa_sc_aa_config
&= C_028BE0_MAX_SAMPLE_DIST
;
821 pa_sc_aa_config
|= S_028BE0_MAX_SAMPLE_DIST(max_sample_dist
);
823 radeon_set_context_reg_seq(cs
, R_028BE0_PA_SC_AA_CONFIG
, 1);
824 radeon_emit(cs
, pa_sc_aa_config
);
826 radeon_set_context_reg_seq(cs
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 2);
827 radeon_emit(cs
, centroid_priority
);
828 radeon_emit(cs
, centroid_priority
>> 32);
830 /* GFX9: Flush DFSM when the AA mode changes. */
831 if (cmd_buffer
->device
->dfsm_allowed
) {
832 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
833 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
836 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
840 radv_emit_inline_push_consts(struct radv_cmd_buffer
*cmd_buffer
,
841 struct radv_pipeline
*pipeline
,
842 gl_shader_stage stage
,
843 int idx
, int count
, uint32_t *values
)
845 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, idx
);
846 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
847 if (loc
->sgpr_idx
== -1)
850 assert(loc
->num_sgprs
== count
);
852 radeon_set_sh_reg_seq(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, count
);
853 radeon_emit_array(cmd_buffer
->cs
, values
, count
);
857 radv_update_multisample_state(struct radv_cmd_buffer
*cmd_buffer
,
858 struct radv_pipeline
*pipeline
)
860 int num_samples
= pipeline
->graphics
.ms
.num_samples
;
861 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
862 struct radv_pipeline
*old_pipeline
= cmd_buffer
->state
.emitted_pipeline
;
864 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.needs_sample_positions
)
865 cmd_buffer
->sample_positions_needed
= true;
867 if (old_pipeline
&& num_samples
== old_pipeline
->graphics
.ms
.num_samples
)
870 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028BDC_PA_SC_LINE_CNTL
, 2);
871 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_line_cntl
);
872 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_config
);
874 radeon_set_context_reg(cmd_buffer
->cs
, R_028A48_PA_SC_MODE_CNTL_0
, ms
->pa_sc_mode_cntl_0
);
876 radv_emit_default_sample_locations(cmd_buffer
->cs
, num_samples
);
878 /* GFX9: Flush DFSM when the AA mode changes. */
879 if (cmd_buffer
->device
->dfsm_allowed
) {
880 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
881 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
884 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
888 radv_update_binning_state(struct radv_cmd_buffer
*cmd_buffer
,
889 struct radv_pipeline
*pipeline
)
891 const struct radv_pipeline
*old_pipeline
= cmd_buffer
->state
.emitted_pipeline
;
894 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX9
)
898 old_pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
== pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
&&
899 old_pipeline
->graphics
.binning
.db_dfsm_control
== pipeline
->graphics
.binning
.db_dfsm_control
)
902 bool binning_flush
= false;
903 if (cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_VEGA12
||
904 cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_VEGA20
||
905 cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_RAVEN2
||
906 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
907 binning_flush
= !old_pipeline
||
908 G_028C44_BINNING_MODE(old_pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
) !=
909 G_028C44_BINNING_MODE(pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
);
912 radeon_set_context_reg(cmd_buffer
->cs
, R_028C44_PA_SC_BINNER_CNTL_0
,
913 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
|
914 S_028C44_FLUSH_ON_BINNING_TRANSITION(!!binning_flush
));
916 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
917 radeon_set_context_reg(cmd_buffer
->cs
, R_028038_DB_DFSM_CONTROL
,
918 pipeline
->graphics
.binning
.db_dfsm_control
);
920 radeon_set_context_reg(cmd_buffer
->cs
, R_028060_DB_DFSM_CONTROL
,
921 pipeline
->graphics
.binning
.db_dfsm_control
);
924 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
929 radv_emit_shader_prefetch(struct radv_cmd_buffer
*cmd_buffer
,
930 struct radv_shader_variant
*shader
)
937 va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
939 si_cp_dma_prefetch(cmd_buffer
, va
, shader
->code_size
);
943 radv_emit_prefetch_L2(struct radv_cmd_buffer
*cmd_buffer
,
944 struct radv_pipeline
*pipeline
,
945 bool vertex_stage_only
)
947 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
948 uint32_t mask
= state
->prefetch_L2_mask
;
950 if (vertex_stage_only
) {
951 /* Fast prefetch path for starting draws as soon as possible.
953 mask
= state
->prefetch_L2_mask
& (RADV_PREFETCH_VS
|
954 RADV_PREFETCH_VBO_DESCRIPTORS
);
957 if (mask
& RADV_PREFETCH_VS
)
958 radv_emit_shader_prefetch(cmd_buffer
,
959 pipeline
->shaders
[MESA_SHADER_VERTEX
]);
961 if (mask
& RADV_PREFETCH_VBO_DESCRIPTORS
)
962 si_cp_dma_prefetch(cmd_buffer
, state
->vb_va
, state
->vb_size
);
964 if (mask
& RADV_PREFETCH_TCS
)
965 radv_emit_shader_prefetch(cmd_buffer
,
966 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]);
968 if (mask
& RADV_PREFETCH_TES
)
969 radv_emit_shader_prefetch(cmd_buffer
,
970 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]);
972 if (mask
& RADV_PREFETCH_GS
) {
973 radv_emit_shader_prefetch(cmd_buffer
,
974 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]);
975 if (radv_pipeline_has_gs_copy_shader(pipeline
))
976 radv_emit_shader_prefetch(cmd_buffer
, pipeline
->gs_copy_shader
);
979 if (mask
& RADV_PREFETCH_PS
)
980 radv_emit_shader_prefetch(cmd_buffer
,
981 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
983 state
->prefetch_L2_mask
&= ~mask
;
987 radv_emit_rbplus_state(struct radv_cmd_buffer
*cmd_buffer
)
989 if (!cmd_buffer
->device
->physical_device
->rbplus_allowed
)
992 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
993 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
994 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
996 unsigned sx_ps_downconvert
= 0;
997 unsigned sx_blend_opt_epsilon
= 0;
998 unsigned sx_blend_opt_control
= 0;
1000 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1001 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
1002 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
1003 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
1007 int idx
= subpass
->color_attachments
[i
].attachment
;
1008 struct radv_color_buffer_info
*cb
= &framebuffer
->attachments
[idx
].cb
;
1010 unsigned format
= G_028C70_FORMAT(cb
->cb_color_info
);
1011 unsigned swap
= G_028C70_COMP_SWAP(cb
->cb_color_info
);
1012 uint32_t spi_format
= (pipeline
->graphics
.col_format
>> (i
* 4)) & 0xf;
1013 uint32_t colormask
= (pipeline
->graphics
.cb_target_mask
>> (i
* 4)) & 0xf;
1015 bool has_alpha
, has_rgb
;
1017 /* Set if RGB and A are present. */
1018 has_alpha
= !G_028C74_FORCE_DST_ALPHA_1(cb
->cb_color_attrib
);
1020 if (format
== V_028C70_COLOR_8
||
1021 format
== V_028C70_COLOR_16
||
1022 format
== V_028C70_COLOR_32
)
1023 has_rgb
= !has_alpha
;
1027 /* Check the colormask and export format. */
1028 if (!(colormask
& 0x7))
1030 if (!(colormask
& 0x8))
1033 if (spi_format
== V_028714_SPI_SHADER_ZERO
) {
1038 /* Disable value checking for disabled channels. */
1040 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
1042 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
1044 /* Enable down-conversion for 32bpp and smaller formats. */
1046 case V_028C70_COLOR_8
:
1047 case V_028C70_COLOR_8_8
:
1048 case V_028C70_COLOR_8_8_8_8
:
1049 /* For 1 and 2-channel formats, use the superset thereof. */
1050 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
||
1051 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
1052 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
1053 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_8_8_8_8
<< (i
* 4);
1054 sx_blend_opt_epsilon
|= V_028758_8BIT_FORMAT
<< (i
* 4);
1058 case V_028C70_COLOR_5_6_5
:
1059 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1060 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_5_6_5
<< (i
* 4);
1061 sx_blend_opt_epsilon
|= V_028758_6BIT_FORMAT
<< (i
* 4);
1065 case V_028C70_COLOR_1_5_5_5
:
1066 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1067 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_1_5_5_5
<< (i
* 4);
1068 sx_blend_opt_epsilon
|= V_028758_5BIT_FORMAT
<< (i
* 4);
1072 case V_028C70_COLOR_4_4_4_4
:
1073 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1074 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_4_4_4_4
<< (i
* 4);
1075 sx_blend_opt_epsilon
|= V_028758_4BIT_FORMAT
<< (i
* 4);
1079 case V_028C70_COLOR_32
:
1080 if (swap
== V_028C70_SWAP_STD
&&
1081 spi_format
== V_028714_SPI_SHADER_32_R
)
1082 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
1083 else if (swap
== V_028C70_SWAP_ALT_REV
&&
1084 spi_format
== V_028714_SPI_SHADER_32_AR
)
1085 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_A
<< (i
* 4);
1088 case V_028C70_COLOR_16
:
1089 case V_028C70_COLOR_16_16
:
1090 /* For 1-channel formats, use the superset thereof. */
1091 if (spi_format
== V_028714_SPI_SHADER_UNORM16_ABGR
||
1092 spi_format
== V_028714_SPI_SHADER_SNORM16_ABGR
||
1093 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
1094 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
1095 if (swap
== V_028C70_SWAP_STD
||
1096 swap
== V_028C70_SWAP_STD_REV
)
1097 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_GR
<< (i
* 4);
1099 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_AR
<< (i
* 4);
1103 case V_028C70_COLOR_10_11_11
:
1104 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1105 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_10_11_11
<< (i
* 4);
1106 sx_blend_opt_epsilon
|= V_028758_11BIT_FORMAT
<< (i
* 4);
1110 case V_028C70_COLOR_2_10_10_10
:
1111 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1112 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_2_10_10_10
<< (i
* 4);
1113 sx_blend_opt_epsilon
|= V_028758_10BIT_FORMAT
<< (i
* 4);
1119 for (unsigned i
= subpass
->color_count
; i
< 8; ++i
) {
1120 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
1121 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
1123 /* TODO: avoid redundantly setting context registers */
1124 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
1125 radeon_emit(cmd_buffer
->cs
, sx_ps_downconvert
);
1126 radeon_emit(cmd_buffer
->cs
, sx_blend_opt_epsilon
);
1127 radeon_emit(cmd_buffer
->cs
, sx_blend_opt_control
);
1129 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1133 radv_emit_graphics_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
1135 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1137 if (!pipeline
|| cmd_buffer
->state
.emitted_pipeline
== pipeline
)
1140 radv_update_multisample_state(cmd_buffer
, pipeline
);
1141 radv_update_binning_state(cmd_buffer
, pipeline
);
1143 cmd_buffer
->scratch_size_needed
=
1144 MAX2(cmd_buffer
->scratch_size_needed
,
1145 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
1147 if (!cmd_buffer
->state
.emitted_pipeline
||
1148 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
!=
1149 pipeline
->graphics
.can_use_guardband
)
1150 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
1152 radeon_emit_array(cmd_buffer
->cs
, pipeline
->cs
.buf
, pipeline
->cs
.cdw
);
1154 if (!cmd_buffer
->state
.emitted_pipeline
||
1155 cmd_buffer
->state
.emitted_pipeline
->ctx_cs
.cdw
!= pipeline
->ctx_cs
.cdw
||
1156 cmd_buffer
->state
.emitted_pipeline
->ctx_cs_hash
!= pipeline
->ctx_cs_hash
||
1157 memcmp(cmd_buffer
->state
.emitted_pipeline
->ctx_cs
.buf
,
1158 pipeline
->ctx_cs
.buf
, pipeline
->ctx_cs
.cdw
* 4)) {
1159 radeon_emit_array(cmd_buffer
->cs
, pipeline
->ctx_cs
.buf
, pipeline
->ctx_cs
.cdw
);
1160 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1163 for (unsigned i
= 0; i
< MESA_SHADER_COMPUTE
; i
++) {
1164 if (!pipeline
->shaders
[i
])
1167 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
1168 pipeline
->shaders
[i
]->bo
);
1171 if (radv_pipeline_has_gs_copy_shader(pipeline
))
1172 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
1173 pipeline
->gs_copy_shader
->bo
);
1175 if (unlikely(cmd_buffer
->device
->trace_bo
))
1176 radv_save_pipeline(cmd_buffer
, pipeline
, RING_GFX
);
1178 cmd_buffer
->state
.emitted_pipeline
= pipeline
;
1180 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_PIPELINE
;
1184 radv_emit_viewport(struct radv_cmd_buffer
*cmd_buffer
)
1186 si_write_viewport(cmd_buffer
->cs
, 0, cmd_buffer
->state
.dynamic
.viewport
.count
,
1187 cmd_buffer
->state
.dynamic
.viewport
.viewports
);
1191 radv_emit_scissor(struct radv_cmd_buffer
*cmd_buffer
)
1193 uint32_t count
= cmd_buffer
->state
.dynamic
.scissor
.count
;
1195 si_write_scissors(cmd_buffer
->cs
, 0, count
,
1196 cmd_buffer
->state
.dynamic
.scissor
.scissors
,
1197 cmd_buffer
->state
.dynamic
.viewport
.viewports
,
1198 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
);
1200 cmd_buffer
->state
.context_roll_without_scissor_emitted
= false;
1204 radv_emit_discard_rectangle(struct radv_cmd_buffer
*cmd_buffer
)
1206 if (!cmd_buffer
->state
.dynamic
.discard_rectangle
.count
)
1209 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028210_PA_SC_CLIPRECT_0_TL
,
1210 cmd_buffer
->state
.dynamic
.discard_rectangle
.count
* 2);
1211 for (unsigned i
= 0; i
< cmd_buffer
->state
.dynamic
.discard_rectangle
.count
; ++i
) {
1212 VkRect2D rect
= cmd_buffer
->state
.dynamic
.discard_rectangle
.rectangles
[i
];
1213 radeon_emit(cmd_buffer
->cs
, S_028210_TL_X(rect
.offset
.x
) | S_028210_TL_Y(rect
.offset
.y
));
1214 radeon_emit(cmd_buffer
->cs
, S_028214_BR_X(rect
.offset
.x
+ rect
.extent
.width
) |
1215 S_028214_BR_Y(rect
.offset
.y
+ rect
.extent
.height
));
1220 radv_emit_line_width(struct radv_cmd_buffer
*cmd_buffer
)
1222 unsigned width
= cmd_buffer
->state
.dynamic
.line_width
* 8;
1224 radeon_set_context_reg(cmd_buffer
->cs
, R_028A08_PA_SU_LINE_CNTL
,
1225 S_028A08_WIDTH(CLAMP(width
, 0, 0xFFF)));
1229 radv_emit_blend_constants(struct radv_cmd_buffer
*cmd_buffer
)
1231 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1233 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028414_CB_BLEND_RED
, 4);
1234 radeon_emit_array(cmd_buffer
->cs
, (uint32_t *)d
->blend_constants
, 4);
1238 radv_emit_stencil(struct radv_cmd_buffer
*cmd_buffer
)
1240 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1242 radeon_set_context_reg_seq(cmd_buffer
->cs
,
1243 R_028430_DB_STENCILREFMASK
, 2);
1244 radeon_emit(cmd_buffer
->cs
,
1245 S_028430_STENCILTESTVAL(d
->stencil_reference
.front
) |
1246 S_028430_STENCILMASK(d
->stencil_compare_mask
.front
) |
1247 S_028430_STENCILWRITEMASK(d
->stencil_write_mask
.front
) |
1248 S_028430_STENCILOPVAL(1));
1249 radeon_emit(cmd_buffer
->cs
,
1250 S_028434_STENCILTESTVAL_BF(d
->stencil_reference
.back
) |
1251 S_028434_STENCILMASK_BF(d
->stencil_compare_mask
.back
) |
1252 S_028434_STENCILWRITEMASK_BF(d
->stencil_write_mask
.back
) |
1253 S_028434_STENCILOPVAL_BF(1));
1257 radv_emit_depth_bounds(struct radv_cmd_buffer
*cmd_buffer
)
1259 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1261 radeon_set_context_reg(cmd_buffer
->cs
, R_028020_DB_DEPTH_BOUNDS_MIN
,
1262 fui(d
->depth_bounds
.min
));
1263 radeon_set_context_reg(cmd_buffer
->cs
, R_028024_DB_DEPTH_BOUNDS_MAX
,
1264 fui(d
->depth_bounds
.max
));
1268 radv_emit_depth_bias(struct radv_cmd_buffer
*cmd_buffer
)
1270 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1271 unsigned slope
= fui(d
->depth_bias
.slope
* 16.0f
);
1272 unsigned bias
= fui(d
->depth_bias
.bias
* cmd_buffer
->state
.offset_scale
);
1275 radeon_set_context_reg_seq(cmd_buffer
->cs
,
1276 R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, 5);
1277 radeon_emit(cmd_buffer
->cs
, fui(d
->depth_bias
.clamp
)); /* CLAMP */
1278 radeon_emit(cmd_buffer
->cs
, slope
); /* FRONT SCALE */
1279 radeon_emit(cmd_buffer
->cs
, bias
); /* FRONT OFFSET */
1280 radeon_emit(cmd_buffer
->cs
, slope
); /* BACK SCALE */
1281 radeon_emit(cmd_buffer
->cs
, bias
); /* BACK OFFSET */
1285 radv_emit_fb_color_state(struct radv_cmd_buffer
*cmd_buffer
,
1287 struct radv_attachment_info
*att
,
1288 struct radv_image_view
*iview
,
1289 VkImageLayout layout
)
1291 bool is_vi
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX8
;
1292 struct radv_color_buffer_info
*cb
= &att
->cb
;
1293 uint32_t cb_color_info
= cb
->cb_color_info
;
1294 struct radv_image
*image
= iview
->image
;
1296 if (!radv_layout_dcc_compressed(image
, layout
,
1297 radv_image_queue_family_mask(image
,
1298 cmd_buffer
->queue_family_index
,
1299 cmd_buffer
->queue_family_index
))) {
1300 cb_color_info
&= C_028C70_DCC_ENABLE
;
1303 if (radv_image_is_tc_compat_cmask(image
) &&
1304 (radv_is_fmask_decompress_pipeline(cmd_buffer
) ||
1305 radv_is_dcc_decompress_pipeline(cmd_buffer
))) {
1306 /* If this bit is set, the FMASK decompression operation
1307 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1309 cb_color_info
&= C_028C70_FMASK_COMPRESS_1FRAG_ONLY
;
1312 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
1313 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1314 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1315 radeon_emit(cmd_buffer
->cs
, 0);
1316 radeon_emit(cmd_buffer
->cs
, 0);
1317 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1318 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1319 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1320 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1321 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1322 radeon_emit(cmd_buffer
->cs
, 0);
1323 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1324 radeon_emit(cmd_buffer
->cs
, 0);
1326 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, 1);
1327 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
);
1329 radeon_set_context_reg(cmd_buffer
->cs
, R_028E40_CB_COLOR0_BASE_EXT
+ index
* 4,
1330 cb
->cb_color_base
>> 32);
1331 radeon_set_context_reg(cmd_buffer
->cs
, R_028E60_CB_COLOR0_CMASK_BASE_EXT
+ index
* 4,
1332 cb
->cb_color_cmask
>> 32);
1333 radeon_set_context_reg(cmd_buffer
->cs
, R_028E80_CB_COLOR0_FMASK_BASE_EXT
+ index
* 4,
1334 cb
->cb_color_fmask
>> 32);
1335 radeon_set_context_reg(cmd_buffer
->cs
, R_028EA0_CB_COLOR0_DCC_BASE_EXT
+ index
* 4,
1336 cb
->cb_dcc_base
>> 32);
1337 radeon_set_context_reg(cmd_buffer
->cs
, R_028EC0_CB_COLOR0_ATTRIB2
+ index
* 4,
1338 cb
->cb_color_attrib2
);
1339 radeon_set_context_reg(cmd_buffer
->cs
, R_028EE0_CB_COLOR0_ATTRIB3
+ index
* 4,
1340 cb
->cb_color_attrib3
);
1341 } else if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
1342 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1343 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1344 radeon_emit(cmd_buffer
->cs
, S_028C64_BASE_256B(cb
->cb_color_base
>> 32));
1345 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib2
);
1346 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1347 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1348 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1349 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1350 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1351 radeon_emit(cmd_buffer
->cs
, S_028C80_BASE_256B(cb
->cb_color_cmask
>> 32));
1352 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1353 radeon_emit(cmd_buffer
->cs
, S_028C88_BASE_256B(cb
->cb_color_fmask
>> 32));
1355 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, 2);
1356 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
);
1357 radeon_emit(cmd_buffer
->cs
, S_028C98_BASE_256B(cb
->cb_dcc_base
>> 32));
1359 radeon_set_context_reg(cmd_buffer
->cs
, R_0287A0_CB_MRT0_EPITCH
+ index
* 4,
1362 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1363 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1364 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_pitch
);
1365 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_slice
);
1366 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1367 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1368 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1369 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1370 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1371 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask_slice
);
1372 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1373 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask_slice
);
1375 if (is_vi
) { /* DCC BASE */
1376 radeon_set_context_reg(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, cb
->cb_dcc_base
);
1380 if (radv_dcc_enabled(image
, iview
->base_mip
)) {
1381 /* Drawing with DCC enabled also compresses colorbuffers. */
1382 VkImageSubresourceRange range
= {
1383 .aspectMask
= iview
->aspect_mask
,
1384 .baseMipLevel
= iview
->base_mip
,
1385 .levelCount
= iview
->level_count
,
1386 .baseArrayLayer
= iview
->base_layer
,
1387 .layerCount
= iview
->layer_count
,
1390 radv_update_dcc_metadata(cmd_buffer
, image
, &range
, true);
1395 radv_update_zrange_precision(struct radv_cmd_buffer
*cmd_buffer
,
1396 struct radv_ds_buffer_info
*ds
,
1397 struct radv_image
*image
, VkImageLayout layout
,
1398 bool requires_cond_exec
)
1400 uint32_t db_z_info
= ds
->db_z_info
;
1401 uint32_t db_z_info_reg
;
1403 if (!cmd_buffer
->device
->physical_device
->has_tc_compat_zrange_bug
||
1404 !radv_image_is_tc_compat_htile(image
))
1407 if (!radv_layout_has_htile(image
, layout
,
1408 radv_image_queue_family_mask(image
,
1409 cmd_buffer
->queue_family_index
,
1410 cmd_buffer
->queue_family_index
))) {
1411 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
1414 db_z_info
&= C_028040_ZRANGE_PRECISION
;
1416 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
1417 db_z_info_reg
= R_028038_DB_Z_INFO
;
1419 db_z_info_reg
= R_028040_DB_Z_INFO
;
1422 /* When we don't know the last fast clear value we need to emit a
1423 * conditional packet that will eventually skip the following
1424 * SET_CONTEXT_REG packet.
1426 if (requires_cond_exec
) {
1427 uint64_t va
= radv_buffer_get_va(image
->bo
);
1428 va
+= image
->offset
+ image
->tc_compat_zrange_offset
;
1430 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_COND_EXEC
, 3, 0));
1431 radeon_emit(cmd_buffer
->cs
, va
);
1432 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1433 radeon_emit(cmd_buffer
->cs
, 0);
1434 radeon_emit(cmd_buffer
->cs
, 3); /* SET_CONTEXT_REG size */
1437 radeon_set_context_reg(cmd_buffer
->cs
, db_z_info_reg
, db_z_info
);
1441 radv_emit_fb_ds_state(struct radv_cmd_buffer
*cmd_buffer
,
1442 struct radv_ds_buffer_info
*ds
,
1443 struct radv_image
*image
,
1444 VkImageLayout layout
)
1446 uint32_t db_z_info
= ds
->db_z_info
;
1447 uint32_t db_stencil_info
= ds
->db_stencil_info
;
1449 if (!radv_layout_has_htile(image
, layout
,
1450 radv_image_queue_family_mask(image
,
1451 cmd_buffer
->queue_family_index
,
1452 cmd_buffer
->queue_family_index
))) {
1453 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
1454 db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
1457 radeon_set_context_reg(cmd_buffer
->cs
, R_028008_DB_DEPTH_VIEW
, ds
->db_depth_view
);
1458 radeon_set_context_reg(cmd_buffer
->cs
, R_028ABC_DB_HTILE_SURFACE
, ds
->db_htile_surface
);
1460 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
1461 radeon_set_context_reg(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, ds
->db_htile_data_base
);
1462 radeon_set_context_reg(cmd_buffer
->cs
, R_02801C_DB_DEPTH_SIZE_XY
, ds
->db_depth_size
);
1464 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_02803C_DB_DEPTH_INFO
, 7);
1465 radeon_emit(cmd_buffer
->cs
, S_02803C_RESOURCE_LEVEL(1));
1466 radeon_emit(cmd_buffer
->cs
, db_z_info
);
1467 radeon_emit(cmd_buffer
->cs
, db_stencil_info
);
1468 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
);
1469 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
);
1470 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
);
1471 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
);
1473 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028068_DB_Z_READ_BASE_HI
, 5);
1474 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
>> 32);
1475 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
>> 32);
1476 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
>> 32);
1477 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
>> 32);
1478 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
>> 32);
1479 } else if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
1480 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
1481 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
);
1482 radeon_emit(cmd_buffer
->cs
, S_028018_BASE_HI(ds
->db_htile_data_base
>> 32));
1483 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
);
1485 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 10);
1486 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* DB_Z_INFO */
1487 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* DB_STENCIL_INFO */
1488 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* DB_Z_READ_BASE */
1489 radeon_emit(cmd_buffer
->cs
, S_028044_BASE_HI(ds
->db_z_read_base
>> 32)); /* DB_Z_READ_BASE_HI */
1490 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* DB_STENCIL_READ_BASE */
1491 radeon_emit(cmd_buffer
->cs
, S_02804C_BASE_HI(ds
->db_stencil_read_base
>> 32)); /* DB_STENCIL_READ_BASE_HI */
1492 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* DB_Z_WRITE_BASE */
1493 radeon_emit(cmd_buffer
->cs
, S_028054_BASE_HI(ds
->db_z_write_base
>> 32)); /* DB_Z_WRITE_BASE_HI */
1494 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* DB_STENCIL_WRITE_BASE */
1495 radeon_emit(cmd_buffer
->cs
, S_02805C_BASE_HI(ds
->db_stencil_write_base
>> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1497 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028068_DB_Z_INFO2
, 2);
1498 radeon_emit(cmd_buffer
->cs
, ds
->db_z_info2
);
1499 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_info2
);
1501 radeon_set_context_reg(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, ds
->db_htile_data_base
);
1503 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_02803C_DB_DEPTH_INFO
, 9);
1504 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_info
); /* R_02803C_DB_DEPTH_INFO */
1505 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* R_028040_DB_Z_INFO */
1506 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* R_028044_DB_STENCIL_INFO */
1507 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* R_028048_DB_Z_READ_BASE */
1508 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* R_02804C_DB_STENCIL_READ_BASE */
1509 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* R_028050_DB_Z_WRITE_BASE */
1510 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* R_028054_DB_STENCIL_WRITE_BASE */
1511 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
); /* R_028058_DB_DEPTH_SIZE */
1512 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_slice
); /* R_02805C_DB_DEPTH_SLICE */
1516 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1517 radv_update_zrange_precision(cmd_buffer
, ds
, image
, layout
, true);
1519 radeon_set_context_reg(cmd_buffer
->cs
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1520 ds
->pa_su_poly_offset_db_fmt_cntl
);
1524 * Update the fast clear depth/stencil values if the image is bound as a
1525 * depth/stencil buffer.
1528 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer
*cmd_buffer
,
1529 struct radv_image
*image
,
1530 VkClearDepthStencilValue ds_clear_value
,
1531 VkImageAspectFlags aspects
)
1533 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1534 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1535 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1536 struct radv_attachment_info
*att
;
1539 if (!framebuffer
|| !subpass
)
1542 if (!subpass
->depth_stencil_attachment
)
1545 att_idx
= subpass
->depth_stencil_attachment
->attachment
;
1546 att
= &framebuffer
->attachments
[att_idx
];
1547 if (att
->attachment
->image
!= image
)
1550 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 2);
1551 radeon_emit(cs
, ds_clear_value
.stencil
);
1552 radeon_emit(cs
, fui(ds_clear_value
.depth
));
1554 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1555 * only needed when clearing Z to 0.0.
1557 if ((aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
1558 ds_clear_value
.depth
== 0.0) {
1559 VkImageLayout layout
= subpass
->depth_stencil_attachment
->layout
;
1561 radv_update_zrange_precision(cmd_buffer
, &att
->ds
, image
,
1565 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1569 * Set the clear depth/stencil values to the image's metadata.
1572 radv_set_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1573 struct radv_image
*image
,
1574 VkClearDepthStencilValue ds_clear_value
,
1575 VkImageAspectFlags aspects
)
1577 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1578 uint64_t va
= radv_buffer_get_va(image
->bo
);
1579 unsigned reg_offset
= 0, reg_count
= 0;
1581 va
+= image
->offset
+ image
->clear_value_offset
;
1583 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1589 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1592 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + reg_count
, cmd_buffer
->state
.predicating
));
1593 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
1594 S_370_WR_CONFIRM(1) |
1595 S_370_ENGINE_SEL(V_370_PFP
));
1596 radeon_emit(cs
, va
);
1597 radeon_emit(cs
, va
>> 32);
1598 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)
1599 radeon_emit(cs
, ds_clear_value
.stencil
);
1600 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1601 radeon_emit(cs
, fui(ds_clear_value
.depth
));
1605 * Update the TC-compat metadata value for this image.
1608 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1609 struct radv_image
*image
,
1612 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1613 uint64_t va
= radv_buffer_get_va(image
->bo
);
1615 if (!cmd_buffer
->device
->physical_device
->has_tc_compat_zrange_bug
)
1618 va
+= image
->offset
+ image
->tc_compat_zrange_offset
;
1620 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, cmd_buffer
->state
.predicating
));
1621 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
1622 S_370_WR_CONFIRM(1) |
1623 S_370_ENGINE_SEL(V_370_PFP
));
1624 radeon_emit(cs
, va
);
1625 radeon_emit(cs
, va
>> 32);
1626 radeon_emit(cs
, value
);
1630 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1631 struct radv_image
*image
,
1632 VkClearDepthStencilValue ds_clear_value
)
1636 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1637 * depth clear value is 0.0f.
1639 cond_val
= ds_clear_value
.depth
== 0.0f
? UINT_MAX
: 0;
1641 radv_set_tc_compat_zrange_metadata(cmd_buffer
, image
, cond_val
);
1645 * Update the clear depth/stencil values for this image.
1648 radv_update_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1649 struct radv_image
*image
,
1650 VkClearDepthStencilValue ds_clear_value
,
1651 VkImageAspectFlags aspects
)
1653 assert(radv_image_has_htile(image
));
1655 radv_set_ds_clear_metadata(cmd_buffer
, image
, ds_clear_value
, aspects
);
1657 if (radv_image_is_tc_compat_htile(image
) &&
1658 (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
1659 radv_update_tc_compat_zrange_metadata(cmd_buffer
, image
,
1663 radv_update_bound_fast_clear_ds(cmd_buffer
, image
, ds_clear_value
,
1668 * Load the clear depth/stencil values from the image's metadata.
1671 radv_load_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1672 struct radv_image
*image
)
1674 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1675 VkImageAspectFlags aspects
= vk_format_aspects(image
->vk_format
);
1676 uint64_t va
= radv_buffer_get_va(image
->bo
);
1677 unsigned reg_offset
= 0, reg_count
= 0;
1679 va
+= image
->offset
+ image
->clear_value_offset
;
1681 if (!radv_image_has_htile(image
))
1684 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1690 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1693 uint32_t reg
= R_028028_DB_STENCIL_CLEAR
+ 4 * reg_offset
;
1695 if (cmd_buffer
->device
->physical_device
->has_load_ctx_reg_pkt
) {
1696 radeon_emit(cs
, PKT3(PKT3_LOAD_CONTEXT_REG
, 3, 0));
1697 radeon_emit(cs
, va
);
1698 radeon_emit(cs
, va
>> 32);
1699 radeon_emit(cs
, (reg
- SI_CONTEXT_REG_OFFSET
) >> 2);
1700 radeon_emit(cs
, reg_count
);
1702 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
1703 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
1704 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1705 (reg_count
== 2 ? COPY_DATA_COUNT_SEL
: 0));
1706 radeon_emit(cs
, va
);
1707 radeon_emit(cs
, va
>> 32);
1708 radeon_emit(cs
, reg
>> 2);
1711 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
1717 * With DCC some colors don't require CMASK elimination before being
1718 * used as a texture. This sets a predicate value to determine if the
1719 * cmask eliminate is required.
1722 radv_update_fce_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1723 struct radv_image
*image
,
1724 const VkImageSubresourceRange
*range
, bool value
)
1726 uint64_t pred_val
= value
;
1727 uint64_t va
= radv_image_get_fce_pred_va(image
, range
->baseMipLevel
);
1728 uint32_t level_count
= radv_get_levelCount(image
, range
);
1729 uint32_t count
= 2 * level_count
;
1731 assert(radv_dcc_enabled(image
, range
->baseMipLevel
));
1733 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, 0));
1734 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM
) |
1735 S_370_WR_CONFIRM(1) |
1736 S_370_ENGINE_SEL(V_370_PFP
));
1737 radeon_emit(cmd_buffer
->cs
, va
);
1738 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1740 for (uint32_t l
= 0; l
< level_count
; l
++) {
1741 radeon_emit(cmd_buffer
->cs
, pred_val
);
1742 radeon_emit(cmd_buffer
->cs
, pred_val
>> 32);
1747 * Update the DCC predicate to reflect the compression state.
1750 radv_update_dcc_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1751 struct radv_image
*image
,
1752 const VkImageSubresourceRange
*range
, bool value
)
1754 uint64_t pred_val
= value
;
1755 uint64_t va
= radv_image_get_dcc_pred_va(image
, range
->baseMipLevel
);
1756 uint32_t level_count
= radv_get_levelCount(image
, range
);
1757 uint32_t count
= 2 * level_count
;
1759 assert(radv_dcc_enabled(image
, range
->baseMipLevel
));
1761 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, 0));
1762 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM
) |
1763 S_370_WR_CONFIRM(1) |
1764 S_370_ENGINE_SEL(V_370_PFP
));
1765 radeon_emit(cmd_buffer
->cs
, va
);
1766 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1768 for (uint32_t l
= 0; l
< level_count
; l
++) {
1769 radeon_emit(cmd_buffer
->cs
, pred_val
);
1770 radeon_emit(cmd_buffer
->cs
, pred_val
>> 32);
1775 * Update the fast clear color values if the image is bound as a color buffer.
1778 radv_update_bound_fast_clear_color(struct radv_cmd_buffer
*cmd_buffer
,
1779 struct radv_image
*image
,
1781 uint32_t color_values
[2])
1783 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1784 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1785 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1786 struct radv_attachment_info
*att
;
1789 if (!framebuffer
|| !subpass
)
1792 att_idx
= subpass
->color_attachments
[cb_idx
].attachment
;
1793 if (att_idx
== VK_ATTACHMENT_UNUSED
)
1796 att
= &framebuffer
->attachments
[att_idx
];
1797 if (att
->attachment
->image
!= image
)
1800 radeon_set_context_reg_seq(cs
, R_028C8C_CB_COLOR0_CLEAR_WORD0
+ cb_idx
* 0x3c, 2);
1801 radeon_emit(cs
, color_values
[0]);
1802 radeon_emit(cs
, color_values
[1]);
1804 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1808 * Set the clear color values to the image's metadata.
1811 radv_set_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1812 struct radv_image
*image
,
1813 const VkImageSubresourceRange
*range
,
1814 uint32_t color_values
[2])
1816 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1817 uint64_t va
= radv_image_get_fast_clear_va(image
, range
->baseMipLevel
);
1818 uint32_t level_count
= radv_get_levelCount(image
, range
);
1819 uint32_t count
= 2 * level_count
;
1821 assert(radv_image_has_cmask(image
) ||
1822 radv_dcc_enabled(image
, range
->baseMipLevel
));
1824 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, cmd_buffer
->state
.predicating
));
1825 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
1826 S_370_WR_CONFIRM(1) |
1827 S_370_ENGINE_SEL(V_370_PFP
));
1828 radeon_emit(cs
, va
);
1829 radeon_emit(cs
, va
>> 32);
1831 for (uint32_t l
= 0; l
< level_count
; l
++) {
1832 radeon_emit(cs
, color_values
[0]);
1833 radeon_emit(cs
, color_values
[1]);
1838 * Update the clear color values for this image.
1841 radv_update_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1842 const struct radv_image_view
*iview
,
1844 uint32_t color_values
[2])
1846 struct radv_image
*image
= iview
->image
;
1847 VkImageSubresourceRange range
= {
1848 .aspectMask
= iview
->aspect_mask
,
1849 .baseMipLevel
= iview
->base_mip
,
1850 .levelCount
= iview
->level_count
,
1851 .baseArrayLayer
= iview
->base_layer
,
1852 .layerCount
= iview
->layer_count
,
1855 assert(radv_image_has_cmask(image
) ||
1856 radv_dcc_enabled(image
, iview
->base_mip
));
1858 radv_set_color_clear_metadata(cmd_buffer
, image
, &range
, color_values
);
1860 radv_update_bound_fast_clear_color(cmd_buffer
, image
, cb_idx
,
1865 * Load the clear color values from the image's metadata.
1868 radv_load_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1869 struct radv_image_view
*iview
,
1872 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1873 struct radv_image
*image
= iview
->image
;
1874 uint64_t va
= radv_image_get_fast_clear_va(image
, iview
->base_mip
);
1876 if (!radv_image_has_cmask(image
) &&
1877 !radv_dcc_enabled(image
, iview
->base_mip
))
1880 uint32_t reg
= R_028C8C_CB_COLOR0_CLEAR_WORD0
+ cb_idx
* 0x3c;
1882 if (cmd_buffer
->device
->physical_device
->has_load_ctx_reg_pkt
) {
1883 radeon_emit(cs
, PKT3(PKT3_LOAD_CONTEXT_REG
, 3, cmd_buffer
->state
.predicating
));
1884 radeon_emit(cs
, va
);
1885 radeon_emit(cs
, va
>> 32);
1886 radeon_emit(cs
, (reg
- SI_CONTEXT_REG_OFFSET
) >> 2);
1889 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, cmd_buffer
->state
.predicating
));
1890 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
1891 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1892 COPY_DATA_COUNT_SEL
);
1893 radeon_emit(cs
, va
);
1894 radeon_emit(cs
, va
>> 32);
1895 radeon_emit(cs
, reg
>> 2);
1898 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, cmd_buffer
->state
.predicating
));
1904 radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer
)
1907 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1908 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1910 /* this may happen for inherited secondary recording */
1914 for (i
= 0; i
< 8; ++i
) {
1915 if (i
>= subpass
->color_count
|| subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
1916 radeon_set_context_reg(cmd_buffer
->cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
1917 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
1921 int idx
= subpass
->color_attachments
[i
].attachment
;
1922 struct radv_attachment_info
*att
= &framebuffer
->attachments
[idx
];
1923 struct radv_image_view
*iview
= att
->attachment
;
1924 VkImageLayout layout
= subpass
->color_attachments
[i
].layout
;
1926 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, att
->attachment
->bo
);
1928 assert(att
->attachment
->aspect_mask
& (VK_IMAGE_ASPECT_COLOR_BIT
| VK_IMAGE_ASPECT_PLANE_0_BIT
|
1929 VK_IMAGE_ASPECT_PLANE_1_BIT
| VK_IMAGE_ASPECT_PLANE_2_BIT
));
1930 radv_emit_fb_color_state(cmd_buffer
, i
, att
, iview
, layout
);
1932 radv_load_color_clear_metadata(cmd_buffer
, iview
, i
);
1935 if (subpass
->depth_stencil_attachment
) {
1936 int idx
= subpass
->depth_stencil_attachment
->attachment
;
1937 VkImageLayout layout
= subpass
->depth_stencil_attachment
->layout
;
1938 struct radv_attachment_info
*att
= &framebuffer
->attachments
[idx
];
1939 struct radv_image
*image
= att
->attachment
->image
;
1940 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, att
->attachment
->bo
);
1941 ASSERTED
uint32_t queue_mask
= radv_image_queue_family_mask(image
,
1942 cmd_buffer
->queue_family_index
,
1943 cmd_buffer
->queue_family_index
);
1944 /* We currently don't support writing decompressed HTILE */
1945 assert(radv_layout_has_htile(image
, layout
, queue_mask
) ==
1946 radv_layout_is_htile_compressed(image
, layout
, queue_mask
));
1948 radv_emit_fb_ds_state(cmd_buffer
, &att
->ds
, image
, layout
);
1950 if (att
->ds
.offset_scale
!= cmd_buffer
->state
.offset_scale
) {
1951 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
1952 cmd_buffer
->state
.offset_scale
= att
->ds
.offset_scale
;
1954 radv_load_ds_clear_metadata(cmd_buffer
, image
);
1956 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
)
1957 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 2);
1959 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028040_DB_Z_INFO
, 2);
1961 radeon_emit(cmd_buffer
->cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
1962 radeon_emit(cmd_buffer
->cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
1964 radeon_set_context_reg(cmd_buffer
->cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
1965 S_028208_BR_X(framebuffer
->width
) |
1966 S_028208_BR_Y(framebuffer
->height
));
1968 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX8
) {
1969 bool disable_constant_encode
=
1970 cmd_buffer
->device
->physical_device
->has_dcc_constant_encode
;
1971 enum chip_class chip_class
=
1972 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
;
1973 uint8_t watermark
= chip_class
>= GFX10
? 6 : 4;
1975 radeon_set_context_reg(cmd_buffer
->cs
, R_028424_CB_DCC_CONTROL
,
1976 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class
<= GFX9
) |
1977 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark
) |
1978 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode
));
1981 if (cmd_buffer
->device
->pbb_allowed
) {
1982 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1983 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
1986 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_FRAMEBUFFER
;
1990 radv_emit_index_buffer(struct radv_cmd_buffer
*cmd_buffer
)
1992 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1993 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
1995 if (state
->index_type
!= state
->last_index_type
) {
1996 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1997 radeon_set_uconfig_reg_idx(cmd_buffer
->device
->physical_device
,
1998 cs
, R_03090C_VGT_INDEX_TYPE
,
1999 2, state
->index_type
);
2001 radeon_emit(cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
2002 radeon_emit(cs
, state
->index_type
);
2005 state
->last_index_type
= state
->index_type
;
2008 radeon_emit(cs
, PKT3(PKT3_INDEX_BASE
, 1, 0));
2009 radeon_emit(cs
, state
->index_va
);
2010 radeon_emit(cs
, state
->index_va
>> 32);
2012 radeon_emit(cs
, PKT3(PKT3_INDEX_BUFFER_SIZE
, 0, 0));
2013 radeon_emit(cs
, state
->max_index_count
);
2015 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_INDEX_BUFFER
;
2018 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
)
2020 bool has_perfect_queries
= cmd_buffer
->state
.perfect_occlusion_queries_enabled
;
2021 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
2022 uint32_t pa_sc_mode_cntl_1
=
2023 pipeline
? pipeline
->graphics
.ms
.pa_sc_mode_cntl_1
: 0;
2024 uint32_t db_count_control
;
2026 if(!cmd_buffer
->state
.active_occlusion_queries
) {
2027 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2028 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1
) &&
2029 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
&&
2030 has_perfect_queries
) {
2031 /* Re-enable out-of-order rasterization if the
2032 * bound pipeline supports it and if it's has
2033 * been disabled before starting any perfect
2034 * occlusion queries.
2036 radeon_set_context_reg(cmd_buffer
->cs
,
2037 R_028A4C_PA_SC_MODE_CNTL_1
,
2041 db_count_control
= S_028004_ZPASS_INCREMENT_DISABLE(1);
2043 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
2044 uint32_t sample_rate
= subpass
? util_logbase2(subpass
->max_sample_count
) : 0;
2045 bool gfx10_perfect
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&& has_perfect_queries
;
2047 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2049 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries
) |
2050 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect
) |
2051 S_028004_SAMPLE_RATE(sample_rate
) |
2052 S_028004_ZPASS_ENABLE(1) |
2053 S_028004_SLICE_EVEN_ENABLE(1) |
2054 S_028004_SLICE_ODD_ENABLE(1);
2056 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1
) &&
2057 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
&&
2058 has_perfect_queries
) {
2059 /* If the bound pipeline has enabled
2060 * out-of-order rasterization, we should
2061 * disable it before starting any perfect
2062 * occlusion queries.
2064 pa_sc_mode_cntl_1
&= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE
;
2066 radeon_set_context_reg(cmd_buffer
->cs
,
2067 R_028A4C_PA_SC_MODE_CNTL_1
,
2071 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(1) |
2072 S_028004_SAMPLE_RATE(sample_rate
);
2076 radeon_set_context_reg(cmd_buffer
->cs
, R_028004_DB_COUNT_CONTROL
, db_count_control
);
2078 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
2082 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
)
2084 uint32_t states
= cmd_buffer
->state
.dirty
& cmd_buffer
->state
.emitted_pipeline
->graphics
.needed_dynamic_state
;
2086 if (states
& (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
))
2087 radv_emit_viewport(cmd_buffer
);
2089 if (states
& (RADV_CMD_DIRTY_DYNAMIC_SCISSOR
| RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
) &&
2090 !cmd_buffer
->device
->physical_device
->has_scissor_bug
)
2091 radv_emit_scissor(cmd_buffer
);
2093 if (states
& RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
)
2094 radv_emit_line_width(cmd_buffer
);
2096 if (states
& RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
)
2097 radv_emit_blend_constants(cmd_buffer
);
2099 if (states
& (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
|
2100 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
|
2101 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
))
2102 radv_emit_stencil(cmd_buffer
);
2104 if (states
& RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
)
2105 radv_emit_depth_bounds(cmd_buffer
);
2107 if (states
& RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
)
2108 radv_emit_depth_bias(cmd_buffer
);
2110 if (states
& RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
)
2111 radv_emit_discard_rectangle(cmd_buffer
);
2113 if (states
& RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS
)
2114 radv_emit_sample_locations(cmd_buffer
);
2116 cmd_buffer
->state
.dirty
&= ~states
;
2120 radv_flush_push_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
2121 VkPipelineBindPoint bind_point
)
2123 struct radv_descriptor_state
*descriptors_state
=
2124 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2125 struct radv_descriptor_set
*set
= &descriptors_state
->push_set
.set
;
2128 if (!radv_cmd_buffer_upload_data(cmd_buffer
, set
->size
, 32,
2133 set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2134 set
->va
+= bo_offset
;
2138 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer
*cmd_buffer
,
2139 VkPipelineBindPoint bind_point
)
2141 struct radv_descriptor_state
*descriptors_state
=
2142 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2143 uint32_t size
= MAX_SETS
* 4;
2147 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
,
2148 256, &offset
, &ptr
))
2151 for (unsigned i
= 0; i
< MAX_SETS
; i
++) {
2152 uint32_t *uptr
= ((uint32_t *)ptr
) + i
;
2153 uint64_t set_va
= 0;
2154 struct radv_descriptor_set
*set
= descriptors_state
->sets
[i
];
2155 if (descriptors_state
->valid
& (1u << i
))
2157 uptr
[0] = set_va
& 0xffffffff;
2160 uint64_t va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2163 if (cmd_buffer
->state
.pipeline
) {
2164 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_VERTEX
])
2165 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
2166 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2168 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_FRAGMENT
])
2169 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_FRAGMENT
,
2170 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2172 if (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
))
2173 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
2174 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2176 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
2177 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_CTRL
,
2178 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2180 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
2181 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_EVAL
,
2182 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2185 if (cmd_buffer
->state
.compute_pipeline
)
2186 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
, MESA_SHADER_COMPUTE
,
2187 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2191 radv_flush_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
2192 VkShaderStageFlags stages
)
2194 VkPipelineBindPoint bind_point
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
?
2195 VK_PIPELINE_BIND_POINT_COMPUTE
:
2196 VK_PIPELINE_BIND_POINT_GRAPHICS
;
2197 struct radv_descriptor_state
*descriptors_state
=
2198 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2199 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2200 bool flush_indirect_descriptors
;
2202 if (!descriptors_state
->dirty
)
2205 if (descriptors_state
->push_dirty
)
2206 radv_flush_push_descriptors(cmd_buffer
, bind_point
);
2208 flush_indirect_descriptors
=
2209 (bind_point
== VK_PIPELINE_BIND_POINT_GRAPHICS
&&
2210 state
->pipeline
&& state
->pipeline
->need_indirect_descriptor_sets
) ||
2211 (bind_point
== VK_PIPELINE_BIND_POINT_COMPUTE
&&
2212 state
->compute_pipeline
&& state
->compute_pipeline
->need_indirect_descriptor_sets
);
2214 if (flush_indirect_descriptors
)
2215 radv_flush_indirect_descriptor_sets(cmd_buffer
, bind_point
);
2217 ASSERTED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
2219 MAX_SETS
* MESA_SHADER_STAGES
* 4);
2221 if (cmd_buffer
->state
.pipeline
) {
2222 radv_foreach_stage(stage
, stages
) {
2223 if (!cmd_buffer
->state
.pipeline
->shaders
[stage
])
2226 radv_emit_descriptor_pointers(cmd_buffer
,
2227 cmd_buffer
->state
.pipeline
,
2228 descriptors_state
, stage
);
2232 if (cmd_buffer
->state
.compute_pipeline
&&
2233 (stages
& VK_SHADER_STAGE_COMPUTE_BIT
)) {
2234 radv_emit_descriptor_pointers(cmd_buffer
,
2235 cmd_buffer
->state
.compute_pipeline
,
2237 MESA_SHADER_COMPUTE
);
2240 descriptors_state
->dirty
= 0;
2241 descriptors_state
->push_dirty
= false;
2243 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2245 if (unlikely(cmd_buffer
->device
->trace_bo
))
2246 radv_save_descriptors(cmd_buffer
, bind_point
);
2250 radv_flush_constants(struct radv_cmd_buffer
*cmd_buffer
,
2251 VkShaderStageFlags stages
)
2253 struct radv_pipeline
*pipeline
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
2254 ? cmd_buffer
->state
.compute_pipeline
2255 : cmd_buffer
->state
.pipeline
;
2256 VkPipelineBindPoint bind_point
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
?
2257 VK_PIPELINE_BIND_POINT_COMPUTE
:
2258 VK_PIPELINE_BIND_POINT_GRAPHICS
;
2259 struct radv_descriptor_state
*descriptors_state
=
2260 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2261 struct radv_pipeline_layout
*layout
= pipeline
->layout
;
2262 struct radv_shader_variant
*shader
, *prev_shader
;
2263 bool need_push_constants
= false;
2268 stages
&= cmd_buffer
->push_constant_stages
;
2270 (!layout
->push_constant_size
&& !layout
->dynamic_offset_count
))
2273 radv_foreach_stage(stage
, stages
) {
2274 if (!pipeline
->shaders
[stage
])
2277 need_push_constants
|= pipeline
->shaders
[stage
]->info
.info
.loads_push_constants
;
2278 need_push_constants
|= pipeline
->shaders
[stage
]->info
.info
.loads_dynamic_offsets
;
2280 uint8_t base
= pipeline
->shaders
[stage
]->info
.info
.base_inline_push_consts
;
2281 uint8_t count
= pipeline
->shaders
[stage
]->info
.info
.num_inline_push_consts
;
2283 radv_emit_inline_push_consts(cmd_buffer
, pipeline
, stage
,
2284 AC_UD_INLINE_PUSH_CONSTANTS
,
2286 (uint32_t *)&cmd_buffer
->push_constants
[base
* 4]);
2289 if (need_push_constants
) {
2290 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, layout
->push_constant_size
+
2291 16 * layout
->dynamic_offset_count
,
2292 256, &offset
, &ptr
))
2295 memcpy(ptr
, cmd_buffer
->push_constants
, layout
->push_constant_size
);
2296 memcpy((char*)ptr
+ layout
->push_constant_size
,
2297 descriptors_state
->dynamic_buffers
,
2298 16 * layout
->dynamic_offset_count
);
2300 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2303 ASSERTED
unsigned cdw_max
=
2304 radeon_check_space(cmd_buffer
->device
->ws
,
2305 cmd_buffer
->cs
, MESA_SHADER_STAGES
* 4);
2308 radv_foreach_stage(stage
, stages
) {
2309 shader
= radv_get_shader(pipeline
, stage
);
2311 /* Avoid redundantly emitting the address for merged stages. */
2312 if (shader
&& shader
!= prev_shader
) {
2313 radv_emit_userdata_address(cmd_buffer
, pipeline
, stage
,
2314 AC_UD_PUSH_CONSTANTS
, va
);
2316 prev_shader
= shader
;
2319 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2322 cmd_buffer
->push_constant_stages
&= ~stages
;
2326 radv_flush_vertex_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
2327 bool pipeline_is_dirty
)
2329 if ((pipeline_is_dirty
||
2330 (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_VERTEX_BUFFER
)) &&
2331 cmd_buffer
->state
.pipeline
->num_vertex_bindings
&&
2332 radv_get_shader(cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
)->info
.info
.vs
.has_vertex_buffers
) {
2333 struct radv_vertex_elements_info
*velems
= &cmd_buffer
->state
.pipeline
->vertex_elements
;
2337 uint32_t count
= cmd_buffer
->state
.pipeline
->num_vertex_bindings
;
2340 /* allocate some descriptor state for vertex buffers */
2341 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, count
* 16, 256,
2342 &vb_offset
, &vb_ptr
))
2345 for (i
= 0; i
< count
; i
++) {
2346 uint32_t *desc
= &((uint32_t *)vb_ptr
)[i
* 4];
2348 struct radv_buffer
*buffer
= cmd_buffer
->vertex_bindings
[i
].buffer
;
2349 uint32_t stride
= cmd_buffer
->state
.pipeline
->binding_stride
[i
];
2354 va
= radv_buffer_get_va(buffer
->bo
);
2356 offset
= cmd_buffer
->vertex_bindings
[i
].offset
;
2357 va
+= offset
+ buffer
->offset
;
2359 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) | S_008F04_STRIDE(stride
);
2360 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
<= GFX7
&& stride
)
2361 desc
[2] = (buffer
->size
- offset
- velems
->format_size
[i
]) / stride
+ 1;
2363 desc
[2] = buffer
->size
- offset
;
2364 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2365 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2366 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2367 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
2369 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2370 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT
) |
2371 S_008F0C_OOB_SELECT(1) |
2372 S_008F0C_RESOURCE_LEVEL(1);
2374 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT
) |
2375 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2379 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2382 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
2383 AC_UD_VS_VERTEX_BUFFERS
, va
);
2385 cmd_buffer
->state
.vb_va
= va
;
2386 cmd_buffer
->state
.vb_size
= count
* 16;
2387 cmd_buffer
->state
.prefetch_L2_mask
|= RADV_PREFETCH_VBO_DESCRIPTORS
;
2389 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_VERTEX_BUFFER
;
2393 radv_emit_streamout_buffers(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
)
2395 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
2396 struct radv_userdata_info
*loc
;
2399 for (unsigned stage
= 0; stage
< MESA_SHADER_STAGES
; ++stage
) {
2400 if (!radv_get_shader(pipeline
, stage
))
2403 loc
= radv_lookup_user_sgpr(pipeline
, stage
,
2404 AC_UD_STREAMOUT_BUFFERS
);
2405 if (loc
->sgpr_idx
== -1)
2408 base_reg
= pipeline
->user_data_0
[stage
];
2410 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
2411 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
2414 if (radv_pipeline_has_gs_copy_shader(pipeline
)) {
2415 loc
= &pipeline
->gs_copy_shader
->info
.user_sgprs_locs
.shader_data
[AC_UD_STREAMOUT_BUFFERS
];
2416 if (loc
->sgpr_idx
!= -1) {
2417 base_reg
= R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2419 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
2420 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
2426 radv_flush_streamout_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
2428 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_STREAMOUT_BUFFER
) {
2429 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
2430 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
2435 /* Allocate some descriptor state for streamout buffers. */
2436 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
,
2437 MAX_SO_BUFFERS
* 16, 256,
2438 &so_offset
, &so_ptr
))
2441 for (uint32_t i
= 0; i
< MAX_SO_BUFFERS
; i
++) {
2442 struct radv_buffer
*buffer
= sb
[i
].buffer
;
2443 uint32_t *desc
= &((uint32_t *)so_ptr
)[i
* 4];
2445 if (!(so
->enabled_mask
& (1 << i
)))
2448 va
= radv_buffer_get_va(buffer
->bo
) + buffer
->offset
;
2452 /* Set the descriptor.
2454 * On GFX8, the format must be non-INVALID, otherwise
2455 * the buffer will be considered not bound and store
2456 * instructions will be no-ops.
2459 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
2460 desc
[2] = 0xffffffff;
2461 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2462 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2463 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2464 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
2466 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2467 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2468 S_008F0C_OOB_SELECT(3) |
2469 S_008F0C_RESOURCE_LEVEL(1);
2471 desc
[3] |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2475 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2478 radv_emit_streamout_buffers(cmd_buffer
, va
);
2481 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER
;
2485 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer
*cmd_buffer
, bool pipeline_is_dirty
)
2487 radv_flush_vertex_descriptors(cmd_buffer
, pipeline_is_dirty
);
2488 radv_flush_streamout_descriptors(cmd_buffer
);
2489 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
2490 radv_flush_constants(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
2493 struct radv_draw_info
{
2495 * Number of vertices.
2500 * Index of the first vertex.
2502 int32_t vertex_offset
;
2505 * First instance id.
2507 uint32_t first_instance
;
2510 * Number of instances.
2512 uint32_t instance_count
;
2515 * First index (indexed draws only).
2517 uint32_t first_index
;
2520 * Whether it's an indexed draw.
2525 * Indirect draw parameters resource.
2527 struct radv_buffer
*indirect
;
2528 uint64_t indirect_offset
;
2532 * Draw count parameters resource.
2534 struct radv_buffer
*count_buffer
;
2535 uint64_t count_buffer_offset
;
2538 * Stream output parameters resource.
2540 struct radv_buffer
*strmout_buffer
;
2541 uint64_t strmout_buffer_offset
;
2545 radv_get_primitive_reset_index(struct radv_cmd_buffer
*cmd_buffer
)
2547 switch (cmd_buffer
->state
.index_type
) {
2548 case V_028A7C_VGT_INDEX_8
:
2550 case V_028A7C_VGT_INDEX_16
:
2552 case V_028A7C_VGT_INDEX_32
:
2555 unreachable("invalid index type");
2560 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
2561 bool instanced_draw
, bool indirect_draw
,
2562 bool count_from_stream_output
,
2563 uint32_t draw_vertex_count
)
2565 struct radeon_info
*info
= &cmd_buffer
->device
->physical_device
->rad_info
;
2566 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2567 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
2568 unsigned ia_multi_vgt_param
;
2570 ia_multi_vgt_param
=
2571 si_get_ia_multi_vgt_param(cmd_buffer
, instanced_draw
,
2573 count_from_stream_output
,
2576 if (state
->last_ia_multi_vgt_param
!= ia_multi_vgt_param
) {
2577 if (info
->chip_class
== GFX9
) {
2578 radeon_set_uconfig_reg_idx(cmd_buffer
->device
->physical_device
,
2580 R_030960_IA_MULTI_VGT_PARAM
,
2581 4, ia_multi_vgt_param
);
2582 } else if (info
->chip_class
>= GFX7
) {
2583 radeon_set_context_reg_idx(cs
,
2584 R_028AA8_IA_MULTI_VGT_PARAM
,
2585 1, ia_multi_vgt_param
);
2587 radeon_set_context_reg(cs
, R_028AA8_IA_MULTI_VGT_PARAM
,
2588 ia_multi_vgt_param
);
2590 state
->last_ia_multi_vgt_param
= ia_multi_vgt_param
;
2595 radv_emit_draw_registers(struct radv_cmd_buffer
*cmd_buffer
,
2596 const struct radv_draw_info
*draw_info
)
2598 struct radeon_info
*info
= &cmd_buffer
->device
->physical_device
->rad_info
;
2599 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2600 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
2601 int32_t primitive_reset_en
;
2604 if (info
->chip_class
< GFX10
) {
2605 si_emit_ia_multi_vgt_param(cmd_buffer
, draw_info
->instance_count
> 1,
2606 draw_info
->indirect
,
2607 !!draw_info
->strmout_buffer
,
2608 draw_info
->indirect
? 0 : draw_info
->count
);
2611 /* Primitive restart. */
2612 primitive_reset_en
=
2613 draw_info
->indexed
&& state
->pipeline
->graphics
.prim_restart_enable
;
2615 if (primitive_reset_en
!= state
->last_primitive_reset_en
) {
2616 state
->last_primitive_reset_en
= primitive_reset_en
;
2617 if (info
->chip_class
>= GFX9
) {
2618 radeon_set_uconfig_reg(cs
,
2619 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN
,
2620 primitive_reset_en
);
2622 radeon_set_context_reg(cs
,
2623 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
,
2624 primitive_reset_en
);
2628 if (primitive_reset_en
) {
2629 uint32_t primitive_reset_index
=
2630 radv_get_primitive_reset_index(cmd_buffer
);
2632 if (primitive_reset_index
!= state
->last_primitive_reset_index
) {
2633 radeon_set_context_reg(cs
,
2634 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
,
2635 primitive_reset_index
);
2636 state
->last_primitive_reset_index
= primitive_reset_index
;
2640 if (draw_info
->strmout_buffer
) {
2641 uint64_t va
= radv_buffer_get_va(draw_info
->strmout_buffer
->bo
);
2643 va
+= draw_info
->strmout_buffer
->offset
+
2644 draw_info
->strmout_buffer_offset
;
2646 radeon_set_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
,
2649 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
2650 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
2651 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
2652 COPY_DATA_WR_CONFIRM
);
2653 radeon_emit(cs
, va
);
2654 radeon_emit(cs
, va
>> 32);
2655 radeon_emit(cs
, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2);
2656 radeon_emit(cs
, 0); /* unused */
2658 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, draw_info
->strmout_buffer
->bo
);
2662 static void radv_stage_flush(struct radv_cmd_buffer
*cmd_buffer
,
2663 VkPipelineStageFlags src_stage_mask
)
2665 if (src_stage_mask
& (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT
|
2666 VK_PIPELINE_STAGE_TRANSFER_BIT
|
2667 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
2668 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
2669 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
;
2672 if (src_stage_mask
& (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT
|
2673 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT
|
2674 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT
|
2675 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
|
2676 VK_PIPELINE_STAGE_TRANSFER_BIT
|
2677 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
2678 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT
|
2679 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
2680 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
;
2681 } else if (src_stage_mask
& (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
2682 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
|
2683 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT
|
2684 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT
|
2685 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT
|
2686 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT
|
2687 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT
)) {
2688 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VS_PARTIAL_FLUSH
;
2692 static enum radv_cmd_flush_bits
2693 radv_src_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
2694 VkAccessFlags src_flags
,
2695 struct radv_image
*image
)
2697 bool flush_CB_meta
= true, flush_DB_meta
= true;
2698 enum radv_cmd_flush_bits flush_bits
= 0;
2702 if (!radv_image_has_CB_metadata(image
))
2703 flush_CB_meta
= false;
2704 if (!radv_image_has_htile(image
))
2705 flush_DB_meta
= false;
2708 for_each_bit(b
, src_flags
) {
2709 switch ((VkAccessFlagBits
)(1 << b
)) {
2710 case VK_ACCESS_SHADER_WRITE_BIT
:
2711 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT
:
2712 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT
:
2713 flush_bits
|= RADV_CMD_FLAG_WB_L2
;
2715 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
2716 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
;
2718 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2720 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
2721 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
;
2723 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2725 case VK_ACCESS_TRANSFER_WRITE_BIT
:
2726 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
2727 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
2728 RADV_CMD_FLAG_INV_L2
;
2731 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2733 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2742 static enum radv_cmd_flush_bits
2743 radv_dst_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
2744 VkAccessFlags dst_flags
,
2745 struct radv_image
*image
)
2747 bool flush_CB_meta
= true, flush_DB_meta
= true;
2748 enum radv_cmd_flush_bits flush_bits
= 0;
2749 bool flush_CB
= true, flush_DB
= true;
2750 bool image_is_coherent
= false;
2754 if (!(image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
)) {
2759 if (!radv_image_has_CB_metadata(image
))
2760 flush_CB_meta
= false;
2761 if (!radv_image_has_htile(image
))
2762 flush_DB_meta
= false;
2764 /* TODO: implement shader coherent for GFX10 */
2766 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
2767 if (image
->info
.samples
== 1 &&
2768 (image
->usage
& (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
|
2769 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
)) &&
2770 !vk_format_is_stencil(image
->vk_format
)) {
2771 /* Single-sample color and single-sample depth
2772 * (not stencil) are coherent with shaders on
2775 image_is_coherent
= true;
2780 for_each_bit(b
, dst_flags
) {
2781 switch ((VkAccessFlagBits
)(1 << b
)) {
2782 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
2783 case VK_ACCESS_INDEX_READ_BIT
:
2784 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT
:
2786 case VK_ACCESS_UNIFORM_READ_BIT
:
2787 flush_bits
|= RADV_CMD_FLAG_INV_VCACHE
| RADV_CMD_FLAG_INV_SCACHE
;
2789 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
2790 case VK_ACCESS_TRANSFER_READ_BIT
:
2791 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
2792 flush_bits
|= RADV_CMD_FLAG_INV_VCACHE
|
2793 RADV_CMD_FLAG_INV_L2
;
2795 case VK_ACCESS_SHADER_READ_BIT
:
2796 flush_bits
|= RADV_CMD_FLAG_INV_VCACHE
;
2798 if (!image_is_coherent
)
2799 flush_bits
|= RADV_CMD_FLAG_INV_L2
;
2801 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
:
2803 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
;
2805 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2807 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT
:
2809 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
;
2811 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2820 void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
,
2821 const struct radv_subpass_barrier
*barrier
)
2823 cmd_buffer
->state
.flush_bits
|= radv_src_access_flush(cmd_buffer
, barrier
->src_access_mask
,
2825 radv_stage_flush(cmd_buffer
, barrier
->src_stage_mask
);
2826 cmd_buffer
->state
.flush_bits
|= radv_dst_access_flush(cmd_buffer
, barrier
->dst_access_mask
,
2831 radv_get_subpass_id(struct radv_cmd_buffer
*cmd_buffer
)
2833 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2834 uint32_t subpass_id
= state
->subpass
- state
->pass
->subpasses
;
2836 /* The id of this subpass shouldn't exceed the number of subpasses in
2837 * this render pass minus 1.
2839 assert(subpass_id
< state
->pass
->subpass_count
);
2843 static struct radv_sample_locations_state
*
2844 radv_get_attachment_sample_locations(struct radv_cmd_buffer
*cmd_buffer
,
2848 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2849 uint32_t subpass_id
= radv_get_subpass_id(cmd_buffer
);
2850 struct radv_image_view
*view
= state
->framebuffer
->attachments
[att_idx
].attachment
;
2852 if (view
->image
->info
.samples
== 1)
2855 if (state
->pass
->attachments
[att_idx
].first_subpass_idx
== subpass_id
) {
2856 /* Return the initial sample locations if this is the initial
2857 * layout transition of the given subpass attachemnt.
2859 if (state
->attachments
[att_idx
].sample_location
.count
> 0)
2860 return &state
->attachments
[att_idx
].sample_location
;
2862 /* Otherwise return the subpass sample locations if defined. */
2863 if (state
->subpass_sample_locs
) {
2864 /* Because the driver sets the current subpass before
2865 * initial layout transitions, we should use the sample
2866 * locations from the previous subpass to avoid an
2867 * off-by-one problem. Otherwise, use the sample
2868 * locations for the current subpass for final layout
2874 for (uint32_t i
= 0; i
< state
->num_subpass_sample_locs
; i
++) {
2875 if (state
->subpass_sample_locs
[i
].subpass_idx
== subpass_id
)
2876 return &state
->subpass_sample_locs
[i
].sample_location
;
2884 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
2885 struct radv_subpass_attachment att
,
2888 unsigned idx
= att
.attachment
;
2889 struct radv_image_view
*view
= cmd_buffer
->state
.framebuffer
->attachments
[idx
].attachment
;
2890 struct radv_sample_locations_state
*sample_locs
;
2891 VkImageSubresourceRange range
;
2892 range
.aspectMask
= 0;
2893 range
.baseMipLevel
= view
->base_mip
;
2894 range
.levelCount
= 1;
2895 range
.baseArrayLayer
= view
->base_layer
;
2896 range
.layerCount
= cmd_buffer
->state
.framebuffer
->layers
;
2898 if (cmd_buffer
->state
.subpass
->view_mask
) {
2899 /* If the current subpass uses multiview, the driver might have
2900 * performed a fast color/depth clear to the whole image
2901 * (including all layers). To make sure the driver will
2902 * decompress the image correctly (if needed), we have to
2903 * account for the "real" number of layers. If the view mask is
2904 * sparse, this will decompress more layers than needed.
2906 range
.layerCount
= util_last_bit(cmd_buffer
->state
.subpass
->view_mask
);
2909 /* Get the subpass sample locations for the given attachment, if NULL
2910 * is returned the driver will use the default HW locations.
2912 sample_locs
= radv_get_attachment_sample_locations(cmd_buffer
, idx
,
2915 radv_handle_image_transition(cmd_buffer
,
2917 cmd_buffer
->state
.attachments
[idx
].current_layout
,
2918 att
.layout
, 0, 0, &range
, sample_locs
);
2920 cmd_buffer
->state
.attachments
[idx
].current_layout
= att
.layout
;
2926 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
2927 const struct radv_subpass
*subpass
)
2929 cmd_buffer
->state
.subpass
= subpass
;
2931 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_FRAMEBUFFER
;
2935 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer
*cmd_buffer
,
2936 struct radv_render_pass
*pass
,
2937 const VkRenderPassBeginInfo
*info
)
2939 const struct VkRenderPassSampleLocationsBeginInfoEXT
*sample_locs
=
2940 vk_find_struct_const(info
->pNext
,
2941 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT
);
2942 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2943 struct radv_framebuffer
*framebuffer
= state
->framebuffer
;
2946 state
->subpass_sample_locs
= NULL
;
2950 for (uint32_t i
= 0; i
< sample_locs
->attachmentInitialSampleLocationsCount
; i
++) {
2951 const VkAttachmentSampleLocationsEXT
*att_sample_locs
=
2952 &sample_locs
->pAttachmentInitialSampleLocations
[i
];
2953 uint32_t att_idx
= att_sample_locs
->attachmentIndex
;
2954 struct radv_attachment_info
*att
= &framebuffer
->attachments
[att_idx
];
2955 struct radv_image
*image
= att
->attachment
->image
;
2957 assert(vk_format_is_depth_or_stencil(image
->vk_format
));
2959 /* From the Vulkan spec 1.1.108:
2961 * "If the image referenced by the framebuffer attachment at
2962 * index attachmentIndex was not created with
2963 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
2964 * then the values specified in sampleLocationsInfo are
2967 if (!(image
->flags
& VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
))
2970 const VkSampleLocationsInfoEXT
*sample_locs_info
=
2971 &att_sample_locs
->sampleLocationsInfo
;
2973 state
->attachments
[att_idx
].sample_location
.per_pixel
=
2974 sample_locs_info
->sampleLocationsPerPixel
;
2975 state
->attachments
[att_idx
].sample_location
.grid_size
=
2976 sample_locs_info
->sampleLocationGridSize
;
2977 state
->attachments
[att_idx
].sample_location
.count
=
2978 sample_locs_info
->sampleLocationsCount
;
2979 typed_memcpy(&state
->attachments
[att_idx
].sample_location
.locations
[0],
2980 sample_locs_info
->pSampleLocations
,
2981 sample_locs_info
->sampleLocationsCount
);
2984 state
->subpass_sample_locs
= vk_alloc(&cmd_buffer
->pool
->alloc
,
2985 sample_locs
->postSubpassSampleLocationsCount
*
2986 sizeof(state
->subpass_sample_locs
[0]),
2987 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2988 if (state
->subpass_sample_locs
== NULL
) {
2989 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2990 return cmd_buffer
->record_result
;
2993 state
->num_subpass_sample_locs
= sample_locs
->postSubpassSampleLocationsCount
;
2995 for (uint32_t i
= 0; i
< sample_locs
->postSubpassSampleLocationsCount
; i
++) {
2996 const VkSubpassSampleLocationsEXT
*subpass_sample_locs_info
=
2997 &sample_locs
->pPostSubpassSampleLocations
[i
];
2998 const VkSampleLocationsInfoEXT
*sample_locs_info
=
2999 &subpass_sample_locs_info
->sampleLocationsInfo
;
3001 state
->subpass_sample_locs
[i
].subpass_idx
=
3002 subpass_sample_locs_info
->subpassIndex
;
3003 state
->subpass_sample_locs
[i
].sample_location
.per_pixel
=
3004 sample_locs_info
->sampleLocationsPerPixel
;
3005 state
->subpass_sample_locs
[i
].sample_location
.grid_size
=
3006 sample_locs_info
->sampleLocationGridSize
;
3007 state
->subpass_sample_locs
[i
].sample_location
.count
=
3008 sample_locs_info
->sampleLocationsCount
;
3009 typed_memcpy(&state
->subpass_sample_locs
[i
].sample_location
.locations
[0],
3010 sample_locs_info
->pSampleLocations
,
3011 sample_locs_info
->sampleLocationsCount
);
3018 radv_cmd_state_setup_attachments(struct radv_cmd_buffer
*cmd_buffer
,
3019 struct radv_render_pass
*pass
,
3020 const VkRenderPassBeginInfo
*info
)
3022 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3024 if (pass
->attachment_count
== 0) {
3025 state
->attachments
= NULL
;
3029 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
3030 pass
->attachment_count
*
3031 sizeof(state
->attachments
[0]),
3032 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3033 if (state
->attachments
== NULL
) {
3034 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
3035 return cmd_buffer
->record_result
;
3038 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
3039 struct radv_render_pass_attachment
*att
= &pass
->attachments
[i
];
3040 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
3041 VkImageAspectFlags clear_aspects
= 0;
3043 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
3044 /* color attachment */
3045 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
3046 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
3049 /* depthstencil attachment */
3050 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
3051 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
3052 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
3053 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
3054 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_DONT_CARE
)
3055 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
3057 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
3058 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
3059 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
3063 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
3064 state
->attachments
[i
].cleared_views
= 0;
3065 if (clear_aspects
&& info
) {
3066 assert(info
->clearValueCount
> i
);
3067 state
->attachments
[i
].clear_value
= info
->pClearValues
[i
];
3070 state
->attachments
[i
].current_layout
= att
->initial_layout
;
3071 state
->attachments
[i
].sample_location
.count
= 0;
3077 VkResult
radv_AllocateCommandBuffers(
3079 const VkCommandBufferAllocateInfo
*pAllocateInfo
,
3080 VkCommandBuffer
*pCommandBuffers
)
3082 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3083 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
3085 VkResult result
= VK_SUCCESS
;
3088 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
3090 if (!list_empty(&pool
->free_cmd_buffers
)) {
3091 struct radv_cmd_buffer
*cmd_buffer
= list_first_entry(&pool
->free_cmd_buffers
, struct radv_cmd_buffer
, pool_link
);
3093 list_del(&cmd_buffer
->pool_link
);
3094 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
3096 result
= radv_reset_cmd_buffer(cmd_buffer
);
3097 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
3098 cmd_buffer
->level
= pAllocateInfo
->level
;
3100 pCommandBuffers
[i
] = radv_cmd_buffer_to_handle(cmd_buffer
);
3102 result
= radv_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
3103 &pCommandBuffers
[i
]);
3105 if (result
!= VK_SUCCESS
)
3109 if (result
!= VK_SUCCESS
) {
3110 radv_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
,
3111 i
, pCommandBuffers
);
3113 /* From the Vulkan 1.0.66 spec:
3115 * "vkAllocateCommandBuffers can be used to create multiple
3116 * command buffers. If the creation of any of those command
3117 * buffers fails, the implementation must destroy all
3118 * successfully created command buffer objects from this
3119 * command, set all entries of the pCommandBuffers array to
3120 * NULL and return the error."
3122 memset(pCommandBuffers
, 0,
3123 sizeof(*pCommandBuffers
) * pAllocateInfo
->commandBufferCount
);
3129 void radv_FreeCommandBuffers(
3131 VkCommandPool commandPool
,
3132 uint32_t commandBufferCount
,
3133 const VkCommandBuffer
*pCommandBuffers
)
3135 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
3136 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
3139 if (cmd_buffer
->pool
) {
3140 list_del(&cmd_buffer
->pool_link
);
3141 list_addtail(&cmd_buffer
->pool_link
, &cmd_buffer
->pool
->free_cmd_buffers
);
3143 radv_cmd_buffer_destroy(cmd_buffer
);
3149 VkResult
radv_ResetCommandBuffer(
3150 VkCommandBuffer commandBuffer
,
3151 VkCommandBufferResetFlags flags
)
3153 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3154 return radv_reset_cmd_buffer(cmd_buffer
);
3157 VkResult
radv_BeginCommandBuffer(
3158 VkCommandBuffer commandBuffer
,
3159 const VkCommandBufferBeginInfo
*pBeginInfo
)
3161 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3162 VkResult result
= VK_SUCCESS
;
3164 if (cmd_buffer
->status
!= RADV_CMD_BUFFER_STATUS_INITIAL
) {
3165 /* If the command buffer has already been resetted with
3166 * vkResetCommandBuffer, no need to do it again.
3168 result
= radv_reset_cmd_buffer(cmd_buffer
);
3169 if (result
!= VK_SUCCESS
)
3173 memset(&cmd_buffer
->state
, 0, sizeof(cmd_buffer
->state
));
3174 cmd_buffer
->state
.last_primitive_reset_en
= -1;
3175 cmd_buffer
->state
.last_index_type
= -1;
3176 cmd_buffer
->state
.last_num_instances
= -1;
3177 cmd_buffer
->state
.last_vertex_offset
= -1;
3178 cmd_buffer
->state
.last_first_instance
= -1;
3179 cmd_buffer
->state
.predication_type
= -1;
3180 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
3182 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
&&
3183 (pBeginInfo
->flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
)) {
3184 assert(pBeginInfo
->pInheritanceInfo
);
3185 cmd_buffer
->state
.framebuffer
= radv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
3186 cmd_buffer
->state
.pass
= radv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
3188 struct radv_subpass
*subpass
=
3189 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
3191 result
= radv_cmd_state_setup_attachments(cmd_buffer
, cmd_buffer
->state
.pass
, NULL
);
3192 if (result
!= VK_SUCCESS
)
3195 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
);
3198 if (unlikely(cmd_buffer
->device
->trace_bo
)) {
3199 struct radv_device
*device
= cmd_buffer
->device
;
3201 radv_cs_add_buffer(device
->ws
, cmd_buffer
->cs
,
3204 radv_cmd_buffer_trace_emit(cmd_buffer
);
3207 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_RECORDING
;
3212 void radv_CmdBindVertexBuffers(
3213 VkCommandBuffer commandBuffer
,
3214 uint32_t firstBinding
,
3215 uint32_t bindingCount
,
3216 const VkBuffer
* pBuffers
,
3217 const VkDeviceSize
* pOffsets
)
3219 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3220 struct radv_vertex_binding
*vb
= cmd_buffer
->vertex_bindings
;
3221 bool changed
= false;
3223 /* We have to defer setting up vertex buffer since we need the buffer
3224 * stride from the pipeline. */
3226 assert(firstBinding
+ bindingCount
<= MAX_VBS
);
3227 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
3228 uint32_t idx
= firstBinding
+ i
;
3231 (vb
[idx
].buffer
!= radv_buffer_from_handle(pBuffers
[i
]) ||
3232 vb
[idx
].offset
!= pOffsets
[i
])) {
3236 vb
[idx
].buffer
= radv_buffer_from_handle(pBuffers
[i
]);
3237 vb
[idx
].offset
= pOffsets
[i
];
3239 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
3240 vb
[idx
].buffer
->bo
);
3244 /* No state changes. */
3248 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_VERTEX_BUFFER
;
3252 vk_to_index_type(VkIndexType type
)
3255 case VK_INDEX_TYPE_UINT8_EXT
:
3256 return V_028A7C_VGT_INDEX_8
;
3257 case VK_INDEX_TYPE_UINT16
:
3258 return V_028A7C_VGT_INDEX_16
;
3259 case VK_INDEX_TYPE_UINT32
:
3260 return V_028A7C_VGT_INDEX_32
;
3262 unreachable("invalid index type");
3267 radv_get_vgt_index_size(uint32_t type
)
3270 case V_028A7C_VGT_INDEX_8
:
3272 case V_028A7C_VGT_INDEX_16
:
3274 case V_028A7C_VGT_INDEX_32
:
3277 unreachable("invalid index type");
3281 void radv_CmdBindIndexBuffer(
3282 VkCommandBuffer commandBuffer
,
3284 VkDeviceSize offset
,
3285 VkIndexType indexType
)
3287 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3288 RADV_FROM_HANDLE(radv_buffer
, index_buffer
, buffer
);
3290 if (cmd_buffer
->state
.index_buffer
== index_buffer
&&
3291 cmd_buffer
->state
.index_offset
== offset
&&
3292 cmd_buffer
->state
.index_type
== indexType
) {
3293 /* No state changes. */
3297 cmd_buffer
->state
.index_buffer
= index_buffer
;
3298 cmd_buffer
->state
.index_offset
= offset
;
3299 cmd_buffer
->state
.index_type
= vk_to_index_type(indexType
);
3300 cmd_buffer
->state
.index_va
= radv_buffer_get_va(index_buffer
->bo
);
3301 cmd_buffer
->state
.index_va
+= index_buffer
->offset
+ offset
;
3303 int index_size
= radv_get_vgt_index_size(indexType
);
3304 cmd_buffer
->state
.max_index_count
= (index_buffer
->size
- offset
) / index_size
;
3305 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
3306 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, index_buffer
->bo
);
3311 radv_bind_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
3312 VkPipelineBindPoint bind_point
,
3313 struct radv_descriptor_set
*set
, unsigned idx
)
3315 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
3317 radv_set_descriptor_set(cmd_buffer
, bind_point
, set
, idx
);
3320 assert(!(set
->layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
));
3322 if (!cmd_buffer
->device
->use_global_bo_list
) {
3323 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
)
3324 if (set
->descriptors
[j
])
3325 radv_cs_add_buffer(ws
, cmd_buffer
->cs
, set
->descriptors
[j
]);
3329 radv_cs_add_buffer(ws
, cmd_buffer
->cs
, set
->bo
);
3332 void radv_CmdBindDescriptorSets(
3333 VkCommandBuffer commandBuffer
,
3334 VkPipelineBindPoint pipelineBindPoint
,
3335 VkPipelineLayout _layout
,
3337 uint32_t descriptorSetCount
,
3338 const VkDescriptorSet
* pDescriptorSets
,
3339 uint32_t dynamicOffsetCount
,
3340 const uint32_t* pDynamicOffsets
)
3342 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3343 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
3344 unsigned dyn_idx
= 0;
3346 const bool no_dynamic_bounds
= cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_NO_DYNAMIC_BOUNDS
;
3347 struct radv_descriptor_state
*descriptors_state
=
3348 radv_get_descriptors_state(cmd_buffer
, pipelineBindPoint
);
3350 for (unsigned i
= 0; i
< descriptorSetCount
; ++i
) {
3351 unsigned idx
= i
+ firstSet
;
3352 RADV_FROM_HANDLE(radv_descriptor_set
, set
, pDescriptorSets
[i
]);
3354 /* If the set is already bound we only need to update the
3355 * (potentially changed) dynamic offsets. */
3356 if (descriptors_state
->sets
[idx
] != set
||
3357 !(descriptors_state
->valid
& (1u << idx
))) {
3358 radv_bind_descriptor_set(cmd_buffer
, pipelineBindPoint
, set
, idx
);
3361 for(unsigned j
= 0; j
< set
->layout
->dynamic_offset_count
; ++j
, ++dyn_idx
) {
3362 unsigned idx
= j
+ layout
->set
[i
+ firstSet
].dynamic_offset_start
;
3363 uint32_t *dst
= descriptors_state
->dynamic_buffers
+ idx
* 4;
3364 assert(dyn_idx
< dynamicOffsetCount
);
3366 struct radv_descriptor_range
*range
= set
->dynamic_descriptors
+ j
;
3367 uint64_t va
= range
->va
+ pDynamicOffsets
[dyn_idx
];
3369 dst
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
3370 dst
[2] = no_dynamic_bounds
? 0xffffffffu
: range
->size
;
3371 dst
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3372 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3373 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3374 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3376 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3377 dst
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3378 S_008F0C_OOB_SELECT(3) |
3379 S_008F0C_RESOURCE_LEVEL(1);
3381 dst
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3382 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3385 cmd_buffer
->push_constant_stages
|=
3386 set
->layout
->dynamic_shader_stages
;
3391 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
3392 struct radv_descriptor_set
*set
,
3393 struct radv_descriptor_set_layout
*layout
,
3394 VkPipelineBindPoint bind_point
)
3396 struct radv_descriptor_state
*descriptors_state
=
3397 radv_get_descriptors_state(cmd_buffer
, bind_point
);
3398 set
->size
= layout
->size
;
3399 set
->layout
= layout
;
3401 if (descriptors_state
->push_set
.capacity
< set
->size
) {
3402 size_t new_size
= MAX2(set
->size
, 1024);
3403 new_size
= MAX2(new_size
, 2 * descriptors_state
->push_set
.capacity
);
3404 new_size
= MIN2(new_size
, 96 * MAX_PUSH_DESCRIPTORS
);
3406 free(set
->mapped_ptr
);
3407 set
->mapped_ptr
= malloc(new_size
);
3409 if (!set
->mapped_ptr
) {
3410 descriptors_state
->push_set
.capacity
= 0;
3411 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
3415 descriptors_state
->push_set
.capacity
= new_size
;
3421 void radv_meta_push_descriptor_set(
3422 struct radv_cmd_buffer
* cmd_buffer
,
3423 VkPipelineBindPoint pipelineBindPoint
,
3424 VkPipelineLayout _layout
,
3426 uint32_t descriptorWriteCount
,
3427 const VkWriteDescriptorSet
* pDescriptorWrites
)
3429 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
3430 struct radv_descriptor_set
*push_set
= &cmd_buffer
->meta_push_descriptors
;
3434 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
3436 push_set
->size
= layout
->set
[set
].layout
->size
;
3437 push_set
->layout
= layout
->set
[set
].layout
;
3439 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, push_set
->size
, 32,
3441 (void**) &push_set
->mapped_ptr
))
3444 push_set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
3445 push_set
->va
+= bo_offset
;
3447 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
3448 radv_descriptor_set_to_handle(push_set
),
3449 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
3451 radv_set_descriptor_set(cmd_buffer
, pipelineBindPoint
, push_set
, set
);
3454 void radv_CmdPushDescriptorSetKHR(
3455 VkCommandBuffer commandBuffer
,
3456 VkPipelineBindPoint pipelineBindPoint
,
3457 VkPipelineLayout _layout
,
3459 uint32_t descriptorWriteCount
,
3460 const VkWriteDescriptorSet
* pDescriptorWrites
)
3462 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3463 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
3464 struct radv_descriptor_state
*descriptors_state
=
3465 radv_get_descriptors_state(cmd_buffer
, pipelineBindPoint
);
3466 struct radv_descriptor_set
*push_set
= &descriptors_state
->push_set
.set
;
3468 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
3470 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
,
3471 layout
->set
[set
].layout
,
3475 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3476 * because it is invalid, according to Vulkan spec.
3478 for (int i
= 0; i
< descriptorWriteCount
; i
++) {
3479 ASSERTED
const VkWriteDescriptorSet
*writeset
= &pDescriptorWrites
[i
];
3480 assert(writeset
->descriptorType
!= VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
);
3483 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
3484 radv_descriptor_set_to_handle(push_set
),
3485 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
3487 radv_set_descriptor_set(cmd_buffer
, pipelineBindPoint
, push_set
, set
);
3488 descriptors_state
->push_dirty
= true;
3491 void radv_CmdPushDescriptorSetWithTemplateKHR(
3492 VkCommandBuffer commandBuffer
,
3493 VkDescriptorUpdateTemplate descriptorUpdateTemplate
,
3494 VkPipelineLayout _layout
,
3498 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3499 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
3500 RADV_FROM_HANDLE(radv_descriptor_update_template
, templ
, descriptorUpdateTemplate
);
3501 struct radv_descriptor_state
*descriptors_state
=
3502 radv_get_descriptors_state(cmd_buffer
, templ
->bind_point
);
3503 struct radv_descriptor_set
*push_set
= &descriptors_state
->push_set
.set
;
3505 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
3507 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
,
3508 layout
->set
[set
].layout
,
3512 radv_update_descriptor_set_with_template(cmd_buffer
->device
, cmd_buffer
, push_set
,
3513 descriptorUpdateTemplate
, pData
);
3515 radv_set_descriptor_set(cmd_buffer
, templ
->bind_point
, push_set
, set
);
3516 descriptors_state
->push_dirty
= true;
3519 void radv_CmdPushConstants(VkCommandBuffer commandBuffer
,
3520 VkPipelineLayout layout
,
3521 VkShaderStageFlags stageFlags
,
3524 const void* pValues
)
3526 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3527 memcpy(cmd_buffer
->push_constants
+ offset
, pValues
, size
);
3528 cmd_buffer
->push_constant_stages
|= stageFlags
;
3531 VkResult
radv_EndCommandBuffer(
3532 VkCommandBuffer commandBuffer
)
3534 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3536 if (cmd_buffer
->queue_family_index
!= RADV_QUEUE_TRANSFER
) {
3537 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX6
)
3538 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
| RADV_CMD_FLAG_WB_L2
;
3540 /* Make sure to sync all pending active queries at the end of
3543 cmd_buffer
->state
.flush_bits
|= cmd_buffer
->active_query_flush_bits
;
3545 si_emit_cache_flush(cmd_buffer
);
3548 /* Make sure CP DMA is idle at the end of IBs because the kernel
3549 * doesn't wait for it.
3551 si_cp_dma_wait_for_idle(cmd_buffer
);
3553 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
3554 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.subpass_sample_locs
);
3556 if (!cmd_buffer
->device
->ws
->cs_finalize(cmd_buffer
->cs
))
3557 return vk_error(cmd_buffer
->device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
3559 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_EXECUTABLE
;
3561 return cmd_buffer
->record_result
;
3565 radv_emit_compute_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
3567 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
3569 if (!pipeline
|| pipeline
== cmd_buffer
->state
.emitted_compute_pipeline
)
3572 assert(!pipeline
->ctx_cs
.cdw
);
3574 cmd_buffer
->state
.emitted_compute_pipeline
= pipeline
;
3576 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, pipeline
->cs
.cdw
);
3577 radeon_emit_array(cmd_buffer
->cs
, pipeline
->cs
.buf
, pipeline
->cs
.cdw
);
3579 cmd_buffer
->compute_scratch_size_needed
=
3580 MAX2(cmd_buffer
->compute_scratch_size_needed
,
3581 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
3583 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
3584 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->bo
);
3586 if (unlikely(cmd_buffer
->device
->trace_bo
))
3587 radv_save_pipeline(cmd_buffer
, pipeline
, RING_COMPUTE
);
3590 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer
*cmd_buffer
,
3591 VkPipelineBindPoint bind_point
)
3593 struct radv_descriptor_state
*descriptors_state
=
3594 radv_get_descriptors_state(cmd_buffer
, bind_point
);
3596 descriptors_state
->dirty
|= descriptors_state
->valid
;
3599 void radv_CmdBindPipeline(
3600 VkCommandBuffer commandBuffer
,
3601 VkPipelineBindPoint pipelineBindPoint
,
3602 VkPipeline _pipeline
)
3604 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3605 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
3607 switch (pipelineBindPoint
) {
3608 case VK_PIPELINE_BIND_POINT_COMPUTE
:
3609 if (cmd_buffer
->state
.compute_pipeline
== pipeline
)
3611 radv_mark_descriptor_sets_dirty(cmd_buffer
, pipelineBindPoint
);
3613 cmd_buffer
->state
.compute_pipeline
= pipeline
;
3614 cmd_buffer
->push_constant_stages
|= VK_SHADER_STAGE_COMPUTE_BIT
;
3616 case VK_PIPELINE_BIND_POINT_GRAPHICS
:
3617 if (cmd_buffer
->state
.pipeline
== pipeline
)
3619 radv_mark_descriptor_sets_dirty(cmd_buffer
, pipelineBindPoint
);
3621 cmd_buffer
->state
.pipeline
= pipeline
;
3625 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
;
3626 cmd_buffer
->push_constant_stages
|= pipeline
->active_stages
;
3628 /* the new vertex shader might not have the same user regs */
3629 cmd_buffer
->state
.last_first_instance
= -1;
3630 cmd_buffer
->state
.last_vertex_offset
= -1;
3632 /* Prefetch all pipeline shaders at first draw time. */
3633 cmd_buffer
->state
.prefetch_L2_mask
|= RADV_PREFETCH_SHADERS
;
3635 if ((cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_NAVI10
||
3636 cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_NAVI12
||
3637 cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_NAVI14
) &&
3638 cmd_buffer
->state
.emitted_pipeline
&&
3639 radv_pipeline_has_ngg(cmd_buffer
->state
.emitted_pipeline
) &&
3640 !radv_pipeline_has_ngg(cmd_buffer
->state
.pipeline
)) {
3641 /* Transitioning from NGG to legacy GS requires
3642 * VGT_FLUSH on Navi10-14. VGT_FLUSH is also emitted
3643 * at the beginning of IBs when legacy GS ring pointers
3646 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VGT_FLUSH
;
3649 radv_bind_dynamic_state(cmd_buffer
, &pipeline
->dynamic_state
);
3650 radv_bind_streamout_state(cmd_buffer
, pipeline
);
3652 if (pipeline
->graphics
.esgs_ring_size
> cmd_buffer
->esgs_ring_size_needed
)
3653 cmd_buffer
->esgs_ring_size_needed
= pipeline
->graphics
.esgs_ring_size
;
3654 if (pipeline
->graphics
.gsvs_ring_size
> cmd_buffer
->gsvs_ring_size_needed
)
3655 cmd_buffer
->gsvs_ring_size_needed
= pipeline
->graphics
.gsvs_ring_size
;
3657 if (radv_pipeline_has_tess(pipeline
))
3658 cmd_buffer
->tess_rings_needed
= true;
3661 assert(!"invalid bind point");
3666 void radv_CmdSetViewport(
3667 VkCommandBuffer commandBuffer
,
3668 uint32_t firstViewport
,
3669 uint32_t viewportCount
,
3670 const VkViewport
* pViewports
)
3672 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3673 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3674 ASSERTED
const uint32_t total_count
= firstViewport
+ viewportCount
;
3676 assert(firstViewport
< MAX_VIEWPORTS
);
3677 assert(total_count
>= 1 && total_count
<= MAX_VIEWPORTS
);
3679 if (!memcmp(state
->dynamic
.viewport
.viewports
+ firstViewport
,
3680 pViewports
, viewportCount
* sizeof(*pViewports
))) {
3684 memcpy(state
->dynamic
.viewport
.viewports
+ firstViewport
, pViewports
,
3685 viewportCount
* sizeof(*pViewports
));
3687 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
3690 void radv_CmdSetScissor(
3691 VkCommandBuffer commandBuffer
,
3692 uint32_t firstScissor
,
3693 uint32_t scissorCount
,
3694 const VkRect2D
* pScissors
)
3696 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3697 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3698 ASSERTED
const uint32_t total_count
= firstScissor
+ scissorCount
;
3700 assert(firstScissor
< MAX_SCISSORS
);
3701 assert(total_count
>= 1 && total_count
<= MAX_SCISSORS
);
3703 if (!memcmp(state
->dynamic
.scissor
.scissors
+ firstScissor
, pScissors
,
3704 scissorCount
* sizeof(*pScissors
))) {
3708 memcpy(state
->dynamic
.scissor
.scissors
+ firstScissor
, pScissors
,
3709 scissorCount
* sizeof(*pScissors
));
3711 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
3714 void radv_CmdSetLineWidth(
3715 VkCommandBuffer commandBuffer
,
3718 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3720 if (cmd_buffer
->state
.dynamic
.line_width
== lineWidth
)
3723 cmd_buffer
->state
.dynamic
.line_width
= lineWidth
;
3724 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
3727 void radv_CmdSetDepthBias(
3728 VkCommandBuffer commandBuffer
,
3729 float depthBiasConstantFactor
,
3730 float depthBiasClamp
,
3731 float depthBiasSlopeFactor
)
3733 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3734 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3736 if (state
->dynamic
.depth_bias
.bias
== depthBiasConstantFactor
&&
3737 state
->dynamic
.depth_bias
.clamp
== depthBiasClamp
&&
3738 state
->dynamic
.depth_bias
.slope
== depthBiasSlopeFactor
) {
3742 state
->dynamic
.depth_bias
.bias
= depthBiasConstantFactor
;
3743 state
->dynamic
.depth_bias
.clamp
= depthBiasClamp
;
3744 state
->dynamic
.depth_bias
.slope
= depthBiasSlopeFactor
;
3746 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
3749 void radv_CmdSetBlendConstants(
3750 VkCommandBuffer commandBuffer
,
3751 const float blendConstants
[4])
3753 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3754 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3756 if (!memcmp(state
->dynamic
.blend_constants
, blendConstants
, sizeof(float) * 4))
3759 memcpy(state
->dynamic
.blend_constants
, blendConstants
, sizeof(float) * 4);
3761 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
3764 void radv_CmdSetDepthBounds(
3765 VkCommandBuffer commandBuffer
,
3766 float minDepthBounds
,
3767 float maxDepthBounds
)
3769 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3770 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3772 if (state
->dynamic
.depth_bounds
.min
== minDepthBounds
&&
3773 state
->dynamic
.depth_bounds
.max
== maxDepthBounds
) {
3777 state
->dynamic
.depth_bounds
.min
= minDepthBounds
;
3778 state
->dynamic
.depth_bounds
.max
= maxDepthBounds
;
3780 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
3783 void radv_CmdSetStencilCompareMask(
3784 VkCommandBuffer commandBuffer
,
3785 VkStencilFaceFlags faceMask
,
3786 uint32_t compareMask
)
3788 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3789 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3790 bool front_same
= state
->dynamic
.stencil_compare_mask
.front
== compareMask
;
3791 bool back_same
= state
->dynamic
.stencil_compare_mask
.back
== compareMask
;
3793 if ((!(faceMask
& VK_STENCIL_FACE_FRONT_BIT
) || front_same
) &&
3794 (!(faceMask
& VK_STENCIL_FACE_BACK_BIT
) || back_same
)) {
3798 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
3799 state
->dynamic
.stencil_compare_mask
.front
= compareMask
;
3800 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
3801 state
->dynamic
.stencil_compare_mask
.back
= compareMask
;
3803 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
3806 void radv_CmdSetStencilWriteMask(
3807 VkCommandBuffer commandBuffer
,
3808 VkStencilFaceFlags faceMask
,
3811 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3812 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3813 bool front_same
= state
->dynamic
.stencil_write_mask
.front
== writeMask
;
3814 bool back_same
= state
->dynamic
.stencil_write_mask
.back
== writeMask
;
3816 if ((!(faceMask
& VK_STENCIL_FACE_FRONT_BIT
) || front_same
) &&
3817 (!(faceMask
& VK_STENCIL_FACE_BACK_BIT
) || back_same
)) {
3821 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
3822 state
->dynamic
.stencil_write_mask
.front
= writeMask
;
3823 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
3824 state
->dynamic
.stencil_write_mask
.back
= writeMask
;
3826 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
3829 void radv_CmdSetStencilReference(
3830 VkCommandBuffer commandBuffer
,
3831 VkStencilFaceFlags faceMask
,
3834 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3835 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3836 bool front_same
= state
->dynamic
.stencil_reference
.front
== reference
;
3837 bool back_same
= state
->dynamic
.stencil_reference
.back
== reference
;
3839 if ((!(faceMask
& VK_STENCIL_FACE_FRONT_BIT
) || front_same
) &&
3840 (!(faceMask
& VK_STENCIL_FACE_BACK_BIT
) || back_same
)) {
3844 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
3845 cmd_buffer
->state
.dynamic
.stencil_reference
.front
= reference
;
3846 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
3847 cmd_buffer
->state
.dynamic
.stencil_reference
.back
= reference
;
3849 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
3852 void radv_CmdSetDiscardRectangleEXT(
3853 VkCommandBuffer commandBuffer
,
3854 uint32_t firstDiscardRectangle
,
3855 uint32_t discardRectangleCount
,
3856 const VkRect2D
* pDiscardRectangles
)
3858 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3859 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3860 ASSERTED
const uint32_t total_count
= firstDiscardRectangle
+ discardRectangleCount
;
3862 assert(firstDiscardRectangle
< MAX_DISCARD_RECTANGLES
);
3863 assert(total_count
>= 1 && total_count
<= MAX_DISCARD_RECTANGLES
);
3865 if (!memcmp(state
->dynamic
.discard_rectangle
.rectangles
+ firstDiscardRectangle
,
3866 pDiscardRectangles
, discardRectangleCount
* sizeof(*pDiscardRectangles
))) {
3870 typed_memcpy(&state
->dynamic
.discard_rectangle
.rectangles
[firstDiscardRectangle
],
3871 pDiscardRectangles
, discardRectangleCount
);
3873 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
;
3876 void radv_CmdSetSampleLocationsEXT(
3877 VkCommandBuffer commandBuffer
,
3878 const VkSampleLocationsInfoEXT
* pSampleLocationsInfo
)
3880 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3881 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3883 assert(pSampleLocationsInfo
->sampleLocationsCount
<= MAX_SAMPLE_LOCATIONS
);
3885 state
->dynamic
.sample_location
.per_pixel
= pSampleLocationsInfo
->sampleLocationsPerPixel
;
3886 state
->dynamic
.sample_location
.grid_size
= pSampleLocationsInfo
->sampleLocationGridSize
;
3887 state
->dynamic
.sample_location
.count
= pSampleLocationsInfo
->sampleLocationsCount
;
3888 typed_memcpy(&state
->dynamic
.sample_location
.locations
[0],
3889 pSampleLocationsInfo
->pSampleLocations
,
3890 pSampleLocationsInfo
->sampleLocationsCount
);
3892 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS
;
3895 void radv_CmdExecuteCommands(
3896 VkCommandBuffer commandBuffer
,
3897 uint32_t commandBufferCount
,
3898 const VkCommandBuffer
* pCmdBuffers
)
3900 RADV_FROM_HANDLE(radv_cmd_buffer
, primary
, commandBuffer
);
3902 assert(commandBufferCount
> 0);
3904 /* Emit pending flushes on primary prior to executing secondary */
3905 si_emit_cache_flush(primary
);
3907 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
3908 RADV_FROM_HANDLE(radv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
3910 primary
->scratch_size_needed
= MAX2(primary
->scratch_size_needed
,
3911 secondary
->scratch_size_needed
);
3912 primary
->compute_scratch_size_needed
= MAX2(primary
->compute_scratch_size_needed
,
3913 secondary
->compute_scratch_size_needed
);
3915 if (secondary
->esgs_ring_size_needed
> primary
->esgs_ring_size_needed
)
3916 primary
->esgs_ring_size_needed
= secondary
->esgs_ring_size_needed
;
3917 if (secondary
->gsvs_ring_size_needed
> primary
->gsvs_ring_size_needed
)
3918 primary
->gsvs_ring_size_needed
= secondary
->gsvs_ring_size_needed
;
3919 if (secondary
->tess_rings_needed
)
3920 primary
->tess_rings_needed
= true;
3921 if (secondary
->sample_positions_needed
)
3922 primary
->sample_positions_needed
= true;
3924 if (!secondary
->state
.framebuffer
&&
3925 (primary
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
)) {
3926 /* Emit the framebuffer state from primary if secondary
3927 * has been recorded without a framebuffer, otherwise
3928 * fast color/depth clears can't work.
3930 radv_emit_framebuffer_state(primary
);
3933 primary
->device
->ws
->cs_execute_secondary(primary
->cs
, secondary
->cs
);
3936 /* When the secondary command buffer is compute only we don't
3937 * need to re-emit the current graphics pipeline.
3939 if (secondary
->state
.emitted_pipeline
) {
3940 primary
->state
.emitted_pipeline
=
3941 secondary
->state
.emitted_pipeline
;
3944 /* When the secondary command buffer is graphics only we don't
3945 * need to re-emit the current compute pipeline.
3947 if (secondary
->state
.emitted_compute_pipeline
) {
3948 primary
->state
.emitted_compute_pipeline
=
3949 secondary
->state
.emitted_compute_pipeline
;
3952 /* Only re-emit the draw packets when needed. */
3953 if (secondary
->state
.last_primitive_reset_en
!= -1) {
3954 primary
->state
.last_primitive_reset_en
=
3955 secondary
->state
.last_primitive_reset_en
;
3958 if (secondary
->state
.last_primitive_reset_index
) {
3959 primary
->state
.last_primitive_reset_index
=
3960 secondary
->state
.last_primitive_reset_index
;
3963 if (secondary
->state
.last_ia_multi_vgt_param
) {
3964 primary
->state
.last_ia_multi_vgt_param
=
3965 secondary
->state
.last_ia_multi_vgt_param
;
3968 primary
->state
.last_first_instance
= secondary
->state
.last_first_instance
;
3969 primary
->state
.last_num_instances
= secondary
->state
.last_num_instances
;
3970 primary
->state
.last_vertex_offset
= secondary
->state
.last_vertex_offset
;
3972 if (secondary
->state
.last_index_type
!= -1) {
3973 primary
->state
.last_index_type
=
3974 secondary
->state
.last_index_type
;
3978 /* After executing commands from secondary buffers we have to dirty
3981 primary
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
|
3982 RADV_CMD_DIRTY_INDEX_BUFFER
|
3983 RADV_CMD_DIRTY_DYNAMIC_ALL
;
3984 radv_mark_descriptor_sets_dirty(primary
, VK_PIPELINE_BIND_POINT_GRAPHICS
);
3985 radv_mark_descriptor_sets_dirty(primary
, VK_PIPELINE_BIND_POINT_COMPUTE
);
3988 VkResult
radv_CreateCommandPool(
3990 const VkCommandPoolCreateInfo
* pCreateInfo
,
3991 const VkAllocationCallbacks
* pAllocator
,
3992 VkCommandPool
* pCmdPool
)
3994 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3995 struct radv_cmd_pool
*pool
;
3997 pool
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pool
), 8,
3998 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4000 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4003 pool
->alloc
= *pAllocator
;
4005 pool
->alloc
= device
->alloc
;
4007 list_inithead(&pool
->cmd_buffers
);
4008 list_inithead(&pool
->free_cmd_buffers
);
4010 pool
->queue_family_index
= pCreateInfo
->queueFamilyIndex
;
4012 *pCmdPool
= radv_cmd_pool_to_handle(pool
);
4018 void radv_DestroyCommandPool(
4020 VkCommandPool commandPool
,
4021 const VkAllocationCallbacks
* pAllocator
)
4023 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4024 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
4029 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
4030 &pool
->cmd_buffers
, pool_link
) {
4031 radv_cmd_buffer_destroy(cmd_buffer
);
4034 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
4035 &pool
->free_cmd_buffers
, pool_link
) {
4036 radv_cmd_buffer_destroy(cmd_buffer
);
4039 vk_free2(&device
->alloc
, pAllocator
, pool
);
4042 VkResult
radv_ResetCommandPool(
4044 VkCommandPool commandPool
,
4045 VkCommandPoolResetFlags flags
)
4047 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
4050 list_for_each_entry(struct radv_cmd_buffer
, cmd_buffer
,
4051 &pool
->cmd_buffers
, pool_link
) {
4052 result
= radv_reset_cmd_buffer(cmd_buffer
);
4053 if (result
!= VK_SUCCESS
)
4060 void radv_TrimCommandPool(
4062 VkCommandPool commandPool
,
4063 VkCommandPoolTrimFlags flags
)
4065 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
4070 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
4071 &pool
->free_cmd_buffers
, pool_link
) {
4072 radv_cmd_buffer_destroy(cmd_buffer
);
4077 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer
*cmd_buffer
,
4078 uint32_t subpass_id
)
4080 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4081 struct radv_subpass
*subpass
= &state
->pass
->subpasses
[subpass_id
];
4083 ASSERTED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
4084 cmd_buffer
->cs
, 4096);
4086 radv_subpass_barrier(cmd_buffer
, &subpass
->start_barrier
);
4088 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
);
4090 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4091 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4092 if (a
== VK_ATTACHMENT_UNUSED
)
4095 radv_handle_subpass_image_transition(cmd_buffer
,
4096 subpass
->attachments
[i
],
4100 radv_cmd_buffer_clear_subpass(cmd_buffer
);
4102 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4106 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer
*cmd_buffer
)
4108 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4109 const struct radv_subpass
*subpass
= state
->subpass
;
4110 uint32_t subpass_id
= radv_get_subpass_id(cmd_buffer
);
4112 radv_cmd_buffer_resolve_subpass(cmd_buffer
);
4114 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4115 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4116 if (a
== VK_ATTACHMENT_UNUSED
)
4119 if (state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
4122 VkImageLayout layout
= state
->pass
->attachments
[a
].final_layout
;
4123 struct radv_subpass_attachment att
= { a
, layout
};
4124 radv_handle_subpass_image_transition(cmd_buffer
, att
, false);
4128 void radv_CmdBeginRenderPass(
4129 VkCommandBuffer commandBuffer
,
4130 const VkRenderPassBeginInfo
* pRenderPassBegin
,
4131 VkSubpassContents contents
)
4133 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4134 RADV_FROM_HANDLE(radv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
4135 RADV_FROM_HANDLE(radv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
4138 cmd_buffer
->state
.framebuffer
= framebuffer
;
4139 cmd_buffer
->state
.pass
= pass
;
4140 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
4142 result
= radv_cmd_state_setup_attachments(cmd_buffer
, pass
, pRenderPassBegin
);
4143 if (result
!= VK_SUCCESS
)
4146 result
= radv_cmd_state_setup_sample_locations(cmd_buffer
, pass
, pRenderPassBegin
);
4147 if (result
!= VK_SUCCESS
)
4150 radv_cmd_buffer_begin_subpass(cmd_buffer
, 0);
4153 void radv_CmdBeginRenderPass2KHR(
4154 VkCommandBuffer commandBuffer
,
4155 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
4156 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
)
4158 radv_CmdBeginRenderPass(commandBuffer
, pRenderPassBeginInfo
,
4159 pSubpassBeginInfo
->contents
);
4162 void radv_CmdNextSubpass(
4163 VkCommandBuffer commandBuffer
,
4164 VkSubpassContents contents
)
4166 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4168 uint32_t prev_subpass
= radv_get_subpass_id(cmd_buffer
);
4169 radv_cmd_buffer_end_subpass(cmd_buffer
);
4170 radv_cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
4173 void radv_CmdNextSubpass2KHR(
4174 VkCommandBuffer commandBuffer
,
4175 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
,
4176 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
4178 radv_CmdNextSubpass(commandBuffer
, pSubpassBeginInfo
->contents
);
4181 static void radv_emit_view_index(struct radv_cmd_buffer
*cmd_buffer
, unsigned index
)
4183 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
4184 for (unsigned stage
= 0; stage
< MESA_SHADER_STAGES
; ++stage
) {
4185 if (!radv_get_shader(pipeline
, stage
))
4188 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, AC_UD_VIEW_INDEX
);
4189 if (loc
->sgpr_idx
== -1)
4191 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
4192 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
4195 if (radv_pipeline_has_gs_copy_shader(pipeline
)) {
4196 struct radv_userdata_info
*loc
= &pipeline
->gs_copy_shader
->info
.user_sgprs_locs
.shader_data
[AC_UD_VIEW_INDEX
];
4197 if (loc
->sgpr_idx
!= -1) {
4198 uint32_t base_reg
= R_00B130_SPI_SHADER_USER_DATA_VS_0
;
4199 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
4205 radv_cs_emit_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
4206 uint32_t vertex_count
,
4209 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, cmd_buffer
->state
.predicating
));
4210 radeon_emit(cmd_buffer
->cs
, vertex_count
);
4211 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
4212 S_0287F0_USE_OPAQUE(use_opaque
));
4216 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer
*cmd_buffer
,
4218 uint32_t index_count
)
4220 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_2
, 4, cmd_buffer
->state
.predicating
));
4221 radeon_emit(cmd_buffer
->cs
, cmd_buffer
->state
.max_index_count
);
4222 radeon_emit(cmd_buffer
->cs
, index_va
);
4223 radeon_emit(cmd_buffer
->cs
, index_va
>> 32);
4224 radeon_emit(cmd_buffer
->cs
, index_count
);
4225 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_DMA
);
4229 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
4231 uint32_t draw_count
,
4235 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4236 unsigned di_src_sel
= indexed
? V_0287F0_DI_SRC_SEL_DMA
4237 : V_0287F0_DI_SRC_SEL_AUTO_INDEX
;
4238 bool draw_id_enable
= radv_get_shader(cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
)->info
.info
.vs
.needs_draw_id
;
4239 uint32_t base_reg
= cmd_buffer
->state
.pipeline
->graphics
.vtx_base_sgpr
;
4240 bool predicating
= cmd_buffer
->state
.predicating
;
4243 /* just reset draw state for vertex data */
4244 cmd_buffer
->state
.last_first_instance
= -1;
4245 cmd_buffer
->state
.last_num_instances
= -1;
4246 cmd_buffer
->state
.last_vertex_offset
= -1;
4248 if (draw_count
== 1 && !count_va
&& !draw_id_enable
) {
4249 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT
:
4250 PKT3_DRAW_INDIRECT
, 3, predicating
));
4252 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
4253 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
4254 radeon_emit(cs
, di_src_sel
);
4256 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT_MULTI
:
4257 PKT3_DRAW_INDIRECT_MULTI
,
4260 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
4261 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
4262 radeon_emit(cs
, (((base_reg
+ 8) - SI_SH_REG_OFFSET
) >> 2) |
4263 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable
) |
4264 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va
));
4265 radeon_emit(cs
, draw_count
); /* count */
4266 radeon_emit(cs
, count_va
); /* count_addr */
4267 radeon_emit(cs
, count_va
>> 32);
4268 radeon_emit(cs
, stride
); /* stride */
4269 radeon_emit(cs
, di_src_sel
);
4274 radv_emit_draw_packets(struct radv_cmd_buffer
*cmd_buffer
,
4275 const struct radv_draw_info
*info
)
4277 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4278 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
4279 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4281 if (info
->indirect
) {
4282 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
4283 uint64_t count_va
= 0;
4285 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
4287 radv_cs_add_buffer(ws
, cs
, info
->indirect
->bo
);
4289 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0));
4291 radeon_emit(cs
, va
);
4292 radeon_emit(cs
, va
>> 32);
4294 if (info
->count_buffer
) {
4295 count_va
= radv_buffer_get_va(info
->count_buffer
->bo
);
4296 count_va
+= info
->count_buffer
->offset
+
4297 info
->count_buffer_offset
;
4299 radv_cs_add_buffer(ws
, cs
, info
->count_buffer
->bo
);
4302 if (!state
->subpass
->view_mask
) {
4303 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
4310 for_each_bit(i
, state
->subpass
->view_mask
) {
4311 radv_emit_view_index(cmd_buffer
, i
);
4313 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
4321 assert(state
->pipeline
->graphics
.vtx_base_sgpr
);
4323 if (info
->vertex_offset
!= state
->last_vertex_offset
||
4324 info
->first_instance
!= state
->last_first_instance
) {
4325 radeon_set_sh_reg_seq(cs
, state
->pipeline
->graphics
.vtx_base_sgpr
,
4326 state
->pipeline
->graphics
.vtx_emit_num
);
4328 radeon_emit(cs
, info
->vertex_offset
);
4329 radeon_emit(cs
, info
->first_instance
);
4330 if (state
->pipeline
->graphics
.vtx_emit_num
== 3)
4332 state
->last_first_instance
= info
->first_instance
;
4333 state
->last_vertex_offset
= info
->vertex_offset
;
4336 if (state
->last_num_instances
!= info
->instance_count
) {
4337 radeon_emit(cs
, PKT3(PKT3_NUM_INSTANCES
, 0, false));
4338 radeon_emit(cs
, info
->instance_count
);
4339 state
->last_num_instances
= info
->instance_count
;
4342 if (info
->indexed
) {
4343 int index_size
= radv_get_vgt_index_size(state
->index_type
);
4346 /* Skip draw calls with 0-sized index buffers. They
4347 * cause a hang on some chips, like Navi10-14.
4349 if (!cmd_buffer
->state
.max_index_count
)
4352 index_va
= state
->index_va
;
4353 index_va
+= info
->first_index
* index_size
;
4355 if (!state
->subpass
->view_mask
) {
4356 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
4361 for_each_bit(i
, state
->subpass
->view_mask
) {
4362 radv_emit_view_index(cmd_buffer
, i
);
4364 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
4370 if (!state
->subpass
->view_mask
) {
4371 radv_cs_emit_draw_packet(cmd_buffer
,
4373 !!info
->strmout_buffer
);
4376 for_each_bit(i
, state
->subpass
->view_mask
) {
4377 radv_emit_view_index(cmd_buffer
, i
);
4379 radv_cs_emit_draw_packet(cmd_buffer
,
4381 !!info
->strmout_buffer
);
4389 * Vega and raven have a bug which triggers if there are multiple context
4390 * register contexts active at the same time with different scissor values.
4392 * There are two possible workarounds:
4393 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
4394 * there is only ever 1 active set of scissor values at the same time.
4396 * 2) Whenever the hardware switches contexts we have to set the scissor
4397 * registers again even if it is a noop. That way the new context gets
4398 * the correct scissor values.
4400 * This implements option 2. radv_need_late_scissor_emission needs to
4401 * return true on affected HW if radv_emit_all_graphics_states sets
4402 * any context registers.
4404 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer
*cmd_buffer
,
4405 const struct radv_draw_info
*info
)
4407 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4409 if (!cmd_buffer
->device
->physical_device
->has_scissor_bug
)
4412 if (cmd_buffer
->state
.context_roll_without_scissor_emitted
|| info
->strmout_buffer
)
4415 uint32_t used_states
= cmd_buffer
->state
.pipeline
->graphics
.needed_dynamic_state
| ~RADV_CMD_DIRTY_DYNAMIC_ALL
;
4417 /* Index, vertex and streamout buffers don't change context regs, and
4418 * pipeline is already handled.
4420 used_states
&= ~(RADV_CMD_DIRTY_INDEX_BUFFER
|
4421 RADV_CMD_DIRTY_VERTEX_BUFFER
|
4422 RADV_CMD_DIRTY_STREAMOUT_BUFFER
|
4423 RADV_CMD_DIRTY_PIPELINE
);
4425 if (cmd_buffer
->state
.dirty
& used_states
)
4428 uint32_t primitive_reset_index
=
4429 radv_get_primitive_reset_index(cmd_buffer
);
4431 if (info
->indexed
&& state
->pipeline
->graphics
.prim_restart_enable
&&
4432 primitive_reset_index
!= state
->last_primitive_reset_index
)
4439 radv_emit_all_graphics_states(struct radv_cmd_buffer
*cmd_buffer
,
4440 const struct radv_draw_info
*info
)
4442 bool late_scissor_emission
;
4444 if ((cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
) ||
4445 cmd_buffer
->state
.emitted_pipeline
!= cmd_buffer
->state
.pipeline
)
4446 radv_emit_rbplus_state(cmd_buffer
);
4448 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
)
4449 radv_emit_graphics_pipeline(cmd_buffer
);
4451 /* This should be before the cmd_buffer->state.dirty is cleared
4452 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4453 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4454 late_scissor_emission
=
4455 radv_need_late_scissor_emission(cmd_buffer
, info
);
4457 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
)
4458 radv_emit_framebuffer_state(cmd_buffer
);
4460 if (info
->indexed
) {
4461 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_INDEX_BUFFER
)
4462 radv_emit_index_buffer(cmd_buffer
);
4464 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4465 * so the state must be re-emitted before the next indexed
4468 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4469 cmd_buffer
->state
.last_index_type
= -1;
4470 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
4474 radv_cmd_buffer_flush_dynamic_state(cmd_buffer
);
4476 radv_emit_draw_registers(cmd_buffer
, info
);
4478 if (late_scissor_emission
)
4479 radv_emit_scissor(cmd_buffer
);
4483 radv_draw(struct radv_cmd_buffer
*cmd_buffer
,
4484 const struct radv_draw_info
*info
)
4486 struct radeon_info
*rad_info
=
4487 &cmd_buffer
->device
->physical_device
->rad_info
;
4489 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
4490 bool pipeline_is_dirty
=
4491 (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
) &&
4492 cmd_buffer
->state
.pipeline
!= cmd_buffer
->state
.emitted_pipeline
;
4494 ASSERTED
unsigned cdw_max
=
4495 radeon_check_space(cmd_buffer
->device
->ws
,
4496 cmd_buffer
->cs
, 4096);
4498 if (likely(!info
->indirect
)) {
4499 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4500 * no workaround for indirect draws, but we can at least skip
4503 if (unlikely(!info
->instance_count
))
4506 /* Handle count == 0. */
4507 if (unlikely(!info
->count
&& !info
->strmout_buffer
))
4511 /* Use optimal packet order based on whether we need to sync the
4514 if (cmd_buffer
->state
.flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4515 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4516 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
4517 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)) {
4518 /* If we have to wait for idle, set all states first, so that
4519 * all SET packets are processed in parallel with previous draw
4520 * calls. Then upload descriptors, set shader pointers, and
4521 * draw, and prefetch at the end. This ensures that the time
4522 * the CUs are idle is very short. (there are only SET_SH
4523 * packets between the wait and the draw)
4525 radv_emit_all_graphics_states(cmd_buffer
, info
);
4526 si_emit_cache_flush(cmd_buffer
);
4527 /* <-- CUs are idle here --> */
4529 radv_upload_graphics_shader_descriptors(cmd_buffer
, pipeline_is_dirty
);
4531 radv_emit_draw_packets(cmd_buffer
, info
);
4532 /* <-- CUs are busy here --> */
4534 /* Start prefetches after the draw has been started. Both will
4535 * run in parallel, but starting the draw first is more
4538 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
4539 radv_emit_prefetch_L2(cmd_buffer
,
4540 cmd_buffer
->state
.pipeline
, false);
4543 /* If we don't wait for idle, start prefetches first, then set
4544 * states, and draw at the end.
4546 si_emit_cache_flush(cmd_buffer
);
4548 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
4549 /* Only prefetch the vertex shader and VBO descriptors
4550 * in order to start the draw as soon as possible.
4552 radv_emit_prefetch_L2(cmd_buffer
,
4553 cmd_buffer
->state
.pipeline
, true);
4556 radv_upload_graphics_shader_descriptors(cmd_buffer
, pipeline_is_dirty
);
4558 radv_emit_all_graphics_states(cmd_buffer
, info
);
4559 radv_emit_draw_packets(cmd_buffer
, info
);
4561 /* Prefetch the remaining shaders after the draw has been
4564 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
4565 radv_emit_prefetch_L2(cmd_buffer
,
4566 cmd_buffer
->state
.pipeline
, false);
4570 /* Workaround for a VGT hang when streamout is enabled.
4571 * It must be done after drawing.
4573 if (cmd_buffer
->state
.streamout
.streamout_enabled
&&
4574 (rad_info
->family
== CHIP_HAWAII
||
4575 rad_info
->family
== CHIP_TONGA
||
4576 rad_info
->family
== CHIP_FIJI
)) {
4577 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC
;
4580 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4581 radv_cmd_buffer_after_draw(cmd_buffer
, RADV_CMD_FLAG_PS_PARTIAL_FLUSH
);
4585 VkCommandBuffer commandBuffer
,
4586 uint32_t vertexCount
,
4587 uint32_t instanceCount
,
4588 uint32_t firstVertex
,
4589 uint32_t firstInstance
)
4591 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4592 struct radv_draw_info info
= {};
4594 info
.count
= vertexCount
;
4595 info
.instance_count
= instanceCount
;
4596 info
.first_instance
= firstInstance
;
4597 info
.vertex_offset
= firstVertex
;
4599 radv_draw(cmd_buffer
, &info
);
4602 void radv_CmdDrawIndexed(
4603 VkCommandBuffer commandBuffer
,
4604 uint32_t indexCount
,
4605 uint32_t instanceCount
,
4606 uint32_t firstIndex
,
4607 int32_t vertexOffset
,
4608 uint32_t firstInstance
)
4610 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4611 struct radv_draw_info info
= {};
4613 info
.indexed
= true;
4614 info
.count
= indexCount
;
4615 info
.instance_count
= instanceCount
;
4616 info
.first_index
= firstIndex
;
4617 info
.vertex_offset
= vertexOffset
;
4618 info
.first_instance
= firstInstance
;
4620 radv_draw(cmd_buffer
, &info
);
4623 void radv_CmdDrawIndirect(
4624 VkCommandBuffer commandBuffer
,
4626 VkDeviceSize offset
,
4630 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4631 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4632 struct radv_draw_info info
= {};
4634 info
.count
= drawCount
;
4635 info
.indirect
= buffer
;
4636 info
.indirect_offset
= offset
;
4637 info
.stride
= stride
;
4639 radv_draw(cmd_buffer
, &info
);
4642 void radv_CmdDrawIndexedIndirect(
4643 VkCommandBuffer commandBuffer
,
4645 VkDeviceSize offset
,
4649 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4650 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4651 struct radv_draw_info info
= {};
4653 info
.indexed
= true;
4654 info
.count
= drawCount
;
4655 info
.indirect
= buffer
;
4656 info
.indirect_offset
= offset
;
4657 info
.stride
= stride
;
4659 radv_draw(cmd_buffer
, &info
);
4662 void radv_CmdDrawIndirectCountKHR(
4663 VkCommandBuffer commandBuffer
,
4665 VkDeviceSize offset
,
4666 VkBuffer _countBuffer
,
4667 VkDeviceSize countBufferOffset
,
4668 uint32_t maxDrawCount
,
4671 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4672 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4673 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
4674 struct radv_draw_info info
= {};
4676 info
.count
= maxDrawCount
;
4677 info
.indirect
= buffer
;
4678 info
.indirect_offset
= offset
;
4679 info
.count_buffer
= count_buffer
;
4680 info
.count_buffer_offset
= countBufferOffset
;
4681 info
.stride
= stride
;
4683 radv_draw(cmd_buffer
, &info
);
4686 void radv_CmdDrawIndexedIndirectCountKHR(
4687 VkCommandBuffer commandBuffer
,
4689 VkDeviceSize offset
,
4690 VkBuffer _countBuffer
,
4691 VkDeviceSize countBufferOffset
,
4692 uint32_t maxDrawCount
,
4695 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4696 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4697 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
4698 struct radv_draw_info info
= {};
4700 info
.indexed
= true;
4701 info
.count
= maxDrawCount
;
4702 info
.indirect
= buffer
;
4703 info
.indirect_offset
= offset
;
4704 info
.count_buffer
= count_buffer
;
4705 info
.count_buffer_offset
= countBufferOffset
;
4706 info
.stride
= stride
;
4708 radv_draw(cmd_buffer
, &info
);
4711 struct radv_dispatch_info
{
4713 * Determine the layout of the grid (in block units) to be used.
4718 * A starting offset for the grid. If unaligned is set, the offset
4719 * must still be aligned.
4721 uint32_t offsets
[3];
4723 * Whether it's an unaligned compute dispatch.
4728 * Indirect compute parameters resource.
4730 struct radv_buffer
*indirect
;
4731 uint64_t indirect_offset
;
4735 radv_emit_dispatch_packets(struct radv_cmd_buffer
*cmd_buffer
,
4736 const struct radv_dispatch_info
*info
)
4738 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
4739 struct radv_shader_variant
*compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
4740 unsigned dispatch_initiator
= cmd_buffer
->device
->dispatch_initiator
;
4741 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
4742 bool predicating
= cmd_buffer
->state
.predicating
;
4743 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4744 struct radv_userdata_info
*loc
;
4746 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_COMPUTE
,
4747 AC_UD_CS_GRID_SIZE
);
4749 ASSERTED
unsigned cdw_max
= radeon_check_space(ws
, cs
, 25);
4751 if (info
->indirect
) {
4752 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
4754 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
4756 radv_cs_add_buffer(ws
, cs
, info
->indirect
->bo
);
4758 if (loc
->sgpr_idx
!= -1) {
4759 for (unsigned i
= 0; i
< 3; ++i
) {
4760 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
4761 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
4762 COPY_DATA_DST_SEL(COPY_DATA_REG
));
4763 radeon_emit(cs
, (va
+ 4 * i
));
4764 radeon_emit(cs
, (va
+ 4 * i
) >> 32);
4765 radeon_emit(cs
, ((R_00B900_COMPUTE_USER_DATA_0
4766 + loc
->sgpr_idx
* 4) >> 2) + i
);
4771 if (radv_cmd_buffer_uses_mec(cmd_buffer
)) {
4772 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 2, predicating
) |
4773 PKT3_SHADER_TYPE_S(1));
4774 radeon_emit(cs
, va
);
4775 radeon_emit(cs
, va
>> 32);
4776 radeon_emit(cs
, dispatch_initiator
);
4778 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0) |
4779 PKT3_SHADER_TYPE_S(1));
4781 radeon_emit(cs
, va
);
4782 radeon_emit(cs
, va
>> 32);
4784 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 1, predicating
) |
4785 PKT3_SHADER_TYPE_S(1));
4787 radeon_emit(cs
, dispatch_initiator
);
4790 unsigned blocks
[3] = { info
->blocks
[0], info
->blocks
[1], info
->blocks
[2] };
4791 unsigned offsets
[3] = { info
->offsets
[0], info
->offsets
[1], info
->offsets
[2] };
4793 if (info
->unaligned
) {
4794 unsigned *cs_block_size
= compute_shader
->info
.cs
.block_size
;
4795 unsigned remainder
[3];
4797 /* If aligned, these should be an entire block size,
4800 remainder
[0] = blocks
[0] + cs_block_size
[0] -
4801 align_u32_npot(blocks
[0], cs_block_size
[0]);
4802 remainder
[1] = blocks
[1] + cs_block_size
[1] -
4803 align_u32_npot(blocks
[1], cs_block_size
[1]);
4804 remainder
[2] = blocks
[2] + cs_block_size
[2] -
4805 align_u32_npot(blocks
[2], cs_block_size
[2]);
4807 blocks
[0] = round_up_u32(blocks
[0], cs_block_size
[0]);
4808 blocks
[1] = round_up_u32(blocks
[1], cs_block_size
[1]);
4809 blocks
[2] = round_up_u32(blocks
[2], cs_block_size
[2]);
4811 for(unsigned i
= 0; i
< 3; ++i
) {
4812 assert(offsets
[i
] % cs_block_size
[i
] == 0);
4813 offsets
[i
] /= cs_block_size
[i
];
4816 radeon_set_sh_reg_seq(cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
4818 S_00B81C_NUM_THREAD_FULL(cs_block_size
[0]) |
4819 S_00B81C_NUM_THREAD_PARTIAL(remainder
[0]));
4821 S_00B81C_NUM_THREAD_FULL(cs_block_size
[1]) |
4822 S_00B81C_NUM_THREAD_PARTIAL(remainder
[1]));
4824 S_00B81C_NUM_THREAD_FULL(cs_block_size
[2]) |
4825 S_00B81C_NUM_THREAD_PARTIAL(remainder
[2]));
4827 dispatch_initiator
|= S_00B800_PARTIAL_TG_EN(1);
4830 if (loc
->sgpr_idx
!= -1) {
4831 assert(loc
->num_sgprs
== 3);
4833 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
+
4834 loc
->sgpr_idx
* 4, 3);
4835 radeon_emit(cs
, blocks
[0]);
4836 radeon_emit(cs
, blocks
[1]);
4837 radeon_emit(cs
, blocks
[2]);
4840 if (offsets
[0] || offsets
[1] || offsets
[2]) {
4841 radeon_set_sh_reg_seq(cs
, R_00B810_COMPUTE_START_X
, 3);
4842 radeon_emit(cs
, offsets
[0]);
4843 radeon_emit(cs
, offsets
[1]);
4844 radeon_emit(cs
, offsets
[2]);
4846 /* The blocks in the packet are not counts but end values. */
4847 for (unsigned i
= 0; i
< 3; ++i
)
4848 blocks
[i
] += offsets
[i
];
4850 dispatch_initiator
|= S_00B800_FORCE_START_AT_000(1);
4853 radeon_emit(cs
, PKT3(PKT3_DISPATCH_DIRECT
, 3, predicating
) |
4854 PKT3_SHADER_TYPE_S(1));
4855 radeon_emit(cs
, blocks
[0]);
4856 radeon_emit(cs
, blocks
[1]);
4857 radeon_emit(cs
, blocks
[2]);
4858 radeon_emit(cs
, dispatch_initiator
);
4861 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4865 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
4867 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
4868 radv_flush_constants(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
4872 radv_dispatch(struct radv_cmd_buffer
*cmd_buffer
,
4873 const struct radv_dispatch_info
*info
)
4875 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
4877 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
4878 bool pipeline_is_dirty
= pipeline
&&
4879 pipeline
!= cmd_buffer
->state
.emitted_compute_pipeline
;
4881 if (cmd_buffer
->state
.flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4882 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4883 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
4884 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)) {
4885 /* If we have to wait for idle, set all states first, so that
4886 * all SET packets are processed in parallel with previous draw
4887 * calls. Then upload descriptors, set shader pointers, and
4888 * dispatch, and prefetch at the end. This ensures that the
4889 * time the CUs are idle is very short. (there are only SET_SH
4890 * packets between the wait and the draw)
4892 radv_emit_compute_pipeline(cmd_buffer
);
4893 si_emit_cache_flush(cmd_buffer
);
4894 /* <-- CUs are idle here --> */
4896 radv_upload_compute_shader_descriptors(cmd_buffer
);
4898 radv_emit_dispatch_packets(cmd_buffer
, info
);
4899 /* <-- CUs are busy here --> */
4901 /* Start prefetches after the dispatch has been started. Both
4902 * will run in parallel, but starting the dispatch first is
4905 if (has_prefetch
&& pipeline_is_dirty
) {
4906 radv_emit_shader_prefetch(cmd_buffer
,
4907 pipeline
->shaders
[MESA_SHADER_COMPUTE
]);
4910 /* If we don't wait for idle, start prefetches first, then set
4911 * states, and dispatch at the end.
4913 si_emit_cache_flush(cmd_buffer
);
4915 if (has_prefetch
&& pipeline_is_dirty
) {
4916 radv_emit_shader_prefetch(cmd_buffer
,
4917 pipeline
->shaders
[MESA_SHADER_COMPUTE
]);
4920 radv_upload_compute_shader_descriptors(cmd_buffer
);
4922 radv_emit_compute_pipeline(cmd_buffer
);
4923 radv_emit_dispatch_packets(cmd_buffer
, info
);
4926 radv_cmd_buffer_after_draw(cmd_buffer
, RADV_CMD_FLAG_CS_PARTIAL_FLUSH
);
4929 void radv_CmdDispatchBase(
4930 VkCommandBuffer commandBuffer
,
4938 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4939 struct radv_dispatch_info info
= {};
4945 info
.offsets
[0] = base_x
;
4946 info
.offsets
[1] = base_y
;
4947 info
.offsets
[2] = base_z
;
4948 radv_dispatch(cmd_buffer
, &info
);
4951 void radv_CmdDispatch(
4952 VkCommandBuffer commandBuffer
,
4957 radv_CmdDispatchBase(commandBuffer
, 0, 0, 0, x
, y
, z
);
4960 void radv_CmdDispatchIndirect(
4961 VkCommandBuffer commandBuffer
,
4963 VkDeviceSize offset
)
4965 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4966 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4967 struct radv_dispatch_info info
= {};
4969 info
.indirect
= buffer
;
4970 info
.indirect_offset
= offset
;
4972 radv_dispatch(cmd_buffer
, &info
);
4975 void radv_unaligned_dispatch(
4976 struct radv_cmd_buffer
*cmd_buffer
,
4981 struct radv_dispatch_info info
= {};
4988 radv_dispatch(cmd_buffer
, &info
);
4991 void radv_CmdEndRenderPass(
4992 VkCommandBuffer commandBuffer
)
4994 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4996 radv_subpass_barrier(cmd_buffer
, &cmd_buffer
->state
.pass
->end_barrier
);
4998 radv_cmd_buffer_end_subpass(cmd_buffer
);
5000 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
5001 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.subpass_sample_locs
);
5003 cmd_buffer
->state
.pass
= NULL
;
5004 cmd_buffer
->state
.subpass
= NULL
;
5005 cmd_buffer
->state
.attachments
= NULL
;
5006 cmd_buffer
->state
.framebuffer
= NULL
;
5007 cmd_buffer
->state
.subpass_sample_locs
= NULL
;
5010 void radv_CmdEndRenderPass2KHR(
5011 VkCommandBuffer commandBuffer
,
5012 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
5014 radv_CmdEndRenderPass(commandBuffer
);
5018 * For HTILE we have the following interesting clear words:
5019 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
5020 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
5021 * 0xfffffff0: Clear depth to 1.0
5022 * 0x00000000: Clear depth to 0.0
5024 static void radv_initialize_htile(struct radv_cmd_buffer
*cmd_buffer
,
5025 struct radv_image
*image
,
5026 const VkImageSubresourceRange
*range
,
5027 uint32_t clear_word
)
5029 assert(range
->baseMipLevel
== 0);
5030 assert(range
->levelCount
== 1 || range
->levelCount
== VK_REMAINING_ARRAY_LAYERS
);
5031 VkImageAspectFlags aspects
= VK_IMAGE_ASPECT_DEPTH_BIT
;
5032 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
5033 VkClearDepthStencilValue value
= {};
5035 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
5036 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
5038 state
->flush_bits
|= radv_clear_htile(cmd_buffer
, image
, range
, clear_word
);
5040 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
5042 if (vk_format_is_stencil(image
->vk_format
))
5043 aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
5045 radv_set_ds_clear_metadata(cmd_buffer
, image
, value
, aspects
);
5047 if (radv_image_is_tc_compat_htile(image
)) {
5048 /* Initialize the TC-compat metada value to 0 because by
5049 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
5050 * need have to conditionally update its value when performing
5051 * a fast depth clear.
5053 radv_set_tc_compat_zrange_metadata(cmd_buffer
, image
, 0);
5057 static void radv_handle_depth_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
5058 struct radv_image
*image
,
5059 VkImageLayout src_layout
,
5060 VkImageLayout dst_layout
,
5061 unsigned src_queue_mask
,
5062 unsigned dst_queue_mask
,
5063 const VkImageSubresourceRange
*range
,
5064 struct radv_sample_locations_state
*sample_locs
)
5066 if (!radv_image_has_htile(image
))
5069 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
5070 uint32_t clear_value
= vk_format_is_stencil(image
->vk_format
) ? 0xfffff30f : 0xfffc000f;
5072 if (radv_layout_is_htile_compressed(image
, dst_layout
,
5077 radv_initialize_htile(cmd_buffer
, image
, range
, clear_value
);
5078 } else if (!radv_layout_is_htile_compressed(image
, src_layout
, src_queue_mask
) &&
5079 radv_layout_is_htile_compressed(image
, dst_layout
, dst_queue_mask
)) {
5080 uint32_t clear_value
= vk_format_is_stencil(image
->vk_format
) ? 0xfffff30f : 0xfffc000f;
5081 radv_initialize_htile(cmd_buffer
, image
, range
, clear_value
);
5082 } else if (radv_layout_is_htile_compressed(image
, src_layout
, src_queue_mask
) &&
5083 !radv_layout_is_htile_compressed(image
, dst_layout
, dst_queue_mask
)) {
5084 VkImageSubresourceRange local_range
= *range
;
5085 local_range
.aspectMask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
5086 local_range
.baseMipLevel
= 0;
5087 local_range
.levelCount
= 1;
5089 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
5090 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
5092 radv_decompress_depth_image_inplace(cmd_buffer
, image
,
5093 &local_range
, sample_locs
);
5095 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
5096 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
5100 static void radv_initialise_cmask(struct radv_cmd_buffer
*cmd_buffer
,
5101 struct radv_image
*image
,
5102 const VkImageSubresourceRange
*range
,
5105 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
5107 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
5108 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5110 state
->flush_bits
|= radv_clear_cmask(cmd_buffer
, image
, range
, value
);
5112 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5115 void radv_initialize_fmask(struct radv_cmd_buffer
*cmd_buffer
,
5116 struct radv_image
*image
,
5117 const VkImageSubresourceRange
*range
)
5119 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
5120 static const uint32_t fmask_clear_values
[4] = {
5126 uint32_t log2_samples
= util_logbase2(image
->info
.samples
);
5127 uint32_t value
= fmask_clear_values
[log2_samples
];
5129 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
5130 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5132 state
->flush_bits
|= radv_clear_fmask(cmd_buffer
, image
, range
, value
);
5134 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5137 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
5138 struct radv_image
*image
,
5139 const VkImageSubresourceRange
*range
, uint32_t value
)
5141 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
5144 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
5145 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5147 state
->flush_bits
|= radv_clear_dcc(cmd_buffer
, image
, range
, value
);
5149 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX8
) {
5150 /* When DCC is enabled with mipmaps, some levels might not
5151 * support fast clears and we have to initialize them as "fully
5154 /* Compute the size of all fast clearable DCC levels. */
5155 for (unsigned i
= 0; i
< image
->planes
[0].surface
.num_dcc_levels
; i
++) {
5156 struct legacy_surf_level
*surf_level
=
5157 &image
->planes
[0].surface
.u
.legacy
.level
[i
];
5158 unsigned dcc_fast_clear_size
=
5159 surf_level
->dcc_slice_fast_clear_size
* image
->info
.array_size
;
5161 if (!dcc_fast_clear_size
)
5164 size
= surf_level
->dcc_offset
+ dcc_fast_clear_size
;
5167 /* Initialize the mipmap levels without DCC. */
5168 if (size
!= image
->planes
[0].surface
.dcc_size
) {
5169 state
->flush_bits
|=
5170 radv_fill_buffer(cmd_buffer
, image
->bo
,
5171 image
->offset
+ image
->dcc_offset
+ size
,
5172 image
->planes
[0].surface
.dcc_size
- size
,
5177 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
5178 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5182 * Initialize DCC/FMASK/CMASK metadata for a color image.
5184 static void radv_init_color_image_metadata(struct radv_cmd_buffer
*cmd_buffer
,
5185 struct radv_image
*image
,
5186 VkImageLayout src_layout
,
5187 VkImageLayout dst_layout
,
5188 unsigned src_queue_mask
,
5189 unsigned dst_queue_mask
,
5190 const VkImageSubresourceRange
*range
)
5192 if (radv_image_has_cmask(image
)) {
5193 uint32_t value
= 0xffffffffu
; /* Fully expanded mode. */
5195 /* TODO: clarify this. */
5196 if (radv_image_has_fmask(image
)) {
5197 value
= 0xccccccccu
;
5200 radv_initialise_cmask(cmd_buffer
, image
, range
, value
);
5203 if (radv_image_has_fmask(image
)) {
5204 radv_initialize_fmask(cmd_buffer
, image
, range
);
5207 if (radv_dcc_enabled(image
, range
->baseMipLevel
)) {
5208 uint32_t value
= 0xffffffffu
; /* Fully expanded mode. */
5209 bool need_decompress_pass
= false;
5211 if (radv_layout_dcc_compressed(image
, dst_layout
,
5213 value
= 0x20202020u
;
5214 need_decompress_pass
= true;
5217 radv_initialize_dcc(cmd_buffer
, image
, range
, value
);
5219 radv_update_fce_metadata(cmd_buffer
, image
, range
,
5220 need_decompress_pass
);
5223 if (radv_image_has_cmask(image
) ||
5224 radv_dcc_enabled(image
, range
->baseMipLevel
)) {
5225 uint32_t color_values
[2] = {};
5226 radv_set_color_clear_metadata(cmd_buffer
, image
, range
,
5232 * Handle color image transitions for DCC/FMASK/CMASK.
5234 static void radv_handle_color_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
5235 struct radv_image
*image
,
5236 VkImageLayout src_layout
,
5237 VkImageLayout dst_layout
,
5238 unsigned src_queue_mask
,
5239 unsigned dst_queue_mask
,
5240 const VkImageSubresourceRange
*range
)
5242 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
5243 radv_init_color_image_metadata(cmd_buffer
, image
,
5244 src_layout
, dst_layout
,
5245 src_queue_mask
, dst_queue_mask
,
5250 if (radv_dcc_enabled(image
, range
->baseMipLevel
)) {
5251 if (src_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
5252 radv_initialize_dcc(cmd_buffer
, image
, range
, 0xffffffffu
);
5253 } else if (radv_layout_dcc_compressed(image
, src_layout
, src_queue_mask
) &&
5254 !radv_layout_dcc_compressed(image
, dst_layout
, dst_queue_mask
)) {
5255 radv_decompress_dcc(cmd_buffer
, image
, range
);
5256 } else if (radv_layout_can_fast_clear(image
, src_layout
, src_queue_mask
) &&
5257 !radv_layout_can_fast_clear(image
, dst_layout
, dst_queue_mask
)) {
5258 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
5260 } else if (radv_image_has_cmask(image
) || radv_image_has_fmask(image
)) {
5261 bool fce_eliminate
= false, fmask_expand
= false;
5263 if (radv_layout_can_fast_clear(image
, src_layout
, src_queue_mask
) &&
5264 !radv_layout_can_fast_clear(image
, dst_layout
, dst_queue_mask
)) {
5265 fce_eliminate
= true;
5268 if (radv_image_has_fmask(image
)) {
5269 if (src_layout
!= VK_IMAGE_LAYOUT_GENERAL
&&
5270 dst_layout
== VK_IMAGE_LAYOUT_GENERAL
) {
5271 /* A FMASK decompress is required before doing
5272 * a MSAA decompress using FMASK.
5274 fmask_expand
= true;
5278 if (fce_eliminate
|| fmask_expand
)
5279 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
5282 radv_expand_fmask_image_inplace(cmd_buffer
, image
, range
);
5286 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
5287 struct radv_image
*image
,
5288 VkImageLayout src_layout
,
5289 VkImageLayout dst_layout
,
5290 uint32_t src_family
,
5291 uint32_t dst_family
,
5292 const VkImageSubresourceRange
*range
,
5293 struct radv_sample_locations_state
*sample_locs
)
5295 if (image
->exclusive
&& src_family
!= dst_family
) {
5296 /* This is an acquire or a release operation and there will be
5297 * a corresponding release/acquire. Do the transition in the
5298 * most flexible queue. */
5300 assert(src_family
== cmd_buffer
->queue_family_index
||
5301 dst_family
== cmd_buffer
->queue_family_index
);
5303 if (src_family
== VK_QUEUE_FAMILY_EXTERNAL
||
5304 src_family
== VK_QUEUE_FAMILY_FOREIGN_EXT
)
5307 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_TRANSFER
)
5310 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
5311 (src_family
== RADV_QUEUE_GENERAL
||
5312 dst_family
== RADV_QUEUE_GENERAL
))
5316 if (src_layout
== dst_layout
)
5319 unsigned src_queue_mask
=
5320 radv_image_queue_family_mask(image
, src_family
,
5321 cmd_buffer
->queue_family_index
);
5322 unsigned dst_queue_mask
=
5323 radv_image_queue_family_mask(image
, dst_family
,
5324 cmd_buffer
->queue_family_index
);
5326 if (vk_format_is_depth(image
->vk_format
)) {
5327 radv_handle_depth_image_transition(cmd_buffer
, image
,
5328 src_layout
, dst_layout
,
5329 src_queue_mask
, dst_queue_mask
,
5330 range
, sample_locs
);
5332 radv_handle_color_image_transition(cmd_buffer
, image
,
5333 src_layout
, dst_layout
,
5334 src_queue_mask
, dst_queue_mask
,
5339 struct radv_barrier_info
{
5340 uint32_t eventCount
;
5341 const VkEvent
*pEvents
;
5342 VkPipelineStageFlags srcStageMask
;
5343 VkPipelineStageFlags dstStageMask
;
5347 radv_barrier(struct radv_cmd_buffer
*cmd_buffer
,
5348 uint32_t memoryBarrierCount
,
5349 const VkMemoryBarrier
*pMemoryBarriers
,
5350 uint32_t bufferMemoryBarrierCount
,
5351 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
5352 uint32_t imageMemoryBarrierCount
,
5353 const VkImageMemoryBarrier
*pImageMemoryBarriers
,
5354 const struct radv_barrier_info
*info
)
5356 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5357 enum radv_cmd_flush_bits src_flush_bits
= 0;
5358 enum radv_cmd_flush_bits dst_flush_bits
= 0;
5360 for (unsigned i
= 0; i
< info
->eventCount
; ++i
) {
5361 RADV_FROM_HANDLE(radv_event
, event
, info
->pEvents
[i
]);
5362 uint64_t va
= radv_buffer_get_va(event
->bo
);
5364 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, event
->bo
);
5366 ASSERTED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 7);
5368 radv_cp_wait_mem(cs
, WAIT_REG_MEM_EQUAL
, va
, 1, 0xffffffff);
5369 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
5372 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
5373 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pMemoryBarriers
[i
].srcAccessMask
,
5375 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pMemoryBarriers
[i
].dstAccessMask
,
5379 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
5380 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].srcAccessMask
,
5382 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].dstAccessMask
,
5386 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
5387 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
5389 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].srcAccessMask
,
5391 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].dstAccessMask
,
5395 /* The Vulkan spec 1.1.98 says:
5397 * "An execution dependency with only
5398 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
5399 * will only prevent that stage from executing in subsequently
5400 * submitted commands. As this stage does not perform any actual
5401 * execution, this is not observable - in effect, it does not delay
5402 * processing of subsequent commands. Similarly an execution dependency
5403 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
5404 * will effectively not wait for any prior commands to complete."
5406 if (info
->dstStageMask
!= VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
)
5407 radv_stage_flush(cmd_buffer
, info
->srcStageMask
);
5408 cmd_buffer
->state
.flush_bits
|= src_flush_bits
;
5410 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
5411 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
5413 const struct VkSampleLocationsInfoEXT
*sample_locs_info
=
5414 vk_find_struct_const(pImageMemoryBarriers
[i
].pNext
,
5415 SAMPLE_LOCATIONS_INFO_EXT
);
5416 struct radv_sample_locations_state sample_locations
= {};
5418 if (sample_locs_info
) {
5419 assert(image
->flags
& VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
);
5420 sample_locations
.per_pixel
= sample_locs_info
->sampleLocationsPerPixel
;
5421 sample_locations
.grid_size
= sample_locs_info
->sampleLocationGridSize
;
5422 sample_locations
.count
= sample_locs_info
->sampleLocationsCount
;
5423 typed_memcpy(&sample_locations
.locations
[0],
5424 sample_locs_info
->pSampleLocations
,
5425 sample_locs_info
->sampleLocationsCount
);
5428 radv_handle_image_transition(cmd_buffer
, image
,
5429 pImageMemoryBarriers
[i
].oldLayout
,
5430 pImageMemoryBarriers
[i
].newLayout
,
5431 pImageMemoryBarriers
[i
].srcQueueFamilyIndex
,
5432 pImageMemoryBarriers
[i
].dstQueueFamilyIndex
,
5433 &pImageMemoryBarriers
[i
].subresourceRange
,
5434 sample_locs_info
? &sample_locations
: NULL
);
5437 /* Make sure CP DMA is idle because the driver might have performed a
5438 * DMA operation for copying or filling buffers/images.
5440 if (info
->srcStageMask
& (VK_PIPELINE_STAGE_TRANSFER_BIT
|
5441 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
))
5442 si_cp_dma_wait_for_idle(cmd_buffer
);
5444 cmd_buffer
->state
.flush_bits
|= dst_flush_bits
;
5447 void radv_CmdPipelineBarrier(
5448 VkCommandBuffer commandBuffer
,
5449 VkPipelineStageFlags srcStageMask
,
5450 VkPipelineStageFlags destStageMask
,
5452 uint32_t memoryBarrierCount
,
5453 const VkMemoryBarrier
* pMemoryBarriers
,
5454 uint32_t bufferMemoryBarrierCount
,
5455 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
5456 uint32_t imageMemoryBarrierCount
,
5457 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
5459 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5460 struct radv_barrier_info info
;
5462 info
.eventCount
= 0;
5463 info
.pEvents
= NULL
;
5464 info
.srcStageMask
= srcStageMask
;
5465 info
.dstStageMask
= destStageMask
;
5467 radv_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
5468 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
5469 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
5473 static void write_event(struct radv_cmd_buffer
*cmd_buffer
,
5474 struct radv_event
*event
,
5475 VkPipelineStageFlags stageMask
,
5478 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5479 uint64_t va
= radv_buffer_get_va(event
->bo
);
5481 si_emit_cache_flush(cmd_buffer
);
5483 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, event
->bo
);
5485 ASSERTED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 21);
5487 /* Flags that only require a top-of-pipe event. */
5488 VkPipelineStageFlags top_of_pipe_flags
=
5489 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
;
5491 /* Flags that only require a post-index-fetch event. */
5492 VkPipelineStageFlags post_index_fetch_flags
=
5494 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
5495 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
;
5497 /* Make sure CP DMA is idle because the driver might have performed a
5498 * DMA operation for copying or filling buffers/images.
5500 if (stageMask
& (VK_PIPELINE_STAGE_TRANSFER_BIT
|
5501 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
))
5502 si_cp_dma_wait_for_idle(cmd_buffer
);
5504 /* TODO: Emit EOS events for syncing PS/CS stages. */
5506 if (!(stageMask
& ~top_of_pipe_flags
)) {
5507 /* Just need to sync the PFP engine. */
5508 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
5509 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
5510 S_370_WR_CONFIRM(1) |
5511 S_370_ENGINE_SEL(V_370_PFP
));
5512 radeon_emit(cs
, va
);
5513 radeon_emit(cs
, va
>> 32);
5514 radeon_emit(cs
, value
);
5515 } else if (!(stageMask
& ~post_index_fetch_flags
)) {
5516 /* Sync ME because PFP reads index and indirect buffers. */
5517 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
5518 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
5519 S_370_WR_CONFIRM(1) |
5520 S_370_ENGINE_SEL(V_370_ME
));
5521 radeon_emit(cs
, va
);
5522 radeon_emit(cs
, va
>> 32);
5523 radeon_emit(cs
, value
);
5525 /* Otherwise, sync all prior GPU work using an EOP event. */
5526 si_cs_emit_write_event_eop(cs
,
5527 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
5528 radv_cmd_buffer_uses_mec(cmd_buffer
),
5529 V_028A90_BOTTOM_OF_PIPE_TS
, 0,
5531 EOP_DATA_SEL_VALUE_32BIT
, va
, value
,
5532 cmd_buffer
->gfx9_eop_bug_va
);
5535 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
5538 void radv_CmdSetEvent(VkCommandBuffer commandBuffer
,
5540 VkPipelineStageFlags stageMask
)
5542 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5543 RADV_FROM_HANDLE(radv_event
, event
, _event
);
5545 write_event(cmd_buffer
, event
, stageMask
, 1);
5548 void radv_CmdResetEvent(VkCommandBuffer commandBuffer
,
5550 VkPipelineStageFlags stageMask
)
5552 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5553 RADV_FROM_HANDLE(radv_event
, event
, _event
);
5555 write_event(cmd_buffer
, event
, stageMask
, 0);
5558 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer
,
5559 uint32_t eventCount
,
5560 const VkEvent
* pEvents
,
5561 VkPipelineStageFlags srcStageMask
,
5562 VkPipelineStageFlags dstStageMask
,
5563 uint32_t memoryBarrierCount
,
5564 const VkMemoryBarrier
* pMemoryBarriers
,
5565 uint32_t bufferMemoryBarrierCount
,
5566 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
5567 uint32_t imageMemoryBarrierCount
,
5568 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
5570 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5571 struct radv_barrier_info info
;
5573 info
.eventCount
= eventCount
;
5574 info
.pEvents
= pEvents
;
5575 info
.srcStageMask
= 0;
5577 radv_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
5578 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
5579 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
5583 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer
,
5584 uint32_t deviceMask
)
5589 /* VK_EXT_conditional_rendering */
5590 void radv_CmdBeginConditionalRenderingEXT(
5591 VkCommandBuffer commandBuffer
,
5592 const VkConditionalRenderingBeginInfoEXT
* pConditionalRenderingBegin
)
5594 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5595 RADV_FROM_HANDLE(radv_buffer
, buffer
, pConditionalRenderingBegin
->buffer
);
5596 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5597 bool draw_visible
= true;
5598 uint64_t pred_value
= 0;
5599 uint64_t va
, new_va
;
5600 unsigned pred_offset
;
5602 va
= radv_buffer_get_va(buffer
->bo
) + pConditionalRenderingBegin
->offset
;
5604 /* By default, if the 32-bit value at offset in buffer memory is zero,
5605 * then the rendering commands are discarded, otherwise they are
5606 * executed as normal. If the inverted flag is set, all commands are
5607 * discarded if the value is non zero.
5609 if (pConditionalRenderingBegin
->flags
&
5610 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT
) {
5611 draw_visible
= false;
5614 si_emit_cache_flush(cmd_buffer
);
5616 /* From the Vulkan spec 1.1.107:
5618 * "If the 32-bit value at offset in buffer memory is zero, then the
5619 * rendering commands are discarded, otherwise they are executed as
5620 * normal. If the value of the predicate in buffer memory changes while
5621 * conditional rendering is active, the rendering commands may be
5622 * discarded in an implementation-dependent way. Some implementations
5623 * may latch the value of the predicate upon beginning conditional
5624 * rendering while others may read it before every rendering command."
5626 * But, the AMD hardware treats the predicate as a 64-bit value which
5627 * means we need a workaround in the driver. Luckily, it's not required
5628 * to support if the value changes when predication is active.
5630 * The workaround is as follows:
5631 * 1) allocate a 64-value in the upload BO and initialize it to 0
5632 * 2) copy the 32-bit predicate value to the upload BO
5633 * 3) use the new allocated VA address for predication
5635 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
5636 * in ME (+ sync PFP) instead of PFP.
5638 radv_cmd_buffer_upload_data(cmd_buffer
, 8, 16, &pred_value
, &pred_offset
);
5640 new_va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
) + pred_offset
;
5642 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
5643 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
5644 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM
) |
5645 COPY_DATA_WR_CONFIRM
);
5646 radeon_emit(cs
, va
);
5647 radeon_emit(cs
, va
>> 32);
5648 radeon_emit(cs
, new_va
);
5649 radeon_emit(cs
, new_va
>> 32);
5651 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
5654 /* Enable predication for this command buffer. */
5655 si_emit_set_predication_state(cmd_buffer
, draw_visible
, new_va
);
5656 cmd_buffer
->state
.predicating
= true;
5658 /* Store conditional rendering user info. */
5659 cmd_buffer
->state
.predication_type
= draw_visible
;
5660 cmd_buffer
->state
.predication_va
= new_va
;
5663 void radv_CmdEndConditionalRenderingEXT(
5664 VkCommandBuffer commandBuffer
)
5666 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5668 /* Disable predication for this command buffer. */
5669 si_emit_set_predication_state(cmd_buffer
, false, 0);
5670 cmd_buffer
->state
.predicating
= false;
5672 /* Reset conditional rendering user info. */
5673 cmd_buffer
->state
.predication_type
= -1;
5674 cmd_buffer
->state
.predication_va
= 0;
5677 /* VK_EXT_transform_feedback */
5678 void radv_CmdBindTransformFeedbackBuffersEXT(
5679 VkCommandBuffer commandBuffer
,
5680 uint32_t firstBinding
,
5681 uint32_t bindingCount
,
5682 const VkBuffer
* pBuffers
,
5683 const VkDeviceSize
* pOffsets
,
5684 const VkDeviceSize
* pSizes
)
5686 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5687 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
5688 uint8_t enabled_mask
= 0;
5690 assert(firstBinding
+ bindingCount
<= MAX_SO_BUFFERS
);
5691 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
5692 uint32_t idx
= firstBinding
+ i
;
5694 sb
[idx
].buffer
= radv_buffer_from_handle(pBuffers
[i
]);
5695 sb
[idx
].offset
= pOffsets
[i
];
5696 sb
[idx
].size
= pSizes
[i
];
5698 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
5699 sb
[idx
].buffer
->bo
);
5701 enabled_mask
|= 1 << idx
;
5704 cmd_buffer
->state
.streamout
.enabled_mask
|= enabled_mask
;
5706 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_STREAMOUT_BUFFER
;
5710 radv_emit_streamout_enable(struct radv_cmd_buffer
*cmd_buffer
)
5712 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
5713 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5715 radeon_set_context_reg_seq(cs
, R_028B94_VGT_STRMOUT_CONFIG
, 2);
5717 S_028B94_STREAMOUT_0_EN(so
->streamout_enabled
) |
5718 S_028B94_RAST_STREAM(0) |
5719 S_028B94_STREAMOUT_1_EN(so
->streamout_enabled
) |
5720 S_028B94_STREAMOUT_2_EN(so
->streamout_enabled
) |
5721 S_028B94_STREAMOUT_3_EN(so
->streamout_enabled
));
5722 radeon_emit(cs
, so
->hw_enabled_mask
&
5723 so
->enabled_stream_buffers_mask
);
5725 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
5729 radv_set_streamout_enable(struct radv_cmd_buffer
*cmd_buffer
, bool enable
)
5731 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
5732 bool old_streamout_enabled
= so
->streamout_enabled
;
5733 uint32_t old_hw_enabled_mask
= so
->hw_enabled_mask
;
5735 so
->streamout_enabled
= enable
;
5737 so
->hw_enabled_mask
= so
->enabled_mask
|
5738 (so
->enabled_mask
<< 4) |
5739 (so
->enabled_mask
<< 8) |
5740 (so
->enabled_mask
<< 12);
5742 if ((old_streamout_enabled
!= so
->streamout_enabled
) ||
5743 (old_hw_enabled_mask
!= so
->hw_enabled_mask
))
5744 radv_emit_streamout_enable(cmd_buffer
);
5747 static void radv_flush_vgt_streamout(struct radv_cmd_buffer
*cmd_buffer
)
5749 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5750 unsigned reg_strmout_cntl
;
5752 /* The register is at different places on different ASICs. */
5753 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
5754 reg_strmout_cntl
= R_0300FC_CP_STRMOUT_CNTL
;
5755 radeon_set_uconfig_reg(cs
, reg_strmout_cntl
, 0);
5757 reg_strmout_cntl
= R_0084FC_CP_STRMOUT_CNTL
;
5758 radeon_set_config_reg(cs
, reg_strmout_cntl
, 0);
5761 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
5762 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH
) | EVENT_INDEX(0));
5764 radeon_emit(cs
, PKT3(PKT3_WAIT_REG_MEM
, 5, 0));
5765 radeon_emit(cs
, WAIT_REG_MEM_EQUAL
); /* wait until the register is equal to the reference value */
5766 radeon_emit(cs
, reg_strmout_cntl
>> 2); /* register */
5768 radeon_emit(cs
, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
5769 radeon_emit(cs
, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
5770 radeon_emit(cs
, 4); /* poll interval */
5774 radv_emit_streamout_begin(struct radv_cmd_buffer
*cmd_buffer
,
5775 uint32_t firstCounterBuffer
,
5776 uint32_t counterBufferCount
,
5777 const VkBuffer
*pCounterBuffers
,
5778 const VkDeviceSize
*pCounterBufferOffsets
)
5781 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
5782 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
5783 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5786 radv_flush_vgt_streamout(cmd_buffer
);
5788 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
5789 for_each_bit(i
, so
->enabled_mask
) {
5790 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
5791 if (counter_buffer_idx
>= 0 && counter_buffer_idx
>= counterBufferCount
)
5792 counter_buffer_idx
= -1;
5794 /* AMD GCN binds streamout buffers as shader resources.
5795 * VGT only counts primitives and tells the shader through
5798 radeon_set_context_reg_seq(cs
, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0
+ 16*i
, 2);
5799 radeon_emit(cs
, sb
[i
].size
>> 2); /* BUFFER_SIZE (in DW) */
5800 radeon_emit(cs
, so
->stride_in_dw
[i
]); /* VTX_STRIDE (in DW) */
5802 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
5804 if (counter_buffer_idx
>= 0 && pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
]) {
5805 /* The array of counter buffers is optional. */
5806 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
5807 uint64_t va
= radv_buffer_get_va(buffer
->bo
);
5809 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
5812 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
5813 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
5814 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5815 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM
)); /* control */
5816 radeon_emit(cs
, 0); /* unused */
5817 radeon_emit(cs
, 0); /* unused */
5818 radeon_emit(cs
, va
); /* src address lo */
5819 radeon_emit(cs
, va
>> 32); /* src address hi */
5821 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, buffer
->bo
);
5823 /* Start from the beginning. */
5824 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
5825 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
5826 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5827 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET
)); /* control */
5828 radeon_emit(cs
, 0); /* unused */
5829 radeon_emit(cs
, 0); /* unused */
5830 radeon_emit(cs
, 0); /* unused */
5831 radeon_emit(cs
, 0); /* unused */
5835 radv_set_streamout_enable(cmd_buffer
, true);
5838 void radv_CmdBeginTransformFeedbackEXT(
5839 VkCommandBuffer commandBuffer
,
5840 uint32_t firstCounterBuffer
,
5841 uint32_t counterBufferCount
,
5842 const VkBuffer
* pCounterBuffers
,
5843 const VkDeviceSize
* pCounterBufferOffsets
)
5845 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5847 radv_emit_streamout_begin(cmd_buffer
,
5848 firstCounterBuffer
, counterBufferCount
,
5849 pCounterBuffers
, pCounterBufferOffsets
);
5853 radv_emit_streamout_end(struct radv_cmd_buffer
*cmd_buffer
,
5854 uint32_t firstCounterBuffer
,
5855 uint32_t counterBufferCount
,
5856 const VkBuffer
*pCounterBuffers
,
5857 const VkDeviceSize
*pCounterBufferOffsets
)
5859 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
5860 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5863 radv_flush_vgt_streamout(cmd_buffer
);
5865 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
5866 for_each_bit(i
, so
->enabled_mask
) {
5867 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
5868 if (counter_buffer_idx
>= 0 && counter_buffer_idx
>= counterBufferCount
)
5869 counter_buffer_idx
= -1;
5871 if (counter_buffer_idx
>= 0 && pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
]) {
5872 /* The array of counters buffer is optional. */
5873 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
5874 uint64_t va
= radv_buffer_get_va(buffer
->bo
);
5876 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
5878 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
5879 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
5880 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5881 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE
) |
5882 STRMOUT_STORE_BUFFER_FILLED_SIZE
); /* control */
5883 radeon_emit(cs
, va
); /* dst address lo */
5884 radeon_emit(cs
, va
>> 32); /* dst address hi */
5885 radeon_emit(cs
, 0); /* unused */
5886 radeon_emit(cs
, 0); /* unused */
5888 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, buffer
->bo
);
5891 /* Deactivate transform feedback by zeroing the buffer size.
5892 * The counters (primitives generated, primitives emitted) may
5893 * be enabled even if there is not buffer bound. This ensures
5894 * that the primitives-emitted query won't increment.
5896 radeon_set_context_reg(cs
, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0
+ 16*i
, 0);
5898 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
5901 radv_set_streamout_enable(cmd_buffer
, false);
5904 void radv_CmdEndTransformFeedbackEXT(
5905 VkCommandBuffer commandBuffer
,
5906 uint32_t firstCounterBuffer
,
5907 uint32_t counterBufferCount
,
5908 const VkBuffer
* pCounterBuffers
,
5909 const VkDeviceSize
* pCounterBufferOffsets
)
5911 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5913 radv_emit_streamout_end(cmd_buffer
,
5914 firstCounterBuffer
, counterBufferCount
,
5915 pCounterBuffers
, pCounterBufferOffsets
);
5918 void radv_CmdDrawIndirectByteCountEXT(
5919 VkCommandBuffer commandBuffer
,
5920 uint32_t instanceCount
,
5921 uint32_t firstInstance
,
5922 VkBuffer _counterBuffer
,
5923 VkDeviceSize counterBufferOffset
,
5924 uint32_t counterOffset
,
5925 uint32_t vertexStride
)
5927 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5928 RADV_FROM_HANDLE(radv_buffer
, counterBuffer
, _counterBuffer
);
5929 struct radv_draw_info info
= {};
5931 info
.instance_count
= instanceCount
;
5932 info
.first_instance
= firstInstance
;
5933 info
.strmout_buffer
= counterBuffer
;
5934 info
.strmout_buffer_offset
= counterBufferOffset
;
5935 info
.stride
= vertexStride
;
5937 radv_draw(cmd_buffer
, &info
);
5940 /* VK_AMD_buffer_marker */
5941 void radv_CmdWriteBufferMarkerAMD(
5942 VkCommandBuffer commandBuffer
,
5943 VkPipelineStageFlagBits pipelineStage
,
5945 VkDeviceSize dstOffset
,
5948 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5949 RADV_FROM_HANDLE(radv_buffer
, buffer
, dstBuffer
);
5950 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5951 uint64_t va
= radv_buffer_get_va(buffer
->bo
) + dstOffset
;
5953 si_emit_cache_flush(cmd_buffer
);
5955 if (!(pipelineStage
& ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
)) {
5956 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
5957 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_IMM
) |
5958 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM
) |
5959 COPY_DATA_WR_CONFIRM
);
5960 radeon_emit(cs
, marker
);
5962 radeon_emit(cs
, va
);
5963 radeon_emit(cs
, va
>> 32);
5965 si_cs_emit_write_event_eop(cs
,
5966 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
5967 radv_cmd_buffer_uses_mec(cmd_buffer
),
5968 V_028A90_BOTTOM_OF_PIPE_TS
, 0,
5970 EOP_DATA_SEL_VALUE_32BIT
,
5972 cmd_buffer
->gfx9_eop_bug_va
);