projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: disable FMASK compression when drawing with GENERAL layout
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 bool src_render_loop,
58 VkImageLayout dst_layout,
59 bool dst_render_loop,
60 uint32_t src_family,
61 uint32_t dst_family,
62 const VkImageSubresourceRange *range,
63 struct radv_sample_locations_state *sample_locs);
64
65 const struct radv_dynamic_state default_dynamic_state = {
66 .viewport = {
67 .count = 0,
68 },
69 .scissor = {
70 .count = 0,
71 },
72 .line_width = 1.0f,
73 .depth_bias = {
74 .bias = 0.0f,
75 .clamp = 0.0f,
76 .slope = 0.0f,
77 },
78 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
79 .depth_bounds = {
80 .min = 0.0f,
81 .max = 1.0f,
82 },
83 .stencil_compare_mask = {
84 .front = ~0u,
85 .back = ~0u,
86 },
87 .stencil_write_mask = {
88 .front = ~0u,
89 .back = ~0u,
90 },
91 .stencil_reference = {
92 .front = 0u,
93 .back = 0u,
94 },
95 .line_stipple = {
96 .factor = 0u,
97 .pattern = 0u,
98 },
99 };
100
101 static void
102 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
103 const struct radv_dynamic_state *src)
104 {
105 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
106 uint32_t copy_mask = src->mask;
107 uint32_t dest_mask = 0;
108
109 /* Make sure to copy the number of viewports/scissors because they can
110 * only be specified at pipeline creation time.
111 */
112 dest->viewport.count = src->viewport.count;
113 dest->scissor.count = src->scissor.count;
114 dest->discard_rectangle.count = src->discard_rectangle.count;
115 dest->sample_location.count = src->sample_location.count;
116
117 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
118 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
119 src->viewport.count * sizeof(VkViewport))) {
120 typed_memcpy(dest->viewport.viewports,
121 src->viewport.viewports,
122 src->viewport.count);
123 dest_mask |= RADV_DYNAMIC_VIEWPORT;
124 }
125 }
126
127 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
128 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
129 src->scissor.count * sizeof(VkRect2D))) {
130 typed_memcpy(dest->scissor.scissors,
131 src->scissor.scissors, src->scissor.count);
132 dest_mask |= RADV_DYNAMIC_SCISSOR;
133 }
134 }
135
136 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
137 if (dest->line_width != src->line_width) {
138 dest->line_width = src->line_width;
139 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
140 }
141 }
142
143 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
144 if (memcmp(&dest->depth_bias, &src->depth_bias,
145 sizeof(src->depth_bias))) {
146 dest->depth_bias = src->depth_bias;
147 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
148 }
149 }
150
151 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
152 if (memcmp(&dest->blend_constants, &src->blend_constants,
153 sizeof(src->blend_constants))) {
154 typed_memcpy(dest->blend_constants,
155 src->blend_constants, 4);
156 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
157 }
158 }
159
160 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
161 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
162 sizeof(src->depth_bounds))) {
163 dest->depth_bounds = src->depth_bounds;
164 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
165 }
166 }
167
168 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
169 if (memcmp(&dest->stencil_compare_mask,
170 &src->stencil_compare_mask,
171 sizeof(src->stencil_compare_mask))) {
172 dest->stencil_compare_mask = src->stencil_compare_mask;
173 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
174 }
175 }
176
177 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
178 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
179 sizeof(src->stencil_write_mask))) {
180 dest->stencil_write_mask = src->stencil_write_mask;
181 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
182 }
183 }
184
185 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
186 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
187 sizeof(src->stencil_reference))) {
188 dest->stencil_reference = src->stencil_reference;
189 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
190 }
191 }
192
193 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
194 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
195 src->discard_rectangle.count * sizeof(VkRect2D))) {
196 typed_memcpy(dest->discard_rectangle.rectangles,
197 src->discard_rectangle.rectangles,
198 src->discard_rectangle.count);
199 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
200 }
201 }
202
203 if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
204 if (dest->sample_location.per_pixel != src->sample_location.per_pixel ||
205 dest->sample_location.grid_size.width != src->sample_location.grid_size.width ||
206 dest->sample_location.grid_size.height != src->sample_location.grid_size.height ||
207 memcmp(&dest->sample_location.locations,
208 &src->sample_location.locations,
209 src->sample_location.count * sizeof(VkSampleLocationEXT))) {
210 dest->sample_location.per_pixel = src->sample_location.per_pixel;
211 dest->sample_location.grid_size = src->sample_location.grid_size;
212 typed_memcpy(dest->sample_location.locations,
213 src->sample_location.locations,
214 src->sample_location.count);
215 dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
216 }
217 }
218
219 if (copy_mask & RADV_DYNAMIC_LINE_STIPPLE) {
220 if (memcmp(&dest->line_stipple, &src->line_stipple,
221 sizeof(src->line_stipple))) {
222 dest->line_stipple = src->line_stipple;
223 dest_mask |= RADV_DYNAMIC_LINE_STIPPLE;
224 }
225 }
226
227 cmd_buffer->state.dirty |= dest_mask;
228 }
229
230 static void
231 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
232 struct radv_pipeline *pipeline)
233 {
234 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
235 struct radv_shader_info *info;
236
237 if (!pipeline->streamout_shader ||
238 cmd_buffer->device->physical_device->use_ngg_streamout)
239 return;
240
241 info = &pipeline->streamout_shader->info;
242 for (int i = 0; i < MAX_SO_BUFFERS; i++)
243 so->stride_in_dw[i] = info->so.strides[i];
244
245 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
246 }
247
248 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
249 {
250 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
251 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
252 }
253
254 enum ring_type radv_queue_family_to_ring(int f) {
255 switch (f) {
256 case RADV_QUEUE_GENERAL:
257 return RING_GFX;
258 case RADV_QUEUE_COMPUTE:
259 return RING_COMPUTE;
260 case RADV_QUEUE_TRANSFER:
261 return RING_DMA;
262 default:
263 unreachable("Unknown queue family");
264 }
265 }
266
267 static VkResult radv_create_cmd_buffer(
268 struct radv_device * device,
269 struct radv_cmd_pool * pool,
270 VkCommandBufferLevel level,
271 VkCommandBuffer* pCommandBuffer)
272 {
273 struct radv_cmd_buffer *cmd_buffer;
274 unsigned ring;
275 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
276 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
277 if (cmd_buffer == NULL)
278 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
279
280 vk_object_base_init(&device->vk, &cmd_buffer->base,
281 VK_OBJECT_TYPE_COMMAND_BUFFER);
282
283 cmd_buffer->device = device;
284 cmd_buffer->pool = pool;
285 cmd_buffer->level = level;
286
287 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
288 cmd_buffer->queue_family_index = pool->queue_family_index;
289
290 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
291
292 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
293 if (!cmd_buffer->cs) {
294 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
295 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
296 }
297
298 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
299
300 list_inithead(&cmd_buffer->upload.list);
301
302 return VK_SUCCESS;
303 }
304
305 static void
306 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
307 {
308 list_del(&cmd_buffer->pool_link);
309
310 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
311 &cmd_buffer->upload.list, list) {
312 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
313 list_del(&up->list);
314 free(up);
315 }
316
317 if (cmd_buffer->upload.upload_bo)
318 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
319 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
320
321 for (unsigned i = 0; i < MAX_BIND_POINTS; i++)
322 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
323
324 vk_object_base_finish(&cmd_buffer->base);
325
326 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
327 }
328
329 static VkResult
330 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
331 {
332 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
333
334 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
335 &cmd_buffer->upload.list, list) {
336 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
337 list_del(&up->list);
338 free(up);
339 }
340
341 cmd_buffer->push_constant_stages = 0;
342 cmd_buffer->scratch_size_per_wave_needed = 0;
343 cmd_buffer->scratch_waves_wanted = 0;
344 cmd_buffer->compute_scratch_size_per_wave_needed = 0;
345 cmd_buffer->compute_scratch_waves_wanted = 0;
346 cmd_buffer->esgs_ring_size_needed = 0;
347 cmd_buffer->gsvs_ring_size_needed = 0;
348 cmd_buffer->tess_rings_needed = false;
349 cmd_buffer->gds_needed = false;
350 cmd_buffer->gds_oa_needed = false;
351 cmd_buffer->sample_positions_needed = false;
352
353 if (cmd_buffer->upload.upload_bo)
354 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
355 cmd_buffer->upload.upload_bo);
356 cmd_buffer->upload.offset = 0;
357
358 cmd_buffer->record_result = VK_SUCCESS;
359
360 memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
361
362 for (unsigned i = 0; i < MAX_BIND_POINTS; i++) {
363 cmd_buffer->descriptors[i].dirty = 0;
364 cmd_buffer->descriptors[i].valid = 0;
365 cmd_buffer->descriptors[i].push_dirty = false;
366 }
367
368 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
369 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
370 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
371 unsigned fence_offset, eop_bug_offset;
372 void *fence_ptr;
373
374 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
375 &fence_ptr);
376
377 cmd_buffer->gfx9_fence_va =
378 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
379 cmd_buffer->gfx9_fence_va += fence_offset;
380
381 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
382 /* Allocate a buffer for the EOP bug on GFX9. */
383 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
384 &eop_bug_offset, &fence_ptr);
385 cmd_buffer->gfx9_eop_bug_va =
386 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
387 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
388 }
389 }
390
391 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
392
393 return cmd_buffer->record_result;
394 }
395
396 static bool
397 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
398 uint64_t min_needed)
399 {
400 uint64_t new_size;
401 struct radeon_winsys_bo *bo;
402 struct radv_cmd_buffer_upload *upload;
403 struct radv_device *device = cmd_buffer->device;
404
405 new_size = MAX2(min_needed, 16 * 1024);
406 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
407
408 bo = device->ws->buffer_create(device->ws,
409 new_size, 4096,
410 RADEON_DOMAIN_GTT,
411 RADEON_FLAG_CPU_ACCESS|
412 RADEON_FLAG_NO_INTERPROCESS_SHARING |
413 RADEON_FLAG_32BIT,
414 RADV_BO_PRIORITY_UPLOAD_BUFFER);
415
416 if (!bo) {
417 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
418 return false;
419 }
420
421 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
422 if (cmd_buffer->upload.upload_bo) {
423 upload = malloc(sizeof(*upload));
424
425 if (!upload) {
426 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
427 device->ws->buffer_destroy(bo);
428 return false;
429 }
430
431 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
432 list_add(&upload->list, &cmd_buffer->upload.list);
433 }
434
435 cmd_buffer->upload.upload_bo = bo;
436 cmd_buffer->upload.size = new_size;
437 cmd_buffer->upload.offset = 0;
438 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
439
440 if (!cmd_buffer->upload.map) {
441 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
442 return false;
443 }
444
445 return true;
446 }
447
448 bool
449 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
450 unsigned size,
451 unsigned alignment,
452 unsigned *out_offset,
453 void **ptr)
454 {
455 assert(util_is_power_of_two_nonzero(alignment));
456
457 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
458 if (offset + size > cmd_buffer->upload.size) {
459 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
460 return false;
461 offset = 0;
462 }
463
464 *out_offset = offset;
465 *ptr = cmd_buffer->upload.map + offset;
466
467 cmd_buffer->upload.offset = offset + size;
468 return true;
469 }
470
471 bool
472 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
473 unsigned size, unsigned alignment,
474 const void *data, unsigned *out_offset)
475 {
476 uint8_t *ptr;
477
478 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
479 out_offset, (void **)&ptr))
480 return false;
481
482 if (ptr)
483 memcpy(ptr, data, size);
484
485 return true;
486 }
487
488 static void
489 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
490 unsigned count, const uint32_t *data)
491 {
492 struct radeon_cmdbuf *cs = cmd_buffer->cs;
493
494 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
495
496 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
497 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
498 S_370_WR_CONFIRM(1) |
499 S_370_ENGINE_SEL(V_370_ME));
500 radeon_emit(cs, va);
501 radeon_emit(cs, va >> 32);
502 radeon_emit_array(cs, data, count);
503 }
504
505 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
506 {
507 struct radv_device *device = cmd_buffer->device;
508 struct radeon_cmdbuf *cs = cmd_buffer->cs;
509 uint64_t va;
510
511 va = radv_buffer_get_va(device->trace_bo);
512 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
513 va += 4;
514
515 ++cmd_buffer->state.trace_id;
516 radv_emit_write_data_packet(cmd_buffer, va, 1,
517 &cmd_buffer->state.trace_id);
518
519 radeon_check_space(cmd_buffer->device->ws, cs, 2);
520
521 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
522 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
523 }
524
525 static void
526 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
527 enum radv_cmd_flush_bits flags)
528 {
529 if (unlikely(cmd_buffer->device->thread_trace_bo)) {
530 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
531 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_THREAD_TRACE_MARKER) | EVENT_INDEX(0));
532 }
533
534 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
535 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
536 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
537
538 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
539
540 /* Force wait for graphics or compute engines to be idle. */
541 si_cs_emit_cache_flush(cmd_buffer->cs,
542 cmd_buffer->device->physical_device->rad_info.chip_class,
543 &cmd_buffer->gfx9_fence_idx,
544 cmd_buffer->gfx9_fence_va,
545 radv_cmd_buffer_uses_mec(cmd_buffer),
546 flags, cmd_buffer->gfx9_eop_bug_va);
547 }
548
549 if (unlikely(cmd_buffer->device->trace_bo))
550 radv_cmd_buffer_trace_emit(cmd_buffer);
551 }
552
553 static void
554 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
555 struct radv_pipeline *pipeline, enum ring_type ring)
556 {
557 struct radv_device *device = cmd_buffer->device;
558 uint32_t data[2];
559 uint64_t va;
560
561 va = radv_buffer_get_va(device->trace_bo);
562
563 switch (ring) {
564 case RING_GFX:
565 va += 8;
566 break;
567 case RING_COMPUTE:
568 va += 16;
569 break;
570 default:
571 assert(!"invalid ring type");
572 }
573
574 uint64_t pipeline_address = (uintptr_t)pipeline;
575 data[0] = pipeline_address;
576 data[1] = pipeline_address >> 32;
577
578 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
579 }
580
581 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
582 VkPipelineBindPoint bind_point,
583 struct radv_descriptor_set *set,
584 unsigned idx)
585 {
586 struct radv_descriptor_state *descriptors_state =
587 radv_get_descriptors_state(cmd_buffer, bind_point);
588
589 descriptors_state->sets[idx] = set;
590
591 descriptors_state->valid |= (1u << idx); /* active descriptors */
592 descriptors_state->dirty |= (1u << idx);
593 }
594
595 static void
596 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
597 VkPipelineBindPoint bind_point)
598 {
599 struct radv_descriptor_state *descriptors_state =
600 radv_get_descriptors_state(cmd_buffer, bind_point);
601 struct radv_device *device = cmd_buffer->device;
602 uint32_t data[MAX_SETS * 2] = {};
603 uint64_t va;
604 unsigned i;
605 va = radv_buffer_get_va(device->trace_bo) + 24;
606
607 for_each_bit(i, descriptors_state->valid) {
608 struct radv_descriptor_set *set = descriptors_state->sets[i];
609 data[i * 2] = (uint64_t)(uintptr_t)set;
610 data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
611 }
612
613 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
614 }
615
616 struct radv_userdata_info *
617 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
618 gl_shader_stage stage,
619 int idx)
620 {
621 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
622 return &shader->info.user_sgprs_locs.shader_data[idx];
623 }
624
625 static void
626 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
627 struct radv_pipeline *pipeline,
628 gl_shader_stage stage,
629 int idx, uint64_t va)
630 {
631 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
632 uint32_t base_reg = pipeline->user_data_0[stage];
633 if (loc->sgpr_idx == -1)
634 return;
635
636 assert(loc->num_sgprs == 1);
637
638 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
639 base_reg + loc->sgpr_idx * 4, va, false);
640 }
641
642 static void
643 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
644 struct radv_pipeline *pipeline,
645 struct radv_descriptor_state *descriptors_state,
646 gl_shader_stage stage)
647 {
648 struct radv_device *device = cmd_buffer->device;
649 struct radeon_cmdbuf *cs = cmd_buffer->cs;
650 uint32_t sh_base = pipeline->user_data_0[stage];
651 struct radv_userdata_locations *locs =
652 &pipeline->shaders[stage]->info.user_sgprs_locs;
653 unsigned mask = locs->descriptor_sets_enabled;
654
655 mask &= descriptors_state->dirty & descriptors_state->valid;
656
657 while (mask) {
658 int start, count;
659
660 u_bit_scan_consecutive_range(&mask, &start, &count);
661
662 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
663 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
664
665 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
666 for (int i = 0; i < count; i++) {
667 struct radv_descriptor_set *set =
668 descriptors_state->sets[start + i];
669
670 radv_emit_shader_pointer_body(device, cs, set->va, true);
671 }
672 }
673 }
674
675 /**
676 * Convert the user sample locations to hardware sample locations (the values
677 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
678 */
679 static void
680 radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
681 uint32_t x, uint32_t y, VkOffset2D *sample_locs)
682 {
683 uint32_t x_offset = x % state->grid_size.width;
684 uint32_t y_offset = y % state->grid_size.height;
685 uint32_t num_samples = (uint32_t)state->per_pixel;
686 VkSampleLocationEXT *user_locs;
687 uint32_t pixel_offset;
688
689 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
690
691 assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
692 user_locs = &state->locations[pixel_offset];
693
694 for (uint32_t i = 0; i < num_samples; i++) {
695 float shifted_pos_x = user_locs[i].x - 0.5;
696 float shifted_pos_y = user_locs[i].y - 0.5;
697
698 int32_t scaled_pos_x = floorf(shifted_pos_x * 16);
699 int32_t scaled_pos_y = floorf(shifted_pos_y * 16);
700
701 sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
702 sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
703 }
704 }
705
706 /**
707 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
708 * locations.
709 */
710 static void
711 radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
712 uint32_t *sample_locs_pixel)
713 {
714 for (uint32_t i = 0; i < num_samples; i++) {
715 uint32_t sample_reg_idx = i / 4;
716 uint32_t sample_loc_idx = i % 4;
717 int32_t pos_x = sample_locs[i].x;
718 int32_t pos_y = sample_locs[i].y;
719
720 uint32_t shift_x = 8 * sample_loc_idx;
721 uint32_t shift_y = shift_x + 4;
722
723 sample_locs_pixel[sample_reg_idx] |= (pos_x & 0xf) << shift_x;
724 sample_locs_pixel[sample_reg_idx] |= (pos_y & 0xf) << shift_y;
725 }
726 }
727
728 /**
729 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
730 * sample locations.
731 */
732 static uint64_t
733 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer,
734 VkOffset2D *sample_locs,
735 uint32_t num_samples)
736 {
737 uint32_t centroid_priorities[num_samples];
738 uint32_t sample_mask = num_samples - 1;
739 uint32_t distances[num_samples];
740 uint64_t centroid_priority = 0;
741
742 /* Compute the distances from center for each sample. */
743 for (int i = 0; i < num_samples; i++) {
744 distances[i] = (sample_locs[i].x * sample_locs[i].x) +
745 (sample_locs[i].y * sample_locs[i].y);
746 }
747
748 /* Compute the centroid priorities by looking at the distances array. */
749 for (int i = 0; i < num_samples; i++) {
750 uint32_t min_idx = 0;
751
752 for (int j = 1; j < num_samples; j++) {
753 if (distances[j] < distances[min_idx])
754 min_idx = j;
755 }
756
757 centroid_priorities[i] = min_idx;
758 distances[min_idx] = 0xffffffff;
759 }
760
761 /* Compute the final centroid priority. */
762 for (int i = 0; i < 8; i++) {
763 centroid_priority |=
764 centroid_priorities[i & sample_mask] << (i * 4);
765 }
766
767 return centroid_priority << 32 | centroid_priority;
768 }
769
770 /**
771 * Emit the sample locations that are specified with VK_EXT_sample_locations.
772 */
773 static void
774 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
775 {
776 struct radv_sample_locations_state *sample_location =
777 &cmd_buffer->state.dynamic.sample_location;
778 uint32_t num_samples = (uint32_t)sample_location->per_pixel;
779 struct radeon_cmdbuf *cs = cmd_buffer->cs;
780 uint32_t sample_locs_pixel[4][2] = {};
781 VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
782 uint32_t max_sample_dist = 0;
783 uint64_t centroid_priority;
784
785 if (!cmd_buffer->state.dynamic.sample_location.count)
786 return;
787
788 /* Convert the user sample locations to hardware sample locations. */
789 radv_convert_user_sample_locs(sample_location, 0, 0, sample_locs[0]);
790 radv_convert_user_sample_locs(sample_location, 1, 0, sample_locs[1]);
791 radv_convert_user_sample_locs(sample_location, 0, 1, sample_locs[2]);
792 radv_convert_user_sample_locs(sample_location, 1, 1, sample_locs[3]);
793
794 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
795 for (uint32_t i = 0; i < 4; i++) {
796 radv_compute_sample_locs_pixel(num_samples, sample_locs[i],
797 sample_locs_pixel[i]);
798 }
799
800 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
801 centroid_priority =
802 radv_compute_centroid_priority(cmd_buffer, sample_locs[0],
803 num_samples);
804
805 /* Compute the maximum sample distance from the specified locations. */
806 for (unsigned i = 0; i < 4; ++i) {
807 for (uint32_t j = 0; j < num_samples; j++) {
808 VkOffset2D offset = sample_locs[i][j];
809 max_sample_dist = MAX2(max_sample_dist,
810 MAX2(abs(offset.x), abs(offset.y)));
811 }
812 }
813
814 /* Emit the specified user sample locations. */
815 switch (num_samples) {
816 case 2:
817 case 4:
818 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
819 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
820 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
821 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
822 break;
823 case 8:
824 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
825 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
826 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
827 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
828 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs_pixel[0][1]);
829 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs_pixel[1][1]);
830 radeon_set_context_reg(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs_pixel[2][1]);
831 radeon_set_context_reg(cs, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs_pixel[3][1]);
832 break;
833 default:
834 unreachable("invalid number of samples");
835 }
836
837 /* Emit the maximum sample distance and the centroid priority. */
838 radeon_set_context_reg_rmw(cs, R_028BE0_PA_SC_AA_CONFIG,
839 S_028BE0_MAX_SAMPLE_DIST(max_sample_dist),
840 ~C_028BE0_MAX_SAMPLE_DIST);
841
842 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
843 radeon_emit(cs, centroid_priority);
844 radeon_emit(cs, centroid_priority >> 32);
845
846 /* GFX9: Flush DFSM when the AA mode changes. */
847 if (cmd_buffer->device->dfsm_allowed) {
848 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
849 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
850 }
851
852 cmd_buffer->state.context_roll_without_scissor_emitted = true;
853 }
854
855 static void
856 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
857 struct radv_pipeline *pipeline,
858 gl_shader_stage stage,
859 int idx, int count, uint32_t *values)
860 {
861 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
862 uint32_t base_reg = pipeline->user_data_0[stage];
863 if (loc->sgpr_idx == -1)
864 return;
865
866 assert(loc->num_sgprs == count);
867
868 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
869 radeon_emit_array(cmd_buffer->cs, values, count);
870 }
871
872 static void
873 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
874 struct radv_pipeline *pipeline)
875 {
876 int num_samples = pipeline->graphics.ms.num_samples;
877 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
878
879 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.needs_sample_positions)
880 cmd_buffer->sample_positions_needed = true;
881
882 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
883 return;
884
885 radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
886
887 cmd_buffer->state.context_roll_without_scissor_emitted = true;
888 }
889
890 static void
891 radv_update_binning_state(struct radv_cmd_buffer *cmd_buffer,
892 struct radv_pipeline *pipeline)
893 {
894 const struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
895
896
897 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
898 return;
899
900 if (old_pipeline &&
901 old_pipeline->graphics.binning.pa_sc_binner_cntl_0 == pipeline->graphics.binning.pa_sc_binner_cntl_0 &&
902 old_pipeline->graphics.binning.db_dfsm_control == pipeline->graphics.binning.db_dfsm_control)
903 return;
904
905 bool binning_flush = false;
906 if (cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA12 ||
907 cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA20 ||
908 cmd_buffer->device->physical_device->rad_info.family == CHIP_RAVEN2 ||
909 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
910 binning_flush = !old_pipeline ||
911 G_028C44_BINNING_MODE(old_pipeline->graphics.binning.pa_sc_binner_cntl_0) !=
912 G_028C44_BINNING_MODE(pipeline->graphics.binning.pa_sc_binner_cntl_0);
913 }
914
915 radeon_set_context_reg(cmd_buffer->cs, R_028C44_PA_SC_BINNER_CNTL_0,
916 pipeline->graphics.binning.pa_sc_binner_cntl_0 |
917 S_028C44_FLUSH_ON_BINNING_TRANSITION(!!binning_flush));
918
919 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
920 radeon_set_context_reg(cmd_buffer->cs, R_028038_DB_DFSM_CONTROL,
921 pipeline->graphics.binning.db_dfsm_control);
922 } else {
923 radeon_set_context_reg(cmd_buffer->cs, R_028060_DB_DFSM_CONTROL,
924 pipeline->graphics.binning.db_dfsm_control);
925 }
926
927 cmd_buffer->state.context_roll_without_scissor_emitted = true;
928 }
929
930
931 static void
932 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
933 struct radv_shader_variant *shader)
934 {
935 uint64_t va;
936
937 if (!shader)
938 return;
939
940 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
941
942 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
943 }
944
945 static void
946 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
947 struct radv_pipeline *pipeline,
948 bool vertex_stage_only)
949 {
950 struct radv_cmd_state *state = &cmd_buffer->state;
951 uint32_t mask = state->prefetch_L2_mask;
952
953 if (vertex_stage_only) {
954 /* Fast prefetch path for starting draws as soon as possible.
955 */
956 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
957 RADV_PREFETCH_VBO_DESCRIPTORS);
958 }
959
960 if (mask & RADV_PREFETCH_VS)
961 radv_emit_shader_prefetch(cmd_buffer,
962 pipeline->shaders[MESA_SHADER_VERTEX]);
963
964 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
965 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
966
967 if (mask & RADV_PREFETCH_TCS)
968 radv_emit_shader_prefetch(cmd_buffer,
969 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
970
971 if (mask & RADV_PREFETCH_TES)
972 radv_emit_shader_prefetch(cmd_buffer,
973 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
974
975 if (mask & RADV_PREFETCH_GS) {
976 radv_emit_shader_prefetch(cmd_buffer,
977 pipeline->shaders[MESA_SHADER_GEOMETRY]);
978 if (radv_pipeline_has_gs_copy_shader(pipeline))
979 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
980 }
981
982 if (mask & RADV_PREFETCH_PS)
983 radv_emit_shader_prefetch(cmd_buffer,
984 pipeline->shaders[MESA_SHADER_FRAGMENT]);
985
986 state->prefetch_L2_mask &= ~mask;
987 }
988
989 static void
990 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
991 {
992 if (!cmd_buffer->device->physical_device->rad_info.rbplus_allowed)
993 return;
994
995 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
996 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
997
998 unsigned sx_ps_downconvert = 0;
999 unsigned sx_blend_opt_epsilon = 0;
1000 unsigned sx_blend_opt_control = 0;
1001
1002 if (!cmd_buffer->state.attachments || !subpass)
1003 return;
1004
1005 for (unsigned i = 0; i < subpass->color_count; ++i) {
1006 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1007 /* We don't set the DISABLE bits, because the HW can't have holes,
1008 * so the SPI color format is set to 32-bit 1-component. */
1009 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1010 continue;
1011 }
1012
1013 int idx = subpass->color_attachments[i].attachment;
1014 struct radv_color_buffer_info *cb = &cmd_buffer->state.attachments[idx].cb;
1015
1016 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
1017 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
1018 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
1019 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
1020
1021 bool has_alpha, has_rgb;
1022
1023 /* Set if RGB and A are present. */
1024 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
1025
1026 if (format == V_028C70_COLOR_8 ||
1027 format == V_028C70_COLOR_16 ||
1028 format == V_028C70_COLOR_32)
1029 has_rgb = !has_alpha;
1030 else
1031 has_rgb = true;
1032
1033 /* Check the colormask and export format. */
1034 if (!(colormask & 0x7))
1035 has_rgb = false;
1036 if (!(colormask & 0x8))
1037 has_alpha = false;
1038
1039 if (spi_format == V_028714_SPI_SHADER_ZERO) {
1040 has_rgb = false;
1041 has_alpha = false;
1042 }
1043
1044 /* Disable value checking for disabled channels. */
1045 if (!has_rgb)
1046 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1047 if (!has_alpha)
1048 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1049
1050 /* Enable down-conversion for 32bpp and smaller formats. */
1051 switch (format) {
1052 case V_028C70_COLOR_8:
1053 case V_028C70_COLOR_8_8:
1054 case V_028C70_COLOR_8_8_8_8:
1055 /* For 1 and 2-channel formats, use the superset thereof. */
1056 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
1057 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1058 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1059 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
1060 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
1061 }
1062 break;
1063
1064 case V_028C70_COLOR_5_6_5:
1065 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1066 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
1067 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
1068 }
1069 break;
1070
1071 case V_028C70_COLOR_1_5_5_5:
1072 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1073 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
1074 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
1075 }
1076 break;
1077
1078 case V_028C70_COLOR_4_4_4_4:
1079 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1080 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
1081 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
1082 }
1083 break;
1084
1085 case V_028C70_COLOR_32:
1086 if (swap == V_028C70_SWAP_STD &&
1087 spi_format == V_028714_SPI_SHADER_32_R)
1088 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1089 else if (swap == V_028C70_SWAP_ALT_REV &&
1090 spi_format == V_028714_SPI_SHADER_32_AR)
1091 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
1092 break;
1093
1094 case V_028C70_COLOR_16:
1095 case V_028C70_COLOR_16_16:
1096 /* For 1-channel formats, use the superset thereof. */
1097 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
1098 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
1099 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1100 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1101 if (swap == V_028C70_SWAP_STD ||
1102 swap == V_028C70_SWAP_STD_REV)
1103 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
1104 else
1105 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
1106 }
1107 break;
1108
1109 case V_028C70_COLOR_10_11_11:
1110 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1111 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
1112 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
1113 }
1114 break;
1115
1116 case V_028C70_COLOR_2_10_10_10:
1117 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1118 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
1119 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
1120 }
1121 break;
1122 }
1123 }
1124
1125 /* Do not set the DISABLE bits for the unused attachments, as that
1126 * breaks dual source blending in SkQP and does not seem to improve
1127 * performance. */
1128
1129 if (sx_ps_downconvert == cmd_buffer->state.last_sx_ps_downconvert &&
1130 sx_blend_opt_epsilon == cmd_buffer->state.last_sx_blend_opt_epsilon &&
1131 sx_blend_opt_control == cmd_buffer->state.last_sx_blend_opt_control)
1132 return;
1133
1134 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
1135 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
1136 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
1137 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
1138
1139 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1140
1141 cmd_buffer->state.last_sx_ps_downconvert = sx_ps_downconvert;
1142 cmd_buffer->state.last_sx_blend_opt_epsilon = sx_blend_opt_epsilon;
1143 cmd_buffer->state.last_sx_blend_opt_control = sx_blend_opt_control;
1144 }
1145
1146 static void
1147 radv_emit_batch_break_on_new_ps(struct radv_cmd_buffer *cmd_buffer)
1148 {
1149 if (!cmd_buffer->device->pbb_allowed)
1150 return;
1151
1152 struct radv_binning_settings settings =
1153 radv_get_binning_settings(cmd_buffer->device->physical_device);
1154 bool break_for_new_ps =
1155 (!cmd_buffer->state.emitted_pipeline ||
1156 cmd_buffer->state.emitted_pipeline->shaders[MESA_SHADER_FRAGMENT] !=
1157 cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT]) &&
1158 (settings.context_states_per_bin > 1 ||
1159 settings.persistent_states_per_bin > 1);
1160 bool break_for_new_cb_target_mask =
1161 (!cmd_buffer->state.emitted_pipeline ||
1162 cmd_buffer->state.emitted_pipeline->graphics.cb_target_mask !=
1163 cmd_buffer->state.pipeline->graphics.cb_target_mask) &&
1164 settings.context_states_per_bin > 1;
1165
1166 if (!break_for_new_ps && !break_for_new_cb_target_mask)
1167 return;
1168
1169 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1170 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1171 }
1172
1173 static void
1174 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1175 {
1176 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1177
1178 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1179 return;
1180
1181 radv_update_multisample_state(cmd_buffer, pipeline);
1182 radv_update_binning_state(cmd_buffer, pipeline);
1183
1184 cmd_buffer->scratch_size_per_wave_needed = MAX2(cmd_buffer->scratch_size_per_wave_needed,
1185 pipeline->scratch_bytes_per_wave);
1186 cmd_buffer->scratch_waves_wanted = MAX2(cmd_buffer->scratch_waves_wanted,
1187 pipeline->max_waves);
1188
1189 if (!cmd_buffer->state.emitted_pipeline ||
1190 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1191 pipeline->graphics.can_use_guardband)
1192 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1193
1194 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
1195
1196 if (!cmd_buffer->state.emitted_pipeline ||
1197 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
1198 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
1199 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
1200 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
1201 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
1202 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1203 }
1204
1205 radv_emit_batch_break_on_new_ps(cmd_buffer);
1206
1207 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
1208 if (!pipeline->shaders[i])
1209 continue;
1210
1211 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1212 pipeline->shaders[i]->bo);
1213 }
1214
1215 if (radv_pipeline_has_gs_copy_shader(pipeline))
1216 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1217 pipeline->gs_copy_shader->bo);
1218
1219 if (unlikely(cmd_buffer->device->trace_bo))
1220 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1221
1222 cmd_buffer->state.emitted_pipeline = pipeline;
1223
1224 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1225 }
1226
1227 static void
1228 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1229 {
1230 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1231 cmd_buffer->state.dynamic.viewport.viewports);
1232 }
1233
1234 static void
1235 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1236 {
1237 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1238
1239 si_write_scissors(cmd_buffer->cs, 0, count,
1240 cmd_buffer->state.dynamic.scissor.scissors,
1241 cmd_buffer->state.dynamic.viewport.viewports,
1242 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1243
1244 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1245 }
1246
1247 static void
1248 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1249 {
1250 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1251 return;
1252
1253 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1254 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1255 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1256 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1257 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1258 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1259 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1260 }
1261 }
1262
1263 static void
1264 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1265 {
1266 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1267
1268 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1269 S_028A08_WIDTH(CLAMP(width, 0, 0xFFFF)));
1270 }
1271
1272 static void
1273 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1274 {
1275 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1276
1277 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1278 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1279 }
1280
1281 static void
1282 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1283 {
1284 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1285
1286 radeon_set_context_reg_seq(cmd_buffer->cs,
1287 R_028430_DB_STENCILREFMASK, 2);
1288 radeon_emit(cmd_buffer->cs,
1289 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1290 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1291 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1292 S_028430_STENCILOPVAL(1));
1293 radeon_emit(cmd_buffer->cs,
1294 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1295 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1296 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1297 S_028434_STENCILOPVAL_BF(1));
1298 }
1299
1300 static void
1301 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1302 {
1303 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1304
1305 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1306 fui(d->depth_bounds.min));
1307 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1308 fui(d->depth_bounds.max));
1309 }
1310
1311 static void
1312 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1313 {
1314 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1315 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1316 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1317
1318
1319 radeon_set_context_reg_seq(cmd_buffer->cs,
1320 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1321 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1322 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1323 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1324 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1325 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1326 }
1327
1328 static void
1329 radv_emit_line_stipple(struct radv_cmd_buffer *cmd_buffer)
1330 {
1331 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1332 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1333 uint32_t auto_reset_cntl = 1;
1334
1335 if (pipeline->graphics.topology == VK_PRIMITIVE_TOPOLOGY_LINE_STRIP)
1336 auto_reset_cntl = 2;
1337
1338 radeon_set_context_reg(cmd_buffer->cs, R_028A0C_PA_SC_LINE_STIPPLE,
1339 S_028A0C_LINE_PATTERN(d->line_stipple.pattern) |
1340 S_028A0C_REPEAT_COUNT(d->line_stipple.factor - 1) |
1341 S_028A0C_AUTO_RESET_CNTL(auto_reset_cntl));
1342 }
1343
1344 static void
1345 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1346 int index,
1347 struct radv_color_buffer_info *cb,
1348 struct radv_image_view *iview,
1349 VkImageLayout layout,
1350 bool in_render_loop)
1351 {
1352 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
1353 uint32_t cb_color_info = cb->cb_color_info;
1354 struct radv_image *image = iview->image;
1355
1356 if (!radv_layout_dcc_compressed(cmd_buffer->device, image, layout, in_render_loop,
1357 radv_image_queue_family_mask(image,
1358 cmd_buffer->queue_family_index,
1359 cmd_buffer->queue_family_index))) {
1360 cb_color_info &= C_028C70_DCC_ENABLE;
1361 }
1362
1363 if (!radv_layout_can_fast_clear(image, layout, in_render_loop,
1364 radv_image_queue_family_mask(image,
1365 cmd_buffer->queue_family_index,
1366 cmd_buffer->queue_family_index))) {
1367 cb_color_info &= C_028C70_COMPRESSION;
1368 }
1369
1370 if (radv_image_is_tc_compat_cmask(image) &&
1371 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1372 radv_is_dcc_decompress_pipeline(cmd_buffer))) {
1373 /* If this bit is set, the FMASK decompression operation
1374 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1375 */
1376 cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
1377 }
1378
1379 if (radv_image_has_fmask(image) &&
1380 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1381 radv_is_hw_resolve_pipeline(cmd_buffer))) {
1382 /* Make sure FMASK is enabled if it has been cleared because:
1383 *
1384 * 1) it's required for FMASK_DECOMPRESS operations to avoid
1385 * GPU hangs
1386 * 2) it's necessary for CB_RESOLVE which can read compressed
1387 * FMASK data anyways.
1388 */
1389 cb_color_info |= S_028C70_COMPRESSION(1);
1390 }
1391
1392 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1393 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1394 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1395 radeon_emit(cmd_buffer->cs, 0);
1396 radeon_emit(cmd_buffer->cs, 0);
1397 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1398 radeon_emit(cmd_buffer->cs, cb_color_info);
1399 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1400 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1401 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1402 radeon_emit(cmd_buffer->cs, 0);
1403 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1404 radeon_emit(cmd_buffer->cs, 0);
1405
1406 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 1);
1407 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1408
1409 radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4,
1410 cb->cb_color_base >> 32);
1411 radeon_set_context_reg(cmd_buffer->cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + index * 4,
1412 cb->cb_color_cmask >> 32);
1413 radeon_set_context_reg(cmd_buffer->cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + index * 4,
1414 cb->cb_color_fmask >> 32);
1415 radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4,
1416 cb->cb_dcc_base >> 32);
1417 radeon_set_context_reg(cmd_buffer->cs, R_028EC0_CB_COLOR0_ATTRIB2 + index * 4,
1418 cb->cb_color_attrib2);
1419 radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4,
1420 cb->cb_color_attrib3);
1421 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1422 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1423 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1424 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1425 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1426 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1427 radeon_emit(cmd_buffer->cs, cb_color_info);
1428 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1429 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1430 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1431 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1432 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1433 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1434
1435 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1436 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1437 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1438
1439 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1440 cb->cb_mrt_epitch);
1441 } else {
1442 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1443 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1444 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1445 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1446 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1447 radeon_emit(cmd_buffer->cs, cb_color_info);
1448 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1449 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1450 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1451 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1452 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1453 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1454
1455 if (is_vi) { /* DCC BASE */
1456 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1457 }
1458 }
1459
1460 if (radv_dcc_enabled(image, iview->base_mip)) {
1461 /* Drawing with DCC enabled also compresses colorbuffers. */
1462 VkImageSubresourceRange range = {
1463 .aspectMask = iview->aspect_mask,
1464 .baseMipLevel = iview->base_mip,
1465 .levelCount = iview->level_count,
1466 .baseArrayLayer = iview->base_layer,
1467 .layerCount = iview->layer_count,
1468 };
1469
1470 radv_update_dcc_metadata(cmd_buffer, image, &range, true);
1471 }
1472 }
1473
1474 static void
1475 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1476 struct radv_ds_buffer_info *ds,
1477 const struct radv_image_view *iview,
1478 VkImageLayout layout,
1479 bool in_render_loop, bool requires_cond_exec)
1480 {
1481 const struct radv_image *image = iview->image;
1482 uint32_t db_z_info = ds->db_z_info;
1483 uint32_t db_z_info_reg;
1484
1485 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug ||
1486 !radv_image_is_tc_compat_htile(image))
1487 return;
1488
1489 if (!radv_layout_is_htile_compressed(image, layout, in_render_loop,
1490 radv_image_queue_family_mask(image,
1491 cmd_buffer->queue_family_index,
1492 cmd_buffer->queue_family_index))) {
1493 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1494 }
1495
1496 db_z_info &= C_028040_ZRANGE_PRECISION;
1497
1498 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1499 db_z_info_reg = R_028038_DB_Z_INFO;
1500 } else {
1501 db_z_info_reg = R_028040_DB_Z_INFO;
1502 }
1503
1504 /* When we don't know the last fast clear value we need to emit a
1505 * conditional packet that will eventually skip the following
1506 * SET_CONTEXT_REG packet.
1507 */
1508 if (requires_cond_exec) {
1509 uint64_t va = radv_get_tc_compat_zrange_va(image, iview->base_mip);
1510
1511 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1512 radeon_emit(cmd_buffer->cs, va);
1513 radeon_emit(cmd_buffer->cs, va >> 32);
1514 radeon_emit(cmd_buffer->cs, 0);
1515 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1516 }
1517
1518 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1519 }
1520
1521 static void
1522 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1523 struct radv_ds_buffer_info *ds,
1524 struct radv_image_view *iview,
1525 VkImageLayout layout,
1526 bool in_render_loop)
1527 {
1528 const struct radv_image *image = iview->image;
1529 uint32_t db_z_info = ds->db_z_info;
1530 uint32_t db_stencil_info = ds->db_stencil_info;
1531
1532 if (!radv_layout_is_htile_compressed(image, layout, in_render_loop,
1533 radv_image_queue_family_mask(image,
1534 cmd_buffer->queue_family_index,
1535 cmd_buffer->queue_family_index))) {
1536 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1537 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1538 }
1539
1540 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1541 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1542
1543 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1544 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1545 radeon_set_context_reg(cmd_buffer->cs, R_02801C_DB_DEPTH_SIZE_XY, ds->db_depth_size);
1546
1547 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 7);
1548 radeon_emit(cmd_buffer->cs, S_02803C_RESOURCE_LEVEL(1));
1549 radeon_emit(cmd_buffer->cs, db_z_info);
1550 radeon_emit(cmd_buffer->cs, db_stencil_info);
1551 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1552 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1553 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1554 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1555
1556 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_READ_BASE_HI, 5);
1557 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1558 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1559 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1560 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1561 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1562 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1563 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1564 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1565 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1566 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1567
1568 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1569 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1570 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1571 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1572 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1573 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1574 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1575 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1576 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1577 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1578 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1579
1580 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1581 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1582 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1583 } else {
1584 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1585
1586 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1587 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1588 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1589 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1590 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1591 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1592 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1593 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1594 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1595 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1596
1597 }
1598
1599 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1600 radv_update_zrange_precision(cmd_buffer, ds, iview, layout,
1601 in_render_loop, true);
1602
1603 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1604 ds->pa_su_poly_offset_db_fmt_cntl);
1605 }
1606
1607 /**
1608 * Update the fast clear depth/stencil values if the image is bound as a
1609 * depth/stencil buffer.
1610 */
1611 static void
1612 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1613 const struct radv_image_view *iview,
1614 VkClearDepthStencilValue ds_clear_value,
1615 VkImageAspectFlags aspects)
1616 {
1617 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1618 const struct radv_image *image = iview->image;
1619 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1620 uint32_t att_idx;
1621
1622 if (!cmd_buffer->state.attachments || !subpass)
1623 return;
1624
1625 if (!subpass->depth_stencil_attachment)
1626 return;
1627
1628 att_idx = subpass->depth_stencil_attachment->attachment;
1629 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1630 return;
1631
1632 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1633 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1634 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1635 radeon_emit(cs, ds_clear_value.stencil);
1636 radeon_emit(cs, fui(ds_clear_value.depth));
1637 } else if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1638 radeon_set_context_reg_seq(cs, R_02802C_DB_DEPTH_CLEAR, 1);
1639 radeon_emit(cs, fui(ds_clear_value.depth));
1640 } else {
1641 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1642 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 1);
1643 radeon_emit(cs, ds_clear_value.stencil);
1644 }
1645
1646 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1647 * only needed when clearing Z to 0.0.
1648 */
1649 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1650 ds_clear_value.depth == 0.0) {
1651 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1652 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
1653
1654 radv_update_zrange_precision(cmd_buffer, &cmd_buffer->state.attachments[att_idx].ds,
1655 iview, layout, in_render_loop, false);
1656 }
1657
1658 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1659 }
1660
1661 /**
1662 * Set the clear depth/stencil values to the image's metadata.
1663 */
1664 static void
1665 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1666 struct radv_image *image,
1667 const VkImageSubresourceRange *range,
1668 VkClearDepthStencilValue ds_clear_value,
1669 VkImageAspectFlags aspects)
1670 {
1671 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1672 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel);
1673 uint32_t level_count = radv_get_levelCount(image, range);
1674
1675 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1676 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1677 /* Use the fastest way when both aspects are used. */
1678 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + 2 * level_count, cmd_buffer->state.predicating));
1679 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1680 S_370_WR_CONFIRM(1) |
1681 S_370_ENGINE_SEL(V_370_PFP));
1682 radeon_emit(cs, va);
1683 radeon_emit(cs, va >> 32);
1684
1685 for (uint32_t l = 0; l < level_count; l++) {
1686 radeon_emit(cs, ds_clear_value.stencil);
1687 radeon_emit(cs, fui(ds_clear_value.depth));
1688 }
1689 } else {
1690 /* Otherwise we need one WRITE_DATA packet per level. */
1691 for (uint32_t l = 0; l < level_count; l++) {
1692 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel + l);
1693 unsigned value;
1694
1695 if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1696 value = fui(ds_clear_value.depth);
1697 va += 4;
1698 } else {
1699 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1700 value = ds_clear_value.stencil;
1701 }
1702
1703 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1704 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1705 S_370_WR_CONFIRM(1) |
1706 S_370_ENGINE_SEL(V_370_PFP));
1707 radeon_emit(cs, va);
1708 radeon_emit(cs, va >> 32);
1709 radeon_emit(cs, value);
1710 }
1711 }
1712 }
1713
1714 /**
1715 * Update the TC-compat metadata value for this image.
1716 */
1717 static void
1718 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1719 struct radv_image *image,
1720 const VkImageSubresourceRange *range,
1721 uint32_t value)
1722 {
1723 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1724
1725 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug)
1726 return;
1727
1728 uint64_t va = radv_get_tc_compat_zrange_va(image, range->baseMipLevel);
1729 uint32_t level_count = radv_get_levelCount(image, range);
1730
1731 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + level_count, cmd_buffer->state.predicating));
1732 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1733 S_370_WR_CONFIRM(1) |
1734 S_370_ENGINE_SEL(V_370_PFP));
1735 radeon_emit(cs, va);
1736 radeon_emit(cs, va >> 32);
1737
1738 for (uint32_t l = 0; l < level_count; l++)
1739 radeon_emit(cs, value);
1740 }
1741
1742 static void
1743 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1744 const struct radv_image_view *iview,
1745 VkClearDepthStencilValue ds_clear_value)
1746 {
1747 VkImageSubresourceRange range = {
1748 .aspectMask = iview->aspect_mask,
1749 .baseMipLevel = iview->base_mip,
1750 .levelCount = iview->level_count,
1751 .baseArrayLayer = iview->base_layer,
1752 .layerCount = iview->layer_count,
1753 };
1754 uint32_t cond_val;
1755
1756 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1757 * depth clear value is 0.0f.
1758 */
1759 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1760
1761 radv_set_tc_compat_zrange_metadata(cmd_buffer, iview->image, &range,
1762 cond_val);
1763 }
1764
1765 /**
1766 * Update the clear depth/stencil values for this image.
1767 */
1768 void
1769 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1770 const struct radv_image_view *iview,
1771 VkClearDepthStencilValue ds_clear_value,
1772 VkImageAspectFlags aspects)
1773 {
1774 VkImageSubresourceRange range = {
1775 .aspectMask = iview->aspect_mask,
1776 .baseMipLevel = iview->base_mip,
1777 .levelCount = iview->level_count,
1778 .baseArrayLayer = iview->base_layer,
1779 .layerCount = iview->layer_count,
1780 };
1781 struct radv_image *image = iview->image;
1782
1783 assert(radv_image_has_htile(image));
1784
1785 radv_set_ds_clear_metadata(cmd_buffer, iview->image, &range,
1786 ds_clear_value, aspects);
1787
1788 if (radv_image_is_tc_compat_htile(image) &&
1789 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1790 radv_update_tc_compat_zrange_metadata(cmd_buffer, iview,
1791 ds_clear_value);
1792 }
1793
1794 radv_update_bound_fast_clear_ds(cmd_buffer, iview, ds_clear_value,
1795 aspects);
1796 }
1797
1798 /**
1799 * Load the clear depth/stencil values from the image's metadata.
1800 */
1801 static void
1802 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1803 const struct radv_image_view *iview)
1804 {
1805 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1806 const struct radv_image *image = iview->image;
1807 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1808 uint64_t va = radv_get_ds_clear_value_va(image, iview->base_mip);
1809 unsigned reg_offset = 0, reg_count = 0;
1810
1811 if (!radv_image_has_htile(image))
1812 return;
1813
1814 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1815 ++reg_count;
1816 } else {
1817 ++reg_offset;
1818 va += 4;
1819 }
1820 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1821 ++reg_count;
1822
1823 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1824
1825 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
1826 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG_INDEX, 3, 0));
1827 radeon_emit(cs, va);
1828 radeon_emit(cs, va >> 32);
1829 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1830 radeon_emit(cs, reg_count);
1831 } else {
1832 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1833 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1834 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1835 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1836 radeon_emit(cs, va);
1837 radeon_emit(cs, va >> 32);
1838 radeon_emit(cs, reg >> 2);
1839 radeon_emit(cs, 0);
1840
1841 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1842 radeon_emit(cs, 0);
1843 }
1844 }
1845
1846 /*
1847 * With DCC some colors don't require CMASK elimination before being
1848 * used as a texture. This sets a predicate value to determine if the
1849 * cmask eliminate is required.
1850 */
1851 void
1852 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1853 struct radv_image *image,
1854 const VkImageSubresourceRange *range, bool value)
1855 {
1856 uint64_t pred_val = value;
1857 uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
1858 uint32_t level_count = radv_get_levelCount(image, range);
1859 uint32_t count = 2 * level_count;
1860
1861 assert(radv_dcc_enabled(image, range->baseMipLevel));
1862
1863 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1864 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1865 S_370_WR_CONFIRM(1) |
1866 S_370_ENGINE_SEL(V_370_PFP));
1867 radeon_emit(cmd_buffer->cs, va);
1868 radeon_emit(cmd_buffer->cs, va >> 32);
1869
1870 for (uint32_t l = 0; l < level_count; l++) {
1871 radeon_emit(cmd_buffer->cs, pred_val);
1872 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1873 }
1874 }
1875
1876 /**
1877 * Update the DCC predicate to reflect the compression state.
1878 */
1879 void
1880 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1881 struct radv_image *image,
1882 const VkImageSubresourceRange *range, bool value)
1883 {
1884 uint64_t pred_val = value;
1885 uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
1886 uint32_t level_count = radv_get_levelCount(image, range);
1887 uint32_t count = 2 * level_count;
1888
1889 assert(radv_dcc_enabled(image, range->baseMipLevel));
1890
1891 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1892 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1893 S_370_WR_CONFIRM(1) |
1894 S_370_ENGINE_SEL(V_370_PFP));
1895 radeon_emit(cmd_buffer->cs, va);
1896 radeon_emit(cmd_buffer->cs, va >> 32);
1897
1898 for (uint32_t l = 0; l < level_count; l++) {
1899 radeon_emit(cmd_buffer->cs, pred_val);
1900 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1901 }
1902 }
1903
1904 /**
1905 * Update the fast clear color values if the image is bound as a color buffer.
1906 */
1907 static void
1908 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1909 struct radv_image *image,
1910 int cb_idx,
1911 uint32_t color_values[2])
1912 {
1913 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1914 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1915 uint32_t att_idx;
1916
1917 if (!cmd_buffer->state.attachments || !subpass)
1918 return;
1919
1920 att_idx = subpass->color_attachments[cb_idx].attachment;
1921 if (att_idx == VK_ATTACHMENT_UNUSED)
1922 return;
1923
1924 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1925 return;
1926
1927 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1928 radeon_emit(cs, color_values[0]);
1929 radeon_emit(cs, color_values[1]);
1930
1931 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1932 }
1933
1934 /**
1935 * Set the clear color values to the image's metadata.
1936 */
1937 static void
1938 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1939 struct radv_image *image,
1940 const VkImageSubresourceRange *range,
1941 uint32_t color_values[2])
1942 {
1943 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1944 uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
1945 uint32_t level_count = radv_get_levelCount(image, range);
1946 uint32_t count = 2 * level_count;
1947
1948 assert(radv_image_has_cmask(image) ||
1949 radv_dcc_enabled(image, range->baseMipLevel));
1950
1951 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
1952 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1953 S_370_WR_CONFIRM(1) |
1954 S_370_ENGINE_SEL(V_370_PFP));
1955 radeon_emit(cs, va);
1956 radeon_emit(cs, va >> 32);
1957
1958 for (uint32_t l = 0; l < level_count; l++) {
1959 radeon_emit(cs, color_values[0]);
1960 radeon_emit(cs, color_values[1]);
1961 }
1962 }
1963
1964 /**
1965 * Update the clear color values for this image.
1966 */
1967 void
1968 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1969 const struct radv_image_view *iview,
1970 int cb_idx,
1971 uint32_t color_values[2])
1972 {
1973 struct radv_image *image = iview->image;
1974 VkImageSubresourceRange range = {
1975 .aspectMask = iview->aspect_mask,
1976 .baseMipLevel = iview->base_mip,
1977 .levelCount = iview->level_count,
1978 .baseArrayLayer = iview->base_layer,
1979 .layerCount = iview->layer_count,
1980 };
1981
1982 assert(radv_image_has_cmask(image) ||
1983 radv_dcc_enabled(image, iview->base_mip));
1984
1985 radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
1986
1987 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1988 color_values);
1989 }
1990
1991 /**
1992 * Load the clear color values from the image's metadata.
1993 */
1994 static void
1995 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1996 struct radv_image_view *iview,
1997 int cb_idx)
1998 {
1999 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2000 struct radv_image *image = iview->image;
2001 uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
2002
2003 if (!radv_image_has_cmask(image) &&
2004 !radv_dcc_enabled(image, iview->base_mip))
2005 return;
2006
2007 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
2008
2009 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
2010 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG_INDEX, 3, cmd_buffer->state.predicating));
2011 radeon_emit(cs, va);
2012 radeon_emit(cs, va >> 32);
2013 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
2014 radeon_emit(cs, 2);
2015 } else {
2016 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
2017 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2018 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2019 COPY_DATA_COUNT_SEL);
2020 radeon_emit(cs, va);
2021 radeon_emit(cs, va >> 32);
2022 radeon_emit(cs, reg >> 2);
2023 radeon_emit(cs, 0);
2024
2025 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
2026 radeon_emit(cs, 0);
2027 }
2028 }
2029
2030 static void
2031 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
2032 {
2033 int i;
2034 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
2035 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2036
2037 /* this may happen for inherited secondary recording */
2038 if (!framebuffer)
2039 return;
2040
2041 for (i = 0; i < 8; ++i) {
2042 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
2043 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2044 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2045 continue;
2046 }
2047
2048 int idx = subpass->color_attachments[i].attachment;
2049 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
2050 VkImageLayout layout = subpass->color_attachments[i].layout;
2051 bool in_render_loop = subpass->color_attachments[i].in_render_loop;
2052
2053 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, iview->bo);
2054
2055 assert(iview->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
2056 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
2057 radv_emit_fb_color_state(cmd_buffer, i, &cmd_buffer->state.attachments[idx].cb, iview, layout, in_render_loop);
2058
2059 radv_load_color_clear_metadata(cmd_buffer, iview, i);
2060 }
2061
2062 if (subpass->depth_stencil_attachment) {
2063 int idx = subpass->depth_stencil_attachment->attachment;
2064 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
2065 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
2066 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
2067 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, cmd_buffer->state.attachments[idx].iview->bo);
2068
2069 radv_emit_fb_ds_state(cmd_buffer, &cmd_buffer->state.attachments[idx].ds, iview, layout, in_render_loop);
2070
2071 if (cmd_buffer->state.attachments[idx].ds.offset_scale != cmd_buffer->state.offset_scale) {
2072 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2073 cmd_buffer->state.offset_scale = cmd_buffer->state.attachments[idx].ds.offset_scale;
2074 }
2075 radv_load_ds_clear_metadata(cmd_buffer, iview);
2076 } else {
2077 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9)
2078 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
2079 else
2080 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
2081
2082 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
2083 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
2084 }
2085 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2086 S_028208_BR_X(framebuffer->width) |
2087 S_028208_BR_Y(framebuffer->height));
2088
2089 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
2090 bool disable_constant_encode =
2091 cmd_buffer->device->physical_device->rad_info.has_dcc_constant_encode;
2092 enum chip_class chip_class =
2093 cmd_buffer->device->physical_device->rad_info.chip_class;
2094 uint8_t watermark = chip_class >= GFX10 ? 6 : 4;
2095
2096 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
2097 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class <= GFX9) |
2098 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
2099 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
2100 }
2101
2102 if (cmd_buffer->device->dfsm_allowed) {
2103 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2104 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
2105 }
2106
2107 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
2108 }
2109
2110 static void
2111 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer, bool indirect)
2112 {
2113 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2114 struct radv_cmd_state *state = &cmd_buffer->state;
2115
2116 if (state->index_type != state->last_index_type) {
2117 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2118 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2119 cs, R_03090C_VGT_INDEX_TYPE,
2120 2, state->index_type);
2121 } else {
2122 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2123 radeon_emit(cs, state->index_type);
2124 }
2125
2126 state->last_index_type = state->index_type;
2127 }
2128
2129 /* For the direct indexed draws we use DRAW_INDEX_2, which includes
2130 * the index_va and max_index_count already. */
2131 if (!indirect)
2132 return;
2133
2134 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2135 radeon_emit(cs, state->index_va);
2136 radeon_emit(cs, state->index_va >> 32);
2137
2138 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2139 radeon_emit(cs, state->max_index_count);
2140
2141 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
2142 }
2143
2144 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
2145 {
2146 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
2147 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2148 uint32_t pa_sc_mode_cntl_1 =
2149 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
2150 uint32_t db_count_control;
2151
2152 if(!cmd_buffer->state.active_occlusion_queries) {
2153 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2154 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2155 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2156 has_perfect_queries) {
2157 /* Re-enable out-of-order rasterization if the
2158 * bound pipeline supports it and if it's has
2159 * been disabled before starting any perfect
2160 * occlusion queries.
2161 */
2162 radeon_set_context_reg(cmd_buffer->cs,
2163 R_028A4C_PA_SC_MODE_CNTL_1,
2164 pa_sc_mode_cntl_1);
2165 }
2166 }
2167 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
2168 } else {
2169 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2170 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
2171 bool gfx10_perfect = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10 && has_perfect_queries;
2172
2173 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2174 db_count_control =
2175 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
2176 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
2177 S_028004_SAMPLE_RATE(sample_rate) |
2178 S_028004_ZPASS_ENABLE(1) |
2179 S_028004_SLICE_EVEN_ENABLE(1) |
2180 S_028004_SLICE_ODD_ENABLE(1);
2181
2182 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2183 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2184 has_perfect_queries) {
2185 /* If the bound pipeline has enabled
2186 * out-of-order rasterization, we should
2187 * disable it before starting any perfect
2188 * occlusion queries.
2189 */
2190 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
2191
2192 radeon_set_context_reg(cmd_buffer->cs,
2193 R_028A4C_PA_SC_MODE_CNTL_1,
2194 pa_sc_mode_cntl_1);
2195 }
2196 } else {
2197 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
2198 S_028004_SAMPLE_RATE(sample_rate);
2199 }
2200 }
2201
2202 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
2203
2204 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2205 }
2206
2207 static void
2208 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
2209 {
2210 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
2211
2212 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
2213 radv_emit_viewport(cmd_buffer);
2214
2215 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
2216 !cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
2217 radv_emit_scissor(cmd_buffer);
2218
2219 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
2220 radv_emit_line_width(cmd_buffer);
2221
2222 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
2223 radv_emit_blend_constants(cmd_buffer);
2224
2225 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
2226 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
2227 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
2228 radv_emit_stencil(cmd_buffer);
2229
2230 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
2231 radv_emit_depth_bounds(cmd_buffer);
2232
2233 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
2234 radv_emit_depth_bias(cmd_buffer);
2235
2236 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
2237 radv_emit_discard_rectangle(cmd_buffer);
2238
2239 if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)
2240 radv_emit_sample_locations(cmd_buffer);
2241
2242 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE)
2243 radv_emit_line_stipple(cmd_buffer);
2244
2245 cmd_buffer->state.dirty &= ~states;
2246 }
2247
2248 static void
2249 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
2250 VkPipelineBindPoint bind_point)
2251 {
2252 struct radv_descriptor_state *descriptors_state =
2253 radv_get_descriptors_state(cmd_buffer, bind_point);
2254 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
2255 unsigned bo_offset;
2256
2257 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
2258 set->mapped_ptr,
2259 &bo_offset))
2260 return;
2261
2262 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2263 set->va += bo_offset;
2264 }
2265
2266 static void
2267 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
2268 VkPipelineBindPoint bind_point)
2269 {
2270 struct radv_descriptor_state *descriptors_state =
2271 radv_get_descriptors_state(cmd_buffer, bind_point);
2272 uint32_t size = MAX_SETS * 4;
2273 uint32_t offset;
2274 void *ptr;
2275
2276 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
2277 256, &offset, &ptr))
2278 return;
2279
2280 for (unsigned i = 0; i < MAX_SETS; i++) {
2281 uint32_t *uptr = ((uint32_t *)ptr) + i;
2282 uint64_t set_va = 0;
2283 struct radv_descriptor_set *set = descriptors_state->sets[i];
2284 if (descriptors_state->valid & (1u << i))
2285 set_va = set->va;
2286 uptr[0] = set_va & 0xffffffff;
2287 }
2288
2289 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2290 va += offset;
2291
2292 if (cmd_buffer->state.pipeline) {
2293 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
2294 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2295 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2296
2297 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
2298 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
2299 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2300
2301 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
2302 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2303 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2304
2305 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2306 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
2307 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2308
2309 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2310 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
2311 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2312 }
2313
2314 if (cmd_buffer->state.compute_pipeline)
2315 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
2316 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2317 }
2318
2319 static void
2320 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
2321 VkShaderStageFlags stages)
2322 {
2323 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2324 VK_PIPELINE_BIND_POINT_COMPUTE :
2325 VK_PIPELINE_BIND_POINT_GRAPHICS;
2326 struct radv_descriptor_state *descriptors_state =
2327 radv_get_descriptors_state(cmd_buffer, bind_point);
2328 struct radv_cmd_state *state = &cmd_buffer->state;
2329 bool flush_indirect_descriptors;
2330
2331 if (!descriptors_state->dirty)
2332 return;
2333
2334 if (descriptors_state->push_dirty)
2335 radv_flush_push_descriptors(cmd_buffer, bind_point);
2336
2337 flush_indirect_descriptors =
2338 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
2339 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
2340 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
2341 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
2342
2343 if (flush_indirect_descriptors)
2344 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
2345
2346 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2347 cmd_buffer->cs,
2348 MAX_SETS * MESA_SHADER_STAGES * 4);
2349
2350 if (cmd_buffer->state.pipeline) {
2351 radv_foreach_stage(stage, stages) {
2352 if (!cmd_buffer->state.pipeline->shaders[stage])
2353 continue;
2354
2355 radv_emit_descriptor_pointers(cmd_buffer,
2356 cmd_buffer->state.pipeline,
2357 descriptors_state, stage);
2358 }
2359 }
2360
2361 if (cmd_buffer->state.compute_pipeline &&
2362 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
2363 radv_emit_descriptor_pointers(cmd_buffer,
2364 cmd_buffer->state.compute_pipeline,
2365 descriptors_state,
2366 MESA_SHADER_COMPUTE);
2367 }
2368
2369 descriptors_state->dirty = 0;
2370 descriptors_state->push_dirty = false;
2371
2372 assert(cmd_buffer->cs->cdw <= cdw_max);
2373
2374 if (unlikely(cmd_buffer->device->trace_bo))
2375 radv_save_descriptors(cmd_buffer, bind_point);
2376 }
2377
2378 static void
2379 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
2380 VkShaderStageFlags stages)
2381 {
2382 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
2383 ? cmd_buffer->state.compute_pipeline
2384 : cmd_buffer->state.pipeline;
2385 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2386 VK_PIPELINE_BIND_POINT_COMPUTE :
2387 VK_PIPELINE_BIND_POINT_GRAPHICS;
2388 struct radv_descriptor_state *descriptors_state =
2389 radv_get_descriptors_state(cmd_buffer, bind_point);
2390 struct radv_pipeline_layout *layout = pipeline->layout;
2391 struct radv_shader_variant *shader, *prev_shader;
2392 bool need_push_constants = false;
2393 unsigned offset;
2394 void *ptr;
2395 uint64_t va;
2396
2397 stages &= cmd_buffer->push_constant_stages;
2398 if (!stages ||
2399 (!layout->push_constant_size && !layout->dynamic_offset_count))
2400 return;
2401
2402 radv_foreach_stage(stage, stages) {
2403 shader = radv_get_shader(pipeline, stage);
2404 if (!shader)
2405 continue;
2406
2407 need_push_constants |= shader->info.loads_push_constants;
2408 need_push_constants |= shader->info.loads_dynamic_offsets;
2409
2410 uint8_t base = shader->info.base_inline_push_consts;
2411 uint8_t count = shader->info.num_inline_push_consts;
2412
2413 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
2414 AC_UD_INLINE_PUSH_CONSTANTS,
2415 count,
2416 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
2417 }
2418
2419 if (need_push_constants) {
2420 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
2421 16 * layout->dynamic_offset_count,
2422 256, &offset, &ptr))
2423 return;
2424
2425 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
2426 memcpy((char*)ptr + layout->push_constant_size,
2427 descriptors_state->dynamic_buffers,
2428 16 * layout->dynamic_offset_count);
2429
2430 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2431 va += offset;
2432
2433 ASSERTED unsigned cdw_max =
2434 radeon_check_space(cmd_buffer->device->ws,
2435 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
2436
2437 prev_shader = NULL;
2438 radv_foreach_stage(stage, stages) {
2439 shader = radv_get_shader(pipeline, stage);
2440
2441 /* Avoid redundantly emitting the address for merged stages. */
2442 if (shader && shader != prev_shader) {
2443 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
2444 AC_UD_PUSH_CONSTANTS, va);
2445
2446 prev_shader = shader;
2447 }
2448 }
2449 assert(cmd_buffer->cs->cdw <= cdw_max);
2450 }
2451
2452 cmd_buffer->push_constant_stages &= ~stages;
2453 }
2454
2455 static void
2456 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
2457 bool pipeline_is_dirty)
2458 {
2459 if ((pipeline_is_dirty ||
2460 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
2461 cmd_buffer->state.pipeline->num_vertex_bindings &&
2462 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.has_vertex_buffers) {
2463 unsigned vb_offset;
2464 void *vb_ptr;
2465 uint32_t i = 0;
2466 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
2467 uint64_t va;
2468
2469 /* allocate some descriptor state for vertex buffers */
2470 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2471 &vb_offset, &vb_ptr))
2472 return;
2473
2474 for (i = 0; i < count; i++) {
2475 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2476 uint32_t offset;
2477 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2478 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[i];
2479 unsigned num_records;
2480
2481 if (!buffer)
2482 continue;
2483
2484 va = radv_buffer_get_va(buffer->bo);
2485
2486 offset = cmd_buffer->vertex_bindings[i].offset;
2487 va += offset + buffer->offset;
2488
2489 num_records = buffer->size - offset;
2490 if (cmd_buffer->device->physical_device->rad_info.chip_class != GFX8 && stride)
2491 num_records /= stride;
2492
2493 desc[0] = va;
2494 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2495 desc[2] = num_records;
2496 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2497 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2498 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2499 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2500
2501 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2502 /* OOB_SELECT chooses the out-of-bounds check:
2503 * - 1: index >= NUM_RECORDS (Structured)
2504 * - 3: offset >= NUM_RECORDS (Raw)
2505 */
2506 int oob_select = stride ? V_008F0C_OOB_SELECT_STRUCTURED : V_008F0C_OOB_SELECT_RAW;
2507
2508 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT) |
2509 S_008F0C_OOB_SELECT(oob_select) |
2510 S_008F0C_RESOURCE_LEVEL(1);
2511 } else {
2512 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2513 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2514 }
2515 }
2516
2517 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2518 va += vb_offset;
2519
2520 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2521 AC_UD_VS_VERTEX_BUFFERS, va);
2522
2523 cmd_buffer->state.vb_va = va;
2524 cmd_buffer->state.vb_size = count * 16;
2525 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2526 }
2527 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2528 }
2529
2530 static void
2531 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2532 {
2533 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2534 struct radv_userdata_info *loc;
2535 uint32_t base_reg;
2536
2537 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2538 if (!radv_get_shader(pipeline, stage))
2539 continue;
2540
2541 loc = radv_lookup_user_sgpr(pipeline, stage,
2542 AC_UD_STREAMOUT_BUFFERS);
2543 if (loc->sgpr_idx == -1)
2544 continue;
2545
2546 base_reg = pipeline->user_data_0[stage];
2547
2548 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2549 base_reg + loc->sgpr_idx * 4, va, false);
2550 }
2551
2552 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
2553 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2554 if (loc->sgpr_idx != -1) {
2555 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2556
2557 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2558 base_reg + loc->sgpr_idx * 4, va, false);
2559 }
2560 }
2561 }
2562
2563 static void
2564 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2565 {
2566 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2567 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2568 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2569 unsigned so_offset;
2570 void *so_ptr;
2571 uint64_t va;
2572
2573 /* Allocate some descriptor state for streamout buffers. */
2574 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2575 MAX_SO_BUFFERS * 16, 256,
2576 &so_offset, &so_ptr))
2577 return;
2578
2579 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2580 struct radv_buffer *buffer = sb[i].buffer;
2581 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2582
2583 if (!(so->enabled_mask & (1 << i)))
2584 continue;
2585
2586 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2587
2588 va += sb[i].offset;
2589
2590 /* Set the descriptor.
2591 *
2592 * On GFX8, the format must be non-INVALID, otherwise
2593 * the buffer will be considered not bound and store
2594 * instructions will be no-ops.
2595 */
2596 uint32_t size = 0xffffffff;
2597
2598 /* Compute the correct buffer size for NGG streamout
2599 * because it's used to determine the max emit per
2600 * buffer.
2601 */
2602 if (cmd_buffer->device->physical_device->use_ngg_streamout)
2603 size = buffer->size - sb[i].offset;
2604
2605 desc[0] = va;
2606 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2607 desc[2] = size;
2608 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2609 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2610 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2611 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2612
2613 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2614 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2615 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
2616 S_008F0C_RESOURCE_LEVEL(1);
2617 } else {
2618 desc[3] |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2619 }
2620 }
2621
2622 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2623 va += so_offset;
2624
2625 radv_emit_streamout_buffers(cmd_buffer, va);
2626 }
2627
2628 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2629 }
2630
2631 static void
2632 radv_flush_ngg_gs_state(struct radv_cmd_buffer *cmd_buffer)
2633 {
2634 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2635 struct radv_userdata_info *loc;
2636 uint32_t ngg_gs_state = 0;
2637 uint32_t base_reg;
2638
2639 if (!radv_pipeline_has_gs(pipeline) ||
2640 !radv_pipeline_has_ngg(pipeline))
2641 return;
2642
2643 /* By default NGG GS queries are disabled but they are enabled if the
2644 * command buffer has active GDS queries or if it's a secondary command
2645 * buffer that inherits the number of generated primitives.
2646 */
2647 if (cmd_buffer->state.active_pipeline_gds_queries ||
2648 (cmd_buffer->state.inherited_pipeline_statistics & VK_QUERY_PIPELINE_STATISTIC_GEOMETRY_SHADER_PRIMITIVES_BIT))
2649 ngg_gs_state = 1;
2650
2651 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_GEOMETRY,
2652 AC_UD_NGG_GS_STATE);
2653 base_reg = pipeline->user_data_0[MESA_SHADER_GEOMETRY];
2654 assert(loc->sgpr_idx != -1);
2655
2656 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
2657 ngg_gs_state);
2658 }
2659
2660 static void
2661 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2662 {
2663 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2664 radv_flush_streamout_descriptors(cmd_buffer);
2665 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2666 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2667 radv_flush_ngg_gs_state(cmd_buffer);
2668 }
2669
2670 struct radv_draw_info {
2671 /**
2672 * Number of vertices.
2673 */
2674 uint32_t count;
2675
2676 /**
2677 * Index of the first vertex.
2678 */
2679 int32_t vertex_offset;
2680
2681 /**
2682 * First instance id.
2683 */
2684 uint32_t first_instance;
2685
2686 /**
2687 * Number of instances.
2688 */
2689 uint32_t instance_count;
2690
2691 /**
2692 * First index (indexed draws only).
2693 */
2694 uint32_t first_index;
2695
2696 /**
2697 * Whether it's an indexed draw.
2698 */
2699 bool indexed;
2700
2701 /**
2702 * Indirect draw parameters resource.
2703 */
2704 struct radv_buffer *indirect;
2705 uint64_t indirect_offset;
2706 uint32_t stride;
2707
2708 /**
2709 * Draw count parameters resource.
2710 */
2711 struct radv_buffer *count_buffer;
2712 uint64_t count_buffer_offset;
2713
2714 /**
2715 * Stream output parameters resource.
2716 */
2717 struct radv_buffer *strmout_buffer;
2718 uint64_t strmout_buffer_offset;
2719 };
2720
2721 static uint32_t
2722 radv_get_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
2723 {
2724 switch (cmd_buffer->state.index_type) {
2725 case V_028A7C_VGT_INDEX_8:
2726 return 0xffu;
2727 case V_028A7C_VGT_INDEX_16:
2728 return 0xffffu;
2729 case V_028A7C_VGT_INDEX_32:
2730 return 0xffffffffu;
2731 default:
2732 unreachable("invalid index type");
2733 }
2734 }
2735
2736 static void
2737 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
2738 bool instanced_draw, bool indirect_draw,
2739 bool count_from_stream_output,
2740 uint32_t draw_vertex_count)
2741 {
2742 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2743 struct radv_cmd_state *state = &cmd_buffer->state;
2744 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2745 unsigned ia_multi_vgt_param;
2746
2747 ia_multi_vgt_param =
2748 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
2749 indirect_draw,
2750 count_from_stream_output,
2751 draw_vertex_count);
2752
2753 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2754 if (info->chip_class == GFX9) {
2755 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2756 cs,
2757 R_030960_IA_MULTI_VGT_PARAM,
2758 4, ia_multi_vgt_param);
2759 } else if (info->chip_class >= GFX7) {
2760 radeon_set_context_reg_idx(cs,
2761 R_028AA8_IA_MULTI_VGT_PARAM,
2762 1, ia_multi_vgt_param);
2763 } else {
2764 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2765 ia_multi_vgt_param);
2766 }
2767 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2768 }
2769 }
2770
2771 static void
2772 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2773 const struct radv_draw_info *draw_info)
2774 {
2775 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2776 struct radv_cmd_state *state = &cmd_buffer->state;
2777 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2778 int32_t primitive_reset_en;
2779
2780 /* Draw state. */
2781 if (info->chip_class < GFX10) {
2782 si_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2783 draw_info->indirect,
2784 !!draw_info->strmout_buffer,
2785 draw_info->indirect ? 0 : draw_info->count);
2786 }
2787
2788 /* Primitive restart. */
2789 primitive_reset_en =
2790 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2791
2792 if (primitive_reset_en != state->last_primitive_reset_en) {
2793 state->last_primitive_reset_en = primitive_reset_en;
2794 if (info->chip_class >= GFX9) {
2795 radeon_set_uconfig_reg(cs,
2796 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2797 primitive_reset_en);
2798 } else {
2799 radeon_set_context_reg(cs,
2800 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2801 primitive_reset_en);
2802 }
2803 }
2804
2805 if (primitive_reset_en) {
2806 uint32_t primitive_reset_index =
2807 radv_get_primitive_reset_index(cmd_buffer);
2808
2809 if (primitive_reset_index != state->last_primitive_reset_index) {
2810 radeon_set_context_reg(cs,
2811 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2812 primitive_reset_index);
2813 state->last_primitive_reset_index = primitive_reset_index;
2814 }
2815 }
2816
2817 if (draw_info->strmout_buffer) {
2818 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2819
2820 va += draw_info->strmout_buffer->offset +
2821 draw_info->strmout_buffer_offset;
2822
2823 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2824 draw_info->stride);
2825
2826 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2827 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2828 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2829 COPY_DATA_WR_CONFIRM);
2830 radeon_emit(cs, va);
2831 radeon_emit(cs, va >> 32);
2832 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2833 radeon_emit(cs, 0); /* unused */
2834
2835 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2836 }
2837 }
2838
2839 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2840 VkPipelineStageFlags src_stage_mask)
2841 {
2842 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2843 VK_PIPELINE_STAGE_TRANSFER_BIT |
2844 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2845 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2846 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2847 }
2848
2849 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2850 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2851 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2852 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2853 VK_PIPELINE_STAGE_TRANSFER_BIT |
2854 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2855 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2856 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2857 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2858 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2859 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2860 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2861 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2862 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2863 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2864 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2865 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2866 }
2867 }
2868
2869 static enum radv_cmd_flush_bits
2870 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2871 VkAccessFlags src_flags,
2872 struct radv_image *image)
2873 {
2874 bool flush_CB_meta = true, flush_DB_meta = true;
2875 enum radv_cmd_flush_bits flush_bits = 0;
2876 uint32_t b;
2877
2878 if (image) {
2879 if (!radv_image_has_CB_metadata(image))
2880 flush_CB_meta = false;
2881 if (!radv_image_has_htile(image))
2882 flush_DB_meta = false;
2883 }
2884
2885 for_each_bit(b, src_flags) {
2886 switch ((VkAccessFlagBits)(1 << b)) {
2887 case VK_ACCESS_SHADER_WRITE_BIT:
2888 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2889 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2890 flush_bits |= RADV_CMD_FLAG_WB_L2;
2891 break;
2892 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2893 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2894 if (flush_CB_meta)
2895 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2896 break;
2897 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2898 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2899 if (flush_DB_meta)
2900 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2901 break;
2902 case VK_ACCESS_TRANSFER_WRITE_BIT:
2903 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2904 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2905 RADV_CMD_FLAG_INV_L2;
2906
2907 if (flush_CB_meta)
2908 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2909 if (flush_DB_meta)
2910 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2911 break;
2912 default:
2913 break;
2914 }
2915 }
2916 return flush_bits;
2917 }
2918
2919 static enum radv_cmd_flush_bits
2920 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2921 VkAccessFlags dst_flags,
2922 struct radv_image *image)
2923 {
2924 bool flush_CB_meta = true, flush_DB_meta = true;
2925 enum radv_cmd_flush_bits flush_bits = 0;
2926 bool flush_CB = true, flush_DB = true;
2927 bool image_is_coherent = false;
2928 uint32_t b;
2929
2930 if (image) {
2931 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2932 flush_CB = false;
2933 flush_DB = false;
2934 }
2935
2936 if (!radv_image_has_CB_metadata(image))
2937 flush_CB_meta = false;
2938 if (!radv_image_has_htile(image))
2939 flush_DB_meta = false;
2940
2941 /* TODO: implement shader coherent for GFX10 */
2942
2943 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
2944 if (image->info.samples == 1 &&
2945 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2946 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2947 !vk_format_is_stencil(image->vk_format)) {
2948 /* Single-sample color and single-sample depth
2949 * (not stencil) are coherent with shaders on
2950 * GFX9.
2951 */
2952 image_is_coherent = true;
2953 }
2954 }
2955 }
2956
2957 for_each_bit(b, dst_flags) {
2958 switch ((VkAccessFlagBits)(1 << b)) {
2959 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2960 case VK_ACCESS_INDEX_READ_BIT:
2961 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2962 break;
2963 case VK_ACCESS_UNIFORM_READ_BIT:
2964 flush_bits |= RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_SCACHE;
2965 break;
2966 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2967 case VK_ACCESS_TRANSFER_READ_BIT:
2968 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2969 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
2970 RADV_CMD_FLAG_INV_L2;
2971 break;
2972 case VK_ACCESS_SHADER_READ_BIT:
2973 flush_bits |= RADV_CMD_FLAG_INV_VCACHE;
2974 /* Unlike LLVM, ACO uses SMEM for SSBOs and we have to
2975 * invalidate the scalar cache. */
2976 if (!cmd_buffer->device->physical_device->use_llvm)
2977 flush_bits |= RADV_CMD_FLAG_INV_SCACHE;
2978
2979 if (!image_is_coherent)
2980 flush_bits |= RADV_CMD_FLAG_INV_L2;
2981 break;
2982 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2983 if (flush_CB)
2984 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2985 if (flush_CB_meta)
2986 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2987 break;
2988 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2989 if (flush_DB)
2990 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2991 if (flush_DB_meta)
2992 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2993 break;
2994 default:
2995 break;
2996 }
2997 }
2998 return flush_bits;
2999 }
3000
3001 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
3002 const struct radv_subpass_barrier *barrier)
3003 {
3004 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
3005 NULL);
3006 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
3007 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
3008 NULL);
3009 }
3010
3011 uint32_t
3012 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
3013 {
3014 struct radv_cmd_state *state = &cmd_buffer->state;
3015 uint32_t subpass_id = state->subpass - state->pass->subpasses;
3016
3017 /* The id of this subpass shouldn't exceed the number of subpasses in
3018 * this render pass minus 1.
3019 */
3020 assert(subpass_id < state->pass->subpass_count);
3021 return subpass_id;
3022 }
3023
3024 static struct radv_sample_locations_state *
3025 radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer,
3026 uint32_t att_idx,
3027 bool begin_subpass)
3028 {
3029 struct radv_cmd_state *state = &cmd_buffer->state;
3030 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
3031 struct radv_image_view *view = state->attachments[att_idx].iview;
3032
3033 if (view->image->info.samples == 1)
3034 return NULL;
3035
3036 if (state->pass->attachments[att_idx].first_subpass_idx == subpass_id) {
3037 /* Return the initial sample locations if this is the initial
3038 * layout transition of the given subpass attachemnt.
3039 */
3040 if (state->attachments[att_idx].sample_location.count > 0)
3041 return &state->attachments[att_idx].sample_location;
3042 } else {
3043 /* Otherwise return the subpass sample locations if defined. */
3044 if (state->subpass_sample_locs) {
3045 /* Because the driver sets the current subpass before
3046 * initial layout transitions, we should use the sample
3047 * locations from the previous subpass to avoid an
3048 * off-by-one problem. Otherwise, use the sample
3049 * locations for the current subpass for final layout
3050 * transitions.
3051 */
3052 if (begin_subpass)
3053 subpass_id--;
3054
3055 for (uint32_t i = 0; i < state->num_subpass_sample_locs; i++) {
3056 if (state->subpass_sample_locs[i].subpass_idx == subpass_id)
3057 return &state->subpass_sample_locs[i].sample_location;
3058 }
3059 }
3060 }
3061
3062 return NULL;
3063 }
3064
3065 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
3066 struct radv_subpass_attachment att,
3067 bool begin_subpass)
3068 {
3069 unsigned idx = att.attachment;
3070 struct radv_image_view *view = cmd_buffer->state.attachments[idx].iview;
3071 struct radv_sample_locations_state *sample_locs;
3072 VkImageSubresourceRange range;
3073 range.aspectMask = view->aspect_mask;
3074 range.baseMipLevel = view->base_mip;
3075 range.levelCount = 1;
3076 range.baseArrayLayer = view->base_layer;
3077 range.layerCount = cmd_buffer->state.framebuffer->layers;
3078
3079 if (cmd_buffer->state.subpass->view_mask) {
3080 /* If the current subpass uses multiview, the driver might have
3081 * performed a fast color/depth clear to the whole image
3082 * (including all layers). To make sure the driver will
3083 * decompress the image correctly (if needed), we have to
3084 * account for the "real" number of layers. If the view mask is
3085 * sparse, this will decompress more layers than needed.
3086 */
3087 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
3088 }
3089
3090 /* Get the subpass sample locations for the given attachment, if NULL
3091 * is returned the driver will use the default HW locations.
3092 */
3093 sample_locs = radv_get_attachment_sample_locations(cmd_buffer, idx,
3094 begin_subpass);
3095
3096 /* Determine if the subpass uses separate depth/stencil layouts. */
3097 bool uses_separate_depth_stencil_layouts = false;
3098 if ((cmd_buffer->state.attachments[idx].current_layout !=
3099 cmd_buffer->state.attachments[idx].current_stencil_layout) ||
3100 (att.layout != att.stencil_layout)) {
3101 uses_separate_depth_stencil_layouts = true;
3102 }
3103
3104 /* For separate layouts, perform depth and stencil transitions
3105 * separately.
3106 */
3107 if (uses_separate_depth_stencil_layouts &&
3108 (range.aspectMask == (VK_IMAGE_ASPECT_DEPTH_BIT |
3109 VK_IMAGE_ASPECT_STENCIL_BIT))) {
3110 /* Depth-only transitions. */
3111 range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3112 radv_handle_image_transition(cmd_buffer,
3113 view->image,
3114 cmd_buffer->state.attachments[idx].current_layout,
3115 cmd_buffer->state.attachments[idx].current_in_render_loop,
3116 att.layout, att.in_render_loop,
3117 0, 0, &range, sample_locs);
3118
3119 /* Stencil-only transitions. */
3120 range.aspectMask = VK_IMAGE_ASPECT_STENCIL_BIT;
3121 radv_handle_image_transition(cmd_buffer,
3122 view->image,
3123 cmd_buffer->state.attachments[idx].current_stencil_layout,
3124 cmd_buffer->state.attachments[idx].current_in_render_loop,
3125 att.stencil_layout, att.in_render_loop,
3126 0, 0, &range, sample_locs);
3127 } else {
3128 radv_handle_image_transition(cmd_buffer,
3129 view->image,
3130 cmd_buffer->state.attachments[idx].current_layout,
3131 cmd_buffer->state.attachments[idx].current_in_render_loop,
3132 att.layout, att.in_render_loop,
3133 0, 0, &range, sample_locs);
3134 }
3135
3136 cmd_buffer->state.attachments[idx].current_layout = att.layout;
3137 cmd_buffer->state.attachments[idx].current_stencil_layout = att.stencil_layout;
3138 cmd_buffer->state.attachments[idx].current_in_render_loop = att.in_render_loop;
3139
3140
3141 }
3142
3143 void
3144 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
3145 const struct radv_subpass *subpass)
3146 {
3147 cmd_buffer->state.subpass = subpass;
3148
3149 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
3150 }
3151
3152 static VkResult
3153 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
3154 struct radv_render_pass *pass,
3155 const VkRenderPassBeginInfo *info)
3156 {
3157 const struct VkRenderPassSampleLocationsBeginInfoEXT *sample_locs =
3158 vk_find_struct_const(info->pNext,
3159 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT);
3160 struct radv_cmd_state *state = &cmd_buffer->state;
3161
3162 if (!sample_locs) {
3163 state->subpass_sample_locs = NULL;
3164 return VK_SUCCESS;
3165 }
3166
3167 for (uint32_t i = 0; i < sample_locs->attachmentInitialSampleLocationsCount; i++) {
3168 const VkAttachmentSampleLocationsEXT *att_sample_locs =
3169 &sample_locs->pAttachmentInitialSampleLocations[i];
3170 uint32_t att_idx = att_sample_locs->attachmentIndex;
3171 struct radv_image *image = cmd_buffer->state.attachments[att_idx].iview->image;
3172
3173 assert(vk_format_is_depth_or_stencil(image->vk_format));
3174
3175 /* From the Vulkan spec 1.1.108:
3176 *
3177 * "If the image referenced by the framebuffer attachment at
3178 * index attachmentIndex was not created with
3179 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
3180 * then the values specified in sampleLocationsInfo are
3181 * ignored."
3182 */
3183 if (!(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT))
3184 continue;
3185
3186 const VkSampleLocationsInfoEXT *sample_locs_info =
3187 &att_sample_locs->sampleLocationsInfo;
3188
3189 state->attachments[att_idx].sample_location.per_pixel =
3190 sample_locs_info->sampleLocationsPerPixel;
3191 state->attachments[att_idx].sample_location.grid_size =
3192 sample_locs_info->sampleLocationGridSize;
3193 state->attachments[att_idx].sample_location.count =
3194 sample_locs_info->sampleLocationsCount;
3195 typed_memcpy(&state->attachments[att_idx].sample_location.locations[0],
3196 sample_locs_info->pSampleLocations,
3197 sample_locs_info->sampleLocationsCount);
3198 }
3199
3200 state->subpass_sample_locs = vk_alloc(&cmd_buffer->pool->alloc,
3201 sample_locs->postSubpassSampleLocationsCount *
3202 sizeof(state->subpass_sample_locs[0]),
3203 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3204 if (state->subpass_sample_locs == NULL) {
3205 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3206 return cmd_buffer->record_result;
3207 }
3208
3209 state->num_subpass_sample_locs = sample_locs->postSubpassSampleLocationsCount;
3210
3211 for (uint32_t i = 0; i < sample_locs->postSubpassSampleLocationsCount; i++) {
3212 const VkSubpassSampleLocationsEXT *subpass_sample_locs_info =
3213 &sample_locs->pPostSubpassSampleLocations[i];
3214 const VkSampleLocationsInfoEXT *sample_locs_info =
3215 &subpass_sample_locs_info->sampleLocationsInfo;
3216
3217 state->subpass_sample_locs[i].subpass_idx =
3218 subpass_sample_locs_info->subpassIndex;
3219 state->subpass_sample_locs[i].sample_location.per_pixel =
3220 sample_locs_info->sampleLocationsPerPixel;
3221 state->subpass_sample_locs[i].sample_location.grid_size =
3222 sample_locs_info->sampleLocationGridSize;
3223 state->subpass_sample_locs[i].sample_location.count =
3224 sample_locs_info->sampleLocationsCount;
3225 typed_memcpy(&state->subpass_sample_locs[i].sample_location.locations[0],
3226 sample_locs_info->pSampleLocations,
3227 sample_locs_info->sampleLocationsCount);
3228 }
3229
3230 return VK_SUCCESS;
3231 }
3232
3233 static VkResult
3234 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
3235 struct radv_render_pass *pass,
3236 const VkRenderPassBeginInfo *info)
3237 {
3238 struct radv_cmd_state *state = &cmd_buffer->state;
3239 const struct VkRenderPassAttachmentBeginInfo *attachment_info = NULL;
3240
3241 if (info) {
3242 attachment_info = vk_find_struct_const(info->pNext,
3243 RENDER_PASS_ATTACHMENT_BEGIN_INFO);
3244 }
3245
3246
3247 if (pass->attachment_count == 0) {
3248 state->attachments = NULL;
3249 return VK_SUCCESS;
3250 }
3251
3252 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
3253 pass->attachment_count *
3254 sizeof(state->attachments[0]),
3255 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3256 if (state->attachments == NULL) {
3257 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3258 return cmd_buffer->record_result;
3259 }
3260
3261 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
3262 struct radv_render_pass_attachment *att = &pass->attachments[i];
3263 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
3264 VkImageAspectFlags clear_aspects = 0;
3265
3266 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
3267 /* color attachment */
3268 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3269 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
3270 }
3271 } else {
3272 /* depthstencil attachment */
3273 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
3274 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3275 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
3276 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3277 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
3278 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3279 }
3280 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3281 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3282 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3283 }
3284 }
3285
3286 state->attachments[i].pending_clear_aspects = clear_aspects;
3287 state->attachments[i].cleared_views = 0;
3288 if (clear_aspects && info) {
3289 assert(info->clearValueCount > i);
3290 state->attachments[i].clear_value = info->pClearValues[i];
3291 }
3292
3293 state->attachments[i].current_layout = att->initial_layout;
3294 state->attachments[i].current_stencil_layout = att->stencil_initial_layout;
3295 state->attachments[i].sample_location.count = 0;
3296
3297 struct radv_image_view *iview;
3298 if (attachment_info && attachment_info->attachmentCount > i) {
3299 iview = radv_image_view_from_handle(attachment_info->pAttachments[i]);
3300 } else {
3301 iview = state->framebuffer->attachments[i];
3302 }
3303
3304 state->attachments[i].iview = iview;
3305 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3306 radv_initialise_ds_surface(cmd_buffer->device, &state->attachments[i].ds, iview);
3307 } else {
3308 radv_initialise_color_surface(cmd_buffer->device, &state->attachments[i].cb, iview);
3309 }
3310 }
3311
3312 return VK_SUCCESS;
3313 }
3314
3315 VkResult radv_AllocateCommandBuffers(
3316 VkDevice _device,
3317 const VkCommandBufferAllocateInfo *pAllocateInfo,
3318 VkCommandBuffer *pCommandBuffers)
3319 {
3320 RADV_FROM_HANDLE(radv_device, device, _device);
3321 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
3322
3323 VkResult result = VK_SUCCESS;
3324 uint32_t i;
3325
3326 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
3327
3328 if (!list_is_empty(&pool->free_cmd_buffers)) {
3329 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
3330
3331 list_del(&cmd_buffer->pool_link);
3332 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
3333
3334 result = radv_reset_cmd_buffer(cmd_buffer);
3335 cmd_buffer->level = pAllocateInfo->level;
3336
3337 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
3338 } else {
3339 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
3340 &pCommandBuffers[i]);
3341 }
3342 if (result != VK_SUCCESS)
3343 break;
3344 }
3345
3346 if (result != VK_SUCCESS) {
3347 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
3348 i, pCommandBuffers);
3349
3350 /* From the Vulkan 1.0.66 spec:
3351 *
3352 * "vkAllocateCommandBuffers can be used to create multiple
3353 * command buffers. If the creation of any of those command
3354 * buffers fails, the implementation must destroy all
3355 * successfully created command buffer objects from this
3356 * command, set all entries of the pCommandBuffers array to
3357 * NULL and return the error."
3358 */
3359 memset(pCommandBuffers, 0,
3360 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
3361 }
3362
3363 return result;
3364 }
3365
3366 void radv_FreeCommandBuffers(
3367 VkDevice device,
3368 VkCommandPool commandPool,
3369 uint32_t commandBufferCount,
3370 const VkCommandBuffer *pCommandBuffers)
3371 {
3372 for (uint32_t i = 0; i < commandBufferCount; i++) {
3373 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
3374
3375 if (cmd_buffer) {
3376 if (cmd_buffer->pool) {
3377 list_del(&cmd_buffer->pool_link);
3378 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
3379 } else
3380 radv_cmd_buffer_destroy(cmd_buffer);
3381
3382 }
3383 }
3384 }
3385
3386 VkResult radv_ResetCommandBuffer(
3387 VkCommandBuffer commandBuffer,
3388 VkCommandBufferResetFlags flags)
3389 {
3390 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3391 return radv_reset_cmd_buffer(cmd_buffer);
3392 }
3393
3394 VkResult radv_BeginCommandBuffer(
3395 VkCommandBuffer commandBuffer,
3396 const VkCommandBufferBeginInfo *pBeginInfo)
3397 {
3398 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3399 VkResult result = VK_SUCCESS;
3400
3401 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
3402 /* If the command buffer has already been resetted with
3403 * vkResetCommandBuffer, no need to do it again.
3404 */
3405 result = radv_reset_cmd_buffer(cmd_buffer);
3406 if (result != VK_SUCCESS)
3407 return result;
3408 }
3409
3410 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
3411 cmd_buffer->state.last_primitive_reset_en = -1;
3412 cmd_buffer->state.last_index_type = -1;
3413 cmd_buffer->state.last_num_instances = -1;
3414 cmd_buffer->state.last_vertex_offset = -1;
3415 cmd_buffer->state.last_first_instance = -1;
3416 cmd_buffer->state.predication_type = -1;
3417 cmd_buffer->state.last_sx_ps_downconvert = -1;
3418 cmd_buffer->state.last_sx_blend_opt_epsilon = -1;
3419 cmd_buffer->state.last_sx_blend_opt_control = -1;
3420 cmd_buffer->usage_flags = pBeginInfo->flags;
3421
3422 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
3423 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
3424 assert(pBeginInfo->pInheritanceInfo);
3425 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
3426 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
3427
3428 struct radv_subpass *subpass =
3429 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
3430
3431 if (cmd_buffer->state.framebuffer) {
3432 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
3433 if (result != VK_SUCCESS)
3434 return result;
3435 }
3436
3437 cmd_buffer->state.inherited_pipeline_statistics =
3438 pBeginInfo->pInheritanceInfo->pipelineStatistics;
3439
3440 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3441 }
3442
3443 if (unlikely(cmd_buffer->device->trace_bo))
3444 radv_cmd_buffer_trace_emit(cmd_buffer);
3445
3446 radv_describe_begin_cmd_buffer(cmd_buffer);
3447
3448 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
3449
3450 return result;
3451 }
3452
3453 void radv_CmdBindVertexBuffers(
3454 VkCommandBuffer commandBuffer,
3455 uint32_t firstBinding,
3456 uint32_t bindingCount,
3457 const VkBuffer* pBuffers,
3458 const VkDeviceSize* pOffsets)
3459 {
3460 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3461 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
3462 bool changed = false;
3463
3464 /* We have to defer setting up vertex buffer since we need the buffer
3465 * stride from the pipeline. */
3466
3467 assert(firstBinding + bindingCount <= MAX_VBS);
3468 for (uint32_t i = 0; i < bindingCount; i++) {
3469 RADV_FROM_HANDLE(radv_buffer, buffer, pBuffers[i]);
3470 uint32_t idx = firstBinding + i;
3471
3472 if (!changed &&
3473 (vb[idx].buffer != buffer ||
3474 vb[idx].offset != pOffsets[i])) {
3475 changed = true;
3476 }
3477
3478 vb[idx].buffer = buffer;
3479 vb[idx].offset = pOffsets[i];
3480
3481 if (buffer) {
3482 radv_cs_add_buffer(cmd_buffer->device->ws,
3483 cmd_buffer->cs, vb[idx].buffer->bo);
3484 }
3485 }
3486
3487 if (!changed) {
3488 /* No state changes. */
3489 return;
3490 }
3491
3492 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
3493 }
3494
3495 static uint32_t
3496 vk_to_index_type(VkIndexType type)
3497 {
3498 switch (type) {
3499 case VK_INDEX_TYPE_UINT8_EXT:
3500 return V_028A7C_VGT_INDEX_8;
3501 case VK_INDEX_TYPE_UINT16:
3502 return V_028A7C_VGT_INDEX_16;
3503 case VK_INDEX_TYPE_UINT32:
3504 return V_028A7C_VGT_INDEX_32;
3505 default:
3506 unreachable("invalid index type");
3507 }
3508 }
3509
3510 static uint32_t
3511 radv_get_vgt_index_size(uint32_t type)
3512 {
3513 switch (type) {
3514 case V_028A7C_VGT_INDEX_8:
3515 return 1;
3516 case V_028A7C_VGT_INDEX_16:
3517 return 2;
3518 case V_028A7C_VGT_INDEX_32:
3519 return 4;
3520 default:
3521 unreachable("invalid index type");
3522 }
3523 }
3524
3525 void radv_CmdBindIndexBuffer(
3526 VkCommandBuffer commandBuffer,
3527 VkBuffer buffer,
3528 VkDeviceSize offset,
3529 VkIndexType indexType)
3530 {
3531 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3532 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
3533
3534 if (cmd_buffer->state.index_buffer == index_buffer &&
3535 cmd_buffer->state.index_offset == offset &&
3536 cmd_buffer->state.index_type == indexType) {
3537 /* No state changes. */
3538 return;
3539 }
3540
3541 cmd_buffer->state.index_buffer = index_buffer;
3542 cmd_buffer->state.index_offset = offset;
3543 cmd_buffer->state.index_type = vk_to_index_type(indexType);
3544 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
3545 cmd_buffer->state.index_va += index_buffer->offset + offset;
3546
3547 int index_size = radv_get_vgt_index_size(vk_to_index_type(indexType));
3548 cmd_buffer->state.max_index_count = (index_buffer->size - offset) / index_size;
3549 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3550 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
3551 }
3552
3553
3554 static void
3555 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3556 VkPipelineBindPoint bind_point,
3557 struct radv_descriptor_set *set, unsigned idx)
3558 {
3559 struct radeon_winsys *ws = cmd_buffer->device->ws;
3560
3561 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
3562
3563 assert(set);
3564 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
3565
3566 if (!cmd_buffer->device->use_global_bo_list) {
3567 for (unsigned j = 0; j < set->buffer_count; ++j)
3568 if (set->descriptors[j])
3569 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
3570 }
3571
3572 if(set->bo)
3573 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
3574 }
3575
3576 void radv_CmdBindDescriptorSets(
3577 VkCommandBuffer commandBuffer,
3578 VkPipelineBindPoint pipelineBindPoint,
3579 VkPipelineLayout _layout,
3580 uint32_t firstSet,
3581 uint32_t descriptorSetCount,
3582 const VkDescriptorSet* pDescriptorSets,
3583 uint32_t dynamicOffsetCount,
3584 const uint32_t* pDynamicOffsets)
3585 {
3586 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3587 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3588 unsigned dyn_idx = 0;
3589
3590 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
3591 struct radv_descriptor_state *descriptors_state =
3592 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3593
3594 for (unsigned i = 0; i < descriptorSetCount; ++i) {
3595 unsigned idx = i + firstSet;
3596 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
3597
3598 /* If the set is already bound we only need to update the
3599 * (potentially changed) dynamic offsets. */
3600 if (descriptors_state->sets[idx] != set ||
3601 !(descriptors_state->valid & (1u << idx))) {
3602 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
3603 }
3604
3605 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
3606 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
3607 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
3608 assert(dyn_idx < dynamicOffsetCount);
3609
3610 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
3611 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
3612 dst[0] = va;
3613 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
3614 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
3615 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3616 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3617 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3618 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3619
3620 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
3621 dst[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3622 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3623 S_008F0C_RESOURCE_LEVEL(1);
3624 } else {
3625 dst[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3626 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3627 }
3628
3629 cmd_buffer->push_constant_stages |=
3630 set->layout->dynamic_shader_stages;
3631 }
3632 }
3633 }
3634
3635 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3636 struct radv_descriptor_set *set,
3637 struct radv_descriptor_set_layout *layout,
3638 VkPipelineBindPoint bind_point)
3639 {
3640 struct radv_descriptor_state *descriptors_state =
3641 radv_get_descriptors_state(cmd_buffer, bind_point);
3642 set->size = layout->size;
3643 set->layout = layout;
3644
3645 if (descriptors_state->push_set.capacity < set->size) {
3646 size_t new_size = MAX2(set->size, 1024);
3647 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
3648 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
3649
3650 free(set->mapped_ptr);
3651 set->mapped_ptr = malloc(new_size);
3652
3653 if (!set->mapped_ptr) {
3654 descriptors_state->push_set.capacity = 0;
3655 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3656 return false;
3657 }
3658
3659 descriptors_state->push_set.capacity = new_size;
3660 }
3661
3662 return true;
3663 }
3664
3665 void radv_meta_push_descriptor_set(
3666 struct radv_cmd_buffer* cmd_buffer,
3667 VkPipelineBindPoint pipelineBindPoint,
3668 VkPipelineLayout _layout,
3669 uint32_t set,
3670 uint32_t descriptorWriteCount,
3671 const VkWriteDescriptorSet* pDescriptorWrites)
3672 {
3673 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3674 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
3675 unsigned bo_offset;
3676
3677 assert(set == 0);
3678 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3679
3680 push_set->size = layout->set[set].layout->size;
3681 push_set->layout = layout->set[set].layout;
3682
3683 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
3684 &bo_offset,
3685 (void**) &push_set->mapped_ptr))
3686 return;
3687
3688 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
3689 push_set->va += bo_offset;
3690
3691 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3692 radv_descriptor_set_to_handle(push_set),
3693 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3694
3695 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3696 }
3697
3698 void radv_CmdPushDescriptorSetKHR(
3699 VkCommandBuffer commandBuffer,
3700 VkPipelineBindPoint pipelineBindPoint,
3701 VkPipelineLayout _layout,
3702 uint32_t set,
3703 uint32_t descriptorWriteCount,
3704 const VkWriteDescriptorSet* pDescriptorWrites)
3705 {
3706 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3707 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3708 struct radv_descriptor_state *descriptors_state =
3709 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3710 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3711
3712 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3713
3714 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3715 layout->set[set].layout,
3716 pipelineBindPoint))
3717 return;
3718
3719 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3720 * because it is invalid, according to Vulkan spec.
3721 */
3722 for (int i = 0; i < descriptorWriteCount; i++) {
3723 ASSERTED const VkWriteDescriptorSet *writeset = &pDescriptorWrites[i];
3724 assert(writeset->descriptorType != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT);
3725 }
3726
3727 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3728 radv_descriptor_set_to_handle(push_set),
3729 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3730
3731 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3732 descriptors_state->push_dirty = true;
3733 }
3734
3735 void radv_CmdPushDescriptorSetWithTemplateKHR(
3736 VkCommandBuffer commandBuffer,
3737 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
3738 VkPipelineLayout _layout,
3739 uint32_t set,
3740 const void* pData)
3741 {
3742 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3743 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3744 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
3745 struct radv_descriptor_state *descriptors_state =
3746 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
3747 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3748
3749 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3750
3751 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3752 layout->set[set].layout,
3753 templ->bind_point))
3754 return;
3755
3756 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
3757 descriptorUpdateTemplate, pData);
3758
3759 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
3760 descriptors_state->push_dirty = true;
3761 }
3762
3763 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
3764 VkPipelineLayout layout,
3765 VkShaderStageFlags stageFlags,
3766 uint32_t offset,
3767 uint32_t size,
3768 const void* pValues)
3769 {
3770 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3771 memcpy(cmd_buffer->push_constants + offset, pValues, size);
3772 cmd_buffer->push_constant_stages |= stageFlags;
3773 }
3774
3775 VkResult radv_EndCommandBuffer(
3776 VkCommandBuffer commandBuffer)
3777 {
3778 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3779
3780 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
3781 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6)
3782 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WB_L2;
3783
3784 /* Make sure to sync all pending active queries at the end of
3785 * command buffer.
3786 */
3787 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
3788
3789 /* Since NGG streamout uses GDS, we need to make GDS idle when
3790 * we leave the IB, otherwise another process might overwrite
3791 * it while our shaders are busy.
3792 */
3793 if (cmd_buffer->gds_needed)
3794 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
3795
3796 si_emit_cache_flush(cmd_buffer);
3797 }
3798
3799 /* Make sure CP DMA is idle at the end of IBs because the kernel
3800 * doesn't wait for it.
3801 */
3802 si_cp_dma_wait_for_idle(cmd_buffer);
3803
3804 radv_describe_end_cmd_buffer(cmd_buffer);
3805
3806 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3807 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
3808
3809 VkResult result = cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs);
3810 if (result != VK_SUCCESS)
3811 return vk_error(cmd_buffer->device->instance, result);
3812
3813 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
3814
3815 return cmd_buffer->record_result;
3816 }
3817
3818 static void
3819 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
3820 {
3821 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3822
3823 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
3824 return;
3825
3826 assert(!pipeline->ctx_cs.cdw);
3827
3828 cmd_buffer->state.emitted_compute_pipeline = pipeline;
3829
3830 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
3831 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
3832
3833 cmd_buffer->compute_scratch_size_per_wave_needed = MAX2(cmd_buffer->compute_scratch_size_per_wave_needed,
3834 pipeline->scratch_bytes_per_wave);
3835 cmd_buffer->compute_scratch_waves_wanted = MAX2(cmd_buffer->compute_scratch_waves_wanted,
3836 pipeline->max_waves);
3837
3838 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3839 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
3840
3841 if (unlikely(cmd_buffer->device->trace_bo))
3842 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
3843 }
3844
3845 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
3846 VkPipelineBindPoint bind_point)
3847 {
3848 struct radv_descriptor_state *descriptors_state =
3849 radv_get_descriptors_state(cmd_buffer, bind_point);
3850
3851 descriptors_state->dirty |= descriptors_state->valid;
3852 }
3853
3854 void radv_CmdBindPipeline(
3855 VkCommandBuffer commandBuffer,
3856 VkPipelineBindPoint pipelineBindPoint,
3857 VkPipeline _pipeline)
3858 {
3859 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3860 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
3861
3862 switch (pipelineBindPoint) {
3863 case VK_PIPELINE_BIND_POINT_COMPUTE:
3864 if (cmd_buffer->state.compute_pipeline == pipeline)
3865 return;
3866 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3867
3868 cmd_buffer->state.compute_pipeline = pipeline;
3869 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
3870 break;
3871 case VK_PIPELINE_BIND_POINT_GRAPHICS:
3872 if (cmd_buffer->state.pipeline == pipeline)
3873 return;
3874 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3875
3876 cmd_buffer->state.pipeline = pipeline;
3877 if (!pipeline)
3878 break;
3879
3880 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
3881 cmd_buffer->push_constant_stages |= pipeline->active_stages;
3882
3883 /* the new vertex shader might not have the same user regs */
3884 cmd_buffer->state.last_first_instance = -1;
3885 cmd_buffer->state.last_vertex_offset = -1;
3886
3887 /* Prefetch all pipeline shaders at first draw time. */
3888 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
3889
3890 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX10 &&
3891 cmd_buffer->state.emitted_pipeline &&
3892 radv_pipeline_has_ngg(cmd_buffer->state.emitted_pipeline) &&
3893 !radv_pipeline_has_ngg(cmd_buffer->state.pipeline)) {
3894 /* Transitioning from NGG to legacy GS requires
3895 * VGT_FLUSH on Navi10-14. VGT_FLUSH is also emitted
3896 * at the beginning of IBs when legacy GS ring pointers
3897 * are set.
3898 */
3899 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
3900 }
3901
3902 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
3903 radv_bind_streamout_state(cmd_buffer, pipeline);
3904
3905 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
3906 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
3907 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
3908 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
3909
3910 if (radv_pipeline_has_tess(pipeline))
3911 cmd_buffer->tess_rings_needed = true;
3912 break;
3913 default:
3914 assert(!"invalid bind point");
3915 break;
3916 }
3917 }
3918
3919 void radv_CmdSetViewport(
3920 VkCommandBuffer commandBuffer,
3921 uint32_t firstViewport,
3922 uint32_t viewportCount,
3923 const VkViewport* pViewports)
3924 {
3925 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3926 struct radv_cmd_state *state = &cmd_buffer->state;
3927 ASSERTED const uint32_t total_count = firstViewport + viewportCount;
3928
3929 assert(firstViewport < MAX_VIEWPORTS);
3930 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
3931
3932 if (!memcmp(state->dynamic.viewport.viewports + firstViewport,
3933 pViewports, viewportCount * sizeof(*pViewports))) {
3934 return;
3935 }
3936
3937 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
3938 viewportCount * sizeof(*pViewports));
3939
3940 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
3941 }
3942
3943 void radv_CmdSetScissor(
3944 VkCommandBuffer commandBuffer,
3945 uint32_t firstScissor,
3946 uint32_t scissorCount,
3947 const VkRect2D* pScissors)
3948 {
3949 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3950 struct radv_cmd_state *state = &cmd_buffer->state;
3951 ASSERTED const uint32_t total_count = firstScissor + scissorCount;
3952
3953 assert(firstScissor < MAX_SCISSORS);
3954 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
3955
3956 if (!memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
3957 scissorCount * sizeof(*pScissors))) {
3958 return;
3959 }
3960
3961 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
3962 scissorCount * sizeof(*pScissors));
3963
3964 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
3965 }
3966
3967 void radv_CmdSetLineWidth(
3968 VkCommandBuffer commandBuffer,
3969 float lineWidth)
3970 {
3971 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3972
3973 if (cmd_buffer->state.dynamic.line_width == lineWidth)
3974 return;
3975
3976 cmd_buffer->state.dynamic.line_width = lineWidth;
3977 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
3978 }
3979
3980 void radv_CmdSetDepthBias(
3981 VkCommandBuffer commandBuffer,
3982 float depthBiasConstantFactor,
3983 float depthBiasClamp,
3984 float depthBiasSlopeFactor)
3985 {
3986 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3987 struct radv_cmd_state *state = &cmd_buffer->state;
3988
3989 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
3990 state->dynamic.depth_bias.clamp == depthBiasClamp &&
3991 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
3992 return;
3993 }
3994
3995 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
3996 state->dynamic.depth_bias.clamp = depthBiasClamp;
3997 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
3998
3999 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
4000 }
4001
4002 void radv_CmdSetBlendConstants(
4003 VkCommandBuffer commandBuffer,
4004 const float blendConstants[4])
4005 {
4006 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4007 struct radv_cmd_state *state = &cmd_buffer->state;
4008
4009 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
4010 return;
4011
4012 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
4013
4014 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
4015 }
4016
4017 void radv_CmdSetDepthBounds(
4018 VkCommandBuffer commandBuffer,
4019 float minDepthBounds,
4020 float maxDepthBounds)
4021 {
4022 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4023 struct radv_cmd_state *state = &cmd_buffer->state;
4024
4025 if (state->dynamic.depth_bounds.min == minDepthBounds &&
4026 state->dynamic.depth_bounds.max == maxDepthBounds) {
4027 return;
4028 }
4029
4030 state->dynamic.depth_bounds.min = minDepthBounds;
4031 state->dynamic.depth_bounds.max = maxDepthBounds;
4032
4033 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
4034 }
4035
4036 void radv_CmdSetStencilCompareMask(
4037 VkCommandBuffer commandBuffer,
4038 VkStencilFaceFlags faceMask,
4039 uint32_t compareMask)
4040 {
4041 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4042 struct radv_cmd_state *state = &cmd_buffer->state;
4043 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
4044 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
4045
4046 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4047 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4048 return;
4049 }
4050
4051 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4052 state->dynamic.stencil_compare_mask.front = compareMask;
4053 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4054 state->dynamic.stencil_compare_mask.back = compareMask;
4055
4056 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
4057 }
4058
4059 void radv_CmdSetStencilWriteMask(
4060 VkCommandBuffer commandBuffer,
4061 VkStencilFaceFlags faceMask,
4062 uint32_t writeMask)
4063 {
4064 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4065 struct radv_cmd_state *state = &cmd_buffer->state;
4066 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
4067 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
4068
4069 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4070 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4071 return;
4072 }
4073
4074 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4075 state->dynamic.stencil_write_mask.front = writeMask;
4076 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4077 state->dynamic.stencil_write_mask.back = writeMask;
4078
4079 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
4080 }
4081
4082 void radv_CmdSetStencilReference(
4083 VkCommandBuffer commandBuffer,
4084 VkStencilFaceFlags faceMask,
4085 uint32_t reference)
4086 {
4087 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4088 struct radv_cmd_state *state = &cmd_buffer->state;
4089 bool front_same = state->dynamic.stencil_reference.front == reference;
4090 bool back_same = state->dynamic.stencil_reference.back == reference;
4091
4092 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4093 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4094 return;
4095 }
4096
4097 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4098 cmd_buffer->state.dynamic.stencil_reference.front = reference;
4099 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4100 cmd_buffer->state.dynamic.stencil_reference.back = reference;
4101
4102 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
4103 }
4104
4105 void radv_CmdSetDiscardRectangleEXT(
4106 VkCommandBuffer commandBuffer,
4107 uint32_t firstDiscardRectangle,
4108 uint32_t discardRectangleCount,
4109 const VkRect2D* pDiscardRectangles)
4110 {
4111 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4112 struct radv_cmd_state *state = &cmd_buffer->state;
4113 ASSERTED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
4114
4115 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
4116 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
4117
4118 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
4119 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
4120 return;
4121 }
4122
4123 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
4124 pDiscardRectangles, discardRectangleCount);
4125
4126 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
4127 }
4128
4129 void radv_CmdSetSampleLocationsEXT(
4130 VkCommandBuffer commandBuffer,
4131 const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
4132 {
4133 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4134 struct radv_cmd_state *state = &cmd_buffer->state;
4135
4136 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
4137
4138 state->dynamic.sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
4139 state->dynamic.sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
4140 state->dynamic.sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
4141 typed_memcpy(&state->dynamic.sample_location.locations[0],
4142 pSampleLocationsInfo->pSampleLocations,
4143 pSampleLocationsInfo->sampleLocationsCount);
4144
4145 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS;
4146 }
4147
4148 void radv_CmdSetLineStippleEXT(
4149 VkCommandBuffer commandBuffer,
4150 uint32_t lineStippleFactor,
4151 uint16_t lineStipplePattern)
4152 {
4153 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4154 struct radv_cmd_state *state = &cmd_buffer->state;
4155
4156 state->dynamic.line_stipple.factor = lineStippleFactor;
4157 state->dynamic.line_stipple.pattern = lineStipplePattern;
4158
4159 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE;
4160 }
4161
4162 void radv_CmdExecuteCommands(
4163 VkCommandBuffer commandBuffer,
4164 uint32_t commandBufferCount,
4165 const VkCommandBuffer* pCmdBuffers)
4166 {
4167 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
4168
4169 assert(commandBufferCount > 0);
4170
4171 /* Emit pending flushes on primary prior to executing secondary */
4172 si_emit_cache_flush(primary);
4173
4174 for (uint32_t i = 0; i < commandBufferCount; i++) {
4175 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
4176
4177 primary->scratch_size_per_wave_needed = MAX2(primary->scratch_size_per_wave_needed,
4178 secondary->scratch_size_per_wave_needed);
4179 primary->scratch_waves_wanted = MAX2(primary->scratch_waves_wanted,
4180 secondary->scratch_waves_wanted);
4181 primary->compute_scratch_size_per_wave_needed = MAX2(primary->compute_scratch_size_per_wave_needed,
4182 secondary->compute_scratch_size_per_wave_needed);
4183 primary->compute_scratch_waves_wanted = MAX2(primary->compute_scratch_waves_wanted,
4184 secondary->compute_scratch_waves_wanted);
4185
4186 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
4187 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
4188 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
4189 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
4190 if (secondary->tess_rings_needed)
4191 primary->tess_rings_needed = true;
4192 if (secondary->sample_positions_needed)
4193 primary->sample_positions_needed = true;
4194 if (secondary->gds_needed)
4195 primary->gds_needed = true;
4196
4197 if (!secondary->state.framebuffer &&
4198 (primary->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)) {
4199 /* Emit the framebuffer state from primary if secondary
4200 * has been recorded without a framebuffer, otherwise
4201 * fast color/depth clears can't work.
4202 */
4203 radv_emit_framebuffer_state(primary);
4204 }
4205
4206 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
4207
4208
4209 /* When the secondary command buffer is compute only we don't
4210 * need to re-emit the current graphics pipeline.
4211 */
4212 if (secondary->state.emitted_pipeline) {
4213 primary->state.emitted_pipeline =
4214 secondary->state.emitted_pipeline;
4215 }
4216
4217 /* When the secondary command buffer is graphics only we don't
4218 * need to re-emit the current compute pipeline.
4219 */
4220 if (secondary->state.emitted_compute_pipeline) {
4221 primary->state.emitted_compute_pipeline =
4222 secondary->state.emitted_compute_pipeline;
4223 }
4224
4225 /* Only re-emit the draw packets when needed. */
4226 if (secondary->state.last_primitive_reset_en != -1) {
4227 primary->state.last_primitive_reset_en =
4228 secondary->state.last_primitive_reset_en;
4229 }
4230
4231 if (secondary->state.last_primitive_reset_index) {
4232 primary->state.last_primitive_reset_index =
4233 secondary->state.last_primitive_reset_index;
4234 }
4235
4236 if (secondary->state.last_ia_multi_vgt_param) {
4237 primary->state.last_ia_multi_vgt_param =
4238 secondary->state.last_ia_multi_vgt_param;
4239 }
4240
4241 primary->state.last_first_instance = secondary->state.last_first_instance;
4242 primary->state.last_num_instances = secondary->state.last_num_instances;
4243 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
4244 primary->state.last_sx_ps_downconvert = secondary->state.last_sx_ps_downconvert;
4245 primary->state.last_sx_blend_opt_epsilon = secondary->state.last_sx_blend_opt_epsilon;
4246 primary->state.last_sx_blend_opt_control = secondary->state.last_sx_blend_opt_control;
4247
4248 if (secondary->state.last_index_type != -1) {
4249 primary->state.last_index_type =
4250 secondary->state.last_index_type;
4251 }
4252 }
4253
4254 /* After executing commands from secondary buffers we have to dirty
4255 * some states.
4256 */
4257 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
4258 RADV_CMD_DIRTY_INDEX_BUFFER |
4259 RADV_CMD_DIRTY_DYNAMIC_ALL;
4260 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
4261 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
4262 }
4263
4264 VkResult radv_CreateCommandPool(
4265 VkDevice _device,
4266 const VkCommandPoolCreateInfo* pCreateInfo,
4267 const VkAllocationCallbacks* pAllocator,
4268 VkCommandPool* pCmdPool)
4269 {
4270 RADV_FROM_HANDLE(radv_device, device, _device);
4271 struct radv_cmd_pool *pool;
4272
4273 pool = vk_alloc2(&device->vk.alloc, pAllocator, sizeof(*pool), 8,
4274 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4275 if (pool == NULL)
4276 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4277
4278 vk_object_base_init(&device->vk, &pool->base,
4279 VK_OBJECT_TYPE_COMMAND_POOL);
4280
4281 if (pAllocator)
4282 pool->alloc = *pAllocator;
4283 else
4284 pool->alloc = device->vk.alloc;
4285
4286 list_inithead(&pool->cmd_buffers);
4287 list_inithead(&pool->free_cmd_buffers);
4288
4289 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
4290
4291 *pCmdPool = radv_cmd_pool_to_handle(pool);
4292
4293 return VK_SUCCESS;
4294
4295 }
4296
4297 void radv_DestroyCommandPool(
4298 VkDevice _device,
4299 VkCommandPool commandPool,
4300 const VkAllocationCallbacks* pAllocator)
4301 {
4302 RADV_FROM_HANDLE(radv_device, device, _device);
4303 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4304
4305 if (!pool)
4306 return;
4307
4308 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4309 &pool->cmd_buffers, pool_link) {
4310 radv_cmd_buffer_destroy(cmd_buffer);
4311 }
4312
4313 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4314 &pool->free_cmd_buffers, pool_link) {
4315 radv_cmd_buffer_destroy(cmd_buffer);
4316 }
4317
4318 vk_object_base_finish(&pool->base);
4319 vk_free2(&device->vk.alloc, pAllocator, pool);
4320 }
4321
4322 VkResult radv_ResetCommandPool(
4323 VkDevice device,
4324 VkCommandPool commandPool,
4325 VkCommandPoolResetFlags flags)
4326 {
4327 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4328 VkResult result;
4329
4330 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
4331 &pool->cmd_buffers, pool_link) {
4332 result = radv_reset_cmd_buffer(cmd_buffer);
4333 if (result != VK_SUCCESS)
4334 return result;
4335 }
4336
4337 return VK_SUCCESS;
4338 }
4339
4340 void radv_TrimCommandPool(
4341 VkDevice device,
4342 VkCommandPool commandPool,
4343 VkCommandPoolTrimFlags flags)
4344 {
4345 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4346
4347 if (!pool)
4348 return;
4349
4350 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4351 &pool->free_cmd_buffers, pool_link) {
4352 radv_cmd_buffer_destroy(cmd_buffer);
4353 }
4354 }
4355
4356 static void
4357 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
4358 uint32_t subpass_id)
4359 {
4360 struct radv_cmd_state *state = &cmd_buffer->state;
4361 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
4362
4363 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
4364 cmd_buffer->cs, 4096);
4365
4366 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
4367
4368 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
4369
4370 radv_describe_barrier_start(cmd_buffer, RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC);
4371
4372 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4373 const uint32_t a = subpass->attachments[i].attachment;
4374 if (a == VK_ATTACHMENT_UNUSED)
4375 continue;
4376
4377 radv_handle_subpass_image_transition(cmd_buffer,
4378 subpass->attachments[i],
4379 true);
4380 }
4381
4382 radv_describe_barrier_end(cmd_buffer);
4383
4384 radv_cmd_buffer_clear_subpass(cmd_buffer);
4385
4386 assert(cmd_buffer->cs->cdw <= cdw_max);
4387 }
4388
4389 static void
4390 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
4391 {
4392 struct radv_cmd_state *state = &cmd_buffer->state;
4393 const struct radv_subpass *subpass = state->subpass;
4394 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
4395
4396 radv_cmd_buffer_resolve_subpass(cmd_buffer);
4397
4398 radv_describe_barrier_start(cmd_buffer, RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC);
4399
4400 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4401 const uint32_t a = subpass->attachments[i].attachment;
4402 if (a == VK_ATTACHMENT_UNUSED)
4403 continue;
4404
4405 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
4406 continue;
4407
4408 VkImageLayout layout = state->pass->attachments[a].final_layout;
4409 VkImageLayout stencil_layout = state->pass->attachments[a].stencil_final_layout;
4410 struct radv_subpass_attachment att = { a, layout, stencil_layout };
4411 radv_handle_subpass_image_transition(cmd_buffer, att, false);
4412 }
4413
4414 radv_describe_barrier_end(cmd_buffer);
4415 }
4416
4417 void
4418 radv_cmd_buffer_begin_render_pass(struct radv_cmd_buffer *cmd_buffer,
4419 const VkRenderPassBeginInfo *pRenderPassBegin)
4420 {
4421 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
4422 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
4423 VkResult result;
4424
4425 cmd_buffer->state.framebuffer = framebuffer;
4426 cmd_buffer->state.pass = pass;
4427 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
4428
4429 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
4430 if (result != VK_SUCCESS)
4431 return;
4432
4433 result = radv_cmd_state_setup_sample_locations(cmd_buffer, pass, pRenderPassBegin);
4434 if (result != VK_SUCCESS)
4435 return;
4436 }
4437
4438 void radv_CmdBeginRenderPass(
4439 VkCommandBuffer commandBuffer,
4440 const VkRenderPassBeginInfo* pRenderPassBegin,
4441 VkSubpassContents contents)
4442 {
4443 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4444
4445 radv_cmd_buffer_begin_render_pass(cmd_buffer, pRenderPassBegin);
4446
4447 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
4448 }
4449
4450 void radv_CmdBeginRenderPass2(
4451 VkCommandBuffer commandBuffer,
4452 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
4453 const VkSubpassBeginInfo* pSubpassBeginInfo)
4454 {
4455 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
4456 pSubpassBeginInfo->contents);
4457 }
4458
4459 void radv_CmdNextSubpass(
4460 VkCommandBuffer commandBuffer,
4461 VkSubpassContents contents)
4462 {
4463 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4464
4465 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
4466 radv_cmd_buffer_end_subpass(cmd_buffer);
4467 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
4468 }
4469
4470 void radv_CmdNextSubpass2(
4471 VkCommandBuffer commandBuffer,
4472 const VkSubpassBeginInfo* pSubpassBeginInfo,
4473 const VkSubpassEndInfo* pSubpassEndInfo)
4474 {
4475 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
4476 }
4477
4478 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
4479 {
4480 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
4481 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
4482 if (!radv_get_shader(pipeline, stage))
4483 continue;
4484
4485 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
4486 if (loc->sgpr_idx == -1)
4487 continue;
4488 uint32_t base_reg = pipeline->user_data_0[stage];
4489 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4490
4491 }
4492 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
4493 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
4494 if (loc->sgpr_idx != -1) {
4495 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
4496 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4497 }
4498 }
4499 }
4500
4501 static void
4502 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4503 uint32_t vertex_count,
4504 bool use_opaque)
4505 {
4506 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
4507 radeon_emit(cmd_buffer->cs, vertex_count);
4508 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
4509 S_0287F0_USE_OPAQUE(use_opaque));
4510 }
4511
4512 static void
4513 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
4514 uint64_t index_va,
4515 uint32_t index_count)
4516 {
4517 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
4518 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
4519 radeon_emit(cmd_buffer->cs, index_va);
4520 radeon_emit(cmd_buffer->cs, index_va >> 32);
4521 radeon_emit(cmd_buffer->cs, index_count);
4522 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
4523 }
4524
4525 static void
4526 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4527 bool indexed,
4528 uint32_t draw_count,
4529 uint64_t count_va,
4530 uint32_t stride)
4531 {
4532 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4533 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
4534 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
4535 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id;
4536 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
4537 bool predicating = cmd_buffer->state.predicating;
4538 assert(base_reg);
4539
4540 /* just reset draw state for vertex data */
4541 cmd_buffer->state.last_first_instance = -1;
4542 cmd_buffer->state.last_num_instances = -1;
4543 cmd_buffer->state.last_vertex_offset = -1;
4544
4545 if (draw_count == 1 && !count_va && !draw_id_enable) {
4546 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
4547 PKT3_DRAW_INDIRECT, 3, predicating));
4548 radeon_emit(cs, 0);
4549 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4550 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4551 radeon_emit(cs, di_src_sel);
4552 } else {
4553 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
4554 PKT3_DRAW_INDIRECT_MULTI,
4555 8, predicating));
4556 radeon_emit(cs, 0);
4557 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4558 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4559 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
4560 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
4561 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
4562 radeon_emit(cs, draw_count); /* count */
4563 radeon_emit(cs, count_va); /* count_addr */
4564 radeon_emit(cs, count_va >> 32);
4565 radeon_emit(cs, stride); /* stride */
4566 radeon_emit(cs, di_src_sel);
4567 }
4568 }
4569
4570 static void
4571 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
4572 const struct radv_draw_info *info)
4573 {
4574 struct radv_cmd_state *state = &cmd_buffer->state;
4575 struct radeon_winsys *ws = cmd_buffer->device->ws;
4576 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4577
4578 if (info->indirect) {
4579 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4580 uint64_t count_va = 0;
4581
4582 va += info->indirect->offset + info->indirect_offset;
4583
4584 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4585
4586 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
4587 radeon_emit(cs, 1);
4588 radeon_emit(cs, va);
4589 radeon_emit(cs, va >> 32);
4590
4591 if (info->count_buffer) {
4592 count_va = radv_buffer_get_va(info->count_buffer->bo);
4593 count_va += info->count_buffer->offset +
4594 info->count_buffer_offset;
4595
4596 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
4597 }
4598
4599 if (!state->subpass->view_mask) {
4600 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4601 info->indexed,
4602 info->count,
4603 count_va,
4604 info->stride);
4605 } else {
4606 unsigned i;
4607 for_each_bit(i, state->subpass->view_mask) {
4608 radv_emit_view_index(cmd_buffer, i);
4609
4610 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4611 info->indexed,
4612 info->count,
4613 count_va,
4614 info->stride);
4615 }
4616 }
4617 } else {
4618 assert(state->pipeline->graphics.vtx_base_sgpr);
4619
4620 if (info->vertex_offset != state->last_vertex_offset ||
4621 info->first_instance != state->last_first_instance) {
4622 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
4623 state->pipeline->graphics.vtx_emit_num);
4624
4625 radeon_emit(cs, info->vertex_offset);
4626 radeon_emit(cs, info->first_instance);
4627 if (state->pipeline->graphics.vtx_emit_num == 3)
4628 radeon_emit(cs, 0);
4629 state->last_first_instance = info->first_instance;
4630 state->last_vertex_offset = info->vertex_offset;
4631 }
4632
4633 if (state->last_num_instances != info->instance_count) {
4634 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
4635 radeon_emit(cs, info->instance_count);
4636 state->last_num_instances = info->instance_count;
4637 }
4638
4639 if (info->indexed) {
4640 int index_size = radv_get_vgt_index_size(state->index_type);
4641 uint64_t index_va;
4642
4643 /* Skip draw calls with 0-sized index buffers. They
4644 * cause a hang on some chips, like Navi10-14.
4645 */
4646 if (!cmd_buffer->state.max_index_count)
4647 return;
4648
4649 index_va = state->index_va;
4650 index_va += info->first_index * index_size;
4651
4652 if (!state->subpass->view_mask) {
4653 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4654 index_va,
4655 info->count);
4656 } else {
4657 unsigned i;
4658 for_each_bit(i, state->subpass->view_mask) {
4659 radv_emit_view_index(cmd_buffer, i);
4660
4661 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4662 index_va,
4663 info->count);
4664 }
4665 }
4666 } else {
4667 if (!state->subpass->view_mask) {
4668 radv_cs_emit_draw_packet(cmd_buffer,
4669 info->count,
4670 !!info->strmout_buffer);
4671 } else {
4672 unsigned i;
4673 for_each_bit(i, state->subpass->view_mask) {
4674 radv_emit_view_index(cmd_buffer, i);
4675
4676 radv_cs_emit_draw_packet(cmd_buffer,
4677 info->count,
4678 !!info->strmout_buffer);
4679 }
4680 }
4681 }
4682 }
4683 }
4684
4685 /*
4686 * Vega and raven have a bug which triggers if there are multiple context
4687 * register contexts active at the same time with different scissor values.
4688 *
4689 * There are two possible workarounds:
4690 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
4691 * there is only ever 1 active set of scissor values at the same time.
4692 *
4693 * 2) Whenever the hardware switches contexts we have to set the scissor
4694 * registers again even if it is a noop. That way the new context gets
4695 * the correct scissor values.
4696 *
4697 * This implements option 2. radv_need_late_scissor_emission needs to
4698 * return true on affected HW if radv_emit_all_graphics_states sets
4699 * any context registers.
4700 */
4701 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
4702 const struct radv_draw_info *info)
4703 {
4704 struct radv_cmd_state *state = &cmd_buffer->state;
4705
4706 if (!cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
4707 return false;
4708
4709 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
4710 return true;
4711
4712 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
4713
4714 /* Index, vertex and streamout buffers don't change context regs, and
4715 * pipeline is already handled.
4716 */
4717 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
4718 RADV_CMD_DIRTY_VERTEX_BUFFER |
4719 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
4720 RADV_CMD_DIRTY_PIPELINE);
4721
4722 if (cmd_buffer->state.dirty & used_states)
4723 return true;
4724
4725 uint32_t primitive_reset_index =
4726 radv_get_primitive_reset_index(cmd_buffer);
4727
4728 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
4729 primitive_reset_index != state->last_primitive_reset_index)
4730 return true;
4731
4732 return false;
4733 }
4734
4735 static void
4736 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
4737 const struct radv_draw_info *info)
4738 {
4739 bool late_scissor_emission;
4740
4741 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
4742 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
4743 radv_emit_rbplus_state(cmd_buffer);
4744
4745 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
4746 radv_emit_graphics_pipeline(cmd_buffer);
4747
4748 /* This should be before the cmd_buffer->state.dirty is cleared
4749 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4750 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4751 late_scissor_emission =
4752 radv_need_late_scissor_emission(cmd_buffer, info);
4753
4754 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
4755 radv_emit_framebuffer_state(cmd_buffer);
4756
4757 if (info->indexed) {
4758 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
4759 radv_emit_index_buffer(cmd_buffer, info->indirect);
4760 } else {
4761 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4762 * so the state must be re-emitted before the next indexed
4763 * draw.
4764 */
4765 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
4766 cmd_buffer->state.last_index_type = -1;
4767 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
4768 }
4769 }
4770
4771 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
4772
4773 radv_emit_draw_registers(cmd_buffer, info);
4774
4775 if (late_scissor_emission)
4776 radv_emit_scissor(cmd_buffer);
4777 }
4778
4779 static void
4780 radv_draw(struct radv_cmd_buffer *cmd_buffer,
4781 const struct radv_draw_info *info)
4782 {
4783 struct radeon_info *rad_info =
4784 &cmd_buffer->device->physical_device->rad_info;
4785 bool has_prefetch =
4786 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4787 bool pipeline_is_dirty =
4788 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
4789 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
4790
4791 ASSERTED unsigned cdw_max =
4792 radeon_check_space(cmd_buffer->device->ws,
4793 cmd_buffer->cs, 4096);
4794
4795 if (likely(!info->indirect)) {
4796 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4797 * no workaround for indirect draws, but we can at least skip
4798 * direct draws.
4799 */
4800 if (unlikely(!info->instance_count))
4801 return;
4802
4803 /* Handle count == 0. */
4804 if (unlikely(!info->count && !info->strmout_buffer))
4805 return;
4806 }
4807
4808 radv_describe_draw(cmd_buffer);
4809
4810 /* Use optimal packet order based on whether we need to sync the
4811 * pipeline.
4812 */
4813 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4814 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4815 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4816 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4817 /* If we have to wait for idle, set all states first, so that
4818 * all SET packets are processed in parallel with previous draw
4819 * calls. Then upload descriptors, set shader pointers, and
4820 * draw, and prefetch at the end. This ensures that the time
4821 * the CUs are idle is very short. (there are only SET_SH
4822 * packets between the wait and the draw)
4823 */
4824 radv_emit_all_graphics_states(cmd_buffer, info);
4825 si_emit_cache_flush(cmd_buffer);
4826 /* <-- CUs are idle here --> */
4827
4828 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4829
4830 radv_emit_draw_packets(cmd_buffer, info);
4831 /* <-- CUs are busy here --> */
4832
4833 /* Start prefetches after the draw has been started. Both will
4834 * run in parallel, but starting the draw first is more
4835 * important.
4836 */
4837 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4838 radv_emit_prefetch_L2(cmd_buffer,
4839 cmd_buffer->state.pipeline, false);
4840 }
4841 } else {
4842 /* If we don't wait for idle, start prefetches first, then set
4843 * states, and draw at the end.
4844 */
4845 si_emit_cache_flush(cmd_buffer);
4846
4847 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4848 /* Only prefetch the vertex shader and VBO descriptors
4849 * in order to start the draw as soon as possible.
4850 */
4851 radv_emit_prefetch_L2(cmd_buffer,
4852 cmd_buffer->state.pipeline, true);
4853 }
4854
4855 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4856
4857 radv_emit_all_graphics_states(cmd_buffer, info);
4858 radv_emit_draw_packets(cmd_buffer, info);
4859
4860 /* Prefetch the remaining shaders after the draw has been
4861 * started.
4862 */
4863 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4864 radv_emit_prefetch_L2(cmd_buffer,
4865 cmd_buffer->state.pipeline, false);
4866 }
4867 }
4868
4869 /* Workaround for a VGT hang when streamout is enabled.
4870 * It must be done after drawing.
4871 */
4872 if (cmd_buffer->state.streamout.streamout_enabled &&
4873 (rad_info->family == CHIP_HAWAII ||
4874 rad_info->family == CHIP_TONGA ||
4875 rad_info->family == CHIP_FIJI)) {
4876 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
4877 }
4878
4879 assert(cmd_buffer->cs->cdw <= cdw_max);
4880 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
4881 }
4882
4883 void radv_CmdDraw(
4884 VkCommandBuffer commandBuffer,
4885 uint32_t vertexCount,
4886 uint32_t instanceCount,
4887 uint32_t firstVertex,
4888 uint32_t firstInstance)
4889 {
4890 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4891 struct radv_draw_info info = {};
4892
4893 info.count = vertexCount;
4894 info.instance_count = instanceCount;
4895 info.first_instance = firstInstance;
4896 info.vertex_offset = firstVertex;
4897
4898 radv_draw(cmd_buffer, &info);
4899 }
4900
4901 void radv_CmdDrawIndexed(
4902 VkCommandBuffer commandBuffer,
4903 uint32_t indexCount,
4904 uint32_t instanceCount,
4905 uint32_t firstIndex,
4906 int32_t vertexOffset,
4907 uint32_t firstInstance)
4908 {
4909 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4910 struct radv_draw_info info = {};
4911
4912 info.indexed = true;
4913 info.count = indexCount;
4914 info.instance_count = instanceCount;
4915 info.first_index = firstIndex;
4916 info.vertex_offset = vertexOffset;
4917 info.first_instance = firstInstance;
4918
4919 radv_draw(cmd_buffer, &info);
4920 }
4921
4922 void radv_CmdDrawIndirect(
4923 VkCommandBuffer commandBuffer,
4924 VkBuffer _buffer,
4925 VkDeviceSize offset,
4926 uint32_t drawCount,
4927 uint32_t stride)
4928 {
4929 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4930 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4931 struct radv_draw_info info = {};
4932
4933 info.count = drawCount;
4934 info.indirect = buffer;
4935 info.indirect_offset = offset;
4936 info.stride = stride;
4937
4938 radv_draw(cmd_buffer, &info);
4939 }
4940
4941 void radv_CmdDrawIndexedIndirect(
4942 VkCommandBuffer commandBuffer,
4943 VkBuffer _buffer,
4944 VkDeviceSize offset,
4945 uint32_t drawCount,
4946 uint32_t stride)
4947 {
4948 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4949 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4950 struct radv_draw_info info = {};
4951
4952 info.indexed = true;
4953 info.count = drawCount;
4954 info.indirect = buffer;
4955 info.indirect_offset = offset;
4956 info.stride = stride;
4957
4958 radv_draw(cmd_buffer, &info);
4959 }
4960
4961 void radv_CmdDrawIndirectCount(
4962 VkCommandBuffer commandBuffer,
4963 VkBuffer _buffer,
4964 VkDeviceSize offset,
4965 VkBuffer _countBuffer,
4966 VkDeviceSize countBufferOffset,
4967 uint32_t maxDrawCount,
4968 uint32_t stride)
4969 {
4970 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4971 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4972 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4973 struct radv_draw_info info = {};
4974
4975 info.count = maxDrawCount;
4976 info.indirect = buffer;
4977 info.indirect_offset = offset;
4978 info.count_buffer = count_buffer;
4979 info.count_buffer_offset = countBufferOffset;
4980 info.stride = stride;
4981
4982 radv_draw(cmd_buffer, &info);
4983 }
4984
4985 void radv_CmdDrawIndexedIndirectCount(
4986 VkCommandBuffer commandBuffer,
4987 VkBuffer _buffer,
4988 VkDeviceSize offset,
4989 VkBuffer _countBuffer,
4990 VkDeviceSize countBufferOffset,
4991 uint32_t maxDrawCount,
4992 uint32_t stride)
4993 {
4994 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4995 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4996 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4997 struct radv_draw_info info = {};
4998
4999 info.indexed = true;
5000 info.count = maxDrawCount;
5001 info.indirect = buffer;
5002 info.indirect_offset = offset;
5003 info.count_buffer = count_buffer;
5004 info.count_buffer_offset = countBufferOffset;
5005 info.stride = stride;
5006
5007 radv_draw(cmd_buffer, &info);
5008 }
5009
5010 struct radv_dispatch_info {
5011 /**
5012 * Determine the layout of the grid (in block units) to be used.
5013 */
5014 uint32_t blocks[3];
5015
5016 /**
5017 * A starting offset for the grid. If unaligned is set, the offset
5018 * must still be aligned.
5019 */
5020 uint32_t offsets[3];
5021 /**
5022 * Whether it's an unaligned compute dispatch.
5023 */
5024 bool unaligned;
5025
5026 /**
5027 * Indirect compute parameters resource.
5028 */
5029 struct radv_buffer *indirect;
5030 uint64_t indirect_offset;
5031 };
5032
5033 static void
5034 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
5035 const struct radv_dispatch_info *info)
5036 {
5037 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
5038 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
5039 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
5040 struct radeon_winsys *ws = cmd_buffer->device->ws;
5041 bool predicating = cmd_buffer->state.predicating;
5042 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5043 struct radv_userdata_info *loc;
5044
5045 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
5046 AC_UD_CS_GRID_SIZE);
5047
5048 ASSERTED unsigned cdw_max = radeon_check_space(ws, cs, 25);
5049
5050 if (compute_shader->info.wave_size == 32) {
5051 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
5052 dispatch_initiator |= S_00B800_CS_W32_EN(1);
5053 }
5054
5055 if (info->indirect) {
5056 uint64_t va = radv_buffer_get_va(info->indirect->bo);
5057
5058 va += info->indirect->offset + info->indirect_offset;
5059
5060 radv_cs_add_buffer(ws, cs, info->indirect->bo);
5061
5062 if (loc->sgpr_idx != -1) {
5063 for (unsigned i = 0; i < 3; ++i) {
5064 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5065 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5066 COPY_DATA_DST_SEL(COPY_DATA_REG));
5067 radeon_emit(cs, (va + 4 * i));
5068 radeon_emit(cs, (va + 4 * i) >> 32);
5069 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
5070 + loc->sgpr_idx * 4) >> 2) + i);
5071 radeon_emit(cs, 0);
5072 }
5073 }
5074
5075 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
5076 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
5077 PKT3_SHADER_TYPE_S(1));
5078 radeon_emit(cs, va);
5079 radeon_emit(cs, va >> 32);
5080 radeon_emit(cs, dispatch_initiator);
5081 } else {
5082 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
5083 PKT3_SHADER_TYPE_S(1));
5084 radeon_emit(cs, 1);
5085 radeon_emit(cs, va);
5086 radeon_emit(cs, va >> 32);
5087
5088 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
5089 PKT3_SHADER_TYPE_S(1));
5090 radeon_emit(cs, 0);
5091 radeon_emit(cs, dispatch_initiator);
5092 }
5093 } else {
5094 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
5095 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
5096
5097 if (info->unaligned) {
5098 unsigned *cs_block_size = compute_shader->info.cs.block_size;
5099 unsigned remainder[3];
5100
5101 /* If aligned, these should be an entire block size,
5102 * not 0.
5103 */
5104 remainder[0] = blocks[0] + cs_block_size[0] -
5105 align_u32_npot(blocks[0], cs_block_size[0]);
5106 remainder[1] = blocks[1] + cs_block_size[1] -
5107 align_u32_npot(blocks[1], cs_block_size[1]);
5108 remainder[2] = blocks[2] + cs_block_size[2] -
5109 align_u32_npot(blocks[2], cs_block_size[2]);
5110
5111 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
5112 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
5113 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
5114
5115 for(unsigned i = 0; i < 3; ++i) {
5116 assert(offsets[i] % cs_block_size[i] == 0);
5117 offsets[i] /= cs_block_size[i];
5118 }
5119
5120 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
5121 radeon_emit(cs,
5122 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
5123 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
5124 radeon_emit(cs,
5125 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
5126 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
5127 radeon_emit(cs,
5128 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
5129 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
5130
5131 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
5132 }
5133
5134 if (loc->sgpr_idx != -1) {
5135 assert(loc->num_sgprs == 3);
5136
5137 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
5138 loc->sgpr_idx * 4, 3);
5139 radeon_emit(cs, blocks[0]);
5140 radeon_emit(cs, blocks[1]);
5141 radeon_emit(cs, blocks[2]);
5142 }
5143
5144 if (offsets[0] || offsets[1] || offsets[2]) {
5145 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
5146 radeon_emit(cs, offsets[0]);
5147 radeon_emit(cs, offsets[1]);
5148 radeon_emit(cs, offsets[2]);
5149
5150 /* The blocks in the packet are not counts but end values. */
5151 for (unsigned i = 0; i < 3; ++i)
5152 blocks[i] += offsets[i];
5153 } else {
5154 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
5155 }
5156
5157 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
5158 PKT3_SHADER_TYPE_S(1));
5159 radeon_emit(cs, blocks[0]);
5160 radeon_emit(cs, blocks[1]);
5161 radeon_emit(cs, blocks[2]);
5162 radeon_emit(cs, dispatch_initiator);
5163 }
5164
5165 assert(cmd_buffer->cs->cdw <= cdw_max);
5166 }
5167
5168 static void
5169 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
5170 {
5171 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
5172 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
5173 }
5174
5175 static void
5176 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
5177 const struct radv_dispatch_info *info)
5178 {
5179 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
5180 bool has_prefetch =
5181 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
5182 bool pipeline_is_dirty = pipeline &&
5183 pipeline != cmd_buffer->state.emitted_compute_pipeline;
5184
5185 radv_describe_dispatch(cmd_buffer, 8, 8, 8);
5186
5187 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5188 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5189 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
5190 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
5191 /* If we have to wait for idle, set all states first, so that
5192 * all SET packets are processed in parallel with previous draw
5193 * calls. Then upload descriptors, set shader pointers, and
5194 * dispatch, and prefetch at the end. This ensures that the
5195 * time the CUs are idle is very short. (there are only SET_SH
5196 * packets between the wait and the draw)
5197 */
5198 radv_emit_compute_pipeline(cmd_buffer);
5199 si_emit_cache_flush(cmd_buffer);
5200 /* <-- CUs are idle here --> */
5201
5202 radv_upload_compute_shader_descriptors(cmd_buffer);
5203
5204 radv_emit_dispatch_packets(cmd_buffer, info);
5205 /* <-- CUs are busy here --> */
5206
5207 /* Start prefetches after the dispatch has been started. Both
5208 * will run in parallel, but starting the dispatch first is
5209 * more important.
5210 */
5211 if (has_prefetch && pipeline_is_dirty) {
5212 radv_emit_shader_prefetch(cmd_buffer,
5213 pipeline->shaders[MESA_SHADER_COMPUTE]);
5214 }
5215 } else {
5216 /* If we don't wait for idle, start prefetches first, then set
5217 * states, and dispatch at the end.
5218 */
5219 si_emit_cache_flush(cmd_buffer);
5220
5221 if (has_prefetch && pipeline_is_dirty) {
5222 radv_emit_shader_prefetch(cmd_buffer,
5223 pipeline->shaders[MESA_SHADER_COMPUTE]);
5224 }
5225
5226 radv_upload_compute_shader_descriptors(cmd_buffer);
5227
5228 radv_emit_compute_pipeline(cmd_buffer);
5229 radv_emit_dispatch_packets(cmd_buffer, info);
5230 }
5231
5232 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
5233 }
5234
5235 void radv_CmdDispatchBase(
5236 VkCommandBuffer commandBuffer,
5237 uint32_t base_x,
5238 uint32_t base_y,
5239 uint32_t base_z,
5240 uint32_t x,
5241 uint32_t y,
5242 uint32_t z)
5243 {
5244 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5245 struct radv_dispatch_info info = {};
5246
5247 info.blocks[0] = x;
5248 info.blocks[1] = y;
5249 info.blocks[2] = z;
5250
5251 info.offsets[0] = base_x;
5252 info.offsets[1] = base_y;
5253 info.offsets[2] = base_z;
5254 radv_dispatch(cmd_buffer, &info);
5255 }
5256
5257 void radv_CmdDispatch(
5258 VkCommandBuffer commandBuffer,
5259 uint32_t x,
5260 uint32_t y,
5261 uint32_t z)
5262 {
5263 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
5264 }
5265
5266 void radv_CmdDispatchIndirect(
5267 VkCommandBuffer commandBuffer,
5268 VkBuffer _buffer,
5269 VkDeviceSize offset)
5270 {
5271 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5272 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5273 struct radv_dispatch_info info = {};
5274
5275 info.indirect = buffer;
5276 info.indirect_offset = offset;
5277
5278 radv_dispatch(cmd_buffer, &info);
5279 }
5280
5281 void radv_unaligned_dispatch(
5282 struct radv_cmd_buffer *cmd_buffer,
5283 uint32_t x,
5284 uint32_t y,
5285 uint32_t z)
5286 {
5287 struct radv_dispatch_info info = {};
5288
5289 info.blocks[0] = x;
5290 info.blocks[1] = y;
5291 info.blocks[2] = z;
5292 info.unaligned = 1;
5293
5294 radv_dispatch(cmd_buffer, &info);
5295 }
5296
5297 void
5298 radv_cmd_buffer_end_render_pass(struct radv_cmd_buffer *cmd_buffer)
5299 {
5300 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
5301 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
5302
5303 cmd_buffer->state.pass = NULL;
5304 cmd_buffer->state.subpass = NULL;
5305 cmd_buffer->state.attachments = NULL;
5306 cmd_buffer->state.framebuffer = NULL;
5307 cmd_buffer->state.subpass_sample_locs = NULL;
5308 }
5309
5310 void radv_CmdEndRenderPass(
5311 VkCommandBuffer commandBuffer)
5312 {
5313 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5314
5315 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
5316
5317 radv_cmd_buffer_end_subpass(cmd_buffer);
5318
5319 radv_cmd_buffer_end_render_pass(cmd_buffer);
5320 }
5321
5322 void radv_CmdEndRenderPass2(
5323 VkCommandBuffer commandBuffer,
5324 const VkSubpassEndInfo* pSubpassEndInfo)
5325 {
5326 radv_CmdEndRenderPass(commandBuffer);
5327 }
5328
5329 /*
5330 * For HTILE we have the following interesting clear words:
5331 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
5332 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
5333 * 0xfffffff0: Clear depth to 1.0
5334 * 0x00000000: Clear depth to 0.0
5335 */
5336 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
5337 struct radv_image *image,
5338 const VkImageSubresourceRange *range)
5339 {
5340 assert(range->baseMipLevel == 0);
5341 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
5342 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
5343 struct radv_cmd_state *state = &cmd_buffer->state;
5344 uint32_t htile_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
5345 VkClearDepthStencilValue value = {};
5346 struct radv_barrier_data barrier = {};
5347
5348 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5349 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5350
5351 barrier.layout_transitions.init_mask_ram = 1;
5352 radv_describe_layout_transition(cmd_buffer, &barrier);
5353
5354 state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, htile_value);
5355
5356 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5357
5358 if (vk_format_is_stencil(image->vk_format))
5359 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
5360
5361 radv_set_ds_clear_metadata(cmd_buffer, image, range, value, aspects);
5362
5363 if (radv_image_is_tc_compat_htile(image)) {
5364 /* Initialize the TC-compat metada value to 0 because by
5365 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
5366 * need have to conditionally update its value when performing
5367 * a fast depth clear.
5368 */
5369 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, range, 0);
5370 }
5371 }
5372
5373 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
5374 struct radv_image *image,
5375 VkImageLayout src_layout,
5376 bool src_render_loop,
5377 VkImageLayout dst_layout,
5378 bool dst_render_loop,
5379 unsigned src_queue_mask,
5380 unsigned dst_queue_mask,
5381 const VkImageSubresourceRange *range,
5382 struct radv_sample_locations_state *sample_locs)
5383 {
5384 if (!radv_image_has_htile(image))
5385 return;
5386
5387 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5388 radv_initialize_htile(cmd_buffer, image, range);
5389 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5390 radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5391 radv_initialize_htile(cmd_buffer, image, range);
5392 } else if (radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5393 !radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5394 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5395 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5396
5397 radv_decompress_depth_stencil(cmd_buffer, image, range,
5398 sample_locs);
5399
5400 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5401 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5402 }
5403 }
5404
5405 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
5406 struct radv_image *image,
5407 const VkImageSubresourceRange *range,
5408 uint32_t value)
5409 {
5410 struct radv_cmd_state *state = &cmd_buffer->state;
5411 struct radv_barrier_data barrier = {};
5412
5413 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5414 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5415
5416 barrier.layout_transitions.init_mask_ram = 1;
5417 radv_describe_layout_transition(cmd_buffer, &barrier);
5418
5419 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, range, value);
5420
5421 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5422 }
5423
5424 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
5425 struct radv_image *image,
5426 const VkImageSubresourceRange *range)
5427 {
5428 struct radv_cmd_state *state = &cmd_buffer->state;
5429 static const uint32_t fmask_clear_values[4] = {
5430 0x00000000,
5431 0x02020202,
5432 0xE4E4E4E4,
5433 0x76543210
5434 };
5435 uint32_t log2_samples = util_logbase2(image->info.samples);
5436 uint32_t value = fmask_clear_values[log2_samples];
5437 struct radv_barrier_data barrier = {};
5438
5439 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5440 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5441
5442 barrier.layout_transitions.init_mask_ram = 1;
5443 radv_describe_layout_transition(cmd_buffer, &barrier);
5444
5445 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, range, value);
5446
5447 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5448 }
5449
5450 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
5451 struct radv_image *image,
5452 const VkImageSubresourceRange *range, uint32_t value)
5453 {
5454 struct radv_cmd_state *state = &cmd_buffer->state;
5455 struct radv_barrier_data barrier = {};
5456 unsigned size = 0;
5457
5458 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5459 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5460
5461 barrier.layout_transitions.init_mask_ram = 1;
5462 radv_describe_layout_transition(cmd_buffer, &barrier);
5463
5464 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
5465
5466 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) {
5467 /* When DCC is enabled with mipmaps, some levels might not
5468 * support fast clears and we have to initialize them as "fully
5469 * expanded".
5470 */
5471 /* Compute the size of all fast clearable DCC levels. */
5472 for (unsigned i = 0; i < image->planes[0].surface.num_dcc_levels; i++) {
5473 struct legacy_surf_level *surf_level =
5474 &image->planes[0].surface.u.legacy.level[i];
5475 unsigned dcc_fast_clear_size =
5476 surf_level->dcc_slice_fast_clear_size * image->info.array_size;
5477
5478 if (!dcc_fast_clear_size)
5479 break;
5480
5481 size = surf_level->dcc_offset + dcc_fast_clear_size;
5482 }
5483
5484 /* Initialize the mipmap levels without DCC. */
5485 if (size != image->planes[0].surface.dcc_size) {
5486 state->flush_bits |=
5487 radv_fill_buffer(cmd_buffer, image->bo,
5488 image->offset + image->planes[0].surface.dcc_offset + size,
5489 image->planes[0].surface.dcc_size - size,
5490 0xffffffff);
5491 }
5492 }
5493
5494 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5495 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5496 }
5497
5498 /**
5499 * Initialize DCC/FMASK/CMASK metadata for a color image.
5500 */
5501 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
5502 struct radv_image *image,
5503 VkImageLayout src_layout,
5504 bool src_render_loop,
5505 VkImageLayout dst_layout,
5506 bool dst_render_loop,
5507 unsigned src_queue_mask,
5508 unsigned dst_queue_mask,
5509 const VkImageSubresourceRange *range)
5510 {
5511 if (radv_image_has_cmask(image)) {
5512 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5513
5514 /* TODO: clarify this. */
5515 if (radv_image_has_fmask(image)) {
5516 value = 0xccccccccu;
5517 }
5518
5519 radv_initialise_cmask(cmd_buffer, image, range, value);
5520 }
5521
5522 if (radv_image_has_fmask(image)) {
5523 radv_initialize_fmask(cmd_buffer, image, range);
5524 }
5525
5526 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5527 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5528 bool need_decompress_pass = false;
5529
5530 if (radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout,
5531 dst_render_loop,
5532 dst_queue_mask)) {
5533 value = 0x20202020u;
5534 need_decompress_pass = true;
5535 }
5536
5537 radv_initialize_dcc(cmd_buffer, image, range, value);
5538
5539 radv_update_fce_metadata(cmd_buffer, image, range,
5540 need_decompress_pass);
5541 }
5542
5543 if (radv_image_has_cmask(image) ||
5544 radv_dcc_enabled(image, range->baseMipLevel)) {
5545 uint32_t color_values[2] = {};
5546 radv_set_color_clear_metadata(cmd_buffer, image, range,
5547 color_values);
5548 }
5549 }
5550
5551 /**
5552 * Handle color image transitions for DCC/FMASK/CMASK.
5553 */
5554 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
5555 struct radv_image *image,
5556 VkImageLayout src_layout,
5557 bool src_render_loop,
5558 VkImageLayout dst_layout,
5559 bool dst_render_loop,
5560 unsigned src_queue_mask,
5561 unsigned dst_queue_mask,
5562 const VkImageSubresourceRange *range)
5563 {
5564 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5565 radv_init_color_image_metadata(cmd_buffer, image,
5566 src_layout, src_render_loop,
5567 dst_layout, dst_render_loop,
5568 src_queue_mask, dst_queue_mask,
5569 range);
5570 return;
5571 }
5572
5573 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5574 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
5575 radv_initialize_dcc(cmd_buffer, image, range, 0xffffffffu);
5576 } else if (radv_layout_dcc_compressed(cmd_buffer->device, image, src_layout, src_render_loop, src_queue_mask) &&
5577 !radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout, dst_render_loop, dst_queue_mask)) {
5578 radv_decompress_dcc(cmd_buffer, image, range);
5579 } else if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
5580 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5581 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5582 }
5583 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
5584 bool fce_eliminate = false, fmask_expand = false;
5585
5586 if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
5587 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5588 fce_eliminate = true;
5589 }
5590
5591 if (radv_image_has_fmask(image)) {
5592 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
5593 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
5594 /* A FMASK decompress is required before doing
5595 * a MSAA decompress using FMASK.
5596 */
5597 fmask_expand = true;
5598 }
5599 }
5600
5601 if (fce_eliminate || fmask_expand)
5602 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5603
5604 if (fmask_expand) {
5605 struct radv_barrier_data barrier = {};
5606 barrier.layout_transitions.fmask_color_expand = 1;
5607 radv_describe_layout_transition(cmd_buffer, &barrier);
5608
5609 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
5610 }
5611 }
5612 }
5613
5614 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
5615 struct radv_image *image,
5616 VkImageLayout src_layout,
5617 bool src_render_loop,
5618 VkImageLayout dst_layout,
5619 bool dst_render_loop,
5620 uint32_t src_family,
5621 uint32_t dst_family,
5622 const VkImageSubresourceRange *range,
5623 struct radv_sample_locations_state *sample_locs)
5624 {
5625 if (image->exclusive && src_family != dst_family) {
5626 /* This is an acquire or a release operation and there will be
5627 * a corresponding release/acquire. Do the transition in the
5628 * most flexible queue. */
5629
5630 assert(src_family == cmd_buffer->queue_family_index ||
5631 dst_family == cmd_buffer->queue_family_index);
5632
5633 if (src_family == VK_QUEUE_FAMILY_EXTERNAL ||
5634 src_family == VK_QUEUE_FAMILY_FOREIGN_EXT)
5635 return;
5636
5637 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
5638 return;
5639
5640 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
5641 (src_family == RADV_QUEUE_GENERAL ||
5642 dst_family == RADV_QUEUE_GENERAL))
5643 return;
5644 }
5645
5646 if (src_layout == dst_layout)
5647 return;
5648
5649 unsigned src_queue_mask =
5650 radv_image_queue_family_mask(image, src_family,
5651 cmd_buffer->queue_family_index);
5652 unsigned dst_queue_mask =
5653 radv_image_queue_family_mask(image, dst_family,
5654 cmd_buffer->queue_family_index);
5655
5656 if (vk_format_is_depth(image->vk_format)) {
5657 radv_handle_depth_image_transition(cmd_buffer, image,
5658 src_layout, src_render_loop,
5659 dst_layout, dst_render_loop,
5660 src_queue_mask, dst_queue_mask,
5661 range, sample_locs);
5662 } else {
5663 radv_handle_color_image_transition(cmd_buffer, image,
5664 src_layout, src_render_loop,
5665 dst_layout, dst_render_loop,
5666 src_queue_mask, dst_queue_mask,
5667 range);
5668 }
5669 }
5670
5671 struct radv_barrier_info {
5672 enum rgp_barrier_reason reason;
5673 uint32_t eventCount;
5674 const VkEvent *pEvents;
5675 VkPipelineStageFlags srcStageMask;
5676 VkPipelineStageFlags dstStageMask;
5677 };
5678
5679 static void
5680 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
5681 uint32_t memoryBarrierCount,
5682 const VkMemoryBarrier *pMemoryBarriers,
5683 uint32_t bufferMemoryBarrierCount,
5684 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
5685 uint32_t imageMemoryBarrierCount,
5686 const VkImageMemoryBarrier *pImageMemoryBarriers,
5687 const struct radv_barrier_info *info)
5688 {
5689 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5690 enum radv_cmd_flush_bits src_flush_bits = 0;
5691 enum radv_cmd_flush_bits dst_flush_bits = 0;
5692
5693 radv_describe_barrier_start(cmd_buffer, info->reason);
5694
5695 for (unsigned i = 0; i < info->eventCount; ++i) {
5696 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
5697 uint64_t va = radv_buffer_get_va(event->bo);
5698
5699 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5700
5701 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
5702
5703 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
5704 assert(cmd_buffer->cs->cdw <= cdw_max);
5705 }
5706
5707 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
5708 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
5709 NULL);
5710 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
5711 NULL);
5712 }
5713
5714 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
5715 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
5716 NULL);
5717 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
5718 NULL);
5719 }
5720
5721 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5722 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5723
5724 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
5725 image);
5726 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
5727 image);
5728 }
5729
5730 /* The Vulkan spec 1.1.98 says:
5731 *
5732 * "An execution dependency with only
5733 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
5734 * will only prevent that stage from executing in subsequently
5735 * submitted commands. As this stage does not perform any actual
5736 * execution, this is not observable - in effect, it does not delay
5737 * processing of subsequent commands. Similarly an execution dependency
5738 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
5739 * will effectively not wait for any prior commands to complete."
5740 */
5741 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
5742 radv_stage_flush(cmd_buffer, info->srcStageMask);
5743 cmd_buffer->state.flush_bits |= src_flush_bits;
5744
5745 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5746 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5747
5748 const struct VkSampleLocationsInfoEXT *sample_locs_info =
5749 vk_find_struct_const(pImageMemoryBarriers[i].pNext,
5750 SAMPLE_LOCATIONS_INFO_EXT);
5751 struct radv_sample_locations_state sample_locations = {};
5752
5753 if (sample_locs_info) {
5754 assert(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
5755 sample_locations.per_pixel = sample_locs_info->sampleLocationsPerPixel;
5756 sample_locations.grid_size = sample_locs_info->sampleLocationGridSize;
5757 sample_locations.count = sample_locs_info->sampleLocationsCount;
5758 typed_memcpy(&sample_locations.locations[0],
5759 sample_locs_info->pSampleLocations,
5760 sample_locs_info->sampleLocationsCount);
5761 }
5762
5763 radv_handle_image_transition(cmd_buffer, image,
5764 pImageMemoryBarriers[i].oldLayout,
5765 false, /* Outside of a renderpass we are never in a renderloop */
5766 pImageMemoryBarriers[i].newLayout,
5767 false, /* Outside of a renderpass we are never in a renderloop */
5768 pImageMemoryBarriers[i].srcQueueFamilyIndex,
5769 pImageMemoryBarriers[i].dstQueueFamilyIndex,
5770 &pImageMemoryBarriers[i].subresourceRange,
5771 sample_locs_info ? &sample_locations : NULL);
5772 }
5773
5774 /* Make sure CP DMA is idle because the driver might have performed a
5775 * DMA operation for copying or filling buffers/images.
5776 */
5777 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5778 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5779 si_cp_dma_wait_for_idle(cmd_buffer);
5780
5781 cmd_buffer->state.flush_bits |= dst_flush_bits;
5782
5783 radv_describe_barrier_end(cmd_buffer);
5784 }
5785
5786 void radv_CmdPipelineBarrier(
5787 VkCommandBuffer commandBuffer,
5788 VkPipelineStageFlags srcStageMask,
5789 VkPipelineStageFlags destStageMask,
5790 VkBool32 byRegion,
5791 uint32_t memoryBarrierCount,
5792 const VkMemoryBarrier* pMemoryBarriers,
5793 uint32_t bufferMemoryBarrierCount,
5794 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5795 uint32_t imageMemoryBarrierCount,
5796 const VkImageMemoryBarrier* pImageMemoryBarriers)
5797 {
5798 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5799 struct radv_barrier_info info;
5800
5801 info.reason = RGP_BARRIER_EXTERNAL_CMD_PIPELINE_BARRIER;
5802 info.eventCount = 0;
5803 info.pEvents = NULL;
5804 info.srcStageMask = srcStageMask;
5805 info.dstStageMask = destStageMask;
5806
5807 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5808 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5809 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5810 }
5811
5812
5813 static void write_event(struct radv_cmd_buffer *cmd_buffer,
5814 struct radv_event *event,
5815 VkPipelineStageFlags stageMask,
5816 unsigned value)
5817 {
5818 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5819 uint64_t va = radv_buffer_get_va(event->bo);
5820
5821 si_emit_cache_flush(cmd_buffer);
5822
5823 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5824
5825 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 21);
5826
5827 /* Flags that only require a top-of-pipe event. */
5828 VkPipelineStageFlags top_of_pipe_flags =
5829 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
5830
5831 /* Flags that only require a post-index-fetch event. */
5832 VkPipelineStageFlags post_index_fetch_flags =
5833 top_of_pipe_flags |
5834 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
5835 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
5836
5837 /* Make sure CP DMA is idle because the driver might have performed a
5838 * DMA operation for copying or filling buffers/images.
5839 */
5840 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5841 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5842 si_cp_dma_wait_for_idle(cmd_buffer);
5843
5844 /* TODO: Emit EOS events for syncing PS/CS stages. */
5845
5846 if (!(stageMask & ~top_of_pipe_flags)) {
5847 /* Just need to sync the PFP engine. */
5848 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5849 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5850 S_370_WR_CONFIRM(1) |
5851 S_370_ENGINE_SEL(V_370_PFP));
5852 radeon_emit(cs, va);
5853 radeon_emit(cs, va >> 32);
5854 radeon_emit(cs, value);
5855 } else if (!(stageMask & ~post_index_fetch_flags)) {
5856 /* Sync ME because PFP reads index and indirect buffers. */
5857 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5858 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5859 S_370_WR_CONFIRM(1) |
5860 S_370_ENGINE_SEL(V_370_ME));
5861 radeon_emit(cs, va);
5862 radeon_emit(cs, va >> 32);
5863 radeon_emit(cs, value);
5864 } else {
5865 /* Otherwise, sync all prior GPU work using an EOP event. */
5866 si_cs_emit_write_event_eop(cs,
5867 cmd_buffer->device->physical_device->rad_info.chip_class,
5868 radv_cmd_buffer_uses_mec(cmd_buffer),
5869 V_028A90_BOTTOM_OF_PIPE_TS, 0,
5870 EOP_DST_SEL_MEM,
5871 EOP_DATA_SEL_VALUE_32BIT, va, value,
5872 cmd_buffer->gfx9_eop_bug_va);
5873 }
5874
5875 assert(cmd_buffer->cs->cdw <= cdw_max);
5876 }
5877
5878 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
5879 VkEvent _event,
5880 VkPipelineStageFlags stageMask)
5881 {
5882 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5883 RADV_FROM_HANDLE(radv_event, event, _event);
5884
5885 write_event(cmd_buffer, event, stageMask, 1);
5886 }
5887
5888 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
5889 VkEvent _event,
5890 VkPipelineStageFlags stageMask)
5891 {
5892 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5893 RADV_FROM_HANDLE(radv_event, event, _event);
5894
5895 write_event(cmd_buffer, event, stageMask, 0);
5896 }
5897
5898 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
5899 uint32_t eventCount,
5900 const VkEvent* pEvents,
5901 VkPipelineStageFlags srcStageMask,
5902 VkPipelineStageFlags dstStageMask,
5903 uint32_t memoryBarrierCount,
5904 const VkMemoryBarrier* pMemoryBarriers,
5905 uint32_t bufferMemoryBarrierCount,
5906 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5907 uint32_t imageMemoryBarrierCount,
5908 const VkImageMemoryBarrier* pImageMemoryBarriers)
5909 {
5910 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5911 struct radv_barrier_info info;
5912
5913 info.reason = RGP_BARRIER_EXTERNAL_CMD_WAIT_EVENTS;
5914 info.eventCount = eventCount;
5915 info.pEvents = pEvents;
5916 info.srcStageMask = 0;
5917
5918 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5919 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5920 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5921 }
5922
5923
5924 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
5925 uint32_t deviceMask)
5926 {
5927 /* No-op */
5928 }
5929
5930 /* VK_EXT_conditional_rendering */
5931 void radv_CmdBeginConditionalRenderingEXT(
5932 VkCommandBuffer commandBuffer,
5933 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
5934 {
5935 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5936 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
5937 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5938 bool draw_visible = true;
5939 uint64_t pred_value = 0;
5940 uint64_t va, new_va;
5941 unsigned pred_offset;
5942
5943 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
5944
5945 /* By default, if the 32-bit value at offset in buffer memory is zero,
5946 * then the rendering commands are discarded, otherwise they are
5947 * executed as normal. If the inverted flag is set, all commands are
5948 * discarded if the value is non zero.
5949 */
5950 if (pConditionalRenderingBegin->flags &
5951 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
5952 draw_visible = false;
5953 }
5954
5955 si_emit_cache_flush(cmd_buffer);
5956
5957 /* From the Vulkan spec 1.1.107:
5958 *
5959 * "If the 32-bit value at offset in buffer memory is zero, then the
5960 * rendering commands are discarded, otherwise they are executed as
5961 * normal. If the value of the predicate in buffer memory changes while
5962 * conditional rendering is active, the rendering commands may be
5963 * discarded in an implementation-dependent way. Some implementations
5964 * may latch the value of the predicate upon beginning conditional
5965 * rendering while others may read it before every rendering command."
5966 *
5967 * But, the AMD hardware treats the predicate as a 64-bit value which
5968 * means we need a workaround in the driver. Luckily, it's not required
5969 * to support if the value changes when predication is active.
5970 *
5971 * The workaround is as follows:
5972 * 1) allocate a 64-value in the upload BO and initialize it to 0
5973 * 2) copy the 32-bit predicate value to the upload BO
5974 * 3) use the new allocated VA address for predication
5975 *
5976 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
5977 * in ME (+ sync PFP) instead of PFP.
5978 */
5979 radv_cmd_buffer_upload_data(cmd_buffer, 8, 16, &pred_value, &pred_offset);
5980
5981 new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
5982
5983 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5984 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5985 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
5986 COPY_DATA_WR_CONFIRM);
5987 radeon_emit(cs, va);
5988 radeon_emit(cs, va >> 32);
5989 radeon_emit(cs, new_va);
5990 radeon_emit(cs, new_va >> 32);
5991
5992 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
5993 radeon_emit(cs, 0);
5994
5995 /* Enable predication for this command buffer. */
5996 si_emit_set_predication_state(cmd_buffer, draw_visible, new_va);
5997 cmd_buffer->state.predicating = true;
5998
5999 /* Store conditional rendering user info. */
6000 cmd_buffer->state.predication_type = draw_visible;
6001 cmd_buffer->state.predication_va = new_va;
6002 }
6003
6004 void radv_CmdEndConditionalRenderingEXT(
6005 VkCommandBuffer commandBuffer)
6006 {
6007 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6008
6009 /* Disable predication for this command buffer. */
6010 si_emit_set_predication_state(cmd_buffer, false, 0);
6011 cmd_buffer->state.predicating = false;
6012
6013 /* Reset conditional rendering user info. */
6014 cmd_buffer->state.predication_type = -1;
6015 cmd_buffer->state.predication_va = 0;
6016 }
6017
6018 /* VK_EXT_transform_feedback */
6019 void radv_CmdBindTransformFeedbackBuffersEXT(
6020 VkCommandBuffer commandBuffer,
6021 uint32_t firstBinding,
6022 uint32_t bindingCount,
6023 const VkBuffer* pBuffers,
6024 const VkDeviceSize* pOffsets,
6025 const VkDeviceSize* pSizes)
6026 {
6027 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6028 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
6029 uint8_t enabled_mask = 0;
6030
6031 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
6032 for (uint32_t i = 0; i < bindingCount; i++) {
6033 uint32_t idx = firstBinding + i;
6034
6035 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
6036 sb[idx].offset = pOffsets[i];
6037
6038 if (!pSizes || pSizes[i] == VK_WHOLE_SIZE) {
6039 sb[idx].size = sb[idx].buffer->size - sb[idx].offset;
6040 } else {
6041 sb[idx].size = pSizes[i];
6042 }
6043
6044 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
6045 sb[idx].buffer->bo);
6046
6047 enabled_mask |= 1 << idx;
6048 }
6049
6050 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
6051
6052 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
6053 }
6054
6055 static void
6056 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
6057 {
6058 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6059 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6060
6061 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
6062 radeon_emit(cs,
6063 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
6064 S_028B94_RAST_STREAM(0) |
6065 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
6066 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
6067 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
6068 radeon_emit(cs, so->hw_enabled_mask &
6069 so->enabled_stream_buffers_mask);
6070
6071 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6072 }
6073
6074 static void
6075 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
6076 {
6077 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6078 bool old_streamout_enabled = so->streamout_enabled;
6079 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
6080
6081 so->streamout_enabled = enable;
6082
6083 so->hw_enabled_mask = so->enabled_mask |
6084 (so->enabled_mask << 4) |
6085 (so->enabled_mask << 8) |
6086 (so->enabled_mask << 12);
6087
6088 if (!cmd_buffer->device->physical_device->use_ngg_streamout &&
6089 ((old_streamout_enabled != so->streamout_enabled) ||
6090 (old_hw_enabled_mask != so->hw_enabled_mask)))
6091 radv_emit_streamout_enable(cmd_buffer);
6092
6093 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6094 cmd_buffer->gds_needed = true;
6095 cmd_buffer->gds_oa_needed = true;
6096 }
6097 }
6098
6099 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
6100 {
6101 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6102 unsigned reg_strmout_cntl;
6103
6104 /* The register is at different places on different ASICs. */
6105 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
6106 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
6107 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
6108 } else {
6109 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
6110 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
6111 }
6112
6113 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
6114 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
6115
6116 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
6117 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
6118 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
6119 radeon_emit(cs, 0);
6120 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
6121 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
6122 radeon_emit(cs, 4); /* poll interval */
6123 }
6124
6125 static void
6126 radv_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
6127 uint32_t firstCounterBuffer,
6128 uint32_t counterBufferCount,
6129 const VkBuffer *pCounterBuffers,
6130 const VkDeviceSize *pCounterBufferOffsets)
6131
6132 {
6133 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
6134 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6135 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6136 uint32_t i;
6137
6138 radv_flush_vgt_streamout(cmd_buffer);
6139
6140 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6141 for_each_bit(i, so->enabled_mask) {
6142 int32_t counter_buffer_idx = i - firstCounterBuffer;
6143 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6144 counter_buffer_idx = -1;
6145
6146 /* AMD GCN binds streamout buffers as shader resources.
6147 * VGT only counts primitives and tells the shader through
6148 * SGPRs what to do.
6149 */
6150 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
6151 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
6152 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
6153
6154 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6155
6156 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6157 /* The array of counter buffers is optional. */
6158 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6159 uint64_t va = radv_buffer_get_va(buffer->bo);
6160
6161 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6162
6163 /* Append */
6164 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6165 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6166 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6167 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
6168 radeon_emit(cs, 0); /* unused */
6169 radeon_emit(cs, 0); /* unused */
6170 radeon_emit(cs, va); /* src address lo */
6171 radeon_emit(cs, va >> 32); /* src address hi */
6172
6173 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6174 } else {
6175 /* Start from the beginning. */
6176 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6177 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6178 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6179 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
6180 radeon_emit(cs, 0); /* unused */
6181 radeon_emit(cs, 0); /* unused */
6182 radeon_emit(cs, 0); /* unused */
6183 radeon_emit(cs, 0); /* unused */
6184 }
6185 }
6186
6187 radv_set_streamout_enable(cmd_buffer, true);
6188 }
6189
6190 static void
6191 gfx10_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
6192 uint32_t firstCounterBuffer,
6193 uint32_t counterBufferCount,
6194 const VkBuffer *pCounterBuffers,
6195 const VkDeviceSize *pCounterBufferOffsets)
6196 {
6197 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6198 unsigned last_target = util_last_bit(so->enabled_mask) - 1;
6199 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6200 uint32_t i;
6201
6202 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6203 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6204
6205 /* Sync because the next streamout operation will overwrite GDS and we
6206 * have to make sure it's idle.
6207 * TODO: Improve by tracking if there is a streamout operation in
6208 * flight.
6209 */
6210 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
6211 si_emit_cache_flush(cmd_buffer);
6212
6213 for_each_bit(i, so->enabled_mask) {
6214 int32_t counter_buffer_idx = i - firstCounterBuffer;
6215 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6216 counter_buffer_idx = -1;
6217
6218 bool append = counter_buffer_idx >= 0 &&
6219 pCounterBuffers && pCounterBuffers[counter_buffer_idx];
6220 uint64_t va = 0;
6221
6222 if (append) {
6223 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6224
6225 va += radv_buffer_get_va(buffer->bo);
6226 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6227
6228 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6229 }
6230
6231 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
6232 radeon_emit(cs, S_411_SRC_SEL(append ? V_411_SRC_ADDR_TC_L2 : V_411_DATA) |
6233 S_411_DST_SEL(V_411_GDS) |
6234 S_411_CP_SYNC(i == last_target));
6235 radeon_emit(cs, va);
6236 radeon_emit(cs, va >> 32);
6237 radeon_emit(cs, 4 * i); /* destination in GDS */
6238 radeon_emit(cs, 0);
6239 radeon_emit(cs, S_414_BYTE_COUNT_GFX9(4) |
6240 S_414_DISABLE_WR_CONFIRM_GFX9(i != last_target));
6241 }
6242
6243 radv_set_streamout_enable(cmd_buffer, true);
6244 }
6245
6246 void radv_CmdBeginTransformFeedbackEXT(
6247 VkCommandBuffer commandBuffer,
6248 uint32_t firstCounterBuffer,
6249 uint32_t counterBufferCount,
6250 const VkBuffer* pCounterBuffers,
6251 const VkDeviceSize* pCounterBufferOffsets)
6252 {
6253 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6254
6255 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6256 gfx10_emit_streamout_begin(cmd_buffer,
6257 firstCounterBuffer, counterBufferCount,
6258 pCounterBuffers, pCounterBufferOffsets);
6259 } else {
6260 radv_emit_streamout_begin(cmd_buffer,
6261 firstCounterBuffer, counterBufferCount,
6262 pCounterBuffers, pCounterBufferOffsets);
6263 }
6264 }
6265
6266 static void
6267 radv_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6268 uint32_t firstCounterBuffer,
6269 uint32_t counterBufferCount,
6270 const VkBuffer *pCounterBuffers,
6271 const VkDeviceSize *pCounterBufferOffsets)
6272 {
6273 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6274 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6275 uint32_t i;
6276
6277 radv_flush_vgt_streamout(cmd_buffer);
6278
6279 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6280 for_each_bit(i, so->enabled_mask) {
6281 int32_t counter_buffer_idx = i - firstCounterBuffer;
6282 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6283 counter_buffer_idx = -1;
6284
6285 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6286 /* The array of counters buffer is optional. */
6287 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6288 uint64_t va = radv_buffer_get_va(buffer->bo);
6289
6290 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6291
6292 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6293 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6294 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6295 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
6296 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
6297 radeon_emit(cs, va); /* dst address lo */
6298 radeon_emit(cs, va >> 32); /* dst address hi */
6299 radeon_emit(cs, 0); /* unused */
6300 radeon_emit(cs, 0); /* unused */
6301
6302 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6303 }
6304
6305 /* Deactivate transform feedback by zeroing the buffer size.
6306 * The counters (primitives generated, primitives emitted) may
6307 * be enabled even if there is not buffer bound. This ensures
6308 * that the primitives-emitted query won't increment.
6309 */
6310 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
6311
6312 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6313 }
6314
6315 radv_set_streamout_enable(cmd_buffer, false);
6316 }
6317
6318 static void
6319 gfx10_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6320 uint32_t firstCounterBuffer,
6321 uint32_t counterBufferCount,
6322 const VkBuffer *pCounterBuffers,
6323 const VkDeviceSize *pCounterBufferOffsets)
6324 {
6325 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6326 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6327 uint32_t i;
6328
6329 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6330 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6331
6332 for_each_bit(i, so->enabled_mask) {
6333 int32_t counter_buffer_idx = i - firstCounterBuffer;
6334 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6335 counter_buffer_idx = -1;
6336
6337 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6338 /* The array of counters buffer is optional. */
6339 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6340 uint64_t va = radv_buffer_get_va(buffer->bo);
6341
6342 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6343
6344 si_cs_emit_write_event_eop(cs,
6345 cmd_buffer->device->physical_device->rad_info.chip_class,
6346 radv_cmd_buffer_uses_mec(cmd_buffer),
6347 V_028A90_PS_DONE, 0,
6348 EOP_DST_SEL_TC_L2,
6349 EOP_DATA_SEL_GDS,
6350 va, EOP_DATA_GDS(i, 1), 0);
6351
6352 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6353 }
6354 }
6355
6356 radv_set_streamout_enable(cmd_buffer, false);
6357 }
6358
6359 void radv_CmdEndTransformFeedbackEXT(
6360 VkCommandBuffer commandBuffer,
6361 uint32_t firstCounterBuffer,
6362 uint32_t counterBufferCount,
6363 const VkBuffer* pCounterBuffers,
6364 const VkDeviceSize* pCounterBufferOffsets)
6365 {
6366 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6367
6368 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6369 gfx10_emit_streamout_end(cmd_buffer,
6370 firstCounterBuffer, counterBufferCount,
6371 pCounterBuffers, pCounterBufferOffsets);
6372 } else {
6373 radv_emit_streamout_end(cmd_buffer,
6374 firstCounterBuffer, counterBufferCount,
6375 pCounterBuffers, pCounterBufferOffsets);
6376 }
6377 }
6378
6379 void radv_CmdDrawIndirectByteCountEXT(
6380 VkCommandBuffer commandBuffer,
6381 uint32_t instanceCount,
6382 uint32_t firstInstance,
6383 VkBuffer _counterBuffer,
6384 VkDeviceSize counterBufferOffset,
6385 uint32_t counterOffset,
6386 uint32_t vertexStride)
6387 {
6388 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6389 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
6390 struct radv_draw_info info = {};
6391
6392 info.instance_count = instanceCount;
6393 info.first_instance = firstInstance;
6394 info.strmout_buffer = counterBuffer;
6395 info.strmout_buffer_offset = counterBufferOffset;
6396 info.stride = vertexStride;
6397
6398 radv_draw(cmd_buffer, &info);
6399 }
6400
6401 /* VK_AMD_buffer_marker */
6402 void radv_CmdWriteBufferMarkerAMD(
6403 VkCommandBuffer commandBuffer,
6404 VkPipelineStageFlagBits pipelineStage,
6405 VkBuffer dstBuffer,
6406 VkDeviceSize dstOffset,
6407 uint32_t marker)
6408 {
6409 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6410 RADV_FROM_HANDLE(radv_buffer, buffer, dstBuffer);
6411 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6412 uint64_t va = radv_buffer_get_va(buffer->bo) + dstOffset;
6413
6414 si_emit_cache_flush(cmd_buffer);
6415
6416 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 12);
6417
6418 if (!(pipelineStage & ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT)) {
6419 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
6420 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
6421 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
6422 COPY_DATA_WR_CONFIRM);
6423 radeon_emit(cs, marker);
6424 radeon_emit(cs, 0);
6425 radeon_emit(cs, va);
6426 radeon_emit(cs, va >> 32);
6427 } else {
6428 si_cs_emit_write_event_eop(cs,
6429 cmd_buffer->device->physical_device->rad_info.chip_class,
6430 radv_cmd_buffer_uses_mec(cmd_buffer),
6431 V_028A90_BOTTOM_OF_PIPE_TS, 0,
6432 EOP_DST_SEL_MEM,
6433 EOP_DATA_SEL_VALUE_32BIT,
6434 va, marker,
6435 cmd_buffer->gfx9_eop_bug_va);
6436 }
6437
6438 assert(cmd_buffer->cs->cdw <= cdw_max);
6439 }