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radv: Implement VK_KHR_imageless_framebuffer.
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range,
61 struct radv_sample_locations_state *sample_locs);
62
63 const struct radv_dynamic_state default_dynamic_state = {
64 .viewport = {
65 .count = 0,
66 },
67 .scissor = {
68 .count = 0,
69 },
70 .line_width = 1.0f,
71 .depth_bias = {
72 .bias = 0.0f,
73 .clamp = 0.0f,
74 .slope = 0.0f,
75 },
76 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
77 .depth_bounds = {
78 .min = 0.0f,
79 .max = 1.0f,
80 },
81 .stencil_compare_mask = {
82 .front = ~0u,
83 .back = ~0u,
84 },
85 .stencil_write_mask = {
86 .front = ~0u,
87 .back = ~0u,
88 },
89 .stencil_reference = {
90 .front = 0u,
91 .back = 0u,
92 },
93 };
94
95 static void
96 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
97 const struct radv_dynamic_state *src)
98 {
99 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
100 uint32_t copy_mask = src->mask;
101 uint32_t dest_mask = 0;
102
103 /* Make sure to copy the number of viewports/scissors because they can
104 * only be specified at pipeline creation time.
105 */
106 dest->viewport.count = src->viewport.count;
107 dest->scissor.count = src->scissor.count;
108 dest->discard_rectangle.count = src->discard_rectangle.count;
109 dest->sample_location.count = src->sample_location.count;
110
111 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
112 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
113 src->viewport.count * sizeof(VkViewport))) {
114 typed_memcpy(dest->viewport.viewports,
115 src->viewport.viewports,
116 src->viewport.count);
117 dest_mask |= RADV_DYNAMIC_VIEWPORT;
118 }
119 }
120
121 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
122 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
123 src->scissor.count * sizeof(VkRect2D))) {
124 typed_memcpy(dest->scissor.scissors,
125 src->scissor.scissors, src->scissor.count);
126 dest_mask |= RADV_DYNAMIC_SCISSOR;
127 }
128 }
129
130 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
131 if (dest->line_width != src->line_width) {
132 dest->line_width = src->line_width;
133 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
134 }
135 }
136
137 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
138 if (memcmp(&dest->depth_bias, &src->depth_bias,
139 sizeof(src->depth_bias))) {
140 dest->depth_bias = src->depth_bias;
141 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
142 }
143 }
144
145 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
146 if (memcmp(&dest->blend_constants, &src->blend_constants,
147 sizeof(src->blend_constants))) {
148 typed_memcpy(dest->blend_constants,
149 src->blend_constants, 4);
150 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
151 }
152 }
153
154 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
155 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
156 sizeof(src->depth_bounds))) {
157 dest->depth_bounds = src->depth_bounds;
158 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
159 }
160 }
161
162 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
163 if (memcmp(&dest->stencil_compare_mask,
164 &src->stencil_compare_mask,
165 sizeof(src->stencil_compare_mask))) {
166 dest->stencil_compare_mask = src->stencil_compare_mask;
167 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
168 }
169 }
170
171 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
172 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
173 sizeof(src->stencil_write_mask))) {
174 dest->stencil_write_mask = src->stencil_write_mask;
175 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
176 }
177 }
178
179 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
180 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
181 sizeof(src->stencil_reference))) {
182 dest->stencil_reference = src->stencil_reference;
183 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
184 }
185 }
186
187 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
188 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
189 src->discard_rectangle.count * sizeof(VkRect2D))) {
190 typed_memcpy(dest->discard_rectangle.rectangles,
191 src->discard_rectangle.rectangles,
192 src->discard_rectangle.count);
193 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
194 }
195 }
196
197 if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
198 if (dest->sample_location.per_pixel != src->sample_location.per_pixel ||
199 dest->sample_location.grid_size.width != src->sample_location.grid_size.width ||
200 dest->sample_location.grid_size.height != src->sample_location.grid_size.height ||
201 memcmp(&dest->sample_location.locations,
202 &src->sample_location.locations,
203 src->sample_location.count * sizeof(VkSampleLocationEXT))) {
204 dest->sample_location.per_pixel = src->sample_location.per_pixel;
205 dest->sample_location.grid_size = src->sample_location.grid_size;
206 typed_memcpy(dest->sample_location.locations,
207 src->sample_location.locations,
208 src->sample_location.count);
209 dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
210 }
211 }
212
213 cmd_buffer->state.dirty |= dest_mask;
214 }
215
216 static void
217 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
218 struct radv_pipeline *pipeline)
219 {
220 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
221 struct radv_shader_info *info;
222
223 if (!pipeline->streamout_shader)
224 return;
225
226 info = &pipeline->streamout_shader->info.info;
227 for (int i = 0; i < MAX_SO_BUFFERS; i++)
228 so->stride_in_dw[i] = info->so.strides[i];
229
230 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
231 }
232
233 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
234 {
235 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
236 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
237 }
238
239 enum ring_type radv_queue_family_to_ring(int f) {
240 switch (f) {
241 case RADV_QUEUE_GENERAL:
242 return RING_GFX;
243 case RADV_QUEUE_COMPUTE:
244 return RING_COMPUTE;
245 case RADV_QUEUE_TRANSFER:
246 return RING_DMA;
247 default:
248 unreachable("Unknown queue family");
249 }
250 }
251
252 static VkResult radv_create_cmd_buffer(
253 struct radv_device * device,
254 struct radv_cmd_pool * pool,
255 VkCommandBufferLevel level,
256 VkCommandBuffer* pCommandBuffer)
257 {
258 struct radv_cmd_buffer *cmd_buffer;
259 unsigned ring;
260 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
261 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
262 if (cmd_buffer == NULL)
263 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
264
265 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
266 cmd_buffer->device = device;
267 cmd_buffer->pool = pool;
268 cmd_buffer->level = level;
269
270 if (pool) {
271 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
272 cmd_buffer->queue_family_index = pool->queue_family_index;
273
274 } else {
275 /* Init the pool_link so we can safely call list_del when we destroy
276 * the command buffer
277 */
278 list_inithead(&cmd_buffer->pool_link);
279 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
280 }
281
282 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
283
284 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
285 if (!cmd_buffer->cs) {
286 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
287 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
288 }
289
290 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
291
292 list_inithead(&cmd_buffer->upload.list);
293
294 return VK_SUCCESS;
295 }
296
297 static void
298 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
299 {
300 list_del(&cmd_buffer->pool_link);
301
302 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
303 &cmd_buffer->upload.list, list) {
304 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
305 list_del(&up->list);
306 free(up);
307 }
308
309 if (cmd_buffer->upload.upload_bo)
310 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
311 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
312
313 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
314 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
315
316 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
317 }
318
319 static VkResult
320 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
321 {
322 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
323
324 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
325 &cmd_buffer->upload.list, list) {
326 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
327 list_del(&up->list);
328 free(up);
329 }
330
331 cmd_buffer->push_constant_stages = 0;
332 cmd_buffer->scratch_size_needed = 0;
333 cmd_buffer->compute_scratch_size_needed = 0;
334 cmd_buffer->esgs_ring_size_needed = 0;
335 cmd_buffer->gsvs_ring_size_needed = 0;
336 cmd_buffer->tess_rings_needed = false;
337 cmd_buffer->sample_positions_needed = false;
338
339 if (cmd_buffer->upload.upload_bo)
340 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
341 cmd_buffer->upload.upload_bo);
342 cmd_buffer->upload.offset = 0;
343
344 cmd_buffer->record_result = VK_SUCCESS;
345
346 memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
347
348 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
349 cmd_buffer->descriptors[i].dirty = 0;
350 cmd_buffer->descriptors[i].valid = 0;
351 cmd_buffer->descriptors[i].push_dirty = false;
352 }
353
354 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
355 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
356 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
357 unsigned fence_offset, eop_bug_offset;
358 void *fence_ptr;
359
360 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
361 &fence_ptr);
362
363 cmd_buffer->gfx9_fence_va =
364 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
365 cmd_buffer->gfx9_fence_va += fence_offset;
366
367 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
368 /* Allocate a buffer for the EOP bug on GFX9. */
369 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
370 &eop_bug_offset, &fence_ptr);
371 cmd_buffer->gfx9_eop_bug_va =
372 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
373 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
374 }
375 }
376
377 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
378
379 return cmd_buffer->record_result;
380 }
381
382 static bool
383 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
384 uint64_t min_needed)
385 {
386 uint64_t new_size;
387 struct radeon_winsys_bo *bo;
388 struct radv_cmd_buffer_upload *upload;
389 struct radv_device *device = cmd_buffer->device;
390
391 new_size = MAX2(min_needed, 16 * 1024);
392 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
393
394 bo = device->ws->buffer_create(device->ws,
395 new_size, 4096,
396 RADEON_DOMAIN_GTT,
397 RADEON_FLAG_CPU_ACCESS|
398 RADEON_FLAG_NO_INTERPROCESS_SHARING |
399 RADEON_FLAG_32BIT,
400 RADV_BO_PRIORITY_UPLOAD_BUFFER);
401
402 if (!bo) {
403 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
404 return false;
405 }
406
407 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
408 if (cmd_buffer->upload.upload_bo) {
409 upload = malloc(sizeof(*upload));
410
411 if (!upload) {
412 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
413 device->ws->buffer_destroy(bo);
414 return false;
415 }
416
417 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
418 list_add(&upload->list, &cmd_buffer->upload.list);
419 }
420
421 cmd_buffer->upload.upload_bo = bo;
422 cmd_buffer->upload.size = new_size;
423 cmd_buffer->upload.offset = 0;
424 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
425
426 if (!cmd_buffer->upload.map) {
427 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
428 return false;
429 }
430
431 return true;
432 }
433
434 bool
435 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
436 unsigned size,
437 unsigned alignment,
438 unsigned *out_offset,
439 void **ptr)
440 {
441 assert(util_is_power_of_two_nonzero(alignment));
442
443 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
444 if (offset + size > cmd_buffer->upload.size) {
445 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
446 return false;
447 offset = 0;
448 }
449
450 *out_offset = offset;
451 *ptr = cmd_buffer->upload.map + offset;
452
453 cmd_buffer->upload.offset = offset + size;
454 return true;
455 }
456
457 bool
458 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
459 unsigned size, unsigned alignment,
460 const void *data, unsigned *out_offset)
461 {
462 uint8_t *ptr;
463
464 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
465 out_offset, (void **)&ptr))
466 return false;
467
468 if (ptr)
469 memcpy(ptr, data, size);
470
471 return true;
472 }
473
474 static void
475 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
476 unsigned count, const uint32_t *data)
477 {
478 struct radeon_cmdbuf *cs = cmd_buffer->cs;
479
480 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
481
482 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
483 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
484 S_370_WR_CONFIRM(1) |
485 S_370_ENGINE_SEL(V_370_ME));
486 radeon_emit(cs, va);
487 radeon_emit(cs, va >> 32);
488 radeon_emit_array(cs, data, count);
489 }
490
491 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
492 {
493 struct radv_device *device = cmd_buffer->device;
494 struct radeon_cmdbuf *cs = cmd_buffer->cs;
495 uint64_t va;
496
497 va = radv_buffer_get_va(device->trace_bo);
498 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
499 va += 4;
500
501 ++cmd_buffer->state.trace_id;
502 radv_emit_write_data_packet(cmd_buffer, va, 1,
503 &cmd_buffer->state.trace_id);
504
505 radeon_check_space(cmd_buffer->device->ws, cs, 2);
506
507 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
508 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
509 }
510
511 static void
512 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
513 enum radv_cmd_flush_bits flags)
514 {
515 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
516 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
517 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
518
519 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
520
521 /* Force wait for graphics or compute engines to be idle. */
522 si_cs_emit_cache_flush(cmd_buffer->cs,
523 cmd_buffer->device->physical_device->rad_info.chip_class,
524 &cmd_buffer->gfx9_fence_idx,
525 cmd_buffer->gfx9_fence_va,
526 radv_cmd_buffer_uses_mec(cmd_buffer),
527 flags, cmd_buffer->gfx9_eop_bug_va);
528 }
529
530 if (unlikely(cmd_buffer->device->trace_bo))
531 radv_cmd_buffer_trace_emit(cmd_buffer);
532 }
533
534 static void
535 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
536 struct radv_pipeline *pipeline, enum ring_type ring)
537 {
538 struct radv_device *device = cmd_buffer->device;
539 uint32_t data[2];
540 uint64_t va;
541
542 va = radv_buffer_get_va(device->trace_bo);
543
544 switch (ring) {
545 case RING_GFX:
546 va += 8;
547 break;
548 case RING_COMPUTE:
549 va += 16;
550 break;
551 default:
552 assert(!"invalid ring type");
553 }
554
555 data[0] = (uintptr_t)pipeline;
556 data[1] = (uintptr_t)pipeline >> 32;
557
558 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
559 }
560
561 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
562 VkPipelineBindPoint bind_point,
563 struct radv_descriptor_set *set,
564 unsigned idx)
565 {
566 struct radv_descriptor_state *descriptors_state =
567 radv_get_descriptors_state(cmd_buffer, bind_point);
568
569 descriptors_state->sets[idx] = set;
570
571 descriptors_state->valid |= (1u << idx); /* active descriptors */
572 descriptors_state->dirty |= (1u << idx);
573 }
574
575 static void
576 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
577 VkPipelineBindPoint bind_point)
578 {
579 struct radv_descriptor_state *descriptors_state =
580 radv_get_descriptors_state(cmd_buffer, bind_point);
581 struct radv_device *device = cmd_buffer->device;
582 uint32_t data[MAX_SETS * 2] = {};
583 uint64_t va;
584 unsigned i;
585 va = radv_buffer_get_va(device->trace_bo) + 24;
586
587 for_each_bit(i, descriptors_state->valid) {
588 struct radv_descriptor_set *set = descriptors_state->sets[i];
589 data[i * 2] = (uint64_t)(uintptr_t)set;
590 data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
591 }
592
593 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
594 }
595
596 struct radv_userdata_info *
597 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
598 gl_shader_stage stage,
599 int idx)
600 {
601 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
602 return &shader->info.user_sgprs_locs.shader_data[idx];
603 }
604
605 static void
606 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
607 struct radv_pipeline *pipeline,
608 gl_shader_stage stage,
609 int idx, uint64_t va)
610 {
611 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
612 uint32_t base_reg = pipeline->user_data_0[stage];
613 if (loc->sgpr_idx == -1)
614 return;
615
616 assert(loc->num_sgprs == 1);
617
618 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
619 base_reg + loc->sgpr_idx * 4, va, false);
620 }
621
622 static void
623 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
624 struct radv_pipeline *pipeline,
625 struct radv_descriptor_state *descriptors_state,
626 gl_shader_stage stage)
627 {
628 struct radv_device *device = cmd_buffer->device;
629 struct radeon_cmdbuf *cs = cmd_buffer->cs;
630 uint32_t sh_base = pipeline->user_data_0[stage];
631 struct radv_userdata_locations *locs =
632 &pipeline->shaders[stage]->info.user_sgprs_locs;
633 unsigned mask = locs->descriptor_sets_enabled;
634
635 mask &= descriptors_state->dirty & descriptors_state->valid;
636
637 while (mask) {
638 int start, count;
639
640 u_bit_scan_consecutive_range(&mask, &start, &count);
641
642 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
643 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
644
645 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
646 for (int i = 0; i < count; i++) {
647 struct radv_descriptor_set *set =
648 descriptors_state->sets[start + i];
649
650 radv_emit_shader_pointer_body(device, cs, set->va, true);
651 }
652 }
653 }
654
655 /**
656 * Convert the user sample locations to hardware sample locations (the values
657 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
658 */
659 static void
660 radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
661 uint32_t x, uint32_t y, VkOffset2D *sample_locs)
662 {
663 uint32_t x_offset = x % state->grid_size.width;
664 uint32_t y_offset = y % state->grid_size.height;
665 uint32_t num_samples = (uint32_t)state->per_pixel;
666 VkSampleLocationEXT *user_locs;
667 uint32_t pixel_offset;
668
669 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
670
671 assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
672 user_locs = &state->locations[pixel_offset];
673
674 for (uint32_t i = 0; i < num_samples; i++) {
675 float shifted_pos_x = user_locs[i].x - 0.5;
676 float shifted_pos_y = user_locs[i].y - 0.5;
677
678 int32_t scaled_pos_x = floor(shifted_pos_x * 16);
679 int32_t scaled_pos_y = floor(shifted_pos_y * 16);
680
681 sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
682 sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
683 }
684 }
685
686 /**
687 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
688 * locations.
689 */
690 static void
691 radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
692 uint32_t *sample_locs_pixel)
693 {
694 for (uint32_t i = 0; i < num_samples; i++) {
695 uint32_t sample_reg_idx = i / 4;
696 uint32_t sample_loc_idx = i % 4;
697 int32_t pos_x = sample_locs[i].x;
698 int32_t pos_y = sample_locs[i].y;
699
700 uint32_t shift_x = 8 * sample_loc_idx;
701 uint32_t shift_y = shift_x + 4;
702
703 sample_locs_pixel[sample_reg_idx] |= (pos_x & 0xf) << shift_x;
704 sample_locs_pixel[sample_reg_idx] |= (pos_y & 0xf) << shift_y;
705 }
706 }
707
708 /**
709 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
710 * sample locations.
711 */
712 static uint64_t
713 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer,
714 VkOffset2D *sample_locs,
715 uint32_t num_samples)
716 {
717 uint32_t centroid_priorities[num_samples];
718 uint32_t sample_mask = num_samples - 1;
719 uint32_t distances[num_samples];
720 uint64_t centroid_priority = 0;
721
722 /* Compute the distances from center for each sample. */
723 for (int i = 0; i < num_samples; i++) {
724 distances[i] = (sample_locs[i].x * sample_locs[i].x) +
725 (sample_locs[i].y * sample_locs[i].y);
726 }
727
728 /* Compute the centroid priorities by looking at the distances array. */
729 for (int i = 0; i < num_samples; i++) {
730 uint32_t min_idx = 0;
731
732 for (int j = 1; j < num_samples; j++) {
733 if (distances[j] < distances[min_idx])
734 min_idx = j;
735 }
736
737 centroid_priorities[i] = min_idx;
738 distances[min_idx] = 0xffffffff;
739 }
740
741 /* Compute the final centroid priority. */
742 for (int i = 0; i < 8; i++) {
743 centroid_priority |=
744 centroid_priorities[i & sample_mask] << (i * 4);
745 }
746
747 return centroid_priority << 32 | centroid_priority;
748 }
749
750 /**
751 * Emit the sample locations that are specified with VK_EXT_sample_locations.
752 */
753 static void
754 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
755 {
756 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
757 struct radv_multisample_state *ms = &pipeline->graphics.ms;
758 struct radv_sample_locations_state *sample_location =
759 &cmd_buffer->state.dynamic.sample_location;
760 uint32_t num_samples = (uint32_t)sample_location->per_pixel;
761 struct radeon_cmdbuf *cs = cmd_buffer->cs;
762 uint32_t sample_locs_pixel[4][2] = {};
763 VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
764 uint32_t max_sample_dist = 0;
765 uint64_t centroid_priority;
766
767 if (!cmd_buffer->state.dynamic.sample_location.count)
768 return;
769
770 /* Convert the user sample locations to hardware sample locations. */
771 radv_convert_user_sample_locs(sample_location, 0, 0, sample_locs[0]);
772 radv_convert_user_sample_locs(sample_location, 1, 0, sample_locs[1]);
773 radv_convert_user_sample_locs(sample_location, 0, 1, sample_locs[2]);
774 radv_convert_user_sample_locs(sample_location, 1, 1, sample_locs[3]);
775
776 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
777 for (uint32_t i = 0; i < 4; i++) {
778 radv_compute_sample_locs_pixel(num_samples, sample_locs[i],
779 sample_locs_pixel[i]);
780 }
781
782 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
783 centroid_priority =
784 radv_compute_centroid_priority(cmd_buffer, sample_locs[0],
785 num_samples);
786
787 /* Compute the maximum sample distance from the specified locations. */
788 for (uint32_t i = 0; i < num_samples; i++) {
789 VkOffset2D offset = sample_locs[0][i];
790 max_sample_dist = MAX2(max_sample_dist,
791 MAX2(abs(offset.x), abs(offset.y)));
792 }
793
794 /* Emit the specified user sample locations. */
795 switch (num_samples) {
796 case 2:
797 case 4:
798 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
799 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
800 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
801 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
802 break;
803 case 8:
804 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
805 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
806 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
807 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
808 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs_pixel[0][1]);
809 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs_pixel[1][1]);
810 radeon_set_context_reg(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs_pixel[2][1]);
811 radeon_set_context_reg(cs, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs_pixel[3][1]);
812 break;
813 default:
814 unreachable("invalid number of samples");
815 }
816
817 /* Emit the maximum sample distance and the centroid priority. */
818 uint32_t pa_sc_aa_config = ms->pa_sc_aa_config;
819
820 pa_sc_aa_config &= C_028BE0_MAX_SAMPLE_DIST;
821 pa_sc_aa_config |= S_028BE0_MAX_SAMPLE_DIST(max_sample_dist);
822
823 radeon_set_context_reg_seq(cs, R_028BE0_PA_SC_AA_CONFIG, 1);
824 radeon_emit(cs, pa_sc_aa_config);
825
826 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
827 radeon_emit(cs, centroid_priority);
828 radeon_emit(cs, centroid_priority >> 32);
829
830 /* GFX9: Flush DFSM when the AA mode changes. */
831 if (cmd_buffer->device->dfsm_allowed) {
832 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
833 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
834 }
835
836 cmd_buffer->state.context_roll_without_scissor_emitted = true;
837 }
838
839 static void
840 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
841 struct radv_pipeline *pipeline,
842 gl_shader_stage stage,
843 int idx, int count, uint32_t *values)
844 {
845 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
846 uint32_t base_reg = pipeline->user_data_0[stage];
847 if (loc->sgpr_idx == -1)
848 return;
849
850 assert(loc->num_sgprs == count);
851
852 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
853 radeon_emit_array(cmd_buffer->cs, values, count);
854 }
855
856 static void
857 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
858 struct radv_pipeline *pipeline)
859 {
860 int num_samples = pipeline->graphics.ms.num_samples;
861 struct radv_multisample_state *ms = &pipeline->graphics.ms;
862 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
863
864 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
865 cmd_buffer->sample_positions_needed = true;
866
867 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
868 return;
869
870 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
871 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
872 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
873
874 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
875
876 radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
877
878 /* GFX9: Flush DFSM when the AA mode changes. */
879 if (cmd_buffer->device->dfsm_allowed) {
880 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
881 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
882 }
883
884 cmd_buffer->state.context_roll_without_scissor_emitted = true;
885 }
886
887 static void
888 radv_update_binning_state(struct radv_cmd_buffer *cmd_buffer,
889 struct radv_pipeline *pipeline)
890 {
891 const struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
892
893
894 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
895 return;
896
897 if (old_pipeline &&
898 old_pipeline->graphics.binning.pa_sc_binner_cntl_0 == pipeline->graphics.binning.pa_sc_binner_cntl_0 &&
899 old_pipeline->graphics.binning.db_dfsm_control == pipeline->graphics.binning.db_dfsm_control)
900 return;
901
902 bool binning_flush = false;
903 if (cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA12 ||
904 cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA20 ||
905 cmd_buffer->device->physical_device->rad_info.family == CHIP_RAVEN2 ||
906 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
907 binning_flush = !old_pipeline ||
908 G_028C44_BINNING_MODE(old_pipeline->graphics.binning.pa_sc_binner_cntl_0) !=
909 G_028C44_BINNING_MODE(pipeline->graphics.binning.pa_sc_binner_cntl_0);
910 }
911
912 radeon_set_context_reg(cmd_buffer->cs, R_028C44_PA_SC_BINNER_CNTL_0,
913 pipeline->graphics.binning.pa_sc_binner_cntl_0 |
914 S_028C44_FLUSH_ON_BINNING_TRANSITION(!!binning_flush));
915
916 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
917 radeon_set_context_reg(cmd_buffer->cs, R_028038_DB_DFSM_CONTROL,
918 pipeline->graphics.binning.db_dfsm_control);
919 } else {
920 radeon_set_context_reg(cmd_buffer->cs, R_028060_DB_DFSM_CONTROL,
921 pipeline->graphics.binning.db_dfsm_control);
922 }
923
924 cmd_buffer->state.context_roll_without_scissor_emitted = true;
925 }
926
927
928 static void
929 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
930 struct radv_shader_variant *shader)
931 {
932 uint64_t va;
933
934 if (!shader)
935 return;
936
937 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
938
939 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
940 }
941
942 static void
943 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
944 struct radv_pipeline *pipeline,
945 bool vertex_stage_only)
946 {
947 struct radv_cmd_state *state = &cmd_buffer->state;
948 uint32_t mask = state->prefetch_L2_mask;
949
950 if (vertex_stage_only) {
951 /* Fast prefetch path for starting draws as soon as possible.
952 */
953 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
954 RADV_PREFETCH_VBO_DESCRIPTORS);
955 }
956
957 if (mask & RADV_PREFETCH_VS)
958 radv_emit_shader_prefetch(cmd_buffer,
959 pipeline->shaders[MESA_SHADER_VERTEX]);
960
961 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
962 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
963
964 if (mask & RADV_PREFETCH_TCS)
965 radv_emit_shader_prefetch(cmd_buffer,
966 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
967
968 if (mask & RADV_PREFETCH_TES)
969 radv_emit_shader_prefetch(cmd_buffer,
970 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
971
972 if (mask & RADV_PREFETCH_GS) {
973 radv_emit_shader_prefetch(cmd_buffer,
974 pipeline->shaders[MESA_SHADER_GEOMETRY]);
975 if (radv_pipeline_has_gs_copy_shader(pipeline))
976 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
977 }
978
979 if (mask & RADV_PREFETCH_PS)
980 radv_emit_shader_prefetch(cmd_buffer,
981 pipeline->shaders[MESA_SHADER_FRAGMENT]);
982
983 state->prefetch_L2_mask &= ~mask;
984 }
985
986 static void
987 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
988 {
989 if (!cmd_buffer->device->physical_device->rbplus_allowed)
990 return;
991
992 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
993 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
994
995 unsigned sx_ps_downconvert = 0;
996 unsigned sx_blend_opt_epsilon = 0;
997 unsigned sx_blend_opt_control = 0;
998
999 for (unsigned i = 0; i < subpass->color_count; ++i) {
1000 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1001 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1002 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1003 continue;
1004 }
1005
1006 int idx = subpass->color_attachments[i].attachment;
1007 struct radv_color_buffer_info *cb = &cmd_buffer->state.attachments[idx].cb;
1008
1009 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
1010 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
1011 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
1012 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
1013
1014 bool has_alpha, has_rgb;
1015
1016 /* Set if RGB and A are present. */
1017 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
1018
1019 if (format == V_028C70_COLOR_8 ||
1020 format == V_028C70_COLOR_16 ||
1021 format == V_028C70_COLOR_32)
1022 has_rgb = !has_alpha;
1023 else
1024 has_rgb = true;
1025
1026 /* Check the colormask and export format. */
1027 if (!(colormask & 0x7))
1028 has_rgb = false;
1029 if (!(colormask & 0x8))
1030 has_alpha = false;
1031
1032 if (spi_format == V_028714_SPI_SHADER_ZERO) {
1033 has_rgb = false;
1034 has_alpha = false;
1035 }
1036
1037 /* Disable value checking for disabled channels. */
1038 if (!has_rgb)
1039 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1040 if (!has_alpha)
1041 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1042
1043 /* Enable down-conversion for 32bpp and smaller formats. */
1044 switch (format) {
1045 case V_028C70_COLOR_8:
1046 case V_028C70_COLOR_8_8:
1047 case V_028C70_COLOR_8_8_8_8:
1048 /* For 1 and 2-channel formats, use the superset thereof. */
1049 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
1050 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1051 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1052 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
1053 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
1054 }
1055 break;
1056
1057 case V_028C70_COLOR_5_6_5:
1058 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1059 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
1060 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
1061 }
1062 break;
1063
1064 case V_028C70_COLOR_1_5_5_5:
1065 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1066 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
1067 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
1068 }
1069 break;
1070
1071 case V_028C70_COLOR_4_4_4_4:
1072 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1073 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
1074 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
1075 }
1076 break;
1077
1078 case V_028C70_COLOR_32:
1079 if (swap == V_028C70_SWAP_STD &&
1080 spi_format == V_028714_SPI_SHADER_32_R)
1081 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1082 else if (swap == V_028C70_SWAP_ALT_REV &&
1083 spi_format == V_028714_SPI_SHADER_32_AR)
1084 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
1085 break;
1086
1087 case V_028C70_COLOR_16:
1088 case V_028C70_COLOR_16_16:
1089 /* For 1-channel formats, use the superset thereof. */
1090 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
1091 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
1092 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1093 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1094 if (swap == V_028C70_SWAP_STD ||
1095 swap == V_028C70_SWAP_STD_REV)
1096 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
1097 else
1098 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
1099 }
1100 break;
1101
1102 case V_028C70_COLOR_10_11_11:
1103 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1104 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
1105 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
1106 }
1107 break;
1108
1109 case V_028C70_COLOR_2_10_10_10:
1110 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1111 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
1112 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
1113 }
1114 break;
1115 }
1116 }
1117
1118 for (unsigned i = subpass->color_count; i < 8; ++i) {
1119 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1120 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1121 }
1122 /* TODO: avoid redundantly setting context registers */
1123 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
1124 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
1125 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
1126 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
1127
1128 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1129 }
1130
1131 static void
1132 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1133 {
1134 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1135
1136 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1137 return;
1138
1139 radv_update_multisample_state(cmd_buffer, pipeline);
1140 radv_update_binning_state(cmd_buffer, pipeline);
1141
1142 cmd_buffer->scratch_size_needed =
1143 MAX2(cmd_buffer->scratch_size_needed,
1144 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1145
1146 if (!cmd_buffer->state.emitted_pipeline ||
1147 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1148 pipeline->graphics.can_use_guardband)
1149 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1150
1151 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
1152
1153 if (!cmd_buffer->state.emitted_pipeline ||
1154 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
1155 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
1156 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
1157 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
1158 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
1159 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1160 }
1161
1162 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
1163 if (!pipeline->shaders[i])
1164 continue;
1165
1166 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1167 pipeline->shaders[i]->bo);
1168 }
1169
1170 if (radv_pipeline_has_gs_copy_shader(pipeline))
1171 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1172 pipeline->gs_copy_shader->bo);
1173
1174 if (unlikely(cmd_buffer->device->trace_bo))
1175 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1176
1177 cmd_buffer->state.emitted_pipeline = pipeline;
1178
1179 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1180 }
1181
1182 static void
1183 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1184 {
1185 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1186 cmd_buffer->state.dynamic.viewport.viewports);
1187 }
1188
1189 static void
1190 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1191 {
1192 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1193
1194 si_write_scissors(cmd_buffer->cs, 0, count,
1195 cmd_buffer->state.dynamic.scissor.scissors,
1196 cmd_buffer->state.dynamic.viewport.viewports,
1197 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1198
1199 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1200 }
1201
1202 static void
1203 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1204 {
1205 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1206 return;
1207
1208 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1209 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1210 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1211 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1212 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1213 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1214 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1215 }
1216 }
1217
1218 static void
1219 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1220 {
1221 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1222
1223 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1224 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1225 }
1226
1227 static void
1228 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1229 {
1230 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1231
1232 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1233 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1234 }
1235
1236 static void
1237 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1238 {
1239 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1240
1241 radeon_set_context_reg_seq(cmd_buffer->cs,
1242 R_028430_DB_STENCILREFMASK, 2);
1243 radeon_emit(cmd_buffer->cs,
1244 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1245 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1246 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1247 S_028430_STENCILOPVAL(1));
1248 radeon_emit(cmd_buffer->cs,
1249 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1250 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1251 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1252 S_028434_STENCILOPVAL_BF(1));
1253 }
1254
1255 static void
1256 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1257 {
1258 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1259
1260 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1261 fui(d->depth_bounds.min));
1262 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1263 fui(d->depth_bounds.max));
1264 }
1265
1266 static void
1267 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1268 {
1269 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1270 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1271 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1272
1273
1274 radeon_set_context_reg_seq(cmd_buffer->cs,
1275 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1276 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1277 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1278 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1279 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1280 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1281 }
1282
1283 static void
1284 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1285 int index,
1286 struct radv_color_buffer_info *cb,
1287 struct radv_image_view *iview,
1288 VkImageLayout layout)
1289 {
1290 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
1291 uint32_t cb_color_info = cb->cb_color_info;
1292 struct radv_image *image = iview->image;
1293
1294 if (!radv_layout_dcc_compressed(image, layout,
1295 radv_image_queue_family_mask(image,
1296 cmd_buffer->queue_family_index,
1297 cmd_buffer->queue_family_index))) {
1298 cb_color_info &= C_028C70_DCC_ENABLE;
1299 }
1300
1301 if (radv_image_is_tc_compat_cmask(image) &&
1302 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1303 radv_is_dcc_decompress_pipeline(cmd_buffer))) {
1304 /* If this bit is set, the FMASK decompression operation
1305 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1306 */
1307 cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
1308 }
1309
1310 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1311 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1312 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1313 radeon_emit(cmd_buffer->cs, 0);
1314 radeon_emit(cmd_buffer->cs, 0);
1315 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1316 radeon_emit(cmd_buffer->cs, cb_color_info);
1317 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1318 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1319 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1320 radeon_emit(cmd_buffer->cs, 0);
1321 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1322 radeon_emit(cmd_buffer->cs, 0);
1323
1324 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 1);
1325 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1326
1327 radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4,
1328 cb->cb_color_base >> 32);
1329 radeon_set_context_reg(cmd_buffer->cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + index * 4,
1330 cb->cb_color_cmask >> 32);
1331 radeon_set_context_reg(cmd_buffer->cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + index * 4,
1332 cb->cb_color_fmask >> 32);
1333 radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4,
1334 cb->cb_dcc_base >> 32);
1335 radeon_set_context_reg(cmd_buffer->cs, R_028EC0_CB_COLOR0_ATTRIB2 + index * 4,
1336 cb->cb_color_attrib2);
1337 radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4,
1338 cb->cb_color_attrib3);
1339 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1340 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1341 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1342 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1343 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1344 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1345 radeon_emit(cmd_buffer->cs, cb_color_info);
1346 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1347 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1348 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1349 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1350 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1351 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1352
1353 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1354 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1355 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1356
1357 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1358 cb->cb_mrt_epitch);
1359 } else {
1360 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1361 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1362 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1363 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1364 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1365 radeon_emit(cmd_buffer->cs, cb_color_info);
1366 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1367 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1368 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1369 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1370 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1371 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1372
1373 if (is_vi) { /* DCC BASE */
1374 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1375 }
1376 }
1377
1378 if (radv_dcc_enabled(image, iview->base_mip)) {
1379 /* Drawing with DCC enabled also compresses colorbuffers. */
1380 VkImageSubresourceRange range = {
1381 .aspectMask = iview->aspect_mask,
1382 .baseMipLevel = iview->base_mip,
1383 .levelCount = iview->level_count,
1384 .baseArrayLayer = iview->base_layer,
1385 .layerCount = iview->layer_count,
1386 };
1387
1388 radv_update_dcc_metadata(cmd_buffer, image, &range, true);
1389 }
1390 }
1391
1392 static void
1393 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1394 struct radv_ds_buffer_info *ds,
1395 struct radv_image *image, VkImageLayout layout,
1396 bool requires_cond_exec)
1397 {
1398 uint32_t db_z_info = ds->db_z_info;
1399 uint32_t db_z_info_reg;
1400
1401 if (!cmd_buffer->device->physical_device->has_tc_compat_zrange_bug ||
1402 !radv_image_is_tc_compat_htile(image))
1403 return;
1404
1405 if (!radv_layout_has_htile(image, layout,
1406 radv_image_queue_family_mask(image,
1407 cmd_buffer->queue_family_index,
1408 cmd_buffer->queue_family_index))) {
1409 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1410 }
1411
1412 db_z_info &= C_028040_ZRANGE_PRECISION;
1413
1414 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1415 db_z_info_reg = R_028038_DB_Z_INFO;
1416 } else {
1417 db_z_info_reg = R_028040_DB_Z_INFO;
1418 }
1419
1420 /* When we don't know the last fast clear value we need to emit a
1421 * conditional packet that will eventually skip the following
1422 * SET_CONTEXT_REG packet.
1423 */
1424 if (requires_cond_exec) {
1425 uint64_t va = radv_buffer_get_va(image->bo);
1426 va += image->offset + image->tc_compat_zrange_offset;
1427
1428 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1429 radeon_emit(cmd_buffer->cs, va);
1430 radeon_emit(cmd_buffer->cs, va >> 32);
1431 radeon_emit(cmd_buffer->cs, 0);
1432 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1433 }
1434
1435 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1436 }
1437
1438 static void
1439 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1440 struct radv_ds_buffer_info *ds,
1441 struct radv_image *image,
1442 VkImageLayout layout)
1443 {
1444 uint32_t db_z_info = ds->db_z_info;
1445 uint32_t db_stencil_info = ds->db_stencil_info;
1446
1447 if (!radv_layout_has_htile(image, layout,
1448 radv_image_queue_family_mask(image,
1449 cmd_buffer->queue_family_index,
1450 cmd_buffer->queue_family_index))) {
1451 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1452 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1453 }
1454
1455 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1456 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1457
1458 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1459 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1460 radeon_set_context_reg(cmd_buffer->cs, R_02801C_DB_DEPTH_SIZE_XY, ds->db_depth_size);
1461
1462 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 7);
1463 radeon_emit(cmd_buffer->cs, S_02803C_RESOURCE_LEVEL(1));
1464 radeon_emit(cmd_buffer->cs, db_z_info);
1465 radeon_emit(cmd_buffer->cs, db_stencil_info);
1466 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1467 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1468 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1469 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1470
1471 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_READ_BASE_HI, 5);
1472 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1473 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1474 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1475 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1476 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1477 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1478 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1479 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1480 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1481 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1482
1483 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1484 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1485 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1486 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1487 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1488 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1489 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1490 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1491 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1492 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1493 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1494
1495 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1496 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1497 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1498 } else {
1499 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1500
1501 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1502 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1503 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1504 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1505 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1506 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1507 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1508 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1509 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1510 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1511
1512 }
1513
1514 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1515 radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1516
1517 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1518 ds->pa_su_poly_offset_db_fmt_cntl);
1519 }
1520
1521 /**
1522 * Update the fast clear depth/stencil values if the image is bound as a
1523 * depth/stencil buffer.
1524 */
1525 static void
1526 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1527 struct radv_image *image,
1528 VkClearDepthStencilValue ds_clear_value,
1529 VkImageAspectFlags aspects)
1530 {
1531 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1532 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1533 uint32_t att_idx;
1534
1535 if (!cmd_buffer->state.attachments || !subpass)
1536 return;
1537
1538 if (!subpass->depth_stencil_attachment)
1539 return;
1540
1541 att_idx = subpass->depth_stencil_attachment->attachment;
1542 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1543 return;
1544
1545 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1546 radeon_emit(cs, ds_clear_value.stencil);
1547 radeon_emit(cs, fui(ds_clear_value.depth));
1548
1549 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1550 * only needed when clearing Z to 0.0.
1551 */
1552 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1553 ds_clear_value.depth == 0.0) {
1554 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1555
1556 radv_update_zrange_precision(cmd_buffer, &cmd_buffer->state.attachments[att_idx].ds, image,
1557 layout, false);
1558 }
1559
1560 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1561 }
1562
1563 /**
1564 * Set the clear depth/stencil values to the image's metadata.
1565 */
1566 static void
1567 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1568 struct radv_image *image,
1569 VkClearDepthStencilValue ds_clear_value,
1570 VkImageAspectFlags aspects)
1571 {
1572 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1573 uint64_t va = radv_buffer_get_va(image->bo);
1574 unsigned reg_offset = 0, reg_count = 0;
1575
1576 va += image->offset + image->clear_value_offset;
1577
1578 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1579 ++reg_count;
1580 } else {
1581 ++reg_offset;
1582 va += 4;
1583 }
1584 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1585 ++reg_count;
1586
1587 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, cmd_buffer->state.predicating));
1588 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1589 S_370_WR_CONFIRM(1) |
1590 S_370_ENGINE_SEL(V_370_PFP));
1591 radeon_emit(cs, va);
1592 radeon_emit(cs, va >> 32);
1593 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1594 radeon_emit(cs, ds_clear_value.stencil);
1595 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1596 radeon_emit(cs, fui(ds_clear_value.depth));
1597 }
1598
1599 /**
1600 * Update the TC-compat metadata value for this image.
1601 */
1602 static void
1603 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1604 struct radv_image *image,
1605 uint32_t value)
1606 {
1607 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1608 uint64_t va = radv_buffer_get_va(image->bo);
1609
1610 if (!cmd_buffer->device->physical_device->has_tc_compat_zrange_bug)
1611 return;
1612
1613 va += image->offset + image->tc_compat_zrange_offset;
1614
1615 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1616 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1617 S_370_WR_CONFIRM(1) |
1618 S_370_ENGINE_SEL(V_370_PFP));
1619 radeon_emit(cs, va);
1620 radeon_emit(cs, va >> 32);
1621 radeon_emit(cs, value);
1622 }
1623
1624 static void
1625 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1626 struct radv_image *image,
1627 VkClearDepthStencilValue ds_clear_value)
1628 {
1629 uint32_t cond_val;
1630
1631 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1632 * depth clear value is 0.0f.
1633 */
1634 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1635
1636 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, cond_val);
1637 }
1638
1639 /**
1640 * Update the clear depth/stencil values for this image.
1641 */
1642 void
1643 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1644 struct radv_image *image,
1645 VkClearDepthStencilValue ds_clear_value,
1646 VkImageAspectFlags aspects)
1647 {
1648 assert(radv_image_has_htile(image));
1649
1650 radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
1651
1652 if (radv_image_is_tc_compat_htile(image) &&
1653 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1654 radv_update_tc_compat_zrange_metadata(cmd_buffer, image,
1655 ds_clear_value);
1656 }
1657
1658 radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1659 aspects);
1660 }
1661
1662 /**
1663 * Load the clear depth/stencil values from the image's metadata.
1664 */
1665 static void
1666 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1667 struct radv_image *image)
1668 {
1669 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1670 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1671 uint64_t va = radv_buffer_get_va(image->bo);
1672 unsigned reg_offset = 0, reg_count = 0;
1673
1674 va += image->offset + image->clear_value_offset;
1675
1676 if (!radv_image_has_htile(image))
1677 return;
1678
1679 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1680 ++reg_count;
1681 } else {
1682 ++reg_offset;
1683 va += 4;
1684 }
1685 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1686 ++reg_count;
1687
1688 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1689
1690 if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) {
1691 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1692 radeon_emit(cs, va);
1693 radeon_emit(cs, va >> 32);
1694 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1695 radeon_emit(cs, reg_count);
1696 } else {
1697 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1698 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1699 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1700 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1701 radeon_emit(cs, va);
1702 radeon_emit(cs, va >> 32);
1703 radeon_emit(cs, reg >> 2);
1704 radeon_emit(cs, 0);
1705
1706 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1707 radeon_emit(cs, 0);
1708 }
1709 }
1710
1711 /*
1712 * With DCC some colors don't require CMASK elimination before being
1713 * used as a texture. This sets a predicate value to determine if the
1714 * cmask eliminate is required.
1715 */
1716 void
1717 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1718 struct radv_image *image,
1719 const VkImageSubresourceRange *range, bool value)
1720 {
1721 uint64_t pred_val = value;
1722 uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
1723 uint32_t level_count = radv_get_levelCount(image, range);
1724 uint32_t count = 2 * level_count;
1725
1726 assert(radv_dcc_enabled(image, range->baseMipLevel));
1727
1728 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1729 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1730 S_370_WR_CONFIRM(1) |
1731 S_370_ENGINE_SEL(V_370_PFP));
1732 radeon_emit(cmd_buffer->cs, va);
1733 radeon_emit(cmd_buffer->cs, va >> 32);
1734
1735 for (uint32_t l = 0; l < level_count; l++) {
1736 radeon_emit(cmd_buffer->cs, pred_val);
1737 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1738 }
1739 }
1740
1741 /**
1742 * Update the DCC predicate to reflect the compression state.
1743 */
1744 void
1745 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1746 struct radv_image *image,
1747 const VkImageSubresourceRange *range, bool value)
1748 {
1749 uint64_t pred_val = value;
1750 uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
1751 uint32_t level_count = radv_get_levelCount(image, range);
1752 uint32_t count = 2 * level_count;
1753
1754 assert(radv_dcc_enabled(image, range->baseMipLevel));
1755
1756 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1757 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1758 S_370_WR_CONFIRM(1) |
1759 S_370_ENGINE_SEL(V_370_PFP));
1760 radeon_emit(cmd_buffer->cs, va);
1761 radeon_emit(cmd_buffer->cs, va >> 32);
1762
1763 for (uint32_t l = 0; l < level_count; l++) {
1764 radeon_emit(cmd_buffer->cs, pred_val);
1765 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1766 }
1767 }
1768
1769 /**
1770 * Update the fast clear color values if the image is bound as a color buffer.
1771 */
1772 static void
1773 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1774 struct radv_image *image,
1775 int cb_idx,
1776 uint32_t color_values[2])
1777 {
1778 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1779 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1780 uint32_t att_idx;
1781
1782 if (!cmd_buffer->state.attachments || !subpass)
1783 return;
1784
1785 att_idx = subpass->color_attachments[cb_idx].attachment;
1786 if (att_idx == VK_ATTACHMENT_UNUSED)
1787 return;
1788
1789 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1790 return;
1791
1792 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1793 radeon_emit(cs, color_values[0]);
1794 radeon_emit(cs, color_values[1]);
1795
1796 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1797 }
1798
1799 /**
1800 * Set the clear color values to the image's metadata.
1801 */
1802 static void
1803 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1804 struct radv_image *image,
1805 const VkImageSubresourceRange *range,
1806 uint32_t color_values[2])
1807 {
1808 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1809 uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
1810 uint32_t level_count = radv_get_levelCount(image, range);
1811 uint32_t count = 2 * level_count;
1812
1813 assert(radv_image_has_cmask(image) ||
1814 radv_dcc_enabled(image, range->baseMipLevel));
1815
1816 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
1817 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1818 S_370_WR_CONFIRM(1) |
1819 S_370_ENGINE_SEL(V_370_PFP));
1820 radeon_emit(cs, va);
1821 radeon_emit(cs, va >> 32);
1822
1823 for (uint32_t l = 0; l < level_count; l++) {
1824 radeon_emit(cs, color_values[0]);
1825 radeon_emit(cs, color_values[1]);
1826 }
1827 }
1828
1829 /**
1830 * Update the clear color values for this image.
1831 */
1832 void
1833 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1834 const struct radv_image_view *iview,
1835 int cb_idx,
1836 uint32_t color_values[2])
1837 {
1838 struct radv_image *image = iview->image;
1839 VkImageSubresourceRange range = {
1840 .aspectMask = iview->aspect_mask,
1841 .baseMipLevel = iview->base_mip,
1842 .levelCount = iview->level_count,
1843 .baseArrayLayer = iview->base_layer,
1844 .layerCount = iview->layer_count,
1845 };
1846
1847 assert(radv_image_has_cmask(image) ||
1848 radv_dcc_enabled(image, iview->base_mip));
1849
1850 radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
1851
1852 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1853 color_values);
1854 }
1855
1856 /**
1857 * Load the clear color values from the image's metadata.
1858 */
1859 static void
1860 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1861 struct radv_image_view *iview,
1862 int cb_idx)
1863 {
1864 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1865 struct radv_image *image = iview->image;
1866 uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
1867
1868 if (!radv_image_has_cmask(image) &&
1869 !radv_dcc_enabled(image, iview->base_mip))
1870 return;
1871
1872 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1873
1874 if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) {
1875 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1876 radeon_emit(cs, va);
1877 radeon_emit(cs, va >> 32);
1878 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1879 radeon_emit(cs, 2);
1880 } else {
1881 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1882 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1883 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1884 COPY_DATA_COUNT_SEL);
1885 radeon_emit(cs, va);
1886 radeon_emit(cs, va >> 32);
1887 radeon_emit(cs, reg >> 2);
1888 radeon_emit(cs, 0);
1889
1890 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1891 radeon_emit(cs, 0);
1892 }
1893 }
1894
1895 static void
1896 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1897 {
1898 int i;
1899 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1900 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1901
1902 /* this may happen for inherited secondary recording */
1903 if (!framebuffer)
1904 return;
1905
1906 for (i = 0; i < 8; ++i) {
1907 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1908 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1909 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1910 continue;
1911 }
1912
1913 int idx = subpass->color_attachments[i].attachment;
1914 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
1915 VkImageLayout layout = subpass->color_attachments[i].layout;
1916
1917 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, iview->bo);
1918
1919 assert(iview->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
1920 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
1921 radv_emit_fb_color_state(cmd_buffer, i, &cmd_buffer->state.attachments[idx].cb, iview, layout);
1922
1923 radv_load_color_clear_metadata(cmd_buffer, iview, i);
1924 }
1925
1926 if (subpass->depth_stencil_attachment) {
1927 int idx = subpass->depth_stencil_attachment->attachment;
1928 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1929 struct radv_image *image = cmd_buffer->state.attachments[idx].iview->image;
1930 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, cmd_buffer->state.attachments[idx].iview->bo);
1931 ASSERTED uint32_t queue_mask = radv_image_queue_family_mask(image,
1932 cmd_buffer->queue_family_index,
1933 cmd_buffer->queue_family_index);
1934 /* We currently don't support writing decompressed HTILE */
1935 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1936 radv_layout_is_htile_compressed(image, layout, queue_mask));
1937
1938 radv_emit_fb_ds_state(cmd_buffer, &cmd_buffer->state.attachments[idx].ds, image, layout);
1939
1940 if (cmd_buffer->state.attachments[idx].ds.offset_scale != cmd_buffer->state.offset_scale) {
1941 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1942 cmd_buffer->state.offset_scale = cmd_buffer->state.attachments[idx].ds.offset_scale;
1943 }
1944 radv_load_ds_clear_metadata(cmd_buffer, image);
1945 } else {
1946 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9)
1947 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1948 else
1949 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1950
1951 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1952 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1953 }
1954 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1955 S_028208_BR_X(framebuffer->width) |
1956 S_028208_BR_Y(framebuffer->height));
1957
1958 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
1959 bool disable_constant_encode =
1960 cmd_buffer->device->physical_device->has_dcc_constant_encode;
1961 enum chip_class chip_class =
1962 cmd_buffer->device->physical_device->rad_info.chip_class;
1963 uint8_t watermark = chip_class >= GFX10 ? 6 : 4;
1964
1965 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
1966 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class <= GFX9) |
1967 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
1968 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
1969 }
1970
1971 if (cmd_buffer->device->pbb_allowed) {
1972 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1973 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1974 }
1975
1976 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1977 }
1978
1979 static void
1980 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1981 {
1982 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1983 struct radv_cmd_state *state = &cmd_buffer->state;
1984
1985 if (state->index_type != state->last_index_type) {
1986 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1987 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
1988 cs, R_03090C_VGT_INDEX_TYPE,
1989 2, state->index_type);
1990 } else {
1991 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1992 radeon_emit(cs, state->index_type);
1993 }
1994
1995 state->last_index_type = state->index_type;
1996 }
1997
1998 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1999 radeon_emit(cs, state->index_va);
2000 radeon_emit(cs, state->index_va >> 32);
2001
2002 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2003 radeon_emit(cs, state->max_index_count);
2004
2005 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
2006 }
2007
2008 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
2009 {
2010 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
2011 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2012 uint32_t pa_sc_mode_cntl_1 =
2013 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
2014 uint32_t db_count_control;
2015
2016 if(!cmd_buffer->state.active_occlusion_queries) {
2017 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2018 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2019 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2020 has_perfect_queries) {
2021 /* Re-enable out-of-order rasterization if the
2022 * bound pipeline supports it and if it's has
2023 * been disabled before starting any perfect
2024 * occlusion queries.
2025 */
2026 radeon_set_context_reg(cmd_buffer->cs,
2027 R_028A4C_PA_SC_MODE_CNTL_1,
2028 pa_sc_mode_cntl_1);
2029 }
2030 }
2031 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
2032 } else {
2033 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2034 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
2035 bool gfx10_perfect = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10 && has_perfect_queries;
2036
2037 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2038 db_count_control =
2039 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
2040 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
2041 S_028004_SAMPLE_RATE(sample_rate) |
2042 S_028004_ZPASS_ENABLE(1) |
2043 S_028004_SLICE_EVEN_ENABLE(1) |
2044 S_028004_SLICE_ODD_ENABLE(1);
2045
2046 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2047 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2048 has_perfect_queries) {
2049 /* If the bound pipeline has enabled
2050 * out-of-order rasterization, we should
2051 * disable it before starting any perfect
2052 * occlusion queries.
2053 */
2054 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
2055
2056 radeon_set_context_reg(cmd_buffer->cs,
2057 R_028A4C_PA_SC_MODE_CNTL_1,
2058 pa_sc_mode_cntl_1);
2059 }
2060 } else {
2061 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
2062 S_028004_SAMPLE_RATE(sample_rate);
2063 }
2064 }
2065
2066 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
2067
2068 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2069 }
2070
2071 static void
2072 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
2073 {
2074 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
2075
2076 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
2077 radv_emit_viewport(cmd_buffer);
2078
2079 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
2080 !cmd_buffer->device->physical_device->has_scissor_bug)
2081 radv_emit_scissor(cmd_buffer);
2082
2083 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
2084 radv_emit_line_width(cmd_buffer);
2085
2086 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
2087 radv_emit_blend_constants(cmd_buffer);
2088
2089 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
2090 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
2091 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
2092 radv_emit_stencil(cmd_buffer);
2093
2094 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
2095 radv_emit_depth_bounds(cmd_buffer);
2096
2097 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
2098 radv_emit_depth_bias(cmd_buffer);
2099
2100 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
2101 radv_emit_discard_rectangle(cmd_buffer);
2102
2103 if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)
2104 radv_emit_sample_locations(cmd_buffer);
2105
2106 cmd_buffer->state.dirty &= ~states;
2107 }
2108
2109 static void
2110 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
2111 VkPipelineBindPoint bind_point)
2112 {
2113 struct radv_descriptor_state *descriptors_state =
2114 radv_get_descriptors_state(cmd_buffer, bind_point);
2115 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
2116 unsigned bo_offset;
2117
2118 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
2119 set->mapped_ptr,
2120 &bo_offset))
2121 return;
2122
2123 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2124 set->va += bo_offset;
2125 }
2126
2127 static void
2128 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
2129 VkPipelineBindPoint bind_point)
2130 {
2131 struct radv_descriptor_state *descriptors_state =
2132 radv_get_descriptors_state(cmd_buffer, bind_point);
2133 uint32_t size = MAX_SETS * 4;
2134 uint32_t offset;
2135 void *ptr;
2136
2137 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
2138 256, &offset, &ptr))
2139 return;
2140
2141 for (unsigned i = 0; i < MAX_SETS; i++) {
2142 uint32_t *uptr = ((uint32_t *)ptr) + i;
2143 uint64_t set_va = 0;
2144 struct radv_descriptor_set *set = descriptors_state->sets[i];
2145 if (descriptors_state->valid & (1u << i))
2146 set_va = set->va;
2147 uptr[0] = set_va & 0xffffffff;
2148 }
2149
2150 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2151 va += offset;
2152
2153 if (cmd_buffer->state.pipeline) {
2154 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
2155 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2156 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2157
2158 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
2159 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
2160 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2161
2162 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
2163 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2164 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2165
2166 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2167 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
2168 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2169
2170 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2171 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
2172 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2173 }
2174
2175 if (cmd_buffer->state.compute_pipeline)
2176 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
2177 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2178 }
2179
2180 static void
2181 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
2182 VkShaderStageFlags stages)
2183 {
2184 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2185 VK_PIPELINE_BIND_POINT_COMPUTE :
2186 VK_PIPELINE_BIND_POINT_GRAPHICS;
2187 struct radv_descriptor_state *descriptors_state =
2188 radv_get_descriptors_state(cmd_buffer, bind_point);
2189 struct radv_cmd_state *state = &cmd_buffer->state;
2190 bool flush_indirect_descriptors;
2191
2192 if (!descriptors_state->dirty)
2193 return;
2194
2195 if (descriptors_state->push_dirty)
2196 radv_flush_push_descriptors(cmd_buffer, bind_point);
2197
2198 flush_indirect_descriptors =
2199 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
2200 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
2201 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
2202 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
2203
2204 if (flush_indirect_descriptors)
2205 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
2206
2207 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2208 cmd_buffer->cs,
2209 MAX_SETS * MESA_SHADER_STAGES * 4);
2210
2211 if (cmd_buffer->state.pipeline) {
2212 radv_foreach_stage(stage, stages) {
2213 if (!cmd_buffer->state.pipeline->shaders[stage])
2214 continue;
2215
2216 radv_emit_descriptor_pointers(cmd_buffer,
2217 cmd_buffer->state.pipeline,
2218 descriptors_state, stage);
2219 }
2220 }
2221
2222 if (cmd_buffer->state.compute_pipeline &&
2223 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
2224 radv_emit_descriptor_pointers(cmd_buffer,
2225 cmd_buffer->state.compute_pipeline,
2226 descriptors_state,
2227 MESA_SHADER_COMPUTE);
2228 }
2229
2230 descriptors_state->dirty = 0;
2231 descriptors_state->push_dirty = false;
2232
2233 assert(cmd_buffer->cs->cdw <= cdw_max);
2234
2235 if (unlikely(cmd_buffer->device->trace_bo))
2236 radv_save_descriptors(cmd_buffer, bind_point);
2237 }
2238
2239 static void
2240 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
2241 VkShaderStageFlags stages)
2242 {
2243 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
2244 ? cmd_buffer->state.compute_pipeline
2245 : cmd_buffer->state.pipeline;
2246 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2247 VK_PIPELINE_BIND_POINT_COMPUTE :
2248 VK_PIPELINE_BIND_POINT_GRAPHICS;
2249 struct radv_descriptor_state *descriptors_state =
2250 radv_get_descriptors_state(cmd_buffer, bind_point);
2251 struct radv_pipeline_layout *layout = pipeline->layout;
2252 struct radv_shader_variant *shader, *prev_shader;
2253 bool need_push_constants = false;
2254 unsigned offset;
2255 void *ptr;
2256 uint64_t va;
2257
2258 stages &= cmd_buffer->push_constant_stages;
2259 if (!stages ||
2260 (!layout->push_constant_size && !layout->dynamic_offset_count))
2261 return;
2262
2263 radv_foreach_stage(stage, stages) {
2264 if (!pipeline->shaders[stage])
2265 continue;
2266
2267 need_push_constants |= pipeline->shaders[stage]->info.info.loads_push_constants;
2268 need_push_constants |= pipeline->shaders[stage]->info.info.loads_dynamic_offsets;
2269
2270 uint8_t base = pipeline->shaders[stage]->info.info.base_inline_push_consts;
2271 uint8_t count = pipeline->shaders[stage]->info.info.num_inline_push_consts;
2272
2273 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
2274 AC_UD_INLINE_PUSH_CONSTANTS,
2275 count,
2276 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
2277 }
2278
2279 if (need_push_constants) {
2280 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
2281 16 * layout->dynamic_offset_count,
2282 256, &offset, &ptr))
2283 return;
2284
2285 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
2286 memcpy((char*)ptr + layout->push_constant_size,
2287 descriptors_state->dynamic_buffers,
2288 16 * layout->dynamic_offset_count);
2289
2290 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2291 va += offset;
2292
2293 ASSERTED unsigned cdw_max =
2294 radeon_check_space(cmd_buffer->device->ws,
2295 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
2296
2297 prev_shader = NULL;
2298 radv_foreach_stage(stage, stages) {
2299 shader = radv_get_shader(pipeline, stage);
2300
2301 /* Avoid redundantly emitting the address for merged stages. */
2302 if (shader && shader != prev_shader) {
2303 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
2304 AC_UD_PUSH_CONSTANTS, va);
2305
2306 prev_shader = shader;
2307 }
2308 }
2309 assert(cmd_buffer->cs->cdw <= cdw_max);
2310 }
2311
2312 cmd_buffer->push_constant_stages &= ~stages;
2313 }
2314
2315 static void
2316 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
2317 bool pipeline_is_dirty)
2318 {
2319 if ((pipeline_is_dirty ||
2320 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
2321 cmd_buffer->state.pipeline->num_vertex_bindings &&
2322 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
2323 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
2324 unsigned vb_offset;
2325 void *vb_ptr;
2326 uint32_t i = 0;
2327 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
2328 uint64_t va;
2329
2330 /* allocate some descriptor state for vertex buffers */
2331 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2332 &vb_offset, &vb_ptr))
2333 return;
2334
2335 for (i = 0; i < count; i++) {
2336 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2337 uint32_t offset;
2338 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2339 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[i];
2340
2341 if (!buffer)
2342 continue;
2343
2344 va = radv_buffer_get_va(buffer->bo);
2345
2346 offset = cmd_buffer->vertex_bindings[i].offset;
2347 va += offset + buffer->offset;
2348 desc[0] = va;
2349 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2350 if (cmd_buffer->device->physical_device->rad_info.chip_class <= GFX7 && stride)
2351 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
2352 else
2353 desc[2] = buffer->size - offset;
2354 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2355 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2356 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2357 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2358
2359 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2360 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT) |
2361 S_008F0C_OOB_SELECT(1) |
2362 S_008F0C_RESOURCE_LEVEL(1);
2363 } else {
2364 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2365 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2366 }
2367 }
2368
2369 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2370 va += vb_offset;
2371
2372 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2373 AC_UD_VS_VERTEX_BUFFERS, va);
2374
2375 cmd_buffer->state.vb_va = va;
2376 cmd_buffer->state.vb_size = count * 16;
2377 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2378 }
2379 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2380 }
2381
2382 static void
2383 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2384 {
2385 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2386 struct radv_userdata_info *loc;
2387 uint32_t base_reg;
2388
2389 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2390 if (!radv_get_shader(pipeline, stage))
2391 continue;
2392
2393 loc = radv_lookup_user_sgpr(pipeline, stage,
2394 AC_UD_STREAMOUT_BUFFERS);
2395 if (loc->sgpr_idx == -1)
2396 continue;
2397
2398 base_reg = pipeline->user_data_0[stage];
2399
2400 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2401 base_reg + loc->sgpr_idx * 4, va, false);
2402 }
2403
2404 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
2405 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2406 if (loc->sgpr_idx != -1) {
2407 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2408
2409 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2410 base_reg + loc->sgpr_idx * 4, va, false);
2411 }
2412 }
2413 }
2414
2415 static void
2416 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2417 {
2418 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2419 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2420 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2421 unsigned so_offset;
2422 void *so_ptr;
2423 uint64_t va;
2424
2425 /* Allocate some descriptor state for streamout buffers. */
2426 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2427 MAX_SO_BUFFERS * 16, 256,
2428 &so_offset, &so_ptr))
2429 return;
2430
2431 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2432 struct radv_buffer *buffer = sb[i].buffer;
2433 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2434
2435 if (!(so->enabled_mask & (1 << i)))
2436 continue;
2437
2438 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2439
2440 va += sb[i].offset;
2441
2442 /* Set the descriptor.
2443 *
2444 * On GFX8, the format must be non-INVALID, otherwise
2445 * the buffer will be considered not bound and store
2446 * instructions will be no-ops.
2447 */
2448 desc[0] = va;
2449 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2450 desc[2] = 0xffffffff;
2451 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2452 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2453 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2454 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2455
2456 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2457 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2458 S_008F0C_OOB_SELECT(3) |
2459 S_008F0C_RESOURCE_LEVEL(1);
2460 } else {
2461 desc[3] |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2462 }
2463 }
2464
2465 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2466 va += so_offset;
2467
2468 radv_emit_streamout_buffers(cmd_buffer, va);
2469 }
2470
2471 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2472 }
2473
2474 static void
2475 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2476 {
2477 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2478 radv_flush_streamout_descriptors(cmd_buffer);
2479 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2480 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2481 }
2482
2483 struct radv_draw_info {
2484 /**
2485 * Number of vertices.
2486 */
2487 uint32_t count;
2488
2489 /**
2490 * Index of the first vertex.
2491 */
2492 int32_t vertex_offset;
2493
2494 /**
2495 * First instance id.
2496 */
2497 uint32_t first_instance;
2498
2499 /**
2500 * Number of instances.
2501 */
2502 uint32_t instance_count;
2503
2504 /**
2505 * First index (indexed draws only).
2506 */
2507 uint32_t first_index;
2508
2509 /**
2510 * Whether it's an indexed draw.
2511 */
2512 bool indexed;
2513
2514 /**
2515 * Indirect draw parameters resource.
2516 */
2517 struct radv_buffer *indirect;
2518 uint64_t indirect_offset;
2519 uint32_t stride;
2520
2521 /**
2522 * Draw count parameters resource.
2523 */
2524 struct radv_buffer *count_buffer;
2525 uint64_t count_buffer_offset;
2526
2527 /**
2528 * Stream output parameters resource.
2529 */
2530 struct radv_buffer *strmout_buffer;
2531 uint64_t strmout_buffer_offset;
2532 };
2533
2534 static uint32_t
2535 radv_get_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
2536 {
2537 switch (cmd_buffer->state.index_type) {
2538 case V_028A7C_VGT_INDEX_8:
2539 return 0xffu;
2540 case V_028A7C_VGT_INDEX_16:
2541 return 0xffffu;
2542 case V_028A7C_VGT_INDEX_32:
2543 return 0xffffffffu;
2544 default:
2545 unreachable("invalid index type");
2546 }
2547 }
2548
2549 static void
2550 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
2551 bool instanced_draw, bool indirect_draw,
2552 bool count_from_stream_output,
2553 uint32_t draw_vertex_count)
2554 {
2555 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2556 struct radv_cmd_state *state = &cmd_buffer->state;
2557 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2558 unsigned ia_multi_vgt_param;
2559
2560 ia_multi_vgt_param =
2561 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
2562 indirect_draw,
2563 count_from_stream_output,
2564 draw_vertex_count);
2565
2566 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2567 if (info->chip_class == GFX9) {
2568 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2569 cs,
2570 R_030960_IA_MULTI_VGT_PARAM,
2571 4, ia_multi_vgt_param);
2572 } else if (info->chip_class >= GFX7) {
2573 radeon_set_context_reg_idx(cs,
2574 R_028AA8_IA_MULTI_VGT_PARAM,
2575 1, ia_multi_vgt_param);
2576 } else {
2577 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2578 ia_multi_vgt_param);
2579 }
2580 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2581 }
2582 }
2583
2584 static void
2585 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2586 const struct radv_draw_info *draw_info)
2587 {
2588 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2589 struct radv_cmd_state *state = &cmd_buffer->state;
2590 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2591 int32_t primitive_reset_en;
2592
2593 /* Draw state. */
2594 if (info->chip_class < GFX10) {
2595 si_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2596 draw_info->indirect,
2597 !!draw_info->strmout_buffer,
2598 draw_info->indirect ? 0 : draw_info->count);
2599 }
2600
2601 /* Primitive restart. */
2602 primitive_reset_en =
2603 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2604
2605 if (primitive_reset_en != state->last_primitive_reset_en) {
2606 state->last_primitive_reset_en = primitive_reset_en;
2607 if (info->chip_class >= GFX9) {
2608 radeon_set_uconfig_reg(cs,
2609 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2610 primitive_reset_en);
2611 } else {
2612 radeon_set_context_reg(cs,
2613 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2614 primitive_reset_en);
2615 }
2616 }
2617
2618 if (primitive_reset_en) {
2619 uint32_t primitive_reset_index =
2620 radv_get_primitive_reset_index(cmd_buffer);
2621
2622 if (primitive_reset_index != state->last_primitive_reset_index) {
2623 radeon_set_context_reg(cs,
2624 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2625 primitive_reset_index);
2626 state->last_primitive_reset_index = primitive_reset_index;
2627 }
2628 }
2629
2630 if (draw_info->strmout_buffer) {
2631 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2632
2633 va += draw_info->strmout_buffer->offset +
2634 draw_info->strmout_buffer_offset;
2635
2636 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2637 draw_info->stride);
2638
2639 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2640 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2641 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2642 COPY_DATA_WR_CONFIRM);
2643 radeon_emit(cs, va);
2644 radeon_emit(cs, va >> 32);
2645 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2646 radeon_emit(cs, 0); /* unused */
2647
2648 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2649 }
2650 }
2651
2652 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2653 VkPipelineStageFlags src_stage_mask)
2654 {
2655 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2656 VK_PIPELINE_STAGE_TRANSFER_BIT |
2657 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2658 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2659 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2660 }
2661
2662 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2663 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2664 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2665 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2666 VK_PIPELINE_STAGE_TRANSFER_BIT |
2667 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2668 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2669 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2670 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2671 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2672 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2673 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2674 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2675 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2676 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2677 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2678 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2679 }
2680 }
2681
2682 static enum radv_cmd_flush_bits
2683 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2684 VkAccessFlags src_flags,
2685 struct radv_image *image)
2686 {
2687 bool flush_CB_meta = true, flush_DB_meta = true;
2688 enum radv_cmd_flush_bits flush_bits = 0;
2689 uint32_t b;
2690
2691 if (image) {
2692 if (!radv_image_has_CB_metadata(image))
2693 flush_CB_meta = false;
2694 if (!radv_image_has_htile(image))
2695 flush_DB_meta = false;
2696 }
2697
2698 for_each_bit(b, src_flags) {
2699 switch ((VkAccessFlagBits)(1 << b)) {
2700 case VK_ACCESS_SHADER_WRITE_BIT:
2701 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2702 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2703 flush_bits |= RADV_CMD_FLAG_WB_L2;
2704 break;
2705 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2706 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2707 if (flush_CB_meta)
2708 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2709 break;
2710 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2711 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2712 if (flush_DB_meta)
2713 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2714 break;
2715 case VK_ACCESS_TRANSFER_WRITE_BIT:
2716 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2717 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2718 RADV_CMD_FLAG_INV_L2;
2719
2720 if (flush_CB_meta)
2721 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2722 if (flush_DB_meta)
2723 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2724 break;
2725 default:
2726 break;
2727 }
2728 }
2729 return flush_bits;
2730 }
2731
2732 static enum radv_cmd_flush_bits
2733 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2734 VkAccessFlags dst_flags,
2735 struct radv_image *image)
2736 {
2737 bool flush_CB_meta = true, flush_DB_meta = true;
2738 enum radv_cmd_flush_bits flush_bits = 0;
2739 bool flush_CB = true, flush_DB = true;
2740 bool image_is_coherent = false;
2741 uint32_t b;
2742
2743 if (image) {
2744 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2745 flush_CB = false;
2746 flush_DB = false;
2747 }
2748
2749 if (!radv_image_has_CB_metadata(image))
2750 flush_CB_meta = false;
2751 if (!radv_image_has_htile(image))
2752 flush_DB_meta = false;
2753
2754 /* TODO: implement shader coherent for GFX10 */
2755
2756 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
2757 if (image->info.samples == 1 &&
2758 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2759 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2760 !vk_format_is_stencil(image->vk_format)) {
2761 /* Single-sample color and single-sample depth
2762 * (not stencil) are coherent with shaders on
2763 * GFX9.
2764 */
2765 image_is_coherent = true;
2766 }
2767 }
2768 }
2769
2770 for_each_bit(b, dst_flags) {
2771 switch ((VkAccessFlagBits)(1 << b)) {
2772 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2773 case VK_ACCESS_INDEX_READ_BIT:
2774 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2775 break;
2776 case VK_ACCESS_UNIFORM_READ_BIT:
2777 flush_bits |= RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_SCACHE;
2778 break;
2779 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2780 case VK_ACCESS_TRANSFER_READ_BIT:
2781 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2782 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
2783 RADV_CMD_FLAG_INV_L2;
2784 break;
2785 case VK_ACCESS_SHADER_READ_BIT:
2786 flush_bits |= RADV_CMD_FLAG_INV_VCACHE;
2787
2788 if (!image_is_coherent)
2789 flush_bits |= RADV_CMD_FLAG_INV_L2;
2790 break;
2791 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2792 if (flush_CB)
2793 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2794 if (flush_CB_meta)
2795 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2796 break;
2797 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2798 if (flush_DB)
2799 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2800 if (flush_DB_meta)
2801 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2802 break;
2803 default:
2804 break;
2805 }
2806 }
2807 return flush_bits;
2808 }
2809
2810 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2811 const struct radv_subpass_barrier *barrier)
2812 {
2813 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2814 NULL);
2815 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2816 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2817 NULL);
2818 }
2819
2820 uint32_t
2821 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
2822 {
2823 struct radv_cmd_state *state = &cmd_buffer->state;
2824 uint32_t subpass_id = state->subpass - state->pass->subpasses;
2825
2826 /* The id of this subpass shouldn't exceed the number of subpasses in
2827 * this render pass minus 1.
2828 */
2829 assert(subpass_id < state->pass->subpass_count);
2830 return subpass_id;
2831 }
2832
2833 static struct radv_sample_locations_state *
2834 radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer,
2835 uint32_t att_idx,
2836 bool begin_subpass)
2837 {
2838 struct radv_cmd_state *state = &cmd_buffer->state;
2839 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
2840 struct radv_image_view *view = state->attachments[att_idx].iview;
2841
2842 if (view->image->info.samples == 1)
2843 return NULL;
2844
2845 if (state->pass->attachments[att_idx].first_subpass_idx == subpass_id) {
2846 /* Return the initial sample locations if this is the initial
2847 * layout transition of the given subpass attachemnt.
2848 */
2849 if (state->attachments[att_idx].sample_location.count > 0)
2850 return &state->attachments[att_idx].sample_location;
2851 } else {
2852 /* Otherwise return the subpass sample locations if defined. */
2853 if (state->subpass_sample_locs) {
2854 /* Because the driver sets the current subpass before
2855 * initial layout transitions, we should use the sample
2856 * locations from the previous subpass to avoid an
2857 * off-by-one problem. Otherwise, use the sample
2858 * locations for the current subpass for final layout
2859 * transitions.
2860 */
2861 if (begin_subpass)
2862 subpass_id--;
2863
2864 for (uint32_t i = 0; i < state->num_subpass_sample_locs; i++) {
2865 if (state->subpass_sample_locs[i].subpass_idx == subpass_id)
2866 return &state->subpass_sample_locs[i].sample_location;
2867 }
2868 }
2869 }
2870
2871 return NULL;
2872 }
2873
2874 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2875 struct radv_subpass_attachment att,
2876 bool begin_subpass)
2877 {
2878 unsigned idx = att.attachment;
2879 struct radv_image_view *view = cmd_buffer->state.attachments[idx].iview;
2880 struct radv_sample_locations_state *sample_locs;
2881 VkImageSubresourceRange range;
2882 range.aspectMask = 0;
2883 range.baseMipLevel = view->base_mip;
2884 range.levelCount = 1;
2885 range.baseArrayLayer = view->base_layer;
2886 range.layerCount = cmd_buffer->state.framebuffer->layers;
2887
2888 if (cmd_buffer->state.subpass->view_mask) {
2889 /* If the current subpass uses multiview, the driver might have
2890 * performed a fast color/depth clear to the whole image
2891 * (including all layers). To make sure the driver will
2892 * decompress the image correctly (if needed), we have to
2893 * account for the "real" number of layers. If the view mask is
2894 * sparse, this will decompress more layers than needed.
2895 */
2896 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
2897 }
2898
2899 /* Get the subpass sample locations for the given attachment, if NULL
2900 * is returned the driver will use the default HW locations.
2901 */
2902 sample_locs = radv_get_attachment_sample_locations(cmd_buffer, idx,
2903 begin_subpass);
2904
2905 radv_handle_image_transition(cmd_buffer,
2906 view->image,
2907 cmd_buffer->state.attachments[idx].current_layout,
2908 att.layout, 0, 0, &range, sample_locs);
2909
2910 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2911
2912
2913 }
2914
2915 void
2916 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2917 const struct radv_subpass *subpass)
2918 {
2919 cmd_buffer->state.subpass = subpass;
2920
2921 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2922 }
2923
2924 static VkResult
2925 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
2926 struct radv_render_pass *pass,
2927 const VkRenderPassBeginInfo *info)
2928 {
2929 const struct VkRenderPassSampleLocationsBeginInfoEXT *sample_locs =
2930 vk_find_struct_const(info->pNext,
2931 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT);
2932 struct radv_cmd_state *state = &cmd_buffer->state;
2933
2934 if (!sample_locs) {
2935 state->subpass_sample_locs = NULL;
2936 return VK_SUCCESS;
2937 }
2938
2939 for (uint32_t i = 0; i < sample_locs->attachmentInitialSampleLocationsCount; i++) {
2940 const VkAttachmentSampleLocationsEXT *att_sample_locs =
2941 &sample_locs->pAttachmentInitialSampleLocations[i];
2942 uint32_t att_idx = att_sample_locs->attachmentIndex;
2943 struct radv_image *image = cmd_buffer->state.attachments[att_idx].iview->image;
2944
2945 assert(vk_format_is_depth_or_stencil(image->vk_format));
2946
2947 /* From the Vulkan spec 1.1.108:
2948 *
2949 * "If the image referenced by the framebuffer attachment at
2950 * index attachmentIndex was not created with
2951 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
2952 * then the values specified in sampleLocationsInfo are
2953 * ignored."
2954 */
2955 if (!(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT))
2956 continue;
2957
2958 const VkSampleLocationsInfoEXT *sample_locs_info =
2959 &att_sample_locs->sampleLocationsInfo;
2960
2961 state->attachments[att_idx].sample_location.per_pixel =
2962 sample_locs_info->sampleLocationsPerPixel;
2963 state->attachments[att_idx].sample_location.grid_size =
2964 sample_locs_info->sampleLocationGridSize;
2965 state->attachments[att_idx].sample_location.count =
2966 sample_locs_info->sampleLocationsCount;
2967 typed_memcpy(&state->attachments[att_idx].sample_location.locations[0],
2968 sample_locs_info->pSampleLocations,
2969 sample_locs_info->sampleLocationsCount);
2970 }
2971
2972 state->subpass_sample_locs = vk_alloc(&cmd_buffer->pool->alloc,
2973 sample_locs->postSubpassSampleLocationsCount *
2974 sizeof(state->subpass_sample_locs[0]),
2975 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2976 if (state->subpass_sample_locs == NULL) {
2977 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2978 return cmd_buffer->record_result;
2979 }
2980
2981 state->num_subpass_sample_locs = sample_locs->postSubpassSampleLocationsCount;
2982
2983 for (uint32_t i = 0; i < sample_locs->postSubpassSampleLocationsCount; i++) {
2984 const VkSubpassSampleLocationsEXT *subpass_sample_locs_info =
2985 &sample_locs->pPostSubpassSampleLocations[i];
2986 const VkSampleLocationsInfoEXT *sample_locs_info =
2987 &subpass_sample_locs_info->sampleLocationsInfo;
2988
2989 state->subpass_sample_locs[i].subpass_idx =
2990 subpass_sample_locs_info->subpassIndex;
2991 state->subpass_sample_locs[i].sample_location.per_pixel =
2992 sample_locs_info->sampleLocationsPerPixel;
2993 state->subpass_sample_locs[i].sample_location.grid_size =
2994 sample_locs_info->sampleLocationGridSize;
2995 state->subpass_sample_locs[i].sample_location.count =
2996 sample_locs_info->sampleLocationsCount;
2997 typed_memcpy(&state->subpass_sample_locs[i].sample_location.locations[0],
2998 sample_locs_info->pSampleLocations,
2999 sample_locs_info->sampleLocationsCount);
3000 }
3001
3002 return VK_SUCCESS;
3003 }
3004
3005 static VkResult
3006 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
3007 struct radv_render_pass *pass,
3008 const VkRenderPassBeginInfo *info)
3009 {
3010 struct radv_cmd_state *state = &cmd_buffer->state;
3011 const struct VkRenderPassAttachmentBeginInfoKHR *attachment_info = NULL;
3012
3013 if (info) {
3014 attachment_info = vk_find_struct_const(info->pNext,
3015 RENDER_PASS_ATTACHMENT_BEGIN_INFO_KHR);
3016 }
3017
3018
3019 if (pass->attachment_count == 0) {
3020 state->attachments = NULL;
3021 return VK_SUCCESS;
3022 }
3023
3024 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
3025 pass->attachment_count *
3026 sizeof(state->attachments[0]),
3027 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3028 if (state->attachments == NULL) {
3029 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3030 return cmd_buffer->record_result;
3031 }
3032
3033 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
3034 struct radv_render_pass_attachment *att = &pass->attachments[i];
3035 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
3036 VkImageAspectFlags clear_aspects = 0;
3037
3038 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
3039 /* color attachment */
3040 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3041 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
3042 }
3043 } else {
3044 /* depthstencil attachment */
3045 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
3046 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3047 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
3048 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3049 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
3050 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3051 }
3052 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3053 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3054 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3055 }
3056 }
3057
3058 state->attachments[i].pending_clear_aspects = clear_aspects;
3059 state->attachments[i].cleared_views = 0;
3060 if (clear_aspects && info) {
3061 assert(info->clearValueCount > i);
3062 state->attachments[i].clear_value = info->pClearValues[i];
3063 }
3064
3065 state->attachments[i].current_layout = att->initial_layout;
3066 state->attachments[i].sample_location.count = 0;
3067
3068 struct radv_image_view *iview;
3069 if (attachment_info && attachment_info->attachmentCount > i) {
3070 iview = radv_image_view_from_handle(attachment_info->pAttachments[i]);
3071 } else {
3072 iview = state->framebuffer->attachments[i];
3073 }
3074
3075 state->attachments[i].iview = iview;
3076 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3077 radv_initialise_ds_surface(cmd_buffer->device, &state->attachments[i].ds, iview);
3078 } else {
3079 radv_initialise_color_surface(cmd_buffer->device, &state->attachments[i].cb, iview);
3080 }
3081 }
3082
3083 return VK_SUCCESS;
3084 }
3085
3086 VkResult radv_AllocateCommandBuffers(
3087 VkDevice _device,
3088 const VkCommandBufferAllocateInfo *pAllocateInfo,
3089 VkCommandBuffer *pCommandBuffers)
3090 {
3091 RADV_FROM_HANDLE(radv_device, device, _device);
3092 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
3093
3094 VkResult result = VK_SUCCESS;
3095 uint32_t i;
3096
3097 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
3098
3099 if (!list_empty(&pool->free_cmd_buffers)) {
3100 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
3101
3102 list_del(&cmd_buffer->pool_link);
3103 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
3104
3105 result = radv_reset_cmd_buffer(cmd_buffer);
3106 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
3107 cmd_buffer->level = pAllocateInfo->level;
3108
3109 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
3110 } else {
3111 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
3112 &pCommandBuffers[i]);
3113 }
3114 if (result != VK_SUCCESS)
3115 break;
3116 }
3117
3118 if (result != VK_SUCCESS) {
3119 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
3120 i, pCommandBuffers);
3121
3122 /* From the Vulkan 1.0.66 spec:
3123 *
3124 * "vkAllocateCommandBuffers can be used to create multiple
3125 * command buffers. If the creation of any of those command
3126 * buffers fails, the implementation must destroy all
3127 * successfully created command buffer objects from this
3128 * command, set all entries of the pCommandBuffers array to
3129 * NULL and return the error."
3130 */
3131 memset(pCommandBuffers, 0,
3132 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
3133 }
3134
3135 return result;
3136 }
3137
3138 void radv_FreeCommandBuffers(
3139 VkDevice device,
3140 VkCommandPool commandPool,
3141 uint32_t commandBufferCount,
3142 const VkCommandBuffer *pCommandBuffers)
3143 {
3144 for (uint32_t i = 0; i < commandBufferCount; i++) {
3145 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
3146
3147 if (cmd_buffer) {
3148 if (cmd_buffer->pool) {
3149 list_del(&cmd_buffer->pool_link);
3150 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
3151 } else
3152 radv_cmd_buffer_destroy(cmd_buffer);
3153
3154 }
3155 }
3156 }
3157
3158 VkResult radv_ResetCommandBuffer(
3159 VkCommandBuffer commandBuffer,
3160 VkCommandBufferResetFlags flags)
3161 {
3162 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3163 return radv_reset_cmd_buffer(cmd_buffer);
3164 }
3165
3166 VkResult radv_BeginCommandBuffer(
3167 VkCommandBuffer commandBuffer,
3168 const VkCommandBufferBeginInfo *pBeginInfo)
3169 {
3170 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3171 VkResult result = VK_SUCCESS;
3172
3173 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
3174 /* If the command buffer has already been resetted with
3175 * vkResetCommandBuffer, no need to do it again.
3176 */
3177 result = radv_reset_cmd_buffer(cmd_buffer);
3178 if (result != VK_SUCCESS)
3179 return result;
3180 }
3181
3182 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
3183 cmd_buffer->state.last_primitive_reset_en = -1;
3184 cmd_buffer->state.last_index_type = -1;
3185 cmd_buffer->state.last_num_instances = -1;
3186 cmd_buffer->state.last_vertex_offset = -1;
3187 cmd_buffer->state.last_first_instance = -1;
3188 cmd_buffer->state.predication_type = -1;
3189 cmd_buffer->usage_flags = pBeginInfo->flags;
3190
3191 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
3192 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
3193 assert(pBeginInfo->pInheritanceInfo);
3194 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
3195 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
3196
3197 struct radv_subpass *subpass =
3198 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
3199
3200 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
3201 if (result != VK_SUCCESS)
3202 return result;
3203
3204 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3205 }
3206
3207 if (unlikely(cmd_buffer->device->trace_bo)) {
3208 struct radv_device *device = cmd_buffer->device;
3209
3210 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
3211 device->trace_bo);
3212
3213 radv_cmd_buffer_trace_emit(cmd_buffer);
3214 }
3215
3216 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
3217
3218 return result;
3219 }
3220
3221 void radv_CmdBindVertexBuffers(
3222 VkCommandBuffer commandBuffer,
3223 uint32_t firstBinding,
3224 uint32_t bindingCount,
3225 const VkBuffer* pBuffers,
3226 const VkDeviceSize* pOffsets)
3227 {
3228 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3229 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
3230 bool changed = false;
3231
3232 /* We have to defer setting up vertex buffer since we need the buffer
3233 * stride from the pipeline. */
3234
3235 assert(firstBinding + bindingCount <= MAX_VBS);
3236 for (uint32_t i = 0; i < bindingCount; i++) {
3237 uint32_t idx = firstBinding + i;
3238
3239 if (!changed &&
3240 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
3241 vb[idx].offset != pOffsets[i])) {
3242 changed = true;
3243 }
3244
3245 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
3246 vb[idx].offset = pOffsets[i];
3247
3248 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3249 vb[idx].buffer->bo);
3250 }
3251
3252 if (!changed) {
3253 /* No state changes. */
3254 return;
3255 }
3256
3257 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
3258 }
3259
3260 static uint32_t
3261 vk_to_index_type(VkIndexType type)
3262 {
3263 switch (type) {
3264 case VK_INDEX_TYPE_UINT8_EXT:
3265 return V_028A7C_VGT_INDEX_8;
3266 case VK_INDEX_TYPE_UINT16:
3267 return V_028A7C_VGT_INDEX_16;
3268 case VK_INDEX_TYPE_UINT32:
3269 return V_028A7C_VGT_INDEX_32;
3270 default:
3271 unreachable("invalid index type");
3272 }
3273 }
3274
3275 static uint32_t
3276 radv_get_vgt_index_size(uint32_t type)
3277 {
3278 switch (type) {
3279 case V_028A7C_VGT_INDEX_8:
3280 return 1;
3281 case V_028A7C_VGT_INDEX_16:
3282 return 2;
3283 case V_028A7C_VGT_INDEX_32:
3284 return 4;
3285 default:
3286 unreachable("invalid index type");
3287 }
3288 }
3289
3290 void radv_CmdBindIndexBuffer(
3291 VkCommandBuffer commandBuffer,
3292 VkBuffer buffer,
3293 VkDeviceSize offset,
3294 VkIndexType indexType)
3295 {
3296 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3297 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
3298
3299 if (cmd_buffer->state.index_buffer == index_buffer &&
3300 cmd_buffer->state.index_offset == offset &&
3301 cmd_buffer->state.index_type == indexType) {
3302 /* No state changes. */
3303 return;
3304 }
3305
3306 cmd_buffer->state.index_buffer = index_buffer;
3307 cmd_buffer->state.index_offset = offset;
3308 cmd_buffer->state.index_type = vk_to_index_type(indexType);
3309 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
3310 cmd_buffer->state.index_va += index_buffer->offset + offset;
3311
3312 int index_size = radv_get_vgt_index_size(indexType);
3313 cmd_buffer->state.max_index_count = (index_buffer->size - offset) / index_size;
3314 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3315 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
3316 }
3317
3318
3319 static void
3320 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3321 VkPipelineBindPoint bind_point,
3322 struct radv_descriptor_set *set, unsigned idx)
3323 {
3324 struct radeon_winsys *ws = cmd_buffer->device->ws;
3325
3326 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
3327
3328 assert(set);
3329 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
3330
3331 if (!cmd_buffer->device->use_global_bo_list) {
3332 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3333 if (set->descriptors[j])
3334 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
3335 }
3336
3337 if(set->bo)
3338 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
3339 }
3340
3341 void radv_CmdBindDescriptorSets(
3342 VkCommandBuffer commandBuffer,
3343 VkPipelineBindPoint pipelineBindPoint,
3344 VkPipelineLayout _layout,
3345 uint32_t firstSet,
3346 uint32_t descriptorSetCount,
3347 const VkDescriptorSet* pDescriptorSets,
3348 uint32_t dynamicOffsetCount,
3349 const uint32_t* pDynamicOffsets)
3350 {
3351 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3352 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3353 unsigned dyn_idx = 0;
3354
3355 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
3356 struct radv_descriptor_state *descriptors_state =
3357 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3358
3359 for (unsigned i = 0; i < descriptorSetCount; ++i) {
3360 unsigned idx = i + firstSet;
3361 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
3362
3363 /* If the set is already bound we only need to update the
3364 * (potentially changed) dynamic offsets. */
3365 if (descriptors_state->sets[idx] != set ||
3366 !(descriptors_state->valid & (1u << idx))) {
3367 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
3368 }
3369
3370 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
3371 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
3372 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
3373 assert(dyn_idx < dynamicOffsetCount);
3374
3375 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
3376 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
3377 dst[0] = va;
3378 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
3379 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
3380 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3381 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3382 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3383 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3384
3385 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
3386 dst[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3387 S_008F0C_OOB_SELECT(3) |
3388 S_008F0C_RESOURCE_LEVEL(1);
3389 } else {
3390 dst[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3391 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3392 }
3393
3394 cmd_buffer->push_constant_stages |=
3395 set->layout->dynamic_shader_stages;
3396 }
3397 }
3398 }
3399
3400 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3401 struct radv_descriptor_set *set,
3402 struct radv_descriptor_set_layout *layout,
3403 VkPipelineBindPoint bind_point)
3404 {
3405 struct radv_descriptor_state *descriptors_state =
3406 radv_get_descriptors_state(cmd_buffer, bind_point);
3407 set->size = layout->size;
3408 set->layout = layout;
3409
3410 if (descriptors_state->push_set.capacity < set->size) {
3411 size_t new_size = MAX2(set->size, 1024);
3412 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
3413 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
3414
3415 free(set->mapped_ptr);
3416 set->mapped_ptr = malloc(new_size);
3417
3418 if (!set->mapped_ptr) {
3419 descriptors_state->push_set.capacity = 0;
3420 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3421 return false;
3422 }
3423
3424 descriptors_state->push_set.capacity = new_size;
3425 }
3426
3427 return true;
3428 }
3429
3430 void radv_meta_push_descriptor_set(
3431 struct radv_cmd_buffer* cmd_buffer,
3432 VkPipelineBindPoint pipelineBindPoint,
3433 VkPipelineLayout _layout,
3434 uint32_t set,
3435 uint32_t descriptorWriteCount,
3436 const VkWriteDescriptorSet* pDescriptorWrites)
3437 {
3438 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3439 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
3440 unsigned bo_offset;
3441
3442 assert(set == 0);
3443 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3444
3445 push_set->size = layout->set[set].layout->size;
3446 push_set->layout = layout->set[set].layout;
3447
3448 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
3449 &bo_offset,
3450 (void**) &push_set->mapped_ptr))
3451 return;
3452
3453 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
3454 push_set->va += bo_offset;
3455
3456 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3457 radv_descriptor_set_to_handle(push_set),
3458 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3459
3460 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3461 }
3462
3463 void radv_CmdPushDescriptorSetKHR(
3464 VkCommandBuffer commandBuffer,
3465 VkPipelineBindPoint pipelineBindPoint,
3466 VkPipelineLayout _layout,
3467 uint32_t set,
3468 uint32_t descriptorWriteCount,
3469 const VkWriteDescriptorSet* pDescriptorWrites)
3470 {
3471 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3472 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3473 struct radv_descriptor_state *descriptors_state =
3474 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3475 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3476
3477 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3478
3479 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3480 layout->set[set].layout,
3481 pipelineBindPoint))
3482 return;
3483
3484 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3485 * because it is invalid, according to Vulkan spec.
3486 */
3487 for (int i = 0; i < descriptorWriteCount; i++) {
3488 ASSERTED const VkWriteDescriptorSet *writeset = &pDescriptorWrites[i];
3489 assert(writeset->descriptorType != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT);
3490 }
3491
3492 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3493 radv_descriptor_set_to_handle(push_set),
3494 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3495
3496 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3497 descriptors_state->push_dirty = true;
3498 }
3499
3500 void radv_CmdPushDescriptorSetWithTemplateKHR(
3501 VkCommandBuffer commandBuffer,
3502 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
3503 VkPipelineLayout _layout,
3504 uint32_t set,
3505 const void* pData)
3506 {
3507 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3508 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3509 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
3510 struct radv_descriptor_state *descriptors_state =
3511 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
3512 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3513
3514 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3515
3516 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3517 layout->set[set].layout,
3518 templ->bind_point))
3519 return;
3520
3521 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
3522 descriptorUpdateTemplate, pData);
3523
3524 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
3525 descriptors_state->push_dirty = true;
3526 }
3527
3528 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
3529 VkPipelineLayout layout,
3530 VkShaderStageFlags stageFlags,
3531 uint32_t offset,
3532 uint32_t size,
3533 const void* pValues)
3534 {
3535 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3536 memcpy(cmd_buffer->push_constants + offset, pValues, size);
3537 cmd_buffer->push_constant_stages |= stageFlags;
3538 }
3539
3540 VkResult radv_EndCommandBuffer(
3541 VkCommandBuffer commandBuffer)
3542 {
3543 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3544
3545 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
3546 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6)
3547 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WB_L2;
3548
3549 /* Make sure to sync all pending active queries at the end of
3550 * command buffer.
3551 */
3552 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
3553
3554 si_emit_cache_flush(cmd_buffer);
3555 }
3556
3557 /* Make sure CP DMA is idle at the end of IBs because the kernel
3558 * doesn't wait for it.
3559 */
3560 si_cp_dma_wait_for_idle(cmd_buffer);
3561
3562 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3563 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
3564
3565 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
3566 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3567
3568 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
3569
3570 return cmd_buffer->record_result;
3571 }
3572
3573 static void
3574 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
3575 {
3576 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3577
3578 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
3579 return;
3580
3581 assert(!pipeline->ctx_cs.cdw);
3582
3583 cmd_buffer->state.emitted_compute_pipeline = pipeline;
3584
3585 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
3586 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
3587
3588 cmd_buffer->compute_scratch_size_needed =
3589 MAX2(cmd_buffer->compute_scratch_size_needed,
3590 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
3591
3592 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3593 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
3594
3595 if (unlikely(cmd_buffer->device->trace_bo))
3596 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
3597 }
3598
3599 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
3600 VkPipelineBindPoint bind_point)
3601 {
3602 struct radv_descriptor_state *descriptors_state =
3603 radv_get_descriptors_state(cmd_buffer, bind_point);
3604
3605 descriptors_state->dirty |= descriptors_state->valid;
3606 }
3607
3608 void radv_CmdBindPipeline(
3609 VkCommandBuffer commandBuffer,
3610 VkPipelineBindPoint pipelineBindPoint,
3611 VkPipeline _pipeline)
3612 {
3613 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3614 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
3615
3616 switch (pipelineBindPoint) {
3617 case VK_PIPELINE_BIND_POINT_COMPUTE:
3618 if (cmd_buffer->state.compute_pipeline == pipeline)
3619 return;
3620 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3621
3622 cmd_buffer->state.compute_pipeline = pipeline;
3623 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
3624 break;
3625 case VK_PIPELINE_BIND_POINT_GRAPHICS:
3626 if (cmd_buffer->state.pipeline == pipeline)
3627 return;
3628 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3629
3630 cmd_buffer->state.pipeline = pipeline;
3631 if (!pipeline)
3632 break;
3633
3634 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
3635 cmd_buffer->push_constant_stages |= pipeline->active_stages;
3636
3637 /* the new vertex shader might not have the same user regs */
3638 cmd_buffer->state.last_first_instance = -1;
3639 cmd_buffer->state.last_vertex_offset = -1;
3640
3641 /* Prefetch all pipeline shaders at first draw time. */
3642 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
3643
3644 if ((cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI10 ||
3645 cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI12 ||
3646 cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI14) &&
3647 cmd_buffer->state.emitted_pipeline &&
3648 radv_pipeline_has_ngg(cmd_buffer->state.emitted_pipeline) &&
3649 !radv_pipeline_has_ngg(cmd_buffer->state.pipeline)) {
3650 /* Transitioning from NGG to legacy GS requires
3651 * VGT_FLUSH on Navi10-14. VGT_FLUSH is also emitted
3652 * at the beginning of IBs when legacy GS ring pointers
3653 * are set.
3654 */
3655 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
3656 }
3657
3658 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
3659 radv_bind_streamout_state(cmd_buffer, pipeline);
3660
3661 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
3662 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
3663 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
3664 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
3665
3666 if (radv_pipeline_has_tess(pipeline))
3667 cmd_buffer->tess_rings_needed = true;
3668 break;
3669 default:
3670 assert(!"invalid bind point");
3671 break;
3672 }
3673 }
3674
3675 void radv_CmdSetViewport(
3676 VkCommandBuffer commandBuffer,
3677 uint32_t firstViewport,
3678 uint32_t viewportCount,
3679 const VkViewport* pViewports)
3680 {
3681 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3682 struct radv_cmd_state *state = &cmd_buffer->state;
3683 ASSERTED const uint32_t total_count = firstViewport + viewportCount;
3684
3685 assert(firstViewport < MAX_VIEWPORTS);
3686 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
3687
3688 if (!memcmp(state->dynamic.viewport.viewports + firstViewport,
3689 pViewports, viewportCount * sizeof(*pViewports))) {
3690 return;
3691 }
3692
3693 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
3694 viewportCount * sizeof(*pViewports));
3695
3696 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
3697 }
3698
3699 void radv_CmdSetScissor(
3700 VkCommandBuffer commandBuffer,
3701 uint32_t firstScissor,
3702 uint32_t scissorCount,
3703 const VkRect2D* pScissors)
3704 {
3705 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3706 struct radv_cmd_state *state = &cmd_buffer->state;
3707 ASSERTED const uint32_t total_count = firstScissor + scissorCount;
3708
3709 assert(firstScissor < MAX_SCISSORS);
3710 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
3711
3712 if (!memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
3713 scissorCount * sizeof(*pScissors))) {
3714 return;
3715 }
3716
3717 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
3718 scissorCount * sizeof(*pScissors));
3719
3720 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
3721 }
3722
3723 void radv_CmdSetLineWidth(
3724 VkCommandBuffer commandBuffer,
3725 float lineWidth)
3726 {
3727 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3728
3729 if (cmd_buffer->state.dynamic.line_width == lineWidth)
3730 return;
3731
3732 cmd_buffer->state.dynamic.line_width = lineWidth;
3733 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
3734 }
3735
3736 void radv_CmdSetDepthBias(
3737 VkCommandBuffer commandBuffer,
3738 float depthBiasConstantFactor,
3739 float depthBiasClamp,
3740 float depthBiasSlopeFactor)
3741 {
3742 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3743 struct radv_cmd_state *state = &cmd_buffer->state;
3744
3745 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
3746 state->dynamic.depth_bias.clamp == depthBiasClamp &&
3747 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
3748 return;
3749 }
3750
3751 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
3752 state->dynamic.depth_bias.clamp = depthBiasClamp;
3753 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
3754
3755 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
3756 }
3757
3758 void radv_CmdSetBlendConstants(
3759 VkCommandBuffer commandBuffer,
3760 const float blendConstants[4])
3761 {
3762 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3763 struct radv_cmd_state *state = &cmd_buffer->state;
3764
3765 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
3766 return;
3767
3768 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
3769
3770 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
3771 }
3772
3773 void radv_CmdSetDepthBounds(
3774 VkCommandBuffer commandBuffer,
3775 float minDepthBounds,
3776 float maxDepthBounds)
3777 {
3778 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3779 struct radv_cmd_state *state = &cmd_buffer->state;
3780
3781 if (state->dynamic.depth_bounds.min == minDepthBounds &&
3782 state->dynamic.depth_bounds.max == maxDepthBounds) {
3783 return;
3784 }
3785
3786 state->dynamic.depth_bounds.min = minDepthBounds;
3787 state->dynamic.depth_bounds.max = maxDepthBounds;
3788
3789 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
3790 }
3791
3792 void radv_CmdSetStencilCompareMask(
3793 VkCommandBuffer commandBuffer,
3794 VkStencilFaceFlags faceMask,
3795 uint32_t compareMask)
3796 {
3797 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3798 struct radv_cmd_state *state = &cmd_buffer->state;
3799 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
3800 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
3801
3802 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3803 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3804 return;
3805 }
3806
3807 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3808 state->dynamic.stencil_compare_mask.front = compareMask;
3809 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3810 state->dynamic.stencil_compare_mask.back = compareMask;
3811
3812 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
3813 }
3814
3815 void radv_CmdSetStencilWriteMask(
3816 VkCommandBuffer commandBuffer,
3817 VkStencilFaceFlags faceMask,
3818 uint32_t writeMask)
3819 {
3820 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3821 struct radv_cmd_state *state = &cmd_buffer->state;
3822 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
3823 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
3824
3825 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3826 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3827 return;
3828 }
3829
3830 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3831 state->dynamic.stencil_write_mask.front = writeMask;
3832 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3833 state->dynamic.stencil_write_mask.back = writeMask;
3834
3835 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
3836 }
3837
3838 void radv_CmdSetStencilReference(
3839 VkCommandBuffer commandBuffer,
3840 VkStencilFaceFlags faceMask,
3841 uint32_t reference)
3842 {
3843 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3844 struct radv_cmd_state *state = &cmd_buffer->state;
3845 bool front_same = state->dynamic.stencil_reference.front == reference;
3846 bool back_same = state->dynamic.stencil_reference.back == reference;
3847
3848 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3849 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3850 return;
3851 }
3852
3853 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3854 cmd_buffer->state.dynamic.stencil_reference.front = reference;
3855 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3856 cmd_buffer->state.dynamic.stencil_reference.back = reference;
3857
3858 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
3859 }
3860
3861 void radv_CmdSetDiscardRectangleEXT(
3862 VkCommandBuffer commandBuffer,
3863 uint32_t firstDiscardRectangle,
3864 uint32_t discardRectangleCount,
3865 const VkRect2D* pDiscardRectangles)
3866 {
3867 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3868 struct radv_cmd_state *state = &cmd_buffer->state;
3869 ASSERTED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
3870
3871 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
3872 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
3873
3874 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
3875 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
3876 return;
3877 }
3878
3879 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
3880 pDiscardRectangles, discardRectangleCount);
3881
3882 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
3883 }
3884
3885 void radv_CmdSetSampleLocationsEXT(
3886 VkCommandBuffer commandBuffer,
3887 const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
3888 {
3889 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3890 struct radv_cmd_state *state = &cmd_buffer->state;
3891
3892 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
3893
3894 state->dynamic.sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
3895 state->dynamic.sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
3896 state->dynamic.sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
3897 typed_memcpy(&state->dynamic.sample_location.locations[0],
3898 pSampleLocationsInfo->pSampleLocations,
3899 pSampleLocationsInfo->sampleLocationsCount);
3900
3901 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS;
3902 }
3903
3904 void radv_CmdExecuteCommands(
3905 VkCommandBuffer commandBuffer,
3906 uint32_t commandBufferCount,
3907 const VkCommandBuffer* pCmdBuffers)
3908 {
3909 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
3910
3911 assert(commandBufferCount > 0);
3912
3913 /* Emit pending flushes on primary prior to executing secondary */
3914 si_emit_cache_flush(primary);
3915
3916 for (uint32_t i = 0; i < commandBufferCount; i++) {
3917 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
3918
3919 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
3920 secondary->scratch_size_needed);
3921 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
3922 secondary->compute_scratch_size_needed);
3923
3924 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
3925 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
3926 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
3927 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
3928 if (secondary->tess_rings_needed)
3929 primary->tess_rings_needed = true;
3930 if (secondary->sample_positions_needed)
3931 primary->sample_positions_needed = true;
3932
3933 if (!secondary->state.framebuffer &&
3934 (primary->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)) {
3935 /* Emit the framebuffer state from primary if secondary
3936 * has been recorded without a framebuffer, otherwise
3937 * fast color/depth clears can't work.
3938 */
3939 radv_emit_framebuffer_state(primary);
3940 }
3941
3942 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
3943
3944
3945 /* When the secondary command buffer is compute only we don't
3946 * need to re-emit the current graphics pipeline.
3947 */
3948 if (secondary->state.emitted_pipeline) {
3949 primary->state.emitted_pipeline =
3950 secondary->state.emitted_pipeline;
3951 }
3952
3953 /* When the secondary command buffer is graphics only we don't
3954 * need to re-emit the current compute pipeline.
3955 */
3956 if (secondary->state.emitted_compute_pipeline) {
3957 primary->state.emitted_compute_pipeline =
3958 secondary->state.emitted_compute_pipeline;
3959 }
3960
3961 /* Only re-emit the draw packets when needed. */
3962 if (secondary->state.last_primitive_reset_en != -1) {
3963 primary->state.last_primitive_reset_en =
3964 secondary->state.last_primitive_reset_en;
3965 }
3966
3967 if (secondary->state.last_primitive_reset_index) {
3968 primary->state.last_primitive_reset_index =
3969 secondary->state.last_primitive_reset_index;
3970 }
3971
3972 if (secondary->state.last_ia_multi_vgt_param) {
3973 primary->state.last_ia_multi_vgt_param =
3974 secondary->state.last_ia_multi_vgt_param;
3975 }
3976
3977 primary->state.last_first_instance = secondary->state.last_first_instance;
3978 primary->state.last_num_instances = secondary->state.last_num_instances;
3979 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
3980
3981 if (secondary->state.last_index_type != -1) {
3982 primary->state.last_index_type =
3983 secondary->state.last_index_type;
3984 }
3985 }
3986
3987 /* After executing commands from secondary buffers we have to dirty
3988 * some states.
3989 */
3990 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
3991 RADV_CMD_DIRTY_INDEX_BUFFER |
3992 RADV_CMD_DIRTY_DYNAMIC_ALL;
3993 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
3994 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
3995 }
3996
3997 VkResult radv_CreateCommandPool(
3998 VkDevice _device,
3999 const VkCommandPoolCreateInfo* pCreateInfo,
4000 const VkAllocationCallbacks* pAllocator,
4001 VkCommandPool* pCmdPool)
4002 {
4003 RADV_FROM_HANDLE(radv_device, device, _device);
4004 struct radv_cmd_pool *pool;
4005
4006 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
4007 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4008 if (pool == NULL)
4009 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4010
4011 if (pAllocator)
4012 pool->alloc = *pAllocator;
4013 else
4014 pool->alloc = device->alloc;
4015
4016 list_inithead(&pool->cmd_buffers);
4017 list_inithead(&pool->free_cmd_buffers);
4018
4019 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
4020
4021 *pCmdPool = radv_cmd_pool_to_handle(pool);
4022
4023 return VK_SUCCESS;
4024
4025 }
4026
4027 void radv_DestroyCommandPool(
4028 VkDevice _device,
4029 VkCommandPool commandPool,
4030 const VkAllocationCallbacks* pAllocator)
4031 {
4032 RADV_FROM_HANDLE(radv_device, device, _device);
4033 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4034
4035 if (!pool)
4036 return;
4037
4038 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4039 &pool->cmd_buffers, pool_link) {
4040 radv_cmd_buffer_destroy(cmd_buffer);
4041 }
4042
4043 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4044 &pool->free_cmd_buffers, pool_link) {
4045 radv_cmd_buffer_destroy(cmd_buffer);
4046 }
4047
4048 vk_free2(&device->alloc, pAllocator, pool);
4049 }
4050
4051 VkResult radv_ResetCommandPool(
4052 VkDevice device,
4053 VkCommandPool commandPool,
4054 VkCommandPoolResetFlags flags)
4055 {
4056 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4057 VkResult result;
4058
4059 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
4060 &pool->cmd_buffers, pool_link) {
4061 result = radv_reset_cmd_buffer(cmd_buffer);
4062 if (result != VK_SUCCESS)
4063 return result;
4064 }
4065
4066 return VK_SUCCESS;
4067 }
4068
4069 void radv_TrimCommandPool(
4070 VkDevice device,
4071 VkCommandPool commandPool,
4072 VkCommandPoolTrimFlags flags)
4073 {
4074 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4075
4076 if (!pool)
4077 return;
4078
4079 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4080 &pool->free_cmd_buffers, pool_link) {
4081 radv_cmd_buffer_destroy(cmd_buffer);
4082 }
4083 }
4084
4085 static void
4086 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
4087 uint32_t subpass_id)
4088 {
4089 struct radv_cmd_state *state = &cmd_buffer->state;
4090 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
4091
4092 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
4093 cmd_buffer->cs, 4096);
4094
4095 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
4096
4097 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
4098
4099 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4100 const uint32_t a = subpass->attachments[i].attachment;
4101 if (a == VK_ATTACHMENT_UNUSED)
4102 continue;
4103
4104 radv_handle_subpass_image_transition(cmd_buffer,
4105 subpass->attachments[i],
4106 true);
4107 }
4108
4109 radv_cmd_buffer_clear_subpass(cmd_buffer);
4110
4111 assert(cmd_buffer->cs->cdw <= cdw_max);
4112 }
4113
4114 static void
4115 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
4116 {
4117 struct radv_cmd_state *state = &cmd_buffer->state;
4118 const struct radv_subpass *subpass = state->subpass;
4119 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
4120
4121 radv_cmd_buffer_resolve_subpass(cmd_buffer);
4122
4123 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4124 const uint32_t a = subpass->attachments[i].attachment;
4125 if (a == VK_ATTACHMENT_UNUSED)
4126 continue;
4127
4128 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
4129 continue;
4130
4131 VkImageLayout layout = state->pass->attachments[a].final_layout;
4132 struct radv_subpass_attachment att = { a, layout };
4133 radv_handle_subpass_image_transition(cmd_buffer, att, false);
4134 }
4135 }
4136
4137 void radv_CmdBeginRenderPass(
4138 VkCommandBuffer commandBuffer,
4139 const VkRenderPassBeginInfo* pRenderPassBegin,
4140 VkSubpassContents contents)
4141 {
4142 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4143 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
4144 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
4145 VkResult result;
4146
4147 cmd_buffer->state.framebuffer = framebuffer;
4148 cmd_buffer->state.pass = pass;
4149 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
4150
4151 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
4152 if (result != VK_SUCCESS)
4153 return;
4154
4155 result = radv_cmd_state_setup_sample_locations(cmd_buffer, pass, pRenderPassBegin);
4156 if (result != VK_SUCCESS)
4157 return;
4158
4159 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
4160 }
4161
4162 void radv_CmdBeginRenderPass2KHR(
4163 VkCommandBuffer commandBuffer,
4164 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
4165 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
4166 {
4167 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
4168 pSubpassBeginInfo->contents);
4169 }
4170
4171 void radv_CmdNextSubpass(
4172 VkCommandBuffer commandBuffer,
4173 VkSubpassContents contents)
4174 {
4175 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4176
4177 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
4178 radv_cmd_buffer_end_subpass(cmd_buffer);
4179 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
4180 }
4181
4182 void radv_CmdNextSubpass2KHR(
4183 VkCommandBuffer commandBuffer,
4184 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
4185 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4186 {
4187 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
4188 }
4189
4190 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
4191 {
4192 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
4193 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
4194 if (!radv_get_shader(pipeline, stage))
4195 continue;
4196
4197 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
4198 if (loc->sgpr_idx == -1)
4199 continue;
4200 uint32_t base_reg = pipeline->user_data_0[stage];
4201 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4202
4203 }
4204 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
4205 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
4206 if (loc->sgpr_idx != -1) {
4207 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
4208 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4209 }
4210 }
4211 }
4212
4213 static void
4214 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4215 uint32_t vertex_count,
4216 bool use_opaque)
4217 {
4218 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
4219 radeon_emit(cmd_buffer->cs, vertex_count);
4220 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
4221 S_0287F0_USE_OPAQUE(use_opaque));
4222 }
4223
4224 static void
4225 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
4226 uint64_t index_va,
4227 uint32_t index_count)
4228 {
4229 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
4230 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
4231 radeon_emit(cmd_buffer->cs, index_va);
4232 radeon_emit(cmd_buffer->cs, index_va >> 32);
4233 radeon_emit(cmd_buffer->cs, index_count);
4234 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
4235 }
4236
4237 static void
4238 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4239 bool indexed,
4240 uint32_t draw_count,
4241 uint64_t count_va,
4242 uint32_t stride)
4243 {
4244 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4245 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
4246 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
4247 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
4248 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
4249 bool predicating = cmd_buffer->state.predicating;
4250 assert(base_reg);
4251
4252 /* just reset draw state for vertex data */
4253 cmd_buffer->state.last_first_instance = -1;
4254 cmd_buffer->state.last_num_instances = -1;
4255 cmd_buffer->state.last_vertex_offset = -1;
4256
4257 if (draw_count == 1 && !count_va && !draw_id_enable) {
4258 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
4259 PKT3_DRAW_INDIRECT, 3, predicating));
4260 radeon_emit(cs, 0);
4261 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4262 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4263 radeon_emit(cs, di_src_sel);
4264 } else {
4265 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
4266 PKT3_DRAW_INDIRECT_MULTI,
4267 8, predicating));
4268 radeon_emit(cs, 0);
4269 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4270 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4271 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
4272 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
4273 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
4274 radeon_emit(cs, draw_count); /* count */
4275 radeon_emit(cs, count_va); /* count_addr */
4276 radeon_emit(cs, count_va >> 32);
4277 radeon_emit(cs, stride); /* stride */
4278 radeon_emit(cs, di_src_sel);
4279 }
4280 }
4281
4282 static void
4283 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
4284 const struct radv_draw_info *info)
4285 {
4286 struct radv_cmd_state *state = &cmd_buffer->state;
4287 struct radeon_winsys *ws = cmd_buffer->device->ws;
4288 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4289
4290 if (info->indirect) {
4291 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4292 uint64_t count_va = 0;
4293
4294 va += info->indirect->offset + info->indirect_offset;
4295
4296 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4297
4298 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
4299 radeon_emit(cs, 1);
4300 radeon_emit(cs, va);
4301 radeon_emit(cs, va >> 32);
4302
4303 if (info->count_buffer) {
4304 count_va = radv_buffer_get_va(info->count_buffer->bo);
4305 count_va += info->count_buffer->offset +
4306 info->count_buffer_offset;
4307
4308 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
4309 }
4310
4311 if (!state->subpass->view_mask) {
4312 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4313 info->indexed,
4314 info->count,
4315 count_va,
4316 info->stride);
4317 } else {
4318 unsigned i;
4319 for_each_bit(i, state->subpass->view_mask) {
4320 radv_emit_view_index(cmd_buffer, i);
4321
4322 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4323 info->indexed,
4324 info->count,
4325 count_va,
4326 info->stride);
4327 }
4328 }
4329 } else {
4330 assert(state->pipeline->graphics.vtx_base_sgpr);
4331
4332 if (info->vertex_offset != state->last_vertex_offset ||
4333 info->first_instance != state->last_first_instance) {
4334 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
4335 state->pipeline->graphics.vtx_emit_num);
4336
4337 radeon_emit(cs, info->vertex_offset);
4338 radeon_emit(cs, info->first_instance);
4339 if (state->pipeline->graphics.vtx_emit_num == 3)
4340 radeon_emit(cs, 0);
4341 state->last_first_instance = info->first_instance;
4342 state->last_vertex_offset = info->vertex_offset;
4343 }
4344
4345 if (state->last_num_instances != info->instance_count) {
4346 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
4347 radeon_emit(cs, info->instance_count);
4348 state->last_num_instances = info->instance_count;
4349 }
4350
4351 if (info->indexed) {
4352 int index_size = radv_get_vgt_index_size(state->index_type);
4353 uint64_t index_va;
4354
4355 /* Skip draw calls with 0-sized index buffers. They
4356 * cause a hang on some chips, like Navi10-14.
4357 */
4358 if (!cmd_buffer->state.max_index_count)
4359 return;
4360
4361 index_va = state->index_va;
4362 index_va += info->first_index * index_size;
4363
4364 if (!state->subpass->view_mask) {
4365 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4366 index_va,
4367 info->count);
4368 } else {
4369 unsigned i;
4370 for_each_bit(i, state->subpass->view_mask) {
4371 radv_emit_view_index(cmd_buffer, i);
4372
4373 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4374 index_va,
4375 info->count);
4376 }
4377 }
4378 } else {
4379 if (!state->subpass->view_mask) {
4380 radv_cs_emit_draw_packet(cmd_buffer,
4381 info->count,
4382 !!info->strmout_buffer);
4383 } else {
4384 unsigned i;
4385 for_each_bit(i, state->subpass->view_mask) {
4386 radv_emit_view_index(cmd_buffer, i);
4387
4388 radv_cs_emit_draw_packet(cmd_buffer,
4389 info->count,
4390 !!info->strmout_buffer);
4391 }
4392 }
4393 }
4394 }
4395 }
4396
4397 /*
4398 * Vega and raven have a bug which triggers if there are multiple context
4399 * register contexts active at the same time with different scissor values.
4400 *
4401 * There are two possible workarounds:
4402 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
4403 * there is only ever 1 active set of scissor values at the same time.
4404 *
4405 * 2) Whenever the hardware switches contexts we have to set the scissor
4406 * registers again even if it is a noop. That way the new context gets
4407 * the correct scissor values.
4408 *
4409 * This implements option 2. radv_need_late_scissor_emission needs to
4410 * return true on affected HW if radv_emit_all_graphics_states sets
4411 * any context registers.
4412 */
4413 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
4414 const struct radv_draw_info *info)
4415 {
4416 struct radv_cmd_state *state = &cmd_buffer->state;
4417
4418 if (!cmd_buffer->device->physical_device->has_scissor_bug)
4419 return false;
4420
4421 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
4422 return true;
4423
4424 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
4425
4426 /* Index, vertex and streamout buffers don't change context regs, and
4427 * pipeline is already handled.
4428 */
4429 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
4430 RADV_CMD_DIRTY_VERTEX_BUFFER |
4431 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
4432 RADV_CMD_DIRTY_PIPELINE);
4433
4434 if (cmd_buffer->state.dirty & used_states)
4435 return true;
4436
4437 uint32_t primitive_reset_index =
4438 radv_get_primitive_reset_index(cmd_buffer);
4439
4440 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
4441 primitive_reset_index != state->last_primitive_reset_index)
4442 return true;
4443
4444 return false;
4445 }
4446
4447 static void
4448 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
4449 const struct radv_draw_info *info)
4450 {
4451 bool late_scissor_emission;
4452
4453 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
4454 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
4455 radv_emit_rbplus_state(cmd_buffer);
4456
4457 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
4458 radv_emit_graphics_pipeline(cmd_buffer);
4459
4460 /* This should be before the cmd_buffer->state.dirty is cleared
4461 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4462 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4463 late_scissor_emission =
4464 radv_need_late_scissor_emission(cmd_buffer, info);
4465
4466 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
4467 radv_emit_framebuffer_state(cmd_buffer);
4468
4469 if (info->indexed) {
4470 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
4471 radv_emit_index_buffer(cmd_buffer);
4472 } else {
4473 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4474 * so the state must be re-emitted before the next indexed
4475 * draw.
4476 */
4477 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
4478 cmd_buffer->state.last_index_type = -1;
4479 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
4480 }
4481 }
4482
4483 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
4484
4485 radv_emit_draw_registers(cmd_buffer, info);
4486
4487 if (late_scissor_emission)
4488 radv_emit_scissor(cmd_buffer);
4489 }
4490
4491 static void
4492 radv_draw(struct radv_cmd_buffer *cmd_buffer,
4493 const struct radv_draw_info *info)
4494 {
4495 struct radeon_info *rad_info =
4496 &cmd_buffer->device->physical_device->rad_info;
4497 bool has_prefetch =
4498 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4499 bool pipeline_is_dirty =
4500 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
4501 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
4502
4503 ASSERTED unsigned cdw_max =
4504 radeon_check_space(cmd_buffer->device->ws,
4505 cmd_buffer->cs, 4096);
4506
4507 if (likely(!info->indirect)) {
4508 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4509 * no workaround for indirect draws, but we can at least skip
4510 * direct draws.
4511 */
4512 if (unlikely(!info->instance_count))
4513 return;
4514
4515 /* Handle count == 0. */
4516 if (unlikely(!info->count && !info->strmout_buffer))
4517 return;
4518 }
4519
4520 /* Use optimal packet order based on whether we need to sync the
4521 * pipeline.
4522 */
4523 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4524 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4525 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4526 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4527 /* If we have to wait for idle, set all states first, so that
4528 * all SET packets are processed in parallel with previous draw
4529 * calls. Then upload descriptors, set shader pointers, and
4530 * draw, and prefetch at the end. This ensures that the time
4531 * the CUs are idle is very short. (there are only SET_SH
4532 * packets between the wait and the draw)
4533 */
4534 radv_emit_all_graphics_states(cmd_buffer, info);
4535 si_emit_cache_flush(cmd_buffer);
4536 /* <-- CUs are idle here --> */
4537
4538 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4539
4540 radv_emit_draw_packets(cmd_buffer, info);
4541 /* <-- CUs are busy here --> */
4542
4543 /* Start prefetches after the draw has been started. Both will
4544 * run in parallel, but starting the draw first is more
4545 * important.
4546 */
4547 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4548 radv_emit_prefetch_L2(cmd_buffer,
4549 cmd_buffer->state.pipeline, false);
4550 }
4551 } else {
4552 /* If we don't wait for idle, start prefetches first, then set
4553 * states, and draw at the end.
4554 */
4555 si_emit_cache_flush(cmd_buffer);
4556
4557 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4558 /* Only prefetch the vertex shader and VBO descriptors
4559 * in order to start the draw as soon as possible.
4560 */
4561 radv_emit_prefetch_L2(cmd_buffer,
4562 cmd_buffer->state.pipeline, true);
4563 }
4564
4565 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4566
4567 radv_emit_all_graphics_states(cmd_buffer, info);
4568 radv_emit_draw_packets(cmd_buffer, info);
4569
4570 /* Prefetch the remaining shaders after the draw has been
4571 * started.
4572 */
4573 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4574 radv_emit_prefetch_L2(cmd_buffer,
4575 cmd_buffer->state.pipeline, false);
4576 }
4577 }
4578
4579 /* Workaround for a VGT hang when streamout is enabled.
4580 * It must be done after drawing.
4581 */
4582 if (cmd_buffer->state.streamout.streamout_enabled &&
4583 (rad_info->family == CHIP_HAWAII ||
4584 rad_info->family == CHIP_TONGA ||
4585 rad_info->family == CHIP_FIJI)) {
4586 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
4587 }
4588
4589 assert(cmd_buffer->cs->cdw <= cdw_max);
4590 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
4591 }
4592
4593 void radv_CmdDraw(
4594 VkCommandBuffer commandBuffer,
4595 uint32_t vertexCount,
4596 uint32_t instanceCount,
4597 uint32_t firstVertex,
4598 uint32_t firstInstance)
4599 {
4600 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4601 struct radv_draw_info info = {};
4602
4603 info.count = vertexCount;
4604 info.instance_count = instanceCount;
4605 info.first_instance = firstInstance;
4606 info.vertex_offset = firstVertex;
4607
4608 radv_draw(cmd_buffer, &info);
4609 }
4610
4611 void radv_CmdDrawIndexed(
4612 VkCommandBuffer commandBuffer,
4613 uint32_t indexCount,
4614 uint32_t instanceCount,
4615 uint32_t firstIndex,
4616 int32_t vertexOffset,
4617 uint32_t firstInstance)
4618 {
4619 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4620 struct radv_draw_info info = {};
4621
4622 info.indexed = true;
4623 info.count = indexCount;
4624 info.instance_count = instanceCount;
4625 info.first_index = firstIndex;
4626 info.vertex_offset = vertexOffset;
4627 info.first_instance = firstInstance;
4628
4629 radv_draw(cmd_buffer, &info);
4630 }
4631
4632 void radv_CmdDrawIndirect(
4633 VkCommandBuffer commandBuffer,
4634 VkBuffer _buffer,
4635 VkDeviceSize offset,
4636 uint32_t drawCount,
4637 uint32_t stride)
4638 {
4639 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4640 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4641 struct radv_draw_info info = {};
4642
4643 info.count = drawCount;
4644 info.indirect = buffer;
4645 info.indirect_offset = offset;
4646 info.stride = stride;
4647
4648 radv_draw(cmd_buffer, &info);
4649 }
4650
4651 void radv_CmdDrawIndexedIndirect(
4652 VkCommandBuffer commandBuffer,
4653 VkBuffer _buffer,
4654 VkDeviceSize offset,
4655 uint32_t drawCount,
4656 uint32_t stride)
4657 {
4658 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4659 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4660 struct radv_draw_info info = {};
4661
4662 info.indexed = true;
4663 info.count = drawCount;
4664 info.indirect = buffer;
4665 info.indirect_offset = offset;
4666 info.stride = stride;
4667
4668 radv_draw(cmd_buffer, &info);
4669 }
4670
4671 void radv_CmdDrawIndirectCountKHR(
4672 VkCommandBuffer commandBuffer,
4673 VkBuffer _buffer,
4674 VkDeviceSize offset,
4675 VkBuffer _countBuffer,
4676 VkDeviceSize countBufferOffset,
4677 uint32_t maxDrawCount,
4678 uint32_t stride)
4679 {
4680 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4681 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4682 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4683 struct radv_draw_info info = {};
4684
4685 info.count = maxDrawCount;
4686 info.indirect = buffer;
4687 info.indirect_offset = offset;
4688 info.count_buffer = count_buffer;
4689 info.count_buffer_offset = countBufferOffset;
4690 info.stride = stride;
4691
4692 radv_draw(cmd_buffer, &info);
4693 }
4694
4695 void radv_CmdDrawIndexedIndirectCountKHR(
4696 VkCommandBuffer commandBuffer,
4697 VkBuffer _buffer,
4698 VkDeviceSize offset,
4699 VkBuffer _countBuffer,
4700 VkDeviceSize countBufferOffset,
4701 uint32_t maxDrawCount,
4702 uint32_t stride)
4703 {
4704 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4705 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4706 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4707 struct radv_draw_info info = {};
4708
4709 info.indexed = true;
4710 info.count = maxDrawCount;
4711 info.indirect = buffer;
4712 info.indirect_offset = offset;
4713 info.count_buffer = count_buffer;
4714 info.count_buffer_offset = countBufferOffset;
4715 info.stride = stride;
4716
4717 radv_draw(cmd_buffer, &info);
4718 }
4719
4720 struct radv_dispatch_info {
4721 /**
4722 * Determine the layout of the grid (in block units) to be used.
4723 */
4724 uint32_t blocks[3];
4725
4726 /**
4727 * A starting offset for the grid. If unaligned is set, the offset
4728 * must still be aligned.
4729 */
4730 uint32_t offsets[3];
4731 /**
4732 * Whether it's an unaligned compute dispatch.
4733 */
4734 bool unaligned;
4735
4736 /**
4737 * Indirect compute parameters resource.
4738 */
4739 struct radv_buffer *indirect;
4740 uint64_t indirect_offset;
4741 };
4742
4743 static void
4744 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
4745 const struct radv_dispatch_info *info)
4746 {
4747 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4748 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4749 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
4750 struct radeon_winsys *ws = cmd_buffer->device->ws;
4751 bool predicating = cmd_buffer->state.predicating;
4752 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4753 struct radv_userdata_info *loc;
4754
4755 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
4756 AC_UD_CS_GRID_SIZE);
4757
4758 ASSERTED unsigned cdw_max = radeon_check_space(ws, cs, 25);
4759
4760 if (info->indirect) {
4761 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4762
4763 va += info->indirect->offset + info->indirect_offset;
4764
4765 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4766
4767 if (loc->sgpr_idx != -1) {
4768 for (unsigned i = 0; i < 3; ++i) {
4769 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
4770 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
4771 COPY_DATA_DST_SEL(COPY_DATA_REG));
4772 radeon_emit(cs, (va + 4 * i));
4773 radeon_emit(cs, (va + 4 * i) >> 32);
4774 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
4775 + loc->sgpr_idx * 4) >> 2) + i);
4776 radeon_emit(cs, 0);
4777 }
4778 }
4779
4780 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
4781 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
4782 PKT3_SHADER_TYPE_S(1));
4783 radeon_emit(cs, va);
4784 radeon_emit(cs, va >> 32);
4785 radeon_emit(cs, dispatch_initiator);
4786 } else {
4787 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
4788 PKT3_SHADER_TYPE_S(1));
4789 radeon_emit(cs, 1);
4790 radeon_emit(cs, va);
4791 radeon_emit(cs, va >> 32);
4792
4793 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
4794 PKT3_SHADER_TYPE_S(1));
4795 radeon_emit(cs, 0);
4796 radeon_emit(cs, dispatch_initiator);
4797 }
4798 } else {
4799 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
4800 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
4801
4802 if (info->unaligned) {
4803 unsigned *cs_block_size = compute_shader->info.cs.block_size;
4804 unsigned remainder[3];
4805
4806 /* If aligned, these should be an entire block size,
4807 * not 0.
4808 */
4809 remainder[0] = blocks[0] + cs_block_size[0] -
4810 align_u32_npot(blocks[0], cs_block_size[0]);
4811 remainder[1] = blocks[1] + cs_block_size[1] -
4812 align_u32_npot(blocks[1], cs_block_size[1]);
4813 remainder[2] = blocks[2] + cs_block_size[2] -
4814 align_u32_npot(blocks[2], cs_block_size[2]);
4815
4816 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
4817 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
4818 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
4819
4820 for(unsigned i = 0; i < 3; ++i) {
4821 assert(offsets[i] % cs_block_size[i] == 0);
4822 offsets[i] /= cs_block_size[i];
4823 }
4824
4825 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4826 radeon_emit(cs,
4827 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
4828 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
4829 radeon_emit(cs,
4830 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
4831 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
4832 radeon_emit(cs,
4833 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
4834 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
4835
4836 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
4837 }
4838
4839 if (loc->sgpr_idx != -1) {
4840 assert(loc->num_sgprs == 3);
4841
4842 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
4843 loc->sgpr_idx * 4, 3);
4844 radeon_emit(cs, blocks[0]);
4845 radeon_emit(cs, blocks[1]);
4846 radeon_emit(cs, blocks[2]);
4847 }
4848
4849 if (offsets[0] || offsets[1] || offsets[2]) {
4850 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
4851 radeon_emit(cs, offsets[0]);
4852 radeon_emit(cs, offsets[1]);
4853 radeon_emit(cs, offsets[2]);
4854
4855 /* The blocks in the packet are not counts but end values. */
4856 for (unsigned i = 0; i < 3; ++i)
4857 blocks[i] += offsets[i];
4858 } else {
4859 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
4860 }
4861
4862 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
4863 PKT3_SHADER_TYPE_S(1));
4864 radeon_emit(cs, blocks[0]);
4865 radeon_emit(cs, blocks[1]);
4866 radeon_emit(cs, blocks[2]);
4867 radeon_emit(cs, dispatch_initiator);
4868 }
4869
4870 assert(cmd_buffer->cs->cdw <= cdw_max);
4871 }
4872
4873 static void
4874 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
4875 {
4876 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4877 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4878 }
4879
4880 static void
4881 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
4882 const struct radv_dispatch_info *info)
4883 {
4884 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4885 bool has_prefetch =
4886 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4887 bool pipeline_is_dirty = pipeline &&
4888 pipeline != cmd_buffer->state.emitted_compute_pipeline;
4889
4890 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4891 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4892 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4893 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4894 /* If we have to wait for idle, set all states first, so that
4895 * all SET packets are processed in parallel with previous draw
4896 * calls. Then upload descriptors, set shader pointers, and
4897 * dispatch, and prefetch at the end. This ensures that the
4898 * time the CUs are idle is very short. (there are only SET_SH
4899 * packets between the wait and the draw)
4900 */
4901 radv_emit_compute_pipeline(cmd_buffer);
4902 si_emit_cache_flush(cmd_buffer);
4903 /* <-- CUs are idle here --> */
4904
4905 radv_upload_compute_shader_descriptors(cmd_buffer);
4906
4907 radv_emit_dispatch_packets(cmd_buffer, info);
4908 /* <-- CUs are busy here --> */
4909
4910 /* Start prefetches after the dispatch has been started. Both
4911 * will run in parallel, but starting the dispatch first is
4912 * more important.
4913 */
4914 if (has_prefetch && pipeline_is_dirty) {
4915 radv_emit_shader_prefetch(cmd_buffer,
4916 pipeline->shaders[MESA_SHADER_COMPUTE]);
4917 }
4918 } else {
4919 /* If we don't wait for idle, start prefetches first, then set
4920 * states, and dispatch at the end.
4921 */
4922 si_emit_cache_flush(cmd_buffer);
4923
4924 if (has_prefetch && pipeline_is_dirty) {
4925 radv_emit_shader_prefetch(cmd_buffer,
4926 pipeline->shaders[MESA_SHADER_COMPUTE]);
4927 }
4928
4929 radv_upload_compute_shader_descriptors(cmd_buffer);
4930
4931 radv_emit_compute_pipeline(cmd_buffer);
4932 radv_emit_dispatch_packets(cmd_buffer, info);
4933 }
4934
4935 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
4936 }
4937
4938 void radv_CmdDispatchBase(
4939 VkCommandBuffer commandBuffer,
4940 uint32_t base_x,
4941 uint32_t base_y,
4942 uint32_t base_z,
4943 uint32_t x,
4944 uint32_t y,
4945 uint32_t z)
4946 {
4947 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4948 struct radv_dispatch_info info = {};
4949
4950 info.blocks[0] = x;
4951 info.blocks[1] = y;
4952 info.blocks[2] = z;
4953
4954 info.offsets[0] = base_x;
4955 info.offsets[1] = base_y;
4956 info.offsets[2] = base_z;
4957 radv_dispatch(cmd_buffer, &info);
4958 }
4959
4960 void radv_CmdDispatch(
4961 VkCommandBuffer commandBuffer,
4962 uint32_t x,
4963 uint32_t y,
4964 uint32_t z)
4965 {
4966 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
4967 }
4968
4969 void radv_CmdDispatchIndirect(
4970 VkCommandBuffer commandBuffer,
4971 VkBuffer _buffer,
4972 VkDeviceSize offset)
4973 {
4974 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4975 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4976 struct radv_dispatch_info info = {};
4977
4978 info.indirect = buffer;
4979 info.indirect_offset = offset;
4980
4981 radv_dispatch(cmd_buffer, &info);
4982 }
4983
4984 void radv_unaligned_dispatch(
4985 struct radv_cmd_buffer *cmd_buffer,
4986 uint32_t x,
4987 uint32_t y,
4988 uint32_t z)
4989 {
4990 struct radv_dispatch_info info = {};
4991
4992 info.blocks[0] = x;
4993 info.blocks[1] = y;
4994 info.blocks[2] = z;
4995 info.unaligned = 1;
4996
4997 radv_dispatch(cmd_buffer, &info);
4998 }
4999
5000 void radv_CmdEndRenderPass(
5001 VkCommandBuffer commandBuffer)
5002 {
5003 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5004
5005 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
5006
5007 radv_cmd_buffer_end_subpass(cmd_buffer);
5008
5009 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
5010 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
5011
5012 cmd_buffer->state.pass = NULL;
5013 cmd_buffer->state.subpass = NULL;
5014 cmd_buffer->state.attachments = NULL;
5015 cmd_buffer->state.framebuffer = NULL;
5016 cmd_buffer->state.subpass_sample_locs = NULL;
5017 }
5018
5019 void radv_CmdEndRenderPass2KHR(
5020 VkCommandBuffer commandBuffer,
5021 const VkSubpassEndInfoKHR* pSubpassEndInfo)
5022 {
5023 radv_CmdEndRenderPass(commandBuffer);
5024 }
5025
5026 /*
5027 * For HTILE we have the following interesting clear words:
5028 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
5029 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
5030 * 0xfffffff0: Clear depth to 1.0
5031 * 0x00000000: Clear depth to 0.0
5032 */
5033 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
5034 struct radv_image *image,
5035 const VkImageSubresourceRange *range,
5036 uint32_t clear_word)
5037 {
5038 assert(range->baseMipLevel == 0);
5039 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
5040 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
5041 struct radv_cmd_state *state = &cmd_buffer->state;
5042 VkClearDepthStencilValue value = {};
5043
5044 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5045 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5046
5047 state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, clear_word);
5048
5049 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5050
5051 if (vk_format_is_stencil(image->vk_format))
5052 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
5053
5054 radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
5055
5056 if (radv_image_is_tc_compat_htile(image)) {
5057 /* Initialize the TC-compat metada value to 0 because by
5058 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
5059 * need have to conditionally update its value when performing
5060 * a fast depth clear.
5061 */
5062 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, 0);
5063 }
5064 }
5065
5066 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
5067 struct radv_image *image,
5068 VkImageLayout src_layout,
5069 VkImageLayout dst_layout,
5070 unsigned src_queue_mask,
5071 unsigned dst_queue_mask,
5072 const VkImageSubresourceRange *range,
5073 struct radv_sample_locations_state *sample_locs)
5074 {
5075 if (!radv_image_has_htile(image))
5076 return;
5077
5078 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5079 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
5080
5081 if (radv_layout_is_htile_compressed(image, dst_layout,
5082 dst_queue_mask)) {
5083 clear_value = 0;
5084 }
5085
5086 radv_initialize_htile(cmd_buffer, image, range, clear_value);
5087 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
5088 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
5089 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
5090 radv_initialize_htile(cmd_buffer, image, range, clear_value);
5091 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
5092 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
5093 VkImageSubresourceRange local_range = *range;
5094 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
5095 local_range.baseMipLevel = 0;
5096 local_range.levelCount = 1;
5097
5098 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5099 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5100
5101 radv_decompress_depth_image_inplace(cmd_buffer, image,
5102 &local_range, sample_locs);
5103
5104 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5105 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5106 }
5107 }
5108
5109 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
5110 struct radv_image *image,
5111 const VkImageSubresourceRange *range,
5112 uint32_t value)
5113 {
5114 struct radv_cmd_state *state = &cmd_buffer->state;
5115
5116 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5117 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5118
5119 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, range, value);
5120
5121 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5122 }
5123
5124 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
5125 struct radv_image *image,
5126 const VkImageSubresourceRange *range)
5127 {
5128 struct radv_cmd_state *state = &cmd_buffer->state;
5129 static const uint32_t fmask_clear_values[4] = {
5130 0x00000000,
5131 0x02020202,
5132 0xE4E4E4E4,
5133 0x76543210
5134 };
5135 uint32_t log2_samples = util_logbase2(image->info.samples);
5136 uint32_t value = fmask_clear_values[log2_samples];
5137
5138 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5139 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5140
5141 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, range, value);
5142
5143 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5144 }
5145
5146 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
5147 struct radv_image *image,
5148 const VkImageSubresourceRange *range, uint32_t value)
5149 {
5150 struct radv_cmd_state *state = &cmd_buffer->state;
5151 unsigned size = 0;
5152
5153 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5154 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5155
5156 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
5157
5158 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) {
5159 /* When DCC is enabled with mipmaps, some levels might not
5160 * support fast clears and we have to initialize them as "fully
5161 * expanded".
5162 */
5163 /* Compute the size of all fast clearable DCC levels. */
5164 for (unsigned i = 0; i < image->planes[0].surface.num_dcc_levels; i++) {
5165 struct legacy_surf_level *surf_level =
5166 &image->planes[0].surface.u.legacy.level[i];
5167 unsigned dcc_fast_clear_size =
5168 surf_level->dcc_slice_fast_clear_size * image->info.array_size;
5169
5170 if (!dcc_fast_clear_size)
5171 break;
5172
5173 size = surf_level->dcc_offset + dcc_fast_clear_size;
5174 }
5175
5176 /* Initialize the mipmap levels without DCC. */
5177 if (size != image->planes[0].surface.dcc_size) {
5178 state->flush_bits |=
5179 radv_fill_buffer(cmd_buffer, image->bo,
5180 image->offset + image->dcc_offset + size,
5181 image->planes[0].surface.dcc_size - size,
5182 0xffffffff);
5183 }
5184 }
5185
5186 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5187 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5188 }
5189
5190 /**
5191 * Initialize DCC/FMASK/CMASK metadata for a color image.
5192 */
5193 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
5194 struct radv_image *image,
5195 VkImageLayout src_layout,
5196 VkImageLayout dst_layout,
5197 unsigned src_queue_mask,
5198 unsigned dst_queue_mask,
5199 const VkImageSubresourceRange *range)
5200 {
5201 if (radv_image_has_cmask(image)) {
5202 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5203
5204 /* TODO: clarify this. */
5205 if (radv_image_has_fmask(image)) {
5206 value = 0xccccccccu;
5207 }
5208
5209 radv_initialise_cmask(cmd_buffer, image, range, value);
5210 }
5211
5212 if (radv_image_has_fmask(image)) {
5213 radv_initialize_fmask(cmd_buffer, image, range);
5214 }
5215
5216 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5217 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5218 bool need_decompress_pass = false;
5219
5220 if (radv_layout_dcc_compressed(image, dst_layout,
5221 dst_queue_mask)) {
5222 value = 0x20202020u;
5223 need_decompress_pass = true;
5224 }
5225
5226 radv_initialize_dcc(cmd_buffer, image, range, value);
5227
5228 radv_update_fce_metadata(cmd_buffer, image, range,
5229 need_decompress_pass);
5230 }
5231
5232 if (radv_image_has_cmask(image) ||
5233 radv_dcc_enabled(image, range->baseMipLevel)) {
5234 uint32_t color_values[2] = {};
5235 radv_set_color_clear_metadata(cmd_buffer, image, range,
5236 color_values);
5237 }
5238 }
5239
5240 /**
5241 * Handle color image transitions for DCC/FMASK/CMASK.
5242 */
5243 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
5244 struct radv_image *image,
5245 VkImageLayout src_layout,
5246 VkImageLayout dst_layout,
5247 unsigned src_queue_mask,
5248 unsigned dst_queue_mask,
5249 const VkImageSubresourceRange *range)
5250 {
5251 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5252 radv_init_color_image_metadata(cmd_buffer, image,
5253 src_layout, dst_layout,
5254 src_queue_mask, dst_queue_mask,
5255 range);
5256 return;
5257 }
5258
5259 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5260 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
5261 radv_initialize_dcc(cmd_buffer, image, range, 0xffffffffu);
5262 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
5263 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
5264 radv_decompress_dcc(cmd_buffer, image, range);
5265 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
5266 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
5267 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5268 }
5269 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
5270 bool fce_eliminate = false, fmask_expand = false;
5271
5272 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
5273 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
5274 fce_eliminate = true;
5275 }
5276
5277 if (radv_image_has_fmask(image)) {
5278 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
5279 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
5280 /* A FMASK decompress is required before doing
5281 * a MSAA decompress using FMASK.
5282 */
5283 fmask_expand = true;
5284 }
5285 }
5286
5287 if (fce_eliminate || fmask_expand)
5288 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5289
5290 if (fmask_expand)
5291 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
5292 }
5293 }
5294
5295 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
5296 struct radv_image *image,
5297 VkImageLayout src_layout,
5298 VkImageLayout dst_layout,
5299 uint32_t src_family,
5300 uint32_t dst_family,
5301 const VkImageSubresourceRange *range,
5302 struct radv_sample_locations_state *sample_locs)
5303 {
5304 if (image->exclusive && src_family != dst_family) {
5305 /* This is an acquire or a release operation and there will be
5306 * a corresponding release/acquire. Do the transition in the
5307 * most flexible queue. */
5308
5309 assert(src_family == cmd_buffer->queue_family_index ||
5310 dst_family == cmd_buffer->queue_family_index);
5311
5312 if (src_family == VK_QUEUE_FAMILY_EXTERNAL ||
5313 src_family == VK_QUEUE_FAMILY_FOREIGN_EXT)
5314 return;
5315
5316 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
5317 return;
5318
5319 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
5320 (src_family == RADV_QUEUE_GENERAL ||
5321 dst_family == RADV_QUEUE_GENERAL))
5322 return;
5323 }
5324
5325 if (src_layout == dst_layout)
5326 return;
5327
5328 unsigned src_queue_mask =
5329 radv_image_queue_family_mask(image, src_family,
5330 cmd_buffer->queue_family_index);
5331 unsigned dst_queue_mask =
5332 radv_image_queue_family_mask(image, dst_family,
5333 cmd_buffer->queue_family_index);
5334
5335 if (vk_format_is_depth(image->vk_format)) {
5336 radv_handle_depth_image_transition(cmd_buffer, image,
5337 src_layout, dst_layout,
5338 src_queue_mask, dst_queue_mask,
5339 range, sample_locs);
5340 } else {
5341 radv_handle_color_image_transition(cmd_buffer, image,
5342 src_layout, dst_layout,
5343 src_queue_mask, dst_queue_mask,
5344 range);
5345 }
5346 }
5347
5348 struct radv_barrier_info {
5349 uint32_t eventCount;
5350 const VkEvent *pEvents;
5351 VkPipelineStageFlags srcStageMask;
5352 VkPipelineStageFlags dstStageMask;
5353 };
5354
5355 static void
5356 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
5357 uint32_t memoryBarrierCount,
5358 const VkMemoryBarrier *pMemoryBarriers,
5359 uint32_t bufferMemoryBarrierCount,
5360 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
5361 uint32_t imageMemoryBarrierCount,
5362 const VkImageMemoryBarrier *pImageMemoryBarriers,
5363 const struct radv_barrier_info *info)
5364 {
5365 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5366 enum radv_cmd_flush_bits src_flush_bits = 0;
5367 enum radv_cmd_flush_bits dst_flush_bits = 0;
5368
5369 for (unsigned i = 0; i < info->eventCount; ++i) {
5370 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
5371 uint64_t va = radv_buffer_get_va(event->bo);
5372
5373 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5374
5375 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
5376
5377 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
5378 assert(cmd_buffer->cs->cdw <= cdw_max);
5379 }
5380
5381 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
5382 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
5383 NULL);
5384 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
5385 NULL);
5386 }
5387
5388 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
5389 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
5390 NULL);
5391 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
5392 NULL);
5393 }
5394
5395 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5396 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5397
5398 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
5399 image);
5400 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
5401 image);
5402 }
5403
5404 /* The Vulkan spec 1.1.98 says:
5405 *
5406 * "An execution dependency with only
5407 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
5408 * will only prevent that stage from executing in subsequently
5409 * submitted commands. As this stage does not perform any actual
5410 * execution, this is not observable - in effect, it does not delay
5411 * processing of subsequent commands. Similarly an execution dependency
5412 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
5413 * will effectively not wait for any prior commands to complete."
5414 */
5415 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
5416 radv_stage_flush(cmd_buffer, info->srcStageMask);
5417 cmd_buffer->state.flush_bits |= src_flush_bits;
5418
5419 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5420 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5421
5422 const struct VkSampleLocationsInfoEXT *sample_locs_info =
5423 vk_find_struct_const(pImageMemoryBarriers[i].pNext,
5424 SAMPLE_LOCATIONS_INFO_EXT);
5425 struct radv_sample_locations_state sample_locations = {};
5426
5427 if (sample_locs_info) {
5428 assert(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
5429 sample_locations.per_pixel = sample_locs_info->sampleLocationsPerPixel;
5430 sample_locations.grid_size = sample_locs_info->sampleLocationGridSize;
5431 sample_locations.count = sample_locs_info->sampleLocationsCount;
5432 typed_memcpy(&sample_locations.locations[0],
5433 sample_locs_info->pSampleLocations,
5434 sample_locs_info->sampleLocationsCount);
5435 }
5436
5437 radv_handle_image_transition(cmd_buffer, image,
5438 pImageMemoryBarriers[i].oldLayout,
5439 pImageMemoryBarriers[i].newLayout,
5440 pImageMemoryBarriers[i].srcQueueFamilyIndex,
5441 pImageMemoryBarriers[i].dstQueueFamilyIndex,
5442 &pImageMemoryBarriers[i].subresourceRange,
5443 sample_locs_info ? &sample_locations : NULL);
5444 }
5445
5446 /* Make sure CP DMA is idle because the driver might have performed a
5447 * DMA operation for copying or filling buffers/images.
5448 */
5449 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5450 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5451 si_cp_dma_wait_for_idle(cmd_buffer);
5452
5453 cmd_buffer->state.flush_bits |= dst_flush_bits;
5454 }
5455
5456 void radv_CmdPipelineBarrier(
5457 VkCommandBuffer commandBuffer,
5458 VkPipelineStageFlags srcStageMask,
5459 VkPipelineStageFlags destStageMask,
5460 VkBool32 byRegion,
5461 uint32_t memoryBarrierCount,
5462 const VkMemoryBarrier* pMemoryBarriers,
5463 uint32_t bufferMemoryBarrierCount,
5464 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5465 uint32_t imageMemoryBarrierCount,
5466 const VkImageMemoryBarrier* pImageMemoryBarriers)
5467 {
5468 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5469 struct radv_barrier_info info;
5470
5471 info.eventCount = 0;
5472 info.pEvents = NULL;
5473 info.srcStageMask = srcStageMask;
5474 info.dstStageMask = destStageMask;
5475
5476 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5477 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5478 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5479 }
5480
5481
5482 static void write_event(struct radv_cmd_buffer *cmd_buffer,
5483 struct radv_event *event,
5484 VkPipelineStageFlags stageMask,
5485 unsigned value)
5486 {
5487 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5488 uint64_t va = radv_buffer_get_va(event->bo);
5489
5490 si_emit_cache_flush(cmd_buffer);
5491
5492 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5493
5494 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 21);
5495
5496 /* Flags that only require a top-of-pipe event. */
5497 VkPipelineStageFlags top_of_pipe_flags =
5498 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
5499
5500 /* Flags that only require a post-index-fetch event. */
5501 VkPipelineStageFlags post_index_fetch_flags =
5502 top_of_pipe_flags |
5503 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
5504 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
5505
5506 /* Make sure CP DMA is idle because the driver might have performed a
5507 * DMA operation for copying or filling buffers/images.
5508 */
5509 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5510 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5511 si_cp_dma_wait_for_idle(cmd_buffer);
5512
5513 /* TODO: Emit EOS events for syncing PS/CS stages. */
5514
5515 if (!(stageMask & ~top_of_pipe_flags)) {
5516 /* Just need to sync the PFP engine. */
5517 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5518 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5519 S_370_WR_CONFIRM(1) |
5520 S_370_ENGINE_SEL(V_370_PFP));
5521 radeon_emit(cs, va);
5522 radeon_emit(cs, va >> 32);
5523 radeon_emit(cs, value);
5524 } else if (!(stageMask & ~post_index_fetch_flags)) {
5525 /* Sync ME because PFP reads index and indirect buffers. */
5526 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5527 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5528 S_370_WR_CONFIRM(1) |
5529 S_370_ENGINE_SEL(V_370_ME));
5530 radeon_emit(cs, va);
5531 radeon_emit(cs, va >> 32);
5532 radeon_emit(cs, value);
5533 } else {
5534 /* Otherwise, sync all prior GPU work using an EOP event. */
5535 si_cs_emit_write_event_eop(cs,
5536 cmd_buffer->device->physical_device->rad_info.chip_class,
5537 radv_cmd_buffer_uses_mec(cmd_buffer),
5538 V_028A90_BOTTOM_OF_PIPE_TS, 0,
5539 EOP_DST_SEL_MEM,
5540 EOP_DATA_SEL_VALUE_32BIT, va, value,
5541 cmd_buffer->gfx9_eop_bug_va);
5542 }
5543
5544 assert(cmd_buffer->cs->cdw <= cdw_max);
5545 }
5546
5547 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
5548 VkEvent _event,
5549 VkPipelineStageFlags stageMask)
5550 {
5551 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5552 RADV_FROM_HANDLE(radv_event, event, _event);
5553
5554 write_event(cmd_buffer, event, stageMask, 1);
5555 }
5556
5557 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
5558 VkEvent _event,
5559 VkPipelineStageFlags stageMask)
5560 {
5561 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5562 RADV_FROM_HANDLE(radv_event, event, _event);
5563
5564 write_event(cmd_buffer, event, stageMask, 0);
5565 }
5566
5567 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
5568 uint32_t eventCount,
5569 const VkEvent* pEvents,
5570 VkPipelineStageFlags srcStageMask,
5571 VkPipelineStageFlags dstStageMask,
5572 uint32_t memoryBarrierCount,
5573 const VkMemoryBarrier* pMemoryBarriers,
5574 uint32_t bufferMemoryBarrierCount,
5575 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5576 uint32_t imageMemoryBarrierCount,
5577 const VkImageMemoryBarrier* pImageMemoryBarriers)
5578 {
5579 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5580 struct radv_barrier_info info;
5581
5582 info.eventCount = eventCount;
5583 info.pEvents = pEvents;
5584 info.srcStageMask = 0;
5585
5586 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5587 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5588 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5589 }
5590
5591
5592 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
5593 uint32_t deviceMask)
5594 {
5595 /* No-op */
5596 }
5597
5598 /* VK_EXT_conditional_rendering */
5599 void radv_CmdBeginConditionalRenderingEXT(
5600 VkCommandBuffer commandBuffer,
5601 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
5602 {
5603 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5604 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
5605 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5606 bool draw_visible = true;
5607 uint64_t pred_value = 0;
5608 uint64_t va, new_va;
5609 unsigned pred_offset;
5610
5611 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
5612
5613 /* By default, if the 32-bit value at offset in buffer memory is zero,
5614 * then the rendering commands are discarded, otherwise they are
5615 * executed as normal. If the inverted flag is set, all commands are
5616 * discarded if the value is non zero.
5617 */
5618 if (pConditionalRenderingBegin->flags &
5619 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
5620 draw_visible = false;
5621 }
5622
5623 si_emit_cache_flush(cmd_buffer);
5624
5625 /* From the Vulkan spec 1.1.107:
5626 *
5627 * "If the 32-bit value at offset in buffer memory is zero, then the
5628 * rendering commands are discarded, otherwise they are executed as
5629 * normal. If the value of the predicate in buffer memory changes while
5630 * conditional rendering is active, the rendering commands may be
5631 * discarded in an implementation-dependent way. Some implementations
5632 * may latch the value of the predicate upon beginning conditional
5633 * rendering while others may read it before every rendering command."
5634 *
5635 * But, the AMD hardware treats the predicate as a 64-bit value which
5636 * means we need a workaround in the driver. Luckily, it's not required
5637 * to support if the value changes when predication is active.
5638 *
5639 * The workaround is as follows:
5640 * 1) allocate a 64-value in the upload BO and initialize it to 0
5641 * 2) copy the 32-bit predicate value to the upload BO
5642 * 3) use the new allocated VA address for predication
5643 *
5644 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
5645 * in ME (+ sync PFP) instead of PFP.
5646 */
5647 radv_cmd_buffer_upload_data(cmd_buffer, 8, 16, &pred_value, &pred_offset);
5648
5649 new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
5650
5651 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5652 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5653 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
5654 COPY_DATA_WR_CONFIRM);
5655 radeon_emit(cs, va);
5656 radeon_emit(cs, va >> 32);
5657 radeon_emit(cs, new_va);
5658 radeon_emit(cs, new_va >> 32);
5659
5660 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
5661 radeon_emit(cs, 0);
5662
5663 /* Enable predication for this command buffer. */
5664 si_emit_set_predication_state(cmd_buffer, draw_visible, new_va);
5665 cmd_buffer->state.predicating = true;
5666
5667 /* Store conditional rendering user info. */
5668 cmd_buffer->state.predication_type = draw_visible;
5669 cmd_buffer->state.predication_va = new_va;
5670 }
5671
5672 void radv_CmdEndConditionalRenderingEXT(
5673 VkCommandBuffer commandBuffer)
5674 {
5675 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5676
5677 /* Disable predication for this command buffer. */
5678 si_emit_set_predication_state(cmd_buffer, false, 0);
5679 cmd_buffer->state.predicating = false;
5680
5681 /* Reset conditional rendering user info. */
5682 cmd_buffer->state.predication_type = -1;
5683 cmd_buffer->state.predication_va = 0;
5684 }
5685
5686 /* VK_EXT_transform_feedback */
5687 void radv_CmdBindTransformFeedbackBuffersEXT(
5688 VkCommandBuffer commandBuffer,
5689 uint32_t firstBinding,
5690 uint32_t bindingCount,
5691 const VkBuffer* pBuffers,
5692 const VkDeviceSize* pOffsets,
5693 const VkDeviceSize* pSizes)
5694 {
5695 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5696 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5697 uint8_t enabled_mask = 0;
5698
5699 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
5700 for (uint32_t i = 0; i < bindingCount; i++) {
5701 uint32_t idx = firstBinding + i;
5702
5703 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
5704 sb[idx].offset = pOffsets[i];
5705 sb[idx].size = pSizes[i];
5706
5707 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
5708 sb[idx].buffer->bo);
5709
5710 enabled_mask |= 1 << idx;
5711 }
5712
5713 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
5714
5715 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
5716 }
5717
5718 static void
5719 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
5720 {
5721 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5722 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5723
5724 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
5725 radeon_emit(cs,
5726 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
5727 S_028B94_RAST_STREAM(0) |
5728 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
5729 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
5730 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
5731 radeon_emit(cs, so->hw_enabled_mask &
5732 so->enabled_stream_buffers_mask);
5733
5734 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5735 }
5736
5737 static void
5738 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
5739 {
5740 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5741 bool old_streamout_enabled = so->streamout_enabled;
5742 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
5743
5744 so->streamout_enabled = enable;
5745
5746 so->hw_enabled_mask = so->enabled_mask |
5747 (so->enabled_mask << 4) |
5748 (so->enabled_mask << 8) |
5749 (so->enabled_mask << 12);
5750
5751 if ((old_streamout_enabled != so->streamout_enabled) ||
5752 (old_hw_enabled_mask != so->hw_enabled_mask))
5753 radv_emit_streamout_enable(cmd_buffer);
5754 }
5755
5756 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
5757 {
5758 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5759 unsigned reg_strmout_cntl;
5760
5761 /* The register is at different places on different ASICs. */
5762 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
5763 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
5764 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
5765 } else {
5766 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
5767 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
5768 }
5769
5770 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
5771 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
5772
5773 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
5774 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
5775 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
5776 radeon_emit(cs, 0);
5777 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
5778 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
5779 radeon_emit(cs, 4); /* poll interval */
5780 }
5781
5782 static void
5783 radv_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
5784 uint32_t firstCounterBuffer,
5785 uint32_t counterBufferCount,
5786 const VkBuffer *pCounterBuffers,
5787 const VkDeviceSize *pCounterBufferOffsets)
5788
5789 {
5790 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5791 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5792 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5793 uint32_t i;
5794
5795 radv_flush_vgt_streamout(cmd_buffer);
5796
5797 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5798 for_each_bit(i, so->enabled_mask) {
5799 int32_t counter_buffer_idx = i - firstCounterBuffer;
5800 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5801 counter_buffer_idx = -1;
5802
5803 /* AMD GCN binds streamout buffers as shader resources.
5804 * VGT only counts primitives and tells the shader through
5805 * SGPRs what to do.
5806 */
5807 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
5808 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
5809 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
5810
5811 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5812
5813 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5814 /* The array of counter buffers is optional. */
5815 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5816 uint64_t va = radv_buffer_get_va(buffer->bo);
5817
5818 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5819
5820 /* Append */
5821 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5822 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5823 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5824 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
5825 radeon_emit(cs, 0); /* unused */
5826 radeon_emit(cs, 0); /* unused */
5827 radeon_emit(cs, va); /* src address lo */
5828 radeon_emit(cs, va >> 32); /* src address hi */
5829
5830 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5831 } else {
5832 /* Start from the beginning. */
5833 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5834 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5835 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5836 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
5837 radeon_emit(cs, 0); /* unused */
5838 radeon_emit(cs, 0); /* unused */
5839 radeon_emit(cs, 0); /* unused */
5840 radeon_emit(cs, 0); /* unused */
5841 }
5842 }
5843
5844 radv_set_streamout_enable(cmd_buffer, true);
5845 }
5846
5847 void radv_CmdBeginTransformFeedbackEXT(
5848 VkCommandBuffer commandBuffer,
5849 uint32_t firstCounterBuffer,
5850 uint32_t counterBufferCount,
5851 const VkBuffer* pCounterBuffers,
5852 const VkDeviceSize* pCounterBufferOffsets)
5853 {
5854 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5855
5856 radv_emit_streamout_begin(cmd_buffer,
5857 firstCounterBuffer, counterBufferCount,
5858 pCounterBuffers, pCounterBufferOffsets);
5859 }
5860
5861 static void
5862 radv_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
5863 uint32_t firstCounterBuffer,
5864 uint32_t counterBufferCount,
5865 const VkBuffer *pCounterBuffers,
5866 const VkDeviceSize *pCounterBufferOffsets)
5867 {
5868 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5869 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5870 uint32_t i;
5871
5872 radv_flush_vgt_streamout(cmd_buffer);
5873
5874 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5875 for_each_bit(i, so->enabled_mask) {
5876 int32_t counter_buffer_idx = i - firstCounterBuffer;
5877 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5878 counter_buffer_idx = -1;
5879
5880 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5881 /* The array of counters buffer is optional. */
5882 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5883 uint64_t va = radv_buffer_get_va(buffer->bo);
5884
5885 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5886
5887 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5888 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5889 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5890 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
5891 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
5892 radeon_emit(cs, va); /* dst address lo */
5893 radeon_emit(cs, va >> 32); /* dst address hi */
5894 radeon_emit(cs, 0); /* unused */
5895 radeon_emit(cs, 0); /* unused */
5896
5897 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5898 }
5899
5900 /* Deactivate transform feedback by zeroing the buffer size.
5901 * The counters (primitives generated, primitives emitted) may
5902 * be enabled even if there is not buffer bound. This ensures
5903 * that the primitives-emitted query won't increment.
5904 */
5905 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
5906
5907 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5908 }
5909
5910 radv_set_streamout_enable(cmd_buffer, false);
5911 }
5912
5913 void radv_CmdEndTransformFeedbackEXT(
5914 VkCommandBuffer commandBuffer,
5915 uint32_t firstCounterBuffer,
5916 uint32_t counterBufferCount,
5917 const VkBuffer* pCounterBuffers,
5918 const VkDeviceSize* pCounterBufferOffsets)
5919 {
5920 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5921
5922 radv_emit_streamout_end(cmd_buffer,
5923 firstCounterBuffer, counterBufferCount,
5924 pCounterBuffers, pCounterBufferOffsets);
5925 }
5926
5927 void radv_CmdDrawIndirectByteCountEXT(
5928 VkCommandBuffer commandBuffer,
5929 uint32_t instanceCount,
5930 uint32_t firstInstance,
5931 VkBuffer _counterBuffer,
5932 VkDeviceSize counterBufferOffset,
5933 uint32_t counterOffset,
5934 uint32_t vertexStride)
5935 {
5936 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5937 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
5938 struct radv_draw_info info = {};
5939
5940 info.instance_count = instanceCount;
5941 info.first_instance = firstInstance;
5942 info.strmout_buffer = counterBuffer;
5943 info.strmout_buffer_offset = counterBufferOffset;
5944 info.stride = vertexStride;
5945
5946 radv_draw(cmd_buffer, &info);
5947 }
5948
5949 /* VK_AMD_buffer_marker */
5950 void radv_CmdWriteBufferMarkerAMD(
5951 VkCommandBuffer commandBuffer,
5952 VkPipelineStageFlagBits pipelineStage,
5953 VkBuffer dstBuffer,
5954 VkDeviceSize dstOffset,
5955 uint32_t marker)
5956 {
5957 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5958 RADV_FROM_HANDLE(radv_buffer, buffer, dstBuffer);
5959 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5960 uint64_t va = radv_buffer_get_va(buffer->bo) + dstOffset;
5961
5962 si_emit_cache_flush(cmd_buffer);
5963
5964 if (!(pipelineStage & ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT)) {
5965 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5966 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
5967 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
5968 COPY_DATA_WR_CONFIRM);
5969 radeon_emit(cs, marker);
5970 radeon_emit(cs, 0);
5971 radeon_emit(cs, va);
5972 radeon_emit(cs, va >> 32);
5973 } else {
5974 si_cs_emit_write_event_eop(cs,
5975 cmd_buffer->device->physical_device->rad_info.chip_class,
5976 radv_cmd_buffer_uses_mec(cmd_buffer),
5977 V_028A90_BOTTOM_OF_PIPE_TS, 0,
5978 EOP_DST_SEL_MEM,
5979 EOP_DATA_SEL_VALUE_32BIT,
5980 va, marker,
5981 cmd_buffer->gfx9_eop_bug_va);
5982 }
5983 }