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radv: add support for dynamic depth/stencil states
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 bool src_render_loop,
58 VkImageLayout dst_layout,
59 bool dst_render_loop,
60 uint32_t src_family,
61 uint32_t dst_family,
62 const VkImageSubresourceRange *range,
63 struct radv_sample_locations_state *sample_locs);
64
65 const struct radv_dynamic_state default_dynamic_state = {
66 .viewport = {
67 .count = 0,
68 },
69 .scissor = {
70 .count = 0,
71 },
72 .line_width = 1.0f,
73 .depth_bias = {
74 .bias = 0.0f,
75 .clamp = 0.0f,
76 .slope = 0.0f,
77 },
78 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
79 .depth_bounds = {
80 .min = 0.0f,
81 .max = 1.0f,
82 },
83 .stencil_compare_mask = {
84 .front = ~0u,
85 .back = ~0u,
86 },
87 .stencil_write_mask = {
88 .front = ~0u,
89 .back = ~0u,
90 },
91 .stencil_reference = {
92 .front = 0u,
93 .back = 0u,
94 },
95 .line_stipple = {
96 .factor = 0u,
97 .pattern = 0u,
98 },
99 .cull_mode = 0u,
100 .front_face = 0u,
101 .primitive_topology = 0u,
102 };
103
104 static void
105 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
106 const struct radv_dynamic_state *src)
107 {
108 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
109 uint32_t copy_mask = src->mask;
110 uint32_t dest_mask = 0;
111
112 dest->discard_rectangle.count = src->discard_rectangle.count;
113 dest->sample_location.count = src->sample_location.count;
114
115 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
116 if (dest->viewport.count != src->viewport.count) {
117 dest->viewport.count = src->viewport.count;
118 dest_mask |= RADV_DYNAMIC_VIEWPORT;
119 }
120
121 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
122 src->viewport.count * sizeof(VkViewport))) {
123 typed_memcpy(dest->viewport.viewports,
124 src->viewport.viewports,
125 src->viewport.count);
126 dest_mask |= RADV_DYNAMIC_VIEWPORT;
127 }
128 }
129
130 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
131 if (dest->scissor.count != src->scissor.count) {
132 dest->scissor.count = src->scissor.count;
133 dest_mask |= RADV_DYNAMIC_SCISSOR;
134 }
135
136 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
137 src->scissor.count * sizeof(VkRect2D))) {
138 typed_memcpy(dest->scissor.scissors,
139 src->scissor.scissors, src->scissor.count);
140 dest_mask |= RADV_DYNAMIC_SCISSOR;
141 }
142 }
143
144 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
145 if (dest->line_width != src->line_width) {
146 dest->line_width = src->line_width;
147 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
148 }
149 }
150
151 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
152 if (memcmp(&dest->depth_bias, &src->depth_bias,
153 sizeof(src->depth_bias))) {
154 dest->depth_bias = src->depth_bias;
155 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
156 }
157 }
158
159 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
160 if (memcmp(&dest->blend_constants, &src->blend_constants,
161 sizeof(src->blend_constants))) {
162 typed_memcpy(dest->blend_constants,
163 src->blend_constants, 4);
164 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
165 }
166 }
167
168 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
169 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
170 sizeof(src->depth_bounds))) {
171 dest->depth_bounds = src->depth_bounds;
172 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
173 }
174 }
175
176 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
177 if (memcmp(&dest->stencil_compare_mask,
178 &src->stencil_compare_mask,
179 sizeof(src->stencil_compare_mask))) {
180 dest->stencil_compare_mask = src->stencil_compare_mask;
181 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
182 }
183 }
184
185 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
186 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
187 sizeof(src->stencil_write_mask))) {
188 dest->stencil_write_mask = src->stencil_write_mask;
189 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
190 }
191 }
192
193 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
194 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
195 sizeof(src->stencil_reference))) {
196 dest->stencil_reference = src->stencil_reference;
197 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
198 }
199 }
200
201 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
202 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
203 src->discard_rectangle.count * sizeof(VkRect2D))) {
204 typed_memcpy(dest->discard_rectangle.rectangles,
205 src->discard_rectangle.rectangles,
206 src->discard_rectangle.count);
207 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
208 }
209 }
210
211 if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
212 if (dest->sample_location.per_pixel != src->sample_location.per_pixel ||
213 dest->sample_location.grid_size.width != src->sample_location.grid_size.width ||
214 dest->sample_location.grid_size.height != src->sample_location.grid_size.height ||
215 memcmp(&dest->sample_location.locations,
216 &src->sample_location.locations,
217 src->sample_location.count * sizeof(VkSampleLocationEXT))) {
218 dest->sample_location.per_pixel = src->sample_location.per_pixel;
219 dest->sample_location.grid_size = src->sample_location.grid_size;
220 typed_memcpy(dest->sample_location.locations,
221 src->sample_location.locations,
222 src->sample_location.count);
223 dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
224 }
225 }
226
227 if (copy_mask & RADV_DYNAMIC_LINE_STIPPLE) {
228 if (memcmp(&dest->line_stipple, &src->line_stipple,
229 sizeof(src->line_stipple))) {
230 dest->line_stipple = src->line_stipple;
231 dest_mask |= RADV_DYNAMIC_LINE_STIPPLE;
232 }
233 }
234
235 if (copy_mask & RADV_DYNAMIC_CULL_MODE) {
236 if (dest->cull_mode != src->cull_mode) {
237 dest->cull_mode = src->cull_mode;
238 dest_mask |= RADV_DYNAMIC_CULL_MODE;
239 }
240 }
241
242 if (copy_mask & RADV_DYNAMIC_FRONT_FACE) {
243 if (dest->front_face != src->front_face) {
244 dest->front_face = src->front_face;
245 dest_mask |= RADV_DYNAMIC_FRONT_FACE;
246 }
247 }
248
249 if (copy_mask & RADV_DYNAMIC_PRIMITIVE_TOPOLOGY) {
250 if (dest->primitive_topology != src->primitive_topology) {
251 dest->primitive_topology = src->primitive_topology;
252 dest_mask |= RADV_DYNAMIC_PRIMITIVE_TOPOLOGY;
253 }
254 }
255
256 if (copy_mask & RADV_DYNAMIC_DEPTH_TEST_ENABLE) {
257 if (dest->depth_test_enable != src->depth_test_enable) {
258 dest->depth_test_enable = src->depth_test_enable;
259 dest_mask |= RADV_DYNAMIC_DEPTH_TEST_ENABLE;
260 }
261 }
262
263 if (copy_mask & RADV_DYNAMIC_DEPTH_WRITE_ENABLE) {
264 if (dest->depth_write_enable != src->depth_write_enable) {
265 dest->depth_write_enable = src->depth_write_enable;
266 dest_mask |= RADV_DYNAMIC_DEPTH_WRITE_ENABLE;
267 }
268 }
269
270 if (copy_mask & RADV_DYNAMIC_DEPTH_COMPARE_OP) {
271 if (dest->depth_compare_op != src->depth_compare_op) {
272 dest->depth_compare_op = src->depth_compare_op;
273 dest_mask |= RADV_DYNAMIC_DEPTH_COMPARE_OP;
274 }
275 }
276
277 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE) {
278 if (dest->depth_bounds_test_enable != src->depth_bounds_test_enable) {
279 dest->depth_bounds_test_enable = src->depth_bounds_test_enable;
280 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE;
281 }
282 }
283
284 if (copy_mask & RADV_DYNAMIC_STENCIL_TEST_ENABLE) {
285 if (dest->stencil_test_enable != src->stencil_test_enable) {
286 dest->stencil_test_enable = src->stencil_test_enable;
287 dest_mask |= RADV_DYNAMIC_STENCIL_TEST_ENABLE;
288 }
289 }
290
291 if (copy_mask & RADV_DYNAMIC_STENCIL_OP) {
292 if (memcmp(&dest->stencil_op, &src->stencil_op,
293 sizeof(src->stencil_op))) {
294 dest->stencil_op = src->stencil_op;
295 dest_mask |= RADV_DYNAMIC_STENCIL_OP;
296 }
297 }
298
299 cmd_buffer->state.dirty |= dest_mask;
300 }
301
302 static void
303 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
304 struct radv_pipeline *pipeline)
305 {
306 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
307 struct radv_shader_info *info;
308
309 if (!pipeline->streamout_shader ||
310 cmd_buffer->device->physical_device->use_ngg_streamout)
311 return;
312
313 info = &pipeline->streamout_shader->info;
314 for (int i = 0; i < MAX_SO_BUFFERS; i++)
315 so->stride_in_dw[i] = info->so.strides[i];
316
317 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
318 }
319
320 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
321 {
322 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
323 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
324 }
325
326 enum ring_type radv_queue_family_to_ring(int f) {
327 switch (f) {
328 case RADV_QUEUE_GENERAL:
329 return RING_GFX;
330 case RADV_QUEUE_COMPUTE:
331 return RING_COMPUTE;
332 case RADV_QUEUE_TRANSFER:
333 return RING_DMA;
334 default:
335 unreachable("Unknown queue family");
336 }
337 }
338
339 static VkResult radv_create_cmd_buffer(
340 struct radv_device * device,
341 struct radv_cmd_pool * pool,
342 VkCommandBufferLevel level,
343 VkCommandBuffer* pCommandBuffer)
344 {
345 struct radv_cmd_buffer *cmd_buffer;
346 unsigned ring;
347 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
348 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
349 if (cmd_buffer == NULL)
350 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
351
352 vk_object_base_init(&device->vk, &cmd_buffer->base,
353 VK_OBJECT_TYPE_COMMAND_BUFFER);
354
355 cmd_buffer->device = device;
356 cmd_buffer->pool = pool;
357 cmd_buffer->level = level;
358
359 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
360 cmd_buffer->queue_family_index = pool->queue_family_index;
361
362 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
363
364 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
365 if (!cmd_buffer->cs) {
366 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
367 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
368 }
369
370 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
371
372 list_inithead(&cmd_buffer->upload.list);
373
374 return VK_SUCCESS;
375 }
376
377 static void
378 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
379 {
380 list_del(&cmd_buffer->pool_link);
381
382 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
383 &cmd_buffer->upload.list, list) {
384 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
385 list_del(&up->list);
386 free(up);
387 }
388
389 if (cmd_buffer->upload.upload_bo)
390 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
391 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
392
393 for (unsigned i = 0; i < MAX_BIND_POINTS; i++)
394 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
395
396 vk_object_base_finish(&cmd_buffer->base);
397
398 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
399 }
400
401 static VkResult
402 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
403 {
404 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
405
406 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
407 &cmd_buffer->upload.list, list) {
408 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
409 list_del(&up->list);
410 free(up);
411 }
412
413 cmd_buffer->push_constant_stages = 0;
414 cmd_buffer->scratch_size_per_wave_needed = 0;
415 cmd_buffer->scratch_waves_wanted = 0;
416 cmd_buffer->compute_scratch_size_per_wave_needed = 0;
417 cmd_buffer->compute_scratch_waves_wanted = 0;
418 cmd_buffer->esgs_ring_size_needed = 0;
419 cmd_buffer->gsvs_ring_size_needed = 0;
420 cmd_buffer->tess_rings_needed = false;
421 cmd_buffer->gds_needed = false;
422 cmd_buffer->gds_oa_needed = false;
423 cmd_buffer->sample_positions_needed = false;
424
425 if (cmd_buffer->upload.upload_bo)
426 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
427 cmd_buffer->upload.upload_bo);
428 cmd_buffer->upload.offset = 0;
429
430 cmd_buffer->record_result = VK_SUCCESS;
431
432 memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
433
434 for (unsigned i = 0; i < MAX_BIND_POINTS; i++) {
435 cmd_buffer->descriptors[i].dirty = 0;
436 cmd_buffer->descriptors[i].valid = 0;
437 cmd_buffer->descriptors[i].push_dirty = false;
438 }
439
440 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
441 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
442 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
443 unsigned fence_offset, eop_bug_offset;
444 void *fence_ptr;
445
446 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
447 &fence_ptr);
448
449 cmd_buffer->gfx9_fence_va =
450 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
451 cmd_buffer->gfx9_fence_va += fence_offset;
452
453 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
454 /* Allocate a buffer for the EOP bug on GFX9. */
455 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
456 &eop_bug_offset, &fence_ptr);
457 cmd_buffer->gfx9_eop_bug_va =
458 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
459 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
460 }
461 }
462
463 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
464
465 return cmd_buffer->record_result;
466 }
467
468 static bool
469 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
470 uint64_t min_needed)
471 {
472 uint64_t new_size;
473 struct radeon_winsys_bo *bo;
474 struct radv_cmd_buffer_upload *upload;
475 struct radv_device *device = cmd_buffer->device;
476
477 new_size = MAX2(min_needed, 16 * 1024);
478 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
479
480 bo = device->ws->buffer_create(device->ws,
481 new_size, 4096,
482 RADEON_DOMAIN_GTT,
483 RADEON_FLAG_CPU_ACCESS|
484 RADEON_FLAG_NO_INTERPROCESS_SHARING |
485 RADEON_FLAG_32BIT,
486 RADV_BO_PRIORITY_UPLOAD_BUFFER);
487
488 if (!bo) {
489 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
490 return false;
491 }
492
493 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
494 if (cmd_buffer->upload.upload_bo) {
495 upload = malloc(sizeof(*upload));
496
497 if (!upload) {
498 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
499 device->ws->buffer_destroy(bo);
500 return false;
501 }
502
503 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
504 list_add(&upload->list, &cmd_buffer->upload.list);
505 }
506
507 cmd_buffer->upload.upload_bo = bo;
508 cmd_buffer->upload.size = new_size;
509 cmd_buffer->upload.offset = 0;
510 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
511
512 if (!cmd_buffer->upload.map) {
513 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
514 return false;
515 }
516
517 return true;
518 }
519
520 bool
521 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
522 unsigned size,
523 unsigned alignment,
524 unsigned *out_offset,
525 void **ptr)
526 {
527 assert(util_is_power_of_two_nonzero(alignment));
528
529 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
530 if (offset + size > cmd_buffer->upload.size) {
531 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
532 return false;
533 offset = 0;
534 }
535
536 *out_offset = offset;
537 *ptr = cmd_buffer->upload.map + offset;
538
539 cmd_buffer->upload.offset = offset + size;
540 return true;
541 }
542
543 bool
544 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
545 unsigned size, unsigned alignment,
546 const void *data, unsigned *out_offset)
547 {
548 uint8_t *ptr;
549
550 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
551 out_offset, (void **)&ptr))
552 return false;
553
554 if (ptr)
555 memcpy(ptr, data, size);
556
557 return true;
558 }
559
560 static void
561 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
562 unsigned count, const uint32_t *data)
563 {
564 struct radeon_cmdbuf *cs = cmd_buffer->cs;
565
566 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
567
568 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
569 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
570 S_370_WR_CONFIRM(1) |
571 S_370_ENGINE_SEL(V_370_ME));
572 radeon_emit(cs, va);
573 radeon_emit(cs, va >> 32);
574 radeon_emit_array(cs, data, count);
575 }
576
577 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
578 {
579 struct radv_device *device = cmd_buffer->device;
580 struct radeon_cmdbuf *cs = cmd_buffer->cs;
581 uint64_t va;
582
583 va = radv_buffer_get_va(device->trace_bo);
584 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
585 va += 4;
586
587 ++cmd_buffer->state.trace_id;
588 radv_emit_write_data_packet(cmd_buffer, va, 1,
589 &cmd_buffer->state.trace_id);
590
591 radeon_check_space(cmd_buffer->device->ws, cs, 2);
592
593 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
594 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
595 }
596
597 static void
598 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
599 enum radv_cmd_flush_bits flags)
600 {
601 if (unlikely(cmd_buffer->device->thread_trace_bo)) {
602 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
603 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_THREAD_TRACE_MARKER) | EVENT_INDEX(0));
604 }
605
606 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
607 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
608 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
609
610 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
611
612 /* Force wait for graphics or compute engines to be idle. */
613 si_cs_emit_cache_flush(cmd_buffer->cs,
614 cmd_buffer->device->physical_device->rad_info.chip_class,
615 &cmd_buffer->gfx9_fence_idx,
616 cmd_buffer->gfx9_fence_va,
617 radv_cmd_buffer_uses_mec(cmd_buffer),
618 flags, cmd_buffer->gfx9_eop_bug_va);
619 }
620
621 if (unlikely(cmd_buffer->device->trace_bo))
622 radv_cmd_buffer_trace_emit(cmd_buffer);
623 }
624
625 static void
626 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
627 struct radv_pipeline *pipeline, enum ring_type ring)
628 {
629 struct radv_device *device = cmd_buffer->device;
630 uint32_t data[2];
631 uint64_t va;
632
633 va = radv_buffer_get_va(device->trace_bo);
634
635 switch (ring) {
636 case RING_GFX:
637 va += 8;
638 break;
639 case RING_COMPUTE:
640 va += 16;
641 break;
642 default:
643 assert(!"invalid ring type");
644 }
645
646 uint64_t pipeline_address = (uintptr_t)pipeline;
647 data[0] = pipeline_address;
648 data[1] = pipeline_address >> 32;
649
650 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
651 }
652
653 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
654 VkPipelineBindPoint bind_point,
655 struct radv_descriptor_set *set,
656 unsigned idx)
657 {
658 struct radv_descriptor_state *descriptors_state =
659 radv_get_descriptors_state(cmd_buffer, bind_point);
660
661 descriptors_state->sets[idx] = set;
662
663 descriptors_state->valid |= (1u << idx); /* active descriptors */
664 descriptors_state->dirty |= (1u << idx);
665 }
666
667 static void
668 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
669 VkPipelineBindPoint bind_point)
670 {
671 struct radv_descriptor_state *descriptors_state =
672 radv_get_descriptors_state(cmd_buffer, bind_point);
673 struct radv_device *device = cmd_buffer->device;
674 uint32_t data[MAX_SETS * 2] = {};
675 uint64_t va;
676 unsigned i;
677 va = radv_buffer_get_va(device->trace_bo) + 24;
678
679 for_each_bit(i, descriptors_state->valid) {
680 struct radv_descriptor_set *set = descriptors_state->sets[i];
681 data[i * 2] = (uint64_t)(uintptr_t)set;
682 data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
683 }
684
685 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
686 }
687
688 struct radv_userdata_info *
689 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
690 gl_shader_stage stage,
691 int idx)
692 {
693 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
694 return &shader->info.user_sgprs_locs.shader_data[idx];
695 }
696
697 static void
698 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
699 struct radv_pipeline *pipeline,
700 gl_shader_stage stage,
701 int idx, uint64_t va)
702 {
703 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
704 uint32_t base_reg = pipeline->user_data_0[stage];
705 if (loc->sgpr_idx == -1)
706 return;
707
708 assert(loc->num_sgprs == 1);
709
710 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
711 base_reg + loc->sgpr_idx * 4, va, false);
712 }
713
714 static void
715 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
716 struct radv_pipeline *pipeline,
717 struct radv_descriptor_state *descriptors_state,
718 gl_shader_stage stage)
719 {
720 struct radv_device *device = cmd_buffer->device;
721 struct radeon_cmdbuf *cs = cmd_buffer->cs;
722 uint32_t sh_base = pipeline->user_data_0[stage];
723 struct radv_userdata_locations *locs =
724 &pipeline->shaders[stage]->info.user_sgprs_locs;
725 unsigned mask = locs->descriptor_sets_enabled;
726
727 mask &= descriptors_state->dirty & descriptors_state->valid;
728
729 while (mask) {
730 int start, count;
731
732 u_bit_scan_consecutive_range(&mask, &start, &count);
733
734 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
735 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
736
737 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
738 for (int i = 0; i < count; i++) {
739 struct radv_descriptor_set *set =
740 descriptors_state->sets[start + i];
741
742 radv_emit_shader_pointer_body(device, cs, set->va, true);
743 }
744 }
745 }
746
747 /**
748 * Convert the user sample locations to hardware sample locations (the values
749 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
750 */
751 static void
752 radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
753 uint32_t x, uint32_t y, VkOffset2D *sample_locs)
754 {
755 uint32_t x_offset = x % state->grid_size.width;
756 uint32_t y_offset = y % state->grid_size.height;
757 uint32_t num_samples = (uint32_t)state->per_pixel;
758 VkSampleLocationEXT *user_locs;
759 uint32_t pixel_offset;
760
761 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
762
763 assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
764 user_locs = &state->locations[pixel_offset];
765
766 for (uint32_t i = 0; i < num_samples; i++) {
767 float shifted_pos_x = user_locs[i].x - 0.5;
768 float shifted_pos_y = user_locs[i].y - 0.5;
769
770 int32_t scaled_pos_x = floorf(shifted_pos_x * 16);
771 int32_t scaled_pos_y = floorf(shifted_pos_y * 16);
772
773 sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
774 sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
775 }
776 }
777
778 /**
779 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
780 * locations.
781 */
782 static void
783 radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
784 uint32_t *sample_locs_pixel)
785 {
786 for (uint32_t i = 0; i < num_samples; i++) {
787 uint32_t sample_reg_idx = i / 4;
788 uint32_t sample_loc_idx = i % 4;
789 int32_t pos_x = sample_locs[i].x;
790 int32_t pos_y = sample_locs[i].y;
791
792 uint32_t shift_x = 8 * sample_loc_idx;
793 uint32_t shift_y = shift_x + 4;
794
795 sample_locs_pixel[sample_reg_idx] |= (pos_x & 0xf) << shift_x;
796 sample_locs_pixel[sample_reg_idx] |= (pos_y & 0xf) << shift_y;
797 }
798 }
799
800 /**
801 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
802 * sample locations.
803 */
804 static uint64_t
805 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer,
806 VkOffset2D *sample_locs,
807 uint32_t num_samples)
808 {
809 uint32_t centroid_priorities[num_samples];
810 uint32_t sample_mask = num_samples - 1;
811 uint32_t distances[num_samples];
812 uint64_t centroid_priority = 0;
813
814 /* Compute the distances from center for each sample. */
815 for (int i = 0; i < num_samples; i++) {
816 distances[i] = (sample_locs[i].x * sample_locs[i].x) +
817 (sample_locs[i].y * sample_locs[i].y);
818 }
819
820 /* Compute the centroid priorities by looking at the distances array. */
821 for (int i = 0; i < num_samples; i++) {
822 uint32_t min_idx = 0;
823
824 for (int j = 1; j < num_samples; j++) {
825 if (distances[j] < distances[min_idx])
826 min_idx = j;
827 }
828
829 centroid_priorities[i] = min_idx;
830 distances[min_idx] = 0xffffffff;
831 }
832
833 /* Compute the final centroid priority. */
834 for (int i = 0; i < 8; i++) {
835 centroid_priority |=
836 centroid_priorities[i & sample_mask] << (i * 4);
837 }
838
839 return centroid_priority << 32 | centroid_priority;
840 }
841
842 /**
843 * Emit the sample locations that are specified with VK_EXT_sample_locations.
844 */
845 static void
846 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
847 {
848 struct radv_sample_locations_state *sample_location =
849 &cmd_buffer->state.dynamic.sample_location;
850 uint32_t num_samples = (uint32_t)sample_location->per_pixel;
851 struct radeon_cmdbuf *cs = cmd_buffer->cs;
852 uint32_t sample_locs_pixel[4][2] = {};
853 VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
854 uint32_t max_sample_dist = 0;
855 uint64_t centroid_priority;
856
857 if (!cmd_buffer->state.dynamic.sample_location.count)
858 return;
859
860 /* Convert the user sample locations to hardware sample locations. */
861 radv_convert_user_sample_locs(sample_location, 0, 0, sample_locs[0]);
862 radv_convert_user_sample_locs(sample_location, 1, 0, sample_locs[1]);
863 radv_convert_user_sample_locs(sample_location, 0, 1, sample_locs[2]);
864 radv_convert_user_sample_locs(sample_location, 1, 1, sample_locs[3]);
865
866 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
867 for (uint32_t i = 0; i < 4; i++) {
868 radv_compute_sample_locs_pixel(num_samples, sample_locs[i],
869 sample_locs_pixel[i]);
870 }
871
872 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
873 centroid_priority =
874 radv_compute_centroid_priority(cmd_buffer, sample_locs[0],
875 num_samples);
876
877 /* Compute the maximum sample distance from the specified locations. */
878 for (unsigned i = 0; i < 4; ++i) {
879 for (uint32_t j = 0; j < num_samples; j++) {
880 VkOffset2D offset = sample_locs[i][j];
881 max_sample_dist = MAX2(max_sample_dist,
882 MAX2(abs(offset.x), abs(offset.y)));
883 }
884 }
885
886 /* Emit the specified user sample locations. */
887 switch (num_samples) {
888 case 2:
889 case 4:
890 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
891 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
892 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
893 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
894 break;
895 case 8:
896 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
897 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
898 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
899 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
900 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs_pixel[0][1]);
901 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs_pixel[1][1]);
902 radeon_set_context_reg(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs_pixel[2][1]);
903 radeon_set_context_reg(cs, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs_pixel[3][1]);
904 break;
905 default:
906 unreachable("invalid number of samples");
907 }
908
909 /* Emit the maximum sample distance and the centroid priority. */
910 radeon_set_context_reg_rmw(cs, R_028BE0_PA_SC_AA_CONFIG,
911 S_028BE0_MAX_SAMPLE_DIST(max_sample_dist),
912 ~C_028BE0_MAX_SAMPLE_DIST);
913
914 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
915 radeon_emit(cs, centroid_priority);
916 radeon_emit(cs, centroid_priority >> 32);
917
918 /* GFX9: Flush DFSM when the AA mode changes. */
919 if (cmd_buffer->device->dfsm_allowed) {
920 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
921 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
922 }
923
924 cmd_buffer->state.context_roll_without_scissor_emitted = true;
925 }
926
927 static void
928 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
929 struct radv_pipeline *pipeline,
930 gl_shader_stage stage,
931 int idx, int count, uint32_t *values)
932 {
933 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
934 uint32_t base_reg = pipeline->user_data_0[stage];
935 if (loc->sgpr_idx == -1)
936 return;
937
938 assert(loc->num_sgprs == count);
939
940 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
941 radeon_emit_array(cmd_buffer->cs, values, count);
942 }
943
944 static void
945 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
946 struct radv_pipeline *pipeline)
947 {
948 int num_samples = pipeline->graphics.ms.num_samples;
949 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
950
951 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.needs_sample_positions)
952 cmd_buffer->sample_positions_needed = true;
953
954 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
955 return;
956
957 radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
958
959 cmd_buffer->state.context_roll_without_scissor_emitted = true;
960 }
961
962 static void
963 radv_update_binning_state(struct radv_cmd_buffer *cmd_buffer,
964 struct radv_pipeline *pipeline)
965 {
966 const struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
967
968
969 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
970 return;
971
972 if (old_pipeline &&
973 old_pipeline->graphics.binning.pa_sc_binner_cntl_0 == pipeline->graphics.binning.pa_sc_binner_cntl_0 &&
974 old_pipeline->graphics.binning.db_dfsm_control == pipeline->graphics.binning.db_dfsm_control)
975 return;
976
977 bool binning_flush = false;
978 if (cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA12 ||
979 cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA20 ||
980 cmd_buffer->device->physical_device->rad_info.family == CHIP_RAVEN2 ||
981 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
982 binning_flush = !old_pipeline ||
983 G_028C44_BINNING_MODE(old_pipeline->graphics.binning.pa_sc_binner_cntl_0) !=
984 G_028C44_BINNING_MODE(pipeline->graphics.binning.pa_sc_binner_cntl_0);
985 }
986
987 radeon_set_context_reg(cmd_buffer->cs, R_028C44_PA_SC_BINNER_CNTL_0,
988 pipeline->graphics.binning.pa_sc_binner_cntl_0 |
989 S_028C44_FLUSH_ON_BINNING_TRANSITION(!!binning_flush));
990
991 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
992 radeon_set_context_reg(cmd_buffer->cs, R_028038_DB_DFSM_CONTROL,
993 pipeline->graphics.binning.db_dfsm_control);
994 } else {
995 radeon_set_context_reg(cmd_buffer->cs, R_028060_DB_DFSM_CONTROL,
996 pipeline->graphics.binning.db_dfsm_control);
997 }
998
999 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1000 }
1001
1002
1003 static void
1004 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
1005 struct radv_shader_variant *shader)
1006 {
1007 uint64_t va;
1008
1009 if (!shader)
1010 return;
1011
1012 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
1013
1014 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
1015 }
1016
1017 static void
1018 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
1019 struct radv_pipeline *pipeline,
1020 bool vertex_stage_only)
1021 {
1022 struct radv_cmd_state *state = &cmd_buffer->state;
1023 uint32_t mask = state->prefetch_L2_mask;
1024
1025 if (vertex_stage_only) {
1026 /* Fast prefetch path for starting draws as soon as possible.
1027 */
1028 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
1029 RADV_PREFETCH_VBO_DESCRIPTORS);
1030 }
1031
1032 if (mask & RADV_PREFETCH_VS)
1033 radv_emit_shader_prefetch(cmd_buffer,
1034 pipeline->shaders[MESA_SHADER_VERTEX]);
1035
1036 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
1037 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
1038
1039 if (mask & RADV_PREFETCH_TCS)
1040 radv_emit_shader_prefetch(cmd_buffer,
1041 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
1042
1043 if (mask & RADV_PREFETCH_TES)
1044 radv_emit_shader_prefetch(cmd_buffer,
1045 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
1046
1047 if (mask & RADV_PREFETCH_GS) {
1048 radv_emit_shader_prefetch(cmd_buffer,
1049 pipeline->shaders[MESA_SHADER_GEOMETRY]);
1050 if (radv_pipeline_has_gs_copy_shader(pipeline))
1051 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
1052 }
1053
1054 if (mask & RADV_PREFETCH_PS)
1055 radv_emit_shader_prefetch(cmd_buffer,
1056 pipeline->shaders[MESA_SHADER_FRAGMENT]);
1057
1058 state->prefetch_L2_mask &= ~mask;
1059 }
1060
1061 static void
1062 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
1063 {
1064 if (!cmd_buffer->device->physical_device->rad_info.rbplus_allowed)
1065 return;
1066
1067 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1068 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1069
1070 unsigned sx_ps_downconvert = 0;
1071 unsigned sx_blend_opt_epsilon = 0;
1072 unsigned sx_blend_opt_control = 0;
1073
1074 if (!cmd_buffer->state.attachments || !subpass)
1075 return;
1076
1077 for (unsigned i = 0; i < subpass->color_count; ++i) {
1078 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1079 /* We don't set the DISABLE bits, because the HW can't have holes,
1080 * so the SPI color format is set to 32-bit 1-component. */
1081 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1082 continue;
1083 }
1084
1085 int idx = subpass->color_attachments[i].attachment;
1086 struct radv_color_buffer_info *cb = &cmd_buffer->state.attachments[idx].cb;
1087
1088 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
1089 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
1090 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
1091 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
1092
1093 bool has_alpha, has_rgb;
1094
1095 /* Set if RGB and A are present. */
1096 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
1097
1098 if (format == V_028C70_COLOR_8 ||
1099 format == V_028C70_COLOR_16 ||
1100 format == V_028C70_COLOR_32)
1101 has_rgb = !has_alpha;
1102 else
1103 has_rgb = true;
1104
1105 /* Check the colormask and export format. */
1106 if (!(colormask & 0x7))
1107 has_rgb = false;
1108 if (!(colormask & 0x8))
1109 has_alpha = false;
1110
1111 if (spi_format == V_028714_SPI_SHADER_ZERO) {
1112 has_rgb = false;
1113 has_alpha = false;
1114 }
1115
1116 /* Disable value checking for disabled channels. */
1117 if (!has_rgb)
1118 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1119 if (!has_alpha)
1120 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1121
1122 /* Enable down-conversion for 32bpp and smaller formats. */
1123 switch (format) {
1124 case V_028C70_COLOR_8:
1125 case V_028C70_COLOR_8_8:
1126 case V_028C70_COLOR_8_8_8_8:
1127 /* For 1 and 2-channel formats, use the superset thereof. */
1128 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
1129 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1130 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1131 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
1132 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
1133 }
1134 break;
1135
1136 case V_028C70_COLOR_5_6_5:
1137 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1138 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
1139 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
1140 }
1141 break;
1142
1143 case V_028C70_COLOR_1_5_5_5:
1144 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1145 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
1146 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
1147 }
1148 break;
1149
1150 case V_028C70_COLOR_4_4_4_4:
1151 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1152 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
1153 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
1154 }
1155 break;
1156
1157 case V_028C70_COLOR_32:
1158 if (swap == V_028C70_SWAP_STD &&
1159 spi_format == V_028714_SPI_SHADER_32_R)
1160 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1161 else if (swap == V_028C70_SWAP_ALT_REV &&
1162 spi_format == V_028714_SPI_SHADER_32_AR)
1163 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
1164 break;
1165
1166 case V_028C70_COLOR_16:
1167 case V_028C70_COLOR_16_16:
1168 /* For 1-channel formats, use the superset thereof. */
1169 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
1170 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
1171 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1172 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1173 if (swap == V_028C70_SWAP_STD ||
1174 swap == V_028C70_SWAP_STD_REV)
1175 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
1176 else
1177 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
1178 }
1179 break;
1180
1181 case V_028C70_COLOR_10_11_11:
1182 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1183 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
1184 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
1185 }
1186 break;
1187
1188 case V_028C70_COLOR_2_10_10_10:
1189 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1190 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
1191 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
1192 }
1193 break;
1194 }
1195 }
1196
1197 /* Do not set the DISABLE bits for the unused attachments, as that
1198 * breaks dual source blending in SkQP and does not seem to improve
1199 * performance. */
1200
1201 if (sx_ps_downconvert == cmd_buffer->state.last_sx_ps_downconvert &&
1202 sx_blend_opt_epsilon == cmd_buffer->state.last_sx_blend_opt_epsilon &&
1203 sx_blend_opt_control == cmd_buffer->state.last_sx_blend_opt_control)
1204 return;
1205
1206 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
1207 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
1208 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
1209 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
1210
1211 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1212
1213 cmd_buffer->state.last_sx_ps_downconvert = sx_ps_downconvert;
1214 cmd_buffer->state.last_sx_blend_opt_epsilon = sx_blend_opt_epsilon;
1215 cmd_buffer->state.last_sx_blend_opt_control = sx_blend_opt_control;
1216 }
1217
1218 static void
1219 radv_emit_batch_break_on_new_ps(struct radv_cmd_buffer *cmd_buffer)
1220 {
1221 if (!cmd_buffer->device->pbb_allowed)
1222 return;
1223
1224 struct radv_binning_settings settings =
1225 radv_get_binning_settings(cmd_buffer->device->physical_device);
1226 bool break_for_new_ps =
1227 (!cmd_buffer->state.emitted_pipeline ||
1228 cmd_buffer->state.emitted_pipeline->shaders[MESA_SHADER_FRAGMENT] !=
1229 cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT]) &&
1230 (settings.context_states_per_bin > 1 ||
1231 settings.persistent_states_per_bin > 1);
1232 bool break_for_new_cb_target_mask =
1233 (!cmd_buffer->state.emitted_pipeline ||
1234 cmd_buffer->state.emitted_pipeline->graphics.cb_target_mask !=
1235 cmd_buffer->state.pipeline->graphics.cb_target_mask) &&
1236 settings.context_states_per_bin > 1;
1237
1238 if (!break_for_new_ps && !break_for_new_cb_target_mask)
1239 return;
1240
1241 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1242 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1243 }
1244
1245 static void
1246 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1247 {
1248 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1249
1250 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1251 return;
1252
1253 radv_update_multisample_state(cmd_buffer, pipeline);
1254 radv_update_binning_state(cmd_buffer, pipeline);
1255
1256 cmd_buffer->scratch_size_per_wave_needed = MAX2(cmd_buffer->scratch_size_per_wave_needed,
1257 pipeline->scratch_bytes_per_wave);
1258 cmd_buffer->scratch_waves_wanted = MAX2(cmd_buffer->scratch_waves_wanted,
1259 pipeline->max_waves);
1260
1261 if (!cmd_buffer->state.emitted_pipeline ||
1262 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1263 pipeline->graphics.can_use_guardband)
1264 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1265
1266 if (!cmd_buffer->state.emitted_pipeline ||
1267 cmd_buffer->state.emitted_pipeline->graphics.pa_su_sc_mode_cntl !=
1268 pipeline->graphics.pa_su_sc_mode_cntl)
1269 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_CULL_MODE |
1270 RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE;
1271
1272 if (!cmd_buffer->state.emitted_pipeline)
1273 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY;
1274
1275 if (!cmd_buffer->state.emitted_pipeline ||
1276 cmd_buffer->state.emitted_pipeline->graphics.db_depth_control !=
1277 pipeline->graphics.db_depth_control)
1278 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE |
1279 RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE |
1280 RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP |
1281 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE |
1282 RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE |
1283 RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP;
1284
1285 if (!cmd_buffer->state.emitted_pipeline)
1286 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP;
1287
1288 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
1289
1290 if (!cmd_buffer->state.emitted_pipeline ||
1291 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
1292 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
1293 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
1294 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
1295 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
1296 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1297 }
1298
1299 radv_emit_batch_break_on_new_ps(cmd_buffer);
1300
1301 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
1302 if (!pipeline->shaders[i])
1303 continue;
1304
1305 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1306 pipeline->shaders[i]->bo);
1307 }
1308
1309 if (radv_pipeline_has_gs_copy_shader(pipeline))
1310 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1311 pipeline->gs_copy_shader->bo);
1312
1313 if (unlikely(cmd_buffer->device->trace_bo))
1314 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1315
1316 cmd_buffer->state.emitted_pipeline = pipeline;
1317
1318 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1319 }
1320
1321 static void
1322 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1323 {
1324 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1325 cmd_buffer->state.dynamic.viewport.viewports);
1326 }
1327
1328 static void
1329 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1330 {
1331 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1332
1333 si_write_scissors(cmd_buffer->cs, 0, count,
1334 cmd_buffer->state.dynamic.scissor.scissors,
1335 cmd_buffer->state.dynamic.viewport.viewports,
1336 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1337
1338 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1339 }
1340
1341 static void
1342 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1343 {
1344 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1345 return;
1346
1347 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1348 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1349 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1350 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1351 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1352 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1353 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1354 }
1355 }
1356
1357 static void
1358 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1359 {
1360 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1361
1362 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1363 S_028A08_WIDTH(CLAMP(width, 0, 0xFFFF)));
1364 }
1365
1366 static void
1367 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1368 {
1369 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1370
1371 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1372 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1373 }
1374
1375 static void
1376 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1377 {
1378 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1379
1380 radeon_set_context_reg_seq(cmd_buffer->cs,
1381 R_028430_DB_STENCILREFMASK, 2);
1382 radeon_emit(cmd_buffer->cs,
1383 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1384 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1385 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1386 S_028430_STENCILOPVAL(1));
1387 radeon_emit(cmd_buffer->cs,
1388 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1389 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1390 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1391 S_028434_STENCILOPVAL_BF(1));
1392 }
1393
1394 static void
1395 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1396 {
1397 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1398
1399 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1400 fui(d->depth_bounds.min));
1401 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1402 fui(d->depth_bounds.max));
1403 }
1404
1405 static void
1406 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1407 {
1408 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1409 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1410 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1411
1412
1413 radeon_set_context_reg_seq(cmd_buffer->cs,
1414 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1415 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1416 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1417 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1418 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1419 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1420 }
1421
1422 static void
1423 radv_emit_line_stipple(struct radv_cmd_buffer *cmd_buffer)
1424 {
1425 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1426 uint32_t auto_reset_cntl = 1;
1427
1428 if (d->primitive_topology == V_008958_DI_PT_LINESTRIP)
1429 auto_reset_cntl = 2;
1430
1431 radeon_set_context_reg(cmd_buffer->cs, R_028A0C_PA_SC_LINE_STIPPLE,
1432 S_028A0C_LINE_PATTERN(d->line_stipple.pattern) |
1433 S_028A0C_REPEAT_COUNT(d->line_stipple.factor - 1) |
1434 S_028A0C_AUTO_RESET_CNTL(auto_reset_cntl));
1435 }
1436
1437 static void
1438 radv_emit_culling(struct radv_cmd_buffer *cmd_buffer, uint32_t states)
1439 {
1440 unsigned pa_su_sc_mode_cntl = cmd_buffer->state.pipeline->graphics.pa_su_sc_mode_cntl;
1441 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1442
1443 if (states & RADV_CMD_DIRTY_DYNAMIC_CULL_MODE) {
1444 pa_su_sc_mode_cntl &= C_028814_CULL_FRONT;
1445 pa_su_sc_mode_cntl |= S_028814_CULL_FRONT(!!(d->cull_mode & VK_CULL_MODE_FRONT_BIT));
1446
1447 pa_su_sc_mode_cntl &= C_028814_CULL_BACK;
1448 pa_su_sc_mode_cntl |= S_028814_CULL_BACK(!!(d->cull_mode & VK_CULL_MODE_BACK_BIT));
1449 }
1450
1451 if (states & RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE) {
1452 pa_su_sc_mode_cntl &= C_028814_FACE;
1453 pa_su_sc_mode_cntl |= S_028814_FACE(d->front_face);
1454 }
1455
1456 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
1457 pa_su_sc_mode_cntl);
1458 }
1459
1460 static void
1461 radv_emit_primitive_topology(struct radv_cmd_buffer *cmd_buffer)
1462 {
1463 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1464
1465 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1466 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
1467 cmd_buffer->cs,
1468 R_030908_VGT_PRIMITIVE_TYPE, 1,
1469 d->primitive_topology);
1470 } else {
1471 radeon_set_config_reg(cmd_buffer->cs,
1472 R_008958_VGT_PRIMITIVE_TYPE,
1473 d->primitive_topology);
1474 }
1475 }
1476
1477 static void
1478 radv_emit_depth_control(struct radv_cmd_buffer *cmd_buffer, uint32_t states)
1479 {
1480 unsigned db_depth_control = cmd_buffer->state.pipeline->graphics.db_depth_control;
1481 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1482
1483 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE) {
1484 db_depth_control &= C_028800_Z_ENABLE;
1485 db_depth_control |= S_028800_Z_ENABLE(d->depth_test_enable ? 1 : 0);
1486 }
1487
1488 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE) {
1489 db_depth_control &= C_028800_Z_WRITE_ENABLE;
1490 db_depth_control |= S_028800_Z_WRITE_ENABLE(d->depth_write_enable ? 1 : 0);
1491 }
1492
1493 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP) {
1494 db_depth_control &= C_028800_ZFUNC;
1495 db_depth_control |= S_028800_ZFUNC(d->depth_compare_op);
1496 }
1497
1498 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE) {
1499 db_depth_control &= C_028800_DEPTH_BOUNDS_ENABLE;
1500 db_depth_control |= S_028800_DEPTH_BOUNDS_ENABLE(d->depth_bounds_test_enable ? 1 : 0);
1501 }
1502
1503 if (states & RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE) {
1504 db_depth_control &= C_028800_STENCIL_ENABLE;
1505 db_depth_control |= S_028800_STENCIL_ENABLE(d->stencil_test_enable ? 1 : 0);
1506
1507 db_depth_control &= C_028800_BACKFACE_ENABLE;
1508 db_depth_control |= S_028800_BACKFACE_ENABLE(d->stencil_test_enable ? 1 : 0);
1509 }
1510
1511 if (states & RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP) {
1512 db_depth_control &= C_028800_STENCILFUNC;
1513 db_depth_control |= S_028800_STENCILFUNC(d->stencil_op.front.compare_op);
1514
1515 db_depth_control &= C_028800_STENCILFUNC_BF;
1516 db_depth_control |= S_028800_STENCILFUNC_BF(d->stencil_op.back.compare_op);
1517 }
1518
1519 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL,
1520 db_depth_control);
1521 }
1522
1523 static void
1524 radv_emit_stencil_control(struct radv_cmd_buffer *cmd_buffer)
1525 {
1526 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1527
1528 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL,
1529 S_02842C_STENCILFAIL(si_translate_stencil_op(d->stencil_op.front.fail_op)) |
1530 S_02842C_STENCILZPASS(si_translate_stencil_op(d->stencil_op.front.pass_op)) |
1531 S_02842C_STENCILZFAIL(si_translate_stencil_op(d->stencil_op.front.depth_fail_op)) |
1532 S_02842C_STENCILFAIL_BF(si_translate_stencil_op(d->stencil_op.back.fail_op)) |
1533 S_02842C_STENCILZPASS_BF(si_translate_stencil_op(d->stencil_op.back.pass_op)) |
1534 S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(d->stencil_op.back.depth_fail_op)));
1535 }
1536
1537 static void
1538 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1539 int index,
1540 struct radv_color_buffer_info *cb,
1541 struct radv_image_view *iview,
1542 VkImageLayout layout,
1543 bool in_render_loop)
1544 {
1545 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
1546 uint32_t cb_color_info = cb->cb_color_info;
1547 struct radv_image *image = iview->image;
1548
1549 if (!radv_layout_dcc_compressed(cmd_buffer->device, image, layout, in_render_loop,
1550 radv_image_queue_family_mask(image,
1551 cmd_buffer->queue_family_index,
1552 cmd_buffer->queue_family_index))) {
1553 cb_color_info &= C_028C70_DCC_ENABLE;
1554 }
1555
1556 if (!radv_layout_can_fast_clear(image, layout, in_render_loop,
1557 radv_image_queue_family_mask(image,
1558 cmd_buffer->queue_family_index,
1559 cmd_buffer->queue_family_index))) {
1560 cb_color_info &= C_028C70_COMPRESSION;
1561 }
1562
1563 if (radv_image_is_tc_compat_cmask(image) &&
1564 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1565 radv_is_dcc_decompress_pipeline(cmd_buffer))) {
1566 /* If this bit is set, the FMASK decompression operation
1567 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1568 */
1569 cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
1570 }
1571
1572 if (radv_image_has_fmask(image) &&
1573 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1574 radv_is_hw_resolve_pipeline(cmd_buffer))) {
1575 /* Make sure FMASK is enabled if it has been cleared because:
1576 *
1577 * 1) it's required for FMASK_DECOMPRESS operations to avoid
1578 * GPU hangs
1579 * 2) it's necessary for CB_RESOLVE which can read compressed
1580 * FMASK data anyways.
1581 */
1582 cb_color_info |= S_028C70_COMPRESSION(1);
1583 }
1584
1585 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1586 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1587 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1588 radeon_emit(cmd_buffer->cs, 0);
1589 radeon_emit(cmd_buffer->cs, 0);
1590 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1591 radeon_emit(cmd_buffer->cs, cb_color_info);
1592 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1593 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1594 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1595 radeon_emit(cmd_buffer->cs, 0);
1596 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1597 radeon_emit(cmd_buffer->cs, 0);
1598
1599 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 1);
1600 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1601
1602 radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4,
1603 cb->cb_color_base >> 32);
1604 radeon_set_context_reg(cmd_buffer->cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + index * 4,
1605 cb->cb_color_cmask >> 32);
1606 radeon_set_context_reg(cmd_buffer->cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + index * 4,
1607 cb->cb_color_fmask >> 32);
1608 radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4,
1609 cb->cb_dcc_base >> 32);
1610 radeon_set_context_reg(cmd_buffer->cs, R_028EC0_CB_COLOR0_ATTRIB2 + index * 4,
1611 cb->cb_color_attrib2);
1612 radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4,
1613 cb->cb_color_attrib3);
1614 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1615 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1616 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1617 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1618 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1619 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1620 radeon_emit(cmd_buffer->cs, cb_color_info);
1621 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1622 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1623 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1624 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1625 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1626 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1627
1628 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1629 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1630 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1631
1632 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1633 cb->cb_mrt_epitch);
1634 } else {
1635 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1636 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1637 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1638 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1639 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1640 radeon_emit(cmd_buffer->cs, cb_color_info);
1641 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1642 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1643 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1644 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1645 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1646 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1647
1648 if (is_vi) { /* DCC BASE */
1649 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1650 }
1651 }
1652
1653 if (radv_dcc_enabled(image, iview->base_mip)) {
1654 /* Drawing with DCC enabled also compresses colorbuffers. */
1655 VkImageSubresourceRange range = {
1656 .aspectMask = iview->aspect_mask,
1657 .baseMipLevel = iview->base_mip,
1658 .levelCount = iview->level_count,
1659 .baseArrayLayer = iview->base_layer,
1660 .layerCount = iview->layer_count,
1661 };
1662
1663 radv_update_dcc_metadata(cmd_buffer, image, &range, true);
1664 }
1665 }
1666
1667 static void
1668 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1669 struct radv_ds_buffer_info *ds,
1670 const struct radv_image_view *iview,
1671 VkImageLayout layout,
1672 bool in_render_loop, bool requires_cond_exec)
1673 {
1674 const struct radv_image *image = iview->image;
1675 uint32_t db_z_info = ds->db_z_info;
1676 uint32_t db_z_info_reg;
1677
1678 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug ||
1679 !radv_image_is_tc_compat_htile(image))
1680 return;
1681
1682 if (!radv_layout_is_htile_compressed(image, layout, in_render_loop,
1683 radv_image_queue_family_mask(image,
1684 cmd_buffer->queue_family_index,
1685 cmd_buffer->queue_family_index))) {
1686 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1687 }
1688
1689 db_z_info &= C_028040_ZRANGE_PRECISION;
1690
1691 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1692 db_z_info_reg = R_028038_DB_Z_INFO;
1693 } else {
1694 db_z_info_reg = R_028040_DB_Z_INFO;
1695 }
1696
1697 /* When we don't know the last fast clear value we need to emit a
1698 * conditional packet that will eventually skip the following
1699 * SET_CONTEXT_REG packet.
1700 */
1701 if (requires_cond_exec) {
1702 uint64_t va = radv_get_tc_compat_zrange_va(image, iview->base_mip);
1703
1704 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1705 radeon_emit(cmd_buffer->cs, va);
1706 radeon_emit(cmd_buffer->cs, va >> 32);
1707 radeon_emit(cmd_buffer->cs, 0);
1708 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1709 }
1710
1711 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1712 }
1713
1714 static void
1715 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1716 struct radv_ds_buffer_info *ds,
1717 struct radv_image_view *iview,
1718 VkImageLayout layout,
1719 bool in_render_loop)
1720 {
1721 const struct radv_image *image = iview->image;
1722 uint32_t db_z_info = ds->db_z_info;
1723 uint32_t db_stencil_info = ds->db_stencil_info;
1724
1725 if (!radv_layout_is_htile_compressed(image, layout, in_render_loop,
1726 radv_image_queue_family_mask(image,
1727 cmd_buffer->queue_family_index,
1728 cmd_buffer->queue_family_index))) {
1729 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1730 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1731 }
1732
1733 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1734 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1735
1736 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1737 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1738 radeon_set_context_reg(cmd_buffer->cs, R_02801C_DB_DEPTH_SIZE_XY, ds->db_depth_size);
1739
1740 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 7);
1741 radeon_emit(cmd_buffer->cs, S_02803C_RESOURCE_LEVEL(1));
1742 radeon_emit(cmd_buffer->cs, db_z_info);
1743 radeon_emit(cmd_buffer->cs, db_stencil_info);
1744 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1745 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1746 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1747 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1748
1749 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_READ_BASE_HI, 5);
1750 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1751 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1752 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1753 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1754 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1755 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1756 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1757 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1758 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1759 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1760
1761 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1762 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1763 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1764 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1765 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1766 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1767 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1768 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1769 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1770 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1771 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1772
1773 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1774 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1775 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1776 } else {
1777 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1778
1779 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1780 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1781 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1782 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1783 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1784 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1785 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1786 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1787 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1788 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1789
1790 }
1791
1792 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1793 radv_update_zrange_precision(cmd_buffer, ds, iview, layout,
1794 in_render_loop, true);
1795
1796 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1797 ds->pa_su_poly_offset_db_fmt_cntl);
1798 }
1799
1800 /**
1801 * Update the fast clear depth/stencil values if the image is bound as a
1802 * depth/stencil buffer.
1803 */
1804 static void
1805 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1806 const struct radv_image_view *iview,
1807 VkClearDepthStencilValue ds_clear_value,
1808 VkImageAspectFlags aspects)
1809 {
1810 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1811 const struct radv_image *image = iview->image;
1812 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1813 uint32_t att_idx;
1814
1815 if (!cmd_buffer->state.attachments || !subpass)
1816 return;
1817
1818 if (!subpass->depth_stencil_attachment)
1819 return;
1820
1821 att_idx = subpass->depth_stencil_attachment->attachment;
1822 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1823 return;
1824
1825 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1826 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1827 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1828 radeon_emit(cs, ds_clear_value.stencil);
1829 radeon_emit(cs, fui(ds_clear_value.depth));
1830 } else if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1831 radeon_set_context_reg_seq(cs, R_02802C_DB_DEPTH_CLEAR, 1);
1832 radeon_emit(cs, fui(ds_clear_value.depth));
1833 } else {
1834 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1835 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 1);
1836 radeon_emit(cs, ds_clear_value.stencil);
1837 }
1838
1839 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1840 * only needed when clearing Z to 0.0.
1841 */
1842 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1843 ds_clear_value.depth == 0.0) {
1844 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1845 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
1846
1847 radv_update_zrange_precision(cmd_buffer, &cmd_buffer->state.attachments[att_idx].ds,
1848 iview, layout, in_render_loop, false);
1849 }
1850
1851 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1852 }
1853
1854 /**
1855 * Set the clear depth/stencil values to the image's metadata.
1856 */
1857 static void
1858 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1859 struct radv_image *image,
1860 const VkImageSubresourceRange *range,
1861 VkClearDepthStencilValue ds_clear_value,
1862 VkImageAspectFlags aspects)
1863 {
1864 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1865 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel);
1866 uint32_t level_count = radv_get_levelCount(image, range);
1867
1868 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1869 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1870 /* Use the fastest way when both aspects are used. */
1871 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + 2 * level_count, cmd_buffer->state.predicating));
1872 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1873 S_370_WR_CONFIRM(1) |
1874 S_370_ENGINE_SEL(V_370_PFP));
1875 radeon_emit(cs, va);
1876 radeon_emit(cs, va >> 32);
1877
1878 for (uint32_t l = 0; l < level_count; l++) {
1879 radeon_emit(cs, ds_clear_value.stencil);
1880 radeon_emit(cs, fui(ds_clear_value.depth));
1881 }
1882 } else {
1883 /* Otherwise we need one WRITE_DATA packet per level. */
1884 for (uint32_t l = 0; l < level_count; l++) {
1885 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel + l);
1886 unsigned value;
1887
1888 if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1889 value = fui(ds_clear_value.depth);
1890 va += 4;
1891 } else {
1892 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1893 value = ds_clear_value.stencil;
1894 }
1895
1896 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1897 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1898 S_370_WR_CONFIRM(1) |
1899 S_370_ENGINE_SEL(V_370_PFP));
1900 radeon_emit(cs, va);
1901 radeon_emit(cs, va >> 32);
1902 radeon_emit(cs, value);
1903 }
1904 }
1905 }
1906
1907 /**
1908 * Update the TC-compat metadata value for this image.
1909 */
1910 static void
1911 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1912 struct radv_image *image,
1913 const VkImageSubresourceRange *range,
1914 uint32_t value)
1915 {
1916 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1917
1918 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug)
1919 return;
1920
1921 uint64_t va = radv_get_tc_compat_zrange_va(image, range->baseMipLevel);
1922 uint32_t level_count = radv_get_levelCount(image, range);
1923
1924 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + level_count, cmd_buffer->state.predicating));
1925 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1926 S_370_WR_CONFIRM(1) |
1927 S_370_ENGINE_SEL(V_370_PFP));
1928 radeon_emit(cs, va);
1929 radeon_emit(cs, va >> 32);
1930
1931 for (uint32_t l = 0; l < level_count; l++)
1932 radeon_emit(cs, value);
1933 }
1934
1935 static void
1936 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1937 const struct radv_image_view *iview,
1938 VkClearDepthStencilValue ds_clear_value)
1939 {
1940 VkImageSubresourceRange range = {
1941 .aspectMask = iview->aspect_mask,
1942 .baseMipLevel = iview->base_mip,
1943 .levelCount = iview->level_count,
1944 .baseArrayLayer = iview->base_layer,
1945 .layerCount = iview->layer_count,
1946 };
1947 uint32_t cond_val;
1948
1949 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1950 * depth clear value is 0.0f.
1951 */
1952 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1953
1954 radv_set_tc_compat_zrange_metadata(cmd_buffer, iview->image, &range,
1955 cond_val);
1956 }
1957
1958 /**
1959 * Update the clear depth/stencil values for this image.
1960 */
1961 void
1962 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1963 const struct radv_image_view *iview,
1964 VkClearDepthStencilValue ds_clear_value,
1965 VkImageAspectFlags aspects)
1966 {
1967 VkImageSubresourceRange range = {
1968 .aspectMask = iview->aspect_mask,
1969 .baseMipLevel = iview->base_mip,
1970 .levelCount = iview->level_count,
1971 .baseArrayLayer = iview->base_layer,
1972 .layerCount = iview->layer_count,
1973 };
1974 struct radv_image *image = iview->image;
1975
1976 assert(radv_image_has_htile(image));
1977
1978 radv_set_ds_clear_metadata(cmd_buffer, iview->image, &range,
1979 ds_clear_value, aspects);
1980
1981 if (radv_image_is_tc_compat_htile(image) &&
1982 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1983 radv_update_tc_compat_zrange_metadata(cmd_buffer, iview,
1984 ds_clear_value);
1985 }
1986
1987 radv_update_bound_fast_clear_ds(cmd_buffer, iview, ds_clear_value,
1988 aspects);
1989 }
1990
1991 /**
1992 * Load the clear depth/stencil values from the image's metadata.
1993 */
1994 static void
1995 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1996 const struct radv_image_view *iview)
1997 {
1998 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1999 const struct radv_image *image = iview->image;
2000 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
2001 uint64_t va = radv_get_ds_clear_value_va(image, iview->base_mip);
2002 unsigned reg_offset = 0, reg_count = 0;
2003
2004 if (!radv_image_has_htile(image))
2005 return;
2006
2007 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
2008 ++reg_count;
2009 } else {
2010 ++reg_offset;
2011 va += 4;
2012 }
2013 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
2014 ++reg_count;
2015
2016 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
2017
2018 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
2019 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG_INDEX, 3, 0));
2020 radeon_emit(cs, va);
2021 radeon_emit(cs, va >> 32);
2022 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
2023 radeon_emit(cs, reg_count);
2024 } else {
2025 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2026 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2027 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2028 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
2029 radeon_emit(cs, va);
2030 radeon_emit(cs, va >> 32);
2031 radeon_emit(cs, reg >> 2);
2032 radeon_emit(cs, 0);
2033
2034 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
2035 radeon_emit(cs, 0);
2036 }
2037 }
2038
2039 /*
2040 * With DCC some colors don't require CMASK elimination before being
2041 * used as a texture. This sets a predicate value to determine if the
2042 * cmask eliminate is required.
2043 */
2044 void
2045 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
2046 struct radv_image *image,
2047 const VkImageSubresourceRange *range, bool value)
2048 {
2049 uint64_t pred_val = value;
2050 uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
2051 uint32_t level_count = radv_get_levelCount(image, range);
2052 uint32_t count = 2 * level_count;
2053
2054 assert(radv_dcc_enabled(image, range->baseMipLevel));
2055
2056 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
2057 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
2058 S_370_WR_CONFIRM(1) |
2059 S_370_ENGINE_SEL(V_370_PFP));
2060 radeon_emit(cmd_buffer->cs, va);
2061 radeon_emit(cmd_buffer->cs, va >> 32);
2062
2063 for (uint32_t l = 0; l < level_count; l++) {
2064 radeon_emit(cmd_buffer->cs, pred_val);
2065 radeon_emit(cmd_buffer->cs, pred_val >> 32);
2066 }
2067 }
2068
2069 /**
2070 * Update the DCC predicate to reflect the compression state.
2071 */
2072 void
2073 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
2074 struct radv_image *image,
2075 const VkImageSubresourceRange *range, bool value)
2076 {
2077 uint64_t pred_val = value;
2078 uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
2079 uint32_t level_count = radv_get_levelCount(image, range);
2080 uint32_t count = 2 * level_count;
2081
2082 assert(radv_dcc_enabled(image, range->baseMipLevel));
2083
2084 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
2085 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
2086 S_370_WR_CONFIRM(1) |
2087 S_370_ENGINE_SEL(V_370_PFP));
2088 radeon_emit(cmd_buffer->cs, va);
2089 radeon_emit(cmd_buffer->cs, va >> 32);
2090
2091 for (uint32_t l = 0; l < level_count; l++) {
2092 radeon_emit(cmd_buffer->cs, pred_val);
2093 radeon_emit(cmd_buffer->cs, pred_val >> 32);
2094 }
2095 }
2096
2097 /**
2098 * Update the fast clear color values if the image is bound as a color buffer.
2099 */
2100 static void
2101 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
2102 struct radv_image *image,
2103 int cb_idx,
2104 uint32_t color_values[2])
2105 {
2106 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2107 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2108 uint32_t att_idx;
2109
2110 if (!cmd_buffer->state.attachments || !subpass)
2111 return;
2112
2113 att_idx = subpass->color_attachments[cb_idx].attachment;
2114 if (att_idx == VK_ATTACHMENT_UNUSED)
2115 return;
2116
2117 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
2118 return;
2119
2120 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
2121 radeon_emit(cs, color_values[0]);
2122 radeon_emit(cs, color_values[1]);
2123
2124 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2125 }
2126
2127 /**
2128 * Set the clear color values to the image's metadata.
2129 */
2130 static void
2131 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
2132 struct radv_image *image,
2133 const VkImageSubresourceRange *range,
2134 uint32_t color_values[2])
2135 {
2136 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2137 uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
2138 uint32_t level_count = radv_get_levelCount(image, range);
2139 uint32_t count = 2 * level_count;
2140
2141 assert(radv_image_has_cmask(image) ||
2142 radv_dcc_enabled(image, range->baseMipLevel));
2143
2144 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
2145 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
2146 S_370_WR_CONFIRM(1) |
2147 S_370_ENGINE_SEL(V_370_PFP));
2148 radeon_emit(cs, va);
2149 radeon_emit(cs, va >> 32);
2150
2151 for (uint32_t l = 0; l < level_count; l++) {
2152 radeon_emit(cs, color_values[0]);
2153 radeon_emit(cs, color_values[1]);
2154 }
2155 }
2156
2157 /**
2158 * Update the clear color values for this image.
2159 */
2160 void
2161 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
2162 const struct radv_image_view *iview,
2163 int cb_idx,
2164 uint32_t color_values[2])
2165 {
2166 struct radv_image *image = iview->image;
2167 VkImageSubresourceRange range = {
2168 .aspectMask = iview->aspect_mask,
2169 .baseMipLevel = iview->base_mip,
2170 .levelCount = iview->level_count,
2171 .baseArrayLayer = iview->base_layer,
2172 .layerCount = iview->layer_count,
2173 };
2174
2175 assert(radv_image_has_cmask(image) ||
2176 radv_dcc_enabled(image, iview->base_mip));
2177
2178 radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
2179
2180 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
2181 color_values);
2182 }
2183
2184 /**
2185 * Load the clear color values from the image's metadata.
2186 */
2187 static void
2188 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
2189 struct radv_image_view *iview,
2190 int cb_idx)
2191 {
2192 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2193 struct radv_image *image = iview->image;
2194 uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
2195
2196 if (!radv_image_has_cmask(image) &&
2197 !radv_dcc_enabled(image, iview->base_mip))
2198 return;
2199
2200 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
2201
2202 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
2203 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG_INDEX, 3, cmd_buffer->state.predicating));
2204 radeon_emit(cs, va);
2205 radeon_emit(cs, va >> 32);
2206 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
2207 radeon_emit(cs, 2);
2208 } else {
2209 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
2210 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2211 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2212 COPY_DATA_COUNT_SEL);
2213 radeon_emit(cs, va);
2214 radeon_emit(cs, va >> 32);
2215 radeon_emit(cs, reg >> 2);
2216 radeon_emit(cs, 0);
2217
2218 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
2219 radeon_emit(cs, 0);
2220 }
2221 }
2222
2223 static void
2224 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
2225 {
2226 int i;
2227 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
2228 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2229
2230 /* this may happen for inherited secondary recording */
2231 if (!framebuffer)
2232 return;
2233
2234 for (i = 0; i < 8; ++i) {
2235 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
2236 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2237 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2238 continue;
2239 }
2240
2241 int idx = subpass->color_attachments[i].attachment;
2242 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
2243 VkImageLayout layout = subpass->color_attachments[i].layout;
2244 bool in_render_loop = subpass->color_attachments[i].in_render_loop;
2245
2246 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, iview->bo);
2247
2248 assert(iview->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
2249 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
2250 radv_emit_fb_color_state(cmd_buffer, i, &cmd_buffer->state.attachments[idx].cb, iview, layout, in_render_loop);
2251
2252 radv_load_color_clear_metadata(cmd_buffer, iview, i);
2253 }
2254
2255 if (subpass->depth_stencil_attachment) {
2256 int idx = subpass->depth_stencil_attachment->attachment;
2257 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
2258 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
2259 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
2260 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, cmd_buffer->state.attachments[idx].iview->bo);
2261
2262 radv_emit_fb_ds_state(cmd_buffer, &cmd_buffer->state.attachments[idx].ds, iview, layout, in_render_loop);
2263
2264 if (cmd_buffer->state.attachments[idx].ds.offset_scale != cmd_buffer->state.offset_scale) {
2265 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2266 cmd_buffer->state.offset_scale = cmd_buffer->state.attachments[idx].ds.offset_scale;
2267 }
2268 radv_load_ds_clear_metadata(cmd_buffer, iview);
2269 } else {
2270 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9)
2271 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
2272 else
2273 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
2274
2275 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
2276 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
2277 }
2278 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2279 S_028208_BR_X(framebuffer->width) |
2280 S_028208_BR_Y(framebuffer->height));
2281
2282 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
2283 bool disable_constant_encode =
2284 cmd_buffer->device->physical_device->rad_info.has_dcc_constant_encode;
2285 enum chip_class chip_class =
2286 cmd_buffer->device->physical_device->rad_info.chip_class;
2287 uint8_t watermark = chip_class >= GFX10 ? 6 : 4;
2288
2289 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
2290 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class <= GFX9) |
2291 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
2292 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
2293 }
2294
2295 if (cmd_buffer->device->dfsm_allowed) {
2296 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2297 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
2298 }
2299
2300 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
2301 }
2302
2303 static void
2304 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer, bool indirect)
2305 {
2306 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2307 struct radv_cmd_state *state = &cmd_buffer->state;
2308
2309 if (state->index_type != state->last_index_type) {
2310 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2311 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2312 cs, R_03090C_VGT_INDEX_TYPE,
2313 2, state->index_type);
2314 } else {
2315 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2316 radeon_emit(cs, state->index_type);
2317 }
2318
2319 state->last_index_type = state->index_type;
2320 }
2321
2322 /* For the direct indexed draws we use DRAW_INDEX_2, which includes
2323 * the index_va and max_index_count already. */
2324 if (!indirect)
2325 return;
2326
2327 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2328 radeon_emit(cs, state->index_va);
2329 radeon_emit(cs, state->index_va >> 32);
2330
2331 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2332 radeon_emit(cs, state->max_index_count);
2333
2334 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
2335 }
2336
2337 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
2338 {
2339 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
2340 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2341 uint32_t pa_sc_mode_cntl_1 =
2342 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
2343 uint32_t db_count_control;
2344
2345 if(!cmd_buffer->state.active_occlusion_queries) {
2346 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2347 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2348 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2349 has_perfect_queries) {
2350 /* Re-enable out-of-order rasterization if the
2351 * bound pipeline supports it and if it's has
2352 * been disabled before starting any perfect
2353 * occlusion queries.
2354 */
2355 radeon_set_context_reg(cmd_buffer->cs,
2356 R_028A4C_PA_SC_MODE_CNTL_1,
2357 pa_sc_mode_cntl_1);
2358 }
2359 }
2360 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
2361 } else {
2362 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2363 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
2364 bool gfx10_perfect = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10 && has_perfect_queries;
2365
2366 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2367 /* Always enable PERFECT_ZPASS_COUNTS due to issues with partially
2368 * covered tiles, discards, and early depth testing. For more details,
2369 * see https://gitlab.freedesktop.org/mesa/mesa/-/issues/3218 */
2370 db_count_control =
2371 S_028004_PERFECT_ZPASS_COUNTS(1) |
2372 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
2373 S_028004_SAMPLE_RATE(sample_rate) |
2374 S_028004_ZPASS_ENABLE(1) |
2375 S_028004_SLICE_EVEN_ENABLE(1) |
2376 S_028004_SLICE_ODD_ENABLE(1);
2377
2378 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2379 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2380 has_perfect_queries) {
2381 /* If the bound pipeline has enabled
2382 * out-of-order rasterization, we should
2383 * disable it before starting any perfect
2384 * occlusion queries.
2385 */
2386 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
2387
2388 radeon_set_context_reg(cmd_buffer->cs,
2389 R_028A4C_PA_SC_MODE_CNTL_1,
2390 pa_sc_mode_cntl_1);
2391 }
2392 } else {
2393 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
2394 S_028004_SAMPLE_RATE(sample_rate);
2395 }
2396 }
2397
2398 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
2399
2400 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2401 }
2402
2403 static void
2404 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
2405 {
2406 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
2407
2408 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
2409 radv_emit_viewport(cmd_buffer);
2410
2411 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
2412 !cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
2413 radv_emit_scissor(cmd_buffer);
2414
2415 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
2416 radv_emit_line_width(cmd_buffer);
2417
2418 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
2419 radv_emit_blend_constants(cmd_buffer);
2420
2421 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
2422 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
2423 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
2424 radv_emit_stencil(cmd_buffer);
2425
2426 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
2427 radv_emit_depth_bounds(cmd_buffer);
2428
2429 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
2430 radv_emit_depth_bias(cmd_buffer);
2431
2432 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
2433 radv_emit_discard_rectangle(cmd_buffer);
2434
2435 if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)
2436 radv_emit_sample_locations(cmd_buffer);
2437
2438 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE)
2439 radv_emit_line_stipple(cmd_buffer);
2440
2441 if (states & (RADV_CMD_DIRTY_DYNAMIC_CULL_MODE |
2442 RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE))
2443 radv_emit_culling(cmd_buffer, states);
2444
2445 if (states & RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY)
2446 radv_emit_primitive_topology(cmd_buffer);
2447
2448 if (states & (RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE |
2449 RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE |
2450 RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP |
2451 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE |
2452 RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE |
2453 RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP))
2454 radv_emit_depth_control(cmd_buffer, states);
2455
2456 if (states & RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP)
2457 radv_emit_stencil_control(cmd_buffer);
2458
2459 cmd_buffer->state.dirty &= ~states;
2460 }
2461
2462 static void
2463 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
2464 VkPipelineBindPoint bind_point)
2465 {
2466 struct radv_descriptor_state *descriptors_state =
2467 radv_get_descriptors_state(cmd_buffer, bind_point);
2468 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
2469 unsigned bo_offset;
2470
2471 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
2472 set->mapped_ptr,
2473 &bo_offset))
2474 return;
2475
2476 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2477 set->va += bo_offset;
2478 }
2479
2480 static void
2481 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
2482 VkPipelineBindPoint bind_point)
2483 {
2484 struct radv_descriptor_state *descriptors_state =
2485 radv_get_descriptors_state(cmd_buffer, bind_point);
2486 uint32_t size = MAX_SETS * 4;
2487 uint32_t offset;
2488 void *ptr;
2489
2490 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
2491 256, &offset, &ptr))
2492 return;
2493
2494 for (unsigned i = 0; i < MAX_SETS; i++) {
2495 uint32_t *uptr = ((uint32_t *)ptr) + i;
2496 uint64_t set_va = 0;
2497 struct radv_descriptor_set *set = descriptors_state->sets[i];
2498 if (descriptors_state->valid & (1u << i))
2499 set_va = set->va;
2500 uptr[0] = set_va & 0xffffffff;
2501 }
2502
2503 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2504 va += offset;
2505
2506 if (cmd_buffer->state.pipeline) {
2507 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
2508 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2509 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2510
2511 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
2512 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
2513 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2514
2515 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
2516 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2517 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2518
2519 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2520 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
2521 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2522
2523 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2524 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
2525 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2526 }
2527
2528 if (cmd_buffer->state.compute_pipeline)
2529 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
2530 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2531 }
2532
2533 static void
2534 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
2535 VkShaderStageFlags stages)
2536 {
2537 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2538 VK_PIPELINE_BIND_POINT_COMPUTE :
2539 VK_PIPELINE_BIND_POINT_GRAPHICS;
2540 struct radv_descriptor_state *descriptors_state =
2541 radv_get_descriptors_state(cmd_buffer, bind_point);
2542 struct radv_cmd_state *state = &cmd_buffer->state;
2543 bool flush_indirect_descriptors;
2544
2545 if (!descriptors_state->dirty)
2546 return;
2547
2548 if (descriptors_state->push_dirty)
2549 radv_flush_push_descriptors(cmd_buffer, bind_point);
2550
2551 flush_indirect_descriptors =
2552 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
2553 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
2554 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
2555 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
2556
2557 if (flush_indirect_descriptors)
2558 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
2559
2560 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2561 cmd_buffer->cs,
2562 MAX_SETS * MESA_SHADER_STAGES * 4);
2563
2564 if (cmd_buffer->state.pipeline) {
2565 radv_foreach_stage(stage, stages) {
2566 if (!cmd_buffer->state.pipeline->shaders[stage])
2567 continue;
2568
2569 radv_emit_descriptor_pointers(cmd_buffer,
2570 cmd_buffer->state.pipeline,
2571 descriptors_state, stage);
2572 }
2573 }
2574
2575 if (cmd_buffer->state.compute_pipeline &&
2576 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
2577 radv_emit_descriptor_pointers(cmd_buffer,
2578 cmd_buffer->state.compute_pipeline,
2579 descriptors_state,
2580 MESA_SHADER_COMPUTE);
2581 }
2582
2583 descriptors_state->dirty = 0;
2584 descriptors_state->push_dirty = false;
2585
2586 assert(cmd_buffer->cs->cdw <= cdw_max);
2587
2588 if (unlikely(cmd_buffer->device->trace_bo))
2589 radv_save_descriptors(cmd_buffer, bind_point);
2590 }
2591
2592 static void
2593 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
2594 VkShaderStageFlags stages)
2595 {
2596 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
2597 ? cmd_buffer->state.compute_pipeline
2598 : cmd_buffer->state.pipeline;
2599 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2600 VK_PIPELINE_BIND_POINT_COMPUTE :
2601 VK_PIPELINE_BIND_POINT_GRAPHICS;
2602 struct radv_descriptor_state *descriptors_state =
2603 radv_get_descriptors_state(cmd_buffer, bind_point);
2604 struct radv_pipeline_layout *layout = pipeline->layout;
2605 struct radv_shader_variant *shader, *prev_shader;
2606 bool need_push_constants = false;
2607 unsigned offset;
2608 void *ptr;
2609 uint64_t va;
2610
2611 stages &= cmd_buffer->push_constant_stages;
2612 if (!stages ||
2613 (!layout->push_constant_size && !layout->dynamic_offset_count))
2614 return;
2615
2616 radv_foreach_stage(stage, stages) {
2617 shader = radv_get_shader(pipeline, stage);
2618 if (!shader)
2619 continue;
2620
2621 need_push_constants |= shader->info.loads_push_constants;
2622 need_push_constants |= shader->info.loads_dynamic_offsets;
2623
2624 uint8_t base = shader->info.base_inline_push_consts;
2625 uint8_t count = shader->info.num_inline_push_consts;
2626
2627 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
2628 AC_UD_INLINE_PUSH_CONSTANTS,
2629 count,
2630 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
2631 }
2632
2633 if (need_push_constants) {
2634 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
2635 16 * layout->dynamic_offset_count,
2636 256, &offset, &ptr))
2637 return;
2638
2639 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
2640 memcpy((char*)ptr + layout->push_constant_size,
2641 descriptors_state->dynamic_buffers,
2642 16 * layout->dynamic_offset_count);
2643
2644 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2645 va += offset;
2646
2647 ASSERTED unsigned cdw_max =
2648 radeon_check_space(cmd_buffer->device->ws,
2649 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
2650
2651 prev_shader = NULL;
2652 radv_foreach_stage(stage, stages) {
2653 shader = radv_get_shader(pipeline, stage);
2654
2655 /* Avoid redundantly emitting the address for merged stages. */
2656 if (shader && shader != prev_shader) {
2657 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
2658 AC_UD_PUSH_CONSTANTS, va);
2659
2660 prev_shader = shader;
2661 }
2662 }
2663 assert(cmd_buffer->cs->cdw <= cdw_max);
2664 }
2665
2666 cmd_buffer->push_constant_stages &= ~stages;
2667 }
2668
2669 static void
2670 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
2671 bool pipeline_is_dirty)
2672 {
2673 if ((pipeline_is_dirty ||
2674 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
2675 cmd_buffer->state.pipeline->num_vertex_bindings &&
2676 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.has_vertex_buffers) {
2677 unsigned vb_offset;
2678 void *vb_ptr;
2679 uint32_t i = 0;
2680 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
2681 uint64_t va;
2682
2683 /* allocate some descriptor state for vertex buffers */
2684 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2685 &vb_offset, &vb_ptr))
2686 return;
2687
2688 for (i = 0; i < count; i++) {
2689 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2690 uint32_t offset;
2691 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2692 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[i];
2693 unsigned num_records;
2694
2695 if (!buffer)
2696 continue;
2697
2698 va = radv_buffer_get_va(buffer->bo);
2699
2700 offset = cmd_buffer->vertex_bindings[i].offset;
2701 va += offset + buffer->offset;
2702
2703 num_records = buffer->size - offset;
2704 if (cmd_buffer->device->physical_device->rad_info.chip_class != GFX8 && stride)
2705 num_records /= stride;
2706
2707 desc[0] = va;
2708 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2709 desc[2] = num_records;
2710 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2711 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2712 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2713 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2714
2715 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2716 /* OOB_SELECT chooses the out-of-bounds check:
2717 * - 1: index >= NUM_RECORDS (Structured)
2718 * - 3: offset >= NUM_RECORDS (Raw)
2719 */
2720 int oob_select = stride ? V_008F0C_OOB_SELECT_STRUCTURED : V_008F0C_OOB_SELECT_RAW;
2721
2722 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT) |
2723 S_008F0C_OOB_SELECT(oob_select) |
2724 S_008F0C_RESOURCE_LEVEL(1);
2725 } else {
2726 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2727 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2728 }
2729 }
2730
2731 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2732 va += vb_offset;
2733
2734 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2735 AC_UD_VS_VERTEX_BUFFERS, va);
2736
2737 cmd_buffer->state.vb_va = va;
2738 cmd_buffer->state.vb_size = count * 16;
2739 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2740 }
2741 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2742 }
2743
2744 static void
2745 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2746 {
2747 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2748 struct radv_userdata_info *loc;
2749 uint32_t base_reg;
2750
2751 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2752 if (!radv_get_shader(pipeline, stage))
2753 continue;
2754
2755 loc = radv_lookup_user_sgpr(pipeline, stage,
2756 AC_UD_STREAMOUT_BUFFERS);
2757 if (loc->sgpr_idx == -1)
2758 continue;
2759
2760 base_reg = pipeline->user_data_0[stage];
2761
2762 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2763 base_reg + loc->sgpr_idx * 4, va, false);
2764 }
2765
2766 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
2767 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2768 if (loc->sgpr_idx != -1) {
2769 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2770
2771 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2772 base_reg + loc->sgpr_idx * 4, va, false);
2773 }
2774 }
2775 }
2776
2777 static void
2778 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2779 {
2780 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2781 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2782 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2783 unsigned so_offset;
2784 void *so_ptr;
2785 uint64_t va;
2786
2787 /* Allocate some descriptor state for streamout buffers. */
2788 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2789 MAX_SO_BUFFERS * 16, 256,
2790 &so_offset, &so_ptr))
2791 return;
2792
2793 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2794 struct radv_buffer *buffer = sb[i].buffer;
2795 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2796
2797 if (!(so->enabled_mask & (1 << i)))
2798 continue;
2799
2800 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2801
2802 va += sb[i].offset;
2803
2804 /* Set the descriptor.
2805 *
2806 * On GFX8, the format must be non-INVALID, otherwise
2807 * the buffer will be considered not bound and store
2808 * instructions will be no-ops.
2809 */
2810 uint32_t size = 0xffffffff;
2811
2812 /* Compute the correct buffer size for NGG streamout
2813 * because it's used to determine the max emit per
2814 * buffer.
2815 */
2816 if (cmd_buffer->device->physical_device->use_ngg_streamout)
2817 size = buffer->size - sb[i].offset;
2818
2819 desc[0] = va;
2820 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2821 desc[2] = size;
2822 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2823 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2824 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2825 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2826
2827 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2828 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2829 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
2830 S_008F0C_RESOURCE_LEVEL(1);
2831 } else {
2832 desc[3] |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2833 }
2834 }
2835
2836 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2837 va += so_offset;
2838
2839 radv_emit_streamout_buffers(cmd_buffer, va);
2840 }
2841
2842 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2843 }
2844
2845 static void
2846 radv_flush_ngg_gs_state(struct radv_cmd_buffer *cmd_buffer)
2847 {
2848 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2849 struct radv_userdata_info *loc;
2850 uint32_t ngg_gs_state = 0;
2851 uint32_t base_reg;
2852
2853 if (!radv_pipeline_has_gs(pipeline) ||
2854 !radv_pipeline_has_ngg(pipeline))
2855 return;
2856
2857 /* By default NGG GS queries are disabled but they are enabled if the
2858 * command buffer has active GDS queries or if it's a secondary command
2859 * buffer that inherits the number of generated primitives.
2860 */
2861 if (cmd_buffer->state.active_pipeline_gds_queries ||
2862 (cmd_buffer->state.inherited_pipeline_statistics & VK_QUERY_PIPELINE_STATISTIC_GEOMETRY_SHADER_PRIMITIVES_BIT))
2863 ngg_gs_state = 1;
2864
2865 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_GEOMETRY,
2866 AC_UD_NGG_GS_STATE);
2867 base_reg = pipeline->user_data_0[MESA_SHADER_GEOMETRY];
2868 assert(loc->sgpr_idx != -1);
2869
2870 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
2871 ngg_gs_state);
2872 }
2873
2874 static void
2875 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2876 {
2877 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2878 radv_flush_streamout_descriptors(cmd_buffer);
2879 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2880 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2881 radv_flush_ngg_gs_state(cmd_buffer);
2882 }
2883
2884 struct radv_draw_info {
2885 /**
2886 * Number of vertices.
2887 */
2888 uint32_t count;
2889
2890 /**
2891 * Index of the first vertex.
2892 */
2893 int32_t vertex_offset;
2894
2895 /**
2896 * First instance id.
2897 */
2898 uint32_t first_instance;
2899
2900 /**
2901 * Number of instances.
2902 */
2903 uint32_t instance_count;
2904
2905 /**
2906 * First index (indexed draws only).
2907 */
2908 uint32_t first_index;
2909
2910 /**
2911 * Whether it's an indexed draw.
2912 */
2913 bool indexed;
2914
2915 /**
2916 * Indirect draw parameters resource.
2917 */
2918 struct radv_buffer *indirect;
2919 uint64_t indirect_offset;
2920 uint32_t stride;
2921
2922 /**
2923 * Draw count parameters resource.
2924 */
2925 struct radv_buffer *count_buffer;
2926 uint64_t count_buffer_offset;
2927
2928 /**
2929 * Stream output parameters resource.
2930 */
2931 struct radv_buffer *strmout_buffer;
2932 uint64_t strmout_buffer_offset;
2933 };
2934
2935 static uint32_t
2936 radv_get_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
2937 {
2938 switch (cmd_buffer->state.index_type) {
2939 case V_028A7C_VGT_INDEX_8:
2940 return 0xffu;
2941 case V_028A7C_VGT_INDEX_16:
2942 return 0xffffu;
2943 case V_028A7C_VGT_INDEX_32:
2944 return 0xffffffffu;
2945 default:
2946 unreachable("invalid index type");
2947 }
2948 }
2949
2950 static void
2951 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
2952 bool instanced_draw, bool indirect_draw,
2953 bool count_from_stream_output,
2954 uint32_t draw_vertex_count)
2955 {
2956 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2957 struct radv_cmd_state *state = &cmd_buffer->state;
2958 unsigned topology = state->dynamic.primitive_topology;
2959 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2960 unsigned ia_multi_vgt_param;
2961
2962 ia_multi_vgt_param =
2963 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
2964 indirect_draw,
2965 count_from_stream_output,
2966 draw_vertex_count,
2967 topology);
2968
2969 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2970 if (info->chip_class == GFX9) {
2971 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2972 cs,
2973 R_030960_IA_MULTI_VGT_PARAM,
2974 4, ia_multi_vgt_param);
2975 } else if (info->chip_class >= GFX7) {
2976 radeon_set_context_reg_idx(cs,
2977 R_028AA8_IA_MULTI_VGT_PARAM,
2978 1, ia_multi_vgt_param);
2979 } else {
2980 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2981 ia_multi_vgt_param);
2982 }
2983 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2984 }
2985 }
2986
2987 static void
2988 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2989 const struct radv_draw_info *draw_info)
2990 {
2991 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2992 struct radv_cmd_state *state = &cmd_buffer->state;
2993 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2994 int32_t primitive_reset_en;
2995
2996 /* Draw state. */
2997 if (info->chip_class < GFX10) {
2998 si_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2999 draw_info->indirect,
3000 !!draw_info->strmout_buffer,
3001 draw_info->indirect ? 0 : draw_info->count);
3002 }
3003
3004 /* Primitive restart. */
3005 primitive_reset_en =
3006 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
3007
3008 if (primitive_reset_en != state->last_primitive_reset_en) {
3009 state->last_primitive_reset_en = primitive_reset_en;
3010 if (info->chip_class >= GFX9) {
3011 radeon_set_uconfig_reg(cs,
3012 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
3013 primitive_reset_en);
3014 } else {
3015 radeon_set_context_reg(cs,
3016 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
3017 primitive_reset_en);
3018 }
3019 }
3020
3021 if (primitive_reset_en) {
3022 uint32_t primitive_reset_index =
3023 radv_get_primitive_reset_index(cmd_buffer);
3024
3025 if (primitive_reset_index != state->last_primitive_reset_index) {
3026 radeon_set_context_reg(cs,
3027 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
3028 primitive_reset_index);
3029 state->last_primitive_reset_index = primitive_reset_index;
3030 }
3031 }
3032
3033 if (draw_info->strmout_buffer) {
3034 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
3035
3036 va += draw_info->strmout_buffer->offset +
3037 draw_info->strmout_buffer_offset;
3038
3039 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
3040 draw_info->stride);
3041
3042 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3043 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
3044 COPY_DATA_DST_SEL(COPY_DATA_REG) |
3045 COPY_DATA_WR_CONFIRM);
3046 radeon_emit(cs, va);
3047 radeon_emit(cs, va >> 32);
3048 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
3049 radeon_emit(cs, 0); /* unused */
3050
3051 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
3052 }
3053 }
3054
3055 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
3056 VkPipelineStageFlags src_stage_mask)
3057 {
3058 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
3059 VK_PIPELINE_STAGE_TRANSFER_BIT |
3060 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
3061 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
3062 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
3063 }
3064
3065 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
3066 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
3067 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
3068 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
3069 VK_PIPELINE_STAGE_TRANSFER_BIT |
3070 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
3071 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
3072 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
3073 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
3074 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
3075 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
3076 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
3077 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
3078 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
3079 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
3080 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
3081 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
3082 }
3083 }
3084
3085 static enum radv_cmd_flush_bits
3086 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
3087 VkAccessFlags src_flags,
3088 struct radv_image *image)
3089 {
3090 bool flush_CB_meta = true, flush_DB_meta = true;
3091 enum radv_cmd_flush_bits flush_bits = 0;
3092 uint32_t b;
3093
3094 if (image) {
3095 if (!radv_image_has_CB_metadata(image))
3096 flush_CB_meta = false;
3097 if (!radv_image_has_htile(image))
3098 flush_DB_meta = false;
3099 }
3100
3101 for_each_bit(b, src_flags) {
3102 switch ((VkAccessFlagBits)(1 << b)) {
3103 case VK_ACCESS_SHADER_WRITE_BIT:
3104 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
3105 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
3106 flush_bits |= RADV_CMD_FLAG_WB_L2;
3107 break;
3108 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
3109 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
3110 if (flush_CB_meta)
3111 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3112 break;
3113 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
3114 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
3115 if (flush_DB_meta)
3116 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3117 break;
3118 case VK_ACCESS_TRANSFER_WRITE_BIT:
3119 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3120 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3121 RADV_CMD_FLAG_INV_L2;
3122
3123 if (flush_CB_meta)
3124 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3125 if (flush_DB_meta)
3126 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3127 break;
3128 case VK_ACCESS_MEMORY_WRITE_BIT:
3129 flush_bits |= RADV_CMD_FLAG_INV_L2 |
3130 RADV_CMD_FLAG_WB_L2 |
3131 RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3132 RADV_CMD_FLAG_FLUSH_AND_INV_DB;
3133
3134 if (flush_CB_meta)
3135 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3136 if (flush_DB_meta)
3137 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3138 break;
3139 default:
3140 break;
3141 }
3142 }
3143 return flush_bits;
3144 }
3145
3146 static enum radv_cmd_flush_bits
3147 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
3148 VkAccessFlags dst_flags,
3149 struct radv_image *image)
3150 {
3151 bool flush_CB_meta = true, flush_DB_meta = true;
3152 enum radv_cmd_flush_bits flush_bits = 0;
3153 bool flush_CB = true, flush_DB = true;
3154 bool image_is_coherent = false;
3155 uint32_t b;
3156
3157 if (image) {
3158 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
3159 flush_CB = false;
3160 flush_DB = false;
3161 }
3162
3163 if (!radv_image_has_CB_metadata(image))
3164 flush_CB_meta = false;
3165 if (!radv_image_has_htile(image))
3166 flush_DB_meta = false;
3167
3168 /* TODO: implement shader coherent for GFX10 */
3169
3170 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
3171 if (image->info.samples == 1 &&
3172 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
3173 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
3174 !vk_format_is_stencil(image->vk_format)) {
3175 /* Single-sample color and single-sample depth
3176 * (not stencil) are coherent with shaders on
3177 * GFX9.
3178 */
3179 image_is_coherent = true;
3180 }
3181 }
3182 }
3183
3184 for_each_bit(b, dst_flags) {
3185 switch ((VkAccessFlagBits)(1 << b)) {
3186 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
3187 case VK_ACCESS_INDEX_READ_BIT:
3188 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
3189 break;
3190 case VK_ACCESS_UNIFORM_READ_BIT:
3191 flush_bits |= RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_SCACHE;
3192 break;
3193 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
3194 case VK_ACCESS_TRANSFER_READ_BIT:
3195 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
3196 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
3197 RADV_CMD_FLAG_INV_L2;
3198 break;
3199 case VK_ACCESS_SHADER_READ_BIT:
3200 flush_bits |= RADV_CMD_FLAG_INV_VCACHE;
3201 /* Unlike LLVM, ACO uses SMEM for SSBOs and we have to
3202 * invalidate the scalar cache. */
3203 if (!cmd_buffer->device->physical_device->use_llvm)
3204 flush_bits |= RADV_CMD_FLAG_INV_SCACHE;
3205
3206 if (!image_is_coherent)
3207 flush_bits |= RADV_CMD_FLAG_INV_L2;
3208 break;
3209 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
3210 if (flush_CB)
3211 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
3212 if (flush_CB_meta)
3213 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3214 break;
3215 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
3216 if (flush_DB)
3217 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
3218 if (flush_DB_meta)
3219 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3220 break;
3221 case VK_ACCESS_MEMORY_READ_BIT:
3222 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
3223 RADV_CMD_FLAG_INV_SCACHE |
3224 RADV_CMD_FLAG_INV_L2;
3225 if (flush_CB)
3226 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
3227 if (flush_CB_meta)
3228 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3229 if (flush_DB)
3230 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
3231 if (flush_DB_meta)
3232 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3233 break;
3234 default:
3235 break;
3236 }
3237 }
3238 return flush_bits;
3239 }
3240
3241 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
3242 const struct radv_subpass_barrier *barrier)
3243 {
3244 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
3245 NULL);
3246 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
3247 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
3248 NULL);
3249 }
3250
3251 uint32_t
3252 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
3253 {
3254 struct radv_cmd_state *state = &cmd_buffer->state;
3255 uint32_t subpass_id = state->subpass - state->pass->subpasses;
3256
3257 /* The id of this subpass shouldn't exceed the number of subpasses in
3258 * this render pass minus 1.
3259 */
3260 assert(subpass_id < state->pass->subpass_count);
3261 return subpass_id;
3262 }
3263
3264 static struct radv_sample_locations_state *
3265 radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer,
3266 uint32_t att_idx,
3267 bool begin_subpass)
3268 {
3269 struct radv_cmd_state *state = &cmd_buffer->state;
3270 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
3271 struct radv_image_view *view = state->attachments[att_idx].iview;
3272
3273 if (view->image->info.samples == 1)
3274 return NULL;
3275
3276 if (state->pass->attachments[att_idx].first_subpass_idx == subpass_id) {
3277 /* Return the initial sample locations if this is the initial
3278 * layout transition of the given subpass attachemnt.
3279 */
3280 if (state->attachments[att_idx].sample_location.count > 0)
3281 return &state->attachments[att_idx].sample_location;
3282 } else {
3283 /* Otherwise return the subpass sample locations if defined. */
3284 if (state->subpass_sample_locs) {
3285 /* Because the driver sets the current subpass before
3286 * initial layout transitions, we should use the sample
3287 * locations from the previous subpass to avoid an
3288 * off-by-one problem. Otherwise, use the sample
3289 * locations for the current subpass for final layout
3290 * transitions.
3291 */
3292 if (begin_subpass)
3293 subpass_id--;
3294
3295 for (uint32_t i = 0; i < state->num_subpass_sample_locs; i++) {
3296 if (state->subpass_sample_locs[i].subpass_idx == subpass_id)
3297 return &state->subpass_sample_locs[i].sample_location;
3298 }
3299 }
3300 }
3301
3302 return NULL;
3303 }
3304
3305 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
3306 struct radv_subpass_attachment att,
3307 bool begin_subpass)
3308 {
3309 unsigned idx = att.attachment;
3310 struct radv_image_view *view = cmd_buffer->state.attachments[idx].iview;
3311 struct radv_sample_locations_state *sample_locs;
3312 VkImageSubresourceRange range;
3313 range.aspectMask = view->aspect_mask;
3314 range.baseMipLevel = view->base_mip;
3315 range.levelCount = 1;
3316 range.baseArrayLayer = view->base_layer;
3317 range.layerCount = cmd_buffer->state.framebuffer->layers;
3318
3319 if (cmd_buffer->state.subpass->view_mask) {
3320 /* If the current subpass uses multiview, the driver might have
3321 * performed a fast color/depth clear to the whole image
3322 * (including all layers). To make sure the driver will
3323 * decompress the image correctly (if needed), we have to
3324 * account for the "real" number of layers. If the view mask is
3325 * sparse, this will decompress more layers than needed.
3326 */
3327 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
3328 }
3329
3330 /* Get the subpass sample locations for the given attachment, if NULL
3331 * is returned the driver will use the default HW locations.
3332 */
3333 sample_locs = radv_get_attachment_sample_locations(cmd_buffer, idx,
3334 begin_subpass);
3335
3336 /* Determine if the subpass uses separate depth/stencil layouts. */
3337 bool uses_separate_depth_stencil_layouts = false;
3338 if ((cmd_buffer->state.attachments[idx].current_layout !=
3339 cmd_buffer->state.attachments[idx].current_stencil_layout) ||
3340 (att.layout != att.stencil_layout)) {
3341 uses_separate_depth_stencil_layouts = true;
3342 }
3343
3344 /* For separate layouts, perform depth and stencil transitions
3345 * separately.
3346 */
3347 if (uses_separate_depth_stencil_layouts &&
3348 (range.aspectMask == (VK_IMAGE_ASPECT_DEPTH_BIT |
3349 VK_IMAGE_ASPECT_STENCIL_BIT))) {
3350 /* Depth-only transitions. */
3351 range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3352 radv_handle_image_transition(cmd_buffer,
3353 view->image,
3354 cmd_buffer->state.attachments[idx].current_layout,
3355 cmd_buffer->state.attachments[idx].current_in_render_loop,
3356 att.layout, att.in_render_loop,
3357 0, 0, &range, sample_locs);
3358
3359 /* Stencil-only transitions. */
3360 range.aspectMask = VK_IMAGE_ASPECT_STENCIL_BIT;
3361 radv_handle_image_transition(cmd_buffer,
3362 view->image,
3363 cmd_buffer->state.attachments[idx].current_stencil_layout,
3364 cmd_buffer->state.attachments[idx].current_in_render_loop,
3365 att.stencil_layout, att.in_render_loop,
3366 0, 0, &range, sample_locs);
3367 } else {
3368 radv_handle_image_transition(cmd_buffer,
3369 view->image,
3370 cmd_buffer->state.attachments[idx].current_layout,
3371 cmd_buffer->state.attachments[idx].current_in_render_loop,
3372 att.layout, att.in_render_loop,
3373 0, 0, &range, sample_locs);
3374 }
3375
3376 cmd_buffer->state.attachments[idx].current_layout = att.layout;
3377 cmd_buffer->state.attachments[idx].current_stencil_layout = att.stencil_layout;
3378 cmd_buffer->state.attachments[idx].current_in_render_loop = att.in_render_loop;
3379
3380
3381 }
3382
3383 void
3384 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
3385 const struct radv_subpass *subpass)
3386 {
3387 cmd_buffer->state.subpass = subpass;
3388
3389 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
3390 }
3391
3392 static VkResult
3393 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
3394 struct radv_render_pass *pass,
3395 const VkRenderPassBeginInfo *info)
3396 {
3397 const struct VkRenderPassSampleLocationsBeginInfoEXT *sample_locs =
3398 vk_find_struct_const(info->pNext,
3399 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT);
3400 struct radv_cmd_state *state = &cmd_buffer->state;
3401
3402 if (!sample_locs) {
3403 state->subpass_sample_locs = NULL;
3404 return VK_SUCCESS;
3405 }
3406
3407 for (uint32_t i = 0; i < sample_locs->attachmentInitialSampleLocationsCount; i++) {
3408 const VkAttachmentSampleLocationsEXT *att_sample_locs =
3409 &sample_locs->pAttachmentInitialSampleLocations[i];
3410 uint32_t att_idx = att_sample_locs->attachmentIndex;
3411 struct radv_image *image = cmd_buffer->state.attachments[att_idx].iview->image;
3412
3413 assert(vk_format_is_depth_or_stencil(image->vk_format));
3414
3415 /* From the Vulkan spec 1.1.108:
3416 *
3417 * "If the image referenced by the framebuffer attachment at
3418 * index attachmentIndex was not created with
3419 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
3420 * then the values specified in sampleLocationsInfo are
3421 * ignored."
3422 */
3423 if (!(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT))
3424 continue;
3425
3426 const VkSampleLocationsInfoEXT *sample_locs_info =
3427 &att_sample_locs->sampleLocationsInfo;
3428
3429 state->attachments[att_idx].sample_location.per_pixel =
3430 sample_locs_info->sampleLocationsPerPixel;
3431 state->attachments[att_idx].sample_location.grid_size =
3432 sample_locs_info->sampleLocationGridSize;
3433 state->attachments[att_idx].sample_location.count =
3434 sample_locs_info->sampleLocationsCount;
3435 typed_memcpy(&state->attachments[att_idx].sample_location.locations[0],
3436 sample_locs_info->pSampleLocations,
3437 sample_locs_info->sampleLocationsCount);
3438 }
3439
3440 state->subpass_sample_locs = vk_alloc(&cmd_buffer->pool->alloc,
3441 sample_locs->postSubpassSampleLocationsCount *
3442 sizeof(state->subpass_sample_locs[0]),
3443 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3444 if (state->subpass_sample_locs == NULL) {
3445 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3446 return cmd_buffer->record_result;
3447 }
3448
3449 state->num_subpass_sample_locs = sample_locs->postSubpassSampleLocationsCount;
3450
3451 for (uint32_t i = 0; i < sample_locs->postSubpassSampleLocationsCount; i++) {
3452 const VkSubpassSampleLocationsEXT *subpass_sample_locs_info =
3453 &sample_locs->pPostSubpassSampleLocations[i];
3454 const VkSampleLocationsInfoEXT *sample_locs_info =
3455 &subpass_sample_locs_info->sampleLocationsInfo;
3456
3457 state->subpass_sample_locs[i].subpass_idx =
3458 subpass_sample_locs_info->subpassIndex;
3459 state->subpass_sample_locs[i].sample_location.per_pixel =
3460 sample_locs_info->sampleLocationsPerPixel;
3461 state->subpass_sample_locs[i].sample_location.grid_size =
3462 sample_locs_info->sampleLocationGridSize;
3463 state->subpass_sample_locs[i].sample_location.count =
3464 sample_locs_info->sampleLocationsCount;
3465 typed_memcpy(&state->subpass_sample_locs[i].sample_location.locations[0],
3466 sample_locs_info->pSampleLocations,
3467 sample_locs_info->sampleLocationsCount);
3468 }
3469
3470 return VK_SUCCESS;
3471 }
3472
3473 static VkResult
3474 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
3475 struct radv_render_pass *pass,
3476 const VkRenderPassBeginInfo *info)
3477 {
3478 struct radv_cmd_state *state = &cmd_buffer->state;
3479 const struct VkRenderPassAttachmentBeginInfo *attachment_info = NULL;
3480
3481 if (info) {
3482 attachment_info = vk_find_struct_const(info->pNext,
3483 RENDER_PASS_ATTACHMENT_BEGIN_INFO);
3484 }
3485
3486
3487 if (pass->attachment_count == 0) {
3488 state->attachments = NULL;
3489 return VK_SUCCESS;
3490 }
3491
3492 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
3493 pass->attachment_count *
3494 sizeof(state->attachments[0]),
3495 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3496 if (state->attachments == NULL) {
3497 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3498 return cmd_buffer->record_result;
3499 }
3500
3501 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
3502 struct radv_render_pass_attachment *att = &pass->attachments[i];
3503 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
3504 VkImageAspectFlags clear_aspects = 0;
3505
3506 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
3507 /* color attachment */
3508 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3509 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
3510 }
3511 } else {
3512 /* depthstencil attachment */
3513 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
3514 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3515 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
3516 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3517 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
3518 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3519 }
3520 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3521 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3522 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3523 }
3524 }
3525
3526 state->attachments[i].pending_clear_aspects = clear_aspects;
3527 state->attachments[i].cleared_views = 0;
3528 if (clear_aspects && info) {
3529 assert(info->clearValueCount > i);
3530 state->attachments[i].clear_value = info->pClearValues[i];
3531 }
3532
3533 state->attachments[i].current_layout = att->initial_layout;
3534 state->attachments[i].current_stencil_layout = att->stencil_initial_layout;
3535 state->attachments[i].sample_location.count = 0;
3536
3537 struct radv_image_view *iview;
3538 if (attachment_info && attachment_info->attachmentCount > i) {
3539 iview = radv_image_view_from_handle(attachment_info->pAttachments[i]);
3540 } else {
3541 iview = state->framebuffer->attachments[i];
3542 }
3543
3544 state->attachments[i].iview = iview;
3545 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3546 radv_initialise_ds_surface(cmd_buffer->device, &state->attachments[i].ds, iview);
3547 } else {
3548 radv_initialise_color_surface(cmd_buffer->device, &state->attachments[i].cb, iview);
3549 }
3550 }
3551
3552 return VK_SUCCESS;
3553 }
3554
3555 VkResult radv_AllocateCommandBuffers(
3556 VkDevice _device,
3557 const VkCommandBufferAllocateInfo *pAllocateInfo,
3558 VkCommandBuffer *pCommandBuffers)
3559 {
3560 RADV_FROM_HANDLE(radv_device, device, _device);
3561 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
3562
3563 VkResult result = VK_SUCCESS;
3564 uint32_t i;
3565
3566 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
3567
3568 if (!list_is_empty(&pool->free_cmd_buffers)) {
3569 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
3570
3571 list_del(&cmd_buffer->pool_link);
3572 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
3573
3574 result = radv_reset_cmd_buffer(cmd_buffer);
3575 cmd_buffer->level = pAllocateInfo->level;
3576
3577 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
3578 } else {
3579 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
3580 &pCommandBuffers[i]);
3581 }
3582 if (result != VK_SUCCESS)
3583 break;
3584 }
3585
3586 if (result != VK_SUCCESS) {
3587 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
3588 i, pCommandBuffers);
3589
3590 /* From the Vulkan 1.0.66 spec:
3591 *
3592 * "vkAllocateCommandBuffers can be used to create multiple
3593 * command buffers. If the creation of any of those command
3594 * buffers fails, the implementation must destroy all
3595 * successfully created command buffer objects from this
3596 * command, set all entries of the pCommandBuffers array to
3597 * NULL and return the error."
3598 */
3599 memset(pCommandBuffers, 0,
3600 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
3601 }
3602
3603 return result;
3604 }
3605
3606 void radv_FreeCommandBuffers(
3607 VkDevice device,
3608 VkCommandPool commandPool,
3609 uint32_t commandBufferCount,
3610 const VkCommandBuffer *pCommandBuffers)
3611 {
3612 for (uint32_t i = 0; i < commandBufferCount; i++) {
3613 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
3614
3615 if (cmd_buffer) {
3616 if (cmd_buffer->pool) {
3617 list_del(&cmd_buffer->pool_link);
3618 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
3619 } else
3620 radv_cmd_buffer_destroy(cmd_buffer);
3621
3622 }
3623 }
3624 }
3625
3626 VkResult radv_ResetCommandBuffer(
3627 VkCommandBuffer commandBuffer,
3628 VkCommandBufferResetFlags flags)
3629 {
3630 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3631 return radv_reset_cmd_buffer(cmd_buffer);
3632 }
3633
3634 VkResult radv_BeginCommandBuffer(
3635 VkCommandBuffer commandBuffer,
3636 const VkCommandBufferBeginInfo *pBeginInfo)
3637 {
3638 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3639 VkResult result = VK_SUCCESS;
3640
3641 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
3642 /* If the command buffer has already been resetted with
3643 * vkResetCommandBuffer, no need to do it again.
3644 */
3645 result = radv_reset_cmd_buffer(cmd_buffer);
3646 if (result != VK_SUCCESS)
3647 return result;
3648 }
3649
3650 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
3651 cmd_buffer->state.last_primitive_reset_en = -1;
3652 cmd_buffer->state.last_index_type = -1;
3653 cmd_buffer->state.last_num_instances = -1;
3654 cmd_buffer->state.last_vertex_offset = -1;
3655 cmd_buffer->state.last_first_instance = -1;
3656 cmd_buffer->state.predication_type = -1;
3657 cmd_buffer->state.last_sx_ps_downconvert = -1;
3658 cmd_buffer->state.last_sx_blend_opt_epsilon = -1;
3659 cmd_buffer->state.last_sx_blend_opt_control = -1;
3660 cmd_buffer->usage_flags = pBeginInfo->flags;
3661
3662 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
3663 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
3664 assert(pBeginInfo->pInheritanceInfo);
3665 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
3666 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
3667
3668 struct radv_subpass *subpass =
3669 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
3670
3671 if (cmd_buffer->state.framebuffer) {
3672 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
3673 if (result != VK_SUCCESS)
3674 return result;
3675 }
3676
3677 cmd_buffer->state.inherited_pipeline_statistics =
3678 pBeginInfo->pInheritanceInfo->pipelineStatistics;
3679
3680 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3681 }
3682
3683 if (unlikely(cmd_buffer->device->trace_bo))
3684 radv_cmd_buffer_trace_emit(cmd_buffer);
3685
3686 radv_describe_begin_cmd_buffer(cmd_buffer);
3687
3688 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
3689
3690 return result;
3691 }
3692
3693 void radv_CmdBindVertexBuffers(
3694 VkCommandBuffer commandBuffer,
3695 uint32_t firstBinding,
3696 uint32_t bindingCount,
3697 const VkBuffer* pBuffers,
3698 const VkDeviceSize* pOffsets)
3699 {
3700 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3701 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
3702 bool changed = false;
3703
3704 /* We have to defer setting up vertex buffer since we need the buffer
3705 * stride from the pipeline. */
3706
3707 assert(firstBinding + bindingCount <= MAX_VBS);
3708 for (uint32_t i = 0; i < bindingCount; i++) {
3709 RADV_FROM_HANDLE(radv_buffer, buffer, pBuffers[i]);
3710 uint32_t idx = firstBinding + i;
3711
3712 if (!changed &&
3713 (vb[idx].buffer != buffer ||
3714 vb[idx].offset != pOffsets[i])) {
3715 changed = true;
3716 }
3717
3718 vb[idx].buffer = buffer;
3719 vb[idx].offset = pOffsets[i];
3720
3721 if (buffer) {
3722 radv_cs_add_buffer(cmd_buffer->device->ws,
3723 cmd_buffer->cs, vb[idx].buffer->bo);
3724 }
3725 }
3726
3727 if (!changed) {
3728 /* No state changes. */
3729 return;
3730 }
3731
3732 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
3733 }
3734
3735 static uint32_t
3736 vk_to_index_type(VkIndexType type)
3737 {
3738 switch (type) {
3739 case VK_INDEX_TYPE_UINT8_EXT:
3740 return V_028A7C_VGT_INDEX_8;
3741 case VK_INDEX_TYPE_UINT16:
3742 return V_028A7C_VGT_INDEX_16;
3743 case VK_INDEX_TYPE_UINT32:
3744 return V_028A7C_VGT_INDEX_32;
3745 default:
3746 unreachable("invalid index type");
3747 }
3748 }
3749
3750 static uint32_t
3751 radv_get_vgt_index_size(uint32_t type)
3752 {
3753 switch (type) {
3754 case V_028A7C_VGT_INDEX_8:
3755 return 1;
3756 case V_028A7C_VGT_INDEX_16:
3757 return 2;
3758 case V_028A7C_VGT_INDEX_32:
3759 return 4;
3760 default:
3761 unreachable("invalid index type");
3762 }
3763 }
3764
3765 void radv_CmdBindIndexBuffer(
3766 VkCommandBuffer commandBuffer,
3767 VkBuffer buffer,
3768 VkDeviceSize offset,
3769 VkIndexType indexType)
3770 {
3771 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3772 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
3773
3774 if (cmd_buffer->state.index_buffer == index_buffer &&
3775 cmd_buffer->state.index_offset == offset &&
3776 cmd_buffer->state.index_type == indexType) {
3777 /* No state changes. */
3778 return;
3779 }
3780
3781 cmd_buffer->state.index_buffer = index_buffer;
3782 cmd_buffer->state.index_offset = offset;
3783 cmd_buffer->state.index_type = vk_to_index_type(indexType);
3784 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
3785 cmd_buffer->state.index_va += index_buffer->offset + offset;
3786
3787 int index_size = radv_get_vgt_index_size(vk_to_index_type(indexType));
3788 cmd_buffer->state.max_index_count = (index_buffer->size - offset) / index_size;
3789 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3790 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
3791 }
3792
3793
3794 static void
3795 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3796 VkPipelineBindPoint bind_point,
3797 struct radv_descriptor_set *set, unsigned idx)
3798 {
3799 struct radeon_winsys *ws = cmd_buffer->device->ws;
3800
3801 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
3802
3803 assert(set);
3804 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
3805
3806 if (!cmd_buffer->device->use_global_bo_list) {
3807 for (unsigned j = 0; j < set->buffer_count; ++j)
3808 if (set->descriptors[j])
3809 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
3810 }
3811
3812 if(set->bo)
3813 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
3814 }
3815
3816 void radv_CmdBindDescriptorSets(
3817 VkCommandBuffer commandBuffer,
3818 VkPipelineBindPoint pipelineBindPoint,
3819 VkPipelineLayout _layout,
3820 uint32_t firstSet,
3821 uint32_t descriptorSetCount,
3822 const VkDescriptorSet* pDescriptorSets,
3823 uint32_t dynamicOffsetCount,
3824 const uint32_t* pDynamicOffsets)
3825 {
3826 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3827 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3828 unsigned dyn_idx = 0;
3829
3830 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
3831 struct radv_descriptor_state *descriptors_state =
3832 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3833
3834 for (unsigned i = 0; i < descriptorSetCount; ++i) {
3835 unsigned idx = i + firstSet;
3836 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
3837
3838 /* If the set is already bound we only need to update the
3839 * (potentially changed) dynamic offsets. */
3840 if (descriptors_state->sets[idx] != set ||
3841 !(descriptors_state->valid & (1u << idx))) {
3842 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
3843 }
3844
3845 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
3846 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
3847 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
3848 assert(dyn_idx < dynamicOffsetCount);
3849
3850 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
3851 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
3852 dst[0] = va;
3853 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
3854 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
3855 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3856 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3857 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3858 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3859
3860 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
3861 dst[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3862 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3863 S_008F0C_RESOURCE_LEVEL(1);
3864 } else {
3865 dst[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3866 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3867 }
3868
3869 cmd_buffer->push_constant_stages |=
3870 set->layout->dynamic_shader_stages;
3871 }
3872 }
3873 }
3874
3875 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3876 struct radv_descriptor_set *set,
3877 struct radv_descriptor_set_layout *layout,
3878 VkPipelineBindPoint bind_point)
3879 {
3880 struct radv_descriptor_state *descriptors_state =
3881 radv_get_descriptors_state(cmd_buffer, bind_point);
3882 set->size = layout->size;
3883 set->layout = layout;
3884
3885 if (descriptors_state->push_set.capacity < set->size) {
3886 size_t new_size = MAX2(set->size, 1024);
3887 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
3888 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
3889
3890 free(set->mapped_ptr);
3891 set->mapped_ptr = malloc(new_size);
3892
3893 if (!set->mapped_ptr) {
3894 descriptors_state->push_set.capacity = 0;
3895 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3896 return false;
3897 }
3898
3899 descriptors_state->push_set.capacity = new_size;
3900 }
3901
3902 return true;
3903 }
3904
3905 void radv_meta_push_descriptor_set(
3906 struct radv_cmd_buffer* cmd_buffer,
3907 VkPipelineBindPoint pipelineBindPoint,
3908 VkPipelineLayout _layout,
3909 uint32_t set,
3910 uint32_t descriptorWriteCount,
3911 const VkWriteDescriptorSet* pDescriptorWrites)
3912 {
3913 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3914 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
3915 unsigned bo_offset;
3916
3917 assert(set == 0);
3918 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3919
3920 push_set->size = layout->set[set].layout->size;
3921 push_set->layout = layout->set[set].layout;
3922
3923 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
3924 &bo_offset,
3925 (void**) &push_set->mapped_ptr))
3926 return;
3927
3928 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
3929 push_set->va += bo_offset;
3930
3931 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3932 radv_descriptor_set_to_handle(push_set),
3933 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3934
3935 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3936 }
3937
3938 void radv_CmdPushDescriptorSetKHR(
3939 VkCommandBuffer commandBuffer,
3940 VkPipelineBindPoint pipelineBindPoint,
3941 VkPipelineLayout _layout,
3942 uint32_t set,
3943 uint32_t descriptorWriteCount,
3944 const VkWriteDescriptorSet* pDescriptorWrites)
3945 {
3946 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3947 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3948 struct radv_descriptor_state *descriptors_state =
3949 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3950 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3951
3952 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3953
3954 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3955 layout->set[set].layout,
3956 pipelineBindPoint))
3957 return;
3958
3959 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3960 * because it is invalid, according to Vulkan spec.
3961 */
3962 for (int i = 0; i < descriptorWriteCount; i++) {
3963 ASSERTED const VkWriteDescriptorSet *writeset = &pDescriptorWrites[i];
3964 assert(writeset->descriptorType != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT);
3965 }
3966
3967 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3968 radv_descriptor_set_to_handle(push_set),
3969 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3970
3971 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3972 descriptors_state->push_dirty = true;
3973 }
3974
3975 void radv_CmdPushDescriptorSetWithTemplateKHR(
3976 VkCommandBuffer commandBuffer,
3977 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
3978 VkPipelineLayout _layout,
3979 uint32_t set,
3980 const void* pData)
3981 {
3982 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3983 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3984 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
3985 struct radv_descriptor_state *descriptors_state =
3986 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
3987 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3988
3989 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3990
3991 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3992 layout->set[set].layout,
3993 templ->bind_point))
3994 return;
3995
3996 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
3997 descriptorUpdateTemplate, pData);
3998
3999 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
4000 descriptors_state->push_dirty = true;
4001 }
4002
4003 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
4004 VkPipelineLayout layout,
4005 VkShaderStageFlags stageFlags,
4006 uint32_t offset,
4007 uint32_t size,
4008 const void* pValues)
4009 {
4010 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4011 memcpy(cmd_buffer->push_constants + offset, pValues, size);
4012 cmd_buffer->push_constant_stages |= stageFlags;
4013 }
4014
4015 VkResult radv_EndCommandBuffer(
4016 VkCommandBuffer commandBuffer)
4017 {
4018 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4019
4020 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
4021 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6)
4022 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WB_L2;
4023
4024 /* Make sure to sync all pending active queries at the end of
4025 * command buffer.
4026 */
4027 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
4028
4029 /* Since NGG streamout uses GDS, we need to make GDS idle when
4030 * we leave the IB, otherwise another process might overwrite
4031 * it while our shaders are busy.
4032 */
4033 if (cmd_buffer->gds_needed)
4034 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
4035
4036 si_emit_cache_flush(cmd_buffer);
4037 }
4038
4039 /* Make sure CP DMA is idle at the end of IBs because the kernel
4040 * doesn't wait for it.
4041 */
4042 si_cp_dma_wait_for_idle(cmd_buffer);
4043
4044 radv_describe_end_cmd_buffer(cmd_buffer);
4045
4046 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
4047 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
4048
4049 VkResult result = cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs);
4050 if (result != VK_SUCCESS)
4051 return vk_error(cmd_buffer->device->instance, result);
4052
4053 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
4054
4055 return cmd_buffer->record_result;
4056 }
4057
4058 static void
4059 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
4060 {
4061 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4062
4063 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
4064 return;
4065
4066 assert(!pipeline->ctx_cs.cdw);
4067
4068 cmd_buffer->state.emitted_compute_pipeline = pipeline;
4069
4070 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
4071 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
4072
4073 cmd_buffer->compute_scratch_size_per_wave_needed = MAX2(cmd_buffer->compute_scratch_size_per_wave_needed,
4074 pipeline->scratch_bytes_per_wave);
4075 cmd_buffer->compute_scratch_waves_wanted = MAX2(cmd_buffer->compute_scratch_waves_wanted,
4076 pipeline->max_waves);
4077
4078 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
4079 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
4080
4081 if (unlikely(cmd_buffer->device->trace_bo))
4082 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
4083 }
4084
4085 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
4086 VkPipelineBindPoint bind_point)
4087 {
4088 struct radv_descriptor_state *descriptors_state =
4089 radv_get_descriptors_state(cmd_buffer, bind_point);
4090
4091 descriptors_state->dirty |= descriptors_state->valid;
4092 }
4093
4094 void radv_CmdBindPipeline(
4095 VkCommandBuffer commandBuffer,
4096 VkPipelineBindPoint pipelineBindPoint,
4097 VkPipeline _pipeline)
4098 {
4099 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4100 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
4101
4102 switch (pipelineBindPoint) {
4103 case VK_PIPELINE_BIND_POINT_COMPUTE:
4104 if (cmd_buffer->state.compute_pipeline == pipeline)
4105 return;
4106 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
4107
4108 cmd_buffer->state.compute_pipeline = pipeline;
4109 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
4110 break;
4111 case VK_PIPELINE_BIND_POINT_GRAPHICS:
4112 if (cmd_buffer->state.pipeline == pipeline)
4113 return;
4114 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
4115
4116 cmd_buffer->state.pipeline = pipeline;
4117 if (!pipeline)
4118 break;
4119
4120 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
4121 cmd_buffer->push_constant_stages |= pipeline->active_stages;
4122
4123 /* the new vertex shader might not have the same user regs */
4124 cmd_buffer->state.last_first_instance = -1;
4125 cmd_buffer->state.last_vertex_offset = -1;
4126
4127 /* Prefetch all pipeline shaders at first draw time. */
4128 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
4129
4130 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX10 &&
4131 cmd_buffer->state.emitted_pipeline &&
4132 radv_pipeline_has_ngg(cmd_buffer->state.emitted_pipeline) &&
4133 !radv_pipeline_has_ngg(cmd_buffer->state.pipeline)) {
4134 /* Transitioning from NGG to legacy GS requires
4135 * VGT_FLUSH on Navi10-14. VGT_FLUSH is also emitted
4136 * at the beginning of IBs when legacy GS ring pointers
4137 * are set.
4138 */
4139 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
4140 }
4141
4142 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
4143 radv_bind_streamout_state(cmd_buffer, pipeline);
4144
4145 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
4146 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
4147 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
4148 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
4149
4150 if (radv_pipeline_has_tess(pipeline))
4151 cmd_buffer->tess_rings_needed = true;
4152 break;
4153 default:
4154 assert(!"invalid bind point");
4155 break;
4156 }
4157 }
4158
4159 void radv_CmdSetViewport(
4160 VkCommandBuffer commandBuffer,
4161 uint32_t firstViewport,
4162 uint32_t viewportCount,
4163 const VkViewport* pViewports)
4164 {
4165 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4166 struct radv_cmd_state *state = &cmd_buffer->state;
4167 ASSERTED const uint32_t total_count = firstViewport + viewportCount;
4168
4169 assert(firstViewport < MAX_VIEWPORTS);
4170 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
4171
4172 if (total_count <= state->dynamic.viewport.count &&
4173 !memcmp(state->dynamic.viewport.viewports + firstViewport,
4174 pViewports, viewportCount * sizeof(*pViewports))) {
4175 return;
4176 }
4177
4178 if (state->dynamic.viewport.count < total_count)
4179 state->dynamic.viewport.count = total_count;
4180
4181 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
4182 viewportCount * sizeof(*pViewports));
4183
4184 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
4185 }
4186
4187 void radv_CmdSetScissor(
4188 VkCommandBuffer commandBuffer,
4189 uint32_t firstScissor,
4190 uint32_t scissorCount,
4191 const VkRect2D* pScissors)
4192 {
4193 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4194 struct radv_cmd_state *state = &cmd_buffer->state;
4195 ASSERTED const uint32_t total_count = firstScissor + scissorCount;
4196
4197 assert(firstScissor < MAX_SCISSORS);
4198 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
4199
4200 if (total_count <= state->dynamic.scissor.count &&
4201 !memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
4202 scissorCount * sizeof(*pScissors))) {
4203 return;
4204 }
4205
4206 if (state->dynamic.scissor.count < total_count)
4207 state->dynamic.scissor.count = total_count;
4208
4209 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
4210 scissorCount * sizeof(*pScissors));
4211
4212 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
4213 }
4214
4215 void radv_CmdSetLineWidth(
4216 VkCommandBuffer commandBuffer,
4217 float lineWidth)
4218 {
4219 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4220
4221 if (cmd_buffer->state.dynamic.line_width == lineWidth)
4222 return;
4223
4224 cmd_buffer->state.dynamic.line_width = lineWidth;
4225 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
4226 }
4227
4228 void radv_CmdSetDepthBias(
4229 VkCommandBuffer commandBuffer,
4230 float depthBiasConstantFactor,
4231 float depthBiasClamp,
4232 float depthBiasSlopeFactor)
4233 {
4234 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4235 struct radv_cmd_state *state = &cmd_buffer->state;
4236
4237 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
4238 state->dynamic.depth_bias.clamp == depthBiasClamp &&
4239 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
4240 return;
4241 }
4242
4243 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
4244 state->dynamic.depth_bias.clamp = depthBiasClamp;
4245 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
4246
4247 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
4248 }
4249
4250 void radv_CmdSetBlendConstants(
4251 VkCommandBuffer commandBuffer,
4252 const float blendConstants[4])
4253 {
4254 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4255 struct radv_cmd_state *state = &cmd_buffer->state;
4256
4257 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
4258 return;
4259
4260 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
4261
4262 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
4263 }
4264
4265 void radv_CmdSetDepthBounds(
4266 VkCommandBuffer commandBuffer,
4267 float minDepthBounds,
4268 float maxDepthBounds)
4269 {
4270 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4271 struct radv_cmd_state *state = &cmd_buffer->state;
4272
4273 if (state->dynamic.depth_bounds.min == minDepthBounds &&
4274 state->dynamic.depth_bounds.max == maxDepthBounds) {
4275 return;
4276 }
4277
4278 state->dynamic.depth_bounds.min = minDepthBounds;
4279 state->dynamic.depth_bounds.max = maxDepthBounds;
4280
4281 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
4282 }
4283
4284 void radv_CmdSetStencilCompareMask(
4285 VkCommandBuffer commandBuffer,
4286 VkStencilFaceFlags faceMask,
4287 uint32_t compareMask)
4288 {
4289 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4290 struct radv_cmd_state *state = &cmd_buffer->state;
4291 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
4292 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
4293
4294 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4295 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4296 return;
4297 }
4298
4299 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4300 state->dynamic.stencil_compare_mask.front = compareMask;
4301 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4302 state->dynamic.stencil_compare_mask.back = compareMask;
4303
4304 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
4305 }
4306
4307 void radv_CmdSetStencilWriteMask(
4308 VkCommandBuffer commandBuffer,
4309 VkStencilFaceFlags faceMask,
4310 uint32_t writeMask)
4311 {
4312 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4313 struct radv_cmd_state *state = &cmd_buffer->state;
4314 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
4315 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
4316
4317 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4318 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4319 return;
4320 }
4321
4322 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4323 state->dynamic.stencil_write_mask.front = writeMask;
4324 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4325 state->dynamic.stencil_write_mask.back = writeMask;
4326
4327 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
4328 }
4329
4330 void radv_CmdSetStencilReference(
4331 VkCommandBuffer commandBuffer,
4332 VkStencilFaceFlags faceMask,
4333 uint32_t reference)
4334 {
4335 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4336 struct radv_cmd_state *state = &cmd_buffer->state;
4337 bool front_same = state->dynamic.stencil_reference.front == reference;
4338 bool back_same = state->dynamic.stencil_reference.back == reference;
4339
4340 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4341 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4342 return;
4343 }
4344
4345 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4346 cmd_buffer->state.dynamic.stencil_reference.front = reference;
4347 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4348 cmd_buffer->state.dynamic.stencil_reference.back = reference;
4349
4350 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
4351 }
4352
4353 void radv_CmdSetDiscardRectangleEXT(
4354 VkCommandBuffer commandBuffer,
4355 uint32_t firstDiscardRectangle,
4356 uint32_t discardRectangleCount,
4357 const VkRect2D* pDiscardRectangles)
4358 {
4359 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4360 struct radv_cmd_state *state = &cmd_buffer->state;
4361 ASSERTED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
4362
4363 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
4364 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
4365
4366 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
4367 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
4368 return;
4369 }
4370
4371 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
4372 pDiscardRectangles, discardRectangleCount);
4373
4374 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
4375 }
4376
4377 void radv_CmdSetSampleLocationsEXT(
4378 VkCommandBuffer commandBuffer,
4379 const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
4380 {
4381 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4382 struct radv_cmd_state *state = &cmd_buffer->state;
4383
4384 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
4385
4386 state->dynamic.sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
4387 state->dynamic.sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
4388 state->dynamic.sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
4389 typed_memcpy(&state->dynamic.sample_location.locations[0],
4390 pSampleLocationsInfo->pSampleLocations,
4391 pSampleLocationsInfo->sampleLocationsCount);
4392
4393 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS;
4394 }
4395
4396 void radv_CmdSetLineStippleEXT(
4397 VkCommandBuffer commandBuffer,
4398 uint32_t lineStippleFactor,
4399 uint16_t lineStipplePattern)
4400 {
4401 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4402 struct radv_cmd_state *state = &cmd_buffer->state;
4403
4404 state->dynamic.line_stipple.factor = lineStippleFactor;
4405 state->dynamic.line_stipple.pattern = lineStipplePattern;
4406
4407 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE;
4408 }
4409
4410 void radv_CmdSetCullModeEXT(
4411 VkCommandBuffer commandBuffer,
4412 VkCullModeFlags cullMode)
4413 {
4414 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4415 struct radv_cmd_state *state = &cmd_buffer->state;
4416
4417 if (state->dynamic.cull_mode == cullMode)
4418 return;
4419
4420 state->dynamic.cull_mode = cullMode;
4421
4422 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_CULL_MODE;
4423 }
4424
4425 void radv_CmdSetFrontFaceEXT(
4426 VkCommandBuffer commandBuffer,
4427 VkFrontFace frontFace)
4428 {
4429 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4430 struct radv_cmd_state *state = &cmd_buffer->state;
4431
4432 if (state->dynamic.front_face == frontFace)
4433 return;
4434
4435 state->dynamic.front_face = frontFace;
4436
4437 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE;
4438 }
4439
4440 void radv_CmdSetPrimitiveTopologyEXT(
4441 VkCommandBuffer commandBuffer,
4442 VkPrimitiveTopology primitiveTopology)
4443 {
4444 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4445 struct radv_cmd_state *state = &cmd_buffer->state;
4446 unsigned primitive_topology = si_translate_prim(primitiveTopology);
4447
4448 if (state->dynamic.primitive_topology == primitive_topology)
4449 return;
4450
4451 state->dynamic.primitive_topology = primitive_topology;
4452
4453 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY;
4454 }
4455
4456 void radv_CmdSetViewportWithCountEXT(
4457 VkCommandBuffer commandBuffer,
4458 uint32_t viewportCount,
4459 const VkViewport* pViewports)
4460 {
4461 radv_CmdSetViewport(commandBuffer, 0, viewportCount, pViewports);
4462 }
4463
4464 void radv_CmdSetScissorWithCountEXT(
4465 VkCommandBuffer commandBuffer,
4466 uint32_t scissorCount,
4467 const VkRect2D* pScissors)
4468 {
4469 radv_CmdSetScissor(commandBuffer, 0, scissorCount, pScissors);
4470 }
4471
4472 void radv_CmdSetDepthTestEnableEXT(
4473 VkCommandBuffer commandBuffer,
4474 VkBool32 depthTestEnable)
4475
4476 {
4477 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4478 struct radv_cmd_state *state = &cmd_buffer->state;
4479
4480 if (state->dynamic.depth_test_enable == depthTestEnable)
4481 return;
4482
4483 state->dynamic.depth_test_enable = depthTestEnable;
4484
4485 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE;
4486 }
4487
4488 void radv_CmdSetDepthWriteEnableEXT(
4489 VkCommandBuffer commandBuffer,
4490 VkBool32 depthWriteEnable)
4491 {
4492 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4493 struct radv_cmd_state *state = &cmd_buffer->state;
4494
4495 if (state->dynamic.depth_write_enable == depthWriteEnable)
4496 return;
4497
4498 state->dynamic.depth_write_enable = depthWriteEnable;
4499
4500 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE;
4501 }
4502
4503 void radv_CmdSetDepthCompareOpEXT(
4504 VkCommandBuffer commandBuffer,
4505 VkCompareOp depthCompareOp)
4506 {
4507 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4508 struct radv_cmd_state *state = &cmd_buffer->state;
4509
4510 if (state->dynamic.depth_compare_op == depthCompareOp)
4511 return;
4512
4513 state->dynamic.depth_compare_op = depthCompareOp;
4514
4515 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP;
4516 }
4517
4518 void radv_CmdSetDepthBoundsTestEnableEXT(
4519 VkCommandBuffer commandBuffer,
4520 VkBool32 depthBoundsTestEnable)
4521 {
4522 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4523 struct radv_cmd_state *state = &cmd_buffer->state;
4524
4525 if (state->dynamic.depth_bounds_test_enable == depthBoundsTestEnable)
4526 return;
4527
4528 state->dynamic.depth_bounds_test_enable = depthBoundsTestEnable;
4529
4530 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE;
4531 }
4532
4533 void radv_CmdSetStencilTestEnableEXT(
4534 VkCommandBuffer commandBuffer,
4535 VkBool32 stencilTestEnable)
4536 {
4537 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4538 struct radv_cmd_state *state = &cmd_buffer->state;
4539
4540 if (state->dynamic.stencil_test_enable == stencilTestEnable)
4541 return;
4542
4543 state->dynamic.stencil_test_enable = stencilTestEnable;
4544
4545 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE;
4546 }
4547
4548 void radv_CmdSetStencilOpEXT(
4549 VkCommandBuffer commandBuffer,
4550 VkStencilFaceFlags faceMask,
4551 VkStencilOp failOp,
4552 VkStencilOp passOp,
4553 VkStencilOp depthFailOp,
4554 VkCompareOp compareOp)
4555 {
4556 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4557 struct radv_cmd_state *state = &cmd_buffer->state;
4558 bool front_same =
4559 state->dynamic.stencil_op.front.fail_op == failOp &&
4560 state->dynamic.stencil_op.front.pass_op == passOp &&
4561 state->dynamic.stencil_op.front.depth_fail_op == depthFailOp &&
4562 state->dynamic.stencil_op.front.compare_op == compareOp;
4563 bool back_same =
4564 state->dynamic.stencil_op.back.fail_op == failOp &&
4565 state->dynamic.stencil_op.back.pass_op == passOp &&
4566 state->dynamic.stencil_op.back.depth_fail_op == depthFailOp &&
4567 state->dynamic.stencil_op.back.compare_op == compareOp;
4568
4569 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4570 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same))
4571 return;
4572
4573 if (faceMask & VK_STENCIL_FACE_FRONT_BIT) {
4574 state->dynamic.stencil_op.front.fail_op = failOp;
4575 state->dynamic.stencil_op.front.pass_op = passOp;
4576 state->dynamic.stencil_op.front.depth_fail_op = depthFailOp;
4577 state->dynamic.stencil_op.front.compare_op = compareOp;
4578 }
4579
4580 if (faceMask & VK_STENCIL_FACE_BACK_BIT) {
4581 state->dynamic.stencil_op.back.fail_op = failOp;
4582 state->dynamic.stencil_op.back.pass_op = passOp;
4583 state->dynamic.stencil_op.back.depth_fail_op = depthFailOp;
4584 state->dynamic.stencil_op.back.compare_op = compareOp;
4585 }
4586
4587 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP;
4588 }
4589
4590 void radv_CmdExecuteCommands(
4591 VkCommandBuffer commandBuffer,
4592 uint32_t commandBufferCount,
4593 const VkCommandBuffer* pCmdBuffers)
4594 {
4595 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
4596
4597 assert(commandBufferCount > 0);
4598
4599 /* Emit pending flushes on primary prior to executing secondary */
4600 si_emit_cache_flush(primary);
4601
4602 for (uint32_t i = 0; i < commandBufferCount; i++) {
4603 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
4604
4605 primary->scratch_size_per_wave_needed = MAX2(primary->scratch_size_per_wave_needed,
4606 secondary->scratch_size_per_wave_needed);
4607 primary->scratch_waves_wanted = MAX2(primary->scratch_waves_wanted,
4608 secondary->scratch_waves_wanted);
4609 primary->compute_scratch_size_per_wave_needed = MAX2(primary->compute_scratch_size_per_wave_needed,
4610 secondary->compute_scratch_size_per_wave_needed);
4611 primary->compute_scratch_waves_wanted = MAX2(primary->compute_scratch_waves_wanted,
4612 secondary->compute_scratch_waves_wanted);
4613
4614 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
4615 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
4616 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
4617 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
4618 if (secondary->tess_rings_needed)
4619 primary->tess_rings_needed = true;
4620 if (secondary->sample_positions_needed)
4621 primary->sample_positions_needed = true;
4622 if (secondary->gds_needed)
4623 primary->gds_needed = true;
4624
4625 if (!secondary->state.framebuffer &&
4626 (primary->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)) {
4627 /* Emit the framebuffer state from primary if secondary
4628 * has been recorded without a framebuffer, otherwise
4629 * fast color/depth clears can't work.
4630 */
4631 radv_emit_framebuffer_state(primary);
4632 }
4633
4634 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
4635
4636
4637 /* When the secondary command buffer is compute only we don't
4638 * need to re-emit the current graphics pipeline.
4639 */
4640 if (secondary->state.emitted_pipeline) {
4641 primary->state.emitted_pipeline =
4642 secondary->state.emitted_pipeline;
4643 }
4644
4645 /* When the secondary command buffer is graphics only we don't
4646 * need to re-emit the current compute pipeline.
4647 */
4648 if (secondary->state.emitted_compute_pipeline) {
4649 primary->state.emitted_compute_pipeline =
4650 secondary->state.emitted_compute_pipeline;
4651 }
4652
4653 /* Only re-emit the draw packets when needed. */
4654 if (secondary->state.last_primitive_reset_en != -1) {
4655 primary->state.last_primitive_reset_en =
4656 secondary->state.last_primitive_reset_en;
4657 }
4658
4659 if (secondary->state.last_primitive_reset_index) {
4660 primary->state.last_primitive_reset_index =
4661 secondary->state.last_primitive_reset_index;
4662 }
4663
4664 if (secondary->state.last_ia_multi_vgt_param) {
4665 primary->state.last_ia_multi_vgt_param =
4666 secondary->state.last_ia_multi_vgt_param;
4667 }
4668
4669 primary->state.last_first_instance = secondary->state.last_first_instance;
4670 primary->state.last_num_instances = secondary->state.last_num_instances;
4671 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
4672 primary->state.last_sx_ps_downconvert = secondary->state.last_sx_ps_downconvert;
4673 primary->state.last_sx_blend_opt_epsilon = secondary->state.last_sx_blend_opt_epsilon;
4674 primary->state.last_sx_blend_opt_control = secondary->state.last_sx_blend_opt_control;
4675
4676 if (secondary->state.last_index_type != -1) {
4677 primary->state.last_index_type =
4678 secondary->state.last_index_type;
4679 }
4680 }
4681
4682 /* After executing commands from secondary buffers we have to dirty
4683 * some states.
4684 */
4685 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
4686 RADV_CMD_DIRTY_INDEX_BUFFER |
4687 RADV_CMD_DIRTY_DYNAMIC_ALL;
4688 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
4689 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
4690 }
4691
4692 VkResult radv_CreateCommandPool(
4693 VkDevice _device,
4694 const VkCommandPoolCreateInfo* pCreateInfo,
4695 const VkAllocationCallbacks* pAllocator,
4696 VkCommandPool* pCmdPool)
4697 {
4698 RADV_FROM_HANDLE(radv_device, device, _device);
4699 struct radv_cmd_pool *pool;
4700
4701 pool = vk_alloc2(&device->vk.alloc, pAllocator, sizeof(*pool), 8,
4702 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4703 if (pool == NULL)
4704 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4705
4706 vk_object_base_init(&device->vk, &pool->base,
4707 VK_OBJECT_TYPE_COMMAND_POOL);
4708
4709 if (pAllocator)
4710 pool->alloc = *pAllocator;
4711 else
4712 pool->alloc = device->vk.alloc;
4713
4714 list_inithead(&pool->cmd_buffers);
4715 list_inithead(&pool->free_cmd_buffers);
4716
4717 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
4718
4719 *pCmdPool = radv_cmd_pool_to_handle(pool);
4720
4721 return VK_SUCCESS;
4722
4723 }
4724
4725 void radv_DestroyCommandPool(
4726 VkDevice _device,
4727 VkCommandPool commandPool,
4728 const VkAllocationCallbacks* pAllocator)
4729 {
4730 RADV_FROM_HANDLE(radv_device, device, _device);
4731 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4732
4733 if (!pool)
4734 return;
4735
4736 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4737 &pool->cmd_buffers, pool_link) {
4738 radv_cmd_buffer_destroy(cmd_buffer);
4739 }
4740
4741 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4742 &pool->free_cmd_buffers, pool_link) {
4743 radv_cmd_buffer_destroy(cmd_buffer);
4744 }
4745
4746 vk_object_base_finish(&pool->base);
4747 vk_free2(&device->vk.alloc, pAllocator, pool);
4748 }
4749
4750 VkResult radv_ResetCommandPool(
4751 VkDevice device,
4752 VkCommandPool commandPool,
4753 VkCommandPoolResetFlags flags)
4754 {
4755 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4756 VkResult result;
4757
4758 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
4759 &pool->cmd_buffers, pool_link) {
4760 result = radv_reset_cmd_buffer(cmd_buffer);
4761 if (result != VK_SUCCESS)
4762 return result;
4763 }
4764
4765 return VK_SUCCESS;
4766 }
4767
4768 void radv_TrimCommandPool(
4769 VkDevice device,
4770 VkCommandPool commandPool,
4771 VkCommandPoolTrimFlags flags)
4772 {
4773 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4774
4775 if (!pool)
4776 return;
4777
4778 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4779 &pool->free_cmd_buffers, pool_link) {
4780 radv_cmd_buffer_destroy(cmd_buffer);
4781 }
4782 }
4783
4784 static void
4785 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
4786 uint32_t subpass_id)
4787 {
4788 struct radv_cmd_state *state = &cmd_buffer->state;
4789 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
4790
4791 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
4792 cmd_buffer->cs, 4096);
4793
4794 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
4795
4796 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
4797
4798 radv_describe_barrier_start(cmd_buffer, RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC);
4799
4800 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4801 const uint32_t a = subpass->attachments[i].attachment;
4802 if (a == VK_ATTACHMENT_UNUSED)
4803 continue;
4804
4805 radv_handle_subpass_image_transition(cmd_buffer,
4806 subpass->attachments[i],
4807 true);
4808 }
4809
4810 radv_describe_barrier_end(cmd_buffer);
4811
4812 radv_cmd_buffer_clear_subpass(cmd_buffer);
4813
4814 assert(cmd_buffer->cs->cdw <= cdw_max);
4815 }
4816
4817 static void
4818 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
4819 {
4820 struct radv_cmd_state *state = &cmd_buffer->state;
4821 const struct radv_subpass *subpass = state->subpass;
4822 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
4823
4824 radv_cmd_buffer_resolve_subpass(cmd_buffer);
4825
4826 radv_describe_barrier_start(cmd_buffer, RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC);
4827
4828 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4829 const uint32_t a = subpass->attachments[i].attachment;
4830 if (a == VK_ATTACHMENT_UNUSED)
4831 continue;
4832
4833 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
4834 continue;
4835
4836 VkImageLayout layout = state->pass->attachments[a].final_layout;
4837 VkImageLayout stencil_layout = state->pass->attachments[a].stencil_final_layout;
4838 struct radv_subpass_attachment att = { a, layout, stencil_layout };
4839 radv_handle_subpass_image_transition(cmd_buffer, att, false);
4840 }
4841
4842 radv_describe_barrier_end(cmd_buffer);
4843 }
4844
4845 void
4846 radv_cmd_buffer_begin_render_pass(struct radv_cmd_buffer *cmd_buffer,
4847 const VkRenderPassBeginInfo *pRenderPassBegin)
4848 {
4849 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
4850 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
4851 VkResult result;
4852
4853 cmd_buffer->state.framebuffer = framebuffer;
4854 cmd_buffer->state.pass = pass;
4855 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
4856
4857 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
4858 if (result != VK_SUCCESS)
4859 return;
4860
4861 result = radv_cmd_state_setup_sample_locations(cmd_buffer, pass, pRenderPassBegin);
4862 if (result != VK_SUCCESS)
4863 return;
4864 }
4865
4866 void radv_CmdBeginRenderPass(
4867 VkCommandBuffer commandBuffer,
4868 const VkRenderPassBeginInfo* pRenderPassBegin,
4869 VkSubpassContents contents)
4870 {
4871 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4872
4873 radv_cmd_buffer_begin_render_pass(cmd_buffer, pRenderPassBegin);
4874
4875 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
4876 }
4877
4878 void radv_CmdBeginRenderPass2(
4879 VkCommandBuffer commandBuffer,
4880 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
4881 const VkSubpassBeginInfo* pSubpassBeginInfo)
4882 {
4883 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
4884 pSubpassBeginInfo->contents);
4885 }
4886
4887 void radv_CmdNextSubpass(
4888 VkCommandBuffer commandBuffer,
4889 VkSubpassContents contents)
4890 {
4891 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4892
4893 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
4894 radv_cmd_buffer_end_subpass(cmd_buffer);
4895 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
4896 }
4897
4898 void radv_CmdNextSubpass2(
4899 VkCommandBuffer commandBuffer,
4900 const VkSubpassBeginInfo* pSubpassBeginInfo,
4901 const VkSubpassEndInfo* pSubpassEndInfo)
4902 {
4903 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
4904 }
4905
4906 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
4907 {
4908 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
4909 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
4910 if (!radv_get_shader(pipeline, stage))
4911 continue;
4912
4913 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
4914 if (loc->sgpr_idx == -1)
4915 continue;
4916 uint32_t base_reg = pipeline->user_data_0[stage];
4917 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4918
4919 }
4920 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
4921 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
4922 if (loc->sgpr_idx != -1) {
4923 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
4924 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4925 }
4926 }
4927 }
4928
4929 static void
4930 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4931 uint32_t vertex_count,
4932 bool use_opaque)
4933 {
4934 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
4935 radeon_emit(cmd_buffer->cs, vertex_count);
4936 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
4937 S_0287F0_USE_OPAQUE(use_opaque));
4938 }
4939
4940 static void
4941 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
4942 uint64_t index_va,
4943 uint32_t index_count)
4944 {
4945 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
4946 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
4947 radeon_emit(cmd_buffer->cs, index_va);
4948 radeon_emit(cmd_buffer->cs, index_va >> 32);
4949 radeon_emit(cmd_buffer->cs, index_count);
4950 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
4951 }
4952
4953 static void
4954 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4955 bool indexed,
4956 uint32_t draw_count,
4957 uint64_t count_va,
4958 uint32_t stride)
4959 {
4960 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4961 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
4962 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
4963 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id;
4964 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
4965 bool predicating = cmd_buffer->state.predicating;
4966 assert(base_reg);
4967
4968 /* just reset draw state for vertex data */
4969 cmd_buffer->state.last_first_instance = -1;
4970 cmd_buffer->state.last_num_instances = -1;
4971 cmd_buffer->state.last_vertex_offset = -1;
4972
4973 if (draw_count == 1 && !count_va && !draw_id_enable) {
4974 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
4975 PKT3_DRAW_INDIRECT, 3, predicating));
4976 radeon_emit(cs, 0);
4977 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4978 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4979 radeon_emit(cs, di_src_sel);
4980 } else {
4981 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
4982 PKT3_DRAW_INDIRECT_MULTI,
4983 8, predicating));
4984 radeon_emit(cs, 0);
4985 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4986 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4987 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
4988 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
4989 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
4990 radeon_emit(cs, draw_count); /* count */
4991 radeon_emit(cs, count_va); /* count_addr */
4992 radeon_emit(cs, count_va >> 32);
4993 radeon_emit(cs, stride); /* stride */
4994 radeon_emit(cs, di_src_sel);
4995 }
4996 }
4997
4998 static void
4999 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
5000 const struct radv_draw_info *info)
5001 {
5002 struct radv_cmd_state *state = &cmd_buffer->state;
5003 struct radeon_winsys *ws = cmd_buffer->device->ws;
5004 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5005
5006 if (info->indirect) {
5007 uint64_t va = radv_buffer_get_va(info->indirect->bo);
5008 uint64_t count_va = 0;
5009
5010 va += info->indirect->offset + info->indirect_offset;
5011
5012 radv_cs_add_buffer(ws, cs, info->indirect->bo);
5013
5014 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
5015 radeon_emit(cs, 1);
5016 radeon_emit(cs, va);
5017 radeon_emit(cs, va >> 32);
5018
5019 if (info->count_buffer) {
5020 count_va = radv_buffer_get_va(info->count_buffer->bo);
5021 count_va += info->count_buffer->offset +
5022 info->count_buffer_offset;
5023
5024 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
5025 }
5026
5027 if (!state->subpass->view_mask) {
5028 radv_cs_emit_indirect_draw_packet(cmd_buffer,
5029 info->indexed,
5030 info->count,
5031 count_va,
5032 info->stride);
5033 } else {
5034 unsigned i;
5035 for_each_bit(i, state->subpass->view_mask) {
5036 radv_emit_view_index(cmd_buffer, i);
5037
5038 radv_cs_emit_indirect_draw_packet(cmd_buffer,
5039 info->indexed,
5040 info->count,
5041 count_va,
5042 info->stride);
5043 }
5044 }
5045 } else {
5046 assert(state->pipeline->graphics.vtx_base_sgpr);
5047
5048 if (info->vertex_offset != state->last_vertex_offset ||
5049 info->first_instance != state->last_first_instance) {
5050 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
5051 state->pipeline->graphics.vtx_emit_num);
5052
5053 radeon_emit(cs, info->vertex_offset);
5054 radeon_emit(cs, info->first_instance);
5055 if (state->pipeline->graphics.vtx_emit_num == 3)
5056 radeon_emit(cs, 0);
5057 state->last_first_instance = info->first_instance;
5058 state->last_vertex_offset = info->vertex_offset;
5059 }
5060
5061 if (state->last_num_instances != info->instance_count) {
5062 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
5063 radeon_emit(cs, info->instance_count);
5064 state->last_num_instances = info->instance_count;
5065 }
5066
5067 if (info->indexed) {
5068 int index_size = radv_get_vgt_index_size(state->index_type);
5069 uint64_t index_va;
5070
5071 /* Skip draw calls with 0-sized index buffers. They
5072 * cause a hang on some chips, like Navi10-14.
5073 */
5074 if (!cmd_buffer->state.max_index_count)
5075 return;
5076
5077 index_va = state->index_va;
5078 index_va += info->first_index * index_size;
5079
5080 if (!state->subpass->view_mask) {
5081 radv_cs_emit_draw_indexed_packet(cmd_buffer,
5082 index_va,
5083 info->count);
5084 } else {
5085 unsigned i;
5086 for_each_bit(i, state->subpass->view_mask) {
5087 radv_emit_view_index(cmd_buffer, i);
5088
5089 radv_cs_emit_draw_indexed_packet(cmd_buffer,
5090 index_va,
5091 info->count);
5092 }
5093 }
5094 } else {
5095 if (!state->subpass->view_mask) {
5096 radv_cs_emit_draw_packet(cmd_buffer,
5097 info->count,
5098 !!info->strmout_buffer);
5099 } else {
5100 unsigned i;
5101 for_each_bit(i, state->subpass->view_mask) {
5102 radv_emit_view_index(cmd_buffer, i);
5103
5104 radv_cs_emit_draw_packet(cmd_buffer,
5105 info->count,
5106 !!info->strmout_buffer);
5107 }
5108 }
5109 }
5110 }
5111 }
5112
5113 /*
5114 * Vega and raven have a bug which triggers if there are multiple context
5115 * register contexts active at the same time with different scissor values.
5116 *
5117 * There are two possible workarounds:
5118 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
5119 * there is only ever 1 active set of scissor values at the same time.
5120 *
5121 * 2) Whenever the hardware switches contexts we have to set the scissor
5122 * registers again even if it is a noop. That way the new context gets
5123 * the correct scissor values.
5124 *
5125 * This implements option 2. radv_need_late_scissor_emission needs to
5126 * return true on affected HW if radv_emit_all_graphics_states sets
5127 * any context registers.
5128 */
5129 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
5130 const struct radv_draw_info *info)
5131 {
5132 struct radv_cmd_state *state = &cmd_buffer->state;
5133
5134 if (!cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
5135 return false;
5136
5137 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
5138 return true;
5139
5140 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
5141
5142 /* Index, vertex and streamout buffers don't change context regs, and
5143 * pipeline is already handled.
5144 */
5145 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
5146 RADV_CMD_DIRTY_VERTEX_BUFFER |
5147 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
5148 RADV_CMD_DIRTY_PIPELINE);
5149
5150 if (cmd_buffer->state.dirty & used_states)
5151 return true;
5152
5153 uint32_t primitive_reset_index =
5154 radv_get_primitive_reset_index(cmd_buffer);
5155
5156 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
5157 primitive_reset_index != state->last_primitive_reset_index)
5158 return true;
5159
5160 return false;
5161 }
5162
5163 static void
5164 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
5165 const struct radv_draw_info *info)
5166 {
5167 bool late_scissor_emission;
5168
5169 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
5170 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
5171 radv_emit_rbplus_state(cmd_buffer);
5172
5173 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
5174 radv_emit_graphics_pipeline(cmd_buffer);
5175
5176 /* This should be before the cmd_buffer->state.dirty is cleared
5177 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
5178 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
5179 late_scissor_emission =
5180 radv_need_late_scissor_emission(cmd_buffer, info);
5181
5182 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
5183 radv_emit_framebuffer_state(cmd_buffer);
5184
5185 if (info->indexed) {
5186 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
5187 radv_emit_index_buffer(cmd_buffer, info->indirect);
5188 } else {
5189 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
5190 * so the state must be re-emitted before the next indexed
5191 * draw.
5192 */
5193 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
5194 cmd_buffer->state.last_index_type = -1;
5195 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
5196 }
5197 }
5198
5199 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
5200
5201 radv_emit_draw_registers(cmd_buffer, info);
5202
5203 if (late_scissor_emission)
5204 radv_emit_scissor(cmd_buffer);
5205 }
5206
5207 static void
5208 radv_draw(struct radv_cmd_buffer *cmd_buffer,
5209 const struct radv_draw_info *info)
5210 {
5211 struct radeon_info *rad_info =
5212 &cmd_buffer->device->physical_device->rad_info;
5213 bool has_prefetch =
5214 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
5215 bool pipeline_is_dirty =
5216 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
5217 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
5218
5219 ASSERTED unsigned cdw_max =
5220 radeon_check_space(cmd_buffer->device->ws,
5221 cmd_buffer->cs, 4096);
5222
5223 if (likely(!info->indirect)) {
5224 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
5225 * no workaround for indirect draws, but we can at least skip
5226 * direct draws.
5227 */
5228 if (unlikely(!info->instance_count))
5229 return;
5230
5231 /* Handle count == 0. */
5232 if (unlikely(!info->count && !info->strmout_buffer))
5233 return;
5234 }
5235
5236 radv_describe_draw(cmd_buffer);
5237
5238 /* Use optimal packet order based on whether we need to sync the
5239 * pipeline.
5240 */
5241 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5242 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5243 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
5244 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
5245 /* If we have to wait for idle, set all states first, so that
5246 * all SET packets are processed in parallel with previous draw
5247 * calls. Then upload descriptors, set shader pointers, and
5248 * draw, and prefetch at the end. This ensures that the time
5249 * the CUs are idle is very short. (there are only SET_SH
5250 * packets between the wait and the draw)
5251 */
5252 radv_emit_all_graphics_states(cmd_buffer, info);
5253 si_emit_cache_flush(cmd_buffer);
5254 /* <-- CUs are idle here --> */
5255
5256 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
5257
5258 radv_emit_draw_packets(cmd_buffer, info);
5259 /* <-- CUs are busy here --> */
5260
5261 /* Start prefetches after the draw has been started. Both will
5262 * run in parallel, but starting the draw first is more
5263 * important.
5264 */
5265 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
5266 radv_emit_prefetch_L2(cmd_buffer,
5267 cmd_buffer->state.pipeline, false);
5268 }
5269 } else {
5270 /* If we don't wait for idle, start prefetches first, then set
5271 * states, and draw at the end.
5272 */
5273 si_emit_cache_flush(cmd_buffer);
5274
5275 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
5276 /* Only prefetch the vertex shader and VBO descriptors
5277 * in order to start the draw as soon as possible.
5278 */
5279 radv_emit_prefetch_L2(cmd_buffer,
5280 cmd_buffer->state.pipeline, true);
5281 }
5282
5283 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
5284
5285 radv_emit_all_graphics_states(cmd_buffer, info);
5286 radv_emit_draw_packets(cmd_buffer, info);
5287
5288 /* Prefetch the remaining shaders after the draw has been
5289 * started.
5290 */
5291 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
5292 radv_emit_prefetch_L2(cmd_buffer,
5293 cmd_buffer->state.pipeline, false);
5294 }
5295 }
5296
5297 /* Workaround for a VGT hang when streamout is enabled.
5298 * It must be done after drawing.
5299 */
5300 if (cmd_buffer->state.streamout.streamout_enabled &&
5301 (rad_info->family == CHIP_HAWAII ||
5302 rad_info->family == CHIP_TONGA ||
5303 rad_info->family == CHIP_FIJI)) {
5304 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
5305 }
5306
5307 assert(cmd_buffer->cs->cdw <= cdw_max);
5308 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
5309 }
5310
5311 void radv_CmdDraw(
5312 VkCommandBuffer commandBuffer,
5313 uint32_t vertexCount,
5314 uint32_t instanceCount,
5315 uint32_t firstVertex,
5316 uint32_t firstInstance)
5317 {
5318 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5319 struct radv_draw_info info = {};
5320
5321 info.count = vertexCount;
5322 info.instance_count = instanceCount;
5323 info.first_instance = firstInstance;
5324 info.vertex_offset = firstVertex;
5325
5326 radv_draw(cmd_buffer, &info);
5327 }
5328
5329 void radv_CmdDrawIndexed(
5330 VkCommandBuffer commandBuffer,
5331 uint32_t indexCount,
5332 uint32_t instanceCount,
5333 uint32_t firstIndex,
5334 int32_t vertexOffset,
5335 uint32_t firstInstance)
5336 {
5337 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5338 struct radv_draw_info info = {};
5339
5340 info.indexed = true;
5341 info.count = indexCount;
5342 info.instance_count = instanceCount;
5343 info.first_index = firstIndex;
5344 info.vertex_offset = vertexOffset;
5345 info.first_instance = firstInstance;
5346
5347 radv_draw(cmd_buffer, &info);
5348 }
5349
5350 void radv_CmdDrawIndirect(
5351 VkCommandBuffer commandBuffer,
5352 VkBuffer _buffer,
5353 VkDeviceSize offset,
5354 uint32_t drawCount,
5355 uint32_t stride)
5356 {
5357 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5358 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5359 struct radv_draw_info info = {};
5360
5361 info.count = drawCount;
5362 info.indirect = buffer;
5363 info.indirect_offset = offset;
5364 info.stride = stride;
5365
5366 radv_draw(cmd_buffer, &info);
5367 }
5368
5369 void radv_CmdDrawIndexedIndirect(
5370 VkCommandBuffer commandBuffer,
5371 VkBuffer _buffer,
5372 VkDeviceSize offset,
5373 uint32_t drawCount,
5374 uint32_t stride)
5375 {
5376 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5377 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5378 struct radv_draw_info info = {};
5379
5380 info.indexed = true;
5381 info.count = drawCount;
5382 info.indirect = buffer;
5383 info.indirect_offset = offset;
5384 info.stride = stride;
5385
5386 radv_draw(cmd_buffer, &info);
5387 }
5388
5389 void radv_CmdDrawIndirectCount(
5390 VkCommandBuffer commandBuffer,
5391 VkBuffer _buffer,
5392 VkDeviceSize offset,
5393 VkBuffer _countBuffer,
5394 VkDeviceSize countBufferOffset,
5395 uint32_t maxDrawCount,
5396 uint32_t stride)
5397 {
5398 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5399 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5400 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
5401 struct radv_draw_info info = {};
5402
5403 info.count = maxDrawCount;
5404 info.indirect = buffer;
5405 info.indirect_offset = offset;
5406 info.count_buffer = count_buffer;
5407 info.count_buffer_offset = countBufferOffset;
5408 info.stride = stride;
5409
5410 radv_draw(cmd_buffer, &info);
5411 }
5412
5413 void radv_CmdDrawIndexedIndirectCount(
5414 VkCommandBuffer commandBuffer,
5415 VkBuffer _buffer,
5416 VkDeviceSize offset,
5417 VkBuffer _countBuffer,
5418 VkDeviceSize countBufferOffset,
5419 uint32_t maxDrawCount,
5420 uint32_t stride)
5421 {
5422 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5423 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5424 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
5425 struct radv_draw_info info = {};
5426
5427 info.indexed = true;
5428 info.count = maxDrawCount;
5429 info.indirect = buffer;
5430 info.indirect_offset = offset;
5431 info.count_buffer = count_buffer;
5432 info.count_buffer_offset = countBufferOffset;
5433 info.stride = stride;
5434
5435 radv_draw(cmd_buffer, &info);
5436 }
5437
5438 struct radv_dispatch_info {
5439 /**
5440 * Determine the layout of the grid (in block units) to be used.
5441 */
5442 uint32_t blocks[3];
5443
5444 /**
5445 * A starting offset for the grid. If unaligned is set, the offset
5446 * must still be aligned.
5447 */
5448 uint32_t offsets[3];
5449 /**
5450 * Whether it's an unaligned compute dispatch.
5451 */
5452 bool unaligned;
5453
5454 /**
5455 * Indirect compute parameters resource.
5456 */
5457 struct radv_buffer *indirect;
5458 uint64_t indirect_offset;
5459 };
5460
5461 static void
5462 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
5463 const struct radv_dispatch_info *info)
5464 {
5465 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
5466 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
5467 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
5468 struct radeon_winsys *ws = cmd_buffer->device->ws;
5469 bool predicating = cmd_buffer->state.predicating;
5470 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5471 struct radv_userdata_info *loc;
5472
5473 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
5474 AC_UD_CS_GRID_SIZE);
5475
5476 ASSERTED unsigned cdw_max = radeon_check_space(ws, cs, 25);
5477
5478 if (compute_shader->info.wave_size == 32) {
5479 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
5480 dispatch_initiator |= S_00B800_CS_W32_EN(1);
5481 }
5482
5483 if (info->indirect) {
5484 uint64_t va = radv_buffer_get_va(info->indirect->bo);
5485
5486 va += info->indirect->offset + info->indirect_offset;
5487
5488 radv_cs_add_buffer(ws, cs, info->indirect->bo);
5489
5490 if (loc->sgpr_idx != -1) {
5491 for (unsigned i = 0; i < 3; ++i) {
5492 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5493 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5494 COPY_DATA_DST_SEL(COPY_DATA_REG));
5495 radeon_emit(cs, (va + 4 * i));
5496 radeon_emit(cs, (va + 4 * i) >> 32);
5497 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
5498 + loc->sgpr_idx * 4) >> 2) + i);
5499 radeon_emit(cs, 0);
5500 }
5501 }
5502
5503 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
5504 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
5505 PKT3_SHADER_TYPE_S(1));
5506 radeon_emit(cs, va);
5507 radeon_emit(cs, va >> 32);
5508 radeon_emit(cs, dispatch_initiator);
5509 } else {
5510 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
5511 PKT3_SHADER_TYPE_S(1));
5512 radeon_emit(cs, 1);
5513 radeon_emit(cs, va);
5514 radeon_emit(cs, va >> 32);
5515
5516 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
5517 PKT3_SHADER_TYPE_S(1));
5518 radeon_emit(cs, 0);
5519 radeon_emit(cs, dispatch_initiator);
5520 }
5521 } else {
5522 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
5523 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
5524
5525 if (info->unaligned) {
5526 unsigned *cs_block_size = compute_shader->info.cs.block_size;
5527 unsigned remainder[3];
5528
5529 /* If aligned, these should be an entire block size,
5530 * not 0.
5531 */
5532 remainder[0] = blocks[0] + cs_block_size[0] -
5533 align_u32_npot(blocks[0], cs_block_size[0]);
5534 remainder[1] = blocks[1] + cs_block_size[1] -
5535 align_u32_npot(blocks[1], cs_block_size[1]);
5536 remainder[2] = blocks[2] + cs_block_size[2] -
5537 align_u32_npot(blocks[2], cs_block_size[2]);
5538
5539 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
5540 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
5541 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
5542
5543 for(unsigned i = 0; i < 3; ++i) {
5544 assert(offsets[i] % cs_block_size[i] == 0);
5545 offsets[i] /= cs_block_size[i];
5546 }
5547
5548 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
5549 radeon_emit(cs,
5550 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
5551 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
5552 radeon_emit(cs,
5553 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
5554 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
5555 radeon_emit(cs,
5556 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
5557 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
5558
5559 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
5560 }
5561
5562 if (loc->sgpr_idx != -1) {
5563 assert(loc->num_sgprs == 3);
5564
5565 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
5566 loc->sgpr_idx * 4, 3);
5567 radeon_emit(cs, blocks[0]);
5568 radeon_emit(cs, blocks[1]);
5569 radeon_emit(cs, blocks[2]);
5570 }
5571
5572 if (offsets[0] || offsets[1] || offsets[2]) {
5573 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
5574 radeon_emit(cs, offsets[0]);
5575 radeon_emit(cs, offsets[1]);
5576 radeon_emit(cs, offsets[2]);
5577
5578 /* The blocks in the packet are not counts but end values. */
5579 for (unsigned i = 0; i < 3; ++i)
5580 blocks[i] += offsets[i];
5581 } else {
5582 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
5583 }
5584
5585 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
5586 PKT3_SHADER_TYPE_S(1));
5587 radeon_emit(cs, blocks[0]);
5588 radeon_emit(cs, blocks[1]);
5589 radeon_emit(cs, blocks[2]);
5590 radeon_emit(cs, dispatch_initiator);
5591 }
5592
5593 assert(cmd_buffer->cs->cdw <= cdw_max);
5594 }
5595
5596 static void
5597 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
5598 {
5599 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
5600 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
5601 }
5602
5603 static void
5604 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
5605 const struct radv_dispatch_info *info)
5606 {
5607 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
5608 bool has_prefetch =
5609 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
5610 bool pipeline_is_dirty = pipeline &&
5611 pipeline != cmd_buffer->state.emitted_compute_pipeline;
5612
5613 radv_describe_dispatch(cmd_buffer, 8, 8, 8);
5614
5615 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5616 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5617 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
5618 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
5619 /* If we have to wait for idle, set all states first, so that
5620 * all SET packets are processed in parallel with previous draw
5621 * calls. Then upload descriptors, set shader pointers, and
5622 * dispatch, and prefetch at the end. This ensures that the
5623 * time the CUs are idle is very short. (there are only SET_SH
5624 * packets between the wait and the draw)
5625 */
5626 radv_emit_compute_pipeline(cmd_buffer);
5627 si_emit_cache_flush(cmd_buffer);
5628 /* <-- CUs are idle here --> */
5629
5630 radv_upload_compute_shader_descriptors(cmd_buffer);
5631
5632 radv_emit_dispatch_packets(cmd_buffer, info);
5633 /* <-- CUs are busy here --> */
5634
5635 /* Start prefetches after the dispatch has been started. Both
5636 * will run in parallel, but starting the dispatch first is
5637 * more important.
5638 */
5639 if (has_prefetch && pipeline_is_dirty) {
5640 radv_emit_shader_prefetch(cmd_buffer,
5641 pipeline->shaders[MESA_SHADER_COMPUTE]);
5642 }
5643 } else {
5644 /* If we don't wait for idle, start prefetches first, then set
5645 * states, and dispatch at the end.
5646 */
5647 si_emit_cache_flush(cmd_buffer);
5648
5649 if (has_prefetch && pipeline_is_dirty) {
5650 radv_emit_shader_prefetch(cmd_buffer,
5651 pipeline->shaders[MESA_SHADER_COMPUTE]);
5652 }
5653
5654 radv_upload_compute_shader_descriptors(cmd_buffer);
5655
5656 radv_emit_compute_pipeline(cmd_buffer);
5657 radv_emit_dispatch_packets(cmd_buffer, info);
5658 }
5659
5660 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
5661 }
5662
5663 void radv_CmdDispatchBase(
5664 VkCommandBuffer commandBuffer,
5665 uint32_t base_x,
5666 uint32_t base_y,
5667 uint32_t base_z,
5668 uint32_t x,
5669 uint32_t y,
5670 uint32_t z)
5671 {
5672 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5673 struct radv_dispatch_info info = {};
5674
5675 info.blocks[0] = x;
5676 info.blocks[1] = y;
5677 info.blocks[2] = z;
5678
5679 info.offsets[0] = base_x;
5680 info.offsets[1] = base_y;
5681 info.offsets[2] = base_z;
5682 radv_dispatch(cmd_buffer, &info);
5683 }
5684
5685 void radv_CmdDispatch(
5686 VkCommandBuffer commandBuffer,
5687 uint32_t x,
5688 uint32_t y,
5689 uint32_t z)
5690 {
5691 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
5692 }
5693
5694 void radv_CmdDispatchIndirect(
5695 VkCommandBuffer commandBuffer,
5696 VkBuffer _buffer,
5697 VkDeviceSize offset)
5698 {
5699 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5700 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5701 struct radv_dispatch_info info = {};
5702
5703 info.indirect = buffer;
5704 info.indirect_offset = offset;
5705
5706 radv_dispatch(cmd_buffer, &info);
5707 }
5708
5709 void radv_unaligned_dispatch(
5710 struct radv_cmd_buffer *cmd_buffer,
5711 uint32_t x,
5712 uint32_t y,
5713 uint32_t z)
5714 {
5715 struct radv_dispatch_info info = {};
5716
5717 info.blocks[0] = x;
5718 info.blocks[1] = y;
5719 info.blocks[2] = z;
5720 info.unaligned = 1;
5721
5722 radv_dispatch(cmd_buffer, &info);
5723 }
5724
5725 void
5726 radv_cmd_buffer_end_render_pass(struct radv_cmd_buffer *cmd_buffer)
5727 {
5728 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
5729 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
5730
5731 cmd_buffer->state.pass = NULL;
5732 cmd_buffer->state.subpass = NULL;
5733 cmd_buffer->state.attachments = NULL;
5734 cmd_buffer->state.framebuffer = NULL;
5735 cmd_buffer->state.subpass_sample_locs = NULL;
5736 }
5737
5738 void radv_CmdEndRenderPass(
5739 VkCommandBuffer commandBuffer)
5740 {
5741 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5742
5743 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
5744
5745 radv_cmd_buffer_end_subpass(cmd_buffer);
5746
5747 radv_cmd_buffer_end_render_pass(cmd_buffer);
5748 }
5749
5750 void radv_CmdEndRenderPass2(
5751 VkCommandBuffer commandBuffer,
5752 const VkSubpassEndInfo* pSubpassEndInfo)
5753 {
5754 radv_CmdEndRenderPass(commandBuffer);
5755 }
5756
5757 /*
5758 * For HTILE we have the following interesting clear words:
5759 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
5760 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
5761 * 0xfffffff0: Clear depth to 1.0
5762 * 0x00000000: Clear depth to 0.0
5763 */
5764 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
5765 struct radv_image *image,
5766 const VkImageSubresourceRange *range)
5767 {
5768 assert(range->baseMipLevel == 0);
5769 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
5770 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
5771 struct radv_cmd_state *state = &cmd_buffer->state;
5772 uint32_t htile_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
5773 VkClearDepthStencilValue value = {};
5774 struct radv_barrier_data barrier = {};
5775
5776 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5777 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5778
5779 barrier.layout_transitions.init_mask_ram = 1;
5780 radv_describe_layout_transition(cmd_buffer, &barrier);
5781
5782 state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, htile_value);
5783
5784 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5785
5786 if (vk_format_is_stencil(image->vk_format))
5787 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
5788
5789 radv_set_ds_clear_metadata(cmd_buffer, image, range, value, aspects);
5790
5791 if (radv_image_is_tc_compat_htile(image)) {
5792 /* Initialize the TC-compat metada value to 0 because by
5793 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
5794 * need have to conditionally update its value when performing
5795 * a fast depth clear.
5796 */
5797 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, range, 0);
5798 }
5799 }
5800
5801 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
5802 struct radv_image *image,
5803 VkImageLayout src_layout,
5804 bool src_render_loop,
5805 VkImageLayout dst_layout,
5806 bool dst_render_loop,
5807 unsigned src_queue_mask,
5808 unsigned dst_queue_mask,
5809 const VkImageSubresourceRange *range,
5810 struct radv_sample_locations_state *sample_locs)
5811 {
5812 if (!radv_image_has_htile(image))
5813 return;
5814
5815 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5816 radv_initialize_htile(cmd_buffer, image, range);
5817 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5818 radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5819 radv_initialize_htile(cmd_buffer, image, range);
5820 } else if (radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5821 !radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5822 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5823 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5824
5825 radv_decompress_depth_stencil(cmd_buffer, image, range,
5826 sample_locs);
5827
5828 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5829 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5830 }
5831 }
5832
5833 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
5834 struct radv_image *image,
5835 const VkImageSubresourceRange *range,
5836 uint32_t value)
5837 {
5838 struct radv_cmd_state *state = &cmd_buffer->state;
5839 struct radv_barrier_data barrier = {};
5840
5841 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5842 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5843
5844 barrier.layout_transitions.init_mask_ram = 1;
5845 radv_describe_layout_transition(cmd_buffer, &barrier);
5846
5847 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, range, value);
5848
5849 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5850 }
5851
5852 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
5853 struct radv_image *image,
5854 const VkImageSubresourceRange *range)
5855 {
5856 struct radv_cmd_state *state = &cmd_buffer->state;
5857 static const uint32_t fmask_clear_values[4] = {
5858 0x00000000,
5859 0x02020202,
5860 0xE4E4E4E4,
5861 0x76543210
5862 };
5863 uint32_t log2_samples = util_logbase2(image->info.samples);
5864 uint32_t value = fmask_clear_values[log2_samples];
5865 struct radv_barrier_data barrier = {};
5866
5867 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5868 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5869
5870 barrier.layout_transitions.init_mask_ram = 1;
5871 radv_describe_layout_transition(cmd_buffer, &barrier);
5872
5873 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, range, value);
5874
5875 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5876 }
5877
5878 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
5879 struct radv_image *image,
5880 const VkImageSubresourceRange *range, uint32_t value)
5881 {
5882 struct radv_cmd_state *state = &cmd_buffer->state;
5883 struct radv_barrier_data barrier = {};
5884 unsigned size = 0;
5885
5886 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5887 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5888
5889 barrier.layout_transitions.init_mask_ram = 1;
5890 radv_describe_layout_transition(cmd_buffer, &barrier);
5891
5892 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
5893
5894 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) {
5895 /* When DCC is enabled with mipmaps, some levels might not
5896 * support fast clears and we have to initialize them as "fully
5897 * expanded".
5898 */
5899 /* Compute the size of all fast clearable DCC levels. */
5900 for (unsigned i = 0; i < image->planes[0].surface.num_dcc_levels; i++) {
5901 struct legacy_surf_level *surf_level =
5902 &image->planes[0].surface.u.legacy.level[i];
5903 unsigned dcc_fast_clear_size =
5904 surf_level->dcc_slice_fast_clear_size * image->info.array_size;
5905
5906 if (!dcc_fast_clear_size)
5907 break;
5908
5909 size = surf_level->dcc_offset + dcc_fast_clear_size;
5910 }
5911
5912 /* Initialize the mipmap levels without DCC. */
5913 if (size != image->planes[0].surface.dcc_size) {
5914 state->flush_bits |=
5915 radv_fill_buffer(cmd_buffer, image->bo,
5916 image->offset + image->planes[0].surface.dcc_offset + size,
5917 image->planes[0].surface.dcc_size - size,
5918 0xffffffff);
5919 }
5920 }
5921
5922 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5923 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5924 }
5925
5926 /**
5927 * Initialize DCC/FMASK/CMASK metadata for a color image.
5928 */
5929 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
5930 struct radv_image *image,
5931 VkImageLayout src_layout,
5932 bool src_render_loop,
5933 VkImageLayout dst_layout,
5934 bool dst_render_loop,
5935 unsigned src_queue_mask,
5936 unsigned dst_queue_mask,
5937 const VkImageSubresourceRange *range)
5938 {
5939 if (radv_image_has_cmask(image)) {
5940 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5941
5942 /* TODO: clarify this. */
5943 if (radv_image_has_fmask(image)) {
5944 value = 0xccccccccu;
5945 }
5946
5947 radv_initialise_cmask(cmd_buffer, image, range, value);
5948 }
5949
5950 if (radv_image_has_fmask(image)) {
5951 radv_initialize_fmask(cmd_buffer, image, range);
5952 }
5953
5954 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5955 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5956 bool need_decompress_pass = false;
5957
5958 if (radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout,
5959 dst_render_loop,
5960 dst_queue_mask)) {
5961 value = 0x20202020u;
5962 need_decompress_pass = true;
5963 }
5964
5965 radv_initialize_dcc(cmd_buffer, image, range, value);
5966
5967 radv_update_fce_metadata(cmd_buffer, image, range,
5968 need_decompress_pass);
5969 }
5970
5971 if (radv_image_has_cmask(image) ||
5972 radv_dcc_enabled(image, range->baseMipLevel)) {
5973 uint32_t color_values[2] = {};
5974 radv_set_color_clear_metadata(cmd_buffer, image, range,
5975 color_values);
5976 }
5977 }
5978
5979 /**
5980 * Handle color image transitions for DCC/FMASK/CMASK.
5981 */
5982 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
5983 struct radv_image *image,
5984 VkImageLayout src_layout,
5985 bool src_render_loop,
5986 VkImageLayout dst_layout,
5987 bool dst_render_loop,
5988 unsigned src_queue_mask,
5989 unsigned dst_queue_mask,
5990 const VkImageSubresourceRange *range)
5991 {
5992 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5993 radv_init_color_image_metadata(cmd_buffer, image,
5994 src_layout, src_render_loop,
5995 dst_layout, dst_render_loop,
5996 src_queue_mask, dst_queue_mask,
5997 range);
5998 return;
5999 }
6000
6001 if (radv_dcc_enabled(image, range->baseMipLevel)) {
6002 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
6003 radv_initialize_dcc(cmd_buffer, image, range, 0xffffffffu);
6004 } else if (radv_layout_dcc_compressed(cmd_buffer->device, image, src_layout, src_render_loop, src_queue_mask) &&
6005 !radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout, dst_render_loop, dst_queue_mask)) {
6006 radv_decompress_dcc(cmd_buffer, image, range);
6007 } else if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
6008 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
6009 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
6010 }
6011 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
6012 bool fce_eliminate = false, fmask_expand = false;
6013
6014 if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
6015 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
6016 fce_eliminate = true;
6017 }
6018
6019 if (radv_image_has_fmask(image)) {
6020 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
6021 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
6022 /* A FMASK decompress is required before doing
6023 * a MSAA decompress using FMASK.
6024 */
6025 fmask_expand = true;
6026 }
6027 }
6028
6029 if (fce_eliminate || fmask_expand)
6030 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
6031
6032 if (fmask_expand) {
6033 struct radv_barrier_data barrier = {};
6034 barrier.layout_transitions.fmask_color_expand = 1;
6035 radv_describe_layout_transition(cmd_buffer, &barrier);
6036
6037 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
6038 }
6039 }
6040 }
6041
6042 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
6043 struct radv_image *image,
6044 VkImageLayout src_layout,
6045 bool src_render_loop,
6046 VkImageLayout dst_layout,
6047 bool dst_render_loop,
6048 uint32_t src_family,
6049 uint32_t dst_family,
6050 const VkImageSubresourceRange *range,
6051 struct radv_sample_locations_state *sample_locs)
6052 {
6053 if (image->exclusive && src_family != dst_family) {
6054 /* This is an acquire or a release operation and there will be
6055 * a corresponding release/acquire. Do the transition in the
6056 * most flexible queue. */
6057
6058 assert(src_family == cmd_buffer->queue_family_index ||
6059 dst_family == cmd_buffer->queue_family_index);
6060
6061 if (src_family == VK_QUEUE_FAMILY_EXTERNAL ||
6062 src_family == VK_QUEUE_FAMILY_FOREIGN_EXT)
6063 return;
6064
6065 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
6066 return;
6067
6068 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
6069 (src_family == RADV_QUEUE_GENERAL ||
6070 dst_family == RADV_QUEUE_GENERAL))
6071 return;
6072 }
6073
6074 if (src_layout == dst_layout)
6075 return;
6076
6077 unsigned src_queue_mask =
6078 radv_image_queue_family_mask(image, src_family,
6079 cmd_buffer->queue_family_index);
6080 unsigned dst_queue_mask =
6081 radv_image_queue_family_mask(image, dst_family,
6082 cmd_buffer->queue_family_index);
6083
6084 if (vk_format_is_depth(image->vk_format)) {
6085 radv_handle_depth_image_transition(cmd_buffer, image,
6086 src_layout, src_render_loop,
6087 dst_layout, dst_render_loop,
6088 src_queue_mask, dst_queue_mask,
6089 range, sample_locs);
6090 } else {
6091 radv_handle_color_image_transition(cmd_buffer, image,
6092 src_layout, src_render_loop,
6093 dst_layout, dst_render_loop,
6094 src_queue_mask, dst_queue_mask,
6095 range);
6096 }
6097 }
6098
6099 struct radv_barrier_info {
6100 enum rgp_barrier_reason reason;
6101 uint32_t eventCount;
6102 const VkEvent *pEvents;
6103 VkPipelineStageFlags srcStageMask;
6104 VkPipelineStageFlags dstStageMask;
6105 };
6106
6107 static void
6108 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
6109 uint32_t memoryBarrierCount,
6110 const VkMemoryBarrier *pMemoryBarriers,
6111 uint32_t bufferMemoryBarrierCount,
6112 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
6113 uint32_t imageMemoryBarrierCount,
6114 const VkImageMemoryBarrier *pImageMemoryBarriers,
6115 const struct radv_barrier_info *info)
6116 {
6117 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6118 enum radv_cmd_flush_bits src_flush_bits = 0;
6119 enum radv_cmd_flush_bits dst_flush_bits = 0;
6120
6121 radv_describe_barrier_start(cmd_buffer, info->reason);
6122
6123 for (unsigned i = 0; i < info->eventCount; ++i) {
6124 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
6125 uint64_t va = radv_buffer_get_va(event->bo);
6126
6127 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
6128
6129 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
6130
6131 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
6132 assert(cmd_buffer->cs->cdw <= cdw_max);
6133 }
6134
6135 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
6136 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
6137 NULL);
6138 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
6139 NULL);
6140 }
6141
6142 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
6143 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
6144 NULL);
6145 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
6146 NULL);
6147 }
6148
6149 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
6150 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
6151
6152 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
6153 image);
6154 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
6155 image);
6156 }
6157
6158 /* The Vulkan spec 1.1.98 says:
6159 *
6160 * "An execution dependency with only
6161 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
6162 * will only prevent that stage from executing in subsequently
6163 * submitted commands. As this stage does not perform any actual
6164 * execution, this is not observable - in effect, it does not delay
6165 * processing of subsequent commands. Similarly an execution dependency
6166 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
6167 * will effectively not wait for any prior commands to complete."
6168 */
6169 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
6170 radv_stage_flush(cmd_buffer, info->srcStageMask);
6171 cmd_buffer->state.flush_bits |= src_flush_bits;
6172
6173 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
6174 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
6175
6176 const struct VkSampleLocationsInfoEXT *sample_locs_info =
6177 vk_find_struct_const(pImageMemoryBarriers[i].pNext,
6178 SAMPLE_LOCATIONS_INFO_EXT);
6179 struct radv_sample_locations_state sample_locations = {};
6180
6181 if (sample_locs_info) {
6182 assert(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
6183 sample_locations.per_pixel = sample_locs_info->sampleLocationsPerPixel;
6184 sample_locations.grid_size = sample_locs_info->sampleLocationGridSize;
6185 sample_locations.count = sample_locs_info->sampleLocationsCount;
6186 typed_memcpy(&sample_locations.locations[0],
6187 sample_locs_info->pSampleLocations,
6188 sample_locs_info->sampleLocationsCount);
6189 }
6190
6191 radv_handle_image_transition(cmd_buffer, image,
6192 pImageMemoryBarriers[i].oldLayout,
6193 false, /* Outside of a renderpass we are never in a renderloop */
6194 pImageMemoryBarriers[i].newLayout,
6195 false, /* Outside of a renderpass we are never in a renderloop */
6196 pImageMemoryBarriers[i].srcQueueFamilyIndex,
6197 pImageMemoryBarriers[i].dstQueueFamilyIndex,
6198 &pImageMemoryBarriers[i].subresourceRange,
6199 sample_locs_info ? &sample_locations : NULL);
6200 }
6201
6202 /* Make sure CP DMA is idle because the driver might have performed a
6203 * DMA operation for copying or filling buffers/images.
6204 */
6205 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
6206 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
6207 si_cp_dma_wait_for_idle(cmd_buffer);
6208
6209 cmd_buffer->state.flush_bits |= dst_flush_bits;
6210
6211 radv_describe_barrier_end(cmd_buffer);
6212 }
6213
6214 void radv_CmdPipelineBarrier(
6215 VkCommandBuffer commandBuffer,
6216 VkPipelineStageFlags srcStageMask,
6217 VkPipelineStageFlags destStageMask,
6218 VkBool32 byRegion,
6219 uint32_t memoryBarrierCount,
6220 const VkMemoryBarrier* pMemoryBarriers,
6221 uint32_t bufferMemoryBarrierCount,
6222 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
6223 uint32_t imageMemoryBarrierCount,
6224 const VkImageMemoryBarrier* pImageMemoryBarriers)
6225 {
6226 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6227 struct radv_barrier_info info;
6228
6229 info.reason = RGP_BARRIER_EXTERNAL_CMD_PIPELINE_BARRIER;
6230 info.eventCount = 0;
6231 info.pEvents = NULL;
6232 info.srcStageMask = srcStageMask;
6233 info.dstStageMask = destStageMask;
6234
6235 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
6236 bufferMemoryBarrierCount, pBufferMemoryBarriers,
6237 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
6238 }
6239
6240
6241 static void write_event(struct radv_cmd_buffer *cmd_buffer,
6242 struct radv_event *event,
6243 VkPipelineStageFlags stageMask,
6244 unsigned value)
6245 {
6246 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6247 uint64_t va = radv_buffer_get_va(event->bo);
6248
6249 si_emit_cache_flush(cmd_buffer);
6250
6251 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
6252
6253 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 21);
6254
6255 /* Flags that only require a top-of-pipe event. */
6256 VkPipelineStageFlags top_of_pipe_flags =
6257 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
6258
6259 /* Flags that only require a post-index-fetch event. */
6260 VkPipelineStageFlags post_index_fetch_flags =
6261 top_of_pipe_flags |
6262 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
6263 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
6264
6265 /* Make sure CP DMA is idle because the driver might have performed a
6266 * DMA operation for copying or filling buffers/images.
6267 */
6268 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
6269 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
6270 si_cp_dma_wait_for_idle(cmd_buffer);
6271
6272 /* TODO: Emit EOS events for syncing PS/CS stages. */
6273
6274 if (!(stageMask & ~top_of_pipe_flags)) {
6275 /* Just need to sync the PFP engine. */
6276 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
6277 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
6278 S_370_WR_CONFIRM(1) |
6279 S_370_ENGINE_SEL(V_370_PFP));
6280 radeon_emit(cs, va);
6281 radeon_emit(cs, va >> 32);
6282 radeon_emit(cs, value);
6283 } else if (!(stageMask & ~post_index_fetch_flags)) {
6284 /* Sync ME because PFP reads index and indirect buffers. */
6285 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
6286 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
6287 S_370_WR_CONFIRM(1) |
6288 S_370_ENGINE_SEL(V_370_ME));
6289 radeon_emit(cs, va);
6290 radeon_emit(cs, va >> 32);
6291 radeon_emit(cs, value);
6292 } else {
6293 /* Otherwise, sync all prior GPU work using an EOP event. */
6294 si_cs_emit_write_event_eop(cs,
6295 cmd_buffer->device->physical_device->rad_info.chip_class,
6296 radv_cmd_buffer_uses_mec(cmd_buffer),
6297 V_028A90_BOTTOM_OF_PIPE_TS, 0,
6298 EOP_DST_SEL_MEM,
6299 EOP_DATA_SEL_VALUE_32BIT, va, value,
6300 cmd_buffer->gfx9_eop_bug_va);
6301 }
6302
6303 assert(cmd_buffer->cs->cdw <= cdw_max);
6304 }
6305
6306 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
6307 VkEvent _event,
6308 VkPipelineStageFlags stageMask)
6309 {
6310 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6311 RADV_FROM_HANDLE(radv_event, event, _event);
6312
6313 write_event(cmd_buffer, event, stageMask, 1);
6314 }
6315
6316 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
6317 VkEvent _event,
6318 VkPipelineStageFlags stageMask)
6319 {
6320 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6321 RADV_FROM_HANDLE(radv_event, event, _event);
6322
6323 write_event(cmd_buffer, event, stageMask, 0);
6324 }
6325
6326 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
6327 uint32_t eventCount,
6328 const VkEvent* pEvents,
6329 VkPipelineStageFlags srcStageMask,
6330 VkPipelineStageFlags dstStageMask,
6331 uint32_t memoryBarrierCount,
6332 const VkMemoryBarrier* pMemoryBarriers,
6333 uint32_t bufferMemoryBarrierCount,
6334 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
6335 uint32_t imageMemoryBarrierCount,
6336 const VkImageMemoryBarrier* pImageMemoryBarriers)
6337 {
6338 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6339 struct radv_barrier_info info;
6340
6341 info.reason = RGP_BARRIER_EXTERNAL_CMD_WAIT_EVENTS;
6342 info.eventCount = eventCount;
6343 info.pEvents = pEvents;
6344 info.srcStageMask = 0;
6345
6346 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
6347 bufferMemoryBarrierCount, pBufferMemoryBarriers,
6348 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
6349 }
6350
6351
6352 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
6353 uint32_t deviceMask)
6354 {
6355 /* No-op */
6356 }
6357
6358 /* VK_EXT_conditional_rendering */
6359 void radv_CmdBeginConditionalRenderingEXT(
6360 VkCommandBuffer commandBuffer,
6361 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
6362 {
6363 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6364 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
6365 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6366 bool draw_visible = true;
6367 uint64_t pred_value = 0;
6368 uint64_t va, new_va;
6369 unsigned pred_offset;
6370
6371 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
6372
6373 /* By default, if the 32-bit value at offset in buffer memory is zero,
6374 * then the rendering commands are discarded, otherwise they are
6375 * executed as normal. If the inverted flag is set, all commands are
6376 * discarded if the value is non zero.
6377 */
6378 if (pConditionalRenderingBegin->flags &
6379 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
6380 draw_visible = false;
6381 }
6382
6383 si_emit_cache_flush(cmd_buffer);
6384
6385 /* From the Vulkan spec 1.1.107:
6386 *
6387 * "If the 32-bit value at offset in buffer memory is zero, then the
6388 * rendering commands are discarded, otherwise they are executed as
6389 * normal. If the value of the predicate in buffer memory changes while
6390 * conditional rendering is active, the rendering commands may be
6391 * discarded in an implementation-dependent way. Some implementations
6392 * may latch the value of the predicate upon beginning conditional
6393 * rendering while others may read it before every rendering command."
6394 *
6395 * But, the AMD hardware treats the predicate as a 64-bit value which
6396 * means we need a workaround in the driver. Luckily, it's not required
6397 * to support if the value changes when predication is active.
6398 *
6399 * The workaround is as follows:
6400 * 1) allocate a 64-value in the upload BO and initialize it to 0
6401 * 2) copy the 32-bit predicate value to the upload BO
6402 * 3) use the new allocated VA address for predication
6403 *
6404 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
6405 * in ME (+ sync PFP) instead of PFP.
6406 */
6407 radv_cmd_buffer_upload_data(cmd_buffer, 8, 16, &pred_value, &pred_offset);
6408
6409 new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
6410
6411 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
6412 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
6413 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
6414 COPY_DATA_WR_CONFIRM);
6415 radeon_emit(cs, va);
6416 radeon_emit(cs, va >> 32);
6417 radeon_emit(cs, new_va);
6418 radeon_emit(cs, new_va >> 32);
6419
6420 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
6421 radeon_emit(cs, 0);
6422
6423 /* Enable predication for this command buffer. */
6424 si_emit_set_predication_state(cmd_buffer, draw_visible, new_va);
6425 cmd_buffer->state.predicating = true;
6426
6427 /* Store conditional rendering user info. */
6428 cmd_buffer->state.predication_type = draw_visible;
6429 cmd_buffer->state.predication_va = new_va;
6430 }
6431
6432 void radv_CmdEndConditionalRenderingEXT(
6433 VkCommandBuffer commandBuffer)
6434 {
6435 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6436
6437 /* Disable predication for this command buffer. */
6438 si_emit_set_predication_state(cmd_buffer, false, 0);
6439 cmd_buffer->state.predicating = false;
6440
6441 /* Reset conditional rendering user info. */
6442 cmd_buffer->state.predication_type = -1;
6443 cmd_buffer->state.predication_va = 0;
6444 }
6445
6446 /* VK_EXT_transform_feedback */
6447 void radv_CmdBindTransformFeedbackBuffersEXT(
6448 VkCommandBuffer commandBuffer,
6449 uint32_t firstBinding,
6450 uint32_t bindingCount,
6451 const VkBuffer* pBuffers,
6452 const VkDeviceSize* pOffsets,
6453 const VkDeviceSize* pSizes)
6454 {
6455 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6456 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
6457 uint8_t enabled_mask = 0;
6458
6459 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
6460 for (uint32_t i = 0; i < bindingCount; i++) {
6461 uint32_t idx = firstBinding + i;
6462
6463 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
6464 sb[idx].offset = pOffsets[i];
6465
6466 if (!pSizes || pSizes[i] == VK_WHOLE_SIZE) {
6467 sb[idx].size = sb[idx].buffer->size - sb[idx].offset;
6468 } else {
6469 sb[idx].size = pSizes[i];
6470 }
6471
6472 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
6473 sb[idx].buffer->bo);
6474
6475 enabled_mask |= 1 << idx;
6476 }
6477
6478 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
6479
6480 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
6481 }
6482
6483 static void
6484 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
6485 {
6486 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6487 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6488
6489 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
6490 radeon_emit(cs,
6491 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
6492 S_028B94_RAST_STREAM(0) |
6493 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
6494 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
6495 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
6496 radeon_emit(cs, so->hw_enabled_mask &
6497 so->enabled_stream_buffers_mask);
6498
6499 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6500 }
6501
6502 static void
6503 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
6504 {
6505 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6506 bool old_streamout_enabled = so->streamout_enabled;
6507 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
6508
6509 so->streamout_enabled = enable;
6510
6511 so->hw_enabled_mask = so->enabled_mask |
6512 (so->enabled_mask << 4) |
6513 (so->enabled_mask << 8) |
6514 (so->enabled_mask << 12);
6515
6516 if (!cmd_buffer->device->physical_device->use_ngg_streamout &&
6517 ((old_streamout_enabled != so->streamout_enabled) ||
6518 (old_hw_enabled_mask != so->hw_enabled_mask)))
6519 radv_emit_streamout_enable(cmd_buffer);
6520
6521 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6522 cmd_buffer->gds_needed = true;
6523 cmd_buffer->gds_oa_needed = true;
6524 }
6525 }
6526
6527 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
6528 {
6529 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6530 unsigned reg_strmout_cntl;
6531
6532 /* The register is at different places on different ASICs. */
6533 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
6534 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
6535 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
6536 } else {
6537 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
6538 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
6539 }
6540
6541 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
6542 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
6543
6544 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
6545 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
6546 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
6547 radeon_emit(cs, 0);
6548 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
6549 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
6550 radeon_emit(cs, 4); /* poll interval */
6551 }
6552
6553 static void
6554 radv_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
6555 uint32_t firstCounterBuffer,
6556 uint32_t counterBufferCount,
6557 const VkBuffer *pCounterBuffers,
6558 const VkDeviceSize *pCounterBufferOffsets)
6559
6560 {
6561 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
6562 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6563 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6564 uint32_t i;
6565
6566 radv_flush_vgt_streamout(cmd_buffer);
6567
6568 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6569 for_each_bit(i, so->enabled_mask) {
6570 int32_t counter_buffer_idx = i - firstCounterBuffer;
6571 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6572 counter_buffer_idx = -1;
6573
6574 /* AMD GCN binds streamout buffers as shader resources.
6575 * VGT only counts primitives and tells the shader through
6576 * SGPRs what to do.
6577 */
6578 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
6579 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
6580 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
6581
6582 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6583
6584 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6585 /* The array of counter buffers is optional. */
6586 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6587 uint64_t va = radv_buffer_get_va(buffer->bo);
6588
6589 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6590
6591 /* Append */
6592 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6593 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6594 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6595 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
6596 radeon_emit(cs, 0); /* unused */
6597 radeon_emit(cs, 0); /* unused */
6598 radeon_emit(cs, va); /* src address lo */
6599 radeon_emit(cs, va >> 32); /* src address hi */
6600
6601 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6602 } else {
6603 /* Start from the beginning. */
6604 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6605 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6606 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6607 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
6608 radeon_emit(cs, 0); /* unused */
6609 radeon_emit(cs, 0); /* unused */
6610 radeon_emit(cs, 0); /* unused */
6611 radeon_emit(cs, 0); /* unused */
6612 }
6613 }
6614
6615 radv_set_streamout_enable(cmd_buffer, true);
6616 }
6617
6618 static void
6619 gfx10_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
6620 uint32_t firstCounterBuffer,
6621 uint32_t counterBufferCount,
6622 const VkBuffer *pCounterBuffers,
6623 const VkDeviceSize *pCounterBufferOffsets)
6624 {
6625 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6626 unsigned last_target = util_last_bit(so->enabled_mask) - 1;
6627 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6628 uint32_t i;
6629
6630 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6631 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6632
6633 /* Sync because the next streamout operation will overwrite GDS and we
6634 * have to make sure it's idle.
6635 * TODO: Improve by tracking if there is a streamout operation in
6636 * flight.
6637 */
6638 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
6639 si_emit_cache_flush(cmd_buffer);
6640
6641 for_each_bit(i, so->enabled_mask) {
6642 int32_t counter_buffer_idx = i - firstCounterBuffer;
6643 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6644 counter_buffer_idx = -1;
6645
6646 bool append = counter_buffer_idx >= 0 &&
6647 pCounterBuffers && pCounterBuffers[counter_buffer_idx];
6648 uint64_t va = 0;
6649
6650 if (append) {
6651 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6652
6653 va += radv_buffer_get_va(buffer->bo);
6654 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6655
6656 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6657 }
6658
6659 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
6660 radeon_emit(cs, S_411_SRC_SEL(append ? V_411_SRC_ADDR_TC_L2 : V_411_DATA) |
6661 S_411_DST_SEL(V_411_GDS) |
6662 S_411_CP_SYNC(i == last_target));
6663 radeon_emit(cs, va);
6664 radeon_emit(cs, va >> 32);
6665 radeon_emit(cs, 4 * i); /* destination in GDS */
6666 radeon_emit(cs, 0);
6667 radeon_emit(cs, S_414_BYTE_COUNT_GFX9(4) |
6668 S_414_DISABLE_WR_CONFIRM_GFX9(i != last_target));
6669 }
6670
6671 radv_set_streamout_enable(cmd_buffer, true);
6672 }
6673
6674 void radv_CmdBeginTransformFeedbackEXT(
6675 VkCommandBuffer commandBuffer,
6676 uint32_t firstCounterBuffer,
6677 uint32_t counterBufferCount,
6678 const VkBuffer* pCounterBuffers,
6679 const VkDeviceSize* pCounterBufferOffsets)
6680 {
6681 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6682
6683 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6684 gfx10_emit_streamout_begin(cmd_buffer,
6685 firstCounterBuffer, counterBufferCount,
6686 pCounterBuffers, pCounterBufferOffsets);
6687 } else {
6688 radv_emit_streamout_begin(cmd_buffer,
6689 firstCounterBuffer, counterBufferCount,
6690 pCounterBuffers, pCounterBufferOffsets);
6691 }
6692 }
6693
6694 static void
6695 radv_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6696 uint32_t firstCounterBuffer,
6697 uint32_t counterBufferCount,
6698 const VkBuffer *pCounterBuffers,
6699 const VkDeviceSize *pCounterBufferOffsets)
6700 {
6701 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6702 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6703 uint32_t i;
6704
6705 radv_flush_vgt_streamout(cmd_buffer);
6706
6707 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6708 for_each_bit(i, so->enabled_mask) {
6709 int32_t counter_buffer_idx = i - firstCounterBuffer;
6710 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6711 counter_buffer_idx = -1;
6712
6713 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6714 /* The array of counters buffer is optional. */
6715 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6716 uint64_t va = radv_buffer_get_va(buffer->bo);
6717
6718 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6719
6720 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6721 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6722 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6723 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
6724 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
6725 radeon_emit(cs, va); /* dst address lo */
6726 radeon_emit(cs, va >> 32); /* dst address hi */
6727 radeon_emit(cs, 0); /* unused */
6728 radeon_emit(cs, 0); /* unused */
6729
6730 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6731 }
6732
6733 /* Deactivate transform feedback by zeroing the buffer size.
6734 * The counters (primitives generated, primitives emitted) may
6735 * be enabled even if there is not buffer bound. This ensures
6736 * that the primitives-emitted query won't increment.
6737 */
6738 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
6739
6740 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6741 }
6742
6743 radv_set_streamout_enable(cmd_buffer, false);
6744 }
6745
6746 static void
6747 gfx10_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6748 uint32_t firstCounterBuffer,
6749 uint32_t counterBufferCount,
6750 const VkBuffer *pCounterBuffers,
6751 const VkDeviceSize *pCounterBufferOffsets)
6752 {
6753 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6754 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6755 uint32_t i;
6756
6757 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6758 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6759
6760 for_each_bit(i, so->enabled_mask) {
6761 int32_t counter_buffer_idx = i - firstCounterBuffer;
6762 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6763 counter_buffer_idx = -1;
6764
6765 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6766 /* The array of counters buffer is optional. */
6767 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6768 uint64_t va = radv_buffer_get_va(buffer->bo);
6769
6770 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6771
6772 si_cs_emit_write_event_eop(cs,
6773 cmd_buffer->device->physical_device->rad_info.chip_class,
6774 radv_cmd_buffer_uses_mec(cmd_buffer),
6775 V_028A90_PS_DONE, 0,
6776 EOP_DST_SEL_TC_L2,
6777 EOP_DATA_SEL_GDS,
6778 va, EOP_DATA_GDS(i, 1), 0);
6779
6780 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6781 }
6782 }
6783
6784 radv_set_streamout_enable(cmd_buffer, false);
6785 }
6786
6787 void radv_CmdEndTransformFeedbackEXT(
6788 VkCommandBuffer commandBuffer,
6789 uint32_t firstCounterBuffer,
6790 uint32_t counterBufferCount,
6791 const VkBuffer* pCounterBuffers,
6792 const VkDeviceSize* pCounterBufferOffsets)
6793 {
6794 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6795
6796 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6797 gfx10_emit_streamout_end(cmd_buffer,
6798 firstCounterBuffer, counterBufferCount,
6799 pCounterBuffers, pCounterBufferOffsets);
6800 } else {
6801 radv_emit_streamout_end(cmd_buffer,
6802 firstCounterBuffer, counterBufferCount,
6803 pCounterBuffers, pCounterBufferOffsets);
6804 }
6805 }
6806
6807 void radv_CmdDrawIndirectByteCountEXT(
6808 VkCommandBuffer commandBuffer,
6809 uint32_t instanceCount,
6810 uint32_t firstInstance,
6811 VkBuffer _counterBuffer,
6812 VkDeviceSize counterBufferOffset,
6813 uint32_t counterOffset,
6814 uint32_t vertexStride)
6815 {
6816 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6817 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
6818 struct radv_draw_info info = {};
6819
6820 info.instance_count = instanceCount;
6821 info.first_instance = firstInstance;
6822 info.strmout_buffer = counterBuffer;
6823 info.strmout_buffer_offset = counterBufferOffset;
6824 info.stride = vertexStride;
6825
6826 radv_draw(cmd_buffer, &info);
6827 }
6828
6829 /* VK_AMD_buffer_marker */
6830 void radv_CmdWriteBufferMarkerAMD(
6831 VkCommandBuffer commandBuffer,
6832 VkPipelineStageFlagBits pipelineStage,
6833 VkBuffer dstBuffer,
6834 VkDeviceSize dstOffset,
6835 uint32_t marker)
6836 {
6837 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6838 RADV_FROM_HANDLE(radv_buffer, buffer, dstBuffer);
6839 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6840 uint64_t va = radv_buffer_get_va(buffer->bo) + dstOffset;
6841
6842 si_emit_cache_flush(cmd_buffer);
6843
6844 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 12);
6845
6846 if (!(pipelineStage & ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT)) {
6847 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
6848 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
6849 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
6850 COPY_DATA_WR_CONFIRM);
6851 radeon_emit(cs, marker);
6852 radeon_emit(cs, 0);
6853 radeon_emit(cs, va);
6854 radeon_emit(cs, va >> 32);
6855 } else {
6856 si_cs_emit_write_event_eop(cs,
6857 cmd_buffer->device->physical_device->rad_info.chip_class,
6858 radv_cmd_buffer_uses_mec(cmd_buffer),
6859 V_028A90_BOTTOM_OF_PIPE_TS, 0,
6860 EOP_DST_SEL_MEM,
6861 EOP_DATA_SEL_VALUE_32BIT,
6862 va, marker,
6863 cmd_buffer->gfx9_eop_bug_va);
6864 }
6865
6866 assert(cmd_buffer->cs->cdw <= cdw_max);
6867 }