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radv: fix updating bound fast ds clear values with different aspects
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 bool src_render_loop,
58 VkImageLayout dst_layout,
59 bool dst_render_loop,
60 uint32_t src_family,
61 uint32_t dst_family,
62 const VkImageSubresourceRange *range,
63 struct radv_sample_locations_state *sample_locs);
64
65 const struct radv_dynamic_state default_dynamic_state = {
66 .viewport = {
67 .count = 0,
68 },
69 .scissor = {
70 .count = 0,
71 },
72 .line_width = 1.0f,
73 .depth_bias = {
74 .bias = 0.0f,
75 .clamp = 0.0f,
76 .slope = 0.0f,
77 },
78 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
79 .depth_bounds = {
80 .min = 0.0f,
81 .max = 1.0f,
82 },
83 .stencil_compare_mask = {
84 .front = ~0u,
85 .back = ~0u,
86 },
87 .stencil_write_mask = {
88 .front = ~0u,
89 .back = ~0u,
90 },
91 .stencil_reference = {
92 .front = 0u,
93 .back = 0u,
94 },
95 };
96
97 static void
98 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
99 const struct radv_dynamic_state *src)
100 {
101 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
102 uint32_t copy_mask = src->mask;
103 uint32_t dest_mask = 0;
104
105 /* Make sure to copy the number of viewports/scissors because they can
106 * only be specified at pipeline creation time.
107 */
108 dest->viewport.count = src->viewport.count;
109 dest->scissor.count = src->scissor.count;
110 dest->discard_rectangle.count = src->discard_rectangle.count;
111 dest->sample_location.count = src->sample_location.count;
112
113 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
114 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
115 src->viewport.count * sizeof(VkViewport))) {
116 typed_memcpy(dest->viewport.viewports,
117 src->viewport.viewports,
118 src->viewport.count);
119 dest_mask |= RADV_DYNAMIC_VIEWPORT;
120 }
121 }
122
123 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
124 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
125 src->scissor.count * sizeof(VkRect2D))) {
126 typed_memcpy(dest->scissor.scissors,
127 src->scissor.scissors, src->scissor.count);
128 dest_mask |= RADV_DYNAMIC_SCISSOR;
129 }
130 }
131
132 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
133 if (dest->line_width != src->line_width) {
134 dest->line_width = src->line_width;
135 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
136 }
137 }
138
139 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
140 if (memcmp(&dest->depth_bias, &src->depth_bias,
141 sizeof(src->depth_bias))) {
142 dest->depth_bias = src->depth_bias;
143 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
144 }
145 }
146
147 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
148 if (memcmp(&dest->blend_constants, &src->blend_constants,
149 sizeof(src->blend_constants))) {
150 typed_memcpy(dest->blend_constants,
151 src->blend_constants, 4);
152 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
153 }
154 }
155
156 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
157 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
158 sizeof(src->depth_bounds))) {
159 dest->depth_bounds = src->depth_bounds;
160 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
161 }
162 }
163
164 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
165 if (memcmp(&dest->stencil_compare_mask,
166 &src->stencil_compare_mask,
167 sizeof(src->stencil_compare_mask))) {
168 dest->stencil_compare_mask = src->stencil_compare_mask;
169 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
170 }
171 }
172
173 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
174 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
175 sizeof(src->stencil_write_mask))) {
176 dest->stencil_write_mask = src->stencil_write_mask;
177 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
178 }
179 }
180
181 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
182 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
183 sizeof(src->stencil_reference))) {
184 dest->stencil_reference = src->stencil_reference;
185 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
186 }
187 }
188
189 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
190 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
191 src->discard_rectangle.count * sizeof(VkRect2D))) {
192 typed_memcpy(dest->discard_rectangle.rectangles,
193 src->discard_rectangle.rectangles,
194 src->discard_rectangle.count);
195 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
196 }
197 }
198
199 if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
200 if (dest->sample_location.per_pixel != src->sample_location.per_pixel ||
201 dest->sample_location.grid_size.width != src->sample_location.grid_size.width ||
202 dest->sample_location.grid_size.height != src->sample_location.grid_size.height ||
203 memcmp(&dest->sample_location.locations,
204 &src->sample_location.locations,
205 src->sample_location.count * sizeof(VkSampleLocationEXT))) {
206 dest->sample_location.per_pixel = src->sample_location.per_pixel;
207 dest->sample_location.grid_size = src->sample_location.grid_size;
208 typed_memcpy(dest->sample_location.locations,
209 src->sample_location.locations,
210 src->sample_location.count);
211 dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
212 }
213 }
214
215 cmd_buffer->state.dirty |= dest_mask;
216 }
217
218 static void
219 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
220 struct radv_pipeline *pipeline)
221 {
222 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
223 struct radv_shader_info *info;
224
225 if (!pipeline->streamout_shader ||
226 cmd_buffer->device->physical_device->use_ngg_streamout)
227 return;
228
229 info = &pipeline->streamout_shader->info;
230 for (int i = 0; i < MAX_SO_BUFFERS; i++)
231 so->stride_in_dw[i] = info->so.strides[i];
232
233 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
234 }
235
236 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
237 {
238 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
239 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
240 }
241
242 enum ring_type radv_queue_family_to_ring(int f) {
243 switch (f) {
244 case RADV_QUEUE_GENERAL:
245 return RING_GFX;
246 case RADV_QUEUE_COMPUTE:
247 return RING_COMPUTE;
248 case RADV_QUEUE_TRANSFER:
249 return RING_DMA;
250 default:
251 unreachable("Unknown queue family");
252 }
253 }
254
255 static VkResult radv_create_cmd_buffer(
256 struct radv_device * device,
257 struct radv_cmd_pool * pool,
258 VkCommandBufferLevel level,
259 VkCommandBuffer* pCommandBuffer)
260 {
261 struct radv_cmd_buffer *cmd_buffer;
262 unsigned ring;
263 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
264 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
265 if (cmd_buffer == NULL)
266 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
267
268 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
269 cmd_buffer->device = device;
270 cmd_buffer->pool = pool;
271 cmd_buffer->level = level;
272
273 if (pool) {
274 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
275 cmd_buffer->queue_family_index = pool->queue_family_index;
276
277 } else {
278 /* Init the pool_link so we can safely call list_del when we destroy
279 * the command buffer
280 */
281 list_inithead(&cmd_buffer->pool_link);
282 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
283 }
284
285 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
286
287 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
288 if (!cmd_buffer->cs) {
289 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
290 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
291 }
292
293 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
294
295 list_inithead(&cmd_buffer->upload.list);
296
297 return VK_SUCCESS;
298 }
299
300 static void
301 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
302 {
303 list_del(&cmd_buffer->pool_link);
304
305 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
306 &cmd_buffer->upload.list, list) {
307 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
308 list_del(&up->list);
309 free(up);
310 }
311
312 if (cmd_buffer->upload.upload_bo)
313 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
314 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
315
316 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
317 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
318
319 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
320 }
321
322 static VkResult
323 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
324 {
325 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
326
327 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
328 &cmd_buffer->upload.list, list) {
329 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
330 list_del(&up->list);
331 free(up);
332 }
333
334 cmd_buffer->push_constant_stages = 0;
335 cmd_buffer->scratch_size_needed = 0;
336 cmd_buffer->compute_scratch_size_needed = 0;
337 cmd_buffer->esgs_ring_size_needed = 0;
338 cmd_buffer->gsvs_ring_size_needed = 0;
339 cmd_buffer->tess_rings_needed = false;
340 cmd_buffer->gds_needed = false;
341 cmd_buffer->sample_positions_needed = false;
342
343 if (cmd_buffer->upload.upload_bo)
344 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
345 cmd_buffer->upload.upload_bo);
346 cmd_buffer->upload.offset = 0;
347
348 cmd_buffer->record_result = VK_SUCCESS;
349
350 memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
351
352 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
353 cmd_buffer->descriptors[i].dirty = 0;
354 cmd_buffer->descriptors[i].valid = 0;
355 cmd_buffer->descriptors[i].push_dirty = false;
356 }
357
358 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
359 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
360 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
361 unsigned fence_offset, eop_bug_offset;
362 void *fence_ptr;
363
364 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
365 &fence_ptr);
366
367 cmd_buffer->gfx9_fence_va =
368 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
369 cmd_buffer->gfx9_fence_va += fence_offset;
370
371 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
372 /* Allocate a buffer for the EOP bug on GFX9. */
373 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
374 &eop_bug_offset, &fence_ptr);
375 cmd_buffer->gfx9_eop_bug_va =
376 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
377 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
378 }
379 }
380
381 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
382
383 return cmd_buffer->record_result;
384 }
385
386 static bool
387 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
388 uint64_t min_needed)
389 {
390 uint64_t new_size;
391 struct radeon_winsys_bo *bo;
392 struct radv_cmd_buffer_upload *upload;
393 struct radv_device *device = cmd_buffer->device;
394
395 new_size = MAX2(min_needed, 16 * 1024);
396 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
397
398 bo = device->ws->buffer_create(device->ws,
399 new_size, 4096,
400 RADEON_DOMAIN_GTT,
401 RADEON_FLAG_CPU_ACCESS|
402 RADEON_FLAG_NO_INTERPROCESS_SHARING |
403 RADEON_FLAG_32BIT,
404 RADV_BO_PRIORITY_UPLOAD_BUFFER);
405
406 if (!bo) {
407 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
408 return false;
409 }
410
411 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
412 if (cmd_buffer->upload.upload_bo) {
413 upload = malloc(sizeof(*upload));
414
415 if (!upload) {
416 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
417 device->ws->buffer_destroy(bo);
418 return false;
419 }
420
421 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
422 list_add(&upload->list, &cmd_buffer->upload.list);
423 }
424
425 cmd_buffer->upload.upload_bo = bo;
426 cmd_buffer->upload.size = new_size;
427 cmd_buffer->upload.offset = 0;
428 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
429
430 if (!cmd_buffer->upload.map) {
431 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
432 return false;
433 }
434
435 return true;
436 }
437
438 bool
439 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
440 unsigned size,
441 unsigned alignment,
442 unsigned *out_offset,
443 void **ptr)
444 {
445 assert(util_is_power_of_two_nonzero(alignment));
446
447 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
448 if (offset + size > cmd_buffer->upload.size) {
449 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
450 return false;
451 offset = 0;
452 }
453
454 *out_offset = offset;
455 *ptr = cmd_buffer->upload.map + offset;
456
457 cmd_buffer->upload.offset = offset + size;
458 return true;
459 }
460
461 bool
462 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
463 unsigned size, unsigned alignment,
464 const void *data, unsigned *out_offset)
465 {
466 uint8_t *ptr;
467
468 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
469 out_offset, (void **)&ptr))
470 return false;
471
472 if (ptr)
473 memcpy(ptr, data, size);
474
475 return true;
476 }
477
478 static void
479 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
480 unsigned count, const uint32_t *data)
481 {
482 struct radeon_cmdbuf *cs = cmd_buffer->cs;
483
484 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
485
486 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
487 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
488 S_370_WR_CONFIRM(1) |
489 S_370_ENGINE_SEL(V_370_ME));
490 radeon_emit(cs, va);
491 radeon_emit(cs, va >> 32);
492 radeon_emit_array(cs, data, count);
493 }
494
495 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
496 {
497 struct radv_device *device = cmd_buffer->device;
498 struct radeon_cmdbuf *cs = cmd_buffer->cs;
499 uint64_t va;
500
501 va = radv_buffer_get_va(device->trace_bo);
502 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
503 va += 4;
504
505 ++cmd_buffer->state.trace_id;
506 radv_emit_write_data_packet(cmd_buffer, va, 1,
507 &cmd_buffer->state.trace_id);
508
509 radeon_check_space(cmd_buffer->device->ws, cs, 2);
510
511 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
512 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
513 }
514
515 static void
516 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
517 enum radv_cmd_flush_bits flags)
518 {
519 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
520 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
521 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
522
523 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
524
525 /* Force wait for graphics or compute engines to be idle. */
526 si_cs_emit_cache_flush(cmd_buffer->cs,
527 cmd_buffer->device->physical_device->rad_info.chip_class,
528 &cmd_buffer->gfx9_fence_idx,
529 cmd_buffer->gfx9_fence_va,
530 radv_cmd_buffer_uses_mec(cmd_buffer),
531 flags, cmd_buffer->gfx9_eop_bug_va);
532 }
533
534 if (unlikely(cmd_buffer->device->trace_bo))
535 radv_cmd_buffer_trace_emit(cmd_buffer);
536 }
537
538 static void
539 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
540 struct radv_pipeline *pipeline, enum ring_type ring)
541 {
542 struct radv_device *device = cmd_buffer->device;
543 uint32_t data[2];
544 uint64_t va;
545
546 va = radv_buffer_get_va(device->trace_bo);
547
548 switch (ring) {
549 case RING_GFX:
550 va += 8;
551 break;
552 case RING_COMPUTE:
553 va += 16;
554 break;
555 default:
556 assert(!"invalid ring type");
557 }
558
559 uint64_t pipeline_address = (uintptr_t)pipeline;
560 data[0] = pipeline_address;
561 data[1] = pipeline_address >> 32;
562
563 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
564 }
565
566 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
567 VkPipelineBindPoint bind_point,
568 struct radv_descriptor_set *set,
569 unsigned idx)
570 {
571 struct radv_descriptor_state *descriptors_state =
572 radv_get_descriptors_state(cmd_buffer, bind_point);
573
574 descriptors_state->sets[idx] = set;
575
576 descriptors_state->valid |= (1u << idx); /* active descriptors */
577 descriptors_state->dirty |= (1u << idx);
578 }
579
580 static void
581 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
582 VkPipelineBindPoint bind_point)
583 {
584 struct radv_descriptor_state *descriptors_state =
585 radv_get_descriptors_state(cmd_buffer, bind_point);
586 struct radv_device *device = cmd_buffer->device;
587 uint32_t data[MAX_SETS * 2] = {};
588 uint64_t va;
589 unsigned i;
590 va = radv_buffer_get_va(device->trace_bo) + 24;
591
592 for_each_bit(i, descriptors_state->valid) {
593 struct radv_descriptor_set *set = descriptors_state->sets[i];
594 data[i * 2] = (uint64_t)(uintptr_t)set;
595 data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
596 }
597
598 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
599 }
600
601 struct radv_userdata_info *
602 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
603 gl_shader_stage stage,
604 int idx)
605 {
606 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
607 return &shader->info.user_sgprs_locs.shader_data[idx];
608 }
609
610 static void
611 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
612 struct radv_pipeline *pipeline,
613 gl_shader_stage stage,
614 int idx, uint64_t va)
615 {
616 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
617 uint32_t base_reg = pipeline->user_data_0[stage];
618 if (loc->sgpr_idx == -1)
619 return;
620
621 assert(loc->num_sgprs == 1);
622
623 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
624 base_reg + loc->sgpr_idx * 4, va, false);
625 }
626
627 static void
628 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
629 struct radv_pipeline *pipeline,
630 struct radv_descriptor_state *descriptors_state,
631 gl_shader_stage stage)
632 {
633 struct radv_device *device = cmd_buffer->device;
634 struct radeon_cmdbuf *cs = cmd_buffer->cs;
635 uint32_t sh_base = pipeline->user_data_0[stage];
636 struct radv_userdata_locations *locs =
637 &pipeline->shaders[stage]->info.user_sgprs_locs;
638 unsigned mask = locs->descriptor_sets_enabled;
639
640 mask &= descriptors_state->dirty & descriptors_state->valid;
641
642 while (mask) {
643 int start, count;
644
645 u_bit_scan_consecutive_range(&mask, &start, &count);
646
647 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
648 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
649
650 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
651 for (int i = 0; i < count; i++) {
652 struct radv_descriptor_set *set =
653 descriptors_state->sets[start + i];
654
655 radv_emit_shader_pointer_body(device, cs, set->va, true);
656 }
657 }
658 }
659
660 /**
661 * Convert the user sample locations to hardware sample locations (the values
662 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
663 */
664 static void
665 radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
666 uint32_t x, uint32_t y, VkOffset2D *sample_locs)
667 {
668 uint32_t x_offset = x % state->grid_size.width;
669 uint32_t y_offset = y % state->grid_size.height;
670 uint32_t num_samples = (uint32_t)state->per_pixel;
671 VkSampleLocationEXT *user_locs;
672 uint32_t pixel_offset;
673
674 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
675
676 assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
677 user_locs = &state->locations[pixel_offset];
678
679 for (uint32_t i = 0; i < num_samples; i++) {
680 float shifted_pos_x = user_locs[i].x - 0.5;
681 float shifted_pos_y = user_locs[i].y - 0.5;
682
683 int32_t scaled_pos_x = floor(shifted_pos_x * 16);
684 int32_t scaled_pos_y = floor(shifted_pos_y * 16);
685
686 sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
687 sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
688 }
689 }
690
691 /**
692 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
693 * locations.
694 */
695 static void
696 radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
697 uint32_t *sample_locs_pixel)
698 {
699 for (uint32_t i = 0; i < num_samples; i++) {
700 uint32_t sample_reg_idx = i / 4;
701 uint32_t sample_loc_idx = i % 4;
702 int32_t pos_x = sample_locs[i].x;
703 int32_t pos_y = sample_locs[i].y;
704
705 uint32_t shift_x = 8 * sample_loc_idx;
706 uint32_t shift_y = shift_x + 4;
707
708 sample_locs_pixel[sample_reg_idx] |= (pos_x & 0xf) << shift_x;
709 sample_locs_pixel[sample_reg_idx] |= (pos_y & 0xf) << shift_y;
710 }
711 }
712
713 /**
714 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
715 * sample locations.
716 */
717 static uint64_t
718 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer,
719 VkOffset2D *sample_locs,
720 uint32_t num_samples)
721 {
722 uint32_t centroid_priorities[num_samples];
723 uint32_t sample_mask = num_samples - 1;
724 uint32_t distances[num_samples];
725 uint64_t centroid_priority = 0;
726
727 /* Compute the distances from center for each sample. */
728 for (int i = 0; i < num_samples; i++) {
729 distances[i] = (sample_locs[i].x * sample_locs[i].x) +
730 (sample_locs[i].y * sample_locs[i].y);
731 }
732
733 /* Compute the centroid priorities by looking at the distances array. */
734 for (int i = 0; i < num_samples; i++) {
735 uint32_t min_idx = 0;
736
737 for (int j = 1; j < num_samples; j++) {
738 if (distances[j] < distances[min_idx])
739 min_idx = j;
740 }
741
742 centroid_priorities[i] = min_idx;
743 distances[min_idx] = 0xffffffff;
744 }
745
746 /* Compute the final centroid priority. */
747 for (int i = 0; i < 8; i++) {
748 centroid_priority |=
749 centroid_priorities[i & sample_mask] << (i * 4);
750 }
751
752 return centroid_priority << 32 | centroid_priority;
753 }
754
755 /**
756 * Emit the sample locations that are specified with VK_EXT_sample_locations.
757 */
758 static void
759 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
760 {
761 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
762 struct radv_multisample_state *ms = &pipeline->graphics.ms;
763 struct radv_sample_locations_state *sample_location =
764 &cmd_buffer->state.dynamic.sample_location;
765 uint32_t num_samples = (uint32_t)sample_location->per_pixel;
766 struct radeon_cmdbuf *cs = cmd_buffer->cs;
767 uint32_t sample_locs_pixel[4][2] = {};
768 VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
769 uint32_t max_sample_dist = 0;
770 uint64_t centroid_priority;
771
772 if (!cmd_buffer->state.dynamic.sample_location.count)
773 return;
774
775 /* Convert the user sample locations to hardware sample locations. */
776 radv_convert_user_sample_locs(sample_location, 0, 0, sample_locs[0]);
777 radv_convert_user_sample_locs(sample_location, 1, 0, sample_locs[1]);
778 radv_convert_user_sample_locs(sample_location, 0, 1, sample_locs[2]);
779 radv_convert_user_sample_locs(sample_location, 1, 1, sample_locs[3]);
780
781 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
782 for (uint32_t i = 0; i < 4; i++) {
783 radv_compute_sample_locs_pixel(num_samples, sample_locs[i],
784 sample_locs_pixel[i]);
785 }
786
787 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
788 centroid_priority =
789 radv_compute_centroid_priority(cmd_buffer, sample_locs[0],
790 num_samples);
791
792 /* Compute the maximum sample distance from the specified locations. */
793 for (uint32_t i = 0; i < num_samples; i++) {
794 VkOffset2D offset = sample_locs[0][i];
795 max_sample_dist = MAX2(max_sample_dist,
796 MAX2(abs(offset.x), abs(offset.y)));
797 }
798
799 /* Emit the specified user sample locations. */
800 switch (num_samples) {
801 case 2:
802 case 4:
803 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
804 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
805 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
806 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
807 break;
808 case 8:
809 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
810 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
811 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
812 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
813 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs_pixel[0][1]);
814 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs_pixel[1][1]);
815 radeon_set_context_reg(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs_pixel[2][1]);
816 radeon_set_context_reg(cs, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs_pixel[3][1]);
817 break;
818 default:
819 unreachable("invalid number of samples");
820 }
821
822 /* Emit the maximum sample distance and the centroid priority. */
823 uint32_t pa_sc_aa_config = ms->pa_sc_aa_config;
824
825 pa_sc_aa_config &= C_028BE0_MAX_SAMPLE_DIST;
826 pa_sc_aa_config |= S_028BE0_MAX_SAMPLE_DIST(max_sample_dist);
827
828 radeon_set_context_reg_seq(cs, R_028BE0_PA_SC_AA_CONFIG, 1);
829 radeon_emit(cs, pa_sc_aa_config);
830
831 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
832 radeon_emit(cs, centroid_priority);
833 radeon_emit(cs, centroid_priority >> 32);
834
835 /* GFX9: Flush DFSM when the AA mode changes. */
836 if (cmd_buffer->device->dfsm_allowed) {
837 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
838 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
839 }
840
841 cmd_buffer->state.context_roll_without_scissor_emitted = true;
842 }
843
844 static void
845 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
846 struct radv_pipeline *pipeline,
847 gl_shader_stage stage,
848 int idx, int count, uint32_t *values)
849 {
850 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
851 uint32_t base_reg = pipeline->user_data_0[stage];
852 if (loc->sgpr_idx == -1)
853 return;
854
855 assert(loc->num_sgprs == count);
856
857 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
858 radeon_emit_array(cmd_buffer->cs, values, count);
859 }
860
861 static void
862 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
863 struct radv_pipeline *pipeline)
864 {
865 int num_samples = pipeline->graphics.ms.num_samples;
866 struct radv_multisample_state *ms = &pipeline->graphics.ms;
867 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
868
869 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.needs_sample_positions)
870 cmd_buffer->sample_positions_needed = true;
871
872 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
873 return;
874
875 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
876 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
877 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
878
879 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
880
881 radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
882
883 /* GFX9: Flush DFSM when the AA mode changes. */
884 if (cmd_buffer->device->dfsm_allowed) {
885 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
886 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
887 }
888
889 cmd_buffer->state.context_roll_without_scissor_emitted = true;
890 }
891
892 static void
893 radv_update_binning_state(struct radv_cmd_buffer *cmd_buffer,
894 struct radv_pipeline *pipeline)
895 {
896 const struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
897
898
899 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
900 return;
901
902 if (old_pipeline &&
903 old_pipeline->graphics.binning.pa_sc_binner_cntl_0 == pipeline->graphics.binning.pa_sc_binner_cntl_0 &&
904 old_pipeline->graphics.binning.db_dfsm_control == pipeline->graphics.binning.db_dfsm_control)
905 return;
906
907 bool binning_flush = false;
908 if (cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA12 ||
909 cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA20 ||
910 cmd_buffer->device->physical_device->rad_info.family == CHIP_RAVEN2 ||
911 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
912 binning_flush = !old_pipeline ||
913 G_028C44_BINNING_MODE(old_pipeline->graphics.binning.pa_sc_binner_cntl_0) !=
914 G_028C44_BINNING_MODE(pipeline->graphics.binning.pa_sc_binner_cntl_0);
915 }
916
917 radeon_set_context_reg(cmd_buffer->cs, R_028C44_PA_SC_BINNER_CNTL_0,
918 pipeline->graphics.binning.pa_sc_binner_cntl_0 |
919 S_028C44_FLUSH_ON_BINNING_TRANSITION(!!binning_flush));
920
921 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
922 radeon_set_context_reg(cmd_buffer->cs, R_028038_DB_DFSM_CONTROL,
923 pipeline->graphics.binning.db_dfsm_control);
924 } else {
925 radeon_set_context_reg(cmd_buffer->cs, R_028060_DB_DFSM_CONTROL,
926 pipeline->graphics.binning.db_dfsm_control);
927 }
928
929 cmd_buffer->state.context_roll_without_scissor_emitted = true;
930 }
931
932
933 static void
934 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
935 struct radv_shader_variant *shader)
936 {
937 uint64_t va;
938
939 if (!shader)
940 return;
941
942 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
943
944 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
945 }
946
947 static void
948 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
949 struct radv_pipeline *pipeline,
950 bool vertex_stage_only)
951 {
952 struct radv_cmd_state *state = &cmd_buffer->state;
953 uint32_t mask = state->prefetch_L2_mask;
954
955 if (vertex_stage_only) {
956 /* Fast prefetch path for starting draws as soon as possible.
957 */
958 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
959 RADV_PREFETCH_VBO_DESCRIPTORS);
960 }
961
962 if (mask & RADV_PREFETCH_VS)
963 radv_emit_shader_prefetch(cmd_buffer,
964 pipeline->shaders[MESA_SHADER_VERTEX]);
965
966 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
967 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
968
969 if (mask & RADV_PREFETCH_TCS)
970 radv_emit_shader_prefetch(cmd_buffer,
971 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
972
973 if (mask & RADV_PREFETCH_TES)
974 radv_emit_shader_prefetch(cmd_buffer,
975 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
976
977 if (mask & RADV_PREFETCH_GS) {
978 radv_emit_shader_prefetch(cmd_buffer,
979 pipeline->shaders[MESA_SHADER_GEOMETRY]);
980 if (radv_pipeline_has_gs_copy_shader(pipeline))
981 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
982 }
983
984 if (mask & RADV_PREFETCH_PS)
985 radv_emit_shader_prefetch(cmd_buffer,
986 pipeline->shaders[MESA_SHADER_FRAGMENT]);
987
988 state->prefetch_L2_mask &= ~mask;
989 }
990
991 static void
992 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
993 {
994 if (!cmd_buffer->device->physical_device->rad_info.rbplus_allowed)
995 return;
996
997 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
998 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
999
1000 unsigned sx_ps_downconvert = 0;
1001 unsigned sx_blend_opt_epsilon = 0;
1002 unsigned sx_blend_opt_control = 0;
1003
1004 for (unsigned i = 0; i < subpass->color_count; ++i) {
1005 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1006 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1007 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1008 continue;
1009 }
1010
1011 int idx = subpass->color_attachments[i].attachment;
1012 struct radv_color_buffer_info *cb = &cmd_buffer->state.attachments[idx].cb;
1013
1014 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
1015 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
1016 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
1017 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
1018
1019 bool has_alpha, has_rgb;
1020
1021 /* Set if RGB and A are present. */
1022 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
1023
1024 if (format == V_028C70_COLOR_8 ||
1025 format == V_028C70_COLOR_16 ||
1026 format == V_028C70_COLOR_32)
1027 has_rgb = !has_alpha;
1028 else
1029 has_rgb = true;
1030
1031 /* Check the colormask and export format. */
1032 if (!(colormask & 0x7))
1033 has_rgb = false;
1034 if (!(colormask & 0x8))
1035 has_alpha = false;
1036
1037 if (spi_format == V_028714_SPI_SHADER_ZERO) {
1038 has_rgb = false;
1039 has_alpha = false;
1040 }
1041
1042 /* Disable value checking for disabled channels. */
1043 if (!has_rgb)
1044 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1045 if (!has_alpha)
1046 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1047
1048 /* Enable down-conversion for 32bpp and smaller formats. */
1049 switch (format) {
1050 case V_028C70_COLOR_8:
1051 case V_028C70_COLOR_8_8:
1052 case V_028C70_COLOR_8_8_8_8:
1053 /* For 1 and 2-channel formats, use the superset thereof. */
1054 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
1055 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1056 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1057 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
1058 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
1059 }
1060 break;
1061
1062 case V_028C70_COLOR_5_6_5:
1063 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1064 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
1065 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
1066 }
1067 break;
1068
1069 case V_028C70_COLOR_1_5_5_5:
1070 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1071 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
1072 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
1073 }
1074 break;
1075
1076 case V_028C70_COLOR_4_4_4_4:
1077 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1078 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
1079 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
1080 }
1081 break;
1082
1083 case V_028C70_COLOR_32:
1084 if (swap == V_028C70_SWAP_STD &&
1085 spi_format == V_028714_SPI_SHADER_32_R)
1086 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1087 else if (swap == V_028C70_SWAP_ALT_REV &&
1088 spi_format == V_028714_SPI_SHADER_32_AR)
1089 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
1090 break;
1091
1092 case V_028C70_COLOR_16:
1093 case V_028C70_COLOR_16_16:
1094 /* For 1-channel formats, use the superset thereof. */
1095 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
1096 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
1097 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1098 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1099 if (swap == V_028C70_SWAP_STD ||
1100 swap == V_028C70_SWAP_STD_REV)
1101 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
1102 else
1103 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
1104 }
1105 break;
1106
1107 case V_028C70_COLOR_10_11_11:
1108 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1109 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
1110 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
1111 }
1112 break;
1113
1114 case V_028C70_COLOR_2_10_10_10:
1115 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1116 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
1117 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
1118 }
1119 break;
1120 }
1121 }
1122
1123 for (unsigned i = subpass->color_count; i < 8; ++i) {
1124 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1125 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1126 }
1127 /* TODO: avoid redundantly setting context registers */
1128 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
1129 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
1130 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
1131 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
1132
1133 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1134 }
1135
1136 static void
1137 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1138 {
1139 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1140
1141 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1142 return;
1143
1144 radv_update_multisample_state(cmd_buffer, pipeline);
1145 radv_update_binning_state(cmd_buffer, pipeline);
1146
1147 cmd_buffer->scratch_size_needed =
1148 MAX2(cmd_buffer->scratch_size_needed,
1149 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1150
1151 if (!cmd_buffer->state.emitted_pipeline ||
1152 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1153 pipeline->graphics.can_use_guardband)
1154 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1155
1156 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
1157
1158 if (!cmd_buffer->state.emitted_pipeline ||
1159 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
1160 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
1161 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
1162 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
1163 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
1164 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1165 }
1166
1167 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
1168 if (!pipeline->shaders[i])
1169 continue;
1170
1171 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1172 pipeline->shaders[i]->bo);
1173 }
1174
1175 if (radv_pipeline_has_gs_copy_shader(pipeline))
1176 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1177 pipeline->gs_copy_shader->bo);
1178
1179 if (unlikely(cmd_buffer->device->trace_bo))
1180 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1181
1182 cmd_buffer->state.emitted_pipeline = pipeline;
1183
1184 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1185 }
1186
1187 static void
1188 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1189 {
1190 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1191 cmd_buffer->state.dynamic.viewport.viewports);
1192 }
1193
1194 static void
1195 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1196 {
1197 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1198
1199 si_write_scissors(cmd_buffer->cs, 0, count,
1200 cmd_buffer->state.dynamic.scissor.scissors,
1201 cmd_buffer->state.dynamic.viewport.viewports,
1202 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1203
1204 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1205 }
1206
1207 static void
1208 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1209 {
1210 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1211 return;
1212
1213 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1214 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1215 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1216 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1217 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1218 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1219 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1220 }
1221 }
1222
1223 static void
1224 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1225 {
1226 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1227
1228 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1229 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1230 }
1231
1232 static void
1233 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1234 {
1235 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1236
1237 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1238 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1239 }
1240
1241 static void
1242 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1243 {
1244 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1245
1246 radeon_set_context_reg_seq(cmd_buffer->cs,
1247 R_028430_DB_STENCILREFMASK, 2);
1248 radeon_emit(cmd_buffer->cs,
1249 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1250 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1251 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1252 S_028430_STENCILOPVAL(1));
1253 radeon_emit(cmd_buffer->cs,
1254 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1255 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1256 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1257 S_028434_STENCILOPVAL_BF(1));
1258 }
1259
1260 static void
1261 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1262 {
1263 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1264
1265 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1266 fui(d->depth_bounds.min));
1267 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1268 fui(d->depth_bounds.max));
1269 }
1270
1271 static void
1272 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1273 {
1274 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1275 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1276 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1277
1278
1279 radeon_set_context_reg_seq(cmd_buffer->cs,
1280 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1281 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1282 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1283 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1284 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1285 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1286 }
1287
1288 static void
1289 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1290 int index,
1291 struct radv_color_buffer_info *cb,
1292 struct radv_image_view *iview,
1293 VkImageLayout layout,
1294 bool in_render_loop)
1295 {
1296 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
1297 uint32_t cb_color_info = cb->cb_color_info;
1298 struct radv_image *image = iview->image;
1299
1300 if (!radv_layout_dcc_compressed(cmd_buffer->device, image, layout, in_render_loop,
1301 radv_image_queue_family_mask(image,
1302 cmd_buffer->queue_family_index,
1303 cmd_buffer->queue_family_index))) {
1304 cb_color_info &= C_028C70_DCC_ENABLE;
1305 }
1306
1307 if (radv_image_is_tc_compat_cmask(image) &&
1308 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1309 radv_is_dcc_decompress_pipeline(cmd_buffer))) {
1310 /* If this bit is set, the FMASK decompression operation
1311 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1312 */
1313 cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
1314 }
1315
1316 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1317 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1318 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1319 radeon_emit(cmd_buffer->cs, 0);
1320 radeon_emit(cmd_buffer->cs, 0);
1321 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1322 radeon_emit(cmd_buffer->cs, cb_color_info);
1323 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1324 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1325 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1326 radeon_emit(cmd_buffer->cs, 0);
1327 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1328 radeon_emit(cmd_buffer->cs, 0);
1329
1330 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 1);
1331 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1332
1333 radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4,
1334 cb->cb_color_base >> 32);
1335 radeon_set_context_reg(cmd_buffer->cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + index * 4,
1336 cb->cb_color_cmask >> 32);
1337 radeon_set_context_reg(cmd_buffer->cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + index * 4,
1338 cb->cb_color_fmask >> 32);
1339 radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4,
1340 cb->cb_dcc_base >> 32);
1341 radeon_set_context_reg(cmd_buffer->cs, R_028EC0_CB_COLOR0_ATTRIB2 + index * 4,
1342 cb->cb_color_attrib2);
1343 radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4,
1344 cb->cb_color_attrib3);
1345 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1346 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1347 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1348 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1349 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1350 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1351 radeon_emit(cmd_buffer->cs, cb_color_info);
1352 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1353 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1354 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1355 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1356 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1357 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1358
1359 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1360 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1361 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1362
1363 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1364 cb->cb_mrt_epitch);
1365 } else {
1366 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1367 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1368 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1369 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1370 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1371 radeon_emit(cmd_buffer->cs, cb_color_info);
1372 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1373 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1374 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1375 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1376 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1377 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1378
1379 if (is_vi) { /* DCC BASE */
1380 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1381 }
1382 }
1383
1384 if (radv_dcc_enabled(image, iview->base_mip)) {
1385 /* Drawing with DCC enabled also compresses colorbuffers. */
1386 VkImageSubresourceRange range = {
1387 .aspectMask = iview->aspect_mask,
1388 .baseMipLevel = iview->base_mip,
1389 .levelCount = iview->level_count,
1390 .baseArrayLayer = iview->base_layer,
1391 .layerCount = iview->layer_count,
1392 };
1393
1394 radv_update_dcc_metadata(cmd_buffer, image, &range, true);
1395 }
1396 }
1397
1398 static void
1399 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1400 struct radv_ds_buffer_info *ds,
1401 const struct radv_image_view *iview,
1402 VkImageLayout layout,
1403 bool in_render_loop, bool requires_cond_exec)
1404 {
1405 const struct radv_image *image = iview->image;
1406 uint32_t db_z_info = ds->db_z_info;
1407 uint32_t db_z_info_reg;
1408
1409 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug ||
1410 !radv_image_is_tc_compat_htile(image))
1411 return;
1412
1413 if (!radv_layout_has_htile(image, layout, in_render_loop,
1414 radv_image_queue_family_mask(image,
1415 cmd_buffer->queue_family_index,
1416 cmd_buffer->queue_family_index))) {
1417 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1418 }
1419
1420 db_z_info &= C_028040_ZRANGE_PRECISION;
1421
1422 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1423 db_z_info_reg = R_028038_DB_Z_INFO;
1424 } else {
1425 db_z_info_reg = R_028040_DB_Z_INFO;
1426 }
1427
1428 /* When we don't know the last fast clear value we need to emit a
1429 * conditional packet that will eventually skip the following
1430 * SET_CONTEXT_REG packet.
1431 */
1432 if (requires_cond_exec) {
1433 uint64_t va = radv_get_tc_compat_zrange_va(image, iview->base_mip);
1434
1435 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1436 radeon_emit(cmd_buffer->cs, va);
1437 radeon_emit(cmd_buffer->cs, va >> 32);
1438 radeon_emit(cmd_buffer->cs, 0);
1439 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1440 }
1441
1442 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1443 }
1444
1445 static void
1446 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1447 struct radv_ds_buffer_info *ds,
1448 struct radv_image_view *iview,
1449 VkImageLayout layout,
1450 bool in_render_loop)
1451 {
1452 const struct radv_image *image = iview->image;
1453 uint32_t db_z_info = ds->db_z_info;
1454 uint32_t db_stencil_info = ds->db_stencil_info;
1455
1456 if (!radv_layout_has_htile(image, layout, in_render_loop,
1457 radv_image_queue_family_mask(image,
1458 cmd_buffer->queue_family_index,
1459 cmd_buffer->queue_family_index))) {
1460 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1461 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1462 }
1463
1464 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1465 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1466
1467 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1468 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1469 radeon_set_context_reg(cmd_buffer->cs, R_02801C_DB_DEPTH_SIZE_XY, ds->db_depth_size);
1470
1471 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 7);
1472 radeon_emit(cmd_buffer->cs, S_02803C_RESOURCE_LEVEL(1));
1473 radeon_emit(cmd_buffer->cs, db_z_info);
1474 radeon_emit(cmd_buffer->cs, db_stencil_info);
1475 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1476 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1477 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1478 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1479
1480 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_READ_BASE_HI, 5);
1481 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1482 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1483 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1484 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1485 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1486 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1487 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1488 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1489 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1490 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1491
1492 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1493 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1494 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1495 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1496 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1497 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1498 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1499 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1500 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1501 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1502 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1503
1504 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1505 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1506 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1507 } else {
1508 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1509
1510 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1511 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1512 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1513 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1514 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1515 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1516 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1517 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1518 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1519 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1520
1521 }
1522
1523 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1524 radv_update_zrange_precision(cmd_buffer, ds, iview, layout,
1525 in_render_loop, true);
1526
1527 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1528 ds->pa_su_poly_offset_db_fmt_cntl);
1529 }
1530
1531 /**
1532 * Update the fast clear depth/stencil values if the image is bound as a
1533 * depth/stencil buffer.
1534 */
1535 static void
1536 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1537 const struct radv_image_view *iview,
1538 VkClearDepthStencilValue ds_clear_value,
1539 VkImageAspectFlags aspects)
1540 {
1541 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1542 const struct radv_image *image = iview->image;
1543 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1544 uint32_t att_idx;
1545
1546 if (!cmd_buffer->state.attachments || !subpass)
1547 return;
1548
1549 if (!subpass->depth_stencil_attachment)
1550 return;
1551
1552 att_idx = subpass->depth_stencil_attachment->attachment;
1553 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1554 return;
1555
1556 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1557 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1558 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1559 radeon_emit(cs, ds_clear_value.stencil);
1560 radeon_emit(cs, fui(ds_clear_value.depth));
1561 } else if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1562 radeon_set_context_reg_seq(cs, R_02802C_DB_DEPTH_CLEAR, 1);
1563 radeon_emit(cs, fui(ds_clear_value.depth));
1564 } else {
1565 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1566 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 1);
1567 radeon_emit(cs, ds_clear_value.stencil);
1568 }
1569
1570 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1571 * only needed when clearing Z to 0.0.
1572 */
1573 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1574 ds_clear_value.depth == 0.0) {
1575 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1576 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
1577
1578 radv_update_zrange_precision(cmd_buffer, &cmd_buffer->state.attachments[att_idx].ds,
1579 iview, layout, in_render_loop, false);
1580 }
1581
1582 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1583 }
1584
1585 /**
1586 * Set the clear depth/stencil values to the image's metadata.
1587 */
1588 static void
1589 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1590 struct radv_image *image,
1591 const VkImageSubresourceRange *range,
1592 VkClearDepthStencilValue ds_clear_value,
1593 VkImageAspectFlags aspects)
1594 {
1595 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1596 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel);
1597 uint32_t level_count = radv_get_levelCount(image, range);
1598
1599 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1600 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1601 /* Use the fastest way when both aspects are used. */
1602 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + 2 * level_count, cmd_buffer->state.predicating));
1603 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1604 S_370_WR_CONFIRM(1) |
1605 S_370_ENGINE_SEL(V_370_PFP));
1606 radeon_emit(cs, va);
1607 radeon_emit(cs, va >> 32);
1608
1609 for (uint32_t l = 0; l < level_count; l++) {
1610 radeon_emit(cs, ds_clear_value.stencil);
1611 radeon_emit(cs, fui(ds_clear_value.depth));
1612 }
1613 } else {
1614 /* Otherwise we need one WRITE_DATA packet per level. */
1615 for (uint32_t l = 0; l < level_count; l++) {
1616 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel + l);
1617 unsigned value;
1618
1619 if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1620 value = fui(ds_clear_value.depth);
1621 va += 4;
1622 } else {
1623 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1624 value = ds_clear_value.stencil;
1625 }
1626
1627 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1628 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1629 S_370_WR_CONFIRM(1) |
1630 S_370_ENGINE_SEL(V_370_PFP));
1631 radeon_emit(cs, va);
1632 radeon_emit(cs, va >> 32);
1633 radeon_emit(cs, value);
1634 }
1635 }
1636 }
1637
1638 /**
1639 * Update the TC-compat metadata value for this image.
1640 */
1641 static void
1642 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1643 struct radv_image *image,
1644 const VkImageSubresourceRange *range,
1645 uint32_t value)
1646 {
1647 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1648
1649 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug)
1650 return;
1651
1652 uint64_t va = radv_get_tc_compat_zrange_va(image, range->baseMipLevel);
1653 uint32_t level_count = radv_get_levelCount(image, range);
1654
1655 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + level_count, cmd_buffer->state.predicating));
1656 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1657 S_370_WR_CONFIRM(1) |
1658 S_370_ENGINE_SEL(V_370_PFP));
1659 radeon_emit(cs, va);
1660 radeon_emit(cs, va >> 32);
1661
1662 for (uint32_t l = 0; l < level_count; l++)
1663 radeon_emit(cs, value);
1664 }
1665
1666 static void
1667 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1668 const struct radv_image_view *iview,
1669 VkClearDepthStencilValue ds_clear_value)
1670 {
1671 VkImageSubresourceRange range = {
1672 .aspectMask = iview->aspect_mask,
1673 .baseMipLevel = iview->base_mip,
1674 .levelCount = iview->level_count,
1675 .baseArrayLayer = iview->base_layer,
1676 .layerCount = iview->layer_count,
1677 };
1678 uint32_t cond_val;
1679
1680 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1681 * depth clear value is 0.0f.
1682 */
1683 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1684
1685 radv_set_tc_compat_zrange_metadata(cmd_buffer, iview->image, &range,
1686 cond_val);
1687 }
1688
1689 /**
1690 * Update the clear depth/stencil values for this image.
1691 */
1692 void
1693 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1694 const struct radv_image_view *iview,
1695 VkClearDepthStencilValue ds_clear_value,
1696 VkImageAspectFlags aspects)
1697 {
1698 VkImageSubresourceRange range = {
1699 .aspectMask = iview->aspect_mask,
1700 .baseMipLevel = iview->base_mip,
1701 .levelCount = iview->level_count,
1702 .baseArrayLayer = iview->base_layer,
1703 .layerCount = iview->layer_count,
1704 };
1705 struct radv_image *image = iview->image;
1706
1707 assert(radv_image_has_htile(image));
1708
1709 radv_set_ds_clear_metadata(cmd_buffer, iview->image, &range,
1710 ds_clear_value, aspects);
1711
1712 if (radv_image_is_tc_compat_htile(image) &&
1713 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1714 radv_update_tc_compat_zrange_metadata(cmd_buffer, iview,
1715 ds_clear_value);
1716 }
1717
1718 radv_update_bound_fast_clear_ds(cmd_buffer, iview, ds_clear_value,
1719 aspects);
1720 }
1721
1722 /**
1723 * Load the clear depth/stencil values from the image's metadata.
1724 */
1725 static void
1726 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1727 const struct radv_image_view *iview)
1728 {
1729 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1730 const struct radv_image *image = iview->image;
1731 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1732 uint64_t va = radv_get_ds_clear_value_va(image, iview->base_mip);
1733 unsigned reg_offset = 0, reg_count = 0;
1734
1735 if (!radv_image_has_htile(image))
1736 return;
1737
1738 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1739 ++reg_count;
1740 } else {
1741 ++reg_offset;
1742 va += 4;
1743 }
1744 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1745 ++reg_count;
1746
1747 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1748
1749 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
1750 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1751 radeon_emit(cs, va);
1752 radeon_emit(cs, va >> 32);
1753 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1754 radeon_emit(cs, reg_count);
1755 } else {
1756 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1757 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1758 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1759 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1760 radeon_emit(cs, va);
1761 radeon_emit(cs, va >> 32);
1762 radeon_emit(cs, reg >> 2);
1763 radeon_emit(cs, 0);
1764
1765 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1766 radeon_emit(cs, 0);
1767 }
1768 }
1769
1770 /*
1771 * With DCC some colors don't require CMASK elimination before being
1772 * used as a texture. This sets a predicate value to determine if the
1773 * cmask eliminate is required.
1774 */
1775 void
1776 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1777 struct radv_image *image,
1778 const VkImageSubresourceRange *range, bool value)
1779 {
1780 uint64_t pred_val = value;
1781 uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
1782 uint32_t level_count = radv_get_levelCount(image, range);
1783 uint32_t count = 2 * level_count;
1784
1785 assert(radv_dcc_enabled(image, range->baseMipLevel));
1786
1787 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1788 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1789 S_370_WR_CONFIRM(1) |
1790 S_370_ENGINE_SEL(V_370_PFP));
1791 radeon_emit(cmd_buffer->cs, va);
1792 radeon_emit(cmd_buffer->cs, va >> 32);
1793
1794 for (uint32_t l = 0; l < level_count; l++) {
1795 radeon_emit(cmd_buffer->cs, pred_val);
1796 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1797 }
1798 }
1799
1800 /**
1801 * Update the DCC predicate to reflect the compression state.
1802 */
1803 void
1804 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1805 struct radv_image *image,
1806 const VkImageSubresourceRange *range, bool value)
1807 {
1808 uint64_t pred_val = value;
1809 uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
1810 uint32_t level_count = radv_get_levelCount(image, range);
1811 uint32_t count = 2 * level_count;
1812
1813 assert(radv_dcc_enabled(image, range->baseMipLevel));
1814
1815 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1816 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1817 S_370_WR_CONFIRM(1) |
1818 S_370_ENGINE_SEL(V_370_PFP));
1819 radeon_emit(cmd_buffer->cs, va);
1820 radeon_emit(cmd_buffer->cs, va >> 32);
1821
1822 for (uint32_t l = 0; l < level_count; l++) {
1823 radeon_emit(cmd_buffer->cs, pred_val);
1824 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1825 }
1826 }
1827
1828 /**
1829 * Update the fast clear color values if the image is bound as a color buffer.
1830 */
1831 static void
1832 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1833 struct radv_image *image,
1834 int cb_idx,
1835 uint32_t color_values[2])
1836 {
1837 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1838 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1839 uint32_t att_idx;
1840
1841 if (!cmd_buffer->state.attachments || !subpass)
1842 return;
1843
1844 att_idx = subpass->color_attachments[cb_idx].attachment;
1845 if (att_idx == VK_ATTACHMENT_UNUSED)
1846 return;
1847
1848 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1849 return;
1850
1851 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1852 radeon_emit(cs, color_values[0]);
1853 radeon_emit(cs, color_values[1]);
1854
1855 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1856 }
1857
1858 /**
1859 * Set the clear color values to the image's metadata.
1860 */
1861 static void
1862 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1863 struct radv_image *image,
1864 const VkImageSubresourceRange *range,
1865 uint32_t color_values[2])
1866 {
1867 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1868 uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
1869 uint32_t level_count = radv_get_levelCount(image, range);
1870 uint32_t count = 2 * level_count;
1871
1872 assert(radv_image_has_cmask(image) ||
1873 radv_dcc_enabled(image, range->baseMipLevel));
1874
1875 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
1876 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1877 S_370_WR_CONFIRM(1) |
1878 S_370_ENGINE_SEL(V_370_PFP));
1879 radeon_emit(cs, va);
1880 radeon_emit(cs, va >> 32);
1881
1882 for (uint32_t l = 0; l < level_count; l++) {
1883 radeon_emit(cs, color_values[0]);
1884 radeon_emit(cs, color_values[1]);
1885 }
1886 }
1887
1888 /**
1889 * Update the clear color values for this image.
1890 */
1891 void
1892 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1893 const struct radv_image_view *iview,
1894 int cb_idx,
1895 uint32_t color_values[2])
1896 {
1897 struct radv_image *image = iview->image;
1898 VkImageSubresourceRange range = {
1899 .aspectMask = iview->aspect_mask,
1900 .baseMipLevel = iview->base_mip,
1901 .levelCount = iview->level_count,
1902 .baseArrayLayer = iview->base_layer,
1903 .layerCount = iview->layer_count,
1904 };
1905
1906 assert(radv_image_has_cmask(image) ||
1907 radv_dcc_enabled(image, iview->base_mip));
1908
1909 radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
1910
1911 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1912 color_values);
1913 }
1914
1915 /**
1916 * Load the clear color values from the image's metadata.
1917 */
1918 static void
1919 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1920 struct radv_image_view *iview,
1921 int cb_idx)
1922 {
1923 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1924 struct radv_image *image = iview->image;
1925 uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
1926
1927 if (!radv_image_has_cmask(image) &&
1928 !radv_dcc_enabled(image, iview->base_mip))
1929 return;
1930
1931 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1932
1933 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
1934 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1935 radeon_emit(cs, va);
1936 radeon_emit(cs, va >> 32);
1937 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1938 radeon_emit(cs, 2);
1939 } else {
1940 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1941 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1942 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1943 COPY_DATA_COUNT_SEL);
1944 radeon_emit(cs, va);
1945 radeon_emit(cs, va >> 32);
1946 radeon_emit(cs, reg >> 2);
1947 radeon_emit(cs, 0);
1948
1949 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1950 radeon_emit(cs, 0);
1951 }
1952 }
1953
1954 static void
1955 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1956 {
1957 int i;
1958 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1959 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1960
1961 /* this may happen for inherited secondary recording */
1962 if (!framebuffer)
1963 return;
1964
1965 for (i = 0; i < 8; ++i) {
1966 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1967 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1968 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1969 continue;
1970 }
1971
1972 int idx = subpass->color_attachments[i].attachment;
1973 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
1974 VkImageLayout layout = subpass->color_attachments[i].layout;
1975 bool in_render_loop = subpass->color_attachments[i].in_render_loop;
1976
1977 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, iview->bo);
1978
1979 assert(iview->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
1980 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
1981 radv_emit_fb_color_state(cmd_buffer, i, &cmd_buffer->state.attachments[idx].cb, iview, layout, in_render_loop);
1982
1983 radv_load_color_clear_metadata(cmd_buffer, iview, i);
1984 }
1985
1986 if (subpass->depth_stencil_attachment) {
1987 int idx = subpass->depth_stencil_attachment->attachment;
1988 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1989 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
1990 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
1991 struct radv_image *image = iview->image;
1992 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, cmd_buffer->state.attachments[idx].iview->bo);
1993 ASSERTED uint32_t queue_mask = radv_image_queue_family_mask(image,
1994 cmd_buffer->queue_family_index,
1995 cmd_buffer->queue_family_index);
1996 /* We currently don't support writing decompressed HTILE */
1997 assert(radv_layout_has_htile(image, layout, in_render_loop, queue_mask) ==
1998 radv_layout_is_htile_compressed(image, layout, in_render_loop, queue_mask));
1999
2000 radv_emit_fb_ds_state(cmd_buffer, &cmd_buffer->state.attachments[idx].ds, iview, layout, in_render_loop);
2001
2002 if (cmd_buffer->state.attachments[idx].ds.offset_scale != cmd_buffer->state.offset_scale) {
2003 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2004 cmd_buffer->state.offset_scale = cmd_buffer->state.attachments[idx].ds.offset_scale;
2005 }
2006 radv_load_ds_clear_metadata(cmd_buffer, iview);
2007 } else {
2008 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9)
2009 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
2010 else
2011 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
2012
2013 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
2014 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
2015 }
2016 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2017 S_028208_BR_X(framebuffer->width) |
2018 S_028208_BR_Y(framebuffer->height));
2019
2020 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
2021 bool disable_constant_encode =
2022 cmd_buffer->device->physical_device->rad_info.has_dcc_constant_encode;
2023 enum chip_class chip_class =
2024 cmd_buffer->device->physical_device->rad_info.chip_class;
2025 uint8_t watermark = chip_class >= GFX10 ? 6 : 4;
2026
2027 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
2028 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class <= GFX9) |
2029 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
2030 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
2031 }
2032
2033 if (cmd_buffer->device->dfsm_allowed) {
2034 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2035 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
2036 }
2037
2038 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
2039 }
2040
2041 static void
2042 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
2043 {
2044 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2045 struct radv_cmd_state *state = &cmd_buffer->state;
2046
2047 if (state->index_type != state->last_index_type) {
2048 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2049 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2050 cs, R_03090C_VGT_INDEX_TYPE,
2051 2, state->index_type);
2052 } else {
2053 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2054 radeon_emit(cs, state->index_type);
2055 }
2056
2057 state->last_index_type = state->index_type;
2058 }
2059
2060 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2061 radeon_emit(cs, state->index_va);
2062 radeon_emit(cs, state->index_va >> 32);
2063
2064 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2065 radeon_emit(cs, state->max_index_count);
2066
2067 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
2068 }
2069
2070 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
2071 {
2072 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
2073 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2074 uint32_t pa_sc_mode_cntl_1 =
2075 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
2076 uint32_t db_count_control;
2077
2078 if(!cmd_buffer->state.active_occlusion_queries) {
2079 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2080 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2081 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2082 has_perfect_queries) {
2083 /* Re-enable out-of-order rasterization if the
2084 * bound pipeline supports it and if it's has
2085 * been disabled before starting any perfect
2086 * occlusion queries.
2087 */
2088 radeon_set_context_reg(cmd_buffer->cs,
2089 R_028A4C_PA_SC_MODE_CNTL_1,
2090 pa_sc_mode_cntl_1);
2091 }
2092 }
2093 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
2094 } else {
2095 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2096 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
2097 bool gfx10_perfect = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10 && has_perfect_queries;
2098
2099 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2100 db_count_control =
2101 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
2102 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
2103 S_028004_SAMPLE_RATE(sample_rate) |
2104 S_028004_ZPASS_ENABLE(1) |
2105 S_028004_SLICE_EVEN_ENABLE(1) |
2106 S_028004_SLICE_ODD_ENABLE(1);
2107
2108 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2109 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2110 has_perfect_queries) {
2111 /* If the bound pipeline has enabled
2112 * out-of-order rasterization, we should
2113 * disable it before starting any perfect
2114 * occlusion queries.
2115 */
2116 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
2117
2118 radeon_set_context_reg(cmd_buffer->cs,
2119 R_028A4C_PA_SC_MODE_CNTL_1,
2120 pa_sc_mode_cntl_1);
2121 }
2122 } else {
2123 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
2124 S_028004_SAMPLE_RATE(sample_rate);
2125 }
2126 }
2127
2128 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
2129
2130 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2131 }
2132
2133 static void
2134 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
2135 {
2136 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
2137
2138 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
2139 radv_emit_viewport(cmd_buffer);
2140
2141 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
2142 !cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
2143 radv_emit_scissor(cmd_buffer);
2144
2145 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
2146 radv_emit_line_width(cmd_buffer);
2147
2148 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
2149 radv_emit_blend_constants(cmd_buffer);
2150
2151 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
2152 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
2153 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
2154 radv_emit_stencil(cmd_buffer);
2155
2156 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
2157 radv_emit_depth_bounds(cmd_buffer);
2158
2159 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
2160 radv_emit_depth_bias(cmd_buffer);
2161
2162 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
2163 radv_emit_discard_rectangle(cmd_buffer);
2164
2165 if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)
2166 radv_emit_sample_locations(cmd_buffer);
2167
2168 cmd_buffer->state.dirty &= ~states;
2169 }
2170
2171 static void
2172 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
2173 VkPipelineBindPoint bind_point)
2174 {
2175 struct radv_descriptor_state *descriptors_state =
2176 radv_get_descriptors_state(cmd_buffer, bind_point);
2177 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
2178 unsigned bo_offset;
2179
2180 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
2181 set->mapped_ptr,
2182 &bo_offset))
2183 return;
2184
2185 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2186 set->va += bo_offset;
2187 }
2188
2189 static void
2190 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
2191 VkPipelineBindPoint bind_point)
2192 {
2193 struct radv_descriptor_state *descriptors_state =
2194 radv_get_descriptors_state(cmd_buffer, bind_point);
2195 uint32_t size = MAX_SETS * 4;
2196 uint32_t offset;
2197 void *ptr;
2198
2199 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
2200 256, &offset, &ptr))
2201 return;
2202
2203 for (unsigned i = 0; i < MAX_SETS; i++) {
2204 uint32_t *uptr = ((uint32_t *)ptr) + i;
2205 uint64_t set_va = 0;
2206 struct radv_descriptor_set *set = descriptors_state->sets[i];
2207 if (descriptors_state->valid & (1u << i))
2208 set_va = set->va;
2209 uptr[0] = set_va & 0xffffffff;
2210 }
2211
2212 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2213 va += offset;
2214
2215 if (cmd_buffer->state.pipeline) {
2216 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
2217 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2218 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2219
2220 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
2221 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
2222 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2223
2224 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
2225 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2226 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2227
2228 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2229 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
2230 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2231
2232 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2233 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
2234 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2235 }
2236
2237 if (cmd_buffer->state.compute_pipeline)
2238 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
2239 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2240 }
2241
2242 static void
2243 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
2244 VkShaderStageFlags stages)
2245 {
2246 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2247 VK_PIPELINE_BIND_POINT_COMPUTE :
2248 VK_PIPELINE_BIND_POINT_GRAPHICS;
2249 struct radv_descriptor_state *descriptors_state =
2250 radv_get_descriptors_state(cmd_buffer, bind_point);
2251 struct radv_cmd_state *state = &cmd_buffer->state;
2252 bool flush_indirect_descriptors;
2253
2254 if (!descriptors_state->dirty)
2255 return;
2256
2257 if (descriptors_state->push_dirty)
2258 radv_flush_push_descriptors(cmd_buffer, bind_point);
2259
2260 flush_indirect_descriptors =
2261 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
2262 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
2263 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
2264 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
2265
2266 if (flush_indirect_descriptors)
2267 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
2268
2269 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2270 cmd_buffer->cs,
2271 MAX_SETS * MESA_SHADER_STAGES * 4);
2272
2273 if (cmd_buffer->state.pipeline) {
2274 radv_foreach_stage(stage, stages) {
2275 if (!cmd_buffer->state.pipeline->shaders[stage])
2276 continue;
2277
2278 radv_emit_descriptor_pointers(cmd_buffer,
2279 cmd_buffer->state.pipeline,
2280 descriptors_state, stage);
2281 }
2282 }
2283
2284 if (cmd_buffer->state.compute_pipeline &&
2285 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
2286 radv_emit_descriptor_pointers(cmd_buffer,
2287 cmd_buffer->state.compute_pipeline,
2288 descriptors_state,
2289 MESA_SHADER_COMPUTE);
2290 }
2291
2292 descriptors_state->dirty = 0;
2293 descriptors_state->push_dirty = false;
2294
2295 assert(cmd_buffer->cs->cdw <= cdw_max);
2296
2297 if (unlikely(cmd_buffer->device->trace_bo))
2298 radv_save_descriptors(cmd_buffer, bind_point);
2299 }
2300
2301 static void
2302 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
2303 VkShaderStageFlags stages)
2304 {
2305 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
2306 ? cmd_buffer->state.compute_pipeline
2307 : cmd_buffer->state.pipeline;
2308 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2309 VK_PIPELINE_BIND_POINT_COMPUTE :
2310 VK_PIPELINE_BIND_POINT_GRAPHICS;
2311 struct radv_descriptor_state *descriptors_state =
2312 radv_get_descriptors_state(cmd_buffer, bind_point);
2313 struct radv_pipeline_layout *layout = pipeline->layout;
2314 struct radv_shader_variant *shader, *prev_shader;
2315 bool need_push_constants = false;
2316 unsigned offset;
2317 void *ptr;
2318 uint64_t va;
2319
2320 stages &= cmd_buffer->push_constant_stages;
2321 if (!stages ||
2322 (!layout->push_constant_size && !layout->dynamic_offset_count))
2323 return;
2324
2325 radv_foreach_stage(stage, stages) {
2326 shader = radv_get_shader(pipeline, stage);
2327 if (!shader)
2328 continue;
2329
2330 need_push_constants |= shader->info.loads_push_constants;
2331 need_push_constants |= shader->info.loads_dynamic_offsets;
2332
2333 uint8_t base = shader->info.base_inline_push_consts;
2334 uint8_t count = shader->info.num_inline_push_consts;
2335
2336 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
2337 AC_UD_INLINE_PUSH_CONSTANTS,
2338 count,
2339 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
2340 }
2341
2342 if (need_push_constants) {
2343 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
2344 16 * layout->dynamic_offset_count,
2345 256, &offset, &ptr))
2346 return;
2347
2348 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
2349 memcpy((char*)ptr + layout->push_constant_size,
2350 descriptors_state->dynamic_buffers,
2351 16 * layout->dynamic_offset_count);
2352
2353 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2354 va += offset;
2355
2356 ASSERTED unsigned cdw_max =
2357 radeon_check_space(cmd_buffer->device->ws,
2358 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
2359
2360 prev_shader = NULL;
2361 radv_foreach_stage(stage, stages) {
2362 shader = radv_get_shader(pipeline, stage);
2363
2364 /* Avoid redundantly emitting the address for merged stages. */
2365 if (shader && shader != prev_shader) {
2366 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
2367 AC_UD_PUSH_CONSTANTS, va);
2368
2369 prev_shader = shader;
2370 }
2371 }
2372 assert(cmd_buffer->cs->cdw <= cdw_max);
2373 }
2374
2375 cmd_buffer->push_constant_stages &= ~stages;
2376 }
2377
2378 static void
2379 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
2380 bool pipeline_is_dirty)
2381 {
2382 if ((pipeline_is_dirty ||
2383 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
2384 cmd_buffer->state.pipeline->num_vertex_bindings &&
2385 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.has_vertex_buffers) {
2386 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
2387 unsigned vb_offset;
2388 void *vb_ptr;
2389 uint32_t i = 0;
2390 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
2391 uint64_t va;
2392
2393 /* allocate some descriptor state for vertex buffers */
2394 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2395 &vb_offset, &vb_ptr))
2396 return;
2397
2398 for (i = 0; i < count; i++) {
2399 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2400 uint32_t offset;
2401 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2402 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[i];
2403
2404 if (!buffer)
2405 continue;
2406
2407 va = radv_buffer_get_va(buffer->bo);
2408
2409 offset = cmd_buffer->vertex_bindings[i].offset;
2410 va += offset + buffer->offset;
2411 desc[0] = va;
2412 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2413 if (cmd_buffer->device->physical_device->rad_info.chip_class <= GFX7 && stride)
2414 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
2415 else
2416 desc[2] = buffer->size - offset;
2417 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2418 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2419 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2420 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2421
2422 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2423 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT) |
2424 S_008F0C_OOB_SELECT(1) |
2425 S_008F0C_RESOURCE_LEVEL(1);
2426 } else {
2427 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2428 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2429 }
2430 }
2431
2432 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2433 va += vb_offset;
2434
2435 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2436 AC_UD_VS_VERTEX_BUFFERS, va);
2437
2438 cmd_buffer->state.vb_va = va;
2439 cmd_buffer->state.vb_size = count * 16;
2440 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2441 }
2442 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2443 }
2444
2445 static void
2446 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2447 {
2448 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2449 struct radv_userdata_info *loc;
2450 uint32_t base_reg;
2451
2452 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2453 if (!radv_get_shader(pipeline, stage))
2454 continue;
2455
2456 loc = radv_lookup_user_sgpr(pipeline, stage,
2457 AC_UD_STREAMOUT_BUFFERS);
2458 if (loc->sgpr_idx == -1)
2459 continue;
2460
2461 base_reg = pipeline->user_data_0[stage];
2462
2463 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2464 base_reg + loc->sgpr_idx * 4, va, false);
2465 }
2466
2467 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
2468 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2469 if (loc->sgpr_idx != -1) {
2470 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2471
2472 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2473 base_reg + loc->sgpr_idx * 4, va, false);
2474 }
2475 }
2476 }
2477
2478 static void
2479 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2480 {
2481 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2482 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2483 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2484 unsigned so_offset;
2485 void *so_ptr;
2486 uint64_t va;
2487
2488 /* Allocate some descriptor state for streamout buffers. */
2489 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2490 MAX_SO_BUFFERS * 16, 256,
2491 &so_offset, &so_ptr))
2492 return;
2493
2494 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2495 struct radv_buffer *buffer = sb[i].buffer;
2496 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2497
2498 if (!(so->enabled_mask & (1 << i)))
2499 continue;
2500
2501 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2502
2503 va += sb[i].offset;
2504
2505 /* Set the descriptor.
2506 *
2507 * On GFX8, the format must be non-INVALID, otherwise
2508 * the buffer will be considered not bound and store
2509 * instructions will be no-ops.
2510 */
2511 uint32_t size = 0xffffffff;
2512
2513 /* Compute the correct buffer size for NGG streamout
2514 * because it's used to determine the max emit per
2515 * buffer.
2516 */
2517 if (cmd_buffer->device->physical_device->use_ngg_streamout)
2518 size = buffer->size - sb[i].offset;
2519
2520 desc[0] = va;
2521 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2522 desc[2] = size;
2523 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2524 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2525 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2526 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2527
2528 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2529 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2530 S_008F0C_OOB_SELECT(3) |
2531 S_008F0C_RESOURCE_LEVEL(1);
2532 } else {
2533 desc[3] |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2534 }
2535 }
2536
2537 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2538 va += so_offset;
2539
2540 radv_emit_streamout_buffers(cmd_buffer, va);
2541 }
2542
2543 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2544 }
2545
2546 static void
2547 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2548 {
2549 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2550 radv_flush_streamout_descriptors(cmd_buffer);
2551 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2552 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2553 }
2554
2555 struct radv_draw_info {
2556 /**
2557 * Number of vertices.
2558 */
2559 uint32_t count;
2560
2561 /**
2562 * Index of the first vertex.
2563 */
2564 int32_t vertex_offset;
2565
2566 /**
2567 * First instance id.
2568 */
2569 uint32_t first_instance;
2570
2571 /**
2572 * Number of instances.
2573 */
2574 uint32_t instance_count;
2575
2576 /**
2577 * First index (indexed draws only).
2578 */
2579 uint32_t first_index;
2580
2581 /**
2582 * Whether it's an indexed draw.
2583 */
2584 bool indexed;
2585
2586 /**
2587 * Indirect draw parameters resource.
2588 */
2589 struct radv_buffer *indirect;
2590 uint64_t indirect_offset;
2591 uint32_t stride;
2592
2593 /**
2594 * Draw count parameters resource.
2595 */
2596 struct radv_buffer *count_buffer;
2597 uint64_t count_buffer_offset;
2598
2599 /**
2600 * Stream output parameters resource.
2601 */
2602 struct radv_buffer *strmout_buffer;
2603 uint64_t strmout_buffer_offset;
2604 };
2605
2606 static uint32_t
2607 radv_get_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
2608 {
2609 switch (cmd_buffer->state.index_type) {
2610 case V_028A7C_VGT_INDEX_8:
2611 return 0xffu;
2612 case V_028A7C_VGT_INDEX_16:
2613 return 0xffffu;
2614 case V_028A7C_VGT_INDEX_32:
2615 return 0xffffffffu;
2616 default:
2617 unreachable("invalid index type");
2618 }
2619 }
2620
2621 static void
2622 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
2623 bool instanced_draw, bool indirect_draw,
2624 bool count_from_stream_output,
2625 uint32_t draw_vertex_count)
2626 {
2627 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2628 struct radv_cmd_state *state = &cmd_buffer->state;
2629 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2630 unsigned ia_multi_vgt_param;
2631
2632 ia_multi_vgt_param =
2633 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
2634 indirect_draw,
2635 count_from_stream_output,
2636 draw_vertex_count);
2637
2638 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2639 if (info->chip_class == GFX9) {
2640 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2641 cs,
2642 R_030960_IA_MULTI_VGT_PARAM,
2643 4, ia_multi_vgt_param);
2644 } else if (info->chip_class >= GFX7) {
2645 radeon_set_context_reg_idx(cs,
2646 R_028AA8_IA_MULTI_VGT_PARAM,
2647 1, ia_multi_vgt_param);
2648 } else {
2649 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2650 ia_multi_vgt_param);
2651 }
2652 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2653 }
2654 }
2655
2656 static void
2657 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2658 const struct radv_draw_info *draw_info)
2659 {
2660 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2661 struct radv_cmd_state *state = &cmd_buffer->state;
2662 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2663 int32_t primitive_reset_en;
2664
2665 /* Draw state. */
2666 if (info->chip_class < GFX10) {
2667 si_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2668 draw_info->indirect,
2669 !!draw_info->strmout_buffer,
2670 draw_info->indirect ? 0 : draw_info->count);
2671 }
2672
2673 /* Primitive restart. */
2674 primitive_reset_en =
2675 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2676
2677 if (primitive_reset_en != state->last_primitive_reset_en) {
2678 state->last_primitive_reset_en = primitive_reset_en;
2679 if (info->chip_class >= GFX9) {
2680 radeon_set_uconfig_reg(cs,
2681 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2682 primitive_reset_en);
2683 } else {
2684 radeon_set_context_reg(cs,
2685 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2686 primitive_reset_en);
2687 }
2688 }
2689
2690 if (primitive_reset_en) {
2691 uint32_t primitive_reset_index =
2692 radv_get_primitive_reset_index(cmd_buffer);
2693
2694 if (primitive_reset_index != state->last_primitive_reset_index) {
2695 radeon_set_context_reg(cs,
2696 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2697 primitive_reset_index);
2698 state->last_primitive_reset_index = primitive_reset_index;
2699 }
2700 }
2701
2702 if (draw_info->strmout_buffer) {
2703 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2704
2705 va += draw_info->strmout_buffer->offset +
2706 draw_info->strmout_buffer_offset;
2707
2708 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2709 draw_info->stride);
2710
2711 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2712 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2713 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2714 COPY_DATA_WR_CONFIRM);
2715 radeon_emit(cs, va);
2716 radeon_emit(cs, va >> 32);
2717 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2718 radeon_emit(cs, 0); /* unused */
2719
2720 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2721 }
2722 }
2723
2724 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2725 VkPipelineStageFlags src_stage_mask)
2726 {
2727 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2728 VK_PIPELINE_STAGE_TRANSFER_BIT |
2729 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2730 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2731 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2732 }
2733
2734 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2735 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2736 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2737 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2738 VK_PIPELINE_STAGE_TRANSFER_BIT |
2739 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2740 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2741 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2742 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2743 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2744 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2745 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2746 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2747 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2748 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2749 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2750 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2751 }
2752 }
2753
2754 static enum radv_cmd_flush_bits
2755 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2756 VkAccessFlags src_flags,
2757 struct radv_image *image)
2758 {
2759 bool flush_CB_meta = true, flush_DB_meta = true;
2760 enum radv_cmd_flush_bits flush_bits = 0;
2761 uint32_t b;
2762
2763 if (image) {
2764 if (!radv_image_has_CB_metadata(image))
2765 flush_CB_meta = false;
2766 if (!radv_image_has_htile(image))
2767 flush_DB_meta = false;
2768 }
2769
2770 for_each_bit(b, src_flags) {
2771 switch ((VkAccessFlagBits)(1 << b)) {
2772 case VK_ACCESS_SHADER_WRITE_BIT:
2773 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2774 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2775 flush_bits |= RADV_CMD_FLAG_WB_L2;
2776 break;
2777 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2778 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2779 if (flush_CB_meta)
2780 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2781 break;
2782 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2783 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2784 if (flush_DB_meta)
2785 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2786 break;
2787 case VK_ACCESS_TRANSFER_WRITE_BIT:
2788 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2789 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2790 RADV_CMD_FLAG_INV_L2;
2791
2792 if (flush_CB_meta)
2793 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2794 if (flush_DB_meta)
2795 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2796 break;
2797 default:
2798 break;
2799 }
2800 }
2801 return flush_bits;
2802 }
2803
2804 static enum radv_cmd_flush_bits
2805 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2806 VkAccessFlags dst_flags,
2807 struct radv_image *image)
2808 {
2809 bool flush_CB_meta = true, flush_DB_meta = true;
2810 enum radv_cmd_flush_bits flush_bits = 0;
2811 bool flush_CB = true, flush_DB = true;
2812 bool image_is_coherent = false;
2813 uint32_t b;
2814
2815 if (image) {
2816 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2817 flush_CB = false;
2818 flush_DB = false;
2819 }
2820
2821 if (!radv_image_has_CB_metadata(image))
2822 flush_CB_meta = false;
2823 if (!radv_image_has_htile(image))
2824 flush_DB_meta = false;
2825
2826 /* TODO: implement shader coherent for GFX10 */
2827
2828 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
2829 if (image->info.samples == 1 &&
2830 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2831 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2832 !vk_format_is_stencil(image->vk_format)) {
2833 /* Single-sample color and single-sample depth
2834 * (not stencil) are coherent with shaders on
2835 * GFX9.
2836 */
2837 image_is_coherent = true;
2838 }
2839 }
2840 }
2841
2842 for_each_bit(b, dst_flags) {
2843 switch ((VkAccessFlagBits)(1 << b)) {
2844 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2845 case VK_ACCESS_INDEX_READ_BIT:
2846 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2847 break;
2848 case VK_ACCESS_UNIFORM_READ_BIT:
2849 flush_bits |= RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_SCACHE;
2850 break;
2851 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2852 case VK_ACCESS_TRANSFER_READ_BIT:
2853 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2854 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
2855 RADV_CMD_FLAG_INV_L2;
2856 break;
2857 case VK_ACCESS_SHADER_READ_BIT:
2858 flush_bits |= RADV_CMD_FLAG_INV_VCACHE;
2859 /* Unlike LLVM, ACO uses SMEM for SSBOs and we have to
2860 * invalidate the scalar cache. */
2861 if (cmd_buffer->device->physical_device->use_aco)
2862 flush_bits |= RADV_CMD_FLAG_INV_SCACHE;
2863
2864 if (!image_is_coherent)
2865 flush_bits |= RADV_CMD_FLAG_INV_L2;
2866 break;
2867 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2868 if (flush_CB)
2869 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2870 if (flush_CB_meta)
2871 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2872 break;
2873 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2874 if (flush_DB)
2875 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2876 if (flush_DB_meta)
2877 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2878 break;
2879 default:
2880 break;
2881 }
2882 }
2883 return flush_bits;
2884 }
2885
2886 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2887 const struct radv_subpass_barrier *barrier)
2888 {
2889 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2890 NULL);
2891 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2892 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2893 NULL);
2894 }
2895
2896 uint32_t
2897 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
2898 {
2899 struct radv_cmd_state *state = &cmd_buffer->state;
2900 uint32_t subpass_id = state->subpass - state->pass->subpasses;
2901
2902 /* The id of this subpass shouldn't exceed the number of subpasses in
2903 * this render pass minus 1.
2904 */
2905 assert(subpass_id < state->pass->subpass_count);
2906 return subpass_id;
2907 }
2908
2909 static struct radv_sample_locations_state *
2910 radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer,
2911 uint32_t att_idx,
2912 bool begin_subpass)
2913 {
2914 struct radv_cmd_state *state = &cmd_buffer->state;
2915 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
2916 struct radv_image_view *view = state->attachments[att_idx].iview;
2917
2918 if (view->image->info.samples == 1)
2919 return NULL;
2920
2921 if (state->pass->attachments[att_idx].first_subpass_idx == subpass_id) {
2922 /* Return the initial sample locations if this is the initial
2923 * layout transition of the given subpass attachemnt.
2924 */
2925 if (state->attachments[att_idx].sample_location.count > 0)
2926 return &state->attachments[att_idx].sample_location;
2927 } else {
2928 /* Otherwise return the subpass sample locations if defined. */
2929 if (state->subpass_sample_locs) {
2930 /* Because the driver sets the current subpass before
2931 * initial layout transitions, we should use the sample
2932 * locations from the previous subpass to avoid an
2933 * off-by-one problem. Otherwise, use the sample
2934 * locations for the current subpass for final layout
2935 * transitions.
2936 */
2937 if (begin_subpass)
2938 subpass_id--;
2939
2940 for (uint32_t i = 0; i < state->num_subpass_sample_locs; i++) {
2941 if (state->subpass_sample_locs[i].subpass_idx == subpass_id)
2942 return &state->subpass_sample_locs[i].sample_location;
2943 }
2944 }
2945 }
2946
2947 return NULL;
2948 }
2949
2950 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2951 struct radv_subpass_attachment att,
2952 bool begin_subpass)
2953 {
2954 unsigned idx = att.attachment;
2955 struct radv_image_view *view = cmd_buffer->state.attachments[idx].iview;
2956 struct radv_sample_locations_state *sample_locs;
2957 VkImageSubresourceRange range;
2958 range.aspectMask = 0;
2959 range.baseMipLevel = view->base_mip;
2960 range.levelCount = 1;
2961 range.baseArrayLayer = view->base_layer;
2962 range.layerCount = cmd_buffer->state.framebuffer->layers;
2963
2964 if (cmd_buffer->state.subpass->view_mask) {
2965 /* If the current subpass uses multiview, the driver might have
2966 * performed a fast color/depth clear to the whole image
2967 * (including all layers). To make sure the driver will
2968 * decompress the image correctly (if needed), we have to
2969 * account for the "real" number of layers. If the view mask is
2970 * sparse, this will decompress more layers than needed.
2971 */
2972 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
2973 }
2974
2975 /* Get the subpass sample locations for the given attachment, if NULL
2976 * is returned the driver will use the default HW locations.
2977 */
2978 sample_locs = radv_get_attachment_sample_locations(cmd_buffer, idx,
2979 begin_subpass);
2980
2981 radv_handle_image_transition(cmd_buffer,
2982 view->image,
2983 cmd_buffer->state.attachments[idx].current_layout,
2984 cmd_buffer->state.attachments[idx].current_in_render_loop,
2985 att.layout, att.in_render_loop,
2986 0, 0, &range, sample_locs);
2987
2988 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2989 cmd_buffer->state.attachments[idx].current_in_render_loop = att.in_render_loop;
2990
2991
2992 }
2993
2994 void
2995 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2996 const struct radv_subpass *subpass)
2997 {
2998 cmd_buffer->state.subpass = subpass;
2999
3000 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
3001 }
3002
3003 static VkResult
3004 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
3005 struct radv_render_pass *pass,
3006 const VkRenderPassBeginInfo *info)
3007 {
3008 const struct VkRenderPassSampleLocationsBeginInfoEXT *sample_locs =
3009 vk_find_struct_const(info->pNext,
3010 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT);
3011 struct radv_cmd_state *state = &cmd_buffer->state;
3012
3013 if (!sample_locs) {
3014 state->subpass_sample_locs = NULL;
3015 return VK_SUCCESS;
3016 }
3017
3018 for (uint32_t i = 0; i < sample_locs->attachmentInitialSampleLocationsCount; i++) {
3019 const VkAttachmentSampleLocationsEXT *att_sample_locs =
3020 &sample_locs->pAttachmentInitialSampleLocations[i];
3021 uint32_t att_idx = att_sample_locs->attachmentIndex;
3022 struct radv_image *image = cmd_buffer->state.attachments[att_idx].iview->image;
3023
3024 assert(vk_format_is_depth_or_stencil(image->vk_format));
3025
3026 /* From the Vulkan spec 1.1.108:
3027 *
3028 * "If the image referenced by the framebuffer attachment at
3029 * index attachmentIndex was not created with
3030 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
3031 * then the values specified in sampleLocationsInfo are
3032 * ignored."
3033 */
3034 if (!(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT))
3035 continue;
3036
3037 const VkSampleLocationsInfoEXT *sample_locs_info =
3038 &att_sample_locs->sampleLocationsInfo;
3039
3040 state->attachments[att_idx].sample_location.per_pixel =
3041 sample_locs_info->sampleLocationsPerPixel;
3042 state->attachments[att_idx].sample_location.grid_size =
3043 sample_locs_info->sampleLocationGridSize;
3044 state->attachments[att_idx].sample_location.count =
3045 sample_locs_info->sampleLocationsCount;
3046 typed_memcpy(&state->attachments[att_idx].sample_location.locations[0],
3047 sample_locs_info->pSampleLocations,
3048 sample_locs_info->sampleLocationsCount);
3049 }
3050
3051 state->subpass_sample_locs = vk_alloc(&cmd_buffer->pool->alloc,
3052 sample_locs->postSubpassSampleLocationsCount *
3053 sizeof(state->subpass_sample_locs[0]),
3054 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3055 if (state->subpass_sample_locs == NULL) {
3056 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3057 return cmd_buffer->record_result;
3058 }
3059
3060 state->num_subpass_sample_locs = sample_locs->postSubpassSampleLocationsCount;
3061
3062 for (uint32_t i = 0; i < sample_locs->postSubpassSampleLocationsCount; i++) {
3063 const VkSubpassSampleLocationsEXT *subpass_sample_locs_info =
3064 &sample_locs->pPostSubpassSampleLocations[i];
3065 const VkSampleLocationsInfoEXT *sample_locs_info =
3066 &subpass_sample_locs_info->sampleLocationsInfo;
3067
3068 state->subpass_sample_locs[i].subpass_idx =
3069 subpass_sample_locs_info->subpassIndex;
3070 state->subpass_sample_locs[i].sample_location.per_pixel =
3071 sample_locs_info->sampleLocationsPerPixel;
3072 state->subpass_sample_locs[i].sample_location.grid_size =
3073 sample_locs_info->sampleLocationGridSize;
3074 state->subpass_sample_locs[i].sample_location.count =
3075 sample_locs_info->sampleLocationsCount;
3076 typed_memcpy(&state->subpass_sample_locs[i].sample_location.locations[0],
3077 sample_locs_info->pSampleLocations,
3078 sample_locs_info->sampleLocationsCount);
3079 }
3080
3081 return VK_SUCCESS;
3082 }
3083
3084 static VkResult
3085 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
3086 struct radv_render_pass *pass,
3087 const VkRenderPassBeginInfo *info)
3088 {
3089 struct radv_cmd_state *state = &cmd_buffer->state;
3090 const struct VkRenderPassAttachmentBeginInfoKHR *attachment_info = NULL;
3091
3092 if (info) {
3093 attachment_info = vk_find_struct_const(info->pNext,
3094 RENDER_PASS_ATTACHMENT_BEGIN_INFO_KHR);
3095 }
3096
3097
3098 if (pass->attachment_count == 0) {
3099 state->attachments = NULL;
3100 return VK_SUCCESS;
3101 }
3102
3103 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
3104 pass->attachment_count *
3105 sizeof(state->attachments[0]),
3106 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3107 if (state->attachments == NULL) {
3108 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3109 return cmd_buffer->record_result;
3110 }
3111
3112 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
3113 struct radv_render_pass_attachment *att = &pass->attachments[i];
3114 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
3115 VkImageAspectFlags clear_aspects = 0;
3116
3117 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
3118 /* color attachment */
3119 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3120 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
3121 }
3122 } else {
3123 /* depthstencil attachment */
3124 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
3125 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3126 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
3127 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3128 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
3129 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3130 }
3131 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3132 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3133 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3134 }
3135 }
3136
3137 state->attachments[i].pending_clear_aspects = clear_aspects;
3138 state->attachments[i].cleared_views = 0;
3139 if (clear_aspects && info) {
3140 assert(info->clearValueCount > i);
3141 state->attachments[i].clear_value = info->pClearValues[i];
3142 }
3143
3144 state->attachments[i].current_layout = att->initial_layout;
3145 state->attachments[i].sample_location.count = 0;
3146
3147 struct radv_image_view *iview;
3148 if (attachment_info && attachment_info->attachmentCount > i) {
3149 iview = radv_image_view_from_handle(attachment_info->pAttachments[i]);
3150 } else {
3151 iview = state->framebuffer->attachments[i];
3152 }
3153
3154 state->attachments[i].iview = iview;
3155 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3156 radv_initialise_ds_surface(cmd_buffer->device, &state->attachments[i].ds, iview);
3157 } else {
3158 radv_initialise_color_surface(cmd_buffer->device, &state->attachments[i].cb, iview);
3159 }
3160 }
3161
3162 return VK_SUCCESS;
3163 }
3164
3165 VkResult radv_AllocateCommandBuffers(
3166 VkDevice _device,
3167 const VkCommandBufferAllocateInfo *pAllocateInfo,
3168 VkCommandBuffer *pCommandBuffers)
3169 {
3170 RADV_FROM_HANDLE(radv_device, device, _device);
3171 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
3172
3173 VkResult result = VK_SUCCESS;
3174 uint32_t i;
3175
3176 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
3177
3178 if (!list_empty(&pool->free_cmd_buffers)) {
3179 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
3180
3181 list_del(&cmd_buffer->pool_link);
3182 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
3183
3184 result = radv_reset_cmd_buffer(cmd_buffer);
3185 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
3186 cmd_buffer->level = pAllocateInfo->level;
3187
3188 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
3189 } else {
3190 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
3191 &pCommandBuffers[i]);
3192 }
3193 if (result != VK_SUCCESS)
3194 break;
3195 }
3196
3197 if (result != VK_SUCCESS) {
3198 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
3199 i, pCommandBuffers);
3200
3201 /* From the Vulkan 1.0.66 spec:
3202 *
3203 * "vkAllocateCommandBuffers can be used to create multiple
3204 * command buffers. If the creation of any of those command
3205 * buffers fails, the implementation must destroy all
3206 * successfully created command buffer objects from this
3207 * command, set all entries of the pCommandBuffers array to
3208 * NULL and return the error."
3209 */
3210 memset(pCommandBuffers, 0,
3211 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
3212 }
3213
3214 return result;
3215 }
3216
3217 void radv_FreeCommandBuffers(
3218 VkDevice device,
3219 VkCommandPool commandPool,
3220 uint32_t commandBufferCount,
3221 const VkCommandBuffer *pCommandBuffers)
3222 {
3223 for (uint32_t i = 0; i < commandBufferCount; i++) {
3224 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
3225
3226 if (cmd_buffer) {
3227 if (cmd_buffer->pool) {
3228 list_del(&cmd_buffer->pool_link);
3229 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
3230 } else
3231 radv_cmd_buffer_destroy(cmd_buffer);
3232
3233 }
3234 }
3235 }
3236
3237 VkResult radv_ResetCommandBuffer(
3238 VkCommandBuffer commandBuffer,
3239 VkCommandBufferResetFlags flags)
3240 {
3241 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3242 return radv_reset_cmd_buffer(cmd_buffer);
3243 }
3244
3245 VkResult radv_BeginCommandBuffer(
3246 VkCommandBuffer commandBuffer,
3247 const VkCommandBufferBeginInfo *pBeginInfo)
3248 {
3249 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3250 VkResult result = VK_SUCCESS;
3251
3252 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
3253 /* If the command buffer has already been resetted with
3254 * vkResetCommandBuffer, no need to do it again.
3255 */
3256 result = radv_reset_cmd_buffer(cmd_buffer);
3257 if (result != VK_SUCCESS)
3258 return result;
3259 }
3260
3261 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
3262 cmd_buffer->state.last_primitive_reset_en = -1;
3263 cmd_buffer->state.last_index_type = -1;
3264 cmd_buffer->state.last_num_instances = -1;
3265 cmd_buffer->state.last_vertex_offset = -1;
3266 cmd_buffer->state.last_first_instance = -1;
3267 cmd_buffer->state.predication_type = -1;
3268 cmd_buffer->usage_flags = pBeginInfo->flags;
3269
3270 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
3271 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
3272 assert(pBeginInfo->pInheritanceInfo);
3273 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
3274 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
3275
3276 struct radv_subpass *subpass =
3277 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
3278
3279 if (cmd_buffer->state.framebuffer) {
3280 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
3281 if (result != VK_SUCCESS)
3282 return result;
3283 }
3284
3285 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3286 }
3287
3288 if (unlikely(cmd_buffer->device->trace_bo)) {
3289 struct radv_device *device = cmd_buffer->device;
3290
3291 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
3292 device->trace_bo);
3293
3294 radv_cmd_buffer_trace_emit(cmd_buffer);
3295 }
3296
3297 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
3298
3299 return result;
3300 }
3301
3302 void radv_CmdBindVertexBuffers(
3303 VkCommandBuffer commandBuffer,
3304 uint32_t firstBinding,
3305 uint32_t bindingCount,
3306 const VkBuffer* pBuffers,
3307 const VkDeviceSize* pOffsets)
3308 {
3309 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3310 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
3311 bool changed = false;
3312
3313 /* We have to defer setting up vertex buffer since we need the buffer
3314 * stride from the pipeline. */
3315
3316 assert(firstBinding + bindingCount <= MAX_VBS);
3317 for (uint32_t i = 0; i < bindingCount; i++) {
3318 uint32_t idx = firstBinding + i;
3319
3320 if (!changed &&
3321 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
3322 vb[idx].offset != pOffsets[i])) {
3323 changed = true;
3324 }
3325
3326 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
3327 vb[idx].offset = pOffsets[i];
3328
3329 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3330 vb[idx].buffer->bo);
3331 }
3332
3333 if (!changed) {
3334 /* No state changes. */
3335 return;
3336 }
3337
3338 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
3339 }
3340
3341 static uint32_t
3342 vk_to_index_type(VkIndexType type)
3343 {
3344 switch (type) {
3345 case VK_INDEX_TYPE_UINT8_EXT:
3346 return V_028A7C_VGT_INDEX_8;
3347 case VK_INDEX_TYPE_UINT16:
3348 return V_028A7C_VGT_INDEX_16;
3349 case VK_INDEX_TYPE_UINT32:
3350 return V_028A7C_VGT_INDEX_32;
3351 default:
3352 unreachable("invalid index type");
3353 }
3354 }
3355
3356 static uint32_t
3357 radv_get_vgt_index_size(uint32_t type)
3358 {
3359 switch (type) {
3360 case V_028A7C_VGT_INDEX_8:
3361 return 1;
3362 case V_028A7C_VGT_INDEX_16:
3363 return 2;
3364 case V_028A7C_VGT_INDEX_32:
3365 return 4;
3366 default:
3367 unreachable("invalid index type");
3368 }
3369 }
3370
3371 void radv_CmdBindIndexBuffer(
3372 VkCommandBuffer commandBuffer,
3373 VkBuffer buffer,
3374 VkDeviceSize offset,
3375 VkIndexType indexType)
3376 {
3377 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3378 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
3379
3380 if (cmd_buffer->state.index_buffer == index_buffer &&
3381 cmd_buffer->state.index_offset == offset &&
3382 cmd_buffer->state.index_type == indexType) {
3383 /* No state changes. */
3384 return;
3385 }
3386
3387 cmd_buffer->state.index_buffer = index_buffer;
3388 cmd_buffer->state.index_offset = offset;
3389 cmd_buffer->state.index_type = vk_to_index_type(indexType);
3390 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
3391 cmd_buffer->state.index_va += index_buffer->offset + offset;
3392
3393 int index_size = radv_get_vgt_index_size(vk_to_index_type(indexType));
3394 cmd_buffer->state.max_index_count = (index_buffer->size - offset) / index_size;
3395 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3396 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
3397 }
3398
3399
3400 static void
3401 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3402 VkPipelineBindPoint bind_point,
3403 struct radv_descriptor_set *set, unsigned idx)
3404 {
3405 struct radeon_winsys *ws = cmd_buffer->device->ws;
3406
3407 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
3408
3409 assert(set);
3410 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
3411
3412 if (!cmd_buffer->device->use_global_bo_list) {
3413 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3414 if (set->descriptors[j])
3415 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
3416 }
3417
3418 if(set->bo)
3419 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
3420 }
3421
3422 void radv_CmdBindDescriptorSets(
3423 VkCommandBuffer commandBuffer,
3424 VkPipelineBindPoint pipelineBindPoint,
3425 VkPipelineLayout _layout,
3426 uint32_t firstSet,
3427 uint32_t descriptorSetCount,
3428 const VkDescriptorSet* pDescriptorSets,
3429 uint32_t dynamicOffsetCount,
3430 const uint32_t* pDynamicOffsets)
3431 {
3432 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3433 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3434 unsigned dyn_idx = 0;
3435
3436 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
3437 struct radv_descriptor_state *descriptors_state =
3438 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3439
3440 for (unsigned i = 0; i < descriptorSetCount; ++i) {
3441 unsigned idx = i + firstSet;
3442 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
3443
3444 /* If the set is already bound we only need to update the
3445 * (potentially changed) dynamic offsets. */
3446 if (descriptors_state->sets[idx] != set ||
3447 !(descriptors_state->valid & (1u << idx))) {
3448 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
3449 }
3450
3451 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
3452 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
3453 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
3454 assert(dyn_idx < dynamicOffsetCount);
3455
3456 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
3457 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
3458 dst[0] = va;
3459 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
3460 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
3461 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3462 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3463 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3464 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3465
3466 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
3467 dst[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3468 S_008F0C_OOB_SELECT(3) |
3469 S_008F0C_RESOURCE_LEVEL(1);
3470 } else {
3471 dst[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3472 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3473 }
3474
3475 cmd_buffer->push_constant_stages |=
3476 set->layout->dynamic_shader_stages;
3477 }
3478 }
3479 }
3480
3481 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3482 struct radv_descriptor_set *set,
3483 struct radv_descriptor_set_layout *layout,
3484 VkPipelineBindPoint bind_point)
3485 {
3486 struct radv_descriptor_state *descriptors_state =
3487 radv_get_descriptors_state(cmd_buffer, bind_point);
3488 set->size = layout->size;
3489 set->layout = layout;
3490
3491 if (descriptors_state->push_set.capacity < set->size) {
3492 size_t new_size = MAX2(set->size, 1024);
3493 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
3494 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
3495
3496 free(set->mapped_ptr);
3497 set->mapped_ptr = malloc(new_size);
3498
3499 if (!set->mapped_ptr) {
3500 descriptors_state->push_set.capacity = 0;
3501 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3502 return false;
3503 }
3504
3505 descriptors_state->push_set.capacity = new_size;
3506 }
3507
3508 return true;
3509 }
3510
3511 void radv_meta_push_descriptor_set(
3512 struct radv_cmd_buffer* cmd_buffer,
3513 VkPipelineBindPoint pipelineBindPoint,
3514 VkPipelineLayout _layout,
3515 uint32_t set,
3516 uint32_t descriptorWriteCount,
3517 const VkWriteDescriptorSet* pDescriptorWrites)
3518 {
3519 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3520 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
3521 unsigned bo_offset;
3522
3523 assert(set == 0);
3524 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3525
3526 push_set->size = layout->set[set].layout->size;
3527 push_set->layout = layout->set[set].layout;
3528
3529 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
3530 &bo_offset,
3531 (void**) &push_set->mapped_ptr))
3532 return;
3533
3534 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
3535 push_set->va += bo_offset;
3536
3537 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3538 radv_descriptor_set_to_handle(push_set),
3539 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3540
3541 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3542 }
3543
3544 void radv_CmdPushDescriptorSetKHR(
3545 VkCommandBuffer commandBuffer,
3546 VkPipelineBindPoint pipelineBindPoint,
3547 VkPipelineLayout _layout,
3548 uint32_t set,
3549 uint32_t descriptorWriteCount,
3550 const VkWriteDescriptorSet* pDescriptorWrites)
3551 {
3552 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3553 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3554 struct radv_descriptor_state *descriptors_state =
3555 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3556 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3557
3558 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3559
3560 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3561 layout->set[set].layout,
3562 pipelineBindPoint))
3563 return;
3564
3565 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3566 * because it is invalid, according to Vulkan spec.
3567 */
3568 for (int i = 0; i < descriptorWriteCount; i++) {
3569 ASSERTED const VkWriteDescriptorSet *writeset = &pDescriptorWrites[i];
3570 assert(writeset->descriptorType != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT);
3571 }
3572
3573 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3574 radv_descriptor_set_to_handle(push_set),
3575 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3576
3577 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3578 descriptors_state->push_dirty = true;
3579 }
3580
3581 void radv_CmdPushDescriptorSetWithTemplateKHR(
3582 VkCommandBuffer commandBuffer,
3583 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
3584 VkPipelineLayout _layout,
3585 uint32_t set,
3586 const void* pData)
3587 {
3588 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3589 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3590 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
3591 struct radv_descriptor_state *descriptors_state =
3592 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
3593 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3594
3595 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3596
3597 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3598 layout->set[set].layout,
3599 templ->bind_point))
3600 return;
3601
3602 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
3603 descriptorUpdateTemplate, pData);
3604
3605 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
3606 descriptors_state->push_dirty = true;
3607 }
3608
3609 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
3610 VkPipelineLayout layout,
3611 VkShaderStageFlags stageFlags,
3612 uint32_t offset,
3613 uint32_t size,
3614 const void* pValues)
3615 {
3616 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3617 memcpy(cmd_buffer->push_constants + offset, pValues, size);
3618 cmd_buffer->push_constant_stages |= stageFlags;
3619 }
3620
3621 VkResult radv_EndCommandBuffer(
3622 VkCommandBuffer commandBuffer)
3623 {
3624 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3625
3626 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
3627 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6)
3628 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WB_L2;
3629
3630 /* Make sure to sync all pending active queries at the end of
3631 * command buffer.
3632 */
3633 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
3634
3635 /* Since NGG streamout uses GDS, we need to make GDS idle when
3636 * we leave the IB, otherwise another process might overwrite
3637 * it while our shaders are busy.
3638 */
3639 if (cmd_buffer->gds_needed)
3640 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
3641
3642 si_emit_cache_flush(cmd_buffer);
3643 }
3644
3645 /* Make sure CP DMA is idle at the end of IBs because the kernel
3646 * doesn't wait for it.
3647 */
3648 si_cp_dma_wait_for_idle(cmd_buffer);
3649
3650 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3651 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
3652
3653 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
3654 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3655
3656 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
3657
3658 return cmd_buffer->record_result;
3659 }
3660
3661 static void
3662 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
3663 {
3664 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3665
3666 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
3667 return;
3668
3669 assert(!pipeline->ctx_cs.cdw);
3670
3671 cmd_buffer->state.emitted_compute_pipeline = pipeline;
3672
3673 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
3674 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
3675
3676 cmd_buffer->compute_scratch_size_needed =
3677 MAX2(cmd_buffer->compute_scratch_size_needed,
3678 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
3679
3680 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3681 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
3682
3683 if (unlikely(cmd_buffer->device->trace_bo))
3684 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
3685 }
3686
3687 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
3688 VkPipelineBindPoint bind_point)
3689 {
3690 struct radv_descriptor_state *descriptors_state =
3691 radv_get_descriptors_state(cmd_buffer, bind_point);
3692
3693 descriptors_state->dirty |= descriptors_state->valid;
3694 }
3695
3696 void radv_CmdBindPipeline(
3697 VkCommandBuffer commandBuffer,
3698 VkPipelineBindPoint pipelineBindPoint,
3699 VkPipeline _pipeline)
3700 {
3701 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3702 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
3703
3704 switch (pipelineBindPoint) {
3705 case VK_PIPELINE_BIND_POINT_COMPUTE:
3706 if (cmd_buffer->state.compute_pipeline == pipeline)
3707 return;
3708 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3709
3710 cmd_buffer->state.compute_pipeline = pipeline;
3711 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
3712 break;
3713 case VK_PIPELINE_BIND_POINT_GRAPHICS:
3714 if (cmd_buffer->state.pipeline == pipeline)
3715 return;
3716 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3717
3718 cmd_buffer->state.pipeline = pipeline;
3719 if (!pipeline)
3720 break;
3721
3722 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
3723 cmd_buffer->push_constant_stages |= pipeline->active_stages;
3724
3725 /* the new vertex shader might not have the same user regs */
3726 cmd_buffer->state.last_first_instance = -1;
3727 cmd_buffer->state.last_vertex_offset = -1;
3728
3729 /* Prefetch all pipeline shaders at first draw time. */
3730 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
3731
3732 if ((cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI10 ||
3733 cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI12 ||
3734 cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI14) &&
3735 cmd_buffer->state.emitted_pipeline &&
3736 radv_pipeline_has_ngg(cmd_buffer->state.emitted_pipeline) &&
3737 !radv_pipeline_has_ngg(cmd_buffer->state.pipeline)) {
3738 /* Transitioning from NGG to legacy GS requires
3739 * VGT_FLUSH on Navi10-14. VGT_FLUSH is also emitted
3740 * at the beginning of IBs when legacy GS ring pointers
3741 * are set.
3742 */
3743 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
3744 }
3745
3746 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
3747 radv_bind_streamout_state(cmd_buffer, pipeline);
3748
3749 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
3750 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
3751 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
3752 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
3753
3754 if (radv_pipeline_has_tess(pipeline))
3755 cmd_buffer->tess_rings_needed = true;
3756 break;
3757 default:
3758 assert(!"invalid bind point");
3759 break;
3760 }
3761 }
3762
3763 void radv_CmdSetViewport(
3764 VkCommandBuffer commandBuffer,
3765 uint32_t firstViewport,
3766 uint32_t viewportCount,
3767 const VkViewport* pViewports)
3768 {
3769 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3770 struct radv_cmd_state *state = &cmd_buffer->state;
3771 ASSERTED const uint32_t total_count = firstViewport + viewportCount;
3772
3773 assert(firstViewport < MAX_VIEWPORTS);
3774 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
3775
3776 if (!memcmp(state->dynamic.viewport.viewports + firstViewport,
3777 pViewports, viewportCount * sizeof(*pViewports))) {
3778 return;
3779 }
3780
3781 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
3782 viewportCount * sizeof(*pViewports));
3783
3784 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
3785 }
3786
3787 void radv_CmdSetScissor(
3788 VkCommandBuffer commandBuffer,
3789 uint32_t firstScissor,
3790 uint32_t scissorCount,
3791 const VkRect2D* pScissors)
3792 {
3793 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3794 struct radv_cmd_state *state = &cmd_buffer->state;
3795 ASSERTED const uint32_t total_count = firstScissor + scissorCount;
3796
3797 assert(firstScissor < MAX_SCISSORS);
3798 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
3799
3800 if (!memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
3801 scissorCount * sizeof(*pScissors))) {
3802 return;
3803 }
3804
3805 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
3806 scissorCount * sizeof(*pScissors));
3807
3808 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
3809 }
3810
3811 void radv_CmdSetLineWidth(
3812 VkCommandBuffer commandBuffer,
3813 float lineWidth)
3814 {
3815 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3816
3817 if (cmd_buffer->state.dynamic.line_width == lineWidth)
3818 return;
3819
3820 cmd_buffer->state.dynamic.line_width = lineWidth;
3821 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
3822 }
3823
3824 void radv_CmdSetDepthBias(
3825 VkCommandBuffer commandBuffer,
3826 float depthBiasConstantFactor,
3827 float depthBiasClamp,
3828 float depthBiasSlopeFactor)
3829 {
3830 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3831 struct radv_cmd_state *state = &cmd_buffer->state;
3832
3833 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
3834 state->dynamic.depth_bias.clamp == depthBiasClamp &&
3835 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
3836 return;
3837 }
3838
3839 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
3840 state->dynamic.depth_bias.clamp = depthBiasClamp;
3841 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
3842
3843 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
3844 }
3845
3846 void radv_CmdSetBlendConstants(
3847 VkCommandBuffer commandBuffer,
3848 const float blendConstants[4])
3849 {
3850 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3851 struct radv_cmd_state *state = &cmd_buffer->state;
3852
3853 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
3854 return;
3855
3856 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
3857
3858 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
3859 }
3860
3861 void radv_CmdSetDepthBounds(
3862 VkCommandBuffer commandBuffer,
3863 float minDepthBounds,
3864 float maxDepthBounds)
3865 {
3866 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3867 struct radv_cmd_state *state = &cmd_buffer->state;
3868
3869 if (state->dynamic.depth_bounds.min == minDepthBounds &&
3870 state->dynamic.depth_bounds.max == maxDepthBounds) {
3871 return;
3872 }
3873
3874 state->dynamic.depth_bounds.min = minDepthBounds;
3875 state->dynamic.depth_bounds.max = maxDepthBounds;
3876
3877 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
3878 }
3879
3880 void radv_CmdSetStencilCompareMask(
3881 VkCommandBuffer commandBuffer,
3882 VkStencilFaceFlags faceMask,
3883 uint32_t compareMask)
3884 {
3885 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3886 struct radv_cmd_state *state = &cmd_buffer->state;
3887 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
3888 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
3889
3890 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3891 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3892 return;
3893 }
3894
3895 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3896 state->dynamic.stencil_compare_mask.front = compareMask;
3897 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3898 state->dynamic.stencil_compare_mask.back = compareMask;
3899
3900 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
3901 }
3902
3903 void radv_CmdSetStencilWriteMask(
3904 VkCommandBuffer commandBuffer,
3905 VkStencilFaceFlags faceMask,
3906 uint32_t writeMask)
3907 {
3908 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3909 struct radv_cmd_state *state = &cmd_buffer->state;
3910 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
3911 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
3912
3913 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3914 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3915 return;
3916 }
3917
3918 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3919 state->dynamic.stencil_write_mask.front = writeMask;
3920 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3921 state->dynamic.stencil_write_mask.back = writeMask;
3922
3923 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
3924 }
3925
3926 void radv_CmdSetStencilReference(
3927 VkCommandBuffer commandBuffer,
3928 VkStencilFaceFlags faceMask,
3929 uint32_t reference)
3930 {
3931 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3932 struct radv_cmd_state *state = &cmd_buffer->state;
3933 bool front_same = state->dynamic.stencil_reference.front == reference;
3934 bool back_same = state->dynamic.stencil_reference.back == reference;
3935
3936 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3937 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3938 return;
3939 }
3940
3941 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3942 cmd_buffer->state.dynamic.stencil_reference.front = reference;
3943 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3944 cmd_buffer->state.dynamic.stencil_reference.back = reference;
3945
3946 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
3947 }
3948
3949 void radv_CmdSetDiscardRectangleEXT(
3950 VkCommandBuffer commandBuffer,
3951 uint32_t firstDiscardRectangle,
3952 uint32_t discardRectangleCount,
3953 const VkRect2D* pDiscardRectangles)
3954 {
3955 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3956 struct radv_cmd_state *state = &cmd_buffer->state;
3957 ASSERTED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
3958
3959 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
3960 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
3961
3962 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
3963 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
3964 return;
3965 }
3966
3967 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
3968 pDiscardRectangles, discardRectangleCount);
3969
3970 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
3971 }
3972
3973 void radv_CmdSetSampleLocationsEXT(
3974 VkCommandBuffer commandBuffer,
3975 const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
3976 {
3977 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3978 struct radv_cmd_state *state = &cmd_buffer->state;
3979
3980 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
3981
3982 state->dynamic.sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
3983 state->dynamic.sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
3984 state->dynamic.sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
3985 typed_memcpy(&state->dynamic.sample_location.locations[0],
3986 pSampleLocationsInfo->pSampleLocations,
3987 pSampleLocationsInfo->sampleLocationsCount);
3988
3989 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS;
3990 }
3991
3992 void radv_CmdExecuteCommands(
3993 VkCommandBuffer commandBuffer,
3994 uint32_t commandBufferCount,
3995 const VkCommandBuffer* pCmdBuffers)
3996 {
3997 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
3998
3999 assert(commandBufferCount > 0);
4000
4001 /* Emit pending flushes on primary prior to executing secondary */
4002 si_emit_cache_flush(primary);
4003
4004 for (uint32_t i = 0; i < commandBufferCount; i++) {
4005 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
4006
4007 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
4008 secondary->scratch_size_needed);
4009 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
4010 secondary->compute_scratch_size_needed);
4011
4012 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
4013 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
4014 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
4015 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
4016 if (secondary->tess_rings_needed)
4017 primary->tess_rings_needed = true;
4018 if (secondary->sample_positions_needed)
4019 primary->sample_positions_needed = true;
4020
4021 if (!secondary->state.framebuffer &&
4022 (primary->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)) {
4023 /* Emit the framebuffer state from primary if secondary
4024 * has been recorded without a framebuffer, otherwise
4025 * fast color/depth clears can't work.
4026 */
4027 radv_emit_framebuffer_state(primary);
4028 }
4029
4030 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
4031
4032
4033 /* When the secondary command buffer is compute only we don't
4034 * need to re-emit the current graphics pipeline.
4035 */
4036 if (secondary->state.emitted_pipeline) {
4037 primary->state.emitted_pipeline =
4038 secondary->state.emitted_pipeline;
4039 }
4040
4041 /* When the secondary command buffer is graphics only we don't
4042 * need to re-emit the current compute pipeline.
4043 */
4044 if (secondary->state.emitted_compute_pipeline) {
4045 primary->state.emitted_compute_pipeline =
4046 secondary->state.emitted_compute_pipeline;
4047 }
4048
4049 /* Only re-emit the draw packets when needed. */
4050 if (secondary->state.last_primitive_reset_en != -1) {
4051 primary->state.last_primitive_reset_en =
4052 secondary->state.last_primitive_reset_en;
4053 }
4054
4055 if (secondary->state.last_primitive_reset_index) {
4056 primary->state.last_primitive_reset_index =
4057 secondary->state.last_primitive_reset_index;
4058 }
4059
4060 if (secondary->state.last_ia_multi_vgt_param) {
4061 primary->state.last_ia_multi_vgt_param =
4062 secondary->state.last_ia_multi_vgt_param;
4063 }
4064
4065 primary->state.last_first_instance = secondary->state.last_first_instance;
4066 primary->state.last_num_instances = secondary->state.last_num_instances;
4067 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
4068
4069 if (secondary->state.last_index_type != -1) {
4070 primary->state.last_index_type =
4071 secondary->state.last_index_type;
4072 }
4073 }
4074
4075 /* After executing commands from secondary buffers we have to dirty
4076 * some states.
4077 */
4078 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
4079 RADV_CMD_DIRTY_INDEX_BUFFER |
4080 RADV_CMD_DIRTY_DYNAMIC_ALL;
4081 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
4082 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
4083 }
4084
4085 VkResult radv_CreateCommandPool(
4086 VkDevice _device,
4087 const VkCommandPoolCreateInfo* pCreateInfo,
4088 const VkAllocationCallbacks* pAllocator,
4089 VkCommandPool* pCmdPool)
4090 {
4091 RADV_FROM_HANDLE(radv_device, device, _device);
4092 struct radv_cmd_pool *pool;
4093
4094 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
4095 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4096 if (pool == NULL)
4097 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4098
4099 if (pAllocator)
4100 pool->alloc = *pAllocator;
4101 else
4102 pool->alloc = device->alloc;
4103
4104 list_inithead(&pool->cmd_buffers);
4105 list_inithead(&pool->free_cmd_buffers);
4106
4107 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
4108
4109 *pCmdPool = radv_cmd_pool_to_handle(pool);
4110
4111 return VK_SUCCESS;
4112
4113 }
4114
4115 void radv_DestroyCommandPool(
4116 VkDevice _device,
4117 VkCommandPool commandPool,
4118 const VkAllocationCallbacks* pAllocator)
4119 {
4120 RADV_FROM_HANDLE(radv_device, device, _device);
4121 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4122
4123 if (!pool)
4124 return;
4125
4126 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4127 &pool->cmd_buffers, pool_link) {
4128 radv_cmd_buffer_destroy(cmd_buffer);
4129 }
4130
4131 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4132 &pool->free_cmd_buffers, pool_link) {
4133 radv_cmd_buffer_destroy(cmd_buffer);
4134 }
4135
4136 vk_free2(&device->alloc, pAllocator, pool);
4137 }
4138
4139 VkResult radv_ResetCommandPool(
4140 VkDevice device,
4141 VkCommandPool commandPool,
4142 VkCommandPoolResetFlags flags)
4143 {
4144 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4145 VkResult result;
4146
4147 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
4148 &pool->cmd_buffers, pool_link) {
4149 result = radv_reset_cmd_buffer(cmd_buffer);
4150 if (result != VK_SUCCESS)
4151 return result;
4152 }
4153
4154 return VK_SUCCESS;
4155 }
4156
4157 void radv_TrimCommandPool(
4158 VkDevice device,
4159 VkCommandPool commandPool,
4160 VkCommandPoolTrimFlags flags)
4161 {
4162 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4163
4164 if (!pool)
4165 return;
4166
4167 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4168 &pool->free_cmd_buffers, pool_link) {
4169 radv_cmd_buffer_destroy(cmd_buffer);
4170 }
4171 }
4172
4173 static void
4174 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
4175 uint32_t subpass_id)
4176 {
4177 struct radv_cmd_state *state = &cmd_buffer->state;
4178 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
4179
4180 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
4181 cmd_buffer->cs, 4096);
4182
4183 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
4184
4185 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
4186
4187 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4188 const uint32_t a = subpass->attachments[i].attachment;
4189 if (a == VK_ATTACHMENT_UNUSED)
4190 continue;
4191
4192 radv_handle_subpass_image_transition(cmd_buffer,
4193 subpass->attachments[i],
4194 true);
4195 }
4196
4197 radv_cmd_buffer_clear_subpass(cmd_buffer);
4198
4199 assert(cmd_buffer->cs->cdw <= cdw_max);
4200 }
4201
4202 static void
4203 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
4204 {
4205 struct radv_cmd_state *state = &cmd_buffer->state;
4206 const struct radv_subpass *subpass = state->subpass;
4207 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
4208
4209 radv_cmd_buffer_resolve_subpass(cmd_buffer);
4210
4211 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4212 const uint32_t a = subpass->attachments[i].attachment;
4213 if (a == VK_ATTACHMENT_UNUSED)
4214 continue;
4215
4216 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
4217 continue;
4218
4219 VkImageLayout layout = state->pass->attachments[a].final_layout;
4220 struct radv_subpass_attachment att = { a, layout };
4221 radv_handle_subpass_image_transition(cmd_buffer, att, false);
4222 }
4223 }
4224
4225 void radv_CmdBeginRenderPass(
4226 VkCommandBuffer commandBuffer,
4227 const VkRenderPassBeginInfo* pRenderPassBegin,
4228 VkSubpassContents contents)
4229 {
4230 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4231 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
4232 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
4233 VkResult result;
4234
4235 cmd_buffer->state.framebuffer = framebuffer;
4236 cmd_buffer->state.pass = pass;
4237 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
4238
4239 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
4240 if (result != VK_SUCCESS)
4241 return;
4242
4243 result = radv_cmd_state_setup_sample_locations(cmd_buffer, pass, pRenderPassBegin);
4244 if (result != VK_SUCCESS)
4245 return;
4246
4247 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
4248 }
4249
4250 void radv_CmdBeginRenderPass2KHR(
4251 VkCommandBuffer commandBuffer,
4252 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
4253 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
4254 {
4255 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
4256 pSubpassBeginInfo->contents);
4257 }
4258
4259 void radv_CmdNextSubpass(
4260 VkCommandBuffer commandBuffer,
4261 VkSubpassContents contents)
4262 {
4263 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4264
4265 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
4266 radv_cmd_buffer_end_subpass(cmd_buffer);
4267 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
4268 }
4269
4270 void radv_CmdNextSubpass2KHR(
4271 VkCommandBuffer commandBuffer,
4272 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
4273 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4274 {
4275 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
4276 }
4277
4278 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
4279 {
4280 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
4281 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
4282 if (!radv_get_shader(pipeline, stage))
4283 continue;
4284
4285 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
4286 if (loc->sgpr_idx == -1)
4287 continue;
4288 uint32_t base_reg = pipeline->user_data_0[stage];
4289 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4290
4291 }
4292 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
4293 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
4294 if (loc->sgpr_idx != -1) {
4295 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
4296 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4297 }
4298 }
4299 }
4300
4301 static void
4302 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4303 uint32_t vertex_count,
4304 bool use_opaque)
4305 {
4306 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
4307 radeon_emit(cmd_buffer->cs, vertex_count);
4308 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
4309 S_0287F0_USE_OPAQUE(use_opaque));
4310 }
4311
4312 static void
4313 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
4314 uint64_t index_va,
4315 uint32_t index_count)
4316 {
4317 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
4318 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
4319 radeon_emit(cmd_buffer->cs, index_va);
4320 radeon_emit(cmd_buffer->cs, index_va >> 32);
4321 radeon_emit(cmd_buffer->cs, index_count);
4322 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
4323 }
4324
4325 static void
4326 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4327 bool indexed,
4328 uint32_t draw_count,
4329 uint64_t count_va,
4330 uint32_t stride)
4331 {
4332 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4333 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
4334 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
4335 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id;
4336 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
4337 bool predicating = cmd_buffer->state.predicating;
4338 assert(base_reg);
4339
4340 /* just reset draw state for vertex data */
4341 cmd_buffer->state.last_first_instance = -1;
4342 cmd_buffer->state.last_num_instances = -1;
4343 cmd_buffer->state.last_vertex_offset = -1;
4344
4345 if (draw_count == 1 && !count_va && !draw_id_enable) {
4346 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
4347 PKT3_DRAW_INDIRECT, 3, predicating));
4348 radeon_emit(cs, 0);
4349 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4350 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4351 radeon_emit(cs, di_src_sel);
4352 } else {
4353 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
4354 PKT3_DRAW_INDIRECT_MULTI,
4355 8, predicating));
4356 radeon_emit(cs, 0);
4357 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4358 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4359 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
4360 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
4361 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
4362 radeon_emit(cs, draw_count); /* count */
4363 radeon_emit(cs, count_va); /* count_addr */
4364 radeon_emit(cs, count_va >> 32);
4365 radeon_emit(cs, stride); /* stride */
4366 radeon_emit(cs, di_src_sel);
4367 }
4368 }
4369
4370 static void
4371 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
4372 const struct radv_draw_info *info)
4373 {
4374 struct radv_cmd_state *state = &cmd_buffer->state;
4375 struct radeon_winsys *ws = cmd_buffer->device->ws;
4376 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4377
4378 if (info->indirect) {
4379 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4380 uint64_t count_va = 0;
4381
4382 va += info->indirect->offset + info->indirect_offset;
4383
4384 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4385
4386 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
4387 radeon_emit(cs, 1);
4388 radeon_emit(cs, va);
4389 radeon_emit(cs, va >> 32);
4390
4391 if (info->count_buffer) {
4392 count_va = radv_buffer_get_va(info->count_buffer->bo);
4393 count_va += info->count_buffer->offset +
4394 info->count_buffer_offset;
4395
4396 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
4397 }
4398
4399 if (!state->subpass->view_mask) {
4400 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4401 info->indexed,
4402 info->count,
4403 count_va,
4404 info->stride);
4405 } else {
4406 unsigned i;
4407 for_each_bit(i, state->subpass->view_mask) {
4408 radv_emit_view_index(cmd_buffer, i);
4409
4410 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4411 info->indexed,
4412 info->count,
4413 count_va,
4414 info->stride);
4415 }
4416 }
4417 } else {
4418 assert(state->pipeline->graphics.vtx_base_sgpr);
4419
4420 if (info->vertex_offset != state->last_vertex_offset ||
4421 info->first_instance != state->last_first_instance) {
4422 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
4423 state->pipeline->graphics.vtx_emit_num);
4424
4425 radeon_emit(cs, info->vertex_offset);
4426 radeon_emit(cs, info->first_instance);
4427 if (state->pipeline->graphics.vtx_emit_num == 3)
4428 radeon_emit(cs, 0);
4429 state->last_first_instance = info->first_instance;
4430 state->last_vertex_offset = info->vertex_offset;
4431 }
4432
4433 if (state->last_num_instances != info->instance_count) {
4434 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
4435 radeon_emit(cs, info->instance_count);
4436 state->last_num_instances = info->instance_count;
4437 }
4438
4439 if (info->indexed) {
4440 int index_size = radv_get_vgt_index_size(state->index_type);
4441 uint64_t index_va;
4442
4443 /* Skip draw calls with 0-sized index buffers. They
4444 * cause a hang on some chips, like Navi10-14.
4445 */
4446 if (!cmd_buffer->state.max_index_count)
4447 return;
4448
4449 index_va = state->index_va;
4450 index_va += info->first_index * index_size;
4451
4452 if (!state->subpass->view_mask) {
4453 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4454 index_va,
4455 info->count);
4456 } else {
4457 unsigned i;
4458 for_each_bit(i, state->subpass->view_mask) {
4459 radv_emit_view_index(cmd_buffer, i);
4460
4461 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4462 index_va,
4463 info->count);
4464 }
4465 }
4466 } else {
4467 if (!state->subpass->view_mask) {
4468 radv_cs_emit_draw_packet(cmd_buffer,
4469 info->count,
4470 !!info->strmout_buffer);
4471 } else {
4472 unsigned i;
4473 for_each_bit(i, state->subpass->view_mask) {
4474 radv_emit_view_index(cmd_buffer, i);
4475
4476 radv_cs_emit_draw_packet(cmd_buffer,
4477 info->count,
4478 !!info->strmout_buffer);
4479 }
4480 }
4481 }
4482 }
4483 }
4484
4485 /*
4486 * Vega and raven have a bug which triggers if there are multiple context
4487 * register contexts active at the same time with different scissor values.
4488 *
4489 * There are two possible workarounds:
4490 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
4491 * there is only ever 1 active set of scissor values at the same time.
4492 *
4493 * 2) Whenever the hardware switches contexts we have to set the scissor
4494 * registers again even if it is a noop. That way the new context gets
4495 * the correct scissor values.
4496 *
4497 * This implements option 2. radv_need_late_scissor_emission needs to
4498 * return true on affected HW if radv_emit_all_graphics_states sets
4499 * any context registers.
4500 */
4501 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
4502 const struct radv_draw_info *info)
4503 {
4504 struct radv_cmd_state *state = &cmd_buffer->state;
4505
4506 if (!cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
4507 return false;
4508
4509 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
4510 return true;
4511
4512 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
4513
4514 /* Index, vertex and streamout buffers don't change context regs, and
4515 * pipeline is already handled.
4516 */
4517 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
4518 RADV_CMD_DIRTY_VERTEX_BUFFER |
4519 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
4520 RADV_CMD_DIRTY_PIPELINE);
4521
4522 if (cmd_buffer->state.dirty & used_states)
4523 return true;
4524
4525 uint32_t primitive_reset_index =
4526 radv_get_primitive_reset_index(cmd_buffer);
4527
4528 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
4529 primitive_reset_index != state->last_primitive_reset_index)
4530 return true;
4531
4532 return false;
4533 }
4534
4535 static void
4536 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
4537 const struct radv_draw_info *info)
4538 {
4539 bool late_scissor_emission;
4540
4541 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
4542 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
4543 radv_emit_rbplus_state(cmd_buffer);
4544
4545 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
4546 radv_emit_graphics_pipeline(cmd_buffer);
4547
4548 /* This should be before the cmd_buffer->state.dirty is cleared
4549 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4550 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4551 late_scissor_emission =
4552 radv_need_late_scissor_emission(cmd_buffer, info);
4553
4554 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
4555 radv_emit_framebuffer_state(cmd_buffer);
4556
4557 if (info->indexed) {
4558 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
4559 radv_emit_index_buffer(cmd_buffer);
4560 } else {
4561 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4562 * so the state must be re-emitted before the next indexed
4563 * draw.
4564 */
4565 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
4566 cmd_buffer->state.last_index_type = -1;
4567 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
4568 }
4569 }
4570
4571 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
4572
4573 radv_emit_draw_registers(cmd_buffer, info);
4574
4575 if (late_scissor_emission)
4576 radv_emit_scissor(cmd_buffer);
4577 }
4578
4579 static void
4580 radv_draw(struct radv_cmd_buffer *cmd_buffer,
4581 const struct radv_draw_info *info)
4582 {
4583 struct radeon_info *rad_info =
4584 &cmd_buffer->device->physical_device->rad_info;
4585 bool has_prefetch =
4586 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4587 bool pipeline_is_dirty =
4588 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
4589 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
4590
4591 ASSERTED unsigned cdw_max =
4592 radeon_check_space(cmd_buffer->device->ws,
4593 cmd_buffer->cs, 4096);
4594
4595 if (likely(!info->indirect)) {
4596 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4597 * no workaround for indirect draws, but we can at least skip
4598 * direct draws.
4599 */
4600 if (unlikely(!info->instance_count))
4601 return;
4602
4603 /* Handle count == 0. */
4604 if (unlikely(!info->count && !info->strmout_buffer))
4605 return;
4606 }
4607
4608 /* Use optimal packet order based on whether we need to sync the
4609 * pipeline.
4610 */
4611 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4612 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4613 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4614 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4615 /* If we have to wait for idle, set all states first, so that
4616 * all SET packets are processed in parallel with previous draw
4617 * calls. Then upload descriptors, set shader pointers, and
4618 * draw, and prefetch at the end. This ensures that the time
4619 * the CUs are idle is very short. (there are only SET_SH
4620 * packets between the wait and the draw)
4621 */
4622 radv_emit_all_graphics_states(cmd_buffer, info);
4623 si_emit_cache_flush(cmd_buffer);
4624 /* <-- CUs are idle here --> */
4625
4626 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4627
4628 radv_emit_draw_packets(cmd_buffer, info);
4629 /* <-- CUs are busy here --> */
4630
4631 /* Start prefetches after the draw has been started. Both will
4632 * run in parallel, but starting the draw first is more
4633 * important.
4634 */
4635 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4636 radv_emit_prefetch_L2(cmd_buffer,
4637 cmd_buffer->state.pipeline, false);
4638 }
4639 } else {
4640 /* If we don't wait for idle, start prefetches first, then set
4641 * states, and draw at the end.
4642 */
4643 si_emit_cache_flush(cmd_buffer);
4644
4645 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4646 /* Only prefetch the vertex shader and VBO descriptors
4647 * in order to start the draw as soon as possible.
4648 */
4649 radv_emit_prefetch_L2(cmd_buffer,
4650 cmd_buffer->state.pipeline, true);
4651 }
4652
4653 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4654
4655 radv_emit_all_graphics_states(cmd_buffer, info);
4656 radv_emit_draw_packets(cmd_buffer, info);
4657
4658 /* Prefetch the remaining shaders after the draw has been
4659 * started.
4660 */
4661 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4662 radv_emit_prefetch_L2(cmd_buffer,
4663 cmd_buffer->state.pipeline, false);
4664 }
4665 }
4666
4667 /* Workaround for a VGT hang when streamout is enabled.
4668 * It must be done after drawing.
4669 */
4670 if (cmd_buffer->state.streamout.streamout_enabled &&
4671 (rad_info->family == CHIP_HAWAII ||
4672 rad_info->family == CHIP_TONGA ||
4673 rad_info->family == CHIP_FIJI)) {
4674 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
4675 }
4676
4677 assert(cmd_buffer->cs->cdw <= cdw_max);
4678 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
4679 }
4680
4681 void radv_CmdDraw(
4682 VkCommandBuffer commandBuffer,
4683 uint32_t vertexCount,
4684 uint32_t instanceCount,
4685 uint32_t firstVertex,
4686 uint32_t firstInstance)
4687 {
4688 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4689 struct radv_draw_info info = {};
4690
4691 info.count = vertexCount;
4692 info.instance_count = instanceCount;
4693 info.first_instance = firstInstance;
4694 info.vertex_offset = firstVertex;
4695
4696 radv_draw(cmd_buffer, &info);
4697 }
4698
4699 void radv_CmdDrawIndexed(
4700 VkCommandBuffer commandBuffer,
4701 uint32_t indexCount,
4702 uint32_t instanceCount,
4703 uint32_t firstIndex,
4704 int32_t vertexOffset,
4705 uint32_t firstInstance)
4706 {
4707 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4708 struct radv_draw_info info = {};
4709
4710 info.indexed = true;
4711 info.count = indexCount;
4712 info.instance_count = instanceCount;
4713 info.first_index = firstIndex;
4714 info.vertex_offset = vertexOffset;
4715 info.first_instance = firstInstance;
4716
4717 radv_draw(cmd_buffer, &info);
4718 }
4719
4720 void radv_CmdDrawIndirect(
4721 VkCommandBuffer commandBuffer,
4722 VkBuffer _buffer,
4723 VkDeviceSize offset,
4724 uint32_t drawCount,
4725 uint32_t stride)
4726 {
4727 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4728 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4729 struct radv_draw_info info = {};
4730
4731 info.count = drawCount;
4732 info.indirect = buffer;
4733 info.indirect_offset = offset;
4734 info.stride = stride;
4735
4736 radv_draw(cmd_buffer, &info);
4737 }
4738
4739 void radv_CmdDrawIndexedIndirect(
4740 VkCommandBuffer commandBuffer,
4741 VkBuffer _buffer,
4742 VkDeviceSize offset,
4743 uint32_t drawCount,
4744 uint32_t stride)
4745 {
4746 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4747 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4748 struct radv_draw_info info = {};
4749
4750 info.indexed = true;
4751 info.count = drawCount;
4752 info.indirect = buffer;
4753 info.indirect_offset = offset;
4754 info.stride = stride;
4755
4756 radv_draw(cmd_buffer, &info);
4757 }
4758
4759 void radv_CmdDrawIndirectCountKHR(
4760 VkCommandBuffer commandBuffer,
4761 VkBuffer _buffer,
4762 VkDeviceSize offset,
4763 VkBuffer _countBuffer,
4764 VkDeviceSize countBufferOffset,
4765 uint32_t maxDrawCount,
4766 uint32_t stride)
4767 {
4768 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4769 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4770 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4771 struct radv_draw_info info = {};
4772
4773 info.count = maxDrawCount;
4774 info.indirect = buffer;
4775 info.indirect_offset = offset;
4776 info.count_buffer = count_buffer;
4777 info.count_buffer_offset = countBufferOffset;
4778 info.stride = stride;
4779
4780 radv_draw(cmd_buffer, &info);
4781 }
4782
4783 void radv_CmdDrawIndexedIndirectCountKHR(
4784 VkCommandBuffer commandBuffer,
4785 VkBuffer _buffer,
4786 VkDeviceSize offset,
4787 VkBuffer _countBuffer,
4788 VkDeviceSize countBufferOffset,
4789 uint32_t maxDrawCount,
4790 uint32_t stride)
4791 {
4792 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4793 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4794 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4795 struct radv_draw_info info = {};
4796
4797 info.indexed = true;
4798 info.count = maxDrawCount;
4799 info.indirect = buffer;
4800 info.indirect_offset = offset;
4801 info.count_buffer = count_buffer;
4802 info.count_buffer_offset = countBufferOffset;
4803 info.stride = stride;
4804
4805 radv_draw(cmd_buffer, &info);
4806 }
4807
4808 struct radv_dispatch_info {
4809 /**
4810 * Determine the layout of the grid (in block units) to be used.
4811 */
4812 uint32_t blocks[3];
4813
4814 /**
4815 * A starting offset for the grid. If unaligned is set, the offset
4816 * must still be aligned.
4817 */
4818 uint32_t offsets[3];
4819 /**
4820 * Whether it's an unaligned compute dispatch.
4821 */
4822 bool unaligned;
4823
4824 /**
4825 * Indirect compute parameters resource.
4826 */
4827 struct radv_buffer *indirect;
4828 uint64_t indirect_offset;
4829 };
4830
4831 static void
4832 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
4833 const struct radv_dispatch_info *info)
4834 {
4835 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4836 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4837 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
4838 struct radeon_winsys *ws = cmd_buffer->device->ws;
4839 bool predicating = cmd_buffer->state.predicating;
4840 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4841 struct radv_userdata_info *loc;
4842
4843 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
4844 AC_UD_CS_GRID_SIZE);
4845
4846 ASSERTED unsigned cdw_max = radeon_check_space(ws, cs, 25);
4847
4848 if (info->indirect) {
4849 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4850
4851 va += info->indirect->offset + info->indirect_offset;
4852
4853 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4854
4855 if (loc->sgpr_idx != -1) {
4856 for (unsigned i = 0; i < 3; ++i) {
4857 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
4858 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
4859 COPY_DATA_DST_SEL(COPY_DATA_REG));
4860 radeon_emit(cs, (va + 4 * i));
4861 radeon_emit(cs, (va + 4 * i) >> 32);
4862 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
4863 + loc->sgpr_idx * 4) >> 2) + i);
4864 radeon_emit(cs, 0);
4865 }
4866 }
4867
4868 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
4869 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
4870 PKT3_SHADER_TYPE_S(1));
4871 radeon_emit(cs, va);
4872 radeon_emit(cs, va >> 32);
4873 radeon_emit(cs, dispatch_initiator);
4874 } else {
4875 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
4876 PKT3_SHADER_TYPE_S(1));
4877 radeon_emit(cs, 1);
4878 radeon_emit(cs, va);
4879 radeon_emit(cs, va >> 32);
4880
4881 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
4882 PKT3_SHADER_TYPE_S(1));
4883 radeon_emit(cs, 0);
4884 radeon_emit(cs, dispatch_initiator);
4885 }
4886 } else {
4887 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
4888 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
4889
4890 if (info->unaligned) {
4891 unsigned *cs_block_size = compute_shader->info.cs.block_size;
4892 unsigned remainder[3];
4893
4894 /* If aligned, these should be an entire block size,
4895 * not 0.
4896 */
4897 remainder[0] = blocks[0] + cs_block_size[0] -
4898 align_u32_npot(blocks[0], cs_block_size[0]);
4899 remainder[1] = blocks[1] + cs_block_size[1] -
4900 align_u32_npot(blocks[1], cs_block_size[1]);
4901 remainder[2] = blocks[2] + cs_block_size[2] -
4902 align_u32_npot(blocks[2], cs_block_size[2]);
4903
4904 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
4905 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
4906 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
4907
4908 for(unsigned i = 0; i < 3; ++i) {
4909 assert(offsets[i] % cs_block_size[i] == 0);
4910 offsets[i] /= cs_block_size[i];
4911 }
4912
4913 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4914 radeon_emit(cs,
4915 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
4916 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
4917 radeon_emit(cs,
4918 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
4919 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
4920 radeon_emit(cs,
4921 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
4922 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
4923
4924 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
4925 }
4926
4927 if (loc->sgpr_idx != -1) {
4928 assert(loc->num_sgprs == 3);
4929
4930 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
4931 loc->sgpr_idx * 4, 3);
4932 radeon_emit(cs, blocks[0]);
4933 radeon_emit(cs, blocks[1]);
4934 radeon_emit(cs, blocks[2]);
4935 }
4936
4937 if (offsets[0] || offsets[1] || offsets[2]) {
4938 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
4939 radeon_emit(cs, offsets[0]);
4940 radeon_emit(cs, offsets[1]);
4941 radeon_emit(cs, offsets[2]);
4942
4943 /* The blocks in the packet are not counts but end values. */
4944 for (unsigned i = 0; i < 3; ++i)
4945 blocks[i] += offsets[i];
4946 } else {
4947 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
4948 }
4949
4950 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
4951 PKT3_SHADER_TYPE_S(1));
4952 radeon_emit(cs, blocks[0]);
4953 radeon_emit(cs, blocks[1]);
4954 radeon_emit(cs, blocks[2]);
4955 radeon_emit(cs, dispatch_initiator);
4956 }
4957
4958 assert(cmd_buffer->cs->cdw <= cdw_max);
4959 }
4960
4961 static void
4962 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
4963 {
4964 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4965 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4966 }
4967
4968 static void
4969 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
4970 const struct radv_dispatch_info *info)
4971 {
4972 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4973 bool has_prefetch =
4974 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4975 bool pipeline_is_dirty = pipeline &&
4976 pipeline != cmd_buffer->state.emitted_compute_pipeline;
4977
4978 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4979 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4980 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4981 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4982 /* If we have to wait for idle, set all states first, so that
4983 * all SET packets are processed in parallel with previous draw
4984 * calls. Then upload descriptors, set shader pointers, and
4985 * dispatch, and prefetch at the end. This ensures that the
4986 * time the CUs are idle is very short. (there are only SET_SH
4987 * packets between the wait and the draw)
4988 */
4989 radv_emit_compute_pipeline(cmd_buffer);
4990 si_emit_cache_flush(cmd_buffer);
4991 /* <-- CUs are idle here --> */
4992
4993 radv_upload_compute_shader_descriptors(cmd_buffer);
4994
4995 radv_emit_dispatch_packets(cmd_buffer, info);
4996 /* <-- CUs are busy here --> */
4997
4998 /* Start prefetches after the dispatch has been started. Both
4999 * will run in parallel, but starting the dispatch first is
5000 * more important.
5001 */
5002 if (has_prefetch && pipeline_is_dirty) {
5003 radv_emit_shader_prefetch(cmd_buffer,
5004 pipeline->shaders[MESA_SHADER_COMPUTE]);
5005 }
5006 } else {
5007 /* If we don't wait for idle, start prefetches first, then set
5008 * states, and dispatch at the end.
5009 */
5010 si_emit_cache_flush(cmd_buffer);
5011
5012 if (has_prefetch && pipeline_is_dirty) {
5013 radv_emit_shader_prefetch(cmd_buffer,
5014 pipeline->shaders[MESA_SHADER_COMPUTE]);
5015 }
5016
5017 radv_upload_compute_shader_descriptors(cmd_buffer);
5018
5019 radv_emit_compute_pipeline(cmd_buffer);
5020 radv_emit_dispatch_packets(cmd_buffer, info);
5021 }
5022
5023 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
5024 }
5025
5026 void radv_CmdDispatchBase(
5027 VkCommandBuffer commandBuffer,
5028 uint32_t base_x,
5029 uint32_t base_y,
5030 uint32_t base_z,
5031 uint32_t x,
5032 uint32_t y,
5033 uint32_t z)
5034 {
5035 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5036 struct radv_dispatch_info info = {};
5037
5038 info.blocks[0] = x;
5039 info.blocks[1] = y;
5040 info.blocks[2] = z;
5041
5042 info.offsets[0] = base_x;
5043 info.offsets[1] = base_y;
5044 info.offsets[2] = base_z;
5045 radv_dispatch(cmd_buffer, &info);
5046 }
5047
5048 void radv_CmdDispatch(
5049 VkCommandBuffer commandBuffer,
5050 uint32_t x,
5051 uint32_t y,
5052 uint32_t z)
5053 {
5054 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
5055 }
5056
5057 void radv_CmdDispatchIndirect(
5058 VkCommandBuffer commandBuffer,
5059 VkBuffer _buffer,
5060 VkDeviceSize offset)
5061 {
5062 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5063 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5064 struct radv_dispatch_info info = {};
5065
5066 info.indirect = buffer;
5067 info.indirect_offset = offset;
5068
5069 radv_dispatch(cmd_buffer, &info);
5070 }
5071
5072 void radv_unaligned_dispatch(
5073 struct radv_cmd_buffer *cmd_buffer,
5074 uint32_t x,
5075 uint32_t y,
5076 uint32_t z)
5077 {
5078 struct radv_dispatch_info info = {};
5079
5080 info.blocks[0] = x;
5081 info.blocks[1] = y;
5082 info.blocks[2] = z;
5083 info.unaligned = 1;
5084
5085 radv_dispatch(cmd_buffer, &info);
5086 }
5087
5088 void radv_CmdEndRenderPass(
5089 VkCommandBuffer commandBuffer)
5090 {
5091 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5092
5093 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
5094
5095 radv_cmd_buffer_end_subpass(cmd_buffer);
5096
5097 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
5098 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
5099
5100 cmd_buffer->state.pass = NULL;
5101 cmd_buffer->state.subpass = NULL;
5102 cmd_buffer->state.attachments = NULL;
5103 cmd_buffer->state.framebuffer = NULL;
5104 cmd_buffer->state.subpass_sample_locs = NULL;
5105 }
5106
5107 void radv_CmdEndRenderPass2KHR(
5108 VkCommandBuffer commandBuffer,
5109 const VkSubpassEndInfoKHR* pSubpassEndInfo)
5110 {
5111 radv_CmdEndRenderPass(commandBuffer);
5112 }
5113
5114 /*
5115 * For HTILE we have the following interesting clear words:
5116 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
5117 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
5118 * 0xfffffff0: Clear depth to 1.0
5119 * 0x00000000: Clear depth to 0.0
5120 */
5121 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
5122 struct radv_image *image,
5123 const VkImageSubresourceRange *range,
5124 uint32_t clear_word)
5125 {
5126 assert(range->baseMipLevel == 0);
5127 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
5128 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
5129 struct radv_cmd_state *state = &cmd_buffer->state;
5130 VkClearDepthStencilValue value = {};
5131
5132 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5133 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5134
5135 state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, clear_word);
5136
5137 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5138
5139 if (vk_format_is_stencil(image->vk_format))
5140 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
5141
5142 radv_set_ds_clear_metadata(cmd_buffer, image, range, value, aspects);
5143
5144 if (radv_image_is_tc_compat_htile(image)) {
5145 /* Initialize the TC-compat metada value to 0 because by
5146 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
5147 * need have to conditionally update its value when performing
5148 * a fast depth clear.
5149 */
5150 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, range, 0);
5151 }
5152 }
5153
5154 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
5155 struct radv_image *image,
5156 VkImageLayout src_layout,
5157 bool src_render_loop,
5158 VkImageLayout dst_layout,
5159 bool dst_render_loop,
5160 unsigned src_queue_mask,
5161 unsigned dst_queue_mask,
5162 const VkImageSubresourceRange *range,
5163 struct radv_sample_locations_state *sample_locs)
5164 {
5165 if (!radv_image_has_htile(image))
5166 return;
5167
5168 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5169 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
5170
5171 if (radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop,
5172 dst_queue_mask)) {
5173 clear_value = 0;
5174 }
5175
5176 radv_initialize_htile(cmd_buffer, image, range, clear_value);
5177 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5178 radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5179 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
5180 radv_initialize_htile(cmd_buffer, image, range, clear_value);
5181 } else if (radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5182 !radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5183 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5184 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5185
5186 radv_decompress_depth_image_inplace(cmd_buffer, image, range,
5187 sample_locs);
5188
5189 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5190 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5191 }
5192 }
5193
5194 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
5195 struct radv_image *image,
5196 const VkImageSubresourceRange *range,
5197 uint32_t value)
5198 {
5199 struct radv_cmd_state *state = &cmd_buffer->state;
5200
5201 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5202 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5203
5204 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, range, value);
5205
5206 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5207 }
5208
5209 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
5210 struct radv_image *image,
5211 const VkImageSubresourceRange *range)
5212 {
5213 struct radv_cmd_state *state = &cmd_buffer->state;
5214 static const uint32_t fmask_clear_values[4] = {
5215 0x00000000,
5216 0x02020202,
5217 0xE4E4E4E4,
5218 0x76543210
5219 };
5220 uint32_t log2_samples = util_logbase2(image->info.samples);
5221 uint32_t value = fmask_clear_values[log2_samples];
5222
5223 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5224 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5225
5226 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, range, value);
5227
5228 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5229 }
5230
5231 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
5232 struct radv_image *image,
5233 const VkImageSubresourceRange *range, uint32_t value)
5234 {
5235 struct radv_cmd_state *state = &cmd_buffer->state;
5236 unsigned size = 0;
5237
5238 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5239 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5240
5241 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
5242
5243 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) {
5244 /* When DCC is enabled with mipmaps, some levels might not
5245 * support fast clears and we have to initialize them as "fully
5246 * expanded".
5247 */
5248 /* Compute the size of all fast clearable DCC levels. */
5249 for (unsigned i = 0; i < image->planes[0].surface.num_dcc_levels; i++) {
5250 struct legacy_surf_level *surf_level =
5251 &image->planes[0].surface.u.legacy.level[i];
5252 unsigned dcc_fast_clear_size =
5253 surf_level->dcc_slice_fast_clear_size * image->info.array_size;
5254
5255 if (!dcc_fast_clear_size)
5256 break;
5257
5258 size = surf_level->dcc_offset + dcc_fast_clear_size;
5259 }
5260
5261 /* Initialize the mipmap levels without DCC. */
5262 if (size != image->planes[0].surface.dcc_size) {
5263 state->flush_bits |=
5264 radv_fill_buffer(cmd_buffer, image->bo,
5265 image->offset + image->dcc_offset + size,
5266 image->planes[0].surface.dcc_size - size,
5267 0xffffffff);
5268 }
5269 }
5270
5271 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5272 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5273 }
5274
5275 /**
5276 * Initialize DCC/FMASK/CMASK metadata for a color image.
5277 */
5278 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
5279 struct radv_image *image,
5280 VkImageLayout src_layout,
5281 bool src_render_loop,
5282 VkImageLayout dst_layout,
5283 bool dst_render_loop,
5284 unsigned src_queue_mask,
5285 unsigned dst_queue_mask,
5286 const VkImageSubresourceRange *range)
5287 {
5288 if (radv_image_has_cmask(image)) {
5289 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5290
5291 /* TODO: clarify this. */
5292 if (radv_image_has_fmask(image)) {
5293 value = 0xccccccccu;
5294 }
5295
5296 radv_initialise_cmask(cmd_buffer, image, range, value);
5297 }
5298
5299 if (radv_image_has_fmask(image)) {
5300 radv_initialize_fmask(cmd_buffer, image, range);
5301 }
5302
5303 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5304 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5305 bool need_decompress_pass = false;
5306
5307 if (radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout,
5308 dst_render_loop,
5309 dst_queue_mask)) {
5310 value = 0x20202020u;
5311 need_decompress_pass = true;
5312 }
5313
5314 radv_initialize_dcc(cmd_buffer, image, range, value);
5315
5316 radv_update_fce_metadata(cmd_buffer, image, range,
5317 need_decompress_pass);
5318 }
5319
5320 if (radv_image_has_cmask(image) ||
5321 radv_dcc_enabled(image, range->baseMipLevel)) {
5322 uint32_t color_values[2] = {};
5323 radv_set_color_clear_metadata(cmd_buffer, image, range,
5324 color_values);
5325 }
5326 }
5327
5328 /**
5329 * Handle color image transitions for DCC/FMASK/CMASK.
5330 */
5331 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
5332 struct radv_image *image,
5333 VkImageLayout src_layout,
5334 bool src_render_loop,
5335 VkImageLayout dst_layout,
5336 bool dst_render_loop,
5337 unsigned src_queue_mask,
5338 unsigned dst_queue_mask,
5339 const VkImageSubresourceRange *range)
5340 {
5341 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5342 radv_init_color_image_metadata(cmd_buffer, image,
5343 src_layout, src_render_loop,
5344 dst_layout, dst_render_loop,
5345 src_queue_mask, dst_queue_mask,
5346 range);
5347 return;
5348 }
5349
5350 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5351 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
5352 radv_initialize_dcc(cmd_buffer, image, range, 0xffffffffu);
5353 } else if (radv_layout_dcc_compressed(cmd_buffer->device, image, src_layout, src_render_loop, src_queue_mask) &&
5354 !radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout, dst_render_loop, dst_queue_mask)) {
5355 radv_decompress_dcc(cmd_buffer, image, range);
5356 } else if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
5357 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5358 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5359 }
5360 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
5361 bool fce_eliminate = false, fmask_expand = false;
5362
5363 if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
5364 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5365 fce_eliminate = true;
5366 }
5367
5368 if (radv_image_has_fmask(image)) {
5369 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
5370 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
5371 /* A FMASK decompress is required before doing
5372 * a MSAA decompress using FMASK.
5373 */
5374 fmask_expand = true;
5375 }
5376 }
5377
5378 if (fce_eliminate || fmask_expand)
5379 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5380
5381 if (fmask_expand)
5382 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
5383 }
5384 }
5385
5386 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
5387 struct radv_image *image,
5388 VkImageLayout src_layout,
5389 bool src_render_loop,
5390 VkImageLayout dst_layout,
5391 bool dst_render_loop,
5392 uint32_t src_family,
5393 uint32_t dst_family,
5394 const VkImageSubresourceRange *range,
5395 struct radv_sample_locations_state *sample_locs)
5396 {
5397 if (image->exclusive && src_family != dst_family) {
5398 /* This is an acquire or a release operation and there will be
5399 * a corresponding release/acquire. Do the transition in the
5400 * most flexible queue. */
5401
5402 assert(src_family == cmd_buffer->queue_family_index ||
5403 dst_family == cmd_buffer->queue_family_index);
5404
5405 if (src_family == VK_QUEUE_FAMILY_EXTERNAL ||
5406 src_family == VK_QUEUE_FAMILY_FOREIGN_EXT)
5407 return;
5408
5409 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
5410 return;
5411
5412 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
5413 (src_family == RADV_QUEUE_GENERAL ||
5414 dst_family == RADV_QUEUE_GENERAL))
5415 return;
5416 }
5417
5418 if (src_layout == dst_layout)
5419 return;
5420
5421 unsigned src_queue_mask =
5422 radv_image_queue_family_mask(image, src_family,
5423 cmd_buffer->queue_family_index);
5424 unsigned dst_queue_mask =
5425 radv_image_queue_family_mask(image, dst_family,
5426 cmd_buffer->queue_family_index);
5427
5428 if (vk_format_is_depth(image->vk_format)) {
5429 radv_handle_depth_image_transition(cmd_buffer, image,
5430 src_layout, src_render_loop,
5431 dst_layout, dst_render_loop,
5432 src_queue_mask, dst_queue_mask,
5433 range, sample_locs);
5434 } else {
5435 radv_handle_color_image_transition(cmd_buffer, image,
5436 src_layout, src_render_loop,
5437 dst_layout, dst_render_loop,
5438 src_queue_mask, dst_queue_mask,
5439 range);
5440 }
5441 }
5442
5443 struct radv_barrier_info {
5444 uint32_t eventCount;
5445 const VkEvent *pEvents;
5446 VkPipelineStageFlags srcStageMask;
5447 VkPipelineStageFlags dstStageMask;
5448 };
5449
5450 static void
5451 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
5452 uint32_t memoryBarrierCount,
5453 const VkMemoryBarrier *pMemoryBarriers,
5454 uint32_t bufferMemoryBarrierCount,
5455 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
5456 uint32_t imageMemoryBarrierCount,
5457 const VkImageMemoryBarrier *pImageMemoryBarriers,
5458 const struct radv_barrier_info *info)
5459 {
5460 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5461 enum radv_cmd_flush_bits src_flush_bits = 0;
5462 enum radv_cmd_flush_bits dst_flush_bits = 0;
5463
5464 for (unsigned i = 0; i < info->eventCount; ++i) {
5465 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
5466 uint64_t va = radv_buffer_get_va(event->bo);
5467
5468 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5469
5470 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
5471
5472 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
5473 assert(cmd_buffer->cs->cdw <= cdw_max);
5474 }
5475
5476 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
5477 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
5478 NULL);
5479 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
5480 NULL);
5481 }
5482
5483 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
5484 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
5485 NULL);
5486 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
5487 NULL);
5488 }
5489
5490 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5491 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5492
5493 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
5494 image);
5495 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
5496 image);
5497 }
5498
5499 /* The Vulkan spec 1.1.98 says:
5500 *
5501 * "An execution dependency with only
5502 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
5503 * will only prevent that stage from executing in subsequently
5504 * submitted commands. As this stage does not perform any actual
5505 * execution, this is not observable - in effect, it does not delay
5506 * processing of subsequent commands. Similarly an execution dependency
5507 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
5508 * will effectively not wait for any prior commands to complete."
5509 */
5510 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
5511 radv_stage_flush(cmd_buffer, info->srcStageMask);
5512 cmd_buffer->state.flush_bits |= src_flush_bits;
5513
5514 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5515 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5516
5517 const struct VkSampleLocationsInfoEXT *sample_locs_info =
5518 vk_find_struct_const(pImageMemoryBarriers[i].pNext,
5519 SAMPLE_LOCATIONS_INFO_EXT);
5520 struct radv_sample_locations_state sample_locations = {};
5521
5522 if (sample_locs_info) {
5523 assert(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
5524 sample_locations.per_pixel = sample_locs_info->sampleLocationsPerPixel;
5525 sample_locations.grid_size = sample_locs_info->sampleLocationGridSize;
5526 sample_locations.count = sample_locs_info->sampleLocationsCount;
5527 typed_memcpy(&sample_locations.locations[0],
5528 sample_locs_info->pSampleLocations,
5529 sample_locs_info->sampleLocationsCount);
5530 }
5531
5532 radv_handle_image_transition(cmd_buffer, image,
5533 pImageMemoryBarriers[i].oldLayout,
5534 false, /* Outside of a renderpass we are never in a renderloop */
5535 pImageMemoryBarriers[i].newLayout,
5536 false, /* Outside of a renderpass we are never in a renderloop */
5537 pImageMemoryBarriers[i].srcQueueFamilyIndex,
5538 pImageMemoryBarriers[i].dstQueueFamilyIndex,
5539 &pImageMemoryBarriers[i].subresourceRange,
5540 sample_locs_info ? &sample_locations : NULL);
5541 }
5542
5543 /* Make sure CP DMA is idle because the driver might have performed a
5544 * DMA operation for copying or filling buffers/images.
5545 */
5546 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5547 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5548 si_cp_dma_wait_for_idle(cmd_buffer);
5549
5550 cmd_buffer->state.flush_bits |= dst_flush_bits;
5551 }
5552
5553 void radv_CmdPipelineBarrier(
5554 VkCommandBuffer commandBuffer,
5555 VkPipelineStageFlags srcStageMask,
5556 VkPipelineStageFlags destStageMask,
5557 VkBool32 byRegion,
5558 uint32_t memoryBarrierCount,
5559 const VkMemoryBarrier* pMemoryBarriers,
5560 uint32_t bufferMemoryBarrierCount,
5561 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5562 uint32_t imageMemoryBarrierCount,
5563 const VkImageMemoryBarrier* pImageMemoryBarriers)
5564 {
5565 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5566 struct radv_barrier_info info;
5567
5568 info.eventCount = 0;
5569 info.pEvents = NULL;
5570 info.srcStageMask = srcStageMask;
5571 info.dstStageMask = destStageMask;
5572
5573 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5574 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5575 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5576 }
5577
5578
5579 static void write_event(struct radv_cmd_buffer *cmd_buffer,
5580 struct radv_event *event,
5581 VkPipelineStageFlags stageMask,
5582 unsigned value)
5583 {
5584 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5585 uint64_t va = radv_buffer_get_va(event->bo);
5586
5587 si_emit_cache_flush(cmd_buffer);
5588
5589 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5590
5591 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 21);
5592
5593 /* Flags that only require a top-of-pipe event. */
5594 VkPipelineStageFlags top_of_pipe_flags =
5595 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
5596
5597 /* Flags that only require a post-index-fetch event. */
5598 VkPipelineStageFlags post_index_fetch_flags =
5599 top_of_pipe_flags |
5600 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
5601 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
5602
5603 /* Make sure CP DMA is idle because the driver might have performed a
5604 * DMA operation for copying or filling buffers/images.
5605 */
5606 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5607 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5608 si_cp_dma_wait_for_idle(cmd_buffer);
5609
5610 /* TODO: Emit EOS events for syncing PS/CS stages. */
5611
5612 if (!(stageMask & ~top_of_pipe_flags)) {
5613 /* Just need to sync the PFP engine. */
5614 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5615 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5616 S_370_WR_CONFIRM(1) |
5617 S_370_ENGINE_SEL(V_370_PFP));
5618 radeon_emit(cs, va);
5619 radeon_emit(cs, va >> 32);
5620 radeon_emit(cs, value);
5621 } else if (!(stageMask & ~post_index_fetch_flags)) {
5622 /* Sync ME because PFP reads index and indirect buffers. */
5623 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5624 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5625 S_370_WR_CONFIRM(1) |
5626 S_370_ENGINE_SEL(V_370_ME));
5627 radeon_emit(cs, va);
5628 radeon_emit(cs, va >> 32);
5629 radeon_emit(cs, value);
5630 } else {
5631 /* Otherwise, sync all prior GPU work using an EOP event. */
5632 si_cs_emit_write_event_eop(cs,
5633 cmd_buffer->device->physical_device->rad_info.chip_class,
5634 radv_cmd_buffer_uses_mec(cmd_buffer),
5635 V_028A90_BOTTOM_OF_PIPE_TS, 0,
5636 EOP_DST_SEL_MEM,
5637 EOP_DATA_SEL_VALUE_32BIT, va, value,
5638 cmd_buffer->gfx9_eop_bug_va);
5639 }
5640
5641 assert(cmd_buffer->cs->cdw <= cdw_max);
5642 }
5643
5644 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
5645 VkEvent _event,
5646 VkPipelineStageFlags stageMask)
5647 {
5648 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5649 RADV_FROM_HANDLE(radv_event, event, _event);
5650
5651 write_event(cmd_buffer, event, stageMask, 1);
5652 }
5653
5654 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
5655 VkEvent _event,
5656 VkPipelineStageFlags stageMask)
5657 {
5658 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5659 RADV_FROM_HANDLE(radv_event, event, _event);
5660
5661 write_event(cmd_buffer, event, stageMask, 0);
5662 }
5663
5664 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
5665 uint32_t eventCount,
5666 const VkEvent* pEvents,
5667 VkPipelineStageFlags srcStageMask,
5668 VkPipelineStageFlags dstStageMask,
5669 uint32_t memoryBarrierCount,
5670 const VkMemoryBarrier* pMemoryBarriers,
5671 uint32_t bufferMemoryBarrierCount,
5672 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5673 uint32_t imageMemoryBarrierCount,
5674 const VkImageMemoryBarrier* pImageMemoryBarriers)
5675 {
5676 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5677 struct radv_barrier_info info;
5678
5679 info.eventCount = eventCount;
5680 info.pEvents = pEvents;
5681 info.srcStageMask = 0;
5682
5683 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5684 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5685 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5686 }
5687
5688
5689 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
5690 uint32_t deviceMask)
5691 {
5692 /* No-op */
5693 }
5694
5695 /* VK_EXT_conditional_rendering */
5696 void radv_CmdBeginConditionalRenderingEXT(
5697 VkCommandBuffer commandBuffer,
5698 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
5699 {
5700 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5701 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
5702 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5703 bool draw_visible = true;
5704 uint64_t pred_value = 0;
5705 uint64_t va, new_va;
5706 unsigned pred_offset;
5707
5708 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
5709
5710 /* By default, if the 32-bit value at offset in buffer memory is zero,
5711 * then the rendering commands are discarded, otherwise they are
5712 * executed as normal. If the inverted flag is set, all commands are
5713 * discarded if the value is non zero.
5714 */
5715 if (pConditionalRenderingBegin->flags &
5716 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
5717 draw_visible = false;
5718 }
5719
5720 si_emit_cache_flush(cmd_buffer);
5721
5722 /* From the Vulkan spec 1.1.107:
5723 *
5724 * "If the 32-bit value at offset in buffer memory is zero, then the
5725 * rendering commands are discarded, otherwise they are executed as
5726 * normal. If the value of the predicate in buffer memory changes while
5727 * conditional rendering is active, the rendering commands may be
5728 * discarded in an implementation-dependent way. Some implementations
5729 * may latch the value of the predicate upon beginning conditional
5730 * rendering while others may read it before every rendering command."
5731 *
5732 * But, the AMD hardware treats the predicate as a 64-bit value which
5733 * means we need a workaround in the driver. Luckily, it's not required
5734 * to support if the value changes when predication is active.
5735 *
5736 * The workaround is as follows:
5737 * 1) allocate a 64-value in the upload BO and initialize it to 0
5738 * 2) copy the 32-bit predicate value to the upload BO
5739 * 3) use the new allocated VA address for predication
5740 *
5741 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
5742 * in ME (+ sync PFP) instead of PFP.
5743 */
5744 radv_cmd_buffer_upload_data(cmd_buffer, 8, 16, &pred_value, &pred_offset);
5745
5746 new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
5747
5748 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5749 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5750 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
5751 COPY_DATA_WR_CONFIRM);
5752 radeon_emit(cs, va);
5753 radeon_emit(cs, va >> 32);
5754 radeon_emit(cs, new_va);
5755 radeon_emit(cs, new_va >> 32);
5756
5757 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
5758 radeon_emit(cs, 0);
5759
5760 /* Enable predication for this command buffer. */
5761 si_emit_set_predication_state(cmd_buffer, draw_visible, new_va);
5762 cmd_buffer->state.predicating = true;
5763
5764 /* Store conditional rendering user info. */
5765 cmd_buffer->state.predication_type = draw_visible;
5766 cmd_buffer->state.predication_va = new_va;
5767 }
5768
5769 void radv_CmdEndConditionalRenderingEXT(
5770 VkCommandBuffer commandBuffer)
5771 {
5772 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5773
5774 /* Disable predication for this command buffer. */
5775 si_emit_set_predication_state(cmd_buffer, false, 0);
5776 cmd_buffer->state.predicating = false;
5777
5778 /* Reset conditional rendering user info. */
5779 cmd_buffer->state.predication_type = -1;
5780 cmd_buffer->state.predication_va = 0;
5781 }
5782
5783 /* VK_EXT_transform_feedback */
5784 void radv_CmdBindTransformFeedbackBuffersEXT(
5785 VkCommandBuffer commandBuffer,
5786 uint32_t firstBinding,
5787 uint32_t bindingCount,
5788 const VkBuffer* pBuffers,
5789 const VkDeviceSize* pOffsets,
5790 const VkDeviceSize* pSizes)
5791 {
5792 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5793 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5794 uint8_t enabled_mask = 0;
5795
5796 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
5797 for (uint32_t i = 0; i < bindingCount; i++) {
5798 uint32_t idx = firstBinding + i;
5799
5800 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
5801 sb[idx].offset = pOffsets[i];
5802 sb[idx].size = pSizes[i];
5803
5804 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
5805 sb[idx].buffer->bo);
5806
5807 enabled_mask |= 1 << idx;
5808 }
5809
5810 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
5811
5812 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
5813 }
5814
5815 static void
5816 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
5817 {
5818 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5819 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5820
5821 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
5822 radeon_emit(cs,
5823 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
5824 S_028B94_RAST_STREAM(0) |
5825 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
5826 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
5827 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
5828 radeon_emit(cs, so->hw_enabled_mask &
5829 so->enabled_stream_buffers_mask);
5830
5831 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5832 }
5833
5834 static void
5835 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
5836 {
5837 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5838 bool old_streamout_enabled = so->streamout_enabled;
5839 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
5840
5841 so->streamout_enabled = enable;
5842
5843 so->hw_enabled_mask = so->enabled_mask |
5844 (so->enabled_mask << 4) |
5845 (so->enabled_mask << 8) |
5846 (so->enabled_mask << 12);
5847
5848 if (!cmd_buffer->device->physical_device->use_ngg_streamout &&
5849 ((old_streamout_enabled != so->streamout_enabled) ||
5850 (old_hw_enabled_mask != so->hw_enabled_mask)))
5851 radv_emit_streamout_enable(cmd_buffer);
5852
5853 if (cmd_buffer->device->physical_device->use_ngg_streamout)
5854 cmd_buffer->gds_needed = true;
5855 }
5856
5857 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
5858 {
5859 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5860 unsigned reg_strmout_cntl;
5861
5862 /* The register is at different places on different ASICs. */
5863 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
5864 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
5865 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
5866 } else {
5867 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
5868 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
5869 }
5870
5871 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
5872 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
5873
5874 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
5875 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
5876 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
5877 radeon_emit(cs, 0);
5878 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
5879 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
5880 radeon_emit(cs, 4); /* poll interval */
5881 }
5882
5883 static void
5884 radv_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
5885 uint32_t firstCounterBuffer,
5886 uint32_t counterBufferCount,
5887 const VkBuffer *pCounterBuffers,
5888 const VkDeviceSize *pCounterBufferOffsets)
5889
5890 {
5891 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5892 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5893 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5894 uint32_t i;
5895
5896 radv_flush_vgt_streamout(cmd_buffer);
5897
5898 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5899 for_each_bit(i, so->enabled_mask) {
5900 int32_t counter_buffer_idx = i - firstCounterBuffer;
5901 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5902 counter_buffer_idx = -1;
5903
5904 /* AMD GCN binds streamout buffers as shader resources.
5905 * VGT only counts primitives and tells the shader through
5906 * SGPRs what to do.
5907 */
5908 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
5909 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
5910 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
5911
5912 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5913
5914 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5915 /* The array of counter buffers is optional. */
5916 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5917 uint64_t va = radv_buffer_get_va(buffer->bo);
5918
5919 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5920
5921 /* Append */
5922 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5923 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5924 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5925 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
5926 radeon_emit(cs, 0); /* unused */
5927 radeon_emit(cs, 0); /* unused */
5928 radeon_emit(cs, va); /* src address lo */
5929 radeon_emit(cs, va >> 32); /* src address hi */
5930
5931 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5932 } else {
5933 /* Start from the beginning. */
5934 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5935 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5936 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5937 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
5938 radeon_emit(cs, 0); /* unused */
5939 radeon_emit(cs, 0); /* unused */
5940 radeon_emit(cs, 0); /* unused */
5941 radeon_emit(cs, 0); /* unused */
5942 }
5943 }
5944
5945 radv_set_streamout_enable(cmd_buffer, true);
5946 }
5947
5948 static void
5949 gfx10_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
5950 uint32_t firstCounterBuffer,
5951 uint32_t counterBufferCount,
5952 const VkBuffer *pCounterBuffers,
5953 const VkDeviceSize *pCounterBufferOffsets)
5954 {
5955 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5956 unsigned last_target = util_last_bit(so->enabled_mask) - 1;
5957 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5958 uint32_t i;
5959
5960 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
5961 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5962
5963 /* Sync because the next streamout operation will overwrite GDS and we
5964 * have to make sure it's idle.
5965 * TODO: Improve by tracking if there is a streamout operation in
5966 * flight.
5967 */
5968 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
5969 si_emit_cache_flush(cmd_buffer);
5970
5971 for_each_bit(i, so->enabled_mask) {
5972 int32_t counter_buffer_idx = i - firstCounterBuffer;
5973 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5974 counter_buffer_idx = -1;
5975
5976 bool append = counter_buffer_idx >= 0 &&
5977 pCounterBuffers && pCounterBuffers[counter_buffer_idx];
5978 uint64_t va = 0;
5979
5980 if (append) {
5981 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5982
5983 va += radv_buffer_get_va(buffer->bo);
5984 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5985
5986 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5987 }
5988
5989 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
5990 radeon_emit(cs, S_411_SRC_SEL(append ? V_411_SRC_ADDR_TC_L2 : V_411_DATA) |
5991 S_411_DST_SEL(V_411_GDS) |
5992 S_411_CP_SYNC(i == last_target));
5993 radeon_emit(cs, va);
5994 radeon_emit(cs, va >> 32);
5995 radeon_emit(cs, 4 * i); /* destination in GDS */
5996 radeon_emit(cs, 0);
5997 radeon_emit(cs, S_414_BYTE_COUNT_GFX9(4) |
5998 S_414_DISABLE_WR_CONFIRM_GFX9(i != last_target));
5999 }
6000
6001 radv_set_streamout_enable(cmd_buffer, true);
6002 }
6003
6004 void radv_CmdBeginTransformFeedbackEXT(
6005 VkCommandBuffer commandBuffer,
6006 uint32_t firstCounterBuffer,
6007 uint32_t counterBufferCount,
6008 const VkBuffer* pCounterBuffers,
6009 const VkDeviceSize* pCounterBufferOffsets)
6010 {
6011 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6012
6013 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6014 gfx10_emit_streamout_begin(cmd_buffer,
6015 firstCounterBuffer, counterBufferCount,
6016 pCounterBuffers, pCounterBufferOffsets);
6017 } else {
6018 radv_emit_streamout_begin(cmd_buffer,
6019 firstCounterBuffer, counterBufferCount,
6020 pCounterBuffers, pCounterBufferOffsets);
6021 }
6022 }
6023
6024 static void
6025 radv_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6026 uint32_t firstCounterBuffer,
6027 uint32_t counterBufferCount,
6028 const VkBuffer *pCounterBuffers,
6029 const VkDeviceSize *pCounterBufferOffsets)
6030 {
6031 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6032 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6033 uint32_t i;
6034
6035 radv_flush_vgt_streamout(cmd_buffer);
6036
6037 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6038 for_each_bit(i, so->enabled_mask) {
6039 int32_t counter_buffer_idx = i - firstCounterBuffer;
6040 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6041 counter_buffer_idx = -1;
6042
6043 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6044 /* The array of counters buffer is optional. */
6045 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6046 uint64_t va = radv_buffer_get_va(buffer->bo);
6047
6048 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6049
6050 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6051 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6052 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6053 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
6054 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
6055 radeon_emit(cs, va); /* dst address lo */
6056 radeon_emit(cs, va >> 32); /* dst address hi */
6057 radeon_emit(cs, 0); /* unused */
6058 radeon_emit(cs, 0); /* unused */
6059
6060 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6061 }
6062
6063 /* Deactivate transform feedback by zeroing the buffer size.
6064 * The counters (primitives generated, primitives emitted) may
6065 * be enabled even if there is not buffer bound. This ensures
6066 * that the primitives-emitted query won't increment.
6067 */
6068 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
6069
6070 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6071 }
6072
6073 radv_set_streamout_enable(cmd_buffer, false);
6074 }
6075
6076 static void
6077 gfx10_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6078 uint32_t firstCounterBuffer,
6079 uint32_t counterBufferCount,
6080 const VkBuffer *pCounterBuffers,
6081 const VkDeviceSize *pCounterBufferOffsets)
6082 {
6083 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6084 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6085 uint32_t i;
6086
6087 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6088 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6089
6090 for_each_bit(i, so->enabled_mask) {
6091 int32_t counter_buffer_idx = i - firstCounterBuffer;
6092 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6093 counter_buffer_idx = -1;
6094
6095 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6096 /* The array of counters buffer is optional. */
6097 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6098 uint64_t va = radv_buffer_get_va(buffer->bo);
6099
6100 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6101
6102 si_cs_emit_write_event_eop(cs,
6103 cmd_buffer->device->physical_device->rad_info.chip_class,
6104 radv_cmd_buffer_uses_mec(cmd_buffer),
6105 V_028A90_PS_DONE, 0,
6106 EOP_DST_SEL_TC_L2,
6107 EOP_DATA_SEL_GDS,
6108 va, EOP_DATA_GDS(i, 1), 0);
6109
6110 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6111 }
6112 }
6113
6114 radv_set_streamout_enable(cmd_buffer, false);
6115 }
6116
6117 void radv_CmdEndTransformFeedbackEXT(
6118 VkCommandBuffer commandBuffer,
6119 uint32_t firstCounterBuffer,
6120 uint32_t counterBufferCount,
6121 const VkBuffer* pCounterBuffers,
6122 const VkDeviceSize* pCounterBufferOffsets)
6123 {
6124 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6125
6126 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6127 gfx10_emit_streamout_end(cmd_buffer,
6128 firstCounterBuffer, counterBufferCount,
6129 pCounterBuffers, pCounterBufferOffsets);
6130 } else {
6131 radv_emit_streamout_end(cmd_buffer,
6132 firstCounterBuffer, counterBufferCount,
6133 pCounterBuffers, pCounterBufferOffsets);
6134 }
6135 }
6136
6137 void radv_CmdDrawIndirectByteCountEXT(
6138 VkCommandBuffer commandBuffer,
6139 uint32_t instanceCount,
6140 uint32_t firstInstance,
6141 VkBuffer _counterBuffer,
6142 VkDeviceSize counterBufferOffset,
6143 uint32_t counterOffset,
6144 uint32_t vertexStride)
6145 {
6146 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6147 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
6148 struct radv_draw_info info = {};
6149
6150 info.instance_count = instanceCount;
6151 info.first_instance = firstInstance;
6152 info.strmout_buffer = counterBuffer;
6153 info.strmout_buffer_offset = counterBufferOffset;
6154 info.stride = vertexStride;
6155
6156 radv_draw(cmd_buffer, &info);
6157 }
6158
6159 /* VK_AMD_buffer_marker */
6160 void radv_CmdWriteBufferMarkerAMD(
6161 VkCommandBuffer commandBuffer,
6162 VkPipelineStageFlagBits pipelineStage,
6163 VkBuffer dstBuffer,
6164 VkDeviceSize dstOffset,
6165 uint32_t marker)
6166 {
6167 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6168 RADV_FROM_HANDLE(radv_buffer, buffer, dstBuffer);
6169 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6170 uint64_t va = radv_buffer_get_va(buffer->bo) + dstOffset;
6171
6172 si_emit_cache_flush(cmd_buffer);
6173
6174 if (!(pipelineStage & ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT)) {
6175 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
6176 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
6177 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
6178 COPY_DATA_WR_CONFIRM);
6179 radeon_emit(cs, marker);
6180 radeon_emit(cs, 0);
6181 radeon_emit(cs, va);
6182 radeon_emit(cs, va >> 32);
6183 } else {
6184 si_cs_emit_write_event_eop(cs,
6185 cmd_buffer->device->physical_device->rad_info.chip_class,
6186 radv_cmd_buffer_uses_mec(cmd_buffer),
6187 V_028A90_BOTTOM_OF_PIPE_TS, 0,
6188 EOP_DST_SEL_MEM,
6189 EOP_DATA_SEL_VALUE_32BIT,
6190 va, marker,
6191 cmd_buffer->gfx9_eop_bug_va);
6192 }
6193 }