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radv/gfx10: add an option to switch from legacy to NGG streamout
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 bool src_render_loop,
58 VkImageLayout dst_layout,
59 bool dst_render_loop,
60 uint32_t src_family,
61 uint32_t dst_family,
62 const VkImageSubresourceRange *range,
63 struct radv_sample_locations_state *sample_locs);
64
65 const struct radv_dynamic_state default_dynamic_state = {
66 .viewport = {
67 .count = 0,
68 },
69 .scissor = {
70 .count = 0,
71 },
72 .line_width = 1.0f,
73 .depth_bias = {
74 .bias = 0.0f,
75 .clamp = 0.0f,
76 .slope = 0.0f,
77 },
78 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
79 .depth_bounds = {
80 .min = 0.0f,
81 .max = 1.0f,
82 },
83 .stencil_compare_mask = {
84 .front = ~0u,
85 .back = ~0u,
86 },
87 .stencil_write_mask = {
88 .front = ~0u,
89 .back = ~0u,
90 },
91 .stencil_reference = {
92 .front = 0u,
93 .back = 0u,
94 },
95 };
96
97 static void
98 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
99 const struct radv_dynamic_state *src)
100 {
101 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
102 uint32_t copy_mask = src->mask;
103 uint32_t dest_mask = 0;
104
105 /* Make sure to copy the number of viewports/scissors because they can
106 * only be specified at pipeline creation time.
107 */
108 dest->viewport.count = src->viewport.count;
109 dest->scissor.count = src->scissor.count;
110 dest->discard_rectangle.count = src->discard_rectangle.count;
111 dest->sample_location.count = src->sample_location.count;
112
113 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
114 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
115 src->viewport.count * sizeof(VkViewport))) {
116 typed_memcpy(dest->viewport.viewports,
117 src->viewport.viewports,
118 src->viewport.count);
119 dest_mask |= RADV_DYNAMIC_VIEWPORT;
120 }
121 }
122
123 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
124 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
125 src->scissor.count * sizeof(VkRect2D))) {
126 typed_memcpy(dest->scissor.scissors,
127 src->scissor.scissors, src->scissor.count);
128 dest_mask |= RADV_DYNAMIC_SCISSOR;
129 }
130 }
131
132 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
133 if (dest->line_width != src->line_width) {
134 dest->line_width = src->line_width;
135 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
136 }
137 }
138
139 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
140 if (memcmp(&dest->depth_bias, &src->depth_bias,
141 sizeof(src->depth_bias))) {
142 dest->depth_bias = src->depth_bias;
143 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
144 }
145 }
146
147 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
148 if (memcmp(&dest->blend_constants, &src->blend_constants,
149 sizeof(src->blend_constants))) {
150 typed_memcpy(dest->blend_constants,
151 src->blend_constants, 4);
152 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
153 }
154 }
155
156 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
157 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
158 sizeof(src->depth_bounds))) {
159 dest->depth_bounds = src->depth_bounds;
160 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
161 }
162 }
163
164 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
165 if (memcmp(&dest->stencil_compare_mask,
166 &src->stencil_compare_mask,
167 sizeof(src->stencil_compare_mask))) {
168 dest->stencil_compare_mask = src->stencil_compare_mask;
169 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
170 }
171 }
172
173 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
174 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
175 sizeof(src->stencil_write_mask))) {
176 dest->stencil_write_mask = src->stencil_write_mask;
177 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
178 }
179 }
180
181 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
182 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
183 sizeof(src->stencil_reference))) {
184 dest->stencil_reference = src->stencil_reference;
185 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
186 }
187 }
188
189 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
190 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
191 src->discard_rectangle.count * sizeof(VkRect2D))) {
192 typed_memcpy(dest->discard_rectangle.rectangles,
193 src->discard_rectangle.rectangles,
194 src->discard_rectangle.count);
195 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
196 }
197 }
198
199 if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
200 if (dest->sample_location.per_pixel != src->sample_location.per_pixel ||
201 dest->sample_location.grid_size.width != src->sample_location.grid_size.width ||
202 dest->sample_location.grid_size.height != src->sample_location.grid_size.height ||
203 memcmp(&dest->sample_location.locations,
204 &src->sample_location.locations,
205 src->sample_location.count * sizeof(VkSampleLocationEXT))) {
206 dest->sample_location.per_pixel = src->sample_location.per_pixel;
207 dest->sample_location.grid_size = src->sample_location.grid_size;
208 typed_memcpy(dest->sample_location.locations,
209 src->sample_location.locations,
210 src->sample_location.count);
211 dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
212 }
213 }
214
215 cmd_buffer->state.dirty |= dest_mask;
216 }
217
218 static void
219 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
220 struct radv_pipeline *pipeline)
221 {
222 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
223 struct radv_shader_info *info;
224
225 if (!pipeline->streamout_shader ||
226 cmd_buffer->device->physical_device->use_ngg_streamout)
227 return;
228
229 info = &pipeline->streamout_shader->info;
230 for (int i = 0; i < MAX_SO_BUFFERS; i++)
231 so->stride_in_dw[i] = info->so.strides[i];
232
233 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
234 }
235
236 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
237 {
238 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
239 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
240 }
241
242 enum ring_type radv_queue_family_to_ring(int f) {
243 switch (f) {
244 case RADV_QUEUE_GENERAL:
245 return RING_GFX;
246 case RADV_QUEUE_COMPUTE:
247 return RING_COMPUTE;
248 case RADV_QUEUE_TRANSFER:
249 return RING_DMA;
250 default:
251 unreachable("Unknown queue family");
252 }
253 }
254
255 static VkResult radv_create_cmd_buffer(
256 struct radv_device * device,
257 struct radv_cmd_pool * pool,
258 VkCommandBufferLevel level,
259 VkCommandBuffer* pCommandBuffer)
260 {
261 struct radv_cmd_buffer *cmd_buffer;
262 unsigned ring;
263 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
264 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
265 if (cmd_buffer == NULL)
266 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
267
268 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
269 cmd_buffer->device = device;
270 cmd_buffer->pool = pool;
271 cmd_buffer->level = level;
272
273 if (pool) {
274 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
275 cmd_buffer->queue_family_index = pool->queue_family_index;
276
277 } else {
278 /* Init the pool_link so we can safely call list_del when we destroy
279 * the command buffer
280 */
281 list_inithead(&cmd_buffer->pool_link);
282 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
283 }
284
285 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
286
287 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
288 if (!cmd_buffer->cs) {
289 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
290 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
291 }
292
293 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
294
295 list_inithead(&cmd_buffer->upload.list);
296
297 return VK_SUCCESS;
298 }
299
300 static void
301 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
302 {
303 list_del(&cmd_buffer->pool_link);
304
305 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
306 &cmd_buffer->upload.list, list) {
307 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
308 list_del(&up->list);
309 free(up);
310 }
311
312 if (cmd_buffer->upload.upload_bo)
313 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
314 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
315
316 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
317 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
318
319 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
320 }
321
322 static VkResult
323 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
324 {
325 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
326
327 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
328 &cmd_buffer->upload.list, list) {
329 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
330 list_del(&up->list);
331 free(up);
332 }
333
334 cmd_buffer->push_constant_stages = 0;
335 cmd_buffer->scratch_size_needed = 0;
336 cmd_buffer->compute_scratch_size_needed = 0;
337 cmd_buffer->esgs_ring_size_needed = 0;
338 cmd_buffer->gsvs_ring_size_needed = 0;
339 cmd_buffer->tess_rings_needed = false;
340 cmd_buffer->sample_positions_needed = false;
341
342 if (cmd_buffer->upload.upload_bo)
343 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
344 cmd_buffer->upload.upload_bo);
345 cmd_buffer->upload.offset = 0;
346
347 cmd_buffer->record_result = VK_SUCCESS;
348
349 memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
350
351 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
352 cmd_buffer->descriptors[i].dirty = 0;
353 cmd_buffer->descriptors[i].valid = 0;
354 cmd_buffer->descriptors[i].push_dirty = false;
355 }
356
357 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
358 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
359 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
360 unsigned fence_offset, eop_bug_offset;
361 void *fence_ptr;
362
363 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
364 &fence_ptr);
365
366 cmd_buffer->gfx9_fence_va =
367 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
368 cmd_buffer->gfx9_fence_va += fence_offset;
369
370 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
371 /* Allocate a buffer for the EOP bug on GFX9. */
372 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
373 &eop_bug_offset, &fence_ptr);
374 cmd_buffer->gfx9_eop_bug_va =
375 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
376 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
377 }
378 }
379
380 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
381
382 return cmd_buffer->record_result;
383 }
384
385 static bool
386 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
387 uint64_t min_needed)
388 {
389 uint64_t new_size;
390 struct radeon_winsys_bo *bo;
391 struct radv_cmd_buffer_upload *upload;
392 struct radv_device *device = cmd_buffer->device;
393
394 new_size = MAX2(min_needed, 16 * 1024);
395 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
396
397 bo = device->ws->buffer_create(device->ws,
398 new_size, 4096,
399 RADEON_DOMAIN_GTT,
400 RADEON_FLAG_CPU_ACCESS|
401 RADEON_FLAG_NO_INTERPROCESS_SHARING |
402 RADEON_FLAG_32BIT,
403 RADV_BO_PRIORITY_UPLOAD_BUFFER);
404
405 if (!bo) {
406 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
407 return false;
408 }
409
410 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
411 if (cmd_buffer->upload.upload_bo) {
412 upload = malloc(sizeof(*upload));
413
414 if (!upload) {
415 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
416 device->ws->buffer_destroy(bo);
417 return false;
418 }
419
420 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
421 list_add(&upload->list, &cmd_buffer->upload.list);
422 }
423
424 cmd_buffer->upload.upload_bo = bo;
425 cmd_buffer->upload.size = new_size;
426 cmd_buffer->upload.offset = 0;
427 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
428
429 if (!cmd_buffer->upload.map) {
430 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
431 return false;
432 }
433
434 return true;
435 }
436
437 bool
438 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
439 unsigned size,
440 unsigned alignment,
441 unsigned *out_offset,
442 void **ptr)
443 {
444 assert(util_is_power_of_two_nonzero(alignment));
445
446 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
447 if (offset + size > cmd_buffer->upload.size) {
448 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
449 return false;
450 offset = 0;
451 }
452
453 *out_offset = offset;
454 *ptr = cmd_buffer->upload.map + offset;
455
456 cmd_buffer->upload.offset = offset + size;
457 return true;
458 }
459
460 bool
461 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
462 unsigned size, unsigned alignment,
463 const void *data, unsigned *out_offset)
464 {
465 uint8_t *ptr;
466
467 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
468 out_offset, (void **)&ptr))
469 return false;
470
471 if (ptr)
472 memcpy(ptr, data, size);
473
474 return true;
475 }
476
477 static void
478 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
479 unsigned count, const uint32_t *data)
480 {
481 struct radeon_cmdbuf *cs = cmd_buffer->cs;
482
483 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
484
485 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
486 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
487 S_370_WR_CONFIRM(1) |
488 S_370_ENGINE_SEL(V_370_ME));
489 radeon_emit(cs, va);
490 radeon_emit(cs, va >> 32);
491 radeon_emit_array(cs, data, count);
492 }
493
494 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
495 {
496 struct radv_device *device = cmd_buffer->device;
497 struct radeon_cmdbuf *cs = cmd_buffer->cs;
498 uint64_t va;
499
500 va = radv_buffer_get_va(device->trace_bo);
501 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
502 va += 4;
503
504 ++cmd_buffer->state.trace_id;
505 radv_emit_write_data_packet(cmd_buffer, va, 1,
506 &cmd_buffer->state.trace_id);
507
508 radeon_check_space(cmd_buffer->device->ws, cs, 2);
509
510 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
511 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
512 }
513
514 static void
515 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
516 enum radv_cmd_flush_bits flags)
517 {
518 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
519 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
520 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
521
522 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
523
524 /* Force wait for graphics or compute engines to be idle. */
525 si_cs_emit_cache_flush(cmd_buffer->cs,
526 cmd_buffer->device->physical_device->rad_info.chip_class,
527 &cmd_buffer->gfx9_fence_idx,
528 cmd_buffer->gfx9_fence_va,
529 radv_cmd_buffer_uses_mec(cmd_buffer),
530 flags, cmd_buffer->gfx9_eop_bug_va);
531 }
532
533 if (unlikely(cmd_buffer->device->trace_bo))
534 radv_cmd_buffer_trace_emit(cmd_buffer);
535 }
536
537 static void
538 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
539 struct radv_pipeline *pipeline, enum ring_type ring)
540 {
541 struct radv_device *device = cmd_buffer->device;
542 uint32_t data[2];
543 uint64_t va;
544
545 va = radv_buffer_get_va(device->trace_bo);
546
547 switch (ring) {
548 case RING_GFX:
549 va += 8;
550 break;
551 case RING_COMPUTE:
552 va += 16;
553 break;
554 default:
555 assert(!"invalid ring type");
556 }
557
558 data[0] = (uintptr_t)pipeline;
559 data[1] = (uintptr_t)pipeline >> 32;
560
561 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
562 }
563
564 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
565 VkPipelineBindPoint bind_point,
566 struct radv_descriptor_set *set,
567 unsigned idx)
568 {
569 struct radv_descriptor_state *descriptors_state =
570 radv_get_descriptors_state(cmd_buffer, bind_point);
571
572 descriptors_state->sets[idx] = set;
573
574 descriptors_state->valid |= (1u << idx); /* active descriptors */
575 descriptors_state->dirty |= (1u << idx);
576 }
577
578 static void
579 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
580 VkPipelineBindPoint bind_point)
581 {
582 struct radv_descriptor_state *descriptors_state =
583 radv_get_descriptors_state(cmd_buffer, bind_point);
584 struct radv_device *device = cmd_buffer->device;
585 uint32_t data[MAX_SETS * 2] = {};
586 uint64_t va;
587 unsigned i;
588 va = radv_buffer_get_va(device->trace_bo) + 24;
589
590 for_each_bit(i, descriptors_state->valid) {
591 struct radv_descriptor_set *set = descriptors_state->sets[i];
592 data[i * 2] = (uint64_t)(uintptr_t)set;
593 data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
594 }
595
596 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
597 }
598
599 struct radv_userdata_info *
600 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
601 gl_shader_stage stage,
602 int idx)
603 {
604 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
605 return &shader->info.user_sgprs_locs.shader_data[idx];
606 }
607
608 static void
609 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
610 struct radv_pipeline *pipeline,
611 gl_shader_stage stage,
612 int idx, uint64_t va)
613 {
614 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
615 uint32_t base_reg = pipeline->user_data_0[stage];
616 if (loc->sgpr_idx == -1)
617 return;
618
619 assert(loc->num_sgprs == 1);
620
621 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
622 base_reg + loc->sgpr_idx * 4, va, false);
623 }
624
625 static void
626 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
627 struct radv_pipeline *pipeline,
628 struct radv_descriptor_state *descriptors_state,
629 gl_shader_stage stage)
630 {
631 struct radv_device *device = cmd_buffer->device;
632 struct radeon_cmdbuf *cs = cmd_buffer->cs;
633 uint32_t sh_base = pipeline->user_data_0[stage];
634 struct radv_userdata_locations *locs =
635 &pipeline->shaders[stage]->info.user_sgprs_locs;
636 unsigned mask = locs->descriptor_sets_enabled;
637
638 mask &= descriptors_state->dirty & descriptors_state->valid;
639
640 while (mask) {
641 int start, count;
642
643 u_bit_scan_consecutive_range(&mask, &start, &count);
644
645 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
646 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
647
648 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
649 for (int i = 0; i < count; i++) {
650 struct radv_descriptor_set *set =
651 descriptors_state->sets[start + i];
652
653 radv_emit_shader_pointer_body(device, cs, set->va, true);
654 }
655 }
656 }
657
658 /**
659 * Convert the user sample locations to hardware sample locations (the values
660 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
661 */
662 static void
663 radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
664 uint32_t x, uint32_t y, VkOffset2D *sample_locs)
665 {
666 uint32_t x_offset = x % state->grid_size.width;
667 uint32_t y_offset = y % state->grid_size.height;
668 uint32_t num_samples = (uint32_t)state->per_pixel;
669 VkSampleLocationEXT *user_locs;
670 uint32_t pixel_offset;
671
672 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
673
674 assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
675 user_locs = &state->locations[pixel_offset];
676
677 for (uint32_t i = 0; i < num_samples; i++) {
678 float shifted_pos_x = user_locs[i].x - 0.5;
679 float shifted_pos_y = user_locs[i].y - 0.5;
680
681 int32_t scaled_pos_x = floor(shifted_pos_x * 16);
682 int32_t scaled_pos_y = floor(shifted_pos_y * 16);
683
684 sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
685 sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
686 }
687 }
688
689 /**
690 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
691 * locations.
692 */
693 static void
694 radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
695 uint32_t *sample_locs_pixel)
696 {
697 for (uint32_t i = 0; i < num_samples; i++) {
698 uint32_t sample_reg_idx = i / 4;
699 uint32_t sample_loc_idx = i % 4;
700 int32_t pos_x = sample_locs[i].x;
701 int32_t pos_y = sample_locs[i].y;
702
703 uint32_t shift_x = 8 * sample_loc_idx;
704 uint32_t shift_y = shift_x + 4;
705
706 sample_locs_pixel[sample_reg_idx] |= (pos_x & 0xf) << shift_x;
707 sample_locs_pixel[sample_reg_idx] |= (pos_y & 0xf) << shift_y;
708 }
709 }
710
711 /**
712 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
713 * sample locations.
714 */
715 static uint64_t
716 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer,
717 VkOffset2D *sample_locs,
718 uint32_t num_samples)
719 {
720 uint32_t centroid_priorities[num_samples];
721 uint32_t sample_mask = num_samples - 1;
722 uint32_t distances[num_samples];
723 uint64_t centroid_priority = 0;
724
725 /* Compute the distances from center for each sample. */
726 for (int i = 0; i < num_samples; i++) {
727 distances[i] = (sample_locs[i].x * sample_locs[i].x) +
728 (sample_locs[i].y * sample_locs[i].y);
729 }
730
731 /* Compute the centroid priorities by looking at the distances array. */
732 for (int i = 0; i < num_samples; i++) {
733 uint32_t min_idx = 0;
734
735 for (int j = 1; j < num_samples; j++) {
736 if (distances[j] < distances[min_idx])
737 min_idx = j;
738 }
739
740 centroid_priorities[i] = min_idx;
741 distances[min_idx] = 0xffffffff;
742 }
743
744 /* Compute the final centroid priority. */
745 for (int i = 0; i < 8; i++) {
746 centroid_priority |=
747 centroid_priorities[i & sample_mask] << (i * 4);
748 }
749
750 return centroid_priority << 32 | centroid_priority;
751 }
752
753 /**
754 * Emit the sample locations that are specified with VK_EXT_sample_locations.
755 */
756 static void
757 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
758 {
759 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
760 struct radv_multisample_state *ms = &pipeline->graphics.ms;
761 struct radv_sample_locations_state *sample_location =
762 &cmd_buffer->state.dynamic.sample_location;
763 uint32_t num_samples = (uint32_t)sample_location->per_pixel;
764 struct radeon_cmdbuf *cs = cmd_buffer->cs;
765 uint32_t sample_locs_pixel[4][2] = {};
766 VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
767 uint32_t max_sample_dist = 0;
768 uint64_t centroid_priority;
769
770 if (!cmd_buffer->state.dynamic.sample_location.count)
771 return;
772
773 /* Convert the user sample locations to hardware sample locations. */
774 radv_convert_user_sample_locs(sample_location, 0, 0, sample_locs[0]);
775 radv_convert_user_sample_locs(sample_location, 1, 0, sample_locs[1]);
776 radv_convert_user_sample_locs(sample_location, 0, 1, sample_locs[2]);
777 radv_convert_user_sample_locs(sample_location, 1, 1, sample_locs[3]);
778
779 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
780 for (uint32_t i = 0; i < 4; i++) {
781 radv_compute_sample_locs_pixel(num_samples, sample_locs[i],
782 sample_locs_pixel[i]);
783 }
784
785 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
786 centroid_priority =
787 radv_compute_centroid_priority(cmd_buffer, sample_locs[0],
788 num_samples);
789
790 /* Compute the maximum sample distance from the specified locations. */
791 for (uint32_t i = 0; i < num_samples; i++) {
792 VkOffset2D offset = sample_locs[0][i];
793 max_sample_dist = MAX2(max_sample_dist,
794 MAX2(abs(offset.x), abs(offset.y)));
795 }
796
797 /* Emit the specified user sample locations. */
798 switch (num_samples) {
799 case 2:
800 case 4:
801 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
802 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
803 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
804 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
805 break;
806 case 8:
807 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
808 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
809 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
810 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
811 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs_pixel[0][1]);
812 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs_pixel[1][1]);
813 radeon_set_context_reg(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs_pixel[2][1]);
814 radeon_set_context_reg(cs, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs_pixel[3][1]);
815 break;
816 default:
817 unreachable("invalid number of samples");
818 }
819
820 /* Emit the maximum sample distance and the centroid priority. */
821 uint32_t pa_sc_aa_config = ms->pa_sc_aa_config;
822
823 pa_sc_aa_config &= C_028BE0_MAX_SAMPLE_DIST;
824 pa_sc_aa_config |= S_028BE0_MAX_SAMPLE_DIST(max_sample_dist);
825
826 radeon_set_context_reg_seq(cs, R_028BE0_PA_SC_AA_CONFIG, 1);
827 radeon_emit(cs, pa_sc_aa_config);
828
829 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
830 radeon_emit(cs, centroid_priority);
831 radeon_emit(cs, centroid_priority >> 32);
832
833 /* GFX9: Flush DFSM when the AA mode changes. */
834 if (cmd_buffer->device->dfsm_allowed) {
835 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
836 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
837 }
838
839 cmd_buffer->state.context_roll_without_scissor_emitted = true;
840 }
841
842 static void
843 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
844 struct radv_pipeline *pipeline,
845 gl_shader_stage stage,
846 int idx, int count, uint32_t *values)
847 {
848 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
849 uint32_t base_reg = pipeline->user_data_0[stage];
850 if (loc->sgpr_idx == -1)
851 return;
852
853 assert(loc->num_sgprs == count);
854
855 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
856 radeon_emit_array(cmd_buffer->cs, values, count);
857 }
858
859 static void
860 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
861 struct radv_pipeline *pipeline)
862 {
863 int num_samples = pipeline->graphics.ms.num_samples;
864 struct radv_multisample_state *ms = &pipeline->graphics.ms;
865 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
866
867 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.needs_sample_positions)
868 cmd_buffer->sample_positions_needed = true;
869
870 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
871 return;
872
873 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
874 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
875 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
876
877 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
878
879 radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
880
881 /* GFX9: Flush DFSM when the AA mode changes. */
882 if (cmd_buffer->device->dfsm_allowed) {
883 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
884 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
885 }
886
887 cmd_buffer->state.context_roll_without_scissor_emitted = true;
888 }
889
890 static void
891 radv_update_binning_state(struct radv_cmd_buffer *cmd_buffer,
892 struct radv_pipeline *pipeline)
893 {
894 const struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
895
896
897 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
898 return;
899
900 if (old_pipeline &&
901 old_pipeline->graphics.binning.pa_sc_binner_cntl_0 == pipeline->graphics.binning.pa_sc_binner_cntl_0 &&
902 old_pipeline->graphics.binning.db_dfsm_control == pipeline->graphics.binning.db_dfsm_control)
903 return;
904
905 bool binning_flush = false;
906 if (cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA12 ||
907 cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA20 ||
908 cmd_buffer->device->physical_device->rad_info.family == CHIP_RAVEN2 ||
909 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
910 binning_flush = !old_pipeline ||
911 G_028C44_BINNING_MODE(old_pipeline->graphics.binning.pa_sc_binner_cntl_0) !=
912 G_028C44_BINNING_MODE(pipeline->graphics.binning.pa_sc_binner_cntl_0);
913 }
914
915 radeon_set_context_reg(cmd_buffer->cs, R_028C44_PA_SC_BINNER_CNTL_0,
916 pipeline->graphics.binning.pa_sc_binner_cntl_0 |
917 S_028C44_FLUSH_ON_BINNING_TRANSITION(!!binning_flush));
918
919 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
920 radeon_set_context_reg(cmd_buffer->cs, R_028038_DB_DFSM_CONTROL,
921 pipeline->graphics.binning.db_dfsm_control);
922 } else {
923 radeon_set_context_reg(cmd_buffer->cs, R_028060_DB_DFSM_CONTROL,
924 pipeline->graphics.binning.db_dfsm_control);
925 }
926
927 cmd_buffer->state.context_roll_without_scissor_emitted = true;
928 }
929
930
931 static void
932 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
933 struct radv_shader_variant *shader)
934 {
935 uint64_t va;
936
937 if (!shader)
938 return;
939
940 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
941
942 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
943 }
944
945 static void
946 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
947 struct radv_pipeline *pipeline,
948 bool vertex_stage_only)
949 {
950 struct radv_cmd_state *state = &cmd_buffer->state;
951 uint32_t mask = state->prefetch_L2_mask;
952
953 if (vertex_stage_only) {
954 /* Fast prefetch path for starting draws as soon as possible.
955 */
956 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
957 RADV_PREFETCH_VBO_DESCRIPTORS);
958 }
959
960 if (mask & RADV_PREFETCH_VS)
961 radv_emit_shader_prefetch(cmd_buffer,
962 pipeline->shaders[MESA_SHADER_VERTEX]);
963
964 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
965 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
966
967 if (mask & RADV_PREFETCH_TCS)
968 radv_emit_shader_prefetch(cmd_buffer,
969 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
970
971 if (mask & RADV_PREFETCH_TES)
972 radv_emit_shader_prefetch(cmd_buffer,
973 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
974
975 if (mask & RADV_PREFETCH_GS) {
976 radv_emit_shader_prefetch(cmd_buffer,
977 pipeline->shaders[MESA_SHADER_GEOMETRY]);
978 if (radv_pipeline_has_gs_copy_shader(pipeline))
979 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
980 }
981
982 if (mask & RADV_PREFETCH_PS)
983 radv_emit_shader_prefetch(cmd_buffer,
984 pipeline->shaders[MESA_SHADER_FRAGMENT]);
985
986 state->prefetch_L2_mask &= ~mask;
987 }
988
989 static void
990 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
991 {
992 if (!cmd_buffer->device->physical_device->rad_info.rbplus_allowed)
993 return;
994
995 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
996 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
997
998 unsigned sx_ps_downconvert = 0;
999 unsigned sx_blend_opt_epsilon = 0;
1000 unsigned sx_blend_opt_control = 0;
1001
1002 for (unsigned i = 0; i < subpass->color_count; ++i) {
1003 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1004 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1005 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1006 continue;
1007 }
1008
1009 int idx = subpass->color_attachments[i].attachment;
1010 struct radv_color_buffer_info *cb = &cmd_buffer->state.attachments[idx].cb;
1011
1012 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
1013 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
1014 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
1015 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
1016
1017 bool has_alpha, has_rgb;
1018
1019 /* Set if RGB and A are present. */
1020 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
1021
1022 if (format == V_028C70_COLOR_8 ||
1023 format == V_028C70_COLOR_16 ||
1024 format == V_028C70_COLOR_32)
1025 has_rgb = !has_alpha;
1026 else
1027 has_rgb = true;
1028
1029 /* Check the colormask and export format. */
1030 if (!(colormask & 0x7))
1031 has_rgb = false;
1032 if (!(colormask & 0x8))
1033 has_alpha = false;
1034
1035 if (spi_format == V_028714_SPI_SHADER_ZERO) {
1036 has_rgb = false;
1037 has_alpha = false;
1038 }
1039
1040 /* Disable value checking for disabled channels. */
1041 if (!has_rgb)
1042 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1043 if (!has_alpha)
1044 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1045
1046 /* Enable down-conversion for 32bpp and smaller formats. */
1047 switch (format) {
1048 case V_028C70_COLOR_8:
1049 case V_028C70_COLOR_8_8:
1050 case V_028C70_COLOR_8_8_8_8:
1051 /* For 1 and 2-channel formats, use the superset thereof. */
1052 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
1053 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1054 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1055 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
1056 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
1057 }
1058 break;
1059
1060 case V_028C70_COLOR_5_6_5:
1061 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1062 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
1063 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
1064 }
1065 break;
1066
1067 case V_028C70_COLOR_1_5_5_5:
1068 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1069 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
1070 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
1071 }
1072 break;
1073
1074 case V_028C70_COLOR_4_4_4_4:
1075 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1076 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
1077 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
1078 }
1079 break;
1080
1081 case V_028C70_COLOR_32:
1082 if (swap == V_028C70_SWAP_STD &&
1083 spi_format == V_028714_SPI_SHADER_32_R)
1084 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1085 else if (swap == V_028C70_SWAP_ALT_REV &&
1086 spi_format == V_028714_SPI_SHADER_32_AR)
1087 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
1088 break;
1089
1090 case V_028C70_COLOR_16:
1091 case V_028C70_COLOR_16_16:
1092 /* For 1-channel formats, use the superset thereof. */
1093 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
1094 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
1095 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1096 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1097 if (swap == V_028C70_SWAP_STD ||
1098 swap == V_028C70_SWAP_STD_REV)
1099 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
1100 else
1101 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
1102 }
1103 break;
1104
1105 case V_028C70_COLOR_10_11_11:
1106 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1107 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
1108 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
1109 }
1110 break;
1111
1112 case V_028C70_COLOR_2_10_10_10:
1113 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1114 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
1115 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
1116 }
1117 break;
1118 }
1119 }
1120
1121 for (unsigned i = subpass->color_count; i < 8; ++i) {
1122 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1123 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1124 }
1125 /* TODO: avoid redundantly setting context registers */
1126 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
1127 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
1128 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
1129 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
1130
1131 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1132 }
1133
1134 static void
1135 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1136 {
1137 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1138
1139 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1140 return;
1141
1142 radv_update_multisample_state(cmd_buffer, pipeline);
1143 radv_update_binning_state(cmd_buffer, pipeline);
1144
1145 cmd_buffer->scratch_size_needed =
1146 MAX2(cmd_buffer->scratch_size_needed,
1147 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1148
1149 if (!cmd_buffer->state.emitted_pipeline ||
1150 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1151 pipeline->graphics.can_use_guardband)
1152 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1153
1154 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
1155
1156 if (!cmd_buffer->state.emitted_pipeline ||
1157 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
1158 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
1159 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
1160 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
1161 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
1162 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1163 }
1164
1165 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
1166 if (!pipeline->shaders[i])
1167 continue;
1168
1169 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1170 pipeline->shaders[i]->bo);
1171 }
1172
1173 if (radv_pipeline_has_gs_copy_shader(pipeline))
1174 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1175 pipeline->gs_copy_shader->bo);
1176
1177 if (unlikely(cmd_buffer->device->trace_bo))
1178 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1179
1180 cmd_buffer->state.emitted_pipeline = pipeline;
1181
1182 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1183 }
1184
1185 static void
1186 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1187 {
1188 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1189 cmd_buffer->state.dynamic.viewport.viewports);
1190 }
1191
1192 static void
1193 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1194 {
1195 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1196
1197 si_write_scissors(cmd_buffer->cs, 0, count,
1198 cmd_buffer->state.dynamic.scissor.scissors,
1199 cmd_buffer->state.dynamic.viewport.viewports,
1200 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1201
1202 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1203 }
1204
1205 static void
1206 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1207 {
1208 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1209 return;
1210
1211 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1212 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1213 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1214 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1215 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1216 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1217 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1218 }
1219 }
1220
1221 static void
1222 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1223 {
1224 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1225
1226 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1227 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1228 }
1229
1230 static void
1231 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1232 {
1233 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1234
1235 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1236 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1237 }
1238
1239 static void
1240 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1241 {
1242 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1243
1244 radeon_set_context_reg_seq(cmd_buffer->cs,
1245 R_028430_DB_STENCILREFMASK, 2);
1246 radeon_emit(cmd_buffer->cs,
1247 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1248 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1249 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1250 S_028430_STENCILOPVAL(1));
1251 radeon_emit(cmd_buffer->cs,
1252 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1253 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1254 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1255 S_028434_STENCILOPVAL_BF(1));
1256 }
1257
1258 static void
1259 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1260 {
1261 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1262
1263 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1264 fui(d->depth_bounds.min));
1265 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1266 fui(d->depth_bounds.max));
1267 }
1268
1269 static void
1270 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1271 {
1272 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1273 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1274 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1275
1276
1277 radeon_set_context_reg_seq(cmd_buffer->cs,
1278 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1279 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1280 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1281 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1282 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1283 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1284 }
1285
1286 static void
1287 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1288 int index,
1289 struct radv_color_buffer_info *cb,
1290 struct radv_image_view *iview,
1291 VkImageLayout layout,
1292 bool in_render_loop)
1293 {
1294 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
1295 uint32_t cb_color_info = cb->cb_color_info;
1296 struct radv_image *image = iview->image;
1297
1298 if (!radv_layout_dcc_compressed(cmd_buffer->device, image, layout, in_render_loop,
1299 radv_image_queue_family_mask(image,
1300 cmd_buffer->queue_family_index,
1301 cmd_buffer->queue_family_index))) {
1302 cb_color_info &= C_028C70_DCC_ENABLE;
1303 }
1304
1305 if (radv_image_is_tc_compat_cmask(image) &&
1306 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1307 radv_is_dcc_decompress_pipeline(cmd_buffer))) {
1308 /* If this bit is set, the FMASK decompression operation
1309 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1310 */
1311 cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
1312 }
1313
1314 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1315 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1316 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1317 radeon_emit(cmd_buffer->cs, 0);
1318 radeon_emit(cmd_buffer->cs, 0);
1319 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1320 radeon_emit(cmd_buffer->cs, cb_color_info);
1321 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1322 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1323 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1324 radeon_emit(cmd_buffer->cs, 0);
1325 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1326 radeon_emit(cmd_buffer->cs, 0);
1327
1328 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 1);
1329 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1330
1331 radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4,
1332 cb->cb_color_base >> 32);
1333 radeon_set_context_reg(cmd_buffer->cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + index * 4,
1334 cb->cb_color_cmask >> 32);
1335 radeon_set_context_reg(cmd_buffer->cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + index * 4,
1336 cb->cb_color_fmask >> 32);
1337 radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4,
1338 cb->cb_dcc_base >> 32);
1339 radeon_set_context_reg(cmd_buffer->cs, R_028EC0_CB_COLOR0_ATTRIB2 + index * 4,
1340 cb->cb_color_attrib2);
1341 radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4,
1342 cb->cb_color_attrib3);
1343 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1344 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1345 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1346 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1347 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1348 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1349 radeon_emit(cmd_buffer->cs, cb_color_info);
1350 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1351 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1352 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1353 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1354 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1355 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1356
1357 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1358 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1359 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1360
1361 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1362 cb->cb_mrt_epitch);
1363 } else {
1364 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1365 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1366 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1367 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1368 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1369 radeon_emit(cmd_buffer->cs, cb_color_info);
1370 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1371 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1372 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1373 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1374 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1375 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1376
1377 if (is_vi) { /* DCC BASE */
1378 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1379 }
1380 }
1381
1382 if (radv_dcc_enabled(image, iview->base_mip)) {
1383 /* Drawing with DCC enabled also compresses colorbuffers. */
1384 VkImageSubresourceRange range = {
1385 .aspectMask = iview->aspect_mask,
1386 .baseMipLevel = iview->base_mip,
1387 .levelCount = iview->level_count,
1388 .baseArrayLayer = iview->base_layer,
1389 .layerCount = iview->layer_count,
1390 };
1391
1392 radv_update_dcc_metadata(cmd_buffer, image, &range, true);
1393 }
1394 }
1395
1396 static void
1397 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1398 struct radv_ds_buffer_info *ds,
1399 const struct radv_image_view *iview,
1400 VkImageLayout layout,
1401 bool in_render_loop, bool requires_cond_exec)
1402 {
1403 const struct radv_image *image = iview->image;
1404 uint32_t db_z_info = ds->db_z_info;
1405 uint32_t db_z_info_reg;
1406
1407 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug ||
1408 !radv_image_is_tc_compat_htile(image))
1409 return;
1410
1411 if (!radv_layout_has_htile(image, layout, in_render_loop,
1412 radv_image_queue_family_mask(image,
1413 cmd_buffer->queue_family_index,
1414 cmd_buffer->queue_family_index))) {
1415 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1416 }
1417
1418 db_z_info &= C_028040_ZRANGE_PRECISION;
1419
1420 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1421 db_z_info_reg = R_028038_DB_Z_INFO;
1422 } else {
1423 db_z_info_reg = R_028040_DB_Z_INFO;
1424 }
1425
1426 /* When we don't know the last fast clear value we need to emit a
1427 * conditional packet that will eventually skip the following
1428 * SET_CONTEXT_REG packet.
1429 */
1430 if (requires_cond_exec) {
1431 uint64_t va = radv_get_tc_compat_zrange_va(image, iview->base_mip);
1432
1433 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1434 radeon_emit(cmd_buffer->cs, va);
1435 radeon_emit(cmd_buffer->cs, va >> 32);
1436 radeon_emit(cmd_buffer->cs, 0);
1437 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1438 }
1439
1440 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1441 }
1442
1443 static void
1444 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1445 struct radv_ds_buffer_info *ds,
1446 struct radv_image_view *iview,
1447 VkImageLayout layout,
1448 bool in_render_loop)
1449 {
1450 const struct radv_image *image = iview->image;
1451 uint32_t db_z_info = ds->db_z_info;
1452 uint32_t db_stencil_info = ds->db_stencil_info;
1453
1454 if (!radv_layout_has_htile(image, layout, in_render_loop,
1455 radv_image_queue_family_mask(image,
1456 cmd_buffer->queue_family_index,
1457 cmd_buffer->queue_family_index))) {
1458 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1459 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1460 }
1461
1462 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1463 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1464
1465 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1466 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1467 radeon_set_context_reg(cmd_buffer->cs, R_02801C_DB_DEPTH_SIZE_XY, ds->db_depth_size);
1468
1469 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 7);
1470 radeon_emit(cmd_buffer->cs, S_02803C_RESOURCE_LEVEL(1));
1471 radeon_emit(cmd_buffer->cs, db_z_info);
1472 radeon_emit(cmd_buffer->cs, db_stencil_info);
1473 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1474 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1475 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1476 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1477
1478 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_READ_BASE_HI, 5);
1479 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1480 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1481 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1482 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1483 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1484 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1485 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1486 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1487 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1488 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1489
1490 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1491 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1492 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1493 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1494 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1495 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1496 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1497 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1498 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1499 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1500 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1501
1502 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1503 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1504 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1505 } else {
1506 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1507
1508 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1509 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1510 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1511 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1512 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1513 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1514 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1515 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1516 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1517 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1518
1519 }
1520
1521 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1522 radv_update_zrange_precision(cmd_buffer, ds, iview, layout,
1523 in_render_loop, true);
1524
1525 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1526 ds->pa_su_poly_offset_db_fmt_cntl);
1527 }
1528
1529 /**
1530 * Update the fast clear depth/stencil values if the image is bound as a
1531 * depth/stencil buffer.
1532 */
1533 static void
1534 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1535 const struct radv_image_view *iview,
1536 VkClearDepthStencilValue ds_clear_value,
1537 VkImageAspectFlags aspects)
1538 {
1539 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1540 const struct radv_image *image = iview->image;
1541 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1542 uint32_t att_idx;
1543
1544 if (!cmd_buffer->state.attachments || !subpass)
1545 return;
1546
1547 if (!subpass->depth_stencil_attachment)
1548 return;
1549
1550 att_idx = subpass->depth_stencil_attachment->attachment;
1551 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1552 return;
1553
1554 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1555 radeon_emit(cs, ds_clear_value.stencil);
1556 radeon_emit(cs, fui(ds_clear_value.depth));
1557
1558 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1559 * only needed when clearing Z to 0.0.
1560 */
1561 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1562 ds_clear_value.depth == 0.0) {
1563 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1564 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
1565
1566 radv_update_zrange_precision(cmd_buffer, &cmd_buffer->state.attachments[att_idx].ds,
1567 iview, layout, in_render_loop, false);
1568 }
1569
1570 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1571 }
1572
1573 /**
1574 * Set the clear depth/stencil values to the image's metadata.
1575 */
1576 static void
1577 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1578 struct radv_image *image,
1579 const VkImageSubresourceRange *range,
1580 VkClearDepthStencilValue ds_clear_value,
1581 VkImageAspectFlags aspects)
1582 {
1583 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1584 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel);
1585 uint32_t level_count = radv_get_levelCount(image, range);
1586
1587 if (aspects & (VK_IMAGE_ASPECT_DEPTH_BIT |
1588 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1589 /* Use the fastest way when both aspects are used. */
1590 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + 2 * level_count, cmd_buffer->state.predicating));
1591 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1592 S_370_WR_CONFIRM(1) |
1593 S_370_ENGINE_SEL(V_370_PFP));
1594 radeon_emit(cs, va);
1595 radeon_emit(cs, va >> 32);
1596
1597 for (uint32_t l = 0; l < level_count; l++) {
1598 radeon_emit(cs, ds_clear_value.stencil);
1599 radeon_emit(cs, fui(ds_clear_value.depth));
1600 }
1601 } else {
1602 /* Otherwise we need one WRITE_DATA packet per level. */
1603 for (uint32_t l = 0; l < level_count; l++) {
1604 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel + l);
1605 unsigned value;
1606
1607 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
1608 value = fui(ds_clear_value.depth);
1609 va += 4;
1610 } else {
1611 value = ds_clear_value.stencil;
1612 }
1613
1614 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1615 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1616 S_370_WR_CONFIRM(1) |
1617 S_370_ENGINE_SEL(V_370_PFP));
1618 radeon_emit(cs, va);
1619 radeon_emit(cs, va >> 32);
1620 radeon_emit(cs, value);
1621 }
1622 }
1623 }
1624
1625 /**
1626 * Update the TC-compat metadata value for this image.
1627 */
1628 static void
1629 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1630 struct radv_image *image,
1631 const VkImageSubresourceRange *range,
1632 uint32_t value)
1633 {
1634 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1635
1636 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug)
1637 return;
1638
1639 uint64_t va = radv_get_tc_compat_zrange_va(image, range->baseMipLevel);
1640 uint32_t level_count = radv_get_levelCount(image, range);
1641
1642 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + level_count, cmd_buffer->state.predicating));
1643 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1644 S_370_WR_CONFIRM(1) |
1645 S_370_ENGINE_SEL(V_370_PFP));
1646 radeon_emit(cs, va);
1647 radeon_emit(cs, va >> 32);
1648
1649 for (uint32_t l = 0; l < level_count; l++)
1650 radeon_emit(cs, value);
1651 }
1652
1653 static void
1654 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1655 const struct radv_image_view *iview,
1656 VkClearDepthStencilValue ds_clear_value)
1657 {
1658 VkImageSubresourceRange range = {
1659 .aspectMask = iview->aspect_mask,
1660 .baseMipLevel = iview->base_mip,
1661 .levelCount = iview->level_count,
1662 .baseArrayLayer = iview->base_layer,
1663 .layerCount = iview->layer_count,
1664 };
1665 uint32_t cond_val;
1666
1667 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1668 * depth clear value is 0.0f.
1669 */
1670 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1671
1672 radv_set_tc_compat_zrange_metadata(cmd_buffer, iview->image, &range,
1673 cond_val);
1674 }
1675
1676 /**
1677 * Update the clear depth/stencil values for this image.
1678 */
1679 void
1680 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1681 const struct radv_image_view *iview,
1682 VkClearDepthStencilValue ds_clear_value,
1683 VkImageAspectFlags aspects)
1684 {
1685 VkImageSubresourceRange range = {
1686 .aspectMask = iview->aspect_mask,
1687 .baseMipLevel = iview->base_mip,
1688 .levelCount = iview->level_count,
1689 .baseArrayLayer = iview->base_layer,
1690 .layerCount = iview->layer_count,
1691 };
1692 struct radv_image *image = iview->image;
1693
1694 assert(radv_image_has_htile(image));
1695
1696 radv_set_ds_clear_metadata(cmd_buffer, iview->image, &range,
1697 ds_clear_value, aspects);
1698
1699 if (radv_image_is_tc_compat_htile(image) &&
1700 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1701 radv_update_tc_compat_zrange_metadata(cmd_buffer, iview,
1702 ds_clear_value);
1703 }
1704
1705 radv_update_bound_fast_clear_ds(cmd_buffer, iview, ds_clear_value,
1706 aspects);
1707 }
1708
1709 /**
1710 * Load the clear depth/stencil values from the image's metadata.
1711 */
1712 static void
1713 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1714 const struct radv_image_view *iview)
1715 {
1716 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1717 const struct radv_image *image = iview->image;
1718 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1719 uint64_t va = radv_get_ds_clear_value_va(image, iview->base_mip);
1720 unsigned reg_offset = 0, reg_count = 0;
1721
1722 if (!radv_image_has_htile(image))
1723 return;
1724
1725 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1726 ++reg_count;
1727 } else {
1728 ++reg_offset;
1729 va += 4;
1730 }
1731 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1732 ++reg_count;
1733
1734 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1735
1736 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
1737 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1738 radeon_emit(cs, va);
1739 radeon_emit(cs, va >> 32);
1740 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1741 radeon_emit(cs, reg_count);
1742 } else {
1743 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1744 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1745 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1746 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1747 radeon_emit(cs, va);
1748 radeon_emit(cs, va >> 32);
1749 radeon_emit(cs, reg >> 2);
1750 radeon_emit(cs, 0);
1751
1752 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1753 radeon_emit(cs, 0);
1754 }
1755 }
1756
1757 /*
1758 * With DCC some colors don't require CMASK elimination before being
1759 * used as a texture. This sets a predicate value to determine if the
1760 * cmask eliminate is required.
1761 */
1762 void
1763 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1764 struct radv_image *image,
1765 const VkImageSubresourceRange *range, bool value)
1766 {
1767 uint64_t pred_val = value;
1768 uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
1769 uint32_t level_count = radv_get_levelCount(image, range);
1770 uint32_t count = 2 * level_count;
1771
1772 assert(radv_dcc_enabled(image, range->baseMipLevel));
1773
1774 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1775 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1776 S_370_WR_CONFIRM(1) |
1777 S_370_ENGINE_SEL(V_370_PFP));
1778 radeon_emit(cmd_buffer->cs, va);
1779 radeon_emit(cmd_buffer->cs, va >> 32);
1780
1781 for (uint32_t l = 0; l < level_count; l++) {
1782 radeon_emit(cmd_buffer->cs, pred_val);
1783 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1784 }
1785 }
1786
1787 /**
1788 * Update the DCC predicate to reflect the compression state.
1789 */
1790 void
1791 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1792 struct radv_image *image,
1793 const VkImageSubresourceRange *range, bool value)
1794 {
1795 uint64_t pred_val = value;
1796 uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
1797 uint32_t level_count = radv_get_levelCount(image, range);
1798 uint32_t count = 2 * level_count;
1799
1800 assert(radv_dcc_enabled(image, range->baseMipLevel));
1801
1802 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1803 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1804 S_370_WR_CONFIRM(1) |
1805 S_370_ENGINE_SEL(V_370_PFP));
1806 radeon_emit(cmd_buffer->cs, va);
1807 radeon_emit(cmd_buffer->cs, va >> 32);
1808
1809 for (uint32_t l = 0; l < level_count; l++) {
1810 radeon_emit(cmd_buffer->cs, pred_val);
1811 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1812 }
1813 }
1814
1815 /**
1816 * Update the fast clear color values if the image is bound as a color buffer.
1817 */
1818 static void
1819 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1820 struct radv_image *image,
1821 int cb_idx,
1822 uint32_t color_values[2])
1823 {
1824 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1825 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1826 uint32_t att_idx;
1827
1828 if (!cmd_buffer->state.attachments || !subpass)
1829 return;
1830
1831 att_idx = subpass->color_attachments[cb_idx].attachment;
1832 if (att_idx == VK_ATTACHMENT_UNUSED)
1833 return;
1834
1835 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1836 return;
1837
1838 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1839 radeon_emit(cs, color_values[0]);
1840 radeon_emit(cs, color_values[1]);
1841
1842 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1843 }
1844
1845 /**
1846 * Set the clear color values to the image's metadata.
1847 */
1848 static void
1849 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1850 struct radv_image *image,
1851 const VkImageSubresourceRange *range,
1852 uint32_t color_values[2])
1853 {
1854 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1855 uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
1856 uint32_t level_count = radv_get_levelCount(image, range);
1857 uint32_t count = 2 * level_count;
1858
1859 assert(radv_image_has_cmask(image) ||
1860 radv_dcc_enabled(image, range->baseMipLevel));
1861
1862 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
1863 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1864 S_370_WR_CONFIRM(1) |
1865 S_370_ENGINE_SEL(V_370_PFP));
1866 radeon_emit(cs, va);
1867 radeon_emit(cs, va >> 32);
1868
1869 for (uint32_t l = 0; l < level_count; l++) {
1870 radeon_emit(cs, color_values[0]);
1871 radeon_emit(cs, color_values[1]);
1872 }
1873 }
1874
1875 /**
1876 * Update the clear color values for this image.
1877 */
1878 void
1879 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1880 const struct radv_image_view *iview,
1881 int cb_idx,
1882 uint32_t color_values[2])
1883 {
1884 struct radv_image *image = iview->image;
1885 VkImageSubresourceRange range = {
1886 .aspectMask = iview->aspect_mask,
1887 .baseMipLevel = iview->base_mip,
1888 .levelCount = iview->level_count,
1889 .baseArrayLayer = iview->base_layer,
1890 .layerCount = iview->layer_count,
1891 };
1892
1893 assert(radv_image_has_cmask(image) ||
1894 radv_dcc_enabled(image, iview->base_mip));
1895
1896 radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
1897
1898 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1899 color_values);
1900 }
1901
1902 /**
1903 * Load the clear color values from the image's metadata.
1904 */
1905 static void
1906 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1907 struct radv_image_view *iview,
1908 int cb_idx)
1909 {
1910 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1911 struct radv_image *image = iview->image;
1912 uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
1913
1914 if (!radv_image_has_cmask(image) &&
1915 !radv_dcc_enabled(image, iview->base_mip))
1916 return;
1917
1918 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1919
1920 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
1921 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1922 radeon_emit(cs, va);
1923 radeon_emit(cs, va >> 32);
1924 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1925 radeon_emit(cs, 2);
1926 } else {
1927 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1928 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1929 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1930 COPY_DATA_COUNT_SEL);
1931 radeon_emit(cs, va);
1932 radeon_emit(cs, va >> 32);
1933 radeon_emit(cs, reg >> 2);
1934 radeon_emit(cs, 0);
1935
1936 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1937 radeon_emit(cs, 0);
1938 }
1939 }
1940
1941 static void
1942 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1943 {
1944 int i;
1945 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1946 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1947
1948 /* this may happen for inherited secondary recording */
1949 if (!framebuffer)
1950 return;
1951
1952 for (i = 0; i < 8; ++i) {
1953 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1954 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1955 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1956 continue;
1957 }
1958
1959 int idx = subpass->color_attachments[i].attachment;
1960 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
1961 VkImageLayout layout = subpass->color_attachments[i].layout;
1962 bool in_render_loop = subpass->color_attachments[i].in_render_loop;
1963
1964 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, iview->bo);
1965
1966 assert(iview->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
1967 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
1968 radv_emit_fb_color_state(cmd_buffer, i, &cmd_buffer->state.attachments[idx].cb, iview, layout, in_render_loop);
1969
1970 radv_load_color_clear_metadata(cmd_buffer, iview, i);
1971 }
1972
1973 if (subpass->depth_stencil_attachment) {
1974 int idx = subpass->depth_stencil_attachment->attachment;
1975 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1976 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
1977 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
1978 struct radv_image *image = iview->image;
1979 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, cmd_buffer->state.attachments[idx].iview->bo);
1980 ASSERTED uint32_t queue_mask = radv_image_queue_family_mask(image,
1981 cmd_buffer->queue_family_index,
1982 cmd_buffer->queue_family_index);
1983 /* We currently don't support writing decompressed HTILE */
1984 assert(radv_layout_has_htile(image, layout, in_render_loop, queue_mask) ==
1985 radv_layout_is_htile_compressed(image, layout, in_render_loop, queue_mask));
1986
1987 radv_emit_fb_ds_state(cmd_buffer, &cmd_buffer->state.attachments[idx].ds, iview, layout, in_render_loop);
1988
1989 if (cmd_buffer->state.attachments[idx].ds.offset_scale != cmd_buffer->state.offset_scale) {
1990 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1991 cmd_buffer->state.offset_scale = cmd_buffer->state.attachments[idx].ds.offset_scale;
1992 }
1993 radv_load_ds_clear_metadata(cmd_buffer, iview);
1994 } else {
1995 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9)
1996 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1997 else
1998 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1999
2000 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
2001 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
2002 }
2003 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2004 S_028208_BR_X(framebuffer->width) |
2005 S_028208_BR_Y(framebuffer->height));
2006
2007 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
2008 bool disable_constant_encode =
2009 cmd_buffer->device->physical_device->rad_info.has_dcc_constant_encode;
2010 enum chip_class chip_class =
2011 cmd_buffer->device->physical_device->rad_info.chip_class;
2012 uint8_t watermark = chip_class >= GFX10 ? 6 : 4;
2013
2014 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
2015 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class <= GFX9) |
2016 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
2017 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
2018 }
2019
2020 if (cmd_buffer->device->pbb_allowed) {
2021 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2022 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
2023 }
2024
2025 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
2026 }
2027
2028 static void
2029 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
2030 {
2031 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2032 struct radv_cmd_state *state = &cmd_buffer->state;
2033
2034 if (state->index_type != state->last_index_type) {
2035 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2036 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2037 cs, R_03090C_VGT_INDEX_TYPE,
2038 2, state->index_type);
2039 } else {
2040 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2041 radeon_emit(cs, state->index_type);
2042 }
2043
2044 state->last_index_type = state->index_type;
2045 }
2046
2047 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2048 radeon_emit(cs, state->index_va);
2049 radeon_emit(cs, state->index_va >> 32);
2050
2051 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2052 radeon_emit(cs, state->max_index_count);
2053
2054 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
2055 }
2056
2057 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
2058 {
2059 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
2060 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2061 uint32_t pa_sc_mode_cntl_1 =
2062 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
2063 uint32_t db_count_control;
2064
2065 if(!cmd_buffer->state.active_occlusion_queries) {
2066 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2067 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2068 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2069 has_perfect_queries) {
2070 /* Re-enable out-of-order rasterization if the
2071 * bound pipeline supports it and if it's has
2072 * been disabled before starting any perfect
2073 * occlusion queries.
2074 */
2075 radeon_set_context_reg(cmd_buffer->cs,
2076 R_028A4C_PA_SC_MODE_CNTL_1,
2077 pa_sc_mode_cntl_1);
2078 }
2079 }
2080 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
2081 } else {
2082 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2083 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
2084 bool gfx10_perfect = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10 && has_perfect_queries;
2085
2086 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2087 db_count_control =
2088 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
2089 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
2090 S_028004_SAMPLE_RATE(sample_rate) |
2091 S_028004_ZPASS_ENABLE(1) |
2092 S_028004_SLICE_EVEN_ENABLE(1) |
2093 S_028004_SLICE_ODD_ENABLE(1);
2094
2095 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2096 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2097 has_perfect_queries) {
2098 /* If the bound pipeline has enabled
2099 * out-of-order rasterization, we should
2100 * disable it before starting any perfect
2101 * occlusion queries.
2102 */
2103 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
2104
2105 radeon_set_context_reg(cmd_buffer->cs,
2106 R_028A4C_PA_SC_MODE_CNTL_1,
2107 pa_sc_mode_cntl_1);
2108 }
2109 } else {
2110 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
2111 S_028004_SAMPLE_RATE(sample_rate);
2112 }
2113 }
2114
2115 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
2116
2117 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2118 }
2119
2120 static void
2121 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
2122 {
2123 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
2124
2125 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
2126 radv_emit_viewport(cmd_buffer);
2127
2128 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
2129 !cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
2130 radv_emit_scissor(cmd_buffer);
2131
2132 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
2133 radv_emit_line_width(cmd_buffer);
2134
2135 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
2136 radv_emit_blend_constants(cmd_buffer);
2137
2138 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
2139 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
2140 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
2141 radv_emit_stencil(cmd_buffer);
2142
2143 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
2144 radv_emit_depth_bounds(cmd_buffer);
2145
2146 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
2147 radv_emit_depth_bias(cmd_buffer);
2148
2149 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
2150 radv_emit_discard_rectangle(cmd_buffer);
2151
2152 if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)
2153 radv_emit_sample_locations(cmd_buffer);
2154
2155 cmd_buffer->state.dirty &= ~states;
2156 }
2157
2158 static void
2159 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
2160 VkPipelineBindPoint bind_point)
2161 {
2162 struct radv_descriptor_state *descriptors_state =
2163 radv_get_descriptors_state(cmd_buffer, bind_point);
2164 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
2165 unsigned bo_offset;
2166
2167 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
2168 set->mapped_ptr,
2169 &bo_offset))
2170 return;
2171
2172 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2173 set->va += bo_offset;
2174 }
2175
2176 static void
2177 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
2178 VkPipelineBindPoint bind_point)
2179 {
2180 struct radv_descriptor_state *descriptors_state =
2181 radv_get_descriptors_state(cmd_buffer, bind_point);
2182 uint32_t size = MAX_SETS * 4;
2183 uint32_t offset;
2184 void *ptr;
2185
2186 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
2187 256, &offset, &ptr))
2188 return;
2189
2190 for (unsigned i = 0; i < MAX_SETS; i++) {
2191 uint32_t *uptr = ((uint32_t *)ptr) + i;
2192 uint64_t set_va = 0;
2193 struct radv_descriptor_set *set = descriptors_state->sets[i];
2194 if (descriptors_state->valid & (1u << i))
2195 set_va = set->va;
2196 uptr[0] = set_va & 0xffffffff;
2197 }
2198
2199 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2200 va += offset;
2201
2202 if (cmd_buffer->state.pipeline) {
2203 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
2204 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2205 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2206
2207 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
2208 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
2209 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2210
2211 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
2212 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2213 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2214
2215 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2216 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
2217 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2218
2219 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2220 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
2221 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2222 }
2223
2224 if (cmd_buffer->state.compute_pipeline)
2225 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
2226 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2227 }
2228
2229 static void
2230 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
2231 VkShaderStageFlags stages)
2232 {
2233 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2234 VK_PIPELINE_BIND_POINT_COMPUTE :
2235 VK_PIPELINE_BIND_POINT_GRAPHICS;
2236 struct radv_descriptor_state *descriptors_state =
2237 radv_get_descriptors_state(cmd_buffer, bind_point);
2238 struct radv_cmd_state *state = &cmd_buffer->state;
2239 bool flush_indirect_descriptors;
2240
2241 if (!descriptors_state->dirty)
2242 return;
2243
2244 if (descriptors_state->push_dirty)
2245 radv_flush_push_descriptors(cmd_buffer, bind_point);
2246
2247 flush_indirect_descriptors =
2248 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
2249 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
2250 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
2251 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
2252
2253 if (flush_indirect_descriptors)
2254 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
2255
2256 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2257 cmd_buffer->cs,
2258 MAX_SETS * MESA_SHADER_STAGES * 4);
2259
2260 if (cmd_buffer->state.pipeline) {
2261 radv_foreach_stage(stage, stages) {
2262 if (!cmd_buffer->state.pipeline->shaders[stage])
2263 continue;
2264
2265 radv_emit_descriptor_pointers(cmd_buffer,
2266 cmd_buffer->state.pipeline,
2267 descriptors_state, stage);
2268 }
2269 }
2270
2271 if (cmd_buffer->state.compute_pipeline &&
2272 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
2273 radv_emit_descriptor_pointers(cmd_buffer,
2274 cmd_buffer->state.compute_pipeline,
2275 descriptors_state,
2276 MESA_SHADER_COMPUTE);
2277 }
2278
2279 descriptors_state->dirty = 0;
2280 descriptors_state->push_dirty = false;
2281
2282 assert(cmd_buffer->cs->cdw <= cdw_max);
2283
2284 if (unlikely(cmd_buffer->device->trace_bo))
2285 radv_save_descriptors(cmd_buffer, bind_point);
2286 }
2287
2288 static void
2289 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
2290 VkShaderStageFlags stages)
2291 {
2292 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
2293 ? cmd_buffer->state.compute_pipeline
2294 : cmd_buffer->state.pipeline;
2295 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2296 VK_PIPELINE_BIND_POINT_COMPUTE :
2297 VK_PIPELINE_BIND_POINT_GRAPHICS;
2298 struct radv_descriptor_state *descriptors_state =
2299 radv_get_descriptors_state(cmd_buffer, bind_point);
2300 struct radv_pipeline_layout *layout = pipeline->layout;
2301 struct radv_shader_variant *shader, *prev_shader;
2302 bool need_push_constants = false;
2303 unsigned offset;
2304 void *ptr;
2305 uint64_t va;
2306
2307 stages &= cmd_buffer->push_constant_stages;
2308 if (!stages ||
2309 (!layout->push_constant_size && !layout->dynamic_offset_count))
2310 return;
2311
2312 radv_foreach_stage(stage, stages) {
2313 if (!pipeline->shaders[stage])
2314 continue;
2315
2316 need_push_constants |= pipeline->shaders[stage]->info.loads_push_constants;
2317 need_push_constants |= pipeline->shaders[stage]->info.loads_dynamic_offsets;
2318
2319 uint8_t base = pipeline->shaders[stage]->info.base_inline_push_consts;
2320 uint8_t count = pipeline->shaders[stage]->info.num_inline_push_consts;
2321
2322 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
2323 AC_UD_INLINE_PUSH_CONSTANTS,
2324 count,
2325 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
2326 }
2327
2328 if (need_push_constants) {
2329 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
2330 16 * layout->dynamic_offset_count,
2331 256, &offset, &ptr))
2332 return;
2333
2334 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
2335 memcpy((char*)ptr + layout->push_constant_size,
2336 descriptors_state->dynamic_buffers,
2337 16 * layout->dynamic_offset_count);
2338
2339 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2340 va += offset;
2341
2342 ASSERTED unsigned cdw_max =
2343 radeon_check_space(cmd_buffer->device->ws,
2344 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
2345
2346 prev_shader = NULL;
2347 radv_foreach_stage(stage, stages) {
2348 shader = radv_get_shader(pipeline, stage);
2349
2350 /* Avoid redundantly emitting the address for merged stages. */
2351 if (shader && shader != prev_shader) {
2352 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
2353 AC_UD_PUSH_CONSTANTS, va);
2354
2355 prev_shader = shader;
2356 }
2357 }
2358 assert(cmd_buffer->cs->cdw <= cdw_max);
2359 }
2360
2361 cmd_buffer->push_constant_stages &= ~stages;
2362 }
2363
2364 static void
2365 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
2366 bool pipeline_is_dirty)
2367 {
2368 if ((pipeline_is_dirty ||
2369 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
2370 cmd_buffer->state.pipeline->num_vertex_bindings &&
2371 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.has_vertex_buffers) {
2372 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
2373 unsigned vb_offset;
2374 void *vb_ptr;
2375 uint32_t i = 0;
2376 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
2377 uint64_t va;
2378
2379 /* allocate some descriptor state for vertex buffers */
2380 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2381 &vb_offset, &vb_ptr))
2382 return;
2383
2384 for (i = 0; i < count; i++) {
2385 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2386 uint32_t offset;
2387 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2388 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[i];
2389
2390 if (!buffer)
2391 continue;
2392
2393 va = radv_buffer_get_va(buffer->bo);
2394
2395 offset = cmd_buffer->vertex_bindings[i].offset;
2396 va += offset + buffer->offset;
2397 desc[0] = va;
2398 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2399 if (cmd_buffer->device->physical_device->rad_info.chip_class <= GFX7 && stride)
2400 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
2401 else
2402 desc[2] = buffer->size - offset;
2403 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2404 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2405 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2406 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2407
2408 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2409 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT) |
2410 S_008F0C_OOB_SELECT(1) |
2411 S_008F0C_RESOURCE_LEVEL(1);
2412 } else {
2413 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2414 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2415 }
2416 }
2417
2418 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2419 va += vb_offset;
2420
2421 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2422 AC_UD_VS_VERTEX_BUFFERS, va);
2423
2424 cmd_buffer->state.vb_va = va;
2425 cmd_buffer->state.vb_size = count * 16;
2426 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2427 }
2428 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2429 }
2430
2431 static void
2432 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2433 {
2434 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2435 struct radv_userdata_info *loc;
2436 uint32_t base_reg;
2437
2438 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2439 if (!radv_get_shader(pipeline, stage))
2440 continue;
2441
2442 loc = radv_lookup_user_sgpr(pipeline, stage,
2443 AC_UD_STREAMOUT_BUFFERS);
2444 if (loc->sgpr_idx == -1)
2445 continue;
2446
2447 base_reg = pipeline->user_data_0[stage];
2448
2449 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2450 base_reg + loc->sgpr_idx * 4, va, false);
2451 }
2452
2453 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
2454 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2455 if (loc->sgpr_idx != -1) {
2456 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2457
2458 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2459 base_reg + loc->sgpr_idx * 4, va, false);
2460 }
2461 }
2462 }
2463
2464 static void
2465 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2466 {
2467 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2468 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2469 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2470 unsigned so_offset;
2471 void *so_ptr;
2472 uint64_t va;
2473
2474 /* Allocate some descriptor state for streamout buffers. */
2475 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2476 MAX_SO_BUFFERS * 16, 256,
2477 &so_offset, &so_ptr))
2478 return;
2479
2480 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2481 struct radv_buffer *buffer = sb[i].buffer;
2482 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2483
2484 if (!(so->enabled_mask & (1 << i)))
2485 continue;
2486
2487 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2488
2489 va += sb[i].offset;
2490
2491 /* Set the descriptor.
2492 *
2493 * On GFX8, the format must be non-INVALID, otherwise
2494 * the buffer will be considered not bound and store
2495 * instructions will be no-ops.
2496 */
2497 desc[0] = va;
2498 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2499 desc[2] = 0xffffffff;
2500 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2501 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2502 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2503 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2504
2505 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2506 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2507 S_008F0C_OOB_SELECT(3) |
2508 S_008F0C_RESOURCE_LEVEL(1);
2509 } else {
2510 desc[3] |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2511 }
2512 }
2513
2514 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2515 va += so_offset;
2516
2517 radv_emit_streamout_buffers(cmd_buffer, va);
2518 }
2519
2520 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2521 }
2522
2523 static void
2524 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2525 {
2526 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2527 radv_flush_streamout_descriptors(cmd_buffer);
2528 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2529 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2530 }
2531
2532 struct radv_draw_info {
2533 /**
2534 * Number of vertices.
2535 */
2536 uint32_t count;
2537
2538 /**
2539 * Index of the first vertex.
2540 */
2541 int32_t vertex_offset;
2542
2543 /**
2544 * First instance id.
2545 */
2546 uint32_t first_instance;
2547
2548 /**
2549 * Number of instances.
2550 */
2551 uint32_t instance_count;
2552
2553 /**
2554 * First index (indexed draws only).
2555 */
2556 uint32_t first_index;
2557
2558 /**
2559 * Whether it's an indexed draw.
2560 */
2561 bool indexed;
2562
2563 /**
2564 * Indirect draw parameters resource.
2565 */
2566 struct radv_buffer *indirect;
2567 uint64_t indirect_offset;
2568 uint32_t stride;
2569
2570 /**
2571 * Draw count parameters resource.
2572 */
2573 struct radv_buffer *count_buffer;
2574 uint64_t count_buffer_offset;
2575
2576 /**
2577 * Stream output parameters resource.
2578 */
2579 struct radv_buffer *strmout_buffer;
2580 uint64_t strmout_buffer_offset;
2581 };
2582
2583 static uint32_t
2584 radv_get_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
2585 {
2586 switch (cmd_buffer->state.index_type) {
2587 case V_028A7C_VGT_INDEX_8:
2588 return 0xffu;
2589 case V_028A7C_VGT_INDEX_16:
2590 return 0xffffu;
2591 case V_028A7C_VGT_INDEX_32:
2592 return 0xffffffffu;
2593 default:
2594 unreachable("invalid index type");
2595 }
2596 }
2597
2598 static void
2599 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
2600 bool instanced_draw, bool indirect_draw,
2601 bool count_from_stream_output,
2602 uint32_t draw_vertex_count)
2603 {
2604 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2605 struct radv_cmd_state *state = &cmd_buffer->state;
2606 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2607 unsigned ia_multi_vgt_param;
2608
2609 ia_multi_vgt_param =
2610 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
2611 indirect_draw,
2612 count_from_stream_output,
2613 draw_vertex_count);
2614
2615 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2616 if (info->chip_class == GFX9) {
2617 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2618 cs,
2619 R_030960_IA_MULTI_VGT_PARAM,
2620 4, ia_multi_vgt_param);
2621 } else if (info->chip_class >= GFX7) {
2622 radeon_set_context_reg_idx(cs,
2623 R_028AA8_IA_MULTI_VGT_PARAM,
2624 1, ia_multi_vgt_param);
2625 } else {
2626 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2627 ia_multi_vgt_param);
2628 }
2629 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2630 }
2631 }
2632
2633 static void
2634 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2635 const struct radv_draw_info *draw_info)
2636 {
2637 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2638 struct radv_cmd_state *state = &cmd_buffer->state;
2639 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2640 int32_t primitive_reset_en;
2641
2642 /* Draw state. */
2643 if (info->chip_class < GFX10) {
2644 si_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2645 draw_info->indirect,
2646 !!draw_info->strmout_buffer,
2647 draw_info->indirect ? 0 : draw_info->count);
2648 }
2649
2650 /* Primitive restart. */
2651 primitive_reset_en =
2652 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2653
2654 if (primitive_reset_en != state->last_primitive_reset_en) {
2655 state->last_primitive_reset_en = primitive_reset_en;
2656 if (info->chip_class >= GFX9) {
2657 radeon_set_uconfig_reg(cs,
2658 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2659 primitive_reset_en);
2660 } else {
2661 radeon_set_context_reg(cs,
2662 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2663 primitive_reset_en);
2664 }
2665 }
2666
2667 if (primitive_reset_en) {
2668 uint32_t primitive_reset_index =
2669 radv_get_primitive_reset_index(cmd_buffer);
2670
2671 if (primitive_reset_index != state->last_primitive_reset_index) {
2672 radeon_set_context_reg(cs,
2673 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2674 primitive_reset_index);
2675 state->last_primitive_reset_index = primitive_reset_index;
2676 }
2677 }
2678
2679 if (draw_info->strmout_buffer) {
2680 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2681
2682 va += draw_info->strmout_buffer->offset +
2683 draw_info->strmout_buffer_offset;
2684
2685 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2686 draw_info->stride);
2687
2688 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2689 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2690 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2691 COPY_DATA_WR_CONFIRM);
2692 radeon_emit(cs, va);
2693 radeon_emit(cs, va >> 32);
2694 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2695 radeon_emit(cs, 0); /* unused */
2696
2697 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2698 }
2699 }
2700
2701 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2702 VkPipelineStageFlags src_stage_mask)
2703 {
2704 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2705 VK_PIPELINE_STAGE_TRANSFER_BIT |
2706 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2707 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2708 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2709 }
2710
2711 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2712 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2713 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2714 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2715 VK_PIPELINE_STAGE_TRANSFER_BIT |
2716 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2717 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2718 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2719 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2720 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2721 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2722 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2723 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2724 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2725 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2726 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2727 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2728 }
2729 }
2730
2731 static enum radv_cmd_flush_bits
2732 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2733 VkAccessFlags src_flags,
2734 struct radv_image *image)
2735 {
2736 bool flush_CB_meta = true, flush_DB_meta = true;
2737 enum radv_cmd_flush_bits flush_bits = 0;
2738 uint32_t b;
2739
2740 if (image) {
2741 if (!radv_image_has_CB_metadata(image))
2742 flush_CB_meta = false;
2743 if (!radv_image_has_htile(image))
2744 flush_DB_meta = false;
2745 }
2746
2747 for_each_bit(b, src_flags) {
2748 switch ((VkAccessFlagBits)(1 << b)) {
2749 case VK_ACCESS_SHADER_WRITE_BIT:
2750 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2751 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2752 flush_bits |= RADV_CMD_FLAG_WB_L2;
2753 break;
2754 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2755 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2756 if (flush_CB_meta)
2757 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2758 break;
2759 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2760 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2761 if (flush_DB_meta)
2762 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2763 break;
2764 case VK_ACCESS_TRANSFER_WRITE_BIT:
2765 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2766 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2767 RADV_CMD_FLAG_INV_L2;
2768
2769 if (flush_CB_meta)
2770 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2771 if (flush_DB_meta)
2772 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2773 break;
2774 default:
2775 break;
2776 }
2777 }
2778 return flush_bits;
2779 }
2780
2781 static enum radv_cmd_flush_bits
2782 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2783 VkAccessFlags dst_flags,
2784 struct radv_image *image)
2785 {
2786 bool flush_CB_meta = true, flush_DB_meta = true;
2787 enum radv_cmd_flush_bits flush_bits = 0;
2788 bool flush_CB = true, flush_DB = true;
2789 bool image_is_coherent = false;
2790 uint32_t b;
2791
2792 if (image) {
2793 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2794 flush_CB = false;
2795 flush_DB = false;
2796 }
2797
2798 if (!radv_image_has_CB_metadata(image))
2799 flush_CB_meta = false;
2800 if (!radv_image_has_htile(image))
2801 flush_DB_meta = false;
2802
2803 /* TODO: implement shader coherent for GFX10 */
2804
2805 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
2806 if (image->info.samples == 1 &&
2807 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2808 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2809 !vk_format_is_stencil(image->vk_format)) {
2810 /* Single-sample color and single-sample depth
2811 * (not stencil) are coherent with shaders on
2812 * GFX9.
2813 */
2814 image_is_coherent = true;
2815 }
2816 }
2817 }
2818
2819 for_each_bit(b, dst_flags) {
2820 switch ((VkAccessFlagBits)(1 << b)) {
2821 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2822 case VK_ACCESS_INDEX_READ_BIT:
2823 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2824 break;
2825 case VK_ACCESS_UNIFORM_READ_BIT:
2826 flush_bits |= RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_SCACHE;
2827 break;
2828 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2829 case VK_ACCESS_TRANSFER_READ_BIT:
2830 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2831 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
2832 RADV_CMD_FLAG_INV_L2;
2833 break;
2834 case VK_ACCESS_SHADER_READ_BIT:
2835 flush_bits |= RADV_CMD_FLAG_INV_VCACHE;
2836
2837 if (!image_is_coherent)
2838 flush_bits |= RADV_CMD_FLAG_INV_L2;
2839 break;
2840 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2841 if (flush_CB)
2842 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2843 if (flush_CB_meta)
2844 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2845 break;
2846 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2847 if (flush_DB)
2848 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2849 if (flush_DB_meta)
2850 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2851 break;
2852 default:
2853 break;
2854 }
2855 }
2856 return flush_bits;
2857 }
2858
2859 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2860 const struct radv_subpass_barrier *barrier)
2861 {
2862 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2863 NULL);
2864 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2865 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2866 NULL);
2867 }
2868
2869 uint32_t
2870 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
2871 {
2872 struct radv_cmd_state *state = &cmd_buffer->state;
2873 uint32_t subpass_id = state->subpass - state->pass->subpasses;
2874
2875 /* The id of this subpass shouldn't exceed the number of subpasses in
2876 * this render pass minus 1.
2877 */
2878 assert(subpass_id < state->pass->subpass_count);
2879 return subpass_id;
2880 }
2881
2882 static struct radv_sample_locations_state *
2883 radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer,
2884 uint32_t att_idx,
2885 bool begin_subpass)
2886 {
2887 struct radv_cmd_state *state = &cmd_buffer->state;
2888 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
2889 struct radv_image_view *view = state->attachments[att_idx].iview;
2890
2891 if (view->image->info.samples == 1)
2892 return NULL;
2893
2894 if (state->pass->attachments[att_idx].first_subpass_idx == subpass_id) {
2895 /* Return the initial sample locations if this is the initial
2896 * layout transition of the given subpass attachemnt.
2897 */
2898 if (state->attachments[att_idx].sample_location.count > 0)
2899 return &state->attachments[att_idx].sample_location;
2900 } else {
2901 /* Otherwise return the subpass sample locations if defined. */
2902 if (state->subpass_sample_locs) {
2903 /* Because the driver sets the current subpass before
2904 * initial layout transitions, we should use the sample
2905 * locations from the previous subpass to avoid an
2906 * off-by-one problem. Otherwise, use the sample
2907 * locations for the current subpass for final layout
2908 * transitions.
2909 */
2910 if (begin_subpass)
2911 subpass_id--;
2912
2913 for (uint32_t i = 0; i < state->num_subpass_sample_locs; i++) {
2914 if (state->subpass_sample_locs[i].subpass_idx == subpass_id)
2915 return &state->subpass_sample_locs[i].sample_location;
2916 }
2917 }
2918 }
2919
2920 return NULL;
2921 }
2922
2923 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2924 struct radv_subpass_attachment att,
2925 bool begin_subpass)
2926 {
2927 unsigned idx = att.attachment;
2928 struct radv_image_view *view = cmd_buffer->state.attachments[idx].iview;
2929 struct radv_sample_locations_state *sample_locs;
2930 VkImageSubresourceRange range;
2931 range.aspectMask = 0;
2932 range.baseMipLevel = view->base_mip;
2933 range.levelCount = 1;
2934 range.baseArrayLayer = view->base_layer;
2935 range.layerCount = cmd_buffer->state.framebuffer->layers;
2936
2937 if (cmd_buffer->state.subpass->view_mask) {
2938 /* If the current subpass uses multiview, the driver might have
2939 * performed a fast color/depth clear to the whole image
2940 * (including all layers). To make sure the driver will
2941 * decompress the image correctly (if needed), we have to
2942 * account for the "real" number of layers. If the view mask is
2943 * sparse, this will decompress more layers than needed.
2944 */
2945 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
2946 }
2947
2948 /* Get the subpass sample locations for the given attachment, if NULL
2949 * is returned the driver will use the default HW locations.
2950 */
2951 sample_locs = radv_get_attachment_sample_locations(cmd_buffer, idx,
2952 begin_subpass);
2953
2954 radv_handle_image_transition(cmd_buffer,
2955 view->image,
2956 cmd_buffer->state.attachments[idx].current_layout,
2957 cmd_buffer->state.attachments[idx].current_in_render_loop,
2958 att.layout, att.in_render_loop,
2959 0, 0, &range, sample_locs);
2960
2961 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2962 cmd_buffer->state.attachments[idx].current_in_render_loop = att.in_render_loop;
2963
2964
2965 }
2966
2967 void
2968 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2969 const struct radv_subpass *subpass)
2970 {
2971 cmd_buffer->state.subpass = subpass;
2972
2973 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2974 }
2975
2976 static VkResult
2977 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
2978 struct radv_render_pass *pass,
2979 const VkRenderPassBeginInfo *info)
2980 {
2981 const struct VkRenderPassSampleLocationsBeginInfoEXT *sample_locs =
2982 vk_find_struct_const(info->pNext,
2983 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT);
2984 struct radv_cmd_state *state = &cmd_buffer->state;
2985
2986 if (!sample_locs) {
2987 state->subpass_sample_locs = NULL;
2988 return VK_SUCCESS;
2989 }
2990
2991 for (uint32_t i = 0; i < sample_locs->attachmentInitialSampleLocationsCount; i++) {
2992 const VkAttachmentSampleLocationsEXT *att_sample_locs =
2993 &sample_locs->pAttachmentInitialSampleLocations[i];
2994 uint32_t att_idx = att_sample_locs->attachmentIndex;
2995 struct radv_image *image = cmd_buffer->state.attachments[att_idx].iview->image;
2996
2997 assert(vk_format_is_depth_or_stencil(image->vk_format));
2998
2999 /* From the Vulkan spec 1.1.108:
3000 *
3001 * "If the image referenced by the framebuffer attachment at
3002 * index attachmentIndex was not created with
3003 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
3004 * then the values specified in sampleLocationsInfo are
3005 * ignored."
3006 */
3007 if (!(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT))
3008 continue;
3009
3010 const VkSampleLocationsInfoEXT *sample_locs_info =
3011 &att_sample_locs->sampleLocationsInfo;
3012
3013 state->attachments[att_idx].sample_location.per_pixel =
3014 sample_locs_info->sampleLocationsPerPixel;
3015 state->attachments[att_idx].sample_location.grid_size =
3016 sample_locs_info->sampleLocationGridSize;
3017 state->attachments[att_idx].sample_location.count =
3018 sample_locs_info->sampleLocationsCount;
3019 typed_memcpy(&state->attachments[att_idx].sample_location.locations[0],
3020 sample_locs_info->pSampleLocations,
3021 sample_locs_info->sampleLocationsCount);
3022 }
3023
3024 state->subpass_sample_locs = vk_alloc(&cmd_buffer->pool->alloc,
3025 sample_locs->postSubpassSampleLocationsCount *
3026 sizeof(state->subpass_sample_locs[0]),
3027 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3028 if (state->subpass_sample_locs == NULL) {
3029 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3030 return cmd_buffer->record_result;
3031 }
3032
3033 state->num_subpass_sample_locs = sample_locs->postSubpassSampleLocationsCount;
3034
3035 for (uint32_t i = 0; i < sample_locs->postSubpassSampleLocationsCount; i++) {
3036 const VkSubpassSampleLocationsEXT *subpass_sample_locs_info =
3037 &sample_locs->pPostSubpassSampleLocations[i];
3038 const VkSampleLocationsInfoEXT *sample_locs_info =
3039 &subpass_sample_locs_info->sampleLocationsInfo;
3040
3041 state->subpass_sample_locs[i].subpass_idx =
3042 subpass_sample_locs_info->subpassIndex;
3043 state->subpass_sample_locs[i].sample_location.per_pixel =
3044 sample_locs_info->sampleLocationsPerPixel;
3045 state->subpass_sample_locs[i].sample_location.grid_size =
3046 sample_locs_info->sampleLocationGridSize;
3047 state->subpass_sample_locs[i].sample_location.count =
3048 sample_locs_info->sampleLocationsCount;
3049 typed_memcpy(&state->subpass_sample_locs[i].sample_location.locations[0],
3050 sample_locs_info->pSampleLocations,
3051 sample_locs_info->sampleLocationsCount);
3052 }
3053
3054 return VK_SUCCESS;
3055 }
3056
3057 static VkResult
3058 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
3059 struct radv_render_pass *pass,
3060 const VkRenderPassBeginInfo *info)
3061 {
3062 struct radv_cmd_state *state = &cmd_buffer->state;
3063 const struct VkRenderPassAttachmentBeginInfoKHR *attachment_info = NULL;
3064
3065 if (info) {
3066 attachment_info = vk_find_struct_const(info->pNext,
3067 RENDER_PASS_ATTACHMENT_BEGIN_INFO_KHR);
3068 }
3069
3070
3071 if (pass->attachment_count == 0) {
3072 state->attachments = NULL;
3073 return VK_SUCCESS;
3074 }
3075
3076 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
3077 pass->attachment_count *
3078 sizeof(state->attachments[0]),
3079 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3080 if (state->attachments == NULL) {
3081 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3082 return cmd_buffer->record_result;
3083 }
3084
3085 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
3086 struct radv_render_pass_attachment *att = &pass->attachments[i];
3087 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
3088 VkImageAspectFlags clear_aspects = 0;
3089
3090 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
3091 /* color attachment */
3092 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3093 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
3094 }
3095 } else {
3096 /* depthstencil attachment */
3097 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
3098 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3099 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
3100 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3101 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
3102 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3103 }
3104 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3105 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3106 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3107 }
3108 }
3109
3110 state->attachments[i].pending_clear_aspects = clear_aspects;
3111 state->attachments[i].cleared_views = 0;
3112 if (clear_aspects && info) {
3113 assert(info->clearValueCount > i);
3114 state->attachments[i].clear_value = info->pClearValues[i];
3115 }
3116
3117 state->attachments[i].current_layout = att->initial_layout;
3118 state->attachments[i].sample_location.count = 0;
3119
3120 struct radv_image_view *iview;
3121 if (attachment_info && attachment_info->attachmentCount > i) {
3122 iview = radv_image_view_from_handle(attachment_info->pAttachments[i]);
3123 } else {
3124 iview = state->framebuffer->attachments[i];
3125 }
3126
3127 state->attachments[i].iview = iview;
3128 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3129 radv_initialise_ds_surface(cmd_buffer->device, &state->attachments[i].ds, iview);
3130 } else {
3131 radv_initialise_color_surface(cmd_buffer->device, &state->attachments[i].cb, iview);
3132 }
3133 }
3134
3135 return VK_SUCCESS;
3136 }
3137
3138 VkResult radv_AllocateCommandBuffers(
3139 VkDevice _device,
3140 const VkCommandBufferAllocateInfo *pAllocateInfo,
3141 VkCommandBuffer *pCommandBuffers)
3142 {
3143 RADV_FROM_HANDLE(radv_device, device, _device);
3144 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
3145
3146 VkResult result = VK_SUCCESS;
3147 uint32_t i;
3148
3149 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
3150
3151 if (!list_empty(&pool->free_cmd_buffers)) {
3152 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
3153
3154 list_del(&cmd_buffer->pool_link);
3155 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
3156
3157 result = radv_reset_cmd_buffer(cmd_buffer);
3158 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
3159 cmd_buffer->level = pAllocateInfo->level;
3160
3161 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
3162 } else {
3163 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
3164 &pCommandBuffers[i]);
3165 }
3166 if (result != VK_SUCCESS)
3167 break;
3168 }
3169
3170 if (result != VK_SUCCESS) {
3171 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
3172 i, pCommandBuffers);
3173
3174 /* From the Vulkan 1.0.66 spec:
3175 *
3176 * "vkAllocateCommandBuffers can be used to create multiple
3177 * command buffers. If the creation of any of those command
3178 * buffers fails, the implementation must destroy all
3179 * successfully created command buffer objects from this
3180 * command, set all entries of the pCommandBuffers array to
3181 * NULL and return the error."
3182 */
3183 memset(pCommandBuffers, 0,
3184 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
3185 }
3186
3187 return result;
3188 }
3189
3190 void radv_FreeCommandBuffers(
3191 VkDevice device,
3192 VkCommandPool commandPool,
3193 uint32_t commandBufferCount,
3194 const VkCommandBuffer *pCommandBuffers)
3195 {
3196 for (uint32_t i = 0; i < commandBufferCount; i++) {
3197 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
3198
3199 if (cmd_buffer) {
3200 if (cmd_buffer->pool) {
3201 list_del(&cmd_buffer->pool_link);
3202 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
3203 } else
3204 radv_cmd_buffer_destroy(cmd_buffer);
3205
3206 }
3207 }
3208 }
3209
3210 VkResult radv_ResetCommandBuffer(
3211 VkCommandBuffer commandBuffer,
3212 VkCommandBufferResetFlags flags)
3213 {
3214 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3215 return radv_reset_cmd_buffer(cmd_buffer);
3216 }
3217
3218 VkResult radv_BeginCommandBuffer(
3219 VkCommandBuffer commandBuffer,
3220 const VkCommandBufferBeginInfo *pBeginInfo)
3221 {
3222 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3223 VkResult result = VK_SUCCESS;
3224
3225 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
3226 /* If the command buffer has already been resetted with
3227 * vkResetCommandBuffer, no need to do it again.
3228 */
3229 result = radv_reset_cmd_buffer(cmd_buffer);
3230 if (result != VK_SUCCESS)
3231 return result;
3232 }
3233
3234 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
3235 cmd_buffer->state.last_primitive_reset_en = -1;
3236 cmd_buffer->state.last_index_type = -1;
3237 cmd_buffer->state.last_num_instances = -1;
3238 cmd_buffer->state.last_vertex_offset = -1;
3239 cmd_buffer->state.last_first_instance = -1;
3240 cmd_buffer->state.predication_type = -1;
3241 cmd_buffer->usage_flags = pBeginInfo->flags;
3242
3243 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
3244 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
3245 assert(pBeginInfo->pInheritanceInfo);
3246 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
3247 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
3248
3249 struct radv_subpass *subpass =
3250 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
3251
3252 if (cmd_buffer->state.framebuffer) {
3253 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
3254 if (result != VK_SUCCESS)
3255 return result;
3256 }
3257
3258 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3259 }
3260
3261 if (unlikely(cmd_buffer->device->trace_bo)) {
3262 struct radv_device *device = cmd_buffer->device;
3263
3264 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
3265 device->trace_bo);
3266
3267 radv_cmd_buffer_trace_emit(cmd_buffer);
3268 }
3269
3270 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
3271
3272 return result;
3273 }
3274
3275 void radv_CmdBindVertexBuffers(
3276 VkCommandBuffer commandBuffer,
3277 uint32_t firstBinding,
3278 uint32_t bindingCount,
3279 const VkBuffer* pBuffers,
3280 const VkDeviceSize* pOffsets)
3281 {
3282 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3283 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
3284 bool changed = false;
3285
3286 /* We have to defer setting up vertex buffer since we need the buffer
3287 * stride from the pipeline. */
3288
3289 assert(firstBinding + bindingCount <= MAX_VBS);
3290 for (uint32_t i = 0; i < bindingCount; i++) {
3291 uint32_t idx = firstBinding + i;
3292
3293 if (!changed &&
3294 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
3295 vb[idx].offset != pOffsets[i])) {
3296 changed = true;
3297 }
3298
3299 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
3300 vb[idx].offset = pOffsets[i];
3301
3302 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3303 vb[idx].buffer->bo);
3304 }
3305
3306 if (!changed) {
3307 /* No state changes. */
3308 return;
3309 }
3310
3311 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
3312 }
3313
3314 static uint32_t
3315 vk_to_index_type(VkIndexType type)
3316 {
3317 switch (type) {
3318 case VK_INDEX_TYPE_UINT8_EXT:
3319 return V_028A7C_VGT_INDEX_8;
3320 case VK_INDEX_TYPE_UINT16:
3321 return V_028A7C_VGT_INDEX_16;
3322 case VK_INDEX_TYPE_UINT32:
3323 return V_028A7C_VGT_INDEX_32;
3324 default:
3325 unreachable("invalid index type");
3326 }
3327 }
3328
3329 static uint32_t
3330 radv_get_vgt_index_size(uint32_t type)
3331 {
3332 switch (type) {
3333 case V_028A7C_VGT_INDEX_8:
3334 return 1;
3335 case V_028A7C_VGT_INDEX_16:
3336 return 2;
3337 case V_028A7C_VGT_INDEX_32:
3338 return 4;
3339 default:
3340 unreachable("invalid index type");
3341 }
3342 }
3343
3344 void radv_CmdBindIndexBuffer(
3345 VkCommandBuffer commandBuffer,
3346 VkBuffer buffer,
3347 VkDeviceSize offset,
3348 VkIndexType indexType)
3349 {
3350 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3351 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
3352
3353 if (cmd_buffer->state.index_buffer == index_buffer &&
3354 cmd_buffer->state.index_offset == offset &&
3355 cmd_buffer->state.index_type == indexType) {
3356 /* No state changes. */
3357 return;
3358 }
3359
3360 cmd_buffer->state.index_buffer = index_buffer;
3361 cmd_buffer->state.index_offset = offset;
3362 cmd_buffer->state.index_type = vk_to_index_type(indexType);
3363 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
3364 cmd_buffer->state.index_va += index_buffer->offset + offset;
3365
3366 int index_size = radv_get_vgt_index_size(vk_to_index_type(indexType));
3367 cmd_buffer->state.max_index_count = (index_buffer->size - offset) / index_size;
3368 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3369 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
3370 }
3371
3372
3373 static void
3374 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3375 VkPipelineBindPoint bind_point,
3376 struct radv_descriptor_set *set, unsigned idx)
3377 {
3378 struct radeon_winsys *ws = cmd_buffer->device->ws;
3379
3380 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
3381
3382 assert(set);
3383 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
3384
3385 if (!cmd_buffer->device->use_global_bo_list) {
3386 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3387 if (set->descriptors[j])
3388 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
3389 }
3390
3391 if(set->bo)
3392 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
3393 }
3394
3395 void radv_CmdBindDescriptorSets(
3396 VkCommandBuffer commandBuffer,
3397 VkPipelineBindPoint pipelineBindPoint,
3398 VkPipelineLayout _layout,
3399 uint32_t firstSet,
3400 uint32_t descriptorSetCount,
3401 const VkDescriptorSet* pDescriptorSets,
3402 uint32_t dynamicOffsetCount,
3403 const uint32_t* pDynamicOffsets)
3404 {
3405 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3406 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3407 unsigned dyn_idx = 0;
3408
3409 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
3410 struct radv_descriptor_state *descriptors_state =
3411 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3412
3413 for (unsigned i = 0; i < descriptorSetCount; ++i) {
3414 unsigned idx = i + firstSet;
3415 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
3416
3417 /* If the set is already bound we only need to update the
3418 * (potentially changed) dynamic offsets. */
3419 if (descriptors_state->sets[idx] != set ||
3420 !(descriptors_state->valid & (1u << idx))) {
3421 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
3422 }
3423
3424 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
3425 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
3426 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
3427 assert(dyn_idx < dynamicOffsetCount);
3428
3429 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
3430 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
3431 dst[0] = va;
3432 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
3433 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
3434 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3435 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3436 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3437 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3438
3439 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
3440 dst[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3441 S_008F0C_OOB_SELECT(3) |
3442 S_008F0C_RESOURCE_LEVEL(1);
3443 } else {
3444 dst[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3445 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3446 }
3447
3448 cmd_buffer->push_constant_stages |=
3449 set->layout->dynamic_shader_stages;
3450 }
3451 }
3452 }
3453
3454 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3455 struct radv_descriptor_set *set,
3456 struct radv_descriptor_set_layout *layout,
3457 VkPipelineBindPoint bind_point)
3458 {
3459 struct radv_descriptor_state *descriptors_state =
3460 radv_get_descriptors_state(cmd_buffer, bind_point);
3461 set->size = layout->size;
3462 set->layout = layout;
3463
3464 if (descriptors_state->push_set.capacity < set->size) {
3465 size_t new_size = MAX2(set->size, 1024);
3466 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
3467 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
3468
3469 free(set->mapped_ptr);
3470 set->mapped_ptr = malloc(new_size);
3471
3472 if (!set->mapped_ptr) {
3473 descriptors_state->push_set.capacity = 0;
3474 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3475 return false;
3476 }
3477
3478 descriptors_state->push_set.capacity = new_size;
3479 }
3480
3481 return true;
3482 }
3483
3484 void radv_meta_push_descriptor_set(
3485 struct radv_cmd_buffer* cmd_buffer,
3486 VkPipelineBindPoint pipelineBindPoint,
3487 VkPipelineLayout _layout,
3488 uint32_t set,
3489 uint32_t descriptorWriteCount,
3490 const VkWriteDescriptorSet* pDescriptorWrites)
3491 {
3492 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3493 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
3494 unsigned bo_offset;
3495
3496 assert(set == 0);
3497 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3498
3499 push_set->size = layout->set[set].layout->size;
3500 push_set->layout = layout->set[set].layout;
3501
3502 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
3503 &bo_offset,
3504 (void**) &push_set->mapped_ptr))
3505 return;
3506
3507 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
3508 push_set->va += bo_offset;
3509
3510 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3511 radv_descriptor_set_to_handle(push_set),
3512 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3513
3514 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3515 }
3516
3517 void radv_CmdPushDescriptorSetKHR(
3518 VkCommandBuffer commandBuffer,
3519 VkPipelineBindPoint pipelineBindPoint,
3520 VkPipelineLayout _layout,
3521 uint32_t set,
3522 uint32_t descriptorWriteCount,
3523 const VkWriteDescriptorSet* pDescriptorWrites)
3524 {
3525 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3526 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3527 struct radv_descriptor_state *descriptors_state =
3528 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3529 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3530
3531 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3532
3533 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3534 layout->set[set].layout,
3535 pipelineBindPoint))
3536 return;
3537
3538 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3539 * because it is invalid, according to Vulkan spec.
3540 */
3541 for (int i = 0; i < descriptorWriteCount; i++) {
3542 ASSERTED const VkWriteDescriptorSet *writeset = &pDescriptorWrites[i];
3543 assert(writeset->descriptorType != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT);
3544 }
3545
3546 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3547 radv_descriptor_set_to_handle(push_set),
3548 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3549
3550 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3551 descriptors_state->push_dirty = true;
3552 }
3553
3554 void radv_CmdPushDescriptorSetWithTemplateKHR(
3555 VkCommandBuffer commandBuffer,
3556 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
3557 VkPipelineLayout _layout,
3558 uint32_t set,
3559 const void* pData)
3560 {
3561 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3562 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3563 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
3564 struct radv_descriptor_state *descriptors_state =
3565 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
3566 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3567
3568 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3569
3570 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3571 layout->set[set].layout,
3572 templ->bind_point))
3573 return;
3574
3575 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
3576 descriptorUpdateTemplate, pData);
3577
3578 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
3579 descriptors_state->push_dirty = true;
3580 }
3581
3582 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
3583 VkPipelineLayout layout,
3584 VkShaderStageFlags stageFlags,
3585 uint32_t offset,
3586 uint32_t size,
3587 const void* pValues)
3588 {
3589 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3590 memcpy(cmd_buffer->push_constants + offset, pValues, size);
3591 cmd_buffer->push_constant_stages |= stageFlags;
3592 }
3593
3594 VkResult radv_EndCommandBuffer(
3595 VkCommandBuffer commandBuffer)
3596 {
3597 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3598
3599 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
3600 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6)
3601 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WB_L2;
3602
3603 /* Make sure to sync all pending active queries at the end of
3604 * command buffer.
3605 */
3606 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
3607
3608 si_emit_cache_flush(cmd_buffer);
3609 }
3610
3611 /* Make sure CP DMA is idle at the end of IBs because the kernel
3612 * doesn't wait for it.
3613 */
3614 si_cp_dma_wait_for_idle(cmd_buffer);
3615
3616 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3617 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
3618
3619 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
3620 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3621
3622 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
3623
3624 return cmd_buffer->record_result;
3625 }
3626
3627 static void
3628 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
3629 {
3630 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3631
3632 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
3633 return;
3634
3635 assert(!pipeline->ctx_cs.cdw);
3636
3637 cmd_buffer->state.emitted_compute_pipeline = pipeline;
3638
3639 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
3640 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
3641
3642 cmd_buffer->compute_scratch_size_needed =
3643 MAX2(cmd_buffer->compute_scratch_size_needed,
3644 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
3645
3646 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3647 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
3648
3649 if (unlikely(cmd_buffer->device->trace_bo))
3650 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
3651 }
3652
3653 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
3654 VkPipelineBindPoint bind_point)
3655 {
3656 struct radv_descriptor_state *descriptors_state =
3657 radv_get_descriptors_state(cmd_buffer, bind_point);
3658
3659 descriptors_state->dirty |= descriptors_state->valid;
3660 }
3661
3662 void radv_CmdBindPipeline(
3663 VkCommandBuffer commandBuffer,
3664 VkPipelineBindPoint pipelineBindPoint,
3665 VkPipeline _pipeline)
3666 {
3667 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3668 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
3669
3670 switch (pipelineBindPoint) {
3671 case VK_PIPELINE_BIND_POINT_COMPUTE:
3672 if (cmd_buffer->state.compute_pipeline == pipeline)
3673 return;
3674 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3675
3676 cmd_buffer->state.compute_pipeline = pipeline;
3677 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
3678 break;
3679 case VK_PIPELINE_BIND_POINT_GRAPHICS:
3680 if (cmd_buffer->state.pipeline == pipeline)
3681 return;
3682 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3683
3684 cmd_buffer->state.pipeline = pipeline;
3685 if (!pipeline)
3686 break;
3687
3688 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
3689 cmd_buffer->push_constant_stages |= pipeline->active_stages;
3690
3691 /* the new vertex shader might not have the same user regs */
3692 cmd_buffer->state.last_first_instance = -1;
3693 cmd_buffer->state.last_vertex_offset = -1;
3694
3695 /* Prefetch all pipeline shaders at first draw time. */
3696 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
3697
3698 if ((cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI10 ||
3699 cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI12 ||
3700 cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI14) &&
3701 cmd_buffer->state.emitted_pipeline &&
3702 radv_pipeline_has_ngg(cmd_buffer->state.emitted_pipeline) &&
3703 !radv_pipeline_has_ngg(cmd_buffer->state.pipeline)) {
3704 /* Transitioning from NGG to legacy GS requires
3705 * VGT_FLUSH on Navi10-14. VGT_FLUSH is also emitted
3706 * at the beginning of IBs when legacy GS ring pointers
3707 * are set.
3708 */
3709 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
3710 }
3711
3712 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
3713 radv_bind_streamout_state(cmd_buffer, pipeline);
3714
3715 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
3716 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
3717 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
3718 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
3719
3720 if (radv_pipeline_has_tess(pipeline))
3721 cmd_buffer->tess_rings_needed = true;
3722 break;
3723 default:
3724 assert(!"invalid bind point");
3725 break;
3726 }
3727 }
3728
3729 void radv_CmdSetViewport(
3730 VkCommandBuffer commandBuffer,
3731 uint32_t firstViewport,
3732 uint32_t viewportCount,
3733 const VkViewport* pViewports)
3734 {
3735 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3736 struct radv_cmd_state *state = &cmd_buffer->state;
3737 ASSERTED const uint32_t total_count = firstViewport + viewportCount;
3738
3739 assert(firstViewport < MAX_VIEWPORTS);
3740 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
3741
3742 if (!memcmp(state->dynamic.viewport.viewports + firstViewport,
3743 pViewports, viewportCount * sizeof(*pViewports))) {
3744 return;
3745 }
3746
3747 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
3748 viewportCount * sizeof(*pViewports));
3749
3750 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
3751 }
3752
3753 void radv_CmdSetScissor(
3754 VkCommandBuffer commandBuffer,
3755 uint32_t firstScissor,
3756 uint32_t scissorCount,
3757 const VkRect2D* pScissors)
3758 {
3759 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3760 struct radv_cmd_state *state = &cmd_buffer->state;
3761 ASSERTED const uint32_t total_count = firstScissor + scissorCount;
3762
3763 assert(firstScissor < MAX_SCISSORS);
3764 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
3765
3766 if (!memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
3767 scissorCount * sizeof(*pScissors))) {
3768 return;
3769 }
3770
3771 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
3772 scissorCount * sizeof(*pScissors));
3773
3774 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
3775 }
3776
3777 void radv_CmdSetLineWidth(
3778 VkCommandBuffer commandBuffer,
3779 float lineWidth)
3780 {
3781 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3782
3783 if (cmd_buffer->state.dynamic.line_width == lineWidth)
3784 return;
3785
3786 cmd_buffer->state.dynamic.line_width = lineWidth;
3787 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
3788 }
3789
3790 void radv_CmdSetDepthBias(
3791 VkCommandBuffer commandBuffer,
3792 float depthBiasConstantFactor,
3793 float depthBiasClamp,
3794 float depthBiasSlopeFactor)
3795 {
3796 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3797 struct radv_cmd_state *state = &cmd_buffer->state;
3798
3799 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
3800 state->dynamic.depth_bias.clamp == depthBiasClamp &&
3801 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
3802 return;
3803 }
3804
3805 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
3806 state->dynamic.depth_bias.clamp = depthBiasClamp;
3807 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
3808
3809 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
3810 }
3811
3812 void radv_CmdSetBlendConstants(
3813 VkCommandBuffer commandBuffer,
3814 const float blendConstants[4])
3815 {
3816 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3817 struct radv_cmd_state *state = &cmd_buffer->state;
3818
3819 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
3820 return;
3821
3822 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
3823
3824 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
3825 }
3826
3827 void radv_CmdSetDepthBounds(
3828 VkCommandBuffer commandBuffer,
3829 float minDepthBounds,
3830 float maxDepthBounds)
3831 {
3832 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3833 struct radv_cmd_state *state = &cmd_buffer->state;
3834
3835 if (state->dynamic.depth_bounds.min == minDepthBounds &&
3836 state->dynamic.depth_bounds.max == maxDepthBounds) {
3837 return;
3838 }
3839
3840 state->dynamic.depth_bounds.min = minDepthBounds;
3841 state->dynamic.depth_bounds.max = maxDepthBounds;
3842
3843 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
3844 }
3845
3846 void radv_CmdSetStencilCompareMask(
3847 VkCommandBuffer commandBuffer,
3848 VkStencilFaceFlags faceMask,
3849 uint32_t compareMask)
3850 {
3851 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3852 struct radv_cmd_state *state = &cmd_buffer->state;
3853 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
3854 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
3855
3856 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3857 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3858 return;
3859 }
3860
3861 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3862 state->dynamic.stencil_compare_mask.front = compareMask;
3863 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3864 state->dynamic.stencil_compare_mask.back = compareMask;
3865
3866 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
3867 }
3868
3869 void radv_CmdSetStencilWriteMask(
3870 VkCommandBuffer commandBuffer,
3871 VkStencilFaceFlags faceMask,
3872 uint32_t writeMask)
3873 {
3874 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3875 struct radv_cmd_state *state = &cmd_buffer->state;
3876 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
3877 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
3878
3879 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3880 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3881 return;
3882 }
3883
3884 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3885 state->dynamic.stencil_write_mask.front = writeMask;
3886 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3887 state->dynamic.stencil_write_mask.back = writeMask;
3888
3889 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
3890 }
3891
3892 void radv_CmdSetStencilReference(
3893 VkCommandBuffer commandBuffer,
3894 VkStencilFaceFlags faceMask,
3895 uint32_t reference)
3896 {
3897 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3898 struct radv_cmd_state *state = &cmd_buffer->state;
3899 bool front_same = state->dynamic.stencil_reference.front == reference;
3900 bool back_same = state->dynamic.stencil_reference.back == reference;
3901
3902 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3903 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3904 return;
3905 }
3906
3907 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3908 cmd_buffer->state.dynamic.stencil_reference.front = reference;
3909 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3910 cmd_buffer->state.dynamic.stencil_reference.back = reference;
3911
3912 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
3913 }
3914
3915 void radv_CmdSetDiscardRectangleEXT(
3916 VkCommandBuffer commandBuffer,
3917 uint32_t firstDiscardRectangle,
3918 uint32_t discardRectangleCount,
3919 const VkRect2D* pDiscardRectangles)
3920 {
3921 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3922 struct radv_cmd_state *state = &cmd_buffer->state;
3923 ASSERTED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
3924
3925 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
3926 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
3927
3928 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
3929 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
3930 return;
3931 }
3932
3933 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
3934 pDiscardRectangles, discardRectangleCount);
3935
3936 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
3937 }
3938
3939 void radv_CmdSetSampleLocationsEXT(
3940 VkCommandBuffer commandBuffer,
3941 const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
3942 {
3943 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3944 struct radv_cmd_state *state = &cmd_buffer->state;
3945
3946 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
3947
3948 state->dynamic.sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
3949 state->dynamic.sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
3950 state->dynamic.sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
3951 typed_memcpy(&state->dynamic.sample_location.locations[0],
3952 pSampleLocationsInfo->pSampleLocations,
3953 pSampleLocationsInfo->sampleLocationsCount);
3954
3955 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS;
3956 }
3957
3958 void radv_CmdExecuteCommands(
3959 VkCommandBuffer commandBuffer,
3960 uint32_t commandBufferCount,
3961 const VkCommandBuffer* pCmdBuffers)
3962 {
3963 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
3964
3965 assert(commandBufferCount > 0);
3966
3967 /* Emit pending flushes on primary prior to executing secondary */
3968 si_emit_cache_flush(primary);
3969
3970 for (uint32_t i = 0; i < commandBufferCount; i++) {
3971 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
3972
3973 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
3974 secondary->scratch_size_needed);
3975 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
3976 secondary->compute_scratch_size_needed);
3977
3978 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
3979 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
3980 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
3981 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
3982 if (secondary->tess_rings_needed)
3983 primary->tess_rings_needed = true;
3984 if (secondary->sample_positions_needed)
3985 primary->sample_positions_needed = true;
3986
3987 if (!secondary->state.framebuffer &&
3988 (primary->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)) {
3989 /* Emit the framebuffer state from primary if secondary
3990 * has been recorded without a framebuffer, otherwise
3991 * fast color/depth clears can't work.
3992 */
3993 radv_emit_framebuffer_state(primary);
3994 }
3995
3996 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
3997
3998
3999 /* When the secondary command buffer is compute only we don't
4000 * need to re-emit the current graphics pipeline.
4001 */
4002 if (secondary->state.emitted_pipeline) {
4003 primary->state.emitted_pipeline =
4004 secondary->state.emitted_pipeline;
4005 }
4006
4007 /* When the secondary command buffer is graphics only we don't
4008 * need to re-emit the current compute pipeline.
4009 */
4010 if (secondary->state.emitted_compute_pipeline) {
4011 primary->state.emitted_compute_pipeline =
4012 secondary->state.emitted_compute_pipeline;
4013 }
4014
4015 /* Only re-emit the draw packets when needed. */
4016 if (secondary->state.last_primitive_reset_en != -1) {
4017 primary->state.last_primitive_reset_en =
4018 secondary->state.last_primitive_reset_en;
4019 }
4020
4021 if (secondary->state.last_primitive_reset_index) {
4022 primary->state.last_primitive_reset_index =
4023 secondary->state.last_primitive_reset_index;
4024 }
4025
4026 if (secondary->state.last_ia_multi_vgt_param) {
4027 primary->state.last_ia_multi_vgt_param =
4028 secondary->state.last_ia_multi_vgt_param;
4029 }
4030
4031 primary->state.last_first_instance = secondary->state.last_first_instance;
4032 primary->state.last_num_instances = secondary->state.last_num_instances;
4033 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
4034
4035 if (secondary->state.last_index_type != -1) {
4036 primary->state.last_index_type =
4037 secondary->state.last_index_type;
4038 }
4039 }
4040
4041 /* After executing commands from secondary buffers we have to dirty
4042 * some states.
4043 */
4044 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
4045 RADV_CMD_DIRTY_INDEX_BUFFER |
4046 RADV_CMD_DIRTY_DYNAMIC_ALL;
4047 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
4048 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
4049 }
4050
4051 VkResult radv_CreateCommandPool(
4052 VkDevice _device,
4053 const VkCommandPoolCreateInfo* pCreateInfo,
4054 const VkAllocationCallbacks* pAllocator,
4055 VkCommandPool* pCmdPool)
4056 {
4057 RADV_FROM_HANDLE(radv_device, device, _device);
4058 struct radv_cmd_pool *pool;
4059
4060 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
4061 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4062 if (pool == NULL)
4063 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4064
4065 if (pAllocator)
4066 pool->alloc = *pAllocator;
4067 else
4068 pool->alloc = device->alloc;
4069
4070 list_inithead(&pool->cmd_buffers);
4071 list_inithead(&pool->free_cmd_buffers);
4072
4073 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
4074
4075 *pCmdPool = radv_cmd_pool_to_handle(pool);
4076
4077 return VK_SUCCESS;
4078
4079 }
4080
4081 void radv_DestroyCommandPool(
4082 VkDevice _device,
4083 VkCommandPool commandPool,
4084 const VkAllocationCallbacks* pAllocator)
4085 {
4086 RADV_FROM_HANDLE(radv_device, device, _device);
4087 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4088
4089 if (!pool)
4090 return;
4091
4092 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4093 &pool->cmd_buffers, pool_link) {
4094 radv_cmd_buffer_destroy(cmd_buffer);
4095 }
4096
4097 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4098 &pool->free_cmd_buffers, pool_link) {
4099 radv_cmd_buffer_destroy(cmd_buffer);
4100 }
4101
4102 vk_free2(&device->alloc, pAllocator, pool);
4103 }
4104
4105 VkResult radv_ResetCommandPool(
4106 VkDevice device,
4107 VkCommandPool commandPool,
4108 VkCommandPoolResetFlags flags)
4109 {
4110 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4111 VkResult result;
4112
4113 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
4114 &pool->cmd_buffers, pool_link) {
4115 result = radv_reset_cmd_buffer(cmd_buffer);
4116 if (result != VK_SUCCESS)
4117 return result;
4118 }
4119
4120 return VK_SUCCESS;
4121 }
4122
4123 void radv_TrimCommandPool(
4124 VkDevice device,
4125 VkCommandPool commandPool,
4126 VkCommandPoolTrimFlags flags)
4127 {
4128 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4129
4130 if (!pool)
4131 return;
4132
4133 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4134 &pool->free_cmd_buffers, pool_link) {
4135 radv_cmd_buffer_destroy(cmd_buffer);
4136 }
4137 }
4138
4139 static void
4140 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
4141 uint32_t subpass_id)
4142 {
4143 struct radv_cmd_state *state = &cmd_buffer->state;
4144 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
4145
4146 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
4147 cmd_buffer->cs, 4096);
4148
4149 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
4150
4151 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
4152
4153 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4154 const uint32_t a = subpass->attachments[i].attachment;
4155 if (a == VK_ATTACHMENT_UNUSED)
4156 continue;
4157
4158 radv_handle_subpass_image_transition(cmd_buffer,
4159 subpass->attachments[i],
4160 true);
4161 }
4162
4163 radv_cmd_buffer_clear_subpass(cmd_buffer);
4164
4165 assert(cmd_buffer->cs->cdw <= cdw_max);
4166 }
4167
4168 static void
4169 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
4170 {
4171 struct radv_cmd_state *state = &cmd_buffer->state;
4172 const struct radv_subpass *subpass = state->subpass;
4173 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
4174
4175 radv_cmd_buffer_resolve_subpass(cmd_buffer);
4176
4177 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4178 const uint32_t a = subpass->attachments[i].attachment;
4179 if (a == VK_ATTACHMENT_UNUSED)
4180 continue;
4181
4182 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
4183 continue;
4184
4185 VkImageLayout layout = state->pass->attachments[a].final_layout;
4186 struct radv_subpass_attachment att = { a, layout };
4187 radv_handle_subpass_image_transition(cmd_buffer, att, false);
4188 }
4189 }
4190
4191 void radv_CmdBeginRenderPass(
4192 VkCommandBuffer commandBuffer,
4193 const VkRenderPassBeginInfo* pRenderPassBegin,
4194 VkSubpassContents contents)
4195 {
4196 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4197 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
4198 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
4199 VkResult result;
4200
4201 cmd_buffer->state.framebuffer = framebuffer;
4202 cmd_buffer->state.pass = pass;
4203 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
4204
4205 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
4206 if (result != VK_SUCCESS)
4207 return;
4208
4209 result = radv_cmd_state_setup_sample_locations(cmd_buffer, pass, pRenderPassBegin);
4210 if (result != VK_SUCCESS)
4211 return;
4212
4213 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
4214 }
4215
4216 void radv_CmdBeginRenderPass2KHR(
4217 VkCommandBuffer commandBuffer,
4218 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
4219 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
4220 {
4221 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
4222 pSubpassBeginInfo->contents);
4223 }
4224
4225 void radv_CmdNextSubpass(
4226 VkCommandBuffer commandBuffer,
4227 VkSubpassContents contents)
4228 {
4229 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4230
4231 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
4232 radv_cmd_buffer_end_subpass(cmd_buffer);
4233 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
4234 }
4235
4236 void radv_CmdNextSubpass2KHR(
4237 VkCommandBuffer commandBuffer,
4238 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
4239 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4240 {
4241 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
4242 }
4243
4244 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
4245 {
4246 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
4247 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
4248 if (!radv_get_shader(pipeline, stage))
4249 continue;
4250
4251 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
4252 if (loc->sgpr_idx == -1)
4253 continue;
4254 uint32_t base_reg = pipeline->user_data_0[stage];
4255 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4256
4257 }
4258 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
4259 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
4260 if (loc->sgpr_idx != -1) {
4261 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
4262 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4263 }
4264 }
4265 }
4266
4267 static void
4268 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4269 uint32_t vertex_count,
4270 bool use_opaque)
4271 {
4272 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
4273 radeon_emit(cmd_buffer->cs, vertex_count);
4274 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
4275 S_0287F0_USE_OPAQUE(use_opaque));
4276 }
4277
4278 static void
4279 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
4280 uint64_t index_va,
4281 uint32_t index_count)
4282 {
4283 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
4284 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
4285 radeon_emit(cmd_buffer->cs, index_va);
4286 radeon_emit(cmd_buffer->cs, index_va >> 32);
4287 radeon_emit(cmd_buffer->cs, index_count);
4288 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
4289 }
4290
4291 static void
4292 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4293 bool indexed,
4294 uint32_t draw_count,
4295 uint64_t count_va,
4296 uint32_t stride)
4297 {
4298 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4299 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
4300 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
4301 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id;
4302 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
4303 bool predicating = cmd_buffer->state.predicating;
4304 assert(base_reg);
4305
4306 /* just reset draw state for vertex data */
4307 cmd_buffer->state.last_first_instance = -1;
4308 cmd_buffer->state.last_num_instances = -1;
4309 cmd_buffer->state.last_vertex_offset = -1;
4310
4311 if (draw_count == 1 && !count_va && !draw_id_enable) {
4312 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
4313 PKT3_DRAW_INDIRECT, 3, predicating));
4314 radeon_emit(cs, 0);
4315 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4316 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4317 radeon_emit(cs, di_src_sel);
4318 } else {
4319 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
4320 PKT3_DRAW_INDIRECT_MULTI,
4321 8, predicating));
4322 radeon_emit(cs, 0);
4323 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4324 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4325 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
4326 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
4327 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
4328 radeon_emit(cs, draw_count); /* count */
4329 radeon_emit(cs, count_va); /* count_addr */
4330 radeon_emit(cs, count_va >> 32);
4331 radeon_emit(cs, stride); /* stride */
4332 radeon_emit(cs, di_src_sel);
4333 }
4334 }
4335
4336 static void
4337 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
4338 const struct radv_draw_info *info)
4339 {
4340 struct radv_cmd_state *state = &cmd_buffer->state;
4341 struct radeon_winsys *ws = cmd_buffer->device->ws;
4342 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4343
4344 if (info->indirect) {
4345 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4346 uint64_t count_va = 0;
4347
4348 va += info->indirect->offset + info->indirect_offset;
4349
4350 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4351
4352 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
4353 radeon_emit(cs, 1);
4354 radeon_emit(cs, va);
4355 radeon_emit(cs, va >> 32);
4356
4357 if (info->count_buffer) {
4358 count_va = radv_buffer_get_va(info->count_buffer->bo);
4359 count_va += info->count_buffer->offset +
4360 info->count_buffer_offset;
4361
4362 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
4363 }
4364
4365 if (!state->subpass->view_mask) {
4366 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4367 info->indexed,
4368 info->count,
4369 count_va,
4370 info->stride);
4371 } else {
4372 unsigned i;
4373 for_each_bit(i, state->subpass->view_mask) {
4374 radv_emit_view_index(cmd_buffer, i);
4375
4376 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4377 info->indexed,
4378 info->count,
4379 count_va,
4380 info->stride);
4381 }
4382 }
4383 } else {
4384 assert(state->pipeline->graphics.vtx_base_sgpr);
4385
4386 if (info->vertex_offset != state->last_vertex_offset ||
4387 info->first_instance != state->last_first_instance) {
4388 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
4389 state->pipeline->graphics.vtx_emit_num);
4390
4391 radeon_emit(cs, info->vertex_offset);
4392 radeon_emit(cs, info->first_instance);
4393 if (state->pipeline->graphics.vtx_emit_num == 3)
4394 radeon_emit(cs, 0);
4395 state->last_first_instance = info->first_instance;
4396 state->last_vertex_offset = info->vertex_offset;
4397 }
4398
4399 if (state->last_num_instances != info->instance_count) {
4400 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
4401 radeon_emit(cs, info->instance_count);
4402 state->last_num_instances = info->instance_count;
4403 }
4404
4405 if (info->indexed) {
4406 int index_size = radv_get_vgt_index_size(state->index_type);
4407 uint64_t index_va;
4408
4409 /* Skip draw calls with 0-sized index buffers. They
4410 * cause a hang on some chips, like Navi10-14.
4411 */
4412 if (!cmd_buffer->state.max_index_count)
4413 return;
4414
4415 index_va = state->index_va;
4416 index_va += info->first_index * index_size;
4417
4418 if (!state->subpass->view_mask) {
4419 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4420 index_va,
4421 info->count);
4422 } else {
4423 unsigned i;
4424 for_each_bit(i, state->subpass->view_mask) {
4425 radv_emit_view_index(cmd_buffer, i);
4426
4427 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4428 index_va,
4429 info->count);
4430 }
4431 }
4432 } else {
4433 if (!state->subpass->view_mask) {
4434 radv_cs_emit_draw_packet(cmd_buffer,
4435 info->count,
4436 !!info->strmout_buffer);
4437 } else {
4438 unsigned i;
4439 for_each_bit(i, state->subpass->view_mask) {
4440 radv_emit_view_index(cmd_buffer, i);
4441
4442 radv_cs_emit_draw_packet(cmd_buffer,
4443 info->count,
4444 !!info->strmout_buffer);
4445 }
4446 }
4447 }
4448 }
4449 }
4450
4451 /*
4452 * Vega and raven have a bug which triggers if there are multiple context
4453 * register contexts active at the same time with different scissor values.
4454 *
4455 * There are two possible workarounds:
4456 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
4457 * there is only ever 1 active set of scissor values at the same time.
4458 *
4459 * 2) Whenever the hardware switches contexts we have to set the scissor
4460 * registers again even if it is a noop. That way the new context gets
4461 * the correct scissor values.
4462 *
4463 * This implements option 2. radv_need_late_scissor_emission needs to
4464 * return true on affected HW if radv_emit_all_graphics_states sets
4465 * any context registers.
4466 */
4467 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
4468 const struct radv_draw_info *info)
4469 {
4470 struct radv_cmd_state *state = &cmd_buffer->state;
4471
4472 if (!cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
4473 return false;
4474
4475 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
4476 return true;
4477
4478 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
4479
4480 /* Index, vertex and streamout buffers don't change context regs, and
4481 * pipeline is already handled.
4482 */
4483 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
4484 RADV_CMD_DIRTY_VERTEX_BUFFER |
4485 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
4486 RADV_CMD_DIRTY_PIPELINE);
4487
4488 if (cmd_buffer->state.dirty & used_states)
4489 return true;
4490
4491 uint32_t primitive_reset_index =
4492 radv_get_primitive_reset_index(cmd_buffer);
4493
4494 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
4495 primitive_reset_index != state->last_primitive_reset_index)
4496 return true;
4497
4498 return false;
4499 }
4500
4501 static void
4502 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
4503 const struct radv_draw_info *info)
4504 {
4505 bool late_scissor_emission;
4506
4507 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
4508 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
4509 radv_emit_rbplus_state(cmd_buffer);
4510
4511 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
4512 radv_emit_graphics_pipeline(cmd_buffer);
4513
4514 /* This should be before the cmd_buffer->state.dirty is cleared
4515 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4516 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4517 late_scissor_emission =
4518 radv_need_late_scissor_emission(cmd_buffer, info);
4519
4520 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
4521 radv_emit_framebuffer_state(cmd_buffer);
4522
4523 if (info->indexed) {
4524 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
4525 radv_emit_index_buffer(cmd_buffer);
4526 } else {
4527 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4528 * so the state must be re-emitted before the next indexed
4529 * draw.
4530 */
4531 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
4532 cmd_buffer->state.last_index_type = -1;
4533 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
4534 }
4535 }
4536
4537 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
4538
4539 radv_emit_draw_registers(cmd_buffer, info);
4540
4541 if (late_scissor_emission)
4542 radv_emit_scissor(cmd_buffer);
4543 }
4544
4545 static void
4546 radv_draw(struct radv_cmd_buffer *cmd_buffer,
4547 const struct radv_draw_info *info)
4548 {
4549 struct radeon_info *rad_info =
4550 &cmd_buffer->device->physical_device->rad_info;
4551 bool has_prefetch =
4552 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4553 bool pipeline_is_dirty =
4554 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
4555 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
4556
4557 ASSERTED unsigned cdw_max =
4558 radeon_check_space(cmd_buffer->device->ws,
4559 cmd_buffer->cs, 4096);
4560
4561 if (likely(!info->indirect)) {
4562 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4563 * no workaround for indirect draws, but we can at least skip
4564 * direct draws.
4565 */
4566 if (unlikely(!info->instance_count))
4567 return;
4568
4569 /* Handle count == 0. */
4570 if (unlikely(!info->count && !info->strmout_buffer))
4571 return;
4572 }
4573
4574 /* Use optimal packet order based on whether we need to sync the
4575 * pipeline.
4576 */
4577 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4578 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4579 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4580 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4581 /* If we have to wait for idle, set all states first, so that
4582 * all SET packets are processed in parallel with previous draw
4583 * calls. Then upload descriptors, set shader pointers, and
4584 * draw, and prefetch at the end. This ensures that the time
4585 * the CUs are idle is very short. (there are only SET_SH
4586 * packets between the wait and the draw)
4587 */
4588 radv_emit_all_graphics_states(cmd_buffer, info);
4589 si_emit_cache_flush(cmd_buffer);
4590 /* <-- CUs are idle here --> */
4591
4592 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4593
4594 radv_emit_draw_packets(cmd_buffer, info);
4595 /* <-- CUs are busy here --> */
4596
4597 /* Start prefetches after the draw has been started. Both will
4598 * run in parallel, but starting the draw first is more
4599 * important.
4600 */
4601 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4602 radv_emit_prefetch_L2(cmd_buffer,
4603 cmd_buffer->state.pipeline, false);
4604 }
4605 } else {
4606 /* If we don't wait for idle, start prefetches first, then set
4607 * states, and draw at the end.
4608 */
4609 si_emit_cache_flush(cmd_buffer);
4610
4611 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4612 /* Only prefetch the vertex shader and VBO descriptors
4613 * in order to start the draw as soon as possible.
4614 */
4615 radv_emit_prefetch_L2(cmd_buffer,
4616 cmd_buffer->state.pipeline, true);
4617 }
4618
4619 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4620
4621 radv_emit_all_graphics_states(cmd_buffer, info);
4622 radv_emit_draw_packets(cmd_buffer, info);
4623
4624 /* Prefetch the remaining shaders after the draw has been
4625 * started.
4626 */
4627 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4628 radv_emit_prefetch_L2(cmd_buffer,
4629 cmd_buffer->state.pipeline, false);
4630 }
4631 }
4632
4633 /* Workaround for a VGT hang when streamout is enabled.
4634 * It must be done after drawing.
4635 */
4636 if (cmd_buffer->state.streamout.streamout_enabled &&
4637 (rad_info->family == CHIP_HAWAII ||
4638 rad_info->family == CHIP_TONGA ||
4639 rad_info->family == CHIP_FIJI)) {
4640 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
4641 }
4642
4643 assert(cmd_buffer->cs->cdw <= cdw_max);
4644 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
4645 }
4646
4647 void radv_CmdDraw(
4648 VkCommandBuffer commandBuffer,
4649 uint32_t vertexCount,
4650 uint32_t instanceCount,
4651 uint32_t firstVertex,
4652 uint32_t firstInstance)
4653 {
4654 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4655 struct radv_draw_info info = {};
4656
4657 info.count = vertexCount;
4658 info.instance_count = instanceCount;
4659 info.first_instance = firstInstance;
4660 info.vertex_offset = firstVertex;
4661
4662 radv_draw(cmd_buffer, &info);
4663 }
4664
4665 void radv_CmdDrawIndexed(
4666 VkCommandBuffer commandBuffer,
4667 uint32_t indexCount,
4668 uint32_t instanceCount,
4669 uint32_t firstIndex,
4670 int32_t vertexOffset,
4671 uint32_t firstInstance)
4672 {
4673 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4674 struct radv_draw_info info = {};
4675
4676 info.indexed = true;
4677 info.count = indexCount;
4678 info.instance_count = instanceCount;
4679 info.first_index = firstIndex;
4680 info.vertex_offset = vertexOffset;
4681 info.first_instance = firstInstance;
4682
4683 radv_draw(cmd_buffer, &info);
4684 }
4685
4686 void radv_CmdDrawIndirect(
4687 VkCommandBuffer commandBuffer,
4688 VkBuffer _buffer,
4689 VkDeviceSize offset,
4690 uint32_t drawCount,
4691 uint32_t stride)
4692 {
4693 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4694 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4695 struct radv_draw_info info = {};
4696
4697 info.count = drawCount;
4698 info.indirect = buffer;
4699 info.indirect_offset = offset;
4700 info.stride = stride;
4701
4702 radv_draw(cmd_buffer, &info);
4703 }
4704
4705 void radv_CmdDrawIndexedIndirect(
4706 VkCommandBuffer commandBuffer,
4707 VkBuffer _buffer,
4708 VkDeviceSize offset,
4709 uint32_t drawCount,
4710 uint32_t stride)
4711 {
4712 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4713 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4714 struct radv_draw_info info = {};
4715
4716 info.indexed = true;
4717 info.count = drawCount;
4718 info.indirect = buffer;
4719 info.indirect_offset = offset;
4720 info.stride = stride;
4721
4722 radv_draw(cmd_buffer, &info);
4723 }
4724
4725 void radv_CmdDrawIndirectCountKHR(
4726 VkCommandBuffer commandBuffer,
4727 VkBuffer _buffer,
4728 VkDeviceSize offset,
4729 VkBuffer _countBuffer,
4730 VkDeviceSize countBufferOffset,
4731 uint32_t maxDrawCount,
4732 uint32_t stride)
4733 {
4734 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4735 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4736 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4737 struct radv_draw_info info = {};
4738
4739 info.count = maxDrawCount;
4740 info.indirect = buffer;
4741 info.indirect_offset = offset;
4742 info.count_buffer = count_buffer;
4743 info.count_buffer_offset = countBufferOffset;
4744 info.stride = stride;
4745
4746 radv_draw(cmd_buffer, &info);
4747 }
4748
4749 void radv_CmdDrawIndexedIndirectCountKHR(
4750 VkCommandBuffer commandBuffer,
4751 VkBuffer _buffer,
4752 VkDeviceSize offset,
4753 VkBuffer _countBuffer,
4754 VkDeviceSize countBufferOffset,
4755 uint32_t maxDrawCount,
4756 uint32_t stride)
4757 {
4758 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4759 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4760 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4761 struct radv_draw_info info = {};
4762
4763 info.indexed = true;
4764 info.count = maxDrawCount;
4765 info.indirect = buffer;
4766 info.indirect_offset = offset;
4767 info.count_buffer = count_buffer;
4768 info.count_buffer_offset = countBufferOffset;
4769 info.stride = stride;
4770
4771 radv_draw(cmd_buffer, &info);
4772 }
4773
4774 struct radv_dispatch_info {
4775 /**
4776 * Determine the layout of the grid (in block units) to be used.
4777 */
4778 uint32_t blocks[3];
4779
4780 /**
4781 * A starting offset for the grid. If unaligned is set, the offset
4782 * must still be aligned.
4783 */
4784 uint32_t offsets[3];
4785 /**
4786 * Whether it's an unaligned compute dispatch.
4787 */
4788 bool unaligned;
4789
4790 /**
4791 * Indirect compute parameters resource.
4792 */
4793 struct radv_buffer *indirect;
4794 uint64_t indirect_offset;
4795 };
4796
4797 static void
4798 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
4799 const struct radv_dispatch_info *info)
4800 {
4801 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4802 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4803 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
4804 struct radeon_winsys *ws = cmd_buffer->device->ws;
4805 bool predicating = cmd_buffer->state.predicating;
4806 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4807 struct radv_userdata_info *loc;
4808
4809 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
4810 AC_UD_CS_GRID_SIZE);
4811
4812 ASSERTED unsigned cdw_max = radeon_check_space(ws, cs, 25);
4813
4814 if (info->indirect) {
4815 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4816
4817 va += info->indirect->offset + info->indirect_offset;
4818
4819 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4820
4821 if (loc->sgpr_idx != -1) {
4822 for (unsigned i = 0; i < 3; ++i) {
4823 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
4824 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
4825 COPY_DATA_DST_SEL(COPY_DATA_REG));
4826 radeon_emit(cs, (va + 4 * i));
4827 radeon_emit(cs, (va + 4 * i) >> 32);
4828 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
4829 + loc->sgpr_idx * 4) >> 2) + i);
4830 radeon_emit(cs, 0);
4831 }
4832 }
4833
4834 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
4835 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
4836 PKT3_SHADER_TYPE_S(1));
4837 radeon_emit(cs, va);
4838 radeon_emit(cs, va >> 32);
4839 radeon_emit(cs, dispatch_initiator);
4840 } else {
4841 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
4842 PKT3_SHADER_TYPE_S(1));
4843 radeon_emit(cs, 1);
4844 radeon_emit(cs, va);
4845 radeon_emit(cs, va >> 32);
4846
4847 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
4848 PKT3_SHADER_TYPE_S(1));
4849 radeon_emit(cs, 0);
4850 radeon_emit(cs, dispatch_initiator);
4851 }
4852 } else {
4853 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
4854 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
4855
4856 if (info->unaligned) {
4857 unsigned *cs_block_size = compute_shader->info.cs.block_size;
4858 unsigned remainder[3];
4859
4860 /* If aligned, these should be an entire block size,
4861 * not 0.
4862 */
4863 remainder[0] = blocks[0] + cs_block_size[0] -
4864 align_u32_npot(blocks[0], cs_block_size[0]);
4865 remainder[1] = blocks[1] + cs_block_size[1] -
4866 align_u32_npot(blocks[1], cs_block_size[1]);
4867 remainder[2] = blocks[2] + cs_block_size[2] -
4868 align_u32_npot(blocks[2], cs_block_size[2]);
4869
4870 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
4871 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
4872 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
4873
4874 for(unsigned i = 0; i < 3; ++i) {
4875 assert(offsets[i] % cs_block_size[i] == 0);
4876 offsets[i] /= cs_block_size[i];
4877 }
4878
4879 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4880 radeon_emit(cs,
4881 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
4882 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
4883 radeon_emit(cs,
4884 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
4885 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
4886 radeon_emit(cs,
4887 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
4888 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
4889
4890 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
4891 }
4892
4893 if (loc->sgpr_idx != -1) {
4894 assert(loc->num_sgprs == 3);
4895
4896 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
4897 loc->sgpr_idx * 4, 3);
4898 radeon_emit(cs, blocks[0]);
4899 radeon_emit(cs, blocks[1]);
4900 radeon_emit(cs, blocks[2]);
4901 }
4902
4903 if (offsets[0] || offsets[1] || offsets[2]) {
4904 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
4905 radeon_emit(cs, offsets[0]);
4906 radeon_emit(cs, offsets[1]);
4907 radeon_emit(cs, offsets[2]);
4908
4909 /* The blocks in the packet are not counts but end values. */
4910 for (unsigned i = 0; i < 3; ++i)
4911 blocks[i] += offsets[i];
4912 } else {
4913 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
4914 }
4915
4916 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
4917 PKT3_SHADER_TYPE_S(1));
4918 radeon_emit(cs, blocks[0]);
4919 radeon_emit(cs, blocks[1]);
4920 radeon_emit(cs, blocks[2]);
4921 radeon_emit(cs, dispatch_initiator);
4922 }
4923
4924 assert(cmd_buffer->cs->cdw <= cdw_max);
4925 }
4926
4927 static void
4928 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
4929 {
4930 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4931 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4932 }
4933
4934 static void
4935 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
4936 const struct radv_dispatch_info *info)
4937 {
4938 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4939 bool has_prefetch =
4940 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4941 bool pipeline_is_dirty = pipeline &&
4942 pipeline != cmd_buffer->state.emitted_compute_pipeline;
4943
4944 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4945 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4946 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4947 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4948 /* If we have to wait for idle, set all states first, so that
4949 * all SET packets are processed in parallel with previous draw
4950 * calls. Then upload descriptors, set shader pointers, and
4951 * dispatch, and prefetch at the end. This ensures that the
4952 * time the CUs are idle is very short. (there are only SET_SH
4953 * packets between the wait and the draw)
4954 */
4955 radv_emit_compute_pipeline(cmd_buffer);
4956 si_emit_cache_flush(cmd_buffer);
4957 /* <-- CUs are idle here --> */
4958
4959 radv_upload_compute_shader_descriptors(cmd_buffer);
4960
4961 radv_emit_dispatch_packets(cmd_buffer, info);
4962 /* <-- CUs are busy here --> */
4963
4964 /* Start prefetches after the dispatch has been started. Both
4965 * will run in parallel, but starting the dispatch first is
4966 * more important.
4967 */
4968 if (has_prefetch && pipeline_is_dirty) {
4969 radv_emit_shader_prefetch(cmd_buffer,
4970 pipeline->shaders[MESA_SHADER_COMPUTE]);
4971 }
4972 } else {
4973 /* If we don't wait for idle, start prefetches first, then set
4974 * states, and dispatch at the end.
4975 */
4976 si_emit_cache_flush(cmd_buffer);
4977
4978 if (has_prefetch && pipeline_is_dirty) {
4979 radv_emit_shader_prefetch(cmd_buffer,
4980 pipeline->shaders[MESA_SHADER_COMPUTE]);
4981 }
4982
4983 radv_upload_compute_shader_descriptors(cmd_buffer);
4984
4985 radv_emit_compute_pipeline(cmd_buffer);
4986 radv_emit_dispatch_packets(cmd_buffer, info);
4987 }
4988
4989 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
4990 }
4991
4992 void radv_CmdDispatchBase(
4993 VkCommandBuffer commandBuffer,
4994 uint32_t base_x,
4995 uint32_t base_y,
4996 uint32_t base_z,
4997 uint32_t x,
4998 uint32_t y,
4999 uint32_t z)
5000 {
5001 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5002 struct radv_dispatch_info info = {};
5003
5004 info.blocks[0] = x;
5005 info.blocks[1] = y;
5006 info.blocks[2] = z;
5007
5008 info.offsets[0] = base_x;
5009 info.offsets[1] = base_y;
5010 info.offsets[2] = base_z;
5011 radv_dispatch(cmd_buffer, &info);
5012 }
5013
5014 void radv_CmdDispatch(
5015 VkCommandBuffer commandBuffer,
5016 uint32_t x,
5017 uint32_t y,
5018 uint32_t z)
5019 {
5020 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
5021 }
5022
5023 void radv_CmdDispatchIndirect(
5024 VkCommandBuffer commandBuffer,
5025 VkBuffer _buffer,
5026 VkDeviceSize offset)
5027 {
5028 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5029 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5030 struct radv_dispatch_info info = {};
5031
5032 info.indirect = buffer;
5033 info.indirect_offset = offset;
5034
5035 radv_dispatch(cmd_buffer, &info);
5036 }
5037
5038 void radv_unaligned_dispatch(
5039 struct radv_cmd_buffer *cmd_buffer,
5040 uint32_t x,
5041 uint32_t y,
5042 uint32_t z)
5043 {
5044 struct radv_dispatch_info info = {};
5045
5046 info.blocks[0] = x;
5047 info.blocks[1] = y;
5048 info.blocks[2] = z;
5049 info.unaligned = 1;
5050
5051 radv_dispatch(cmd_buffer, &info);
5052 }
5053
5054 void radv_CmdEndRenderPass(
5055 VkCommandBuffer commandBuffer)
5056 {
5057 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5058
5059 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
5060
5061 radv_cmd_buffer_end_subpass(cmd_buffer);
5062
5063 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
5064 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
5065
5066 cmd_buffer->state.pass = NULL;
5067 cmd_buffer->state.subpass = NULL;
5068 cmd_buffer->state.attachments = NULL;
5069 cmd_buffer->state.framebuffer = NULL;
5070 cmd_buffer->state.subpass_sample_locs = NULL;
5071 }
5072
5073 void radv_CmdEndRenderPass2KHR(
5074 VkCommandBuffer commandBuffer,
5075 const VkSubpassEndInfoKHR* pSubpassEndInfo)
5076 {
5077 radv_CmdEndRenderPass(commandBuffer);
5078 }
5079
5080 /*
5081 * For HTILE we have the following interesting clear words:
5082 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
5083 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
5084 * 0xfffffff0: Clear depth to 1.0
5085 * 0x00000000: Clear depth to 0.0
5086 */
5087 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
5088 struct radv_image *image,
5089 const VkImageSubresourceRange *range,
5090 uint32_t clear_word)
5091 {
5092 assert(range->baseMipLevel == 0);
5093 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
5094 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
5095 struct radv_cmd_state *state = &cmd_buffer->state;
5096 VkClearDepthStencilValue value = {};
5097
5098 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5099 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5100
5101 state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, clear_word);
5102
5103 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5104
5105 if (vk_format_is_stencil(image->vk_format))
5106 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
5107
5108 radv_set_ds_clear_metadata(cmd_buffer, image, range, value, aspects);
5109
5110 if (radv_image_is_tc_compat_htile(image)) {
5111 /* Initialize the TC-compat metada value to 0 because by
5112 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
5113 * need have to conditionally update its value when performing
5114 * a fast depth clear.
5115 */
5116 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, range, 0);
5117 }
5118 }
5119
5120 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
5121 struct radv_image *image,
5122 VkImageLayout src_layout,
5123 bool src_render_loop,
5124 VkImageLayout dst_layout,
5125 bool dst_render_loop,
5126 unsigned src_queue_mask,
5127 unsigned dst_queue_mask,
5128 const VkImageSubresourceRange *range,
5129 struct radv_sample_locations_state *sample_locs)
5130 {
5131 if (!radv_image_has_htile(image))
5132 return;
5133
5134 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5135 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
5136
5137 if (radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop,
5138 dst_queue_mask)) {
5139 clear_value = 0;
5140 }
5141
5142 radv_initialize_htile(cmd_buffer, image, range, clear_value);
5143 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5144 radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5145 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
5146 radv_initialize_htile(cmd_buffer, image, range, clear_value);
5147 } else if (radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5148 !radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5149 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5150 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5151
5152 radv_decompress_depth_image_inplace(cmd_buffer, image, range,
5153 sample_locs);
5154
5155 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5156 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5157 }
5158 }
5159
5160 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
5161 struct radv_image *image,
5162 const VkImageSubresourceRange *range,
5163 uint32_t value)
5164 {
5165 struct radv_cmd_state *state = &cmd_buffer->state;
5166
5167 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5168 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5169
5170 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, range, value);
5171
5172 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5173 }
5174
5175 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
5176 struct radv_image *image,
5177 const VkImageSubresourceRange *range)
5178 {
5179 struct radv_cmd_state *state = &cmd_buffer->state;
5180 static const uint32_t fmask_clear_values[4] = {
5181 0x00000000,
5182 0x02020202,
5183 0xE4E4E4E4,
5184 0x76543210
5185 };
5186 uint32_t log2_samples = util_logbase2(image->info.samples);
5187 uint32_t value = fmask_clear_values[log2_samples];
5188
5189 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5190 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5191
5192 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, range, value);
5193
5194 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5195 }
5196
5197 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
5198 struct radv_image *image,
5199 const VkImageSubresourceRange *range, uint32_t value)
5200 {
5201 struct radv_cmd_state *state = &cmd_buffer->state;
5202 unsigned size = 0;
5203
5204 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5205 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5206
5207 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
5208
5209 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) {
5210 /* When DCC is enabled with mipmaps, some levels might not
5211 * support fast clears and we have to initialize them as "fully
5212 * expanded".
5213 */
5214 /* Compute the size of all fast clearable DCC levels. */
5215 for (unsigned i = 0; i < image->planes[0].surface.num_dcc_levels; i++) {
5216 struct legacy_surf_level *surf_level =
5217 &image->planes[0].surface.u.legacy.level[i];
5218 unsigned dcc_fast_clear_size =
5219 surf_level->dcc_slice_fast_clear_size * image->info.array_size;
5220
5221 if (!dcc_fast_clear_size)
5222 break;
5223
5224 size = surf_level->dcc_offset + dcc_fast_clear_size;
5225 }
5226
5227 /* Initialize the mipmap levels without DCC. */
5228 if (size != image->planes[0].surface.dcc_size) {
5229 state->flush_bits |=
5230 radv_fill_buffer(cmd_buffer, image->bo,
5231 image->offset + image->dcc_offset + size,
5232 image->planes[0].surface.dcc_size - size,
5233 0xffffffff);
5234 }
5235 }
5236
5237 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5238 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5239 }
5240
5241 /**
5242 * Initialize DCC/FMASK/CMASK metadata for a color image.
5243 */
5244 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
5245 struct radv_image *image,
5246 VkImageLayout src_layout,
5247 bool src_render_loop,
5248 VkImageLayout dst_layout,
5249 bool dst_render_loop,
5250 unsigned src_queue_mask,
5251 unsigned dst_queue_mask,
5252 const VkImageSubresourceRange *range)
5253 {
5254 if (radv_image_has_cmask(image)) {
5255 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5256
5257 /* TODO: clarify this. */
5258 if (radv_image_has_fmask(image)) {
5259 value = 0xccccccccu;
5260 }
5261
5262 radv_initialise_cmask(cmd_buffer, image, range, value);
5263 }
5264
5265 if (radv_image_has_fmask(image)) {
5266 radv_initialize_fmask(cmd_buffer, image, range);
5267 }
5268
5269 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5270 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5271 bool need_decompress_pass = false;
5272
5273 if (radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout,
5274 dst_render_loop,
5275 dst_queue_mask)) {
5276 value = 0x20202020u;
5277 need_decompress_pass = true;
5278 }
5279
5280 radv_initialize_dcc(cmd_buffer, image, range, value);
5281
5282 radv_update_fce_metadata(cmd_buffer, image, range,
5283 need_decompress_pass);
5284 }
5285
5286 if (radv_image_has_cmask(image) ||
5287 radv_dcc_enabled(image, range->baseMipLevel)) {
5288 uint32_t color_values[2] = {};
5289 radv_set_color_clear_metadata(cmd_buffer, image, range,
5290 color_values);
5291 }
5292 }
5293
5294 /**
5295 * Handle color image transitions for DCC/FMASK/CMASK.
5296 */
5297 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
5298 struct radv_image *image,
5299 VkImageLayout src_layout,
5300 bool src_render_loop,
5301 VkImageLayout dst_layout,
5302 bool dst_render_loop,
5303 unsigned src_queue_mask,
5304 unsigned dst_queue_mask,
5305 const VkImageSubresourceRange *range)
5306 {
5307 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5308 radv_init_color_image_metadata(cmd_buffer, image,
5309 src_layout, src_render_loop,
5310 dst_layout, dst_render_loop,
5311 src_queue_mask, dst_queue_mask,
5312 range);
5313 return;
5314 }
5315
5316 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5317 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
5318 radv_initialize_dcc(cmd_buffer, image, range, 0xffffffffu);
5319 } else if (radv_layout_dcc_compressed(cmd_buffer->device, image, src_layout, src_render_loop, src_queue_mask) &&
5320 !radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout, dst_render_loop, dst_queue_mask)) {
5321 radv_decompress_dcc(cmd_buffer, image, range);
5322 } else if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
5323 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5324 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5325 }
5326 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
5327 bool fce_eliminate = false, fmask_expand = false;
5328
5329 if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
5330 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5331 fce_eliminate = true;
5332 }
5333
5334 if (radv_image_has_fmask(image)) {
5335 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
5336 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
5337 /* A FMASK decompress is required before doing
5338 * a MSAA decompress using FMASK.
5339 */
5340 fmask_expand = true;
5341 }
5342 }
5343
5344 if (fce_eliminate || fmask_expand)
5345 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5346
5347 if (fmask_expand)
5348 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
5349 }
5350 }
5351
5352 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
5353 struct radv_image *image,
5354 VkImageLayout src_layout,
5355 bool src_render_loop,
5356 VkImageLayout dst_layout,
5357 bool dst_render_loop,
5358 uint32_t src_family,
5359 uint32_t dst_family,
5360 const VkImageSubresourceRange *range,
5361 struct radv_sample_locations_state *sample_locs)
5362 {
5363 if (image->exclusive && src_family != dst_family) {
5364 /* This is an acquire or a release operation and there will be
5365 * a corresponding release/acquire. Do the transition in the
5366 * most flexible queue. */
5367
5368 assert(src_family == cmd_buffer->queue_family_index ||
5369 dst_family == cmd_buffer->queue_family_index);
5370
5371 if (src_family == VK_QUEUE_FAMILY_EXTERNAL ||
5372 src_family == VK_QUEUE_FAMILY_FOREIGN_EXT)
5373 return;
5374
5375 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
5376 return;
5377
5378 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
5379 (src_family == RADV_QUEUE_GENERAL ||
5380 dst_family == RADV_QUEUE_GENERAL))
5381 return;
5382 }
5383
5384 if (src_layout == dst_layout)
5385 return;
5386
5387 unsigned src_queue_mask =
5388 radv_image_queue_family_mask(image, src_family,
5389 cmd_buffer->queue_family_index);
5390 unsigned dst_queue_mask =
5391 radv_image_queue_family_mask(image, dst_family,
5392 cmd_buffer->queue_family_index);
5393
5394 if (vk_format_is_depth(image->vk_format)) {
5395 radv_handle_depth_image_transition(cmd_buffer, image,
5396 src_layout, src_render_loop,
5397 dst_layout, dst_render_loop,
5398 src_queue_mask, dst_queue_mask,
5399 range, sample_locs);
5400 } else {
5401 radv_handle_color_image_transition(cmd_buffer, image,
5402 src_layout, src_render_loop,
5403 dst_layout, dst_render_loop,
5404 src_queue_mask, dst_queue_mask,
5405 range);
5406 }
5407 }
5408
5409 struct radv_barrier_info {
5410 uint32_t eventCount;
5411 const VkEvent *pEvents;
5412 VkPipelineStageFlags srcStageMask;
5413 VkPipelineStageFlags dstStageMask;
5414 };
5415
5416 static void
5417 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
5418 uint32_t memoryBarrierCount,
5419 const VkMemoryBarrier *pMemoryBarriers,
5420 uint32_t bufferMemoryBarrierCount,
5421 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
5422 uint32_t imageMemoryBarrierCount,
5423 const VkImageMemoryBarrier *pImageMemoryBarriers,
5424 const struct radv_barrier_info *info)
5425 {
5426 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5427 enum radv_cmd_flush_bits src_flush_bits = 0;
5428 enum radv_cmd_flush_bits dst_flush_bits = 0;
5429
5430 for (unsigned i = 0; i < info->eventCount; ++i) {
5431 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
5432 uint64_t va = radv_buffer_get_va(event->bo);
5433
5434 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5435
5436 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
5437
5438 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
5439 assert(cmd_buffer->cs->cdw <= cdw_max);
5440 }
5441
5442 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
5443 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
5444 NULL);
5445 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
5446 NULL);
5447 }
5448
5449 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
5450 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
5451 NULL);
5452 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
5453 NULL);
5454 }
5455
5456 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5457 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5458
5459 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
5460 image);
5461 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
5462 image);
5463 }
5464
5465 /* The Vulkan spec 1.1.98 says:
5466 *
5467 * "An execution dependency with only
5468 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
5469 * will only prevent that stage from executing in subsequently
5470 * submitted commands. As this stage does not perform any actual
5471 * execution, this is not observable - in effect, it does not delay
5472 * processing of subsequent commands. Similarly an execution dependency
5473 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
5474 * will effectively not wait for any prior commands to complete."
5475 */
5476 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
5477 radv_stage_flush(cmd_buffer, info->srcStageMask);
5478 cmd_buffer->state.flush_bits |= src_flush_bits;
5479
5480 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5481 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5482
5483 const struct VkSampleLocationsInfoEXT *sample_locs_info =
5484 vk_find_struct_const(pImageMemoryBarriers[i].pNext,
5485 SAMPLE_LOCATIONS_INFO_EXT);
5486 struct radv_sample_locations_state sample_locations = {};
5487
5488 if (sample_locs_info) {
5489 assert(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
5490 sample_locations.per_pixel = sample_locs_info->sampleLocationsPerPixel;
5491 sample_locations.grid_size = sample_locs_info->sampleLocationGridSize;
5492 sample_locations.count = sample_locs_info->sampleLocationsCount;
5493 typed_memcpy(&sample_locations.locations[0],
5494 sample_locs_info->pSampleLocations,
5495 sample_locs_info->sampleLocationsCount);
5496 }
5497
5498 radv_handle_image_transition(cmd_buffer, image,
5499 pImageMemoryBarriers[i].oldLayout,
5500 false, /* Outside of a renderpass we are never in a renderloop */
5501 pImageMemoryBarriers[i].newLayout,
5502 false, /* Outside of a renderpass we are never in a renderloop */
5503 pImageMemoryBarriers[i].srcQueueFamilyIndex,
5504 pImageMemoryBarriers[i].dstQueueFamilyIndex,
5505 &pImageMemoryBarriers[i].subresourceRange,
5506 sample_locs_info ? &sample_locations : NULL);
5507 }
5508
5509 /* Make sure CP DMA is idle because the driver might have performed a
5510 * DMA operation for copying or filling buffers/images.
5511 */
5512 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5513 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5514 si_cp_dma_wait_for_idle(cmd_buffer);
5515
5516 cmd_buffer->state.flush_bits |= dst_flush_bits;
5517 }
5518
5519 void radv_CmdPipelineBarrier(
5520 VkCommandBuffer commandBuffer,
5521 VkPipelineStageFlags srcStageMask,
5522 VkPipelineStageFlags destStageMask,
5523 VkBool32 byRegion,
5524 uint32_t memoryBarrierCount,
5525 const VkMemoryBarrier* pMemoryBarriers,
5526 uint32_t bufferMemoryBarrierCount,
5527 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5528 uint32_t imageMemoryBarrierCount,
5529 const VkImageMemoryBarrier* pImageMemoryBarriers)
5530 {
5531 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5532 struct radv_barrier_info info;
5533
5534 info.eventCount = 0;
5535 info.pEvents = NULL;
5536 info.srcStageMask = srcStageMask;
5537 info.dstStageMask = destStageMask;
5538
5539 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5540 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5541 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5542 }
5543
5544
5545 static void write_event(struct radv_cmd_buffer *cmd_buffer,
5546 struct radv_event *event,
5547 VkPipelineStageFlags stageMask,
5548 unsigned value)
5549 {
5550 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5551 uint64_t va = radv_buffer_get_va(event->bo);
5552
5553 si_emit_cache_flush(cmd_buffer);
5554
5555 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5556
5557 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 21);
5558
5559 /* Flags that only require a top-of-pipe event. */
5560 VkPipelineStageFlags top_of_pipe_flags =
5561 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
5562
5563 /* Flags that only require a post-index-fetch event. */
5564 VkPipelineStageFlags post_index_fetch_flags =
5565 top_of_pipe_flags |
5566 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
5567 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
5568
5569 /* Make sure CP DMA is idle because the driver might have performed a
5570 * DMA operation for copying or filling buffers/images.
5571 */
5572 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5573 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5574 si_cp_dma_wait_for_idle(cmd_buffer);
5575
5576 /* TODO: Emit EOS events for syncing PS/CS stages. */
5577
5578 if (!(stageMask & ~top_of_pipe_flags)) {
5579 /* Just need to sync the PFP engine. */
5580 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5581 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5582 S_370_WR_CONFIRM(1) |
5583 S_370_ENGINE_SEL(V_370_PFP));
5584 radeon_emit(cs, va);
5585 radeon_emit(cs, va >> 32);
5586 radeon_emit(cs, value);
5587 } else if (!(stageMask & ~post_index_fetch_flags)) {
5588 /* Sync ME because PFP reads index and indirect buffers. */
5589 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5590 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5591 S_370_WR_CONFIRM(1) |
5592 S_370_ENGINE_SEL(V_370_ME));
5593 radeon_emit(cs, va);
5594 radeon_emit(cs, va >> 32);
5595 radeon_emit(cs, value);
5596 } else {
5597 /* Otherwise, sync all prior GPU work using an EOP event. */
5598 si_cs_emit_write_event_eop(cs,
5599 cmd_buffer->device->physical_device->rad_info.chip_class,
5600 radv_cmd_buffer_uses_mec(cmd_buffer),
5601 V_028A90_BOTTOM_OF_PIPE_TS, 0,
5602 EOP_DST_SEL_MEM,
5603 EOP_DATA_SEL_VALUE_32BIT, va, value,
5604 cmd_buffer->gfx9_eop_bug_va);
5605 }
5606
5607 assert(cmd_buffer->cs->cdw <= cdw_max);
5608 }
5609
5610 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
5611 VkEvent _event,
5612 VkPipelineStageFlags stageMask)
5613 {
5614 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5615 RADV_FROM_HANDLE(radv_event, event, _event);
5616
5617 write_event(cmd_buffer, event, stageMask, 1);
5618 }
5619
5620 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
5621 VkEvent _event,
5622 VkPipelineStageFlags stageMask)
5623 {
5624 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5625 RADV_FROM_HANDLE(radv_event, event, _event);
5626
5627 write_event(cmd_buffer, event, stageMask, 0);
5628 }
5629
5630 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
5631 uint32_t eventCount,
5632 const VkEvent* pEvents,
5633 VkPipelineStageFlags srcStageMask,
5634 VkPipelineStageFlags dstStageMask,
5635 uint32_t memoryBarrierCount,
5636 const VkMemoryBarrier* pMemoryBarriers,
5637 uint32_t bufferMemoryBarrierCount,
5638 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5639 uint32_t imageMemoryBarrierCount,
5640 const VkImageMemoryBarrier* pImageMemoryBarriers)
5641 {
5642 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5643 struct radv_barrier_info info;
5644
5645 info.eventCount = eventCount;
5646 info.pEvents = pEvents;
5647 info.srcStageMask = 0;
5648
5649 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5650 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5651 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5652 }
5653
5654
5655 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
5656 uint32_t deviceMask)
5657 {
5658 /* No-op */
5659 }
5660
5661 /* VK_EXT_conditional_rendering */
5662 void radv_CmdBeginConditionalRenderingEXT(
5663 VkCommandBuffer commandBuffer,
5664 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
5665 {
5666 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5667 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
5668 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5669 bool draw_visible = true;
5670 uint64_t pred_value = 0;
5671 uint64_t va, new_va;
5672 unsigned pred_offset;
5673
5674 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
5675
5676 /* By default, if the 32-bit value at offset in buffer memory is zero,
5677 * then the rendering commands are discarded, otherwise they are
5678 * executed as normal. If the inverted flag is set, all commands are
5679 * discarded if the value is non zero.
5680 */
5681 if (pConditionalRenderingBegin->flags &
5682 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
5683 draw_visible = false;
5684 }
5685
5686 si_emit_cache_flush(cmd_buffer);
5687
5688 /* From the Vulkan spec 1.1.107:
5689 *
5690 * "If the 32-bit value at offset in buffer memory is zero, then the
5691 * rendering commands are discarded, otherwise they are executed as
5692 * normal. If the value of the predicate in buffer memory changes while
5693 * conditional rendering is active, the rendering commands may be
5694 * discarded in an implementation-dependent way. Some implementations
5695 * may latch the value of the predicate upon beginning conditional
5696 * rendering while others may read it before every rendering command."
5697 *
5698 * But, the AMD hardware treats the predicate as a 64-bit value which
5699 * means we need a workaround in the driver. Luckily, it's not required
5700 * to support if the value changes when predication is active.
5701 *
5702 * The workaround is as follows:
5703 * 1) allocate a 64-value in the upload BO and initialize it to 0
5704 * 2) copy the 32-bit predicate value to the upload BO
5705 * 3) use the new allocated VA address for predication
5706 *
5707 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
5708 * in ME (+ sync PFP) instead of PFP.
5709 */
5710 radv_cmd_buffer_upload_data(cmd_buffer, 8, 16, &pred_value, &pred_offset);
5711
5712 new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
5713
5714 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5715 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5716 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
5717 COPY_DATA_WR_CONFIRM);
5718 radeon_emit(cs, va);
5719 radeon_emit(cs, va >> 32);
5720 radeon_emit(cs, new_va);
5721 radeon_emit(cs, new_va >> 32);
5722
5723 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
5724 radeon_emit(cs, 0);
5725
5726 /* Enable predication for this command buffer. */
5727 si_emit_set_predication_state(cmd_buffer, draw_visible, new_va);
5728 cmd_buffer->state.predicating = true;
5729
5730 /* Store conditional rendering user info. */
5731 cmd_buffer->state.predication_type = draw_visible;
5732 cmd_buffer->state.predication_va = new_va;
5733 }
5734
5735 void radv_CmdEndConditionalRenderingEXT(
5736 VkCommandBuffer commandBuffer)
5737 {
5738 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5739
5740 /* Disable predication for this command buffer. */
5741 si_emit_set_predication_state(cmd_buffer, false, 0);
5742 cmd_buffer->state.predicating = false;
5743
5744 /* Reset conditional rendering user info. */
5745 cmd_buffer->state.predication_type = -1;
5746 cmd_buffer->state.predication_va = 0;
5747 }
5748
5749 /* VK_EXT_transform_feedback */
5750 void radv_CmdBindTransformFeedbackBuffersEXT(
5751 VkCommandBuffer commandBuffer,
5752 uint32_t firstBinding,
5753 uint32_t bindingCount,
5754 const VkBuffer* pBuffers,
5755 const VkDeviceSize* pOffsets,
5756 const VkDeviceSize* pSizes)
5757 {
5758 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5759 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5760 uint8_t enabled_mask = 0;
5761
5762 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
5763 for (uint32_t i = 0; i < bindingCount; i++) {
5764 uint32_t idx = firstBinding + i;
5765
5766 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
5767 sb[idx].offset = pOffsets[i];
5768 sb[idx].size = pSizes[i];
5769
5770 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
5771 sb[idx].buffer->bo);
5772
5773 enabled_mask |= 1 << idx;
5774 }
5775
5776 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
5777
5778 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
5779 }
5780
5781 static void
5782 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
5783 {
5784 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5785 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5786
5787 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
5788 radeon_emit(cs,
5789 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
5790 S_028B94_RAST_STREAM(0) |
5791 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
5792 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
5793 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
5794 radeon_emit(cs, so->hw_enabled_mask &
5795 so->enabled_stream_buffers_mask);
5796
5797 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5798 }
5799
5800 static void
5801 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
5802 {
5803 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5804 bool old_streamout_enabled = so->streamout_enabled;
5805 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
5806
5807 so->streamout_enabled = enable;
5808
5809 so->hw_enabled_mask = so->enabled_mask |
5810 (so->enabled_mask << 4) |
5811 (so->enabled_mask << 8) |
5812 (so->enabled_mask << 12);
5813
5814 if (!cmd_buffer->device->physical_device->use_ngg_streamout &&
5815 ((old_streamout_enabled != so->streamout_enabled) ||
5816 (old_hw_enabled_mask != so->hw_enabled_mask)))
5817 radv_emit_streamout_enable(cmd_buffer);
5818 }
5819
5820 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
5821 {
5822 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5823 unsigned reg_strmout_cntl;
5824
5825 /* The register is at different places on different ASICs. */
5826 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
5827 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
5828 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
5829 } else {
5830 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
5831 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
5832 }
5833
5834 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
5835 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
5836
5837 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
5838 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
5839 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
5840 radeon_emit(cs, 0);
5841 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
5842 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
5843 radeon_emit(cs, 4); /* poll interval */
5844 }
5845
5846 static void
5847 radv_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
5848 uint32_t firstCounterBuffer,
5849 uint32_t counterBufferCount,
5850 const VkBuffer *pCounterBuffers,
5851 const VkDeviceSize *pCounterBufferOffsets)
5852
5853 {
5854 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5855 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5856 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5857 uint32_t i;
5858
5859 radv_flush_vgt_streamout(cmd_buffer);
5860
5861 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5862 for_each_bit(i, so->enabled_mask) {
5863 int32_t counter_buffer_idx = i - firstCounterBuffer;
5864 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5865 counter_buffer_idx = -1;
5866
5867 /* AMD GCN binds streamout buffers as shader resources.
5868 * VGT only counts primitives and tells the shader through
5869 * SGPRs what to do.
5870 */
5871 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
5872 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
5873 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
5874
5875 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5876
5877 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5878 /* The array of counter buffers is optional. */
5879 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5880 uint64_t va = radv_buffer_get_va(buffer->bo);
5881
5882 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5883
5884 /* Append */
5885 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5886 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5887 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5888 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
5889 radeon_emit(cs, 0); /* unused */
5890 radeon_emit(cs, 0); /* unused */
5891 radeon_emit(cs, va); /* src address lo */
5892 radeon_emit(cs, va >> 32); /* src address hi */
5893
5894 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5895 } else {
5896 /* Start from the beginning. */
5897 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5898 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5899 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5900 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
5901 radeon_emit(cs, 0); /* unused */
5902 radeon_emit(cs, 0); /* unused */
5903 radeon_emit(cs, 0); /* unused */
5904 radeon_emit(cs, 0); /* unused */
5905 }
5906 }
5907
5908 radv_set_streamout_enable(cmd_buffer, true);
5909 }
5910
5911 void radv_CmdBeginTransformFeedbackEXT(
5912 VkCommandBuffer commandBuffer,
5913 uint32_t firstCounterBuffer,
5914 uint32_t counterBufferCount,
5915 const VkBuffer* pCounterBuffers,
5916 const VkDeviceSize* pCounterBufferOffsets)
5917 {
5918 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5919
5920 radv_emit_streamout_begin(cmd_buffer,
5921 firstCounterBuffer, counterBufferCount,
5922 pCounterBuffers, pCounterBufferOffsets);
5923 }
5924
5925 static void
5926 radv_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
5927 uint32_t firstCounterBuffer,
5928 uint32_t counterBufferCount,
5929 const VkBuffer *pCounterBuffers,
5930 const VkDeviceSize *pCounterBufferOffsets)
5931 {
5932 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5933 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5934 uint32_t i;
5935
5936 radv_flush_vgt_streamout(cmd_buffer);
5937
5938 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5939 for_each_bit(i, so->enabled_mask) {
5940 int32_t counter_buffer_idx = i - firstCounterBuffer;
5941 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5942 counter_buffer_idx = -1;
5943
5944 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5945 /* The array of counters buffer is optional. */
5946 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5947 uint64_t va = radv_buffer_get_va(buffer->bo);
5948
5949 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5950
5951 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5952 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5953 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5954 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
5955 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
5956 radeon_emit(cs, va); /* dst address lo */
5957 radeon_emit(cs, va >> 32); /* dst address hi */
5958 radeon_emit(cs, 0); /* unused */
5959 radeon_emit(cs, 0); /* unused */
5960
5961 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5962 }
5963
5964 /* Deactivate transform feedback by zeroing the buffer size.
5965 * The counters (primitives generated, primitives emitted) may
5966 * be enabled even if there is not buffer bound. This ensures
5967 * that the primitives-emitted query won't increment.
5968 */
5969 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
5970
5971 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5972 }
5973
5974 radv_set_streamout_enable(cmd_buffer, false);
5975 }
5976
5977 void radv_CmdEndTransformFeedbackEXT(
5978 VkCommandBuffer commandBuffer,
5979 uint32_t firstCounterBuffer,
5980 uint32_t counterBufferCount,
5981 const VkBuffer* pCounterBuffers,
5982 const VkDeviceSize* pCounterBufferOffsets)
5983 {
5984 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5985
5986 radv_emit_streamout_end(cmd_buffer,
5987 firstCounterBuffer, counterBufferCount,
5988 pCounterBuffers, pCounterBufferOffsets);
5989 }
5990
5991 void radv_CmdDrawIndirectByteCountEXT(
5992 VkCommandBuffer commandBuffer,
5993 uint32_t instanceCount,
5994 uint32_t firstInstance,
5995 VkBuffer _counterBuffer,
5996 VkDeviceSize counterBufferOffset,
5997 uint32_t counterOffset,
5998 uint32_t vertexStride)
5999 {
6000 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6001 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
6002 struct radv_draw_info info = {};
6003
6004 info.instance_count = instanceCount;
6005 info.first_instance = firstInstance;
6006 info.strmout_buffer = counterBuffer;
6007 info.strmout_buffer_offset = counterBufferOffset;
6008 info.stride = vertexStride;
6009
6010 radv_draw(cmd_buffer, &info);
6011 }
6012
6013 /* VK_AMD_buffer_marker */
6014 void radv_CmdWriteBufferMarkerAMD(
6015 VkCommandBuffer commandBuffer,
6016 VkPipelineStageFlagBits pipelineStage,
6017 VkBuffer dstBuffer,
6018 VkDeviceSize dstOffset,
6019 uint32_t marker)
6020 {
6021 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6022 RADV_FROM_HANDLE(radv_buffer, buffer, dstBuffer);
6023 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6024 uint64_t va = radv_buffer_get_va(buffer->bo) + dstOffset;
6025
6026 si_emit_cache_flush(cmd_buffer);
6027
6028 if (!(pipelineStage & ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT)) {
6029 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
6030 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
6031 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
6032 COPY_DATA_WR_CONFIRM);
6033 radeon_emit(cs, marker);
6034 radeon_emit(cs, 0);
6035 radeon_emit(cs, va);
6036 radeon_emit(cs, va >> 32);
6037 } else {
6038 si_cs_emit_write_event_eop(cs,
6039 cmd_buffer->device->physical_device->rad_info.chip_class,
6040 radv_cmd_buffer_uses_mec(cmd_buffer),
6041 V_028A90_BOTTOM_OF_PIPE_TS, 0,
6042 EOP_DST_SEL_MEM,
6043 EOP_DATA_SEL_VALUE_32BIT,
6044 va, marker,
6045 cmd_buffer->gfx9_eop_bug_va);
6046 }
6047 }