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radv: Consider maximum sample distances for entire grid.
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 bool src_render_loop,
58 VkImageLayout dst_layout,
59 bool dst_render_loop,
60 uint32_t src_family,
61 uint32_t dst_family,
62 const VkImageSubresourceRange *range,
63 struct radv_sample_locations_state *sample_locs);
64
65 const struct radv_dynamic_state default_dynamic_state = {
66 .viewport = {
67 .count = 0,
68 },
69 .scissor = {
70 .count = 0,
71 },
72 .line_width = 1.0f,
73 .depth_bias = {
74 .bias = 0.0f,
75 .clamp = 0.0f,
76 .slope = 0.0f,
77 },
78 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
79 .depth_bounds = {
80 .min = 0.0f,
81 .max = 1.0f,
82 },
83 .stencil_compare_mask = {
84 .front = ~0u,
85 .back = ~0u,
86 },
87 .stencil_write_mask = {
88 .front = ~0u,
89 .back = ~0u,
90 },
91 .stencil_reference = {
92 .front = 0u,
93 .back = 0u,
94 },
95 .line_stipple = {
96 .factor = 0u,
97 .pattern = 0u,
98 },
99 };
100
101 static void
102 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
103 const struct radv_dynamic_state *src)
104 {
105 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
106 uint32_t copy_mask = src->mask;
107 uint32_t dest_mask = 0;
108
109 /* Make sure to copy the number of viewports/scissors because they can
110 * only be specified at pipeline creation time.
111 */
112 dest->viewport.count = src->viewport.count;
113 dest->scissor.count = src->scissor.count;
114 dest->discard_rectangle.count = src->discard_rectangle.count;
115 dest->sample_location.count = src->sample_location.count;
116
117 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
118 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
119 src->viewport.count * sizeof(VkViewport))) {
120 typed_memcpy(dest->viewport.viewports,
121 src->viewport.viewports,
122 src->viewport.count);
123 dest_mask |= RADV_DYNAMIC_VIEWPORT;
124 }
125 }
126
127 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
128 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
129 src->scissor.count * sizeof(VkRect2D))) {
130 typed_memcpy(dest->scissor.scissors,
131 src->scissor.scissors, src->scissor.count);
132 dest_mask |= RADV_DYNAMIC_SCISSOR;
133 }
134 }
135
136 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
137 if (dest->line_width != src->line_width) {
138 dest->line_width = src->line_width;
139 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
140 }
141 }
142
143 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
144 if (memcmp(&dest->depth_bias, &src->depth_bias,
145 sizeof(src->depth_bias))) {
146 dest->depth_bias = src->depth_bias;
147 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
148 }
149 }
150
151 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
152 if (memcmp(&dest->blend_constants, &src->blend_constants,
153 sizeof(src->blend_constants))) {
154 typed_memcpy(dest->blend_constants,
155 src->blend_constants, 4);
156 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
157 }
158 }
159
160 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
161 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
162 sizeof(src->depth_bounds))) {
163 dest->depth_bounds = src->depth_bounds;
164 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
165 }
166 }
167
168 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
169 if (memcmp(&dest->stencil_compare_mask,
170 &src->stencil_compare_mask,
171 sizeof(src->stencil_compare_mask))) {
172 dest->stencil_compare_mask = src->stencil_compare_mask;
173 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
174 }
175 }
176
177 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
178 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
179 sizeof(src->stencil_write_mask))) {
180 dest->stencil_write_mask = src->stencil_write_mask;
181 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
182 }
183 }
184
185 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
186 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
187 sizeof(src->stencil_reference))) {
188 dest->stencil_reference = src->stencil_reference;
189 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
190 }
191 }
192
193 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
194 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
195 src->discard_rectangle.count * sizeof(VkRect2D))) {
196 typed_memcpy(dest->discard_rectangle.rectangles,
197 src->discard_rectangle.rectangles,
198 src->discard_rectangle.count);
199 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
200 }
201 }
202
203 if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
204 if (dest->sample_location.per_pixel != src->sample_location.per_pixel ||
205 dest->sample_location.grid_size.width != src->sample_location.grid_size.width ||
206 dest->sample_location.grid_size.height != src->sample_location.grid_size.height ||
207 memcmp(&dest->sample_location.locations,
208 &src->sample_location.locations,
209 src->sample_location.count * sizeof(VkSampleLocationEXT))) {
210 dest->sample_location.per_pixel = src->sample_location.per_pixel;
211 dest->sample_location.grid_size = src->sample_location.grid_size;
212 typed_memcpy(dest->sample_location.locations,
213 src->sample_location.locations,
214 src->sample_location.count);
215 dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
216 }
217 }
218
219 if (copy_mask & RADV_DYNAMIC_LINE_STIPPLE) {
220 if (memcmp(&dest->line_stipple, &src->line_stipple,
221 sizeof(src->line_stipple))) {
222 dest->line_stipple = src->line_stipple;
223 dest_mask |= RADV_DYNAMIC_LINE_STIPPLE;
224 }
225 }
226
227 cmd_buffer->state.dirty |= dest_mask;
228 }
229
230 static void
231 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
232 struct radv_pipeline *pipeline)
233 {
234 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
235 struct radv_shader_info *info;
236
237 if (!pipeline->streamout_shader ||
238 cmd_buffer->device->physical_device->use_ngg_streamout)
239 return;
240
241 info = &pipeline->streamout_shader->info;
242 for (int i = 0; i < MAX_SO_BUFFERS; i++)
243 so->stride_in_dw[i] = info->so.strides[i];
244
245 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
246 }
247
248 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
249 {
250 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
251 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
252 }
253
254 enum ring_type radv_queue_family_to_ring(int f) {
255 switch (f) {
256 case RADV_QUEUE_GENERAL:
257 return RING_GFX;
258 case RADV_QUEUE_COMPUTE:
259 return RING_COMPUTE;
260 case RADV_QUEUE_TRANSFER:
261 return RING_DMA;
262 default:
263 unreachable("Unknown queue family");
264 }
265 }
266
267 static VkResult radv_create_cmd_buffer(
268 struct radv_device * device,
269 struct radv_cmd_pool * pool,
270 VkCommandBufferLevel level,
271 VkCommandBuffer* pCommandBuffer)
272 {
273 struct radv_cmd_buffer *cmd_buffer;
274 unsigned ring;
275 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
276 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
277 if (cmd_buffer == NULL)
278 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
279
280 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
281 cmd_buffer->device = device;
282 cmd_buffer->pool = pool;
283 cmd_buffer->level = level;
284
285 if (pool) {
286 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
287 cmd_buffer->queue_family_index = pool->queue_family_index;
288
289 } else {
290 /* Init the pool_link so we can safely call list_del when we destroy
291 * the command buffer
292 */
293 list_inithead(&cmd_buffer->pool_link);
294 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
295 }
296
297 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
298
299 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
300 if (!cmd_buffer->cs) {
301 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
302 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
303 }
304
305 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
306
307 list_inithead(&cmd_buffer->upload.list);
308
309 return VK_SUCCESS;
310 }
311
312 static void
313 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
314 {
315 list_del(&cmd_buffer->pool_link);
316
317 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
318 &cmd_buffer->upload.list, list) {
319 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
320 list_del(&up->list);
321 free(up);
322 }
323
324 if (cmd_buffer->upload.upload_bo)
325 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
326 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
327
328 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
329 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
330
331 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
332 }
333
334 static VkResult
335 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
336 {
337 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
338
339 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
340 &cmd_buffer->upload.list, list) {
341 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
342 list_del(&up->list);
343 free(up);
344 }
345
346 cmd_buffer->push_constant_stages = 0;
347 cmd_buffer->scratch_size_per_wave_needed = 0;
348 cmd_buffer->scratch_waves_wanted = 0;
349 cmd_buffer->compute_scratch_size_per_wave_needed = 0;
350 cmd_buffer->compute_scratch_waves_wanted = 0;
351 cmd_buffer->esgs_ring_size_needed = 0;
352 cmd_buffer->gsvs_ring_size_needed = 0;
353 cmd_buffer->tess_rings_needed = false;
354 cmd_buffer->gds_needed = false;
355 cmd_buffer->gds_oa_needed = false;
356 cmd_buffer->sample_positions_needed = false;
357
358 if (cmd_buffer->upload.upload_bo)
359 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
360 cmd_buffer->upload.upload_bo);
361 cmd_buffer->upload.offset = 0;
362
363 cmd_buffer->record_result = VK_SUCCESS;
364
365 memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
366
367 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
368 cmd_buffer->descriptors[i].dirty = 0;
369 cmd_buffer->descriptors[i].valid = 0;
370 cmd_buffer->descriptors[i].push_dirty = false;
371 }
372
373 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
374 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
375 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
376 unsigned fence_offset, eop_bug_offset;
377 void *fence_ptr;
378
379 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
380 &fence_ptr);
381
382 cmd_buffer->gfx9_fence_va =
383 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
384 cmd_buffer->gfx9_fence_va += fence_offset;
385
386 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
387 /* Allocate a buffer for the EOP bug on GFX9. */
388 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
389 &eop_bug_offset, &fence_ptr);
390 cmd_buffer->gfx9_eop_bug_va =
391 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
392 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
393 }
394 }
395
396 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
397
398 return cmd_buffer->record_result;
399 }
400
401 static bool
402 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
403 uint64_t min_needed)
404 {
405 uint64_t new_size;
406 struct radeon_winsys_bo *bo;
407 struct radv_cmd_buffer_upload *upload;
408 struct radv_device *device = cmd_buffer->device;
409
410 new_size = MAX2(min_needed, 16 * 1024);
411 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
412
413 bo = device->ws->buffer_create(device->ws,
414 new_size, 4096,
415 RADEON_DOMAIN_GTT,
416 RADEON_FLAG_CPU_ACCESS|
417 RADEON_FLAG_NO_INTERPROCESS_SHARING |
418 RADEON_FLAG_32BIT,
419 RADV_BO_PRIORITY_UPLOAD_BUFFER);
420
421 if (!bo) {
422 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
423 return false;
424 }
425
426 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
427 if (cmd_buffer->upload.upload_bo) {
428 upload = malloc(sizeof(*upload));
429
430 if (!upload) {
431 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
432 device->ws->buffer_destroy(bo);
433 return false;
434 }
435
436 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
437 list_add(&upload->list, &cmd_buffer->upload.list);
438 }
439
440 cmd_buffer->upload.upload_bo = bo;
441 cmd_buffer->upload.size = new_size;
442 cmd_buffer->upload.offset = 0;
443 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
444
445 if (!cmd_buffer->upload.map) {
446 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
447 return false;
448 }
449
450 return true;
451 }
452
453 bool
454 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
455 unsigned size,
456 unsigned alignment,
457 unsigned *out_offset,
458 void **ptr)
459 {
460 assert(util_is_power_of_two_nonzero(alignment));
461
462 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
463 if (offset + size > cmd_buffer->upload.size) {
464 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
465 return false;
466 offset = 0;
467 }
468
469 *out_offset = offset;
470 *ptr = cmd_buffer->upload.map + offset;
471
472 cmd_buffer->upload.offset = offset + size;
473 return true;
474 }
475
476 bool
477 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
478 unsigned size, unsigned alignment,
479 const void *data, unsigned *out_offset)
480 {
481 uint8_t *ptr;
482
483 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
484 out_offset, (void **)&ptr))
485 return false;
486
487 if (ptr)
488 memcpy(ptr, data, size);
489
490 return true;
491 }
492
493 static void
494 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
495 unsigned count, const uint32_t *data)
496 {
497 struct radeon_cmdbuf *cs = cmd_buffer->cs;
498
499 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
500
501 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
502 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
503 S_370_WR_CONFIRM(1) |
504 S_370_ENGINE_SEL(V_370_ME));
505 radeon_emit(cs, va);
506 radeon_emit(cs, va >> 32);
507 radeon_emit_array(cs, data, count);
508 }
509
510 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
511 {
512 struct radv_device *device = cmd_buffer->device;
513 struct radeon_cmdbuf *cs = cmd_buffer->cs;
514 uint64_t va;
515
516 va = radv_buffer_get_va(device->trace_bo);
517 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
518 va += 4;
519
520 ++cmd_buffer->state.trace_id;
521 radv_emit_write_data_packet(cmd_buffer, va, 1,
522 &cmd_buffer->state.trace_id);
523
524 radeon_check_space(cmd_buffer->device->ws, cs, 2);
525
526 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
527 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
528 }
529
530 static void
531 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
532 enum radv_cmd_flush_bits flags)
533 {
534 if (unlikely(cmd_buffer->device->thread_trace_bo)) {
535 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
536 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_THREAD_TRACE_MARKER) | EVENT_INDEX(0));
537 }
538
539 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
540 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
541 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
542
543 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
544
545 /* Force wait for graphics or compute engines to be idle. */
546 si_cs_emit_cache_flush(cmd_buffer->cs,
547 cmd_buffer->device->physical_device->rad_info.chip_class,
548 &cmd_buffer->gfx9_fence_idx,
549 cmd_buffer->gfx9_fence_va,
550 radv_cmd_buffer_uses_mec(cmd_buffer),
551 flags, cmd_buffer->gfx9_eop_bug_va);
552 }
553
554 if (unlikely(cmd_buffer->device->trace_bo))
555 radv_cmd_buffer_trace_emit(cmd_buffer);
556 }
557
558 static void
559 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
560 struct radv_pipeline *pipeline, enum ring_type ring)
561 {
562 struct radv_device *device = cmd_buffer->device;
563 uint32_t data[2];
564 uint64_t va;
565
566 va = radv_buffer_get_va(device->trace_bo);
567
568 switch (ring) {
569 case RING_GFX:
570 va += 8;
571 break;
572 case RING_COMPUTE:
573 va += 16;
574 break;
575 default:
576 assert(!"invalid ring type");
577 }
578
579 uint64_t pipeline_address = (uintptr_t)pipeline;
580 data[0] = pipeline_address;
581 data[1] = pipeline_address >> 32;
582
583 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
584 }
585
586 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
587 VkPipelineBindPoint bind_point,
588 struct radv_descriptor_set *set,
589 unsigned idx)
590 {
591 struct radv_descriptor_state *descriptors_state =
592 radv_get_descriptors_state(cmd_buffer, bind_point);
593
594 descriptors_state->sets[idx] = set;
595
596 descriptors_state->valid |= (1u << idx); /* active descriptors */
597 descriptors_state->dirty |= (1u << idx);
598 }
599
600 static void
601 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
602 VkPipelineBindPoint bind_point)
603 {
604 struct radv_descriptor_state *descriptors_state =
605 radv_get_descriptors_state(cmd_buffer, bind_point);
606 struct radv_device *device = cmd_buffer->device;
607 uint32_t data[MAX_SETS * 2] = {};
608 uint64_t va;
609 unsigned i;
610 va = radv_buffer_get_va(device->trace_bo) + 24;
611
612 for_each_bit(i, descriptors_state->valid) {
613 struct radv_descriptor_set *set = descriptors_state->sets[i];
614 data[i * 2] = (uint64_t)(uintptr_t)set;
615 data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
616 }
617
618 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
619 }
620
621 struct radv_userdata_info *
622 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
623 gl_shader_stage stage,
624 int idx)
625 {
626 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
627 return &shader->info.user_sgprs_locs.shader_data[idx];
628 }
629
630 static void
631 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
632 struct radv_pipeline *pipeline,
633 gl_shader_stage stage,
634 int idx, uint64_t va)
635 {
636 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
637 uint32_t base_reg = pipeline->user_data_0[stage];
638 if (loc->sgpr_idx == -1)
639 return;
640
641 assert(loc->num_sgprs == 1);
642
643 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
644 base_reg + loc->sgpr_idx * 4, va, false);
645 }
646
647 static void
648 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
649 struct radv_pipeline *pipeline,
650 struct radv_descriptor_state *descriptors_state,
651 gl_shader_stage stage)
652 {
653 struct radv_device *device = cmd_buffer->device;
654 struct radeon_cmdbuf *cs = cmd_buffer->cs;
655 uint32_t sh_base = pipeline->user_data_0[stage];
656 struct radv_userdata_locations *locs =
657 &pipeline->shaders[stage]->info.user_sgprs_locs;
658 unsigned mask = locs->descriptor_sets_enabled;
659
660 mask &= descriptors_state->dirty & descriptors_state->valid;
661
662 while (mask) {
663 int start, count;
664
665 u_bit_scan_consecutive_range(&mask, &start, &count);
666
667 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
668 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
669
670 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
671 for (int i = 0; i < count; i++) {
672 struct radv_descriptor_set *set =
673 descriptors_state->sets[start + i];
674
675 radv_emit_shader_pointer_body(device, cs, set->va, true);
676 }
677 }
678 }
679
680 /**
681 * Convert the user sample locations to hardware sample locations (the values
682 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
683 */
684 static void
685 radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
686 uint32_t x, uint32_t y, VkOffset2D *sample_locs)
687 {
688 uint32_t x_offset = x % state->grid_size.width;
689 uint32_t y_offset = y % state->grid_size.height;
690 uint32_t num_samples = (uint32_t)state->per_pixel;
691 VkSampleLocationEXT *user_locs;
692 uint32_t pixel_offset;
693
694 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
695
696 assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
697 user_locs = &state->locations[pixel_offset];
698
699 for (uint32_t i = 0; i < num_samples; i++) {
700 float shifted_pos_x = user_locs[i].x - 0.5;
701 float shifted_pos_y = user_locs[i].y - 0.5;
702
703 int32_t scaled_pos_x = floor(shifted_pos_x * 16);
704 int32_t scaled_pos_y = floor(shifted_pos_y * 16);
705
706 sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
707 sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
708 }
709 }
710
711 /**
712 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
713 * locations.
714 */
715 static void
716 radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
717 uint32_t *sample_locs_pixel)
718 {
719 for (uint32_t i = 0; i < num_samples; i++) {
720 uint32_t sample_reg_idx = i / 4;
721 uint32_t sample_loc_idx = i % 4;
722 int32_t pos_x = sample_locs[i].x;
723 int32_t pos_y = sample_locs[i].y;
724
725 uint32_t shift_x = 8 * sample_loc_idx;
726 uint32_t shift_y = shift_x + 4;
727
728 sample_locs_pixel[sample_reg_idx] |= (pos_x & 0xf) << shift_x;
729 sample_locs_pixel[sample_reg_idx] |= (pos_y & 0xf) << shift_y;
730 }
731 }
732
733 /**
734 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
735 * sample locations.
736 */
737 static uint64_t
738 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer,
739 VkOffset2D *sample_locs,
740 uint32_t num_samples)
741 {
742 uint32_t centroid_priorities[num_samples];
743 uint32_t sample_mask = num_samples - 1;
744 uint32_t distances[num_samples];
745 uint64_t centroid_priority = 0;
746
747 /* Compute the distances from center for each sample. */
748 for (int i = 0; i < num_samples; i++) {
749 distances[i] = (sample_locs[i].x * sample_locs[i].x) +
750 (sample_locs[i].y * sample_locs[i].y);
751 }
752
753 /* Compute the centroid priorities by looking at the distances array. */
754 for (int i = 0; i < num_samples; i++) {
755 uint32_t min_idx = 0;
756
757 for (int j = 1; j < num_samples; j++) {
758 if (distances[j] < distances[min_idx])
759 min_idx = j;
760 }
761
762 centroid_priorities[i] = min_idx;
763 distances[min_idx] = 0xffffffff;
764 }
765
766 /* Compute the final centroid priority. */
767 for (int i = 0; i < 8; i++) {
768 centroid_priority |=
769 centroid_priorities[i & sample_mask] << (i * 4);
770 }
771
772 return centroid_priority << 32 | centroid_priority;
773 }
774
775 /**
776 * Emit the sample locations that are specified with VK_EXT_sample_locations.
777 */
778 static void
779 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
780 {
781 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
782 struct radv_multisample_state *ms = &pipeline->graphics.ms;
783 struct radv_sample_locations_state *sample_location =
784 &cmd_buffer->state.dynamic.sample_location;
785 uint32_t num_samples = (uint32_t)sample_location->per_pixel;
786 struct radeon_cmdbuf *cs = cmd_buffer->cs;
787 uint32_t sample_locs_pixel[4][2] = {};
788 VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
789 uint32_t max_sample_dist = 0;
790 uint64_t centroid_priority;
791
792 if (!cmd_buffer->state.dynamic.sample_location.count)
793 return;
794
795 /* Convert the user sample locations to hardware sample locations. */
796 radv_convert_user_sample_locs(sample_location, 0, 0, sample_locs[0]);
797 radv_convert_user_sample_locs(sample_location, 1, 0, sample_locs[1]);
798 radv_convert_user_sample_locs(sample_location, 0, 1, sample_locs[2]);
799 radv_convert_user_sample_locs(sample_location, 1, 1, sample_locs[3]);
800
801 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
802 for (uint32_t i = 0; i < 4; i++) {
803 radv_compute_sample_locs_pixel(num_samples, sample_locs[i],
804 sample_locs_pixel[i]);
805 }
806
807 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
808 centroid_priority =
809 radv_compute_centroid_priority(cmd_buffer, sample_locs[0],
810 num_samples);
811
812 /* Compute the maximum sample distance from the specified locations. */
813 for (unsigned i = 0; i < 4; ++i) {
814 for (uint32_t j = 0; j < num_samples; j++) {
815 VkOffset2D offset = sample_locs[i][j];
816 max_sample_dist = MAX2(max_sample_dist,
817 MAX2(abs(offset.x), abs(offset.y)));
818 }
819 }
820
821 /* Emit the specified user sample locations. */
822 switch (num_samples) {
823 case 2:
824 case 4:
825 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
826 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
827 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
828 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
829 break;
830 case 8:
831 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
832 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
833 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
834 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
835 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs_pixel[0][1]);
836 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs_pixel[1][1]);
837 radeon_set_context_reg(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs_pixel[2][1]);
838 radeon_set_context_reg(cs, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs_pixel[3][1]);
839 break;
840 default:
841 unreachable("invalid number of samples");
842 }
843
844 /* Emit the maximum sample distance and the centroid priority. */
845 uint32_t pa_sc_aa_config = ms->pa_sc_aa_config;
846
847 pa_sc_aa_config &= C_028BE0_MAX_SAMPLE_DIST;
848 pa_sc_aa_config |= S_028BE0_MAX_SAMPLE_DIST(max_sample_dist);
849
850 radeon_set_context_reg_seq(cs, R_028BE0_PA_SC_AA_CONFIG, 1);
851 radeon_emit(cs, pa_sc_aa_config);
852
853 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
854 radeon_emit(cs, centroid_priority);
855 radeon_emit(cs, centroid_priority >> 32);
856
857 /* GFX9: Flush DFSM when the AA mode changes. */
858 if (cmd_buffer->device->dfsm_allowed) {
859 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
860 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
861 }
862
863 cmd_buffer->state.context_roll_without_scissor_emitted = true;
864 }
865
866 static void
867 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
868 struct radv_pipeline *pipeline,
869 gl_shader_stage stage,
870 int idx, int count, uint32_t *values)
871 {
872 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
873 uint32_t base_reg = pipeline->user_data_0[stage];
874 if (loc->sgpr_idx == -1)
875 return;
876
877 assert(loc->num_sgprs == count);
878
879 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
880 radeon_emit_array(cmd_buffer->cs, values, count);
881 }
882
883 static void
884 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
885 struct radv_pipeline *pipeline)
886 {
887 int num_samples = pipeline->graphics.ms.num_samples;
888 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
889
890 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.needs_sample_positions)
891 cmd_buffer->sample_positions_needed = true;
892
893 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
894 return;
895
896 radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
897
898 cmd_buffer->state.context_roll_without_scissor_emitted = true;
899 }
900
901 static void
902 radv_update_binning_state(struct radv_cmd_buffer *cmd_buffer,
903 struct radv_pipeline *pipeline)
904 {
905 const struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
906
907
908 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
909 return;
910
911 if (old_pipeline &&
912 old_pipeline->graphics.binning.pa_sc_binner_cntl_0 == pipeline->graphics.binning.pa_sc_binner_cntl_0 &&
913 old_pipeline->graphics.binning.db_dfsm_control == pipeline->graphics.binning.db_dfsm_control)
914 return;
915
916 bool binning_flush = false;
917 if (cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA12 ||
918 cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA20 ||
919 cmd_buffer->device->physical_device->rad_info.family == CHIP_RAVEN2 ||
920 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
921 binning_flush = !old_pipeline ||
922 G_028C44_BINNING_MODE(old_pipeline->graphics.binning.pa_sc_binner_cntl_0) !=
923 G_028C44_BINNING_MODE(pipeline->graphics.binning.pa_sc_binner_cntl_0);
924 }
925
926 radeon_set_context_reg(cmd_buffer->cs, R_028C44_PA_SC_BINNER_CNTL_0,
927 pipeline->graphics.binning.pa_sc_binner_cntl_0 |
928 S_028C44_FLUSH_ON_BINNING_TRANSITION(!!binning_flush));
929
930 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
931 radeon_set_context_reg(cmd_buffer->cs, R_028038_DB_DFSM_CONTROL,
932 pipeline->graphics.binning.db_dfsm_control);
933 } else {
934 radeon_set_context_reg(cmd_buffer->cs, R_028060_DB_DFSM_CONTROL,
935 pipeline->graphics.binning.db_dfsm_control);
936 }
937
938 cmd_buffer->state.context_roll_without_scissor_emitted = true;
939 }
940
941
942 static void
943 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
944 struct radv_shader_variant *shader)
945 {
946 uint64_t va;
947
948 if (!shader)
949 return;
950
951 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
952
953 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
954 }
955
956 static void
957 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
958 struct radv_pipeline *pipeline,
959 bool vertex_stage_only)
960 {
961 struct radv_cmd_state *state = &cmd_buffer->state;
962 uint32_t mask = state->prefetch_L2_mask;
963
964 if (vertex_stage_only) {
965 /* Fast prefetch path for starting draws as soon as possible.
966 */
967 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
968 RADV_PREFETCH_VBO_DESCRIPTORS);
969 }
970
971 if (mask & RADV_PREFETCH_VS)
972 radv_emit_shader_prefetch(cmd_buffer,
973 pipeline->shaders[MESA_SHADER_VERTEX]);
974
975 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
976 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
977
978 if (mask & RADV_PREFETCH_TCS)
979 radv_emit_shader_prefetch(cmd_buffer,
980 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
981
982 if (mask & RADV_PREFETCH_TES)
983 radv_emit_shader_prefetch(cmd_buffer,
984 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
985
986 if (mask & RADV_PREFETCH_GS) {
987 radv_emit_shader_prefetch(cmd_buffer,
988 pipeline->shaders[MESA_SHADER_GEOMETRY]);
989 if (radv_pipeline_has_gs_copy_shader(pipeline))
990 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
991 }
992
993 if (mask & RADV_PREFETCH_PS)
994 radv_emit_shader_prefetch(cmd_buffer,
995 pipeline->shaders[MESA_SHADER_FRAGMENT]);
996
997 state->prefetch_L2_mask &= ~mask;
998 }
999
1000 static void
1001 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
1002 {
1003 if (!cmd_buffer->device->physical_device->rad_info.rbplus_allowed)
1004 return;
1005
1006 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1007 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1008
1009 unsigned sx_ps_downconvert = 0;
1010 unsigned sx_blend_opt_epsilon = 0;
1011 unsigned sx_blend_opt_control = 0;
1012
1013 if (!cmd_buffer->state.attachments || !subpass)
1014 return;
1015
1016 for (unsigned i = 0; i < subpass->color_count; ++i) {
1017 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1018 /* We don't set the DISABLE bits, because the HW can't have holes,
1019 * so the SPI color format is set to 32-bit 1-component. */
1020 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1021 continue;
1022 }
1023
1024 int idx = subpass->color_attachments[i].attachment;
1025 struct radv_color_buffer_info *cb = &cmd_buffer->state.attachments[idx].cb;
1026
1027 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
1028 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
1029 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
1030 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
1031
1032 bool has_alpha, has_rgb;
1033
1034 /* Set if RGB and A are present. */
1035 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
1036
1037 if (format == V_028C70_COLOR_8 ||
1038 format == V_028C70_COLOR_16 ||
1039 format == V_028C70_COLOR_32)
1040 has_rgb = !has_alpha;
1041 else
1042 has_rgb = true;
1043
1044 /* Check the colormask and export format. */
1045 if (!(colormask & 0x7))
1046 has_rgb = false;
1047 if (!(colormask & 0x8))
1048 has_alpha = false;
1049
1050 if (spi_format == V_028714_SPI_SHADER_ZERO) {
1051 has_rgb = false;
1052 has_alpha = false;
1053 }
1054
1055 /* Disable value checking for disabled channels. */
1056 if (!has_rgb)
1057 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1058 if (!has_alpha)
1059 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1060
1061 /* Enable down-conversion for 32bpp and smaller formats. */
1062 switch (format) {
1063 case V_028C70_COLOR_8:
1064 case V_028C70_COLOR_8_8:
1065 case V_028C70_COLOR_8_8_8_8:
1066 /* For 1 and 2-channel formats, use the superset thereof. */
1067 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
1068 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1069 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1070 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
1071 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
1072 }
1073 break;
1074
1075 case V_028C70_COLOR_5_6_5:
1076 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1077 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
1078 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
1079 }
1080 break;
1081
1082 case V_028C70_COLOR_1_5_5_5:
1083 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1084 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
1085 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
1086 }
1087 break;
1088
1089 case V_028C70_COLOR_4_4_4_4:
1090 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1091 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
1092 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
1093 }
1094 break;
1095
1096 case V_028C70_COLOR_32:
1097 if (swap == V_028C70_SWAP_STD &&
1098 spi_format == V_028714_SPI_SHADER_32_R)
1099 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1100 else if (swap == V_028C70_SWAP_ALT_REV &&
1101 spi_format == V_028714_SPI_SHADER_32_AR)
1102 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
1103 break;
1104
1105 case V_028C70_COLOR_16:
1106 case V_028C70_COLOR_16_16:
1107 /* For 1-channel formats, use the superset thereof. */
1108 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
1109 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
1110 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1111 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1112 if (swap == V_028C70_SWAP_STD ||
1113 swap == V_028C70_SWAP_STD_REV)
1114 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
1115 else
1116 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
1117 }
1118 break;
1119
1120 case V_028C70_COLOR_10_11_11:
1121 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1122 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
1123 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
1124 }
1125 break;
1126
1127 case V_028C70_COLOR_2_10_10_10:
1128 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1129 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
1130 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
1131 }
1132 break;
1133 }
1134 }
1135
1136 /* Do not set the DISABLE bits for the unused attachments, as that
1137 * breaks dual source blending in SkQP and does not seem to improve
1138 * performance. */
1139
1140 if (sx_ps_downconvert == cmd_buffer->state.last_sx_ps_downconvert &&
1141 sx_blend_opt_epsilon == cmd_buffer->state.last_sx_blend_opt_epsilon &&
1142 sx_blend_opt_control == cmd_buffer->state.last_sx_blend_opt_control)
1143 return;
1144
1145 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
1146 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
1147 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
1148 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
1149
1150 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1151
1152 cmd_buffer->state.last_sx_ps_downconvert = sx_ps_downconvert;
1153 cmd_buffer->state.last_sx_blend_opt_epsilon = sx_blend_opt_epsilon;
1154 cmd_buffer->state.last_sx_blend_opt_control = sx_blend_opt_control;
1155 }
1156
1157 static void
1158 radv_emit_batch_break_on_new_ps(struct radv_cmd_buffer *cmd_buffer)
1159 {
1160 if (!cmd_buffer->device->pbb_allowed)
1161 return;
1162
1163 struct radv_binning_settings settings =
1164 radv_get_binning_settings(cmd_buffer->device->physical_device);
1165 bool break_for_new_ps =
1166 (!cmd_buffer->state.emitted_pipeline ||
1167 cmd_buffer->state.emitted_pipeline->shaders[MESA_SHADER_FRAGMENT] !=
1168 cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT]) &&
1169 (settings.context_states_per_bin > 1 ||
1170 settings.persistent_states_per_bin > 1);
1171 bool break_for_new_cb_target_mask =
1172 (!cmd_buffer->state.emitted_pipeline ||
1173 cmd_buffer->state.emitted_pipeline->graphics.cb_target_mask !=
1174 cmd_buffer->state.pipeline->graphics.cb_target_mask) &&
1175 settings.context_states_per_bin > 1;
1176
1177 if (!break_for_new_ps && !break_for_new_cb_target_mask)
1178 return;
1179
1180 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1181 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1182 }
1183
1184 static void
1185 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1186 {
1187 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1188
1189 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1190 return;
1191
1192 radv_update_multisample_state(cmd_buffer, pipeline);
1193 radv_update_binning_state(cmd_buffer, pipeline);
1194
1195 cmd_buffer->scratch_size_per_wave_needed = MAX2(cmd_buffer->scratch_size_per_wave_needed,
1196 pipeline->scratch_bytes_per_wave);
1197 cmd_buffer->scratch_waves_wanted = MAX2(cmd_buffer->scratch_waves_wanted,
1198 pipeline->max_waves);
1199
1200 if (!cmd_buffer->state.emitted_pipeline ||
1201 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1202 pipeline->graphics.can_use_guardband)
1203 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1204
1205 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
1206
1207 if (!cmd_buffer->state.emitted_pipeline ||
1208 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
1209 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
1210 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
1211 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
1212 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
1213 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1214 }
1215
1216 radv_emit_batch_break_on_new_ps(cmd_buffer);
1217
1218 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
1219 if (!pipeline->shaders[i])
1220 continue;
1221
1222 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1223 pipeline->shaders[i]->bo);
1224 }
1225
1226 if (radv_pipeline_has_gs_copy_shader(pipeline))
1227 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1228 pipeline->gs_copy_shader->bo);
1229
1230 if (unlikely(cmd_buffer->device->trace_bo))
1231 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1232
1233 cmd_buffer->state.emitted_pipeline = pipeline;
1234
1235 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1236 }
1237
1238 static void
1239 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1240 {
1241 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1242 cmd_buffer->state.dynamic.viewport.viewports);
1243 }
1244
1245 static void
1246 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1247 {
1248 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1249
1250 si_write_scissors(cmd_buffer->cs, 0, count,
1251 cmd_buffer->state.dynamic.scissor.scissors,
1252 cmd_buffer->state.dynamic.viewport.viewports,
1253 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1254
1255 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1256 }
1257
1258 static void
1259 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1260 {
1261 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1262 return;
1263
1264 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1265 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1266 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1267 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1268 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1269 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1270 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1271 }
1272 }
1273
1274 static void
1275 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1276 {
1277 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1278
1279 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1280 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1281 }
1282
1283 static void
1284 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1285 {
1286 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1287
1288 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1289 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1290 }
1291
1292 static void
1293 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1294 {
1295 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1296
1297 radeon_set_context_reg_seq(cmd_buffer->cs,
1298 R_028430_DB_STENCILREFMASK, 2);
1299 radeon_emit(cmd_buffer->cs,
1300 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1301 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1302 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1303 S_028430_STENCILOPVAL(1));
1304 radeon_emit(cmd_buffer->cs,
1305 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1306 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1307 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1308 S_028434_STENCILOPVAL_BF(1));
1309 }
1310
1311 static void
1312 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1313 {
1314 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1315
1316 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1317 fui(d->depth_bounds.min));
1318 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1319 fui(d->depth_bounds.max));
1320 }
1321
1322 static void
1323 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1324 {
1325 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1326 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1327 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1328
1329
1330 radeon_set_context_reg_seq(cmd_buffer->cs,
1331 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1332 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1333 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1334 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1335 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1336 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1337 }
1338
1339 static void
1340 radv_emit_line_stipple(struct radv_cmd_buffer *cmd_buffer)
1341 {
1342 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1343 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1344 uint32_t auto_reset_cntl = 1;
1345
1346 if (pipeline->graphics.topology == VK_PRIMITIVE_TOPOLOGY_LINE_STRIP)
1347 auto_reset_cntl = 2;
1348
1349 radeon_set_context_reg(cmd_buffer->cs, R_028A0C_PA_SC_LINE_STIPPLE,
1350 S_028A0C_LINE_PATTERN(d->line_stipple.pattern) |
1351 S_028A0C_REPEAT_COUNT(d->line_stipple.factor - 1) |
1352 S_028A0C_AUTO_RESET_CNTL(auto_reset_cntl));
1353 }
1354
1355 static void
1356 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1357 int index,
1358 struct radv_color_buffer_info *cb,
1359 struct radv_image_view *iview,
1360 VkImageLayout layout,
1361 bool in_render_loop)
1362 {
1363 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
1364 uint32_t cb_color_info = cb->cb_color_info;
1365 struct radv_image *image = iview->image;
1366
1367 if (!radv_layout_dcc_compressed(cmd_buffer->device, image, layout, in_render_loop,
1368 radv_image_queue_family_mask(image,
1369 cmd_buffer->queue_family_index,
1370 cmd_buffer->queue_family_index))) {
1371 cb_color_info &= C_028C70_DCC_ENABLE;
1372 }
1373
1374 if (radv_image_is_tc_compat_cmask(image) &&
1375 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1376 radv_is_dcc_decompress_pipeline(cmd_buffer))) {
1377 /* If this bit is set, the FMASK decompression operation
1378 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1379 */
1380 cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
1381 }
1382
1383 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1384 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1385 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1386 radeon_emit(cmd_buffer->cs, 0);
1387 radeon_emit(cmd_buffer->cs, 0);
1388 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1389 radeon_emit(cmd_buffer->cs, cb_color_info);
1390 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1391 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1392 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1393 radeon_emit(cmd_buffer->cs, 0);
1394 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1395 radeon_emit(cmd_buffer->cs, 0);
1396
1397 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 1);
1398 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1399
1400 radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4,
1401 cb->cb_color_base >> 32);
1402 radeon_set_context_reg(cmd_buffer->cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + index * 4,
1403 cb->cb_color_cmask >> 32);
1404 radeon_set_context_reg(cmd_buffer->cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + index * 4,
1405 cb->cb_color_fmask >> 32);
1406 radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4,
1407 cb->cb_dcc_base >> 32);
1408 radeon_set_context_reg(cmd_buffer->cs, R_028EC0_CB_COLOR0_ATTRIB2 + index * 4,
1409 cb->cb_color_attrib2);
1410 radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4,
1411 cb->cb_color_attrib3);
1412 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1413 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1414 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1415 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1416 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1417 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1418 radeon_emit(cmd_buffer->cs, cb_color_info);
1419 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1420 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1421 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1422 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1423 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1424 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1425
1426 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1427 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1428 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1429
1430 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1431 cb->cb_mrt_epitch);
1432 } else {
1433 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1434 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1435 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1436 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1437 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1438 radeon_emit(cmd_buffer->cs, cb_color_info);
1439 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1440 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1441 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1442 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1443 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1444 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1445
1446 if (is_vi) { /* DCC BASE */
1447 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1448 }
1449 }
1450
1451 if (radv_dcc_enabled(image, iview->base_mip)) {
1452 /* Drawing with DCC enabled also compresses colorbuffers. */
1453 VkImageSubresourceRange range = {
1454 .aspectMask = iview->aspect_mask,
1455 .baseMipLevel = iview->base_mip,
1456 .levelCount = iview->level_count,
1457 .baseArrayLayer = iview->base_layer,
1458 .layerCount = iview->layer_count,
1459 };
1460
1461 radv_update_dcc_metadata(cmd_buffer, image, &range, true);
1462 }
1463 }
1464
1465 static void
1466 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1467 struct radv_ds_buffer_info *ds,
1468 const struct radv_image_view *iview,
1469 VkImageLayout layout,
1470 bool in_render_loop, bool requires_cond_exec)
1471 {
1472 const struct radv_image *image = iview->image;
1473 uint32_t db_z_info = ds->db_z_info;
1474 uint32_t db_z_info_reg;
1475
1476 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug ||
1477 !radv_image_is_tc_compat_htile(image))
1478 return;
1479
1480 if (!radv_layout_is_htile_compressed(image, layout, in_render_loop,
1481 radv_image_queue_family_mask(image,
1482 cmd_buffer->queue_family_index,
1483 cmd_buffer->queue_family_index))) {
1484 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1485 }
1486
1487 db_z_info &= C_028040_ZRANGE_PRECISION;
1488
1489 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1490 db_z_info_reg = R_028038_DB_Z_INFO;
1491 } else {
1492 db_z_info_reg = R_028040_DB_Z_INFO;
1493 }
1494
1495 /* When we don't know the last fast clear value we need to emit a
1496 * conditional packet that will eventually skip the following
1497 * SET_CONTEXT_REG packet.
1498 */
1499 if (requires_cond_exec) {
1500 uint64_t va = radv_get_tc_compat_zrange_va(image, iview->base_mip);
1501
1502 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1503 radeon_emit(cmd_buffer->cs, va);
1504 radeon_emit(cmd_buffer->cs, va >> 32);
1505 radeon_emit(cmd_buffer->cs, 0);
1506 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1507 }
1508
1509 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1510 }
1511
1512 static void
1513 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1514 struct radv_ds_buffer_info *ds,
1515 struct radv_image_view *iview,
1516 VkImageLayout layout,
1517 bool in_render_loop)
1518 {
1519 const struct radv_image *image = iview->image;
1520 uint32_t db_z_info = ds->db_z_info;
1521 uint32_t db_stencil_info = ds->db_stencil_info;
1522
1523 if (!radv_layout_is_htile_compressed(image, layout, in_render_loop,
1524 radv_image_queue_family_mask(image,
1525 cmd_buffer->queue_family_index,
1526 cmd_buffer->queue_family_index))) {
1527 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1528 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1529 }
1530
1531 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1532 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1533
1534 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1535 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1536 radeon_set_context_reg(cmd_buffer->cs, R_02801C_DB_DEPTH_SIZE_XY, ds->db_depth_size);
1537
1538 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 7);
1539 radeon_emit(cmd_buffer->cs, S_02803C_RESOURCE_LEVEL(1));
1540 radeon_emit(cmd_buffer->cs, db_z_info);
1541 radeon_emit(cmd_buffer->cs, db_stencil_info);
1542 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1543 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1544 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1545 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1546
1547 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_READ_BASE_HI, 5);
1548 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1549 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1550 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1551 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1552 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1553 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1554 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1555 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1556 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1557 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1558
1559 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1560 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1561 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1562 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1563 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1564 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1565 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1566 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1567 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1568 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1569 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1570
1571 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1572 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1573 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1574 } else {
1575 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1576
1577 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1578 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1579 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1580 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1581 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1582 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1583 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1584 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1585 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1586 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1587
1588 }
1589
1590 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1591 radv_update_zrange_precision(cmd_buffer, ds, iview, layout,
1592 in_render_loop, true);
1593
1594 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1595 ds->pa_su_poly_offset_db_fmt_cntl);
1596 }
1597
1598 /**
1599 * Update the fast clear depth/stencil values if the image is bound as a
1600 * depth/stencil buffer.
1601 */
1602 static void
1603 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1604 const struct radv_image_view *iview,
1605 VkClearDepthStencilValue ds_clear_value,
1606 VkImageAspectFlags aspects)
1607 {
1608 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1609 const struct radv_image *image = iview->image;
1610 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1611 uint32_t att_idx;
1612
1613 if (!cmd_buffer->state.attachments || !subpass)
1614 return;
1615
1616 if (!subpass->depth_stencil_attachment)
1617 return;
1618
1619 att_idx = subpass->depth_stencil_attachment->attachment;
1620 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1621 return;
1622
1623 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1624 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1625 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1626 radeon_emit(cs, ds_clear_value.stencil);
1627 radeon_emit(cs, fui(ds_clear_value.depth));
1628 } else if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1629 radeon_set_context_reg_seq(cs, R_02802C_DB_DEPTH_CLEAR, 1);
1630 radeon_emit(cs, fui(ds_clear_value.depth));
1631 } else {
1632 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1633 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 1);
1634 radeon_emit(cs, ds_clear_value.stencil);
1635 }
1636
1637 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1638 * only needed when clearing Z to 0.0.
1639 */
1640 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1641 ds_clear_value.depth == 0.0) {
1642 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1643 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
1644
1645 radv_update_zrange_precision(cmd_buffer, &cmd_buffer->state.attachments[att_idx].ds,
1646 iview, layout, in_render_loop, false);
1647 }
1648
1649 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1650 }
1651
1652 /**
1653 * Set the clear depth/stencil values to the image's metadata.
1654 */
1655 static void
1656 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1657 struct radv_image *image,
1658 const VkImageSubresourceRange *range,
1659 VkClearDepthStencilValue ds_clear_value,
1660 VkImageAspectFlags aspects)
1661 {
1662 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1663 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel);
1664 uint32_t level_count = radv_get_levelCount(image, range);
1665
1666 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1667 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1668 /* Use the fastest way when both aspects are used. */
1669 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + 2 * level_count, cmd_buffer->state.predicating));
1670 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1671 S_370_WR_CONFIRM(1) |
1672 S_370_ENGINE_SEL(V_370_PFP));
1673 radeon_emit(cs, va);
1674 radeon_emit(cs, va >> 32);
1675
1676 for (uint32_t l = 0; l < level_count; l++) {
1677 radeon_emit(cs, ds_clear_value.stencil);
1678 radeon_emit(cs, fui(ds_clear_value.depth));
1679 }
1680 } else {
1681 /* Otherwise we need one WRITE_DATA packet per level. */
1682 for (uint32_t l = 0; l < level_count; l++) {
1683 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel + l);
1684 unsigned value;
1685
1686 if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1687 value = fui(ds_clear_value.depth);
1688 va += 4;
1689 } else {
1690 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1691 value = ds_clear_value.stencil;
1692 }
1693
1694 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1695 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1696 S_370_WR_CONFIRM(1) |
1697 S_370_ENGINE_SEL(V_370_PFP));
1698 radeon_emit(cs, va);
1699 radeon_emit(cs, va >> 32);
1700 radeon_emit(cs, value);
1701 }
1702 }
1703 }
1704
1705 /**
1706 * Update the TC-compat metadata value for this image.
1707 */
1708 static void
1709 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1710 struct radv_image *image,
1711 const VkImageSubresourceRange *range,
1712 uint32_t value)
1713 {
1714 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1715
1716 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug)
1717 return;
1718
1719 uint64_t va = radv_get_tc_compat_zrange_va(image, range->baseMipLevel);
1720 uint32_t level_count = radv_get_levelCount(image, range);
1721
1722 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + level_count, cmd_buffer->state.predicating));
1723 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1724 S_370_WR_CONFIRM(1) |
1725 S_370_ENGINE_SEL(V_370_PFP));
1726 radeon_emit(cs, va);
1727 radeon_emit(cs, va >> 32);
1728
1729 for (uint32_t l = 0; l < level_count; l++)
1730 radeon_emit(cs, value);
1731 }
1732
1733 static void
1734 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1735 const struct radv_image_view *iview,
1736 VkClearDepthStencilValue ds_clear_value)
1737 {
1738 VkImageSubresourceRange range = {
1739 .aspectMask = iview->aspect_mask,
1740 .baseMipLevel = iview->base_mip,
1741 .levelCount = iview->level_count,
1742 .baseArrayLayer = iview->base_layer,
1743 .layerCount = iview->layer_count,
1744 };
1745 uint32_t cond_val;
1746
1747 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1748 * depth clear value is 0.0f.
1749 */
1750 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1751
1752 radv_set_tc_compat_zrange_metadata(cmd_buffer, iview->image, &range,
1753 cond_val);
1754 }
1755
1756 /**
1757 * Update the clear depth/stencil values for this image.
1758 */
1759 void
1760 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1761 const struct radv_image_view *iview,
1762 VkClearDepthStencilValue ds_clear_value,
1763 VkImageAspectFlags aspects)
1764 {
1765 VkImageSubresourceRange range = {
1766 .aspectMask = iview->aspect_mask,
1767 .baseMipLevel = iview->base_mip,
1768 .levelCount = iview->level_count,
1769 .baseArrayLayer = iview->base_layer,
1770 .layerCount = iview->layer_count,
1771 };
1772 struct radv_image *image = iview->image;
1773
1774 assert(radv_image_has_htile(image));
1775
1776 radv_set_ds_clear_metadata(cmd_buffer, iview->image, &range,
1777 ds_clear_value, aspects);
1778
1779 if (radv_image_is_tc_compat_htile(image) &&
1780 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1781 radv_update_tc_compat_zrange_metadata(cmd_buffer, iview,
1782 ds_clear_value);
1783 }
1784
1785 radv_update_bound_fast_clear_ds(cmd_buffer, iview, ds_clear_value,
1786 aspects);
1787 }
1788
1789 /**
1790 * Load the clear depth/stencil values from the image's metadata.
1791 */
1792 static void
1793 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1794 const struct radv_image_view *iview)
1795 {
1796 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1797 const struct radv_image *image = iview->image;
1798 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1799 uint64_t va = radv_get_ds_clear_value_va(image, iview->base_mip);
1800 unsigned reg_offset = 0, reg_count = 0;
1801
1802 if (!radv_image_has_htile(image))
1803 return;
1804
1805 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1806 ++reg_count;
1807 } else {
1808 ++reg_offset;
1809 va += 4;
1810 }
1811 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1812 ++reg_count;
1813
1814 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1815
1816 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
1817 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1818 radeon_emit(cs, va);
1819 radeon_emit(cs, va >> 32);
1820 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1821 radeon_emit(cs, reg_count);
1822 } else {
1823 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1824 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1825 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1826 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1827 radeon_emit(cs, va);
1828 radeon_emit(cs, va >> 32);
1829 radeon_emit(cs, reg >> 2);
1830 radeon_emit(cs, 0);
1831
1832 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1833 radeon_emit(cs, 0);
1834 }
1835 }
1836
1837 /*
1838 * With DCC some colors don't require CMASK elimination before being
1839 * used as a texture. This sets a predicate value to determine if the
1840 * cmask eliminate is required.
1841 */
1842 void
1843 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1844 struct radv_image *image,
1845 const VkImageSubresourceRange *range, bool value)
1846 {
1847 uint64_t pred_val = value;
1848 uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
1849 uint32_t level_count = radv_get_levelCount(image, range);
1850 uint32_t count = 2 * level_count;
1851
1852 assert(radv_dcc_enabled(image, range->baseMipLevel));
1853
1854 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1855 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1856 S_370_WR_CONFIRM(1) |
1857 S_370_ENGINE_SEL(V_370_PFP));
1858 radeon_emit(cmd_buffer->cs, va);
1859 radeon_emit(cmd_buffer->cs, va >> 32);
1860
1861 for (uint32_t l = 0; l < level_count; l++) {
1862 radeon_emit(cmd_buffer->cs, pred_val);
1863 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1864 }
1865 }
1866
1867 /**
1868 * Update the DCC predicate to reflect the compression state.
1869 */
1870 void
1871 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1872 struct radv_image *image,
1873 const VkImageSubresourceRange *range, bool value)
1874 {
1875 uint64_t pred_val = value;
1876 uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
1877 uint32_t level_count = radv_get_levelCount(image, range);
1878 uint32_t count = 2 * level_count;
1879
1880 assert(radv_dcc_enabled(image, range->baseMipLevel));
1881
1882 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1883 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1884 S_370_WR_CONFIRM(1) |
1885 S_370_ENGINE_SEL(V_370_PFP));
1886 radeon_emit(cmd_buffer->cs, va);
1887 radeon_emit(cmd_buffer->cs, va >> 32);
1888
1889 for (uint32_t l = 0; l < level_count; l++) {
1890 radeon_emit(cmd_buffer->cs, pred_val);
1891 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1892 }
1893 }
1894
1895 /**
1896 * Update the fast clear color values if the image is bound as a color buffer.
1897 */
1898 static void
1899 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1900 struct radv_image *image,
1901 int cb_idx,
1902 uint32_t color_values[2])
1903 {
1904 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1905 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1906 uint32_t att_idx;
1907
1908 if (!cmd_buffer->state.attachments || !subpass)
1909 return;
1910
1911 att_idx = subpass->color_attachments[cb_idx].attachment;
1912 if (att_idx == VK_ATTACHMENT_UNUSED)
1913 return;
1914
1915 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1916 return;
1917
1918 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1919 radeon_emit(cs, color_values[0]);
1920 radeon_emit(cs, color_values[1]);
1921
1922 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1923 }
1924
1925 /**
1926 * Set the clear color values to the image's metadata.
1927 */
1928 static void
1929 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1930 struct radv_image *image,
1931 const VkImageSubresourceRange *range,
1932 uint32_t color_values[2])
1933 {
1934 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1935 uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
1936 uint32_t level_count = radv_get_levelCount(image, range);
1937 uint32_t count = 2 * level_count;
1938
1939 assert(radv_image_has_cmask(image) ||
1940 radv_dcc_enabled(image, range->baseMipLevel));
1941
1942 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
1943 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1944 S_370_WR_CONFIRM(1) |
1945 S_370_ENGINE_SEL(V_370_PFP));
1946 radeon_emit(cs, va);
1947 radeon_emit(cs, va >> 32);
1948
1949 for (uint32_t l = 0; l < level_count; l++) {
1950 radeon_emit(cs, color_values[0]);
1951 radeon_emit(cs, color_values[1]);
1952 }
1953 }
1954
1955 /**
1956 * Update the clear color values for this image.
1957 */
1958 void
1959 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1960 const struct radv_image_view *iview,
1961 int cb_idx,
1962 uint32_t color_values[2])
1963 {
1964 struct radv_image *image = iview->image;
1965 VkImageSubresourceRange range = {
1966 .aspectMask = iview->aspect_mask,
1967 .baseMipLevel = iview->base_mip,
1968 .levelCount = iview->level_count,
1969 .baseArrayLayer = iview->base_layer,
1970 .layerCount = iview->layer_count,
1971 };
1972
1973 assert(radv_image_has_cmask(image) ||
1974 radv_dcc_enabled(image, iview->base_mip));
1975
1976 radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
1977
1978 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1979 color_values);
1980 }
1981
1982 /**
1983 * Load the clear color values from the image's metadata.
1984 */
1985 static void
1986 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1987 struct radv_image_view *iview,
1988 int cb_idx)
1989 {
1990 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1991 struct radv_image *image = iview->image;
1992 uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
1993
1994 if (!radv_image_has_cmask(image) &&
1995 !radv_dcc_enabled(image, iview->base_mip))
1996 return;
1997
1998 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1999
2000 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
2001 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
2002 radeon_emit(cs, va);
2003 radeon_emit(cs, va >> 32);
2004 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
2005 radeon_emit(cs, 2);
2006 } else {
2007 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
2008 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2009 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2010 COPY_DATA_COUNT_SEL);
2011 radeon_emit(cs, va);
2012 radeon_emit(cs, va >> 32);
2013 radeon_emit(cs, reg >> 2);
2014 radeon_emit(cs, 0);
2015
2016 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
2017 radeon_emit(cs, 0);
2018 }
2019 }
2020
2021 static void
2022 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
2023 {
2024 int i;
2025 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
2026 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2027
2028 /* this may happen for inherited secondary recording */
2029 if (!framebuffer)
2030 return;
2031
2032 for (i = 0; i < 8; ++i) {
2033 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
2034 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2035 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2036 continue;
2037 }
2038
2039 int idx = subpass->color_attachments[i].attachment;
2040 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
2041 VkImageLayout layout = subpass->color_attachments[i].layout;
2042 bool in_render_loop = subpass->color_attachments[i].in_render_loop;
2043
2044 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, iview->bo);
2045
2046 assert(iview->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
2047 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
2048 radv_emit_fb_color_state(cmd_buffer, i, &cmd_buffer->state.attachments[idx].cb, iview, layout, in_render_loop);
2049
2050 radv_load_color_clear_metadata(cmd_buffer, iview, i);
2051 }
2052
2053 if (subpass->depth_stencil_attachment) {
2054 int idx = subpass->depth_stencil_attachment->attachment;
2055 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
2056 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
2057 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
2058 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, cmd_buffer->state.attachments[idx].iview->bo);
2059
2060 radv_emit_fb_ds_state(cmd_buffer, &cmd_buffer->state.attachments[idx].ds, iview, layout, in_render_loop);
2061
2062 if (cmd_buffer->state.attachments[idx].ds.offset_scale != cmd_buffer->state.offset_scale) {
2063 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2064 cmd_buffer->state.offset_scale = cmd_buffer->state.attachments[idx].ds.offset_scale;
2065 }
2066 radv_load_ds_clear_metadata(cmd_buffer, iview);
2067 } else {
2068 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9)
2069 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
2070 else
2071 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
2072
2073 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
2074 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
2075 }
2076 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2077 S_028208_BR_X(framebuffer->width) |
2078 S_028208_BR_Y(framebuffer->height));
2079
2080 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
2081 bool disable_constant_encode =
2082 cmd_buffer->device->physical_device->rad_info.has_dcc_constant_encode;
2083 enum chip_class chip_class =
2084 cmd_buffer->device->physical_device->rad_info.chip_class;
2085 uint8_t watermark = chip_class >= GFX10 ? 6 : 4;
2086
2087 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
2088 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class <= GFX9) |
2089 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
2090 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
2091 }
2092
2093 if (cmd_buffer->device->dfsm_allowed) {
2094 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2095 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
2096 }
2097
2098 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
2099 }
2100
2101 static void
2102 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer, bool indirect)
2103 {
2104 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2105 struct radv_cmd_state *state = &cmd_buffer->state;
2106
2107 if (state->index_type != state->last_index_type) {
2108 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2109 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2110 cs, R_03090C_VGT_INDEX_TYPE,
2111 2, state->index_type);
2112 } else {
2113 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2114 radeon_emit(cs, state->index_type);
2115 }
2116
2117 state->last_index_type = state->index_type;
2118 }
2119
2120 /* For the direct indexed draws we use DRAW_INDEX_2, which includes
2121 * the index_va and max_index_count already. */
2122 if (!indirect)
2123 return;
2124
2125 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2126 radeon_emit(cs, state->index_va);
2127 radeon_emit(cs, state->index_va >> 32);
2128
2129 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2130 radeon_emit(cs, state->max_index_count);
2131
2132 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
2133 }
2134
2135 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
2136 {
2137 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
2138 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2139 uint32_t pa_sc_mode_cntl_1 =
2140 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
2141 uint32_t db_count_control;
2142
2143 if(!cmd_buffer->state.active_occlusion_queries) {
2144 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2145 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2146 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2147 has_perfect_queries) {
2148 /* Re-enable out-of-order rasterization if the
2149 * bound pipeline supports it and if it's has
2150 * been disabled before starting any perfect
2151 * occlusion queries.
2152 */
2153 radeon_set_context_reg(cmd_buffer->cs,
2154 R_028A4C_PA_SC_MODE_CNTL_1,
2155 pa_sc_mode_cntl_1);
2156 }
2157 }
2158 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
2159 } else {
2160 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2161 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
2162 bool gfx10_perfect = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10 && has_perfect_queries;
2163
2164 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2165 db_count_control =
2166 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
2167 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
2168 S_028004_SAMPLE_RATE(sample_rate) |
2169 S_028004_ZPASS_ENABLE(1) |
2170 S_028004_SLICE_EVEN_ENABLE(1) |
2171 S_028004_SLICE_ODD_ENABLE(1);
2172
2173 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2174 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2175 has_perfect_queries) {
2176 /* If the bound pipeline has enabled
2177 * out-of-order rasterization, we should
2178 * disable it before starting any perfect
2179 * occlusion queries.
2180 */
2181 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
2182
2183 radeon_set_context_reg(cmd_buffer->cs,
2184 R_028A4C_PA_SC_MODE_CNTL_1,
2185 pa_sc_mode_cntl_1);
2186 }
2187 } else {
2188 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
2189 S_028004_SAMPLE_RATE(sample_rate);
2190 }
2191 }
2192
2193 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
2194
2195 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2196 }
2197
2198 static void
2199 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
2200 {
2201 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
2202
2203 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
2204 radv_emit_viewport(cmd_buffer);
2205
2206 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
2207 !cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
2208 radv_emit_scissor(cmd_buffer);
2209
2210 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
2211 radv_emit_line_width(cmd_buffer);
2212
2213 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
2214 radv_emit_blend_constants(cmd_buffer);
2215
2216 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
2217 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
2218 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
2219 radv_emit_stencil(cmd_buffer);
2220
2221 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
2222 radv_emit_depth_bounds(cmd_buffer);
2223
2224 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
2225 radv_emit_depth_bias(cmd_buffer);
2226
2227 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
2228 radv_emit_discard_rectangle(cmd_buffer);
2229
2230 if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)
2231 radv_emit_sample_locations(cmd_buffer);
2232
2233 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE)
2234 radv_emit_line_stipple(cmd_buffer);
2235
2236 cmd_buffer->state.dirty &= ~states;
2237 }
2238
2239 static void
2240 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
2241 VkPipelineBindPoint bind_point)
2242 {
2243 struct radv_descriptor_state *descriptors_state =
2244 radv_get_descriptors_state(cmd_buffer, bind_point);
2245 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
2246 unsigned bo_offset;
2247
2248 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
2249 set->mapped_ptr,
2250 &bo_offset))
2251 return;
2252
2253 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2254 set->va += bo_offset;
2255 }
2256
2257 static void
2258 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
2259 VkPipelineBindPoint bind_point)
2260 {
2261 struct radv_descriptor_state *descriptors_state =
2262 radv_get_descriptors_state(cmd_buffer, bind_point);
2263 uint32_t size = MAX_SETS * 4;
2264 uint32_t offset;
2265 void *ptr;
2266
2267 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
2268 256, &offset, &ptr))
2269 return;
2270
2271 for (unsigned i = 0; i < MAX_SETS; i++) {
2272 uint32_t *uptr = ((uint32_t *)ptr) + i;
2273 uint64_t set_va = 0;
2274 struct radv_descriptor_set *set = descriptors_state->sets[i];
2275 if (descriptors_state->valid & (1u << i))
2276 set_va = set->va;
2277 uptr[0] = set_va & 0xffffffff;
2278 }
2279
2280 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2281 va += offset;
2282
2283 if (cmd_buffer->state.pipeline) {
2284 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
2285 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2286 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2287
2288 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
2289 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
2290 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2291
2292 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
2293 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2294 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2295
2296 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2297 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
2298 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2299
2300 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2301 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
2302 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2303 }
2304
2305 if (cmd_buffer->state.compute_pipeline)
2306 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
2307 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2308 }
2309
2310 static void
2311 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
2312 VkShaderStageFlags stages)
2313 {
2314 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2315 VK_PIPELINE_BIND_POINT_COMPUTE :
2316 VK_PIPELINE_BIND_POINT_GRAPHICS;
2317 struct radv_descriptor_state *descriptors_state =
2318 radv_get_descriptors_state(cmd_buffer, bind_point);
2319 struct radv_cmd_state *state = &cmd_buffer->state;
2320 bool flush_indirect_descriptors;
2321
2322 if (!descriptors_state->dirty)
2323 return;
2324
2325 if (descriptors_state->push_dirty)
2326 radv_flush_push_descriptors(cmd_buffer, bind_point);
2327
2328 flush_indirect_descriptors =
2329 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
2330 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
2331 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
2332 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
2333
2334 if (flush_indirect_descriptors)
2335 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
2336
2337 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2338 cmd_buffer->cs,
2339 MAX_SETS * MESA_SHADER_STAGES * 4);
2340
2341 if (cmd_buffer->state.pipeline) {
2342 radv_foreach_stage(stage, stages) {
2343 if (!cmd_buffer->state.pipeline->shaders[stage])
2344 continue;
2345
2346 radv_emit_descriptor_pointers(cmd_buffer,
2347 cmd_buffer->state.pipeline,
2348 descriptors_state, stage);
2349 }
2350 }
2351
2352 if (cmd_buffer->state.compute_pipeline &&
2353 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
2354 radv_emit_descriptor_pointers(cmd_buffer,
2355 cmd_buffer->state.compute_pipeline,
2356 descriptors_state,
2357 MESA_SHADER_COMPUTE);
2358 }
2359
2360 descriptors_state->dirty = 0;
2361 descriptors_state->push_dirty = false;
2362
2363 assert(cmd_buffer->cs->cdw <= cdw_max);
2364
2365 if (unlikely(cmd_buffer->device->trace_bo))
2366 radv_save_descriptors(cmd_buffer, bind_point);
2367 }
2368
2369 static void
2370 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
2371 VkShaderStageFlags stages)
2372 {
2373 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
2374 ? cmd_buffer->state.compute_pipeline
2375 : cmd_buffer->state.pipeline;
2376 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2377 VK_PIPELINE_BIND_POINT_COMPUTE :
2378 VK_PIPELINE_BIND_POINT_GRAPHICS;
2379 struct radv_descriptor_state *descriptors_state =
2380 radv_get_descriptors_state(cmd_buffer, bind_point);
2381 struct radv_pipeline_layout *layout = pipeline->layout;
2382 struct radv_shader_variant *shader, *prev_shader;
2383 bool need_push_constants = false;
2384 unsigned offset;
2385 void *ptr;
2386 uint64_t va;
2387
2388 stages &= cmd_buffer->push_constant_stages;
2389 if (!stages ||
2390 (!layout->push_constant_size && !layout->dynamic_offset_count))
2391 return;
2392
2393 radv_foreach_stage(stage, stages) {
2394 shader = radv_get_shader(pipeline, stage);
2395 if (!shader)
2396 continue;
2397
2398 need_push_constants |= shader->info.loads_push_constants;
2399 need_push_constants |= shader->info.loads_dynamic_offsets;
2400
2401 uint8_t base = shader->info.base_inline_push_consts;
2402 uint8_t count = shader->info.num_inline_push_consts;
2403
2404 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
2405 AC_UD_INLINE_PUSH_CONSTANTS,
2406 count,
2407 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
2408 }
2409
2410 if (need_push_constants) {
2411 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
2412 16 * layout->dynamic_offset_count,
2413 256, &offset, &ptr))
2414 return;
2415
2416 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
2417 memcpy((char*)ptr + layout->push_constant_size,
2418 descriptors_state->dynamic_buffers,
2419 16 * layout->dynamic_offset_count);
2420
2421 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2422 va += offset;
2423
2424 ASSERTED unsigned cdw_max =
2425 radeon_check_space(cmd_buffer->device->ws,
2426 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
2427
2428 prev_shader = NULL;
2429 radv_foreach_stage(stage, stages) {
2430 shader = radv_get_shader(pipeline, stage);
2431
2432 /* Avoid redundantly emitting the address for merged stages. */
2433 if (shader && shader != prev_shader) {
2434 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
2435 AC_UD_PUSH_CONSTANTS, va);
2436
2437 prev_shader = shader;
2438 }
2439 }
2440 assert(cmd_buffer->cs->cdw <= cdw_max);
2441 }
2442
2443 cmd_buffer->push_constant_stages &= ~stages;
2444 }
2445
2446 static void
2447 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
2448 bool pipeline_is_dirty)
2449 {
2450 if ((pipeline_is_dirty ||
2451 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
2452 cmd_buffer->state.pipeline->num_vertex_bindings &&
2453 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.has_vertex_buffers) {
2454 unsigned vb_offset;
2455 void *vb_ptr;
2456 uint32_t i = 0;
2457 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
2458 uint64_t va;
2459
2460 /* allocate some descriptor state for vertex buffers */
2461 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2462 &vb_offset, &vb_ptr))
2463 return;
2464
2465 for (i = 0; i < count; i++) {
2466 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2467 uint32_t offset;
2468 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2469 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[i];
2470 unsigned num_records;
2471
2472 if (!buffer)
2473 continue;
2474
2475 va = radv_buffer_get_va(buffer->bo);
2476
2477 offset = cmd_buffer->vertex_bindings[i].offset;
2478 va += offset + buffer->offset;
2479
2480 num_records = buffer->size - offset;
2481 if (cmd_buffer->device->physical_device->rad_info.chip_class != GFX8 && stride)
2482 num_records /= stride;
2483
2484 desc[0] = va;
2485 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2486 desc[2] = num_records;
2487 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2488 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2489 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2490 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2491
2492 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2493 /* OOB_SELECT chooses the out-of-bounds check:
2494 * - 1: index >= NUM_RECORDS (Structured)
2495 * - 3: offset >= NUM_RECORDS (Raw)
2496 */
2497 int oob_select = stride ? V_008F0C_OOB_SELECT_STRUCTURED : V_008F0C_OOB_SELECT_RAW;
2498
2499 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT) |
2500 S_008F0C_OOB_SELECT(oob_select) |
2501 S_008F0C_RESOURCE_LEVEL(1);
2502 } else {
2503 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2504 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2505 }
2506 }
2507
2508 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2509 va += vb_offset;
2510
2511 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2512 AC_UD_VS_VERTEX_BUFFERS, va);
2513
2514 cmd_buffer->state.vb_va = va;
2515 cmd_buffer->state.vb_size = count * 16;
2516 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2517 }
2518 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2519 }
2520
2521 static void
2522 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2523 {
2524 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2525 struct radv_userdata_info *loc;
2526 uint32_t base_reg;
2527
2528 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2529 if (!radv_get_shader(pipeline, stage))
2530 continue;
2531
2532 loc = radv_lookup_user_sgpr(pipeline, stage,
2533 AC_UD_STREAMOUT_BUFFERS);
2534 if (loc->sgpr_idx == -1)
2535 continue;
2536
2537 base_reg = pipeline->user_data_0[stage];
2538
2539 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2540 base_reg + loc->sgpr_idx * 4, va, false);
2541 }
2542
2543 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
2544 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2545 if (loc->sgpr_idx != -1) {
2546 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2547
2548 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2549 base_reg + loc->sgpr_idx * 4, va, false);
2550 }
2551 }
2552 }
2553
2554 static void
2555 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2556 {
2557 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2558 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2559 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2560 unsigned so_offset;
2561 void *so_ptr;
2562 uint64_t va;
2563
2564 /* Allocate some descriptor state for streamout buffers. */
2565 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2566 MAX_SO_BUFFERS * 16, 256,
2567 &so_offset, &so_ptr))
2568 return;
2569
2570 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2571 struct radv_buffer *buffer = sb[i].buffer;
2572 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2573
2574 if (!(so->enabled_mask & (1 << i)))
2575 continue;
2576
2577 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2578
2579 va += sb[i].offset;
2580
2581 /* Set the descriptor.
2582 *
2583 * On GFX8, the format must be non-INVALID, otherwise
2584 * the buffer will be considered not bound and store
2585 * instructions will be no-ops.
2586 */
2587 uint32_t size = 0xffffffff;
2588
2589 /* Compute the correct buffer size for NGG streamout
2590 * because it's used to determine the max emit per
2591 * buffer.
2592 */
2593 if (cmd_buffer->device->physical_device->use_ngg_streamout)
2594 size = buffer->size - sb[i].offset;
2595
2596 desc[0] = va;
2597 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2598 desc[2] = size;
2599 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2600 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2601 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2602 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2603
2604 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2605 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2606 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
2607 S_008F0C_RESOURCE_LEVEL(1);
2608 } else {
2609 desc[3] |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2610 }
2611 }
2612
2613 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2614 va += so_offset;
2615
2616 radv_emit_streamout_buffers(cmd_buffer, va);
2617 }
2618
2619 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2620 }
2621
2622 static void
2623 radv_flush_ngg_gs_state(struct radv_cmd_buffer *cmd_buffer)
2624 {
2625 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2626 struct radv_userdata_info *loc;
2627 uint32_t ngg_gs_state = 0;
2628 uint32_t base_reg;
2629
2630 if (!radv_pipeline_has_gs(pipeline) ||
2631 !radv_pipeline_has_ngg(pipeline))
2632 return;
2633
2634 /* By default NGG GS queries are disabled but they are enabled if the
2635 * command buffer has active GDS queries or if it's a secondary command
2636 * buffer that inherits the number of generated primitives.
2637 */
2638 if (cmd_buffer->state.active_pipeline_gds_queries ||
2639 (cmd_buffer->state.inherited_pipeline_statistics & VK_QUERY_PIPELINE_STATISTIC_GEOMETRY_SHADER_PRIMITIVES_BIT))
2640 ngg_gs_state = 1;
2641
2642 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_GEOMETRY,
2643 AC_UD_NGG_GS_STATE);
2644 base_reg = pipeline->user_data_0[MESA_SHADER_GEOMETRY];
2645 assert(loc->sgpr_idx != -1);
2646
2647 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
2648 ngg_gs_state);
2649 }
2650
2651 static void
2652 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2653 {
2654 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2655 radv_flush_streamout_descriptors(cmd_buffer);
2656 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2657 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2658 radv_flush_ngg_gs_state(cmd_buffer);
2659 }
2660
2661 struct radv_draw_info {
2662 /**
2663 * Number of vertices.
2664 */
2665 uint32_t count;
2666
2667 /**
2668 * Index of the first vertex.
2669 */
2670 int32_t vertex_offset;
2671
2672 /**
2673 * First instance id.
2674 */
2675 uint32_t first_instance;
2676
2677 /**
2678 * Number of instances.
2679 */
2680 uint32_t instance_count;
2681
2682 /**
2683 * First index (indexed draws only).
2684 */
2685 uint32_t first_index;
2686
2687 /**
2688 * Whether it's an indexed draw.
2689 */
2690 bool indexed;
2691
2692 /**
2693 * Indirect draw parameters resource.
2694 */
2695 struct radv_buffer *indirect;
2696 uint64_t indirect_offset;
2697 uint32_t stride;
2698
2699 /**
2700 * Draw count parameters resource.
2701 */
2702 struct radv_buffer *count_buffer;
2703 uint64_t count_buffer_offset;
2704
2705 /**
2706 * Stream output parameters resource.
2707 */
2708 struct radv_buffer *strmout_buffer;
2709 uint64_t strmout_buffer_offset;
2710 };
2711
2712 static uint32_t
2713 radv_get_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
2714 {
2715 switch (cmd_buffer->state.index_type) {
2716 case V_028A7C_VGT_INDEX_8:
2717 return 0xffu;
2718 case V_028A7C_VGT_INDEX_16:
2719 return 0xffffu;
2720 case V_028A7C_VGT_INDEX_32:
2721 return 0xffffffffu;
2722 default:
2723 unreachable("invalid index type");
2724 }
2725 }
2726
2727 static void
2728 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
2729 bool instanced_draw, bool indirect_draw,
2730 bool count_from_stream_output,
2731 uint32_t draw_vertex_count)
2732 {
2733 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2734 struct radv_cmd_state *state = &cmd_buffer->state;
2735 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2736 unsigned ia_multi_vgt_param;
2737
2738 ia_multi_vgt_param =
2739 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
2740 indirect_draw,
2741 count_from_stream_output,
2742 draw_vertex_count);
2743
2744 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2745 if (info->chip_class == GFX9) {
2746 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2747 cs,
2748 R_030960_IA_MULTI_VGT_PARAM,
2749 4, ia_multi_vgt_param);
2750 } else if (info->chip_class >= GFX7) {
2751 radeon_set_context_reg_idx(cs,
2752 R_028AA8_IA_MULTI_VGT_PARAM,
2753 1, ia_multi_vgt_param);
2754 } else {
2755 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2756 ia_multi_vgt_param);
2757 }
2758 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2759 }
2760 }
2761
2762 static void
2763 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2764 const struct radv_draw_info *draw_info)
2765 {
2766 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2767 struct radv_cmd_state *state = &cmd_buffer->state;
2768 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2769 int32_t primitive_reset_en;
2770
2771 /* Draw state. */
2772 if (info->chip_class < GFX10) {
2773 si_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2774 draw_info->indirect,
2775 !!draw_info->strmout_buffer,
2776 draw_info->indirect ? 0 : draw_info->count);
2777 }
2778
2779 /* Primitive restart. */
2780 primitive_reset_en =
2781 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2782
2783 if (primitive_reset_en != state->last_primitive_reset_en) {
2784 state->last_primitive_reset_en = primitive_reset_en;
2785 if (info->chip_class >= GFX9) {
2786 radeon_set_uconfig_reg(cs,
2787 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2788 primitive_reset_en);
2789 } else {
2790 radeon_set_context_reg(cs,
2791 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2792 primitive_reset_en);
2793 }
2794 }
2795
2796 if (primitive_reset_en) {
2797 uint32_t primitive_reset_index =
2798 radv_get_primitive_reset_index(cmd_buffer);
2799
2800 if (primitive_reset_index != state->last_primitive_reset_index) {
2801 radeon_set_context_reg(cs,
2802 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2803 primitive_reset_index);
2804 state->last_primitive_reset_index = primitive_reset_index;
2805 }
2806 }
2807
2808 if (draw_info->strmout_buffer) {
2809 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2810
2811 va += draw_info->strmout_buffer->offset +
2812 draw_info->strmout_buffer_offset;
2813
2814 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2815 draw_info->stride);
2816
2817 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2818 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2819 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2820 COPY_DATA_WR_CONFIRM);
2821 radeon_emit(cs, va);
2822 radeon_emit(cs, va >> 32);
2823 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2824 radeon_emit(cs, 0); /* unused */
2825
2826 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2827 }
2828 }
2829
2830 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2831 VkPipelineStageFlags src_stage_mask)
2832 {
2833 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2834 VK_PIPELINE_STAGE_TRANSFER_BIT |
2835 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2836 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2837 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2838 }
2839
2840 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2841 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2842 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2843 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2844 VK_PIPELINE_STAGE_TRANSFER_BIT |
2845 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2846 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2847 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2848 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2849 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2850 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2851 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2852 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2853 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2854 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2855 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2856 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2857 }
2858 }
2859
2860 static enum radv_cmd_flush_bits
2861 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2862 VkAccessFlags src_flags,
2863 struct radv_image *image)
2864 {
2865 bool flush_CB_meta = true, flush_DB_meta = true;
2866 enum radv_cmd_flush_bits flush_bits = 0;
2867 uint32_t b;
2868
2869 if (image) {
2870 if (!radv_image_has_CB_metadata(image))
2871 flush_CB_meta = false;
2872 if (!radv_image_has_htile(image))
2873 flush_DB_meta = false;
2874 }
2875
2876 for_each_bit(b, src_flags) {
2877 switch ((VkAccessFlagBits)(1 << b)) {
2878 case VK_ACCESS_SHADER_WRITE_BIT:
2879 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2880 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2881 flush_bits |= RADV_CMD_FLAG_WB_L2;
2882 break;
2883 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2884 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2885 if (flush_CB_meta)
2886 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2887 break;
2888 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2889 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2890 if (flush_DB_meta)
2891 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2892 break;
2893 case VK_ACCESS_TRANSFER_WRITE_BIT:
2894 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2895 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2896 RADV_CMD_FLAG_INV_L2;
2897
2898 if (flush_CB_meta)
2899 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2900 if (flush_DB_meta)
2901 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2902 break;
2903 default:
2904 break;
2905 }
2906 }
2907 return flush_bits;
2908 }
2909
2910 static enum radv_cmd_flush_bits
2911 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2912 VkAccessFlags dst_flags,
2913 struct radv_image *image)
2914 {
2915 bool flush_CB_meta = true, flush_DB_meta = true;
2916 enum radv_cmd_flush_bits flush_bits = 0;
2917 bool flush_CB = true, flush_DB = true;
2918 bool image_is_coherent = false;
2919 uint32_t b;
2920
2921 if (image) {
2922 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2923 flush_CB = false;
2924 flush_DB = false;
2925 }
2926
2927 if (!radv_image_has_CB_metadata(image))
2928 flush_CB_meta = false;
2929 if (!radv_image_has_htile(image))
2930 flush_DB_meta = false;
2931
2932 /* TODO: implement shader coherent for GFX10 */
2933
2934 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
2935 if (image->info.samples == 1 &&
2936 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2937 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2938 !vk_format_is_stencil(image->vk_format)) {
2939 /* Single-sample color and single-sample depth
2940 * (not stencil) are coherent with shaders on
2941 * GFX9.
2942 */
2943 image_is_coherent = true;
2944 }
2945 }
2946 }
2947
2948 for_each_bit(b, dst_flags) {
2949 switch ((VkAccessFlagBits)(1 << b)) {
2950 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2951 case VK_ACCESS_INDEX_READ_BIT:
2952 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2953 break;
2954 case VK_ACCESS_UNIFORM_READ_BIT:
2955 flush_bits |= RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_SCACHE;
2956 break;
2957 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2958 case VK_ACCESS_TRANSFER_READ_BIT:
2959 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2960 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
2961 RADV_CMD_FLAG_INV_L2;
2962 break;
2963 case VK_ACCESS_SHADER_READ_BIT:
2964 flush_bits |= RADV_CMD_FLAG_INV_VCACHE;
2965 /* Unlike LLVM, ACO uses SMEM for SSBOs and we have to
2966 * invalidate the scalar cache. */
2967 if (cmd_buffer->device->physical_device->use_aco &&
2968 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8)
2969 flush_bits |= RADV_CMD_FLAG_INV_SCACHE;
2970
2971 if (!image_is_coherent)
2972 flush_bits |= RADV_CMD_FLAG_INV_L2;
2973 break;
2974 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2975 if (flush_CB)
2976 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2977 if (flush_CB_meta)
2978 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2979 break;
2980 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2981 if (flush_DB)
2982 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2983 if (flush_DB_meta)
2984 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2985 break;
2986 default:
2987 break;
2988 }
2989 }
2990 return flush_bits;
2991 }
2992
2993 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2994 const struct radv_subpass_barrier *barrier)
2995 {
2996 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2997 NULL);
2998 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2999 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
3000 NULL);
3001 }
3002
3003 uint32_t
3004 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
3005 {
3006 struct radv_cmd_state *state = &cmd_buffer->state;
3007 uint32_t subpass_id = state->subpass - state->pass->subpasses;
3008
3009 /* The id of this subpass shouldn't exceed the number of subpasses in
3010 * this render pass minus 1.
3011 */
3012 assert(subpass_id < state->pass->subpass_count);
3013 return subpass_id;
3014 }
3015
3016 static struct radv_sample_locations_state *
3017 radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer,
3018 uint32_t att_idx,
3019 bool begin_subpass)
3020 {
3021 struct radv_cmd_state *state = &cmd_buffer->state;
3022 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
3023 struct radv_image_view *view = state->attachments[att_idx].iview;
3024
3025 if (view->image->info.samples == 1)
3026 return NULL;
3027
3028 if (state->pass->attachments[att_idx].first_subpass_idx == subpass_id) {
3029 /* Return the initial sample locations if this is the initial
3030 * layout transition of the given subpass attachemnt.
3031 */
3032 if (state->attachments[att_idx].sample_location.count > 0)
3033 return &state->attachments[att_idx].sample_location;
3034 } else {
3035 /* Otherwise return the subpass sample locations if defined. */
3036 if (state->subpass_sample_locs) {
3037 /* Because the driver sets the current subpass before
3038 * initial layout transitions, we should use the sample
3039 * locations from the previous subpass to avoid an
3040 * off-by-one problem. Otherwise, use the sample
3041 * locations for the current subpass for final layout
3042 * transitions.
3043 */
3044 if (begin_subpass)
3045 subpass_id--;
3046
3047 for (uint32_t i = 0; i < state->num_subpass_sample_locs; i++) {
3048 if (state->subpass_sample_locs[i].subpass_idx == subpass_id)
3049 return &state->subpass_sample_locs[i].sample_location;
3050 }
3051 }
3052 }
3053
3054 return NULL;
3055 }
3056
3057 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
3058 struct radv_subpass_attachment att,
3059 bool begin_subpass)
3060 {
3061 unsigned idx = att.attachment;
3062 struct radv_image_view *view = cmd_buffer->state.attachments[idx].iview;
3063 struct radv_sample_locations_state *sample_locs;
3064 VkImageSubresourceRange range;
3065 range.aspectMask = view->aspect_mask;
3066 range.baseMipLevel = view->base_mip;
3067 range.levelCount = 1;
3068 range.baseArrayLayer = view->base_layer;
3069 range.layerCount = cmd_buffer->state.framebuffer->layers;
3070
3071 if (cmd_buffer->state.subpass->view_mask) {
3072 /* If the current subpass uses multiview, the driver might have
3073 * performed a fast color/depth clear to the whole image
3074 * (including all layers). To make sure the driver will
3075 * decompress the image correctly (if needed), we have to
3076 * account for the "real" number of layers. If the view mask is
3077 * sparse, this will decompress more layers than needed.
3078 */
3079 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
3080 }
3081
3082 /* Get the subpass sample locations for the given attachment, if NULL
3083 * is returned the driver will use the default HW locations.
3084 */
3085 sample_locs = radv_get_attachment_sample_locations(cmd_buffer, idx,
3086 begin_subpass);
3087
3088 /* Determine if the subpass uses separate depth/stencil layouts. */
3089 bool uses_separate_depth_stencil_layouts = false;
3090 if ((cmd_buffer->state.attachments[idx].current_layout !=
3091 cmd_buffer->state.attachments[idx].current_stencil_layout) ||
3092 (att.layout != att.stencil_layout)) {
3093 uses_separate_depth_stencil_layouts = true;
3094 }
3095
3096 /* For separate layouts, perform depth and stencil transitions
3097 * separately.
3098 */
3099 if (uses_separate_depth_stencil_layouts &&
3100 (range.aspectMask == (VK_IMAGE_ASPECT_DEPTH_BIT |
3101 VK_IMAGE_ASPECT_STENCIL_BIT))) {
3102 /* Depth-only transitions. */
3103 range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3104 radv_handle_image_transition(cmd_buffer,
3105 view->image,
3106 cmd_buffer->state.attachments[idx].current_layout,
3107 cmd_buffer->state.attachments[idx].current_in_render_loop,
3108 att.layout, att.in_render_loop,
3109 0, 0, &range, sample_locs);
3110
3111 /* Stencil-only transitions. */
3112 range.aspectMask = VK_IMAGE_ASPECT_STENCIL_BIT;
3113 radv_handle_image_transition(cmd_buffer,
3114 view->image,
3115 cmd_buffer->state.attachments[idx].current_stencil_layout,
3116 cmd_buffer->state.attachments[idx].current_in_render_loop,
3117 att.stencil_layout, att.in_render_loop,
3118 0, 0, &range, sample_locs);
3119 } else {
3120 radv_handle_image_transition(cmd_buffer,
3121 view->image,
3122 cmd_buffer->state.attachments[idx].current_layout,
3123 cmd_buffer->state.attachments[idx].current_in_render_loop,
3124 att.layout, att.in_render_loop,
3125 0, 0, &range, sample_locs);
3126 }
3127
3128 cmd_buffer->state.attachments[idx].current_layout = att.layout;
3129 cmd_buffer->state.attachments[idx].current_stencil_layout = att.stencil_layout;
3130 cmd_buffer->state.attachments[idx].current_in_render_loop = att.in_render_loop;
3131
3132
3133 }
3134
3135 void
3136 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
3137 const struct radv_subpass *subpass)
3138 {
3139 cmd_buffer->state.subpass = subpass;
3140
3141 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
3142 }
3143
3144 static VkResult
3145 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
3146 struct radv_render_pass *pass,
3147 const VkRenderPassBeginInfo *info)
3148 {
3149 const struct VkRenderPassSampleLocationsBeginInfoEXT *sample_locs =
3150 vk_find_struct_const(info->pNext,
3151 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT);
3152 struct radv_cmd_state *state = &cmd_buffer->state;
3153
3154 if (!sample_locs) {
3155 state->subpass_sample_locs = NULL;
3156 return VK_SUCCESS;
3157 }
3158
3159 for (uint32_t i = 0; i < sample_locs->attachmentInitialSampleLocationsCount; i++) {
3160 const VkAttachmentSampleLocationsEXT *att_sample_locs =
3161 &sample_locs->pAttachmentInitialSampleLocations[i];
3162 uint32_t att_idx = att_sample_locs->attachmentIndex;
3163 struct radv_image *image = cmd_buffer->state.attachments[att_idx].iview->image;
3164
3165 assert(vk_format_is_depth_or_stencil(image->vk_format));
3166
3167 /* From the Vulkan spec 1.1.108:
3168 *
3169 * "If the image referenced by the framebuffer attachment at
3170 * index attachmentIndex was not created with
3171 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
3172 * then the values specified in sampleLocationsInfo are
3173 * ignored."
3174 */
3175 if (!(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT))
3176 continue;
3177
3178 const VkSampleLocationsInfoEXT *sample_locs_info =
3179 &att_sample_locs->sampleLocationsInfo;
3180
3181 state->attachments[att_idx].sample_location.per_pixel =
3182 sample_locs_info->sampleLocationsPerPixel;
3183 state->attachments[att_idx].sample_location.grid_size =
3184 sample_locs_info->sampleLocationGridSize;
3185 state->attachments[att_idx].sample_location.count =
3186 sample_locs_info->sampleLocationsCount;
3187 typed_memcpy(&state->attachments[att_idx].sample_location.locations[0],
3188 sample_locs_info->pSampleLocations,
3189 sample_locs_info->sampleLocationsCount);
3190 }
3191
3192 state->subpass_sample_locs = vk_alloc(&cmd_buffer->pool->alloc,
3193 sample_locs->postSubpassSampleLocationsCount *
3194 sizeof(state->subpass_sample_locs[0]),
3195 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3196 if (state->subpass_sample_locs == NULL) {
3197 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3198 return cmd_buffer->record_result;
3199 }
3200
3201 state->num_subpass_sample_locs = sample_locs->postSubpassSampleLocationsCount;
3202
3203 for (uint32_t i = 0; i < sample_locs->postSubpassSampleLocationsCount; i++) {
3204 const VkSubpassSampleLocationsEXT *subpass_sample_locs_info =
3205 &sample_locs->pPostSubpassSampleLocations[i];
3206 const VkSampleLocationsInfoEXT *sample_locs_info =
3207 &subpass_sample_locs_info->sampleLocationsInfo;
3208
3209 state->subpass_sample_locs[i].subpass_idx =
3210 subpass_sample_locs_info->subpassIndex;
3211 state->subpass_sample_locs[i].sample_location.per_pixel =
3212 sample_locs_info->sampleLocationsPerPixel;
3213 state->subpass_sample_locs[i].sample_location.grid_size =
3214 sample_locs_info->sampleLocationGridSize;
3215 state->subpass_sample_locs[i].sample_location.count =
3216 sample_locs_info->sampleLocationsCount;
3217 typed_memcpy(&state->subpass_sample_locs[i].sample_location.locations[0],
3218 sample_locs_info->pSampleLocations,
3219 sample_locs_info->sampleLocationsCount);
3220 }
3221
3222 return VK_SUCCESS;
3223 }
3224
3225 static VkResult
3226 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
3227 struct radv_render_pass *pass,
3228 const VkRenderPassBeginInfo *info)
3229 {
3230 struct radv_cmd_state *state = &cmd_buffer->state;
3231 const struct VkRenderPassAttachmentBeginInfo *attachment_info = NULL;
3232
3233 if (info) {
3234 attachment_info = vk_find_struct_const(info->pNext,
3235 RENDER_PASS_ATTACHMENT_BEGIN_INFO);
3236 }
3237
3238
3239 if (pass->attachment_count == 0) {
3240 state->attachments = NULL;
3241 return VK_SUCCESS;
3242 }
3243
3244 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
3245 pass->attachment_count *
3246 sizeof(state->attachments[0]),
3247 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3248 if (state->attachments == NULL) {
3249 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3250 return cmd_buffer->record_result;
3251 }
3252
3253 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
3254 struct radv_render_pass_attachment *att = &pass->attachments[i];
3255 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
3256 VkImageAspectFlags clear_aspects = 0;
3257
3258 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
3259 /* color attachment */
3260 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3261 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
3262 }
3263 } else {
3264 /* depthstencil attachment */
3265 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
3266 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3267 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
3268 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3269 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
3270 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3271 }
3272 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3273 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3274 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3275 }
3276 }
3277
3278 state->attachments[i].pending_clear_aspects = clear_aspects;
3279 state->attachments[i].cleared_views = 0;
3280 if (clear_aspects && info) {
3281 assert(info->clearValueCount > i);
3282 state->attachments[i].clear_value = info->pClearValues[i];
3283 }
3284
3285 state->attachments[i].current_layout = att->initial_layout;
3286 state->attachments[i].current_stencil_layout = att->stencil_initial_layout;
3287 state->attachments[i].sample_location.count = 0;
3288
3289 struct radv_image_view *iview;
3290 if (attachment_info && attachment_info->attachmentCount > i) {
3291 iview = radv_image_view_from_handle(attachment_info->pAttachments[i]);
3292 } else {
3293 iview = state->framebuffer->attachments[i];
3294 }
3295
3296 state->attachments[i].iview = iview;
3297 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3298 radv_initialise_ds_surface(cmd_buffer->device, &state->attachments[i].ds, iview);
3299 } else {
3300 radv_initialise_color_surface(cmd_buffer->device, &state->attachments[i].cb, iview);
3301 }
3302 }
3303
3304 return VK_SUCCESS;
3305 }
3306
3307 VkResult radv_AllocateCommandBuffers(
3308 VkDevice _device,
3309 const VkCommandBufferAllocateInfo *pAllocateInfo,
3310 VkCommandBuffer *pCommandBuffers)
3311 {
3312 RADV_FROM_HANDLE(radv_device, device, _device);
3313 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
3314
3315 VkResult result = VK_SUCCESS;
3316 uint32_t i;
3317
3318 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
3319
3320 if (!list_is_empty(&pool->free_cmd_buffers)) {
3321 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
3322
3323 list_del(&cmd_buffer->pool_link);
3324 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
3325
3326 result = radv_reset_cmd_buffer(cmd_buffer);
3327 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
3328 cmd_buffer->level = pAllocateInfo->level;
3329
3330 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
3331 } else {
3332 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
3333 &pCommandBuffers[i]);
3334 }
3335 if (result != VK_SUCCESS)
3336 break;
3337 }
3338
3339 if (result != VK_SUCCESS) {
3340 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
3341 i, pCommandBuffers);
3342
3343 /* From the Vulkan 1.0.66 spec:
3344 *
3345 * "vkAllocateCommandBuffers can be used to create multiple
3346 * command buffers. If the creation of any of those command
3347 * buffers fails, the implementation must destroy all
3348 * successfully created command buffer objects from this
3349 * command, set all entries of the pCommandBuffers array to
3350 * NULL and return the error."
3351 */
3352 memset(pCommandBuffers, 0,
3353 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
3354 }
3355
3356 return result;
3357 }
3358
3359 void radv_FreeCommandBuffers(
3360 VkDevice device,
3361 VkCommandPool commandPool,
3362 uint32_t commandBufferCount,
3363 const VkCommandBuffer *pCommandBuffers)
3364 {
3365 for (uint32_t i = 0; i < commandBufferCount; i++) {
3366 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
3367
3368 if (cmd_buffer) {
3369 if (cmd_buffer->pool) {
3370 list_del(&cmd_buffer->pool_link);
3371 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
3372 } else
3373 radv_cmd_buffer_destroy(cmd_buffer);
3374
3375 }
3376 }
3377 }
3378
3379 VkResult radv_ResetCommandBuffer(
3380 VkCommandBuffer commandBuffer,
3381 VkCommandBufferResetFlags flags)
3382 {
3383 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3384 return radv_reset_cmd_buffer(cmd_buffer);
3385 }
3386
3387 VkResult radv_BeginCommandBuffer(
3388 VkCommandBuffer commandBuffer,
3389 const VkCommandBufferBeginInfo *pBeginInfo)
3390 {
3391 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3392 VkResult result = VK_SUCCESS;
3393
3394 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
3395 /* If the command buffer has already been resetted with
3396 * vkResetCommandBuffer, no need to do it again.
3397 */
3398 result = radv_reset_cmd_buffer(cmd_buffer);
3399 if (result != VK_SUCCESS)
3400 return result;
3401 }
3402
3403 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
3404 cmd_buffer->state.last_primitive_reset_en = -1;
3405 cmd_buffer->state.last_index_type = -1;
3406 cmd_buffer->state.last_num_instances = -1;
3407 cmd_buffer->state.last_vertex_offset = -1;
3408 cmd_buffer->state.last_first_instance = -1;
3409 cmd_buffer->state.predication_type = -1;
3410 cmd_buffer->state.last_sx_ps_downconvert = -1;
3411 cmd_buffer->state.last_sx_blend_opt_epsilon = -1;
3412 cmd_buffer->state.last_sx_blend_opt_control = -1;
3413 cmd_buffer->usage_flags = pBeginInfo->flags;
3414
3415 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
3416 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
3417 assert(pBeginInfo->pInheritanceInfo);
3418 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
3419 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
3420
3421 struct radv_subpass *subpass =
3422 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
3423
3424 if (cmd_buffer->state.framebuffer) {
3425 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
3426 if (result != VK_SUCCESS)
3427 return result;
3428 }
3429
3430 cmd_buffer->state.inherited_pipeline_statistics =
3431 pBeginInfo->pInheritanceInfo->pipelineStatistics;
3432
3433 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3434 }
3435
3436 if (unlikely(cmd_buffer->device->trace_bo))
3437 radv_cmd_buffer_trace_emit(cmd_buffer);
3438
3439 radv_describe_begin_cmd_buffer(cmd_buffer);
3440
3441 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
3442
3443 return result;
3444 }
3445
3446 void radv_CmdBindVertexBuffers(
3447 VkCommandBuffer commandBuffer,
3448 uint32_t firstBinding,
3449 uint32_t bindingCount,
3450 const VkBuffer* pBuffers,
3451 const VkDeviceSize* pOffsets)
3452 {
3453 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3454 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
3455 bool changed = false;
3456
3457 /* We have to defer setting up vertex buffer since we need the buffer
3458 * stride from the pipeline. */
3459
3460 assert(firstBinding + bindingCount <= MAX_VBS);
3461 for (uint32_t i = 0; i < bindingCount; i++) {
3462 uint32_t idx = firstBinding + i;
3463
3464 if (!changed &&
3465 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
3466 vb[idx].offset != pOffsets[i])) {
3467 changed = true;
3468 }
3469
3470 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
3471 vb[idx].offset = pOffsets[i];
3472
3473 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3474 vb[idx].buffer->bo);
3475 }
3476
3477 if (!changed) {
3478 /* No state changes. */
3479 return;
3480 }
3481
3482 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
3483 }
3484
3485 static uint32_t
3486 vk_to_index_type(VkIndexType type)
3487 {
3488 switch (type) {
3489 case VK_INDEX_TYPE_UINT8_EXT:
3490 return V_028A7C_VGT_INDEX_8;
3491 case VK_INDEX_TYPE_UINT16:
3492 return V_028A7C_VGT_INDEX_16;
3493 case VK_INDEX_TYPE_UINT32:
3494 return V_028A7C_VGT_INDEX_32;
3495 default:
3496 unreachable("invalid index type");
3497 }
3498 }
3499
3500 static uint32_t
3501 radv_get_vgt_index_size(uint32_t type)
3502 {
3503 switch (type) {
3504 case V_028A7C_VGT_INDEX_8:
3505 return 1;
3506 case V_028A7C_VGT_INDEX_16:
3507 return 2;
3508 case V_028A7C_VGT_INDEX_32:
3509 return 4;
3510 default:
3511 unreachable("invalid index type");
3512 }
3513 }
3514
3515 void radv_CmdBindIndexBuffer(
3516 VkCommandBuffer commandBuffer,
3517 VkBuffer buffer,
3518 VkDeviceSize offset,
3519 VkIndexType indexType)
3520 {
3521 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3522 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
3523
3524 if (cmd_buffer->state.index_buffer == index_buffer &&
3525 cmd_buffer->state.index_offset == offset &&
3526 cmd_buffer->state.index_type == indexType) {
3527 /* No state changes. */
3528 return;
3529 }
3530
3531 cmd_buffer->state.index_buffer = index_buffer;
3532 cmd_buffer->state.index_offset = offset;
3533 cmd_buffer->state.index_type = vk_to_index_type(indexType);
3534 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
3535 cmd_buffer->state.index_va += index_buffer->offset + offset;
3536
3537 int index_size = radv_get_vgt_index_size(vk_to_index_type(indexType));
3538 cmd_buffer->state.max_index_count = (index_buffer->size - offset) / index_size;
3539 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3540 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
3541 }
3542
3543
3544 static void
3545 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3546 VkPipelineBindPoint bind_point,
3547 struct radv_descriptor_set *set, unsigned idx)
3548 {
3549 struct radeon_winsys *ws = cmd_buffer->device->ws;
3550
3551 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
3552
3553 assert(set);
3554 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
3555
3556 if (!cmd_buffer->device->use_global_bo_list) {
3557 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3558 if (set->descriptors[j])
3559 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
3560 }
3561
3562 if(set->bo)
3563 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
3564 }
3565
3566 void radv_CmdBindDescriptorSets(
3567 VkCommandBuffer commandBuffer,
3568 VkPipelineBindPoint pipelineBindPoint,
3569 VkPipelineLayout _layout,
3570 uint32_t firstSet,
3571 uint32_t descriptorSetCount,
3572 const VkDescriptorSet* pDescriptorSets,
3573 uint32_t dynamicOffsetCount,
3574 const uint32_t* pDynamicOffsets)
3575 {
3576 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3577 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3578 unsigned dyn_idx = 0;
3579
3580 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
3581 struct radv_descriptor_state *descriptors_state =
3582 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3583
3584 for (unsigned i = 0; i < descriptorSetCount; ++i) {
3585 unsigned idx = i + firstSet;
3586 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
3587
3588 /* If the set is already bound we only need to update the
3589 * (potentially changed) dynamic offsets. */
3590 if (descriptors_state->sets[idx] != set ||
3591 !(descriptors_state->valid & (1u << idx))) {
3592 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
3593 }
3594
3595 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
3596 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
3597 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
3598 assert(dyn_idx < dynamicOffsetCount);
3599
3600 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
3601 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
3602 dst[0] = va;
3603 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
3604 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
3605 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3606 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3607 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3608 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3609
3610 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
3611 dst[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3612 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3613 S_008F0C_RESOURCE_LEVEL(1);
3614 } else {
3615 dst[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3616 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3617 }
3618
3619 cmd_buffer->push_constant_stages |=
3620 set->layout->dynamic_shader_stages;
3621 }
3622 }
3623 }
3624
3625 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3626 struct radv_descriptor_set *set,
3627 struct radv_descriptor_set_layout *layout,
3628 VkPipelineBindPoint bind_point)
3629 {
3630 struct radv_descriptor_state *descriptors_state =
3631 radv_get_descriptors_state(cmd_buffer, bind_point);
3632 set->size = layout->size;
3633 set->layout = layout;
3634
3635 if (descriptors_state->push_set.capacity < set->size) {
3636 size_t new_size = MAX2(set->size, 1024);
3637 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
3638 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
3639
3640 free(set->mapped_ptr);
3641 set->mapped_ptr = malloc(new_size);
3642
3643 if (!set->mapped_ptr) {
3644 descriptors_state->push_set.capacity = 0;
3645 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3646 return false;
3647 }
3648
3649 descriptors_state->push_set.capacity = new_size;
3650 }
3651
3652 return true;
3653 }
3654
3655 void radv_meta_push_descriptor_set(
3656 struct radv_cmd_buffer* cmd_buffer,
3657 VkPipelineBindPoint pipelineBindPoint,
3658 VkPipelineLayout _layout,
3659 uint32_t set,
3660 uint32_t descriptorWriteCount,
3661 const VkWriteDescriptorSet* pDescriptorWrites)
3662 {
3663 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3664 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
3665 unsigned bo_offset;
3666
3667 assert(set == 0);
3668 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3669
3670 push_set->size = layout->set[set].layout->size;
3671 push_set->layout = layout->set[set].layout;
3672
3673 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
3674 &bo_offset,
3675 (void**) &push_set->mapped_ptr))
3676 return;
3677
3678 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
3679 push_set->va += bo_offset;
3680
3681 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3682 radv_descriptor_set_to_handle(push_set),
3683 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3684
3685 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3686 }
3687
3688 void radv_CmdPushDescriptorSetKHR(
3689 VkCommandBuffer commandBuffer,
3690 VkPipelineBindPoint pipelineBindPoint,
3691 VkPipelineLayout _layout,
3692 uint32_t set,
3693 uint32_t descriptorWriteCount,
3694 const VkWriteDescriptorSet* pDescriptorWrites)
3695 {
3696 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3697 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3698 struct radv_descriptor_state *descriptors_state =
3699 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3700 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3701
3702 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3703
3704 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3705 layout->set[set].layout,
3706 pipelineBindPoint))
3707 return;
3708
3709 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3710 * because it is invalid, according to Vulkan spec.
3711 */
3712 for (int i = 0; i < descriptorWriteCount; i++) {
3713 ASSERTED const VkWriteDescriptorSet *writeset = &pDescriptorWrites[i];
3714 assert(writeset->descriptorType != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT);
3715 }
3716
3717 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3718 radv_descriptor_set_to_handle(push_set),
3719 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3720
3721 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3722 descriptors_state->push_dirty = true;
3723 }
3724
3725 void radv_CmdPushDescriptorSetWithTemplateKHR(
3726 VkCommandBuffer commandBuffer,
3727 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
3728 VkPipelineLayout _layout,
3729 uint32_t set,
3730 const void* pData)
3731 {
3732 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3733 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3734 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
3735 struct radv_descriptor_state *descriptors_state =
3736 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
3737 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3738
3739 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3740
3741 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3742 layout->set[set].layout,
3743 templ->bind_point))
3744 return;
3745
3746 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
3747 descriptorUpdateTemplate, pData);
3748
3749 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
3750 descriptors_state->push_dirty = true;
3751 }
3752
3753 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
3754 VkPipelineLayout layout,
3755 VkShaderStageFlags stageFlags,
3756 uint32_t offset,
3757 uint32_t size,
3758 const void* pValues)
3759 {
3760 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3761 memcpy(cmd_buffer->push_constants + offset, pValues, size);
3762 cmd_buffer->push_constant_stages |= stageFlags;
3763 }
3764
3765 VkResult radv_EndCommandBuffer(
3766 VkCommandBuffer commandBuffer)
3767 {
3768 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3769
3770 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
3771 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6)
3772 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WB_L2;
3773
3774 /* Make sure to sync all pending active queries at the end of
3775 * command buffer.
3776 */
3777 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
3778
3779 /* Since NGG streamout uses GDS, we need to make GDS idle when
3780 * we leave the IB, otherwise another process might overwrite
3781 * it while our shaders are busy.
3782 */
3783 if (cmd_buffer->gds_needed)
3784 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
3785
3786 si_emit_cache_flush(cmd_buffer);
3787 }
3788
3789 /* Make sure CP DMA is idle at the end of IBs because the kernel
3790 * doesn't wait for it.
3791 */
3792 si_cp_dma_wait_for_idle(cmd_buffer);
3793
3794 radv_describe_end_cmd_buffer(cmd_buffer);
3795
3796 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3797 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
3798
3799 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
3800 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3801
3802 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
3803
3804 return cmd_buffer->record_result;
3805 }
3806
3807 static void
3808 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
3809 {
3810 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3811
3812 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
3813 return;
3814
3815 assert(!pipeline->ctx_cs.cdw);
3816
3817 cmd_buffer->state.emitted_compute_pipeline = pipeline;
3818
3819 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
3820 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
3821
3822 cmd_buffer->compute_scratch_size_per_wave_needed = MAX2(cmd_buffer->compute_scratch_size_per_wave_needed,
3823 pipeline->scratch_bytes_per_wave);
3824 cmd_buffer->compute_scratch_waves_wanted = MAX2(cmd_buffer->compute_scratch_waves_wanted,
3825 pipeline->max_waves);
3826
3827 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3828 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
3829
3830 if (unlikely(cmd_buffer->device->trace_bo))
3831 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
3832 }
3833
3834 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
3835 VkPipelineBindPoint bind_point)
3836 {
3837 struct radv_descriptor_state *descriptors_state =
3838 radv_get_descriptors_state(cmd_buffer, bind_point);
3839
3840 descriptors_state->dirty |= descriptors_state->valid;
3841 }
3842
3843 void radv_CmdBindPipeline(
3844 VkCommandBuffer commandBuffer,
3845 VkPipelineBindPoint pipelineBindPoint,
3846 VkPipeline _pipeline)
3847 {
3848 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3849 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
3850
3851 switch (pipelineBindPoint) {
3852 case VK_PIPELINE_BIND_POINT_COMPUTE:
3853 if (cmd_buffer->state.compute_pipeline == pipeline)
3854 return;
3855 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3856
3857 cmd_buffer->state.compute_pipeline = pipeline;
3858 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
3859 break;
3860 case VK_PIPELINE_BIND_POINT_GRAPHICS:
3861 if (cmd_buffer->state.pipeline == pipeline)
3862 return;
3863 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3864
3865 cmd_buffer->state.pipeline = pipeline;
3866 if (!pipeline)
3867 break;
3868
3869 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
3870 cmd_buffer->push_constant_stages |= pipeline->active_stages;
3871
3872 /* the new vertex shader might not have the same user regs */
3873 cmd_buffer->state.last_first_instance = -1;
3874 cmd_buffer->state.last_vertex_offset = -1;
3875
3876 /* Prefetch all pipeline shaders at first draw time. */
3877 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
3878
3879 if ((cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI10 ||
3880 cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI12 ||
3881 cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI14) &&
3882 cmd_buffer->state.emitted_pipeline &&
3883 radv_pipeline_has_ngg(cmd_buffer->state.emitted_pipeline) &&
3884 !radv_pipeline_has_ngg(cmd_buffer->state.pipeline)) {
3885 /* Transitioning from NGG to legacy GS requires
3886 * VGT_FLUSH on Navi10-14. VGT_FLUSH is also emitted
3887 * at the beginning of IBs when legacy GS ring pointers
3888 * are set.
3889 */
3890 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
3891 }
3892
3893 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
3894 radv_bind_streamout_state(cmd_buffer, pipeline);
3895
3896 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
3897 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
3898 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
3899 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
3900
3901 if (radv_pipeline_has_tess(pipeline))
3902 cmd_buffer->tess_rings_needed = true;
3903 break;
3904 default:
3905 assert(!"invalid bind point");
3906 break;
3907 }
3908 }
3909
3910 void radv_CmdSetViewport(
3911 VkCommandBuffer commandBuffer,
3912 uint32_t firstViewport,
3913 uint32_t viewportCount,
3914 const VkViewport* pViewports)
3915 {
3916 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3917 struct radv_cmd_state *state = &cmd_buffer->state;
3918 ASSERTED const uint32_t total_count = firstViewport + viewportCount;
3919
3920 assert(firstViewport < MAX_VIEWPORTS);
3921 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
3922
3923 if (!memcmp(state->dynamic.viewport.viewports + firstViewport,
3924 pViewports, viewportCount * sizeof(*pViewports))) {
3925 return;
3926 }
3927
3928 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
3929 viewportCount * sizeof(*pViewports));
3930
3931 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
3932 }
3933
3934 void radv_CmdSetScissor(
3935 VkCommandBuffer commandBuffer,
3936 uint32_t firstScissor,
3937 uint32_t scissorCount,
3938 const VkRect2D* pScissors)
3939 {
3940 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3941 struct radv_cmd_state *state = &cmd_buffer->state;
3942 ASSERTED const uint32_t total_count = firstScissor + scissorCount;
3943
3944 assert(firstScissor < MAX_SCISSORS);
3945 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
3946
3947 if (!memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
3948 scissorCount * sizeof(*pScissors))) {
3949 return;
3950 }
3951
3952 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
3953 scissorCount * sizeof(*pScissors));
3954
3955 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
3956 }
3957
3958 void radv_CmdSetLineWidth(
3959 VkCommandBuffer commandBuffer,
3960 float lineWidth)
3961 {
3962 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3963
3964 if (cmd_buffer->state.dynamic.line_width == lineWidth)
3965 return;
3966
3967 cmd_buffer->state.dynamic.line_width = lineWidth;
3968 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
3969 }
3970
3971 void radv_CmdSetDepthBias(
3972 VkCommandBuffer commandBuffer,
3973 float depthBiasConstantFactor,
3974 float depthBiasClamp,
3975 float depthBiasSlopeFactor)
3976 {
3977 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3978 struct radv_cmd_state *state = &cmd_buffer->state;
3979
3980 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
3981 state->dynamic.depth_bias.clamp == depthBiasClamp &&
3982 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
3983 return;
3984 }
3985
3986 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
3987 state->dynamic.depth_bias.clamp = depthBiasClamp;
3988 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
3989
3990 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
3991 }
3992
3993 void radv_CmdSetBlendConstants(
3994 VkCommandBuffer commandBuffer,
3995 const float blendConstants[4])
3996 {
3997 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3998 struct radv_cmd_state *state = &cmd_buffer->state;
3999
4000 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
4001 return;
4002
4003 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
4004
4005 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
4006 }
4007
4008 void radv_CmdSetDepthBounds(
4009 VkCommandBuffer commandBuffer,
4010 float minDepthBounds,
4011 float maxDepthBounds)
4012 {
4013 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4014 struct radv_cmd_state *state = &cmd_buffer->state;
4015
4016 if (state->dynamic.depth_bounds.min == minDepthBounds &&
4017 state->dynamic.depth_bounds.max == maxDepthBounds) {
4018 return;
4019 }
4020
4021 state->dynamic.depth_bounds.min = minDepthBounds;
4022 state->dynamic.depth_bounds.max = maxDepthBounds;
4023
4024 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
4025 }
4026
4027 void radv_CmdSetStencilCompareMask(
4028 VkCommandBuffer commandBuffer,
4029 VkStencilFaceFlags faceMask,
4030 uint32_t compareMask)
4031 {
4032 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4033 struct radv_cmd_state *state = &cmd_buffer->state;
4034 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
4035 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
4036
4037 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4038 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4039 return;
4040 }
4041
4042 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4043 state->dynamic.stencil_compare_mask.front = compareMask;
4044 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4045 state->dynamic.stencil_compare_mask.back = compareMask;
4046
4047 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
4048 }
4049
4050 void radv_CmdSetStencilWriteMask(
4051 VkCommandBuffer commandBuffer,
4052 VkStencilFaceFlags faceMask,
4053 uint32_t writeMask)
4054 {
4055 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4056 struct radv_cmd_state *state = &cmd_buffer->state;
4057 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
4058 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
4059
4060 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4061 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4062 return;
4063 }
4064
4065 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4066 state->dynamic.stencil_write_mask.front = writeMask;
4067 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4068 state->dynamic.stencil_write_mask.back = writeMask;
4069
4070 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
4071 }
4072
4073 void radv_CmdSetStencilReference(
4074 VkCommandBuffer commandBuffer,
4075 VkStencilFaceFlags faceMask,
4076 uint32_t reference)
4077 {
4078 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4079 struct radv_cmd_state *state = &cmd_buffer->state;
4080 bool front_same = state->dynamic.stencil_reference.front == reference;
4081 bool back_same = state->dynamic.stencil_reference.back == reference;
4082
4083 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4084 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4085 return;
4086 }
4087
4088 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4089 cmd_buffer->state.dynamic.stencil_reference.front = reference;
4090 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4091 cmd_buffer->state.dynamic.stencil_reference.back = reference;
4092
4093 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
4094 }
4095
4096 void radv_CmdSetDiscardRectangleEXT(
4097 VkCommandBuffer commandBuffer,
4098 uint32_t firstDiscardRectangle,
4099 uint32_t discardRectangleCount,
4100 const VkRect2D* pDiscardRectangles)
4101 {
4102 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4103 struct radv_cmd_state *state = &cmd_buffer->state;
4104 ASSERTED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
4105
4106 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
4107 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
4108
4109 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
4110 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
4111 return;
4112 }
4113
4114 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
4115 pDiscardRectangles, discardRectangleCount);
4116
4117 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
4118 }
4119
4120 void radv_CmdSetSampleLocationsEXT(
4121 VkCommandBuffer commandBuffer,
4122 const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
4123 {
4124 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4125 struct radv_cmd_state *state = &cmd_buffer->state;
4126
4127 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
4128
4129 state->dynamic.sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
4130 state->dynamic.sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
4131 state->dynamic.sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
4132 typed_memcpy(&state->dynamic.sample_location.locations[0],
4133 pSampleLocationsInfo->pSampleLocations,
4134 pSampleLocationsInfo->sampleLocationsCount);
4135
4136 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS;
4137 }
4138
4139 void radv_CmdSetLineStippleEXT(
4140 VkCommandBuffer commandBuffer,
4141 uint32_t lineStippleFactor,
4142 uint16_t lineStipplePattern)
4143 {
4144 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4145 struct radv_cmd_state *state = &cmd_buffer->state;
4146
4147 state->dynamic.line_stipple.factor = lineStippleFactor;
4148 state->dynamic.line_stipple.pattern = lineStipplePattern;
4149
4150 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE;
4151 }
4152
4153 void radv_CmdExecuteCommands(
4154 VkCommandBuffer commandBuffer,
4155 uint32_t commandBufferCount,
4156 const VkCommandBuffer* pCmdBuffers)
4157 {
4158 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
4159
4160 assert(commandBufferCount > 0);
4161
4162 /* Emit pending flushes on primary prior to executing secondary */
4163 si_emit_cache_flush(primary);
4164
4165 for (uint32_t i = 0; i < commandBufferCount; i++) {
4166 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
4167
4168 primary->scratch_size_per_wave_needed = MAX2(primary->scratch_size_per_wave_needed,
4169 secondary->scratch_size_per_wave_needed);
4170 primary->scratch_waves_wanted = MAX2(primary->scratch_waves_wanted,
4171 secondary->scratch_waves_wanted);
4172 primary->compute_scratch_size_per_wave_needed = MAX2(primary->compute_scratch_size_per_wave_needed,
4173 secondary->compute_scratch_size_per_wave_needed);
4174 primary->compute_scratch_waves_wanted = MAX2(primary->compute_scratch_waves_wanted,
4175 secondary->compute_scratch_waves_wanted);
4176
4177 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
4178 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
4179 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
4180 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
4181 if (secondary->tess_rings_needed)
4182 primary->tess_rings_needed = true;
4183 if (secondary->sample_positions_needed)
4184 primary->sample_positions_needed = true;
4185 if (secondary->gds_needed)
4186 primary->gds_needed = true;
4187
4188 if (!secondary->state.framebuffer &&
4189 (primary->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)) {
4190 /* Emit the framebuffer state from primary if secondary
4191 * has been recorded without a framebuffer, otherwise
4192 * fast color/depth clears can't work.
4193 */
4194 radv_emit_framebuffer_state(primary);
4195 }
4196
4197 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
4198
4199
4200 /* When the secondary command buffer is compute only we don't
4201 * need to re-emit the current graphics pipeline.
4202 */
4203 if (secondary->state.emitted_pipeline) {
4204 primary->state.emitted_pipeline =
4205 secondary->state.emitted_pipeline;
4206 }
4207
4208 /* When the secondary command buffer is graphics only we don't
4209 * need to re-emit the current compute pipeline.
4210 */
4211 if (secondary->state.emitted_compute_pipeline) {
4212 primary->state.emitted_compute_pipeline =
4213 secondary->state.emitted_compute_pipeline;
4214 }
4215
4216 /* Only re-emit the draw packets when needed. */
4217 if (secondary->state.last_primitive_reset_en != -1) {
4218 primary->state.last_primitive_reset_en =
4219 secondary->state.last_primitive_reset_en;
4220 }
4221
4222 if (secondary->state.last_primitive_reset_index) {
4223 primary->state.last_primitive_reset_index =
4224 secondary->state.last_primitive_reset_index;
4225 }
4226
4227 if (secondary->state.last_ia_multi_vgt_param) {
4228 primary->state.last_ia_multi_vgt_param =
4229 secondary->state.last_ia_multi_vgt_param;
4230 }
4231
4232 primary->state.last_first_instance = secondary->state.last_first_instance;
4233 primary->state.last_num_instances = secondary->state.last_num_instances;
4234 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
4235 primary->state.last_sx_ps_downconvert = secondary->state.last_sx_ps_downconvert;
4236 primary->state.last_sx_blend_opt_epsilon = secondary->state.last_sx_blend_opt_epsilon;
4237 primary->state.last_sx_blend_opt_control = secondary->state.last_sx_blend_opt_control;
4238
4239 if (secondary->state.last_index_type != -1) {
4240 primary->state.last_index_type =
4241 secondary->state.last_index_type;
4242 }
4243 }
4244
4245 /* After executing commands from secondary buffers we have to dirty
4246 * some states.
4247 */
4248 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
4249 RADV_CMD_DIRTY_INDEX_BUFFER |
4250 RADV_CMD_DIRTY_DYNAMIC_ALL;
4251 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
4252 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
4253 }
4254
4255 VkResult radv_CreateCommandPool(
4256 VkDevice _device,
4257 const VkCommandPoolCreateInfo* pCreateInfo,
4258 const VkAllocationCallbacks* pAllocator,
4259 VkCommandPool* pCmdPool)
4260 {
4261 RADV_FROM_HANDLE(radv_device, device, _device);
4262 struct radv_cmd_pool *pool;
4263
4264 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
4265 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4266 if (pool == NULL)
4267 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4268
4269 if (pAllocator)
4270 pool->alloc = *pAllocator;
4271 else
4272 pool->alloc = device->alloc;
4273
4274 list_inithead(&pool->cmd_buffers);
4275 list_inithead(&pool->free_cmd_buffers);
4276
4277 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
4278
4279 *pCmdPool = radv_cmd_pool_to_handle(pool);
4280
4281 return VK_SUCCESS;
4282
4283 }
4284
4285 void radv_DestroyCommandPool(
4286 VkDevice _device,
4287 VkCommandPool commandPool,
4288 const VkAllocationCallbacks* pAllocator)
4289 {
4290 RADV_FROM_HANDLE(radv_device, device, _device);
4291 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4292
4293 if (!pool)
4294 return;
4295
4296 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4297 &pool->cmd_buffers, pool_link) {
4298 radv_cmd_buffer_destroy(cmd_buffer);
4299 }
4300
4301 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4302 &pool->free_cmd_buffers, pool_link) {
4303 radv_cmd_buffer_destroy(cmd_buffer);
4304 }
4305
4306 vk_free2(&device->alloc, pAllocator, pool);
4307 }
4308
4309 VkResult radv_ResetCommandPool(
4310 VkDevice device,
4311 VkCommandPool commandPool,
4312 VkCommandPoolResetFlags flags)
4313 {
4314 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4315 VkResult result;
4316
4317 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
4318 &pool->cmd_buffers, pool_link) {
4319 result = radv_reset_cmd_buffer(cmd_buffer);
4320 if (result != VK_SUCCESS)
4321 return result;
4322 }
4323
4324 return VK_SUCCESS;
4325 }
4326
4327 void radv_TrimCommandPool(
4328 VkDevice device,
4329 VkCommandPool commandPool,
4330 VkCommandPoolTrimFlags flags)
4331 {
4332 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4333
4334 if (!pool)
4335 return;
4336
4337 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4338 &pool->free_cmd_buffers, pool_link) {
4339 radv_cmd_buffer_destroy(cmd_buffer);
4340 }
4341 }
4342
4343 static void
4344 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
4345 uint32_t subpass_id)
4346 {
4347 struct radv_cmd_state *state = &cmd_buffer->state;
4348 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
4349
4350 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
4351 cmd_buffer->cs, 4096);
4352
4353 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
4354
4355 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
4356
4357 radv_describe_barrier_start(cmd_buffer, RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC);
4358
4359 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4360 const uint32_t a = subpass->attachments[i].attachment;
4361 if (a == VK_ATTACHMENT_UNUSED)
4362 continue;
4363
4364 radv_handle_subpass_image_transition(cmd_buffer,
4365 subpass->attachments[i],
4366 true);
4367 }
4368
4369 radv_describe_barrier_end(cmd_buffer);
4370
4371 radv_cmd_buffer_clear_subpass(cmd_buffer);
4372
4373 assert(cmd_buffer->cs->cdw <= cdw_max);
4374 }
4375
4376 static void
4377 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
4378 {
4379 struct radv_cmd_state *state = &cmd_buffer->state;
4380 const struct radv_subpass *subpass = state->subpass;
4381 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
4382
4383 radv_cmd_buffer_resolve_subpass(cmd_buffer);
4384
4385 radv_describe_barrier_start(cmd_buffer, RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC);
4386
4387 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4388 const uint32_t a = subpass->attachments[i].attachment;
4389 if (a == VK_ATTACHMENT_UNUSED)
4390 continue;
4391
4392 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
4393 continue;
4394
4395 VkImageLayout layout = state->pass->attachments[a].final_layout;
4396 VkImageLayout stencil_layout = state->pass->attachments[a].stencil_final_layout;
4397 struct radv_subpass_attachment att = { a, layout, stencil_layout };
4398 radv_handle_subpass_image_transition(cmd_buffer, att, false);
4399 }
4400
4401 radv_describe_barrier_end(cmd_buffer);
4402 }
4403
4404 void
4405 radv_cmd_buffer_begin_render_pass(struct radv_cmd_buffer *cmd_buffer,
4406 const VkRenderPassBeginInfo *pRenderPassBegin)
4407 {
4408 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
4409 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
4410 VkResult result;
4411
4412 cmd_buffer->state.framebuffer = framebuffer;
4413 cmd_buffer->state.pass = pass;
4414 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
4415
4416 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
4417 if (result != VK_SUCCESS)
4418 return;
4419
4420 result = radv_cmd_state_setup_sample_locations(cmd_buffer, pass, pRenderPassBegin);
4421 if (result != VK_SUCCESS)
4422 return;
4423 }
4424
4425 void radv_CmdBeginRenderPass(
4426 VkCommandBuffer commandBuffer,
4427 const VkRenderPassBeginInfo* pRenderPassBegin,
4428 VkSubpassContents contents)
4429 {
4430 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4431
4432 radv_cmd_buffer_begin_render_pass(cmd_buffer, pRenderPassBegin);
4433
4434 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
4435 }
4436
4437 void radv_CmdBeginRenderPass2(
4438 VkCommandBuffer commandBuffer,
4439 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
4440 const VkSubpassBeginInfo* pSubpassBeginInfo)
4441 {
4442 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
4443 pSubpassBeginInfo->contents);
4444 }
4445
4446 void radv_CmdNextSubpass(
4447 VkCommandBuffer commandBuffer,
4448 VkSubpassContents contents)
4449 {
4450 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4451
4452 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
4453 radv_cmd_buffer_end_subpass(cmd_buffer);
4454 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
4455 }
4456
4457 void radv_CmdNextSubpass2(
4458 VkCommandBuffer commandBuffer,
4459 const VkSubpassBeginInfo* pSubpassBeginInfo,
4460 const VkSubpassEndInfo* pSubpassEndInfo)
4461 {
4462 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
4463 }
4464
4465 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
4466 {
4467 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
4468 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
4469 if (!radv_get_shader(pipeline, stage))
4470 continue;
4471
4472 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
4473 if (loc->sgpr_idx == -1)
4474 continue;
4475 uint32_t base_reg = pipeline->user_data_0[stage];
4476 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4477
4478 }
4479 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
4480 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
4481 if (loc->sgpr_idx != -1) {
4482 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
4483 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4484 }
4485 }
4486 }
4487
4488 static void
4489 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4490 uint32_t vertex_count,
4491 bool use_opaque)
4492 {
4493 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
4494 radeon_emit(cmd_buffer->cs, vertex_count);
4495 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
4496 S_0287F0_USE_OPAQUE(use_opaque));
4497 }
4498
4499 static void
4500 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
4501 uint64_t index_va,
4502 uint32_t index_count)
4503 {
4504 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
4505 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
4506 radeon_emit(cmd_buffer->cs, index_va);
4507 radeon_emit(cmd_buffer->cs, index_va >> 32);
4508 radeon_emit(cmd_buffer->cs, index_count);
4509 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
4510 }
4511
4512 static void
4513 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4514 bool indexed,
4515 uint32_t draw_count,
4516 uint64_t count_va,
4517 uint32_t stride)
4518 {
4519 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4520 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
4521 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
4522 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id;
4523 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
4524 bool predicating = cmd_buffer->state.predicating;
4525 assert(base_reg);
4526
4527 /* just reset draw state for vertex data */
4528 cmd_buffer->state.last_first_instance = -1;
4529 cmd_buffer->state.last_num_instances = -1;
4530 cmd_buffer->state.last_vertex_offset = -1;
4531
4532 if (draw_count == 1 && !count_va && !draw_id_enable) {
4533 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
4534 PKT3_DRAW_INDIRECT, 3, predicating));
4535 radeon_emit(cs, 0);
4536 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4537 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4538 radeon_emit(cs, di_src_sel);
4539 } else {
4540 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
4541 PKT3_DRAW_INDIRECT_MULTI,
4542 8, predicating));
4543 radeon_emit(cs, 0);
4544 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4545 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4546 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
4547 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
4548 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
4549 radeon_emit(cs, draw_count); /* count */
4550 radeon_emit(cs, count_va); /* count_addr */
4551 radeon_emit(cs, count_va >> 32);
4552 radeon_emit(cs, stride); /* stride */
4553 radeon_emit(cs, di_src_sel);
4554 }
4555 }
4556
4557 static void
4558 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
4559 const struct radv_draw_info *info)
4560 {
4561 struct radv_cmd_state *state = &cmd_buffer->state;
4562 struct radeon_winsys *ws = cmd_buffer->device->ws;
4563 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4564
4565 if (info->indirect) {
4566 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4567 uint64_t count_va = 0;
4568
4569 va += info->indirect->offset + info->indirect_offset;
4570
4571 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4572
4573 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
4574 radeon_emit(cs, 1);
4575 radeon_emit(cs, va);
4576 radeon_emit(cs, va >> 32);
4577
4578 if (info->count_buffer) {
4579 count_va = radv_buffer_get_va(info->count_buffer->bo);
4580 count_va += info->count_buffer->offset +
4581 info->count_buffer_offset;
4582
4583 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
4584 }
4585
4586 if (!state->subpass->view_mask) {
4587 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4588 info->indexed,
4589 info->count,
4590 count_va,
4591 info->stride);
4592 } else {
4593 unsigned i;
4594 for_each_bit(i, state->subpass->view_mask) {
4595 radv_emit_view_index(cmd_buffer, i);
4596
4597 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4598 info->indexed,
4599 info->count,
4600 count_va,
4601 info->stride);
4602 }
4603 }
4604 } else {
4605 assert(state->pipeline->graphics.vtx_base_sgpr);
4606
4607 if (info->vertex_offset != state->last_vertex_offset ||
4608 info->first_instance != state->last_first_instance) {
4609 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
4610 state->pipeline->graphics.vtx_emit_num);
4611
4612 radeon_emit(cs, info->vertex_offset);
4613 radeon_emit(cs, info->first_instance);
4614 if (state->pipeline->graphics.vtx_emit_num == 3)
4615 radeon_emit(cs, 0);
4616 state->last_first_instance = info->first_instance;
4617 state->last_vertex_offset = info->vertex_offset;
4618 }
4619
4620 if (state->last_num_instances != info->instance_count) {
4621 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
4622 radeon_emit(cs, info->instance_count);
4623 state->last_num_instances = info->instance_count;
4624 }
4625
4626 if (info->indexed) {
4627 int index_size = radv_get_vgt_index_size(state->index_type);
4628 uint64_t index_va;
4629
4630 /* Skip draw calls with 0-sized index buffers. They
4631 * cause a hang on some chips, like Navi10-14.
4632 */
4633 if (!cmd_buffer->state.max_index_count)
4634 return;
4635
4636 index_va = state->index_va;
4637 index_va += info->first_index * index_size;
4638
4639 if (!state->subpass->view_mask) {
4640 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4641 index_va,
4642 info->count);
4643 } else {
4644 unsigned i;
4645 for_each_bit(i, state->subpass->view_mask) {
4646 radv_emit_view_index(cmd_buffer, i);
4647
4648 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4649 index_va,
4650 info->count);
4651 }
4652 }
4653 } else {
4654 if (!state->subpass->view_mask) {
4655 radv_cs_emit_draw_packet(cmd_buffer,
4656 info->count,
4657 !!info->strmout_buffer);
4658 } else {
4659 unsigned i;
4660 for_each_bit(i, state->subpass->view_mask) {
4661 radv_emit_view_index(cmd_buffer, i);
4662
4663 radv_cs_emit_draw_packet(cmd_buffer,
4664 info->count,
4665 !!info->strmout_buffer);
4666 }
4667 }
4668 }
4669 }
4670 }
4671
4672 /*
4673 * Vega and raven have a bug which triggers if there are multiple context
4674 * register contexts active at the same time with different scissor values.
4675 *
4676 * There are two possible workarounds:
4677 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
4678 * there is only ever 1 active set of scissor values at the same time.
4679 *
4680 * 2) Whenever the hardware switches contexts we have to set the scissor
4681 * registers again even if it is a noop. That way the new context gets
4682 * the correct scissor values.
4683 *
4684 * This implements option 2. radv_need_late_scissor_emission needs to
4685 * return true on affected HW if radv_emit_all_graphics_states sets
4686 * any context registers.
4687 */
4688 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
4689 const struct radv_draw_info *info)
4690 {
4691 struct radv_cmd_state *state = &cmd_buffer->state;
4692
4693 if (!cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
4694 return false;
4695
4696 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
4697 return true;
4698
4699 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
4700
4701 /* Index, vertex and streamout buffers don't change context regs, and
4702 * pipeline is already handled.
4703 */
4704 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
4705 RADV_CMD_DIRTY_VERTEX_BUFFER |
4706 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
4707 RADV_CMD_DIRTY_PIPELINE);
4708
4709 if (cmd_buffer->state.dirty & used_states)
4710 return true;
4711
4712 uint32_t primitive_reset_index =
4713 radv_get_primitive_reset_index(cmd_buffer);
4714
4715 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
4716 primitive_reset_index != state->last_primitive_reset_index)
4717 return true;
4718
4719 return false;
4720 }
4721
4722 static void
4723 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
4724 const struct radv_draw_info *info)
4725 {
4726 bool late_scissor_emission;
4727
4728 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
4729 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
4730 radv_emit_rbplus_state(cmd_buffer);
4731
4732 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
4733 radv_emit_graphics_pipeline(cmd_buffer);
4734
4735 /* This should be before the cmd_buffer->state.dirty is cleared
4736 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4737 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4738 late_scissor_emission =
4739 radv_need_late_scissor_emission(cmd_buffer, info);
4740
4741 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
4742 radv_emit_framebuffer_state(cmd_buffer);
4743
4744 if (info->indexed) {
4745 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
4746 radv_emit_index_buffer(cmd_buffer, info->indirect);
4747 } else {
4748 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4749 * so the state must be re-emitted before the next indexed
4750 * draw.
4751 */
4752 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
4753 cmd_buffer->state.last_index_type = -1;
4754 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
4755 }
4756 }
4757
4758 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
4759
4760 radv_emit_draw_registers(cmd_buffer, info);
4761
4762 if (late_scissor_emission)
4763 radv_emit_scissor(cmd_buffer);
4764 }
4765
4766 static void
4767 radv_draw(struct radv_cmd_buffer *cmd_buffer,
4768 const struct radv_draw_info *info)
4769 {
4770 struct radeon_info *rad_info =
4771 &cmd_buffer->device->physical_device->rad_info;
4772 bool has_prefetch =
4773 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4774 bool pipeline_is_dirty =
4775 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
4776 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
4777
4778 ASSERTED unsigned cdw_max =
4779 radeon_check_space(cmd_buffer->device->ws,
4780 cmd_buffer->cs, 4096);
4781
4782 if (likely(!info->indirect)) {
4783 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4784 * no workaround for indirect draws, but we can at least skip
4785 * direct draws.
4786 */
4787 if (unlikely(!info->instance_count))
4788 return;
4789
4790 /* Handle count == 0. */
4791 if (unlikely(!info->count && !info->strmout_buffer))
4792 return;
4793 }
4794
4795 radv_describe_draw(cmd_buffer);
4796
4797 /* Use optimal packet order based on whether we need to sync the
4798 * pipeline.
4799 */
4800 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4801 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4802 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4803 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4804 /* If we have to wait for idle, set all states first, so that
4805 * all SET packets are processed in parallel with previous draw
4806 * calls. Then upload descriptors, set shader pointers, and
4807 * draw, and prefetch at the end. This ensures that the time
4808 * the CUs are idle is very short. (there are only SET_SH
4809 * packets between the wait and the draw)
4810 */
4811 radv_emit_all_graphics_states(cmd_buffer, info);
4812 si_emit_cache_flush(cmd_buffer);
4813 /* <-- CUs are idle here --> */
4814
4815 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4816
4817 radv_emit_draw_packets(cmd_buffer, info);
4818 /* <-- CUs are busy here --> */
4819
4820 /* Start prefetches after the draw has been started. Both will
4821 * run in parallel, but starting the draw first is more
4822 * important.
4823 */
4824 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4825 radv_emit_prefetch_L2(cmd_buffer,
4826 cmd_buffer->state.pipeline, false);
4827 }
4828 } else {
4829 /* If we don't wait for idle, start prefetches first, then set
4830 * states, and draw at the end.
4831 */
4832 si_emit_cache_flush(cmd_buffer);
4833
4834 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4835 /* Only prefetch the vertex shader and VBO descriptors
4836 * in order to start the draw as soon as possible.
4837 */
4838 radv_emit_prefetch_L2(cmd_buffer,
4839 cmd_buffer->state.pipeline, true);
4840 }
4841
4842 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4843
4844 radv_emit_all_graphics_states(cmd_buffer, info);
4845 radv_emit_draw_packets(cmd_buffer, info);
4846
4847 /* Prefetch the remaining shaders after the draw has been
4848 * started.
4849 */
4850 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4851 radv_emit_prefetch_L2(cmd_buffer,
4852 cmd_buffer->state.pipeline, false);
4853 }
4854 }
4855
4856 /* Workaround for a VGT hang when streamout is enabled.
4857 * It must be done after drawing.
4858 */
4859 if (cmd_buffer->state.streamout.streamout_enabled &&
4860 (rad_info->family == CHIP_HAWAII ||
4861 rad_info->family == CHIP_TONGA ||
4862 rad_info->family == CHIP_FIJI)) {
4863 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
4864 }
4865
4866 assert(cmd_buffer->cs->cdw <= cdw_max);
4867 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
4868 }
4869
4870 void radv_CmdDraw(
4871 VkCommandBuffer commandBuffer,
4872 uint32_t vertexCount,
4873 uint32_t instanceCount,
4874 uint32_t firstVertex,
4875 uint32_t firstInstance)
4876 {
4877 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4878 struct radv_draw_info info = {};
4879
4880 info.count = vertexCount;
4881 info.instance_count = instanceCount;
4882 info.first_instance = firstInstance;
4883 info.vertex_offset = firstVertex;
4884
4885 radv_draw(cmd_buffer, &info);
4886 }
4887
4888 void radv_CmdDrawIndexed(
4889 VkCommandBuffer commandBuffer,
4890 uint32_t indexCount,
4891 uint32_t instanceCount,
4892 uint32_t firstIndex,
4893 int32_t vertexOffset,
4894 uint32_t firstInstance)
4895 {
4896 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4897 struct radv_draw_info info = {};
4898
4899 info.indexed = true;
4900 info.count = indexCount;
4901 info.instance_count = instanceCount;
4902 info.first_index = firstIndex;
4903 info.vertex_offset = vertexOffset;
4904 info.first_instance = firstInstance;
4905
4906 radv_draw(cmd_buffer, &info);
4907 }
4908
4909 void radv_CmdDrawIndirect(
4910 VkCommandBuffer commandBuffer,
4911 VkBuffer _buffer,
4912 VkDeviceSize offset,
4913 uint32_t drawCount,
4914 uint32_t stride)
4915 {
4916 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4917 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4918 struct radv_draw_info info = {};
4919
4920 info.count = drawCount;
4921 info.indirect = buffer;
4922 info.indirect_offset = offset;
4923 info.stride = stride;
4924
4925 radv_draw(cmd_buffer, &info);
4926 }
4927
4928 void radv_CmdDrawIndexedIndirect(
4929 VkCommandBuffer commandBuffer,
4930 VkBuffer _buffer,
4931 VkDeviceSize offset,
4932 uint32_t drawCount,
4933 uint32_t stride)
4934 {
4935 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4936 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4937 struct radv_draw_info info = {};
4938
4939 info.indexed = true;
4940 info.count = drawCount;
4941 info.indirect = buffer;
4942 info.indirect_offset = offset;
4943 info.stride = stride;
4944
4945 radv_draw(cmd_buffer, &info);
4946 }
4947
4948 void radv_CmdDrawIndirectCount(
4949 VkCommandBuffer commandBuffer,
4950 VkBuffer _buffer,
4951 VkDeviceSize offset,
4952 VkBuffer _countBuffer,
4953 VkDeviceSize countBufferOffset,
4954 uint32_t maxDrawCount,
4955 uint32_t stride)
4956 {
4957 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4958 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4959 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4960 struct radv_draw_info info = {};
4961
4962 info.count = maxDrawCount;
4963 info.indirect = buffer;
4964 info.indirect_offset = offset;
4965 info.count_buffer = count_buffer;
4966 info.count_buffer_offset = countBufferOffset;
4967 info.stride = stride;
4968
4969 radv_draw(cmd_buffer, &info);
4970 }
4971
4972 void radv_CmdDrawIndexedIndirectCount(
4973 VkCommandBuffer commandBuffer,
4974 VkBuffer _buffer,
4975 VkDeviceSize offset,
4976 VkBuffer _countBuffer,
4977 VkDeviceSize countBufferOffset,
4978 uint32_t maxDrawCount,
4979 uint32_t stride)
4980 {
4981 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4982 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4983 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4984 struct radv_draw_info info = {};
4985
4986 info.indexed = true;
4987 info.count = maxDrawCount;
4988 info.indirect = buffer;
4989 info.indirect_offset = offset;
4990 info.count_buffer = count_buffer;
4991 info.count_buffer_offset = countBufferOffset;
4992 info.stride = stride;
4993
4994 radv_draw(cmd_buffer, &info);
4995 }
4996
4997 struct radv_dispatch_info {
4998 /**
4999 * Determine the layout of the grid (in block units) to be used.
5000 */
5001 uint32_t blocks[3];
5002
5003 /**
5004 * A starting offset for the grid. If unaligned is set, the offset
5005 * must still be aligned.
5006 */
5007 uint32_t offsets[3];
5008 /**
5009 * Whether it's an unaligned compute dispatch.
5010 */
5011 bool unaligned;
5012
5013 /**
5014 * Indirect compute parameters resource.
5015 */
5016 struct radv_buffer *indirect;
5017 uint64_t indirect_offset;
5018 };
5019
5020 static void
5021 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
5022 const struct radv_dispatch_info *info)
5023 {
5024 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
5025 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
5026 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
5027 struct radeon_winsys *ws = cmd_buffer->device->ws;
5028 bool predicating = cmd_buffer->state.predicating;
5029 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5030 struct radv_userdata_info *loc;
5031
5032 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
5033 AC_UD_CS_GRID_SIZE);
5034
5035 ASSERTED unsigned cdw_max = radeon_check_space(ws, cs, 25);
5036
5037 if (compute_shader->info.wave_size == 32) {
5038 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
5039 dispatch_initiator |= S_00B800_CS_W32_EN(1);
5040 }
5041
5042 if (info->indirect) {
5043 uint64_t va = radv_buffer_get_va(info->indirect->bo);
5044
5045 va += info->indirect->offset + info->indirect_offset;
5046
5047 radv_cs_add_buffer(ws, cs, info->indirect->bo);
5048
5049 if (loc->sgpr_idx != -1) {
5050 for (unsigned i = 0; i < 3; ++i) {
5051 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5052 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5053 COPY_DATA_DST_SEL(COPY_DATA_REG));
5054 radeon_emit(cs, (va + 4 * i));
5055 radeon_emit(cs, (va + 4 * i) >> 32);
5056 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
5057 + loc->sgpr_idx * 4) >> 2) + i);
5058 radeon_emit(cs, 0);
5059 }
5060 }
5061
5062 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
5063 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
5064 PKT3_SHADER_TYPE_S(1));
5065 radeon_emit(cs, va);
5066 radeon_emit(cs, va >> 32);
5067 radeon_emit(cs, dispatch_initiator);
5068 } else {
5069 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
5070 PKT3_SHADER_TYPE_S(1));
5071 radeon_emit(cs, 1);
5072 radeon_emit(cs, va);
5073 radeon_emit(cs, va >> 32);
5074
5075 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
5076 PKT3_SHADER_TYPE_S(1));
5077 radeon_emit(cs, 0);
5078 radeon_emit(cs, dispatch_initiator);
5079 }
5080 } else {
5081 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
5082 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
5083
5084 if (info->unaligned) {
5085 unsigned *cs_block_size = compute_shader->info.cs.block_size;
5086 unsigned remainder[3];
5087
5088 /* If aligned, these should be an entire block size,
5089 * not 0.
5090 */
5091 remainder[0] = blocks[0] + cs_block_size[0] -
5092 align_u32_npot(blocks[0], cs_block_size[0]);
5093 remainder[1] = blocks[1] + cs_block_size[1] -
5094 align_u32_npot(blocks[1], cs_block_size[1]);
5095 remainder[2] = blocks[2] + cs_block_size[2] -
5096 align_u32_npot(blocks[2], cs_block_size[2]);
5097
5098 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
5099 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
5100 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
5101
5102 for(unsigned i = 0; i < 3; ++i) {
5103 assert(offsets[i] % cs_block_size[i] == 0);
5104 offsets[i] /= cs_block_size[i];
5105 }
5106
5107 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
5108 radeon_emit(cs,
5109 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
5110 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
5111 radeon_emit(cs,
5112 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
5113 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
5114 radeon_emit(cs,
5115 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
5116 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
5117
5118 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
5119 }
5120
5121 if (loc->sgpr_idx != -1) {
5122 assert(loc->num_sgprs == 3);
5123
5124 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
5125 loc->sgpr_idx * 4, 3);
5126 radeon_emit(cs, blocks[0]);
5127 radeon_emit(cs, blocks[1]);
5128 radeon_emit(cs, blocks[2]);
5129 }
5130
5131 if (offsets[0] || offsets[1] || offsets[2]) {
5132 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
5133 radeon_emit(cs, offsets[0]);
5134 radeon_emit(cs, offsets[1]);
5135 radeon_emit(cs, offsets[2]);
5136
5137 /* The blocks in the packet are not counts but end values. */
5138 for (unsigned i = 0; i < 3; ++i)
5139 blocks[i] += offsets[i];
5140 } else {
5141 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
5142 }
5143
5144 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
5145 PKT3_SHADER_TYPE_S(1));
5146 radeon_emit(cs, blocks[0]);
5147 radeon_emit(cs, blocks[1]);
5148 radeon_emit(cs, blocks[2]);
5149 radeon_emit(cs, dispatch_initiator);
5150 }
5151
5152 assert(cmd_buffer->cs->cdw <= cdw_max);
5153 }
5154
5155 static void
5156 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
5157 {
5158 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
5159 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
5160 }
5161
5162 static void
5163 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
5164 const struct radv_dispatch_info *info)
5165 {
5166 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
5167 bool has_prefetch =
5168 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
5169 bool pipeline_is_dirty = pipeline &&
5170 pipeline != cmd_buffer->state.emitted_compute_pipeline;
5171
5172 radv_describe_dispatch(cmd_buffer, 8, 8, 8);
5173
5174 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5175 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5176 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
5177 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
5178 /* If we have to wait for idle, set all states first, so that
5179 * all SET packets are processed in parallel with previous draw
5180 * calls. Then upload descriptors, set shader pointers, and
5181 * dispatch, and prefetch at the end. This ensures that the
5182 * time the CUs are idle is very short. (there are only SET_SH
5183 * packets between the wait and the draw)
5184 */
5185 radv_emit_compute_pipeline(cmd_buffer);
5186 si_emit_cache_flush(cmd_buffer);
5187 /* <-- CUs are idle here --> */
5188
5189 radv_upload_compute_shader_descriptors(cmd_buffer);
5190
5191 radv_emit_dispatch_packets(cmd_buffer, info);
5192 /* <-- CUs are busy here --> */
5193
5194 /* Start prefetches after the dispatch has been started. Both
5195 * will run in parallel, but starting the dispatch first is
5196 * more important.
5197 */
5198 if (has_prefetch && pipeline_is_dirty) {
5199 radv_emit_shader_prefetch(cmd_buffer,
5200 pipeline->shaders[MESA_SHADER_COMPUTE]);
5201 }
5202 } else {
5203 /* If we don't wait for idle, start prefetches first, then set
5204 * states, and dispatch at the end.
5205 */
5206 si_emit_cache_flush(cmd_buffer);
5207
5208 if (has_prefetch && pipeline_is_dirty) {
5209 radv_emit_shader_prefetch(cmd_buffer,
5210 pipeline->shaders[MESA_SHADER_COMPUTE]);
5211 }
5212
5213 radv_upload_compute_shader_descriptors(cmd_buffer);
5214
5215 radv_emit_compute_pipeline(cmd_buffer);
5216 radv_emit_dispatch_packets(cmd_buffer, info);
5217 }
5218
5219 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
5220 }
5221
5222 void radv_CmdDispatchBase(
5223 VkCommandBuffer commandBuffer,
5224 uint32_t base_x,
5225 uint32_t base_y,
5226 uint32_t base_z,
5227 uint32_t x,
5228 uint32_t y,
5229 uint32_t z)
5230 {
5231 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5232 struct radv_dispatch_info info = {};
5233
5234 info.blocks[0] = x;
5235 info.blocks[1] = y;
5236 info.blocks[2] = z;
5237
5238 info.offsets[0] = base_x;
5239 info.offsets[1] = base_y;
5240 info.offsets[2] = base_z;
5241 radv_dispatch(cmd_buffer, &info);
5242 }
5243
5244 void radv_CmdDispatch(
5245 VkCommandBuffer commandBuffer,
5246 uint32_t x,
5247 uint32_t y,
5248 uint32_t z)
5249 {
5250 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
5251 }
5252
5253 void radv_CmdDispatchIndirect(
5254 VkCommandBuffer commandBuffer,
5255 VkBuffer _buffer,
5256 VkDeviceSize offset)
5257 {
5258 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5259 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5260 struct radv_dispatch_info info = {};
5261
5262 info.indirect = buffer;
5263 info.indirect_offset = offset;
5264
5265 radv_dispatch(cmd_buffer, &info);
5266 }
5267
5268 void radv_unaligned_dispatch(
5269 struct radv_cmd_buffer *cmd_buffer,
5270 uint32_t x,
5271 uint32_t y,
5272 uint32_t z)
5273 {
5274 struct radv_dispatch_info info = {};
5275
5276 info.blocks[0] = x;
5277 info.blocks[1] = y;
5278 info.blocks[2] = z;
5279 info.unaligned = 1;
5280
5281 radv_dispatch(cmd_buffer, &info);
5282 }
5283
5284 void
5285 radv_cmd_buffer_end_render_pass(struct radv_cmd_buffer *cmd_buffer)
5286 {
5287 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
5288 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
5289
5290 cmd_buffer->state.pass = NULL;
5291 cmd_buffer->state.subpass = NULL;
5292 cmd_buffer->state.attachments = NULL;
5293 cmd_buffer->state.framebuffer = NULL;
5294 cmd_buffer->state.subpass_sample_locs = NULL;
5295 }
5296
5297 void radv_CmdEndRenderPass(
5298 VkCommandBuffer commandBuffer)
5299 {
5300 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5301
5302 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
5303
5304 radv_cmd_buffer_end_subpass(cmd_buffer);
5305
5306 radv_cmd_buffer_end_render_pass(cmd_buffer);
5307 }
5308
5309 void radv_CmdEndRenderPass2(
5310 VkCommandBuffer commandBuffer,
5311 const VkSubpassEndInfo* pSubpassEndInfo)
5312 {
5313 radv_CmdEndRenderPass(commandBuffer);
5314 }
5315
5316 /*
5317 * For HTILE we have the following interesting clear words:
5318 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
5319 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
5320 * 0xfffffff0: Clear depth to 1.0
5321 * 0x00000000: Clear depth to 0.0
5322 */
5323 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
5324 struct radv_image *image,
5325 const VkImageSubresourceRange *range)
5326 {
5327 assert(range->baseMipLevel == 0);
5328 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
5329 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
5330 struct radv_cmd_state *state = &cmd_buffer->state;
5331 uint32_t htile_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
5332 VkClearDepthStencilValue value = {};
5333 struct radv_barrier_data barrier = {};
5334
5335 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5336 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5337
5338 barrier.layout_transitions.init_mask_ram = 1;
5339 radv_describe_layout_transition(cmd_buffer, &barrier);
5340
5341 state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, htile_value);
5342
5343 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5344
5345 if (vk_format_is_stencil(image->vk_format))
5346 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
5347
5348 radv_set_ds_clear_metadata(cmd_buffer, image, range, value, aspects);
5349
5350 if (radv_image_is_tc_compat_htile(image)) {
5351 /* Initialize the TC-compat metada value to 0 because by
5352 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
5353 * need have to conditionally update its value when performing
5354 * a fast depth clear.
5355 */
5356 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, range, 0);
5357 }
5358 }
5359
5360 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
5361 struct radv_image *image,
5362 VkImageLayout src_layout,
5363 bool src_render_loop,
5364 VkImageLayout dst_layout,
5365 bool dst_render_loop,
5366 unsigned src_queue_mask,
5367 unsigned dst_queue_mask,
5368 const VkImageSubresourceRange *range,
5369 struct radv_sample_locations_state *sample_locs)
5370 {
5371 if (!radv_image_has_htile(image))
5372 return;
5373
5374 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5375 radv_initialize_htile(cmd_buffer, image, range);
5376 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5377 radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5378 radv_initialize_htile(cmd_buffer, image, range);
5379 } else if (radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5380 !radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5381 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5382 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5383
5384 radv_decompress_depth_stencil(cmd_buffer, image, range,
5385 sample_locs);
5386
5387 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5388 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5389 }
5390 }
5391
5392 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
5393 struct radv_image *image,
5394 const VkImageSubresourceRange *range,
5395 uint32_t value)
5396 {
5397 struct radv_cmd_state *state = &cmd_buffer->state;
5398 struct radv_barrier_data barrier = {};
5399
5400 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5401 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5402
5403 barrier.layout_transitions.init_mask_ram = 1;
5404 radv_describe_layout_transition(cmd_buffer, &barrier);
5405
5406 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, range, value);
5407
5408 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5409 }
5410
5411 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
5412 struct radv_image *image,
5413 const VkImageSubresourceRange *range)
5414 {
5415 struct radv_cmd_state *state = &cmd_buffer->state;
5416 static const uint32_t fmask_clear_values[4] = {
5417 0x00000000,
5418 0x02020202,
5419 0xE4E4E4E4,
5420 0x76543210
5421 };
5422 uint32_t log2_samples = util_logbase2(image->info.samples);
5423 uint32_t value = fmask_clear_values[log2_samples];
5424 struct radv_barrier_data barrier = {};
5425
5426 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5427 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5428
5429 barrier.layout_transitions.init_mask_ram = 1;
5430 radv_describe_layout_transition(cmd_buffer, &barrier);
5431
5432 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, range, value);
5433
5434 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5435 }
5436
5437 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
5438 struct radv_image *image,
5439 const VkImageSubresourceRange *range, uint32_t value)
5440 {
5441 struct radv_cmd_state *state = &cmd_buffer->state;
5442 struct radv_barrier_data barrier = {};
5443 unsigned size = 0;
5444
5445 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5446 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5447
5448 barrier.layout_transitions.init_mask_ram = 1;
5449 radv_describe_layout_transition(cmd_buffer, &barrier);
5450
5451 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
5452
5453 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) {
5454 /* When DCC is enabled with mipmaps, some levels might not
5455 * support fast clears and we have to initialize them as "fully
5456 * expanded".
5457 */
5458 /* Compute the size of all fast clearable DCC levels. */
5459 for (unsigned i = 0; i < image->planes[0].surface.num_dcc_levels; i++) {
5460 struct legacy_surf_level *surf_level =
5461 &image->planes[0].surface.u.legacy.level[i];
5462 unsigned dcc_fast_clear_size =
5463 surf_level->dcc_slice_fast_clear_size * image->info.array_size;
5464
5465 if (!dcc_fast_clear_size)
5466 break;
5467
5468 size = surf_level->dcc_offset + dcc_fast_clear_size;
5469 }
5470
5471 /* Initialize the mipmap levels without DCC. */
5472 if (size != image->planes[0].surface.dcc_size) {
5473 state->flush_bits |=
5474 radv_fill_buffer(cmd_buffer, image->bo,
5475 image->offset + image->dcc_offset + size,
5476 image->planes[0].surface.dcc_size - size,
5477 0xffffffff);
5478 }
5479 }
5480
5481 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5482 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5483 }
5484
5485 /**
5486 * Initialize DCC/FMASK/CMASK metadata for a color image.
5487 */
5488 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
5489 struct radv_image *image,
5490 VkImageLayout src_layout,
5491 bool src_render_loop,
5492 VkImageLayout dst_layout,
5493 bool dst_render_loop,
5494 unsigned src_queue_mask,
5495 unsigned dst_queue_mask,
5496 const VkImageSubresourceRange *range)
5497 {
5498 if (radv_image_has_cmask(image)) {
5499 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5500
5501 /* TODO: clarify this. */
5502 if (radv_image_has_fmask(image)) {
5503 value = 0xccccccccu;
5504 }
5505
5506 radv_initialise_cmask(cmd_buffer, image, range, value);
5507 }
5508
5509 if (radv_image_has_fmask(image)) {
5510 radv_initialize_fmask(cmd_buffer, image, range);
5511 }
5512
5513 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5514 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5515 bool need_decompress_pass = false;
5516
5517 if (radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout,
5518 dst_render_loop,
5519 dst_queue_mask)) {
5520 value = 0x20202020u;
5521 need_decompress_pass = true;
5522 }
5523
5524 radv_initialize_dcc(cmd_buffer, image, range, value);
5525
5526 radv_update_fce_metadata(cmd_buffer, image, range,
5527 need_decompress_pass);
5528 }
5529
5530 if (radv_image_has_cmask(image) ||
5531 radv_dcc_enabled(image, range->baseMipLevel)) {
5532 uint32_t color_values[2] = {};
5533 radv_set_color_clear_metadata(cmd_buffer, image, range,
5534 color_values);
5535 }
5536 }
5537
5538 /**
5539 * Handle color image transitions for DCC/FMASK/CMASK.
5540 */
5541 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
5542 struct radv_image *image,
5543 VkImageLayout src_layout,
5544 bool src_render_loop,
5545 VkImageLayout dst_layout,
5546 bool dst_render_loop,
5547 unsigned src_queue_mask,
5548 unsigned dst_queue_mask,
5549 const VkImageSubresourceRange *range)
5550 {
5551 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5552 radv_init_color_image_metadata(cmd_buffer, image,
5553 src_layout, src_render_loop,
5554 dst_layout, dst_render_loop,
5555 src_queue_mask, dst_queue_mask,
5556 range);
5557 return;
5558 }
5559
5560 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5561 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
5562 radv_initialize_dcc(cmd_buffer, image, range, 0xffffffffu);
5563 } else if (radv_layout_dcc_compressed(cmd_buffer->device, image, src_layout, src_render_loop, src_queue_mask) &&
5564 !radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout, dst_render_loop, dst_queue_mask)) {
5565 radv_decompress_dcc(cmd_buffer, image, range);
5566 } else if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
5567 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5568 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5569 }
5570 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
5571 bool fce_eliminate = false, fmask_expand = false;
5572
5573 if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
5574 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5575 fce_eliminate = true;
5576 }
5577
5578 if (radv_image_has_fmask(image)) {
5579 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
5580 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
5581 /* A FMASK decompress is required before doing
5582 * a MSAA decompress using FMASK.
5583 */
5584 fmask_expand = true;
5585 }
5586 }
5587
5588 if (fce_eliminate || fmask_expand)
5589 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5590
5591 if (fmask_expand) {
5592 struct radv_barrier_data barrier = {};
5593 barrier.layout_transitions.fmask_color_expand = 1;
5594 radv_describe_layout_transition(cmd_buffer, &barrier);
5595
5596 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
5597 }
5598 }
5599 }
5600
5601 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
5602 struct radv_image *image,
5603 VkImageLayout src_layout,
5604 bool src_render_loop,
5605 VkImageLayout dst_layout,
5606 bool dst_render_loop,
5607 uint32_t src_family,
5608 uint32_t dst_family,
5609 const VkImageSubresourceRange *range,
5610 struct radv_sample_locations_state *sample_locs)
5611 {
5612 if (image->exclusive && src_family != dst_family) {
5613 /* This is an acquire or a release operation and there will be
5614 * a corresponding release/acquire. Do the transition in the
5615 * most flexible queue. */
5616
5617 assert(src_family == cmd_buffer->queue_family_index ||
5618 dst_family == cmd_buffer->queue_family_index);
5619
5620 if (src_family == VK_QUEUE_FAMILY_EXTERNAL ||
5621 src_family == VK_QUEUE_FAMILY_FOREIGN_EXT)
5622 return;
5623
5624 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
5625 return;
5626
5627 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
5628 (src_family == RADV_QUEUE_GENERAL ||
5629 dst_family == RADV_QUEUE_GENERAL))
5630 return;
5631 }
5632
5633 if (src_layout == dst_layout)
5634 return;
5635
5636 unsigned src_queue_mask =
5637 radv_image_queue_family_mask(image, src_family,
5638 cmd_buffer->queue_family_index);
5639 unsigned dst_queue_mask =
5640 radv_image_queue_family_mask(image, dst_family,
5641 cmd_buffer->queue_family_index);
5642
5643 if (vk_format_is_depth(image->vk_format)) {
5644 radv_handle_depth_image_transition(cmd_buffer, image,
5645 src_layout, src_render_loop,
5646 dst_layout, dst_render_loop,
5647 src_queue_mask, dst_queue_mask,
5648 range, sample_locs);
5649 } else {
5650 radv_handle_color_image_transition(cmd_buffer, image,
5651 src_layout, src_render_loop,
5652 dst_layout, dst_render_loop,
5653 src_queue_mask, dst_queue_mask,
5654 range);
5655 }
5656 }
5657
5658 struct radv_barrier_info {
5659 enum rgp_barrier_reason reason;
5660 uint32_t eventCount;
5661 const VkEvent *pEvents;
5662 VkPipelineStageFlags srcStageMask;
5663 VkPipelineStageFlags dstStageMask;
5664 };
5665
5666 static void
5667 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
5668 uint32_t memoryBarrierCount,
5669 const VkMemoryBarrier *pMemoryBarriers,
5670 uint32_t bufferMemoryBarrierCount,
5671 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
5672 uint32_t imageMemoryBarrierCount,
5673 const VkImageMemoryBarrier *pImageMemoryBarriers,
5674 const struct radv_barrier_info *info)
5675 {
5676 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5677 enum radv_cmd_flush_bits src_flush_bits = 0;
5678 enum radv_cmd_flush_bits dst_flush_bits = 0;
5679
5680 radv_describe_barrier_start(cmd_buffer, info->reason);
5681
5682 for (unsigned i = 0; i < info->eventCount; ++i) {
5683 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
5684 uint64_t va = radv_buffer_get_va(event->bo);
5685
5686 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5687
5688 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
5689
5690 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
5691 assert(cmd_buffer->cs->cdw <= cdw_max);
5692 }
5693
5694 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
5695 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
5696 NULL);
5697 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
5698 NULL);
5699 }
5700
5701 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
5702 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
5703 NULL);
5704 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
5705 NULL);
5706 }
5707
5708 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5709 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5710
5711 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
5712 image);
5713 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
5714 image);
5715 }
5716
5717 /* The Vulkan spec 1.1.98 says:
5718 *
5719 * "An execution dependency with only
5720 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
5721 * will only prevent that stage from executing in subsequently
5722 * submitted commands. As this stage does not perform any actual
5723 * execution, this is not observable - in effect, it does not delay
5724 * processing of subsequent commands. Similarly an execution dependency
5725 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
5726 * will effectively not wait for any prior commands to complete."
5727 */
5728 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
5729 radv_stage_flush(cmd_buffer, info->srcStageMask);
5730 cmd_buffer->state.flush_bits |= src_flush_bits;
5731
5732 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5733 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5734
5735 const struct VkSampleLocationsInfoEXT *sample_locs_info =
5736 vk_find_struct_const(pImageMemoryBarriers[i].pNext,
5737 SAMPLE_LOCATIONS_INFO_EXT);
5738 struct radv_sample_locations_state sample_locations = {};
5739
5740 if (sample_locs_info) {
5741 assert(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
5742 sample_locations.per_pixel = sample_locs_info->sampleLocationsPerPixel;
5743 sample_locations.grid_size = sample_locs_info->sampleLocationGridSize;
5744 sample_locations.count = sample_locs_info->sampleLocationsCount;
5745 typed_memcpy(&sample_locations.locations[0],
5746 sample_locs_info->pSampleLocations,
5747 sample_locs_info->sampleLocationsCount);
5748 }
5749
5750 radv_handle_image_transition(cmd_buffer, image,
5751 pImageMemoryBarriers[i].oldLayout,
5752 false, /* Outside of a renderpass we are never in a renderloop */
5753 pImageMemoryBarriers[i].newLayout,
5754 false, /* Outside of a renderpass we are never in a renderloop */
5755 pImageMemoryBarriers[i].srcQueueFamilyIndex,
5756 pImageMemoryBarriers[i].dstQueueFamilyIndex,
5757 &pImageMemoryBarriers[i].subresourceRange,
5758 sample_locs_info ? &sample_locations : NULL);
5759 }
5760
5761 /* Make sure CP DMA is idle because the driver might have performed a
5762 * DMA operation for copying or filling buffers/images.
5763 */
5764 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5765 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5766 si_cp_dma_wait_for_idle(cmd_buffer);
5767
5768 cmd_buffer->state.flush_bits |= dst_flush_bits;
5769
5770 radv_describe_barrier_end(cmd_buffer);
5771 }
5772
5773 void radv_CmdPipelineBarrier(
5774 VkCommandBuffer commandBuffer,
5775 VkPipelineStageFlags srcStageMask,
5776 VkPipelineStageFlags destStageMask,
5777 VkBool32 byRegion,
5778 uint32_t memoryBarrierCount,
5779 const VkMemoryBarrier* pMemoryBarriers,
5780 uint32_t bufferMemoryBarrierCount,
5781 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5782 uint32_t imageMemoryBarrierCount,
5783 const VkImageMemoryBarrier* pImageMemoryBarriers)
5784 {
5785 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5786 struct radv_barrier_info info;
5787
5788 info.reason = RGP_BARRIER_EXTERNAL_CMD_PIPELINE_BARRIER;
5789 info.eventCount = 0;
5790 info.pEvents = NULL;
5791 info.srcStageMask = srcStageMask;
5792 info.dstStageMask = destStageMask;
5793
5794 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5795 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5796 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5797 }
5798
5799
5800 static void write_event(struct radv_cmd_buffer *cmd_buffer,
5801 struct radv_event *event,
5802 VkPipelineStageFlags stageMask,
5803 unsigned value)
5804 {
5805 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5806 uint64_t va = radv_buffer_get_va(event->bo);
5807
5808 si_emit_cache_flush(cmd_buffer);
5809
5810 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5811
5812 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 21);
5813
5814 /* Flags that only require a top-of-pipe event. */
5815 VkPipelineStageFlags top_of_pipe_flags =
5816 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
5817
5818 /* Flags that only require a post-index-fetch event. */
5819 VkPipelineStageFlags post_index_fetch_flags =
5820 top_of_pipe_flags |
5821 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
5822 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
5823
5824 /* Make sure CP DMA is idle because the driver might have performed a
5825 * DMA operation for copying or filling buffers/images.
5826 */
5827 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5828 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5829 si_cp_dma_wait_for_idle(cmd_buffer);
5830
5831 /* TODO: Emit EOS events for syncing PS/CS stages. */
5832
5833 if (!(stageMask & ~top_of_pipe_flags)) {
5834 /* Just need to sync the PFP engine. */
5835 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5836 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5837 S_370_WR_CONFIRM(1) |
5838 S_370_ENGINE_SEL(V_370_PFP));
5839 radeon_emit(cs, va);
5840 radeon_emit(cs, va >> 32);
5841 radeon_emit(cs, value);
5842 } else if (!(stageMask & ~post_index_fetch_flags)) {
5843 /* Sync ME because PFP reads index and indirect buffers. */
5844 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5845 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5846 S_370_WR_CONFIRM(1) |
5847 S_370_ENGINE_SEL(V_370_ME));
5848 radeon_emit(cs, va);
5849 radeon_emit(cs, va >> 32);
5850 radeon_emit(cs, value);
5851 } else {
5852 /* Otherwise, sync all prior GPU work using an EOP event. */
5853 si_cs_emit_write_event_eop(cs,
5854 cmd_buffer->device->physical_device->rad_info.chip_class,
5855 radv_cmd_buffer_uses_mec(cmd_buffer),
5856 V_028A90_BOTTOM_OF_PIPE_TS, 0,
5857 EOP_DST_SEL_MEM,
5858 EOP_DATA_SEL_VALUE_32BIT, va, value,
5859 cmd_buffer->gfx9_eop_bug_va);
5860 }
5861
5862 assert(cmd_buffer->cs->cdw <= cdw_max);
5863 }
5864
5865 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
5866 VkEvent _event,
5867 VkPipelineStageFlags stageMask)
5868 {
5869 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5870 RADV_FROM_HANDLE(radv_event, event, _event);
5871
5872 write_event(cmd_buffer, event, stageMask, 1);
5873 }
5874
5875 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
5876 VkEvent _event,
5877 VkPipelineStageFlags stageMask)
5878 {
5879 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5880 RADV_FROM_HANDLE(radv_event, event, _event);
5881
5882 write_event(cmd_buffer, event, stageMask, 0);
5883 }
5884
5885 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
5886 uint32_t eventCount,
5887 const VkEvent* pEvents,
5888 VkPipelineStageFlags srcStageMask,
5889 VkPipelineStageFlags dstStageMask,
5890 uint32_t memoryBarrierCount,
5891 const VkMemoryBarrier* pMemoryBarriers,
5892 uint32_t bufferMemoryBarrierCount,
5893 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5894 uint32_t imageMemoryBarrierCount,
5895 const VkImageMemoryBarrier* pImageMemoryBarriers)
5896 {
5897 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5898 struct radv_barrier_info info;
5899
5900 info.reason = RGP_BARRIER_EXTERNAL_CMD_WAIT_EVENTS;
5901 info.eventCount = eventCount;
5902 info.pEvents = pEvents;
5903 info.srcStageMask = 0;
5904
5905 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5906 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5907 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5908 }
5909
5910
5911 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
5912 uint32_t deviceMask)
5913 {
5914 /* No-op */
5915 }
5916
5917 /* VK_EXT_conditional_rendering */
5918 void radv_CmdBeginConditionalRenderingEXT(
5919 VkCommandBuffer commandBuffer,
5920 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
5921 {
5922 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5923 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
5924 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5925 bool draw_visible = true;
5926 uint64_t pred_value = 0;
5927 uint64_t va, new_va;
5928 unsigned pred_offset;
5929
5930 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
5931
5932 /* By default, if the 32-bit value at offset in buffer memory is zero,
5933 * then the rendering commands are discarded, otherwise they are
5934 * executed as normal. If the inverted flag is set, all commands are
5935 * discarded if the value is non zero.
5936 */
5937 if (pConditionalRenderingBegin->flags &
5938 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
5939 draw_visible = false;
5940 }
5941
5942 si_emit_cache_flush(cmd_buffer);
5943
5944 /* From the Vulkan spec 1.1.107:
5945 *
5946 * "If the 32-bit value at offset in buffer memory is zero, then the
5947 * rendering commands are discarded, otherwise they are executed as
5948 * normal. If the value of the predicate in buffer memory changes while
5949 * conditional rendering is active, the rendering commands may be
5950 * discarded in an implementation-dependent way. Some implementations
5951 * may latch the value of the predicate upon beginning conditional
5952 * rendering while others may read it before every rendering command."
5953 *
5954 * But, the AMD hardware treats the predicate as a 64-bit value which
5955 * means we need a workaround in the driver. Luckily, it's not required
5956 * to support if the value changes when predication is active.
5957 *
5958 * The workaround is as follows:
5959 * 1) allocate a 64-value in the upload BO and initialize it to 0
5960 * 2) copy the 32-bit predicate value to the upload BO
5961 * 3) use the new allocated VA address for predication
5962 *
5963 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
5964 * in ME (+ sync PFP) instead of PFP.
5965 */
5966 radv_cmd_buffer_upload_data(cmd_buffer, 8, 16, &pred_value, &pred_offset);
5967
5968 new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
5969
5970 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5971 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5972 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
5973 COPY_DATA_WR_CONFIRM);
5974 radeon_emit(cs, va);
5975 radeon_emit(cs, va >> 32);
5976 radeon_emit(cs, new_va);
5977 radeon_emit(cs, new_va >> 32);
5978
5979 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
5980 radeon_emit(cs, 0);
5981
5982 /* Enable predication for this command buffer. */
5983 si_emit_set_predication_state(cmd_buffer, draw_visible, new_va);
5984 cmd_buffer->state.predicating = true;
5985
5986 /* Store conditional rendering user info. */
5987 cmd_buffer->state.predication_type = draw_visible;
5988 cmd_buffer->state.predication_va = new_va;
5989 }
5990
5991 void radv_CmdEndConditionalRenderingEXT(
5992 VkCommandBuffer commandBuffer)
5993 {
5994 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5995
5996 /* Disable predication for this command buffer. */
5997 si_emit_set_predication_state(cmd_buffer, false, 0);
5998 cmd_buffer->state.predicating = false;
5999
6000 /* Reset conditional rendering user info. */
6001 cmd_buffer->state.predication_type = -1;
6002 cmd_buffer->state.predication_va = 0;
6003 }
6004
6005 /* VK_EXT_transform_feedback */
6006 void radv_CmdBindTransformFeedbackBuffersEXT(
6007 VkCommandBuffer commandBuffer,
6008 uint32_t firstBinding,
6009 uint32_t bindingCount,
6010 const VkBuffer* pBuffers,
6011 const VkDeviceSize* pOffsets,
6012 const VkDeviceSize* pSizes)
6013 {
6014 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6015 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
6016 uint8_t enabled_mask = 0;
6017
6018 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
6019 for (uint32_t i = 0; i < bindingCount; i++) {
6020 uint32_t idx = firstBinding + i;
6021
6022 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
6023 sb[idx].offset = pOffsets[i];
6024
6025 if (!pSizes || pSizes[i] == VK_WHOLE_SIZE) {
6026 sb[idx].size = sb[idx].buffer->size - sb[idx].offset;
6027 } else {
6028 sb[idx].size = pSizes[i];
6029 }
6030
6031 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
6032 sb[idx].buffer->bo);
6033
6034 enabled_mask |= 1 << idx;
6035 }
6036
6037 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
6038
6039 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
6040 }
6041
6042 static void
6043 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
6044 {
6045 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6046 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6047
6048 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
6049 radeon_emit(cs,
6050 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
6051 S_028B94_RAST_STREAM(0) |
6052 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
6053 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
6054 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
6055 radeon_emit(cs, so->hw_enabled_mask &
6056 so->enabled_stream_buffers_mask);
6057
6058 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6059 }
6060
6061 static void
6062 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
6063 {
6064 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6065 bool old_streamout_enabled = so->streamout_enabled;
6066 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
6067
6068 so->streamout_enabled = enable;
6069
6070 so->hw_enabled_mask = so->enabled_mask |
6071 (so->enabled_mask << 4) |
6072 (so->enabled_mask << 8) |
6073 (so->enabled_mask << 12);
6074
6075 if (!cmd_buffer->device->physical_device->use_ngg_streamout &&
6076 ((old_streamout_enabled != so->streamout_enabled) ||
6077 (old_hw_enabled_mask != so->hw_enabled_mask)))
6078 radv_emit_streamout_enable(cmd_buffer);
6079
6080 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6081 cmd_buffer->gds_needed = true;
6082 cmd_buffer->gds_oa_needed = true;
6083 }
6084 }
6085
6086 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
6087 {
6088 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6089 unsigned reg_strmout_cntl;
6090
6091 /* The register is at different places on different ASICs. */
6092 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
6093 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
6094 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
6095 } else {
6096 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
6097 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
6098 }
6099
6100 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
6101 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
6102
6103 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
6104 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
6105 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
6106 radeon_emit(cs, 0);
6107 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
6108 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
6109 radeon_emit(cs, 4); /* poll interval */
6110 }
6111
6112 static void
6113 radv_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
6114 uint32_t firstCounterBuffer,
6115 uint32_t counterBufferCount,
6116 const VkBuffer *pCounterBuffers,
6117 const VkDeviceSize *pCounterBufferOffsets)
6118
6119 {
6120 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
6121 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6122 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6123 uint32_t i;
6124
6125 radv_flush_vgt_streamout(cmd_buffer);
6126
6127 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6128 for_each_bit(i, so->enabled_mask) {
6129 int32_t counter_buffer_idx = i - firstCounterBuffer;
6130 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6131 counter_buffer_idx = -1;
6132
6133 /* AMD GCN binds streamout buffers as shader resources.
6134 * VGT only counts primitives and tells the shader through
6135 * SGPRs what to do.
6136 */
6137 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
6138 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
6139 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
6140
6141 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6142
6143 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6144 /* The array of counter buffers is optional. */
6145 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6146 uint64_t va = radv_buffer_get_va(buffer->bo);
6147
6148 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6149
6150 /* Append */
6151 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6152 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6153 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6154 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
6155 radeon_emit(cs, 0); /* unused */
6156 radeon_emit(cs, 0); /* unused */
6157 radeon_emit(cs, va); /* src address lo */
6158 radeon_emit(cs, va >> 32); /* src address hi */
6159
6160 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6161 } else {
6162 /* Start from the beginning. */
6163 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6164 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6165 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6166 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
6167 radeon_emit(cs, 0); /* unused */
6168 radeon_emit(cs, 0); /* unused */
6169 radeon_emit(cs, 0); /* unused */
6170 radeon_emit(cs, 0); /* unused */
6171 }
6172 }
6173
6174 radv_set_streamout_enable(cmd_buffer, true);
6175 }
6176
6177 static void
6178 gfx10_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
6179 uint32_t firstCounterBuffer,
6180 uint32_t counterBufferCount,
6181 const VkBuffer *pCounterBuffers,
6182 const VkDeviceSize *pCounterBufferOffsets)
6183 {
6184 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6185 unsigned last_target = util_last_bit(so->enabled_mask) - 1;
6186 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6187 uint32_t i;
6188
6189 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6190 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6191
6192 /* Sync because the next streamout operation will overwrite GDS and we
6193 * have to make sure it's idle.
6194 * TODO: Improve by tracking if there is a streamout operation in
6195 * flight.
6196 */
6197 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
6198 si_emit_cache_flush(cmd_buffer);
6199
6200 for_each_bit(i, so->enabled_mask) {
6201 int32_t counter_buffer_idx = i - firstCounterBuffer;
6202 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6203 counter_buffer_idx = -1;
6204
6205 bool append = counter_buffer_idx >= 0 &&
6206 pCounterBuffers && pCounterBuffers[counter_buffer_idx];
6207 uint64_t va = 0;
6208
6209 if (append) {
6210 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6211
6212 va += radv_buffer_get_va(buffer->bo);
6213 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6214
6215 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6216 }
6217
6218 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
6219 radeon_emit(cs, S_411_SRC_SEL(append ? V_411_SRC_ADDR_TC_L2 : V_411_DATA) |
6220 S_411_DST_SEL(V_411_GDS) |
6221 S_411_CP_SYNC(i == last_target));
6222 radeon_emit(cs, va);
6223 radeon_emit(cs, va >> 32);
6224 radeon_emit(cs, 4 * i); /* destination in GDS */
6225 radeon_emit(cs, 0);
6226 radeon_emit(cs, S_414_BYTE_COUNT_GFX9(4) |
6227 S_414_DISABLE_WR_CONFIRM_GFX9(i != last_target));
6228 }
6229
6230 radv_set_streamout_enable(cmd_buffer, true);
6231 }
6232
6233 void radv_CmdBeginTransformFeedbackEXT(
6234 VkCommandBuffer commandBuffer,
6235 uint32_t firstCounterBuffer,
6236 uint32_t counterBufferCount,
6237 const VkBuffer* pCounterBuffers,
6238 const VkDeviceSize* pCounterBufferOffsets)
6239 {
6240 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6241
6242 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6243 gfx10_emit_streamout_begin(cmd_buffer,
6244 firstCounterBuffer, counterBufferCount,
6245 pCounterBuffers, pCounterBufferOffsets);
6246 } else {
6247 radv_emit_streamout_begin(cmd_buffer,
6248 firstCounterBuffer, counterBufferCount,
6249 pCounterBuffers, pCounterBufferOffsets);
6250 }
6251 }
6252
6253 static void
6254 radv_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6255 uint32_t firstCounterBuffer,
6256 uint32_t counterBufferCount,
6257 const VkBuffer *pCounterBuffers,
6258 const VkDeviceSize *pCounterBufferOffsets)
6259 {
6260 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6261 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6262 uint32_t i;
6263
6264 radv_flush_vgt_streamout(cmd_buffer);
6265
6266 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6267 for_each_bit(i, so->enabled_mask) {
6268 int32_t counter_buffer_idx = i - firstCounterBuffer;
6269 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6270 counter_buffer_idx = -1;
6271
6272 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6273 /* The array of counters buffer is optional. */
6274 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6275 uint64_t va = radv_buffer_get_va(buffer->bo);
6276
6277 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6278
6279 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6280 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6281 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6282 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
6283 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
6284 radeon_emit(cs, va); /* dst address lo */
6285 radeon_emit(cs, va >> 32); /* dst address hi */
6286 radeon_emit(cs, 0); /* unused */
6287 radeon_emit(cs, 0); /* unused */
6288
6289 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6290 }
6291
6292 /* Deactivate transform feedback by zeroing the buffer size.
6293 * The counters (primitives generated, primitives emitted) may
6294 * be enabled even if there is not buffer bound. This ensures
6295 * that the primitives-emitted query won't increment.
6296 */
6297 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
6298
6299 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6300 }
6301
6302 radv_set_streamout_enable(cmd_buffer, false);
6303 }
6304
6305 static void
6306 gfx10_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6307 uint32_t firstCounterBuffer,
6308 uint32_t counterBufferCount,
6309 const VkBuffer *pCounterBuffers,
6310 const VkDeviceSize *pCounterBufferOffsets)
6311 {
6312 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6313 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6314 uint32_t i;
6315
6316 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6317 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6318
6319 for_each_bit(i, so->enabled_mask) {
6320 int32_t counter_buffer_idx = i - firstCounterBuffer;
6321 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6322 counter_buffer_idx = -1;
6323
6324 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6325 /* The array of counters buffer is optional. */
6326 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6327 uint64_t va = radv_buffer_get_va(buffer->bo);
6328
6329 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6330
6331 si_cs_emit_write_event_eop(cs,
6332 cmd_buffer->device->physical_device->rad_info.chip_class,
6333 radv_cmd_buffer_uses_mec(cmd_buffer),
6334 V_028A90_PS_DONE, 0,
6335 EOP_DST_SEL_TC_L2,
6336 EOP_DATA_SEL_GDS,
6337 va, EOP_DATA_GDS(i, 1), 0);
6338
6339 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6340 }
6341 }
6342
6343 radv_set_streamout_enable(cmd_buffer, false);
6344 }
6345
6346 void radv_CmdEndTransformFeedbackEXT(
6347 VkCommandBuffer commandBuffer,
6348 uint32_t firstCounterBuffer,
6349 uint32_t counterBufferCount,
6350 const VkBuffer* pCounterBuffers,
6351 const VkDeviceSize* pCounterBufferOffsets)
6352 {
6353 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6354
6355 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6356 gfx10_emit_streamout_end(cmd_buffer,
6357 firstCounterBuffer, counterBufferCount,
6358 pCounterBuffers, pCounterBufferOffsets);
6359 } else {
6360 radv_emit_streamout_end(cmd_buffer,
6361 firstCounterBuffer, counterBufferCount,
6362 pCounterBuffers, pCounterBufferOffsets);
6363 }
6364 }
6365
6366 void radv_CmdDrawIndirectByteCountEXT(
6367 VkCommandBuffer commandBuffer,
6368 uint32_t instanceCount,
6369 uint32_t firstInstance,
6370 VkBuffer _counterBuffer,
6371 VkDeviceSize counterBufferOffset,
6372 uint32_t counterOffset,
6373 uint32_t vertexStride)
6374 {
6375 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6376 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
6377 struct radv_draw_info info = {};
6378
6379 info.instance_count = instanceCount;
6380 info.first_instance = firstInstance;
6381 info.strmout_buffer = counterBuffer;
6382 info.strmout_buffer_offset = counterBufferOffset;
6383 info.stride = vertexStride;
6384
6385 radv_draw(cmd_buffer, &info);
6386 }
6387
6388 /* VK_AMD_buffer_marker */
6389 void radv_CmdWriteBufferMarkerAMD(
6390 VkCommandBuffer commandBuffer,
6391 VkPipelineStageFlagBits pipelineStage,
6392 VkBuffer dstBuffer,
6393 VkDeviceSize dstOffset,
6394 uint32_t marker)
6395 {
6396 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6397 RADV_FROM_HANDLE(radv_buffer, buffer, dstBuffer);
6398 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6399 uint64_t va = radv_buffer_get_va(buffer->bo) + dstOffset;
6400
6401 si_emit_cache_flush(cmd_buffer);
6402
6403 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 12);
6404
6405 if (!(pipelineStage & ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT)) {
6406 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
6407 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
6408 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
6409 COPY_DATA_WR_CONFIRM);
6410 radeon_emit(cs, marker);
6411 radeon_emit(cs, 0);
6412 radeon_emit(cs, va);
6413 radeon_emit(cs, va >> 32);
6414 } else {
6415 si_cs_emit_write_event_eop(cs,
6416 cmd_buffer->device->physical_device->rad_info.chip_class,
6417 radv_cmd_buffer_uses_mec(cmd_buffer),
6418 V_028A90_BOTTOM_OF_PIPE_TS, 0,
6419 EOP_DST_SEL_MEM,
6420 EOP_DATA_SEL_VALUE_32BIT,
6421 va, marker,
6422 cmd_buffer->gfx9_eop_bug_va);
6423 }
6424
6425 assert(cmd_buffer->cs->cdw <= cdw_max);
6426 }