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radv: add support for dynamic vertex input binding stride
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 bool src_render_loop,
58 VkImageLayout dst_layout,
59 bool dst_render_loop,
60 uint32_t src_family,
61 uint32_t dst_family,
62 const VkImageSubresourceRange *range,
63 struct radv_sample_locations_state *sample_locs);
64
65 const struct radv_dynamic_state default_dynamic_state = {
66 .viewport = {
67 .count = 0,
68 },
69 .scissor = {
70 .count = 0,
71 },
72 .line_width = 1.0f,
73 .depth_bias = {
74 .bias = 0.0f,
75 .clamp = 0.0f,
76 .slope = 0.0f,
77 },
78 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
79 .depth_bounds = {
80 .min = 0.0f,
81 .max = 1.0f,
82 },
83 .stencil_compare_mask = {
84 .front = ~0u,
85 .back = ~0u,
86 },
87 .stencil_write_mask = {
88 .front = ~0u,
89 .back = ~0u,
90 },
91 .stencil_reference = {
92 .front = 0u,
93 .back = 0u,
94 },
95 .line_stipple = {
96 .factor = 0u,
97 .pattern = 0u,
98 },
99 .cull_mode = 0u,
100 .front_face = 0u,
101 .primitive_topology = 0u,
102 };
103
104 static void
105 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
106 const struct radv_dynamic_state *src)
107 {
108 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
109 uint32_t copy_mask = src->mask;
110 uint32_t dest_mask = 0;
111
112 dest->discard_rectangle.count = src->discard_rectangle.count;
113 dest->sample_location.count = src->sample_location.count;
114
115 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
116 if (dest->viewport.count != src->viewport.count) {
117 dest->viewport.count = src->viewport.count;
118 dest_mask |= RADV_DYNAMIC_VIEWPORT;
119 }
120
121 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
122 src->viewport.count * sizeof(VkViewport))) {
123 typed_memcpy(dest->viewport.viewports,
124 src->viewport.viewports,
125 src->viewport.count);
126 dest_mask |= RADV_DYNAMIC_VIEWPORT;
127 }
128 }
129
130 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
131 if (dest->scissor.count != src->scissor.count) {
132 dest->scissor.count = src->scissor.count;
133 dest_mask |= RADV_DYNAMIC_SCISSOR;
134 }
135
136 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
137 src->scissor.count * sizeof(VkRect2D))) {
138 typed_memcpy(dest->scissor.scissors,
139 src->scissor.scissors, src->scissor.count);
140 dest_mask |= RADV_DYNAMIC_SCISSOR;
141 }
142 }
143
144 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
145 if (dest->line_width != src->line_width) {
146 dest->line_width = src->line_width;
147 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
148 }
149 }
150
151 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
152 if (memcmp(&dest->depth_bias, &src->depth_bias,
153 sizeof(src->depth_bias))) {
154 dest->depth_bias = src->depth_bias;
155 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
156 }
157 }
158
159 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
160 if (memcmp(&dest->blend_constants, &src->blend_constants,
161 sizeof(src->blend_constants))) {
162 typed_memcpy(dest->blend_constants,
163 src->blend_constants, 4);
164 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
165 }
166 }
167
168 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
169 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
170 sizeof(src->depth_bounds))) {
171 dest->depth_bounds = src->depth_bounds;
172 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
173 }
174 }
175
176 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
177 if (memcmp(&dest->stencil_compare_mask,
178 &src->stencil_compare_mask,
179 sizeof(src->stencil_compare_mask))) {
180 dest->stencil_compare_mask = src->stencil_compare_mask;
181 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
182 }
183 }
184
185 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
186 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
187 sizeof(src->stencil_write_mask))) {
188 dest->stencil_write_mask = src->stencil_write_mask;
189 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
190 }
191 }
192
193 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
194 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
195 sizeof(src->stencil_reference))) {
196 dest->stencil_reference = src->stencil_reference;
197 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
198 }
199 }
200
201 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
202 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
203 src->discard_rectangle.count * sizeof(VkRect2D))) {
204 typed_memcpy(dest->discard_rectangle.rectangles,
205 src->discard_rectangle.rectangles,
206 src->discard_rectangle.count);
207 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
208 }
209 }
210
211 if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
212 if (dest->sample_location.per_pixel != src->sample_location.per_pixel ||
213 dest->sample_location.grid_size.width != src->sample_location.grid_size.width ||
214 dest->sample_location.grid_size.height != src->sample_location.grid_size.height ||
215 memcmp(&dest->sample_location.locations,
216 &src->sample_location.locations,
217 src->sample_location.count * sizeof(VkSampleLocationEXT))) {
218 dest->sample_location.per_pixel = src->sample_location.per_pixel;
219 dest->sample_location.grid_size = src->sample_location.grid_size;
220 typed_memcpy(dest->sample_location.locations,
221 src->sample_location.locations,
222 src->sample_location.count);
223 dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
224 }
225 }
226
227 if (copy_mask & RADV_DYNAMIC_LINE_STIPPLE) {
228 if (memcmp(&dest->line_stipple, &src->line_stipple,
229 sizeof(src->line_stipple))) {
230 dest->line_stipple = src->line_stipple;
231 dest_mask |= RADV_DYNAMIC_LINE_STIPPLE;
232 }
233 }
234
235 if (copy_mask & RADV_DYNAMIC_CULL_MODE) {
236 if (dest->cull_mode != src->cull_mode) {
237 dest->cull_mode = src->cull_mode;
238 dest_mask |= RADV_DYNAMIC_CULL_MODE;
239 }
240 }
241
242 if (copy_mask & RADV_DYNAMIC_FRONT_FACE) {
243 if (dest->front_face != src->front_face) {
244 dest->front_face = src->front_face;
245 dest_mask |= RADV_DYNAMIC_FRONT_FACE;
246 }
247 }
248
249 if (copy_mask & RADV_DYNAMIC_PRIMITIVE_TOPOLOGY) {
250 if (dest->primitive_topology != src->primitive_topology) {
251 dest->primitive_topology = src->primitive_topology;
252 dest_mask |= RADV_DYNAMIC_PRIMITIVE_TOPOLOGY;
253 }
254 }
255
256 if (copy_mask & RADV_DYNAMIC_DEPTH_TEST_ENABLE) {
257 if (dest->depth_test_enable != src->depth_test_enable) {
258 dest->depth_test_enable = src->depth_test_enable;
259 dest_mask |= RADV_DYNAMIC_DEPTH_TEST_ENABLE;
260 }
261 }
262
263 if (copy_mask & RADV_DYNAMIC_DEPTH_WRITE_ENABLE) {
264 if (dest->depth_write_enable != src->depth_write_enable) {
265 dest->depth_write_enable = src->depth_write_enable;
266 dest_mask |= RADV_DYNAMIC_DEPTH_WRITE_ENABLE;
267 }
268 }
269
270 if (copy_mask & RADV_DYNAMIC_DEPTH_COMPARE_OP) {
271 if (dest->depth_compare_op != src->depth_compare_op) {
272 dest->depth_compare_op = src->depth_compare_op;
273 dest_mask |= RADV_DYNAMIC_DEPTH_COMPARE_OP;
274 }
275 }
276
277 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE) {
278 if (dest->depth_bounds_test_enable != src->depth_bounds_test_enable) {
279 dest->depth_bounds_test_enable = src->depth_bounds_test_enable;
280 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE;
281 }
282 }
283
284 if (copy_mask & RADV_DYNAMIC_STENCIL_TEST_ENABLE) {
285 if (dest->stencil_test_enable != src->stencil_test_enable) {
286 dest->stencil_test_enable = src->stencil_test_enable;
287 dest_mask |= RADV_DYNAMIC_STENCIL_TEST_ENABLE;
288 }
289 }
290
291 if (copy_mask & RADV_DYNAMIC_STENCIL_OP) {
292 if (memcmp(&dest->stencil_op, &src->stencil_op,
293 sizeof(src->stencil_op))) {
294 dest->stencil_op = src->stencil_op;
295 dest_mask |= RADV_DYNAMIC_STENCIL_OP;
296 }
297 }
298
299 cmd_buffer->state.dirty |= dest_mask;
300 }
301
302 static void
303 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
304 struct radv_pipeline *pipeline)
305 {
306 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
307 struct radv_shader_info *info;
308
309 if (!pipeline->streamout_shader ||
310 cmd_buffer->device->physical_device->use_ngg_streamout)
311 return;
312
313 info = &pipeline->streamout_shader->info;
314 for (int i = 0; i < MAX_SO_BUFFERS; i++)
315 so->stride_in_dw[i] = info->so.strides[i];
316
317 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
318 }
319
320 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
321 {
322 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
323 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
324 }
325
326 enum ring_type radv_queue_family_to_ring(int f) {
327 switch (f) {
328 case RADV_QUEUE_GENERAL:
329 return RING_GFX;
330 case RADV_QUEUE_COMPUTE:
331 return RING_COMPUTE;
332 case RADV_QUEUE_TRANSFER:
333 return RING_DMA;
334 default:
335 unreachable("Unknown queue family");
336 }
337 }
338
339 static VkResult radv_create_cmd_buffer(
340 struct radv_device * device,
341 struct radv_cmd_pool * pool,
342 VkCommandBufferLevel level,
343 VkCommandBuffer* pCommandBuffer)
344 {
345 struct radv_cmd_buffer *cmd_buffer;
346 unsigned ring;
347 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
348 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
349 if (cmd_buffer == NULL)
350 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
351
352 vk_object_base_init(&device->vk, &cmd_buffer->base,
353 VK_OBJECT_TYPE_COMMAND_BUFFER);
354
355 cmd_buffer->device = device;
356 cmd_buffer->pool = pool;
357 cmd_buffer->level = level;
358
359 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
360 cmd_buffer->queue_family_index = pool->queue_family_index;
361
362 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
363
364 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
365 if (!cmd_buffer->cs) {
366 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
367 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
368 }
369
370 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
371
372 list_inithead(&cmd_buffer->upload.list);
373
374 return VK_SUCCESS;
375 }
376
377 static void
378 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
379 {
380 list_del(&cmd_buffer->pool_link);
381
382 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
383 &cmd_buffer->upload.list, list) {
384 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
385 list_del(&up->list);
386 free(up);
387 }
388
389 if (cmd_buffer->upload.upload_bo)
390 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
391 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
392
393 for (unsigned i = 0; i < MAX_BIND_POINTS; i++)
394 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
395
396 vk_object_base_finish(&cmd_buffer->base);
397
398 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
399 }
400
401 static VkResult
402 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
403 {
404 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
405
406 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
407 &cmd_buffer->upload.list, list) {
408 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
409 list_del(&up->list);
410 free(up);
411 }
412
413 cmd_buffer->push_constant_stages = 0;
414 cmd_buffer->scratch_size_per_wave_needed = 0;
415 cmd_buffer->scratch_waves_wanted = 0;
416 cmd_buffer->compute_scratch_size_per_wave_needed = 0;
417 cmd_buffer->compute_scratch_waves_wanted = 0;
418 cmd_buffer->esgs_ring_size_needed = 0;
419 cmd_buffer->gsvs_ring_size_needed = 0;
420 cmd_buffer->tess_rings_needed = false;
421 cmd_buffer->gds_needed = false;
422 cmd_buffer->gds_oa_needed = false;
423 cmd_buffer->sample_positions_needed = false;
424
425 if (cmd_buffer->upload.upload_bo)
426 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
427 cmd_buffer->upload.upload_bo);
428 cmd_buffer->upload.offset = 0;
429
430 cmd_buffer->record_result = VK_SUCCESS;
431
432 memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
433
434 for (unsigned i = 0; i < MAX_BIND_POINTS; i++) {
435 cmd_buffer->descriptors[i].dirty = 0;
436 cmd_buffer->descriptors[i].valid = 0;
437 cmd_buffer->descriptors[i].push_dirty = false;
438 }
439
440 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
441 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
442 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
443 unsigned fence_offset, eop_bug_offset;
444 void *fence_ptr;
445
446 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
447 &fence_ptr);
448
449 cmd_buffer->gfx9_fence_va =
450 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
451 cmd_buffer->gfx9_fence_va += fence_offset;
452
453 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
454 /* Allocate a buffer for the EOP bug on GFX9. */
455 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
456 &eop_bug_offset, &fence_ptr);
457 cmd_buffer->gfx9_eop_bug_va =
458 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
459 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
460 }
461 }
462
463 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
464
465 return cmd_buffer->record_result;
466 }
467
468 static bool
469 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
470 uint64_t min_needed)
471 {
472 uint64_t new_size;
473 struct radeon_winsys_bo *bo;
474 struct radv_cmd_buffer_upload *upload;
475 struct radv_device *device = cmd_buffer->device;
476
477 new_size = MAX2(min_needed, 16 * 1024);
478 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
479
480 bo = device->ws->buffer_create(device->ws,
481 new_size, 4096,
482 RADEON_DOMAIN_GTT,
483 RADEON_FLAG_CPU_ACCESS|
484 RADEON_FLAG_NO_INTERPROCESS_SHARING |
485 RADEON_FLAG_32BIT,
486 RADV_BO_PRIORITY_UPLOAD_BUFFER);
487
488 if (!bo) {
489 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
490 return false;
491 }
492
493 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
494 if (cmd_buffer->upload.upload_bo) {
495 upload = malloc(sizeof(*upload));
496
497 if (!upload) {
498 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
499 device->ws->buffer_destroy(bo);
500 return false;
501 }
502
503 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
504 list_add(&upload->list, &cmd_buffer->upload.list);
505 }
506
507 cmd_buffer->upload.upload_bo = bo;
508 cmd_buffer->upload.size = new_size;
509 cmd_buffer->upload.offset = 0;
510 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
511
512 if (!cmd_buffer->upload.map) {
513 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
514 return false;
515 }
516
517 return true;
518 }
519
520 bool
521 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
522 unsigned size,
523 unsigned alignment,
524 unsigned *out_offset,
525 void **ptr)
526 {
527 assert(util_is_power_of_two_nonzero(alignment));
528
529 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
530 if (offset + size > cmd_buffer->upload.size) {
531 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
532 return false;
533 offset = 0;
534 }
535
536 *out_offset = offset;
537 *ptr = cmd_buffer->upload.map + offset;
538
539 cmd_buffer->upload.offset = offset + size;
540 return true;
541 }
542
543 bool
544 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
545 unsigned size, unsigned alignment,
546 const void *data, unsigned *out_offset)
547 {
548 uint8_t *ptr;
549
550 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
551 out_offset, (void **)&ptr))
552 return false;
553
554 if (ptr)
555 memcpy(ptr, data, size);
556
557 return true;
558 }
559
560 static void
561 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
562 unsigned count, const uint32_t *data)
563 {
564 struct radeon_cmdbuf *cs = cmd_buffer->cs;
565
566 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
567
568 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
569 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
570 S_370_WR_CONFIRM(1) |
571 S_370_ENGINE_SEL(V_370_ME));
572 radeon_emit(cs, va);
573 radeon_emit(cs, va >> 32);
574 radeon_emit_array(cs, data, count);
575 }
576
577 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
578 {
579 struct radv_device *device = cmd_buffer->device;
580 struct radeon_cmdbuf *cs = cmd_buffer->cs;
581 uint64_t va;
582
583 va = radv_buffer_get_va(device->trace_bo);
584 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
585 va += 4;
586
587 ++cmd_buffer->state.trace_id;
588 radv_emit_write_data_packet(cmd_buffer, va, 1,
589 &cmd_buffer->state.trace_id);
590
591 radeon_check_space(cmd_buffer->device->ws, cs, 2);
592
593 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
594 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
595 }
596
597 static void
598 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
599 enum radv_cmd_flush_bits flags)
600 {
601 if (unlikely(cmd_buffer->device->thread_trace_bo)) {
602 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
603 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_THREAD_TRACE_MARKER) | EVENT_INDEX(0));
604 }
605
606 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
607 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
608 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
609
610 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
611
612 /* Force wait for graphics or compute engines to be idle. */
613 si_cs_emit_cache_flush(cmd_buffer->cs,
614 cmd_buffer->device->physical_device->rad_info.chip_class,
615 &cmd_buffer->gfx9_fence_idx,
616 cmd_buffer->gfx9_fence_va,
617 radv_cmd_buffer_uses_mec(cmd_buffer),
618 flags, cmd_buffer->gfx9_eop_bug_va);
619 }
620
621 if (unlikely(cmd_buffer->device->trace_bo))
622 radv_cmd_buffer_trace_emit(cmd_buffer);
623 }
624
625 static void
626 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
627 struct radv_pipeline *pipeline, enum ring_type ring)
628 {
629 struct radv_device *device = cmd_buffer->device;
630 uint32_t data[2];
631 uint64_t va;
632
633 va = radv_buffer_get_va(device->trace_bo);
634
635 switch (ring) {
636 case RING_GFX:
637 va += 8;
638 break;
639 case RING_COMPUTE:
640 va += 16;
641 break;
642 default:
643 assert(!"invalid ring type");
644 }
645
646 uint64_t pipeline_address = (uintptr_t)pipeline;
647 data[0] = pipeline_address;
648 data[1] = pipeline_address >> 32;
649
650 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
651 }
652
653 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
654 VkPipelineBindPoint bind_point,
655 struct radv_descriptor_set *set,
656 unsigned idx)
657 {
658 struct radv_descriptor_state *descriptors_state =
659 radv_get_descriptors_state(cmd_buffer, bind_point);
660
661 descriptors_state->sets[idx] = set;
662
663 descriptors_state->valid |= (1u << idx); /* active descriptors */
664 descriptors_state->dirty |= (1u << idx);
665 }
666
667 static void
668 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
669 VkPipelineBindPoint bind_point)
670 {
671 struct radv_descriptor_state *descriptors_state =
672 radv_get_descriptors_state(cmd_buffer, bind_point);
673 struct radv_device *device = cmd_buffer->device;
674 uint32_t data[MAX_SETS * 2] = {};
675 uint64_t va;
676 unsigned i;
677 va = radv_buffer_get_va(device->trace_bo) + 24;
678
679 for_each_bit(i, descriptors_state->valid) {
680 struct radv_descriptor_set *set = descriptors_state->sets[i];
681 data[i * 2] = (uint64_t)(uintptr_t)set;
682 data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
683 }
684
685 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
686 }
687
688 struct radv_userdata_info *
689 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
690 gl_shader_stage stage,
691 int idx)
692 {
693 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
694 return &shader->info.user_sgprs_locs.shader_data[idx];
695 }
696
697 static void
698 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
699 struct radv_pipeline *pipeline,
700 gl_shader_stage stage,
701 int idx, uint64_t va)
702 {
703 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
704 uint32_t base_reg = pipeline->user_data_0[stage];
705 if (loc->sgpr_idx == -1)
706 return;
707
708 assert(loc->num_sgprs == 1);
709
710 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
711 base_reg + loc->sgpr_idx * 4, va, false);
712 }
713
714 static void
715 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
716 struct radv_pipeline *pipeline,
717 struct radv_descriptor_state *descriptors_state,
718 gl_shader_stage stage)
719 {
720 struct radv_device *device = cmd_buffer->device;
721 struct radeon_cmdbuf *cs = cmd_buffer->cs;
722 uint32_t sh_base = pipeline->user_data_0[stage];
723 struct radv_userdata_locations *locs =
724 &pipeline->shaders[stage]->info.user_sgprs_locs;
725 unsigned mask = locs->descriptor_sets_enabled;
726
727 mask &= descriptors_state->dirty & descriptors_state->valid;
728
729 while (mask) {
730 int start, count;
731
732 u_bit_scan_consecutive_range(&mask, &start, &count);
733
734 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
735 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
736
737 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
738 for (int i = 0; i < count; i++) {
739 struct radv_descriptor_set *set =
740 descriptors_state->sets[start + i];
741
742 radv_emit_shader_pointer_body(device, cs, set->va, true);
743 }
744 }
745 }
746
747 /**
748 * Convert the user sample locations to hardware sample locations (the values
749 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
750 */
751 static void
752 radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
753 uint32_t x, uint32_t y, VkOffset2D *sample_locs)
754 {
755 uint32_t x_offset = x % state->grid_size.width;
756 uint32_t y_offset = y % state->grid_size.height;
757 uint32_t num_samples = (uint32_t)state->per_pixel;
758 VkSampleLocationEXT *user_locs;
759 uint32_t pixel_offset;
760
761 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
762
763 assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
764 user_locs = &state->locations[pixel_offset];
765
766 for (uint32_t i = 0; i < num_samples; i++) {
767 float shifted_pos_x = user_locs[i].x - 0.5;
768 float shifted_pos_y = user_locs[i].y - 0.5;
769
770 int32_t scaled_pos_x = floorf(shifted_pos_x * 16);
771 int32_t scaled_pos_y = floorf(shifted_pos_y * 16);
772
773 sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
774 sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
775 }
776 }
777
778 /**
779 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
780 * locations.
781 */
782 static void
783 radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
784 uint32_t *sample_locs_pixel)
785 {
786 for (uint32_t i = 0; i < num_samples; i++) {
787 uint32_t sample_reg_idx = i / 4;
788 uint32_t sample_loc_idx = i % 4;
789 int32_t pos_x = sample_locs[i].x;
790 int32_t pos_y = sample_locs[i].y;
791
792 uint32_t shift_x = 8 * sample_loc_idx;
793 uint32_t shift_y = shift_x + 4;
794
795 sample_locs_pixel[sample_reg_idx] |= (pos_x & 0xf) << shift_x;
796 sample_locs_pixel[sample_reg_idx] |= (pos_y & 0xf) << shift_y;
797 }
798 }
799
800 /**
801 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
802 * sample locations.
803 */
804 static uint64_t
805 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer,
806 VkOffset2D *sample_locs,
807 uint32_t num_samples)
808 {
809 uint32_t centroid_priorities[num_samples];
810 uint32_t sample_mask = num_samples - 1;
811 uint32_t distances[num_samples];
812 uint64_t centroid_priority = 0;
813
814 /* Compute the distances from center for each sample. */
815 for (int i = 0; i < num_samples; i++) {
816 distances[i] = (sample_locs[i].x * sample_locs[i].x) +
817 (sample_locs[i].y * sample_locs[i].y);
818 }
819
820 /* Compute the centroid priorities by looking at the distances array. */
821 for (int i = 0; i < num_samples; i++) {
822 uint32_t min_idx = 0;
823
824 for (int j = 1; j < num_samples; j++) {
825 if (distances[j] < distances[min_idx])
826 min_idx = j;
827 }
828
829 centroid_priorities[i] = min_idx;
830 distances[min_idx] = 0xffffffff;
831 }
832
833 /* Compute the final centroid priority. */
834 for (int i = 0; i < 8; i++) {
835 centroid_priority |=
836 centroid_priorities[i & sample_mask] << (i * 4);
837 }
838
839 return centroid_priority << 32 | centroid_priority;
840 }
841
842 /**
843 * Emit the sample locations that are specified with VK_EXT_sample_locations.
844 */
845 static void
846 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
847 {
848 struct radv_sample_locations_state *sample_location =
849 &cmd_buffer->state.dynamic.sample_location;
850 uint32_t num_samples = (uint32_t)sample_location->per_pixel;
851 struct radeon_cmdbuf *cs = cmd_buffer->cs;
852 uint32_t sample_locs_pixel[4][2] = {};
853 VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
854 uint32_t max_sample_dist = 0;
855 uint64_t centroid_priority;
856
857 if (!cmd_buffer->state.dynamic.sample_location.count)
858 return;
859
860 /* Convert the user sample locations to hardware sample locations. */
861 radv_convert_user_sample_locs(sample_location, 0, 0, sample_locs[0]);
862 radv_convert_user_sample_locs(sample_location, 1, 0, sample_locs[1]);
863 radv_convert_user_sample_locs(sample_location, 0, 1, sample_locs[2]);
864 radv_convert_user_sample_locs(sample_location, 1, 1, sample_locs[3]);
865
866 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
867 for (uint32_t i = 0; i < 4; i++) {
868 radv_compute_sample_locs_pixel(num_samples, sample_locs[i],
869 sample_locs_pixel[i]);
870 }
871
872 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
873 centroid_priority =
874 radv_compute_centroid_priority(cmd_buffer, sample_locs[0],
875 num_samples);
876
877 /* Compute the maximum sample distance from the specified locations. */
878 for (unsigned i = 0; i < 4; ++i) {
879 for (uint32_t j = 0; j < num_samples; j++) {
880 VkOffset2D offset = sample_locs[i][j];
881 max_sample_dist = MAX2(max_sample_dist,
882 MAX2(abs(offset.x), abs(offset.y)));
883 }
884 }
885
886 /* Emit the specified user sample locations. */
887 switch (num_samples) {
888 case 2:
889 case 4:
890 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
891 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
892 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
893 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
894 break;
895 case 8:
896 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
897 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
898 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
899 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
900 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs_pixel[0][1]);
901 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs_pixel[1][1]);
902 radeon_set_context_reg(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs_pixel[2][1]);
903 radeon_set_context_reg(cs, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs_pixel[3][1]);
904 break;
905 default:
906 unreachable("invalid number of samples");
907 }
908
909 /* Emit the maximum sample distance and the centroid priority. */
910 radeon_set_context_reg_rmw(cs, R_028BE0_PA_SC_AA_CONFIG,
911 S_028BE0_MAX_SAMPLE_DIST(max_sample_dist),
912 ~C_028BE0_MAX_SAMPLE_DIST);
913
914 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
915 radeon_emit(cs, centroid_priority);
916 radeon_emit(cs, centroid_priority >> 32);
917
918 /* GFX9: Flush DFSM when the AA mode changes. */
919 if (cmd_buffer->device->dfsm_allowed) {
920 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
921 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
922 }
923
924 cmd_buffer->state.context_roll_without_scissor_emitted = true;
925 }
926
927 static void
928 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
929 struct radv_pipeline *pipeline,
930 gl_shader_stage stage,
931 int idx, int count, uint32_t *values)
932 {
933 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
934 uint32_t base_reg = pipeline->user_data_0[stage];
935 if (loc->sgpr_idx == -1)
936 return;
937
938 assert(loc->num_sgprs == count);
939
940 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
941 radeon_emit_array(cmd_buffer->cs, values, count);
942 }
943
944 static void
945 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
946 struct radv_pipeline *pipeline)
947 {
948 int num_samples = pipeline->graphics.ms.num_samples;
949 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
950
951 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.needs_sample_positions)
952 cmd_buffer->sample_positions_needed = true;
953
954 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
955 return;
956
957 radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
958
959 cmd_buffer->state.context_roll_without_scissor_emitted = true;
960 }
961
962 static void
963 radv_update_binning_state(struct radv_cmd_buffer *cmd_buffer,
964 struct radv_pipeline *pipeline)
965 {
966 const struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
967
968
969 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
970 return;
971
972 if (old_pipeline &&
973 old_pipeline->graphics.binning.pa_sc_binner_cntl_0 == pipeline->graphics.binning.pa_sc_binner_cntl_0 &&
974 old_pipeline->graphics.binning.db_dfsm_control == pipeline->graphics.binning.db_dfsm_control)
975 return;
976
977 bool binning_flush = false;
978 if (cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA12 ||
979 cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA20 ||
980 cmd_buffer->device->physical_device->rad_info.family == CHIP_RAVEN2 ||
981 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
982 binning_flush = !old_pipeline ||
983 G_028C44_BINNING_MODE(old_pipeline->graphics.binning.pa_sc_binner_cntl_0) !=
984 G_028C44_BINNING_MODE(pipeline->graphics.binning.pa_sc_binner_cntl_0);
985 }
986
987 radeon_set_context_reg(cmd_buffer->cs, R_028C44_PA_SC_BINNER_CNTL_0,
988 pipeline->graphics.binning.pa_sc_binner_cntl_0 |
989 S_028C44_FLUSH_ON_BINNING_TRANSITION(!!binning_flush));
990
991 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
992 radeon_set_context_reg(cmd_buffer->cs, R_028038_DB_DFSM_CONTROL,
993 pipeline->graphics.binning.db_dfsm_control);
994 } else {
995 radeon_set_context_reg(cmd_buffer->cs, R_028060_DB_DFSM_CONTROL,
996 pipeline->graphics.binning.db_dfsm_control);
997 }
998
999 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1000 }
1001
1002
1003 static void
1004 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
1005 struct radv_shader_variant *shader)
1006 {
1007 uint64_t va;
1008
1009 if (!shader)
1010 return;
1011
1012 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
1013
1014 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
1015 }
1016
1017 static void
1018 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
1019 struct radv_pipeline *pipeline,
1020 bool vertex_stage_only)
1021 {
1022 struct radv_cmd_state *state = &cmd_buffer->state;
1023 uint32_t mask = state->prefetch_L2_mask;
1024
1025 if (vertex_stage_only) {
1026 /* Fast prefetch path for starting draws as soon as possible.
1027 */
1028 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
1029 RADV_PREFETCH_VBO_DESCRIPTORS);
1030 }
1031
1032 if (mask & RADV_PREFETCH_VS)
1033 radv_emit_shader_prefetch(cmd_buffer,
1034 pipeline->shaders[MESA_SHADER_VERTEX]);
1035
1036 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
1037 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
1038
1039 if (mask & RADV_PREFETCH_TCS)
1040 radv_emit_shader_prefetch(cmd_buffer,
1041 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
1042
1043 if (mask & RADV_PREFETCH_TES)
1044 radv_emit_shader_prefetch(cmd_buffer,
1045 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
1046
1047 if (mask & RADV_PREFETCH_GS) {
1048 radv_emit_shader_prefetch(cmd_buffer,
1049 pipeline->shaders[MESA_SHADER_GEOMETRY]);
1050 if (radv_pipeline_has_gs_copy_shader(pipeline))
1051 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
1052 }
1053
1054 if (mask & RADV_PREFETCH_PS)
1055 radv_emit_shader_prefetch(cmd_buffer,
1056 pipeline->shaders[MESA_SHADER_FRAGMENT]);
1057
1058 state->prefetch_L2_mask &= ~mask;
1059 }
1060
1061 static void
1062 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
1063 {
1064 if (!cmd_buffer->device->physical_device->rad_info.rbplus_allowed)
1065 return;
1066
1067 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1068 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1069
1070 unsigned sx_ps_downconvert = 0;
1071 unsigned sx_blend_opt_epsilon = 0;
1072 unsigned sx_blend_opt_control = 0;
1073
1074 if (!cmd_buffer->state.attachments || !subpass)
1075 return;
1076
1077 for (unsigned i = 0; i < subpass->color_count; ++i) {
1078 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1079 /* We don't set the DISABLE bits, because the HW can't have holes,
1080 * so the SPI color format is set to 32-bit 1-component. */
1081 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1082 continue;
1083 }
1084
1085 int idx = subpass->color_attachments[i].attachment;
1086 struct radv_color_buffer_info *cb = &cmd_buffer->state.attachments[idx].cb;
1087
1088 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
1089 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
1090 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
1091 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
1092
1093 bool has_alpha, has_rgb;
1094
1095 /* Set if RGB and A are present. */
1096 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
1097
1098 if (format == V_028C70_COLOR_8 ||
1099 format == V_028C70_COLOR_16 ||
1100 format == V_028C70_COLOR_32)
1101 has_rgb = !has_alpha;
1102 else
1103 has_rgb = true;
1104
1105 /* Check the colormask and export format. */
1106 if (!(colormask & 0x7))
1107 has_rgb = false;
1108 if (!(colormask & 0x8))
1109 has_alpha = false;
1110
1111 if (spi_format == V_028714_SPI_SHADER_ZERO) {
1112 has_rgb = false;
1113 has_alpha = false;
1114 }
1115
1116 /* Disable value checking for disabled channels. */
1117 if (!has_rgb)
1118 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1119 if (!has_alpha)
1120 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1121
1122 /* Enable down-conversion for 32bpp and smaller formats. */
1123 switch (format) {
1124 case V_028C70_COLOR_8:
1125 case V_028C70_COLOR_8_8:
1126 case V_028C70_COLOR_8_8_8_8:
1127 /* For 1 and 2-channel formats, use the superset thereof. */
1128 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
1129 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1130 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1131 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
1132 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
1133 }
1134 break;
1135
1136 case V_028C70_COLOR_5_6_5:
1137 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1138 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
1139 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
1140 }
1141 break;
1142
1143 case V_028C70_COLOR_1_5_5_5:
1144 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1145 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
1146 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
1147 }
1148 break;
1149
1150 case V_028C70_COLOR_4_4_4_4:
1151 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1152 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
1153 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
1154 }
1155 break;
1156
1157 case V_028C70_COLOR_32:
1158 if (swap == V_028C70_SWAP_STD &&
1159 spi_format == V_028714_SPI_SHADER_32_R)
1160 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1161 else if (swap == V_028C70_SWAP_ALT_REV &&
1162 spi_format == V_028714_SPI_SHADER_32_AR)
1163 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
1164 break;
1165
1166 case V_028C70_COLOR_16:
1167 case V_028C70_COLOR_16_16:
1168 /* For 1-channel formats, use the superset thereof. */
1169 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
1170 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
1171 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1172 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1173 if (swap == V_028C70_SWAP_STD ||
1174 swap == V_028C70_SWAP_STD_REV)
1175 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
1176 else
1177 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
1178 }
1179 break;
1180
1181 case V_028C70_COLOR_10_11_11:
1182 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1183 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
1184 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
1185 }
1186 break;
1187
1188 case V_028C70_COLOR_2_10_10_10:
1189 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1190 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
1191 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
1192 }
1193 break;
1194 }
1195 }
1196
1197 /* Do not set the DISABLE bits for the unused attachments, as that
1198 * breaks dual source blending in SkQP and does not seem to improve
1199 * performance. */
1200
1201 if (sx_ps_downconvert == cmd_buffer->state.last_sx_ps_downconvert &&
1202 sx_blend_opt_epsilon == cmd_buffer->state.last_sx_blend_opt_epsilon &&
1203 sx_blend_opt_control == cmd_buffer->state.last_sx_blend_opt_control)
1204 return;
1205
1206 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
1207 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
1208 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
1209 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
1210
1211 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1212
1213 cmd_buffer->state.last_sx_ps_downconvert = sx_ps_downconvert;
1214 cmd_buffer->state.last_sx_blend_opt_epsilon = sx_blend_opt_epsilon;
1215 cmd_buffer->state.last_sx_blend_opt_control = sx_blend_opt_control;
1216 }
1217
1218 static void
1219 radv_emit_batch_break_on_new_ps(struct radv_cmd_buffer *cmd_buffer)
1220 {
1221 if (!cmd_buffer->device->pbb_allowed)
1222 return;
1223
1224 struct radv_binning_settings settings =
1225 radv_get_binning_settings(cmd_buffer->device->physical_device);
1226 bool break_for_new_ps =
1227 (!cmd_buffer->state.emitted_pipeline ||
1228 cmd_buffer->state.emitted_pipeline->shaders[MESA_SHADER_FRAGMENT] !=
1229 cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT]) &&
1230 (settings.context_states_per_bin > 1 ||
1231 settings.persistent_states_per_bin > 1);
1232 bool break_for_new_cb_target_mask =
1233 (!cmd_buffer->state.emitted_pipeline ||
1234 cmd_buffer->state.emitted_pipeline->graphics.cb_target_mask !=
1235 cmd_buffer->state.pipeline->graphics.cb_target_mask) &&
1236 settings.context_states_per_bin > 1;
1237
1238 if (!break_for_new_ps && !break_for_new_cb_target_mask)
1239 return;
1240
1241 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1242 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1243 }
1244
1245 static void
1246 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1247 {
1248 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1249
1250 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1251 return;
1252
1253 radv_update_multisample_state(cmd_buffer, pipeline);
1254 radv_update_binning_state(cmd_buffer, pipeline);
1255
1256 cmd_buffer->scratch_size_per_wave_needed = MAX2(cmd_buffer->scratch_size_per_wave_needed,
1257 pipeline->scratch_bytes_per_wave);
1258 cmd_buffer->scratch_waves_wanted = MAX2(cmd_buffer->scratch_waves_wanted,
1259 pipeline->max_waves);
1260
1261 if (!cmd_buffer->state.emitted_pipeline ||
1262 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1263 pipeline->graphics.can_use_guardband)
1264 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1265
1266 if (!cmd_buffer->state.emitted_pipeline ||
1267 cmd_buffer->state.emitted_pipeline->graphics.pa_su_sc_mode_cntl !=
1268 pipeline->graphics.pa_su_sc_mode_cntl)
1269 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_CULL_MODE |
1270 RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE;
1271
1272 if (!cmd_buffer->state.emitted_pipeline)
1273 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY;
1274
1275 if (!cmd_buffer->state.emitted_pipeline ||
1276 cmd_buffer->state.emitted_pipeline->graphics.db_depth_control !=
1277 pipeline->graphics.db_depth_control)
1278 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE |
1279 RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE |
1280 RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP |
1281 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE |
1282 RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE |
1283 RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP;
1284
1285 if (!cmd_buffer->state.emitted_pipeline)
1286 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP;
1287
1288 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
1289
1290 if (!cmd_buffer->state.emitted_pipeline ||
1291 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
1292 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
1293 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
1294 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
1295 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
1296 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1297 }
1298
1299 radv_emit_batch_break_on_new_ps(cmd_buffer);
1300
1301 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
1302 if (!pipeline->shaders[i])
1303 continue;
1304
1305 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1306 pipeline->shaders[i]->bo);
1307 }
1308
1309 if (radv_pipeline_has_gs_copy_shader(pipeline))
1310 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1311 pipeline->gs_copy_shader->bo);
1312
1313 if (unlikely(cmd_buffer->device->trace_bo))
1314 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1315
1316 cmd_buffer->state.emitted_pipeline = pipeline;
1317
1318 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1319 }
1320
1321 static void
1322 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1323 {
1324 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1325 cmd_buffer->state.dynamic.viewport.viewports);
1326 }
1327
1328 static void
1329 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1330 {
1331 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1332
1333 si_write_scissors(cmd_buffer->cs, 0, count,
1334 cmd_buffer->state.dynamic.scissor.scissors,
1335 cmd_buffer->state.dynamic.viewport.viewports,
1336 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1337
1338 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1339 }
1340
1341 static void
1342 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1343 {
1344 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1345 return;
1346
1347 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1348 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1349 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1350 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1351 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1352 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1353 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1354 }
1355 }
1356
1357 static void
1358 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1359 {
1360 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1361
1362 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1363 S_028A08_WIDTH(CLAMP(width, 0, 0xFFFF)));
1364 }
1365
1366 static void
1367 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1368 {
1369 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1370
1371 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1372 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1373 }
1374
1375 static void
1376 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1377 {
1378 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1379
1380 radeon_set_context_reg_seq(cmd_buffer->cs,
1381 R_028430_DB_STENCILREFMASK, 2);
1382 radeon_emit(cmd_buffer->cs,
1383 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1384 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1385 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1386 S_028430_STENCILOPVAL(1));
1387 radeon_emit(cmd_buffer->cs,
1388 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1389 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1390 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1391 S_028434_STENCILOPVAL_BF(1));
1392 }
1393
1394 static void
1395 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1396 {
1397 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1398
1399 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1400 fui(d->depth_bounds.min));
1401 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1402 fui(d->depth_bounds.max));
1403 }
1404
1405 static void
1406 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1407 {
1408 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1409 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1410 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1411
1412
1413 radeon_set_context_reg_seq(cmd_buffer->cs,
1414 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1415 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1416 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1417 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1418 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1419 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1420 }
1421
1422 static void
1423 radv_emit_line_stipple(struct radv_cmd_buffer *cmd_buffer)
1424 {
1425 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1426 uint32_t auto_reset_cntl = 1;
1427
1428 if (d->primitive_topology == V_008958_DI_PT_LINESTRIP)
1429 auto_reset_cntl = 2;
1430
1431 radeon_set_context_reg(cmd_buffer->cs, R_028A0C_PA_SC_LINE_STIPPLE,
1432 S_028A0C_LINE_PATTERN(d->line_stipple.pattern) |
1433 S_028A0C_REPEAT_COUNT(d->line_stipple.factor - 1) |
1434 S_028A0C_AUTO_RESET_CNTL(auto_reset_cntl));
1435 }
1436
1437 static void
1438 radv_emit_culling(struct radv_cmd_buffer *cmd_buffer, uint32_t states)
1439 {
1440 unsigned pa_su_sc_mode_cntl = cmd_buffer->state.pipeline->graphics.pa_su_sc_mode_cntl;
1441 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1442
1443 if (states & RADV_CMD_DIRTY_DYNAMIC_CULL_MODE) {
1444 pa_su_sc_mode_cntl &= C_028814_CULL_FRONT;
1445 pa_su_sc_mode_cntl |= S_028814_CULL_FRONT(!!(d->cull_mode & VK_CULL_MODE_FRONT_BIT));
1446
1447 pa_su_sc_mode_cntl &= C_028814_CULL_BACK;
1448 pa_su_sc_mode_cntl |= S_028814_CULL_BACK(!!(d->cull_mode & VK_CULL_MODE_BACK_BIT));
1449 }
1450
1451 if (states & RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE) {
1452 pa_su_sc_mode_cntl &= C_028814_FACE;
1453 pa_su_sc_mode_cntl |= S_028814_FACE(d->front_face);
1454 }
1455
1456 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
1457 pa_su_sc_mode_cntl);
1458 }
1459
1460 static void
1461 radv_emit_primitive_topology(struct radv_cmd_buffer *cmd_buffer)
1462 {
1463 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1464
1465 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1466 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
1467 cmd_buffer->cs,
1468 R_030908_VGT_PRIMITIVE_TYPE, 1,
1469 d->primitive_topology);
1470 } else {
1471 radeon_set_config_reg(cmd_buffer->cs,
1472 R_008958_VGT_PRIMITIVE_TYPE,
1473 d->primitive_topology);
1474 }
1475 }
1476
1477 static void
1478 radv_emit_depth_control(struct radv_cmd_buffer *cmd_buffer, uint32_t states)
1479 {
1480 unsigned db_depth_control = cmd_buffer->state.pipeline->graphics.db_depth_control;
1481 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1482
1483 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE) {
1484 db_depth_control &= C_028800_Z_ENABLE;
1485 db_depth_control |= S_028800_Z_ENABLE(d->depth_test_enable ? 1 : 0);
1486 }
1487
1488 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE) {
1489 db_depth_control &= C_028800_Z_WRITE_ENABLE;
1490 db_depth_control |= S_028800_Z_WRITE_ENABLE(d->depth_write_enable ? 1 : 0);
1491 }
1492
1493 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP) {
1494 db_depth_control &= C_028800_ZFUNC;
1495 db_depth_control |= S_028800_ZFUNC(d->depth_compare_op);
1496 }
1497
1498 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE) {
1499 db_depth_control &= C_028800_DEPTH_BOUNDS_ENABLE;
1500 db_depth_control |= S_028800_DEPTH_BOUNDS_ENABLE(d->depth_bounds_test_enable ? 1 : 0);
1501 }
1502
1503 if (states & RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE) {
1504 db_depth_control &= C_028800_STENCIL_ENABLE;
1505 db_depth_control |= S_028800_STENCIL_ENABLE(d->stencil_test_enable ? 1 : 0);
1506
1507 db_depth_control &= C_028800_BACKFACE_ENABLE;
1508 db_depth_control |= S_028800_BACKFACE_ENABLE(d->stencil_test_enable ? 1 : 0);
1509 }
1510
1511 if (states & RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP) {
1512 db_depth_control &= C_028800_STENCILFUNC;
1513 db_depth_control |= S_028800_STENCILFUNC(d->stencil_op.front.compare_op);
1514
1515 db_depth_control &= C_028800_STENCILFUNC_BF;
1516 db_depth_control |= S_028800_STENCILFUNC_BF(d->stencil_op.back.compare_op);
1517 }
1518
1519 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL,
1520 db_depth_control);
1521 }
1522
1523 static void
1524 radv_emit_stencil_control(struct radv_cmd_buffer *cmd_buffer)
1525 {
1526 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1527
1528 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL,
1529 S_02842C_STENCILFAIL(si_translate_stencil_op(d->stencil_op.front.fail_op)) |
1530 S_02842C_STENCILZPASS(si_translate_stencil_op(d->stencil_op.front.pass_op)) |
1531 S_02842C_STENCILZFAIL(si_translate_stencil_op(d->stencil_op.front.depth_fail_op)) |
1532 S_02842C_STENCILFAIL_BF(si_translate_stencil_op(d->stencil_op.back.fail_op)) |
1533 S_02842C_STENCILZPASS_BF(si_translate_stencil_op(d->stencil_op.back.pass_op)) |
1534 S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(d->stencil_op.back.depth_fail_op)));
1535 }
1536
1537 static void
1538 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1539 int index,
1540 struct radv_color_buffer_info *cb,
1541 struct radv_image_view *iview,
1542 VkImageLayout layout,
1543 bool in_render_loop)
1544 {
1545 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
1546 uint32_t cb_color_info = cb->cb_color_info;
1547 struct radv_image *image = iview->image;
1548
1549 if (!radv_layout_dcc_compressed(cmd_buffer->device, image, layout, in_render_loop,
1550 radv_image_queue_family_mask(image,
1551 cmd_buffer->queue_family_index,
1552 cmd_buffer->queue_family_index))) {
1553 cb_color_info &= C_028C70_DCC_ENABLE;
1554 }
1555
1556 if (!radv_layout_can_fast_clear(image, layout, in_render_loop,
1557 radv_image_queue_family_mask(image,
1558 cmd_buffer->queue_family_index,
1559 cmd_buffer->queue_family_index))) {
1560 cb_color_info &= C_028C70_COMPRESSION;
1561 }
1562
1563 if (radv_image_is_tc_compat_cmask(image) &&
1564 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1565 radv_is_dcc_decompress_pipeline(cmd_buffer))) {
1566 /* If this bit is set, the FMASK decompression operation
1567 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1568 */
1569 cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
1570 }
1571
1572 if (radv_image_has_fmask(image) &&
1573 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1574 radv_is_hw_resolve_pipeline(cmd_buffer))) {
1575 /* Make sure FMASK is enabled if it has been cleared because:
1576 *
1577 * 1) it's required for FMASK_DECOMPRESS operations to avoid
1578 * GPU hangs
1579 * 2) it's necessary for CB_RESOLVE which can read compressed
1580 * FMASK data anyways.
1581 */
1582 cb_color_info |= S_028C70_COMPRESSION(1);
1583 }
1584
1585 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1586 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1587 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1588 radeon_emit(cmd_buffer->cs, 0);
1589 radeon_emit(cmd_buffer->cs, 0);
1590 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1591 radeon_emit(cmd_buffer->cs, cb_color_info);
1592 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1593 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1594 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1595 radeon_emit(cmd_buffer->cs, 0);
1596 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1597 radeon_emit(cmd_buffer->cs, 0);
1598
1599 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 1);
1600 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1601
1602 radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4,
1603 cb->cb_color_base >> 32);
1604 radeon_set_context_reg(cmd_buffer->cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + index * 4,
1605 cb->cb_color_cmask >> 32);
1606 radeon_set_context_reg(cmd_buffer->cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + index * 4,
1607 cb->cb_color_fmask >> 32);
1608 radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4,
1609 cb->cb_dcc_base >> 32);
1610 radeon_set_context_reg(cmd_buffer->cs, R_028EC0_CB_COLOR0_ATTRIB2 + index * 4,
1611 cb->cb_color_attrib2);
1612 radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4,
1613 cb->cb_color_attrib3);
1614 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1615 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1616 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1617 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1618 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1619 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1620 radeon_emit(cmd_buffer->cs, cb_color_info);
1621 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1622 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1623 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1624 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1625 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1626 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1627
1628 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1629 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1630 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1631
1632 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1633 cb->cb_mrt_epitch);
1634 } else {
1635 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1636 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1637 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1638 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1639 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1640 radeon_emit(cmd_buffer->cs, cb_color_info);
1641 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1642 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1643 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1644 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1645 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1646 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1647
1648 if (is_vi) { /* DCC BASE */
1649 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1650 }
1651 }
1652
1653 if (radv_dcc_enabled(image, iview->base_mip)) {
1654 /* Drawing with DCC enabled also compresses colorbuffers. */
1655 VkImageSubresourceRange range = {
1656 .aspectMask = iview->aspect_mask,
1657 .baseMipLevel = iview->base_mip,
1658 .levelCount = iview->level_count,
1659 .baseArrayLayer = iview->base_layer,
1660 .layerCount = iview->layer_count,
1661 };
1662
1663 radv_update_dcc_metadata(cmd_buffer, image, &range, true);
1664 }
1665 }
1666
1667 static void
1668 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1669 struct radv_ds_buffer_info *ds,
1670 const struct radv_image_view *iview,
1671 VkImageLayout layout,
1672 bool in_render_loop, bool requires_cond_exec)
1673 {
1674 const struct radv_image *image = iview->image;
1675 uint32_t db_z_info = ds->db_z_info;
1676 uint32_t db_z_info_reg;
1677
1678 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug ||
1679 !radv_image_is_tc_compat_htile(image))
1680 return;
1681
1682 if (!radv_layout_is_htile_compressed(image, layout, in_render_loop,
1683 radv_image_queue_family_mask(image,
1684 cmd_buffer->queue_family_index,
1685 cmd_buffer->queue_family_index))) {
1686 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1687 }
1688
1689 db_z_info &= C_028040_ZRANGE_PRECISION;
1690
1691 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1692 db_z_info_reg = R_028038_DB_Z_INFO;
1693 } else {
1694 db_z_info_reg = R_028040_DB_Z_INFO;
1695 }
1696
1697 /* When we don't know the last fast clear value we need to emit a
1698 * conditional packet that will eventually skip the following
1699 * SET_CONTEXT_REG packet.
1700 */
1701 if (requires_cond_exec) {
1702 uint64_t va = radv_get_tc_compat_zrange_va(image, iview->base_mip);
1703
1704 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1705 radeon_emit(cmd_buffer->cs, va);
1706 radeon_emit(cmd_buffer->cs, va >> 32);
1707 radeon_emit(cmd_buffer->cs, 0);
1708 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1709 }
1710
1711 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1712 }
1713
1714 static void
1715 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1716 struct radv_ds_buffer_info *ds,
1717 struct radv_image_view *iview,
1718 VkImageLayout layout,
1719 bool in_render_loop)
1720 {
1721 const struct radv_image *image = iview->image;
1722 uint32_t db_z_info = ds->db_z_info;
1723 uint32_t db_stencil_info = ds->db_stencil_info;
1724
1725 if (!radv_layout_is_htile_compressed(image, layout, in_render_loop,
1726 radv_image_queue_family_mask(image,
1727 cmd_buffer->queue_family_index,
1728 cmd_buffer->queue_family_index))) {
1729 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1730 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1731 }
1732
1733 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1734 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1735
1736 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1737 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1738 radeon_set_context_reg(cmd_buffer->cs, R_02801C_DB_DEPTH_SIZE_XY, ds->db_depth_size);
1739
1740 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 7);
1741 radeon_emit(cmd_buffer->cs, S_02803C_RESOURCE_LEVEL(1));
1742 radeon_emit(cmd_buffer->cs, db_z_info);
1743 radeon_emit(cmd_buffer->cs, db_stencil_info);
1744 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1745 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1746 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1747 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1748
1749 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_READ_BASE_HI, 5);
1750 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1751 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1752 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1753 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1754 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1755 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1756 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1757 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1758 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1759 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1760
1761 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1762 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1763 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1764 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1765 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1766 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1767 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1768 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1769 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1770 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1771 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1772
1773 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1774 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1775 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1776 } else {
1777 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1778
1779 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1780 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1781 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1782 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1783 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1784 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1785 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1786 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1787 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1788 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1789
1790 }
1791
1792 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1793 radv_update_zrange_precision(cmd_buffer, ds, iview, layout,
1794 in_render_loop, true);
1795
1796 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1797 ds->pa_su_poly_offset_db_fmt_cntl);
1798 }
1799
1800 /**
1801 * Update the fast clear depth/stencil values if the image is bound as a
1802 * depth/stencil buffer.
1803 */
1804 static void
1805 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1806 const struct radv_image_view *iview,
1807 VkClearDepthStencilValue ds_clear_value,
1808 VkImageAspectFlags aspects)
1809 {
1810 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1811 const struct radv_image *image = iview->image;
1812 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1813 uint32_t att_idx;
1814
1815 if (!cmd_buffer->state.attachments || !subpass)
1816 return;
1817
1818 if (!subpass->depth_stencil_attachment)
1819 return;
1820
1821 att_idx = subpass->depth_stencil_attachment->attachment;
1822 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1823 return;
1824
1825 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1826 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1827 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1828 radeon_emit(cs, ds_clear_value.stencil);
1829 radeon_emit(cs, fui(ds_clear_value.depth));
1830 } else if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1831 radeon_set_context_reg_seq(cs, R_02802C_DB_DEPTH_CLEAR, 1);
1832 radeon_emit(cs, fui(ds_clear_value.depth));
1833 } else {
1834 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1835 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 1);
1836 radeon_emit(cs, ds_clear_value.stencil);
1837 }
1838
1839 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1840 * only needed when clearing Z to 0.0.
1841 */
1842 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1843 ds_clear_value.depth == 0.0) {
1844 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1845 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
1846
1847 radv_update_zrange_precision(cmd_buffer, &cmd_buffer->state.attachments[att_idx].ds,
1848 iview, layout, in_render_loop, false);
1849 }
1850
1851 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1852 }
1853
1854 /**
1855 * Set the clear depth/stencil values to the image's metadata.
1856 */
1857 static void
1858 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1859 struct radv_image *image,
1860 const VkImageSubresourceRange *range,
1861 VkClearDepthStencilValue ds_clear_value,
1862 VkImageAspectFlags aspects)
1863 {
1864 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1865 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel);
1866 uint32_t level_count = radv_get_levelCount(image, range);
1867
1868 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1869 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1870 /* Use the fastest way when both aspects are used. */
1871 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + 2 * level_count, cmd_buffer->state.predicating));
1872 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1873 S_370_WR_CONFIRM(1) |
1874 S_370_ENGINE_SEL(V_370_PFP));
1875 radeon_emit(cs, va);
1876 radeon_emit(cs, va >> 32);
1877
1878 for (uint32_t l = 0; l < level_count; l++) {
1879 radeon_emit(cs, ds_clear_value.stencil);
1880 radeon_emit(cs, fui(ds_clear_value.depth));
1881 }
1882 } else {
1883 /* Otherwise we need one WRITE_DATA packet per level. */
1884 for (uint32_t l = 0; l < level_count; l++) {
1885 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel + l);
1886 unsigned value;
1887
1888 if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1889 value = fui(ds_clear_value.depth);
1890 va += 4;
1891 } else {
1892 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1893 value = ds_clear_value.stencil;
1894 }
1895
1896 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1897 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1898 S_370_WR_CONFIRM(1) |
1899 S_370_ENGINE_SEL(V_370_PFP));
1900 radeon_emit(cs, va);
1901 radeon_emit(cs, va >> 32);
1902 radeon_emit(cs, value);
1903 }
1904 }
1905 }
1906
1907 /**
1908 * Update the TC-compat metadata value for this image.
1909 */
1910 static void
1911 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1912 struct radv_image *image,
1913 const VkImageSubresourceRange *range,
1914 uint32_t value)
1915 {
1916 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1917
1918 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug)
1919 return;
1920
1921 uint64_t va = radv_get_tc_compat_zrange_va(image, range->baseMipLevel);
1922 uint32_t level_count = radv_get_levelCount(image, range);
1923
1924 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + level_count, cmd_buffer->state.predicating));
1925 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1926 S_370_WR_CONFIRM(1) |
1927 S_370_ENGINE_SEL(V_370_PFP));
1928 radeon_emit(cs, va);
1929 radeon_emit(cs, va >> 32);
1930
1931 for (uint32_t l = 0; l < level_count; l++)
1932 radeon_emit(cs, value);
1933 }
1934
1935 static void
1936 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1937 const struct radv_image_view *iview,
1938 VkClearDepthStencilValue ds_clear_value)
1939 {
1940 VkImageSubresourceRange range = {
1941 .aspectMask = iview->aspect_mask,
1942 .baseMipLevel = iview->base_mip,
1943 .levelCount = iview->level_count,
1944 .baseArrayLayer = iview->base_layer,
1945 .layerCount = iview->layer_count,
1946 };
1947 uint32_t cond_val;
1948
1949 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1950 * depth clear value is 0.0f.
1951 */
1952 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1953
1954 radv_set_tc_compat_zrange_metadata(cmd_buffer, iview->image, &range,
1955 cond_val);
1956 }
1957
1958 /**
1959 * Update the clear depth/stencil values for this image.
1960 */
1961 void
1962 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1963 const struct radv_image_view *iview,
1964 VkClearDepthStencilValue ds_clear_value,
1965 VkImageAspectFlags aspects)
1966 {
1967 VkImageSubresourceRange range = {
1968 .aspectMask = iview->aspect_mask,
1969 .baseMipLevel = iview->base_mip,
1970 .levelCount = iview->level_count,
1971 .baseArrayLayer = iview->base_layer,
1972 .layerCount = iview->layer_count,
1973 };
1974 struct radv_image *image = iview->image;
1975
1976 assert(radv_image_has_htile(image));
1977
1978 radv_set_ds_clear_metadata(cmd_buffer, iview->image, &range,
1979 ds_clear_value, aspects);
1980
1981 if (radv_image_is_tc_compat_htile(image) &&
1982 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1983 radv_update_tc_compat_zrange_metadata(cmd_buffer, iview,
1984 ds_clear_value);
1985 }
1986
1987 radv_update_bound_fast_clear_ds(cmd_buffer, iview, ds_clear_value,
1988 aspects);
1989 }
1990
1991 /**
1992 * Load the clear depth/stencil values from the image's metadata.
1993 */
1994 static void
1995 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1996 const struct radv_image_view *iview)
1997 {
1998 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1999 const struct radv_image *image = iview->image;
2000 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
2001 uint64_t va = radv_get_ds_clear_value_va(image, iview->base_mip);
2002 unsigned reg_offset = 0, reg_count = 0;
2003
2004 if (!radv_image_has_htile(image))
2005 return;
2006
2007 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
2008 ++reg_count;
2009 } else {
2010 ++reg_offset;
2011 va += 4;
2012 }
2013 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
2014 ++reg_count;
2015
2016 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
2017
2018 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
2019 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG_INDEX, 3, 0));
2020 radeon_emit(cs, va);
2021 radeon_emit(cs, va >> 32);
2022 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
2023 radeon_emit(cs, reg_count);
2024 } else {
2025 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2026 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2027 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2028 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
2029 radeon_emit(cs, va);
2030 radeon_emit(cs, va >> 32);
2031 radeon_emit(cs, reg >> 2);
2032 radeon_emit(cs, 0);
2033
2034 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
2035 radeon_emit(cs, 0);
2036 }
2037 }
2038
2039 /*
2040 * With DCC some colors don't require CMASK elimination before being
2041 * used as a texture. This sets a predicate value to determine if the
2042 * cmask eliminate is required.
2043 */
2044 void
2045 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
2046 struct radv_image *image,
2047 const VkImageSubresourceRange *range, bool value)
2048 {
2049 uint64_t pred_val = value;
2050 uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
2051 uint32_t level_count = radv_get_levelCount(image, range);
2052 uint32_t count = 2 * level_count;
2053
2054 assert(radv_dcc_enabled(image, range->baseMipLevel));
2055
2056 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
2057 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
2058 S_370_WR_CONFIRM(1) |
2059 S_370_ENGINE_SEL(V_370_PFP));
2060 radeon_emit(cmd_buffer->cs, va);
2061 radeon_emit(cmd_buffer->cs, va >> 32);
2062
2063 for (uint32_t l = 0; l < level_count; l++) {
2064 radeon_emit(cmd_buffer->cs, pred_val);
2065 radeon_emit(cmd_buffer->cs, pred_val >> 32);
2066 }
2067 }
2068
2069 /**
2070 * Update the DCC predicate to reflect the compression state.
2071 */
2072 void
2073 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
2074 struct radv_image *image,
2075 const VkImageSubresourceRange *range, bool value)
2076 {
2077 uint64_t pred_val = value;
2078 uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
2079 uint32_t level_count = radv_get_levelCount(image, range);
2080 uint32_t count = 2 * level_count;
2081
2082 assert(radv_dcc_enabled(image, range->baseMipLevel));
2083
2084 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
2085 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
2086 S_370_WR_CONFIRM(1) |
2087 S_370_ENGINE_SEL(V_370_PFP));
2088 radeon_emit(cmd_buffer->cs, va);
2089 radeon_emit(cmd_buffer->cs, va >> 32);
2090
2091 for (uint32_t l = 0; l < level_count; l++) {
2092 radeon_emit(cmd_buffer->cs, pred_val);
2093 radeon_emit(cmd_buffer->cs, pred_val >> 32);
2094 }
2095 }
2096
2097 /**
2098 * Update the fast clear color values if the image is bound as a color buffer.
2099 */
2100 static void
2101 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
2102 struct radv_image *image,
2103 int cb_idx,
2104 uint32_t color_values[2])
2105 {
2106 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2107 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2108 uint32_t att_idx;
2109
2110 if (!cmd_buffer->state.attachments || !subpass)
2111 return;
2112
2113 att_idx = subpass->color_attachments[cb_idx].attachment;
2114 if (att_idx == VK_ATTACHMENT_UNUSED)
2115 return;
2116
2117 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
2118 return;
2119
2120 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
2121 radeon_emit(cs, color_values[0]);
2122 radeon_emit(cs, color_values[1]);
2123
2124 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2125 }
2126
2127 /**
2128 * Set the clear color values to the image's metadata.
2129 */
2130 static void
2131 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
2132 struct radv_image *image,
2133 const VkImageSubresourceRange *range,
2134 uint32_t color_values[2])
2135 {
2136 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2137 uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
2138 uint32_t level_count = radv_get_levelCount(image, range);
2139 uint32_t count = 2 * level_count;
2140
2141 assert(radv_image_has_cmask(image) ||
2142 radv_dcc_enabled(image, range->baseMipLevel));
2143
2144 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
2145 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
2146 S_370_WR_CONFIRM(1) |
2147 S_370_ENGINE_SEL(V_370_PFP));
2148 radeon_emit(cs, va);
2149 radeon_emit(cs, va >> 32);
2150
2151 for (uint32_t l = 0; l < level_count; l++) {
2152 radeon_emit(cs, color_values[0]);
2153 radeon_emit(cs, color_values[1]);
2154 }
2155 }
2156
2157 /**
2158 * Update the clear color values for this image.
2159 */
2160 void
2161 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
2162 const struct radv_image_view *iview,
2163 int cb_idx,
2164 uint32_t color_values[2])
2165 {
2166 struct radv_image *image = iview->image;
2167 VkImageSubresourceRange range = {
2168 .aspectMask = iview->aspect_mask,
2169 .baseMipLevel = iview->base_mip,
2170 .levelCount = iview->level_count,
2171 .baseArrayLayer = iview->base_layer,
2172 .layerCount = iview->layer_count,
2173 };
2174
2175 assert(radv_image_has_cmask(image) ||
2176 radv_dcc_enabled(image, iview->base_mip));
2177
2178 radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
2179
2180 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
2181 color_values);
2182 }
2183
2184 /**
2185 * Load the clear color values from the image's metadata.
2186 */
2187 static void
2188 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
2189 struct radv_image_view *iview,
2190 int cb_idx)
2191 {
2192 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2193 struct radv_image *image = iview->image;
2194 uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
2195
2196 if (!radv_image_has_cmask(image) &&
2197 !radv_dcc_enabled(image, iview->base_mip))
2198 return;
2199
2200 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
2201
2202 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
2203 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG_INDEX, 3, cmd_buffer->state.predicating));
2204 radeon_emit(cs, va);
2205 radeon_emit(cs, va >> 32);
2206 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
2207 radeon_emit(cs, 2);
2208 } else {
2209 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
2210 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2211 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2212 COPY_DATA_COUNT_SEL);
2213 radeon_emit(cs, va);
2214 radeon_emit(cs, va >> 32);
2215 radeon_emit(cs, reg >> 2);
2216 radeon_emit(cs, 0);
2217
2218 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
2219 radeon_emit(cs, 0);
2220 }
2221 }
2222
2223 static void
2224 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
2225 {
2226 int i;
2227 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
2228 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2229
2230 /* this may happen for inherited secondary recording */
2231 if (!framebuffer)
2232 return;
2233
2234 for (i = 0; i < 8; ++i) {
2235 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
2236 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2237 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2238 continue;
2239 }
2240
2241 int idx = subpass->color_attachments[i].attachment;
2242 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
2243 VkImageLayout layout = subpass->color_attachments[i].layout;
2244 bool in_render_loop = subpass->color_attachments[i].in_render_loop;
2245
2246 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, iview->bo);
2247
2248 assert(iview->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
2249 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
2250 radv_emit_fb_color_state(cmd_buffer, i, &cmd_buffer->state.attachments[idx].cb, iview, layout, in_render_loop);
2251
2252 radv_load_color_clear_metadata(cmd_buffer, iview, i);
2253 }
2254
2255 if (subpass->depth_stencil_attachment) {
2256 int idx = subpass->depth_stencil_attachment->attachment;
2257 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
2258 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
2259 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
2260 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, cmd_buffer->state.attachments[idx].iview->bo);
2261
2262 radv_emit_fb_ds_state(cmd_buffer, &cmd_buffer->state.attachments[idx].ds, iview, layout, in_render_loop);
2263
2264 if (cmd_buffer->state.attachments[idx].ds.offset_scale != cmd_buffer->state.offset_scale) {
2265 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2266 cmd_buffer->state.offset_scale = cmd_buffer->state.attachments[idx].ds.offset_scale;
2267 }
2268 radv_load_ds_clear_metadata(cmd_buffer, iview);
2269 } else {
2270 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9)
2271 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
2272 else
2273 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
2274
2275 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
2276 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
2277 }
2278 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2279 S_028208_BR_X(framebuffer->width) |
2280 S_028208_BR_Y(framebuffer->height));
2281
2282 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
2283 bool disable_constant_encode =
2284 cmd_buffer->device->physical_device->rad_info.has_dcc_constant_encode;
2285 enum chip_class chip_class =
2286 cmd_buffer->device->physical_device->rad_info.chip_class;
2287 uint8_t watermark = chip_class >= GFX10 ? 6 : 4;
2288
2289 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
2290 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class <= GFX9) |
2291 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
2292 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
2293 }
2294
2295 if (cmd_buffer->device->dfsm_allowed) {
2296 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2297 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
2298 }
2299
2300 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
2301 }
2302
2303 static void
2304 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer, bool indirect)
2305 {
2306 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2307 struct radv_cmd_state *state = &cmd_buffer->state;
2308
2309 if (state->index_type != state->last_index_type) {
2310 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2311 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2312 cs, R_03090C_VGT_INDEX_TYPE,
2313 2, state->index_type);
2314 } else {
2315 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2316 radeon_emit(cs, state->index_type);
2317 }
2318
2319 state->last_index_type = state->index_type;
2320 }
2321
2322 /* For the direct indexed draws we use DRAW_INDEX_2, which includes
2323 * the index_va and max_index_count already. */
2324 if (!indirect)
2325 return;
2326
2327 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2328 radeon_emit(cs, state->index_va);
2329 radeon_emit(cs, state->index_va >> 32);
2330
2331 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2332 radeon_emit(cs, state->max_index_count);
2333
2334 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
2335 }
2336
2337 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
2338 {
2339 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
2340 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2341 uint32_t pa_sc_mode_cntl_1 =
2342 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
2343 uint32_t db_count_control;
2344
2345 if(!cmd_buffer->state.active_occlusion_queries) {
2346 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2347 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2348 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2349 has_perfect_queries) {
2350 /* Re-enable out-of-order rasterization if the
2351 * bound pipeline supports it and if it's has
2352 * been disabled before starting any perfect
2353 * occlusion queries.
2354 */
2355 radeon_set_context_reg(cmd_buffer->cs,
2356 R_028A4C_PA_SC_MODE_CNTL_1,
2357 pa_sc_mode_cntl_1);
2358 }
2359 }
2360 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
2361 } else {
2362 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2363 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
2364 bool gfx10_perfect = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10 && has_perfect_queries;
2365
2366 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2367 /* Always enable PERFECT_ZPASS_COUNTS due to issues with partially
2368 * covered tiles, discards, and early depth testing. For more details,
2369 * see https://gitlab.freedesktop.org/mesa/mesa/-/issues/3218 */
2370 db_count_control =
2371 S_028004_PERFECT_ZPASS_COUNTS(1) |
2372 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
2373 S_028004_SAMPLE_RATE(sample_rate) |
2374 S_028004_ZPASS_ENABLE(1) |
2375 S_028004_SLICE_EVEN_ENABLE(1) |
2376 S_028004_SLICE_ODD_ENABLE(1);
2377
2378 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2379 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2380 has_perfect_queries) {
2381 /* If the bound pipeline has enabled
2382 * out-of-order rasterization, we should
2383 * disable it before starting any perfect
2384 * occlusion queries.
2385 */
2386 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
2387
2388 radeon_set_context_reg(cmd_buffer->cs,
2389 R_028A4C_PA_SC_MODE_CNTL_1,
2390 pa_sc_mode_cntl_1);
2391 }
2392 } else {
2393 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
2394 S_028004_SAMPLE_RATE(sample_rate);
2395 }
2396 }
2397
2398 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
2399
2400 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2401 }
2402
2403 static void
2404 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
2405 {
2406 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
2407
2408 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
2409 radv_emit_viewport(cmd_buffer);
2410
2411 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
2412 !cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
2413 radv_emit_scissor(cmd_buffer);
2414
2415 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
2416 radv_emit_line_width(cmd_buffer);
2417
2418 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
2419 radv_emit_blend_constants(cmd_buffer);
2420
2421 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
2422 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
2423 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
2424 radv_emit_stencil(cmd_buffer);
2425
2426 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
2427 radv_emit_depth_bounds(cmd_buffer);
2428
2429 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
2430 radv_emit_depth_bias(cmd_buffer);
2431
2432 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
2433 radv_emit_discard_rectangle(cmd_buffer);
2434
2435 if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)
2436 radv_emit_sample_locations(cmd_buffer);
2437
2438 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE)
2439 radv_emit_line_stipple(cmd_buffer);
2440
2441 if (states & (RADV_CMD_DIRTY_DYNAMIC_CULL_MODE |
2442 RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE))
2443 radv_emit_culling(cmd_buffer, states);
2444
2445 if (states & RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY)
2446 radv_emit_primitive_topology(cmd_buffer);
2447
2448 if (states & (RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE |
2449 RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE |
2450 RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP |
2451 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE |
2452 RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE |
2453 RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP))
2454 radv_emit_depth_control(cmd_buffer, states);
2455
2456 if (states & RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP)
2457 radv_emit_stencil_control(cmd_buffer);
2458
2459 cmd_buffer->state.dirty &= ~states;
2460 }
2461
2462 static void
2463 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
2464 VkPipelineBindPoint bind_point)
2465 {
2466 struct radv_descriptor_state *descriptors_state =
2467 radv_get_descriptors_state(cmd_buffer, bind_point);
2468 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
2469 unsigned bo_offset;
2470
2471 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
2472 set->mapped_ptr,
2473 &bo_offset))
2474 return;
2475
2476 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2477 set->va += bo_offset;
2478 }
2479
2480 static void
2481 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
2482 VkPipelineBindPoint bind_point)
2483 {
2484 struct radv_descriptor_state *descriptors_state =
2485 radv_get_descriptors_state(cmd_buffer, bind_point);
2486 uint32_t size = MAX_SETS * 4;
2487 uint32_t offset;
2488 void *ptr;
2489
2490 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
2491 256, &offset, &ptr))
2492 return;
2493
2494 for (unsigned i = 0; i < MAX_SETS; i++) {
2495 uint32_t *uptr = ((uint32_t *)ptr) + i;
2496 uint64_t set_va = 0;
2497 struct radv_descriptor_set *set = descriptors_state->sets[i];
2498 if (descriptors_state->valid & (1u << i))
2499 set_va = set->va;
2500 uptr[0] = set_va & 0xffffffff;
2501 }
2502
2503 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2504 va += offset;
2505
2506 if (cmd_buffer->state.pipeline) {
2507 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
2508 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2509 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2510
2511 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
2512 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
2513 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2514
2515 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
2516 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2517 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2518
2519 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2520 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
2521 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2522
2523 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2524 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
2525 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2526 }
2527
2528 if (cmd_buffer->state.compute_pipeline)
2529 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
2530 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2531 }
2532
2533 static void
2534 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
2535 VkShaderStageFlags stages)
2536 {
2537 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2538 VK_PIPELINE_BIND_POINT_COMPUTE :
2539 VK_PIPELINE_BIND_POINT_GRAPHICS;
2540 struct radv_descriptor_state *descriptors_state =
2541 radv_get_descriptors_state(cmd_buffer, bind_point);
2542 struct radv_cmd_state *state = &cmd_buffer->state;
2543 bool flush_indirect_descriptors;
2544
2545 if (!descriptors_state->dirty)
2546 return;
2547
2548 if (descriptors_state->push_dirty)
2549 radv_flush_push_descriptors(cmd_buffer, bind_point);
2550
2551 flush_indirect_descriptors =
2552 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
2553 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
2554 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
2555 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
2556
2557 if (flush_indirect_descriptors)
2558 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
2559
2560 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2561 cmd_buffer->cs,
2562 MAX_SETS * MESA_SHADER_STAGES * 4);
2563
2564 if (cmd_buffer->state.pipeline) {
2565 radv_foreach_stage(stage, stages) {
2566 if (!cmd_buffer->state.pipeline->shaders[stage])
2567 continue;
2568
2569 radv_emit_descriptor_pointers(cmd_buffer,
2570 cmd_buffer->state.pipeline,
2571 descriptors_state, stage);
2572 }
2573 }
2574
2575 if (cmd_buffer->state.compute_pipeline &&
2576 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
2577 radv_emit_descriptor_pointers(cmd_buffer,
2578 cmd_buffer->state.compute_pipeline,
2579 descriptors_state,
2580 MESA_SHADER_COMPUTE);
2581 }
2582
2583 descriptors_state->dirty = 0;
2584 descriptors_state->push_dirty = false;
2585
2586 assert(cmd_buffer->cs->cdw <= cdw_max);
2587
2588 if (unlikely(cmd_buffer->device->trace_bo))
2589 radv_save_descriptors(cmd_buffer, bind_point);
2590 }
2591
2592 static void
2593 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
2594 VkShaderStageFlags stages)
2595 {
2596 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
2597 ? cmd_buffer->state.compute_pipeline
2598 : cmd_buffer->state.pipeline;
2599 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2600 VK_PIPELINE_BIND_POINT_COMPUTE :
2601 VK_PIPELINE_BIND_POINT_GRAPHICS;
2602 struct radv_descriptor_state *descriptors_state =
2603 radv_get_descriptors_state(cmd_buffer, bind_point);
2604 struct radv_pipeline_layout *layout = pipeline->layout;
2605 struct radv_shader_variant *shader, *prev_shader;
2606 bool need_push_constants = false;
2607 unsigned offset;
2608 void *ptr;
2609 uint64_t va;
2610
2611 stages &= cmd_buffer->push_constant_stages;
2612 if (!stages ||
2613 (!layout->push_constant_size && !layout->dynamic_offset_count))
2614 return;
2615
2616 radv_foreach_stage(stage, stages) {
2617 shader = radv_get_shader(pipeline, stage);
2618 if (!shader)
2619 continue;
2620
2621 need_push_constants |= shader->info.loads_push_constants;
2622 need_push_constants |= shader->info.loads_dynamic_offsets;
2623
2624 uint8_t base = shader->info.base_inline_push_consts;
2625 uint8_t count = shader->info.num_inline_push_consts;
2626
2627 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
2628 AC_UD_INLINE_PUSH_CONSTANTS,
2629 count,
2630 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
2631 }
2632
2633 if (need_push_constants) {
2634 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
2635 16 * layout->dynamic_offset_count,
2636 256, &offset, &ptr))
2637 return;
2638
2639 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
2640 memcpy((char*)ptr + layout->push_constant_size,
2641 descriptors_state->dynamic_buffers,
2642 16 * layout->dynamic_offset_count);
2643
2644 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2645 va += offset;
2646
2647 ASSERTED unsigned cdw_max =
2648 radeon_check_space(cmd_buffer->device->ws,
2649 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
2650
2651 prev_shader = NULL;
2652 radv_foreach_stage(stage, stages) {
2653 shader = radv_get_shader(pipeline, stage);
2654
2655 /* Avoid redundantly emitting the address for merged stages. */
2656 if (shader && shader != prev_shader) {
2657 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
2658 AC_UD_PUSH_CONSTANTS, va);
2659
2660 prev_shader = shader;
2661 }
2662 }
2663 assert(cmd_buffer->cs->cdw <= cdw_max);
2664 }
2665
2666 cmd_buffer->push_constant_stages &= ~stages;
2667 }
2668
2669 static void
2670 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
2671 bool pipeline_is_dirty)
2672 {
2673 if ((pipeline_is_dirty ||
2674 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
2675 cmd_buffer->state.pipeline->num_vertex_bindings &&
2676 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.has_vertex_buffers) {
2677 unsigned vb_offset;
2678 void *vb_ptr;
2679 uint32_t i = 0;
2680 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
2681 uint64_t va;
2682
2683 /* allocate some descriptor state for vertex buffers */
2684 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2685 &vb_offset, &vb_ptr))
2686 return;
2687
2688 for (i = 0; i < count; i++) {
2689 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2690 uint32_t offset;
2691 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2692 unsigned num_records;
2693 unsigned stride;
2694
2695 if (!buffer)
2696 continue;
2697
2698 va = radv_buffer_get_va(buffer->bo);
2699
2700 offset = cmd_buffer->vertex_bindings[i].offset;
2701 va += offset + buffer->offset;
2702
2703 if (cmd_buffer->vertex_bindings[i].size) {
2704 num_records = cmd_buffer->vertex_bindings[i].size;
2705 } else {
2706 num_records = buffer->size - offset;
2707 }
2708
2709 if (cmd_buffer->state.pipeline->graphics.uses_dynamic_stride) {
2710 stride = cmd_buffer->vertex_bindings[i].stride;
2711 } else {
2712 stride = cmd_buffer->state.pipeline->binding_stride[i];
2713 }
2714
2715 if (cmd_buffer->device->physical_device->rad_info.chip_class != GFX8 && stride)
2716 num_records /= stride;
2717
2718 desc[0] = va;
2719 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2720 desc[2] = num_records;
2721 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2722 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2723 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2724 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2725
2726 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2727 /* OOB_SELECT chooses the out-of-bounds check:
2728 * - 1: index >= NUM_RECORDS (Structured)
2729 * - 3: offset >= NUM_RECORDS (Raw)
2730 */
2731 int oob_select = stride ? V_008F0C_OOB_SELECT_STRUCTURED : V_008F0C_OOB_SELECT_RAW;
2732
2733 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT) |
2734 S_008F0C_OOB_SELECT(oob_select) |
2735 S_008F0C_RESOURCE_LEVEL(1);
2736 } else {
2737 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2738 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2739 }
2740 }
2741
2742 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2743 va += vb_offset;
2744
2745 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2746 AC_UD_VS_VERTEX_BUFFERS, va);
2747
2748 cmd_buffer->state.vb_va = va;
2749 cmd_buffer->state.vb_size = count * 16;
2750 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2751 }
2752 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2753 }
2754
2755 static void
2756 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2757 {
2758 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2759 struct radv_userdata_info *loc;
2760 uint32_t base_reg;
2761
2762 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2763 if (!radv_get_shader(pipeline, stage))
2764 continue;
2765
2766 loc = radv_lookup_user_sgpr(pipeline, stage,
2767 AC_UD_STREAMOUT_BUFFERS);
2768 if (loc->sgpr_idx == -1)
2769 continue;
2770
2771 base_reg = pipeline->user_data_0[stage];
2772
2773 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2774 base_reg + loc->sgpr_idx * 4, va, false);
2775 }
2776
2777 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
2778 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2779 if (loc->sgpr_idx != -1) {
2780 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2781
2782 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2783 base_reg + loc->sgpr_idx * 4, va, false);
2784 }
2785 }
2786 }
2787
2788 static void
2789 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2790 {
2791 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2792 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2793 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2794 unsigned so_offset;
2795 void *so_ptr;
2796 uint64_t va;
2797
2798 /* Allocate some descriptor state for streamout buffers. */
2799 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2800 MAX_SO_BUFFERS * 16, 256,
2801 &so_offset, &so_ptr))
2802 return;
2803
2804 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2805 struct radv_buffer *buffer = sb[i].buffer;
2806 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2807
2808 if (!(so->enabled_mask & (1 << i)))
2809 continue;
2810
2811 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2812
2813 va += sb[i].offset;
2814
2815 /* Set the descriptor.
2816 *
2817 * On GFX8, the format must be non-INVALID, otherwise
2818 * the buffer will be considered not bound and store
2819 * instructions will be no-ops.
2820 */
2821 uint32_t size = 0xffffffff;
2822
2823 /* Compute the correct buffer size for NGG streamout
2824 * because it's used to determine the max emit per
2825 * buffer.
2826 */
2827 if (cmd_buffer->device->physical_device->use_ngg_streamout)
2828 size = buffer->size - sb[i].offset;
2829
2830 desc[0] = va;
2831 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2832 desc[2] = size;
2833 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2834 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2835 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2836 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2837
2838 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2839 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2840 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
2841 S_008F0C_RESOURCE_LEVEL(1);
2842 } else {
2843 desc[3] |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2844 }
2845 }
2846
2847 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2848 va += so_offset;
2849
2850 radv_emit_streamout_buffers(cmd_buffer, va);
2851 }
2852
2853 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2854 }
2855
2856 static void
2857 radv_flush_ngg_gs_state(struct radv_cmd_buffer *cmd_buffer)
2858 {
2859 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2860 struct radv_userdata_info *loc;
2861 uint32_t ngg_gs_state = 0;
2862 uint32_t base_reg;
2863
2864 if (!radv_pipeline_has_gs(pipeline) ||
2865 !radv_pipeline_has_ngg(pipeline))
2866 return;
2867
2868 /* By default NGG GS queries are disabled but they are enabled if the
2869 * command buffer has active GDS queries or if it's a secondary command
2870 * buffer that inherits the number of generated primitives.
2871 */
2872 if (cmd_buffer->state.active_pipeline_gds_queries ||
2873 (cmd_buffer->state.inherited_pipeline_statistics & VK_QUERY_PIPELINE_STATISTIC_GEOMETRY_SHADER_PRIMITIVES_BIT))
2874 ngg_gs_state = 1;
2875
2876 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_GEOMETRY,
2877 AC_UD_NGG_GS_STATE);
2878 base_reg = pipeline->user_data_0[MESA_SHADER_GEOMETRY];
2879 assert(loc->sgpr_idx != -1);
2880
2881 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
2882 ngg_gs_state);
2883 }
2884
2885 static void
2886 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2887 {
2888 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2889 radv_flush_streamout_descriptors(cmd_buffer);
2890 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2891 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2892 radv_flush_ngg_gs_state(cmd_buffer);
2893 }
2894
2895 struct radv_draw_info {
2896 /**
2897 * Number of vertices.
2898 */
2899 uint32_t count;
2900
2901 /**
2902 * Index of the first vertex.
2903 */
2904 int32_t vertex_offset;
2905
2906 /**
2907 * First instance id.
2908 */
2909 uint32_t first_instance;
2910
2911 /**
2912 * Number of instances.
2913 */
2914 uint32_t instance_count;
2915
2916 /**
2917 * First index (indexed draws only).
2918 */
2919 uint32_t first_index;
2920
2921 /**
2922 * Whether it's an indexed draw.
2923 */
2924 bool indexed;
2925
2926 /**
2927 * Indirect draw parameters resource.
2928 */
2929 struct radv_buffer *indirect;
2930 uint64_t indirect_offset;
2931 uint32_t stride;
2932
2933 /**
2934 * Draw count parameters resource.
2935 */
2936 struct radv_buffer *count_buffer;
2937 uint64_t count_buffer_offset;
2938
2939 /**
2940 * Stream output parameters resource.
2941 */
2942 struct radv_buffer *strmout_buffer;
2943 uint64_t strmout_buffer_offset;
2944 };
2945
2946 static uint32_t
2947 radv_get_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
2948 {
2949 switch (cmd_buffer->state.index_type) {
2950 case V_028A7C_VGT_INDEX_8:
2951 return 0xffu;
2952 case V_028A7C_VGT_INDEX_16:
2953 return 0xffffu;
2954 case V_028A7C_VGT_INDEX_32:
2955 return 0xffffffffu;
2956 default:
2957 unreachable("invalid index type");
2958 }
2959 }
2960
2961 static void
2962 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
2963 bool instanced_draw, bool indirect_draw,
2964 bool count_from_stream_output,
2965 uint32_t draw_vertex_count)
2966 {
2967 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2968 struct radv_cmd_state *state = &cmd_buffer->state;
2969 unsigned topology = state->dynamic.primitive_topology;
2970 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2971 unsigned ia_multi_vgt_param;
2972
2973 ia_multi_vgt_param =
2974 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
2975 indirect_draw,
2976 count_from_stream_output,
2977 draw_vertex_count,
2978 topology);
2979
2980 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2981 if (info->chip_class == GFX9) {
2982 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2983 cs,
2984 R_030960_IA_MULTI_VGT_PARAM,
2985 4, ia_multi_vgt_param);
2986 } else if (info->chip_class >= GFX7) {
2987 radeon_set_context_reg_idx(cs,
2988 R_028AA8_IA_MULTI_VGT_PARAM,
2989 1, ia_multi_vgt_param);
2990 } else {
2991 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2992 ia_multi_vgt_param);
2993 }
2994 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2995 }
2996 }
2997
2998 static void
2999 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
3000 const struct radv_draw_info *draw_info)
3001 {
3002 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
3003 struct radv_cmd_state *state = &cmd_buffer->state;
3004 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3005 int32_t primitive_reset_en;
3006
3007 /* Draw state. */
3008 if (info->chip_class < GFX10) {
3009 si_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
3010 draw_info->indirect,
3011 !!draw_info->strmout_buffer,
3012 draw_info->indirect ? 0 : draw_info->count);
3013 }
3014
3015 /* Primitive restart. */
3016 primitive_reset_en =
3017 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
3018
3019 if (primitive_reset_en != state->last_primitive_reset_en) {
3020 state->last_primitive_reset_en = primitive_reset_en;
3021 if (info->chip_class >= GFX9) {
3022 radeon_set_uconfig_reg(cs,
3023 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
3024 primitive_reset_en);
3025 } else {
3026 radeon_set_context_reg(cs,
3027 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
3028 primitive_reset_en);
3029 }
3030 }
3031
3032 if (primitive_reset_en) {
3033 uint32_t primitive_reset_index =
3034 radv_get_primitive_reset_index(cmd_buffer);
3035
3036 if (primitive_reset_index != state->last_primitive_reset_index) {
3037 radeon_set_context_reg(cs,
3038 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
3039 primitive_reset_index);
3040 state->last_primitive_reset_index = primitive_reset_index;
3041 }
3042 }
3043
3044 if (draw_info->strmout_buffer) {
3045 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
3046
3047 va += draw_info->strmout_buffer->offset +
3048 draw_info->strmout_buffer_offset;
3049
3050 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
3051 draw_info->stride);
3052
3053 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3054 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
3055 COPY_DATA_DST_SEL(COPY_DATA_REG) |
3056 COPY_DATA_WR_CONFIRM);
3057 radeon_emit(cs, va);
3058 radeon_emit(cs, va >> 32);
3059 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
3060 radeon_emit(cs, 0); /* unused */
3061
3062 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
3063 }
3064 }
3065
3066 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
3067 VkPipelineStageFlags src_stage_mask)
3068 {
3069 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
3070 VK_PIPELINE_STAGE_TRANSFER_BIT |
3071 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
3072 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
3073 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
3074 }
3075
3076 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
3077 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
3078 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
3079 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
3080 VK_PIPELINE_STAGE_TRANSFER_BIT |
3081 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
3082 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
3083 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
3084 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
3085 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
3086 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
3087 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
3088 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
3089 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
3090 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
3091 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
3092 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
3093 }
3094 }
3095
3096 static enum radv_cmd_flush_bits
3097 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
3098 VkAccessFlags src_flags,
3099 struct radv_image *image)
3100 {
3101 bool flush_CB_meta = true, flush_DB_meta = true;
3102 enum radv_cmd_flush_bits flush_bits = 0;
3103 uint32_t b;
3104
3105 if (image) {
3106 if (!radv_image_has_CB_metadata(image))
3107 flush_CB_meta = false;
3108 if (!radv_image_has_htile(image))
3109 flush_DB_meta = false;
3110 }
3111
3112 for_each_bit(b, src_flags) {
3113 switch ((VkAccessFlagBits)(1 << b)) {
3114 case VK_ACCESS_SHADER_WRITE_BIT:
3115 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
3116 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
3117 flush_bits |= RADV_CMD_FLAG_WB_L2;
3118 break;
3119 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
3120 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
3121 if (flush_CB_meta)
3122 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3123 break;
3124 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
3125 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
3126 if (flush_DB_meta)
3127 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3128 break;
3129 case VK_ACCESS_TRANSFER_WRITE_BIT:
3130 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3131 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3132 RADV_CMD_FLAG_INV_L2;
3133
3134 if (flush_CB_meta)
3135 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3136 if (flush_DB_meta)
3137 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3138 break;
3139 case VK_ACCESS_MEMORY_WRITE_BIT:
3140 flush_bits |= RADV_CMD_FLAG_INV_L2 |
3141 RADV_CMD_FLAG_WB_L2 |
3142 RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3143 RADV_CMD_FLAG_FLUSH_AND_INV_DB;
3144
3145 if (flush_CB_meta)
3146 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3147 if (flush_DB_meta)
3148 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3149 break;
3150 default:
3151 break;
3152 }
3153 }
3154 return flush_bits;
3155 }
3156
3157 static enum radv_cmd_flush_bits
3158 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
3159 VkAccessFlags dst_flags,
3160 struct radv_image *image)
3161 {
3162 bool flush_CB_meta = true, flush_DB_meta = true;
3163 enum radv_cmd_flush_bits flush_bits = 0;
3164 bool flush_CB = true, flush_DB = true;
3165 bool image_is_coherent = false;
3166 uint32_t b;
3167
3168 if (image) {
3169 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
3170 flush_CB = false;
3171 flush_DB = false;
3172 }
3173
3174 if (!radv_image_has_CB_metadata(image))
3175 flush_CB_meta = false;
3176 if (!radv_image_has_htile(image))
3177 flush_DB_meta = false;
3178
3179 /* TODO: implement shader coherent for GFX10 */
3180
3181 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
3182 if (image->info.samples == 1 &&
3183 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
3184 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
3185 !vk_format_is_stencil(image->vk_format)) {
3186 /* Single-sample color and single-sample depth
3187 * (not stencil) are coherent with shaders on
3188 * GFX9.
3189 */
3190 image_is_coherent = true;
3191 }
3192 }
3193 }
3194
3195 for_each_bit(b, dst_flags) {
3196 switch ((VkAccessFlagBits)(1 << b)) {
3197 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
3198 case VK_ACCESS_INDEX_READ_BIT:
3199 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
3200 break;
3201 case VK_ACCESS_UNIFORM_READ_BIT:
3202 flush_bits |= RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_SCACHE;
3203 break;
3204 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
3205 case VK_ACCESS_TRANSFER_READ_BIT:
3206 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
3207 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
3208 RADV_CMD_FLAG_INV_L2;
3209 break;
3210 case VK_ACCESS_SHADER_READ_BIT:
3211 flush_bits |= RADV_CMD_FLAG_INV_VCACHE;
3212 /* Unlike LLVM, ACO uses SMEM for SSBOs and we have to
3213 * invalidate the scalar cache. */
3214 if (!cmd_buffer->device->physical_device->use_llvm)
3215 flush_bits |= RADV_CMD_FLAG_INV_SCACHE;
3216
3217 if (!image_is_coherent)
3218 flush_bits |= RADV_CMD_FLAG_INV_L2;
3219 break;
3220 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
3221 if (flush_CB)
3222 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
3223 if (flush_CB_meta)
3224 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3225 break;
3226 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
3227 if (flush_DB)
3228 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
3229 if (flush_DB_meta)
3230 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3231 break;
3232 case VK_ACCESS_MEMORY_READ_BIT:
3233 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
3234 RADV_CMD_FLAG_INV_SCACHE |
3235 RADV_CMD_FLAG_INV_L2;
3236 if (flush_CB)
3237 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
3238 if (flush_CB_meta)
3239 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3240 if (flush_DB)
3241 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
3242 if (flush_DB_meta)
3243 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3244 break;
3245 default:
3246 break;
3247 }
3248 }
3249 return flush_bits;
3250 }
3251
3252 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
3253 const struct radv_subpass_barrier *barrier)
3254 {
3255 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
3256 NULL);
3257 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
3258 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
3259 NULL);
3260 }
3261
3262 uint32_t
3263 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
3264 {
3265 struct radv_cmd_state *state = &cmd_buffer->state;
3266 uint32_t subpass_id = state->subpass - state->pass->subpasses;
3267
3268 /* The id of this subpass shouldn't exceed the number of subpasses in
3269 * this render pass minus 1.
3270 */
3271 assert(subpass_id < state->pass->subpass_count);
3272 return subpass_id;
3273 }
3274
3275 static struct radv_sample_locations_state *
3276 radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer,
3277 uint32_t att_idx,
3278 bool begin_subpass)
3279 {
3280 struct radv_cmd_state *state = &cmd_buffer->state;
3281 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
3282 struct radv_image_view *view = state->attachments[att_idx].iview;
3283
3284 if (view->image->info.samples == 1)
3285 return NULL;
3286
3287 if (state->pass->attachments[att_idx].first_subpass_idx == subpass_id) {
3288 /* Return the initial sample locations if this is the initial
3289 * layout transition of the given subpass attachemnt.
3290 */
3291 if (state->attachments[att_idx].sample_location.count > 0)
3292 return &state->attachments[att_idx].sample_location;
3293 } else {
3294 /* Otherwise return the subpass sample locations if defined. */
3295 if (state->subpass_sample_locs) {
3296 /* Because the driver sets the current subpass before
3297 * initial layout transitions, we should use the sample
3298 * locations from the previous subpass to avoid an
3299 * off-by-one problem. Otherwise, use the sample
3300 * locations for the current subpass for final layout
3301 * transitions.
3302 */
3303 if (begin_subpass)
3304 subpass_id--;
3305
3306 for (uint32_t i = 0; i < state->num_subpass_sample_locs; i++) {
3307 if (state->subpass_sample_locs[i].subpass_idx == subpass_id)
3308 return &state->subpass_sample_locs[i].sample_location;
3309 }
3310 }
3311 }
3312
3313 return NULL;
3314 }
3315
3316 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
3317 struct radv_subpass_attachment att,
3318 bool begin_subpass)
3319 {
3320 unsigned idx = att.attachment;
3321 struct radv_image_view *view = cmd_buffer->state.attachments[idx].iview;
3322 struct radv_sample_locations_state *sample_locs;
3323 VkImageSubresourceRange range;
3324 range.aspectMask = view->aspect_mask;
3325 range.baseMipLevel = view->base_mip;
3326 range.levelCount = 1;
3327 range.baseArrayLayer = view->base_layer;
3328 range.layerCount = cmd_buffer->state.framebuffer->layers;
3329
3330 if (cmd_buffer->state.subpass->view_mask) {
3331 /* If the current subpass uses multiview, the driver might have
3332 * performed a fast color/depth clear to the whole image
3333 * (including all layers). To make sure the driver will
3334 * decompress the image correctly (if needed), we have to
3335 * account for the "real" number of layers. If the view mask is
3336 * sparse, this will decompress more layers than needed.
3337 */
3338 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
3339 }
3340
3341 /* Get the subpass sample locations for the given attachment, if NULL
3342 * is returned the driver will use the default HW locations.
3343 */
3344 sample_locs = radv_get_attachment_sample_locations(cmd_buffer, idx,
3345 begin_subpass);
3346
3347 /* Determine if the subpass uses separate depth/stencil layouts. */
3348 bool uses_separate_depth_stencil_layouts = false;
3349 if ((cmd_buffer->state.attachments[idx].current_layout !=
3350 cmd_buffer->state.attachments[idx].current_stencil_layout) ||
3351 (att.layout != att.stencil_layout)) {
3352 uses_separate_depth_stencil_layouts = true;
3353 }
3354
3355 /* For separate layouts, perform depth and stencil transitions
3356 * separately.
3357 */
3358 if (uses_separate_depth_stencil_layouts &&
3359 (range.aspectMask == (VK_IMAGE_ASPECT_DEPTH_BIT |
3360 VK_IMAGE_ASPECT_STENCIL_BIT))) {
3361 /* Depth-only transitions. */
3362 range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3363 radv_handle_image_transition(cmd_buffer,
3364 view->image,
3365 cmd_buffer->state.attachments[idx].current_layout,
3366 cmd_buffer->state.attachments[idx].current_in_render_loop,
3367 att.layout, att.in_render_loop,
3368 0, 0, &range, sample_locs);
3369
3370 /* Stencil-only transitions. */
3371 range.aspectMask = VK_IMAGE_ASPECT_STENCIL_BIT;
3372 radv_handle_image_transition(cmd_buffer,
3373 view->image,
3374 cmd_buffer->state.attachments[idx].current_stencil_layout,
3375 cmd_buffer->state.attachments[idx].current_in_render_loop,
3376 att.stencil_layout, att.in_render_loop,
3377 0, 0, &range, sample_locs);
3378 } else {
3379 radv_handle_image_transition(cmd_buffer,
3380 view->image,
3381 cmd_buffer->state.attachments[idx].current_layout,
3382 cmd_buffer->state.attachments[idx].current_in_render_loop,
3383 att.layout, att.in_render_loop,
3384 0, 0, &range, sample_locs);
3385 }
3386
3387 cmd_buffer->state.attachments[idx].current_layout = att.layout;
3388 cmd_buffer->state.attachments[idx].current_stencil_layout = att.stencil_layout;
3389 cmd_buffer->state.attachments[idx].current_in_render_loop = att.in_render_loop;
3390
3391
3392 }
3393
3394 void
3395 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
3396 const struct radv_subpass *subpass)
3397 {
3398 cmd_buffer->state.subpass = subpass;
3399
3400 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
3401 }
3402
3403 static VkResult
3404 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
3405 struct radv_render_pass *pass,
3406 const VkRenderPassBeginInfo *info)
3407 {
3408 const struct VkRenderPassSampleLocationsBeginInfoEXT *sample_locs =
3409 vk_find_struct_const(info->pNext,
3410 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT);
3411 struct radv_cmd_state *state = &cmd_buffer->state;
3412
3413 if (!sample_locs) {
3414 state->subpass_sample_locs = NULL;
3415 return VK_SUCCESS;
3416 }
3417
3418 for (uint32_t i = 0; i < sample_locs->attachmentInitialSampleLocationsCount; i++) {
3419 const VkAttachmentSampleLocationsEXT *att_sample_locs =
3420 &sample_locs->pAttachmentInitialSampleLocations[i];
3421 uint32_t att_idx = att_sample_locs->attachmentIndex;
3422 struct radv_image *image = cmd_buffer->state.attachments[att_idx].iview->image;
3423
3424 assert(vk_format_is_depth_or_stencil(image->vk_format));
3425
3426 /* From the Vulkan spec 1.1.108:
3427 *
3428 * "If the image referenced by the framebuffer attachment at
3429 * index attachmentIndex was not created with
3430 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
3431 * then the values specified in sampleLocationsInfo are
3432 * ignored."
3433 */
3434 if (!(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT))
3435 continue;
3436
3437 const VkSampleLocationsInfoEXT *sample_locs_info =
3438 &att_sample_locs->sampleLocationsInfo;
3439
3440 state->attachments[att_idx].sample_location.per_pixel =
3441 sample_locs_info->sampleLocationsPerPixel;
3442 state->attachments[att_idx].sample_location.grid_size =
3443 sample_locs_info->sampleLocationGridSize;
3444 state->attachments[att_idx].sample_location.count =
3445 sample_locs_info->sampleLocationsCount;
3446 typed_memcpy(&state->attachments[att_idx].sample_location.locations[0],
3447 sample_locs_info->pSampleLocations,
3448 sample_locs_info->sampleLocationsCount);
3449 }
3450
3451 state->subpass_sample_locs = vk_alloc(&cmd_buffer->pool->alloc,
3452 sample_locs->postSubpassSampleLocationsCount *
3453 sizeof(state->subpass_sample_locs[0]),
3454 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3455 if (state->subpass_sample_locs == NULL) {
3456 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3457 return cmd_buffer->record_result;
3458 }
3459
3460 state->num_subpass_sample_locs = sample_locs->postSubpassSampleLocationsCount;
3461
3462 for (uint32_t i = 0; i < sample_locs->postSubpassSampleLocationsCount; i++) {
3463 const VkSubpassSampleLocationsEXT *subpass_sample_locs_info =
3464 &sample_locs->pPostSubpassSampleLocations[i];
3465 const VkSampleLocationsInfoEXT *sample_locs_info =
3466 &subpass_sample_locs_info->sampleLocationsInfo;
3467
3468 state->subpass_sample_locs[i].subpass_idx =
3469 subpass_sample_locs_info->subpassIndex;
3470 state->subpass_sample_locs[i].sample_location.per_pixel =
3471 sample_locs_info->sampleLocationsPerPixel;
3472 state->subpass_sample_locs[i].sample_location.grid_size =
3473 sample_locs_info->sampleLocationGridSize;
3474 state->subpass_sample_locs[i].sample_location.count =
3475 sample_locs_info->sampleLocationsCount;
3476 typed_memcpy(&state->subpass_sample_locs[i].sample_location.locations[0],
3477 sample_locs_info->pSampleLocations,
3478 sample_locs_info->sampleLocationsCount);
3479 }
3480
3481 return VK_SUCCESS;
3482 }
3483
3484 static VkResult
3485 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
3486 struct radv_render_pass *pass,
3487 const VkRenderPassBeginInfo *info)
3488 {
3489 struct radv_cmd_state *state = &cmd_buffer->state;
3490 const struct VkRenderPassAttachmentBeginInfo *attachment_info = NULL;
3491
3492 if (info) {
3493 attachment_info = vk_find_struct_const(info->pNext,
3494 RENDER_PASS_ATTACHMENT_BEGIN_INFO);
3495 }
3496
3497
3498 if (pass->attachment_count == 0) {
3499 state->attachments = NULL;
3500 return VK_SUCCESS;
3501 }
3502
3503 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
3504 pass->attachment_count *
3505 sizeof(state->attachments[0]),
3506 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3507 if (state->attachments == NULL) {
3508 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3509 return cmd_buffer->record_result;
3510 }
3511
3512 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
3513 struct radv_render_pass_attachment *att = &pass->attachments[i];
3514 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
3515 VkImageAspectFlags clear_aspects = 0;
3516
3517 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
3518 /* color attachment */
3519 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3520 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
3521 }
3522 } else {
3523 /* depthstencil attachment */
3524 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
3525 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3526 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
3527 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3528 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
3529 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3530 }
3531 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3532 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3533 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3534 }
3535 }
3536
3537 state->attachments[i].pending_clear_aspects = clear_aspects;
3538 state->attachments[i].cleared_views = 0;
3539 if (clear_aspects && info) {
3540 assert(info->clearValueCount > i);
3541 state->attachments[i].clear_value = info->pClearValues[i];
3542 }
3543
3544 state->attachments[i].current_layout = att->initial_layout;
3545 state->attachments[i].current_stencil_layout = att->stencil_initial_layout;
3546 state->attachments[i].sample_location.count = 0;
3547
3548 struct radv_image_view *iview;
3549 if (attachment_info && attachment_info->attachmentCount > i) {
3550 iview = radv_image_view_from_handle(attachment_info->pAttachments[i]);
3551 } else {
3552 iview = state->framebuffer->attachments[i];
3553 }
3554
3555 state->attachments[i].iview = iview;
3556 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3557 radv_initialise_ds_surface(cmd_buffer->device, &state->attachments[i].ds, iview);
3558 } else {
3559 radv_initialise_color_surface(cmd_buffer->device, &state->attachments[i].cb, iview);
3560 }
3561 }
3562
3563 return VK_SUCCESS;
3564 }
3565
3566 VkResult radv_AllocateCommandBuffers(
3567 VkDevice _device,
3568 const VkCommandBufferAllocateInfo *pAllocateInfo,
3569 VkCommandBuffer *pCommandBuffers)
3570 {
3571 RADV_FROM_HANDLE(radv_device, device, _device);
3572 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
3573
3574 VkResult result = VK_SUCCESS;
3575 uint32_t i;
3576
3577 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
3578
3579 if (!list_is_empty(&pool->free_cmd_buffers)) {
3580 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
3581
3582 list_del(&cmd_buffer->pool_link);
3583 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
3584
3585 result = radv_reset_cmd_buffer(cmd_buffer);
3586 cmd_buffer->level = pAllocateInfo->level;
3587
3588 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
3589 } else {
3590 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
3591 &pCommandBuffers[i]);
3592 }
3593 if (result != VK_SUCCESS)
3594 break;
3595 }
3596
3597 if (result != VK_SUCCESS) {
3598 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
3599 i, pCommandBuffers);
3600
3601 /* From the Vulkan 1.0.66 spec:
3602 *
3603 * "vkAllocateCommandBuffers can be used to create multiple
3604 * command buffers. If the creation of any of those command
3605 * buffers fails, the implementation must destroy all
3606 * successfully created command buffer objects from this
3607 * command, set all entries of the pCommandBuffers array to
3608 * NULL and return the error."
3609 */
3610 memset(pCommandBuffers, 0,
3611 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
3612 }
3613
3614 return result;
3615 }
3616
3617 void radv_FreeCommandBuffers(
3618 VkDevice device,
3619 VkCommandPool commandPool,
3620 uint32_t commandBufferCount,
3621 const VkCommandBuffer *pCommandBuffers)
3622 {
3623 for (uint32_t i = 0; i < commandBufferCount; i++) {
3624 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
3625
3626 if (cmd_buffer) {
3627 if (cmd_buffer->pool) {
3628 list_del(&cmd_buffer->pool_link);
3629 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
3630 } else
3631 radv_cmd_buffer_destroy(cmd_buffer);
3632
3633 }
3634 }
3635 }
3636
3637 VkResult radv_ResetCommandBuffer(
3638 VkCommandBuffer commandBuffer,
3639 VkCommandBufferResetFlags flags)
3640 {
3641 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3642 return radv_reset_cmd_buffer(cmd_buffer);
3643 }
3644
3645 VkResult radv_BeginCommandBuffer(
3646 VkCommandBuffer commandBuffer,
3647 const VkCommandBufferBeginInfo *pBeginInfo)
3648 {
3649 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3650 VkResult result = VK_SUCCESS;
3651
3652 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
3653 /* If the command buffer has already been resetted with
3654 * vkResetCommandBuffer, no need to do it again.
3655 */
3656 result = radv_reset_cmd_buffer(cmd_buffer);
3657 if (result != VK_SUCCESS)
3658 return result;
3659 }
3660
3661 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
3662 cmd_buffer->state.last_primitive_reset_en = -1;
3663 cmd_buffer->state.last_index_type = -1;
3664 cmd_buffer->state.last_num_instances = -1;
3665 cmd_buffer->state.last_vertex_offset = -1;
3666 cmd_buffer->state.last_first_instance = -1;
3667 cmd_buffer->state.predication_type = -1;
3668 cmd_buffer->state.last_sx_ps_downconvert = -1;
3669 cmd_buffer->state.last_sx_blend_opt_epsilon = -1;
3670 cmd_buffer->state.last_sx_blend_opt_control = -1;
3671 cmd_buffer->usage_flags = pBeginInfo->flags;
3672
3673 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
3674 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
3675 assert(pBeginInfo->pInheritanceInfo);
3676 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
3677 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
3678
3679 struct radv_subpass *subpass =
3680 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
3681
3682 if (cmd_buffer->state.framebuffer) {
3683 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
3684 if (result != VK_SUCCESS)
3685 return result;
3686 }
3687
3688 cmd_buffer->state.inherited_pipeline_statistics =
3689 pBeginInfo->pInheritanceInfo->pipelineStatistics;
3690
3691 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3692 }
3693
3694 if (unlikely(cmd_buffer->device->trace_bo))
3695 radv_cmd_buffer_trace_emit(cmd_buffer);
3696
3697 radv_describe_begin_cmd_buffer(cmd_buffer);
3698
3699 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
3700
3701 return result;
3702 }
3703
3704 void radv_CmdBindVertexBuffers(
3705 VkCommandBuffer commandBuffer,
3706 uint32_t firstBinding,
3707 uint32_t bindingCount,
3708 const VkBuffer* pBuffers,
3709 const VkDeviceSize* pOffsets)
3710 {
3711 radv_CmdBindVertexBuffers2EXT(commandBuffer, firstBinding,
3712 bindingCount, pBuffers, pOffsets,
3713 NULL, NULL);
3714 }
3715
3716 void radv_CmdBindVertexBuffers2EXT(
3717 VkCommandBuffer commandBuffer,
3718 uint32_t firstBinding,
3719 uint32_t bindingCount,
3720 const VkBuffer* pBuffers,
3721 const VkDeviceSize* pOffsets,
3722 const VkDeviceSize* pSizes,
3723 const VkDeviceSize* pStrides)
3724 {
3725 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3726 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
3727 bool changed = false;
3728
3729 /* We have to defer setting up vertex buffer since we need the buffer
3730 * stride from the pipeline. */
3731
3732 assert(firstBinding + bindingCount <= MAX_VBS);
3733 for (uint32_t i = 0; i < bindingCount; i++) {
3734 RADV_FROM_HANDLE(radv_buffer, buffer, pBuffers[i]);
3735 uint32_t idx = firstBinding + i;
3736 VkDeviceSize size = pSizes ? pSizes[i] : 0;
3737 VkDeviceSize stride = pStrides ? pStrides[i] : 0;
3738
3739 /* pSizes and pStrides are optional. */
3740 if (!changed &&
3741 (vb[idx].buffer != buffer ||
3742 vb[idx].offset != pOffsets[i] ||
3743 vb[idx].size != size ||
3744 vb[idx].stride != stride)) {
3745 changed = true;
3746 }
3747
3748 vb[idx].buffer = buffer;
3749 vb[idx].offset = pOffsets[i];
3750 vb[idx].size = size;
3751 vb[idx].stride = stride;
3752
3753 if (buffer) {
3754 radv_cs_add_buffer(cmd_buffer->device->ws,
3755 cmd_buffer->cs, vb[idx].buffer->bo);
3756 }
3757 }
3758
3759 if (!changed) {
3760 /* No state changes. */
3761 return;
3762 }
3763
3764 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
3765 }
3766
3767 static uint32_t
3768 vk_to_index_type(VkIndexType type)
3769 {
3770 switch (type) {
3771 case VK_INDEX_TYPE_UINT8_EXT:
3772 return V_028A7C_VGT_INDEX_8;
3773 case VK_INDEX_TYPE_UINT16:
3774 return V_028A7C_VGT_INDEX_16;
3775 case VK_INDEX_TYPE_UINT32:
3776 return V_028A7C_VGT_INDEX_32;
3777 default:
3778 unreachable("invalid index type");
3779 }
3780 }
3781
3782 static uint32_t
3783 radv_get_vgt_index_size(uint32_t type)
3784 {
3785 switch (type) {
3786 case V_028A7C_VGT_INDEX_8:
3787 return 1;
3788 case V_028A7C_VGT_INDEX_16:
3789 return 2;
3790 case V_028A7C_VGT_INDEX_32:
3791 return 4;
3792 default:
3793 unreachable("invalid index type");
3794 }
3795 }
3796
3797 void radv_CmdBindIndexBuffer(
3798 VkCommandBuffer commandBuffer,
3799 VkBuffer buffer,
3800 VkDeviceSize offset,
3801 VkIndexType indexType)
3802 {
3803 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3804 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
3805
3806 if (cmd_buffer->state.index_buffer == index_buffer &&
3807 cmd_buffer->state.index_offset == offset &&
3808 cmd_buffer->state.index_type == indexType) {
3809 /* No state changes. */
3810 return;
3811 }
3812
3813 cmd_buffer->state.index_buffer = index_buffer;
3814 cmd_buffer->state.index_offset = offset;
3815 cmd_buffer->state.index_type = vk_to_index_type(indexType);
3816 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
3817 cmd_buffer->state.index_va += index_buffer->offset + offset;
3818
3819 int index_size = radv_get_vgt_index_size(vk_to_index_type(indexType));
3820 cmd_buffer->state.max_index_count = (index_buffer->size - offset) / index_size;
3821 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3822 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
3823 }
3824
3825
3826 static void
3827 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3828 VkPipelineBindPoint bind_point,
3829 struct radv_descriptor_set *set, unsigned idx)
3830 {
3831 struct radeon_winsys *ws = cmd_buffer->device->ws;
3832
3833 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
3834
3835 assert(set);
3836 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
3837
3838 if (!cmd_buffer->device->use_global_bo_list) {
3839 for (unsigned j = 0; j < set->buffer_count; ++j)
3840 if (set->descriptors[j])
3841 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
3842 }
3843
3844 if(set->bo)
3845 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
3846 }
3847
3848 void radv_CmdBindDescriptorSets(
3849 VkCommandBuffer commandBuffer,
3850 VkPipelineBindPoint pipelineBindPoint,
3851 VkPipelineLayout _layout,
3852 uint32_t firstSet,
3853 uint32_t descriptorSetCount,
3854 const VkDescriptorSet* pDescriptorSets,
3855 uint32_t dynamicOffsetCount,
3856 const uint32_t* pDynamicOffsets)
3857 {
3858 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3859 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3860 unsigned dyn_idx = 0;
3861
3862 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
3863 struct radv_descriptor_state *descriptors_state =
3864 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3865
3866 for (unsigned i = 0; i < descriptorSetCount; ++i) {
3867 unsigned idx = i + firstSet;
3868 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
3869
3870 /* If the set is already bound we only need to update the
3871 * (potentially changed) dynamic offsets. */
3872 if (descriptors_state->sets[idx] != set ||
3873 !(descriptors_state->valid & (1u << idx))) {
3874 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
3875 }
3876
3877 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
3878 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
3879 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
3880 assert(dyn_idx < dynamicOffsetCount);
3881
3882 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
3883 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
3884 dst[0] = va;
3885 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
3886 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
3887 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3888 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3889 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3890 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3891
3892 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
3893 dst[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3894 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3895 S_008F0C_RESOURCE_LEVEL(1);
3896 } else {
3897 dst[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3898 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3899 }
3900
3901 cmd_buffer->push_constant_stages |=
3902 set->layout->dynamic_shader_stages;
3903 }
3904 }
3905 }
3906
3907 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3908 struct radv_descriptor_set *set,
3909 struct radv_descriptor_set_layout *layout,
3910 VkPipelineBindPoint bind_point)
3911 {
3912 struct radv_descriptor_state *descriptors_state =
3913 radv_get_descriptors_state(cmd_buffer, bind_point);
3914 set->size = layout->size;
3915 set->layout = layout;
3916
3917 if (descriptors_state->push_set.capacity < set->size) {
3918 size_t new_size = MAX2(set->size, 1024);
3919 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
3920 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
3921
3922 free(set->mapped_ptr);
3923 set->mapped_ptr = malloc(new_size);
3924
3925 if (!set->mapped_ptr) {
3926 descriptors_state->push_set.capacity = 0;
3927 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3928 return false;
3929 }
3930
3931 descriptors_state->push_set.capacity = new_size;
3932 }
3933
3934 return true;
3935 }
3936
3937 void radv_meta_push_descriptor_set(
3938 struct radv_cmd_buffer* cmd_buffer,
3939 VkPipelineBindPoint pipelineBindPoint,
3940 VkPipelineLayout _layout,
3941 uint32_t set,
3942 uint32_t descriptorWriteCount,
3943 const VkWriteDescriptorSet* pDescriptorWrites)
3944 {
3945 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3946 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
3947 unsigned bo_offset;
3948
3949 assert(set == 0);
3950 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3951
3952 push_set->size = layout->set[set].layout->size;
3953 push_set->layout = layout->set[set].layout;
3954
3955 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
3956 &bo_offset,
3957 (void**) &push_set->mapped_ptr))
3958 return;
3959
3960 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
3961 push_set->va += bo_offset;
3962
3963 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3964 radv_descriptor_set_to_handle(push_set),
3965 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3966
3967 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3968 }
3969
3970 void radv_CmdPushDescriptorSetKHR(
3971 VkCommandBuffer commandBuffer,
3972 VkPipelineBindPoint pipelineBindPoint,
3973 VkPipelineLayout _layout,
3974 uint32_t set,
3975 uint32_t descriptorWriteCount,
3976 const VkWriteDescriptorSet* pDescriptorWrites)
3977 {
3978 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3979 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3980 struct radv_descriptor_state *descriptors_state =
3981 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3982 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3983
3984 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3985
3986 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3987 layout->set[set].layout,
3988 pipelineBindPoint))
3989 return;
3990
3991 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3992 * because it is invalid, according to Vulkan spec.
3993 */
3994 for (int i = 0; i < descriptorWriteCount; i++) {
3995 ASSERTED const VkWriteDescriptorSet *writeset = &pDescriptorWrites[i];
3996 assert(writeset->descriptorType != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT);
3997 }
3998
3999 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
4000 radv_descriptor_set_to_handle(push_set),
4001 descriptorWriteCount, pDescriptorWrites, 0, NULL);
4002
4003 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
4004 descriptors_state->push_dirty = true;
4005 }
4006
4007 void radv_CmdPushDescriptorSetWithTemplateKHR(
4008 VkCommandBuffer commandBuffer,
4009 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
4010 VkPipelineLayout _layout,
4011 uint32_t set,
4012 const void* pData)
4013 {
4014 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4015 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
4016 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
4017 struct radv_descriptor_state *descriptors_state =
4018 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
4019 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
4020
4021 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
4022
4023 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
4024 layout->set[set].layout,
4025 templ->bind_point))
4026 return;
4027
4028 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
4029 descriptorUpdateTemplate, pData);
4030
4031 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
4032 descriptors_state->push_dirty = true;
4033 }
4034
4035 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
4036 VkPipelineLayout layout,
4037 VkShaderStageFlags stageFlags,
4038 uint32_t offset,
4039 uint32_t size,
4040 const void* pValues)
4041 {
4042 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4043 memcpy(cmd_buffer->push_constants + offset, pValues, size);
4044 cmd_buffer->push_constant_stages |= stageFlags;
4045 }
4046
4047 VkResult radv_EndCommandBuffer(
4048 VkCommandBuffer commandBuffer)
4049 {
4050 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4051
4052 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
4053 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6)
4054 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WB_L2;
4055
4056 /* Make sure to sync all pending active queries at the end of
4057 * command buffer.
4058 */
4059 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
4060
4061 /* Since NGG streamout uses GDS, we need to make GDS idle when
4062 * we leave the IB, otherwise another process might overwrite
4063 * it while our shaders are busy.
4064 */
4065 if (cmd_buffer->gds_needed)
4066 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
4067
4068 si_emit_cache_flush(cmd_buffer);
4069 }
4070
4071 /* Make sure CP DMA is idle at the end of IBs because the kernel
4072 * doesn't wait for it.
4073 */
4074 si_cp_dma_wait_for_idle(cmd_buffer);
4075
4076 radv_describe_end_cmd_buffer(cmd_buffer);
4077
4078 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
4079 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
4080
4081 VkResult result = cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs);
4082 if (result != VK_SUCCESS)
4083 return vk_error(cmd_buffer->device->instance, result);
4084
4085 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
4086
4087 return cmd_buffer->record_result;
4088 }
4089
4090 static void
4091 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
4092 {
4093 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4094
4095 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
4096 return;
4097
4098 assert(!pipeline->ctx_cs.cdw);
4099
4100 cmd_buffer->state.emitted_compute_pipeline = pipeline;
4101
4102 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
4103 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
4104
4105 cmd_buffer->compute_scratch_size_per_wave_needed = MAX2(cmd_buffer->compute_scratch_size_per_wave_needed,
4106 pipeline->scratch_bytes_per_wave);
4107 cmd_buffer->compute_scratch_waves_wanted = MAX2(cmd_buffer->compute_scratch_waves_wanted,
4108 pipeline->max_waves);
4109
4110 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
4111 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
4112
4113 if (unlikely(cmd_buffer->device->trace_bo))
4114 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
4115 }
4116
4117 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
4118 VkPipelineBindPoint bind_point)
4119 {
4120 struct radv_descriptor_state *descriptors_state =
4121 radv_get_descriptors_state(cmd_buffer, bind_point);
4122
4123 descriptors_state->dirty |= descriptors_state->valid;
4124 }
4125
4126 void radv_CmdBindPipeline(
4127 VkCommandBuffer commandBuffer,
4128 VkPipelineBindPoint pipelineBindPoint,
4129 VkPipeline _pipeline)
4130 {
4131 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4132 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
4133
4134 switch (pipelineBindPoint) {
4135 case VK_PIPELINE_BIND_POINT_COMPUTE:
4136 if (cmd_buffer->state.compute_pipeline == pipeline)
4137 return;
4138 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
4139
4140 cmd_buffer->state.compute_pipeline = pipeline;
4141 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
4142 break;
4143 case VK_PIPELINE_BIND_POINT_GRAPHICS:
4144 if (cmd_buffer->state.pipeline == pipeline)
4145 return;
4146 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
4147
4148 cmd_buffer->state.pipeline = pipeline;
4149 if (!pipeline)
4150 break;
4151
4152 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
4153 cmd_buffer->push_constant_stages |= pipeline->active_stages;
4154
4155 /* the new vertex shader might not have the same user regs */
4156 cmd_buffer->state.last_first_instance = -1;
4157 cmd_buffer->state.last_vertex_offset = -1;
4158
4159 /* Prefetch all pipeline shaders at first draw time. */
4160 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
4161
4162 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX10 &&
4163 cmd_buffer->state.emitted_pipeline &&
4164 radv_pipeline_has_ngg(cmd_buffer->state.emitted_pipeline) &&
4165 !radv_pipeline_has_ngg(cmd_buffer->state.pipeline)) {
4166 /* Transitioning from NGG to legacy GS requires
4167 * VGT_FLUSH on Navi10-14. VGT_FLUSH is also emitted
4168 * at the beginning of IBs when legacy GS ring pointers
4169 * are set.
4170 */
4171 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
4172 }
4173
4174 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
4175 radv_bind_streamout_state(cmd_buffer, pipeline);
4176
4177 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
4178 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
4179 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
4180 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
4181
4182 if (radv_pipeline_has_tess(pipeline))
4183 cmd_buffer->tess_rings_needed = true;
4184 break;
4185 default:
4186 assert(!"invalid bind point");
4187 break;
4188 }
4189 }
4190
4191 void radv_CmdSetViewport(
4192 VkCommandBuffer commandBuffer,
4193 uint32_t firstViewport,
4194 uint32_t viewportCount,
4195 const VkViewport* pViewports)
4196 {
4197 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4198 struct radv_cmd_state *state = &cmd_buffer->state;
4199 ASSERTED const uint32_t total_count = firstViewport + viewportCount;
4200
4201 assert(firstViewport < MAX_VIEWPORTS);
4202 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
4203
4204 if (total_count <= state->dynamic.viewport.count &&
4205 !memcmp(state->dynamic.viewport.viewports + firstViewport,
4206 pViewports, viewportCount * sizeof(*pViewports))) {
4207 return;
4208 }
4209
4210 if (state->dynamic.viewport.count < total_count)
4211 state->dynamic.viewport.count = total_count;
4212
4213 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
4214 viewportCount * sizeof(*pViewports));
4215
4216 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
4217 }
4218
4219 void radv_CmdSetScissor(
4220 VkCommandBuffer commandBuffer,
4221 uint32_t firstScissor,
4222 uint32_t scissorCount,
4223 const VkRect2D* pScissors)
4224 {
4225 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4226 struct radv_cmd_state *state = &cmd_buffer->state;
4227 ASSERTED const uint32_t total_count = firstScissor + scissorCount;
4228
4229 assert(firstScissor < MAX_SCISSORS);
4230 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
4231
4232 if (total_count <= state->dynamic.scissor.count &&
4233 !memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
4234 scissorCount * sizeof(*pScissors))) {
4235 return;
4236 }
4237
4238 if (state->dynamic.scissor.count < total_count)
4239 state->dynamic.scissor.count = total_count;
4240
4241 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
4242 scissorCount * sizeof(*pScissors));
4243
4244 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
4245 }
4246
4247 void radv_CmdSetLineWidth(
4248 VkCommandBuffer commandBuffer,
4249 float lineWidth)
4250 {
4251 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4252
4253 if (cmd_buffer->state.dynamic.line_width == lineWidth)
4254 return;
4255
4256 cmd_buffer->state.dynamic.line_width = lineWidth;
4257 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
4258 }
4259
4260 void radv_CmdSetDepthBias(
4261 VkCommandBuffer commandBuffer,
4262 float depthBiasConstantFactor,
4263 float depthBiasClamp,
4264 float depthBiasSlopeFactor)
4265 {
4266 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4267 struct radv_cmd_state *state = &cmd_buffer->state;
4268
4269 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
4270 state->dynamic.depth_bias.clamp == depthBiasClamp &&
4271 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
4272 return;
4273 }
4274
4275 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
4276 state->dynamic.depth_bias.clamp = depthBiasClamp;
4277 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
4278
4279 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
4280 }
4281
4282 void radv_CmdSetBlendConstants(
4283 VkCommandBuffer commandBuffer,
4284 const float blendConstants[4])
4285 {
4286 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4287 struct radv_cmd_state *state = &cmd_buffer->state;
4288
4289 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
4290 return;
4291
4292 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
4293
4294 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
4295 }
4296
4297 void radv_CmdSetDepthBounds(
4298 VkCommandBuffer commandBuffer,
4299 float minDepthBounds,
4300 float maxDepthBounds)
4301 {
4302 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4303 struct radv_cmd_state *state = &cmd_buffer->state;
4304
4305 if (state->dynamic.depth_bounds.min == minDepthBounds &&
4306 state->dynamic.depth_bounds.max == maxDepthBounds) {
4307 return;
4308 }
4309
4310 state->dynamic.depth_bounds.min = minDepthBounds;
4311 state->dynamic.depth_bounds.max = maxDepthBounds;
4312
4313 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
4314 }
4315
4316 void radv_CmdSetStencilCompareMask(
4317 VkCommandBuffer commandBuffer,
4318 VkStencilFaceFlags faceMask,
4319 uint32_t compareMask)
4320 {
4321 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4322 struct radv_cmd_state *state = &cmd_buffer->state;
4323 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
4324 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
4325
4326 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4327 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4328 return;
4329 }
4330
4331 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4332 state->dynamic.stencil_compare_mask.front = compareMask;
4333 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4334 state->dynamic.stencil_compare_mask.back = compareMask;
4335
4336 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
4337 }
4338
4339 void radv_CmdSetStencilWriteMask(
4340 VkCommandBuffer commandBuffer,
4341 VkStencilFaceFlags faceMask,
4342 uint32_t writeMask)
4343 {
4344 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4345 struct radv_cmd_state *state = &cmd_buffer->state;
4346 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
4347 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
4348
4349 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4350 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4351 return;
4352 }
4353
4354 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4355 state->dynamic.stencil_write_mask.front = writeMask;
4356 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4357 state->dynamic.stencil_write_mask.back = writeMask;
4358
4359 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
4360 }
4361
4362 void radv_CmdSetStencilReference(
4363 VkCommandBuffer commandBuffer,
4364 VkStencilFaceFlags faceMask,
4365 uint32_t reference)
4366 {
4367 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4368 struct radv_cmd_state *state = &cmd_buffer->state;
4369 bool front_same = state->dynamic.stencil_reference.front == reference;
4370 bool back_same = state->dynamic.stencil_reference.back == reference;
4371
4372 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4373 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4374 return;
4375 }
4376
4377 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4378 cmd_buffer->state.dynamic.stencil_reference.front = reference;
4379 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4380 cmd_buffer->state.dynamic.stencil_reference.back = reference;
4381
4382 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
4383 }
4384
4385 void radv_CmdSetDiscardRectangleEXT(
4386 VkCommandBuffer commandBuffer,
4387 uint32_t firstDiscardRectangle,
4388 uint32_t discardRectangleCount,
4389 const VkRect2D* pDiscardRectangles)
4390 {
4391 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4392 struct radv_cmd_state *state = &cmd_buffer->state;
4393 ASSERTED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
4394
4395 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
4396 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
4397
4398 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
4399 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
4400 return;
4401 }
4402
4403 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
4404 pDiscardRectangles, discardRectangleCount);
4405
4406 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
4407 }
4408
4409 void radv_CmdSetSampleLocationsEXT(
4410 VkCommandBuffer commandBuffer,
4411 const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
4412 {
4413 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4414 struct radv_cmd_state *state = &cmd_buffer->state;
4415
4416 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
4417
4418 state->dynamic.sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
4419 state->dynamic.sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
4420 state->dynamic.sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
4421 typed_memcpy(&state->dynamic.sample_location.locations[0],
4422 pSampleLocationsInfo->pSampleLocations,
4423 pSampleLocationsInfo->sampleLocationsCount);
4424
4425 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS;
4426 }
4427
4428 void radv_CmdSetLineStippleEXT(
4429 VkCommandBuffer commandBuffer,
4430 uint32_t lineStippleFactor,
4431 uint16_t lineStipplePattern)
4432 {
4433 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4434 struct radv_cmd_state *state = &cmd_buffer->state;
4435
4436 state->dynamic.line_stipple.factor = lineStippleFactor;
4437 state->dynamic.line_stipple.pattern = lineStipplePattern;
4438
4439 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE;
4440 }
4441
4442 void radv_CmdSetCullModeEXT(
4443 VkCommandBuffer commandBuffer,
4444 VkCullModeFlags cullMode)
4445 {
4446 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4447 struct radv_cmd_state *state = &cmd_buffer->state;
4448
4449 if (state->dynamic.cull_mode == cullMode)
4450 return;
4451
4452 state->dynamic.cull_mode = cullMode;
4453
4454 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_CULL_MODE;
4455 }
4456
4457 void radv_CmdSetFrontFaceEXT(
4458 VkCommandBuffer commandBuffer,
4459 VkFrontFace frontFace)
4460 {
4461 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4462 struct radv_cmd_state *state = &cmd_buffer->state;
4463
4464 if (state->dynamic.front_face == frontFace)
4465 return;
4466
4467 state->dynamic.front_face = frontFace;
4468
4469 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE;
4470 }
4471
4472 void radv_CmdSetPrimitiveTopologyEXT(
4473 VkCommandBuffer commandBuffer,
4474 VkPrimitiveTopology primitiveTopology)
4475 {
4476 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4477 struct radv_cmd_state *state = &cmd_buffer->state;
4478 unsigned primitive_topology = si_translate_prim(primitiveTopology);
4479
4480 if (state->dynamic.primitive_topology == primitive_topology)
4481 return;
4482
4483 state->dynamic.primitive_topology = primitive_topology;
4484
4485 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY;
4486 }
4487
4488 void radv_CmdSetViewportWithCountEXT(
4489 VkCommandBuffer commandBuffer,
4490 uint32_t viewportCount,
4491 const VkViewport* pViewports)
4492 {
4493 radv_CmdSetViewport(commandBuffer, 0, viewportCount, pViewports);
4494 }
4495
4496 void radv_CmdSetScissorWithCountEXT(
4497 VkCommandBuffer commandBuffer,
4498 uint32_t scissorCount,
4499 const VkRect2D* pScissors)
4500 {
4501 radv_CmdSetScissor(commandBuffer, 0, scissorCount, pScissors);
4502 }
4503
4504 void radv_CmdSetDepthTestEnableEXT(
4505 VkCommandBuffer commandBuffer,
4506 VkBool32 depthTestEnable)
4507
4508 {
4509 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4510 struct radv_cmd_state *state = &cmd_buffer->state;
4511
4512 if (state->dynamic.depth_test_enable == depthTestEnable)
4513 return;
4514
4515 state->dynamic.depth_test_enable = depthTestEnable;
4516
4517 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE;
4518 }
4519
4520 void radv_CmdSetDepthWriteEnableEXT(
4521 VkCommandBuffer commandBuffer,
4522 VkBool32 depthWriteEnable)
4523 {
4524 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4525 struct radv_cmd_state *state = &cmd_buffer->state;
4526
4527 if (state->dynamic.depth_write_enable == depthWriteEnable)
4528 return;
4529
4530 state->dynamic.depth_write_enable = depthWriteEnable;
4531
4532 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE;
4533 }
4534
4535 void radv_CmdSetDepthCompareOpEXT(
4536 VkCommandBuffer commandBuffer,
4537 VkCompareOp depthCompareOp)
4538 {
4539 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4540 struct radv_cmd_state *state = &cmd_buffer->state;
4541
4542 if (state->dynamic.depth_compare_op == depthCompareOp)
4543 return;
4544
4545 state->dynamic.depth_compare_op = depthCompareOp;
4546
4547 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP;
4548 }
4549
4550 void radv_CmdSetDepthBoundsTestEnableEXT(
4551 VkCommandBuffer commandBuffer,
4552 VkBool32 depthBoundsTestEnable)
4553 {
4554 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4555 struct radv_cmd_state *state = &cmd_buffer->state;
4556
4557 if (state->dynamic.depth_bounds_test_enable == depthBoundsTestEnable)
4558 return;
4559
4560 state->dynamic.depth_bounds_test_enable = depthBoundsTestEnable;
4561
4562 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE;
4563 }
4564
4565 void radv_CmdSetStencilTestEnableEXT(
4566 VkCommandBuffer commandBuffer,
4567 VkBool32 stencilTestEnable)
4568 {
4569 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4570 struct radv_cmd_state *state = &cmd_buffer->state;
4571
4572 if (state->dynamic.stencil_test_enable == stencilTestEnable)
4573 return;
4574
4575 state->dynamic.stencil_test_enable = stencilTestEnable;
4576
4577 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE;
4578 }
4579
4580 void radv_CmdSetStencilOpEXT(
4581 VkCommandBuffer commandBuffer,
4582 VkStencilFaceFlags faceMask,
4583 VkStencilOp failOp,
4584 VkStencilOp passOp,
4585 VkStencilOp depthFailOp,
4586 VkCompareOp compareOp)
4587 {
4588 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4589 struct radv_cmd_state *state = &cmd_buffer->state;
4590 bool front_same =
4591 state->dynamic.stencil_op.front.fail_op == failOp &&
4592 state->dynamic.stencil_op.front.pass_op == passOp &&
4593 state->dynamic.stencil_op.front.depth_fail_op == depthFailOp &&
4594 state->dynamic.stencil_op.front.compare_op == compareOp;
4595 bool back_same =
4596 state->dynamic.stencil_op.back.fail_op == failOp &&
4597 state->dynamic.stencil_op.back.pass_op == passOp &&
4598 state->dynamic.stencil_op.back.depth_fail_op == depthFailOp &&
4599 state->dynamic.stencil_op.back.compare_op == compareOp;
4600
4601 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4602 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same))
4603 return;
4604
4605 if (faceMask & VK_STENCIL_FACE_FRONT_BIT) {
4606 state->dynamic.stencil_op.front.fail_op = failOp;
4607 state->dynamic.stencil_op.front.pass_op = passOp;
4608 state->dynamic.stencil_op.front.depth_fail_op = depthFailOp;
4609 state->dynamic.stencil_op.front.compare_op = compareOp;
4610 }
4611
4612 if (faceMask & VK_STENCIL_FACE_BACK_BIT) {
4613 state->dynamic.stencil_op.back.fail_op = failOp;
4614 state->dynamic.stencil_op.back.pass_op = passOp;
4615 state->dynamic.stencil_op.back.depth_fail_op = depthFailOp;
4616 state->dynamic.stencil_op.back.compare_op = compareOp;
4617 }
4618
4619 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP;
4620 }
4621
4622 void radv_CmdExecuteCommands(
4623 VkCommandBuffer commandBuffer,
4624 uint32_t commandBufferCount,
4625 const VkCommandBuffer* pCmdBuffers)
4626 {
4627 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
4628
4629 assert(commandBufferCount > 0);
4630
4631 /* Emit pending flushes on primary prior to executing secondary */
4632 si_emit_cache_flush(primary);
4633
4634 for (uint32_t i = 0; i < commandBufferCount; i++) {
4635 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
4636
4637 primary->scratch_size_per_wave_needed = MAX2(primary->scratch_size_per_wave_needed,
4638 secondary->scratch_size_per_wave_needed);
4639 primary->scratch_waves_wanted = MAX2(primary->scratch_waves_wanted,
4640 secondary->scratch_waves_wanted);
4641 primary->compute_scratch_size_per_wave_needed = MAX2(primary->compute_scratch_size_per_wave_needed,
4642 secondary->compute_scratch_size_per_wave_needed);
4643 primary->compute_scratch_waves_wanted = MAX2(primary->compute_scratch_waves_wanted,
4644 secondary->compute_scratch_waves_wanted);
4645
4646 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
4647 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
4648 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
4649 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
4650 if (secondary->tess_rings_needed)
4651 primary->tess_rings_needed = true;
4652 if (secondary->sample_positions_needed)
4653 primary->sample_positions_needed = true;
4654 if (secondary->gds_needed)
4655 primary->gds_needed = true;
4656
4657 if (!secondary->state.framebuffer &&
4658 (primary->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)) {
4659 /* Emit the framebuffer state from primary if secondary
4660 * has been recorded without a framebuffer, otherwise
4661 * fast color/depth clears can't work.
4662 */
4663 radv_emit_framebuffer_state(primary);
4664 }
4665
4666 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
4667
4668
4669 /* When the secondary command buffer is compute only we don't
4670 * need to re-emit the current graphics pipeline.
4671 */
4672 if (secondary->state.emitted_pipeline) {
4673 primary->state.emitted_pipeline =
4674 secondary->state.emitted_pipeline;
4675 }
4676
4677 /* When the secondary command buffer is graphics only we don't
4678 * need to re-emit the current compute pipeline.
4679 */
4680 if (secondary->state.emitted_compute_pipeline) {
4681 primary->state.emitted_compute_pipeline =
4682 secondary->state.emitted_compute_pipeline;
4683 }
4684
4685 /* Only re-emit the draw packets when needed. */
4686 if (secondary->state.last_primitive_reset_en != -1) {
4687 primary->state.last_primitive_reset_en =
4688 secondary->state.last_primitive_reset_en;
4689 }
4690
4691 if (secondary->state.last_primitive_reset_index) {
4692 primary->state.last_primitive_reset_index =
4693 secondary->state.last_primitive_reset_index;
4694 }
4695
4696 if (secondary->state.last_ia_multi_vgt_param) {
4697 primary->state.last_ia_multi_vgt_param =
4698 secondary->state.last_ia_multi_vgt_param;
4699 }
4700
4701 primary->state.last_first_instance = secondary->state.last_first_instance;
4702 primary->state.last_num_instances = secondary->state.last_num_instances;
4703 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
4704 primary->state.last_sx_ps_downconvert = secondary->state.last_sx_ps_downconvert;
4705 primary->state.last_sx_blend_opt_epsilon = secondary->state.last_sx_blend_opt_epsilon;
4706 primary->state.last_sx_blend_opt_control = secondary->state.last_sx_blend_opt_control;
4707
4708 if (secondary->state.last_index_type != -1) {
4709 primary->state.last_index_type =
4710 secondary->state.last_index_type;
4711 }
4712 }
4713
4714 /* After executing commands from secondary buffers we have to dirty
4715 * some states.
4716 */
4717 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
4718 RADV_CMD_DIRTY_INDEX_BUFFER |
4719 RADV_CMD_DIRTY_DYNAMIC_ALL;
4720 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
4721 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
4722 }
4723
4724 VkResult radv_CreateCommandPool(
4725 VkDevice _device,
4726 const VkCommandPoolCreateInfo* pCreateInfo,
4727 const VkAllocationCallbacks* pAllocator,
4728 VkCommandPool* pCmdPool)
4729 {
4730 RADV_FROM_HANDLE(radv_device, device, _device);
4731 struct radv_cmd_pool *pool;
4732
4733 pool = vk_alloc2(&device->vk.alloc, pAllocator, sizeof(*pool), 8,
4734 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4735 if (pool == NULL)
4736 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4737
4738 vk_object_base_init(&device->vk, &pool->base,
4739 VK_OBJECT_TYPE_COMMAND_POOL);
4740
4741 if (pAllocator)
4742 pool->alloc = *pAllocator;
4743 else
4744 pool->alloc = device->vk.alloc;
4745
4746 list_inithead(&pool->cmd_buffers);
4747 list_inithead(&pool->free_cmd_buffers);
4748
4749 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
4750
4751 *pCmdPool = radv_cmd_pool_to_handle(pool);
4752
4753 return VK_SUCCESS;
4754
4755 }
4756
4757 void radv_DestroyCommandPool(
4758 VkDevice _device,
4759 VkCommandPool commandPool,
4760 const VkAllocationCallbacks* pAllocator)
4761 {
4762 RADV_FROM_HANDLE(radv_device, device, _device);
4763 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4764
4765 if (!pool)
4766 return;
4767
4768 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4769 &pool->cmd_buffers, pool_link) {
4770 radv_cmd_buffer_destroy(cmd_buffer);
4771 }
4772
4773 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4774 &pool->free_cmd_buffers, pool_link) {
4775 radv_cmd_buffer_destroy(cmd_buffer);
4776 }
4777
4778 vk_object_base_finish(&pool->base);
4779 vk_free2(&device->vk.alloc, pAllocator, pool);
4780 }
4781
4782 VkResult radv_ResetCommandPool(
4783 VkDevice device,
4784 VkCommandPool commandPool,
4785 VkCommandPoolResetFlags flags)
4786 {
4787 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4788 VkResult result;
4789
4790 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
4791 &pool->cmd_buffers, pool_link) {
4792 result = radv_reset_cmd_buffer(cmd_buffer);
4793 if (result != VK_SUCCESS)
4794 return result;
4795 }
4796
4797 return VK_SUCCESS;
4798 }
4799
4800 void radv_TrimCommandPool(
4801 VkDevice device,
4802 VkCommandPool commandPool,
4803 VkCommandPoolTrimFlags flags)
4804 {
4805 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4806
4807 if (!pool)
4808 return;
4809
4810 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4811 &pool->free_cmd_buffers, pool_link) {
4812 radv_cmd_buffer_destroy(cmd_buffer);
4813 }
4814 }
4815
4816 static void
4817 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
4818 uint32_t subpass_id)
4819 {
4820 struct radv_cmd_state *state = &cmd_buffer->state;
4821 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
4822
4823 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
4824 cmd_buffer->cs, 4096);
4825
4826 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
4827
4828 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
4829
4830 radv_describe_barrier_start(cmd_buffer, RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC);
4831
4832 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4833 const uint32_t a = subpass->attachments[i].attachment;
4834 if (a == VK_ATTACHMENT_UNUSED)
4835 continue;
4836
4837 radv_handle_subpass_image_transition(cmd_buffer,
4838 subpass->attachments[i],
4839 true);
4840 }
4841
4842 radv_describe_barrier_end(cmd_buffer);
4843
4844 radv_cmd_buffer_clear_subpass(cmd_buffer);
4845
4846 assert(cmd_buffer->cs->cdw <= cdw_max);
4847 }
4848
4849 static void
4850 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
4851 {
4852 struct radv_cmd_state *state = &cmd_buffer->state;
4853 const struct radv_subpass *subpass = state->subpass;
4854 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
4855
4856 radv_cmd_buffer_resolve_subpass(cmd_buffer);
4857
4858 radv_describe_barrier_start(cmd_buffer, RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC);
4859
4860 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4861 const uint32_t a = subpass->attachments[i].attachment;
4862 if (a == VK_ATTACHMENT_UNUSED)
4863 continue;
4864
4865 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
4866 continue;
4867
4868 VkImageLayout layout = state->pass->attachments[a].final_layout;
4869 VkImageLayout stencil_layout = state->pass->attachments[a].stencil_final_layout;
4870 struct radv_subpass_attachment att = { a, layout, stencil_layout };
4871 radv_handle_subpass_image_transition(cmd_buffer, att, false);
4872 }
4873
4874 radv_describe_barrier_end(cmd_buffer);
4875 }
4876
4877 void
4878 radv_cmd_buffer_begin_render_pass(struct radv_cmd_buffer *cmd_buffer,
4879 const VkRenderPassBeginInfo *pRenderPassBegin)
4880 {
4881 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
4882 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
4883 VkResult result;
4884
4885 cmd_buffer->state.framebuffer = framebuffer;
4886 cmd_buffer->state.pass = pass;
4887 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
4888
4889 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
4890 if (result != VK_SUCCESS)
4891 return;
4892
4893 result = radv_cmd_state_setup_sample_locations(cmd_buffer, pass, pRenderPassBegin);
4894 if (result != VK_SUCCESS)
4895 return;
4896 }
4897
4898 void radv_CmdBeginRenderPass(
4899 VkCommandBuffer commandBuffer,
4900 const VkRenderPassBeginInfo* pRenderPassBegin,
4901 VkSubpassContents contents)
4902 {
4903 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4904
4905 radv_cmd_buffer_begin_render_pass(cmd_buffer, pRenderPassBegin);
4906
4907 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
4908 }
4909
4910 void radv_CmdBeginRenderPass2(
4911 VkCommandBuffer commandBuffer,
4912 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
4913 const VkSubpassBeginInfo* pSubpassBeginInfo)
4914 {
4915 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
4916 pSubpassBeginInfo->contents);
4917 }
4918
4919 void radv_CmdNextSubpass(
4920 VkCommandBuffer commandBuffer,
4921 VkSubpassContents contents)
4922 {
4923 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4924
4925 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
4926 radv_cmd_buffer_end_subpass(cmd_buffer);
4927 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
4928 }
4929
4930 void radv_CmdNextSubpass2(
4931 VkCommandBuffer commandBuffer,
4932 const VkSubpassBeginInfo* pSubpassBeginInfo,
4933 const VkSubpassEndInfo* pSubpassEndInfo)
4934 {
4935 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
4936 }
4937
4938 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
4939 {
4940 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
4941 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
4942 if (!radv_get_shader(pipeline, stage))
4943 continue;
4944
4945 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
4946 if (loc->sgpr_idx == -1)
4947 continue;
4948 uint32_t base_reg = pipeline->user_data_0[stage];
4949 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4950
4951 }
4952 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
4953 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
4954 if (loc->sgpr_idx != -1) {
4955 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
4956 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4957 }
4958 }
4959 }
4960
4961 static void
4962 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4963 uint32_t vertex_count,
4964 bool use_opaque)
4965 {
4966 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
4967 radeon_emit(cmd_buffer->cs, vertex_count);
4968 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
4969 S_0287F0_USE_OPAQUE(use_opaque));
4970 }
4971
4972 static void
4973 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
4974 uint64_t index_va,
4975 uint32_t index_count)
4976 {
4977 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
4978 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
4979 radeon_emit(cmd_buffer->cs, index_va);
4980 radeon_emit(cmd_buffer->cs, index_va >> 32);
4981 radeon_emit(cmd_buffer->cs, index_count);
4982 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
4983 }
4984
4985 static void
4986 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4987 bool indexed,
4988 uint32_t draw_count,
4989 uint64_t count_va,
4990 uint32_t stride)
4991 {
4992 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4993 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
4994 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
4995 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id;
4996 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
4997 bool predicating = cmd_buffer->state.predicating;
4998 assert(base_reg);
4999
5000 /* just reset draw state for vertex data */
5001 cmd_buffer->state.last_first_instance = -1;
5002 cmd_buffer->state.last_num_instances = -1;
5003 cmd_buffer->state.last_vertex_offset = -1;
5004
5005 if (draw_count == 1 && !count_va && !draw_id_enable) {
5006 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
5007 PKT3_DRAW_INDIRECT, 3, predicating));
5008 radeon_emit(cs, 0);
5009 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
5010 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
5011 radeon_emit(cs, di_src_sel);
5012 } else {
5013 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
5014 PKT3_DRAW_INDIRECT_MULTI,
5015 8, predicating));
5016 radeon_emit(cs, 0);
5017 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
5018 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
5019 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
5020 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
5021 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
5022 radeon_emit(cs, draw_count); /* count */
5023 radeon_emit(cs, count_va); /* count_addr */
5024 radeon_emit(cs, count_va >> 32);
5025 radeon_emit(cs, stride); /* stride */
5026 radeon_emit(cs, di_src_sel);
5027 }
5028 }
5029
5030 static void
5031 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
5032 const struct radv_draw_info *info)
5033 {
5034 struct radv_cmd_state *state = &cmd_buffer->state;
5035 struct radeon_winsys *ws = cmd_buffer->device->ws;
5036 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5037
5038 if (info->indirect) {
5039 uint64_t va = radv_buffer_get_va(info->indirect->bo);
5040 uint64_t count_va = 0;
5041
5042 va += info->indirect->offset + info->indirect_offset;
5043
5044 radv_cs_add_buffer(ws, cs, info->indirect->bo);
5045
5046 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
5047 radeon_emit(cs, 1);
5048 radeon_emit(cs, va);
5049 radeon_emit(cs, va >> 32);
5050
5051 if (info->count_buffer) {
5052 count_va = radv_buffer_get_va(info->count_buffer->bo);
5053 count_va += info->count_buffer->offset +
5054 info->count_buffer_offset;
5055
5056 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
5057 }
5058
5059 if (!state->subpass->view_mask) {
5060 radv_cs_emit_indirect_draw_packet(cmd_buffer,
5061 info->indexed,
5062 info->count,
5063 count_va,
5064 info->stride);
5065 } else {
5066 unsigned i;
5067 for_each_bit(i, state->subpass->view_mask) {
5068 radv_emit_view_index(cmd_buffer, i);
5069
5070 radv_cs_emit_indirect_draw_packet(cmd_buffer,
5071 info->indexed,
5072 info->count,
5073 count_va,
5074 info->stride);
5075 }
5076 }
5077 } else {
5078 assert(state->pipeline->graphics.vtx_base_sgpr);
5079
5080 if (info->vertex_offset != state->last_vertex_offset ||
5081 info->first_instance != state->last_first_instance) {
5082 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
5083 state->pipeline->graphics.vtx_emit_num);
5084
5085 radeon_emit(cs, info->vertex_offset);
5086 radeon_emit(cs, info->first_instance);
5087 if (state->pipeline->graphics.vtx_emit_num == 3)
5088 radeon_emit(cs, 0);
5089 state->last_first_instance = info->first_instance;
5090 state->last_vertex_offset = info->vertex_offset;
5091 }
5092
5093 if (state->last_num_instances != info->instance_count) {
5094 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
5095 radeon_emit(cs, info->instance_count);
5096 state->last_num_instances = info->instance_count;
5097 }
5098
5099 if (info->indexed) {
5100 int index_size = radv_get_vgt_index_size(state->index_type);
5101 uint64_t index_va;
5102
5103 /* Skip draw calls with 0-sized index buffers. They
5104 * cause a hang on some chips, like Navi10-14.
5105 */
5106 if (!cmd_buffer->state.max_index_count)
5107 return;
5108
5109 index_va = state->index_va;
5110 index_va += info->first_index * index_size;
5111
5112 if (!state->subpass->view_mask) {
5113 radv_cs_emit_draw_indexed_packet(cmd_buffer,
5114 index_va,
5115 info->count);
5116 } else {
5117 unsigned i;
5118 for_each_bit(i, state->subpass->view_mask) {
5119 radv_emit_view_index(cmd_buffer, i);
5120
5121 radv_cs_emit_draw_indexed_packet(cmd_buffer,
5122 index_va,
5123 info->count);
5124 }
5125 }
5126 } else {
5127 if (!state->subpass->view_mask) {
5128 radv_cs_emit_draw_packet(cmd_buffer,
5129 info->count,
5130 !!info->strmout_buffer);
5131 } else {
5132 unsigned i;
5133 for_each_bit(i, state->subpass->view_mask) {
5134 radv_emit_view_index(cmd_buffer, i);
5135
5136 radv_cs_emit_draw_packet(cmd_buffer,
5137 info->count,
5138 !!info->strmout_buffer);
5139 }
5140 }
5141 }
5142 }
5143 }
5144
5145 /*
5146 * Vega and raven have a bug which triggers if there are multiple context
5147 * register contexts active at the same time with different scissor values.
5148 *
5149 * There are two possible workarounds:
5150 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
5151 * there is only ever 1 active set of scissor values at the same time.
5152 *
5153 * 2) Whenever the hardware switches contexts we have to set the scissor
5154 * registers again even if it is a noop. That way the new context gets
5155 * the correct scissor values.
5156 *
5157 * This implements option 2. radv_need_late_scissor_emission needs to
5158 * return true on affected HW if radv_emit_all_graphics_states sets
5159 * any context registers.
5160 */
5161 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
5162 const struct radv_draw_info *info)
5163 {
5164 struct radv_cmd_state *state = &cmd_buffer->state;
5165
5166 if (!cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
5167 return false;
5168
5169 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
5170 return true;
5171
5172 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
5173
5174 /* Index, vertex and streamout buffers don't change context regs, and
5175 * pipeline is already handled.
5176 */
5177 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
5178 RADV_CMD_DIRTY_VERTEX_BUFFER |
5179 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
5180 RADV_CMD_DIRTY_PIPELINE);
5181
5182 if (cmd_buffer->state.dirty & used_states)
5183 return true;
5184
5185 uint32_t primitive_reset_index =
5186 radv_get_primitive_reset_index(cmd_buffer);
5187
5188 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
5189 primitive_reset_index != state->last_primitive_reset_index)
5190 return true;
5191
5192 return false;
5193 }
5194
5195 static void
5196 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
5197 const struct radv_draw_info *info)
5198 {
5199 bool late_scissor_emission;
5200
5201 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
5202 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
5203 radv_emit_rbplus_state(cmd_buffer);
5204
5205 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
5206 radv_emit_graphics_pipeline(cmd_buffer);
5207
5208 /* This should be before the cmd_buffer->state.dirty is cleared
5209 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
5210 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
5211 late_scissor_emission =
5212 radv_need_late_scissor_emission(cmd_buffer, info);
5213
5214 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
5215 radv_emit_framebuffer_state(cmd_buffer);
5216
5217 if (info->indexed) {
5218 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
5219 radv_emit_index_buffer(cmd_buffer, info->indirect);
5220 } else {
5221 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
5222 * so the state must be re-emitted before the next indexed
5223 * draw.
5224 */
5225 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
5226 cmd_buffer->state.last_index_type = -1;
5227 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
5228 }
5229 }
5230
5231 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
5232
5233 radv_emit_draw_registers(cmd_buffer, info);
5234
5235 if (late_scissor_emission)
5236 radv_emit_scissor(cmd_buffer);
5237 }
5238
5239 static void
5240 radv_draw(struct radv_cmd_buffer *cmd_buffer,
5241 const struct radv_draw_info *info)
5242 {
5243 struct radeon_info *rad_info =
5244 &cmd_buffer->device->physical_device->rad_info;
5245 bool has_prefetch =
5246 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
5247 bool pipeline_is_dirty =
5248 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
5249 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
5250
5251 ASSERTED unsigned cdw_max =
5252 radeon_check_space(cmd_buffer->device->ws,
5253 cmd_buffer->cs, 4096);
5254
5255 if (likely(!info->indirect)) {
5256 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
5257 * no workaround for indirect draws, but we can at least skip
5258 * direct draws.
5259 */
5260 if (unlikely(!info->instance_count))
5261 return;
5262
5263 /* Handle count == 0. */
5264 if (unlikely(!info->count && !info->strmout_buffer))
5265 return;
5266 }
5267
5268 radv_describe_draw(cmd_buffer);
5269
5270 /* Use optimal packet order based on whether we need to sync the
5271 * pipeline.
5272 */
5273 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5274 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5275 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
5276 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
5277 /* If we have to wait for idle, set all states first, so that
5278 * all SET packets are processed in parallel with previous draw
5279 * calls. Then upload descriptors, set shader pointers, and
5280 * draw, and prefetch at the end. This ensures that the time
5281 * the CUs are idle is very short. (there are only SET_SH
5282 * packets between the wait and the draw)
5283 */
5284 radv_emit_all_graphics_states(cmd_buffer, info);
5285 si_emit_cache_flush(cmd_buffer);
5286 /* <-- CUs are idle here --> */
5287
5288 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
5289
5290 radv_emit_draw_packets(cmd_buffer, info);
5291 /* <-- CUs are busy here --> */
5292
5293 /* Start prefetches after the draw has been started. Both will
5294 * run in parallel, but starting the draw first is more
5295 * important.
5296 */
5297 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
5298 radv_emit_prefetch_L2(cmd_buffer,
5299 cmd_buffer->state.pipeline, false);
5300 }
5301 } else {
5302 /* If we don't wait for idle, start prefetches first, then set
5303 * states, and draw at the end.
5304 */
5305 si_emit_cache_flush(cmd_buffer);
5306
5307 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
5308 /* Only prefetch the vertex shader and VBO descriptors
5309 * in order to start the draw as soon as possible.
5310 */
5311 radv_emit_prefetch_L2(cmd_buffer,
5312 cmd_buffer->state.pipeline, true);
5313 }
5314
5315 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
5316
5317 radv_emit_all_graphics_states(cmd_buffer, info);
5318 radv_emit_draw_packets(cmd_buffer, info);
5319
5320 /* Prefetch the remaining shaders after the draw has been
5321 * started.
5322 */
5323 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
5324 radv_emit_prefetch_L2(cmd_buffer,
5325 cmd_buffer->state.pipeline, false);
5326 }
5327 }
5328
5329 /* Workaround for a VGT hang when streamout is enabled.
5330 * It must be done after drawing.
5331 */
5332 if (cmd_buffer->state.streamout.streamout_enabled &&
5333 (rad_info->family == CHIP_HAWAII ||
5334 rad_info->family == CHIP_TONGA ||
5335 rad_info->family == CHIP_FIJI)) {
5336 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
5337 }
5338
5339 assert(cmd_buffer->cs->cdw <= cdw_max);
5340 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
5341 }
5342
5343 void radv_CmdDraw(
5344 VkCommandBuffer commandBuffer,
5345 uint32_t vertexCount,
5346 uint32_t instanceCount,
5347 uint32_t firstVertex,
5348 uint32_t firstInstance)
5349 {
5350 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5351 struct radv_draw_info info = {};
5352
5353 info.count = vertexCount;
5354 info.instance_count = instanceCount;
5355 info.first_instance = firstInstance;
5356 info.vertex_offset = firstVertex;
5357
5358 radv_draw(cmd_buffer, &info);
5359 }
5360
5361 void radv_CmdDrawIndexed(
5362 VkCommandBuffer commandBuffer,
5363 uint32_t indexCount,
5364 uint32_t instanceCount,
5365 uint32_t firstIndex,
5366 int32_t vertexOffset,
5367 uint32_t firstInstance)
5368 {
5369 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5370 struct radv_draw_info info = {};
5371
5372 info.indexed = true;
5373 info.count = indexCount;
5374 info.instance_count = instanceCount;
5375 info.first_index = firstIndex;
5376 info.vertex_offset = vertexOffset;
5377 info.first_instance = firstInstance;
5378
5379 radv_draw(cmd_buffer, &info);
5380 }
5381
5382 void radv_CmdDrawIndirect(
5383 VkCommandBuffer commandBuffer,
5384 VkBuffer _buffer,
5385 VkDeviceSize offset,
5386 uint32_t drawCount,
5387 uint32_t stride)
5388 {
5389 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5390 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5391 struct radv_draw_info info = {};
5392
5393 info.count = drawCount;
5394 info.indirect = buffer;
5395 info.indirect_offset = offset;
5396 info.stride = stride;
5397
5398 radv_draw(cmd_buffer, &info);
5399 }
5400
5401 void radv_CmdDrawIndexedIndirect(
5402 VkCommandBuffer commandBuffer,
5403 VkBuffer _buffer,
5404 VkDeviceSize offset,
5405 uint32_t drawCount,
5406 uint32_t stride)
5407 {
5408 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5409 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5410 struct radv_draw_info info = {};
5411
5412 info.indexed = true;
5413 info.count = drawCount;
5414 info.indirect = buffer;
5415 info.indirect_offset = offset;
5416 info.stride = stride;
5417
5418 radv_draw(cmd_buffer, &info);
5419 }
5420
5421 void radv_CmdDrawIndirectCount(
5422 VkCommandBuffer commandBuffer,
5423 VkBuffer _buffer,
5424 VkDeviceSize offset,
5425 VkBuffer _countBuffer,
5426 VkDeviceSize countBufferOffset,
5427 uint32_t maxDrawCount,
5428 uint32_t stride)
5429 {
5430 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5431 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5432 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
5433 struct radv_draw_info info = {};
5434
5435 info.count = maxDrawCount;
5436 info.indirect = buffer;
5437 info.indirect_offset = offset;
5438 info.count_buffer = count_buffer;
5439 info.count_buffer_offset = countBufferOffset;
5440 info.stride = stride;
5441
5442 radv_draw(cmd_buffer, &info);
5443 }
5444
5445 void radv_CmdDrawIndexedIndirectCount(
5446 VkCommandBuffer commandBuffer,
5447 VkBuffer _buffer,
5448 VkDeviceSize offset,
5449 VkBuffer _countBuffer,
5450 VkDeviceSize countBufferOffset,
5451 uint32_t maxDrawCount,
5452 uint32_t stride)
5453 {
5454 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5455 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5456 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
5457 struct radv_draw_info info = {};
5458
5459 info.indexed = true;
5460 info.count = maxDrawCount;
5461 info.indirect = buffer;
5462 info.indirect_offset = offset;
5463 info.count_buffer = count_buffer;
5464 info.count_buffer_offset = countBufferOffset;
5465 info.stride = stride;
5466
5467 radv_draw(cmd_buffer, &info);
5468 }
5469
5470 struct radv_dispatch_info {
5471 /**
5472 * Determine the layout of the grid (in block units) to be used.
5473 */
5474 uint32_t blocks[3];
5475
5476 /**
5477 * A starting offset for the grid. If unaligned is set, the offset
5478 * must still be aligned.
5479 */
5480 uint32_t offsets[3];
5481 /**
5482 * Whether it's an unaligned compute dispatch.
5483 */
5484 bool unaligned;
5485
5486 /**
5487 * Indirect compute parameters resource.
5488 */
5489 struct radv_buffer *indirect;
5490 uint64_t indirect_offset;
5491 };
5492
5493 static void
5494 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
5495 const struct radv_dispatch_info *info)
5496 {
5497 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
5498 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
5499 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
5500 struct radeon_winsys *ws = cmd_buffer->device->ws;
5501 bool predicating = cmd_buffer->state.predicating;
5502 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5503 struct radv_userdata_info *loc;
5504
5505 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
5506 AC_UD_CS_GRID_SIZE);
5507
5508 ASSERTED unsigned cdw_max = radeon_check_space(ws, cs, 25);
5509
5510 if (compute_shader->info.wave_size == 32) {
5511 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
5512 dispatch_initiator |= S_00B800_CS_W32_EN(1);
5513 }
5514
5515 if (info->indirect) {
5516 uint64_t va = radv_buffer_get_va(info->indirect->bo);
5517
5518 va += info->indirect->offset + info->indirect_offset;
5519
5520 radv_cs_add_buffer(ws, cs, info->indirect->bo);
5521
5522 if (loc->sgpr_idx != -1) {
5523 for (unsigned i = 0; i < 3; ++i) {
5524 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5525 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5526 COPY_DATA_DST_SEL(COPY_DATA_REG));
5527 radeon_emit(cs, (va + 4 * i));
5528 radeon_emit(cs, (va + 4 * i) >> 32);
5529 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
5530 + loc->sgpr_idx * 4) >> 2) + i);
5531 radeon_emit(cs, 0);
5532 }
5533 }
5534
5535 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
5536 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
5537 PKT3_SHADER_TYPE_S(1));
5538 radeon_emit(cs, va);
5539 radeon_emit(cs, va >> 32);
5540 radeon_emit(cs, dispatch_initiator);
5541 } else {
5542 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
5543 PKT3_SHADER_TYPE_S(1));
5544 radeon_emit(cs, 1);
5545 radeon_emit(cs, va);
5546 radeon_emit(cs, va >> 32);
5547
5548 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
5549 PKT3_SHADER_TYPE_S(1));
5550 radeon_emit(cs, 0);
5551 radeon_emit(cs, dispatch_initiator);
5552 }
5553 } else {
5554 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
5555 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
5556
5557 if (info->unaligned) {
5558 unsigned *cs_block_size = compute_shader->info.cs.block_size;
5559 unsigned remainder[3];
5560
5561 /* If aligned, these should be an entire block size,
5562 * not 0.
5563 */
5564 remainder[0] = blocks[0] + cs_block_size[0] -
5565 align_u32_npot(blocks[0], cs_block_size[0]);
5566 remainder[1] = blocks[1] + cs_block_size[1] -
5567 align_u32_npot(blocks[1], cs_block_size[1]);
5568 remainder[2] = blocks[2] + cs_block_size[2] -
5569 align_u32_npot(blocks[2], cs_block_size[2]);
5570
5571 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
5572 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
5573 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
5574
5575 for(unsigned i = 0; i < 3; ++i) {
5576 assert(offsets[i] % cs_block_size[i] == 0);
5577 offsets[i] /= cs_block_size[i];
5578 }
5579
5580 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
5581 radeon_emit(cs,
5582 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
5583 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
5584 radeon_emit(cs,
5585 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
5586 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
5587 radeon_emit(cs,
5588 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
5589 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
5590
5591 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
5592 }
5593
5594 if (loc->sgpr_idx != -1) {
5595 assert(loc->num_sgprs == 3);
5596
5597 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
5598 loc->sgpr_idx * 4, 3);
5599 radeon_emit(cs, blocks[0]);
5600 radeon_emit(cs, blocks[1]);
5601 radeon_emit(cs, blocks[2]);
5602 }
5603
5604 if (offsets[0] || offsets[1] || offsets[2]) {
5605 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
5606 radeon_emit(cs, offsets[0]);
5607 radeon_emit(cs, offsets[1]);
5608 radeon_emit(cs, offsets[2]);
5609
5610 /* The blocks in the packet are not counts but end values. */
5611 for (unsigned i = 0; i < 3; ++i)
5612 blocks[i] += offsets[i];
5613 } else {
5614 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
5615 }
5616
5617 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
5618 PKT3_SHADER_TYPE_S(1));
5619 radeon_emit(cs, blocks[0]);
5620 radeon_emit(cs, blocks[1]);
5621 radeon_emit(cs, blocks[2]);
5622 radeon_emit(cs, dispatch_initiator);
5623 }
5624
5625 assert(cmd_buffer->cs->cdw <= cdw_max);
5626 }
5627
5628 static void
5629 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
5630 {
5631 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
5632 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
5633 }
5634
5635 static void
5636 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
5637 const struct radv_dispatch_info *info)
5638 {
5639 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
5640 bool has_prefetch =
5641 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
5642 bool pipeline_is_dirty = pipeline &&
5643 pipeline != cmd_buffer->state.emitted_compute_pipeline;
5644
5645 radv_describe_dispatch(cmd_buffer, 8, 8, 8);
5646
5647 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5648 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5649 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
5650 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
5651 /* If we have to wait for idle, set all states first, so that
5652 * all SET packets are processed in parallel with previous draw
5653 * calls. Then upload descriptors, set shader pointers, and
5654 * dispatch, and prefetch at the end. This ensures that the
5655 * time the CUs are idle is very short. (there are only SET_SH
5656 * packets between the wait and the draw)
5657 */
5658 radv_emit_compute_pipeline(cmd_buffer);
5659 si_emit_cache_flush(cmd_buffer);
5660 /* <-- CUs are idle here --> */
5661
5662 radv_upload_compute_shader_descriptors(cmd_buffer);
5663
5664 radv_emit_dispatch_packets(cmd_buffer, info);
5665 /* <-- CUs are busy here --> */
5666
5667 /* Start prefetches after the dispatch has been started. Both
5668 * will run in parallel, but starting the dispatch first is
5669 * more important.
5670 */
5671 if (has_prefetch && pipeline_is_dirty) {
5672 radv_emit_shader_prefetch(cmd_buffer,
5673 pipeline->shaders[MESA_SHADER_COMPUTE]);
5674 }
5675 } else {
5676 /* If we don't wait for idle, start prefetches first, then set
5677 * states, and dispatch at the end.
5678 */
5679 si_emit_cache_flush(cmd_buffer);
5680
5681 if (has_prefetch && pipeline_is_dirty) {
5682 radv_emit_shader_prefetch(cmd_buffer,
5683 pipeline->shaders[MESA_SHADER_COMPUTE]);
5684 }
5685
5686 radv_upload_compute_shader_descriptors(cmd_buffer);
5687
5688 radv_emit_compute_pipeline(cmd_buffer);
5689 radv_emit_dispatch_packets(cmd_buffer, info);
5690 }
5691
5692 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
5693 }
5694
5695 void radv_CmdDispatchBase(
5696 VkCommandBuffer commandBuffer,
5697 uint32_t base_x,
5698 uint32_t base_y,
5699 uint32_t base_z,
5700 uint32_t x,
5701 uint32_t y,
5702 uint32_t z)
5703 {
5704 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5705 struct radv_dispatch_info info = {};
5706
5707 info.blocks[0] = x;
5708 info.blocks[1] = y;
5709 info.blocks[2] = z;
5710
5711 info.offsets[0] = base_x;
5712 info.offsets[1] = base_y;
5713 info.offsets[2] = base_z;
5714 radv_dispatch(cmd_buffer, &info);
5715 }
5716
5717 void radv_CmdDispatch(
5718 VkCommandBuffer commandBuffer,
5719 uint32_t x,
5720 uint32_t y,
5721 uint32_t z)
5722 {
5723 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
5724 }
5725
5726 void radv_CmdDispatchIndirect(
5727 VkCommandBuffer commandBuffer,
5728 VkBuffer _buffer,
5729 VkDeviceSize offset)
5730 {
5731 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5732 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5733 struct radv_dispatch_info info = {};
5734
5735 info.indirect = buffer;
5736 info.indirect_offset = offset;
5737
5738 radv_dispatch(cmd_buffer, &info);
5739 }
5740
5741 void radv_unaligned_dispatch(
5742 struct radv_cmd_buffer *cmd_buffer,
5743 uint32_t x,
5744 uint32_t y,
5745 uint32_t z)
5746 {
5747 struct radv_dispatch_info info = {};
5748
5749 info.blocks[0] = x;
5750 info.blocks[1] = y;
5751 info.blocks[2] = z;
5752 info.unaligned = 1;
5753
5754 radv_dispatch(cmd_buffer, &info);
5755 }
5756
5757 void
5758 radv_cmd_buffer_end_render_pass(struct radv_cmd_buffer *cmd_buffer)
5759 {
5760 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
5761 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
5762
5763 cmd_buffer->state.pass = NULL;
5764 cmd_buffer->state.subpass = NULL;
5765 cmd_buffer->state.attachments = NULL;
5766 cmd_buffer->state.framebuffer = NULL;
5767 cmd_buffer->state.subpass_sample_locs = NULL;
5768 }
5769
5770 void radv_CmdEndRenderPass(
5771 VkCommandBuffer commandBuffer)
5772 {
5773 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5774
5775 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
5776
5777 radv_cmd_buffer_end_subpass(cmd_buffer);
5778
5779 radv_cmd_buffer_end_render_pass(cmd_buffer);
5780 }
5781
5782 void radv_CmdEndRenderPass2(
5783 VkCommandBuffer commandBuffer,
5784 const VkSubpassEndInfo* pSubpassEndInfo)
5785 {
5786 radv_CmdEndRenderPass(commandBuffer);
5787 }
5788
5789 /*
5790 * For HTILE we have the following interesting clear words:
5791 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
5792 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
5793 * 0xfffffff0: Clear depth to 1.0
5794 * 0x00000000: Clear depth to 0.0
5795 */
5796 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
5797 struct radv_image *image,
5798 const VkImageSubresourceRange *range)
5799 {
5800 assert(range->baseMipLevel == 0);
5801 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
5802 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
5803 struct radv_cmd_state *state = &cmd_buffer->state;
5804 uint32_t htile_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
5805 VkClearDepthStencilValue value = {};
5806 struct radv_barrier_data barrier = {};
5807
5808 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5809 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5810
5811 barrier.layout_transitions.init_mask_ram = 1;
5812 radv_describe_layout_transition(cmd_buffer, &barrier);
5813
5814 state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, htile_value);
5815
5816 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5817
5818 if (vk_format_is_stencil(image->vk_format))
5819 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
5820
5821 radv_set_ds_clear_metadata(cmd_buffer, image, range, value, aspects);
5822
5823 if (radv_image_is_tc_compat_htile(image)) {
5824 /* Initialize the TC-compat metada value to 0 because by
5825 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
5826 * need have to conditionally update its value when performing
5827 * a fast depth clear.
5828 */
5829 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, range, 0);
5830 }
5831 }
5832
5833 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
5834 struct radv_image *image,
5835 VkImageLayout src_layout,
5836 bool src_render_loop,
5837 VkImageLayout dst_layout,
5838 bool dst_render_loop,
5839 unsigned src_queue_mask,
5840 unsigned dst_queue_mask,
5841 const VkImageSubresourceRange *range,
5842 struct radv_sample_locations_state *sample_locs)
5843 {
5844 if (!radv_image_has_htile(image))
5845 return;
5846
5847 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5848 radv_initialize_htile(cmd_buffer, image, range);
5849 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5850 radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5851 radv_initialize_htile(cmd_buffer, image, range);
5852 } else if (radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5853 !radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5854 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5855 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5856
5857 radv_decompress_depth_stencil(cmd_buffer, image, range,
5858 sample_locs);
5859
5860 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5861 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5862 }
5863 }
5864
5865 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
5866 struct radv_image *image,
5867 const VkImageSubresourceRange *range,
5868 uint32_t value)
5869 {
5870 struct radv_cmd_state *state = &cmd_buffer->state;
5871 struct radv_barrier_data barrier = {};
5872
5873 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5874 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5875
5876 barrier.layout_transitions.init_mask_ram = 1;
5877 radv_describe_layout_transition(cmd_buffer, &barrier);
5878
5879 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, range, value);
5880
5881 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5882 }
5883
5884 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
5885 struct radv_image *image,
5886 const VkImageSubresourceRange *range)
5887 {
5888 struct radv_cmd_state *state = &cmd_buffer->state;
5889 static const uint32_t fmask_clear_values[4] = {
5890 0x00000000,
5891 0x02020202,
5892 0xE4E4E4E4,
5893 0x76543210
5894 };
5895 uint32_t log2_samples = util_logbase2(image->info.samples);
5896 uint32_t value = fmask_clear_values[log2_samples];
5897 struct radv_barrier_data barrier = {};
5898
5899 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5900 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5901
5902 barrier.layout_transitions.init_mask_ram = 1;
5903 radv_describe_layout_transition(cmd_buffer, &barrier);
5904
5905 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, range, value);
5906
5907 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5908 }
5909
5910 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
5911 struct radv_image *image,
5912 const VkImageSubresourceRange *range, uint32_t value)
5913 {
5914 struct radv_cmd_state *state = &cmd_buffer->state;
5915 struct radv_barrier_data barrier = {};
5916 unsigned size = 0;
5917
5918 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5919 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5920
5921 barrier.layout_transitions.init_mask_ram = 1;
5922 radv_describe_layout_transition(cmd_buffer, &barrier);
5923
5924 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
5925
5926 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) {
5927 /* When DCC is enabled with mipmaps, some levels might not
5928 * support fast clears and we have to initialize them as "fully
5929 * expanded".
5930 */
5931 /* Compute the size of all fast clearable DCC levels. */
5932 for (unsigned i = 0; i < image->planes[0].surface.num_dcc_levels; i++) {
5933 struct legacy_surf_level *surf_level =
5934 &image->planes[0].surface.u.legacy.level[i];
5935 unsigned dcc_fast_clear_size =
5936 surf_level->dcc_slice_fast_clear_size * image->info.array_size;
5937
5938 if (!dcc_fast_clear_size)
5939 break;
5940
5941 size = surf_level->dcc_offset + dcc_fast_clear_size;
5942 }
5943
5944 /* Initialize the mipmap levels without DCC. */
5945 if (size != image->planes[0].surface.dcc_size) {
5946 state->flush_bits |=
5947 radv_fill_buffer(cmd_buffer, image->bo,
5948 image->offset + image->planes[0].surface.dcc_offset + size,
5949 image->planes[0].surface.dcc_size - size,
5950 0xffffffff);
5951 }
5952 }
5953
5954 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5955 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5956 }
5957
5958 /**
5959 * Initialize DCC/FMASK/CMASK metadata for a color image.
5960 */
5961 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
5962 struct radv_image *image,
5963 VkImageLayout src_layout,
5964 bool src_render_loop,
5965 VkImageLayout dst_layout,
5966 bool dst_render_loop,
5967 unsigned src_queue_mask,
5968 unsigned dst_queue_mask,
5969 const VkImageSubresourceRange *range)
5970 {
5971 if (radv_image_has_cmask(image)) {
5972 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5973
5974 /* TODO: clarify this. */
5975 if (radv_image_has_fmask(image)) {
5976 value = 0xccccccccu;
5977 }
5978
5979 radv_initialise_cmask(cmd_buffer, image, range, value);
5980 }
5981
5982 if (radv_image_has_fmask(image)) {
5983 radv_initialize_fmask(cmd_buffer, image, range);
5984 }
5985
5986 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5987 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5988 bool need_decompress_pass = false;
5989
5990 if (radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout,
5991 dst_render_loop,
5992 dst_queue_mask)) {
5993 value = 0x20202020u;
5994 need_decompress_pass = true;
5995 }
5996
5997 radv_initialize_dcc(cmd_buffer, image, range, value);
5998
5999 radv_update_fce_metadata(cmd_buffer, image, range,
6000 need_decompress_pass);
6001 }
6002
6003 if (radv_image_has_cmask(image) ||
6004 radv_dcc_enabled(image, range->baseMipLevel)) {
6005 uint32_t color_values[2] = {};
6006 radv_set_color_clear_metadata(cmd_buffer, image, range,
6007 color_values);
6008 }
6009 }
6010
6011 /**
6012 * Handle color image transitions for DCC/FMASK/CMASK.
6013 */
6014 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
6015 struct radv_image *image,
6016 VkImageLayout src_layout,
6017 bool src_render_loop,
6018 VkImageLayout dst_layout,
6019 bool dst_render_loop,
6020 unsigned src_queue_mask,
6021 unsigned dst_queue_mask,
6022 const VkImageSubresourceRange *range)
6023 {
6024 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
6025 radv_init_color_image_metadata(cmd_buffer, image,
6026 src_layout, src_render_loop,
6027 dst_layout, dst_render_loop,
6028 src_queue_mask, dst_queue_mask,
6029 range);
6030 return;
6031 }
6032
6033 if (radv_dcc_enabled(image, range->baseMipLevel)) {
6034 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
6035 radv_initialize_dcc(cmd_buffer, image, range, 0xffffffffu);
6036 } else if (radv_layout_dcc_compressed(cmd_buffer->device, image, src_layout, src_render_loop, src_queue_mask) &&
6037 !radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout, dst_render_loop, dst_queue_mask)) {
6038 radv_decompress_dcc(cmd_buffer, image, range);
6039 } else if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
6040 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
6041 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
6042 }
6043 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
6044 bool fce_eliminate = false, fmask_expand = false;
6045
6046 if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
6047 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
6048 fce_eliminate = true;
6049 }
6050
6051 if (radv_image_has_fmask(image)) {
6052 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
6053 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
6054 /* A FMASK decompress is required before doing
6055 * a MSAA decompress using FMASK.
6056 */
6057 fmask_expand = true;
6058 }
6059 }
6060
6061 if (fce_eliminate || fmask_expand)
6062 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
6063
6064 if (fmask_expand) {
6065 struct radv_barrier_data barrier = {};
6066 barrier.layout_transitions.fmask_color_expand = 1;
6067 radv_describe_layout_transition(cmd_buffer, &barrier);
6068
6069 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
6070 }
6071 }
6072 }
6073
6074 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
6075 struct radv_image *image,
6076 VkImageLayout src_layout,
6077 bool src_render_loop,
6078 VkImageLayout dst_layout,
6079 bool dst_render_loop,
6080 uint32_t src_family,
6081 uint32_t dst_family,
6082 const VkImageSubresourceRange *range,
6083 struct radv_sample_locations_state *sample_locs)
6084 {
6085 if (image->exclusive && src_family != dst_family) {
6086 /* This is an acquire or a release operation and there will be
6087 * a corresponding release/acquire. Do the transition in the
6088 * most flexible queue. */
6089
6090 assert(src_family == cmd_buffer->queue_family_index ||
6091 dst_family == cmd_buffer->queue_family_index);
6092
6093 if (src_family == VK_QUEUE_FAMILY_EXTERNAL ||
6094 src_family == VK_QUEUE_FAMILY_FOREIGN_EXT)
6095 return;
6096
6097 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
6098 return;
6099
6100 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
6101 (src_family == RADV_QUEUE_GENERAL ||
6102 dst_family == RADV_QUEUE_GENERAL))
6103 return;
6104 }
6105
6106 if (src_layout == dst_layout)
6107 return;
6108
6109 unsigned src_queue_mask =
6110 radv_image_queue_family_mask(image, src_family,
6111 cmd_buffer->queue_family_index);
6112 unsigned dst_queue_mask =
6113 radv_image_queue_family_mask(image, dst_family,
6114 cmd_buffer->queue_family_index);
6115
6116 if (vk_format_is_depth(image->vk_format)) {
6117 radv_handle_depth_image_transition(cmd_buffer, image,
6118 src_layout, src_render_loop,
6119 dst_layout, dst_render_loop,
6120 src_queue_mask, dst_queue_mask,
6121 range, sample_locs);
6122 } else {
6123 radv_handle_color_image_transition(cmd_buffer, image,
6124 src_layout, src_render_loop,
6125 dst_layout, dst_render_loop,
6126 src_queue_mask, dst_queue_mask,
6127 range);
6128 }
6129 }
6130
6131 struct radv_barrier_info {
6132 enum rgp_barrier_reason reason;
6133 uint32_t eventCount;
6134 const VkEvent *pEvents;
6135 VkPipelineStageFlags srcStageMask;
6136 VkPipelineStageFlags dstStageMask;
6137 };
6138
6139 static void
6140 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
6141 uint32_t memoryBarrierCount,
6142 const VkMemoryBarrier *pMemoryBarriers,
6143 uint32_t bufferMemoryBarrierCount,
6144 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
6145 uint32_t imageMemoryBarrierCount,
6146 const VkImageMemoryBarrier *pImageMemoryBarriers,
6147 const struct radv_barrier_info *info)
6148 {
6149 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6150 enum radv_cmd_flush_bits src_flush_bits = 0;
6151 enum radv_cmd_flush_bits dst_flush_bits = 0;
6152
6153 radv_describe_barrier_start(cmd_buffer, info->reason);
6154
6155 for (unsigned i = 0; i < info->eventCount; ++i) {
6156 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
6157 uint64_t va = radv_buffer_get_va(event->bo);
6158
6159 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
6160
6161 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
6162
6163 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
6164 assert(cmd_buffer->cs->cdw <= cdw_max);
6165 }
6166
6167 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
6168 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
6169 NULL);
6170 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
6171 NULL);
6172 }
6173
6174 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
6175 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
6176 NULL);
6177 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
6178 NULL);
6179 }
6180
6181 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
6182 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
6183
6184 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
6185 image);
6186 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
6187 image);
6188 }
6189
6190 /* The Vulkan spec 1.1.98 says:
6191 *
6192 * "An execution dependency with only
6193 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
6194 * will only prevent that stage from executing in subsequently
6195 * submitted commands. As this stage does not perform any actual
6196 * execution, this is not observable - in effect, it does not delay
6197 * processing of subsequent commands. Similarly an execution dependency
6198 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
6199 * will effectively not wait for any prior commands to complete."
6200 */
6201 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
6202 radv_stage_flush(cmd_buffer, info->srcStageMask);
6203 cmd_buffer->state.flush_bits |= src_flush_bits;
6204
6205 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
6206 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
6207
6208 const struct VkSampleLocationsInfoEXT *sample_locs_info =
6209 vk_find_struct_const(pImageMemoryBarriers[i].pNext,
6210 SAMPLE_LOCATIONS_INFO_EXT);
6211 struct radv_sample_locations_state sample_locations = {};
6212
6213 if (sample_locs_info) {
6214 assert(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
6215 sample_locations.per_pixel = sample_locs_info->sampleLocationsPerPixel;
6216 sample_locations.grid_size = sample_locs_info->sampleLocationGridSize;
6217 sample_locations.count = sample_locs_info->sampleLocationsCount;
6218 typed_memcpy(&sample_locations.locations[0],
6219 sample_locs_info->pSampleLocations,
6220 sample_locs_info->sampleLocationsCount);
6221 }
6222
6223 radv_handle_image_transition(cmd_buffer, image,
6224 pImageMemoryBarriers[i].oldLayout,
6225 false, /* Outside of a renderpass we are never in a renderloop */
6226 pImageMemoryBarriers[i].newLayout,
6227 false, /* Outside of a renderpass we are never in a renderloop */
6228 pImageMemoryBarriers[i].srcQueueFamilyIndex,
6229 pImageMemoryBarriers[i].dstQueueFamilyIndex,
6230 &pImageMemoryBarriers[i].subresourceRange,
6231 sample_locs_info ? &sample_locations : NULL);
6232 }
6233
6234 /* Make sure CP DMA is idle because the driver might have performed a
6235 * DMA operation for copying or filling buffers/images.
6236 */
6237 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
6238 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
6239 si_cp_dma_wait_for_idle(cmd_buffer);
6240
6241 cmd_buffer->state.flush_bits |= dst_flush_bits;
6242
6243 radv_describe_barrier_end(cmd_buffer);
6244 }
6245
6246 void radv_CmdPipelineBarrier(
6247 VkCommandBuffer commandBuffer,
6248 VkPipelineStageFlags srcStageMask,
6249 VkPipelineStageFlags destStageMask,
6250 VkBool32 byRegion,
6251 uint32_t memoryBarrierCount,
6252 const VkMemoryBarrier* pMemoryBarriers,
6253 uint32_t bufferMemoryBarrierCount,
6254 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
6255 uint32_t imageMemoryBarrierCount,
6256 const VkImageMemoryBarrier* pImageMemoryBarriers)
6257 {
6258 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6259 struct radv_barrier_info info;
6260
6261 info.reason = RGP_BARRIER_EXTERNAL_CMD_PIPELINE_BARRIER;
6262 info.eventCount = 0;
6263 info.pEvents = NULL;
6264 info.srcStageMask = srcStageMask;
6265 info.dstStageMask = destStageMask;
6266
6267 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
6268 bufferMemoryBarrierCount, pBufferMemoryBarriers,
6269 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
6270 }
6271
6272
6273 static void write_event(struct radv_cmd_buffer *cmd_buffer,
6274 struct radv_event *event,
6275 VkPipelineStageFlags stageMask,
6276 unsigned value)
6277 {
6278 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6279 uint64_t va = radv_buffer_get_va(event->bo);
6280
6281 si_emit_cache_flush(cmd_buffer);
6282
6283 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
6284
6285 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 21);
6286
6287 /* Flags that only require a top-of-pipe event. */
6288 VkPipelineStageFlags top_of_pipe_flags =
6289 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
6290
6291 /* Flags that only require a post-index-fetch event. */
6292 VkPipelineStageFlags post_index_fetch_flags =
6293 top_of_pipe_flags |
6294 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
6295 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
6296
6297 /* Make sure CP DMA is idle because the driver might have performed a
6298 * DMA operation for copying or filling buffers/images.
6299 */
6300 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
6301 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
6302 si_cp_dma_wait_for_idle(cmd_buffer);
6303
6304 /* TODO: Emit EOS events for syncing PS/CS stages. */
6305
6306 if (!(stageMask & ~top_of_pipe_flags)) {
6307 /* Just need to sync the PFP engine. */
6308 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
6309 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
6310 S_370_WR_CONFIRM(1) |
6311 S_370_ENGINE_SEL(V_370_PFP));
6312 radeon_emit(cs, va);
6313 radeon_emit(cs, va >> 32);
6314 radeon_emit(cs, value);
6315 } else if (!(stageMask & ~post_index_fetch_flags)) {
6316 /* Sync ME because PFP reads index and indirect buffers. */
6317 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
6318 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
6319 S_370_WR_CONFIRM(1) |
6320 S_370_ENGINE_SEL(V_370_ME));
6321 radeon_emit(cs, va);
6322 radeon_emit(cs, va >> 32);
6323 radeon_emit(cs, value);
6324 } else {
6325 /* Otherwise, sync all prior GPU work using an EOP event. */
6326 si_cs_emit_write_event_eop(cs,
6327 cmd_buffer->device->physical_device->rad_info.chip_class,
6328 radv_cmd_buffer_uses_mec(cmd_buffer),
6329 V_028A90_BOTTOM_OF_PIPE_TS, 0,
6330 EOP_DST_SEL_MEM,
6331 EOP_DATA_SEL_VALUE_32BIT, va, value,
6332 cmd_buffer->gfx9_eop_bug_va);
6333 }
6334
6335 assert(cmd_buffer->cs->cdw <= cdw_max);
6336 }
6337
6338 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
6339 VkEvent _event,
6340 VkPipelineStageFlags stageMask)
6341 {
6342 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6343 RADV_FROM_HANDLE(radv_event, event, _event);
6344
6345 write_event(cmd_buffer, event, stageMask, 1);
6346 }
6347
6348 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
6349 VkEvent _event,
6350 VkPipelineStageFlags stageMask)
6351 {
6352 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6353 RADV_FROM_HANDLE(radv_event, event, _event);
6354
6355 write_event(cmd_buffer, event, stageMask, 0);
6356 }
6357
6358 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
6359 uint32_t eventCount,
6360 const VkEvent* pEvents,
6361 VkPipelineStageFlags srcStageMask,
6362 VkPipelineStageFlags dstStageMask,
6363 uint32_t memoryBarrierCount,
6364 const VkMemoryBarrier* pMemoryBarriers,
6365 uint32_t bufferMemoryBarrierCount,
6366 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
6367 uint32_t imageMemoryBarrierCount,
6368 const VkImageMemoryBarrier* pImageMemoryBarriers)
6369 {
6370 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6371 struct radv_barrier_info info;
6372
6373 info.reason = RGP_BARRIER_EXTERNAL_CMD_WAIT_EVENTS;
6374 info.eventCount = eventCount;
6375 info.pEvents = pEvents;
6376 info.srcStageMask = 0;
6377
6378 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
6379 bufferMemoryBarrierCount, pBufferMemoryBarriers,
6380 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
6381 }
6382
6383
6384 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
6385 uint32_t deviceMask)
6386 {
6387 /* No-op */
6388 }
6389
6390 /* VK_EXT_conditional_rendering */
6391 void radv_CmdBeginConditionalRenderingEXT(
6392 VkCommandBuffer commandBuffer,
6393 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
6394 {
6395 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6396 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
6397 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6398 bool draw_visible = true;
6399 uint64_t pred_value = 0;
6400 uint64_t va, new_va;
6401 unsigned pred_offset;
6402
6403 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
6404
6405 /* By default, if the 32-bit value at offset in buffer memory is zero,
6406 * then the rendering commands are discarded, otherwise they are
6407 * executed as normal. If the inverted flag is set, all commands are
6408 * discarded if the value is non zero.
6409 */
6410 if (pConditionalRenderingBegin->flags &
6411 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
6412 draw_visible = false;
6413 }
6414
6415 si_emit_cache_flush(cmd_buffer);
6416
6417 /* From the Vulkan spec 1.1.107:
6418 *
6419 * "If the 32-bit value at offset in buffer memory is zero, then the
6420 * rendering commands are discarded, otherwise they are executed as
6421 * normal. If the value of the predicate in buffer memory changes while
6422 * conditional rendering is active, the rendering commands may be
6423 * discarded in an implementation-dependent way. Some implementations
6424 * may latch the value of the predicate upon beginning conditional
6425 * rendering while others may read it before every rendering command."
6426 *
6427 * But, the AMD hardware treats the predicate as a 64-bit value which
6428 * means we need a workaround in the driver. Luckily, it's not required
6429 * to support if the value changes when predication is active.
6430 *
6431 * The workaround is as follows:
6432 * 1) allocate a 64-value in the upload BO and initialize it to 0
6433 * 2) copy the 32-bit predicate value to the upload BO
6434 * 3) use the new allocated VA address for predication
6435 *
6436 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
6437 * in ME (+ sync PFP) instead of PFP.
6438 */
6439 radv_cmd_buffer_upload_data(cmd_buffer, 8, 16, &pred_value, &pred_offset);
6440
6441 new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
6442
6443 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
6444 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
6445 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
6446 COPY_DATA_WR_CONFIRM);
6447 radeon_emit(cs, va);
6448 radeon_emit(cs, va >> 32);
6449 radeon_emit(cs, new_va);
6450 radeon_emit(cs, new_va >> 32);
6451
6452 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
6453 radeon_emit(cs, 0);
6454
6455 /* Enable predication for this command buffer. */
6456 si_emit_set_predication_state(cmd_buffer, draw_visible, new_va);
6457 cmd_buffer->state.predicating = true;
6458
6459 /* Store conditional rendering user info. */
6460 cmd_buffer->state.predication_type = draw_visible;
6461 cmd_buffer->state.predication_va = new_va;
6462 }
6463
6464 void radv_CmdEndConditionalRenderingEXT(
6465 VkCommandBuffer commandBuffer)
6466 {
6467 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6468
6469 /* Disable predication for this command buffer. */
6470 si_emit_set_predication_state(cmd_buffer, false, 0);
6471 cmd_buffer->state.predicating = false;
6472
6473 /* Reset conditional rendering user info. */
6474 cmd_buffer->state.predication_type = -1;
6475 cmd_buffer->state.predication_va = 0;
6476 }
6477
6478 /* VK_EXT_transform_feedback */
6479 void radv_CmdBindTransformFeedbackBuffersEXT(
6480 VkCommandBuffer commandBuffer,
6481 uint32_t firstBinding,
6482 uint32_t bindingCount,
6483 const VkBuffer* pBuffers,
6484 const VkDeviceSize* pOffsets,
6485 const VkDeviceSize* pSizes)
6486 {
6487 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6488 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
6489 uint8_t enabled_mask = 0;
6490
6491 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
6492 for (uint32_t i = 0; i < bindingCount; i++) {
6493 uint32_t idx = firstBinding + i;
6494
6495 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
6496 sb[idx].offset = pOffsets[i];
6497
6498 if (!pSizes || pSizes[i] == VK_WHOLE_SIZE) {
6499 sb[idx].size = sb[idx].buffer->size - sb[idx].offset;
6500 } else {
6501 sb[idx].size = pSizes[i];
6502 }
6503
6504 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
6505 sb[idx].buffer->bo);
6506
6507 enabled_mask |= 1 << idx;
6508 }
6509
6510 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
6511
6512 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
6513 }
6514
6515 static void
6516 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
6517 {
6518 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6519 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6520
6521 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
6522 radeon_emit(cs,
6523 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
6524 S_028B94_RAST_STREAM(0) |
6525 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
6526 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
6527 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
6528 radeon_emit(cs, so->hw_enabled_mask &
6529 so->enabled_stream_buffers_mask);
6530
6531 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6532 }
6533
6534 static void
6535 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
6536 {
6537 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6538 bool old_streamout_enabled = so->streamout_enabled;
6539 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
6540
6541 so->streamout_enabled = enable;
6542
6543 so->hw_enabled_mask = so->enabled_mask |
6544 (so->enabled_mask << 4) |
6545 (so->enabled_mask << 8) |
6546 (so->enabled_mask << 12);
6547
6548 if (!cmd_buffer->device->physical_device->use_ngg_streamout &&
6549 ((old_streamout_enabled != so->streamout_enabled) ||
6550 (old_hw_enabled_mask != so->hw_enabled_mask)))
6551 radv_emit_streamout_enable(cmd_buffer);
6552
6553 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6554 cmd_buffer->gds_needed = true;
6555 cmd_buffer->gds_oa_needed = true;
6556 }
6557 }
6558
6559 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
6560 {
6561 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6562 unsigned reg_strmout_cntl;
6563
6564 /* The register is at different places on different ASICs. */
6565 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
6566 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
6567 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
6568 } else {
6569 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
6570 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
6571 }
6572
6573 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
6574 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
6575
6576 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
6577 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
6578 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
6579 radeon_emit(cs, 0);
6580 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
6581 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
6582 radeon_emit(cs, 4); /* poll interval */
6583 }
6584
6585 static void
6586 radv_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
6587 uint32_t firstCounterBuffer,
6588 uint32_t counterBufferCount,
6589 const VkBuffer *pCounterBuffers,
6590 const VkDeviceSize *pCounterBufferOffsets)
6591
6592 {
6593 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
6594 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6595 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6596 uint32_t i;
6597
6598 radv_flush_vgt_streamout(cmd_buffer);
6599
6600 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6601 for_each_bit(i, so->enabled_mask) {
6602 int32_t counter_buffer_idx = i - firstCounterBuffer;
6603 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6604 counter_buffer_idx = -1;
6605
6606 /* AMD GCN binds streamout buffers as shader resources.
6607 * VGT only counts primitives and tells the shader through
6608 * SGPRs what to do.
6609 */
6610 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
6611 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
6612 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
6613
6614 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6615
6616 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6617 /* The array of counter buffers is optional. */
6618 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6619 uint64_t va = radv_buffer_get_va(buffer->bo);
6620
6621 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6622
6623 /* Append */
6624 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6625 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6626 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6627 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
6628 radeon_emit(cs, 0); /* unused */
6629 radeon_emit(cs, 0); /* unused */
6630 radeon_emit(cs, va); /* src address lo */
6631 radeon_emit(cs, va >> 32); /* src address hi */
6632
6633 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6634 } else {
6635 /* Start from the beginning. */
6636 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6637 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6638 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6639 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
6640 radeon_emit(cs, 0); /* unused */
6641 radeon_emit(cs, 0); /* unused */
6642 radeon_emit(cs, 0); /* unused */
6643 radeon_emit(cs, 0); /* unused */
6644 }
6645 }
6646
6647 radv_set_streamout_enable(cmd_buffer, true);
6648 }
6649
6650 static void
6651 gfx10_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
6652 uint32_t firstCounterBuffer,
6653 uint32_t counterBufferCount,
6654 const VkBuffer *pCounterBuffers,
6655 const VkDeviceSize *pCounterBufferOffsets)
6656 {
6657 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6658 unsigned last_target = util_last_bit(so->enabled_mask) - 1;
6659 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6660 uint32_t i;
6661
6662 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6663 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6664
6665 /* Sync because the next streamout operation will overwrite GDS and we
6666 * have to make sure it's idle.
6667 * TODO: Improve by tracking if there is a streamout operation in
6668 * flight.
6669 */
6670 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
6671 si_emit_cache_flush(cmd_buffer);
6672
6673 for_each_bit(i, so->enabled_mask) {
6674 int32_t counter_buffer_idx = i - firstCounterBuffer;
6675 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6676 counter_buffer_idx = -1;
6677
6678 bool append = counter_buffer_idx >= 0 &&
6679 pCounterBuffers && pCounterBuffers[counter_buffer_idx];
6680 uint64_t va = 0;
6681
6682 if (append) {
6683 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6684
6685 va += radv_buffer_get_va(buffer->bo);
6686 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6687
6688 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6689 }
6690
6691 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
6692 radeon_emit(cs, S_411_SRC_SEL(append ? V_411_SRC_ADDR_TC_L2 : V_411_DATA) |
6693 S_411_DST_SEL(V_411_GDS) |
6694 S_411_CP_SYNC(i == last_target));
6695 radeon_emit(cs, va);
6696 radeon_emit(cs, va >> 32);
6697 radeon_emit(cs, 4 * i); /* destination in GDS */
6698 radeon_emit(cs, 0);
6699 radeon_emit(cs, S_414_BYTE_COUNT_GFX9(4) |
6700 S_414_DISABLE_WR_CONFIRM_GFX9(i != last_target));
6701 }
6702
6703 radv_set_streamout_enable(cmd_buffer, true);
6704 }
6705
6706 void radv_CmdBeginTransformFeedbackEXT(
6707 VkCommandBuffer commandBuffer,
6708 uint32_t firstCounterBuffer,
6709 uint32_t counterBufferCount,
6710 const VkBuffer* pCounterBuffers,
6711 const VkDeviceSize* pCounterBufferOffsets)
6712 {
6713 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6714
6715 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6716 gfx10_emit_streamout_begin(cmd_buffer,
6717 firstCounterBuffer, counterBufferCount,
6718 pCounterBuffers, pCounterBufferOffsets);
6719 } else {
6720 radv_emit_streamout_begin(cmd_buffer,
6721 firstCounterBuffer, counterBufferCount,
6722 pCounterBuffers, pCounterBufferOffsets);
6723 }
6724 }
6725
6726 static void
6727 radv_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6728 uint32_t firstCounterBuffer,
6729 uint32_t counterBufferCount,
6730 const VkBuffer *pCounterBuffers,
6731 const VkDeviceSize *pCounterBufferOffsets)
6732 {
6733 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6734 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6735 uint32_t i;
6736
6737 radv_flush_vgt_streamout(cmd_buffer);
6738
6739 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6740 for_each_bit(i, so->enabled_mask) {
6741 int32_t counter_buffer_idx = i - firstCounterBuffer;
6742 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6743 counter_buffer_idx = -1;
6744
6745 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6746 /* The array of counters buffer is optional. */
6747 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6748 uint64_t va = radv_buffer_get_va(buffer->bo);
6749
6750 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6751
6752 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6753 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6754 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6755 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
6756 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
6757 radeon_emit(cs, va); /* dst address lo */
6758 radeon_emit(cs, va >> 32); /* dst address hi */
6759 radeon_emit(cs, 0); /* unused */
6760 radeon_emit(cs, 0); /* unused */
6761
6762 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6763 }
6764
6765 /* Deactivate transform feedback by zeroing the buffer size.
6766 * The counters (primitives generated, primitives emitted) may
6767 * be enabled even if there is not buffer bound. This ensures
6768 * that the primitives-emitted query won't increment.
6769 */
6770 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
6771
6772 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6773 }
6774
6775 radv_set_streamout_enable(cmd_buffer, false);
6776 }
6777
6778 static void
6779 gfx10_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6780 uint32_t firstCounterBuffer,
6781 uint32_t counterBufferCount,
6782 const VkBuffer *pCounterBuffers,
6783 const VkDeviceSize *pCounterBufferOffsets)
6784 {
6785 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6786 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6787 uint32_t i;
6788
6789 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6790 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6791
6792 for_each_bit(i, so->enabled_mask) {
6793 int32_t counter_buffer_idx = i - firstCounterBuffer;
6794 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6795 counter_buffer_idx = -1;
6796
6797 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6798 /* The array of counters buffer is optional. */
6799 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6800 uint64_t va = radv_buffer_get_va(buffer->bo);
6801
6802 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6803
6804 si_cs_emit_write_event_eop(cs,
6805 cmd_buffer->device->physical_device->rad_info.chip_class,
6806 radv_cmd_buffer_uses_mec(cmd_buffer),
6807 V_028A90_PS_DONE, 0,
6808 EOP_DST_SEL_TC_L2,
6809 EOP_DATA_SEL_GDS,
6810 va, EOP_DATA_GDS(i, 1), 0);
6811
6812 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6813 }
6814 }
6815
6816 radv_set_streamout_enable(cmd_buffer, false);
6817 }
6818
6819 void radv_CmdEndTransformFeedbackEXT(
6820 VkCommandBuffer commandBuffer,
6821 uint32_t firstCounterBuffer,
6822 uint32_t counterBufferCount,
6823 const VkBuffer* pCounterBuffers,
6824 const VkDeviceSize* pCounterBufferOffsets)
6825 {
6826 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6827
6828 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6829 gfx10_emit_streamout_end(cmd_buffer,
6830 firstCounterBuffer, counterBufferCount,
6831 pCounterBuffers, pCounterBufferOffsets);
6832 } else {
6833 radv_emit_streamout_end(cmd_buffer,
6834 firstCounterBuffer, counterBufferCount,
6835 pCounterBuffers, pCounterBufferOffsets);
6836 }
6837 }
6838
6839 void radv_CmdDrawIndirectByteCountEXT(
6840 VkCommandBuffer commandBuffer,
6841 uint32_t instanceCount,
6842 uint32_t firstInstance,
6843 VkBuffer _counterBuffer,
6844 VkDeviceSize counterBufferOffset,
6845 uint32_t counterOffset,
6846 uint32_t vertexStride)
6847 {
6848 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6849 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
6850 struct radv_draw_info info = {};
6851
6852 info.instance_count = instanceCount;
6853 info.first_instance = firstInstance;
6854 info.strmout_buffer = counterBuffer;
6855 info.strmout_buffer_offset = counterBufferOffset;
6856 info.stride = vertexStride;
6857
6858 radv_draw(cmd_buffer, &info);
6859 }
6860
6861 /* VK_AMD_buffer_marker */
6862 void radv_CmdWriteBufferMarkerAMD(
6863 VkCommandBuffer commandBuffer,
6864 VkPipelineStageFlagBits pipelineStage,
6865 VkBuffer dstBuffer,
6866 VkDeviceSize dstOffset,
6867 uint32_t marker)
6868 {
6869 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6870 RADV_FROM_HANDLE(radv_buffer, buffer, dstBuffer);
6871 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6872 uint64_t va = radv_buffer_get_va(buffer->bo) + dstOffset;
6873
6874 si_emit_cache_flush(cmd_buffer);
6875
6876 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 12);
6877
6878 if (!(pipelineStage & ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT)) {
6879 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
6880 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
6881 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
6882 COPY_DATA_WR_CONFIRM);
6883 radeon_emit(cs, marker);
6884 radeon_emit(cs, 0);
6885 radeon_emit(cs, va);
6886 radeon_emit(cs, va >> 32);
6887 } else {
6888 si_cs_emit_write_event_eop(cs,
6889 cmd_buffer->device->physical_device->rad_info.chip_class,
6890 radv_cmd_buffer_uses_mec(cmd_buffer),
6891 V_028A90_BOTTOM_OF_PIPE_TS, 0,
6892 EOP_DST_SEL_MEM,
6893 EOP_DATA_SEL_VALUE_32BIT,
6894 va, marker,
6895 cmd_buffer->gfx9_eop_bug_va);
6896 }
6897
6898 assert(cmd_buffer->cs->cdw <= cdw_max);
6899 }