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radv: do not perform read-modify-write with the upload BO
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 bool src_render_loop,
58 VkImageLayout dst_layout,
59 bool dst_render_loop,
60 uint32_t src_family,
61 uint32_t dst_family,
62 const VkImageSubresourceRange *range,
63 struct radv_sample_locations_state *sample_locs);
64
65 const struct radv_dynamic_state default_dynamic_state = {
66 .viewport = {
67 .count = 0,
68 },
69 .scissor = {
70 .count = 0,
71 },
72 .line_width = 1.0f,
73 .depth_bias = {
74 .bias = 0.0f,
75 .clamp = 0.0f,
76 .slope = 0.0f,
77 },
78 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
79 .depth_bounds = {
80 .min = 0.0f,
81 .max = 1.0f,
82 },
83 .stencil_compare_mask = {
84 .front = ~0u,
85 .back = ~0u,
86 },
87 .stencil_write_mask = {
88 .front = ~0u,
89 .back = ~0u,
90 },
91 .stencil_reference = {
92 .front = 0u,
93 .back = 0u,
94 },
95 .line_stipple = {
96 .factor = 0u,
97 .pattern = 0u,
98 },
99 .cull_mode = 0u,
100 .front_face = 0u,
101 .primitive_topology = 0u,
102 };
103
104 static void
105 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
106 const struct radv_dynamic_state *src)
107 {
108 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
109 uint32_t copy_mask = src->mask;
110 uint32_t dest_mask = 0;
111
112 dest->discard_rectangle.count = src->discard_rectangle.count;
113 dest->sample_location.count = src->sample_location.count;
114
115 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
116 if (dest->viewport.count != src->viewport.count) {
117 dest->viewport.count = src->viewport.count;
118 dest_mask |= RADV_DYNAMIC_VIEWPORT;
119 }
120
121 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
122 src->viewport.count * sizeof(VkViewport))) {
123 typed_memcpy(dest->viewport.viewports,
124 src->viewport.viewports,
125 src->viewport.count);
126 dest_mask |= RADV_DYNAMIC_VIEWPORT;
127 }
128 }
129
130 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
131 if (dest->scissor.count != src->scissor.count) {
132 dest->scissor.count = src->scissor.count;
133 dest_mask |= RADV_DYNAMIC_SCISSOR;
134 }
135
136 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
137 src->scissor.count * sizeof(VkRect2D))) {
138 typed_memcpy(dest->scissor.scissors,
139 src->scissor.scissors, src->scissor.count);
140 dest_mask |= RADV_DYNAMIC_SCISSOR;
141 }
142 }
143
144 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
145 if (dest->line_width != src->line_width) {
146 dest->line_width = src->line_width;
147 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
148 }
149 }
150
151 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
152 if (memcmp(&dest->depth_bias, &src->depth_bias,
153 sizeof(src->depth_bias))) {
154 dest->depth_bias = src->depth_bias;
155 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
156 }
157 }
158
159 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
160 if (memcmp(&dest->blend_constants, &src->blend_constants,
161 sizeof(src->blend_constants))) {
162 typed_memcpy(dest->blend_constants,
163 src->blend_constants, 4);
164 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
165 }
166 }
167
168 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
169 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
170 sizeof(src->depth_bounds))) {
171 dest->depth_bounds = src->depth_bounds;
172 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
173 }
174 }
175
176 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
177 if (memcmp(&dest->stencil_compare_mask,
178 &src->stencil_compare_mask,
179 sizeof(src->stencil_compare_mask))) {
180 dest->stencil_compare_mask = src->stencil_compare_mask;
181 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
182 }
183 }
184
185 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
186 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
187 sizeof(src->stencil_write_mask))) {
188 dest->stencil_write_mask = src->stencil_write_mask;
189 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
190 }
191 }
192
193 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
194 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
195 sizeof(src->stencil_reference))) {
196 dest->stencil_reference = src->stencil_reference;
197 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
198 }
199 }
200
201 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
202 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
203 src->discard_rectangle.count * sizeof(VkRect2D))) {
204 typed_memcpy(dest->discard_rectangle.rectangles,
205 src->discard_rectangle.rectangles,
206 src->discard_rectangle.count);
207 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
208 }
209 }
210
211 if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
212 if (dest->sample_location.per_pixel != src->sample_location.per_pixel ||
213 dest->sample_location.grid_size.width != src->sample_location.grid_size.width ||
214 dest->sample_location.grid_size.height != src->sample_location.grid_size.height ||
215 memcmp(&dest->sample_location.locations,
216 &src->sample_location.locations,
217 src->sample_location.count * sizeof(VkSampleLocationEXT))) {
218 dest->sample_location.per_pixel = src->sample_location.per_pixel;
219 dest->sample_location.grid_size = src->sample_location.grid_size;
220 typed_memcpy(dest->sample_location.locations,
221 src->sample_location.locations,
222 src->sample_location.count);
223 dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
224 }
225 }
226
227 if (copy_mask & RADV_DYNAMIC_LINE_STIPPLE) {
228 if (memcmp(&dest->line_stipple, &src->line_stipple,
229 sizeof(src->line_stipple))) {
230 dest->line_stipple = src->line_stipple;
231 dest_mask |= RADV_DYNAMIC_LINE_STIPPLE;
232 }
233 }
234
235 if (copy_mask & RADV_DYNAMIC_CULL_MODE) {
236 if (dest->cull_mode != src->cull_mode) {
237 dest->cull_mode = src->cull_mode;
238 dest_mask |= RADV_DYNAMIC_CULL_MODE;
239 }
240 }
241
242 if (copy_mask & RADV_DYNAMIC_FRONT_FACE) {
243 if (dest->front_face != src->front_face) {
244 dest->front_face = src->front_face;
245 dest_mask |= RADV_DYNAMIC_FRONT_FACE;
246 }
247 }
248
249 if (copy_mask & RADV_DYNAMIC_PRIMITIVE_TOPOLOGY) {
250 if (dest->primitive_topology != src->primitive_topology) {
251 dest->primitive_topology = src->primitive_topology;
252 dest_mask |= RADV_DYNAMIC_PRIMITIVE_TOPOLOGY;
253 }
254 }
255
256 if (copy_mask & RADV_DYNAMIC_DEPTH_TEST_ENABLE) {
257 if (dest->depth_test_enable != src->depth_test_enable) {
258 dest->depth_test_enable = src->depth_test_enable;
259 dest_mask |= RADV_DYNAMIC_DEPTH_TEST_ENABLE;
260 }
261 }
262
263 if (copy_mask & RADV_DYNAMIC_DEPTH_WRITE_ENABLE) {
264 if (dest->depth_write_enable != src->depth_write_enable) {
265 dest->depth_write_enable = src->depth_write_enable;
266 dest_mask |= RADV_DYNAMIC_DEPTH_WRITE_ENABLE;
267 }
268 }
269
270 if (copy_mask & RADV_DYNAMIC_DEPTH_COMPARE_OP) {
271 if (dest->depth_compare_op != src->depth_compare_op) {
272 dest->depth_compare_op = src->depth_compare_op;
273 dest_mask |= RADV_DYNAMIC_DEPTH_COMPARE_OP;
274 }
275 }
276
277 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE) {
278 if (dest->depth_bounds_test_enable != src->depth_bounds_test_enable) {
279 dest->depth_bounds_test_enable = src->depth_bounds_test_enable;
280 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE;
281 }
282 }
283
284 if (copy_mask & RADV_DYNAMIC_STENCIL_TEST_ENABLE) {
285 if (dest->stencil_test_enable != src->stencil_test_enable) {
286 dest->stencil_test_enable = src->stencil_test_enable;
287 dest_mask |= RADV_DYNAMIC_STENCIL_TEST_ENABLE;
288 }
289 }
290
291 if (copy_mask & RADV_DYNAMIC_STENCIL_OP) {
292 if (memcmp(&dest->stencil_op, &src->stencil_op,
293 sizeof(src->stencil_op))) {
294 dest->stencil_op = src->stencil_op;
295 dest_mask |= RADV_DYNAMIC_STENCIL_OP;
296 }
297 }
298
299 cmd_buffer->state.dirty |= dest_mask;
300 }
301
302 static void
303 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
304 struct radv_pipeline *pipeline)
305 {
306 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
307 struct radv_shader_info *info;
308
309 if (!pipeline->streamout_shader ||
310 cmd_buffer->device->physical_device->use_ngg_streamout)
311 return;
312
313 info = &pipeline->streamout_shader->info;
314 for (int i = 0; i < MAX_SO_BUFFERS; i++)
315 so->stride_in_dw[i] = info->so.strides[i];
316
317 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
318 }
319
320 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
321 {
322 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
323 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
324 }
325
326 enum ring_type radv_queue_family_to_ring(int f) {
327 switch (f) {
328 case RADV_QUEUE_GENERAL:
329 return RING_GFX;
330 case RADV_QUEUE_COMPUTE:
331 return RING_COMPUTE;
332 case RADV_QUEUE_TRANSFER:
333 return RING_DMA;
334 default:
335 unreachable("Unknown queue family");
336 }
337 }
338
339 static void
340 radv_destroy_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
341 {
342 list_del(&cmd_buffer->pool_link);
343
344 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
345 &cmd_buffer->upload.list, list) {
346 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
347 list_del(&up->list);
348 free(up);
349 }
350
351 if (cmd_buffer->upload.upload_bo)
352 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
353
354 if (cmd_buffer->cs)
355 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
356
357 for (unsigned i = 0; i < MAX_BIND_POINTS; i++)
358 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
359
360 vk_object_base_finish(&cmd_buffer->base);
361 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
362 }
363
364 static VkResult radv_create_cmd_buffer(
365 struct radv_device * device,
366 struct radv_cmd_pool * pool,
367 VkCommandBufferLevel level,
368 VkCommandBuffer* pCommandBuffer)
369 {
370 struct radv_cmd_buffer *cmd_buffer;
371 unsigned ring;
372 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
373 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
374 if (cmd_buffer == NULL)
375 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
376
377 vk_object_base_init(&device->vk, &cmd_buffer->base,
378 VK_OBJECT_TYPE_COMMAND_BUFFER);
379
380 cmd_buffer->device = device;
381 cmd_buffer->pool = pool;
382 cmd_buffer->level = level;
383
384 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
385 cmd_buffer->queue_family_index = pool->queue_family_index;
386
387 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
388
389 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
390 if (!cmd_buffer->cs) {
391 radv_destroy_cmd_buffer(cmd_buffer);
392 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
393 }
394
395 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
396
397 list_inithead(&cmd_buffer->upload.list);
398
399 return VK_SUCCESS;
400 }
401
402 static VkResult
403 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
404 {
405 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
406
407 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
408 &cmd_buffer->upload.list, list) {
409 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
410 list_del(&up->list);
411 free(up);
412 }
413
414 cmd_buffer->push_constant_stages = 0;
415 cmd_buffer->scratch_size_per_wave_needed = 0;
416 cmd_buffer->scratch_waves_wanted = 0;
417 cmd_buffer->compute_scratch_size_per_wave_needed = 0;
418 cmd_buffer->compute_scratch_waves_wanted = 0;
419 cmd_buffer->esgs_ring_size_needed = 0;
420 cmd_buffer->gsvs_ring_size_needed = 0;
421 cmd_buffer->tess_rings_needed = false;
422 cmd_buffer->gds_needed = false;
423 cmd_buffer->gds_oa_needed = false;
424 cmd_buffer->sample_positions_needed = false;
425
426 if (cmd_buffer->upload.upload_bo)
427 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
428 cmd_buffer->upload.upload_bo);
429 cmd_buffer->upload.offset = 0;
430
431 cmd_buffer->record_result = VK_SUCCESS;
432
433 memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
434
435 for (unsigned i = 0; i < MAX_BIND_POINTS; i++) {
436 cmd_buffer->descriptors[i].dirty = 0;
437 cmd_buffer->descriptors[i].valid = 0;
438 cmd_buffer->descriptors[i].push_dirty = false;
439 }
440
441 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
442 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
443 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
444 unsigned fence_offset, eop_bug_offset;
445 void *fence_ptr;
446
447 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
448 &fence_ptr);
449
450 cmd_buffer->gfx9_fence_va =
451 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
452 cmd_buffer->gfx9_fence_va += fence_offset;
453
454 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
455 /* Allocate a buffer for the EOP bug on GFX9. */
456 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
457 &eop_bug_offset, &fence_ptr);
458 cmd_buffer->gfx9_eop_bug_va =
459 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
460 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
461 }
462 }
463
464 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
465
466 return cmd_buffer->record_result;
467 }
468
469 static bool
470 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
471 uint64_t min_needed)
472 {
473 uint64_t new_size;
474 struct radeon_winsys_bo *bo;
475 struct radv_cmd_buffer_upload *upload;
476 struct radv_device *device = cmd_buffer->device;
477
478 new_size = MAX2(min_needed, 16 * 1024);
479 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
480
481 bo = device->ws->buffer_create(device->ws,
482 new_size, 4096,
483 RADEON_DOMAIN_GTT,
484 RADEON_FLAG_CPU_ACCESS|
485 RADEON_FLAG_NO_INTERPROCESS_SHARING |
486 RADEON_FLAG_32BIT,
487 RADV_BO_PRIORITY_UPLOAD_BUFFER);
488
489 if (!bo) {
490 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
491 return false;
492 }
493
494 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
495 if (cmd_buffer->upload.upload_bo) {
496 upload = malloc(sizeof(*upload));
497
498 if (!upload) {
499 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
500 device->ws->buffer_destroy(bo);
501 return false;
502 }
503
504 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
505 list_add(&upload->list, &cmd_buffer->upload.list);
506 }
507
508 cmd_buffer->upload.upload_bo = bo;
509 cmd_buffer->upload.size = new_size;
510 cmd_buffer->upload.offset = 0;
511 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
512
513 if (!cmd_buffer->upload.map) {
514 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
515 return false;
516 }
517
518 return true;
519 }
520
521 bool
522 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
523 unsigned size,
524 unsigned alignment,
525 unsigned *out_offset,
526 void **ptr)
527 {
528 assert(util_is_power_of_two_nonzero(alignment));
529
530 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
531 if (offset + size > cmd_buffer->upload.size) {
532 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
533 return false;
534 offset = 0;
535 }
536
537 *out_offset = offset;
538 *ptr = cmd_buffer->upload.map + offset;
539
540 cmd_buffer->upload.offset = offset + size;
541 return true;
542 }
543
544 bool
545 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
546 unsigned size, unsigned alignment,
547 const void *data, unsigned *out_offset)
548 {
549 uint8_t *ptr;
550
551 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
552 out_offset, (void **)&ptr))
553 return false;
554
555 if (ptr)
556 memcpy(ptr, data, size);
557
558 return true;
559 }
560
561 static void
562 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
563 unsigned count, const uint32_t *data)
564 {
565 struct radeon_cmdbuf *cs = cmd_buffer->cs;
566
567 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
568
569 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
570 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
571 S_370_WR_CONFIRM(1) |
572 S_370_ENGINE_SEL(V_370_ME));
573 radeon_emit(cs, va);
574 radeon_emit(cs, va >> 32);
575 radeon_emit_array(cs, data, count);
576 }
577
578 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
579 {
580 struct radv_device *device = cmd_buffer->device;
581 struct radeon_cmdbuf *cs = cmd_buffer->cs;
582 uint64_t va;
583
584 va = radv_buffer_get_va(device->trace_bo);
585 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
586 va += 4;
587
588 ++cmd_buffer->state.trace_id;
589 radv_emit_write_data_packet(cmd_buffer, va, 1,
590 &cmd_buffer->state.trace_id);
591
592 radeon_check_space(cmd_buffer->device->ws, cs, 2);
593
594 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
595 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
596 }
597
598 static void
599 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
600 enum radv_cmd_flush_bits flags)
601 {
602 if (unlikely(cmd_buffer->device->thread_trace_bo)) {
603 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
604 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_THREAD_TRACE_MARKER) | EVENT_INDEX(0));
605 }
606
607 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
608 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
609 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
610
611 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
612
613 /* Force wait for graphics or compute engines to be idle. */
614 si_cs_emit_cache_flush(cmd_buffer->cs,
615 cmd_buffer->device->physical_device->rad_info.chip_class,
616 &cmd_buffer->gfx9_fence_idx,
617 cmd_buffer->gfx9_fence_va,
618 radv_cmd_buffer_uses_mec(cmd_buffer),
619 flags, cmd_buffer->gfx9_eop_bug_va);
620 }
621
622 if (unlikely(cmd_buffer->device->trace_bo))
623 radv_cmd_buffer_trace_emit(cmd_buffer);
624 }
625
626 static void
627 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
628 struct radv_pipeline *pipeline, enum ring_type ring)
629 {
630 struct radv_device *device = cmd_buffer->device;
631 uint32_t data[2];
632 uint64_t va;
633
634 va = radv_buffer_get_va(device->trace_bo);
635
636 switch (ring) {
637 case RING_GFX:
638 va += 8;
639 break;
640 case RING_COMPUTE:
641 va += 16;
642 break;
643 default:
644 assert(!"invalid ring type");
645 }
646
647 uint64_t pipeline_address = (uintptr_t)pipeline;
648 data[0] = pipeline_address;
649 data[1] = pipeline_address >> 32;
650
651 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
652 }
653
654 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
655 VkPipelineBindPoint bind_point,
656 struct radv_descriptor_set *set,
657 unsigned idx)
658 {
659 struct radv_descriptor_state *descriptors_state =
660 radv_get_descriptors_state(cmd_buffer, bind_point);
661
662 descriptors_state->sets[idx] = set;
663
664 descriptors_state->valid |= (1u << idx); /* active descriptors */
665 descriptors_state->dirty |= (1u << idx);
666 }
667
668 static void
669 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
670 VkPipelineBindPoint bind_point)
671 {
672 struct radv_descriptor_state *descriptors_state =
673 radv_get_descriptors_state(cmd_buffer, bind_point);
674 struct radv_device *device = cmd_buffer->device;
675 uint32_t data[MAX_SETS * 2] = {};
676 uint64_t va;
677 unsigned i;
678 va = radv_buffer_get_va(device->trace_bo) + 24;
679
680 for_each_bit(i, descriptors_state->valid) {
681 struct radv_descriptor_set *set = descriptors_state->sets[i];
682 data[i * 2] = (uint64_t)(uintptr_t)set;
683 data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
684 }
685
686 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
687 }
688
689 struct radv_userdata_info *
690 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
691 gl_shader_stage stage,
692 int idx)
693 {
694 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
695 return &shader->info.user_sgprs_locs.shader_data[idx];
696 }
697
698 static void
699 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
700 struct radv_pipeline *pipeline,
701 gl_shader_stage stage,
702 int idx, uint64_t va)
703 {
704 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
705 uint32_t base_reg = pipeline->user_data_0[stage];
706 if (loc->sgpr_idx == -1)
707 return;
708
709 assert(loc->num_sgprs == 1);
710
711 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
712 base_reg + loc->sgpr_idx * 4, va, false);
713 }
714
715 static void
716 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
717 struct radv_pipeline *pipeline,
718 struct radv_descriptor_state *descriptors_state,
719 gl_shader_stage stage)
720 {
721 struct radv_device *device = cmd_buffer->device;
722 struct radeon_cmdbuf *cs = cmd_buffer->cs;
723 uint32_t sh_base = pipeline->user_data_0[stage];
724 struct radv_userdata_locations *locs =
725 &pipeline->shaders[stage]->info.user_sgprs_locs;
726 unsigned mask = locs->descriptor_sets_enabled;
727
728 mask &= descriptors_state->dirty & descriptors_state->valid;
729
730 while (mask) {
731 int start, count;
732
733 u_bit_scan_consecutive_range(&mask, &start, &count);
734
735 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
736 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
737
738 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
739 for (int i = 0; i < count; i++) {
740 struct radv_descriptor_set *set =
741 descriptors_state->sets[start + i];
742
743 radv_emit_shader_pointer_body(device, cs, set->va, true);
744 }
745 }
746 }
747
748 /**
749 * Convert the user sample locations to hardware sample locations (the values
750 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
751 */
752 static void
753 radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
754 uint32_t x, uint32_t y, VkOffset2D *sample_locs)
755 {
756 uint32_t x_offset = x % state->grid_size.width;
757 uint32_t y_offset = y % state->grid_size.height;
758 uint32_t num_samples = (uint32_t)state->per_pixel;
759 VkSampleLocationEXT *user_locs;
760 uint32_t pixel_offset;
761
762 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
763
764 assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
765 user_locs = &state->locations[pixel_offset];
766
767 for (uint32_t i = 0; i < num_samples; i++) {
768 float shifted_pos_x = user_locs[i].x - 0.5;
769 float shifted_pos_y = user_locs[i].y - 0.5;
770
771 int32_t scaled_pos_x = floorf(shifted_pos_x * 16);
772 int32_t scaled_pos_y = floorf(shifted_pos_y * 16);
773
774 sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
775 sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
776 }
777 }
778
779 /**
780 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
781 * locations.
782 */
783 static void
784 radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
785 uint32_t *sample_locs_pixel)
786 {
787 for (uint32_t i = 0; i < num_samples; i++) {
788 uint32_t sample_reg_idx = i / 4;
789 uint32_t sample_loc_idx = i % 4;
790 int32_t pos_x = sample_locs[i].x;
791 int32_t pos_y = sample_locs[i].y;
792
793 uint32_t shift_x = 8 * sample_loc_idx;
794 uint32_t shift_y = shift_x + 4;
795
796 sample_locs_pixel[sample_reg_idx] |= (pos_x & 0xf) << shift_x;
797 sample_locs_pixel[sample_reg_idx] |= (pos_y & 0xf) << shift_y;
798 }
799 }
800
801 /**
802 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
803 * sample locations.
804 */
805 static uint64_t
806 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer,
807 VkOffset2D *sample_locs,
808 uint32_t num_samples)
809 {
810 uint32_t centroid_priorities[num_samples];
811 uint32_t sample_mask = num_samples - 1;
812 uint32_t distances[num_samples];
813 uint64_t centroid_priority = 0;
814
815 /* Compute the distances from center for each sample. */
816 for (int i = 0; i < num_samples; i++) {
817 distances[i] = (sample_locs[i].x * sample_locs[i].x) +
818 (sample_locs[i].y * sample_locs[i].y);
819 }
820
821 /* Compute the centroid priorities by looking at the distances array. */
822 for (int i = 0; i < num_samples; i++) {
823 uint32_t min_idx = 0;
824
825 for (int j = 1; j < num_samples; j++) {
826 if (distances[j] < distances[min_idx])
827 min_idx = j;
828 }
829
830 centroid_priorities[i] = min_idx;
831 distances[min_idx] = 0xffffffff;
832 }
833
834 /* Compute the final centroid priority. */
835 for (int i = 0; i < 8; i++) {
836 centroid_priority |=
837 centroid_priorities[i & sample_mask] << (i * 4);
838 }
839
840 return centroid_priority << 32 | centroid_priority;
841 }
842
843 /**
844 * Emit the sample locations that are specified with VK_EXT_sample_locations.
845 */
846 static void
847 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
848 {
849 struct radv_sample_locations_state *sample_location =
850 &cmd_buffer->state.dynamic.sample_location;
851 uint32_t num_samples = (uint32_t)sample_location->per_pixel;
852 struct radeon_cmdbuf *cs = cmd_buffer->cs;
853 uint32_t sample_locs_pixel[4][2] = {};
854 VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
855 uint32_t max_sample_dist = 0;
856 uint64_t centroid_priority;
857
858 if (!cmd_buffer->state.dynamic.sample_location.count)
859 return;
860
861 /* Convert the user sample locations to hardware sample locations. */
862 radv_convert_user_sample_locs(sample_location, 0, 0, sample_locs[0]);
863 radv_convert_user_sample_locs(sample_location, 1, 0, sample_locs[1]);
864 radv_convert_user_sample_locs(sample_location, 0, 1, sample_locs[2]);
865 radv_convert_user_sample_locs(sample_location, 1, 1, sample_locs[3]);
866
867 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
868 for (uint32_t i = 0; i < 4; i++) {
869 radv_compute_sample_locs_pixel(num_samples, sample_locs[i],
870 sample_locs_pixel[i]);
871 }
872
873 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
874 centroid_priority =
875 radv_compute_centroid_priority(cmd_buffer, sample_locs[0],
876 num_samples);
877
878 /* Compute the maximum sample distance from the specified locations. */
879 for (unsigned i = 0; i < 4; ++i) {
880 for (uint32_t j = 0; j < num_samples; j++) {
881 VkOffset2D offset = sample_locs[i][j];
882 max_sample_dist = MAX2(max_sample_dist,
883 MAX2(abs(offset.x), abs(offset.y)));
884 }
885 }
886
887 /* Emit the specified user sample locations. */
888 switch (num_samples) {
889 case 2:
890 case 4:
891 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
892 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
893 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
894 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
895 break;
896 case 8:
897 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
898 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
899 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
900 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
901 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs_pixel[0][1]);
902 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs_pixel[1][1]);
903 radeon_set_context_reg(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs_pixel[2][1]);
904 radeon_set_context_reg(cs, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs_pixel[3][1]);
905 break;
906 default:
907 unreachable("invalid number of samples");
908 }
909
910 /* Emit the maximum sample distance and the centroid priority. */
911 radeon_set_context_reg_rmw(cs, R_028BE0_PA_SC_AA_CONFIG,
912 S_028BE0_MAX_SAMPLE_DIST(max_sample_dist),
913 ~C_028BE0_MAX_SAMPLE_DIST);
914
915 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
916 radeon_emit(cs, centroid_priority);
917 radeon_emit(cs, centroid_priority >> 32);
918
919 /* GFX9: Flush DFSM when the AA mode changes. */
920 if (cmd_buffer->device->dfsm_allowed) {
921 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
922 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
923 }
924
925 cmd_buffer->state.context_roll_without_scissor_emitted = true;
926 }
927
928 static void
929 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
930 struct radv_pipeline *pipeline,
931 gl_shader_stage stage,
932 int idx, int count, uint32_t *values)
933 {
934 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
935 uint32_t base_reg = pipeline->user_data_0[stage];
936 if (loc->sgpr_idx == -1)
937 return;
938
939 assert(loc->num_sgprs == count);
940
941 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
942 radeon_emit_array(cmd_buffer->cs, values, count);
943 }
944
945 static void
946 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
947 struct radv_pipeline *pipeline)
948 {
949 int num_samples = pipeline->graphics.ms.num_samples;
950 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
951
952 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.needs_sample_positions)
953 cmd_buffer->sample_positions_needed = true;
954
955 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
956 return;
957
958 radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
959
960 cmd_buffer->state.context_roll_without_scissor_emitted = true;
961 }
962
963 static void
964 radv_update_binning_state(struct radv_cmd_buffer *cmd_buffer,
965 struct radv_pipeline *pipeline)
966 {
967 const struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
968
969
970 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
971 return;
972
973 if (old_pipeline &&
974 old_pipeline->graphics.binning.pa_sc_binner_cntl_0 == pipeline->graphics.binning.pa_sc_binner_cntl_0 &&
975 old_pipeline->graphics.binning.db_dfsm_control == pipeline->graphics.binning.db_dfsm_control)
976 return;
977
978 bool binning_flush = false;
979 if (cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA12 ||
980 cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA20 ||
981 cmd_buffer->device->physical_device->rad_info.family == CHIP_RAVEN2 ||
982 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
983 binning_flush = !old_pipeline ||
984 G_028C44_BINNING_MODE(old_pipeline->graphics.binning.pa_sc_binner_cntl_0) !=
985 G_028C44_BINNING_MODE(pipeline->graphics.binning.pa_sc_binner_cntl_0);
986 }
987
988 radeon_set_context_reg(cmd_buffer->cs, R_028C44_PA_SC_BINNER_CNTL_0,
989 pipeline->graphics.binning.pa_sc_binner_cntl_0 |
990 S_028C44_FLUSH_ON_BINNING_TRANSITION(!!binning_flush));
991
992 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
993 radeon_set_context_reg(cmd_buffer->cs, R_028038_DB_DFSM_CONTROL,
994 pipeline->graphics.binning.db_dfsm_control);
995 } else {
996 radeon_set_context_reg(cmd_buffer->cs, R_028060_DB_DFSM_CONTROL,
997 pipeline->graphics.binning.db_dfsm_control);
998 }
999
1000 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1001 }
1002
1003
1004 static void
1005 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
1006 struct radv_shader_variant *shader)
1007 {
1008 uint64_t va;
1009
1010 if (!shader)
1011 return;
1012
1013 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
1014
1015 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
1016 }
1017
1018 static void
1019 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
1020 struct radv_pipeline *pipeline,
1021 bool vertex_stage_only)
1022 {
1023 struct radv_cmd_state *state = &cmd_buffer->state;
1024 uint32_t mask = state->prefetch_L2_mask;
1025
1026 if (vertex_stage_only) {
1027 /* Fast prefetch path for starting draws as soon as possible.
1028 */
1029 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
1030 RADV_PREFETCH_VBO_DESCRIPTORS);
1031 }
1032
1033 if (mask & RADV_PREFETCH_VS)
1034 radv_emit_shader_prefetch(cmd_buffer,
1035 pipeline->shaders[MESA_SHADER_VERTEX]);
1036
1037 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
1038 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
1039
1040 if (mask & RADV_PREFETCH_TCS)
1041 radv_emit_shader_prefetch(cmd_buffer,
1042 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
1043
1044 if (mask & RADV_PREFETCH_TES)
1045 radv_emit_shader_prefetch(cmd_buffer,
1046 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
1047
1048 if (mask & RADV_PREFETCH_GS) {
1049 radv_emit_shader_prefetch(cmd_buffer,
1050 pipeline->shaders[MESA_SHADER_GEOMETRY]);
1051 if (radv_pipeline_has_gs_copy_shader(pipeline))
1052 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
1053 }
1054
1055 if (mask & RADV_PREFETCH_PS)
1056 radv_emit_shader_prefetch(cmd_buffer,
1057 pipeline->shaders[MESA_SHADER_FRAGMENT]);
1058
1059 state->prefetch_L2_mask &= ~mask;
1060 }
1061
1062 static void
1063 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
1064 {
1065 if (!cmd_buffer->device->physical_device->rad_info.rbplus_allowed)
1066 return;
1067
1068 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1069 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1070
1071 unsigned sx_ps_downconvert = 0;
1072 unsigned sx_blend_opt_epsilon = 0;
1073 unsigned sx_blend_opt_control = 0;
1074
1075 if (!cmd_buffer->state.attachments || !subpass)
1076 return;
1077
1078 for (unsigned i = 0; i < subpass->color_count; ++i) {
1079 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1080 /* We don't set the DISABLE bits, because the HW can't have holes,
1081 * so the SPI color format is set to 32-bit 1-component. */
1082 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1083 continue;
1084 }
1085
1086 int idx = subpass->color_attachments[i].attachment;
1087 struct radv_color_buffer_info *cb = &cmd_buffer->state.attachments[idx].cb;
1088
1089 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
1090 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
1091 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
1092 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
1093
1094 bool has_alpha, has_rgb;
1095
1096 /* Set if RGB and A are present. */
1097 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
1098
1099 if (format == V_028C70_COLOR_8 ||
1100 format == V_028C70_COLOR_16 ||
1101 format == V_028C70_COLOR_32)
1102 has_rgb = !has_alpha;
1103 else
1104 has_rgb = true;
1105
1106 /* Check the colormask and export format. */
1107 if (!(colormask & 0x7))
1108 has_rgb = false;
1109 if (!(colormask & 0x8))
1110 has_alpha = false;
1111
1112 if (spi_format == V_028714_SPI_SHADER_ZERO) {
1113 has_rgb = false;
1114 has_alpha = false;
1115 }
1116
1117 /* Disable value checking for disabled channels. */
1118 if (!has_rgb)
1119 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1120 if (!has_alpha)
1121 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1122
1123 /* Enable down-conversion for 32bpp and smaller formats. */
1124 switch (format) {
1125 case V_028C70_COLOR_8:
1126 case V_028C70_COLOR_8_8:
1127 case V_028C70_COLOR_8_8_8_8:
1128 /* For 1 and 2-channel formats, use the superset thereof. */
1129 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
1130 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1131 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1132 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
1133 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
1134 }
1135 break;
1136
1137 case V_028C70_COLOR_5_6_5:
1138 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1139 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
1140 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
1141 }
1142 break;
1143
1144 case V_028C70_COLOR_1_5_5_5:
1145 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1146 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
1147 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
1148 }
1149 break;
1150
1151 case V_028C70_COLOR_4_4_4_4:
1152 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1153 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
1154 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
1155 }
1156 break;
1157
1158 case V_028C70_COLOR_32:
1159 if (swap == V_028C70_SWAP_STD &&
1160 spi_format == V_028714_SPI_SHADER_32_R)
1161 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1162 else if (swap == V_028C70_SWAP_ALT_REV &&
1163 spi_format == V_028714_SPI_SHADER_32_AR)
1164 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
1165 break;
1166
1167 case V_028C70_COLOR_16:
1168 case V_028C70_COLOR_16_16:
1169 /* For 1-channel formats, use the superset thereof. */
1170 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
1171 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
1172 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1173 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1174 if (swap == V_028C70_SWAP_STD ||
1175 swap == V_028C70_SWAP_STD_REV)
1176 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
1177 else
1178 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
1179 }
1180 break;
1181
1182 case V_028C70_COLOR_10_11_11:
1183 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1184 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
1185 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
1186 }
1187 break;
1188
1189 case V_028C70_COLOR_2_10_10_10:
1190 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1191 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
1192 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
1193 }
1194 break;
1195 }
1196 }
1197
1198 /* Do not set the DISABLE bits for the unused attachments, as that
1199 * breaks dual source blending in SkQP and does not seem to improve
1200 * performance. */
1201
1202 if (sx_ps_downconvert == cmd_buffer->state.last_sx_ps_downconvert &&
1203 sx_blend_opt_epsilon == cmd_buffer->state.last_sx_blend_opt_epsilon &&
1204 sx_blend_opt_control == cmd_buffer->state.last_sx_blend_opt_control)
1205 return;
1206
1207 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
1208 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
1209 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
1210 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
1211
1212 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1213
1214 cmd_buffer->state.last_sx_ps_downconvert = sx_ps_downconvert;
1215 cmd_buffer->state.last_sx_blend_opt_epsilon = sx_blend_opt_epsilon;
1216 cmd_buffer->state.last_sx_blend_opt_control = sx_blend_opt_control;
1217 }
1218
1219 static void
1220 radv_emit_batch_break_on_new_ps(struct radv_cmd_buffer *cmd_buffer)
1221 {
1222 if (!cmd_buffer->device->pbb_allowed)
1223 return;
1224
1225 struct radv_binning_settings settings =
1226 radv_get_binning_settings(cmd_buffer->device->physical_device);
1227 bool break_for_new_ps =
1228 (!cmd_buffer->state.emitted_pipeline ||
1229 cmd_buffer->state.emitted_pipeline->shaders[MESA_SHADER_FRAGMENT] !=
1230 cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT]) &&
1231 (settings.context_states_per_bin > 1 ||
1232 settings.persistent_states_per_bin > 1);
1233 bool break_for_new_cb_target_mask =
1234 (!cmd_buffer->state.emitted_pipeline ||
1235 cmd_buffer->state.emitted_pipeline->graphics.cb_target_mask !=
1236 cmd_buffer->state.pipeline->graphics.cb_target_mask) &&
1237 settings.context_states_per_bin > 1;
1238
1239 if (!break_for_new_ps && !break_for_new_cb_target_mask)
1240 return;
1241
1242 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1243 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1244 }
1245
1246 static void
1247 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1248 {
1249 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1250
1251 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1252 return;
1253
1254 radv_update_multisample_state(cmd_buffer, pipeline);
1255 radv_update_binning_state(cmd_buffer, pipeline);
1256
1257 cmd_buffer->scratch_size_per_wave_needed = MAX2(cmd_buffer->scratch_size_per_wave_needed,
1258 pipeline->scratch_bytes_per_wave);
1259 cmd_buffer->scratch_waves_wanted = MAX2(cmd_buffer->scratch_waves_wanted,
1260 pipeline->max_waves);
1261
1262 if (!cmd_buffer->state.emitted_pipeline ||
1263 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1264 pipeline->graphics.can_use_guardband)
1265 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1266
1267 if (!cmd_buffer->state.emitted_pipeline ||
1268 cmd_buffer->state.emitted_pipeline->graphics.pa_su_sc_mode_cntl !=
1269 pipeline->graphics.pa_su_sc_mode_cntl)
1270 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_CULL_MODE |
1271 RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE;
1272
1273 if (!cmd_buffer->state.emitted_pipeline)
1274 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY;
1275
1276 if (!cmd_buffer->state.emitted_pipeline ||
1277 cmd_buffer->state.emitted_pipeline->graphics.db_depth_control !=
1278 pipeline->graphics.db_depth_control)
1279 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE |
1280 RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE |
1281 RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP |
1282 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE |
1283 RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE |
1284 RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP;
1285
1286 if (!cmd_buffer->state.emitted_pipeline)
1287 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP;
1288
1289 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
1290
1291 if (!cmd_buffer->state.emitted_pipeline ||
1292 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
1293 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
1294 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
1295 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
1296 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
1297 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1298 }
1299
1300 radv_emit_batch_break_on_new_ps(cmd_buffer);
1301
1302 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
1303 if (!pipeline->shaders[i])
1304 continue;
1305
1306 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1307 pipeline->shaders[i]->bo);
1308 }
1309
1310 if (radv_pipeline_has_gs_copy_shader(pipeline))
1311 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1312 pipeline->gs_copy_shader->bo);
1313
1314 if (unlikely(cmd_buffer->device->trace_bo))
1315 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1316
1317 cmd_buffer->state.emitted_pipeline = pipeline;
1318
1319 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1320 }
1321
1322 static void
1323 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1324 {
1325 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1326 cmd_buffer->state.dynamic.viewport.viewports);
1327 }
1328
1329 static void
1330 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1331 {
1332 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1333
1334 si_write_scissors(cmd_buffer->cs, 0, count,
1335 cmd_buffer->state.dynamic.scissor.scissors,
1336 cmd_buffer->state.dynamic.viewport.viewports,
1337 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1338
1339 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1340 }
1341
1342 static void
1343 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1344 {
1345 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1346 return;
1347
1348 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1349 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1350 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1351 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1352 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1353 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1354 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1355 }
1356 }
1357
1358 static void
1359 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1360 {
1361 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1362
1363 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1364 S_028A08_WIDTH(CLAMP(width, 0, 0xFFFF)));
1365 }
1366
1367 static void
1368 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1369 {
1370 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1371
1372 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1373 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1374 }
1375
1376 static void
1377 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1378 {
1379 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1380
1381 radeon_set_context_reg_seq(cmd_buffer->cs,
1382 R_028430_DB_STENCILREFMASK, 2);
1383 radeon_emit(cmd_buffer->cs,
1384 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1385 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1386 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1387 S_028430_STENCILOPVAL(1));
1388 radeon_emit(cmd_buffer->cs,
1389 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1390 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1391 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1392 S_028434_STENCILOPVAL_BF(1));
1393 }
1394
1395 static void
1396 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1397 {
1398 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1399
1400 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1401 fui(d->depth_bounds.min));
1402 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1403 fui(d->depth_bounds.max));
1404 }
1405
1406 static void
1407 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1408 {
1409 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1410 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1411 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1412
1413
1414 radeon_set_context_reg_seq(cmd_buffer->cs,
1415 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1416 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1417 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1418 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1419 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1420 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1421 }
1422
1423 static void
1424 radv_emit_line_stipple(struct radv_cmd_buffer *cmd_buffer)
1425 {
1426 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1427 uint32_t auto_reset_cntl = 1;
1428
1429 if (d->primitive_topology == V_008958_DI_PT_LINESTRIP)
1430 auto_reset_cntl = 2;
1431
1432 radeon_set_context_reg(cmd_buffer->cs, R_028A0C_PA_SC_LINE_STIPPLE,
1433 S_028A0C_LINE_PATTERN(d->line_stipple.pattern) |
1434 S_028A0C_REPEAT_COUNT(d->line_stipple.factor - 1) |
1435 S_028A0C_AUTO_RESET_CNTL(auto_reset_cntl));
1436 }
1437
1438 static void
1439 radv_emit_culling(struct radv_cmd_buffer *cmd_buffer, uint32_t states)
1440 {
1441 unsigned pa_su_sc_mode_cntl = cmd_buffer->state.pipeline->graphics.pa_su_sc_mode_cntl;
1442 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1443
1444 if (states & RADV_CMD_DIRTY_DYNAMIC_CULL_MODE) {
1445 pa_su_sc_mode_cntl &= C_028814_CULL_FRONT;
1446 pa_su_sc_mode_cntl |= S_028814_CULL_FRONT(!!(d->cull_mode & VK_CULL_MODE_FRONT_BIT));
1447
1448 pa_su_sc_mode_cntl &= C_028814_CULL_BACK;
1449 pa_su_sc_mode_cntl |= S_028814_CULL_BACK(!!(d->cull_mode & VK_CULL_MODE_BACK_BIT));
1450 }
1451
1452 if (states & RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE) {
1453 pa_su_sc_mode_cntl &= C_028814_FACE;
1454 pa_su_sc_mode_cntl |= S_028814_FACE(d->front_face);
1455 }
1456
1457 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
1458 pa_su_sc_mode_cntl);
1459 }
1460
1461 static void
1462 radv_emit_primitive_topology(struct radv_cmd_buffer *cmd_buffer)
1463 {
1464 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1465
1466 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1467 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
1468 cmd_buffer->cs,
1469 R_030908_VGT_PRIMITIVE_TYPE, 1,
1470 d->primitive_topology);
1471 } else {
1472 radeon_set_config_reg(cmd_buffer->cs,
1473 R_008958_VGT_PRIMITIVE_TYPE,
1474 d->primitive_topology);
1475 }
1476 }
1477
1478 static void
1479 radv_emit_depth_control(struct radv_cmd_buffer *cmd_buffer, uint32_t states)
1480 {
1481 unsigned db_depth_control = cmd_buffer->state.pipeline->graphics.db_depth_control;
1482 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1483
1484 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE) {
1485 db_depth_control &= C_028800_Z_ENABLE;
1486 db_depth_control |= S_028800_Z_ENABLE(d->depth_test_enable ? 1 : 0);
1487 }
1488
1489 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE) {
1490 db_depth_control &= C_028800_Z_WRITE_ENABLE;
1491 db_depth_control |= S_028800_Z_WRITE_ENABLE(d->depth_write_enable ? 1 : 0);
1492 }
1493
1494 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP) {
1495 db_depth_control &= C_028800_ZFUNC;
1496 db_depth_control |= S_028800_ZFUNC(d->depth_compare_op);
1497 }
1498
1499 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE) {
1500 db_depth_control &= C_028800_DEPTH_BOUNDS_ENABLE;
1501 db_depth_control |= S_028800_DEPTH_BOUNDS_ENABLE(d->depth_bounds_test_enable ? 1 : 0);
1502 }
1503
1504 if (states & RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE) {
1505 db_depth_control &= C_028800_STENCIL_ENABLE;
1506 db_depth_control |= S_028800_STENCIL_ENABLE(d->stencil_test_enable ? 1 : 0);
1507
1508 db_depth_control &= C_028800_BACKFACE_ENABLE;
1509 db_depth_control |= S_028800_BACKFACE_ENABLE(d->stencil_test_enable ? 1 : 0);
1510 }
1511
1512 if (states & RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP) {
1513 db_depth_control &= C_028800_STENCILFUNC;
1514 db_depth_control |= S_028800_STENCILFUNC(d->stencil_op.front.compare_op);
1515
1516 db_depth_control &= C_028800_STENCILFUNC_BF;
1517 db_depth_control |= S_028800_STENCILFUNC_BF(d->stencil_op.back.compare_op);
1518 }
1519
1520 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL,
1521 db_depth_control);
1522 }
1523
1524 static void
1525 radv_emit_stencil_control(struct radv_cmd_buffer *cmd_buffer)
1526 {
1527 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1528
1529 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL,
1530 S_02842C_STENCILFAIL(si_translate_stencil_op(d->stencil_op.front.fail_op)) |
1531 S_02842C_STENCILZPASS(si_translate_stencil_op(d->stencil_op.front.pass_op)) |
1532 S_02842C_STENCILZFAIL(si_translate_stencil_op(d->stencil_op.front.depth_fail_op)) |
1533 S_02842C_STENCILFAIL_BF(si_translate_stencil_op(d->stencil_op.back.fail_op)) |
1534 S_02842C_STENCILZPASS_BF(si_translate_stencil_op(d->stencil_op.back.pass_op)) |
1535 S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(d->stencil_op.back.depth_fail_op)));
1536 }
1537
1538 static void
1539 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1540 int index,
1541 struct radv_color_buffer_info *cb,
1542 struct radv_image_view *iview,
1543 VkImageLayout layout,
1544 bool in_render_loop)
1545 {
1546 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
1547 uint32_t cb_color_info = cb->cb_color_info;
1548 struct radv_image *image = iview->image;
1549
1550 if (!radv_layout_dcc_compressed(cmd_buffer->device, image, layout, in_render_loop,
1551 radv_image_queue_family_mask(image,
1552 cmd_buffer->queue_family_index,
1553 cmd_buffer->queue_family_index))) {
1554 cb_color_info &= C_028C70_DCC_ENABLE;
1555 }
1556
1557 if (!radv_layout_can_fast_clear(image, layout, in_render_loop,
1558 radv_image_queue_family_mask(image,
1559 cmd_buffer->queue_family_index,
1560 cmd_buffer->queue_family_index))) {
1561 cb_color_info &= C_028C70_COMPRESSION;
1562 }
1563
1564 if (radv_image_is_tc_compat_cmask(image) &&
1565 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1566 radv_is_dcc_decompress_pipeline(cmd_buffer))) {
1567 /* If this bit is set, the FMASK decompression operation
1568 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1569 */
1570 cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
1571 }
1572
1573 if (radv_image_has_fmask(image) &&
1574 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1575 radv_is_hw_resolve_pipeline(cmd_buffer))) {
1576 /* Make sure FMASK is enabled if it has been cleared because:
1577 *
1578 * 1) it's required for FMASK_DECOMPRESS operations to avoid
1579 * GPU hangs
1580 * 2) it's necessary for CB_RESOLVE which can read compressed
1581 * FMASK data anyways.
1582 */
1583 cb_color_info |= S_028C70_COMPRESSION(1);
1584 }
1585
1586 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1587 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1588 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1589 radeon_emit(cmd_buffer->cs, 0);
1590 radeon_emit(cmd_buffer->cs, 0);
1591 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1592 radeon_emit(cmd_buffer->cs, cb_color_info);
1593 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1594 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1595 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1596 radeon_emit(cmd_buffer->cs, 0);
1597 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1598 radeon_emit(cmd_buffer->cs, 0);
1599
1600 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 1);
1601 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1602
1603 radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4,
1604 cb->cb_color_base >> 32);
1605 radeon_set_context_reg(cmd_buffer->cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + index * 4,
1606 cb->cb_color_cmask >> 32);
1607 radeon_set_context_reg(cmd_buffer->cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + index * 4,
1608 cb->cb_color_fmask >> 32);
1609 radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4,
1610 cb->cb_dcc_base >> 32);
1611 radeon_set_context_reg(cmd_buffer->cs, R_028EC0_CB_COLOR0_ATTRIB2 + index * 4,
1612 cb->cb_color_attrib2);
1613 radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4,
1614 cb->cb_color_attrib3);
1615 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1616 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1617 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1618 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1619 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1620 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1621 radeon_emit(cmd_buffer->cs, cb_color_info);
1622 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1623 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1624 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1625 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1626 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1627 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1628
1629 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1630 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1631 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1632
1633 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1634 cb->cb_mrt_epitch);
1635 } else {
1636 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1637 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1638 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1639 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1640 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1641 radeon_emit(cmd_buffer->cs, cb_color_info);
1642 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1643 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1644 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1645 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1646 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1647 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1648
1649 if (is_vi) { /* DCC BASE */
1650 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1651 }
1652 }
1653
1654 if (radv_dcc_enabled(image, iview->base_mip)) {
1655 /* Drawing with DCC enabled also compresses colorbuffers. */
1656 VkImageSubresourceRange range = {
1657 .aspectMask = iview->aspect_mask,
1658 .baseMipLevel = iview->base_mip,
1659 .levelCount = iview->level_count,
1660 .baseArrayLayer = iview->base_layer,
1661 .layerCount = iview->layer_count,
1662 };
1663
1664 radv_update_dcc_metadata(cmd_buffer, image, &range, true);
1665 }
1666 }
1667
1668 static void
1669 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1670 struct radv_ds_buffer_info *ds,
1671 const struct radv_image_view *iview,
1672 VkImageLayout layout,
1673 bool in_render_loop, bool requires_cond_exec)
1674 {
1675 const struct radv_image *image = iview->image;
1676 uint32_t db_z_info = ds->db_z_info;
1677 uint32_t db_z_info_reg;
1678
1679 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug ||
1680 !radv_image_is_tc_compat_htile(image))
1681 return;
1682
1683 if (!radv_layout_is_htile_compressed(image, layout, in_render_loop,
1684 radv_image_queue_family_mask(image,
1685 cmd_buffer->queue_family_index,
1686 cmd_buffer->queue_family_index))) {
1687 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1688 }
1689
1690 db_z_info &= C_028040_ZRANGE_PRECISION;
1691
1692 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1693 db_z_info_reg = R_028038_DB_Z_INFO;
1694 } else {
1695 db_z_info_reg = R_028040_DB_Z_INFO;
1696 }
1697
1698 /* When we don't know the last fast clear value we need to emit a
1699 * conditional packet that will eventually skip the following
1700 * SET_CONTEXT_REG packet.
1701 */
1702 if (requires_cond_exec) {
1703 uint64_t va = radv_get_tc_compat_zrange_va(image, iview->base_mip);
1704
1705 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1706 radeon_emit(cmd_buffer->cs, va);
1707 radeon_emit(cmd_buffer->cs, va >> 32);
1708 radeon_emit(cmd_buffer->cs, 0);
1709 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1710 }
1711
1712 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1713 }
1714
1715 static void
1716 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1717 struct radv_ds_buffer_info *ds,
1718 struct radv_image_view *iview,
1719 VkImageLayout layout,
1720 bool in_render_loop)
1721 {
1722 const struct radv_image *image = iview->image;
1723 uint32_t db_z_info = ds->db_z_info;
1724 uint32_t db_stencil_info = ds->db_stencil_info;
1725
1726 if (!radv_layout_is_htile_compressed(image, layout, in_render_loop,
1727 radv_image_queue_family_mask(image,
1728 cmd_buffer->queue_family_index,
1729 cmd_buffer->queue_family_index))) {
1730 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1731 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1732 }
1733
1734 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1735 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1736
1737 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1738 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1739 radeon_set_context_reg(cmd_buffer->cs, R_02801C_DB_DEPTH_SIZE_XY, ds->db_depth_size);
1740
1741 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 7);
1742 radeon_emit(cmd_buffer->cs, S_02803C_RESOURCE_LEVEL(1));
1743 radeon_emit(cmd_buffer->cs, db_z_info);
1744 radeon_emit(cmd_buffer->cs, db_stencil_info);
1745 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1746 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1747 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1748 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1749
1750 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_READ_BASE_HI, 5);
1751 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1752 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1753 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1754 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1755 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1756 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1757 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1758 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1759 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1760 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1761
1762 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1763 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1764 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1765 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1766 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1767 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1768 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1769 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1770 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1771 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1772 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1773
1774 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1775 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1776 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1777 } else {
1778 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1779
1780 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1781 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1782 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1783 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1784 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1785 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1786 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1787 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1788 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1789 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1790
1791 }
1792
1793 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1794 radv_update_zrange_precision(cmd_buffer, ds, iview, layout,
1795 in_render_loop, true);
1796
1797 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1798 ds->pa_su_poly_offset_db_fmt_cntl);
1799 }
1800
1801 /**
1802 * Update the fast clear depth/stencil values if the image is bound as a
1803 * depth/stencil buffer.
1804 */
1805 static void
1806 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1807 const struct radv_image_view *iview,
1808 VkClearDepthStencilValue ds_clear_value,
1809 VkImageAspectFlags aspects)
1810 {
1811 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1812 const struct radv_image *image = iview->image;
1813 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1814 uint32_t att_idx;
1815
1816 if (!cmd_buffer->state.attachments || !subpass)
1817 return;
1818
1819 if (!subpass->depth_stencil_attachment)
1820 return;
1821
1822 att_idx = subpass->depth_stencil_attachment->attachment;
1823 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1824 return;
1825
1826 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1827 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1828 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1829 radeon_emit(cs, ds_clear_value.stencil);
1830 radeon_emit(cs, fui(ds_clear_value.depth));
1831 } else if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1832 radeon_set_context_reg_seq(cs, R_02802C_DB_DEPTH_CLEAR, 1);
1833 radeon_emit(cs, fui(ds_clear_value.depth));
1834 } else {
1835 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1836 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 1);
1837 radeon_emit(cs, ds_clear_value.stencil);
1838 }
1839
1840 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1841 * only needed when clearing Z to 0.0.
1842 */
1843 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1844 ds_clear_value.depth == 0.0) {
1845 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1846 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
1847
1848 radv_update_zrange_precision(cmd_buffer, &cmd_buffer->state.attachments[att_idx].ds,
1849 iview, layout, in_render_loop, false);
1850 }
1851
1852 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1853 }
1854
1855 /**
1856 * Set the clear depth/stencil values to the image's metadata.
1857 */
1858 static void
1859 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1860 struct radv_image *image,
1861 const VkImageSubresourceRange *range,
1862 VkClearDepthStencilValue ds_clear_value,
1863 VkImageAspectFlags aspects)
1864 {
1865 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1866 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel);
1867 uint32_t level_count = radv_get_levelCount(image, range);
1868
1869 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1870 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1871 /* Use the fastest way when both aspects are used. */
1872 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + 2 * level_count, cmd_buffer->state.predicating));
1873 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1874 S_370_WR_CONFIRM(1) |
1875 S_370_ENGINE_SEL(V_370_PFP));
1876 radeon_emit(cs, va);
1877 radeon_emit(cs, va >> 32);
1878
1879 for (uint32_t l = 0; l < level_count; l++) {
1880 radeon_emit(cs, ds_clear_value.stencil);
1881 radeon_emit(cs, fui(ds_clear_value.depth));
1882 }
1883 } else {
1884 /* Otherwise we need one WRITE_DATA packet per level. */
1885 for (uint32_t l = 0; l < level_count; l++) {
1886 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel + l);
1887 unsigned value;
1888
1889 if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1890 value = fui(ds_clear_value.depth);
1891 va += 4;
1892 } else {
1893 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1894 value = ds_clear_value.stencil;
1895 }
1896
1897 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1898 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1899 S_370_WR_CONFIRM(1) |
1900 S_370_ENGINE_SEL(V_370_PFP));
1901 radeon_emit(cs, va);
1902 radeon_emit(cs, va >> 32);
1903 radeon_emit(cs, value);
1904 }
1905 }
1906 }
1907
1908 /**
1909 * Update the TC-compat metadata value for this image.
1910 */
1911 static void
1912 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1913 struct radv_image *image,
1914 const VkImageSubresourceRange *range,
1915 uint32_t value)
1916 {
1917 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1918
1919 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug)
1920 return;
1921
1922 uint64_t va = radv_get_tc_compat_zrange_va(image, range->baseMipLevel);
1923 uint32_t level_count = radv_get_levelCount(image, range);
1924
1925 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + level_count, cmd_buffer->state.predicating));
1926 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1927 S_370_WR_CONFIRM(1) |
1928 S_370_ENGINE_SEL(V_370_PFP));
1929 radeon_emit(cs, va);
1930 radeon_emit(cs, va >> 32);
1931
1932 for (uint32_t l = 0; l < level_count; l++)
1933 radeon_emit(cs, value);
1934 }
1935
1936 static void
1937 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1938 const struct radv_image_view *iview,
1939 VkClearDepthStencilValue ds_clear_value)
1940 {
1941 VkImageSubresourceRange range = {
1942 .aspectMask = iview->aspect_mask,
1943 .baseMipLevel = iview->base_mip,
1944 .levelCount = iview->level_count,
1945 .baseArrayLayer = iview->base_layer,
1946 .layerCount = iview->layer_count,
1947 };
1948 uint32_t cond_val;
1949
1950 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1951 * depth clear value is 0.0f.
1952 */
1953 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1954
1955 radv_set_tc_compat_zrange_metadata(cmd_buffer, iview->image, &range,
1956 cond_val);
1957 }
1958
1959 /**
1960 * Update the clear depth/stencil values for this image.
1961 */
1962 void
1963 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1964 const struct radv_image_view *iview,
1965 VkClearDepthStencilValue ds_clear_value,
1966 VkImageAspectFlags aspects)
1967 {
1968 VkImageSubresourceRange range = {
1969 .aspectMask = iview->aspect_mask,
1970 .baseMipLevel = iview->base_mip,
1971 .levelCount = iview->level_count,
1972 .baseArrayLayer = iview->base_layer,
1973 .layerCount = iview->layer_count,
1974 };
1975 struct radv_image *image = iview->image;
1976
1977 assert(radv_image_has_htile(image));
1978
1979 radv_set_ds_clear_metadata(cmd_buffer, iview->image, &range,
1980 ds_clear_value, aspects);
1981
1982 if (radv_image_is_tc_compat_htile(image) &&
1983 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1984 radv_update_tc_compat_zrange_metadata(cmd_buffer, iview,
1985 ds_clear_value);
1986 }
1987
1988 radv_update_bound_fast_clear_ds(cmd_buffer, iview, ds_clear_value,
1989 aspects);
1990 }
1991
1992 /**
1993 * Load the clear depth/stencil values from the image's metadata.
1994 */
1995 static void
1996 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1997 const struct radv_image_view *iview)
1998 {
1999 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2000 const struct radv_image *image = iview->image;
2001 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
2002 uint64_t va = radv_get_ds_clear_value_va(image, iview->base_mip);
2003 unsigned reg_offset = 0, reg_count = 0;
2004
2005 if (!radv_image_has_htile(image))
2006 return;
2007
2008 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
2009 ++reg_count;
2010 } else {
2011 ++reg_offset;
2012 va += 4;
2013 }
2014 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
2015 ++reg_count;
2016
2017 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
2018
2019 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
2020 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG_INDEX, 3, 0));
2021 radeon_emit(cs, va);
2022 radeon_emit(cs, va >> 32);
2023 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
2024 radeon_emit(cs, reg_count);
2025 } else {
2026 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2027 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2028 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2029 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
2030 radeon_emit(cs, va);
2031 radeon_emit(cs, va >> 32);
2032 radeon_emit(cs, reg >> 2);
2033 radeon_emit(cs, 0);
2034
2035 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
2036 radeon_emit(cs, 0);
2037 }
2038 }
2039
2040 /*
2041 * With DCC some colors don't require CMASK elimination before being
2042 * used as a texture. This sets a predicate value to determine if the
2043 * cmask eliminate is required.
2044 */
2045 void
2046 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
2047 struct radv_image *image,
2048 const VkImageSubresourceRange *range, bool value)
2049 {
2050 uint64_t pred_val = value;
2051 uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
2052 uint32_t level_count = radv_get_levelCount(image, range);
2053 uint32_t count = 2 * level_count;
2054
2055 assert(radv_dcc_enabled(image, range->baseMipLevel));
2056
2057 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
2058 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
2059 S_370_WR_CONFIRM(1) |
2060 S_370_ENGINE_SEL(V_370_PFP));
2061 radeon_emit(cmd_buffer->cs, va);
2062 radeon_emit(cmd_buffer->cs, va >> 32);
2063
2064 for (uint32_t l = 0; l < level_count; l++) {
2065 radeon_emit(cmd_buffer->cs, pred_val);
2066 radeon_emit(cmd_buffer->cs, pred_val >> 32);
2067 }
2068 }
2069
2070 /**
2071 * Update the DCC predicate to reflect the compression state.
2072 */
2073 void
2074 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
2075 struct radv_image *image,
2076 const VkImageSubresourceRange *range, bool value)
2077 {
2078 uint64_t pred_val = value;
2079 uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
2080 uint32_t level_count = radv_get_levelCount(image, range);
2081 uint32_t count = 2 * level_count;
2082
2083 assert(radv_dcc_enabled(image, range->baseMipLevel));
2084
2085 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
2086 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
2087 S_370_WR_CONFIRM(1) |
2088 S_370_ENGINE_SEL(V_370_PFP));
2089 radeon_emit(cmd_buffer->cs, va);
2090 radeon_emit(cmd_buffer->cs, va >> 32);
2091
2092 for (uint32_t l = 0; l < level_count; l++) {
2093 radeon_emit(cmd_buffer->cs, pred_val);
2094 radeon_emit(cmd_buffer->cs, pred_val >> 32);
2095 }
2096 }
2097
2098 /**
2099 * Update the fast clear color values if the image is bound as a color buffer.
2100 */
2101 static void
2102 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
2103 struct radv_image *image,
2104 int cb_idx,
2105 uint32_t color_values[2])
2106 {
2107 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2108 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2109 uint32_t att_idx;
2110
2111 if (!cmd_buffer->state.attachments || !subpass)
2112 return;
2113
2114 att_idx = subpass->color_attachments[cb_idx].attachment;
2115 if (att_idx == VK_ATTACHMENT_UNUSED)
2116 return;
2117
2118 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
2119 return;
2120
2121 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
2122 radeon_emit(cs, color_values[0]);
2123 radeon_emit(cs, color_values[1]);
2124
2125 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2126 }
2127
2128 /**
2129 * Set the clear color values to the image's metadata.
2130 */
2131 static void
2132 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
2133 struct radv_image *image,
2134 const VkImageSubresourceRange *range,
2135 uint32_t color_values[2])
2136 {
2137 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2138 uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
2139 uint32_t level_count = radv_get_levelCount(image, range);
2140 uint32_t count = 2 * level_count;
2141
2142 assert(radv_image_has_cmask(image) ||
2143 radv_dcc_enabled(image, range->baseMipLevel));
2144
2145 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
2146 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
2147 S_370_WR_CONFIRM(1) |
2148 S_370_ENGINE_SEL(V_370_PFP));
2149 radeon_emit(cs, va);
2150 radeon_emit(cs, va >> 32);
2151
2152 for (uint32_t l = 0; l < level_count; l++) {
2153 radeon_emit(cs, color_values[0]);
2154 radeon_emit(cs, color_values[1]);
2155 }
2156 }
2157
2158 /**
2159 * Update the clear color values for this image.
2160 */
2161 void
2162 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
2163 const struct radv_image_view *iview,
2164 int cb_idx,
2165 uint32_t color_values[2])
2166 {
2167 struct radv_image *image = iview->image;
2168 VkImageSubresourceRange range = {
2169 .aspectMask = iview->aspect_mask,
2170 .baseMipLevel = iview->base_mip,
2171 .levelCount = iview->level_count,
2172 .baseArrayLayer = iview->base_layer,
2173 .layerCount = iview->layer_count,
2174 };
2175
2176 assert(radv_image_has_cmask(image) ||
2177 radv_dcc_enabled(image, iview->base_mip));
2178
2179 radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
2180
2181 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
2182 color_values);
2183 }
2184
2185 /**
2186 * Load the clear color values from the image's metadata.
2187 */
2188 static void
2189 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
2190 struct radv_image_view *iview,
2191 int cb_idx)
2192 {
2193 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2194 struct radv_image *image = iview->image;
2195 uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
2196
2197 if (!radv_image_has_cmask(image) &&
2198 !radv_dcc_enabled(image, iview->base_mip))
2199 return;
2200
2201 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
2202
2203 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
2204 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG_INDEX, 3, cmd_buffer->state.predicating));
2205 radeon_emit(cs, va);
2206 radeon_emit(cs, va >> 32);
2207 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
2208 radeon_emit(cs, 2);
2209 } else {
2210 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
2211 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2212 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2213 COPY_DATA_COUNT_SEL);
2214 radeon_emit(cs, va);
2215 radeon_emit(cs, va >> 32);
2216 radeon_emit(cs, reg >> 2);
2217 radeon_emit(cs, 0);
2218
2219 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
2220 radeon_emit(cs, 0);
2221 }
2222 }
2223
2224 static void
2225 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
2226 {
2227 int i;
2228 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
2229 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2230
2231 /* this may happen for inherited secondary recording */
2232 if (!framebuffer)
2233 return;
2234
2235 for (i = 0; i < 8; ++i) {
2236 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
2237 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2238 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2239 continue;
2240 }
2241
2242 int idx = subpass->color_attachments[i].attachment;
2243 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
2244 VkImageLayout layout = subpass->color_attachments[i].layout;
2245 bool in_render_loop = subpass->color_attachments[i].in_render_loop;
2246
2247 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, iview->bo);
2248
2249 assert(iview->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
2250 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
2251 radv_emit_fb_color_state(cmd_buffer, i, &cmd_buffer->state.attachments[idx].cb, iview, layout, in_render_loop);
2252
2253 radv_load_color_clear_metadata(cmd_buffer, iview, i);
2254 }
2255
2256 if (subpass->depth_stencil_attachment) {
2257 int idx = subpass->depth_stencil_attachment->attachment;
2258 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
2259 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
2260 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
2261 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, cmd_buffer->state.attachments[idx].iview->bo);
2262
2263 radv_emit_fb_ds_state(cmd_buffer, &cmd_buffer->state.attachments[idx].ds, iview, layout, in_render_loop);
2264
2265 if (cmd_buffer->state.attachments[idx].ds.offset_scale != cmd_buffer->state.offset_scale) {
2266 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2267 cmd_buffer->state.offset_scale = cmd_buffer->state.attachments[idx].ds.offset_scale;
2268 }
2269 radv_load_ds_clear_metadata(cmd_buffer, iview);
2270 } else {
2271 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9)
2272 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
2273 else
2274 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
2275
2276 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
2277 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
2278 }
2279 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2280 S_028208_BR_X(framebuffer->width) |
2281 S_028208_BR_Y(framebuffer->height));
2282
2283 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
2284 bool disable_constant_encode =
2285 cmd_buffer->device->physical_device->rad_info.has_dcc_constant_encode;
2286 enum chip_class chip_class =
2287 cmd_buffer->device->physical_device->rad_info.chip_class;
2288 uint8_t watermark = chip_class >= GFX10 ? 6 : 4;
2289
2290 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
2291 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class <= GFX9) |
2292 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
2293 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
2294 }
2295
2296 if (cmd_buffer->device->dfsm_allowed) {
2297 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2298 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
2299 }
2300
2301 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
2302 }
2303
2304 static void
2305 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer, bool indirect)
2306 {
2307 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2308 struct radv_cmd_state *state = &cmd_buffer->state;
2309
2310 if (state->index_type != state->last_index_type) {
2311 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2312 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2313 cs, R_03090C_VGT_INDEX_TYPE,
2314 2, state->index_type);
2315 } else {
2316 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2317 radeon_emit(cs, state->index_type);
2318 }
2319
2320 state->last_index_type = state->index_type;
2321 }
2322
2323 /* For the direct indexed draws we use DRAW_INDEX_2, which includes
2324 * the index_va and max_index_count already. */
2325 if (!indirect)
2326 return;
2327
2328 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2329 radeon_emit(cs, state->index_va);
2330 radeon_emit(cs, state->index_va >> 32);
2331
2332 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2333 radeon_emit(cs, state->max_index_count);
2334
2335 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
2336 }
2337
2338 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
2339 {
2340 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
2341 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2342 uint32_t pa_sc_mode_cntl_1 =
2343 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
2344 uint32_t db_count_control;
2345
2346 if(!cmd_buffer->state.active_occlusion_queries) {
2347 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2348 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2349 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2350 has_perfect_queries) {
2351 /* Re-enable out-of-order rasterization if the
2352 * bound pipeline supports it and if it's has
2353 * been disabled before starting any perfect
2354 * occlusion queries.
2355 */
2356 radeon_set_context_reg(cmd_buffer->cs,
2357 R_028A4C_PA_SC_MODE_CNTL_1,
2358 pa_sc_mode_cntl_1);
2359 }
2360 }
2361 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
2362 } else {
2363 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2364 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
2365 bool gfx10_perfect = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10 && has_perfect_queries;
2366
2367 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2368 /* Always enable PERFECT_ZPASS_COUNTS due to issues with partially
2369 * covered tiles, discards, and early depth testing. For more details,
2370 * see https://gitlab.freedesktop.org/mesa/mesa/-/issues/3218 */
2371 db_count_control =
2372 S_028004_PERFECT_ZPASS_COUNTS(1) |
2373 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
2374 S_028004_SAMPLE_RATE(sample_rate) |
2375 S_028004_ZPASS_ENABLE(1) |
2376 S_028004_SLICE_EVEN_ENABLE(1) |
2377 S_028004_SLICE_ODD_ENABLE(1);
2378
2379 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2380 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2381 has_perfect_queries) {
2382 /* If the bound pipeline has enabled
2383 * out-of-order rasterization, we should
2384 * disable it before starting any perfect
2385 * occlusion queries.
2386 */
2387 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
2388
2389 radeon_set_context_reg(cmd_buffer->cs,
2390 R_028A4C_PA_SC_MODE_CNTL_1,
2391 pa_sc_mode_cntl_1);
2392 }
2393 } else {
2394 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
2395 S_028004_SAMPLE_RATE(sample_rate);
2396 }
2397 }
2398
2399 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
2400
2401 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2402 }
2403
2404 static void
2405 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
2406 {
2407 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
2408
2409 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
2410 radv_emit_viewport(cmd_buffer);
2411
2412 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
2413 !cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
2414 radv_emit_scissor(cmd_buffer);
2415
2416 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
2417 radv_emit_line_width(cmd_buffer);
2418
2419 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
2420 radv_emit_blend_constants(cmd_buffer);
2421
2422 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
2423 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
2424 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
2425 radv_emit_stencil(cmd_buffer);
2426
2427 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
2428 radv_emit_depth_bounds(cmd_buffer);
2429
2430 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
2431 radv_emit_depth_bias(cmd_buffer);
2432
2433 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
2434 radv_emit_discard_rectangle(cmd_buffer);
2435
2436 if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)
2437 radv_emit_sample_locations(cmd_buffer);
2438
2439 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE)
2440 radv_emit_line_stipple(cmd_buffer);
2441
2442 if (states & (RADV_CMD_DIRTY_DYNAMIC_CULL_MODE |
2443 RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE))
2444 radv_emit_culling(cmd_buffer, states);
2445
2446 if (states & RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY)
2447 radv_emit_primitive_topology(cmd_buffer);
2448
2449 if (states & (RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE |
2450 RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE |
2451 RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP |
2452 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE |
2453 RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE |
2454 RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP))
2455 radv_emit_depth_control(cmd_buffer, states);
2456
2457 if (states & RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP)
2458 radv_emit_stencil_control(cmd_buffer);
2459
2460 cmd_buffer->state.dirty &= ~states;
2461 }
2462
2463 static void
2464 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
2465 VkPipelineBindPoint bind_point)
2466 {
2467 struct radv_descriptor_state *descriptors_state =
2468 radv_get_descriptors_state(cmd_buffer, bind_point);
2469 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
2470 unsigned bo_offset;
2471
2472 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
2473 set->mapped_ptr,
2474 &bo_offset))
2475 return;
2476
2477 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2478 set->va += bo_offset;
2479 }
2480
2481 static void
2482 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
2483 VkPipelineBindPoint bind_point)
2484 {
2485 struct radv_descriptor_state *descriptors_state =
2486 radv_get_descriptors_state(cmd_buffer, bind_point);
2487 uint32_t size = MAX_SETS * 4;
2488 uint32_t offset;
2489 void *ptr;
2490
2491 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
2492 256, &offset, &ptr))
2493 return;
2494
2495 for (unsigned i = 0; i < MAX_SETS; i++) {
2496 uint32_t *uptr = ((uint32_t *)ptr) + i;
2497 uint64_t set_va = 0;
2498 struct radv_descriptor_set *set = descriptors_state->sets[i];
2499 if (descriptors_state->valid & (1u << i))
2500 set_va = set->va;
2501 uptr[0] = set_va & 0xffffffff;
2502 }
2503
2504 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2505 va += offset;
2506
2507 if (cmd_buffer->state.pipeline) {
2508 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
2509 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2510 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2511
2512 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
2513 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
2514 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2515
2516 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
2517 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2518 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2519
2520 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2521 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
2522 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2523
2524 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2525 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
2526 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2527 }
2528
2529 if (cmd_buffer->state.compute_pipeline)
2530 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
2531 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2532 }
2533
2534 static void
2535 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
2536 VkShaderStageFlags stages)
2537 {
2538 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2539 VK_PIPELINE_BIND_POINT_COMPUTE :
2540 VK_PIPELINE_BIND_POINT_GRAPHICS;
2541 struct radv_descriptor_state *descriptors_state =
2542 radv_get_descriptors_state(cmd_buffer, bind_point);
2543 struct radv_cmd_state *state = &cmd_buffer->state;
2544 bool flush_indirect_descriptors;
2545
2546 if (!descriptors_state->dirty)
2547 return;
2548
2549 if (descriptors_state->push_dirty)
2550 radv_flush_push_descriptors(cmd_buffer, bind_point);
2551
2552 flush_indirect_descriptors =
2553 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
2554 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
2555 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
2556 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
2557
2558 if (flush_indirect_descriptors)
2559 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
2560
2561 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2562 cmd_buffer->cs,
2563 MAX_SETS * MESA_SHADER_STAGES * 4);
2564
2565 if (cmd_buffer->state.pipeline) {
2566 radv_foreach_stage(stage, stages) {
2567 if (!cmd_buffer->state.pipeline->shaders[stage])
2568 continue;
2569
2570 radv_emit_descriptor_pointers(cmd_buffer,
2571 cmd_buffer->state.pipeline,
2572 descriptors_state, stage);
2573 }
2574 }
2575
2576 if (cmd_buffer->state.compute_pipeline &&
2577 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
2578 radv_emit_descriptor_pointers(cmd_buffer,
2579 cmd_buffer->state.compute_pipeline,
2580 descriptors_state,
2581 MESA_SHADER_COMPUTE);
2582 }
2583
2584 descriptors_state->dirty = 0;
2585 descriptors_state->push_dirty = false;
2586
2587 assert(cmd_buffer->cs->cdw <= cdw_max);
2588
2589 if (unlikely(cmd_buffer->device->trace_bo))
2590 radv_save_descriptors(cmd_buffer, bind_point);
2591 }
2592
2593 static void
2594 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
2595 VkShaderStageFlags stages)
2596 {
2597 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
2598 ? cmd_buffer->state.compute_pipeline
2599 : cmd_buffer->state.pipeline;
2600 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2601 VK_PIPELINE_BIND_POINT_COMPUTE :
2602 VK_PIPELINE_BIND_POINT_GRAPHICS;
2603 struct radv_descriptor_state *descriptors_state =
2604 radv_get_descriptors_state(cmd_buffer, bind_point);
2605 struct radv_pipeline_layout *layout = pipeline->layout;
2606 struct radv_shader_variant *shader, *prev_shader;
2607 bool need_push_constants = false;
2608 unsigned offset;
2609 void *ptr;
2610 uint64_t va;
2611
2612 stages &= cmd_buffer->push_constant_stages;
2613 if (!stages ||
2614 (!layout->push_constant_size && !layout->dynamic_offset_count))
2615 return;
2616
2617 radv_foreach_stage(stage, stages) {
2618 shader = radv_get_shader(pipeline, stage);
2619 if (!shader)
2620 continue;
2621
2622 need_push_constants |= shader->info.loads_push_constants;
2623 need_push_constants |= shader->info.loads_dynamic_offsets;
2624
2625 uint8_t base = shader->info.base_inline_push_consts;
2626 uint8_t count = shader->info.num_inline_push_consts;
2627
2628 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
2629 AC_UD_INLINE_PUSH_CONSTANTS,
2630 count,
2631 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
2632 }
2633
2634 if (need_push_constants) {
2635 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
2636 16 * layout->dynamic_offset_count,
2637 256, &offset, &ptr))
2638 return;
2639
2640 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
2641 memcpy((char*)ptr + layout->push_constant_size,
2642 descriptors_state->dynamic_buffers,
2643 16 * layout->dynamic_offset_count);
2644
2645 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2646 va += offset;
2647
2648 ASSERTED unsigned cdw_max =
2649 radeon_check_space(cmd_buffer->device->ws,
2650 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
2651
2652 prev_shader = NULL;
2653 radv_foreach_stage(stage, stages) {
2654 shader = radv_get_shader(pipeline, stage);
2655
2656 /* Avoid redundantly emitting the address for merged stages. */
2657 if (shader && shader != prev_shader) {
2658 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
2659 AC_UD_PUSH_CONSTANTS, va);
2660
2661 prev_shader = shader;
2662 }
2663 }
2664 assert(cmd_buffer->cs->cdw <= cdw_max);
2665 }
2666
2667 cmd_buffer->push_constant_stages &= ~stages;
2668 }
2669
2670 static void
2671 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
2672 bool pipeline_is_dirty)
2673 {
2674 if ((pipeline_is_dirty ||
2675 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
2676 cmd_buffer->state.pipeline->num_vertex_bindings &&
2677 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.has_vertex_buffers) {
2678 unsigned vb_offset;
2679 void *vb_ptr;
2680 uint32_t i = 0;
2681 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
2682 uint64_t va;
2683
2684 /* allocate some descriptor state for vertex buffers */
2685 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2686 &vb_offset, &vb_ptr))
2687 return;
2688
2689 for (i = 0; i < count; i++) {
2690 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2691 uint32_t offset;
2692 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2693 unsigned num_records;
2694 unsigned stride;
2695
2696 if (!buffer)
2697 continue;
2698
2699 va = radv_buffer_get_va(buffer->bo);
2700
2701 offset = cmd_buffer->vertex_bindings[i].offset;
2702 va += offset + buffer->offset;
2703
2704 if (cmd_buffer->vertex_bindings[i].size) {
2705 num_records = cmd_buffer->vertex_bindings[i].size;
2706 } else {
2707 num_records = buffer->size - offset;
2708 }
2709
2710 if (cmd_buffer->state.pipeline->graphics.uses_dynamic_stride) {
2711 stride = cmd_buffer->vertex_bindings[i].stride;
2712 } else {
2713 stride = cmd_buffer->state.pipeline->binding_stride[i];
2714 }
2715
2716 if (cmd_buffer->device->physical_device->rad_info.chip_class != GFX8 && stride)
2717 num_records /= stride;
2718
2719 uint32_t rsrc_word3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2720 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2721 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2722 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2723
2724 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2725 /* OOB_SELECT chooses the out-of-bounds check:
2726 * - 1: index >= NUM_RECORDS (Structured)
2727 * - 3: offset >= NUM_RECORDS (Raw)
2728 */
2729 int oob_select = stride ? V_008F0C_OOB_SELECT_STRUCTURED : V_008F0C_OOB_SELECT_RAW;
2730
2731 rsrc_word3 |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT) |
2732 S_008F0C_OOB_SELECT(oob_select) |
2733 S_008F0C_RESOURCE_LEVEL(1);
2734 } else {
2735 rsrc_word3 |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2736 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2737 }
2738
2739 desc[0] = va;
2740 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2741 desc[2] = num_records;
2742 desc[3] = rsrc_word3;
2743 }
2744
2745 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2746 va += vb_offset;
2747
2748 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2749 AC_UD_VS_VERTEX_BUFFERS, va);
2750
2751 cmd_buffer->state.vb_va = va;
2752 cmd_buffer->state.vb_size = count * 16;
2753 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2754 }
2755 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2756 }
2757
2758 static void
2759 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2760 {
2761 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2762 struct radv_userdata_info *loc;
2763 uint32_t base_reg;
2764
2765 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2766 if (!radv_get_shader(pipeline, stage))
2767 continue;
2768
2769 loc = radv_lookup_user_sgpr(pipeline, stage,
2770 AC_UD_STREAMOUT_BUFFERS);
2771 if (loc->sgpr_idx == -1)
2772 continue;
2773
2774 base_reg = pipeline->user_data_0[stage];
2775
2776 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2777 base_reg + loc->sgpr_idx * 4, va, false);
2778 }
2779
2780 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
2781 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2782 if (loc->sgpr_idx != -1) {
2783 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2784
2785 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2786 base_reg + loc->sgpr_idx * 4, va, false);
2787 }
2788 }
2789 }
2790
2791 static void
2792 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2793 {
2794 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2795 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2796 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2797 unsigned so_offset;
2798 void *so_ptr;
2799 uint64_t va;
2800
2801 /* Allocate some descriptor state for streamout buffers. */
2802 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2803 MAX_SO_BUFFERS * 16, 256,
2804 &so_offset, &so_ptr))
2805 return;
2806
2807 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2808 struct radv_buffer *buffer = sb[i].buffer;
2809 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2810
2811 if (!(so->enabled_mask & (1 << i)))
2812 continue;
2813
2814 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2815
2816 va += sb[i].offset;
2817
2818 /* Set the descriptor.
2819 *
2820 * On GFX8, the format must be non-INVALID, otherwise
2821 * the buffer will be considered not bound and store
2822 * instructions will be no-ops.
2823 */
2824 uint32_t size = 0xffffffff;
2825
2826 /* Compute the correct buffer size for NGG streamout
2827 * because it's used to determine the max emit per
2828 * buffer.
2829 */
2830 if (cmd_buffer->device->physical_device->use_ngg_streamout)
2831 size = buffer->size - sb[i].offset;
2832
2833 uint32_t rsrc_word3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2834 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2835 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2836 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2837
2838 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2839 rsrc_word3 |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2840 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
2841 S_008F0C_RESOURCE_LEVEL(1);
2842 } else {
2843 rsrc_word3 |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2844 }
2845
2846 desc[0] = va;
2847 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2848 desc[2] = size;
2849 desc[3] = rsrc_word3;
2850 }
2851
2852 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2853 va += so_offset;
2854
2855 radv_emit_streamout_buffers(cmd_buffer, va);
2856 }
2857
2858 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2859 }
2860
2861 static void
2862 radv_flush_ngg_gs_state(struct radv_cmd_buffer *cmd_buffer)
2863 {
2864 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2865 struct radv_userdata_info *loc;
2866 uint32_t ngg_gs_state = 0;
2867 uint32_t base_reg;
2868
2869 if (!radv_pipeline_has_gs(pipeline) ||
2870 !radv_pipeline_has_ngg(pipeline))
2871 return;
2872
2873 /* By default NGG GS queries are disabled but they are enabled if the
2874 * command buffer has active GDS queries or if it's a secondary command
2875 * buffer that inherits the number of generated primitives.
2876 */
2877 if (cmd_buffer->state.active_pipeline_gds_queries ||
2878 (cmd_buffer->state.inherited_pipeline_statistics & VK_QUERY_PIPELINE_STATISTIC_GEOMETRY_SHADER_PRIMITIVES_BIT))
2879 ngg_gs_state = 1;
2880
2881 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_GEOMETRY,
2882 AC_UD_NGG_GS_STATE);
2883 base_reg = pipeline->user_data_0[MESA_SHADER_GEOMETRY];
2884 assert(loc->sgpr_idx != -1);
2885
2886 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
2887 ngg_gs_state);
2888 }
2889
2890 static void
2891 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2892 {
2893 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2894 radv_flush_streamout_descriptors(cmd_buffer);
2895 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2896 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2897 radv_flush_ngg_gs_state(cmd_buffer);
2898 }
2899
2900 struct radv_draw_info {
2901 /**
2902 * Number of vertices.
2903 */
2904 uint32_t count;
2905
2906 /**
2907 * Index of the first vertex.
2908 */
2909 int32_t vertex_offset;
2910
2911 /**
2912 * First instance id.
2913 */
2914 uint32_t first_instance;
2915
2916 /**
2917 * Number of instances.
2918 */
2919 uint32_t instance_count;
2920
2921 /**
2922 * First index (indexed draws only).
2923 */
2924 uint32_t first_index;
2925
2926 /**
2927 * Whether it's an indexed draw.
2928 */
2929 bool indexed;
2930
2931 /**
2932 * Indirect draw parameters resource.
2933 */
2934 struct radv_buffer *indirect;
2935 uint64_t indirect_offset;
2936 uint32_t stride;
2937
2938 /**
2939 * Draw count parameters resource.
2940 */
2941 struct radv_buffer *count_buffer;
2942 uint64_t count_buffer_offset;
2943
2944 /**
2945 * Stream output parameters resource.
2946 */
2947 struct radv_buffer *strmout_buffer;
2948 uint64_t strmout_buffer_offset;
2949 };
2950
2951 static uint32_t
2952 radv_get_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
2953 {
2954 switch (cmd_buffer->state.index_type) {
2955 case V_028A7C_VGT_INDEX_8:
2956 return 0xffu;
2957 case V_028A7C_VGT_INDEX_16:
2958 return 0xffffu;
2959 case V_028A7C_VGT_INDEX_32:
2960 return 0xffffffffu;
2961 default:
2962 unreachable("invalid index type");
2963 }
2964 }
2965
2966 static void
2967 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
2968 bool instanced_draw, bool indirect_draw,
2969 bool count_from_stream_output,
2970 uint32_t draw_vertex_count)
2971 {
2972 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2973 struct radv_cmd_state *state = &cmd_buffer->state;
2974 unsigned topology = state->dynamic.primitive_topology;
2975 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2976 unsigned ia_multi_vgt_param;
2977
2978 ia_multi_vgt_param =
2979 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
2980 indirect_draw,
2981 count_from_stream_output,
2982 draw_vertex_count,
2983 topology);
2984
2985 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2986 if (info->chip_class == GFX9) {
2987 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2988 cs,
2989 R_030960_IA_MULTI_VGT_PARAM,
2990 4, ia_multi_vgt_param);
2991 } else if (info->chip_class >= GFX7) {
2992 radeon_set_context_reg_idx(cs,
2993 R_028AA8_IA_MULTI_VGT_PARAM,
2994 1, ia_multi_vgt_param);
2995 } else {
2996 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2997 ia_multi_vgt_param);
2998 }
2999 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
3000 }
3001 }
3002
3003 static void
3004 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
3005 const struct radv_draw_info *draw_info)
3006 {
3007 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
3008 struct radv_cmd_state *state = &cmd_buffer->state;
3009 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3010 int32_t primitive_reset_en;
3011
3012 /* Draw state. */
3013 if (info->chip_class < GFX10) {
3014 si_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
3015 draw_info->indirect,
3016 !!draw_info->strmout_buffer,
3017 draw_info->indirect ? 0 : draw_info->count);
3018 }
3019
3020 /* Primitive restart. */
3021 primitive_reset_en =
3022 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
3023
3024 if (primitive_reset_en != state->last_primitive_reset_en) {
3025 state->last_primitive_reset_en = primitive_reset_en;
3026 if (info->chip_class >= GFX9) {
3027 radeon_set_uconfig_reg(cs,
3028 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
3029 primitive_reset_en);
3030 } else {
3031 radeon_set_context_reg(cs,
3032 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
3033 primitive_reset_en);
3034 }
3035 }
3036
3037 if (primitive_reset_en) {
3038 uint32_t primitive_reset_index =
3039 radv_get_primitive_reset_index(cmd_buffer);
3040
3041 if (primitive_reset_index != state->last_primitive_reset_index) {
3042 radeon_set_context_reg(cs,
3043 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
3044 primitive_reset_index);
3045 state->last_primitive_reset_index = primitive_reset_index;
3046 }
3047 }
3048
3049 if (draw_info->strmout_buffer) {
3050 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
3051
3052 va += draw_info->strmout_buffer->offset +
3053 draw_info->strmout_buffer_offset;
3054
3055 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
3056 draw_info->stride);
3057
3058 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3059 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
3060 COPY_DATA_DST_SEL(COPY_DATA_REG) |
3061 COPY_DATA_WR_CONFIRM);
3062 radeon_emit(cs, va);
3063 radeon_emit(cs, va >> 32);
3064 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
3065 radeon_emit(cs, 0); /* unused */
3066
3067 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
3068 }
3069 }
3070
3071 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
3072 VkPipelineStageFlags src_stage_mask)
3073 {
3074 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
3075 VK_PIPELINE_STAGE_TRANSFER_BIT |
3076 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
3077 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
3078 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
3079 }
3080
3081 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
3082 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
3083 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
3084 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
3085 VK_PIPELINE_STAGE_TRANSFER_BIT |
3086 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
3087 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
3088 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
3089 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
3090 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
3091 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
3092 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
3093 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
3094 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
3095 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
3096 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
3097 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
3098 }
3099 }
3100
3101 static enum radv_cmd_flush_bits
3102 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
3103 VkAccessFlags src_flags,
3104 struct radv_image *image)
3105 {
3106 bool flush_CB_meta = true, flush_DB_meta = true;
3107 enum radv_cmd_flush_bits flush_bits = 0;
3108 uint32_t b;
3109
3110 if (image) {
3111 if (!radv_image_has_CB_metadata(image))
3112 flush_CB_meta = false;
3113 if (!radv_image_has_htile(image))
3114 flush_DB_meta = false;
3115 }
3116
3117 for_each_bit(b, src_flags) {
3118 switch ((VkAccessFlagBits)(1 << b)) {
3119 case VK_ACCESS_SHADER_WRITE_BIT:
3120 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
3121 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
3122 flush_bits |= RADV_CMD_FLAG_WB_L2;
3123 break;
3124 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
3125 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
3126 if (flush_CB_meta)
3127 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3128 break;
3129 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
3130 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
3131 if (flush_DB_meta)
3132 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3133 break;
3134 case VK_ACCESS_TRANSFER_WRITE_BIT:
3135 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3136 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3137 RADV_CMD_FLAG_INV_L2;
3138
3139 if (flush_CB_meta)
3140 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3141 if (flush_DB_meta)
3142 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3143 break;
3144 case VK_ACCESS_MEMORY_WRITE_BIT:
3145 flush_bits |= RADV_CMD_FLAG_INV_L2 |
3146 RADV_CMD_FLAG_WB_L2 |
3147 RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3148 RADV_CMD_FLAG_FLUSH_AND_INV_DB;
3149
3150 if (flush_CB_meta)
3151 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3152 if (flush_DB_meta)
3153 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3154 break;
3155 default:
3156 break;
3157 }
3158 }
3159 return flush_bits;
3160 }
3161
3162 static enum radv_cmd_flush_bits
3163 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
3164 VkAccessFlags dst_flags,
3165 struct radv_image *image)
3166 {
3167 bool flush_CB_meta = true, flush_DB_meta = true;
3168 enum radv_cmd_flush_bits flush_bits = 0;
3169 bool flush_CB = true, flush_DB = true;
3170 bool image_is_coherent = false;
3171 uint32_t b;
3172
3173 if (image) {
3174 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
3175 flush_CB = false;
3176 flush_DB = false;
3177 }
3178
3179 if (!radv_image_has_CB_metadata(image))
3180 flush_CB_meta = false;
3181 if (!radv_image_has_htile(image))
3182 flush_DB_meta = false;
3183
3184 /* TODO: implement shader coherent for GFX10 */
3185
3186 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
3187 if (image->info.samples == 1 &&
3188 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
3189 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
3190 !vk_format_is_stencil(image->vk_format)) {
3191 /* Single-sample color and single-sample depth
3192 * (not stencil) are coherent with shaders on
3193 * GFX9.
3194 */
3195 image_is_coherent = true;
3196 }
3197 }
3198 }
3199
3200 for_each_bit(b, dst_flags) {
3201 switch ((VkAccessFlagBits)(1 << b)) {
3202 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
3203 case VK_ACCESS_INDEX_READ_BIT:
3204 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
3205 break;
3206 case VK_ACCESS_UNIFORM_READ_BIT:
3207 flush_bits |= RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_SCACHE;
3208 break;
3209 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
3210 case VK_ACCESS_TRANSFER_READ_BIT:
3211 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
3212 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
3213 RADV_CMD_FLAG_INV_L2;
3214 break;
3215 case VK_ACCESS_SHADER_READ_BIT:
3216 flush_bits |= RADV_CMD_FLAG_INV_VCACHE;
3217 /* Unlike LLVM, ACO uses SMEM for SSBOs and we have to
3218 * invalidate the scalar cache. */
3219 if (!cmd_buffer->device->physical_device->use_llvm)
3220 flush_bits |= RADV_CMD_FLAG_INV_SCACHE;
3221
3222 if (!image_is_coherent)
3223 flush_bits |= RADV_CMD_FLAG_INV_L2;
3224 break;
3225 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
3226 if (flush_CB)
3227 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
3228 if (flush_CB_meta)
3229 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3230 break;
3231 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
3232 if (flush_DB)
3233 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
3234 if (flush_DB_meta)
3235 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3236 break;
3237 case VK_ACCESS_MEMORY_READ_BIT:
3238 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
3239 RADV_CMD_FLAG_INV_SCACHE |
3240 RADV_CMD_FLAG_INV_L2;
3241 if (flush_CB)
3242 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
3243 if (flush_CB_meta)
3244 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3245 if (flush_DB)
3246 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
3247 if (flush_DB_meta)
3248 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3249 break;
3250 default:
3251 break;
3252 }
3253 }
3254 return flush_bits;
3255 }
3256
3257 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
3258 const struct radv_subpass_barrier *barrier)
3259 {
3260 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
3261 NULL);
3262 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
3263 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
3264 NULL);
3265 }
3266
3267 uint32_t
3268 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
3269 {
3270 struct radv_cmd_state *state = &cmd_buffer->state;
3271 uint32_t subpass_id = state->subpass - state->pass->subpasses;
3272
3273 /* The id of this subpass shouldn't exceed the number of subpasses in
3274 * this render pass minus 1.
3275 */
3276 assert(subpass_id < state->pass->subpass_count);
3277 return subpass_id;
3278 }
3279
3280 static struct radv_sample_locations_state *
3281 radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer,
3282 uint32_t att_idx,
3283 bool begin_subpass)
3284 {
3285 struct radv_cmd_state *state = &cmd_buffer->state;
3286 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
3287 struct radv_image_view *view = state->attachments[att_idx].iview;
3288
3289 if (view->image->info.samples == 1)
3290 return NULL;
3291
3292 if (state->pass->attachments[att_idx].first_subpass_idx == subpass_id) {
3293 /* Return the initial sample locations if this is the initial
3294 * layout transition of the given subpass attachemnt.
3295 */
3296 if (state->attachments[att_idx].sample_location.count > 0)
3297 return &state->attachments[att_idx].sample_location;
3298 } else {
3299 /* Otherwise return the subpass sample locations if defined. */
3300 if (state->subpass_sample_locs) {
3301 /* Because the driver sets the current subpass before
3302 * initial layout transitions, we should use the sample
3303 * locations from the previous subpass to avoid an
3304 * off-by-one problem. Otherwise, use the sample
3305 * locations for the current subpass for final layout
3306 * transitions.
3307 */
3308 if (begin_subpass)
3309 subpass_id--;
3310
3311 for (uint32_t i = 0; i < state->num_subpass_sample_locs; i++) {
3312 if (state->subpass_sample_locs[i].subpass_idx == subpass_id)
3313 return &state->subpass_sample_locs[i].sample_location;
3314 }
3315 }
3316 }
3317
3318 return NULL;
3319 }
3320
3321 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
3322 struct radv_subpass_attachment att,
3323 bool begin_subpass)
3324 {
3325 unsigned idx = att.attachment;
3326 struct radv_image_view *view = cmd_buffer->state.attachments[idx].iview;
3327 struct radv_sample_locations_state *sample_locs;
3328 VkImageSubresourceRange range;
3329 range.aspectMask = view->aspect_mask;
3330 range.baseMipLevel = view->base_mip;
3331 range.levelCount = 1;
3332 range.baseArrayLayer = view->base_layer;
3333 range.layerCount = cmd_buffer->state.framebuffer->layers;
3334
3335 if (cmd_buffer->state.subpass->view_mask) {
3336 /* If the current subpass uses multiview, the driver might have
3337 * performed a fast color/depth clear to the whole image
3338 * (including all layers). To make sure the driver will
3339 * decompress the image correctly (if needed), we have to
3340 * account for the "real" number of layers. If the view mask is
3341 * sparse, this will decompress more layers than needed.
3342 */
3343 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
3344 }
3345
3346 /* Get the subpass sample locations for the given attachment, if NULL
3347 * is returned the driver will use the default HW locations.
3348 */
3349 sample_locs = radv_get_attachment_sample_locations(cmd_buffer, idx,
3350 begin_subpass);
3351
3352 /* Determine if the subpass uses separate depth/stencil layouts. */
3353 bool uses_separate_depth_stencil_layouts = false;
3354 if ((cmd_buffer->state.attachments[idx].current_layout !=
3355 cmd_buffer->state.attachments[idx].current_stencil_layout) ||
3356 (att.layout != att.stencil_layout)) {
3357 uses_separate_depth_stencil_layouts = true;
3358 }
3359
3360 /* For separate layouts, perform depth and stencil transitions
3361 * separately.
3362 */
3363 if (uses_separate_depth_stencil_layouts &&
3364 (range.aspectMask == (VK_IMAGE_ASPECT_DEPTH_BIT |
3365 VK_IMAGE_ASPECT_STENCIL_BIT))) {
3366 /* Depth-only transitions. */
3367 range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3368 radv_handle_image_transition(cmd_buffer,
3369 view->image,
3370 cmd_buffer->state.attachments[idx].current_layout,
3371 cmd_buffer->state.attachments[idx].current_in_render_loop,
3372 att.layout, att.in_render_loop,
3373 0, 0, &range, sample_locs);
3374
3375 /* Stencil-only transitions. */
3376 range.aspectMask = VK_IMAGE_ASPECT_STENCIL_BIT;
3377 radv_handle_image_transition(cmd_buffer,
3378 view->image,
3379 cmd_buffer->state.attachments[idx].current_stencil_layout,
3380 cmd_buffer->state.attachments[idx].current_in_render_loop,
3381 att.stencil_layout, att.in_render_loop,
3382 0, 0, &range, sample_locs);
3383 } else {
3384 radv_handle_image_transition(cmd_buffer,
3385 view->image,
3386 cmd_buffer->state.attachments[idx].current_layout,
3387 cmd_buffer->state.attachments[idx].current_in_render_loop,
3388 att.layout, att.in_render_loop,
3389 0, 0, &range, sample_locs);
3390 }
3391
3392 cmd_buffer->state.attachments[idx].current_layout = att.layout;
3393 cmd_buffer->state.attachments[idx].current_stencil_layout = att.stencil_layout;
3394 cmd_buffer->state.attachments[idx].current_in_render_loop = att.in_render_loop;
3395
3396
3397 }
3398
3399 void
3400 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
3401 const struct radv_subpass *subpass)
3402 {
3403 cmd_buffer->state.subpass = subpass;
3404
3405 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
3406 }
3407
3408 static VkResult
3409 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
3410 struct radv_render_pass *pass,
3411 const VkRenderPassBeginInfo *info)
3412 {
3413 const struct VkRenderPassSampleLocationsBeginInfoEXT *sample_locs =
3414 vk_find_struct_const(info->pNext,
3415 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT);
3416 struct radv_cmd_state *state = &cmd_buffer->state;
3417
3418 if (!sample_locs) {
3419 state->subpass_sample_locs = NULL;
3420 return VK_SUCCESS;
3421 }
3422
3423 for (uint32_t i = 0; i < sample_locs->attachmentInitialSampleLocationsCount; i++) {
3424 const VkAttachmentSampleLocationsEXT *att_sample_locs =
3425 &sample_locs->pAttachmentInitialSampleLocations[i];
3426 uint32_t att_idx = att_sample_locs->attachmentIndex;
3427 struct radv_image *image = cmd_buffer->state.attachments[att_idx].iview->image;
3428
3429 assert(vk_format_is_depth_or_stencil(image->vk_format));
3430
3431 /* From the Vulkan spec 1.1.108:
3432 *
3433 * "If the image referenced by the framebuffer attachment at
3434 * index attachmentIndex was not created with
3435 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
3436 * then the values specified in sampleLocationsInfo are
3437 * ignored."
3438 */
3439 if (!(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT))
3440 continue;
3441
3442 const VkSampleLocationsInfoEXT *sample_locs_info =
3443 &att_sample_locs->sampleLocationsInfo;
3444
3445 state->attachments[att_idx].sample_location.per_pixel =
3446 sample_locs_info->sampleLocationsPerPixel;
3447 state->attachments[att_idx].sample_location.grid_size =
3448 sample_locs_info->sampleLocationGridSize;
3449 state->attachments[att_idx].sample_location.count =
3450 sample_locs_info->sampleLocationsCount;
3451 typed_memcpy(&state->attachments[att_idx].sample_location.locations[0],
3452 sample_locs_info->pSampleLocations,
3453 sample_locs_info->sampleLocationsCount);
3454 }
3455
3456 state->subpass_sample_locs = vk_alloc(&cmd_buffer->pool->alloc,
3457 sample_locs->postSubpassSampleLocationsCount *
3458 sizeof(state->subpass_sample_locs[0]),
3459 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3460 if (state->subpass_sample_locs == NULL) {
3461 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3462 return cmd_buffer->record_result;
3463 }
3464
3465 state->num_subpass_sample_locs = sample_locs->postSubpassSampleLocationsCount;
3466
3467 for (uint32_t i = 0; i < sample_locs->postSubpassSampleLocationsCount; i++) {
3468 const VkSubpassSampleLocationsEXT *subpass_sample_locs_info =
3469 &sample_locs->pPostSubpassSampleLocations[i];
3470 const VkSampleLocationsInfoEXT *sample_locs_info =
3471 &subpass_sample_locs_info->sampleLocationsInfo;
3472
3473 state->subpass_sample_locs[i].subpass_idx =
3474 subpass_sample_locs_info->subpassIndex;
3475 state->subpass_sample_locs[i].sample_location.per_pixel =
3476 sample_locs_info->sampleLocationsPerPixel;
3477 state->subpass_sample_locs[i].sample_location.grid_size =
3478 sample_locs_info->sampleLocationGridSize;
3479 state->subpass_sample_locs[i].sample_location.count =
3480 sample_locs_info->sampleLocationsCount;
3481 typed_memcpy(&state->subpass_sample_locs[i].sample_location.locations[0],
3482 sample_locs_info->pSampleLocations,
3483 sample_locs_info->sampleLocationsCount);
3484 }
3485
3486 return VK_SUCCESS;
3487 }
3488
3489 static VkResult
3490 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
3491 struct radv_render_pass *pass,
3492 const VkRenderPassBeginInfo *info)
3493 {
3494 struct radv_cmd_state *state = &cmd_buffer->state;
3495 const struct VkRenderPassAttachmentBeginInfo *attachment_info = NULL;
3496
3497 if (info) {
3498 attachment_info = vk_find_struct_const(info->pNext,
3499 RENDER_PASS_ATTACHMENT_BEGIN_INFO);
3500 }
3501
3502
3503 if (pass->attachment_count == 0) {
3504 state->attachments = NULL;
3505 return VK_SUCCESS;
3506 }
3507
3508 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
3509 pass->attachment_count *
3510 sizeof(state->attachments[0]),
3511 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3512 if (state->attachments == NULL) {
3513 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3514 return cmd_buffer->record_result;
3515 }
3516
3517 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
3518 struct radv_render_pass_attachment *att = &pass->attachments[i];
3519 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
3520 VkImageAspectFlags clear_aspects = 0;
3521
3522 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
3523 /* color attachment */
3524 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3525 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
3526 }
3527 } else {
3528 /* depthstencil attachment */
3529 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
3530 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3531 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
3532 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3533 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
3534 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3535 }
3536 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3537 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3538 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3539 }
3540 }
3541
3542 state->attachments[i].pending_clear_aspects = clear_aspects;
3543 state->attachments[i].cleared_views = 0;
3544 if (clear_aspects && info) {
3545 assert(info->clearValueCount > i);
3546 state->attachments[i].clear_value = info->pClearValues[i];
3547 }
3548
3549 state->attachments[i].current_layout = att->initial_layout;
3550 state->attachments[i].current_stencil_layout = att->stencil_initial_layout;
3551 state->attachments[i].sample_location.count = 0;
3552
3553 struct radv_image_view *iview;
3554 if (attachment_info && attachment_info->attachmentCount > i) {
3555 iview = radv_image_view_from_handle(attachment_info->pAttachments[i]);
3556 } else {
3557 iview = state->framebuffer->attachments[i];
3558 }
3559
3560 state->attachments[i].iview = iview;
3561 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3562 radv_initialise_ds_surface(cmd_buffer->device, &state->attachments[i].ds, iview);
3563 } else {
3564 radv_initialise_color_surface(cmd_buffer->device, &state->attachments[i].cb, iview);
3565 }
3566 }
3567
3568 return VK_SUCCESS;
3569 }
3570
3571 VkResult radv_AllocateCommandBuffers(
3572 VkDevice _device,
3573 const VkCommandBufferAllocateInfo *pAllocateInfo,
3574 VkCommandBuffer *pCommandBuffers)
3575 {
3576 RADV_FROM_HANDLE(radv_device, device, _device);
3577 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
3578
3579 VkResult result = VK_SUCCESS;
3580 uint32_t i;
3581
3582 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
3583
3584 if (!list_is_empty(&pool->free_cmd_buffers)) {
3585 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
3586
3587 list_del(&cmd_buffer->pool_link);
3588 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
3589
3590 result = radv_reset_cmd_buffer(cmd_buffer);
3591 cmd_buffer->level = pAllocateInfo->level;
3592
3593 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
3594 } else {
3595 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
3596 &pCommandBuffers[i]);
3597 }
3598 if (result != VK_SUCCESS)
3599 break;
3600 }
3601
3602 if (result != VK_SUCCESS) {
3603 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
3604 i, pCommandBuffers);
3605
3606 /* From the Vulkan 1.0.66 spec:
3607 *
3608 * "vkAllocateCommandBuffers can be used to create multiple
3609 * command buffers. If the creation of any of those command
3610 * buffers fails, the implementation must destroy all
3611 * successfully created command buffer objects from this
3612 * command, set all entries of the pCommandBuffers array to
3613 * NULL and return the error."
3614 */
3615 memset(pCommandBuffers, 0,
3616 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
3617 }
3618
3619 return result;
3620 }
3621
3622 void radv_FreeCommandBuffers(
3623 VkDevice device,
3624 VkCommandPool commandPool,
3625 uint32_t commandBufferCount,
3626 const VkCommandBuffer *pCommandBuffers)
3627 {
3628 for (uint32_t i = 0; i < commandBufferCount; i++) {
3629 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
3630
3631 if (cmd_buffer) {
3632 if (cmd_buffer->pool) {
3633 list_del(&cmd_buffer->pool_link);
3634 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
3635 } else
3636 radv_destroy_cmd_buffer(cmd_buffer);
3637
3638 }
3639 }
3640 }
3641
3642 VkResult radv_ResetCommandBuffer(
3643 VkCommandBuffer commandBuffer,
3644 VkCommandBufferResetFlags flags)
3645 {
3646 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3647 return radv_reset_cmd_buffer(cmd_buffer);
3648 }
3649
3650 VkResult radv_BeginCommandBuffer(
3651 VkCommandBuffer commandBuffer,
3652 const VkCommandBufferBeginInfo *pBeginInfo)
3653 {
3654 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3655 VkResult result = VK_SUCCESS;
3656
3657 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
3658 /* If the command buffer has already been resetted with
3659 * vkResetCommandBuffer, no need to do it again.
3660 */
3661 result = radv_reset_cmd_buffer(cmd_buffer);
3662 if (result != VK_SUCCESS)
3663 return result;
3664 }
3665
3666 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
3667 cmd_buffer->state.last_primitive_reset_en = -1;
3668 cmd_buffer->state.last_index_type = -1;
3669 cmd_buffer->state.last_num_instances = -1;
3670 cmd_buffer->state.last_vertex_offset = -1;
3671 cmd_buffer->state.last_first_instance = -1;
3672 cmd_buffer->state.predication_type = -1;
3673 cmd_buffer->state.last_sx_ps_downconvert = -1;
3674 cmd_buffer->state.last_sx_blend_opt_epsilon = -1;
3675 cmd_buffer->state.last_sx_blend_opt_control = -1;
3676 cmd_buffer->usage_flags = pBeginInfo->flags;
3677
3678 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
3679 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
3680 assert(pBeginInfo->pInheritanceInfo);
3681 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
3682 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
3683
3684 struct radv_subpass *subpass =
3685 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
3686
3687 if (cmd_buffer->state.framebuffer) {
3688 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
3689 if (result != VK_SUCCESS)
3690 return result;
3691 }
3692
3693 cmd_buffer->state.inherited_pipeline_statistics =
3694 pBeginInfo->pInheritanceInfo->pipelineStatistics;
3695
3696 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3697 }
3698
3699 if (unlikely(cmd_buffer->device->trace_bo))
3700 radv_cmd_buffer_trace_emit(cmd_buffer);
3701
3702 radv_describe_begin_cmd_buffer(cmd_buffer);
3703
3704 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
3705
3706 return result;
3707 }
3708
3709 void radv_CmdBindVertexBuffers(
3710 VkCommandBuffer commandBuffer,
3711 uint32_t firstBinding,
3712 uint32_t bindingCount,
3713 const VkBuffer* pBuffers,
3714 const VkDeviceSize* pOffsets)
3715 {
3716 radv_CmdBindVertexBuffers2EXT(commandBuffer, firstBinding,
3717 bindingCount, pBuffers, pOffsets,
3718 NULL, NULL);
3719 }
3720
3721 void radv_CmdBindVertexBuffers2EXT(
3722 VkCommandBuffer commandBuffer,
3723 uint32_t firstBinding,
3724 uint32_t bindingCount,
3725 const VkBuffer* pBuffers,
3726 const VkDeviceSize* pOffsets,
3727 const VkDeviceSize* pSizes,
3728 const VkDeviceSize* pStrides)
3729 {
3730 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3731 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
3732 bool changed = false;
3733
3734 /* We have to defer setting up vertex buffer since we need the buffer
3735 * stride from the pipeline. */
3736
3737 assert(firstBinding + bindingCount <= MAX_VBS);
3738 for (uint32_t i = 0; i < bindingCount; i++) {
3739 RADV_FROM_HANDLE(radv_buffer, buffer, pBuffers[i]);
3740 uint32_t idx = firstBinding + i;
3741 VkDeviceSize size = pSizes ? pSizes[i] : 0;
3742 VkDeviceSize stride = pStrides ? pStrides[i] : 0;
3743
3744 /* pSizes and pStrides are optional. */
3745 if (!changed &&
3746 (vb[idx].buffer != buffer ||
3747 vb[idx].offset != pOffsets[i] ||
3748 vb[idx].size != size ||
3749 vb[idx].stride != stride)) {
3750 changed = true;
3751 }
3752
3753 vb[idx].buffer = buffer;
3754 vb[idx].offset = pOffsets[i];
3755 vb[idx].size = size;
3756 vb[idx].stride = stride;
3757
3758 if (buffer) {
3759 radv_cs_add_buffer(cmd_buffer->device->ws,
3760 cmd_buffer->cs, vb[idx].buffer->bo);
3761 }
3762 }
3763
3764 if (!changed) {
3765 /* No state changes. */
3766 return;
3767 }
3768
3769 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
3770 }
3771
3772 static uint32_t
3773 vk_to_index_type(VkIndexType type)
3774 {
3775 switch (type) {
3776 case VK_INDEX_TYPE_UINT8_EXT:
3777 return V_028A7C_VGT_INDEX_8;
3778 case VK_INDEX_TYPE_UINT16:
3779 return V_028A7C_VGT_INDEX_16;
3780 case VK_INDEX_TYPE_UINT32:
3781 return V_028A7C_VGT_INDEX_32;
3782 default:
3783 unreachable("invalid index type");
3784 }
3785 }
3786
3787 static uint32_t
3788 radv_get_vgt_index_size(uint32_t type)
3789 {
3790 switch (type) {
3791 case V_028A7C_VGT_INDEX_8:
3792 return 1;
3793 case V_028A7C_VGT_INDEX_16:
3794 return 2;
3795 case V_028A7C_VGT_INDEX_32:
3796 return 4;
3797 default:
3798 unreachable("invalid index type");
3799 }
3800 }
3801
3802 void radv_CmdBindIndexBuffer(
3803 VkCommandBuffer commandBuffer,
3804 VkBuffer buffer,
3805 VkDeviceSize offset,
3806 VkIndexType indexType)
3807 {
3808 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3809 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
3810
3811 if (cmd_buffer->state.index_buffer == index_buffer &&
3812 cmd_buffer->state.index_offset == offset &&
3813 cmd_buffer->state.index_type == indexType) {
3814 /* No state changes. */
3815 return;
3816 }
3817
3818 cmd_buffer->state.index_buffer = index_buffer;
3819 cmd_buffer->state.index_offset = offset;
3820 cmd_buffer->state.index_type = vk_to_index_type(indexType);
3821 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
3822 cmd_buffer->state.index_va += index_buffer->offset + offset;
3823
3824 int index_size = radv_get_vgt_index_size(vk_to_index_type(indexType));
3825 cmd_buffer->state.max_index_count = (index_buffer->size - offset) / index_size;
3826 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3827 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
3828 }
3829
3830
3831 static void
3832 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3833 VkPipelineBindPoint bind_point,
3834 struct radv_descriptor_set *set, unsigned idx)
3835 {
3836 struct radeon_winsys *ws = cmd_buffer->device->ws;
3837
3838 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
3839
3840 assert(set);
3841 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
3842
3843 if (!cmd_buffer->device->use_global_bo_list) {
3844 for (unsigned j = 0; j < set->buffer_count; ++j)
3845 if (set->descriptors[j])
3846 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
3847 }
3848
3849 if(set->bo)
3850 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
3851 }
3852
3853 void radv_CmdBindDescriptorSets(
3854 VkCommandBuffer commandBuffer,
3855 VkPipelineBindPoint pipelineBindPoint,
3856 VkPipelineLayout _layout,
3857 uint32_t firstSet,
3858 uint32_t descriptorSetCount,
3859 const VkDescriptorSet* pDescriptorSets,
3860 uint32_t dynamicOffsetCount,
3861 const uint32_t* pDynamicOffsets)
3862 {
3863 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3864 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3865 unsigned dyn_idx = 0;
3866
3867 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
3868 struct radv_descriptor_state *descriptors_state =
3869 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3870
3871 for (unsigned i = 0; i < descriptorSetCount; ++i) {
3872 unsigned idx = i + firstSet;
3873 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
3874
3875 /* If the set is already bound we only need to update the
3876 * (potentially changed) dynamic offsets. */
3877 if (descriptors_state->sets[idx] != set ||
3878 !(descriptors_state->valid & (1u << idx))) {
3879 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
3880 }
3881
3882 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
3883 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
3884 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
3885 assert(dyn_idx < dynamicOffsetCount);
3886
3887 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
3888 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
3889 dst[0] = va;
3890 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
3891 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
3892 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3893 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3894 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3895 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3896
3897 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
3898 dst[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3899 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3900 S_008F0C_RESOURCE_LEVEL(1);
3901 } else {
3902 dst[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3903 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3904 }
3905
3906 cmd_buffer->push_constant_stages |=
3907 set->layout->dynamic_shader_stages;
3908 }
3909 }
3910 }
3911
3912 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3913 struct radv_descriptor_set *set,
3914 struct radv_descriptor_set_layout *layout,
3915 VkPipelineBindPoint bind_point)
3916 {
3917 struct radv_descriptor_state *descriptors_state =
3918 radv_get_descriptors_state(cmd_buffer, bind_point);
3919 set->size = layout->size;
3920 set->layout = layout;
3921
3922 if (descriptors_state->push_set.capacity < set->size) {
3923 size_t new_size = MAX2(set->size, 1024);
3924 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
3925 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
3926
3927 free(set->mapped_ptr);
3928 set->mapped_ptr = malloc(new_size);
3929
3930 if (!set->mapped_ptr) {
3931 descriptors_state->push_set.capacity = 0;
3932 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3933 return false;
3934 }
3935
3936 descriptors_state->push_set.capacity = new_size;
3937 }
3938
3939 return true;
3940 }
3941
3942 void radv_meta_push_descriptor_set(
3943 struct radv_cmd_buffer* cmd_buffer,
3944 VkPipelineBindPoint pipelineBindPoint,
3945 VkPipelineLayout _layout,
3946 uint32_t set,
3947 uint32_t descriptorWriteCount,
3948 const VkWriteDescriptorSet* pDescriptorWrites)
3949 {
3950 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3951 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
3952 unsigned bo_offset;
3953
3954 assert(set == 0);
3955 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3956
3957 push_set->size = layout->set[set].layout->size;
3958 push_set->layout = layout->set[set].layout;
3959
3960 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
3961 &bo_offset,
3962 (void**) &push_set->mapped_ptr))
3963 return;
3964
3965 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
3966 push_set->va += bo_offset;
3967
3968 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3969 radv_descriptor_set_to_handle(push_set),
3970 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3971
3972 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3973 }
3974
3975 void radv_CmdPushDescriptorSetKHR(
3976 VkCommandBuffer commandBuffer,
3977 VkPipelineBindPoint pipelineBindPoint,
3978 VkPipelineLayout _layout,
3979 uint32_t set,
3980 uint32_t descriptorWriteCount,
3981 const VkWriteDescriptorSet* pDescriptorWrites)
3982 {
3983 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3984 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3985 struct radv_descriptor_state *descriptors_state =
3986 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3987 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3988
3989 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3990
3991 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3992 layout->set[set].layout,
3993 pipelineBindPoint))
3994 return;
3995
3996 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3997 * because it is invalid, according to Vulkan spec.
3998 */
3999 for (int i = 0; i < descriptorWriteCount; i++) {
4000 ASSERTED const VkWriteDescriptorSet *writeset = &pDescriptorWrites[i];
4001 assert(writeset->descriptorType != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT);
4002 }
4003
4004 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
4005 radv_descriptor_set_to_handle(push_set),
4006 descriptorWriteCount, pDescriptorWrites, 0, NULL);
4007
4008 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
4009 descriptors_state->push_dirty = true;
4010 }
4011
4012 void radv_CmdPushDescriptorSetWithTemplateKHR(
4013 VkCommandBuffer commandBuffer,
4014 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
4015 VkPipelineLayout _layout,
4016 uint32_t set,
4017 const void* pData)
4018 {
4019 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4020 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
4021 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
4022 struct radv_descriptor_state *descriptors_state =
4023 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
4024 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
4025
4026 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
4027
4028 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
4029 layout->set[set].layout,
4030 templ->bind_point))
4031 return;
4032
4033 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
4034 descriptorUpdateTemplate, pData);
4035
4036 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
4037 descriptors_state->push_dirty = true;
4038 }
4039
4040 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
4041 VkPipelineLayout layout,
4042 VkShaderStageFlags stageFlags,
4043 uint32_t offset,
4044 uint32_t size,
4045 const void* pValues)
4046 {
4047 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4048 memcpy(cmd_buffer->push_constants + offset, pValues, size);
4049 cmd_buffer->push_constant_stages |= stageFlags;
4050 }
4051
4052 VkResult radv_EndCommandBuffer(
4053 VkCommandBuffer commandBuffer)
4054 {
4055 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4056
4057 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
4058 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6)
4059 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WB_L2;
4060
4061 /* Make sure to sync all pending active queries at the end of
4062 * command buffer.
4063 */
4064 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
4065
4066 /* Since NGG streamout uses GDS, we need to make GDS idle when
4067 * we leave the IB, otherwise another process might overwrite
4068 * it while our shaders are busy.
4069 */
4070 if (cmd_buffer->gds_needed)
4071 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
4072
4073 si_emit_cache_flush(cmd_buffer);
4074 }
4075
4076 /* Make sure CP DMA is idle at the end of IBs because the kernel
4077 * doesn't wait for it.
4078 */
4079 si_cp_dma_wait_for_idle(cmd_buffer);
4080
4081 radv_describe_end_cmd_buffer(cmd_buffer);
4082
4083 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
4084 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
4085
4086 VkResult result = cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs);
4087 if (result != VK_SUCCESS)
4088 return vk_error(cmd_buffer->device->instance, result);
4089
4090 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
4091
4092 return cmd_buffer->record_result;
4093 }
4094
4095 static void
4096 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
4097 {
4098 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4099
4100 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
4101 return;
4102
4103 assert(!pipeline->ctx_cs.cdw);
4104
4105 cmd_buffer->state.emitted_compute_pipeline = pipeline;
4106
4107 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
4108 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
4109
4110 cmd_buffer->compute_scratch_size_per_wave_needed = MAX2(cmd_buffer->compute_scratch_size_per_wave_needed,
4111 pipeline->scratch_bytes_per_wave);
4112 cmd_buffer->compute_scratch_waves_wanted = MAX2(cmd_buffer->compute_scratch_waves_wanted,
4113 pipeline->max_waves);
4114
4115 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
4116 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
4117
4118 if (unlikely(cmd_buffer->device->trace_bo))
4119 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
4120 }
4121
4122 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
4123 VkPipelineBindPoint bind_point)
4124 {
4125 struct radv_descriptor_state *descriptors_state =
4126 radv_get_descriptors_state(cmd_buffer, bind_point);
4127
4128 descriptors_state->dirty |= descriptors_state->valid;
4129 }
4130
4131 void radv_CmdBindPipeline(
4132 VkCommandBuffer commandBuffer,
4133 VkPipelineBindPoint pipelineBindPoint,
4134 VkPipeline _pipeline)
4135 {
4136 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4137 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
4138
4139 switch (pipelineBindPoint) {
4140 case VK_PIPELINE_BIND_POINT_COMPUTE:
4141 if (cmd_buffer->state.compute_pipeline == pipeline)
4142 return;
4143 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
4144
4145 cmd_buffer->state.compute_pipeline = pipeline;
4146 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
4147 break;
4148 case VK_PIPELINE_BIND_POINT_GRAPHICS:
4149 if (cmd_buffer->state.pipeline == pipeline)
4150 return;
4151 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
4152
4153 cmd_buffer->state.pipeline = pipeline;
4154 if (!pipeline)
4155 break;
4156
4157 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
4158 cmd_buffer->push_constant_stages |= pipeline->active_stages;
4159
4160 /* the new vertex shader might not have the same user regs */
4161 cmd_buffer->state.last_first_instance = -1;
4162 cmd_buffer->state.last_vertex_offset = -1;
4163
4164 /* Prefetch all pipeline shaders at first draw time. */
4165 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
4166
4167 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX10 &&
4168 cmd_buffer->state.emitted_pipeline &&
4169 radv_pipeline_has_ngg(cmd_buffer->state.emitted_pipeline) &&
4170 !radv_pipeline_has_ngg(cmd_buffer->state.pipeline)) {
4171 /* Transitioning from NGG to legacy GS requires
4172 * VGT_FLUSH on Navi10-14. VGT_FLUSH is also emitted
4173 * at the beginning of IBs when legacy GS ring pointers
4174 * are set.
4175 */
4176 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
4177 }
4178
4179 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
4180 radv_bind_streamout_state(cmd_buffer, pipeline);
4181
4182 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
4183 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
4184 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
4185 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
4186
4187 if (radv_pipeline_has_tess(pipeline))
4188 cmd_buffer->tess_rings_needed = true;
4189 break;
4190 default:
4191 assert(!"invalid bind point");
4192 break;
4193 }
4194 }
4195
4196 void radv_CmdSetViewport(
4197 VkCommandBuffer commandBuffer,
4198 uint32_t firstViewport,
4199 uint32_t viewportCount,
4200 const VkViewport* pViewports)
4201 {
4202 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4203 struct radv_cmd_state *state = &cmd_buffer->state;
4204 ASSERTED const uint32_t total_count = firstViewport + viewportCount;
4205
4206 assert(firstViewport < MAX_VIEWPORTS);
4207 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
4208
4209 if (total_count <= state->dynamic.viewport.count &&
4210 !memcmp(state->dynamic.viewport.viewports + firstViewport,
4211 pViewports, viewportCount * sizeof(*pViewports))) {
4212 return;
4213 }
4214
4215 if (state->dynamic.viewport.count < total_count)
4216 state->dynamic.viewport.count = total_count;
4217
4218 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
4219 viewportCount * sizeof(*pViewports));
4220
4221 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
4222 }
4223
4224 void radv_CmdSetScissor(
4225 VkCommandBuffer commandBuffer,
4226 uint32_t firstScissor,
4227 uint32_t scissorCount,
4228 const VkRect2D* pScissors)
4229 {
4230 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4231 struct radv_cmd_state *state = &cmd_buffer->state;
4232 ASSERTED const uint32_t total_count = firstScissor + scissorCount;
4233
4234 assert(firstScissor < MAX_SCISSORS);
4235 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
4236
4237 if (total_count <= state->dynamic.scissor.count &&
4238 !memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
4239 scissorCount * sizeof(*pScissors))) {
4240 return;
4241 }
4242
4243 if (state->dynamic.scissor.count < total_count)
4244 state->dynamic.scissor.count = total_count;
4245
4246 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
4247 scissorCount * sizeof(*pScissors));
4248
4249 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
4250 }
4251
4252 void radv_CmdSetLineWidth(
4253 VkCommandBuffer commandBuffer,
4254 float lineWidth)
4255 {
4256 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4257
4258 if (cmd_buffer->state.dynamic.line_width == lineWidth)
4259 return;
4260
4261 cmd_buffer->state.dynamic.line_width = lineWidth;
4262 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
4263 }
4264
4265 void radv_CmdSetDepthBias(
4266 VkCommandBuffer commandBuffer,
4267 float depthBiasConstantFactor,
4268 float depthBiasClamp,
4269 float depthBiasSlopeFactor)
4270 {
4271 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4272 struct radv_cmd_state *state = &cmd_buffer->state;
4273
4274 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
4275 state->dynamic.depth_bias.clamp == depthBiasClamp &&
4276 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
4277 return;
4278 }
4279
4280 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
4281 state->dynamic.depth_bias.clamp = depthBiasClamp;
4282 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
4283
4284 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
4285 }
4286
4287 void radv_CmdSetBlendConstants(
4288 VkCommandBuffer commandBuffer,
4289 const float blendConstants[4])
4290 {
4291 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4292 struct radv_cmd_state *state = &cmd_buffer->state;
4293
4294 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
4295 return;
4296
4297 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
4298
4299 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
4300 }
4301
4302 void radv_CmdSetDepthBounds(
4303 VkCommandBuffer commandBuffer,
4304 float minDepthBounds,
4305 float maxDepthBounds)
4306 {
4307 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4308 struct radv_cmd_state *state = &cmd_buffer->state;
4309
4310 if (state->dynamic.depth_bounds.min == minDepthBounds &&
4311 state->dynamic.depth_bounds.max == maxDepthBounds) {
4312 return;
4313 }
4314
4315 state->dynamic.depth_bounds.min = minDepthBounds;
4316 state->dynamic.depth_bounds.max = maxDepthBounds;
4317
4318 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
4319 }
4320
4321 void radv_CmdSetStencilCompareMask(
4322 VkCommandBuffer commandBuffer,
4323 VkStencilFaceFlags faceMask,
4324 uint32_t compareMask)
4325 {
4326 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4327 struct radv_cmd_state *state = &cmd_buffer->state;
4328 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
4329 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
4330
4331 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4332 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4333 return;
4334 }
4335
4336 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4337 state->dynamic.stencil_compare_mask.front = compareMask;
4338 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4339 state->dynamic.stencil_compare_mask.back = compareMask;
4340
4341 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
4342 }
4343
4344 void radv_CmdSetStencilWriteMask(
4345 VkCommandBuffer commandBuffer,
4346 VkStencilFaceFlags faceMask,
4347 uint32_t writeMask)
4348 {
4349 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4350 struct radv_cmd_state *state = &cmd_buffer->state;
4351 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
4352 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
4353
4354 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4355 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4356 return;
4357 }
4358
4359 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4360 state->dynamic.stencil_write_mask.front = writeMask;
4361 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4362 state->dynamic.stencil_write_mask.back = writeMask;
4363
4364 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
4365 }
4366
4367 void radv_CmdSetStencilReference(
4368 VkCommandBuffer commandBuffer,
4369 VkStencilFaceFlags faceMask,
4370 uint32_t reference)
4371 {
4372 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4373 struct radv_cmd_state *state = &cmd_buffer->state;
4374 bool front_same = state->dynamic.stencil_reference.front == reference;
4375 bool back_same = state->dynamic.stencil_reference.back == reference;
4376
4377 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4378 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4379 return;
4380 }
4381
4382 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4383 cmd_buffer->state.dynamic.stencil_reference.front = reference;
4384 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4385 cmd_buffer->state.dynamic.stencil_reference.back = reference;
4386
4387 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
4388 }
4389
4390 void radv_CmdSetDiscardRectangleEXT(
4391 VkCommandBuffer commandBuffer,
4392 uint32_t firstDiscardRectangle,
4393 uint32_t discardRectangleCount,
4394 const VkRect2D* pDiscardRectangles)
4395 {
4396 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4397 struct radv_cmd_state *state = &cmd_buffer->state;
4398 ASSERTED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
4399
4400 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
4401 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
4402
4403 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
4404 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
4405 return;
4406 }
4407
4408 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
4409 pDiscardRectangles, discardRectangleCount);
4410
4411 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
4412 }
4413
4414 void radv_CmdSetSampleLocationsEXT(
4415 VkCommandBuffer commandBuffer,
4416 const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
4417 {
4418 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4419 struct radv_cmd_state *state = &cmd_buffer->state;
4420
4421 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
4422
4423 state->dynamic.sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
4424 state->dynamic.sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
4425 state->dynamic.sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
4426 typed_memcpy(&state->dynamic.sample_location.locations[0],
4427 pSampleLocationsInfo->pSampleLocations,
4428 pSampleLocationsInfo->sampleLocationsCount);
4429
4430 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS;
4431 }
4432
4433 void radv_CmdSetLineStippleEXT(
4434 VkCommandBuffer commandBuffer,
4435 uint32_t lineStippleFactor,
4436 uint16_t lineStipplePattern)
4437 {
4438 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4439 struct radv_cmd_state *state = &cmd_buffer->state;
4440
4441 state->dynamic.line_stipple.factor = lineStippleFactor;
4442 state->dynamic.line_stipple.pattern = lineStipplePattern;
4443
4444 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE;
4445 }
4446
4447 void radv_CmdSetCullModeEXT(
4448 VkCommandBuffer commandBuffer,
4449 VkCullModeFlags cullMode)
4450 {
4451 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4452 struct radv_cmd_state *state = &cmd_buffer->state;
4453
4454 if (state->dynamic.cull_mode == cullMode)
4455 return;
4456
4457 state->dynamic.cull_mode = cullMode;
4458
4459 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_CULL_MODE;
4460 }
4461
4462 void radv_CmdSetFrontFaceEXT(
4463 VkCommandBuffer commandBuffer,
4464 VkFrontFace frontFace)
4465 {
4466 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4467 struct radv_cmd_state *state = &cmd_buffer->state;
4468
4469 if (state->dynamic.front_face == frontFace)
4470 return;
4471
4472 state->dynamic.front_face = frontFace;
4473
4474 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE;
4475 }
4476
4477 void radv_CmdSetPrimitiveTopologyEXT(
4478 VkCommandBuffer commandBuffer,
4479 VkPrimitiveTopology primitiveTopology)
4480 {
4481 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4482 struct radv_cmd_state *state = &cmd_buffer->state;
4483 unsigned primitive_topology = si_translate_prim(primitiveTopology);
4484
4485 if (state->dynamic.primitive_topology == primitive_topology)
4486 return;
4487
4488 state->dynamic.primitive_topology = primitive_topology;
4489
4490 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY;
4491 }
4492
4493 void radv_CmdSetViewportWithCountEXT(
4494 VkCommandBuffer commandBuffer,
4495 uint32_t viewportCount,
4496 const VkViewport* pViewports)
4497 {
4498 radv_CmdSetViewport(commandBuffer, 0, viewportCount, pViewports);
4499 }
4500
4501 void radv_CmdSetScissorWithCountEXT(
4502 VkCommandBuffer commandBuffer,
4503 uint32_t scissorCount,
4504 const VkRect2D* pScissors)
4505 {
4506 radv_CmdSetScissor(commandBuffer, 0, scissorCount, pScissors);
4507 }
4508
4509 void radv_CmdSetDepthTestEnableEXT(
4510 VkCommandBuffer commandBuffer,
4511 VkBool32 depthTestEnable)
4512
4513 {
4514 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4515 struct radv_cmd_state *state = &cmd_buffer->state;
4516
4517 if (state->dynamic.depth_test_enable == depthTestEnable)
4518 return;
4519
4520 state->dynamic.depth_test_enable = depthTestEnable;
4521
4522 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE;
4523 }
4524
4525 void radv_CmdSetDepthWriteEnableEXT(
4526 VkCommandBuffer commandBuffer,
4527 VkBool32 depthWriteEnable)
4528 {
4529 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4530 struct radv_cmd_state *state = &cmd_buffer->state;
4531
4532 if (state->dynamic.depth_write_enable == depthWriteEnable)
4533 return;
4534
4535 state->dynamic.depth_write_enable = depthWriteEnable;
4536
4537 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE;
4538 }
4539
4540 void radv_CmdSetDepthCompareOpEXT(
4541 VkCommandBuffer commandBuffer,
4542 VkCompareOp depthCompareOp)
4543 {
4544 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4545 struct radv_cmd_state *state = &cmd_buffer->state;
4546
4547 if (state->dynamic.depth_compare_op == depthCompareOp)
4548 return;
4549
4550 state->dynamic.depth_compare_op = depthCompareOp;
4551
4552 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP;
4553 }
4554
4555 void radv_CmdSetDepthBoundsTestEnableEXT(
4556 VkCommandBuffer commandBuffer,
4557 VkBool32 depthBoundsTestEnable)
4558 {
4559 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4560 struct radv_cmd_state *state = &cmd_buffer->state;
4561
4562 if (state->dynamic.depth_bounds_test_enable == depthBoundsTestEnable)
4563 return;
4564
4565 state->dynamic.depth_bounds_test_enable = depthBoundsTestEnable;
4566
4567 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE;
4568 }
4569
4570 void radv_CmdSetStencilTestEnableEXT(
4571 VkCommandBuffer commandBuffer,
4572 VkBool32 stencilTestEnable)
4573 {
4574 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4575 struct radv_cmd_state *state = &cmd_buffer->state;
4576
4577 if (state->dynamic.stencil_test_enable == stencilTestEnable)
4578 return;
4579
4580 state->dynamic.stencil_test_enable = stencilTestEnable;
4581
4582 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE;
4583 }
4584
4585 void radv_CmdSetStencilOpEXT(
4586 VkCommandBuffer commandBuffer,
4587 VkStencilFaceFlags faceMask,
4588 VkStencilOp failOp,
4589 VkStencilOp passOp,
4590 VkStencilOp depthFailOp,
4591 VkCompareOp compareOp)
4592 {
4593 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4594 struct radv_cmd_state *state = &cmd_buffer->state;
4595 bool front_same =
4596 state->dynamic.stencil_op.front.fail_op == failOp &&
4597 state->dynamic.stencil_op.front.pass_op == passOp &&
4598 state->dynamic.stencil_op.front.depth_fail_op == depthFailOp &&
4599 state->dynamic.stencil_op.front.compare_op == compareOp;
4600 bool back_same =
4601 state->dynamic.stencil_op.back.fail_op == failOp &&
4602 state->dynamic.stencil_op.back.pass_op == passOp &&
4603 state->dynamic.stencil_op.back.depth_fail_op == depthFailOp &&
4604 state->dynamic.stencil_op.back.compare_op == compareOp;
4605
4606 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4607 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same))
4608 return;
4609
4610 if (faceMask & VK_STENCIL_FACE_FRONT_BIT) {
4611 state->dynamic.stencil_op.front.fail_op = failOp;
4612 state->dynamic.stencil_op.front.pass_op = passOp;
4613 state->dynamic.stencil_op.front.depth_fail_op = depthFailOp;
4614 state->dynamic.stencil_op.front.compare_op = compareOp;
4615 }
4616
4617 if (faceMask & VK_STENCIL_FACE_BACK_BIT) {
4618 state->dynamic.stencil_op.back.fail_op = failOp;
4619 state->dynamic.stencil_op.back.pass_op = passOp;
4620 state->dynamic.stencil_op.back.depth_fail_op = depthFailOp;
4621 state->dynamic.stencil_op.back.compare_op = compareOp;
4622 }
4623
4624 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP;
4625 }
4626
4627 void radv_CmdExecuteCommands(
4628 VkCommandBuffer commandBuffer,
4629 uint32_t commandBufferCount,
4630 const VkCommandBuffer* pCmdBuffers)
4631 {
4632 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
4633
4634 assert(commandBufferCount > 0);
4635
4636 /* Emit pending flushes on primary prior to executing secondary */
4637 si_emit_cache_flush(primary);
4638
4639 for (uint32_t i = 0; i < commandBufferCount; i++) {
4640 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
4641
4642 primary->scratch_size_per_wave_needed = MAX2(primary->scratch_size_per_wave_needed,
4643 secondary->scratch_size_per_wave_needed);
4644 primary->scratch_waves_wanted = MAX2(primary->scratch_waves_wanted,
4645 secondary->scratch_waves_wanted);
4646 primary->compute_scratch_size_per_wave_needed = MAX2(primary->compute_scratch_size_per_wave_needed,
4647 secondary->compute_scratch_size_per_wave_needed);
4648 primary->compute_scratch_waves_wanted = MAX2(primary->compute_scratch_waves_wanted,
4649 secondary->compute_scratch_waves_wanted);
4650
4651 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
4652 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
4653 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
4654 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
4655 if (secondary->tess_rings_needed)
4656 primary->tess_rings_needed = true;
4657 if (secondary->sample_positions_needed)
4658 primary->sample_positions_needed = true;
4659 if (secondary->gds_needed)
4660 primary->gds_needed = true;
4661
4662 if (!secondary->state.framebuffer &&
4663 (primary->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)) {
4664 /* Emit the framebuffer state from primary if secondary
4665 * has been recorded without a framebuffer, otherwise
4666 * fast color/depth clears can't work.
4667 */
4668 radv_emit_framebuffer_state(primary);
4669 }
4670
4671 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
4672
4673
4674 /* When the secondary command buffer is compute only we don't
4675 * need to re-emit the current graphics pipeline.
4676 */
4677 if (secondary->state.emitted_pipeline) {
4678 primary->state.emitted_pipeline =
4679 secondary->state.emitted_pipeline;
4680 }
4681
4682 /* When the secondary command buffer is graphics only we don't
4683 * need to re-emit the current compute pipeline.
4684 */
4685 if (secondary->state.emitted_compute_pipeline) {
4686 primary->state.emitted_compute_pipeline =
4687 secondary->state.emitted_compute_pipeline;
4688 }
4689
4690 /* Only re-emit the draw packets when needed. */
4691 if (secondary->state.last_primitive_reset_en != -1) {
4692 primary->state.last_primitive_reset_en =
4693 secondary->state.last_primitive_reset_en;
4694 }
4695
4696 if (secondary->state.last_primitive_reset_index) {
4697 primary->state.last_primitive_reset_index =
4698 secondary->state.last_primitive_reset_index;
4699 }
4700
4701 if (secondary->state.last_ia_multi_vgt_param) {
4702 primary->state.last_ia_multi_vgt_param =
4703 secondary->state.last_ia_multi_vgt_param;
4704 }
4705
4706 primary->state.last_first_instance = secondary->state.last_first_instance;
4707 primary->state.last_num_instances = secondary->state.last_num_instances;
4708 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
4709 primary->state.last_sx_ps_downconvert = secondary->state.last_sx_ps_downconvert;
4710 primary->state.last_sx_blend_opt_epsilon = secondary->state.last_sx_blend_opt_epsilon;
4711 primary->state.last_sx_blend_opt_control = secondary->state.last_sx_blend_opt_control;
4712
4713 if (secondary->state.last_index_type != -1) {
4714 primary->state.last_index_type =
4715 secondary->state.last_index_type;
4716 }
4717 }
4718
4719 /* After executing commands from secondary buffers we have to dirty
4720 * some states.
4721 */
4722 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
4723 RADV_CMD_DIRTY_INDEX_BUFFER |
4724 RADV_CMD_DIRTY_DYNAMIC_ALL;
4725 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
4726 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
4727 }
4728
4729 VkResult radv_CreateCommandPool(
4730 VkDevice _device,
4731 const VkCommandPoolCreateInfo* pCreateInfo,
4732 const VkAllocationCallbacks* pAllocator,
4733 VkCommandPool* pCmdPool)
4734 {
4735 RADV_FROM_HANDLE(radv_device, device, _device);
4736 struct radv_cmd_pool *pool;
4737
4738 pool = vk_alloc2(&device->vk.alloc, pAllocator, sizeof(*pool), 8,
4739 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4740 if (pool == NULL)
4741 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4742
4743 vk_object_base_init(&device->vk, &pool->base,
4744 VK_OBJECT_TYPE_COMMAND_POOL);
4745
4746 if (pAllocator)
4747 pool->alloc = *pAllocator;
4748 else
4749 pool->alloc = device->vk.alloc;
4750
4751 list_inithead(&pool->cmd_buffers);
4752 list_inithead(&pool->free_cmd_buffers);
4753
4754 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
4755
4756 *pCmdPool = radv_cmd_pool_to_handle(pool);
4757
4758 return VK_SUCCESS;
4759
4760 }
4761
4762 void radv_DestroyCommandPool(
4763 VkDevice _device,
4764 VkCommandPool commandPool,
4765 const VkAllocationCallbacks* pAllocator)
4766 {
4767 RADV_FROM_HANDLE(radv_device, device, _device);
4768 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4769
4770 if (!pool)
4771 return;
4772
4773 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4774 &pool->cmd_buffers, pool_link) {
4775 radv_destroy_cmd_buffer(cmd_buffer);
4776 }
4777
4778 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4779 &pool->free_cmd_buffers, pool_link) {
4780 radv_destroy_cmd_buffer(cmd_buffer);
4781 }
4782
4783 vk_object_base_finish(&pool->base);
4784 vk_free2(&device->vk.alloc, pAllocator, pool);
4785 }
4786
4787 VkResult radv_ResetCommandPool(
4788 VkDevice device,
4789 VkCommandPool commandPool,
4790 VkCommandPoolResetFlags flags)
4791 {
4792 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4793 VkResult result;
4794
4795 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
4796 &pool->cmd_buffers, pool_link) {
4797 result = radv_reset_cmd_buffer(cmd_buffer);
4798 if (result != VK_SUCCESS)
4799 return result;
4800 }
4801
4802 return VK_SUCCESS;
4803 }
4804
4805 void radv_TrimCommandPool(
4806 VkDevice device,
4807 VkCommandPool commandPool,
4808 VkCommandPoolTrimFlags flags)
4809 {
4810 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4811
4812 if (!pool)
4813 return;
4814
4815 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4816 &pool->free_cmd_buffers, pool_link) {
4817 radv_destroy_cmd_buffer(cmd_buffer);
4818 }
4819 }
4820
4821 static void
4822 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
4823 uint32_t subpass_id)
4824 {
4825 struct radv_cmd_state *state = &cmd_buffer->state;
4826 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
4827
4828 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
4829 cmd_buffer->cs, 4096);
4830
4831 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
4832
4833 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
4834
4835 radv_describe_barrier_start(cmd_buffer, RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC);
4836
4837 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4838 const uint32_t a = subpass->attachments[i].attachment;
4839 if (a == VK_ATTACHMENT_UNUSED)
4840 continue;
4841
4842 radv_handle_subpass_image_transition(cmd_buffer,
4843 subpass->attachments[i],
4844 true);
4845 }
4846
4847 radv_describe_barrier_end(cmd_buffer);
4848
4849 radv_cmd_buffer_clear_subpass(cmd_buffer);
4850
4851 assert(cmd_buffer->cs->cdw <= cdw_max);
4852 }
4853
4854 static void
4855 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
4856 {
4857 struct radv_cmd_state *state = &cmd_buffer->state;
4858 const struct radv_subpass *subpass = state->subpass;
4859 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
4860
4861 radv_cmd_buffer_resolve_subpass(cmd_buffer);
4862
4863 radv_describe_barrier_start(cmd_buffer, RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC);
4864
4865 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4866 const uint32_t a = subpass->attachments[i].attachment;
4867 if (a == VK_ATTACHMENT_UNUSED)
4868 continue;
4869
4870 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
4871 continue;
4872
4873 VkImageLayout layout = state->pass->attachments[a].final_layout;
4874 VkImageLayout stencil_layout = state->pass->attachments[a].stencil_final_layout;
4875 struct radv_subpass_attachment att = { a, layout, stencil_layout };
4876 radv_handle_subpass_image_transition(cmd_buffer, att, false);
4877 }
4878
4879 radv_describe_barrier_end(cmd_buffer);
4880 }
4881
4882 void
4883 radv_cmd_buffer_begin_render_pass(struct radv_cmd_buffer *cmd_buffer,
4884 const VkRenderPassBeginInfo *pRenderPassBegin)
4885 {
4886 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
4887 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
4888 VkResult result;
4889
4890 cmd_buffer->state.framebuffer = framebuffer;
4891 cmd_buffer->state.pass = pass;
4892 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
4893
4894 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
4895 if (result != VK_SUCCESS)
4896 return;
4897
4898 result = radv_cmd_state_setup_sample_locations(cmd_buffer, pass, pRenderPassBegin);
4899 if (result != VK_SUCCESS)
4900 return;
4901 }
4902
4903 void radv_CmdBeginRenderPass(
4904 VkCommandBuffer commandBuffer,
4905 const VkRenderPassBeginInfo* pRenderPassBegin,
4906 VkSubpassContents contents)
4907 {
4908 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4909
4910 radv_cmd_buffer_begin_render_pass(cmd_buffer, pRenderPassBegin);
4911
4912 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
4913 }
4914
4915 void radv_CmdBeginRenderPass2(
4916 VkCommandBuffer commandBuffer,
4917 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
4918 const VkSubpassBeginInfo* pSubpassBeginInfo)
4919 {
4920 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
4921 pSubpassBeginInfo->contents);
4922 }
4923
4924 void radv_CmdNextSubpass(
4925 VkCommandBuffer commandBuffer,
4926 VkSubpassContents contents)
4927 {
4928 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4929
4930 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
4931 radv_cmd_buffer_end_subpass(cmd_buffer);
4932 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
4933 }
4934
4935 void radv_CmdNextSubpass2(
4936 VkCommandBuffer commandBuffer,
4937 const VkSubpassBeginInfo* pSubpassBeginInfo,
4938 const VkSubpassEndInfo* pSubpassEndInfo)
4939 {
4940 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
4941 }
4942
4943 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
4944 {
4945 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
4946 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
4947 if (!radv_get_shader(pipeline, stage))
4948 continue;
4949
4950 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
4951 if (loc->sgpr_idx == -1)
4952 continue;
4953 uint32_t base_reg = pipeline->user_data_0[stage];
4954 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4955
4956 }
4957 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
4958 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
4959 if (loc->sgpr_idx != -1) {
4960 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
4961 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4962 }
4963 }
4964 }
4965
4966 static void
4967 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4968 uint32_t vertex_count,
4969 bool use_opaque)
4970 {
4971 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
4972 radeon_emit(cmd_buffer->cs, vertex_count);
4973 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
4974 S_0287F0_USE_OPAQUE(use_opaque));
4975 }
4976
4977 static void
4978 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
4979 uint64_t index_va,
4980 uint32_t index_count)
4981 {
4982 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
4983 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
4984 radeon_emit(cmd_buffer->cs, index_va);
4985 radeon_emit(cmd_buffer->cs, index_va >> 32);
4986 radeon_emit(cmd_buffer->cs, index_count);
4987 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
4988 }
4989
4990 static void
4991 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4992 bool indexed,
4993 uint32_t draw_count,
4994 uint64_t count_va,
4995 uint32_t stride)
4996 {
4997 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4998 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
4999 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
5000 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id;
5001 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
5002 bool predicating = cmd_buffer->state.predicating;
5003 assert(base_reg);
5004
5005 /* just reset draw state for vertex data */
5006 cmd_buffer->state.last_first_instance = -1;
5007 cmd_buffer->state.last_num_instances = -1;
5008 cmd_buffer->state.last_vertex_offset = -1;
5009
5010 if (draw_count == 1 && !count_va && !draw_id_enable) {
5011 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
5012 PKT3_DRAW_INDIRECT, 3, predicating));
5013 radeon_emit(cs, 0);
5014 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
5015 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
5016 radeon_emit(cs, di_src_sel);
5017 } else {
5018 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
5019 PKT3_DRAW_INDIRECT_MULTI,
5020 8, predicating));
5021 radeon_emit(cs, 0);
5022 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
5023 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
5024 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
5025 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
5026 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
5027 radeon_emit(cs, draw_count); /* count */
5028 radeon_emit(cs, count_va); /* count_addr */
5029 radeon_emit(cs, count_va >> 32);
5030 radeon_emit(cs, stride); /* stride */
5031 radeon_emit(cs, di_src_sel);
5032 }
5033 }
5034
5035 static void
5036 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
5037 const struct radv_draw_info *info)
5038 {
5039 struct radv_cmd_state *state = &cmd_buffer->state;
5040 struct radeon_winsys *ws = cmd_buffer->device->ws;
5041 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5042
5043 if (info->indirect) {
5044 uint64_t va = radv_buffer_get_va(info->indirect->bo);
5045 uint64_t count_va = 0;
5046
5047 va += info->indirect->offset + info->indirect_offset;
5048
5049 radv_cs_add_buffer(ws, cs, info->indirect->bo);
5050
5051 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
5052 radeon_emit(cs, 1);
5053 radeon_emit(cs, va);
5054 radeon_emit(cs, va >> 32);
5055
5056 if (info->count_buffer) {
5057 count_va = radv_buffer_get_va(info->count_buffer->bo);
5058 count_va += info->count_buffer->offset +
5059 info->count_buffer_offset;
5060
5061 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
5062 }
5063
5064 if (!state->subpass->view_mask) {
5065 radv_cs_emit_indirect_draw_packet(cmd_buffer,
5066 info->indexed,
5067 info->count,
5068 count_va,
5069 info->stride);
5070 } else {
5071 unsigned i;
5072 for_each_bit(i, state->subpass->view_mask) {
5073 radv_emit_view_index(cmd_buffer, i);
5074
5075 radv_cs_emit_indirect_draw_packet(cmd_buffer,
5076 info->indexed,
5077 info->count,
5078 count_va,
5079 info->stride);
5080 }
5081 }
5082 } else {
5083 assert(state->pipeline->graphics.vtx_base_sgpr);
5084
5085 if (info->vertex_offset != state->last_vertex_offset ||
5086 info->first_instance != state->last_first_instance) {
5087 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
5088 state->pipeline->graphics.vtx_emit_num);
5089
5090 radeon_emit(cs, info->vertex_offset);
5091 radeon_emit(cs, info->first_instance);
5092 if (state->pipeline->graphics.vtx_emit_num == 3)
5093 radeon_emit(cs, 0);
5094 state->last_first_instance = info->first_instance;
5095 state->last_vertex_offset = info->vertex_offset;
5096 }
5097
5098 if (state->last_num_instances != info->instance_count) {
5099 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
5100 radeon_emit(cs, info->instance_count);
5101 state->last_num_instances = info->instance_count;
5102 }
5103
5104 if (info->indexed) {
5105 int index_size = radv_get_vgt_index_size(state->index_type);
5106 uint64_t index_va;
5107
5108 /* Skip draw calls with 0-sized index buffers. They
5109 * cause a hang on some chips, like Navi10-14.
5110 */
5111 if (!cmd_buffer->state.max_index_count)
5112 return;
5113
5114 index_va = state->index_va;
5115 index_va += info->first_index * index_size;
5116
5117 if (!state->subpass->view_mask) {
5118 radv_cs_emit_draw_indexed_packet(cmd_buffer,
5119 index_va,
5120 info->count);
5121 } else {
5122 unsigned i;
5123 for_each_bit(i, state->subpass->view_mask) {
5124 radv_emit_view_index(cmd_buffer, i);
5125
5126 radv_cs_emit_draw_indexed_packet(cmd_buffer,
5127 index_va,
5128 info->count);
5129 }
5130 }
5131 } else {
5132 if (!state->subpass->view_mask) {
5133 radv_cs_emit_draw_packet(cmd_buffer,
5134 info->count,
5135 !!info->strmout_buffer);
5136 } else {
5137 unsigned i;
5138 for_each_bit(i, state->subpass->view_mask) {
5139 radv_emit_view_index(cmd_buffer, i);
5140
5141 radv_cs_emit_draw_packet(cmd_buffer,
5142 info->count,
5143 !!info->strmout_buffer);
5144 }
5145 }
5146 }
5147 }
5148 }
5149
5150 /*
5151 * Vega and raven have a bug which triggers if there are multiple context
5152 * register contexts active at the same time with different scissor values.
5153 *
5154 * There are two possible workarounds:
5155 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
5156 * there is only ever 1 active set of scissor values at the same time.
5157 *
5158 * 2) Whenever the hardware switches contexts we have to set the scissor
5159 * registers again even if it is a noop. That way the new context gets
5160 * the correct scissor values.
5161 *
5162 * This implements option 2. radv_need_late_scissor_emission needs to
5163 * return true on affected HW if radv_emit_all_graphics_states sets
5164 * any context registers.
5165 */
5166 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
5167 const struct radv_draw_info *info)
5168 {
5169 struct radv_cmd_state *state = &cmd_buffer->state;
5170
5171 if (!cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
5172 return false;
5173
5174 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
5175 return true;
5176
5177 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
5178
5179 /* Index, vertex and streamout buffers don't change context regs, and
5180 * pipeline is already handled.
5181 */
5182 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
5183 RADV_CMD_DIRTY_VERTEX_BUFFER |
5184 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
5185 RADV_CMD_DIRTY_PIPELINE);
5186
5187 if (cmd_buffer->state.dirty & used_states)
5188 return true;
5189
5190 uint32_t primitive_reset_index =
5191 radv_get_primitive_reset_index(cmd_buffer);
5192
5193 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
5194 primitive_reset_index != state->last_primitive_reset_index)
5195 return true;
5196
5197 return false;
5198 }
5199
5200 static void
5201 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
5202 const struct radv_draw_info *info)
5203 {
5204 bool late_scissor_emission;
5205
5206 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
5207 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
5208 radv_emit_rbplus_state(cmd_buffer);
5209
5210 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
5211 radv_emit_graphics_pipeline(cmd_buffer);
5212
5213 /* This should be before the cmd_buffer->state.dirty is cleared
5214 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
5215 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
5216 late_scissor_emission =
5217 radv_need_late_scissor_emission(cmd_buffer, info);
5218
5219 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
5220 radv_emit_framebuffer_state(cmd_buffer);
5221
5222 if (info->indexed) {
5223 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
5224 radv_emit_index_buffer(cmd_buffer, info->indirect);
5225 } else {
5226 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
5227 * so the state must be re-emitted before the next indexed
5228 * draw.
5229 */
5230 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
5231 cmd_buffer->state.last_index_type = -1;
5232 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
5233 }
5234 }
5235
5236 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
5237
5238 radv_emit_draw_registers(cmd_buffer, info);
5239
5240 if (late_scissor_emission)
5241 radv_emit_scissor(cmd_buffer);
5242 }
5243
5244 static void
5245 radv_draw(struct radv_cmd_buffer *cmd_buffer,
5246 const struct radv_draw_info *info)
5247 {
5248 struct radeon_info *rad_info =
5249 &cmd_buffer->device->physical_device->rad_info;
5250 bool has_prefetch =
5251 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
5252 bool pipeline_is_dirty =
5253 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
5254 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
5255
5256 ASSERTED unsigned cdw_max =
5257 radeon_check_space(cmd_buffer->device->ws,
5258 cmd_buffer->cs, 4096);
5259
5260 if (likely(!info->indirect)) {
5261 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
5262 * no workaround for indirect draws, but we can at least skip
5263 * direct draws.
5264 */
5265 if (unlikely(!info->instance_count))
5266 return;
5267
5268 /* Handle count == 0. */
5269 if (unlikely(!info->count && !info->strmout_buffer))
5270 return;
5271 }
5272
5273 radv_describe_draw(cmd_buffer);
5274
5275 /* Use optimal packet order based on whether we need to sync the
5276 * pipeline.
5277 */
5278 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5279 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5280 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
5281 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
5282 /* If we have to wait for idle, set all states first, so that
5283 * all SET packets are processed in parallel with previous draw
5284 * calls. Then upload descriptors, set shader pointers, and
5285 * draw, and prefetch at the end. This ensures that the time
5286 * the CUs are idle is very short. (there are only SET_SH
5287 * packets between the wait and the draw)
5288 */
5289 radv_emit_all_graphics_states(cmd_buffer, info);
5290 si_emit_cache_flush(cmd_buffer);
5291 /* <-- CUs are idle here --> */
5292
5293 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
5294
5295 radv_emit_draw_packets(cmd_buffer, info);
5296 /* <-- CUs are busy here --> */
5297
5298 /* Start prefetches after the draw has been started. Both will
5299 * run in parallel, but starting the draw first is more
5300 * important.
5301 */
5302 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
5303 radv_emit_prefetch_L2(cmd_buffer,
5304 cmd_buffer->state.pipeline, false);
5305 }
5306 } else {
5307 /* If we don't wait for idle, start prefetches first, then set
5308 * states, and draw at the end.
5309 */
5310 si_emit_cache_flush(cmd_buffer);
5311
5312 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
5313 /* Only prefetch the vertex shader and VBO descriptors
5314 * in order to start the draw as soon as possible.
5315 */
5316 radv_emit_prefetch_L2(cmd_buffer,
5317 cmd_buffer->state.pipeline, true);
5318 }
5319
5320 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
5321
5322 radv_emit_all_graphics_states(cmd_buffer, info);
5323 radv_emit_draw_packets(cmd_buffer, info);
5324
5325 /* Prefetch the remaining shaders after the draw has been
5326 * started.
5327 */
5328 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
5329 radv_emit_prefetch_L2(cmd_buffer,
5330 cmd_buffer->state.pipeline, false);
5331 }
5332 }
5333
5334 /* Workaround for a VGT hang when streamout is enabled.
5335 * It must be done after drawing.
5336 */
5337 if (cmd_buffer->state.streamout.streamout_enabled &&
5338 (rad_info->family == CHIP_HAWAII ||
5339 rad_info->family == CHIP_TONGA ||
5340 rad_info->family == CHIP_FIJI)) {
5341 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
5342 }
5343
5344 assert(cmd_buffer->cs->cdw <= cdw_max);
5345 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
5346 }
5347
5348 void radv_CmdDraw(
5349 VkCommandBuffer commandBuffer,
5350 uint32_t vertexCount,
5351 uint32_t instanceCount,
5352 uint32_t firstVertex,
5353 uint32_t firstInstance)
5354 {
5355 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5356 struct radv_draw_info info = {};
5357
5358 info.count = vertexCount;
5359 info.instance_count = instanceCount;
5360 info.first_instance = firstInstance;
5361 info.vertex_offset = firstVertex;
5362
5363 radv_draw(cmd_buffer, &info);
5364 }
5365
5366 void radv_CmdDrawIndexed(
5367 VkCommandBuffer commandBuffer,
5368 uint32_t indexCount,
5369 uint32_t instanceCount,
5370 uint32_t firstIndex,
5371 int32_t vertexOffset,
5372 uint32_t firstInstance)
5373 {
5374 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5375 struct radv_draw_info info = {};
5376
5377 info.indexed = true;
5378 info.count = indexCount;
5379 info.instance_count = instanceCount;
5380 info.first_index = firstIndex;
5381 info.vertex_offset = vertexOffset;
5382 info.first_instance = firstInstance;
5383
5384 radv_draw(cmd_buffer, &info);
5385 }
5386
5387 void radv_CmdDrawIndirect(
5388 VkCommandBuffer commandBuffer,
5389 VkBuffer _buffer,
5390 VkDeviceSize offset,
5391 uint32_t drawCount,
5392 uint32_t stride)
5393 {
5394 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5395 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5396 struct radv_draw_info info = {};
5397
5398 info.count = drawCount;
5399 info.indirect = buffer;
5400 info.indirect_offset = offset;
5401 info.stride = stride;
5402
5403 radv_draw(cmd_buffer, &info);
5404 }
5405
5406 void radv_CmdDrawIndexedIndirect(
5407 VkCommandBuffer commandBuffer,
5408 VkBuffer _buffer,
5409 VkDeviceSize offset,
5410 uint32_t drawCount,
5411 uint32_t stride)
5412 {
5413 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5414 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5415 struct radv_draw_info info = {};
5416
5417 info.indexed = true;
5418 info.count = drawCount;
5419 info.indirect = buffer;
5420 info.indirect_offset = offset;
5421 info.stride = stride;
5422
5423 radv_draw(cmd_buffer, &info);
5424 }
5425
5426 void radv_CmdDrawIndirectCount(
5427 VkCommandBuffer commandBuffer,
5428 VkBuffer _buffer,
5429 VkDeviceSize offset,
5430 VkBuffer _countBuffer,
5431 VkDeviceSize countBufferOffset,
5432 uint32_t maxDrawCount,
5433 uint32_t stride)
5434 {
5435 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5436 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5437 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
5438 struct radv_draw_info info = {};
5439
5440 info.count = maxDrawCount;
5441 info.indirect = buffer;
5442 info.indirect_offset = offset;
5443 info.count_buffer = count_buffer;
5444 info.count_buffer_offset = countBufferOffset;
5445 info.stride = stride;
5446
5447 radv_draw(cmd_buffer, &info);
5448 }
5449
5450 void radv_CmdDrawIndexedIndirectCount(
5451 VkCommandBuffer commandBuffer,
5452 VkBuffer _buffer,
5453 VkDeviceSize offset,
5454 VkBuffer _countBuffer,
5455 VkDeviceSize countBufferOffset,
5456 uint32_t maxDrawCount,
5457 uint32_t stride)
5458 {
5459 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5460 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5461 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
5462 struct radv_draw_info info = {};
5463
5464 info.indexed = true;
5465 info.count = maxDrawCount;
5466 info.indirect = buffer;
5467 info.indirect_offset = offset;
5468 info.count_buffer = count_buffer;
5469 info.count_buffer_offset = countBufferOffset;
5470 info.stride = stride;
5471
5472 radv_draw(cmd_buffer, &info);
5473 }
5474
5475 struct radv_dispatch_info {
5476 /**
5477 * Determine the layout of the grid (in block units) to be used.
5478 */
5479 uint32_t blocks[3];
5480
5481 /**
5482 * A starting offset for the grid. If unaligned is set, the offset
5483 * must still be aligned.
5484 */
5485 uint32_t offsets[3];
5486 /**
5487 * Whether it's an unaligned compute dispatch.
5488 */
5489 bool unaligned;
5490
5491 /**
5492 * Indirect compute parameters resource.
5493 */
5494 struct radv_buffer *indirect;
5495 uint64_t indirect_offset;
5496 };
5497
5498 static void
5499 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
5500 const struct radv_dispatch_info *info)
5501 {
5502 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
5503 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
5504 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
5505 struct radeon_winsys *ws = cmd_buffer->device->ws;
5506 bool predicating = cmd_buffer->state.predicating;
5507 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5508 struct radv_userdata_info *loc;
5509
5510 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
5511 AC_UD_CS_GRID_SIZE);
5512
5513 ASSERTED unsigned cdw_max = radeon_check_space(ws, cs, 25);
5514
5515 if (compute_shader->info.wave_size == 32) {
5516 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
5517 dispatch_initiator |= S_00B800_CS_W32_EN(1);
5518 }
5519
5520 if (info->indirect) {
5521 uint64_t va = radv_buffer_get_va(info->indirect->bo);
5522
5523 va += info->indirect->offset + info->indirect_offset;
5524
5525 radv_cs_add_buffer(ws, cs, info->indirect->bo);
5526
5527 if (loc->sgpr_idx != -1) {
5528 for (unsigned i = 0; i < 3; ++i) {
5529 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5530 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5531 COPY_DATA_DST_SEL(COPY_DATA_REG));
5532 radeon_emit(cs, (va + 4 * i));
5533 radeon_emit(cs, (va + 4 * i) >> 32);
5534 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
5535 + loc->sgpr_idx * 4) >> 2) + i);
5536 radeon_emit(cs, 0);
5537 }
5538 }
5539
5540 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
5541 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
5542 PKT3_SHADER_TYPE_S(1));
5543 radeon_emit(cs, va);
5544 radeon_emit(cs, va >> 32);
5545 radeon_emit(cs, dispatch_initiator);
5546 } else {
5547 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
5548 PKT3_SHADER_TYPE_S(1));
5549 radeon_emit(cs, 1);
5550 radeon_emit(cs, va);
5551 radeon_emit(cs, va >> 32);
5552
5553 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
5554 PKT3_SHADER_TYPE_S(1));
5555 radeon_emit(cs, 0);
5556 radeon_emit(cs, dispatch_initiator);
5557 }
5558 } else {
5559 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
5560 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
5561
5562 if (info->unaligned) {
5563 unsigned *cs_block_size = compute_shader->info.cs.block_size;
5564 unsigned remainder[3];
5565
5566 /* If aligned, these should be an entire block size,
5567 * not 0.
5568 */
5569 remainder[0] = blocks[0] + cs_block_size[0] -
5570 align_u32_npot(blocks[0], cs_block_size[0]);
5571 remainder[1] = blocks[1] + cs_block_size[1] -
5572 align_u32_npot(blocks[1], cs_block_size[1]);
5573 remainder[2] = blocks[2] + cs_block_size[2] -
5574 align_u32_npot(blocks[2], cs_block_size[2]);
5575
5576 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
5577 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
5578 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
5579
5580 for(unsigned i = 0; i < 3; ++i) {
5581 assert(offsets[i] % cs_block_size[i] == 0);
5582 offsets[i] /= cs_block_size[i];
5583 }
5584
5585 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
5586 radeon_emit(cs,
5587 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
5588 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
5589 radeon_emit(cs,
5590 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
5591 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
5592 radeon_emit(cs,
5593 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
5594 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
5595
5596 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
5597 }
5598
5599 if (loc->sgpr_idx != -1) {
5600 assert(loc->num_sgprs == 3);
5601
5602 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
5603 loc->sgpr_idx * 4, 3);
5604 radeon_emit(cs, blocks[0]);
5605 radeon_emit(cs, blocks[1]);
5606 radeon_emit(cs, blocks[2]);
5607 }
5608
5609 if (offsets[0] || offsets[1] || offsets[2]) {
5610 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
5611 radeon_emit(cs, offsets[0]);
5612 radeon_emit(cs, offsets[1]);
5613 radeon_emit(cs, offsets[2]);
5614
5615 /* The blocks in the packet are not counts but end values. */
5616 for (unsigned i = 0; i < 3; ++i)
5617 blocks[i] += offsets[i];
5618 } else {
5619 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
5620 }
5621
5622 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
5623 PKT3_SHADER_TYPE_S(1));
5624 radeon_emit(cs, blocks[0]);
5625 radeon_emit(cs, blocks[1]);
5626 radeon_emit(cs, blocks[2]);
5627 radeon_emit(cs, dispatch_initiator);
5628 }
5629
5630 assert(cmd_buffer->cs->cdw <= cdw_max);
5631 }
5632
5633 static void
5634 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
5635 {
5636 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
5637 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
5638 }
5639
5640 static void
5641 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
5642 const struct radv_dispatch_info *info)
5643 {
5644 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
5645 bool has_prefetch =
5646 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
5647 bool pipeline_is_dirty = pipeline &&
5648 pipeline != cmd_buffer->state.emitted_compute_pipeline;
5649
5650 radv_describe_dispatch(cmd_buffer, 8, 8, 8);
5651
5652 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5653 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5654 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
5655 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
5656 /* If we have to wait for idle, set all states first, so that
5657 * all SET packets are processed in parallel with previous draw
5658 * calls. Then upload descriptors, set shader pointers, and
5659 * dispatch, and prefetch at the end. This ensures that the
5660 * time the CUs are idle is very short. (there are only SET_SH
5661 * packets between the wait and the draw)
5662 */
5663 radv_emit_compute_pipeline(cmd_buffer);
5664 si_emit_cache_flush(cmd_buffer);
5665 /* <-- CUs are idle here --> */
5666
5667 radv_upload_compute_shader_descriptors(cmd_buffer);
5668
5669 radv_emit_dispatch_packets(cmd_buffer, info);
5670 /* <-- CUs are busy here --> */
5671
5672 /* Start prefetches after the dispatch has been started. Both
5673 * will run in parallel, but starting the dispatch first is
5674 * more important.
5675 */
5676 if (has_prefetch && pipeline_is_dirty) {
5677 radv_emit_shader_prefetch(cmd_buffer,
5678 pipeline->shaders[MESA_SHADER_COMPUTE]);
5679 }
5680 } else {
5681 /* If we don't wait for idle, start prefetches first, then set
5682 * states, and dispatch at the end.
5683 */
5684 si_emit_cache_flush(cmd_buffer);
5685
5686 if (has_prefetch && pipeline_is_dirty) {
5687 radv_emit_shader_prefetch(cmd_buffer,
5688 pipeline->shaders[MESA_SHADER_COMPUTE]);
5689 }
5690
5691 radv_upload_compute_shader_descriptors(cmd_buffer);
5692
5693 radv_emit_compute_pipeline(cmd_buffer);
5694 radv_emit_dispatch_packets(cmd_buffer, info);
5695 }
5696
5697 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
5698 }
5699
5700 void radv_CmdDispatchBase(
5701 VkCommandBuffer commandBuffer,
5702 uint32_t base_x,
5703 uint32_t base_y,
5704 uint32_t base_z,
5705 uint32_t x,
5706 uint32_t y,
5707 uint32_t z)
5708 {
5709 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5710 struct radv_dispatch_info info = {};
5711
5712 info.blocks[0] = x;
5713 info.blocks[1] = y;
5714 info.blocks[2] = z;
5715
5716 info.offsets[0] = base_x;
5717 info.offsets[1] = base_y;
5718 info.offsets[2] = base_z;
5719 radv_dispatch(cmd_buffer, &info);
5720 }
5721
5722 void radv_CmdDispatch(
5723 VkCommandBuffer commandBuffer,
5724 uint32_t x,
5725 uint32_t y,
5726 uint32_t z)
5727 {
5728 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
5729 }
5730
5731 void radv_CmdDispatchIndirect(
5732 VkCommandBuffer commandBuffer,
5733 VkBuffer _buffer,
5734 VkDeviceSize offset)
5735 {
5736 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5737 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5738 struct radv_dispatch_info info = {};
5739
5740 info.indirect = buffer;
5741 info.indirect_offset = offset;
5742
5743 radv_dispatch(cmd_buffer, &info);
5744 }
5745
5746 void radv_unaligned_dispatch(
5747 struct radv_cmd_buffer *cmd_buffer,
5748 uint32_t x,
5749 uint32_t y,
5750 uint32_t z)
5751 {
5752 struct radv_dispatch_info info = {};
5753
5754 info.blocks[0] = x;
5755 info.blocks[1] = y;
5756 info.blocks[2] = z;
5757 info.unaligned = 1;
5758
5759 radv_dispatch(cmd_buffer, &info);
5760 }
5761
5762 void
5763 radv_cmd_buffer_end_render_pass(struct radv_cmd_buffer *cmd_buffer)
5764 {
5765 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
5766 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
5767
5768 cmd_buffer->state.pass = NULL;
5769 cmd_buffer->state.subpass = NULL;
5770 cmd_buffer->state.attachments = NULL;
5771 cmd_buffer->state.framebuffer = NULL;
5772 cmd_buffer->state.subpass_sample_locs = NULL;
5773 }
5774
5775 void radv_CmdEndRenderPass(
5776 VkCommandBuffer commandBuffer)
5777 {
5778 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5779
5780 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
5781
5782 radv_cmd_buffer_end_subpass(cmd_buffer);
5783
5784 radv_cmd_buffer_end_render_pass(cmd_buffer);
5785 }
5786
5787 void radv_CmdEndRenderPass2(
5788 VkCommandBuffer commandBuffer,
5789 const VkSubpassEndInfo* pSubpassEndInfo)
5790 {
5791 radv_CmdEndRenderPass(commandBuffer);
5792 }
5793
5794 /*
5795 * For HTILE we have the following interesting clear words:
5796 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
5797 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
5798 * 0xfffffff0: Clear depth to 1.0
5799 * 0x00000000: Clear depth to 0.0
5800 */
5801 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
5802 struct radv_image *image,
5803 const VkImageSubresourceRange *range)
5804 {
5805 assert(range->baseMipLevel == 0);
5806 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
5807 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
5808 struct radv_cmd_state *state = &cmd_buffer->state;
5809 uint32_t htile_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
5810 VkClearDepthStencilValue value = {};
5811 struct radv_barrier_data barrier = {};
5812
5813 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5814 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5815
5816 barrier.layout_transitions.init_mask_ram = 1;
5817 radv_describe_layout_transition(cmd_buffer, &barrier);
5818
5819 state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, htile_value);
5820
5821 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5822
5823 if (vk_format_is_stencil(image->vk_format))
5824 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
5825
5826 radv_set_ds_clear_metadata(cmd_buffer, image, range, value, aspects);
5827
5828 if (radv_image_is_tc_compat_htile(image)) {
5829 /* Initialize the TC-compat metada value to 0 because by
5830 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
5831 * need have to conditionally update its value when performing
5832 * a fast depth clear.
5833 */
5834 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, range, 0);
5835 }
5836 }
5837
5838 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
5839 struct radv_image *image,
5840 VkImageLayout src_layout,
5841 bool src_render_loop,
5842 VkImageLayout dst_layout,
5843 bool dst_render_loop,
5844 unsigned src_queue_mask,
5845 unsigned dst_queue_mask,
5846 const VkImageSubresourceRange *range,
5847 struct radv_sample_locations_state *sample_locs)
5848 {
5849 if (!radv_image_has_htile(image))
5850 return;
5851
5852 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5853 radv_initialize_htile(cmd_buffer, image, range);
5854 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5855 radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5856 radv_initialize_htile(cmd_buffer, image, range);
5857 } else if (radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5858 !radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5859 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5860 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5861
5862 radv_decompress_depth_stencil(cmd_buffer, image, range,
5863 sample_locs);
5864
5865 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5866 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5867 }
5868 }
5869
5870 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
5871 struct radv_image *image,
5872 const VkImageSubresourceRange *range,
5873 uint32_t value)
5874 {
5875 struct radv_cmd_state *state = &cmd_buffer->state;
5876 struct radv_barrier_data barrier = {};
5877
5878 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5879 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5880
5881 barrier.layout_transitions.init_mask_ram = 1;
5882 radv_describe_layout_transition(cmd_buffer, &barrier);
5883
5884 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, range, value);
5885
5886 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5887 }
5888
5889 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
5890 struct radv_image *image,
5891 const VkImageSubresourceRange *range)
5892 {
5893 struct radv_cmd_state *state = &cmd_buffer->state;
5894 static const uint32_t fmask_clear_values[4] = {
5895 0x00000000,
5896 0x02020202,
5897 0xE4E4E4E4,
5898 0x76543210
5899 };
5900 uint32_t log2_samples = util_logbase2(image->info.samples);
5901 uint32_t value = fmask_clear_values[log2_samples];
5902 struct radv_barrier_data barrier = {};
5903
5904 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5905 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5906
5907 barrier.layout_transitions.init_mask_ram = 1;
5908 radv_describe_layout_transition(cmd_buffer, &barrier);
5909
5910 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, range, value);
5911
5912 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5913 }
5914
5915 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
5916 struct radv_image *image,
5917 const VkImageSubresourceRange *range, uint32_t value)
5918 {
5919 struct radv_cmd_state *state = &cmd_buffer->state;
5920 struct radv_barrier_data barrier = {};
5921 unsigned size = 0;
5922
5923 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5924 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5925
5926 barrier.layout_transitions.init_mask_ram = 1;
5927 radv_describe_layout_transition(cmd_buffer, &barrier);
5928
5929 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
5930
5931 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) {
5932 /* When DCC is enabled with mipmaps, some levels might not
5933 * support fast clears and we have to initialize them as "fully
5934 * expanded".
5935 */
5936 /* Compute the size of all fast clearable DCC levels. */
5937 for (unsigned i = 0; i < image->planes[0].surface.num_dcc_levels; i++) {
5938 struct legacy_surf_level *surf_level =
5939 &image->planes[0].surface.u.legacy.level[i];
5940 unsigned dcc_fast_clear_size =
5941 surf_level->dcc_slice_fast_clear_size * image->info.array_size;
5942
5943 if (!dcc_fast_clear_size)
5944 break;
5945
5946 size = surf_level->dcc_offset + dcc_fast_clear_size;
5947 }
5948
5949 /* Initialize the mipmap levels without DCC. */
5950 if (size != image->planes[0].surface.dcc_size) {
5951 state->flush_bits |=
5952 radv_fill_buffer(cmd_buffer, image->bo,
5953 image->offset + image->planes[0].surface.dcc_offset + size,
5954 image->planes[0].surface.dcc_size - size,
5955 0xffffffff);
5956 }
5957 }
5958
5959 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5960 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5961 }
5962
5963 /**
5964 * Initialize DCC/FMASK/CMASK metadata for a color image.
5965 */
5966 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
5967 struct radv_image *image,
5968 VkImageLayout src_layout,
5969 bool src_render_loop,
5970 VkImageLayout dst_layout,
5971 bool dst_render_loop,
5972 unsigned src_queue_mask,
5973 unsigned dst_queue_mask,
5974 const VkImageSubresourceRange *range)
5975 {
5976 if (radv_image_has_cmask(image)) {
5977 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5978
5979 /* TODO: clarify this. */
5980 if (radv_image_has_fmask(image)) {
5981 value = 0xccccccccu;
5982 }
5983
5984 radv_initialise_cmask(cmd_buffer, image, range, value);
5985 }
5986
5987 if (radv_image_has_fmask(image)) {
5988 radv_initialize_fmask(cmd_buffer, image, range);
5989 }
5990
5991 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5992 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5993 bool need_decompress_pass = false;
5994
5995 if (radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout,
5996 dst_render_loop,
5997 dst_queue_mask)) {
5998 value = 0x20202020u;
5999 need_decompress_pass = true;
6000 }
6001
6002 radv_initialize_dcc(cmd_buffer, image, range, value);
6003
6004 radv_update_fce_metadata(cmd_buffer, image, range,
6005 need_decompress_pass);
6006 }
6007
6008 if (radv_image_has_cmask(image) ||
6009 radv_dcc_enabled(image, range->baseMipLevel)) {
6010 uint32_t color_values[2] = {};
6011 radv_set_color_clear_metadata(cmd_buffer, image, range,
6012 color_values);
6013 }
6014 }
6015
6016 /**
6017 * Handle color image transitions for DCC/FMASK/CMASK.
6018 */
6019 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
6020 struct radv_image *image,
6021 VkImageLayout src_layout,
6022 bool src_render_loop,
6023 VkImageLayout dst_layout,
6024 bool dst_render_loop,
6025 unsigned src_queue_mask,
6026 unsigned dst_queue_mask,
6027 const VkImageSubresourceRange *range)
6028 {
6029 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
6030 radv_init_color_image_metadata(cmd_buffer, image,
6031 src_layout, src_render_loop,
6032 dst_layout, dst_render_loop,
6033 src_queue_mask, dst_queue_mask,
6034 range);
6035 return;
6036 }
6037
6038 if (radv_dcc_enabled(image, range->baseMipLevel)) {
6039 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
6040 radv_initialize_dcc(cmd_buffer, image, range, 0xffffffffu);
6041 } else if (radv_layout_dcc_compressed(cmd_buffer->device, image, src_layout, src_render_loop, src_queue_mask) &&
6042 !radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout, dst_render_loop, dst_queue_mask)) {
6043 radv_decompress_dcc(cmd_buffer, image, range);
6044 } else if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
6045 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
6046 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
6047 }
6048 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
6049 bool fce_eliminate = false, fmask_expand = false;
6050
6051 if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
6052 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
6053 fce_eliminate = true;
6054 }
6055
6056 if (radv_image_has_fmask(image)) {
6057 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
6058 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
6059 /* A FMASK decompress is required before doing
6060 * a MSAA decompress using FMASK.
6061 */
6062 fmask_expand = true;
6063 }
6064 }
6065
6066 if (fce_eliminate || fmask_expand)
6067 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
6068
6069 if (fmask_expand) {
6070 struct radv_barrier_data barrier = {};
6071 barrier.layout_transitions.fmask_color_expand = 1;
6072 radv_describe_layout_transition(cmd_buffer, &barrier);
6073
6074 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
6075 }
6076 }
6077 }
6078
6079 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
6080 struct radv_image *image,
6081 VkImageLayout src_layout,
6082 bool src_render_loop,
6083 VkImageLayout dst_layout,
6084 bool dst_render_loop,
6085 uint32_t src_family,
6086 uint32_t dst_family,
6087 const VkImageSubresourceRange *range,
6088 struct radv_sample_locations_state *sample_locs)
6089 {
6090 if (image->exclusive && src_family != dst_family) {
6091 /* This is an acquire or a release operation and there will be
6092 * a corresponding release/acquire. Do the transition in the
6093 * most flexible queue. */
6094
6095 assert(src_family == cmd_buffer->queue_family_index ||
6096 dst_family == cmd_buffer->queue_family_index);
6097
6098 if (src_family == VK_QUEUE_FAMILY_EXTERNAL ||
6099 src_family == VK_QUEUE_FAMILY_FOREIGN_EXT)
6100 return;
6101
6102 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
6103 return;
6104
6105 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
6106 (src_family == RADV_QUEUE_GENERAL ||
6107 dst_family == RADV_QUEUE_GENERAL))
6108 return;
6109 }
6110
6111 if (src_layout == dst_layout)
6112 return;
6113
6114 unsigned src_queue_mask =
6115 radv_image_queue_family_mask(image, src_family,
6116 cmd_buffer->queue_family_index);
6117 unsigned dst_queue_mask =
6118 radv_image_queue_family_mask(image, dst_family,
6119 cmd_buffer->queue_family_index);
6120
6121 if (vk_format_is_depth(image->vk_format)) {
6122 radv_handle_depth_image_transition(cmd_buffer, image,
6123 src_layout, src_render_loop,
6124 dst_layout, dst_render_loop,
6125 src_queue_mask, dst_queue_mask,
6126 range, sample_locs);
6127 } else {
6128 radv_handle_color_image_transition(cmd_buffer, image,
6129 src_layout, src_render_loop,
6130 dst_layout, dst_render_loop,
6131 src_queue_mask, dst_queue_mask,
6132 range);
6133 }
6134 }
6135
6136 struct radv_barrier_info {
6137 enum rgp_barrier_reason reason;
6138 uint32_t eventCount;
6139 const VkEvent *pEvents;
6140 VkPipelineStageFlags srcStageMask;
6141 VkPipelineStageFlags dstStageMask;
6142 };
6143
6144 static void
6145 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
6146 uint32_t memoryBarrierCount,
6147 const VkMemoryBarrier *pMemoryBarriers,
6148 uint32_t bufferMemoryBarrierCount,
6149 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
6150 uint32_t imageMemoryBarrierCount,
6151 const VkImageMemoryBarrier *pImageMemoryBarriers,
6152 const struct radv_barrier_info *info)
6153 {
6154 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6155 enum radv_cmd_flush_bits src_flush_bits = 0;
6156 enum radv_cmd_flush_bits dst_flush_bits = 0;
6157
6158 radv_describe_barrier_start(cmd_buffer, info->reason);
6159
6160 for (unsigned i = 0; i < info->eventCount; ++i) {
6161 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
6162 uint64_t va = radv_buffer_get_va(event->bo);
6163
6164 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
6165
6166 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
6167
6168 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
6169 assert(cmd_buffer->cs->cdw <= cdw_max);
6170 }
6171
6172 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
6173 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
6174 NULL);
6175 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
6176 NULL);
6177 }
6178
6179 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
6180 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
6181 NULL);
6182 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
6183 NULL);
6184 }
6185
6186 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
6187 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
6188
6189 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
6190 image);
6191 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
6192 image);
6193 }
6194
6195 /* The Vulkan spec 1.1.98 says:
6196 *
6197 * "An execution dependency with only
6198 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
6199 * will only prevent that stage from executing in subsequently
6200 * submitted commands. As this stage does not perform any actual
6201 * execution, this is not observable - in effect, it does not delay
6202 * processing of subsequent commands. Similarly an execution dependency
6203 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
6204 * will effectively not wait for any prior commands to complete."
6205 */
6206 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
6207 radv_stage_flush(cmd_buffer, info->srcStageMask);
6208 cmd_buffer->state.flush_bits |= src_flush_bits;
6209
6210 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
6211 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
6212
6213 const struct VkSampleLocationsInfoEXT *sample_locs_info =
6214 vk_find_struct_const(pImageMemoryBarriers[i].pNext,
6215 SAMPLE_LOCATIONS_INFO_EXT);
6216 struct radv_sample_locations_state sample_locations = {};
6217
6218 if (sample_locs_info) {
6219 assert(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
6220 sample_locations.per_pixel = sample_locs_info->sampleLocationsPerPixel;
6221 sample_locations.grid_size = sample_locs_info->sampleLocationGridSize;
6222 sample_locations.count = sample_locs_info->sampleLocationsCount;
6223 typed_memcpy(&sample_locations.locations[0],
6224 sample_locs_info->pSampleLocations,
6225 sample_locs_info->sampleLocationsCount);
6226 }
6227
6228 radv_handle_image_transition(cmd_buffer, image,
6229 pImageMemoryBarriers[i].oldLayout,
6230 false, /* Outside of a renderpass we are never in a renderloop */
6231 pImageMemoryBarriers[i].newLayout,
6232 false, /* Outside of a renderpass we are never in a renderloop */
6233 pImageMemoryBarriers[i].srcQueueFamilyIndex,
6234 pImageMemoryBarriers[i].dstQueueFamilyIndex,
6235 &pImageMemoryBarriers[i].subresourceRange,
6236 sample_locs_info ? &sample_locations : NULL);
6237 }
6238
6239 /* Make sure CP DMA is idle because the driver might have performed a
6240 * DMA operation for copying or filling buffers/images.
6241 */
6242 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
6243 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
6244 si_cp_dma_wait_for_idle(cmd_buffer);
6245
6246 cmd_buffer->state.flush_bits |= dst_flush_bits;
6247
6248 radv_describe_barrier_end(cmd_buffer);
6249 }
6250
6251 void radv_CmdPipelineBarrier(
6252 VkCommandBuffer commandBuffer,
6253 VkPipelineStageFlags srcStageMask,
6254 VkPipelineStageFlags destStageMask,
6255 VkBool32 byRegion,
6256 uint32_t memoryBarrierCount,
6257 const VkMemoryBarrier* pMemoryBarriers,
6258 uint32_t bufferMemoryBarrierCount,
6259 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
6260 uint32_t imageMemoryBarrierCount,
6261 const VkImageMemoryBarrier* pImageMemoryBarriers)
6262 {
6263 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6264 struct radv_barrier_info info;
6265
6266 info.reason = RGP_BARRIER_EXTERNAL_CMD_PIPELINE_BARRIER;
6267 info.eventCount = 0;
6268 info.pEvents = NULL;
6269 info.srcStageMask = srcStageMask;
6270 info.dstStageMask = destStageMask;
6271
6272 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
6273 bufferMemoryBarrierCount, pBufferMemoryBarriers,
6274 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
6275 }
6276
6277
6278 static void write_event(struct radv_cmd_buffer *cmd_buffer,
6279 struct radv_event *event,
6280 VkPipelineStageFlags stageMask,
6281 unsigned value)
6282 {
6283 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6284 uint64_t va = radv_buffer_get_va(event->bo);
6285
6286 si_emit_cache_flush(cmd_buffer);
6287
6288 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
6289
6290 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 21);
6291
6292 /* Flags that only require a top-of-pipe event. */
6293 VkPipelineStageFlags top_of_pipe_flags =
6294 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
6295
6296 /* Flags that only require a post-index-fetch event. */
6297 VkPipelineStageFlags post_index_fetch_flags =
6298 top_of_pipe_flags |
6299 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
6300 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
6301
6302 /* Make sure CP DMA is idle because the driver might have performed a
6303 * DMA operation for copying or filling buffers/images.
6304 */
6305 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
6306 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
6307 si_cp_dma_wait_for_idle(cmd_buffer);
6308
6309 /* TODO: Emit EOS events for syncing PS/CS stages. */
6310
6311 if (!(stageMask & ~top_of_pipe_flags)) {
6312 /* Just need to sync the PFP engine. */
6313 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
6314 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
6315 S_370_WR_CONFIRM(1) |
6316 S_370_ENGINE_SEL(V_370_PFP));
6317 radeon_emit(cs, va);
6318 radeon_emit(cs, va >> 32);
6319 radeon_emit(cs, value);
6320 } else if (!(stageMask & ~post_index_fetch_flags)) {
6321 /* Sync ME because PFP reads index and indirect buffers. */
6322 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
6323 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
6324 S_370_WR_CONFIRM(1) |
6325 S_370_ENGINE_SEL(V_370_ME));
6326 radeon_emit(cs, va);
6327 radeon_emit(cs, va >> 32);
6328 radeon_emit(cs, value);
6329 } else {
6330 /* Otherwise, sync all prior GPU work using an EOP event. */
6331 si_cs_emit_write_event_eop(cs,
6332 cmd_buffer->device->physical_device->rad_info.chip_class,
6333 radv_cmd_buffer_uses_mec(cmd_buffer),
6334 V_028A90_BOTTOM_OF_PIPE_TS, 0,
6335 EOP_DST_SEL_MEM,
6336 EOP_DATA_SEL_VALUE_32BIT, va, value,
6337 cmd_buffer->gfx9_eop_bug_va);
6338 }
6339
6340 assert(cmd_buffer->cs->cdw <= cdw_max);
6341 }
6342
6343 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
6344 VkEvent _event,
6345 VkPipelineStageFlags stageMask)
6346 {
6347 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6348 RADV_FROM_HANDLE(radv_event, event, _event);
6349
6350 write_event(cmd_buffer, event, stageMask, 1);
6351 }
6352
6353 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
6354 VkEvent _event,
6355 VkPipelineStageFlags stageMask)
6356 {
6357 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6358 RADV_FROM_HANDLE(radv_event, event, _event);
6359
6360 write_event(cmd_buffer, event, stageMask, 0);
6361 }
6362
6363 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
6364 uint32_t eventCount,
6365 const VkEvent* pEvents,
6366 VkPipelineStageFlags srcStageMask,
6367 VkPipelineStageFlags dstStageMask,
6368 uint32_t memoryBarrierCount,
6369 const VkMemoryBarrier* pMemoryBarriers,
6370 uint32_t bufferMemoryBarrierCount,
6371 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
6372 uint32_t imageMemoryBarrierCount,
6373 const VkImageMemoryBarrier* pImageMemoryBarriers)
6374 {
6375 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6376 struct radv_barrier_info info;
6377
6378 info.reason = RGP_BARRIER_EXTERNAL_CMD_WAIT_EVENTS;
6379 info.eventCount = eventCount;
6380 info.pEvents = pEvents;
6381 info.srcStageMask = 0;
6382
6383 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
6384 bufferMemoryBarrierCount, pBufferMemoryBarriers,
6385 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
6386 }
6387
6388
6389 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
6390 uint32_t deviceMask)
6391 {
6392 /* No-op */
6393 }
6394
6395 /* VK_EXT_conditional_rendering */
6396 void radv_CmdBeginConditionalRenderingEXT(
6397 VkCommandBuffer commandBuffer,
6398 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
6399 {
6400 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6401 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
6402 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6403 bool draw_visible = true;
6404 uint64_t pred_value = 0;
6405 uint64_t va, new_va;
6406 unsigned pred_offset;
6407
6408 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
6409
6410 /* By default, if the 32-bit value at offset in buffer memory is zero,
6411 * then the rendering commands are discarded, otherwise they are
6412 * executed as normal. If the inverted flag is set, all commands are
6413 * discarded if the value is non zero.
6414 */
6415 if (pConditionalRenderingBegin->flags &
6416 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
6417 draw_visible = false;
6418 }
6419
6420 si_emit_cache_flush(cmd_buffer);
6421
6422 /* From the Vulkan spec 1.1.107:
6423 *
6424 * "If the 32-bit value at offset in buffer memory is zero, then the
6425 * rendering commands are discarded, otherwise they are executed as
6426 * normal. If the value of the predicate in buffer memory changes while
6427 * conditional rendering is active, the rendering commands may be
6428 * discarded in an implementation-dependent way. Some implementations
6429 * may latch the value of the predicate upon beginning conditional
6430 * rendering while others may read it before every rendering command."
6431 *
6432 * But, the AMD hardware treats the predicate as a 64-bit value which
6433 * means we need a workaround in the driver. Luckily, it's not required
6434 * to support if the value changes when predication is active.
6435 *
6436 * The workaround is as follows:
6437 * 1) allocate a 64-value in the upload BO and initialize it to 0
6438 * 2) copy the 32-bit predicate value to the upload BO
6439 * 3) use the new allocated VA address for predication
6440 *
6441 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
6442 * in ME (+ sync PFP) instead of PFP.
6443 */
6444 radv_cmd_buffer_upload_data(cmd_buffer, 8, 16, &pred_value, &pred_offset);
6445
6446 new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
6447
6448 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
6449 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
6450 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
6451 COPY_DATA_WR_CONFIRM);
6452 radeon_emit(cs, va);
6453 radeon_emit(cs, va >> 32);
6454 radeon_emit(cs, new_va);
6455 radeon_emit(cs, new_va >> 32);
6456
6457 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
6458 radeon_emit(cs, 0);
6459
6460 /* Enable predication for this command buffer. */
6461 si_emit_set_predication_state(cmd_buffer, draw_visible, new_va);
6462 cmd_buffer->state.predicating = true;
6463
6464 /* Store conditional rendering user info. */
6465 cmd_buffer->state.predication_type = draw_visible;
6466 cmd_buffer->state.predication_va = new_va;
6467 }
6468
6469 void radv_CmdEndConditionalRenderingEXT(
6470 VkCommandBuffer commandBuffer)
6471 {
6472 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6473
6474 /* Disable predication for this command buffer. */
6475 si_emit_set_predication_state(cmd_buffer, false, 0);
6476 cmd_buffer->state.predicating = false;
6477
6478 /* Reset conditional rendering user info. */
6479 cmd_buffer->state.predication_type = -1;
6480 cmd_buffer->state.predication_va = 0;
6481 }
6482
6483 /* VK_EXT_transform_feedback */
6484 void radv_CmdBindTransformFeedbackBuffersEXT(
6485 VkCommandBuffer commandBuffer,
6486 uint32_t firstBinding,
6487 uint32_t bindingCount,
6488 const VkBuffer* pBuffers,
6489 const VkDeviceSize* pOffsets,
6490 const VkDeviceSize* pSizes)
6491 {
6492 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6493 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
6494 uint8_t enabled_mask = 0;
6495
6496 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
6497 for (uint32_t i = 0; i < bindingCount; i++) {
6498 uint32_t idx = firstBinding + i;
6499
6500 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
6501 sb[idx].offset = pOffsets[i];
6502
6503 if (!pSizes || pSizes[i] == VK_WHOLE_SIZE) {
6504 sb[idx].size = sb[idx].buffer->size - sb[idx].offset;
6505 } else {
6506 sb[idx].size = pSizes[i];
6507 }
6508
6509 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
6510 sb[idx].buffer->bo);
6511
6512 enabled_mask |= 1 << idx;
6513 }
6514
6515 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
6516
6517 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
6518 }
6519
6520 static void
6521 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
6522 {
6523 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6524 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6525
6526 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
6527 radeon_emit(cs,
6528 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
6529 S_028B94_RAST_STREAM(0) |
6530 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
6531 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
6532 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
6533 radeon_emit(cs, so->hw_enabled_mask &
6534 so->enabled_stream_buffers_mask);
6535
6536 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6537 }
6538
6539 static void
6540 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
6541 {
6542 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6543 bool old_streamout_enabled = so->streamout_enabled;
6544 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
6545
6546 so->streamout_enabled = enable;
6547
6548 so->hw_enabled_mask = so->enabled_mask |
6549 (so->enabled_mask << 4) |
6550 (so->enabled_mask << 8) |
6551 (so->enabled_mask << 12);
6552
6553 if (!cmd_buffer->device->physical_device->use_ngg_streamout &&
6554 ((old_streamout_enabled != so->streamout_enabled) ||
6555 (old_hw_enabled_mask != so->hw_enabled_mask)))
6556 radv_emit_streamout_enable(cmd_buffer);
6557
6558 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6559 cmd_buffer->gds_needed = true;
6560 cmd_buffer->gds_oa_needed = true;
6561 }
6562 }
6563
6564 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
6565 {
6566 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6567 unsigned reg_strmout_cntl;
6568
6569 /* The register is at different places on different ASICs. */
6570 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
6571 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
6572 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
6573 } else {
6574 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
6575 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
6576 }
6577
6578 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
6579 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
6580
6581 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
6582 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
6583 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
6584 radeon_emit(cs, 0);
6585 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
6586 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
6587 radeon_emit(cs, 4); /* poll interval */
6588 }
6589
6590 static void
6591 radv_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
6592 uint32_t firstCounterBuffer,
6593 uint32_t counterBufferCount,
6594 const VkBuffer *pCounterBuffers,
6595 const VkDeviceSize *pCounterBufferOffsets)
6596
6597 {
6598 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
6599 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6600 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6601 uint32_t i;
6602
6603 radv_flush_vgt_streamout(cmd_buffer);
6604
6605 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6606 for_each_bit(i, so->enabled_mask) {
6607 int32_t counter_buffer_idx = i - firstCounterBuffer;
6608 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6609 counter_buffer_idx = -1;
6610
6611 /* AMD GCN binds streamout buffers as shader resources.
6612 * VGT only counts primitives and tells the shader through
6613 * SGPRs what to do.
6614 */
6615 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
6616 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
6617 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
6618
6619 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6620
6621 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6622 /* The array of counter buffers is optional. */
6623 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6624 uint64_t va = radv_buffer_get_va(buffer->bo);
6625
6626 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6627
6628 /* Append */
6629 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6630 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6631 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6632 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
6633 radeon_emit(cs, 0); /* unused */
6634 radeon_emit(cs, 0); /* unused */
6635 radeon_emit(cs, va); /* src address lo */
6636 radeon_emit(cs, va >> 32); /* src address hi */
6637
6638 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6639 } else {
6640 /* Start from the beginning. */
6641 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6642 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6643 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6644 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
6645 radeon_emit(cs, 0); /* unused */
6646 radeon_emit(cs, 0); /* unused */
6647 radeon_emit(cs, 0); /* unused */
6648 radeon_emit(cs, 0); /* unused */
6649 }
6650 }
6651
6652 radv_set_streamout_enable(cmd_buffer, true);
6653 }
6654
6655 static void
6656 gfx10_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
6657 uint32_t firstCounterBuffer,
6658 uint32_t counterBufferCount,
6659 const VkBuffer *pCounterBuffers,
6660 const VkDeviceSize *pCounterBufferOffsets)
6661 {
6662 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6663 unsigned last_target = util_last_bit(so->enabled_mask) - 1;
6664 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6665 uint32_t i;
6666
6667 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6668 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6669
6670 /* Sync because the next streamout operation will overwrite GDS and we
6671 * have to make sure it's idle.
6672 * TODO: Improve by tracking if there is a streamout operation in
6673 * flight.
6674 */
6675 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
6676 si_emit_cache_flush(cmd_buffer);
6677
6678 for_each_bit(i, so->enabled_mask) {
6679 int32_t counter_buffer_idx = i - firstCounterBuffer;
6680 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6681 counter_buffer_idx = -1;
6682
6683 bool append = counter_buffer_idx >= 0 &&
6684 pCounterBuffers && pCounterBuffers[counter_buffer_idx];
6685 uint64_t va = 0;
6686
6687 if (append) {
6688 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6689
6690 va += radv_buffer_get_va(buffer->bo);
6691 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6692
6693 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6694 }
6695
6696 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
6697 radeon_emit(cs, S_411_SRC_SEL(append ? V_411_SRC_ADDR_TC_L2 : V_411_DATA) |
6698 S_411_DST_SEL(V_411_GDS) |
6699 S_411_CP_SYNC(i == last_target));
6700 radeon_emit(cs, va);
6701 radeon_emit(cs, va >> 32);
6702 radeon_emit(cs, 4 * i); /* destination in GDS */
6703 radeon_emit(cs, 0);
6704 radeon_emit(cs, S_414_BYTE_COUNT_GFX9(4) |
6705 S_414_DISABLE_WR_CONFIRM_GFX9(i != last_target));
6706 }
6707
6708 radv_set_streamout_enable(cmd_buffer, true);
6709 }
6710
6711 void radv_CmdBeginTransformFeedbackEXT(
6712 VkCommandBuffer commandBuffer,
6713 uint32_t firstCounterBuffer,
6714 uint32_t counterBufferCount,
6715 const VkBuffer* pCounterBuffers,
6716 const VkDeviceSize* pCounterBufferOffsets)
6717 {
6718 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6719
6720 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6721 gfx10_emit_streamout_begin(cmd_buffer,
6722 firstCounterBuffer, counterBufferCount,
6723 pCounterBuffers, pCounterBufferOffsets);
6724 } else {
6725 radv_emit_streamout_begin(cmd_buffer,
6726 firstCounterBuffer, counterBufferCount,
6727 pCounterBuffers, pCounterBufferOffsets);
6728 }
6729 }
6730
6731 static void
6732 radv_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6733 uint32_t firstCounterBuffer,
6734 uint32_t counterBufferCount,
6735 const VkBuffer *pCounterBuffers,
6736 const VkDeviceSize *pCounterBufferOffsets)
6737 {
6738 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6739 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6740 uint32_t i;
6741
6742 radv_flush_vgt_streamout(cmd_buffer);
6743
6744 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6745 for_each_bit(i, so->enabled_mask) {
6746 int32_t counter_buffer_idx = i - firstCounterBuffer;
6747 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6748 counter_buffer_idx = -1;
6749
6750 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6751 /* The array of counters buffer is optional. */
6752 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6753 uint64_t va = radv_buffer_get_va(buffer->bo);
6754
6755 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6756
6757 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6758 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6759 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6760 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
6761 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
6762 radeon_emit(cs, va); /* dst address lo */
6763 radeon_emit(cs, va >> 32); /* dst address hi */
6764 radeon_emit(cs, 0); /* unused */
6765 radeon_emit(cs, 0); /* unused */
6766
6767 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6768 }
6769
6770 /* Deactivate transform feedback by zeroing the buffer size.
6771 * The counters (primitives generated, primitives emitted) may
6772 * be enabled even if there is not buffer bound. This ensures
6773 * that the primitives-emitted query won't increment.
6774 */
6775 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
6776
6777 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6778 }
6779
6780 radv_set_streamout_enable(cmd_buffer, false);
6781 }
6782
6783 static void
6784 gfx10_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6785 uint32_t firstCounterBuffer,
6786 uint32_t counterBufferCount,
6787 const VkBuffer *pCounterBuffers,
6788 const VkDeviceSize *pCounterBufferOffsets)
6789 {
6790 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6791 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6792 uint32_t i;
6793
6794 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6795 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6796
6797 for_each_bit(i, so->enabled_mask) {
6798 int32_t counter_buffer_idx = i - firstCounterBuffer;
6799 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6800 counter_buffer_idx = -1;
6801
6802 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6803 /* The array of counters buffer is optional. */
6804 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6805 uint64_t va = radv_buffer_get_va(buffer->bo);
6806
6807 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6808
6809 si_cs_emit_write_event_eop(cs,
6810 cmd_buffer->device->physical_device->rad_info.chip_class,
6811 radv_cmd_buffer_uses_mec(cmd_buffer),
6812 V_028A90_PS_DONE, 0,
6813 EOP_DST_SEL_TC_L2,
6814 EOP_DATA_SEL_GDS,
6815 va, EOP_DATA_GDS(i, 1), 0);
6816
6817 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6818 }
6819 }
6820
6821 radv_set_streamout_enable(cmd_buffer, false);
6822 }
6823
6824 void radv_CmdEndTransformFeedbackEXT(
6825 VkCommandBuffer commandBuffer,
6826 uint32_t firstCounterBuffer,
6827 uint32_t counterBufferCount,
6828 const VkBuffer* pCounterBuffers,
6829 const VkDeviceSize* pCounterBufferOffsets)
6830 {
6831 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6832
6833 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6834 gfx10_emit_streamout_end(cmd_buffer,
6835 firstCounterBuffer, counterBufferCount,
6836 pCounterBuffers, pCounterBufferOffsets);
6837 } else {
6838 radv_emit_streamout_end(cmd_buffer,
6839 firstCounterBuffer, counterBufferCount,
6840 pCounterBuffers, pCounterBufferOffsets);
6841 }
6842 }
6843
6844 void radv_CmdDrawIndirectByteCountEXT(
6845 VkCommandBuffer commandBuffer,
6846 uint32_t instanceCount,
6847 uint32_t firstInstance,
6848 VkBuffer _counterBuffer,
6849 VkDeviceSize counterBufferOffset,
6850 uint32_t counterOffset,
6851 uint32_t vertexStride)
6852 {
6853 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6854 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
6855 struct radv_draw_info info = {};
6856
6857 info.instance_count = instanceCount;
6858 info.first_instance = firstInstance;
6859 info.strmout_buffer = counterBuffer;
6860 info.strmout_buffer_offset = counterBufferOffset;
6861 info.stride = vertexStride;
6862
6863 radv_draw(cmd_buffer, &info);
6864 }
6865
6866 /* VK_AMD_buffer_marker */
6867 void radv_CmdWriteBufferMarkerAMD(
6868 VkCommandBuffer commandBuffer,
6869 VkPipelineStageFlagBits pipelineStage,
6870 VkBuffer dstBuffer,
6871 VkDeviceSize dstOffset,
6872 uint32_t marker)
6873 {
6874 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6875 RADV_FROM_HANDLE(radv_buffer, buffer, dstBuffer);
6876 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6877 uint64_t va = radv_buffer_get_va(buffer->bo) + dstOffset;
6878
6879 si_emit_cache_flush(cmd_buffer);
6880
6881 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 12);
6882
6883 if (!(pipelineStage & ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT)) {
6884 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
6885 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
6886 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
6887 COPY_DATA_WR_CONFIRM);
6888 radeon_emit(cs, marker);
6889 radeon_emit(cs, 0);
6890 radeon_emit(cs, va);
6891 radeon_emit(cs, va >> 32);
6892 } else {
6893 si_cs_emit_write_event_eop(cs,
6894 cmd_buffer->device->physical_device->rad_info.chip_class,
6895 radv_cmd_buffer_uses_mec(cmd_buffer),
6896 V_028A90_BOTTOM_OF_PIPE_TS, 0,
6897 EOP_DST_SEL_MEM,
6898 EOP_DATA_SEL_VALUE_32BIT,
6899 va, marker,
6900 cmd_buffer->gfx9_eop_bug_va);
6901 }
6902
6903 assert(cmd_buffer->cs->cdw <= cdw_max);
6904 }