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radv: Remove dead code.
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 bool src_render_loop,
58 VkImageLayout dst_layout,
59 bool dst_render_loop,
60 uint32_t src_family,
61 uint32_t dst_family,
62 const VkImageSubresourceRange *range,
63 struct radv_sample_locations_state *sample_locs);
64
65 const struct radv_dynamic_state default_dynamic_state = {
66 .viewport = {
67 .count = 0,
68 },
69 .scissor = {
70 .count = 0,
71 },
72 .line_width = 1.0f,
73 .depth_bias = {
74 .bias = 0.0f,
75 .clamp = 0.0f,
76 .slope = 0.0f,
77 },
78 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
79 .depth_bounds = {
80 .min = 0.0f,
81 .max = 1.0f,
82 },
83 .stencil_compare_mask = {
84 .front = ~0u,
85 .back = ~0u,
86 },
87 .stencil_write_mask = {
88 .front = ~0u,
89 .back = ~0u,
90 },
91 .stencil_reference = {
92 .front = 0u,
93 .back = 0u,
94 },
95 .line_stipple = {
96 .factor = 0u,
97 .pattern = 0u,
98 },
99 };
100
101 static void
102 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
103 const struct radv_dynamic_state *src)
104 {
105 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
106 uint32_t copy_mask = src->mask;
107 uint32_t dest_mask = 0;
108
109 /* Make sure to copy the number of viewports/scissors because they can
110 * only be specified at pipeline creation time.
111 */
112 dest->viewport.count = src->viewport.count;
113 dest->scissor.count = src->scissor.count;
114 dest->discard_rectangle.count = src->discard_rectangle.count;
115 dest->sample_location.count = src->sample_location.count;
116
117 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
118 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
119 src->viewport.count * sizeof(VkViewport))) {
120 typed_memcpy(dest->viewport.viewports,
121 src->viewport.viewports,
122 src->viewport.count);
123 dest_mask |= RADV_DYNAMIC_VIEWPORT;
124 }
125 }
126
127 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
128 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
129 src->scissor.count * sizeof(VkRect2D))) {
130 typed_memcpy(dest->scissor.scissors,
131 src->scissor.scissors, src->scissor.count);
132 dest_mask |= RADV_DYNAMIC_SCISSOR;
133 }
134 }
135
136 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
137 if (dest->line_width != src->line_width) {
138 dest->line_width = src->line_width;
139 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
140 }
141 }
142
143 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
144 if (memcmp(&dest->depth_bias, &src->depth_bias,
145 sizeof(src->depth_bias))) {
146 dest->depth_bias = src->depth_bias;
147 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
148 }
149 }
150
151 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
152 if (memcmp(&dest->blend_constants, &src->blend_constants,
153 sizeof(src->blend_constants))) {
154 typed_memcpy(dest->blend_constants,
155 src->blend_constants, 4);
156 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
157 }
158 }
159
160 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
161 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
162 sizeof(src->depth_bounds))) {
163 dest->depth_bounds = src->depth_bounds;
164 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
165 }
166 }
167
168 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
169 if (memcmp(&dest->stencil_compare_mask,
170 &src->stencil_compare_mask,
171 sizeof(src->stencil_compare_mask))) {
172 dest->stencil_compare_mask = src->stencil_compare_mask;
173 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
174 }
175 }
176
177 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
178 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
179 sizeof(src->stencil_write_mask))) {
180 dest->stencil_write_mask = src->stencil_write_mask;
181 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
182 }
183 }
184
185 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
186 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
187 sizeof(src->stencil_reference))) {
188 dest->stencil_reference = src->stencil_reference;
189 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
190 }
191 }
192
193 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
194 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
195 src->discard_rectangle.count * sizeof(VkRect2D))) {
196 typed_memcpy(dest->discard_rectangle.rectangles,
197 src->discard_rectangle.rectangles,
198 src->discard_rectangle.count);
199 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
200 }
201 }
202
203 if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
204 if (dest->sample_location.per_pixel != src->sample_location.per_pixel ||
205 dest->sample_location.grid_size.width != src->sample_location.grid_size.width ||
206 dest->sample_location.grid_size.height != src->sample_location.grid_size.height ||
207 memcmp(&dest->sample_location.locations,
208 &src->sample_location.locations,
209 src->sample_location.count * sizeof(VkSampleLocationEXT))) {
210 dest->sample_location.per_pixel = src->sample_location.per_pixel;
211 dest->sample_location.grid_size = src->sample_location.grid_size;
212 typed_memcpy(dest->sample_location.locations,
213 src->sample_location.locations,
214 src->sample_location.count);
215 dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
216 }
217 }
218
219 if (copy_mask & RADV_DYNAMIC_LINE_STIPPLE) {
220 if (memcmp(&dest->line_stipple, &src->line_stipple,
221 sizeof(src->line_stipple))) {
222 dest->line_stipple = src->line_stipple;
223 dest_mask |= RADV_DYNAMIC_LINE_STIPPLE;
224 }
225 }
226
227 cmd_buffer->state.dirty |= dest_mask;
228 }
229
230 static void
231 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
232 struct radv_pipeline *pipeline)
233 {
234 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
235 struct radv_shader_info *info;
236
237 if (!pipeline->streamout_shader ||
238 cmd_buffer->device->physical_device->use_ngg_streamout)
239 return;
240
241 info = &pipeline->streamout_shader->info;
242 for (int i = 0; i < MAX_SO_BUFFERS; i++)
243 so->stride_in_dw[i] = info->so.strides[i];
244
245 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
246 }
247
248 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
249 {
250 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
251 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
252 }
253
254 enum ring_type radv_queue_family_to_ring(int f) {
255 switch (f) {
256 case RADV_QUEUE_GENERAL:
257 return RING_GFX;
258 case RADV_QUEUE_COMPUTE:
259 return RING_COMPUTE;
260 case RADV_QUEUE_TRANSFER:
261 return RING_DMA;
262 default:
263 unreachable("Unknown queue family");
264 }
265 }
266
267 static VkResult radv_create_cmd_buffer(
268 struct radv_device * device,
269 struct radv_cmd_pool * pool,
270 VkCommandBufferLevel level,
271 VkCommandBuffer* pCommandBuffer)
272 {
273 struct radv_cmd_buffer *cmd_buffer;
274 unsigned ring;
275 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
276 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
277 if (cmd_buffer == NULL)
278 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
279
280 vk_object_base_init(&device->vk, &cmd_buffer->base,
281 VK_OBJECT_TYPE_COMMAND_BUFFER);
282
283 cmd_buffer->device = device;
284 cmd_buffer->pool = pool;
285 cmd_buffer->level = level;
286
287 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
288 cmd_buffer->queue_family_index = pool->queue_family_index;
289
290 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
291
292 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
293 if (!cmd_buffer->cs) {
294 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
295 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
296 }
297
298 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
299
300 list_inithead(&cmd_buffer->upload.list);
301
302 return VK_SUCCESS;
303 }
304
305 static void
306 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
307 {
308 list_del(&cmd_buffer->pool_link);
309
310 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
311 &cmd_buffer->upload.list, list) {
312 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
313 list_del(&up->list);
314 free(up);
315 }
316
317 if (cmd_buffer->upload.upload_bo)
318 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
319 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
320
321 for (unsigned i = 0; i < MAX_BIND_POINTS; i++)
322 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
323
324 vk_object_base_finish(&cmd_buffer->base);
325
326 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
327 }
328
329 static VkResult
330 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
331 {
332 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
333
334 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
335 &cmd_buffer->upload.list, list) {
336 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
337 list_del(&up->list);
338 free(up);
339 }
340
341 cmd_buffer->push_constant_stages = 0;
342 cmd_buffer->scratch_size_per_wave_needed = 0;
343 cmd_buffer->scratch_waves_wanted = 0;
344 cmd_buffer->compute_scratch_size_per_wave_needed = 0;
345 cmd_buffer->compute_scratch_waves_wanted = 0;
346 cmd_buffer->esgs_ring_size_needed = 0;
347 cmd_buffer->gsvs_ring_size_needed = 0;
348 cmd_buffer->tess_rings_needed = false;
349 cmd_buffer->gds_needed = false;
350 cmd_buffer->gds_oa_needed = false;
351 cmd_buffer->sample_positions_needed = false;
352
353 if (cmd_buffer->upload.upload_bo)
354 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
355 cmd_buffer->upload.upload_bo);
356 cmd_buffer->upload.offset = 0;
357
358 cmd_buffer->record_result = VK_SUCCESS;
359
360 memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
361
362 for (unsigned i = 0; i < MAX_BIND_POINTS; i++) {
363 cmd_buffer->descriptors[i].dirty = 0;
364 cmd_buffer->descriptors[i].valid = 0;
365 cmd_buffer->descriptors[i].push_dirty = false;
366 }
367
368 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
369 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
370 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
371 unsigned fence_offset, eop_bug_offset;
372 void *fence_ptr;
373
374 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
375 &fence_ptr);
376
377 cmd_buffer->gfx9_fence_va =
378 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
379 cmd_buffer->gfx9_fence_va += fence_offset;
380
381 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
382 /* Allocate a buffer for the EOP bug on GFX9. */
383 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
384 &eop_bug_offset, &fence_ptr);
385 cmd_buffer->gfx9_eop_bug_va =
386 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
387 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
388 }
389 }
390
391 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
392
393 return cmd_buffer->record_result;
394 }
395
396 static bool
397 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
398 uint64_t min_needed)
399 {
400 uint64_t new_size;
401 struct radeon_winsys_bo *bo;
402 struct radv_cmd_buffer_upload *upload;
403 struct radv_device *device = cmd_buffer->device;
404
405 new_size = MAX2(min_needed, 16 * 1024);
406 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
407
408 bo = device->ws->buffer_create(device->ws,
409 new_size, 4096,
410 RADEON_DOMAIN_GTT,
411 RADEON_FLAG_CPU_ACCESS|
412 RADEON_FLAG_NO_INTERPROCESS_SHARING |
413 RADEON_FLAG_32BIT,
414 RADV_BO_PRIORITY_UPLOAD_BUFFER);
415
416 if (!bo) {
417 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
418 return false;
419 }
420
421 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
422 if (cmd_buffer->upload.upload_bo) {
423 upload = malloc(sizeof(*upload));
424
425 if (!upload) {
426 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
427 device->ws->buffer_destroy(bo);
428 return false;
429 }
430
431 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
432 list_add(&upload->list, &cmd_buffer->upload.list);
433 }
434
435 cmd_buffer->upload.upload_bo = bo;
436 cmd_buffer->upload.size = new_size;
437 cmd_buffer->upload.offset = 0;
438 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
439
440 if (!cmd_buffer->upload.map) {
441 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
442 return false;
443 }
444
445 return true;
446 }
447
448 bool
449 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
450 unsigned size,
451 unsigned alignment,
452 unsigned *out_offset,
453 void **ptr)
454 {
455 assert(util_is_power_of_two_nonzero(alignment));
456
457 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
458 if (offset + size > cmd_buffer->upload.size) {
459 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
460 return false;
461 offset = 0;
462 }
463
464 *out_offset = offset;
465 *ptr = cmd_buffer->upload.map + offset;
466
467 cmd_buffer->upload.offset = offset + size;
468 return true;
469 }
470
471 bool
472 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
473 unsigned size, unsigned alignment,
474 const void *data, unsigned *out_offset)
475 {
476 uint8_t *ptr;
477
478 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
479 out_offset, (void **)&ptr))
480 return false;
481
482 if (ptr)
483 memcpy(ptr, data, size);
484
485 return true;
486 }
487
488 static void
489 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
490 unsigned count, const uint32_t *data)
491 {
492 struct radeon_cmdbuf *cs = cmd_buffer->cs;
493
494 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
495
496 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
497 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
498 S_370_WR_CONFIRM(1) |
499 S_370_ENGINE_SEL(V_370_ME));
500 radeon_emit(cs, va);
501 radeon_emit(cs, va >> 32);
502 radeon_emit_array(cs, data, count);
503 }
504
505 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
506 {
507 struct radv_device *device = cmd_buffer->device;
508 struct radeon_cmdbuf *cs = cmd_buffer->cs;
509 uint64_t va;
510
511 va = radv_buffer_get_va(device->trace_bo);
512 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
513 va += 4;
514
515 ++cmd_buffer->state.trace_id;
516 radv_emit_write_data_packet(cmd_buffer, va, 1,
517 &cmd_buffer->state.trace_id);
518
519 radeon_check_space(cmd_buffer->device->ws, cs, 2);
520
521 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
522 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
523 }
524
525 static void
526 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
527 enum radv_cmd_flush_bits flags)
528 {
529 if (unlikely(cmd_buffer->device->thread_trace_bo)) {
530 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
531 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_THREAD_TRACE_MARKER) | EVENT_INDEX(0));
532 }
533
534 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
535 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
536 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
537
538 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
539
540 /* Force wait for graphics or compute engines to be idle. */
541 si_cs_emit_cache_flush(cmd_buffer->cs,
542 cmd_buffer->device->physical_device->rad_info.chip_class,
543 &cmd_buffer->gfx9_fence_idx,
544 cmd_buffer->gfx9_fence_va,
545 radv_cmd_buffer_uses_mec(cmd_buffer),
546 flags, cmd_buffer->gfx9_eop_bug_va);
547 }
548
549 if (unlikely(cmd_buffer->device->trace_bo))
550 radv_cmd_buffer_trace_emit(cmd_buffer);
551 }
552
553 static void
554 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
555 struct radv_pipeline *pipeline, enum ring_type ring)
556 {
557 struct radv_device *device = cmd_buffer->device;
558 uint32_t data[2];
559 uint64_t va;
560
561 va = radv_buffer_get_va(device->trace_bo);
562
563 switch (ring) {
564 case RING_GFX:
565 va += 8;
566 break;
567 case RING_COMPUTE:
568 va += 16;
569 break;
570 default:
571 assert(!"invalid ring type");
572 }
573
574 uint64_t pipeline_address = (uintptr_t)pipeline;
575 data[0] = pipeline_address;
576 data[1] = pipeline_address >> 32;
577
578 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
579 }
580
581 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
582 VkPipelineBindPoint bind_point,
583 struct radv_descriptor_set *set,
584 unsigned idx)
585 {
586 struct radv_descriptor_state *descriptors_state =
587 radv_get_descriptors_state(cmd_buffer, bind_point);
588
589 descriptors_state->sets[idx] = set;
590
591 descriptors_state->valid |= (1u << idx); /* active descriptors */
592 descriptors_state->dirty |= (1u << idx);
593 }
594
595 static void
596 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
597 VkPipelineBindPoint bind_point)
598 {
599 struct radv_descriptor_state *descriptors_state =
600 radv_get_descriptors_state(cmd_buffer, bind_point);
601 struct radv_device *device = cmd_buffer->device;
602 uint32_t data[MAX_SETS * 2] = {};
603 uint64_t va;
604 unsigned i;
605 va = radv_buffer_get_va(device->trace_bo) + 24;
606
607 for_each_bit(i, descriptors_state->valid) {
608 struct radv_descriptor_set *set = descriptors_state->sets[i];
609 data[i * 2] = (uint64_t)(uintptr_t)set;
610 data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
611 }
612
613 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
614 }
615
616 struct radv_userdata_info *
617 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
618 gl_shader_stage stage,
619 int idx)
620 {
621 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
622 return &shader->info.user_sgprs_locs.shader_data[idx];
623 }
624
625 static void
626 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
627 struct radv_pipeline *pipeline,
628 gl_shader_stage stage,
629 int idx, uint64_t va)
630 {
631 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
632 uint32_t base_reg = pipeline->user_data_0[stage];
633 if (loc->sgpr_idx == -1)
634 return;
635
636 assert(loc->num_sgprs == 1);
637
638 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
639 base_reg + loc->sgpr_idx * 4, va, false);
640 }
641
642 static void
643 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
644 struct radv_pipeline *pipeline,
645 struct radv_descriptor_state *descriptors_state,
646 gl_shader_stage stage)
647 {
648 struct radv_device *device = cmd_buffer->device;
649 struct radeon_cmdbuf *cs = cmd_buffer->cs;
650 uint32_t sh_base = pipeline->user_data_0[stage];
651 struct radv_userdata_locations *locs =
652 &pipeline->shaders[stage]->info.user_sgprs_locs;
653 unsigned mask = locs->descriptor_sets_enabled;
654
655 mask &= descriptors_state->dirty & descriptors_state->valid;
656
657 while (mask) {
658 int start, count;
659
660 u_bit_scan_consecutive_range(&mask, &start, &count);
661
662 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
663 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
664
665 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
666 for (int i = 0; i < count; i++) {
667 struct radv_descriptor_set *set =
668 descriptors_state->sets[start + i];
669
670 radv_emit_shader_pointer_body(device, cs, set->va, true);
671 }
672 }
673 }
674
675 /**
676 * Convert the user sample locations to hardware sample locations (the values
677 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
678 */
679 static void
680 radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
681 uint32_t x, uint32_t y, VkOffset2D *sample_locs)
682 {
683 uint32_t x_offset = x % state->grid_size.width;
684 uint32_t y_offset = y % state->grid_size.height;
685 uint32_t num_samples = (uint32_t)state->per_pixel;
686 VkSampleLocationEXT *user_locs;
687 uint32_t pixel_offset;
688
689 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
690
691 assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
692 user_locs = &state->locations[pixel_offset];
693
694 for (uint32_t i = 0; i < num_samples; i++) {
695 float shifted_pos_x = user_locs[i].x - 0.5;
696 float shifted_pos_y = user_locs[i].y - 0.5;
697
698 int32_t scaled_pos_x = floorf(shifted_pos_x * 16);
699 int32_t scaled_pos_y = floorf(shifted_pos_y * 16);
700
701 sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
702 sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
703 }
704 }
705
706 /**
707 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
708 * locations.
709 */
710 static void
711 radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
712 uint32_t *sample_locs_pixel)
713 {
714 for (uint32_t i = 0; i < num_samples; i++) {
715 uint32_t sample_reg_idx = i / 4;
716 uint32_t sample_loc_idx = i % 4;
717 int32_t pos_x = sample_locs[i].x;
718 int32_t pos_y = sample_locs[i].y;
719
720 uint32_t shift_x = 8 * sample_loc_idx;
721 uint32_t shift_y = shift_x + 4;
722
723 sample_locs_pixel[sample_reg_idx] |= (pos_x & 0xf) << shift_x;
724 sample_locs_pixel[sample_reg_idx] |= (pos_y & 0xf) << shift_y;
725 }
726 }
727
728 /**
729 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
730 * sample locations.
731 */
732 static uint64_t
733 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer,
734 VkOffset2D *sample_locs,
735 uint32_t num_samples)
736 {
737 uint32_t centroid_priorities[num_samples];
738 uint32_t sample_mask = num_samples - 1;
739 uint32_t distances[num_samples];
740 uint64_t centroid_priority = 0;
741
742 /* Compute the distances from center for each sample. */
743 for (int i = 0; i < num_samples; i++) {
744 distances[i] = (sample_locs[i].x * sample_locs[i].x) +
745 (sample_locs[i].y * sample_locs[i].y);
746 }
747
748 /* Compute the centroid priorities by looking at the distances array. */
749 for (int i = 0; i < num_samples; i++) {
750 uint32_t min_idx = 0;
751
752 for (int j = 1; j < num_samples; j++) {
753 if (distances[j] < distances[min_idx])
754 min_idx = j;
755 }
756
757 centroid_priorities[i] = min_idx;
758 distances[min_idx] = 0xffffffff;
759 }
760
761 /* Compute the final centroid priority. */
762 for (int i = 0; i < 8; i++) {
763 centroid_priority |=
764 centroid_priorities[i & sample_mask] << (i * 4);
765 }
766
767 return centroid_priority << 32 | centroid_priority;
768 }
769
770 /**
771 * Emit the sample locations that are specified with VK_EXT_sample_locations.
772 */
773 static void
774 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
775 {
776 struct radv_sample_locations_state *sample_location =
777 &cmd_buffer->state.dynamic.sample_location;
778 uint32_t num_samples = (uint32_t)sample_location->per_pixel;
779 struct radeon_cmdbuf *cs = cmd_buffer->cs;
780 uint32_t sample_locs_pixel[4][2] = {};
781 VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
782 uint32_t max_sample_dist = 0;
783 uint64_t centroid_priority;
784
785 if (!cmd_buffer->state.dynamic.sample_location.count)
786 return;
787
788 /* Convert the user sample locations to hardware sample locations. */
789 radv_convert_user_sample_locs(sample_location, 0, 0, sample_locs[0]);
790 radv_convert_user_sample_locs(sample_location, 1, 0, sample_locs[1]);
791 radv_convert_user_sample_locs(sample_location, 0, 1, sample_locs[2]);
792 radv_convert_user_sample_locs(sample_location, 1, 1, sample_locs[3]);
793
794 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
795 for (uint32_t i = 0; i < 4; i++) {
796 radv_compute_sample_locs_pixel(num_samples, sample_locs[i],
797 sample_locs_pixel[i]);
798 }
799
800 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
801 centroid_priority =
802 radv_compute_centroid_priority(cmd_buffer, sample_locs[0],
803 num_samples);
804
805 /* Compute the maximum sample distance from the specified locations. */
806 for (unsigned i = 0; i < 4; ++i) {
807 for (uint32_t j = 0; j < num_samples; j++) {
808 VkOffset2D offset = sample_locs[i][j];
809 max_sample_dist = MAX2(max_sample_dist,
810 MAX2(abs(offset.x), abs(offset.y)));
811 }
812 }
813
814 /* Emit the specified user sample locations. */
815 switch (num_samples) {
816 case 2:
817 case 4:
818 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
819 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
820 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
821 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
822 break;
823 case 8:
824 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
825 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
826 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
827 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
828 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs_pixel[0][1]);
829 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs_pixel[1][1]);
830 radeon_set_context_reg(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs_pixel[2][1]);
831 radeon_set_context_reg(cs, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs_pixel[3][1]);
832 break;
833 default:
834 unreachable("invalid number of samples");
835 }
836
837 /* Emit the maximum sample distance and the centroid priority. */
838 radeon_set_context_reg_rmw(cs, R_028BE0_PA_SC_AA_CONFIG,
839 S_028BE0_MAX_SAMPLE_DIST(max_sample_dist),
840 ~C_028BE0_MAX_SAMPLE_DIST);
841
842 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
843 radeon_emit(cs, centroid_priority);
844 radeon_emit(cs, centroid_priority >> 32);
845
846 /* GFX9: Flush DFSM when the AA mode changes. */
847 if (cmd_buffer->device->dfsm_allowed) {
848 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
849 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
850 }
851
852 cmd_buffer->state.context_roll_without_scissor_emitted = true;
853 }
854
855 static void
856 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
857 struct radv_pipeline *pipeline,
858 gl_shader_stage stage,
859 int idx, int count, uint32_t *values)
860 {
861 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
862 uint32_t base_reg = pipeline->user_data_0[stage];
863 if (loc->sgpr_idx == -1)
864 return;
865
866 assert(loc->num_sgprs == count);
867
868 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
869 radeon_emit_array(cmd_buffer->cs, values, count);
870 }
871
872 static void
873 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
874 struct radv_pipeline *pipeline)
875 {
876 int num_samples = pipeline->graphics.ms.num_samples;
877 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
878
879 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.needs_sample_positions)
880 cmd_buffer->sample_positions_needed = true;
881
882 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
883 return;
884
885 radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
886
887 cmd_buffer->state.context_roll_without_scissor_emitted = true;
888 }
889
890 static void
891 radv_update_binning_state(struct radv_cmd_buffer *cmd_buffer,
892 struct radv_pipeline *pipeline)
893 {
894 const struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
895
896
897 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
898 return;
899
900 if (old_pipeline &&
901 old_pipeline->graphics.binning.pa_sc_binner_cntl_0 == pipeline->graphics.binning.pa_sc_binner_cntl_0 &&
902 old_pipeline->graphics.binning.db_dfsm_control == pipeline->graphics.binning.db_dfsm_control)
903 return;
904
905 bool binning_flush = false;
906 if (cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA12 ||
907 cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA20 ||
908 cmd_buffer->device->physical_device->rad_info.family == CHIP_RAVEN2 ||
909 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
910 binning_flush = !old_pipeline ||
911 G_028C44_BINNING_MODE(old_pipeline->graphics.binning.pa_sc_binner_cntl_0) !=
912 G_028C44_BINNING_MODE(pipeline->graphics.binning.pa_sc_binner_cntl_0);
913 }
914
915 radeon_set_context_reg(cmd_buffer->cs, R_028C44_PA_SC_BINNER_CNTL_0,
916 pipeline->graphics.binning.pa_sc_binner_cntl_0 |
917 S_028C44_FLUSH_ON_BINNING_TRANSITION(!!binning_flush));
918
919 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
920 radeon_set_context_reg(cmd_buffer->cs, R_028038_DB_DFSM_CONTROL,
921 pipeline->graphics.binning.db_dfsm_control);
922 } else {
923 radeon_set_context_reg(cmd_buffer->cs, R_028060_DB_DFSM_CONTROL,
924 pipeline->graphics.binning.db_dfsm_control);
925 }
926
927 cmd_buffer->state.context_roll_without_scissor_emitted = true;
928 }
929
930
931 static void
932 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
933 struct radv_shader_variant *shader)
934 {
935 uint64_t va;
936
937 if (!shader)
938 return;
939
940 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
941
942 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
943 }
944
945 static void
946 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
947 struct radv_pipeline *pipeline,
948 bool vertex_stage_only)
949 {
950 struct radv_cmd_state *state = &cmd_buffer->state;
951 uint32_t mask = state->prefetch_L2_mask;
952
953 if (vertex_stage_only) {
954 /* Fast prefetch path for starting draws as soon as possible.
955 */
956 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
957 RADV_PREFETCH_VBO_DESCRIPTORS);
958 }
959
960 if (mask & RADV_PREFETCH_VS)
961 radv_emit_shader_prefetch(cmd_buffer,
962 pipeline->shaders[MESA_SHADER_VERTEX]);
963
964 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
965 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
966
967 if (mask & RADV_PREFETCH_TCS)
968 radv_emit_shader_prefetch(cmd_buffer,
969 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
970
971 if (mask & RADV_PREFETCH_TES)
972 radv_emit_shader_prefetch(cmd_buffer,
973 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
974
975 if (mask & RADV_PREFETCH_GS) {
976 radv_emit_shader_prefetch(cmd_buffer,
977 pipeline->shaders[MESA_SHADER_GEOMETRY]);
978 if (radv_pipeline_has_gs_copy_shader(pipeline))
979 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
980 }
981
982 if (mask & RADV_PREFETCH_PS)
983 radv_emit_shader_prefetch(cmd_buffer,
984 pipeline->shaders[MESA_SHADER_FRAGMENT]);
985
986 state->prefetch_L2_mask &= ~mask;
987 }
988
989 static void
990 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
991 {
992 if (!cmd_buffer->device->physical_device->rad_info.rbplus_allowed)
993 return;
994
995 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
996 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
997
998 unsigned sx_ps_downconvert = 0;
999 unsigned sx_blend_opt_epsilon = 0;
1000 unsigned sx_blend_opt_control = 0;
1001
1002 if (!cmd_buffer->state.attachments || !subpass)
1003 return;
1004
1005 for (unsigned i = 0; i < subpass->color_count; ++i) {
1006 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1007 /* We don't set the DISABLE bits, because the HW can't have holes,
1008 * so the SPI color format is set to 32-bit 1-component. */
1009 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1010 continue;
1011 }
1012
1013 int idx = subpass->color_attachments[i].attachment;
1014 struct radv_color_buffer_info *cb = &cmd_buffer->state.attachments[idx].cb;
1015
1016 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
1017 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
1018 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
1019 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
1020
1021 bool has_alpha, has_rgb;
1022
1023 /* Set if RGB and A are present. */
1024 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
1025
1026 if (format == V_028C70_COLOR_8 ||
1027 format == V_028C70_COLOR_16 ||
1028 format == V_028C70_COLOR_32)
1029 has_rgb = !has_alpha;
1030 else
1031 has_rgb = true;
1032
1033 /* Check the colormask and export format. */
1034 if (!(colormask & 0x7))
1035 has_rgb = false;
1036 if (!(colormask & 0x8))
1037 has_alpha = false;
1038
1039 if (spi_format == V_028714_SPI_SHADER_ZERO) {
1040 has_rgb = false;
1041 has_alpha = false;
1042 }
1043
1044 /* Disable value checking for disabled channels. */
1045 if (!has_rgb)
1046 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1047 if (!has_alpha)
1048 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1049
1050 /* Enable down-conversion for 32bpp and smaller formats. */
1051 switch (format) {
1052 case V_028C70_COLOR_8:
1053 case V_028C70_COLOR_8_8:
1054 case V_028C70_COLOR_8_8_8_8:
1055 /* For 1 and 2-channel formats, use the superset thereof. */
1056 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
1057 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1058 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1059 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
1060 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
1061 }
1062 break;
1063
1064 case V_028C70_COLOR_5_6_5:
1065 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1066 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
1067 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
1068 }
1069 break;
1070
1071 case V_028C70_COLOR_1_5_5_5:
1072 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1073 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
1074 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
1075 }
1076 break;
1077
1078 case V_028C70_COLOR_4_4_4_4:
1079 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1080 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
1081 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
1082 }
1083 break;
1084
1085 case V_028C70_COLOR_32:
1086 if (swap == V_028C70_SWAP_STD &&
1087 spi_format == V_028714_SPI_SHADER_32_R)
1088 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1089 else if (swap == V_028C70_SWAP_ALT_REV &&
1090 spi_format == V_028714_SPI_SHADER_32_AR)
1091 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
1092 break;
1093
1094 case V_028C70_COLOR_16:
1095 case V_028C70_COLOR_16_16:
1096 /* For 1-channel formats, use the superset thereof. */
1097 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
1098 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
1099 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1100 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1101 if (swap == V_028C70_SWAP_STD ||
1102 swap == V_028C70_SWAP_STD_REV)
1103 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
1104 else
1105 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
1106 }
1107 break;
1108
1109 case V_028C70_COLOR_10_11_11:
1110 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1111 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
1112 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
1113 }
1114 break;
1115
1116 case V_028C70_COLOR_2_10_10_10:
1117 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1118 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
1119 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
1120 }
1121 break;
1122 }
1123 }
1124
1125 /* Do not set the DISABLE bits for the unused attachments, as that
1126 * breaks dual source blending in SkQP and does not seem to improve
1127 * performance. */
1128
1129 if (sx_ps_downconvert == cmd_buffer->state.last_sx_ps_downconvert &&
1130 sx_blend_opt_epsilon == cmd_buffer->state.last_sx_blend_opt_epsilon &&
1131 sx_blend_opt_control == cmd_buffer->state.last_sx_blend_opt_control)
1132 return;
1133
1134 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
1135 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
1136 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
1137 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
1138
1139 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1140
1141 cmd_buffer->state.last_sx_ps_downconvert = sx_ps_downconvert;
1142 cmd_buffer->state.last_sx_blend_opt_epsilon = sx_blend_opt_epsilon;
1143 cmd_buffer->state.last_sx_blend_opt_control = sx_blend_opt_control;
1144 }
1145
1146 static void
1147 radv_emit_batch_break_on_new_ps(struct radv_cmd_buffer *cmd_buffer)
1148 {
1149 if (!cmd_buffer->device->pbb_allowed)
1150 return;
1151
1152 struct radv_binning_settings settings =
1153 radv_get_binning_settings(cmd_buffer->device->physical_device);
1154 bool break_for_new_ps =
1155 (!cmd_buffer->state.emitted_pipeline ||
1156 cmd_buffer->state.emitted_pipeline->shaders[MESA_SHADER_FRAGMENT] !=
1157 cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT]) &&
1158 (settings.context_states_per_bin > 1 ||
1159 settings.persistent_states_per_bin > 1);
1160 bool break_for_new_cb_target_mask =
1161 (!cmd_buffer->state.emitted_pipeline ||
1162 cmd_buffer->state.emitted_pipeline->graphics.cb_target_mask !=
1163 cmd_buffer->state.pipeline->graphics.cb_target_mask) &&
1164 settings.context_states_per_bin > 1;
1165
1166 if (!break_for_new_ps && !break_for_new_cb_target_mask)
1167 return;
1168
1169 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1170 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1171 }
1172
1173 static void
1174 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1175 {
1176 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1177
1178 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1179 return;
1180
1181 radv_update_multisample_state(cmd_buffer, pipeline);
1182 radv_update_binning_state(cmd_buffer, pipeline);
1183
1184 cmd_buffer->scratch_size_per_wave_needed = MAX2(cmd_buffer->scratch_size_per_wave_needed,
1185 pipeline->scratch_bytes_per_wave);
1186 cmd_buffer->scratch_waves_wanted = MAX2(cmd_buffer->scratch_waves_wanted,
1187 pipeline->max_waves);
1188
1189 if (!cmd_buffer->state.emitted_pipeline ||
1190 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1191 pipeline->graphics.can_use_guardband)
1192 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1193
1194 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
1195
1196 if (!cmd_buffer->state.emitted_pipeline ||
1197 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
1198 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
1199 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
1200 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
1201 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
1202 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1203 }
1204
1205 radv_emit_batch_break_on_new_ps(cmd_buffer);
1206
1207 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
1208 if (!pipeline->shaders[i])
1209 continue;
1210
1211 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1212 pipeline->shaders[i]->bo);
1213 }
1214
1215 if (radv_pipeline_has_gs_copy_shader(pipeline))
1216 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1217 pipeline->gs_copy_shader->bo);
1218
1219 if (unlikely(cmd_buffer->device->trace_bo))
1220 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1221
1222 cmd_buffer->state.emitted_pipeline = pipeline;
1223
1224 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1225 }
1226
1227 static void
1228 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1229 {
1230 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1231 cmd_buffer->state.dynamic.viewport.viewports);
1232 }
1233
1234 static void
1235 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1236 {
1237 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1238
1239 si_write_scissors(cmd_buffer->cs, 0, count,
1240 cmd_buffer->state.dynamic.scissor.scissors,
1241 cmd_buffer->state.dynamic.viewport.viewports,
1242 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1243
1244 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1245 }
1246
1247 static void
1248 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1249 {
1250 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1251 return;
1252
1253 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1254 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1255 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1256 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1257 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1258 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1259 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1260 }
1261 }
1262
1263 static void
1264 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1265 {
1266 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1267
1268 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1269 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1270 }
1271
1272 static void
1273 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1274 {
1275 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1276
1277 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1278 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1279 }
1280
1281 static void
1282 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1283 {
1284 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1285
1286 radeon_set_context_reg_seq(cmd_buffer->cs,
1287 R_028430_DB_STENCILREFMASK, 2);
1288 radeon_emit(cmd_buffer->cs,
1289 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1290 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1291 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1292 S_028430_STENCILOPVAL(1));
1293 radeon_emit(cmd_buffer->cs,
1294 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1295 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1296 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1297 S_028434_STENCILOPVAL_BF(1));
1298 }
1299
1300 static void
1301 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1302 {
1303 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1304
1305 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1306 fui(d->depth_bounds.min));
1307 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1308 fui(d->depth_bounds.max));
1309 }
1310
1311 static void
1312 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1313 {
1314 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1315 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1316 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1317
1318
1319 radeon_set_context_reg_seq(cmd_buffer->cs,
1320 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1321 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1322 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1323 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1324 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1325 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1326 }
1327
1328 static void
1329 radv_emit_line_stipple(struct radv_cmd_buffer *cmd_buffer)
1330 {
1331 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1332 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1333 uint32_t auto_reset_cntl = 1;
1334
1335 if (pipeline->graphics.topology == VK_PRIMITIVE_TOPOLOGY_LINE_STRIP)
1336 auto_reset_cntl = 2;
1337
1338 radeon_set_context_reg(cmd_buffer->cs, R_028A0C_PA_SC_LINE_STIPPLE,
1339 S_028A0C_LINE_PATTERN(d->line_stipple.pattern) |
1340 S_028A0C_REPEAT_COUNT(d->line_stipple.factor - 1) |
1341 S_028A0C_AUTO_RESET_CNTL(auto_reset_cntl));
1342 }
1343
1344 static void
1345 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1346 int index,
1347 struct radv_color_buffer_info *cb,
1348 struct radv_image_view *iview,
1349 VkImageLayout layout,
1350 bool in_render_loop)
1351 {
1352 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
1353 uint32_t cb_color_info = cb->cb_color_info;
1354 struct radv_image *image = iview->image;
1355
1356 if (!radv_layout_dcc_compressed(cmd_buffer->device, image, layout, in_render_loop,
1357 radv_image_queue_family_mask(image,
1358 cmd_buffer->queue_family_index,
1359 cmd_buffer->queue_family_index))) {
1360 cb_color_info &= C_028C70_DCC_ENABLE;
1361 }
1362
1363 if (radv_image_is_tc_compat_cmask(image) &&
1364 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1365 radv_is_dcc_decompress_pipeline(cmd_buffer))) {
1366 /* If this bit is set, the FMASK decompression operation
1367 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1368 */
1369 cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
1370 }
1371
1372 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1373 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1374 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1375 radeon_emit(cmd_buffer->cs, 0);
1376 radeon_emit(cmd_buffer->cs, 0);
1377 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1378 radeon_emit(cmd_buffer->cs, cb_color_info);
1379 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1380 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1381 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1382 radeon_emit(cmd_buffer->cs, 0);
1383 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1384 radeon_emit(cmd_buffer->cs, 0);
1385
1386 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 1);
1387 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1388
1389 radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4,
1390 cb->cb_color_base >> 32);
1391 radeon_set_context_reg(cmd_buffer->cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + index * 4,
1392 cb->cb_color_cmask >> 32);
1393 radeon_set_context_reg(cmd_buffer->cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + index * 4,
1394 cb->cb_color_fmask >> 32);
1395 radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4,
1396 cb->cb_dcc_base >> 32);
1397 radeon_set_context_reg(cmd_buffer->cs, R_028EC0_CB_COLOR0_ATTRIB2 + index * 4,
1398 cb->cb_color_attrib2);
1399 radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4,
1400 cb->cb_color_attrib3);
1401 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1402 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1403 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1404 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1405 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1406 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1407 radeon_emit(cmd_buffer->cs, cb_color_info);
1408 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1409 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1410 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1411 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1412 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1413 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1414
1415 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1416 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1417 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1418
1419 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1420 cb->cb_mrt_epitch);
1421 } else {
1422 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1423 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1424 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1425 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1426 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1427 radeon_emit(cmd_buffer->cs, cb_color_info);
1428 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1429 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1430 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1431 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1432 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1433 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1434
1435 if (is_vi) { /* DCC BASE */
1436 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1437 }
1438 }
1439
1440 if (radv_dcc_enabled(image, iview->base_mip)) {
1441 /* Drawing with DCC enabled also compresses colorbuffers. */
1442 VkImageSubresourceRange range = {
1443 .aspectMask = iview->aspect_mask,
1444 .baseMipLevel = iview->base_mip,
1445 .levelCount = iview->level_count,
1446 .baseArrayLayer = iview->base_layer,
1447 .layerCount = iview->layer_count,
1448 };
1449
1450 radv_update_dcc_metadata(cmd_buffer, image, &range, true);
1451 }
1452 }
1453
1454 static void
1455 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1456 struct radv_ds_buffer_info *ds,
1457 const struct radv_image_view *iview,
1458 VkImageLayout layout,
1459 bool in_render_loop, bool requires_cond_exec)
1460 {
1461 const struct radv_image *image = iview->image;
1462 uint32_t db_z_info = ds->db_z_info;
1463 uint32_t db_z_info_reg;
1464
1465 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug ||
1466 !radv_image_is_tc_compat_htile(image))
1467 return;
1468
1469 if (!radv_layout_is_htile_compressed(image, layout, in_render_loop,
1470 radv_image_queue_family_mask(image,
1471 cmd_buffer->queue_family_index,
1472 cmd_buffer->queue_family_index))) {
1473 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1474 }
1475
1476 db_z_info &= C_028040_ZRANGE_PRECISION;
1477
1478 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1479 db_z_info_reg = R_028038_DB_Z_INFO;
1480 } else {
1481 db_z_info_reg = R_028040_DB_Z_INFO;
1482 }
1483
1484 /* When we don't know the last fast clear value we need to emit a
1485 * conditional packet that will eventually skip the following
1486 * SET_CONTEXT_REG packet.
1487 */
1488 if (requires_cond_exec) {
1489 uint64_t va = radv_get_tc_compat_zrange_va(image, iview->base_mip);
1490
1491 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1492 radeon_emit(cmd_buffer->cs, va);
1493 radeon_emit(cmd_buffer->cs, va >> 32);
1494 radeon_emit(cmd_buffer->cs, 0);
1495 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1496 }
1497
1498 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1499 }
1500
1501 static void
1502 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1503 struct radv_ds_buffer_info *ds,
1504 struct radv_image_view *iview,
1505 VkImageLayout layout,
1506 bool in_render_loop)
1507 {
1508 const struct radv_image *image = iview->image;
1509 uint32_t db_z_info = ds->db_z_info;
1510 uint32_t db_stencil_info = ds->db_stencil_info;
1511
1512 if (!radv_layout_is_htile_compressed(image, layout, in_render_loop,
1513 radv_image_queue_family_mask(image,
1514 cmd_buffer->queue_family_index,
1515 cmd_buffer->queue_family_index))) {
1516 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1517 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1518 }
1519
1520 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1521 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1522
1523 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1524 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1525 radeon_set_context_reg(cmd_buffer->cs, R_02801C_DB_DEPTH_SIZE_XY, ds->db_depth_size);
1526
1527 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 7);
1528 radeon_emit(cmd_buffer->cs, S_02803C_RESOURCE_LEVEL(1));
1529 radeon_emit(cmd_buffer->cs, db_z_info);
1530 radeon_emit(cmd_buffer->cs, db_stencil_info);
1531 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1532 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1533 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1534 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1535
1536 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_READ_BASE_HI, 5);
1537 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1538 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1539 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1540 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1541 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1542 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1543 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1544 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1545 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1546 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1547
1548 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1549 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1550 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1551 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1552 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1553 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1554 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1555 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1556 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1557 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1558 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1559
1560 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1561 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1562 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1563 } else {
1564 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1565
1566 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1567 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1568 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1569 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1570 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1571 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1572 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1573 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1574 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1575 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1576
1577 }
1578
1579 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1580 radv_update_zrange_precision(cmd_buffer, ds, iview, layout,
1581 in_render_loop, true);
1582
1583 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1584 ds->pa_su_poly_offset_db_fmt_cntl);
1585 }
1586
1587 /**
1588 * Update the fast clear depth/stencil values if the image is bound as a
1589 * depth/stencil buffer.
1590 */
1591 static void
1592 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1593 const struct radv_image_view *iview,
1594 VkClearDepthStencilValue ds_clear_value,
1595 VkImageAspectFlags aspects)
1596 {
1597 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1598 const struct radv_image *image = iview->image;
1599 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1600 uint32_t att_idx;
1601
1602 if (!cmd_buffer->state.attachments || !subpass)
1603 return;
1604
1605 if (!subpass->depth_stencil_attachment)
1606 return;
1607
1608 att_idx = subpass->depth_stencil_attachment->attachment;
1609 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1610 return;
1611
1612 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1613 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1614 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1615 radeon_emit(cs, ds_clear_value.stencil);
1616 radeon_emit(cs, fui(ds_clear_value.depth));
1617 } else if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1618 radeon_set_context_reg_seq(cs, R_02802C_DB_DEPTH_CLEAR, 1);
1619 radeon_emit(cs, fui(ds_clear_value.depth));
1620 } else {
1621 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1622 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 1);
1623 radeon_emit(cs, ds_clear_value.stencil);
1624 }
1625
1626 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1627 * only needed when clearing Z to 0.0.
1628 */
1629 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1630 ds_clear_value.depth == 0.0) {
1631 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1632 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
1633
1634 radv_update_zrange_precision(cmd_buffer, &cmd_buffer->state.attachments[att_idx].ds,
1635 iview, layout, in_render_loop, false);
1636 }
1637
1638 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1639 }
1640
1641 /**
1642 * Set the clear depth/stencil values to the image's metadata.
1643 */
1644 static void
1645 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1646 struct radv_image *image,
1647 const VkImageSubresourceRange *range,
1648 VkClearDepthStencilValue ds_clear_value,
1649 VkImageAspectFlags aspects)
1650 {
1651 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1652 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel);
1653 uint32_t level_count = radv_get_levelCount(image, range);
1654
1655 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1656 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1657 /* Use the fastest way when both aspects are used. */
1658 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + 2 * level_count, cmd_buffer->state.predicating));
1659 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1660 S_370_WR_CONFIRM(1) |
1661 S_370_ENGINE_SEL(V_370_PFP));
1662 radeon_emit(cs, va);
1663 radeon_emit(cs, va >> 32);
1664
1665 for (uint32_t l = 0; l < level_count; l++) {
1666 radeon_emit(cs, ds_clear_value.stencil);
1667 radeon_emit(cs, fui(ds_clear_value.depth));
1668 }
1669 } else {
1670 /* Otherwise we need one WRITE_DATA packet per level. */
1671 for (uint32_t l = 0; l < level_count; l++) {
1672 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel + l);
1673 unsigned value;
1674
1675 if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1676 value = fui(ds_clear_value.depth);
1677 va += 4;
1678 } else {
1679 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1680 value = ds_clear_value.stencil;
1681 }
1682
1683 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1684 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1685 S_370_WR_CONFIRM(1) |
1686 S_370_ENGINE_SEL(V_370_PFP));
1687 radeon_emit(cs, va);
1688 radeon_emit(cs, va >> 32);
1689 radeon_emit(cs, value);
1690 }
1691 }
1692 }
1693
1694 /**
1695 * Update the TC-compat metadata value for this image.
1696 */
1697 static void
1698 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1699 struct radv_image *image,
1700 const VkImageSubresourceRange *range,
1701 uint32_t value)
1702 {
1703 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1704
1705 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug)
1706 return;
1707
1708 uint64_t va = radv_get_tc_compat_zrange_va(image, range->baseMipLevel);
1709 uint32_t level_count = radv_get_levelCount(image, range);
1710
1711 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + level_count, cmd_buffer->state.predicating));
1712 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1713 S_370_WR_CONFIRM(1) |
1714 S_370_ENGINE_SEL(V_370_PFP));
1715 radeon_emit(cs, va);
1716 radeon_emit(cs, va >> 32);
1717
1718 for (uint32_t l = 0; l < level_count; l++)
1719 radeon_emit(cs, value);
1720 }
1721
1722 static void
1723 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1724 const struct radv_image_view *iview,
1725 VkClearDepthStencilValue ds_clear_value)
1726 {
1727 VkImageSubresourceRange range = {
1728 .aspectMask = iview->aspect_mask,
1729 .baseMipLevel = iview->base_mip,
1730 .levelCount = iview->level_count,
1731 .baseArrayLayer = iview->base_layer,
1732 .layerCount = iview->layer_count,
1733 };
1734 uint32_t cond_val;
1735
1736 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1737 * depth clear value is 0.0f.
1738 */
1739 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1740
1741 radv_set_tc_compat_zrange_metadata(cmd_buffer, iview->image, &range,
1742 cond_val);
1743 }
1744
1745 /**
1746 * Update the clear depth/stencil values for this image.
1747 */
1748 void
1749 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1750 const struct radv_image_view *iview,
1751 VkClearDepthStencilValue ds_clear_value,
1752 VkImageAspectFlags aspects)
1753 {
1754 VkImageSubresourceRange range = {
1755 .aspectMask = iview->aspect_mask,
1756 .baseMipLevel = iview->base_mip,
1757 .levelCount = iview->level_count,
1758 .baseArrayLayer = iview->base_layer,
1759 .layerCount = iview->layer_count,
1760 };
1761 struct radv_image *image = iview->image;
1762
1763 assert(radv_image_has_htile(image));
1764
1765 radv_set_ds_clear_metadata(cmd_buffer, iview->image, &range,
1766 ds_clear_value, aspects);
1767
1768 if (radv_image_is_tc_compat_htile(image) &&
1769 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1770 radv_update_tc_compat_zrange_metadata(cmd_buffer, iview,
1771 ds_clear_value);
1772 }
1773
1774 radv_update_bound_fast_clear_ds(cmd_buffer, iview, ds_clear_value,
1775 aspects);
1776 }
1777
1778 /**
1779 * Load the clear depth/stencil values from the image's metadata.
1780 */
1781 static void
1782 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1783 const struct radv_image_view *iview)
1784 {
1785 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1786 const struct radv_image *image = iview->image;
1787 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1788 uint64_t va = radv_get_ds_clear_value_va(image, iview->base_mip);
1789 unsigned reg_offset = 0, reg_count = 0;
1790
1791 if (!radv_image_has_htile(image))
1792 return;
1793
1794 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1795 ++reg_count;
1796 } else {
1797 ++reg_offset;
1798 va += 4;
1799 }
1800 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1801 ++reg_count;
1802
1803 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1804
1805 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
1806 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG_INDEX, 3, 0));
1807 radeon_emit(cs, va);
1808 radeon_emit(cs, va >> 32);
1809 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1810 radeon_emit(cs, reg_count);
1811 } else {
1812 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1813 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1814 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1815 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1816 radeon_emit(cs, va);
1817 radeon_emit(cs, va >> 32);
1818 radeon_emit(cs, reg >> 2);
1819 radeon_emit(cs, 0);
1820
1821 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1822 radeon_emit(cs, 0);
1823 }
1824 }
1825
1826 /*
1827 * With DCC some colors don't require CMASK elimination before being
1828 * used as a texture. This sets a predicate value to determine if the
1829 * cmask eliminate is required.
1830 */
1831 void
1832 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1833 struct radv_image *image,
1834 const VkImageSubresourceRange *range, bool value)
1835 {
1836 uint64_t pred_val = value;
1837 uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
1838 uint32_t level_count = radv_get_levelCount(image, range);
1839 uint32_t count = 2 * level_count;
1840
1841 assert(radv_dcc_enabled(image, range->baseMipLevel));
1842
1843 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1844 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1845 S_370_WR_CONFIRM(1) |
1846 S_370_ENGINE_SEL(V_370_PFP));
1847 radeon_emit(cmd_buffer->cs, va);
1848 radeon_emit(cmd_buffer->cs, va >> 32);
1849
1850 for (uint32_t l = 0; l < level_count; l++) {
1851 radeon_emit(cmd_buffer->cs, pred_val);
1852 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1853 }
1854 }
1855
1856 /**
1857 * Update the DCC predicate to reflect the compression state.
1858 */
1859 void
1860 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1861 struct radv_image *image,
1862 const VkImageSubresourceRange *range, bool value)
1863 {
1864 uint64_t pred_val = value;
1865 uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
1866 uint32_t level_count = radv_get_levelCount(image, range);
1867 uint32_t count = 2 * level_count;
1868
1869 assert(radv_dcc_enabled(image, range->baseMipLevel));
1870
1871 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1872 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1873 S_370_WR_CONFIRM(1) |
1874 S_370_ENGINE_SEL(V_370_PFP));
1875 radeon_emit(cmd_buffer->cs, va);
1876 radeon_emit(cmd_buffer->cs, va >> 32);
1877
1878 for (uint32_t l = 0; l < level_count; l++) {
1879 radeon_emit(cmd_buffer->cs, pred_val);
1880 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1881 }
1882 }
1883
1884 /**
1885 * Update the fast clear color values if the image is bound as a color buffer.
1886 */
1887 static void
1888 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1889 struct radv_image *image,
1890 int cb_idx,
1891 uint32_t color_values[2])
1892 {
1893 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1894 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1895 uint32_t att_idx;
1896
1897 if (!cmd_buffer->state.attachments || !subpass)
1898 return;
1899
1900 att_idx = subpass->color_attachments[cb_idx].attachment;
1901 if (att_idx == VK_ATTACHMENT_UNUSED)
1902 return;
1903
1904 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1905 return;
1906
1907 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1908 radeon_emit(cs, color_values[0]);
1909 radeon_emit(cs, color_values[1]);
1910
1911 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1912 }
1913
1914 /**
1915 * Set the clear color values to the image's metadata.
1916 */
1917 static void
1918 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1919 struct radv_image *image,
1920 const VkImageSubresourceRange *range,
1921 uint32_t color_values[2])
1922 {
1923 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1924 uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
1925 uint32_t level_count = radv_get_levelCount(image, range);
1926 uint32_t count = 2 * level_count;
1927
1928 assert(radv_image_has_cmask(image) ||
1929 radv_dcc_enabled(image, range->baseMipLevel));
1930
1931 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
1932 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1933 S_370_WR_CONFIRM(1) |
1934 S_370_ENGINE_SEL(V_370_PFP));
1935 radeon_emit(cs, va);
1936 radeon_emit(cs, va >> 32);
1937
1938 for (uint32_t l = 0; l < level_count; l++) {
1939 radeon_emit(cs, color_values[0]);
1940 radeon_emit(cs, color_values[1]);
1941 }
1942 }
1943
1944 /**
1945 * Update the clear color values for this image.
1946 */
1947 void
1948 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1949 const struct radv_image_view *iview,
1950 int cb_idx,
1951 uint32_t color_values[2])
1952 {
1953 struct radv_image *image = iview->image;
1954 VkImageSubresourceRange range = {
1955 .aspectMask = iview->aspect_mask,
1956 .baseMipLevel = iview->base_mip,
1957 .levelCount = iview->level_count,
1958 .baseArrayLayer = iview->base_layer,
1959 .layerCount = iview->layer_count,
1960 };
1961
1962 assert(radv_image_has_cmask(image) ||
1963 radv_dcc_enabled(image, iview->base_mip));
1964
1965 radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
1966
1967 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1968 color_values);
1969 }
1970
1971 /**
1972 * Load the clear color values from the image's metadata.
1973 */
1974 static void
1975 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1976 struct radv_image_view *iview,
1977 int cb_idx)
1978 {
1979 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1980 struct radv_image *image = iview->image;
1981 uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
1982
1983 if (!radv_image_has_cmask(image) &&
1984 !radv_dcc_enabled(image, iview->base_mip))
1985 return;
1986
1987 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1988
1989 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
1990 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG_INDEX, 3, cmd_buffer->state.predicating));
1991 radeon_emit(cs, va);
1992 radeon_emit(cs, va >> 32);
1993 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1994 radeon_emit(cs, 2);
1995 } else {
1996 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1997 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1998 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1999 COPY_DATA_COUNT_SEL);
2000 radeon_emit(cs, va);
2001 radeon_emit(cs, va >> 32);
2002 radeon_emit(cs, reg >> 2);
2003 radeon_emit(cs, 0);
2004
2005 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
2006 radeon_emit(cs, 0);
2007 }
2008 }
2009
2010 static void
2011 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
2012 {
2013 int i;
2014 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
2015 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2016
2017 /* this may happen for inherited secondary recording */
2018 if (!framebuffer)
2019 return;
2020
2021 for (i = 0; i < 8; ++i) {
2022 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
2023 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2024 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2025 continue;
2026 }
2027
2028 int idx = subpass->color_attachments[i].attachment;
2029 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
2030 VkImageLayout layout = subpass->color_attachments[i].layout;
2031 bool in_render_loop = subpass->color_attachments[i].in_render_loop;
2032
2033 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, iview->bo);
2034
2035 assert(iview->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
2036 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
2037 radv_emit_fb_color_state(cmd_buffer, i, &cmd_buffer->state.attachments[idx].cb, iview, layout, in_render_loop);
2038
2039 radv_load_color_clear_metadata(cmd_buffer, iview, i);
2040 }
2041
2042 if (subpass->depth_stencil_attachment) {
2043 int idx = subpass->depth_stencil_attachment->attachment;
2044 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
2045 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
2046 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
2047 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, cmd_buffer->state.attachments[idx].iview->bo);
2048
2049 radv_emit_fb_ds_state(cmd_buffer, &cmd_buffer->state.attachments[idx].ds, iview, layout, in_render_loop);
2050
2051 if (cmd_buffer->state.attachments[idx].ds.offset_scale != cmd_buffer->state.offset_scale) {
2052 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2053 cmd_buffer->state.offset_scale = cmd_buffer->state.attachments[idx].ds.offset_scale;
2054 }
2055 radv_load_ds_clear_metadata(cmd_buffer, iview);
2056 } else {
2057 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9)
2058 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
2059 else
2060 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
2061
2062 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
2063 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
2064 }
2065 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2066 S_028208_BR_X(framebuffer->width) |
2067 S_028208_BR_Y(framebuffer->height));
2068
2069 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
2070 bool disable_constant_encode =
2071 cmd_buffer->device->physical_device->rad_info.has_dcc_constant_encode;
2072 enum chip_class chip_class =
2073 cmd_buffer->device->physical_device->rad_info.chip_class;
2074 uint8_t watermark = chip_class >= GFX10 ? 6 : 4;
2075
2076 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
2077 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class <= GFX9) |
2078 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
2079 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
2080 }
2081
2082 if (cmd_buffer->device->dfsm_allowed) {
2083 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2084 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
2085 }
2086
2087 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
2088 }
2089
2090 static void
2091 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer, bool indirect)
2092 {
2093 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2094 struct radv_cmd_state *state = &cmd_buffer->state;
2095
2096 if (state->index_type != state->last_index_type) {
2097 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2098 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2099 cs, R_03090C_VGT_INDEX_TYPE,
2100 2, state->index_type);
2101 } else {
2102 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2103 radeon_emit(cs, state->index_type);
2104 }
2105
2106 state->last_index_type = state->index_type;
2107 }
2108
2109 /* For the direct indexed draws we use DRAW_INDEX_2, which includes
2110 * the index_va and max_index_count already. */
2111 if (!indirect)
2112 return;
2113
2114 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2115 radeon_emit(cs, state->index_va);
2116 radeon_emit(cs, state->index_va >> 32);
2117
2118 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2119 radeon_emit(cs, state->max_index_count);
2120
2121 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
2122 }
2123
2124 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
2125 {
2126 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
2127 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2128 uint32_t pa_sc_mode_cntl_1 =
2129 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
2130 uint32_t db_count_control;
2131
2132 if(!cmd_buffer->state.active_occlusion_queries) {
2133 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2134 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2135 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2136 has_perfect_queries) {
2137 /* Re-enable out-of-order rasterization if the
2138 * bound pipeline supports it and if it's has
2139 * been disabled before starting any perfect
2140 * occlusion queries.
2141 */
2142 radeon_set_context_reg(cmd_buffer->cs,
2143 R_028A4C_PA_SC_MODE_CNTL_1,
2144 pa_sc_mode_cntl_1);
2145 }
2146 }
2147 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
2148 } else {
2149 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2150 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
2151 bool gfx10_perfect = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10 && has_perfect_queries;
2152
2153 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2154 db_count_control =
2155 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
2156 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
2157 S_028004_SAMPLE_RATE(sample_rate) |
2158 S_028004_ZPASS_ENABLE(1) |
2159 S_028004_SLICE_EVEN_ENABLE(1) |
2160 S_028004_SLICE_ODD_ENABLE(1);
2161
2162 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2163 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2164 has_perfect_queries) {
2165 /* If the bound pipeline has enabled
2166 * out-of-order rasterization, we should
2167 * disable it before starting any perfect
2168 * occlusion queries.
2169 */
2170 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
2171
2172 radeon_set_context_reg(cmd_buffer->cs,
2173 R_028A4C_PA_SC_MODE_CNTL_1,
2174 pa_sc_mode_cntl_1);
2175 }
2176 } else {
2177 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
2178 S_028004_SAMPLE_RATE(sample_rate);
2179 }
2180 }
2181
2182 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
2183
2184 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2185 }
2186
2187 static void
2188 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
2189 {
2190 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
2191
2192 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
2193 radv_emit_viewport(cmd_buffer);
2194
2195 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
2196 !cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
2197 radv_emit_scissor(cmd_buffer);
2198
2199 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
2200 radv_emit_line_width(cmd_buffer);
2201
2202 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
2203 radv_emit_blend_constants(cmd_buffer);
2204
2205 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
2206 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
2207 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
2208 radv_emit_stencil(cmd_buffer);
2209
2210 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
2211 radv_emit_depth_bounds(cmd_buffer);
2212
2213 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
2214 radv_emit_depth_bias(cmd_buffer);
2215
2216 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
2217 radv_emit_discard_rectangle(cmd_buffer);
2218
2219 if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)
2220 radv_emit_sample_locations(cmd_buffer);
2221
2222 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE)
2223 radv_emit_line_stipple(cmd_buffer);
2224
2225 cmd_buffer->state.dirty &= ~states;
2226 }
2227
2228 static void
2229 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
2230 VkPipelineBindPoint bind_point)
2231 {
2232 struct radv_descriptor_state *descriptors_state =
2233 radv_get_descriptors_state(cmd_buffer, bind_point);
2234 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
2235 unsigned bo_offset;
2236
2237 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
2238 set->mapped_ptr,
2239 &bo_offset))
2240 return;
2241
2242 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2243 set->va += bo_offset;
2244 }
2245
2246 static void
2247 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
2248 VkPipelineBindPoint bind_point)
2249 {
2250 struct radv_descriptor_state *descriptors_state =
2251 radv_get_descriptors_state(cmd_buffer, bind_point);
2252 uint32_t size = MAX_SETS * 4;
2253 uint32_t offset;
2254 void *ptr;
2255
2256 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
2257 256, &offset, &ptr))
2258 return;
2259
2260 for (unsigned i = 0; i < MAX_SETS; i++) {
2261 uint32_t *uptr = ((uint32_t *)ptr) + i;
2262 uint64_t set_va = 0;
2263 struct radv_descriptor_set *set = descriptors_state->sets[i];
2264 if (descriptors_state->valid & (1u << i))
2265 set_va = set->va;
2266 uptr[0] = set_va & 0xffffffff;
2267 }
2268
2269 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2270 va += offset;
2271
2272 if (cmd_buffer->state.pipeline) {
2273 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
2274 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2275 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2276
2277 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
2278 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
2279 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2280
2281 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
2282 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2283 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2284
2285 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2286 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
2287 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2288
2289 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2290 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
2291 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2292 }
2293
2294 if (cmd_buffer->state.compute_pipeline)
2295 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
2296 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2297 }
2298
2299 static void
2300 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
2301 VkShaderStageFlags stages)
2302 {
2303 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2304 VK_PIPELINE_BIND_POINT_COMPUTE :
2305 VK_PIPELINE_BIND_POINT_GRAPHICS;
2306 struct radv_descriptor_state *descriptors_state =
2307 radv_get_descriptors_state(cmd_buffer, bind_point);
2308 struct radv_cmd_state *state = &cmd_buffer->state;
2309 bool flush_indirect_descriptors;
2310
2311 if (!descriptors_state->dirty)
2312 return;
2313
2314 if (descriptors_state->push_dirty)
2315 radv_flush_push_descriptors(cmd_buffer, bind_point);
2316
2317 flush_indirect_descriptors =
2318 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
2319 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
2320 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
2321 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
2322
2323 if (flush_indirect_descriptors)
2324 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
2325
2326 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2327 cmd_buffer->cs,
2328 MAX_SETS * MESA_SHADER_STAGES * 4);
2329
2330 if (cmd_buffer->state.pipeline) {
2331 radv_foreach_stage(stage, stages) {
2332 if (!cmd_buffer->state.pipeline->shaders[stage])
2333 continue;
2334
2335 radv_emit_descriptor_pointers(cmd_buffer,
2336 cmd_buffer->state.pipeline,
2337 descriptors_state, stage);
2338 }
2339 }
2340
2341 if (cmd_buffer->state.compute_pipeline &&
2342 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
2343 radv_emit_descriptor_pointers(cmd_buffer,
2344 cmd_buffer->state.compute_pipeline,
2345 descriptors_state,
2346 MESA_SHADER_COMPUTE);
2347 }
2348
2349 descriptors_state->dirty = 0;
2350 descriptors_state->push_dirty = false;
2351
2352 assert(cmd_buffer->cs->cdw <= cdw_max);
2353
2354 if (unlikely(cmd_buffer->device->trace_bo))
2355 radv_save_descriptors(cmd_buffer, bind_point);
2356 }
2357
2358 static void
2359 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
2360 VkShaderStageFlags stages)
2361 {
2362 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
2363 ? cmd_buffer->state.compute_pipeline
2364 : cmd_buffer->state.pipeline;
2365 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2366 VK_PIPELINE_BIND_POINT_COMPUTE :
2367 VK_PIPELINE_BIND_POINT_GRAPHICS;
2368 struct radv_descriptor_state *descriptors_state =
2369 radv_get_descriptors_state(cmd_buffer, bind_point);
2370 struct radv_pipeline_layout *layout = pipeline->layout;
2371 struct radv_shader_variant *shader, *prev_shader;
2372 bool need_push_constants = false;
2373 unsigned offset;
2374 void *ptr;
2375 uint64_t va;
2376
2377 stages &= cmd_buffer->push_constant_stages;
2378 if (!stages ||
2379 (!layout->push_constant_size && !layout->dynamic_offset_count))
2380 return;
2381
2382 radv_foreach_stage(stage, stages) {
2383 shader = radv_get_shader(pipeline, stage);
2384 if (!shader)
2385 continue;
2386
2387 need_push_constants |= shader->info.loads_push_constants;
2388 need_push_constants |= shader->info.loads_dynamic_offsets;
2389
2390 uint8_t base = shader->info.base_inline_push_consts;
2391 uint8_t count = shader->info.num_inline_push_consts;
2392
2393 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
2394 AC_UD_INLINE_PUSH_CONSTANTS,
2395 count,
2396 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
2397 }
2398
2399 if (need_push_constants) {
2400 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
2401 16 * layout->dynamic_offset_count,
2402 256, &offset, &ptr))
2403 return;
2404
2405 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
2406 memcpy((char*)ptr + layout->push_constant_size,
2407 descriptors_state->dynamic_buffers,
2408 16 * layout->dynamic_offset_count);
2409
2410 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2411 va += offset;
2412
2413 ASSERTED unsigned cdw_max =
2414 radeon_check_space(cmd_buffer->device->ws,
2415 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
2416
2417 prev_shader = NULL;
2418 radv_foreach_stage(stage, stages) {
2419 shader = radv_get_shader(pipeline, stage);
2420
2421 /* Avoid redundantly emitting the address for merged stages. */
2422 if (shader && shader != prev_shader) {
2423 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
2424 AC_UD_PUSH_CONSTANTS, va);
2425
2426 prev_shader = shader;
2427 }
2428 }
2429 assert(cmd_buffer->cs->cdw <= cdw_max);
2430 }
2431
2432 cmd_buffer->push_constant_stages &= ~stages;
2433 }
2434
2435 static void
2436 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
2437 bool pipeline_is_dirty)
2438 {
2439 if ((pipeline_is_dirty ||
2440 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
2441 cmd_buffer->state.pipeline->num_vertex_bindings &&
2442 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.has_vertex_buffers) {
2443 unsigned vb_offset;
2444 void *vb_ptr;
2445 uint32_t i = 0;
2446 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
2447 uint64_t va;
2448
2449 /* allocate some descriptor state for vertex buffers */
2450 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2451 &vb_offset, &vb_ptr))
2452 return;
2453
2454 for (i = 0; i < count; i++) {
2455 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2456 uint32_t offset;
2457 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2458 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[i];
2459 unsigned num_records;
2460
2461 if (!buffer)
2462 continue;
2463
2464 va = radv_buffer_get_va(buffer->bo);
2465
2466 offset = cmd_buffer->vertex_bindings[i].offset;
2467 va += offset + buffer->offset;
2468
2469 num_records = buffer->size - offset;
2470 if (cmd_buffer->device->physical_device->rad_info.chip_class != GFX8 && stride)
2471 num_records /= stride;
2472
2473 desc[0] = va;
2474 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2475 desc[2] = num_records;
2476 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2477 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2478 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2479 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2480
2481 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2482 /* OOB_SELECT chooses the out-of-bounds check:
2483 * - 1: index >= NUM_RECORDS (Structured)
2484 * - 3: offset >= NUM_RECORDS (Raw)
2485 */
2486 int oob_select = stride ? V_008F0C_OOB_SELECT_STRUCTURED : V_008F0C_OOB_SELECT_RAW;
2487
2488 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT) |
2489 S_008F0C_OOB_SELECT(oob_select) |
2490 S_008F0C_RESOURCE_LEVEL(1);
2491 } else {
2492 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2493 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2494 }
2495 }
2496
2497 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2498 va += vb_offset;
2499
2500 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2501 AC_UD_VS_VERTEX_BUFFERS, va);
2502
2503 cmd_buffer->state.vb_va = va;
2504 cmd_buffer->state.vb_size = count * 16;
2505 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2506 }
2507 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2508 }
2509
2510 static void
2511 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2512 {
2513 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2514 struct radv_userdata_info *loc;
2515 uint32_t base_reg;
2516
2517 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2518 if (!radv_get_shader(pipeline, stage))
2519 continue;
2520
2521 loc = radv_lookup_user_sgpr(pipeline, stage,
2522 AC_UD_STREAMOUT_BUFFERS);
2523 if (loc->sgpr_idx == -1)
2524 continue;
2525
2526 base_reg = pipeline->user_data_0[stage];
2527
2528 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2529 base_reg + loc->sgpr_idx * 4, va, false);
2530 }
2531
2532 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
2533 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2534 if (loc->sgpr_idx != -1) {
2535 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2536
2537 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2538 base_reg + loc->sgpr_idx * 4, va, false);
2539 }
2540 }
2541 }
2542
2543 static void
2544 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2545 {
2546 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2547 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2548 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2549 unsigned so_offset;
2550 void *so_ptr;
2551 uint64_t va;
2552
2553 /* Allocate some descriptor state for streamout buffers. */
2554 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2555 MAX_SO_BUFFERS * 16, 256,
2556 &so_offset, &so_ptr))
2557 return;
2558
2559 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2560 struct radv_buffer *buffer = sb[i].buffer;
2561 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2562
2563 if (!(so->enabled_mask & (1 << i)))
2564 continue;
2565
2566 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2567
2568 va += sb[i].offset;
2569
2570 /* Set the descriptor.
2571 *
2572 * On GFX8, the format must be non-INVALID, otherwise
2573 * the buffer will be considered not bound and store
2574 * instructions will be no-ops.
2575 */
2576 uint32_t size = 0xffffffff;
2577
2578 /* Compute the correct buffer size for NGG streamout
2579 * because it's used to determine the max emit per
2580 * buffer.
2581 */
2582 if (cmd_buffer->device->physical_device->use_ngg_streamout)
2583 size = buffer->size - sb[i].offset;
2584
2585 desc[0] = va;
2586 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2587 desc[2] = size;
2588 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2589 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2590 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2591 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2592
2593 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2594 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2595 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
2596 S_008F0C_RESOURCE_LEVEL(1);
2597 } else {
2598 desc[3] |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2599 }
2600 }
2601
2602 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2603 va += so_offset;
2604
2605 radv_emit_streamout_buffers(cmd_buffer, va);
2606 }
2607
2608 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2609 }
2610
2611 static void
2612 radv_flush_ngg_gs_state(struct radv_cmd_buffer *cmd_buffer)
2613 {
2614 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2615 struct radv_userdata_info *loc;
2616 uint32_t ngg_gs_state = 0;
2617 uint32_t base_reg;
2618
2619 if (!radv_pipeline_has_gs(pipeline) ||
2620 !radv_pipeline_has_ngg(pipeline))
2621 return;
2622
2623 /* By default NGG GS queries are disabled but they are enabled if the
2624 * command buffer has active GDS queries or if it's a secondary command
2625 * buffer that inherits the number of generated primitives.
2626 */
2627 if (cmd_buffer->state.active_pipeline_gds_queries ||
2628 (cmd_buffer->state.inherited_pipeline_statistics & VK_QUERY_PIPELINE_STATISTIC_GEOMETRY_SHADER_PRIMITIVES_BIT))
2629 ngg_gs_state = 1;
2630
2631 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_GEOMETRY,
2632 AC_UD_NGG_GS_STATE);
2633 base_reg = pipeline->user_data_0[MESA_SHADER_GEOMETRY];
2634 assert(loc->sgpr_idx != -1);
2635
2636 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
2637 ngg_gs_state);
2638 }
2639
2640 static void
2641 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2642 {
2643 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2644 radv_flush_streamout_descriptors(cmd_buffer);
2645 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2646 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2647 radv_flush_ngg_gs_state(cmd_buffer);
2648 }
2649
2650 struct radv_draw_info {
2651 /**
2652 * Number of vertices.
2653 */
2654 uint32_t count;
2655
2656 /**
2657 * Index of the first vertex.
2658 */
2659 int32_t vertex_offset;
2660
2661 /**
2662 * First instance id.
2663 */
2664 uint32_t first_instance;
2665
2666 /**
2667 * Number of instances.
2668 */
2669 uint32_t instance_count;
2670
2671 /**
2672 * First index (indexed draws only).
2673 */
2674 uint32_t first_index;
2675
2676 /**
2677 * Whether it's an indexed draw.
2678 */
2679 bool indexed;
2680
2681 /**
2682 * Indirect draw parameters resource.
2683 */
2684 struct radv_buffer *indirect;
2685 uint64_t indirect_offset;
2686 uint32_t stride;
2687
2688 /**
2689 * Draw count parameters resource.
2690 */
2691 struct radv_buffer *count_buffer;
2692 uint64_t count_buffer_offset;
2693
2694 /**
2695 * Stream output parameters resource.
2696 */
2697 struct radv_buffer *strmout_buffer;
2698 uint64_t strmout_buffer_offset;
2699 };
2700
2701 static uint32_t
2702 radv_get_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
2703 {
2704 switch (cmd_buffer->state.index_type) {
2705 case V_028A7C_VGT_INDEX_8:
2706 return 0xffu;
2707 case V_028A7C_VGT_INDEX_16:
2708 return 0xffffu;
2709 case V_028A7C_VGT_INDEX_32:
2710 return 0xffffffffu;
2711 default:
2712 unreachable("invalid index type");
2713 }
2714 }
2715
2716 static void
2717 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
2718 bool instanced_draw, bool indirect_draw,
2719 bool count_from_stream_output,
2720 uint32_t draw_vertex_count)
2721 {
2722 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2723 struct radv_cmd_state *state = &cmd_buffer->state;
2724 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2725 unsigned ia_multi_vgt_param;
2726
2727 ia_multi_vgt_param =
2728 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
2729 indirect_draw,
2730 count_from_stream_output,
2731 draw_vertex_count);
2732
2733 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2734 if (info->chip_class == GFX9) {
2735 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2736 cs,
2737 R_030960_IA_MULTI_VGT_PARAM,
2738 4, ia_multi_vgt_param);
2739 } else if (info->chip_class >= GFX7) {
2740 radeon_set_context_reg_idx(cs,
2741 R_028AA8_IA_MULTI_VGT_PARAM,
2742 1, ia_multi_vgt_param);
2743 } else {
2744 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2745 ia_multi_vgt_param);
2746 }
2747 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2748 }
2749 }
2750
2751 static void
2752 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2753 const struct radv_draw_info *draw_info)
2754 {
2755 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2756 struct radv_cmd_state *state = &cmd_buffer->state;
2757 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2758 int32_t primitive_reset_en;
2759
2760 /* Draw state. */
2761 if (info->chip_class < GFX10) {
2762 si_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2763 draw_info->indirect,
2764 !!draw_info->strmout_buffer,
2765 draw_info->indirect ? 0 : draw_info->count);
2766 }
2767
2768 /* Primitive restart. */
2769 primitive_reset_en =
2770 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2771
2772 if (primitive_reset_en != state->last_primitive_reset_en) {
2773 state->last_primitive_reset_en = primitive_reset_en;
2774 if (info->chip_class >= GFX9) {
2775 radeon_set_uconfig_reg(cs,
2776 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2777 primitive_reset_en);
2778 } else {
2779 radeon_set_context_reg(cs,
2780 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2781 primitive_reset_en);
2782 }
2783 }
2784
2785 if (primitive_reset_en) {
2786 uint32_t primitive_reset_index =
2787 radv_get_primitive_reset_index(cmd_buffer);
2788
2789 if (primitive_reset_index != state->last_primitive_reset_index) {
2790 radeon_set_context_reg(cs,
2791 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2792 primitive_reset_index);
2793 state->last_primitive_reset_index = primitive_reset_index;
2794 }
2795 }
2796
2797 if (draw_info->strmout_buffer) {
2798 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2799
2800 va += draw_info->strmout_buffer->offset +
2801 draw_info->strmout_buffer_offset;
2802
2803 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2804 draw_info->stride);
2805
2806 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2807 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2808 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2809 COPY_DATA_WR_CONFIRM);
2810 radeon_emit(cs, va);
2811 radeon_emit(cs, va >> 32);
2812 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2813 radeon_emit(cs, 0); /* unused */
2814
2815 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2816 }
2817 }
2818
2819 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2820 VkPipelineStageFlags src_stage_mask)
2821 {
2822 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2823 VK_PIPELINE_STAGE_TRANSFER_BIT |
2824 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2825 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2826 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2827 }
2828
2829 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2830 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2831 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2832 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2833 VK_PIPELINE_STAGE_TRANSFER_BIT |
2834 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2835 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2836 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2837 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2838 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2839 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2840 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2841 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2842 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2843 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2844 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2845 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2846 }
2847 }
2848
2849 static enum radv_cmd_flush_bits
2850 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2851 VkAccessFlags src_flags,
2852 struct radv_image *image)
2853 {
2854 bool flush_CB_meta = true, flush_DB_meta = true;
2855 enum radv_cmd_flush_bits flush_bits = 0;
2856 uint32_t b;
2857
2858 if (image) {
2859 if (!radv_image_has_CB_metadata(image))
2860 flush_CB_meta = false;
2861 if (!radv_image_has_htile(image))
2862 flush_DB_meta = false;
2863 }
2864
2865 for_each_bit(b, src_flags) {
2866 switch ((VkAccessFlagBits)(1 << b)) {
2867 case VK_ACCESS_SHADER_WRITE_BIT:
2868 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2869 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2870 flush_bits |= RADV_CMD_FLAG_WB_L2;
2871 break;
2872 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2873 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2874 if (flush_CB_meta)
2875 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2876 break;
2877 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2878 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2879 if (flush_DB_meta)
2880 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2881 break;
2882 case VK_ACCESS_TRANSFER_WRITE_BIT:
2883 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2884 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2885 RADV_CMD_FLAG_INV_L2;
2886
2887 if (flush_CB_meta)
2888 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2889 if (flush_DB_meta)
2890 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2891 break;
2892 default:
2893 break;
2894 }
2895 }
2896 return flush_bits;
2897 }
2898
2899 static enum radv_cmd_flush_bits
2900 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2901 VkAccessFlags dst_flags,
2902 struct radv_image *image)
2903 {
2904 bool flush_CB_meta = true, flush_DB_meta = true;
2905 enum radv_cmd_flush_bits flush_bits = 0;
2906 bool flush_CB = true, flush_DB = true;
2907 bool image_is_coherent = false;
2908 uint32_t b;
2909
2910 if (image) {
2911 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2912 flush_CB = false;
2913 flush_DB = false;
2914 }
2915
2916 if (!radv_image_has_CB_metadata(image))
2917 flush_CB_meta = false;
2918 if (!radv_image_has_htile(image))
2919 flush_DB_meta = false;
2920
2921 /* TODO: implement shader coherent for GFX10 */
2922
2923 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
2924 if (image->info.samples == 1 &&
2925 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2926 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2927 !vk_format_is_stencil(image->vk_format)) {
2928 /* Single-sample color and single-sample depth
2929 * (not stencil) are coherent with shaders on
2930 * GFX9.
2931 */
2932 image_is_coherent = true;
2933 }
2934 }
2935 }
2936
2937 for_each_bit(b, dst_flags) {
2938 switch ((VkAccessFlagBits)(1 << b)) {
2939 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2940 case VK_ACCESS_INDEX_READ_BIT:
2941 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2942 break;
2943 case VK_ACCESS_UNIFORM_READ_BIT:
2944 flush_bits |= RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_SCACHE;
2945 break;
2946 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2947 case VK_ACCESS_TRANSFER_READ_BIT:
2948 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2949 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
2950 RADV_CMD_FLAG_INV_L2;
2951 break;
2952 case VK_ACCESS_SHADER_READ_BIT:
2953 flush_bits |= RADV_CMD_FLAG_INV_VCACHE;
2954 /* Unlike LLVM, ACO uses SMEM for SSBOs and we have to
2955 * invalidate the scalar cache. */
2956 if (cmd_buffer->device->physical_device->use_aco &&
2957 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8)
2958 flush_bits |= RADV_CMD_FLAG_INV_SCACHE;
2959
2960 if (!image_is_coherent)
2961 flush_bits |= RADV_CMD_FLAG_INV_L2;
2962 break;
2963 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2964 if (flush_CB)
2965 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2966 if (flush_CB_meta)
2967 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2968 break;
2969 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2970 if (flush_DB)
2971 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2972 if (flush_DB_meta)
2973 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2974 break;
2975 default:
2976 break;
2977 }
2978 }
2979 return flush_bits;
2980 }
2981
2982 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2983 const struct radv_subpass_barrier *barrier)
2984 {
2985 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2986 NULL);
2987 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2988 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2989 NULL);
2990 }
2991
2992 uint32_t
2993 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
2994 {
2995 struct radv_cmd_state *state = &cmd_buffer->state;
2996 uint32_t subpass_id = state->subpass - state->pass->subpasses;
2997
2998 /* The id of this subpass shouldn't exceed the number of subpasses in
2999 * this render pass minus 1.
3000 */
3001 assert(subpass_id < state->pass->subpass_count);
3002 return subpass_id;
3003 }
3004
3005 static struct radv_sample_locations_state *
3006 radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer,
3007 uint32_t att_idx,
3008 bool begin_subpass)
3009 {
3010 struct radv_cmd_state *state = &cmd_buffer->state;
3011 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
3012 struct radv_image_view *view = state->attachments[att_idx].iview;
3013
3014 if (view->image->info.samples == 1)
3015 return NULL;
3016
3017 if (state->pass->attachments[att_idx].first_subpass_idx == subpass_id) {
3018 /* Return the initial sample locations if this is the initial
3019 * layout transition of the given subpass attachemnt.
3020 */
3021 if (state->attachments[att_idx].sample_location.count > 0)
3022 return &state->attachments[att_idx].sample_location;
3023 } else {
3024 /* Otherwise return the subpass sample locations if defined. */
3025 if (state->subpass_sample_locs) {
3026 /* Because the driver sets the current subpass before
3027 * initial layout transitions, we should use the sample
3028 * locations from the previous subpass to avoid an
3029 * off-by-one problem. Otherwise, use the sample
3030 * locations for the current subpass for final layout
3031 * transitions.
3032 */
3033 if (begin_subpass)
3034 subpass_id--;
3035
3036 for (uint32_t i = 0; i < state->num_subpass_sample_locs; i++) {
3037 if (state->subpass_sample_locs[i].subpass_idx == subpass_id)
3038 return &state->subpass_sample_locs[i].sample_location;
3039 }
3040 }
3041 }
3042
3043 return NULL;
3044 }
3045
3046 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
3047 struct radv_subpass_attachment att,
3048 bool begin_subpass)
3049 {
3050 unsigned idx = att.attachment;
3051 struct radv_image_view *view = cmd_buffer->state.attachments[idx].iview;
3052 struct radv_sample_locations_state *sample_locs;
3053 VkImageSubresourceRange range;
3054 range.aspectMask = view->aspect_mask;
3055 range.baseMipLevel = view->base_mip;
3056 range.levelCount = 1;
3057 range.baseArrayLayer = view->base_layer;
3058 range.layerCount = cmd_buffer->state.framebuffer->layers;
3059
3060 if (cmd_buffer->state.subpass->view_mask) {
3061 /* If the current subpass uses multiview, the driver might have
3062 * performed a fast color/depth clear to the whole image
3063 * (including all layers). To make sure the driver will
3064 * decompress the image correctly (if needed), we have to
3065 * account for the "real" number of layers. If the view mask is
3066 * sparse, this will decompress more layers than needed.
3067 */
3068 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
3069 }
3070
3071 /* Get the subpass sample locations for the given attachment, if NULL
3072 * is returned the driver will use the default HW locations.
3073 */
3074 sample_locs = radv_get_attachment_sample_locations(cmd_buffer, idx,
3075 begin_subpass);
3076
3077 /* Determine if the subpass uses separate depth/stencil layouts. */
3078 bool uses_separate_depth_stencil_layouts = false;
3079 if ((cmd_buffer->state.attachments[idx].current_layout !=
3080 cmd_buffer->state.attachments[idx].current_stencil_layout) ||
3081 (att.layout != att.stencil_layout)) {
3082 uses_separate_depth_stencil_layouts = true;
3083 }
3084
3085 /* For separate layouts, perform depth and stencil transitions
3086 * separately.
3087 */
3088 if (uses_separate_depth_stencil_layouts &&
3089 (range.aspectMask == (VK_IMAGE_ASPECT_DEPTH_BIT |
3090 VK_IMAGE_ASPECT_STENCIL_BIT))) {
3091 /* Depth-only transitions. */
3092 range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3093 radv_handle_image_transition(cmd_buffer,
3094 view->image,
3095 cmd_buffer->state.attachments[idx].current_layout,
3096 cmd_buffer->state.attachments[idx].current_in_render_loop,
3097 att.layout, att.in_render_loop,
3098 0, 0, &range, sample_locs);
3099
3100 /* Stencil-only transitions. */
3101 range.aspectMask = VK_IMAGE_ASPECT_STENCIL_BIT;
3102 radv_handle_image_transition(cmd_buffer,
3103 view->image,
3104 cmd_buffer->state.attachments[idx].current_stencil_layout,
3105 cmd_buffer->state.attachments[idx].current_in_render_loop,
3106 att.stencil_layout, att.in_render_loop,
3107 0, 0, &range, sample_locs);
3108 } else {
3109 radv_handle_image_transition(cmd_buffer,
3110 view->image,
3111 cmd_buffer->state.attachments[idx].current_layout,
3112 cmd_buffer->state.attachments[idx].current_in_render_loop,
3113 att.layout, att.in_render_loop,
3114 0, 0, &range, sample_locs);
3115 }
3116
3117 cmd_buffer->state.attachments[idx].current_layout = att.layout;
3118 cmd_buffer->state.attachments[idx].current_stencil_layout = att.stencil_layout;
3119 cmd_buffer->state.attachments[idx].current_in_render_loop = att.in_render_loop;
3120
3121
3122 }
3123
3124 void
3125 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
3126 const struct radv_subpass *subpass)
3127 {
3128 cmd_buffer->state.subpass = subpass;
3129
3130 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
3131 }
3132
3133 static VkResult
3134 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
3135 struct radv_render_pass *pass,
3136 const VkRenderPassBeginInfo *info)
3137 {
3138 const struct VkRenderPassSampleLocationsBeginInfoEXT *sample_locs =
3139 vk_find_struct_const(info->pNext,
3140 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT);
3141 struct radv_cmd_state *state = &cmd_buffer->state;
3142
3143 if (!sample_locs) {
3144 state->subpass_sample_locs = NULL;
3145 return VK_SUCCESS;
3146 }
3147
3148 for (uint32_t i = 0; i < sample_locs->attachmentInitialSampleLocationsCount; i++) {
3149 const VkAttachmentSampleLocationsEXT *att_sample_locs =
3150 &sample_locs->pAttachmentInitialSampleLocations[i];
3151 uint32_t att_idx = att_sample_locs->attachmentIndex;
3152 struct radv_image *image = cmd_buffer->state.attachments[att_idx].iview->image;
3153
3154 assert(vk_format_is_depth_or_stencil(image->vk_format));
3155
3156 /* From the Vulkan spec 1.1.108:
3157 *
3158 * "If the image referenced by the framebuffer attachment at
3159 * index attachmentIndex was not created with
3160 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
3161 * then the values specified in sampleLocationsInfo are
3162 * ignored."
3163 */
3164 if (!(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT))
3165 continue;
3166
3167 const VkSampleLocationsInfoEXT *sample_locs_info =
3168 &att_sample_locs->sampleLocationsInfo;
3169
3170 state->attachments[att_idx].sample_location.per_pixel =
3171 sample_locs_info->sampleLocationsPerPixel;
3172 state->attachments[att_idx].sample_location.grid_size =
3173 sample_locs_info->sampleLocationGridSize;
3174 state->attachments[att_idx].sample_location.count =
3175 sample_locs_info->sampleLocationsCount;
3176 typed_memcpy(&state->attachments[att_idx].sample_location.locations[0],
3177 sample_locs_info->pSampleLocations,
3178 sample_locs_info->sampleLocationsCount);
3179 }
3180
3181 state->subpass_sample_locs = vk_alloc(&cmd_buffer->pool->alloc,
3182 sample_locs->postSubpassSampleLocationsCount *
3183 sizeof(state->subpass_sample_locs[0]),
3184 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3185 if (state->subpass_sample_locs == NULL) {
3186 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3187 return cmd_buffer->record_result;
3188 }
3189
3190 state->num_subpass_sample_locs = sample_locs->postSubpassSampleLocationsCount;
3191
3192 for (uint32_t i = 0; i < sample_locs->postSubpassSampleLocationsCount; i++) {
3193 const VkSubpassSampleLocationsEXT *subpass_sample_locs_info =
3194 &sample_locs->pPostSubpassSampleLocations[i];
3195 const VkSampleLocationsInfoEXT *sample_locs_info =
3196 &subpass_sample_locs_info->sampleLocationsInfo;
3197
3198 state->subpass_sample_locs[i].subpass_idx =
3199 subpass_sample_locs_info->subpassIndex;
3200 state->subpass_sample_locs[i].sample_location.per_pixel =
3201 sample_locs_info->sampleLocationsPerPixel;
3202 state->subpass_sample_locs[i].sample_location.grid_size =
3203 sample_locs_info->sampleLocationGridSize;
3204 state->subpass_sample_locs[i].sample_location.count =
3205 sample_locs_info->sampleLocationsCount;
3206 typed_memcpy(&state->subpass_sample_locs[i].sample_location.locations[0],
3207 sample_locs_info->pSampleLocations,
3208 sample_locs_info->sampleLocationsCount);
3209 }
3210
3211 return VK_SUCCESS;
3212 }
3213
3214 static VkResult
3215 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
3216 struct radv_render_pass *pass,
3217 const VkRenderPassBeginInfo *info)
3218 {
3219 struct radv_cmd_state *state = &cmd_buffer->state;
3220 const struct VkRenderPassAttachmentBeginInfo *attachment_info = NULL;
3221
3222 if (info) {
3223 attachment_info = vk_find_struct_const(info->pNext,
3224 RENDER_PASS_ATTACHMENT_BEGIN_INFO);
3225 }
3226
3227
3228 if (pass->attachment_count == 0) {
3229 state->attachments = NULL;
3230 return VK_SUCCESS;
3231 }
3232
3233 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
3234 pass->attachment_count *
3235 sizeof(state->attachments[0]),
3236 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3237 if (state->attachments == NULL) {
3238 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3239 return cmd_buffer->record_result;
3240 }
3241
3242 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
3243 struct radv_render_pass_attachment *att = &pass->attachments[i];
3244 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
3245 VkImageAspectFlags clear_aspects = 0;
3246
3247 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
3248 /* color attachment */
3249 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3250 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
3251 }
3252 } else {
3253 /* depthstencil attachment */
3254 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
3255 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3256 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
3257 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3258 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
3259 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3260 }
3261 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3262 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3263 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3264 }
3265 }
3266
3267 state->attachments[i].pending_clear_aspects = clear_aspects;
3268 state->attachments[i].cleared_views = 0;
3269 if (clear_aspects && info) {
3270 assert(info->clearValueCount > i);
3271 state->attachments[i].clear_value = info->pClearValues[i];
3272 }
3273
3274 state->attachments[i].current_layout = att->initial_layout;
3275 state->attachments[i].current_stencil_layout = att->stencil_initial_layout;
3276 state->attachments[i].sample_location.count = 0;
3277
3278 struct radv_image_view *iview;
3279 if (attachment_info && attachment_info->attachmentCount > i) {
3280 iview = radv_image_view_from_handle(attachment_info->pAttachments[i]);
3281 } else {
3282 iview = state->framebuffer->attachments[i];
3283 }
3284
3285 state->attachments[i].iview = iview;
3286 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3287 radv_initialise_ds_surface(cmd_buffer->device, &state->attachments[i].ds, iview);
3288 } else {
3289 radv_initialise_color_surface(cmd_buffer->device, &state->attachments[i].cb, iview);
3290 }
3291 }
3292
3293 return VK_SUCCESS;
3294 }
3295
3296 VkResult radv_AllocateCommandBuffers(
3297 VkDevice _device,
3298 const VkCommandBufferAllocateInfo *pAllocateInfo,
3299 VkCommandBuffer *pCommandBuffers)
3300 {
3301 RADV_FROM_HANDLE(radv_device, device, _device);
3302 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
3303
3304 VkResult result = VK_SUCCESS;
3305 uint32_t i;
3306
3307 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
3308
3309 if (!list_is_empty(&pool->free_cmd_buffers)) {
3310 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
3311
3312 list_del(&cmd_buffer->pool_link);
3313 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
3314
3315 result = radv_reset_cmd_buffer(cmd_buffer);
3316 cmd_buffer->level = pAllocateInfo->level;
3317
3318 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
3319 } else {
3320 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
3321 &pCommandBuffers[i]);
3322 }
3323 if (result != VK_SUCCESS)
3324 break;
3325 }
3326
3327 if (result != VK_SUCCESS) {
3328 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
3329 i, pCommandBuffers);
3330
3331 /* From the Vulkan 1.0.66 spec:
3332 *
3333 * "vkAllocateCommandBuffers can be used to create multiple
3334 * command buffers. If the creation of any of those command
3335 * buffers fails, the implementation must destroy all
3336 * successfully created command buffer objects from this
3337 * command, set all entries of the pCommandBuffers array to
3338 * NULL and return the error."
3339 */
3340 memset(pCommandBuffers, 0,
3341 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
3342 }
3343
3344 return result;
3345 }
3346
3347 void radv_FreeCommandBuffers(
3348 VkDevice device,
3349 VkCommandPool commandPool,
3350 uint32_t commandBufferCount,
3351 const VkCommandBuffer *pCommandBuffers)
3352 {
3353 for (uint32_t i = 0; i < commandBufferCount; i++) {
3354 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
3355
3356 if (cmd_buffer) {
3357 if (cmd_buffer->pool) {
3358 list_del(&cmd_buffer->pool_link);
3359 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
3360 } else
3361 radv_cmd_buffer_destroy(cmd_buffer);
3362
3363 }
3364 }
3365 }
3366
3367 VkResult radv_ResetCommandBuffer(
3368 VkCommandBuffer commandBuffer,
3369 VkCommandBufferResetFlags flags)
3370 {
3371 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3372 return radv_reset_cmd_buffer(cmd_buffer);
3373 }
3374
3375 VkResult radv_BeginCommandBuffer(
3376 VkCommandBuffer commandBuffer,
3377 const VkCommandBufferBeginInfo *pBeginInfo)
3378 {
3379 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3380 VkResult result = VK_SUCCESS;
3381
3382 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
3383 /* If the command buffer has already been resetted with
3384 * vkResetCommandBuffer, no need to do it again.
3385 */
3386 result = radv_reset_cmd_buffer(cmd_buffer);
3387 if (result != VK_SUCCESS)
3388 return result;
3389 }
3390
3391 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
3392 cmd_buffer->state.last_primitive_reset_en = -1;
3393 cmd_buffer->state.last_index_type = -1;
3394 cmd_buffer->state.last_num_instances = -1;
3395 cmd_buffer->state.last_vertex_offset = -1;
3396 cmd_buffer->state.last_first_instance = -1;
3397 cmd_buffer->state.predication_type = -1;
3398 cmd_buffer->state.last_sx_ps_downconvert = -1;
3399 cmd_buffer->state.last_sx_blend_opt_epsilon = -1;
3400 cmd_buffer->state.last_sx_blend_opt_control = -1;
3401 cmd_buffer->usage_flags = pBeginInfo->flags;
3402
3403 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
3404 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
3405 assert(pBeginInfo->pInheritanceInfo);
3406 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
3407 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
3408
3409 struct radv_subpass *subpass =
3410 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
3411
3412 if (cmd_buffer->state.framebuffer) {
3413 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
3414 if (result != VK_SUCCESS)
3415 return result;
3416 }
3417
3418 cmd_buffer->state.inherited_pipeline_statistics =
3419 pBeginInfo->pInheritanceInfo->pipelineStatistics;
3420
3421 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3422 }
3423
3424 if (unlikely(cmd_buffer->device->trace_bo))
3425 radv_cmd_buffer_trace_emit(cmd_buffer);
3426
3427 radv_describe_begin_cmd_buffer(cmd_buffer);
3428
3429 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
3430
3431 return result;
3432 }
3433
3434 void radv_CmdBindVertexBuffers(
3435 VkCommandBuffer commandBuffer,
3436 uint32_t firstBinding,
3437 uint32_t bindingCount,
3438 const VkBuffer* pBuffers,
3439 const VkDeviceSize* pOffsets)
3440 {
3441 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3442 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
3443 bool changed = false;
3444
3445 /* We have to defer setting up vertex buffer since we need the buffer
3446 * stride from the pipeline. */
3447
3448 assert(firstBinding + bindingCount <= MAX_VBS);
3449 for (uint32_t i = 0; i < bindingCount; i++) {
3450 RADV_FROM_HANDLE(radv_buffer, buffer, pBuffers[i]);
3451 uint32_t idx = firstBinding + i;
3452
3453 if (!changed &&
3454 (vb[idx].buffer != buffer ||
3455 vb[idx].offset != pOffsets[i])) {
3456 changed = true;
3457 }
3458
3459 vb[idx].buffer = buffer;
3460 vb[idx].offset = pOffsets[i];
3461
3462 if (buffer) {
3463 radv_cs_add_buffer(cmd_buffer->device->ws,
3464 cmd_buffer->cs, vb[idx].buffer->bo);
3465 }
3466 }
3467
3468 if (!changed) {
3469 /* No state changes. */
3470 return;
3471 }
3472
3473 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
3474 }
3475
3476 static uint32_t
3477 vk_to_index_type(VkIndexType type)
3478 {
3479 switch (type) {
3480 case VK_INDEX_TYPE_UINT8_EXT:
3481 return V_028A7C_VGT_INDEX_8;
3482 case VK_INDEX_TYPE_UINT16:
3483 return V_028A7C_VGT_INDEX_16;
3484 case VK_INDEX_TYPE_UINT32:
3485 return V_028A7C_VGT_INDEX_32;
3486 default:
3487 unreachable("invalid index type");
3488 }
3489 }
3490
3491 static uint32_t
3492 radv_get_vgt_index_size(uint32_t type)
3493 {
3494 switch (type) {
3495 case V_028A7C_VGT_INDEX_8:
3496 return 1;
3497 case V_028A7C_VGT_INDEX_16:
3498 return 2;
3499 case V_028A7C_VGT_INDEX_32:
3500 return 4;
3501 default:
3502 unreachable("invalid index type");
3503 }
3504 }
3505
3506 void radv_CmdBindIndexBuffer(
3507 VkCommandBuffer commandBuffer,
3508 VkBuffer buffer,
3509 VkDeviceSize offset,
3510 VkIndexType indexType)
3511 {
3512 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3513 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
3514
3515 if (cmd_buffer->state.index_buffer == index_buffer &&
3516 cmd_buffer->state.index_offset == offset &&
3517 cmd_buffer->state.index_type == indexType) {
3518 /* No state changes. */
3519 return;
3520 }
3521
3522 cmd_buffer->state.index_buffer = index_buffer;
3523 cmd_buffer->state.index_offset = offset;
3524 cmd_buffer->state.index_type = vk_to_index_type(indexType);
3525 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
3526 cmd_buffer->state.index_va += index_buffer->offset + offset;
3527
3528 int index_size = radv_get_vgt_index_size(vk_to_index_type(indexType));
3529 cmd_buffer->state.max_index_count = (index_buffer->size - offset) / index_size;
3530 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3531 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
3532 }
3533
3534
3535 static void
3536 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3537 VkPipelineBindPoint bind_point,
3538 struct radv_descriptor_set *set, unsigned idx)
3539 {
3540 struct radeon_winsys *ws = cmd_buffer->device->ws;
3541
3542 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
3543
3544 assert(set);
3545 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
3546
3547 if (!cmd_buffer->device->use_global_bo_list) {
3548 for (unsigned j = 0; j < set->buffer_count; ++j)
3549 if (set->descriptors[j])
3550 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
3551 }
3552
3553 if(set->bo)
3554 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
3555 }
3556
3557 void radv_CmdBindDescriptorSets(
3558 VkCommandBuffer commandBuffer,
3559 VkPipelineBindPoint pipelineBindPoint,
3560 VkPipelineLayout _layout,
3561 uint32_t firstSet,
3562 uint32_t descriptorSetCount,
3563 const VkDescriptorSet* pDescriptorSets,
3564 uint32_t dynamicOffsetCount,
3565 const uint32_t* pDynamicOffsets)
3566 {
3567 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3568 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3569 unsigned dyn_idx = 0;
3570
3571 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
3572 struct radv_descriptor_state *descriptors_state =
3573 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3574
3575 for (unsigned i = 0; i < descriptorSetCount; ++i) {
3576 unsigned idx = i + firstSet;
3577 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
3578
3579 /* If the set is already bound we only need to update the
3580 * (potentially changed) dynamic offsets. */
3581 if (descriptors_state->sets[idx] != set ||
3582 !(descriptors_state->valid & (1u << idx))) {
3583 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
3584 }
3585
3586 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
3587 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
3588 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
3589 assert(dyn_idx < dynamicOffsetCount);
3590
3591 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
3592 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
3593 dst[0] = va;
3594 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
3595 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
3596 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3597 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3598 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3599 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3600
3601 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
3602 dst[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3603 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3604 S_008F0C_RESOURCE_LEVEL(1);
3605 } else {
3606 dst[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3607 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3608 }
3609
3610 cmd_buffer->push_constant_stages |=
3611 set->layout->dynamic_shader_stages;
3612 }
3613 }
3614 }
3615
3616 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3617 struct radv_descriptor_set *set,
3618 struct radv_descriptor_set_layout *layout,
3619 VkPipelineBindPoint bind_point)
3620 {
3621 struct radv_descriptor_state *descriptors_state =
3622 radv_get_descriptors_state(cmd_buffer, bind_point);
3623 set->size = layout->size;
3624 set->layout = layout;
3625
3626 if (descriptors_state->push_set.capacity < set->size) {
3627 size_t new_size = MAX2(set->size, 1024);
3628 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
3629 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
3630
3631 free(set->mapped_ptr);
3632 set->mapped_ptr = malloc(new_size);
3633
3634 if (!set->mapped_ptr) {
3635 descriptors_state->push_set.capacity = 0;
3636 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3637 return false;
3638 }
3639
3640 descriptors_state->push_set.capacity = new_size;
3641 }
3642
3643 return true;
3644 }
3645
3646 void radv_meta_push_descriptor_set(
3647 struct radv_cmd_buffer* cmd_buffer,
3648 VkPipelineBindPoint pipelineBindPoint,
3649 VkPipelineLayout _layout,
3650 uint32_t set,
3651 uint32_t descriptorWriteCount,
3652 const VkWriteDescriptorSet* pDescriptorWrites)
3653 {
3654 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3655 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
3656 unsigned bo_offset;
3657
3658 assert(set == 0);
3659 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3660
3661 push_set->size = layout->set[set].layout->size;
3662 push_set->layout = layout->set[set].layout;
3663
3664 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
3665 &bo_offset,
3666 (void**) &push_set->mapped_ptr))
3667 return;
3668
3669 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
3670 push_set->va += bo_offset;
3671
3672 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3673 radv_descriptor_set_to_handle(push_set),
3674 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3675
3676 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3677 }
3678
3679 void radv_CmdPushDescriptorSetKHR(
3680 VkCommandBuffer commandBuffer,
3681 VkPipelineBindPoint pipelineBindPoint,
3682 VkPipelineLayout _layout,
3683 uint32_t set,
3684 uint32_t descriptorWriteCount,
3685 const VkWriteDescriptorSet* pDescriptorWrites)
3686 {
3687 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3688 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3689 struct radv_descriptor_state *descriptors_state =
3690 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3691 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3692
3693 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3694
3695 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3696 layout->set[set].layout,
3697 pipelineBindPoint))
3698 return;
3699
3700 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3701 * because it is invalid, according to Vulkan spec.
3702 */
3703 for (int i = 0; i < descriptorWriteCount; i++) {
3704 ASSERTED const VkWriteDescriptorSet *writeset = &pDescriptorWrites[i];
3705 assert(writeset->descriptorType != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT);
3706 }
3707
3708 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3709 radv_descriptor_set_to_handle(push_set),
3710 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3711
3712 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3713 descriptors_state->push_dirty = true;
3714 }
3715
3716 void radv_CmdPushDescriptorSetWithTemplateKHR(
3717 VkCommandBuffer commandBuffer,
3718 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
3719 VkPipelineLayout _layout,
3720 uint32_t set,
3721 const void* pData)
3722 {
3723 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3724 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3725 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
3726 struct radv_descriptor_state *descriptors_state =
3727 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
3728 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3729
3730 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3731
3732 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3733 layout->set[set].layout,
3734 templ->bind_point))
3735 return;
3736
3737 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
3738 descriptorUpdateTemplate, pData);
3739
3740 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
3741 descriptors_state->push_dirty = true;
3742 }
3743
3744 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
3745 VkPipelineLayout layout,
3746 VkShaderStageFlags stageFlags,
3747 uint32_t offset,
3748 uint32_t size,
3749 const void* pValues)
3750 {
3751 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3752 memcpy(cmd_buffer->push_constants + offset, pValues, size);
3753 cmd_buffer->push_constant_stages |= stageFlags;
3754 }
3755
3756 VkResult radv_EndCommandBuffer(
3757 VkCommandBuffer commandBuffer)
3758 {
3759 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3760
3761 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
3762 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6)
3763 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WB_L2;
3764
3765 /* Make sure to sync all pending active queries at the end of
3766 * command buffer.
3767 */
3768 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
3769
3770 /* Since NGG streamout uses GDS, we need to make GDS idle when
3771 * we leave the IB, otherwise another process might overwrite
3772 * it while our shaders are busy.
3773 */
3774 if (cmd_buffer->gds_needed)
3775 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
3776
3777 si_emit_cache_flush(cmd_buffer);
3778 }
3779
3780 /* Make sure CP DMA is idle at the end of IBs because the kernel
3781 * doesn't wait for it.
3782 */
3783 si_cp_dma_wait_for_idle(cmd_buffer);
3784
3785 radv_describe_end_cmd_buffer(cmd_buffer);
3786
3787 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3788 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
3789
3790 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
3791 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3792
3793 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
3794
3795 return cmd_buffer->record_result;
3796 }
3797
3798 static void
3799 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
3800 {
3801 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3802
3803 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
3804 return;
3805
3806 assert(!pipeline->ctx_cs.cdw);
3807
3808 cmd_buffer->state.emitted_compute_pipeline = pipeline;
3809
3810 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
3811 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
3812
3813 cmd_buffer->compute_scratch_size_per_wave_needed = MAX2(cmd_buffer->compute_scratch_size_per_wave_needed,
3814 pipeline->scratch_bytes_per_wave);
3815 cmd_buffer->compute_scratch_waves_wanted = MAX2(cmd_buffer->compute_scratch_waves_wanted,
3816 pipeline->max_waves);
3817
3818 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3819 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
3820
3821 if (unlikely(cmd_buffer->device->trace_bo))
3822 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
3823 }
3824
3825 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
3826 VkPipelineBindPoint bind_point)
3827 {
3828 struct radv_descriptor_state *descriptors_state =
3829 radv_get_descriptors_state(cmd_buffer, bind_point);
3830
3831 descriptors_state->dirty |= descriptors_state->valid;
3832 }
3833
3834 void radv_CmdBindPipeline(
3835 VkCommandBuffer commandBuffer,
3836 VkPipelineBindPoint pipelineBindPoint,
3837 VkPipeline _pipeline)
3838 {
3839 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3840 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
3841
3842 switch (pipelineBindPoint) {
3843 case VK_PIPELINE_BIND_POINT_COMPUTE:
3844 if (cmd_buffer->state.compute_pipeline == pipeline)
3845 return;
3846 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3847
3848 cmd_buffer->state.compute_pipeline = pipeline;
3849 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
3850 break;
3851 case VK_PIPELINE_BIND_POINT_GRAPHICS:
3852 if (cmd_buffer->state.pipeline == pipeline)
3853 return;
3854 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3855
3856 cmd_buffer->state.pipeline = pipeline;
3857 if (!pipeline)
3858 break;
3859
3860 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
3861 cmd_buffer->push_constant_stages |= pipeline->active_stages;
3862
3863 /* the new vertex shader might not have the same user regs */
3864 cmd_buffer->state.last_first_instance = -1;
3865 cmd_buffer->state.last_vertex_offset = -1;
3866
3867 /* Prefetch all pipeline shaders at first draw time. */
3868 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
3869
3870 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX10 &&
3871 cmd_buffer->state.emitted_pipeline &&
3872 radv_pipeline_has_ngg(cmd_buffer->state.emitted_pipeline) &&
3873 !radv_pipeline_has_ngg(cmd_buffer->state.pipeline)) {
3874 /* Transitioning from NGG to legacy GS requires
3875 * VGT_FLUSH on Navi10-14. VGT_FLUSH is also emitted
3876 * at the beginning of IBs when legacy GS ring pointers
3877 * are set.
3878 */
3879 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
3880 }
3881
3882 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
3883 radv_bind_streamout_state(cmd_buffer, pipeline);
3884
3885 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
3886 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
3887 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
3888 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
3889
3890 if (radv_pipeline_has_tess(pipeline))
3891 cmd_buffer->tess_rings_needed = true;
3892 break;
3893 default:
3894 assert(!"invalid bind point");
3895 break;
3896 }
3897 }
3898
3899 void radv_CmdSetViewport(
3900 VkCommandBuffer commandBuffer,
3901 uint32_t firstViewport,
3902 uint32_t viewportCount,
3903 const VkViewport* pViewports)
3904 {
3905 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3906 struct radv_cmd_state *state = &cmd_buffer->state;
3907 ASSERTED const uint32_t total_count = firstViewport + viewportCount;
3908
3909 assert(firstViewport < MAX_VIEWPORTS);
3910 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
3911
3912 if (!memcmp(state->dynamic.viewport.viewports + firstViewport,
3913 pViewports, viewportCount * sizeof(*pViewports))) {
3914 return;
3915 }
3916
3917 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
3918 viewportCount * sizeof(*pViewports));
3919
3920 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
3921 }
3922
3923 void radv_CmdSetScissor(
3924 VkCommandBuffer commandBuffer,
3925 uint32_t firstScissor,
3926 uint32_t scissorCount,
3927 const VkRect2D* pScissors)
3928 {
3929 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3930 struct radv_cmd_state *state = &cmd_buffer->state;
3931 ASSERTED const uint32_t total_count = firstScissor + scissorCount;
3932
3933 assert(firstScissor < MAX_SCISSORS);
3934 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
3935
3936 if (!memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
3937 scissorCount * sizeof(*pScissors))) {
3938 return;
3939 }
3940
3941 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
3942 scissorCount * sizeof(*pScissors));
3943
3944 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
3945 }
3946
3947 void radv_CmdSetLineWidth(
3948 VkCommandBuffer commandBuffer,
3949 float lineWidth)
3950 {
3951 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3952
3953 if (cmd_buffer->state.dynamic.line_width == lineWidth)
3954 return;
3955
3956 cmd_buffer->state.dynamic.line_width = lineWidth;
3957 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
3958 }
3959
3960 void radv_CmdSetDepthBias(
3961 VkCommandBuffer commandBuffer,
3962 float depthBiasConstantFactor,
3963 float depthBiasClamp,
3964 float depthBiasSlopeFactor)
3965 {
3966 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3967 struct radv_cmd_state *state = &cmd_buffer->state;
3968
3969 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
3970 state->dynamic.depth_bias.clamp == depthBiasClamp &&
3971 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
3972 return;
3973 }
3974
3975 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
3976 state->dynamic.depth_bias.clamp = depthBiasClamp;
3977 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
3978
3979 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
3980 }
3981
3982 void radv_CmdSetBlendConstants(
3983 VkCommandBuffer commandBuffer,
3984 const float blendConstants[4])
3985 {
3986 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3987 struct radv_cmd_state *state = &cmd_buffer->state;
3988
3989 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
3990 return;
3991
3992 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
3993
3994 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
3995 }
3996
3997 void radv_CmdSetDepthBounds(
3998 VkCommandBuffer commandBuffer,
3999 float minDepthBounds,
4000 float maxDepthBounds)
4001 {
4002 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4003 struct radv_cmd_state *state = &cmd_buffer->state;
4004
4005 if (state->dynamic.depth_bounds.min == minDepthBounds &&
4006 state->dynamic.depth_bounds.max == maxDepthBounds) {
4007 return;
4008 }
4009
4010 state->dynamic.depth_bounds.min = minDepthBounds;
4011 state->dynamic.depth_bounds.max = maxDepthBounds;
4012
4013 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
4014 }
4015
4016 void radv_CmdSetStencilCompareMask(
4017 VkCommandBuffer commandBuffer,
4018 VkStencilFaceFlags faceMask,
4019 uint32_t compareMask)
4020 {
4021 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4022 struct radv_cmd_state *state = &cmd_buffer->state;
4023 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
4024 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
4025
4026 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4027 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4028 return;
4029 }
4030
4031 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4032 state->dynamic.stencil_compare_mask.front = compareMask;
4033 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4034 state->dynamic.stencil_compare_mask.back = compareMask;
4035
4036 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
4037 }
4038
4039 void radv_CmdSetStencilWriteMask(
4040 VkCommandBuffer commandBuffer,
4041 VkStencilFaceFlags faceMask,
4042 uint32_t writeMask)
4043 {
4044 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4045 struct radv_cmd_state *state = &cmd_buffer->state;
4046 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
4047 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
4048
4049 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4050 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4051 return;
4052 }
4053
4054 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4055 state->dynamic.stencil_write_mask.front = writeMask;
4056 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4057 state->dynamic.stencil_write_mask.back = writeMask;
4058
4059 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
4060 }
4061
4062 void radv_CmdSetStencilReference(
4063 VkCommandBuffer commandBuffer,
4064 VkStencilFaceFlags faceMask,
4065 uint32_t reference)
4066 {
4067 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4068 struct radv_cmd_state *state = &cmd_buffer->state;
4069 bool front_same = state->dynamic.stencil_reference.front == reference;
4070 bool back_same = state->dynamic.stencil_reference.back == reference;
4071
4072 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4073 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4074 return;
4075 }
4076
4077 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4078 cmd_buffer->state.dynamic.stencil_reference.front = reference;
4079 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4080 cmd_buffer->state.dynamic.stencil_reference.back = reference;
4081
4082 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
4083 }
4084
4085 void radv_CmdSetDiscardRectangleEXT(
4086 VkCommandBuffer commandBuffer,
4087 uint32_t firstDiscardRectangle,
4088 uint32_t discardRectangleCount,
4089 const VkRect2D* pDiscardRectangles)
4090 {
4091 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4092 struct radv_cmd_state *state = &cmd_buffer->state;
4093 ASSERTED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
4094
4095 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
4096 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
4097
4098 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
4099 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
4100 return;
4101 }
4102
4103 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
4104 pDiscardRectangles, discardRectangleCount);
4105
4106 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
4107 }
4108
4109 void radv_CmdSetSampleLocationsEXT(
4110 VkCommandBuffer commandBuffer,
4111 const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
4112 {
4113 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4114 struct radv_cmd_state *state = &cmd_buffer->state;
4115
4116 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
4117
4118 state->dynamic.sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
4119 state->dynamic.sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
4120 state->dynamic.sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
4121 typed_memcpy(&state->dynamic.sample_location.locations[0],
4122 pSampleLocationsInfo->pSampleLocations,
4123 pSampleLocationsInfo->sampleLocationsCount);
4124
4125 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS;
4126 }
4127
4128 void radv_CmdSetLineStippleEXT(
4129 VkCommandBuffer commandBuffer,
4130 uint32_t lineStippleFactor,
4131 uint16_t lineStipplePattern)
4132 {
4133 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4134 struct radv_cmd_state *state = &cmd_buffer->state;
4135
4136 state->dynamic.line_stipple.factor = lineStippleFactor;
4137 state->dynamic.line_stipple.pattern = lineStipplePattern;
4138
4139 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE;
4140 }
4141
4142 void radv_CmdExecuteCommands(
4143 VkCommandBuffer commandBuffer,
4144 uint32_t commandBufferCount,
4145 const VkCommandBuffer* pCmdBuffers)
4146 {
4147 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
4148
4149 assert(commandBufferCount > 0);
4150
4151 /* Emit pending flushes on primary prior to executing secondary */
4152 si_emit_cache_flush(primary);
4153
4154 for (uint32_t i = 0; i < commandBufferCount; i++) {
4155 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
4156
4157 primary->scratch_size_per_wave_needed = MAX2(primary->scratch_size_per_wave_needed,
4158 secondary->scratch_size_per_wave_needed);
4159 primary->scratch_waves_wanted = MAX2(primary->scratch_waves_wanted,
4160 secondary->scratch_waves_wanted);
4161 primary->compute_scratch_size_per_wave_needed = MAX2(primary->compute_scratch_size_per_wave_needed,
4162 secondary->compute_scratch_size_per_wave_needed);
4163 primary->compute_scratch_waves_wanted = MAX2(primary->compute_scratch_waves_wanted,
4164 secondary->compute_scratch_waves_wanted);
4165
4166 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
4167 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
4168 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
4169 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
4170 if (secondary->tess_rings_needed)
4171 primary->tess_rings_needed = true;
4172 if (secondary->sample_positions_needed)
4173 primary->sample_positions_needed = true;
4174 if (secondary->gds_needed)
4175 primary->gds_needed = true;
4176
4177 if (!secondary->state.framebuffer &&
4178 (primary->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)) {
4179 /* Emit the framebuffer state from primary if secondary
4180 * has been recorded without a framebuffer, otherwise
4181 * fast color/depth clears can't work.
4182 */
4183 radv_emit_framebuffer_state(primary);
4184 }
4185
4186 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
4187
4188
4189 /* When the secondary command buffer is compute only we don't
4190 * need to re-emit the current graphics pipeline.
4191 */
4192 if (secondary->state.emitted_pipeline) {
4193 primary->state.emitted_pipeline =
4194 secondary->state.emitted_pipeline;
4195 }
4196
4197 /* When the secondary command buffer is graphics only we don't
4198 * need to re-emit the current compute pipeline.
4199 */
4200 if (secondary->state.emitted_compute_pipeline) {
4201 primary->state.emitted_compute_pipeline =
4202 secondary->state.emitted_compute_pipeline;
4203 }
4204
4205 /* Only re-emit the draw packets when needed. */
4206 if (secondary->state.last_primitive_reset_en != -1) {
4207 primary->state.last_primitive_reset_en =
4208 secondary->state.last_primitive_reset_en;
4209 }
4210
4211 if (secondary->state.last_primitive_reset_index) {
4212 primary->state.last_primitive_reset_index =
4213 secondary->state.last_primitive_reset_index;
4214 }
4215
4216 if (secondary->state.last_ia_multi_vgt_param) {
4217 primary->state.last_ia_multi_vgt_param =
4218 secondary->state.last_ia_multi_vgt_param;
4219 }
4220
4221 primary->state.last_first_instance = secondary->state.last_first_instance;
4222 primary->state.last_num_instances = secondary->state.last_num_instances;
4223 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
4224 primary->state.last_sx_ps_downconvert = secondary->state.last_sx_ps_downconvert;
4225 primary->state.last_sx_blend_opt_epsilon = secondary->state.last_sx_blend_opt_epsilon;
4226 primary->state.last_sx_blend_opt_control = secondary->state.last_sx_blend_opt_control;
4227
4228 if (secondary->state.last_index_type != -1) {
4229 primary->state.last_index_type =
4230 secondary->state.last_index_type;
4231 }
4232 }
4233
4234 /* After executing commands from secondary buffers we have to dirty
4235 * some states.
4236 */
4237 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
4238 RADV_CMD_DIRTY_INDEX_BUFFER |
4239 RADV_CMD_DIRTY_DYNAMIC_ALL;
4240 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
4241 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
4242 }
4243
4244 VkResult radv_CreateCommandPool(
4245 VkDevice _device,
4246 const VkCommandPoolCreateInfo* pCreateInfo,
4247 const VkAllocationCallbacks* pAllocator,
4248 VkCommandPool* pCmdPool)
4249 {
4250 RADV_FROM_HANDLE(radv_device, device, _device);
4251 struct radv_cmd_pool *pool;
4252
4253 pool = vk_alloc2(&device->vk.alloc, pAllocator, sizeof(*pool), 8,
4254 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4255 if (pool == NULL)
4256 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4257
4258 vk_object_base_init(&device->vk, &pool->base,
4259 VK_OBJECT_TYPE_COMMAND_POOL);
4260
4261 if (pAllocator)
4262 pool->alloc = *pAllocator;
4263 else
4264 pool->alloc = device->vk.alloc;
4265
4266 list_inithead(&pool->cmd_buffers);
4267 list_inithead(&pool->free_cmd_buffers);
4268
4269 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
4270
4271 *pCmdPool = radv_cmd_pool_to_handle(pool);
4272
4273 return VK_SUCCESS;
4274
4275 }
4276
4277 void radv_DestroyCommandPool(
4278 VkDevice _device,
4279 VkCommandPool commandPool,
4280 const VkAllocationCallbacks* pAllocator)
4281 {
4282 RADV_FROM_HANDLE(radv_device, device, _device);
4283 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4284
4285 if (!pool)
4286 return;
4287
4288 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4289 &pool->cmd_buffers, pool_link) {
4290 radv_cmd_buffer_destroy(cmd_buffer);
4291 }
4292
4293 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4294 &pool->free_cmd_buffers, pool_link) {
4295 radv_cmd_buffer_destroy(cmd_buffer);
4296 }
4297
4298 vk_object_base_finish(&pool->base);
4299 vk_free2(&device->vk.alloc, pAllocator, pool);
4300 }
4301
4302 VkResult radv_ResetCommandPool(
4303 VkDevice device,
4304 VkCommandPool commandPool,
4305 VkCommandPoolResetFlags flags)
4306 {
4307 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4308 VkResult result;
4309
4310 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
4311 &pool->cmd_buffers, pool_link) {
4312 result = radv_reset_cmd_buffer(cmd_buffer);
4313 if (result != VK_SUCCESS)
4314 return result;
4315 }
4316
4317 return VK_SUCCESS;
4318 }
4319
4320 void radv_TrimCommandPool(
4321 VkDevice device,
4322 VkCommandPool commandPool,
4323 VkCommandPoolTrimFlags flags)
4324 {
4325 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4326
4327 if (!pool)
4328 return;
4329
4330 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4331 &pool->free_cmd_buffers, pool_link) {
4332 radv_cmd_buffer_destroy(cmd_buffer);
4333 }
4334 }
4335
4336 static void
4337 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
4338 uint32_t subpass_id)
4339 {
4340 struct radv_cmd_state *state = &cmd_buffer->state;
4341 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
4342
4343 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
4344 cmd_buffer->cs, 4096);
4345
4346 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
4347
4348 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
4349
4350 radv_describe_barrier_start(cmd_buffer, RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC);
4351
4352 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4353 const uint32_t a = subpass->attachments[i].attachment;
4354 if (a == VK_ATTACHMENT_UNUSED)
4355 continue;
4356
4357 radv_handle_subpass_image_transition(cmd_buffer,
4358 subpass->attachments[i],
4359 true);
4360 }
4361
4362 radv_describe_barrier_end(cmd_buffer);
4363
4364 radv_cmd_buffer_clear_subpass(cmd_buffer);
4365
4366 assert(cmd_buffer->cs->cdw <= cdw_max);
4367 }
4368
4369 static void
4370 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
4371 {
4372 struct radv_cmd_state *state = &cmd_buffer->state;
4373 const struct radv_subpass *subpass = state->subpass;
4374 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
4375
4376 radv_cmd_buffer_resolve_subpass(cmd_buffer);
4377
4378 radv_describe_barrier_start(cmd_buffer, RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC);
4379
4380 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4381 const uint32_t a = subpass->attachments[i].attachment;
4382 if (a == VK_ATTACHMENT_UNUSED)
4383 continue;
4384
4385 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
4386 continue;
4387
4388 VkImageLayout layout = state->pass->attachments[a].final_layout;
4389 VkImageLayout stencil_layout = state->pass->attachments[a].stencil_final_layout;
4390 struct radv_subpass_attachment att = { a, layout, stencil_layout };
4391 radv_handle_subpass_image_transition(cmd_buffer, att, false);
4392 }
4393
4394 radv_describe_barrier_end(cmd_buffer);
4395 }
4396
4397 void
4398 radv_cmd_buffer_begin_render_pass(struct radv_cmd_buffer *cmd_buffer,
4399 const VkRenderPassBeginInfo *pRenderPassBegin)
4400 {
4401 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
4402 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
4403 VkResult result;
4404
4405 cmd_buffer->state.framebuffer = framebuffer;
4406 cmd_buffer->state.pass = pass;
4407 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
4408
4409 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
4410 if (result != VK_SUCCESS)
4411 return;
4412
4413 result = radv_cmd_state_setup_sample_locations(cmd_buffer, pass, pRenderPassBegin);
4414 if (result != VK_SUCCESS)
4415 return;
4416 }
4417
4418 void radv_CmdBeginRenderPass(
4419 VkCommandBuffer commandBuffer,
4420 const VkRenderPassBeginInfo* pRenderPassBegin,
4421 VkSubpassContents contents)
4422 {
4423 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4424
4425 radv_cmd_buffer_begin_render_pass(cmd_buffer, pRenderPassBegin);
4426
4427 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
4428 }
4429
4430 void radv_CmdBeginRenderPass2(
4431 VkCommandBuffer commandBuffer,
4432 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
4433 const VkSubpassBeginInfo* pSubpassBeginInfo)
4434 {
4435 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
4436 pSubpassBeginInfo->contents);
4437 }
4438
4439 void radv_CmdNextSubpass(
4440 VkCommandBuffer commandBuffer,
4441 VkSubpassContents contents)
4442 {
4443 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4444
4445 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
4446 radv_cmd_buffer_end_subpass(cmd_buffer);
4447 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
4448 }
4449
4450 void radv_CmdNextSubpass2(
4451 VkCommandBuffer commandBuffer,
4452 const VkSubpassBeginInfo* pSubpassBeginInfo,
4453 const VkSubpassEndInfo* pSubpassEndInfo)
4454 {
4455 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
4456 }
4457
4458 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
4459 {
4460 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
4461 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
4462 if (!radv_get_shader(pipeline, stage))
4463 continue;
4464
4465 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
4466 if (loc->sgpr_idx == -1)
4467 continue;
4468 uint32_t base_reg = pipeline->user_data_0[stage];
4469 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4470
4471 }
4472 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
4473 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
4474 if (loc->sgpr_idx != -1) {
4475 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
4476 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4477 }
4478 }
4479 }
4480
4481 static void
4482 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4483 uint32_t vertex_count,
4484 bool use_opaque)
4485 {
4486 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
4487 radeon_emit(cmd_buffer->cs, vertex_count);
4488 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
4489 S_0287F0_USE_OPAQUE(use_opaque));
4490 }
4491
4492 static void
4493 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
4494 uint64_t index_va,
4495 uint32_t index_count)
4496 {
4497 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
4498 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
4499 radeon_emit(cmd_buffer->cs, index_va);
4500 radeon_emit(cmd_buffer->cs, index_va >> 32);
4501 radeon_emit(cmd_buffer->cs, index_count);
4502 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
4503 }
4504
4505 static void
4506 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4507 bool indexed,
4508 uint32_t draw_count,
4509 uint64_t count_va,
4510 uint32_t stride)
4511 {
4512 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4513 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
4514 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
4515 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id;
4516 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
4517 bool predicating = cmd_buffer->state.predicating;
4518 assert(base_reg);
4519
4520 /* just reset draw state for vertex data */
4521 cmd_buffer->state.last_first_instance = -1;
4522 cmd_buffer->state.last_num_instances = -1;
4523 cmd_buffer->state.last_vertex_offset = -1;
4524
4525 if (draw_count == 1 && !count_va && !draw_id_enable) {
4526 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
4527 PKT3_DRAW_INDIRECT, 3, predicating));
4528 radeon_emit(cs, 0);
4529 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4530 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4531 radeon_emit(cs, di_src_sel);
4532 } else {
4533 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
4534 PKT3_DRAW_INDIRECT_MULTI,
4535 8, predicating));
4536 radeon_emit(cs, 0);
4537 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4538 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4539 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
4540 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
4541 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
4542 radeon_emit(cs, draw_count); /* count */
4543 radeon_emit(cs, count_va); /* count_addr */
4544 radeon_emit(cs, count_va >> 32);
4545 radeon_emit(cs, stride); /* stride */
4546 radeon_emit(cs, di_src_sel);
4547 }
4548 }
4549
4550 static void
4551 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
4552 const struct radv_draw_info *info)
4553 {
4554 struct radv_cmd_state *state = &cmd_buffer->state;
4555 struct radeon_winsys *ws = cmd_buffer->device->ws;
4556 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4557
4558 if (info->indirect) {
4559 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4560 uint64_t count_va = 0;
4561
4562 va += info->indirect->offset + info->indirect_offset;
4563
4564 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4565
4566 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
4567 radeon_emit(cs, 1);
4568 radeon_emit(cs, va);
4569 radeon_emit(cs, va >> 32);
4570
4571 if (info->count_buffer) {
4572 count_va = radv_buffer_get_va(info->count_buffer->bo);
4573 count_va += info->count_buffer->offset +
4574 info->count_buffer_offset;
4575
4576 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
4577 }
4578
4579 if (!state->subpass->view_mask) {
4580 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4581 info->indexed,
4582 info->count,
4583 count_va,
4584 info->stride);
4585 } else {
4586 unsigned i;
4587 for_each_bit(i, state->subpass->view_mask) {
4588 radv_emit_view_index(cmd_buffer, i);
4589
4590 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4591 info->indexed,
4592 info->count,
4593 count_va,
4594 info->stride);
4595 }
4596 }
4597 } else {
4598 assert(state->pipeline->graphics.vtx_base_sgpr);
4599
4600 if (info->vertex_offset != state->last_vertex_offset ||
4601 info->first_instance != state->last_first_instance) {
4602 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
4603 state->pipeline->graphics.vtx_emit_num);
4604
4605 radeon_emit(cs, info->vertex_offset);
4606 radeon_emit(cs, info->first_instance);
4607 if (state->pipeline->graphics.vtx_emit_num == 3)
4608 radeon_emit(cs, 0);
4609 state->last_first_instance = info->first_instance;
4610 state->last_vertex_offset = info->vertex_offset;
4611 }
4612
4613 if (state->last_num_instances != info->instance_count) {
4614 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
4615 radeon_emit(cs, info->instance_count);
4616 state->last_num_instances = info->instance_count;
4617 }
4618
4619 if (info->indexed) {
4620 int index_size = radv_get_vgt_index_size(state->index_type);
4621 uint64_t index_va;
4622
4623 /* Skip draw calls with 0-sized index buffers. They
4624 * cause a hang on some chips, like Navi10-14.
4625 */
4626 if (!cmd_buffer->state.max_index_count)
4627 return;
4628
4629 index_va = state->index_va;
4630 index_va += info->first_index * index_size;
4631
4632 if (!state->subpass->view_mask) {
4633 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4634 index_va,
4635 info->count);
4636 } else {
4637 unsigned i;
4638 for_each_bit(i, state->subpass->view_mask) {
4639 radv_emit_view_index(cmd_buffer, i);
4640
4641 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4642 index_va,
4643 info->count);
4644 }
4645 }
4646 } else {
4647 if (!state->subpass->view_mask) {
4648 radv_cs_emit_draw_packet(cmd_buffer,
4649 info->count,
4650 !!info->strmout_buffer);
4651 } else {
4652 unsigned i;
4653 for_each_bit(i, state->subpass->view_mask) {
4654 radv_emit_view_index(cmd_buffer, i);
4655
4656 radv_cs_emit_draw_packet(cmd_buffer,
4657 info->count,
4658 !!info->strmout_buffer);
4659 }
4660 }
4661 }
4662 }
4663 }
4664
4665 /*
4666 * Vega and raven have a bug which triggers if there are multiple context
4667 * register contexts active at the same time with different scissor values.
4668 *
4669 * There are two possible workarounds:
4670 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
4671 * there is only ever 1 active set of scissor values at the same time.
4672 *
4673 * 2) Whenever the hardware switches contexts we have to set the scissor
4674 * registers again even if it is a noop. That way the new context gets
4675 * the correct scissor values.
4676 *
4677 * This implements option 2. radv_need_late_scissor_emission needs to
4678 * return true on affected HW if radv_emit_all_graphics_states sets
4679 * any context registers.
4680 */
4681 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
4682 const struct radv_draw_info *info)
4683 {
4684 struct radv_cmd_state *state = &cmd_buffer->state;
4685
4686 if (!cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
4687 return false;
4688
4689 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
4690 return true;
4691
4692 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
4693
4694 /* Index, vertex and streamout buffers don't change context regs, and
4695 * pipeline is already handled.
4696 */
4697 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
4698 RADV_CMD_DIRTY_VERTEX_BUFFER |
4699 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
4700 RADV_CMD_DIRTY_PIPELINE);
4701
4702 if (cmd_buffer->state.dirty & used_states)
4703 return true;
4704
4705 uint32_t primitive_reset_index =
4706 radv_get_primitive_reset_index(cmd_buffer);
4707
4708 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
4709 primitive_reset_index != state->last_primitive_reset_index)
4710 return true;
4711
4712 return false;
4713 }
4714
4715 static void
4716 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
4717 const struct radv_draw_info *info)
4718 {
4719 bool late_scissor_emission;
4720
4721 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
4722 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
4723 radv_emit_rbplus_state(cmd_buffer);
4724
4725 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
4726 radv_emit_graphics_pipeline(cmd_buffer);
4727
4728 /* This should be before the cmd_buffer->state.dirty is cleared
4729 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4730 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4731 late_scissor_emission =
4732 radv_need_late_scissor_emission(cmd_buffer, info);
4733
4734 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
4735 radv_emit_framebuffer_state(cmd_buffer);
4736
4737 if (info->indexed) {
4738 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
4739 radv_emit_index_buffer(cmd_buffer, info->indirect);
4740 } else {
4741 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4742 * so the state must be re-emitted before the next indexed
4743 * draw.
4744 */
4745 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
4746 cmd_buffer->state.last_index_type = -1;
4747 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
4748 }
4749 }
4750
4751 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
4752
4753 radv_emit_draw_registers(cmd_buffer, info);
4754
4755 if (late_scissor_emission)
4756 radv_emit_scissor(cmd_buffer);
4757 }
4758
4759 static void
4760 radv_draw(struct radv_cmd_buffer *cmd_buffer,
4761 const struct radv_draw_info *info)
4762 {
4763 struct radeon_info *rad_info =
4764 &cmd_buffer->device->physical_device->rad_info;
4765 bool has_prefetch =
4766 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4767 bool pipeline_is_dirty =
4768 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
4769 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
4770
4771 ASSERTED unsigned cdw_max =
4772 radeon_check_space(cmd_buffer->device->ws,
4773 cmd_buffer->cs, 4096);
4774
4775 if (likely(!info->indirect)) {
4776 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4777 * no workaround for indirect draws, but we can at least skip
4778 * direct draws.
4779 */
4780 if (unlikely(!info->instance_count))
4781 return;
4782
4783 /* Handle count == 0. */
4784 if (unlikely(!info->count && !info->strmout_buffer))
4785 return;
4786 }
4787
4788 radv_describe_draw(cmd_buffer);
4789
4790 /* Use optimal packet order based on whether we need to sync the
4791 * pipeline.
4792 */
4793 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4794 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4795 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4796 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4797 /* If we have to wait for idle, set all states first, so that
4798 * all SET packets are processed in parallel with previous draw
4799 * calls. Then upload descriptors, set shader pointers, and
4800 * draw, and prefetch at the end. This ensures that the time
4801 * the CUs are idle is very short. (there are only SET_SH
4802 * packets between the wait and the draw)
4803 */
4804 radv_emit_all_graphics_states(cmd_buffer, info);
4805 si_emit_cache_flush(cmd_buffer);
4806 /* <-- CUs are idle here --> */
4807
4808 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4809
4810 radv_emit_draw_packets(cmd_buffer, info);
4811 /* <-- CUs are busy here --> */
4812
4813 /* Start prefetches after the draw has been started. Both will
4814 * run in parallel, but starting the draw first is more
4815 * important.
4816 */
4817 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4818 radv_emit_prefetch_L2(cmd_buffer,
4819 cmd_buffer->state.pipeline, false);
4820 }
4821 } else {
4822 /* If we don't wait for idle, start prefetches first, then set
4823 * states, and draw at the end.
4824 */
4825 si_emit_cache_flush(cmd_buffer);
4826
4827 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4828 /* Only prefetch the vertex shader and VBO descriptors
4829 * in order to start the draw as soon as possible.
4830 */
4831 radv_emit_prefetch_L2(cmd_buffer,
4832 cmd_buffer->state.pipeline, true);
4833 }
4834
4835 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4836
4837 radv_emit_all_graphics_states(cmd_buffer, info);
4838 radv_emit_draw_packets(cmd_buffer, info);
4839
4840 /* Prefetch the remaining shaders after the draw has been
4841 * started.
4842 */
4843 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4844 radv_emit_prefetch_L2(cmd_buffer,
4845 cmd_buffer->state.pipeline, false);
4846 }
4847 }
4848
4849 /* Workaround for a VGT hang when streamout is enabled.
4850 * It must be done after drawing.
4851 */
4852 if (cmd_buffer->state.streamout.streamout_enabled &&
4853 (rad_info->family == CHIP_HAWAII ||
4854 rad_info->family == CHIP_TONGA ||
4855 rad_info->family == CHIP_FIJI)) {
4856 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
4857 }
4858
4859 assert(cmd_buffer->cs->cdw <= cdw_max);
4860 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
4861 }
4862
4863 void radv_CmdDraw(
4864 VkCommandBuffer commandBuffer,
4865 uint32_t vertexCount,
4866 uint32_t instanceCount,
4867 uint32_t firstVertex,
4868 uint32_t firstInstance)
4869 {
4870 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4871 struct radv_draw_info info = {};
4872
4873 info.count = vertexCount;
4874 info.instance_count = instanceCount;
4875 info.first_instance = firstInstance;
4876 info.vertex_offset = firstVertex;
4877
4878 radv_draw(cmd_buffer, &info);
4879 }
4880
4881 void radv_CmdDrawIndexed(
4882 VkCommandBuffer commandBuffer,
4883 uint32_t indexCount,
4884 uint32_t instanceCount,
4885 uint32_t firstIndex,
4886 int32_t vertexOffset,
4887 uint32_t firstInstance)
4888 {
4889 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4890 struct radv_draw_info info = {};
4891
4892 info.indexed = true;
4893 info.count = indexCount;
4894 info.instance_count = instanceCount;
4895 info.first_index = firstIndex;
4896 info.vertex_offset = vertexOffset;
4897 info.first_instance = firstInstance;
4898
4899 radv_draw(cmd_buffer, &info);
4900 }
4901
4902 void radv_CmdDrawIndirect(
4903 VkCommandBuffer commandBuffer,
4904 VkBuffer _buffer,
4905 VkDeviceSize offset,
4906 uint32_t drawCount,
4907 uint32_t stride)
4908 {
4909 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4910 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4911 struct radv_draw_info info = {};
4912
4913 info.count = drawCount;
4914 info.indirect = buffer;
4915 info.indirect_offset = offset;
4916 info.stride = stride;
4917
4918 radv_draw(cmd_buffer, &info);
4919 }
4920
4921 void radv_CmdDrawIndexedIndirect(
4922 VkCommandBuffer commandBuffer,
4923 VkBuffer _buffer,
4924 VkDeviceSize offset,
4925 uint32_t drawCount,
4926 uint32_t stride)
4927 {
4928 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4929 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4930 struct radv_draw_info info = {};
4931
4932 info.indexed = true;
4933 info.count = drawCount;
4934 info.indirect = buffer;
4935 info.indirect_offset = offset;
4936 info.stride = stride;
4937
4938 radv_draw(cmd_buffer, &info);
4939 }
4940
4941 void radv_CmdDrawIndirectCount(
4942 VkCommandBuffer commandBuffer,
4943 VkBuffer _buffer,
4944 VkDeviceSize offset,
4945 VkBuffer _countBuffer,
4946 VkDeviceSize countBufferOffset,
4947 uint32_t maxDrawCount,
4948 uint32_t stride)
4949 {
4950 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4951 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4952 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4953 struct radv_draw_info info = {};
4954
4955 info.count = maxDrawCount;
4956 info.indirect = buffer;
4957 info.indirect_offset = offset;
4958 info.count_buffer = count_buffer;
4959 info.count_buffer_offset = countBufferOffset;
4960 info.stride = stride;
4961
4962 radv_draw(cmd_buffer, &info);
4963 }
4964
4965 void radv_CmdDrawIndexedIndirectCount(
4966 VkCommandBuffer commandBuffer,
4967 VkBuffer _buffer,
4968 VkDeviceSize offset,
4969 VkBuffer _countBuffer,
4970 VkDeviceSize countBufferOffset,
4971 uint32_t maxDrawCount,
4972 uint32_t stride)
4973 {
4974 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4975 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4976 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4977 struct radv_draw_info info = {};
4978
4979 info.indexed = true;
4980 info.count = maxDrawCount;
4981 info.indirect = buffer;
4982 info.indirect_offset = offset;
4983 info.count_buffer = count_buffer;
4984 info.count_buffer_offset = countBufferOffset;
4985 info.stride = stride;
4986
4987 radv_draw(cmd_buffer, &info);
4988 }
4989
4990 struct radv_dispatch_info {
4991 /**
4992 * Determine the layout of the grid (in block units) to be used.
4993 */
4994 uint32_t blocks[3];
4995
4996 /**
4997 * A starting offset for the grid. If unaligned is set, the offset
4998 * must still be aligned.
4999 */
5000 uint32_t offsets[3];
5001 /**
5002 * Whether it's an unaligned compute dispatch.
5003 */
5004 bool unaligned;
5005
5006 /**
5007 * Indirect compute parameters resource.
5008 */
5009 struct radv_buffer *indirect;
5010 uint64_t indirect_offset;
5011 };
5012
5013 static void
5014 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
5015 const struct radv_dispatch_info *info)
5016 {
5017 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
5018 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
5019 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
5020 struct radeon_winsys *ws = cmd_buffer->device->ws;
5021 bool predicating = cmd_buffer->state.predicating;
5022 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5023 struct radv_userdata_info *loc;
5024
5025 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
5026 AC_UD_CS_GRID_SIZE);
5027
5028 ASSERTED unsigned cdw_max = radeon_check_space(ws, cs, 25);
5029
5030 if (compute_shader->info.wave_size == 32) {
5031 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
5032 dispatch_initiator |= S_00B800_CS_W32_EN(1);
5033 }
5034
5035 if (info->indirect) {
5036 uint64_t va = radv_buffer_get_va(info->indirect->bo);
5037
5038 va += info->indirect->offset + info->indirect_offset;
5039
5040 radv_cs_add_buffer(ws, cs, info->indirect->bo);
5041
5042 if (loc->sgpr_idx != -1) {
5043 for (unsigned i = 0; i < 3; ++i) {
5044 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5045 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5046 COPY_DATA_DST_SEL(COPY_DATA_REG));
5047 radeon_emit(cs, (va + 4 * i));
5048 radeon_emit(cs, (va + 4 * i) >> 32);
5049 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
5050 + loc->sgpr_idx * 4) >> 2) + i);
5051 radeon_emit(cs, 0);
5052 }
5053 }
5054
5055 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
5056 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
5057 PKT3_SHADER_TYPE_S(1));
5058 radeon_emit(cs, va);
5059 radeon_emit(cs, va >> 32);
5060 radeon_emit(cs, dispatch_initiator);
5061 } else {
5062 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
5063 PKT3_SHADER_TYPE_S(1));
5064 radeon_emit(cs, 1);
5065 radeon_emit(cs, va);
5066 radeon_emit(cs, va >> 32);
5067
5068 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
5069 PKT3_SHADER_TYPE_S(1));
5070 radeon_emit(cs, 0);
5071 radeon_emit(cs, dispatch_initiator);
5072 }
5073 } else {
5074 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
5075 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
5076
5077 if (info->unaligned) {
5078 unsigned *cs_block_size = compute_shader->info.cs.block_size;
5079 unsigned remainder[3];
5080
5081 /* If aligned, these should be an entire block size,
5082 * not 0.
5083 */
5084 remainder[0] = blocks[0] + cs_block_size[0] -
5085 align_u32_npot(blocks[0], cs_block_size[0]);
5086 remainder[1] = blocks[1] + cs_block_size[1] -
5087 align_u32_npot(blocks[1], cs_block_size[1]);
5088 remainder[2] = blocks[2] + cs_block_size[2] -
5089 align_u32_npot(blocks[2], cs_block_size[2]);
5090
5091 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
5092 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
5093 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
5094
5095 for(unsigned i = 0; i < 3; ++i) {
5096 assert(offsets[i] % cs_block_size[i] == 0);
5097 offsets[i] /= cs_block_size[i];
5098 }
5099
5100 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
5101 radeon_emit(cs,
5102 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
5103 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
5104 radeon_emit(cs,
5105 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
5106 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
5107 radeon_emit(cs,
5108 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
5109 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
5110
5111 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
5112 }
5113
5114 if (loc->sgpr_idx != -1) {
5115 assert(loc->num_sgprs == 3);
5116
5117 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
5118 loc->sgpr_idx * 4, 3);
5119 radeon_emit(cs, blocks[0]);
5120 radeon_emit(cs, blocks[1]);
5121 radeon_emit(cs, blocks[2]);
5122 }
5123
5124 if (offsets[0] || offsets[1] || offsets[2]) {
5125 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
5126 radeon_emit(cs, offsets[0]);
5127 radeon_emit(cs, offsets[1]);
5128 radeon_emit(cs, offsets[2]);
5129
5130 /* The blocks in the packet are not counts but end values. */
5131 for (unsigned i = 0; i < 3; ++i)
5132 blocks[i] += offsets[i];
5133 } else {
5134 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
5135 }
5136
5137 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
5138 PKT3_SHADER_TYPE_S(1));
5139 radeon_emit(cs, blocks[0]);
5140 radeon_emit(cs, blocks[1]);
5141 radeon_emit(cs, blocks[2]);
5142 radeon_emit(cs, dispatch_initiator);
5143 }
5144
5145 assert(cmd_buffer->cs->cdw <= cdw_max);
5146 }
5147
5148 static void
5149 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
5150 {
5151 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
5152 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
5153 }
5154
5155 static void
5156 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
5157 const struct radv_dispatch_info *info)
5158 {
5159 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
5160 bool has_prefetch =
5161 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
5162 bool pipeline_is_dirty = pipeline &&
5163 pipeline != cmd_buffer->state.emitted_compute_pipeline;
5164
5165 radv_describe_dispatch(cmd_buffer, 8, 8, 8);
5166
5167 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5168 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5169 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
5170 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
5171 /* If we have to wait for idle, set all states first, so that
5172 * all SET packets are processed in parallel with previous draw
5173 * calls. Then upload descriptors, set shader pointers, and
5174 * dispatch, and prefetch at the end. This ensures that the
5175 * time the CUs are idle is very short. (there are only SET_SH
5176 * packets between the wait and the draw)
5177 */
5178 radv_emit_compute_pipeline(cmd_buffer);
5179 si_emit_cache_flush(cmd_buffer);
5180 /* <-- CUs are idle here --> */
5181
5182 radv_upload_compute_shader_descriptors(cmd_buffer);
5183
5184 radv_emit_dispatch_packets(cmd_buffer, info);
5185 /* <-- CUs are busy here --> */
5186
5187 /* Start prefetches after the dispatch has been started. Both
5188 * will run in parallel, but starting the dispatch first is
5189 * more important.
5190 */
5191 if (has_prefetch && pipeline_is_dirty) {
5192 radv_emit_shader_prefetch(cmd_buffer,
5193 pipeline->shaders[MESA_SHADER_COMPUTE]);
5194 }
5195 } else {
5196 /* If we don't wait for idle, start prefetches first, then set
5197 * states, and dispatch at the end.
5198 */
5199 si_emit_cache_flush(cmd_buffer);
5200
5201 if (has_prefetch && pipeline_is_dirty) {
5202 radv_emit_shader_prefetch(cmd_buffer,
5203 pipeline->shaders[MESA_SHADER_COMPUTE]);
5204 }
5205
5206 radv_upload_compute_shader_descriptors(cmd_buffer);
5207
5208 radv_emit_compute_pipeline(cmd_buffer);
5209 radv_emit_dispatch_packets(cmd_buffer, info);
5210 }
5211
5212 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
5213 }
5214
5215 void radv_CmdDispatchBase(
5216 VkCommandBuffer commandBuffer,
5217 uint32_t base_x,
5218 uint32_t base_y,
5219 uint32_t base_z,
5220 uint32_t x,
5221 uint32_t y,
5222 uint32_t z)
5223 {
5224 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5225 struct radv_dispatch_info info = {};
5226
5227 info.blocks[0] = x;
5228 info.blocks[1] = y;
5229 info.blocks[2] = z;
5230
5231 info.offsets[0] = base_x;
5232 info.offsets[1] = base_y;
5233 info.offsets[2] = base_z;
5234 radv_dispatch(cmd_buffer, &info);
5235 }
5236
5237 void radv_CmdDispatch(
5238 VkCommandBuffer commandBuffer,
5239 uint32_t x,
5240 uint32_t y,
5241 uint32_t z)
5242 {
5243 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
5244 }
5245
5246 void radv_CmdDispatchIndirect(
5247 VkCommandBuffer commandBuffer,
5248 VkBuffer _buffer,
5249 VkDeviceSize offset)
5250 {
5251 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5252 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5253 struct radv_dispatch_info info = {};
5254
5255 info.indirect = buffer;
5256 info.indirect_offset = offset;
5257
5258 radv_dispatch(cmd_buffer, &info);
5259 }
5260
5261 void radv_unaligned_dispatch(
5262 struct radv_cmd_buffer *cmd_buffer,
5263 uint32_t x,
5264 uint32_t y,
5265 uint32_t z)
5266 {
5267 struct radv_dispatch_info info = {};
5268
5269 info.blocks[0] = x;
5270 info.blocks[1] = y;
5271 info.blocks[2] = z;
5272 info.unaligned = 1;
5273
5274 radv_dispatch(cmd_buffer, &info);
5275 }
5276
5277 void
5278 radv_cmd_buffer_end_render_pass(struct radv_cmd_buffer *cmd_buffer)
5279 {
5280 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
5281 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
5282
5283 cmd_buffer->state.pass = NULL;
5284 cmd_buffer->state.subpass = NULL;
5285 cmd_buffer->state.attachments = NULL;
5286 cmd_buffer->state.framebuffer = NULL;
5287 cmd_buffer->state.subpass_sample_locs = NULL;
5288 }
5289
5290 void radv_CmdEndRenderPass(
5291 VkCommandBuffer commandBuffer)
5292 {
5293 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5294
5295 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
5296
5297 radv_cmd_buffer_end_subpass(cmd_buffer);
5298
5299 radv_cmd_buffer_end_render_pass(cmd_buffer);
5300 }
5301
5302 void radv_CmdEndRenderPass2(
5303 VkCommandBuffer commandBuffer,
5304 const VkSubpassEndInfo* pSubpassEndInfo)
5305 {
5306 radv_CmdEndRenderPass(commandBuffer);
5307 }
5308
5309 /*
5310 * For HTILE we have the following interesting clear words:
5311 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
5312 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
5313 * 0xfffffff0: Clear depth to 1.0
5314 * 0x00000000: Clear depth to 0.0
5315 */
5316 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
5317 struct radv_image *image,
5318 const VkImageSubresourceRange *range)
5319 {
5320 assert(range->baseMipLevel == 0);
5321 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
5322 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
5323 struct radv_cmd_state *state = &cmd_buffer->state;
5324 uint32_t htile_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
5325 VkClearDepthStencilValue value = {};
5326 struct radv_barrier_data barrier = {};
5327
5328 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5329 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5330
5331 barrier.layout_transitions.init_mask_ram = 1;
5332 radv_describe_layout_transition(cmd_buffer, &barrier);
5333
5334 state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, htile_value);
5335
5336 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5337
5338 if (vk_format_is_stencil(image->vk_format))
5339 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
5340
5341 radv_set_ds_clear_metadata(cmd_buffer, image, range, value, aspects);
5342
5343 if (radv_image_is_tc_compat_htile(image)) {
5344 /* Initialize the TC-compat metada value to 0 because by
5345 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
5346 * need have to conditionally update its value when performing
5347 * a fast depth clear.
5348 */
5349 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, range, 0);
5350 }
5351 }
5352
5353 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
5354 struct radv_image *image,
5355 VkImageLayout src_layout,
5356 bool src_render_loop,
5357 VkImageLayout dst_layout,
5358 bool dst_render_loop,
5359 unsigned src_queue_mask,
5360 unsigned dst_queue_mask,
5361 const VkImageSubresourceRange *range,
5362 struct radv_sample_locations_state *sample_locs)
5363 {
5364 if (!radv_image_has_htile(image))
5365 return;
5366
5367 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5368 radv_initialize_htile(cmd_buffer, image, range);
5369 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5370 radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5371 radv_initialize_htile(cmd_buffer, image, range);
5372 } else if (radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5373 !radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5374 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5375 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5376
5377 radv_decompress_depth_stencil(cmd_buffer, image, range,
5378 sample_locs);
5379
5380 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5381 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5382 }
5383 }
5384
5385 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
5386 struct radv_image *image,
5387 const VkImageSubresourceRange *range,
5388 uint32_t value)
5389 {
5390 struct radv_cmd_state *state = &cmd_buffer->state;
5391 struct radv_barrier_data barrier = {};
5392
5393 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5394 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5395
5396 barrier.layout_transitions.init_mask_ram = 1;
5397 radv_describe_layout_transition(cmd_buffer, &barrier);
5398
5399 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, range, value);
5400
5401 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5402 }
5403
5404 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
5405 struct radv_image *image,
5406 const VkImageSubresourceRange *range)
5407 {
5408 struct radv_cmd_state *state = &cmd_buffer->state;
5409 static const uint32_t fmask_clear_values[4] = {
5410 0x00000000,
5411 0x02020202,
5412 0xE4E4E4E4,
5413 0x76543210
5414 };
5415 uint32_t log2_samples = util_logbase2(image->info.samples);
5416 uint32_t value = fmask_clear_values[log2_samples];
5417 struct radv_barrier_data barrier = {};
5418
5419 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5420 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5421
5422 barrier.layout_transitions.init_mask_ram = 1;
5423 radv_describe_layout_transition(cmd_buffer, &barrier);
5424
5425 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, range, value);
5426
5427 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5428 }
5429
5430 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
5431 struct radv_image *image,
5432 const VkImageSubresourceRange *range, uint32_t value)
5433 {
5434 struct radv_cmd_state *state = &cmd_buffer->state;
5435 struct radv_barrier_data barrier = {};
5436 unsigned size = 0;
5437
5438 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5439 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5440
5441 barrier.layout_transitions.init_mask_ram = 1;
5442 radv_describe_layout_transition(cmd_buffer, &barrier);
5443
5444 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
5445
5446 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) {
5447 /* When DCC is enabled with mipmaps, some levels might not
5448 * support fast clears and we have to initialize them as "fully
5449 * expanded".
5450 */
5451 /* Compute the size of all fast clearable DCC levels. */
5452 for (unsigned i = 0; i < image->planes[0].surface.num_dcc_levels; i++) {
5453 struct legacy_surf_level *surf_level =
5454 &image->planes[0].surface.u.legacy.level[i];
5455 unsigned dcc_fast_clear_size =
5456 surf_level->dcc_slice_fast_clear_size * image->info.array_size;
5457
5458 if (!dcc_fast_clear_size)
5459 break;
5460
5461 size = surf_level->dcc_offset + dcc_fast_clear_size;
5462 }
5463
5464 /* Initialize the mipmap levels without DCC. */
5465 if (size != image->planes[0].surface.dcc_size) {
5466 state->flush_bits |=
5467 radv_fill_buffer(cmd_buffer, image->bo,
5468 image->offset + image->dcc_offset + size,
5469 image->planes[0].surface.dcc_size - size,
5470 0xffffffff);
5471 }
5472 }
5473
5474 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5475 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5476 }
5477
5478 /**
5479 * Initialize DCC/FMASK/CMASK metadata for a color image.
5480 */
5481 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
5482 struct radv_image *image,
5483 VkImageLayout src_layout,
5484 bool src_render_loop,
5485 VkImageLayout dst_layout,
5486 bool dst_render_loop,
5487 unsigned src_queue_mask,
5488 unsigned dst_queue_mask,
5489 const VkImageSubresourceRange *range)
5490 {
5491 if (radv_image_has_cmask(image)) {
5492 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5493
5494 /* TODO: clarify this. */
5495 if (radv_image_has_fmask(image)) {
5496 value = 0xccccccccu;
5497 }
5498
5499 radv_initialise_cmask(cmd_buffer, image, range, value);
5500 }
5501
5502 if (radv_image_has_fmask(image)) {
5503 radv_initialize_fmask(cmd_buffer, image, range);
5504 }
5505
5506 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5507 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5508 bool need_decompress_pass = false;
5509
5510 if (radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout,
5511 dst_render_loop,
5512 dst_queue_mask)) {
5513 value = 0x20202020u;
5514 need_decompress_pass = true;
5515 }
5516
5517 radv_initialize_dcc(cmd_buffer, image, range, value);
5518
5519 radv_update_fce_metadata(cmd_buffer, image, range,
5520 need_decompress_pass);
5521 }
5522
5523 if (radv_image_has_cmask(image) ||
5524 radv_dcc_enabled(image, range->baseMipLevel)) {
5525 uint32_t color_values[2] = {};
5526 radv_set_color_clear_metadata(cmd_buffer, image, range,
5527 color_values);
5528 }
5529 }
5530
5531 /**
5532 * Handle color image transitions for DCC/FMASK/CMASK.
5533 */
5534 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
5535 struct radv_image *image,
5536 VkImageLayout src_layout,
5537 bool src_render_loop,
5538 VkImageLayout dst_layout,
5539 bool dst_render_loop,
5540 unsigned src_queue_mask,
5541 unsigned dst_queue_mask,
5542 const VkImageSubresourceRange *range)
5543 {
5544 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5545 radv_init_color_image_metadata(cmd_buffer, image,
5546 src_layout, src_render_loop,
5547 dst_layout, dst_render_loop,
5548 src_queue_mask, dst_queue_mask,
5549 range);
5550 return;
5551 }
5552
5553 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5554 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
5555 radv_initialize_dcc(cmd_buffer, image, range, 0xffffffffu);
5556 } else if (radv_layout_dcc_compressed(cmd_buffer->device, image, src_layout, src_render_loop, src_queue_mask) &&
5557 !radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout, dst_render_loop, dst_queue_mask)) {
5558 radv_decompress_dcc(cmd_buffer, image, range);
5559 } else if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
5560 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5561 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5562 }
5563 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
5564 bool fce_eliminate = false, fmask_expand = false;
5565
5566 if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
5567 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5568 fce_eliminate = true;
5569 }
5570
5571 if (radv_image_has_fmask(image)) {
5572 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
5573 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
5574 /* A FMASK decompress is required before doing
5575 * a MSAA decompress using FMASK.
5576 */
5577 fmask_expand = true;
5578 }
5579 }
5580
5581 if (fce_eliminate || fmask_expand)
5582 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5583
5584 if (fmask_expand) {
5585 struct radv_barrier_data barrier = {};
5586 barrier.layout_transitions.fmask_color_expand = 1;
5587 radv_describe_layout_transition(cmd_buffer, &barrier);
5588
5589 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
5590 }
5591 }
5592 }
5593
5594 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
5595 struct radv_image *image,
5596 VkImageLayout src_layout,
5597 bool src_render_loop,
5598 VkImageLayout dst_layout,
5599 bool dst_render_loop,
5600 uint32_t src_family,
5601 uint32_t dst_family,
5602 const VkImageSubresourceRange *range,
5603 struct radv_sample_locations_state *sample_locs)
5604 {
5605 if (image->exclusive && src_family != dst_family) {
5606 /* This is an acquire or a release operation and there will be
5607 * a corresponding release/acquire. Do the transition in the
5608 * most flexible queue. */
5609
5610 assert(src_family == cmd_buffer->queue_family_index ||
5611 dst_family == cmd_buffer->queue_family_index);
5612
5613 if (src_family == VK_QUEUE_FAMILY_EXTERNAL ||
5614 src_family == VK_QUEUE_FAMILY_FOREIGN_EXT)
5615 return;
5616
5617 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
5618 return;
5619
5620 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
5621 (src_family == RADV_QUEUE_GENERAL ||
5622 dst_family == RADV_QUEUE_GENERAL))
5623 return;
5624 }
5625
5626 if (src_layout == dst_layout)
5627 return;
5628
5629 unsigned src_queue_mask =
5630 radv_image_queue_family_mask(image, src_family,
5631 cmd_buffer->queue_family_index);
5632 unsigned dst_queue_mask =
5633 radv_image_queue_family_mask(image, dst_family,
5634 cmd_buffer->queue_family_index);
5635
5636 if (vk_format_is_depth(image->vk_format)) {
5637 radv_handle_depth_image_transition(cmd_buffer, image,
5638 src_layout, src_render_loop,
5639 dst_layout, dst_render_loop,
5640 src_queue_mask, dst_queue_mask,
5641 range, sample_locs);
5642 } else {
5643 radv_handle_color_image_transition(cmd_buffer, image,
5644 src_layout, src_render_loop,
5645 dst_layout, dst_render_loop,
5646 src_queue_mask, dst_queue_mask,
5647 range);
5648 }
5649 }
5650
5651 struct radv_barrier_info {
5652 enum rgp_barrier_reason reason;
5653 uint32_t eventCount;
5654 const VkEvent *pEvents;
5655 VkPipelineStageFlags srcStageMask;
5656 VkPipelineStageFlags dstStageMask;
5657 };
5658
5659 static void
5660 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
5661 uint32_t memoryBarrierCount,
5662 const VkMemoryBarrier *pMemoryBarriers,
5663 uint32_t bufferMemoryBarrierCount,
5664 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
5665 uint32_t imageMemoryBarrierCount,
5666 const VkImageMemoryBarrier *pImageMemoryBarriers,
5667 const struct radv_barrier_info *info)
5668 {
5669 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5670 enum radv_cmd_flush_bits src_flush_bits = 0;
5671 enum radv_cmd_flush_bits dst_flush_bits = 0;
5672
5673 radv_describe_barrier_start(cmd_buffer, info->reason);
5674
5675 for (unsigned i = 0; i < info->eventCount; ++i) {
5676 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
5677 uint64_t va = radv_buffer_get_va(event->bo);
5678
5679 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5680
5681 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
5682
5683 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
5684 assert(cmd_buffer->cs->cdw <= cdw_max);
5685 }
5686
5687 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
5688 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
5689 NULL);
5690 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
5691 NULL);
5692 }
5693
5694 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
5695 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
5696 NULL);
5697 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
5698 NULL);
5699 }
5700
5701 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5702 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5703
5704 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
5705 image);
5706 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
5707 image);
5708 }
5709
5710 /* The Vulkan spec 1.1.98 says:
5711 *
5712 * "An execution dependency with only
5713 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
5714 * will only prevent that stage from executing in subsequently
5715 * submitted commands. As this stage does not perform any actual
5716 * execution, this is not observable - in effect, it does not delay
5717 * processing of subsequent commands. Similarly an execution dependency
5718 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
5719 * will effectively not wait for any prior commands to complete."
5720 */
5721 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
5722 radv_stage_flush(cmd_buffer, info->srcStageMask);
5723 cmd_buffer->state.flush_bits |= src_flush_bits;
5724
5725 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5726 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5727
5728 const struct VkSampleLocationsInfoEXT *sample_locs_info =
5729 vk_find_struct_const(pImageMemoryBarriers[i].pNext,
5730 SAMPLE_LOCATIONS_INFO_EXT);
5731 struct radv_sample_locations_state sample_locations = {};
5732
5733 if (sample_locs_info) {
5734 assert(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
5735 sample_locations.per_pixel = sample_locs_info->sampleLocationsPerPixel;
5736 sample_locations.grid_size = sample_locs_info->sampleLocationGridSize;
5737 sample_locations.count = sample_locs_info->sampleLocationsCount;
5738 typed_memcpy(&sample_locations.locations[0],
5739 sample_locs_info->pSampleLocations,
5740 sample_locs_info->sampleLocationsCount);
5741 }
5742
5743 radv_handle_image_transition(cmd_buffer, image,
5744 pImageMemoryBarriers[i].oldLayout,
5745 false, /* Outside of a renderpass we are never in a renderloop */
5746 pImageMemoryBarriers[i].newLayout,
5747 false, /* Outside of a renderpass we are never in a renderloop */
5748 pImageMemoryBarriers[i].srcQueueFamilyIndex,
5749 pImageMemoryBarriers[i].dstQueueFamilyIndex,
5750 &pImageMemoryBarriers[i].subresourceRange,
5751 sample_locs_info ? &sample_locations : NULL);
5752 }
5753
5754 /* Make sure CP DMA is idle because the driver might have performed a
5755 * DMA operation for copying or filling buffers/images.
5756 */
5757 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5758 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5759 si_cp_dma_wait_for_idle(cmd_buffer);
5760
5761 cmd_buffer->state.flush_bits |= dst_flush_bits;
5762
5763 radv_describe_barrier_end(cmd_buffer);
5764 }
5765
5766 void radv_CmdPipelineBarrier(
5767 VkCommandBuffer commandBuffer,
5768 VkPipelineStageFlags srcStageMask,
5769 VkPipelineStageFlags destStageMask,
5770 VkBool32 byRegion,
5771 uint32_t memoryBarrierCount,
5772 const VkMemoryBarrier* pMemoryBarriers,
5773 uint32_t bufferMemoryBarrierCount,
5774 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5775 uint32_t imageMemoryBarrierCount,
5776 const VkImageMemoryBarrier* pImageMemoryBarriers)
5777 {
5778 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5779 struct radv_barrier_info info;
5780
5781 info.reason = RGP_BARRIER_EXTERNAL_CMD_PIPELINE_BARRIER;
5782 info.eventCount = 0;
5783 info.pEvents = NULL;
5784 info.srcStageMask = srcStageMask;
5785 info.dstStageMask = destStageMask;
5786
5787 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5788 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5789 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5790 }
5791
5792
5793 static void write_event(struct radv_cmd_buffer *cmd_buffer,
5794 struct radv_event *event,
5795 VkPipelineStageFlags stageMask,
5796 unsigned value)
5797 {
5798 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5799 uint64_t va = radv_buffer_get_va(event->bo);
5800
5801 si_emit_cache_flush(cmd_buffer);
5802
5803 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5804
5805 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 21);
5806
5807 /* Flags that only require a top-of-pipe event. */
5808 VkPipelineStageFlags top_of_pipe_flags =
5809 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
5810
5811 /* Flags that only require a post-index-fetch event. */
5812 VkPipelineStageFlags post_index_fetch_flags =
5813 top_of_pipe_flags |
5814 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
5815 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
5816
5817 /* Make sure CP DMA is idle because the driver might have performed a
5818 * DMA operation for copying or filling buffers/images.
5819 */
5820 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5821 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5822 si_cp_dma_wait_for_idle(cmd_buffer);
5823
5824 /* TODO: Emit EOS events for syncing PS/CS stages. */
5825
5826 if (!(stageMask & ~top_of_pipe_flags)) {
5827 /* Just need to sync the PFP engine. */
5828 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5829 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5830 S_370_WR_CONFIRM(1) |
5831 S_370_ENGINE_SEL(V_370_PFP));
5832 radeon_emit(cs, va);
5833 radeon_emit(cs, va >> 32);
5834 radeon_emit(cs, value);
5835 } else if (!(stageMask & ~post_index_fetch_flags)) {
5836 /* Sync ME because PFP reads index and indirect buffers. */
5837 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5838 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5839 S_370_WR_CONFIRM(1) |
5840 S_370_ENGINE_SEL(V_370_ME));
5841 radeon_emit(cs, va);
5842 radeon_emit(cs, va >> 32);
5843 radeon_emit(cs, value);
5844 } else {
5845 /* Otherwise, sync all prior GPU work using an EOP event. */
5846 si_cs_emit_write_event_eop(cs,
5847 cmd_buffer->device->physical_device->rad_info.chip_class,
5848 radv_cmd_buffer_uses_mec(cmd_buffer),
5849 V_028A90_BOTTOM_OF_PIPE_TS, 0,
5850 EOP_DST_SEL_MEM,
5851 EOP_DATA_SEL_VALUE_32BIT, va, value,
5852 cmd_buffer->gfx9_eop_bug_va);
5853 }
5854
5855 assert(cmd_buffer->cs->cdw <= cdw_max);
5856 }
5857
5858 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
5859 VkEvent _event,
5860 VkPipelineStageFlags stageMask)
5861 {
5862 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5863 RADV_FROM_HANDLE(radv_event, event, _event);
5864
5865 write_event(cmd_buffer, event, stageMask, 1);
5866 }
5867
5868 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
5869 VkEvent _event,
5870 VkPipelineStageFlags stageMask)
5871 {
5872 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5873 RADV_FROM_HANDLE(radv_event, event, _event);
5874
5875 write_event(cmd_buffer, event, stageMask, 0);
5876 }
5877
5878 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
5879 uint32_t eventCount,
5880 const VkEvent* pEvents,
5881 VkPipelineStageFlags srcStageMask,
5882 VkPipelineStageFlags dstStageMask,
5883 uint32_t memoryBarrierCount,
5884 const VkMemoryBarrier* pMemoryBarriers,
5885 uint32_t bufferMemoryBarrierCount,
5886 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5887 uint32_t imageMemoryBarrierCount,
5888 const VkImageMemoryBarrier* pImageMemoryBarriers)
5889 {
5890 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5891 struct radv_barrier_info info;
5892
5893 info.reason = RGP_BARRIER_EXTERNAL_CMD_WAIT_EVENTS;
5894 info.eventCount = eventCount;
5895 info.pEvents = pEvents;
5896 info.srcStageMask = 0;
5897
5898 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5899 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5900 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5901 }
5902
5903
5904 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
5905 uint32_t deviceMask)
5906 {
5907 /* No-op */
5908 }
5909
5910 /* VK_EXT_conditional_rendering */
5911 void radv_CmdBeginConditionalRenderingEXT(
5912 VkCommandBuffer commandBuffer,
5913 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
5914 {
5915 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5916 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
5917 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5918 bool draw_visible = true;
5919 uint64_t pred_value = 0;
5920 uint64_t va, new_va;
5921 unsigned pred_offset;
5922
5923 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
5924
5925 /* By default, if the 32-bit value at offset in buffer memory is zero,
5926 * then the rendering commands are discarded, otherwise they are
5927 * executed as normal. If the inverted flag is set, all commands are
5928 * discarded if the value is non zero.
5929 */
5930 if (pConditionalRenderingBegin->flags &
5931 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
5932 draw_visible = false;
5933 }
5934
5935 si_emit_cache_flush(cmd_buffer);
5936
5937 /* From the Vulkan spec 1.1.107:
5938 *
5939 * "If the 32-bit value at offset in buffer memory is zero, then the
5940 * rendering commands are discarded, otherwise they are executed as
5941 * normal. If the value of the predicate in buffer memory changes while
5942 * conditional rendering is active, the rendering commands may be
5943 * discarded in an implementation-dependent way. Some implementations
5944 * may latch the value of the predicate upon beginning conditional
5945 * rendering while others may read it before every rendering command."
5946 *
5947 * But, the AMD hardware treats the predicate as a 64-bit value which
5948 * means we need a workaround in the driver. Luckily, it's not required
5949 * to support if the value changes when predication is active.
5950 *
5951 * The workaround is as follows:
5952 * 1) allocate a 64-value in the upload BO and initialize it to 0
5953 * 2) copy the 32-bit predicate value to the upload BO
5954 * 3) use the new allocated VA address for predication
5955 *
5956 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
5957 * in ME (+ sync PFP) instead of PFP.
5958 */
5959 radv_cmd_buffer_upload_data(cmd_buffer, 8, 16, &pred_value, &pred_offset);
5960
5961 new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
5962
5963 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5964 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5965 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
5966 COPY_DATA_WR_CONFIRM);
5967 radeon_emit(cs, va);
5968 radeon_emit(cs, va >> 32);
5969 radeon_emit(cs, new_va);
5970 radeon_emit(cs, new_va >> 32);
5971
5972 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
5973 radeon_emit(cs, 0);
5974
5975 /* Enable predication for this command buffer. */
5976 si_emit_set_predication_state(cmd_buffer, draw_visible, new_va);
5977 cmd_buffer->state.predicating = true;
5978
5979 /* Store conditional rendering user info. */
5980 cmd_buffer->state.predication_type = draw_visible;
5981 cmd_buffer->state.predication_va = new_va;
5982 }
5983
5984 void radv_CmdEndConditionalRenderingEXT(
5985 VkCommandBuffer commandBuffer)
5986 {
5987 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5988
5989 /* Disable predication for this command buffer. */
5990 si_emit_set_predication_state(cmd_buffer, false, 0);
5991 cmd_buffer->state.predicating = false;
5992
5993 /* Reset conditional rendering user info. */
5994 cmd_buffer->state.predication_type = -1;
5995 cmd_buffer->state.predication_va = 0;
5996 }
5997
5998 /* VK_EXT_transform_feedback */
5999 void radv_CmdBindTransformFeedbackBuffersEXT(
6000 VkCommandBuffer commandBuffer,
6001 uint32_t firstBinding,
6002 uint32_t bindingCount,
6003 const VkBuffer* pBuffers,
6004 const VkDeviceSize* pOffsets,
6005 const VkDeviceSize* pSizes)
6006 {
6007 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6008 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
6009 uint8_t enabled_mask = 0;
6010
6011 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
6012 for (uint32_t i = 0; i < bindingCount; i++) {
6013 uint32_t idx = firstBinding + i;
6014
6015 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
6016 sb[idx].offset = pOffsets[i];
6017
6018 if (!pSizes || pSizes[i] == VK_WHOLE_SIZE) {
6019 sb[idx].size = sb[idx].buffer->size - sb[idx].offset;
6020 } else {
6021 sb[idx].size = pSizes[i];
6022 }
6023
6024 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
6025 sb[idx].buffer->bo);
6026
6027 enabled_mask |= 1 << idx;
6028 }
6029
6030 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
6031
6032 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
6033 }
6034
6035 static void
6036 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
6037 {
6038 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6039 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6040
6041 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
6042 radeon_emit(cs,
6043 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
6044 S_028B94_RAST_STREAM(0) |
6045 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
6046 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
6047 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
6048 radeon_emit(cs, so->hw_enabled_mask &
6049 so->enabled_stream_buffers_mask);
6050
6051 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6052 }
6053
6054 static void
6055 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
6056 {
6057 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6058 bool old_streamout_enabled = so->streamout_enabled;
6059 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
6060
6061 so->streamout_enabled = enable;
6062
6063 so->hw_enabled_mask = so->enabled_mask |
6064 (so->enabled_mask << 4) |
6065 (so->enabled_mask << 8) |
6066 (so->enabled_mask << 12);
6067
6068 if (!cmd_buffer->device->physical_device->use_ngg_streamout &&
6069 ((old_streamout_enabled != so->streamout_enabled) ||
6070 (old_hw_enabled_mask != so->hw_enabled_mask)))
6071 radv_emit_streamout_enable(cmd_buffer);
6072
6073 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6074 cmd_buffer->gds_needed = true;
6075 cmd_buffer->gds_oa_needed = true;
6076 }
6077 }
6078
6079 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
6080 {
6081 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6082 unsigned reg_strmout_cntl;
6083
6084 /* The register is at different places on different ASICs. */
6085 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
6086 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
6087 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
6088 } else {
6089 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
6090 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
6091 }
6092
6093 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
6094 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
6095
6096 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
6097 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
6098 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
6099 radeon_emit(cs, 0);
6100 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
6101 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
6102 radeon_emit(cs, 4); /* poll interval */
6103 }
6104
6105 static void
6106 radv_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
6107 uint32_t firstCounterBuffer,
6108 uint32_t counterBufferCount,
6109 const VkBuffer *pCounterBuffers,
6110 const VkDeviceSize *pCounterBufferOffsets)
6111
6112 {
6113 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
6114 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6115 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6116 uint32_t i;
6117
6118 radv_flush_vgt_streamout(cmd_buffer);
6119
6120 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6121 for_each_bit(i, so->enabled_mask) {
6122 int32_t counter_buffer_idx = i - firstCounterBuffer;
6123 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6124 counter_buffer_idx = -1;
6125
6126 /* AMD GCN binds streamout buffers as shader resources.
6127 * VGT only counts primitives and tells the shader through
6128 * SGPRs what to do.
6129 */
6130 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
6131 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
6132 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
6133
6134 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6135
6136 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6137 /* The array of counter buffers is optional. */
6138 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6139 uint64_t va = radv_buffer_get_va(buffer->bo);
6140
6141 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6142
6143 /* Append */
6144 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6145 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6146 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6147 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
6148 radeon_emit(cs, 0); /* unused */
6149 radeon_emit(cs, 0); /* unused */
6150 radeon_emit(cs, va); /* src address lo */
6151 radeon_emit(cs, va >> 32); /* src address hi */
6152
6153 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6154 } else {
6155 /* Start from the beginning. */
6156 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6157 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6158 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6159 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
6160 radeon_emit(cs, 0); /* unused */
6161 radeon_emit(cs, 0); /* unused */
6162 radeon_emit(cs, 0); /* unused */
6163 radeon_emit(cs, 0); /* unused */
6164 }
6165 }
6166
6167 radv_set_streamout_enable(cmd_buffer, true);
6168 }
6169
6170 static void
6171 gfx10_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
6172 uint32_t firstCounterBuffer,
6173 uint32_t counterBufferCount,
6174 const VkBuffer *pCounterBuffers,
6175 const VkDeviceSize *pCounterBufferOffsets)
6176 {
6177 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6178 unsigned last_target = util_last_bit(so->enabled_mask) - 1;
6179 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6180 uint32_t i;
6181
6182 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6183 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6184
6185 /* Sync because the next streamout operation will overwrite GDS and we
6186 * have to make sure it's idle.
6187 * TODO: Improve by tracking if there is a streamout operation in
6188 * flight.
6189 */
6190 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
6191 si_emit_cache_flush(cmd_buffer);
6192
6193 for_each_bit(i, so->enabled_mask) {
6194 int32_t counter_buffer_idx = i - firstCounterBuffer;
6195 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6196 counter_buffer_idx = -1;
6197
6198 bool append = counter_buffer_idx >= 0 &&
6199 pCounterBuffers && pCounterBuffers[counter_buffer_idx];
6200 uint64_t va = 0;
6201
6202 if (append) {
6203 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6204
6205 va += radv_buffer_get_va(buffer->bo);
6206 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6207
6208 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6209 }
6210
6211 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
6212 radeon_emit(cs, S_411_SRC_SEL(append ? V_411_SRC_ADDR_TC_L2 : V_411_DATA) |
6213 S_411_DST_SEL(V_411_GDS) |
6214 S_411_CP_SYNC(i == last_target));
6215 radeon_emit(cs, va);
6216 radeon_emit(cs, va >> 32);
6217 radeon_emit(cs, 4 * i); /* destination in GDS */
6218 radeon_emit(cs, 0);
6219 radeon_emit(cs, S_414_BYTE_COUNT_GFX9(4) |
6220 S_414_DISABLE_WR_CONFIRM_GFX9(i != last_target));
6221 }
6222
6223 radv_set_streamout_enable(cmd_buffer, true);
6224 }
6225
6226 void radv_CmdBeginTransformFeedbackEXT(
6227 VkCommandBuffer commandBuffer,
6228 uint32_t firstCounterBuffer,
6229 uint32_t counterBufferCount,
6230 const VkBuffer* pCounterBuffers,
6231 const VkDeviceSize* pCounterBufferOffsets)
6232 {
6233 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6234
6235 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6236 gfx10_emit_streamout_begin(cmd_buffer,
6237 firstCounterBuffer, counterBufferCount,
6238 pCounterBuffers, pCounterBufferOffsets);
6239 } else {
6240 radv_emit_streamout_begin(cmd_buffer,
6241 firstCounterBuffer, counterBufferCount,
6242 pCounterBuffers, pCounterBufferOffsets);
6243 }
6244 }
6245
6246 static void
6247 radv_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6248 uint32_t firstCounterBuffer,
6249 uint32_t counterBufferCount,
6250 const VkBuffer *pCounterBuffers,
6251 const VkDeviceSize *pCounterBufferOffsets)
6252 {
6253 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6254 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6255 uint32_t i;
6256
6257 radv_flush_vgt_streamout(cmd_buffer);
6258
6259 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6260 for_each_bit(i, so->enabled_mask) {
6261 int32_t counter_buffer_idx = i - firstCounterBuffer;
6262 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6263 counter_buffer_idx = -1;
6264
6265 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6266 /* The array of counters buffer is optional. */
6267 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6268 uint64_t va = radv_buffer_get_va(buffer->bo);
6269
6270 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6271
6272 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6273 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6274 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6275 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
6276 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
6277 radeon_emit(cs, va); /* dst address lo */
6278 radeon_emit(cs, va >> 32); /* dst address hi */
6279 radeon_emit(cs, 0); /* unused */
6280 radeon_emit(cs, 0); /* unused */
6281
6282 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6283 }
6284
6285 /* Deactivate transform feedback by zeroing the buffer size.
6286 * The counters (primitives generated, primitives emitted) may
6287 * be enabled even if there is not buffer bound. This ensures
6288 * that the primitives-emitted query won't increment.
6289 */
6290 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
6291
6292 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6293 }
6294
6295 radv_set_streamout_enable(cmd_buffer, false);
6296 }
6297
6298 static void
6299 gfx10_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6300 uint32_t firstCounterBuffer,
6301 uint32_t counterBufferCount,
6302 const VkBuffer *pCounterBuffers,
6303 const VkDeviceSize *pCounterBufferOffsets)
6304 {
6305 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6306 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6307 uint32_t i;
6308
6309 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6310 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6311
6312 for_each_bit(i, so->enabled_mask) {
6313 int32_t counter_buffer_idx = i - firstCounterBuffer;
6314 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6315 counter_buffer_idx = -1;
6316
6317 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6318 /* The array of counters buffer is optional. */
6319 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6320 uint64_t va = radv_buffer_get_va(buffer->bo);
6321
6322 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6323
6324 si_cs_emit_write_event_eop(cs,
6325 cmd_buffer->device->physical_device->rad_info.chip_class,
6326 radv_cmd_buffer_uses_mec(cmd_buffer),
6327 V_028A90_PS_DONE, 0,
6328 EOP_DST_SEL_TC_L2,
6329 EOP_DATA_SEL_GDS,
6330 va, EOP_DATA_GDS(i, 1), 0);
6331
6332 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6333 }
6334 }
6335
6336 radv_set_streamout_enable(cmd_buffer, false);
6337 }
6338
6339 void radv_CmdEndTransformFeedbackEXT(
6340 VkCommandBuffer commandBuffer,
6341 uint32_t firstCounterBuffer,
6342 uint32_t counterBufferCount,
6343 const VkBuffer* pCounterBuffers,
6344 const VkDeviceSize* pCounterBufferOffsets)
6345 {
6346 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6347
6348 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6349 gfx10_emit_streamout_end(cmd_buffer,
6350 firstCounterBuffer, counterBufferCount,
6351 pCounterBuffers, pCounterBufferOffsets);
6352 } else {
6353 radv_emit_streamout_end(cmd_buffer,
6354 firstCounterBuffer, counterBufferCount,
6355 pCounterBuffers, pCounterBufferOffsets);
6356 }
6357 }
6358
6359 void radv_CmdDrawIndirectByteCountEXT(
6360 VkCommandBuffer commandBuffer,
6361 uint32_t instanceCount,
6362 uint32_t firstInstance,
6363 VkBuffer _counterBuffer,
6364 VkDeviceSize counterBufferOffset,
6365 uint32_t counterOffset,
6366 uint32_t vertexStride)
6367 {
6368 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6369 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
6370 struct radv_draw_info info = {};
6371
6372 info.instance_count = instanceCount;
6373 info.first_instance = firstInstance;
6374 info.strmout_buffer = counterBuffer;
6375 info.strmout_buffer_offset = counterBufferOffset;
6376 info.stride = vertexStride;
6377
6378 radv_draw(cmd_buffer, &info);
6379 }
6380
6381 /* VK_AMD_buffer_marker */
6382 void radv_CmdWriteBufferMarkerAMD(
6383 VkCommandBuffer commandBuffer,
6384 VkPipelineStageFlagBits pipelineStage,
6385 VkBuffer dstBuffer,
6386 VkDeviceSize dstOffset,
6387 uint32_t marker)
6388 {
6389 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6390 RADV_FROM_HANDLE(radv_buffer, buffer, dstBuffer);
6391 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6392 uint64_t va = radv_buffer_get_va(buffer->bo) + dstOffset;
6393
6394 si_emit_cache_flush(cmd_buffer);
6395
6396 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 12);
6397
6398 if (!(pipelineStage & ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT)) {
6399 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
6400 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
6401 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
6402 COPY_DATA_WR_CONFIRM);
6403 radeon_emit(cs, marker);
6404 radeon_emit(cs, 0);
6405 radeon_emit(cs, va);
6406 radeon_emit(cs, va >> 32);
6407 } else {
6408 si_cs_emit_write_event_eop(cs,
6409 cmd_buffer->device->physical_device->rad_info.chip_class,
6410 radv_cmd_buffer_uses_mec(cmd_buffer),
6411 V_028A90_BOTTOM_OF_PIPE_TS, 0,
6412 EOP_DST_SEL_MEM,
6413 EOP_DATA_SEL_VALUE_32BIT,
6414 va, marker,
6415 cmd_buffer->gfx9_eop_bug_va);
6416 }
6417
6418 assert(cmd_buffer->cs->cdw <= cdw_max);
6419 }