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radv: Do not setup attachments without a framebuffer.
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 bool src_render_loop,
58 VkImageLayout dst_layout,
59 bool dst_render_loop,
60 uint32_t src_family,
61 uint32_t dst_family,
62 const VkImageSubresourceRange *range,
63 struct radv_sample_locations_state *sample_locs);
64
65 const struct radv_dynamic_state default_dynamic_state = {
66 .viewport = {
67 .count = 0,
68 },
69 .scissor = {
70 .count = 0,
71 },
72 .line_width = 1.0f,
73 .depth_bias = {
74 .bias = 0.0f,
75 .clamp = 0.0f,
76 .slope = 0.0f,
77 },
78 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
79 .depth_bounds = {
80 .min = 0.0f,
81 .max = 1.0f,
82 },
83 .stencil_compare_mask = {
84 .front = ~0u,
85 .back = ~0u,
86 },
87 .stencil_write_mask = {
88 .front = ~0u,
89 .back = ~0u,
90 },
91 .stencil_reference = {
92 .front = 0u,
93 .back = 0u,
94 },
95 };
96
97 static void
98 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
99 const struct radv_dynamic_state *src)
100 {
101 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
102 uint32_t copy_mask = src->mask;
103 uint32_t dest_mask = 0;
104
105 /* Make sure to copy the number of viewports/scissors because they can
106 * only be specified at pipeline creation time.
107 */
108 dest->viewport.count = src->viewport.count;
109 dest->scissor.count = src->scissor.count;
110 dest->discard_rectangle.count = src->discard_rectangle.count;
111 dest->sample_location.count = src->sample_location.count;
112
113 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
114 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
115 src->viewport.count * sizeof(VkViewport))) {
116 typed_memcpy(dest->viewport.viewports,
117 src->viewport.viewports,
118 src->viewport.count);
119 dest_mask |= RADV_DYNAMIC_VIEWPORT;
120 }
121 }
122
123 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
124 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
125 src->scissor.count * sizeof(VkRect2D))) {
126 typed_memcpy(dest->scissor.scissors,
127 src->scissor.scissors, src->scissor.count);
128 dest_mask |= RADV_DYNAMIC_SCISSOR;
129 }
130 }
131
132 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
133 if (dest->line_width != src->line_width) {
134 dest->line_width = src->line_width;
135 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
136 }
137 }
138
139 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
140 if (memcmp(&dest->depth_bias, &src->depth_bias,
141 sizeof(src->depth_bias))) {
142 dest->depth_bias = src->depth_bias;
143 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
144 }
145 }
146
147 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
148 if (memcmp(&dest->blend_constants, &src->blend_constants,
149 sizeof(src->blend_constants))) {
150 typed_memcpy(dest->blend_constants,
151 src->blend_constants, 4);
152 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
153 }
154 }
155
156 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
157 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
158 sizeof(src->depth_bounds))) {
159 dest->depth_bounds = src->depth_bounds;
160 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
161 }
162 }
163
164 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
165 if (memcmp(&dest->stencil_compare_mask,
166 &src->stencil_compare_mask,
167 sizeof(src->stencil_compare_mask))) {
168 dest->stencil_compare_mask = src->stencil_compare_mask;
169 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
170 }
171 }
172
173 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
174 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
175 sizeof(src->stencil_write_mask))) {
176 dest->stencil_write_mask = src->stencil_write_mask;
177 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
178 }
179 }
180
181 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
182 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
183 sizeof(src->stencil_reference))) {
184 dest->stencil_reference = src->stencil_reference;
185 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
186 }
187 }
188
189 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
190 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
191 src->discard_rectangle.count * sizeof(VkRect2D))) {
192 typed_memcpy(dest->discard_rectangle.rectangles,
193 src->discard_rectangle.rectangles,
194 src->discard_rectangle.count);
195 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
196 }
197 }
198
199 if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
200 if (dest->sample_location.per_pixel != src->sample_location.per_pixel ||
201 dest->sample_location.grid_size.width != src->sample_location.grid_size.width ||
202 dest->sample_location.grid_size.height != src->sample_location.grid_size.height ||
203 memcmp(&dest->sample_location.locations,
204 &src->sample_location.locations,
205 src->sample_location.count * sizeof(VkSampleLocationEXT))) {
206 dest->sample_location.per_pixel = src->sample_location.per_pixel;
207 dest->sample_location.grid_size = src->sample_location.grid_size;
208 typed_memcpy(dest->sample_location.locations,
209 src->sample_location.locations,
210 src->sample_location.count);
211 dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
212 }
213 }
214
215 cmd_buffer->state.dirty |= dest_mask;
216 }
217
218 static void
219 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
220 struct radv_pipeline *pipeline)
221 {
222 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
223 struct radv_shader_info *info;
224
225 if (!pipeline->streamout_shader)
226 return;
227
228 info = &pipeline->streamout_shader->info.info;
229 for (int i = 0; i < MAX_SO_BUFFERS; i++)
230 so->stride_in_dw[i] = info->so.strides[i];
231
232 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
233 }
234
235 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
236 {
237 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
238 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
239 }
240
241 enum ring_type radv_queue_family_to_ring(int f) {
242 switch (f) {
243 case RADV_QUEUE_GENERAL:
244 return RING_GFX;
245 case RADV_QUEUE_COMPUTE:
246 return RING_COMPUTE;
247 case RADV_QUEUE_TRANSFER:
248 return RING_DMA;
249 default:
250 unreachable("Unknown queue family");
251 }
252 }
253
254 static VkResult radv_create_cmd_buffer(
255 struct radv_device * device,
256 struct radv_cmd_pool * pool,
257 VkCommandBufferLevel level,
258 VkCommandBuffer* pCommandBuffer)
259 {
260 struct radv_cmd_buffer *cmd_buffer;
261 unsigned ring;
262 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
263 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
264 if (cmd_buffer == NULL)
265 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
266
267 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
268 cmd_buffer->device = device;
269 cmd_buffer->pool = pool;
270 cmd_buffer->level = level;
271
272 if (pool) {
273 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
274 cmd_buffer->queue_family_index = pool->queue_family_index;
275
276 } else {
277 /* Init the pool_link so we can safely call list_del when we destroy
278 * the command buffer
279 */
280 list_inithead(&cmd_buffer->pool_link);
281 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
282 }
283
284 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
285
286 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
287 if (!cmd_buffer->cs) {
288 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
289 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
290 }
291
292 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
293
294 list_inithead(&cmd_buffer->upload.list);
295
296 return VK_SUCCESS;
297 }
298
299 static void
300 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
301 {
302 list_del(&cmd_buffer->pool_link);
303
304 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
305 &cmd_buffer->upload.list, list) {
306 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
307 list_del(&up->list);
308 free(up);
309 }
310
311 if (cmd_buffer->upload.upload_bo)
312 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
313 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
314
315 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
316 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
317
318 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
319 }
320
321 static VkResult
322 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
323 {
324 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
325
326 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
327 &cmd_buffer->upload.list, list) {
328 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
329 list_del(&up->list);
330 free(up);
331 }
332
333 cmd_buffer->push_constant_stages = 0;
334 cmd_buffer->scratch_size_needed = 0;
335 cmd_buffer->compute_scratch_size_needed = 0;
336 cmd_buffer->esgs_ring_size_needed = 0;
337 cmd_buffer->gsvs_ring_size_needed = 0;
338 cmd_buffer->tess_rings_needed = false;
339 cmd_buffer->sample_positions_needed = false;
340
341 if (cmd_buffer->upload.upload_bo)
342 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
343 cmd_buffer->upload.upload_bo);
344 cmd_buffer->upload.offset = 0;
345
346 cmd_buffer->record_result = VK_SUCCESS;
347
348 memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
349
350 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
351 cmd_buffer->descriptors[i].dirty = 0;
352 cmd_buffer->descriptors[i].valid = 0;
353 cmd_buffer->descriptors[i].push_dirty = false;
354 }
355
356 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
357 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
358 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
359 unsigned fence_offset, eop_bug_offset;
360 void *fence_ptr;
361
362 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
363 &fence_ptr);
364
365 cmd_buffer->gfx9_fence_va =
366 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
367 cmd_buffer->gfx9_fence_va += fence_offset;
368
369 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
370 /* Allocate a buffer for the EOP bug on GFX9. */
371 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
372 &eop_bug_offset, &fence_ptr);
373 cmd_buffer->gfx9_eop_bug_va =
374 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
375 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
376 }
377 }
378
379 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
380
381 return cmd_buffer->record_result;
382 }
383
384 static bool
385 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
386 uint64_t min_needed)
387 {
388 uint64_t new_size;
389 struct radeon_winsys_bo *bo;
390 struct radv_cmd_buffer_upload *upload;
391 struct radv_device *device = cmd_buffer->device;
392
393 new_size = MAX2(min_needed, 16 * 1024);
394 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
395
396 bo = device->ws->buffer_create(device->ws,
397 new_size, 4096,
398 RADEON_DOMAIN_GTT,
399 RADEON_FLAG_CPU_ACCESS|
400 RADEON_FLAG_NO_INTERPROCESS_SHARING |
401 RADEON_FLAG_32BIT,
402 RADV_BO_PRIORITY_UPLOAD_BUFFER);
403
404 if (!bo) {
405 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
406 return false;
407 }
408
409 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
410 if (cmd_buffer->upload.upload_bo) {
411 upload = malloc(sizeof(*upload));
412
413 if (!upload) {
414 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
415 device->ws->buffer_destroy(bo);
416 return false;
417 }
418
419 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
420 list_add(&upload->list, &cmd_buffer->upload.list);
421 }
422
423 cmd_buffer->upload.upload_bo = bo;
424 cmd_buffer->upload.size = new_size;
425 cmd_buffer->upload.offset = 0;
426 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
427
428 if (!cmd_buffer->upload.map) {
429 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
430 return false;
431 }
432
433 return true;
434 }
435
436 bool
437 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
438 unsigned size,
439 unsigned alignment,
440 unsigned *out_offset,
441 void **ptr)
442 {
443 assert(util_is_power_of_two_nonzero(alignment));
444
445 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
446 if (offset + size > cmd_buffer->upload.size) {
447 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
448 return false;
449 offset = 0;
450 }
451
452 *out_offset = offset;
453 *ptr = cmd_buffer->upload.map + offset;
454
455 cmd_buffer->upload.offset = offset + size;
456 return true;
457 }
458
459 bool
460 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
461 unsigned size, unsigned alignment,
462 const void *data, unsigned *out_offset)
463 {
464 uint8_t *ptr;
465
466 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
467 out_offset, (void **)&ptr))
468 return false;
469
470 if (ptr)
471 memcpy(ptr, data, size);
472
473 return true;
474 }
475
476 static void
477 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
478 unsigned count, const uint32_t *data)
479 {
480 struct radeon_cmdbuf *cs = cmd_buffer->cs;
481
482 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
483
484 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
485 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
486 S_370_WR_CONFIRM(1) |
487 S_370_ENGINE_SEL(V_370_ME));
488 radeon_emit(cs, va);
489 radeon_emit(cs, va >> 32);
490 radeon_emit_array(cs, data, count);
491 }
492
493 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
494 {
495 struct radv_device *device = cmd_buffer->device;
496 struct radeon_cmdbuf *cs = cmd_buffer->cs;
497 uint64_t va;
498
499 va = radv_buffer_get_va(device->trace_bo);
500 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
501 va += 4;
502
503 ++cmd_buffer->state.trace_id;
504 radv_emit_write_data_packet(cmd_buffer, va, 1,
505 &cmd_buffer->state.trace_id);
506
507 radeon_check_space(cmd_buffer->device->ws, cs, 2);
508
509 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
510 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
511 }
512
513 static void
514 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
515 enum radv_cmd_flush_bits flags)
516 {
517 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
518 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
519 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
520
521 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
522
523 /* Force wait for graphics or compute engines to be idle. */
524 si_cs_emit_cache_flush(cmd_buffer->cs,
525 cmd_buffer->device->physical_device->rad_info.chip_class,
526 &cmd_buffer->gfx9_fence_idx,
527 cmd_buffer->gfx9_fence_va,
528 radv_cmd_buffer_uses_mec(cmd_buffer),
529 flags, cmd_buffer->gfx9_eop_bug_va);
530 }
531
532 if (unlikely(cmd_buffer->device->trace_bo))
533 radv_cmd_buffer_trace_emit(cmd_buffer);
534 }
535
536 static void
537 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
538 struct radv_pipeline *pipeline, enum ring_type ring)
539 {
540 struct radv_device *device = cmd_buffer->device;
541 uint32_t data[2];
542 uint64_t va;
543
544 va = radv_buffer_get_va(device->trace_bo);
545
546 switch (ring) {
547 case RING_GFX:
548 va += 8;
549 break;
550 case RING_COMPUTE:
551 va += 16;
552 break;
553 default:
554 assert(!"invalid ring type");
555 }
556
557 data[0] = (uintptr_t)pipeline;
558 data[1] = (uintptr_t)pipeline >> 32;
559
560 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
561 }
562
563 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
564 VkPipelineBindPoint bind_point,
565 struct radv_descriptor_set *set,
566 unsigned idx)
567 {
568 struct radv_descriptor_state *descriptors_state =
569 radv_get_descriptors_state(cmd_buffer, bind_point);
570
571 descriptors_state->sets[idx] = set;
572
573 descriptors_state->valid |= (1u << idx); /* active descriptors */
574 descriptors_state->dirty |= (1u << idx);
575 }
576
577 static void
578 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
579 VkPipelineBindPoint bind_point)
580 {
581 struct radv_descriptor_state *descriptors_state =
582 radv_get_descriptors_state(cmd_buffer, bind_point);
583 struct radv_device *device = cmd_buffer->device;
584 uint32_t data[MAX_SETS * 2] = {};
585 uint64_t va;
586 unsigned i;
587 va = radv_buffer_get_va(device->trace_bo) + 24;
588
589 for_each_bit(i, descriptors_state->valid) {
590 struct radv_descriptor_set *set = descriptors_state->sets[i];
591 data[i * 2] = (uint64_t)(uintptr_t)set;
592 data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
593 }
594
595 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
596 }
597
598 struct radv_userdata_info *
599 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
600 gl_shader_stage stage,
601 int idx)
602 {
603 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
604 return &shader->info.user_sgprs_locs.shader_data[idx];
605 }
606
607 static void
608 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
609 struct radv_pipeline *pipeline,
610 gl_shader_stage stage,
611 int idx, uint64_t va)
612 {
613 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
614 uint32_t base_reg = pipeline->user_data_0[stage];
615 if (loc->sgpr_idx == -1)
616 return;
617
618 assert(loc->num_sgprs == 1);
619
620 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
621 base_reg + loc->sgpr_idx * 4, va, false);
622 }
623
624 static void
625 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
626 struct radv_pipeline *pipeline,
627 struct radv_descriptor_state *descriptors_state,
628 gl_shader_stage stage)
629 {
630 struct radv_device *device = cmd_buffer->device;
631 struct radeon_cmdbuf *cs = cmd_buffer->cs;
632 uint32_t sh_base = pipeline->user_data_0[stage];
633 struct radv_userdata_locations *locs =
634 &pipeline->shaders[stage]->info.user_sgprs_locs;
635 unsigned mask = locs->descriptor_sets_enabled;
636
637 mask &= descriptors_state->dirty & descriptors_state->valid;
638
639 while (mask) {
640 int start, count;
641
642 u_bit_scan_consecutive_range(&mask, &start, &count);
643
644 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
645 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
646
647 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
648 for (int i = 0; i < count; i++) {
649 struct radv_descriptor_set *set =
650 descriptors_state->sets[start + i];
651
652 radv_emit_shader_pointer_body(device, cs, set->va, true);
653 }
654 }
655 }
656
657 /**
658 * Convert the user sample locations to hardware sample locations (the values
659 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
660 */
661 static void
662 radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
663 uint32_t x, uint32_t y, VkOffset2D *sample_locs)
664 {
665 uint32_t x_offset = x % state->grid_size.width;
666 uint32_t y_offset = y % state->grid_size.height;
667 uint32_t num_samples = (uint32_t)state->per_pixel;
668 VkSampleLocationEXT *user_locs;
669 uint32_t pixel_offset;
670
671 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
672
673 assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
674 user_locs = &state->locations[pixel_offset];
675
676 for (uint32_t i = 0; i < num_samples; i++) {
677 float shifted_pos_x = user_locs[i].x - 0.5;
678 float shifted_pos_y = user_locs[i].y - 0.5;
679
680 int32_t scaled_pos_x = floor(shifted_pos_x * 16);
681 int32_t scaled_pos_y = floor(shifted_pos_y * 16);
682
683 sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
684 sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
685 }
686 }
687
688 /**
689 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
690 * locations.
691 */
692 static void
693 radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
694 uint32_t *sample_locs_pixel)
695 {
696 for (uint32_t i = 0; i < num_samples; i++) {
697 uint32_t sample_reg_idx = i / 4;
698 uint32_t sample_loc_idx = i % 4;
699 int32_t pos_x = sample_locs[i].x;
700 int32_t pos_y = sample_locs[i].y;
701
702 uint32_t shift_x = 8 * sample_loc_idx;
703 uint32_t shift_y = shift_x + 4;
704
705 sample_locs_pixel[sample_reg_idx] |= (pos_x & 0xf) << shift_x;
706 sample_locs_pixel[sample_reg_idx] |= (pos_y & 0xf) << shift_y;
707 }
708 }
709
710 /**
711 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
712 * sample locations.
713 */
714 static uint64_t
715 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer,
716 VkOffset2D *sample_locs,
717 uint32_t num_samples)
718 {
719 uint32_t centroid_priorities[num_samples];
720 uint32_t sample_mask = num_samples - 1;
721 uint32_t distances[num_samples];
722 uint64_t centroid_priority = 0;
723
724 /* Compute the distances from center for each sample. */
725 for (int i = 0; i < num_samples; i++) {
726 distances[i] = (sample_locs[i].x * sample_locs[i].x) +
727 (sample_locs[i].y * sample_locs[i].y);
728 }
729
730 /* Compute the centroid priorities by looking at the distances array. */
731 for (int i = 0; i < num_samples; i++) {
732 uint32_t min_idx = 0;
733
734 for (int j = 1; j < num_samples; j++) {
735 if (distances[j] < distances[min_idx])
736 min_idx = j;
737 }
738
739 centroid_priorities[i] = min_idx;
740 distances[min_idx] = 0xffffffff;
741 }
742
743 /* Compute the final centroid priority. */
744 for (int i = 0; i < 8; i++) {
745 centroid_priority |=
746 centroid_priorities[i & sample_mask] << (i * 4);
747 }
748
749 return centroid_priority << 32 | centroid_priority;
750 }
751
752 /**
753 * Emit the sample locations that are specified with VK_EXT_sample_locations.
754 */
755 static void
756 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
757 {
758 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
759 struct radv_multisample_state *ms = &pipeline->graphics.ms;
760 struct radv_sample_locations_state *sample_location =
761 &cmd_buffer->state.dynamic.sample_location;
762 uint32_t num_samples = (uint32_t)sample_location->per_pixel;
763 struct radeon_cmdbuf *cs = cmd_buffer->cs;
764 uint32_t sample_locs_pixel[4][2] = {};
765 VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
766 uint32_t max_sample_dist = 0;
767 uint64_t centroid_priority;
768
769 if (!cmd_buffer->state.dynamic.sample_location.count)
770 return;
771
772 /* Convert the user sample locations to hardware sample locations. */
773 radv_convert_user_sample_locs(sample_location, 0, 0, sample_locs[0]);
774 radv_convert_user_sample_locs(sample_location, 1, 0, sample_locs[1]);
775 radv_convert_user_sample_locs(sample_location, 0, 1, sample_locs[2]);
776 radv_convert_user_sample_locs(sample_location, 1, 1, sample_locs[3]);
777
778 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
779 for (uint32_t i = 0; i < 4; i++) {
780 radv_compute_sample_locs_pixel(num_samples, sample_locs[i],
781 sample_locs_pixel[i]);
782 }
783
784 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
785 centroid_priority =
786 radv_compute_centroid_priority(cmd_buffer, sample_locs[0],
787 num_samples);
788
789 /* Compute the maximum sample distance from the specified locations. */
790 for (uint32_t i = 0; i < num_samples; i++) {
791 VkOffset2D offset = sample_locs[0][i];
792 max_sample_dist = MAX2(max_sample_dist,
793 MAX2(abs(offset.x), abs(offset.y)));
794 }
795
796 /* Emit the specified user sample locations. */
797 switch (num_samples) {
798 case 2:
799 case 4:
800 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
801 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
802 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
803 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
804 break;
805 case 8:
806 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
807 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
808 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
809 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
810 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs_pixel[0][1]);
811 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs_pixel[1][1]);
812 radeon_set_context_reg(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs_pixel[2][1]);
813 radeon_set_context_reg(cs, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs_pixel[3][1]);
814 break;
815 default:
816 unreachable("invalid number of samples");
817 }
818
819 /* Emit the maximum sample distance and the centroid priority. */
820 uint32_t pa_sc_aa_config = ms->pa_sc_aa_config;
821
822 pa_sc_aa_config &= C_028BE0_MAX_SAMPLE_DIST;
823 pa_sc_aa_config |= S_028BE0_MAX_SAMPLE_DIST(max_sample_dist);
824
825 radeon_set_context_reg_seq(cs, R_028BE0_PA_SC_AA_CONFIG, 1);
826 radeon_emit(cs, pa_sc_aa_config);
827
828 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
829 radeon_emit(cs, centroid_priority);
830 radeon_emit(cs, centroid_priority >> 32);
831
832 /* GFX9: Flush DFSM when the AA mode changes. */
833 if (cmd_buffer->device->dfsm_allowed) {
834 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
835 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
836 }
837
838 cmd_buffer->state.context_roll_without_scissor_emitted = true;
839 }
840
841 static void
842 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
843 struct radv_pipeline *pipeline,
844 gl_shader_stage stage,
845 int idx, int count, uint32_t *values)
846 {
847 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
848 uint32_t base_reg = pipeline->user_data_0[stage];
849 if (loc->sgpr_idx == -1)
850 return;
851
852 assert(loc->num_sgprs == count);
853
854 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
855 radeon_emit_array(cmd_buffer->cs, values, count);
856 }
857
858 static void
859 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
860 struct radv_pipeline *pipeline)
861 {
862 int num_samples = pipeline->graphics.ms.num_samples;
863 struct radv_multisample_state *ms = &pipeline->graphics.ms;
864 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
865
866 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
867 cmd_buffer->sample_positions_needed = true;
868
869 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
870 return;
871
872 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
873 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
874 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
875
876 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
877
878 radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
879
880 /* GFX9: Flush DFSM when the AA mode changes. */
881 if (cmd_buffer->device->dfsm_allowed) {
882 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
883 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
884 }
885
886 cmd_buffer->state.context_roll_without_scissor_emitted = true;
887 }
888
889 static void
890 radv_update_binning_state(struct radv_cmd_buffer *cmd_buffer,
891 struct radv_pipeline *pipeline)
892 {
893 const struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
894
895
896 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
897 return;
898
899 if (old_pipeline &&
900 old_pipeline->graphics.binning.pa_sc_binner_cntl_0 == pipeline->graphics.binning.pa_sc_binner_cntl_0 &&
901 old_pipeline->graphics.binning.db_dfsm_control == pipeline->graphics.binning.db_dfsm_control)
902 return;
903
904 bool binning_flush = false;
905 if (cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA12 ||
906 cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA20 ||
907 cmd_buffer->device->physical_device->rad_info.family == CHIP_RAVEN2 ||
908 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
909 binning_flush = !old_pipeline ||
910 G_028C44_BINNING_MODE(old_pipeline->graphics.binning.pa_sc_binner_cntl_0) !=
911 G_028C44_BINNING_MODE(pipeline->graphics.binning.pa_sc_binner_cntl_0);
912 }
913
914 radeon_set_context_reg(cmd_buffer->cs, R_028C44_PA_SC_BINNER_CNTL_0,
915 pipeline->graphics.binning.pa_sc_binner_cntl_0 |
916 S_028C44_FLUSH_ON_BINNING_TRANSITION(!!binning_flush));
917
918 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
919 radeon_set_context_reg(cmd_buffer->cs, R_028038_DB_DFSM_CONTROL,
920 pipeline->graphics.binning.db_dfsm_control);
921 } else {
922 radeon_set_context_reg(cmd_buffer->cs, R_028060_DB_DFSM_CONTROL,
923 pipeline->graphics.binning.db_dfsm_control);
924 }
925
926 cmd_buffer->state.context_roll_without_scissor_emitted = true;
927 }
928
929
930 static void
931 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
932 struct radv_shader_variant *shader)
933 {
934 uint64_t va;
935
936 if (!shader)
937 return;
938
939 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
940
941 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
942 }
943
944 static void
945 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
946 struct radv_pipeline *pipeline,
947 bool vertex_stage_only)
948 {
949 struct radv_cmd_state *state = &cmd_buffer->state;
950 uint32_t mask = state->prefetch_L2_mask;
951
952 if (vertex_stage_only) {
953 /* Fast prefetch path for starting draws as soon as possible.
954 */
955 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
956 RADV_PREFETCH_VBO_DESCRIPTORS);
957 }
958
959 if (mask & RADV_PREFETCH_VS)
960 radv_emit_shader_prefetch(cmd_buffer,
961 pipeline->shaders[MESA_SHADER_VERTEX]);
962
963 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
964 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
965
966 if (mask & RADV_PREFETCH_TCS)
967 radv_emit_shader_prefetch(cmd_buffer,
968 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
969
970 if (mask & RADV_PREFETCH_TES)
971 radv_emit_shader_prefetch(cmd_buffer,
972 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
973
974 if (mask & RADV_PREFETCH_GS) {
975 radv_emit_shader_prefetch(cmd_buffer,
976 pipeline->shaders[MESA_SHADER_GEOMETRY]);
977 if (radv_pipeline_has_gs_copy_shader(pipeline))
978 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
979 }
980
981 if (mask & RADV_PREFETCH_PS)
982 radv_emit_shader_prefetch(cmd_buffer,
983 pipeline->shaders[MESA_SHADER_FRAGMENT]);
984
985 state->prefetch_L2_mask &= ~mask;
986 }
987
988 static void
989 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
990 {
991 if (!cmd_buffer->device->physical_device->rbplus_allowed)
992 return;
993
994 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
995 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
996
997 unsigned sx_ps_downconvert = 0;
998 unsigned sx_blend_opt_epsilon = 0;
999 unsigned sx_blend_opt_control = 0;
1000
1001 for (unsigned i = 0; i < subpass->color_count; ++i) {
1002 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1003 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1004 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1005 continue;
1006 }
1007
1008 int idx = subpass->color_attachments[i].attachment;
1009 struct radv_color_buffer_info *cb = &cmd_buffer->state.attachments[idx].cb;
1010
1011 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
1012 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
1013 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
1014 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
1015
1016 bool has_alpha, has_rgb;
1017
1018 /* Set if RGB and A are present. */
1019 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
1020
1021 if (format == V_028C70_COLOR_8 ||
1022 format == V_028C70_COLOR_16 ||
1023 format == V_028C70_COLOR_32)
1024 has_rgb = !has_alpha;
1025 else
1026 has_rgb = true;
1027
1028 /* Check the colormask and export format. */
1029 if (!(colormask & 0x7))
1030 has_rgb = false;
1031 if (!(colormask & 0x8))
1032 has_alpha = false;
1033
1034 if (spi_format == V_028714_SPI_SHADER_ZERO) {
1035 has_rgb = false;
1036 has_alpha = false;
1037 }
1038
1039 /* Disable value checking for disabled channels. */
1040 if (!has_rgb)
1041 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1042 if (!has_alpha)
1043 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1044
1045 /* Enable down-conversion for 32bpp and smaller formats. */
1046 switch (format) {
1047 case V_028C70_COLOR_8:
1048 case V_028C70_COLOR_8_8:
1049 case V_028C70_COLOR_8_8_8_8:
1050 /* For 1 and 2-channel formats, use the superset thereof. */
1051 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
1052 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1053 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1054 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
1055 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
1056 }
1057 break;
1058
1059 case V_028C70_COLOR_5_6_5:
1060 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1061 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
1062 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
1063 }
1064 break;
1065
1066 case V_028C70_COLOR_1_5_5_5:
1067 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1068 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
1069 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
1070 }
1071 break;
1072
1073 case V_028C70_COLOR_4_4_4_4:
1074 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1075 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
1076 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
1077 }
1078 break;
1079
1080 case V_028C70_COLOR_32:
1081 if (swap == V_028C70_SWAP_STD &&
1082 spi_format == V_028714_SPI_SHADER_32_R)
1083 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1084 else if (swap == V_028C70_SWAP_ALT_REV &&
1085 spi_format == V_028714_SPI_SHADER_32_AR)
1086 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
1087 break;
1088
1089 case V_028C70_COLOR_16:
1090 case V_028C70_COLOR_16_16:
1091 /* For 1-channel formats, use the superset thereof. */
1092 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
1093 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
1094 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1095 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1096 if (swap == V_028C70_SWAP_STD ||
1097 swap == V_028C70_SWAP_STD_REV)
1098 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
1099 else
1100 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
1101 }
1102 break;
1103
1104 case V_028C70_COLOR_10_11_11:
1105 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1106 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
1107 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
1108 }
1109 break;
1110
1111 case V_028C70_COLOR_2_10_10_10:
1112 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1113 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
1114 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
1115 }
1116 break;
1117 }
1118 }
1119
1120 for (unsigned i = subpass->color_count; i < 8; ++i) {
1121 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1122 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1123 }
1124 /* TODO: avoid redundantly setting context registers */
1125 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
1126 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
1127 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
1128 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
1129
1130 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1131 }
1132
1133 static void
1134 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1135 {
1136 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1137
1138 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1139 return;
1140
1141 radv_update_multisample_state(cmd_buffer, pipeline);
1142 radv_update_binning_state(cmd_buffer, pipeline);
1143
1144 cmd_buffer->scratch_size_needed =
1145 MAX2(cmd_buffer->scratch_size_needed,
1146 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1147
1148 if (!cmd_buffer->state.emitted_pipeline ||
1149 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1150 pipeline->graphics.can_use_guardband)
1151 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1152
1153 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
1154
1155 if (!cmd_buffer->state.emitted_pipeline ||
1156 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
1157 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
1158 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
1159 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
1160 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
1161 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1162 }
1163
1164 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
1165 if (!pipeline->shaders[i])
1166 continue;
1167
1168 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1169 pipeline->shaders[i]->bo);
1170 }
1171
1172 if (radv_pipeline_has_gs_copy_shader(pipeline))
1173 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1174 pipeline->gs_copy_shader->bo);
1175
1176 if (unlikely(cmd_buffer->device->trace_bo))
1177 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1178
1179 cmd_buffer->state.emitted_pipeline = pipeline;
1180
1181 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1182 }
1183
1184 static void
1185 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1186 {
1187 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1188 cmd_buffer->state.dynamic.viewport.viewports);
1189 }
1190
1191 static void
1192 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1193 {
1194 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1195
1196 si_write_scissors(cmd_buffer->cs, 0, count,
1197 cmd_buffer->state.dynamic.scissor.scissors,
1198 cmd_buffer->state.dynamic.viewport.viewports,
1199 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1200
1201 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1202 }
1203
1204 static void
1205 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1206 {
1207 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1208 return;
1209
1210 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1211 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1212 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1213 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1214 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1215 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1216 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1217 }
1218 }
1219
1220 static void
1221 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1222 {
1223 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1224
1225 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1226 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1227 }
1228
1229 static void
1230 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1231 {
1232 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1233
1234 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1235 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1236 }
1237
1238 static void
1239 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1240 {
1241 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1242
1243 radeon_set_context_reg_seq(cmd_buffer->cs,
1244 R_028430_DB_STENCILREFMASK, 2);
1245 radeon_emit(cmd_buffer->cs,
1246 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1247 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1248 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1249 S_028430_STENCILOPVAL(1));
1250 radeon_emit(cmd_buffer->cs,
1251 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1252 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1253 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1254 S_028434_STENCILOPVAL_BF(1));
1255 }
1256
1257 static void
1258 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1259 {
1260 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1261
1262 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1263 fui(d->depth_bounds.min));
1264 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1265 fui(d->depth_bounds.max));
1266 }
1267
1268 static void
1269 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1270 {
1271 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1272 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1273 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1274
1275
1276 radeon_set_context_reg_seq(cmd_buffer->cs,
1277 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1278 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1279 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1280 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1281 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1282 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1283 }
1284
1285 static void
1286 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1287 int index,
1288 struct radv_color_buffer_info *cb,
1289 struct radv_image_view *iview,
1290 VkImageLayout layout,
1291 bool in_render_loop)
1292 {
1293 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
1294 uint32_t cb_color_info = cb->cb_color_info;
1295 struct radv_image *image = iview->image;
1296
1297 if (!radv_layout_dcc_compressed(cmd_buffer->device, image, layout, in_render_loop,
1298 radv_image_queue_family_mask(image,
1299 cmd_buffer->queue_family_index,
1300 cmd_buffer->queue_family_index))) {
1301 cb_color_info &= C_028C70_DCC_ENABLE;
1302 }
1303
1304 if (radv_image_is_tc_compat_cmask(image) &&
1305 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1306 radv_is_dcc_decompress_pipeline(cmd_buffer))) {
1307 /* If this bit is set, the FMASK decompression operation
1308 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1309 */
1310 cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
1311 }
1312
1313 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1314 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1315 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1316 radeon_emit(cmd_buffer->cs, 0);
1317 radeon_emit(cmd_buffer->cs, 0);
1318 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1319 radeon_emit(cmd_buffer->cs, cb_color_info);
1320 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1321 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1322 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1323 radeon_emit(cmd_buffer->cs, 0);
1324 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1325 radeon_emit(cmd_buffer->cs, 0);
1326
1327 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 1);
1328 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1329
1330 radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4,
1331 cb->cb_color_base >> 32);
1332 radeon_set_context_reg(cmd_buffer->cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + index * 4,
1333 cb->cb_color_cmask >> 32);
1334 radeon_set_context_reg(cmd_buffer->cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + index * 4,
1335 cb->cb_color_fmask >> 32);
1336 radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4,
1337 cb->cb_dcc_base >> 32);
1338 radeon_set_context_reg(cmd_buffer->cs, R_028EC0_CB_COLOR0_ATTRIB2 + index * 4,
1339 cb->cb_color_attrib2);
1340 radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4,
1341 cb->cb_color_attrib3);
1342 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1343 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1344 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1345 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1346 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1347 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1348 radeon_emit(cmd_buffer->cs, cb_color_info);
1349 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1350 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1351 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1352 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1353 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1354 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1355
1356 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1357 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1358 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1359
1360 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1361 cb->cb_mrt_epitch);
1362 } else {
1363 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1364 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1365 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1366 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1367 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1368 radeon_emit(cmd_buffer->cs, cb_color_info);
1369 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1370 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1371 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1372 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1373 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1374 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1375
1376 if (is_vi) { /* DCC BASE */
1377 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1378 }
1379 }
1380
1381 if (radv_dcc_enabled(image, iview->base_mip)) {
1382 /* Drawing with DCC enabled also compresses colorbuffers. */
1383 VkImageSubresourceRange range = {
1384 .aspectMask = iview->aspect_mask,
1385 .baseMipLevel = iview->base_mip,
1386 .levelCount = iview->level_count,
1387 .baseArrayLayer = iview->base_layer,
1388 .layerCount = iview->layer_count,
1389 };
1390
1391 radv_update_dcc_metadata(cmd_buffer, image, &range, true);
1392 }
1393 }
1394
1395 static void
1396 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1397 struct radv_ds_buffer_info *ds,
1398 struct radv_image *image, VkImageLayout layout,
1399 bool in_render_loop, bool requires_cond_exec)
1400 {
1401 uint32_t db_z_info = ds->db_z_info;
1402 uint32_t db_z_info_reg;
1403
1404 if (!cmd_buffer->device->physical_device->has_tc_compat_zrange_bug ||
1405 !radv_image_is_tc_compat_htile(image))
1406 return;
1407
1408 if (!radv_layout_has_htile(image, layout, in_render_loop,
1409 radv_image_queue_family_mask(image,
1410 cmd_buffer->queue_family_index,
1411 cmd_buffer->queue_family_index))) {
1412 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1413 }
1414
1415 db_z_info &= C_028040_ZRANGE_PRECISION;
1416
1417 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1418 db_z_info_reg = R_028038_DB_Z_INFO;
1419 } else {
1420 db_z_info_reg = R_028040_DB_Z_INFO;
1421 }
1422
1423 /* When we don't know the last fast clear value we need to emit a
1424 * conditional packet that will eventually skip the following
1425 * SET_CONTEXT_REG packet.
1426 */
1427 if (requires_cond_exec) {
1428 uint64_t va = radv_buffer_get_va(image->bo);
1429 va += image->offset + image->tc_compat_zrange_offset;
1430
1431 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1432 radeon_emit(cmd_buffer->cs, va);
1433 radeon_emit(cmd_buffer->cs, va >> 32);
1434 radeon_emit(cmd_buffer->cs, 0);
1435 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1436 }
1437
1438 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1439 }
1440
1441 static void
1442 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1443 struct radv_ds_buffer_info *ds,
1444 struct radv_image *image,
1445 VkImageLayout layout,
1446 bool in_render_loop)
1447 {
1448 uint32_t db_z_info = ds->db_z_info;
1449 uint32_t db_stencil_info = ds->db_stencil_info;
1450
1451 if (!radv_layout_has_htile(image, layout, in_render_loop,
1452 radv_image_queue_family_mask(image,
1453 cmd_buffer->queue_family_index,
1454 cmd_buffer->queue_family_index))) {
1455 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1456 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1457 }
1458
1459 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1460 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1461
1462 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1463 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1464 radeon_set_context_reg(cmd_buffer->cs, R_02801C_DB_DEPTH_SIZE_XY, ds->db_depth_size);
1465
1466 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 7);
1467 radeon_emit(cmd_buffer->cs, S_02803C_RESOURCE_LEVEL(1));
1468 radeon_emit(cmd_buffer->cs, db_z_info);
1469 radeon_emit(cmd_buffer->cs, db_stencil_info);
1470 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1471 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1472 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1473 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1474
1475 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_READ_BASE_HI, 5);
1476 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1477 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1478 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1479 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1480 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1481 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1482 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1483 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1484 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1485 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1486
1487 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1488 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1489 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1490 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1491 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1492 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1493 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1494 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1495 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1496 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1497 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1498
1499 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1500 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1501 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1502 } else {
1503 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1504
1505 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1506 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1507 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1508 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1509 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1510 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1511 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1512 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1513 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1514 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1515
1516 }
1517
1518 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1519 radv_update_zrange_precision(cmd_buffer, ds, image, layout, in_render_loop, true);
1520
1521 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1522 ds->pa_su_poly_offset_db_fmt_cntl);
1523 }
1524
1525 /**
1526 * Update the fast clear depth/stencil values if the image is bound as a
1527 * depth/stencil buffer.
1528 */
1529 static void
1530 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1531 struct radv_image *image,
1532 VkClearDepthStencilValue ds_clear_value,
1533 VkImageAspectFlags aspects)
1534 {
1535 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1536 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1537 uint32_t att_idx;
1538
1539 if (!cmd_buffer->state.attachments || !subpass)
1540 return;
1541
1542 if (!subpass->depth_stencil_attachment)
1543 return;
1544
1545 att_idx = subpass->depth_stencil_attachment->attachment;
1546 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1547 return;
1548
1549 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1550 radeon_emit(cs, ds_clear_value.stencil);
1551 radeon_emit(cs, fui(ds_clear_value.depth));
1552
1553 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1554 * only needed when clearing Z to 0.0.
1555 */
1556 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1557 ds_clear_value.depth == 0.0) {
1558 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1559 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
1560
1561 radv_update_zrange_precision(cmd_buffer, &cmd_buffer->state.attachments[att_idx].ds, image,
1562 layout, in_render_loop, false);
1563 }
1564
1565 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1566 }
1567
1568 /**
1569 * Set the clear depth/stencil values to the image's metadata.
1570 */
1571 static void
1572 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1573 struct radv_image *image,
1574 VkClearDepthStencilValue ds_clear_value,
1575 VkImageAspectFlags aspects)
1576 {
1577 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1578 uint64_t va = radv_buffer_get_va(image->bo);
1579 unsigned reg_offset = 0, reg_count = 0;
1580
1581 va += image->offset + image->clear_value_offset;
1582
1583 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1584 ++reg_count;
1585 } else {
1586 ++reg_offset;
1587 va += 4;
1588 }
1589 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1590 ++reg_count;
1591
1592 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, cmd_buffer->state.predicating));
1593 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1594 S_370_WR_CONFIRM(1) |
1595 S_370_ENGINE_SEL(V_370_PFP));
1596 radeon_emit(cs, va);
1597 radeon_emit(cs, va >> 32);
1598 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1599 radeon_emit(cs, ds_clear_value.stencil);
1600 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1601 radeon_emit(cs, fui(ds_clear_value.depth));
1602 }
1603
1604 /**
1605 * Update the TC-compat metadata value for this image.
1606 */
1607 static void
1608 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1609 struct radv_image *image,
1610 uint32_t value)
1611 {
1612 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1613 uint64_t va = radv_buffer_get_va(image->bo);
1614
1615 if (!cmd_buffer->device->physical_device->has_tc_compat_zrange_bug)
1616 return;
1617
1618 va += image->offset + image->tc_compat_zrange_offset;
1619
1620 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1621 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1622 S_370_WR_CONFIRM(1) |
1623 S_370_ENGINE_SEL(V_370_PFP));
1624 radeon_emit(cs, va);
1625 radeon_emit(cs, va >> 32);
1626 radeon_emit(cs, value);
1627 }
1628
1629 static void
1630 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1631 struct radv_image *image,
1632 VkClearDepthStencilValue ds_clear_value)
1633 {
1634 uint32_t cond_val;
1635
1636 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1637 * depth clear value is 0.0f.
1638 */
1639 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1640
1641 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, cond_val);
1642 }
1643
1644 /**
1645 * Update the clear depth/stencil values for this image.
1646 */
1647 void
1648 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1649 struct radv_image *image,
1650 VkClearDepthStencilValue ds_clear_value,
1651 VkImageAspectFlags aspects)
1652 {
1653 assert(radv_image_has_htile(image));
1654
1655 radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
1656
1657 if (radv_image_is_tc_compat_htile(image) &&
1658 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1659 radv_update_tc_compat_zrange_metadata(cmd_buffer, image,
1660 ds_clear_value);
1661 }
1662
1663 radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1664 aspects);
1665 }
1666
1667 /**
1668 * Load the clear depth/stencil values from the image's metadata.
1669 */
1670 static void
1671 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1672 struct radv_image *image)
1673 {
1674 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1675 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1676 uint64_t va = radv_buffer_get_va(image->bo);
1677 unsigned reg_offset = 0, reg_count = 0;
1678
1679 va += image->offset + image->clear_value_offset;
1680
1681 if (!radv_image_has_htile(image))
1682 return;
1683
1684 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1685 ++reg_count;
1686 } else {
1687 ++reg_offset;
1688 va += 4;
1689 }
1690 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1691 ++reg_count;
1692
1693 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1694
1695 if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) {
1696 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1697 radeon_emit(cs, va);
1698 radeon_emit(cs, va >> 32);
1699 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1700 radeon_emit(cs, reg_count);
1701 } else {
1702 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1703 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1704 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1705 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1706 radeon_emit(cs, va);
1707 radeon_emit(cs, va >> 32);
1708 radeon_emit(cs, reg >> 2);
1709 radeon_emit(cs, 0);
1710
1711 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1712 radeon_emit(cs, 0);
1713 }
1714 }
1715
1716 /*
1717 * With DCC some colors don't require CMASK elimination before being
1718 * used as a texture. This sets a predicate value to determine if the
1719 * cmask eliminate is required.
1720 */
1721 void
1722 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1723 struct radv_image *image,
1724 const VkImageSubresourceRange *range, bool value)
1725 {
1726 uint64_t pred_val = value;
1727 uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
1728 uint32_t level_count = radv_get_levelCount(image, range);
1729 uint32_t count = 2 * level_count;
1730
1731 assert(radv_dcc_enabled(image, range->baseMipLevel));
1732
1733 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1734 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1735 S_370_WR_CONFIRM(1) |
1736 S_370_ENGINE_SEL(V_370_PFP));
1737 radeon_emit(cmd_buffer->cs, va);
1738 radeon_emit(cmd_buffer->cs, va >> 32);
1739
1740 for (uint32_t l = 0; l < level_count; l++) {
1741 radeon_emit(cmd_buffer->cs, pred_val);
1742 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1743 }
1744 }
1745
1746 /**
1747 * Update the DCC predicate to reflect the compression state.
1748 */
1749 void
1750 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1751 struct radv_image *image,
1752 const VkImageSubresourceRange *range, bool value)
1753 {
1754 uint64_t pred_val = value;
1755 uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
1756 uint32_t level_count = radv_get_levelCount(image, range);
1757 uint32_t count = 2 * level_count;
1758
1759 assert(radv_dcc_enabled(image, range->baseMipLevel));
1760
1761 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1762 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1763 S_370_WR_CONFIRM(1) |
1764 S_370_ENGINE_SEL(V_370_PFP));
1765 radeon_emit(cmd_buffer->cs, va);
1766 radeon_emit(cmd_buffer->cs, va >> 32);
1767
1768 for (uint32_t l = 0; l < level_count; l++) {
1769 radeon_emit(cmd_buffer->cs, pred_val);
1770 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1771 }
1772 }
1773
1774 /**
1775 * Update the fast clear color values if the image is bound as a color buffer.
1776 */
1777 static void
1778 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1779 struct radv_image *image,
1780 int cb_idx,
1781 uint32_t color_values[2])
1782 {
1783 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1784 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1785 uint32_t att_idx;
1786
1787 if (!cmd_buffer->state.attachments || !subpass)
1788 return;
1789
1790 att_idx = subpass->color_attachments[cb_idx].attachment;
1791 if (att_idx == VK_ATTACHMENT_UNUSED)
1792 return;
1793
1794 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1795 return;
1796
1797 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1798 radeon_emit(cs, color_values[0]);
1799 radeon_emit(cs, color_values[1]);
1800
1801 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1802 }
1803
1804 /**
1805 * Set the clear color values to the image's metadata.
1806 */
1807 static void
1808 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1809 struct radv_image *image,
1810 const VkImageSubresourceRange *range,
1811 uint32_t color_values[2])
1812 {
1813 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1814 uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
1815 uint32_t level_count = radv_get_levelCount(image, range);
1816 uint32_t count = 2 * level_count;
1817
1818 assert(radv_image_has_cmask(image) ||
1819 radv_dcc_enabled(image, range->baseMipLevel));
1820
1821 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
1822 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1823 S_370_WR_CONFIRM(1) |
1824 S_370_ENGINE_SEL(V_370_PFP));
1825 radeon_emit(cs, va);
1826 radeon_emit(cs, va >> 32);
1827
1828 for (uint32_t l = 0; l < level_count; l++) {
1829 radeon_emit(cs, color_values[0]);
1830 radeon_emit(cs, color_values[1]);
1831 }
1832 }
1833
1834 /**
1835 * Update the clear color values for this image.
1836 */
1837 void
1838 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1839 const struct radv_image_view *iview,
1840 int cb_idx,
1841 uint32_t color_values[2])
1842 {
1843 struct radv_image *image = iview->image;
1844 VkImageSubresourceRange range = {
1845 .aspectMask = iview->aspect_mask,
1846 .baseMipLevel = iview->base_mip,
1847 .levelCount = iview->level_count,
1848 .baseArrayLayer = iview->base_layer,
1849 .layerCount = iview->layer_count,
1850 };
1851
1852 assert(radv_image_has_cmask(image) ||
1853 radv_dcc_enabled(image, iview->base_mip));
1854
1855 radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
1856
1857 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1858 color_values);
1859 }
1860
1861 /**
1862 * Load the clear color values from the image's metadata.
1863 */
1864 static void
1865 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1866 struct radv_image_view *iview,
1867 int cb_idx)
1868 {
1869 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1870 struct radv_image *image = iview->image;
1871 uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
1872
1873 if (!radv_image_has_cmask(image) &&
1874 !radv_dcc_enabled(image, iview->base_mip))
1875 return;
1876
1877 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1878
1879 if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) {
1880 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1881 radeon_emit(cs, va);
1882 radeon_emit(cs, va >> 32);
1883 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1884 radeon_emit(cs, 2);
1885 } else {
1886 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1887 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1888 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1889 COPY_DATA_COUNT_SEL);
1890 radeon_emit(cs, va);
1891 radeon_emit(cs, va >> 32);
1892 radeon_emit(cs, reg >> 2);
1893 radeon_emit(cs, 0);
1894
1895 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1896 radeon_emit(cs, 0);
1897 }
1898 }
1899
1900 static void
1901 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1902 {
1903 int i;
1904 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1905 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1906
1907 /* this may happen for inherited secondary recording */
1908 if (!framebuffer)
1909 return;
1910
1911 for (i = 0; i < 8; ++i) {
1912 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1913 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1914 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1915 continue;
1916 }
1917
1918 int idx = subpass->color_attachments[i].attachment;
1919 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
1920 VkImageLayout layout = subpass->color_attachments[i].layout;
1921 bool in_render_loop = subpass->color_attachments[i].in_render_loop;
1922
1923 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, iview->bo);
1924
1925 assert(iview->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
1926 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
1927 radv_emit_fb_color_state(cmd_buffer, i, &cmd_buffer->state.attachments[idx].cb, iview, layout, in_render_loop);
1928
1929 radv_load_color_clear_metadata(cmd_buffer, iview, i);
1930 }
1931
1932 if (subpass->depth_stencil_attachment) {
1933 int idx = subpass->depth_stencil_attachment->attachment;
1934 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1935 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
1936 struct radv_image *image = cmd_buffer->state.attachments[idx].iview->image;
1937 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, cmd_buffer->state.attachments[idx].iview->bo);
1938 ASSERTED uint32_t queue_mask = radv_image_queue_family_mask(image,
1939 cmd_buffer->queue_family_index,
1940 cmd_buffer->queue_family_index);
1941 /* We currently don't support writing decompressed HTILE */
1942 assert(radv_layout_has_htile(image, layout, in_render_loop, queue_mask) ==
1943 radv_layout_is_htile_compressed(image, layout, in_render_loop, queue_mask));
1944
1945 radv_emit_fb_ds_state(cmd_buffer, &cmd_buffer->state.attachments[idx].ds, image, layout, in_render_loop);
1946
1947 if (cmd_buffer->state.attachments[idx].ds.offset_scale != cmd_buffer->state.offset_scale) {
1948 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1949 cmd_buffer->state.offset_scale = cmd_buffer->state.attachments[idx].ds.offset_scale;
1950 }
1951 radv_load_ds_clear_metadata(cmd_buffer, image);
1952 } else {
1953 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9)
1954 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1955 else
1956 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1957
1958 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1959 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1960 }
1961 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1962 S_028208_BR_X(framebuffer->width) |
1963 S_028208_BR_Y(framebuffer->height));
1964
1965 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
1966 bool disable_constant_encode =
1967 cmd_buffer->device->physical_device->has_dcc_constant_encode;
1968 enum chip_class chip_class =
1969 cmd_buffer->device->physical_device->rad_info.chip_class;
1970 uint8_t watermark = chip_class >= GFX10 ? 6 : 4;
1971
1972 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
1973 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class <= GFX9) |
1974 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
1975 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
1976 }
1977
1978 if (cmd_buffer->device->pbb_allowed) {
1979 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1980 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1981 }
1982
1983 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1984 }
1985
1986 static void
1987 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1988 {
1989 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1990 struct radv_cmd_state *state = &cmd_buffer->state;
1991
1992 if (state->index_type != state->last_index_type) {
1993 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1994 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
1995 cs, R_03090C_VGT_INDEX_TYPE,
1996 2, state->index_type);
1997 } else {
1998 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1999 radeon_emit(cs, state->index_type);
2000 }
2001
2002 state->last_index_type = state->index_type;
2003 }
2004
2005 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2006 radeon_emit(cs, state->index_va);
2007 radeon_emit(cs, state->index_va >> 32);
2008
2009 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2010 radeon_emit(cs, state->max_index_count);
2011
2012 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
2013 }
2014
2015 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
2016 {
2017 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
2018 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2019 uint32_t pa_sc_mode_cntl_1 =
2020 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
2021 uint32_t db_count_control;
2022
2023 if(!cmd_buffer->state.active_occlusion_queries) {
2024 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2025 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2026 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2027 has_perfect_queries) {
2028 /* Re-enable out-of-order rasterization if the
2029 * bound pipeline supports it and if it's has
2030 * been disabled before starting any perfect
2031 * occlusion queries.
2032 */
2033 radeon_set_context_reg(cmd_buffer->cs,
2034 R_028A4C_PA_SC_MODE_CNTL_1,
2035 pa_sc_mode_cntl_1);
2036 }
2037 }
2038 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
2039 } else {
2040 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2041 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
2042 bool gfx10_perfect = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10 && has_perfect_queries;
2043
2044 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2045 db_count_control =
2046 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
2047 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
2048 S_028004_SAMPLE_RATE(sample_rate) |
2049 S_028004_ZPASS_ENABLE(1) |
2050 S_028004_SLICE_EVEN_ENABLE(1) |
2051 S_028004_SLICE_ODD_ENABLE(1);
2052
2053 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2054 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2055 has_perfect_queries) {
2056 /* If the bound pipeline has enabled
2057 * out-of-order rasterization, we should
2058 * disable it before starting any perfect
2059 * occlusion queries.
2060 */
2061 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
2062
2063 radeon_set_context_reg(cmd_buffer->cs,
2064 R_028A4C_PA_SC_MODE_CNTL_1,
2065 pa_sc_mode_cntl_1);
2066 }
2067 } else {
2068 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
2069 S_028004_SAMPLE_RATE(sample_rate);
2070 }
2071 }
2072
2073 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
2074
2075 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2076 }
2077
2078 static void
2079 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
2080 {
2081 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
2082
2083 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
2084 radv_emit_viewport(cmd_buffer);
2085
2086 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
2087 !cmd_buffer->device->physical_device->has_scissor_bug)
2088 radv_emit_scissor(cmd_buffer);
2089
2090 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
2091 radv_emit_line_width(cmd_buffer);
2092
2093 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
2094 radv_emit_blend_constants(cmd_buffer);
2095
2096 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
2097 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
2098 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
2099 radv_emit_stencil(cmd_buffer);
2100
2101 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
2102 radv_emit_depth_bounds(cmd_buffer);
2103
2104 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
2105 radv_emit_depth_bias(cmd_buffer);
2106
2107 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
2108 radv_emit_discard_rectangle(cmd_buffer);
2109
2110 if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)
2111 radv_emit_sample_locations(cmd_buffer);
2112
2113 cmd_buffer->state.dirty &= ~states;
2114 }
2115
2116 static void
2117 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
2118 VkPipelineBindPoint bind_point)
2119 {
2120 struct radv_descriptor_state *descriptors_state =
2121 radv_get_descriptors_state(cmd_buffer, bind_point);
2122 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
2123 unsigned bo_offset;
2124
2125 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
2126 set->mapped_ptr,
2127 &bo_offset))
2128 return;
2129
2130 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2131 set->va += bo_offset;
2132 }
2133
2134 static void
2135 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
2136 VkPipelineBindPoint bind_point)
2137 {
2138 struct radv_descriptor_state *descriptors_state =
2139 radv_get_descriptors_state(cmd_buffer, bind_point);
2140 uint32_t size = MAX_SETS * 4;
2141 uint32_t offset;
2142 void *ptr;
2143
2144 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
2145 256, &offset, &ptr))
2146 return;
2147
2148 for (unsigned i = 0; i < MAX_SETS; i++) {
2149 uint32_t *uptr = ((uint32_t *)ptr) + i;
2150 uint64_t set_va = 0;
2151 struct radv_descriptor_set *set = descriptors_state->sets[i];
2152 if (descriptors_state->valid & (1u << i))
2153 set_va = set->va;
2154 uptr[0] = set_va & 0xffffffff;
2155 }
2156
2157 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2158 va += offset;
2159
2160 if (cmd_buffer->state.pipeline) {
2161 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
2162 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2163 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2164
2165 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
2166 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
2167 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2168
2169 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
2170 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2171 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2172
2173 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2174 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
2175 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2176
2177 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2178 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
2179 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2180 }
2181
2182 if (cmd_buffer->state.compute_pipeline)
2183 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
2184 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2185 }
2186
2187 static void
2188 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
2189 VkShaderStageFlags stages)
2190 {
2191 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2192 VK_PIPELINE_BIND_POINT_COMPUTE :
2193 VK_PIPELINE_BIND_POINT_GRAPHICS;
2194 struct radv_descriptor_state *descriptors_state =
2195 radv_get_descriptors_state(cmd_buffer, bind_point);
2196 struct radv_cmd_state *state = &cmd_buffer->state;
2197 bool flush_indirect_descriptors;
2198
2199 if (!descriptors_state->dirty)
2200 return;
2201
2202 if (descriptors_state->push_dirty)
2203 radv_flush_push_descriptors(cmd_buffer, bind_point);
2204
2205 flush_indirect_descriptors =
2206 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
2207 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
2208 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
2209 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
2210
2211 if (flush_indirect_descriptors)
2212 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
2213
2214 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2215 cmd_buffer->cs,
2216 MAX_SETS * MESA_SHADER_STAGES * 4);
2217
2218 if (cmd_buffer->state.pipeline) {
2219 radv_foreach_stage(stage, stages) {
2220 if (!cmd_buffer->state.pipeline->shaders[stage])
2221 continue;
2222
2223 radv_emit_descriptor_pointers(cmd_buffer,
2224 cmd_buffer->state.pipeline,
2225 descriptors_state, stage);
2226 }
2227 }
2228
2229 if (cmd_buffer->state.compute_pipeline &&
2230 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
2231 radv_emit_descriptor_pointers(cmd_buffer,
2232 cmd_buffer->state.compute_pipeline,
2233 descriptors_state,
2234 MESA_SHADER_COMPUTE);
2235 }
2236
2237 descriptors_state->dirty = 0;
2238 descriptors_state->push_dirty = false;
2239
2240 assert(cmd_buffer->cs->cdw <= cdw_max);
2241
2242 if (unlikely(cmd_buffer->device->trace_bo))
2243 radv_save_descriptors(cmd_buffer, bind_point);
2244 }
2245
2246 static void
2247 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
2248 VkShaderStageFlags stages)
2249 {
2250 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
2251 ? cmd_buffer->state.compute_pipeline
2252 : cmd_buffer->state.pipeline;
2253 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2254 VK_PIPELINE_BIND_POINT_COMPUTE :
2255 VK_PIPELINE_BIND_POINT_GRAPHICS;
2256 struct radv_descriptor_state *descriptors_state =
2257 radv_get_descriptors_state(cmd_buffer, bind_point);
2258 struct radv_pipeline_layout *layout = pipeline->layout;
2259 struct radv_shader_variant *shader, *prev_shader;
2260 bool need_push_constants = false;
2261 unsigned offset;
2262 void *ptr;
2263 uint64_t va;
2264
2265 stages &= cmd_buffer->push_constant_stages;
2266 if (!stages ||
2267 (!layout->push_constant_size && !layout->dynamic_offset_count))
2268 return;
2269
2270 radv_foreach_stage(stage, stages) {
2271 if (!pipeline->shaders[stage])
2272 continue;
2273
2274 need_push_constants |= pipeline->shaders[stage]->info.info.loads_push_constants;
2275 need_push_constants |= pipeline->shaders[stage]->info.info.loads_dynamic_offsets;
2276
2277 uint8_t base = pipeline->shaders[stage]->info.info.base_inline_push_consts;
2278 uint8_t count = pipeline->shaders[stage]->info.info.num_inline_push_consts;
2279
2280 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
2281 AC_UD_INLINE_PUSH_CONSTANTS,
2282 count,
2283 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
2284 }
2285
2286 if (need_push_constants) {
2287 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
2288 16 * layout->dynamic_offset_count,
2289 256, &offset, &ptr))
2290 return;
2291
2292 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
2293 memcpy((char*)ptr + layout->push_constant_size,
2294 descriptors_state->dynamic_buffers,
2295 16 * layout->dynamic_offset_count);
2296
2297 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2298 va += offset;
2299
2300 ASSERTED unsigned cdw_max =
2301 radeon_check_space(cmd_buffer->device->ws,
2302 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
2303
2304 prev_shader = NULL;
2305 radv_foreach_stage(stage, stages) {
2306 shader = radv_get_shader(pipeline, stage);
2307
2308 /* Avoid redundantly emitting the address for merged stages. */
2309 if (shader && shader != prev_shader) {
2310 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
2311 AC_UD_PUSH_CONSTANTS, va);
2312
2313 prev_shader = shader;
2314 }
2315 }
2316 assert(cmd_buffer->cs->cdw <= cdw_max);
2317 }
2318
2319 cmd_buffer->push_constant_stages &= ~stages;
2320 }
2321
2322 static void
2323 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
2324 bool pipeline_is_dirty)
2325 {
2326 if ((pipeline_is_dirty ||
2327 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
2328 cmd_buffer->state.pipeline->num_vertex_bindings &&
2329 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
2330 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
2331 unsigned vb_offset;
2332 void *vb_ptr;
2333 uint32_t i = 0;
2334 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
2335 uint64_t va;
2336
2337 /* allocate some descriptor state for vertex buffers */
2338 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2339 &vb_offset, &vb_ptr))
2340 return;
2341
2342 for (i = 0; i < count; i++) {
2343 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2344 uint32_t offset;
2345 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2346 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[i];
2347
2348 if (!buffer)
2349 continue;
2350
2351 va = radv_buffer_get_va(buffer->bo);
2352
2353 offset = cmd_buffer->vertex_bindings[i].offset;
2354 va += offset + buffer->offset;
2355 desc[0] = va;
2356 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2357 if (cmd_buffer->device->physical_device->rad_info.chip_class <= GFX7 && stride)
2358 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
2359 else
2360 desc[2] = buffer->size - offset;
2361 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2362 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2363 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2364 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2365
2366 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2367 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT) |
2368 S_008F0C_OOB_SELECT(1) |
2369 S_008F0C_RESOURCE_LEVEL(1);
2370 } else {
2371 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2372 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2373 }
2374 }
2375
2376 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2377 va += vb_offset;
2378
2379 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2380 AC_UD_VS_VERTEX_BUFFERS, va);
2381
2382 cmd_buffer->state.vb_va = va;
2383 cmd_buffer->state.vb_size = count * 16;
2384 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2385 }
2386 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2387 }
2388
2389 static void
2390 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2391 {
2392 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2393 struct radv_userdata_info *loc;
2394 uint32_t base_reg;
2395
2396 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2397 if (!radv_get_shader(pipeline, stage))
2398 continue;
2399
2400 loc = radv_lookup_user_sgpr(pipeline, stage,
2401 AC_UD_STREAMOUT_BUFFERS);
2402 if (loc->sgpr_idx == -1)
2403 continue;
2404
2405 base_reg = pipeline->user_data_0[stage];
2406
2407 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2408 base_reg + loc->sgpr_idx * 4, va, false);
2409 }
2410
2411 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
2412 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2413 if (loc->sgpr_idx != -1) {
2414 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2415
2416 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2417 base_reg + loc->sgpr_idx * 4, va, false);
2418 }
2419 }
2420 }
2421
2422 static void
2423 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2424 {
2425 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2426 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2427 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2428 unsigned so_offset;
2429 void *so_ptr;
2430 uint64_t va;
2431
2432 /* Allocate some descriptor state for streamout buffers. */
2433 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2434 MAX_SO_BUFFERS * 16, 256,
2435 &so_offset, &so_ptr))
2436 return;
2437
2438 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2439 struct radv_buffer *buffer = sb[i].buffer;
2440 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2441
2442 if (!(so->enabled_mask & (1 << i)))
2443 continue;
2444
2445 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2446
2447 va += sb[i].offset;
2448
2449 /* Set the descriptor.
2450 *
2451 * On GFX8, the format must be non-INVALID, otherwise
2452 * the buffer will be considered not bound and store
2453 * instructions will be no-ops.
2454 */
2455 desc[0] = va;
2456 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2457 desc[2] = 0xffffffff;
2458 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2459 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2460 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2461 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2462
2463 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2464 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2465 S_008F0C_OOB_SELECT(3) |
2466 S_008F0C_RESOURCE_LEVEL(1);
2467 } else {
2468 desc[3] |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2469 }
2470 }
2471
2472 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2473 va += so_offset;
2474
2475 radv_emit_streamout_buffers(cmd_buffer, va);
2476 }
2477
2478 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2479 }
2480
2481 static void
2482 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2483 {
2484 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2485 radv_flush_streamout_descriptors(cmd_buffer);
2486 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2487 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2488 }
2489
2490 struct radv_draw_info {
2491 /**
2492 * Number of vertices.
2493 */
2494 uint32_t count;
2495
2496 /**
2497 * Index of the first vertex.
2498 */
2499 int32_t vertex_offset;
2500
2501 /**
2502 * First instance id.
2503 */
2504 uint32_t first_instance;
2505
2506 /**
2507 * Number of instances.
2508 */
2509 uint32_t instance_count;
2510
2511 /**
2512 * First index (indexed draws only).
2513 */
2514 uint32_t first_index;
2515
2516 /**
2517 * Whether it's an indexed draw.
2518 */
2519 bool indexed;
2520
2521 /**
2522 * Indirect draw parameters resource.
2523 */
2524 struct radv_buffer *indirect;
2525 uint64_t indirect_offset;
2526 uint32_t stride;
2527
2528 /**
2529 * Draw count parameters resource.
2530 */
2531 struct radv_buffer *count_buffer;
2532 uint64_t count_buffer_offset;
2533
2534 /**
2535 * Stream output parameters resource.
2536 */
2537 struct radv_buffer *strmout_buffer;
2538 uint64_t strmout_buffer_offset;
2539 };
2540
2541 static uint32_t
2542 radv_get_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
2543 {
2544 switch (cmd_buffer->state.index_type) {
2545 case V_028A7C_VGT_INDEX_8:
2546 return 0xffu;
2547 case V_028A7C_VGT_INDEX_16:
2548 return 0xffffu;
2549 case V_028A7C_VGT_INDEX_32:
2550 return 0xffffffffu;
2551 default:
2552 unreachable("invalid index type");
2553 }
2554 }
2555
2556 static void
2557 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
2558 bool instanced_draw, bool indirect_draw,
2559 bool count_from_stream_output,
2560 uint32_t draw_vertex_count)
2561 {
2562 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2563 struct radv_cmd_state *state = &cmd_buffer->state;
2564 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2565 unsigned ia_multi_vgt_param;
2566
2567 ia_multi_vgt_param =
2568 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
2569 indirect_draw,
2570 count_from_stream_output,
2571 draw_vertex_count);
2572
2573 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2574 if (info->chip_class == GFX9) {
2575 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2576 cs,
2577 R_030960_IA_MULTI_VGT_PARAM,
2578 4, ia_multi_vgt_param);
2579 } else if (info->chip_class >= GFX7) {
2580 radeon_set_context_reg_idx(cs,
2581 R_028AA8_IA_MULTI_VGT_PARAM,
2582 1, ia_multi_vgt_param);
2583 } else {
2584 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2585 ia_multi_vgt_param);
2586 }
2587 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2588 }
2589 }
2590
2591 static void
2592 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2593 const struct radv_draw_info *draw_info)
2594 {
2595 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2596 struct radv_cmd_state *state = &cmd_buffer->state;
2597 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2598 int32_t primitive_reset_en;
2599
2600 /* Draw state. */
2601 if (info->chip_class < GFX10) {
2602 si_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2603 draw_info->indirect,
2604 !!draw_info->strmout_buffer,
2605 draw_info->indirect ? 0 : draw_info->count);
2606 }
2607
2608 /* Primitive restart. */
2609 primitive_reset_en =
2610 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2611
2612 if (primitive_reset_en != state->last_primitive_reset_en) {
2613 state->last_primitive_reset_en = primitive_reset_en;
2614 if (info->chip_class >= GFX9) {
2615 radeon_set_uconfig_reg(cs,
2616 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2617 primitive_reset_en);
2618 } else {
2619 radeon_set_context_reg(cs,
2620 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2621 primitive_reset_en);
2622 }
2623 }
2624
2625 if (primitive_reset_en) {
2626 uint32_t primitive_reset_index =
2627 radv_get_primitive_reset_index(cmd_buffer);
2628
2629 if (primitive_reset_index != state->last_primitive_reset_index) {
2630 radeon_set_context_reg(cs,
2631 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2632 primitive_reset_index);
2633 state->last_primitive_reset_index = primitive_reset_index;
2634 }
2635 }
2636
2637 if (draw_info->strmout_buffer) {
2638 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2639
2640 va += draw_info->strmout_buffer->offset +
2641 draw_info->strmout_buffer_offset;
2642
2643 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2644 draw_info->stride);
2645
2646 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2647 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2648 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2649 COPY_DATA_WR_CONFIRM);
2650 radeon_emit(cs, va);
2651 radeon_emit(cs, va >> 32);
2652 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2653 radeon_emit(cs, 0); /* unused */
2654
2655 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2656 }
2657 }
2658
2659 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2660 VkPipelineStageFlags src_stage_mask)
2661 {
2662 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2663 VK_PIPELINE_STAGE_TRANSFER_BIT |
2664 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2665 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2666 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2667 }
2668
2669 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2670 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2671 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2672 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2673 VK_PIPELINE_STAGE_TRANSFER_BIT |
2674 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2675 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2676 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2677 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2678 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2679 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2680 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2681 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2682 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2683 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2684 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2685 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2686 }
2687 }
2688
2689 static enum radv_cmd_flush_bits
2690 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2691 VkAccessFlags src_flags,
2692 struct radv_image *image)
2693 {
2694 bool flush_CB_meta = true, flush_DB_meta = true;
2695 enum radv_cmd_flush_bits flush_bits = 0;
2696 uint32_t b;
2697
2698 if (image) {
2699 if (!radv_image_has_CB_metadata(image))
2700 flush_CB_meta = false;
2701 if (!radv_image_has_htile(image))
2702 flush_DB_meta = false;
2703 }
2704
2705 for_each_bit(b, src_flags) {
2706 switch ((VkAccessFlagBits)(1 << b)) {
2707 case VK_ACCESS_SHADER_WRITE_BIT:
2708 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2709 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2710 flush_bits |= RADV_CMD_FLAG_WB_L2;
2711 break;
2712 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2713 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2714 if (flush_CB_meta)
2715 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2716 break;
2717 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2718 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2719 if (flush_DB_meta)
2720 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2721 break;
2722 case VK_ACCESS_TRANSFER_WRITE_BIT:
2723 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2724 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2725 RADV_CMD_FLAG_INV_L2;
2726
2727 if (flush_CB_meta)
2728 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2729 if (flush_DB_meta)
2730 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2731 break;
2732 default:
2733 break;
2734 }
2735 }
2736 return flush_bits;
2737 }
2738
2739 static enum radv_cmd_flush_bits
2740 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2741 VkAccessFlags dst_flags,
2742 struct radv_image *image)
2743 {
2744 bool flush_CB_meta = true, flush_DB_meta = true;
2745 enum radv_cmd_flush_bits flush_bits = 0;
2746 bool flush_CB = true, flush_DB = true;
2747 bool image_is_coherent = false;
2748 uint32_t b;
2749
2750 if (image) {
2751 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2752 flush_CB = false;
2753 flush_DB = false;
2754 }
2755
2756 if (!radv_image_has_CB_metadata(image))
2757 flush_CB_meta = false;
2758 if (!radv_image_has_htile(image))
2759 flush_DB_meta = false;
2760
2761 /* TODO: implement shader coherent for GFX10 */
2762
2763 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
2764 if (image->info.samples == 1 &&
2765 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2766 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2767 !vk_format_is_stencil(image->vk_format)) {
2768 /* Single-sample color and single-sample depth
2769 * (not stencil) are coherent with shaders on
2770 * GFX9.
2771 */
2772 image_is_coherent = true;
2773 }
2774 }
2775 }
2776
2777 for_each_bit(b, dst_flags) {
2778 switch ((VkAccessFlagBits)(1 << b)) {
2779 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2780 case VK_ACCESS_INDEX_READ_BIT:
2781 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2782 break;
2783 case VK_ACCESS_UNIFORM_READ_BIT:
2784 flush_bits |= RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_SCACHE;
2785 break;
2786 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2787 case VK_ACCESS_TRANSFER_READ_BIT:
2788 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2789 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
2790 RADV_CMD_FLAG_INV_L2;
2791 break;
2792 case VK_ACCESS_SHADER_READ_BIT:
2793 flush_bits |= RADV_CMD_FLAG_INV_VCACHE;
2794
2795 if (!image_is_coherent)
2796 flush_bits |= RADV_CMD_FLAG_INV_L2;
2797 break;
2798 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2799 if (flush_CB)
2800 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2801 if (flush_CB_meta)
2802 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2803 break;
2804 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2805 if (flush_DB)
2806 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2807 if (flush_DB_meta)
2808 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2809 break;
2810 default:
2811 break;
2812 }
2813 }
2814 return flush_bits;
2815 }
2816
2817 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2818 const struct radv_subpass_barrier *barrier)
2819 {
2820 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2821 NULL);
2822 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2823 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2824 NULL);
2825 }
2826
2827 uint32_t
2828 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
2829 {
2830 struct radv_cmd_state *state = &cmd_buffer->state;
2831 uint32_t subpass_id = state->subpass - state->pass->subpasses;
2832
2833 /* The id of this subpass shouldn't exceed the number of subpasses in
2834 * this render pass minus 1.
2835 */
2836 assert(subpass_id < state->pass->subpass_count);
2837 return subpass_id;
2838 }
2839
2840 static struct radv_sample_locations_state *
2841 radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer,
2842 uint32_t att_idx,
2843 bool begin_subpass)
2844 {
2845 struct radv_cmd_state *state = &cmd_buffer->state;
2846 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
2847 struct radv_image_view *view = state->attachments[att_idx].iview;
2848
2849 if (view->image->info.samples == 1)
2850 return NULL;
2851
2852 if (state->pass->attachments[att_idx].first_subpass_idx == subpass_id) {
2853 /* Return the initial sample locations if this is the initial
2854 * layout transition of the given subpass attachemnt.
2855 */
2856 if (state->attachments[att_idx].sample_location.count > 0)
2857 return &state->attachments[att_idx].sample_location;
2858 } else {
2859 /* Otherwise return the subpass sample locations if defined. */
2860 if (state->subpass_sample_locs) {
2861 /* Because the driver sets the current subpass before
2862 * initial layout transitions, we should use the sample
2863 * locations from the previous subpass to avoid an
2864 * off-by-one problem. Otherwise, use the sample
2865 * locations for the current subpass for final layout
2866 * transitions.
2867 */
2868 if (begin_subpass)
2869 subpass_id--;
2870
2871 for (uint32_t i = 0; i < state->num_subpass_sample_locs; i++) {
2872 if (state->subpass_sample_locs[i].subpass_idx == subpass_id)
2873 return &state->subpass_sample_locs[i].sample_location;
2874 }
2875 }
2876 }
2877
2878 return NULL;
2879 }
2880
2881 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2882 struct radv_subpass_attachment att,
2883 bool begin_subpass)
2884 {
2885 unsigned idx = att.attachment;
2886 struct radv_image_view *view = cmd_buffer->state.attachments[idx].iview;
2887 struct radv_sample_locations_state *sample_locs;
2888 VkImageSubresourceRange range;
2889 range.aspectMask = 0;
2890 range.baseMipLevel = view->base_mip;
2891 range.levelCount = 1;
2892 range.baseArrayLayer = view->base_layer;
2893 range.layerCount = cmd_buffer->state.framebuffer->layers;
2894
2895 if (cmd_buffer->state.subpass->view_mask) {
2896 /* If the current subpass uses multiview, the driver might have
2897 * performed a fast color/depth clear to the whole image
2898 * (including all layers). To make sure the driver will
2899 * decompress the image correctly (if needed), we have to
2900 * account for the "real" number of layers. If the view mask is
2901 * sparse, this will decompress more layers than needed.
2902 */
2903 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
2904 }
2905
2906 /* Get the subpass sample locations for the given attachment, if NULL
2907 * is returned the driver will use the default HW locations.
2908 */
2909 sample_locs = radv_get_attachment_sample_locations(cmd_buffer, idx,
2910 begin_subpass);
2911
2912 radv_handle_image_transition(cmd_buffer,
2913 view->image,
2914 cmd_buffer->state.attachments[idx].current_layout,
2915 cmd_buffer->state.attachments[idx].current_in_render_loop,
2916 att.layout, att.in_render_loop,
2917 0, 0, &range, sample_locs);
2918
2919 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2920 cmd_buffer->state.attachments[idx].current_in_render_loop = att.in_render_loop;
2921
2922
2923 }
2924
2925 void
2926 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2927 const struct radv_subpass *subpass)
2928 {
2929 cmd_buffer->state.subpass = subpass;
2930
2931 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2932 }
2933
2934 static VkResult
2935 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
2936 struct radv_render_pass *pass,
2937 const VkRenderPassBeginInfo *info)
2938 {
2939 const struct VkRenderPassSampleLocationsBeginInfoEXT *sample_locs =
2940 vk_find_struct_const(info->pNext,
2941 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT);
2942 struct radv_cmd_state *state = &cmd_buffer->state;
2943
2944 if (!sample_locs) {
2945 state->subpass_sample_locs = NULL;
2946 return VK_SUCCESS;
2947 }
2948
2949 for (uint32_t i = 0; i < sample_locs->attachmentInitialSampleLocationsCount; i++) {
2950 const VkAttachmentSampleLocationsEXT *att_sample_locs =
2951 &sample_locs->pAttachmentInitialSampleLocations[i];
2952 uint32_t att_idx = att_sample_locs->attachmentIndex;
2953 struct radv_image *image = cmd_buffer->state.attachments[att_idx].iview->image;
2954
2955 assert(vk_format_is_depth_or_stencil(image->vk_format));
2956
2957 /* From the Vulkan spec 1.1.108:
2958 *
2959 * "If the image referenced by the framebuffer attachment at
2960 * index attachmentIndex was not created with
2961 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
2962 * then the values specified in sampleLocationsInfo are
2963 * ignored."
2964 */
2965 if (!(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT))
2966 continue;
2967
2968 const VkSampleLocationsInfoEXT *sample_locs_info =
2969 &att_sample_locs->sampleLocationsInfo;
2970
2971 state->attachments[att_idx].sample_location.per_pixel =
2972 sample_locs_info->sampleLocationsPerPixel;
2973 state->attachments[att_idx].sample_location.grid_size =
2974 sample_locs_info->sampleLocationGridSize;
2975 state->attachments[att_idx].sample_location.count =
2976 sample_locs_info->sampleLocationsCount;
2977 typed_memcpy(&state->attachments[att_idx].sample_location.locations[0],
2978 sample_locs_info->pSampleLocations,
2979 sample_locs_info->sampleLocationsCount);
2980 }
2981
2982 state->subpass_sample_locs = vk_alloc(&cmd_buffer->pool->alloc,
2983 sample_locs->postSubpassSampleLocationsCount *
2984 sizeof(state->subpass_sample_locs[0]),
2985 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2986 if (state->subpass_sample_locs == NULL) {
2987 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2988 return cmd_buffer->record_result;
2989 }
2990
2991 state->num_subpass_sample_locs = sample_locs->postSubpassSampleLocationsCount;
2992
2993 for (uint32_t i = 0; i < sample_locs->postSubpassSampleLocationsCount; i++) {
2994 const VkSubpassSampleLocationsEXT *subpass_sample_locs_info =
2995 &sample_locs->pPostSubpassSampleLocations[i];
2996 const VkSampleLocationsInfoEXT *sample_locs_info =
2997 &subpass_sample_locs_info->sampleLocationsInfo;
2998
2999 state->subpass_sample_locs[i].subpass_idx =
3000 subpass_sample_locs_info->subpassIndex;
3001 state->subpass_sample_locs[i].sample_location.per_pixel =
3002 sample_locs_info->sampleLocationsPerPixel;
3003 state->subpass_sample_locs[i].sample_location.grid_size =
3004 sample_locs_info->sampleLocationGridSize;
3005 state->subpass_sample_locs[i].sample_location.count =
3006 sample_locs_info->sampleLocationsCount;
3007 typed_memcpy(&state->subpass_sample_locs[i].sample_location.locations[0],
3008 sample_locs_info->pSampleLocations,
3009 sample_locs_info->sampleLocationsCount);
3010 }
3011
3012 return VK_SUCCESS;
3013 }
3014
3015 static VkResult
3016 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
3017 struct radv_render_pass *pass,
3018 const VkRenderPassBeginInfo *info)
3019 {
3020 struct radv_cmd_state *state = &cmd_buffer->state;
3021 const struct VkRenderPassAttachmentBeginInfoKHR *attachment_info = NULL;
3022
3023 if (info) {
3024 attachment_info = vk_find_struct_const(info->pNext,
3025 RENDER_PASS_ATTACHMENT_BEGIN_INFO_KHR);
3026 }
3027
3028
3029 if (pass->attachment_count == 0) {
3030 state->attachments = NULL;
3031 return VK_SUCCESS;
3032 }
3033
3034 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
3035 pass->attachment_count *
3036 sizeof(state->attachments[0]),
3037 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3038 if (state->attachments == NULL) {
3039 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3040 return cmd_buffer->record_result;
3041 }
3042
3043 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
3044 struct radv_render_pass_attachment *att = &pass->attachments[i];
3045 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
3046 VkImageAspectFlags clear_aspects = 0;
3047
3048 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
3049 /* color attachment */
3050 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3051 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
3052 }
3053 } else {
3054 /* depthstencil attachment */
3055 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
3056 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3057 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
3058 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3059 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
3060 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3061 }
3062 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3063 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3064 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3065 }
3066 }
3067
3068 state->attachments[i].pending_clear_aspects = clear_aspects;
3069 state->attachments[i].cleared_views = 0;
3070 if (clear_aspects && info) {
3071 assert(info->clearValueCount > i);
3072 state->attachments[i].clear_value = info->pClearValues[i];
3073 }
3074
3075 state->attachments[i].current_layout = att->initial_layout;
3076 state->attachments[i].sample_location.count = 0;
3077
3078 struct radv_image_view *iview;
3079 if (attachment_info && attachment_info->attachmentCount > i) {
3080 iview = radv_image_view_from_handle(attachment_info->pAttachments[i]);
3081 } else {
3082 iview = state->framebuffer->attachments[i];
3083 }
3084
3085 state->attachments[i].iview = iview;
3086 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3087 radv_initialise_ds_surface(cmd_buffer->device, &state->attachments[i].ds, iview);
3088 } else {
3089 radv_initialise_color_surface(cmd_buffer->device, &state->attachments[i].cb, iview);
3090 }
3091 }
3092
3093 return VK_SUCCESS;
3094 }
3095
3096 VkResult radv_AllocateCommandBuffers(
3097 VkDevice _device,
3098 const VkCommandBufferAllocateInfo *pAllocateInfo,
3099 VkCommandBuffer *pCommandBuffers)
3100 {
3101 RADV_FROM_HANDLE(radv_device, device, _device);
3102 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
3103
3104 VkResult result = VK_SUCCESS;
3105 uint32_t i;
3106
3107 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
3108
3109 if (!list_empty(&pool->free_cmd_buffers)) {
3110 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
3111
3112 list_del(&cmd_buffer->pool_link);
3113 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
3114
3115 result = radv_reset_cmd_buffer(cmd_buffer);
3116 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
3117 cmd_buffer->level = pAllocateInfo->level;
3118
3119 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
3120 } else {
3121 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
3122 &pCommandBuffers[i]);
3123 }
3124 if (result != VK_SUCCESS)
3125 break;
3126 }
3127
3128 if (result != VK_SUCCESS) {
3129 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
3130 i, pCommandBuffers);
3131
3132 /* From the Vulkan 1.0.66 spec:
3133 *
3134 * "vkAllocateCommandBuffers can be used to create multiple
3135 * command buffers. If the creation of any of those command
3136 * buffers fails, the implementation must destroy all
3137 * successfully created command buffer objects from this
3138 * command, set all entries of the pCommandBuffers array to
3139 * NULL and return the error."
3140 */
3141 memset(pCommandBuffers, 0,
3142 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
3143 }
3144
3145 return result;
3146 }
3147
3148 void radv_FreeCommandBuffers(
3149 VkDevice device,
3150 VkCommandPool commandPool,
3151 uint32_t commandBufferCount,
3152 const VkCommandBuffer *pCommandBuffers)
3153 {
3154 for (uint32_t i = 0; i < commandBufferCount; i++) {
3155 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
3156
3157 if (cmd_buffer) {
3158 if (cmd_buffer->pool) {
3159 list_del(&cmd_buffer->pool_link);
3160 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
3161 } else
3162 radv_cmd_buffer_destroy(cmd_buffer);
3163
3164 }
3165 }
3166 }
3167
3168 VkResult radv_ResetCommandBuffer(
3169 VkCommandBuffer commandBuffer,
3170 VkCommandBufferResetFlags flags)
3171 {
3172 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3173 return radv_reset_cmd_buffer(cmd_buffer);
3174 }
3175
3176 VkResult radv_BeginCommandBuffer(
3177 VkCommandBuffer commandBuffer,
3178 const VkCommandBufferBeginInfo *pBeginInfo)
3179 {
3180 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3181 VkResult result = VK_SUCCESS;
3182
3183 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
3184 /* If the command buffer has already been resetted with
3185 * vkResetCommandBuffer, no need to do it again.
3186 */
3187 result = radv_reset_cmd_buffer(cmd_buffer);
3188 if (result != VK_SUCCESS)
3189 return result;
3190 }
3191
3192 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
3193 cmd_buffer->state.last_primitive_reset_en = -1;
3194 cmd_buffer->state.last_index_type = -1;
3195 cmd_buffer->state.last_num_instances = -1;
3196 cmd_buffer->state.last_vertex_offset = -1;
3197 cmd_buffer->state.last_first_instance = -1;
3198 cmd_buffer->state.predication_type = -1;
3199 cmd_buffer->usage_flags = pBeginInfo->flags;
3200
3201 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
3202 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
3203 assert(pBeginInfo->pInheritanceInfo);
3204 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
3205 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
3206
3207 struct radv_subpass *subpass =
3208 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
3209
3210 if (cmd_buffer->state.framebuffer) {
3211 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
3212 if (result != VK_SUCCESS)
3213 return result;
3214 }
3215
3216 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3217 }
3218
3219 if (unlikely(cmd_buffer->device->trace_bo)) {
3220 struct radv_device *device = cmd_buffer->device;
3221
3222 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
3223 device->trace_bo);
3224
3225 radv_cmd_buffer_trace_emit(cmd_buffer);
3226 }
3227
3228 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
3229
3230 return result;
3231 }
3232
3233 void radv_CmdBindVertexBuffers(
3234 VkCommandBuffer commandBuffer,
3235 uint32_t firstBinding,
3236 uint32_t bindingCount,
3237 const VkBuffer* pBuffers,
3238 const VkDeviceSize* pOffsets)
3239 {
3240 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3241 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
3242 bool changed = false;
3243
3244 /* We have to defer setting up vertex buffer since we need the buffer
3245 * stride from the pipeline. */
3246
3247 assert(firstBinding + bindingCount <= MAX_VBS);
3248 for (uint32_t i = 0; i < bindingCount; i++) {
3249 uint32_t idx = firstBinding + i;
3250
3251 if (!changed &&
3252 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
3253 vb[idx].offset != pOffsets[i])) {
3254 changed = true;
3255 }
3256
3257 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
3258 vb[idx].offset = pOffsets[i];
3259
3260 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3261 vb[idx].buffer->bo);
3262 }
3263
3264 if (!changed) {
3265 /* No state changes. */
3266 return;
3267 }
3268
3269 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
3270 }
3271
3272 static uint32_t
3273 vk_to_index_type(VkIndexType type)
3274 {
3275 switch (type) {
3276 case VK_INDEX_TYPE_UINT8_EXT:
3277 return V_028A7C_VGT_INDEX_8;
3278 case VK_INDEX_TYPE_UINT16:
3279 return V_028A7C_VGT_INDEX_16;
3280 case VK_INDEX_TYPE_UINT32:
3281 return V_028A7C_VGT_INDEX_32;
3282 default:
3283 unreachable("invalid index type");
3284 }
3285 }
3286
3287 static uint32_t
3288 radv_get_vgt_index_size(uint32_t type)
3289 {
3290 switch (type) {
3291 case V_028A7C_VGT_INDEX_8:
3292 return 1;
3293 case V_028A7C_VGT_INDEX_16:
3294 return 2;
3295 case V_028A7C_VGT_INDEX_32:
3296 return 4;
3297 default:
3298 unreachable("invalid index type");
3299 }
3300 }
3301
3302 void radv_CmdBindIndexBuffer(
3303 VkCommandBuffer commandBuffer,
3304 VkBuffer buffer,
3305 VkDeviceSize offset,
3306 VkIndexType indexType)
3307 {
3308 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3309 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
3310
3311 if (cmd_buffer->state.index_buffer == index_buffer &&
3312 cmd_buffer->state.index_offset == offset &&
3313 cmd_buffer->state.index_type == indexType) {
3314 /* No state changes. */
3315 return;
3316 }
3317
3318 cmd_buffer->state.index_buffer = index_buffer;
3319 cmd_buffer->state.index_offset = offset;
3320 cmd_buffer->state.index_type = vk_to_index_type(indexType);
3321 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
3322 cmd_buffer->state.index_va += index_buffer->offset + offset;
3323
3324 int index_size = radv_get_vgt_index_size(indexType);
3325 cmd_buffer->state.max_index_count = (index_buffer->size - offset) / index_size;
3326 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3327 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
3328 }
3329
3330
3331 static void
3332 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3333 VkPipelineBindPoint bind_point,
3334 struct radv_descriptor_set *set, unsigned idx)
3335 {
3336 struct radeon_winsys *ws = cmd_buffer->device->ws;
3337
3338 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
3339
3340 assert(set);
3341 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
3342
3343 if (!cmd_buffer->device->use_global_bo_list) {
3344 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3345 if (set->descriptors[j])
3346 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
3347 }
3348
3349 if(set->bo)
3350 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
3351 }
3352
3353 void radv_CmdBindDescriptorSets(
3354 VkCommandBuffer commandBuffer,
3355 VkPipelineBindPoint pipelineBindPoint,
3356 VkPipelineLayout _layout,
3357 uint32_t firstSet,
3358 uint32_t descriptorSetCount,
3359 const VkDescriptorSet* pDescriptorSets,
3360 uint32_t dynamicOffsetCount,
3361 const uint32_t* pDynamicOffsets)
3362 {
3363 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3364 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3365 unsigned dyn_idx = 0;
3366
3367 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
3368 struct radv_descriptor_state *descriptors_state =
3369 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3370
3371 for (unsigned i = 0; i < descriptorSetCount; ++i) {
3372 unsigned idx = i + firstSet;
3373 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
3374
3375 /* If the set is already bound we only need to update the
3376 * (potentially changed) dynamic offsets. */
3377 if (descriptors_state->sets[idx] != set ||
3378 !(descriptors_state->valid & (1u << idx))) {
3379 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
3380 }
3381
3382 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
3383 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
3384 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
3385 assert(dyn_idx < dynamicOffsetCount);
3386
3387 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
3388 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
3389 dst[0] = va;
3390 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
3391 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
3392 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3393 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3394 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3395 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3396
3397 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
3398 dst[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3399 S_008F0C_OOB_SELECT(3) |
3400 S_008F0C_RESOURCE_LEVEL(1);
3401 } else {
3402 dst[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3403 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3404 }
3405
3406 cmd_buffer->push_constant_stages |=
3407 set->layout->dynamic_shader_stages;
3408 }
3409 }
3410 }
3411
3412 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3413 struct radv_descriptor_set *set,
3414 struct radv_descriptor_set_layout *layout,
3415 VkPipelineBindPoint bind_point)
3416 {
3417 struct radv_descriptor_state *descriptors_state =
3418 radv_get_descriptors_state(cmd_buffer, bind_point);
3419 set->size = layout->size;
3420 set->layout = layout;
3421
3422 if (descriptors_state->push_set.capacity < set->size) {
3423 size_t new_size = MAX2(set->size, 1024);
3424 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
3425 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
3426
3427 free(set->mapped_ptr);
3428 set->mapped_ptr = malloc(new_size);
3429
3430 if (!set->mapped_ptr) {
3431 descriptors_state->push_set.capacity = 0;
3432 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3433 return false;
3434 }
3435
3436 descriptors_state->push_set.capacity = new_size;
3437 }
3438
3439 return true;
3440 }
3441
3442 void radv_meta_push_descriptor_set(
3443 struct radv_cmd_buffer* cmd_buffer,
3444 VkPipelineBindPoint pipelineBindPoint,
3445 VkPipelineLayout _layout,
3446 uint32_t set,
3447 uint32_t descriptorWriteCount,
3448 const VkWriteDescriptorSet* pDescriptorWrites)
3449 {
3450 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3451 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
3452 unsigned bo_offset;
3453
3454 assert(set == 0);
3455 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3456
3457 push_set->size = layout->set[set].layout->size;
3458 push_set->layout = layout->set[set].layout;
3459
3460 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
3461 &bo_offset,
3462 (void**) &push_set->mapped_ptr))
3463 return;
3464
3465 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
3466 push_set->va += bo_offset;
3467
3468 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3469 radv_descriptor_set_to_handle(push_set),
3470 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3471
3472 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3473 }
3474
3475 void radv_CmdPushDescriptorSetKHR(
3476 VkCommandBuffer commandBuffer,
3477 VkPipelineBindPoint pipelineBindPoint,
3478 VkPipelineLayout _layout,
3479 uint32_t set,
3480 uint32_t descriptorWriteCount,
3481 const VkWriteDescriptorSet* pDescriptorWrites)
3482 {
3483 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3484 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3485 struct radv_descriptor_state *descriptors_state =
3486 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3487 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3488
3489 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3490
3491 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3492 layout->set[set].layout,
3493 pipelineBindPoint))
3494 return;
3495
3496 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3497 * because it is invalid, according to Vulkan spec.
3498 */
3499 for (int i = 0; i < descriptorWriteCount; i++) {
3500 ASSERTED const VkWriteDescriptorSet *writeset = &pDescriptorWrites[i];
3501 assert(writeset->descriptorType != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT);
3502 }
3503
3504 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3505 radv_descriptor_set_to_handle(push_set),
3506 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3507
3508 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3509 descriptors_state->push_dirty = true;
3510 }
3511
3512 void radv_CmdPushDescriptorSetWithTemplateKHR(
3513 VkCommandBuffer commandBuffer,
3514 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
3515 VkPipelineLayout _layout,
3516 uint32_t set,
3517 const void* pData)
3518 {
3519 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3520 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3521 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
3522 struct radv_descriptor_state *descriptors_state =
3523 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
3524 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3525
3526 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3527
3528 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3529 layout->set[set].layout,
3530 templ->bind_point))
3531 return;
3532
3533 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
3534 descriptorUpdateTemplate, pData);
3535
3536 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
3537 descriptors_state->push_dirty = true;
3538 }
3539
3540 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
3541 VkPipelineLayout layout,
3542 VkShaderStageFlags stageFlags,
3543 uint32_t offset,
3544 uint32_t size,
3545 const void* pValues)
3546 {
3547 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3548 memcpy(cmd_buffer->push_constants + offset, pValues, size);
3549 cmd_buffer->push_constant_stages |= stageFlags;
3550 }
3551
3552 VkResult radv_EndCommandBuffer(
3553 VkCommandBuffer commandBuffer)
3554 {
3555 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3556
3557 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
3558 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6)
3559 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WB_L2;
3560
3561 /* Make sure to sync all pending active queries at the end of
3562 * command buffer.
3563 */
3564 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
3565
3566 si_emit_cache_flush(cmd_buffer);
3567 }
3568
3569 /* Make sure CP DMA is idle at the end of IBs because the kernel
3570 * doesn't wait for it.
3571 */
3572 si_cp_dma_wait_for_idle(cmd_buffer);
3573
3574 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3575 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
3576
3577 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
3578 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3579
3580 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
3581
3582 return cmd_buffer->record_result;
3583 }
3584
3585 static void
3586 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
3587 {
3588 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3589
3590 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
3591 return;
3592
3593 assert(!pipeline->ctx_cs.cdw);
3594
3595 cmd_buffer->state.emitted_compute_pipeline = pipeline;
3596
3597 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
3598 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
3599
3600 cmd_buffer->compute_scratch_size_needed =
3601 MAX2(cmd_buffer->compute_scratch_size_needed,
3602 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
3603
3604 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3605 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
3606
3607 if (unlikely(cmd_buffer->device->trace_bo))
3608 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
3609 }
3610
3611 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
3612 VkPipelineBindPoint bind_point)
3613 {
3614 struct radv_descriptor_state *descriptors_state =
3615 radv_get_descriptors_state(cmd_buffer, bind_point);
3616
3617 descriptors_state->dirty |= descriptors_state->valid;
3618 }
3619
3620 void radv_CmdBindPipeline(
3621 VkCommandBuffer commandBuffer,
3622 VkPipelineBindPoint pipelineBindPoint,
3623 VkPipeline _pipeline)
3624 {
3625 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3626 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
3627
3628 switch (pipelineBindPoint) {
3629 case VK_PIPELINE_BIND_POINT_COMPUTE:
3630 if (cmd_buffer->state.compute_pipeline == pipeline)
3631 return;
3632 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3633
3634 cmd_buffer->state.compute_pipeline = pipeline;
3635 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
3636 break;
3637 case VK_PIPELINE_BIND_POINT_GRAPHICS:
3638 if (cmd_buffer->state.pipeline == pipeline)
3639 return;
3640 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3641
3642 cmd_buffer->state.pipeline = pipeline;
3643 if (!pipeline)
3644 break;
3645
3646 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
3647 cmd_buffer->push_constant_stages |= pipeline->active_stages;
3648
3649 /* the new vertex shader might not have the same user regs */
3650 cmd_buffer->state.last_first_instance = -1;
3651 cmd_buffer->state.last_vertex_offset = -1;
3652
3653 /* Prefetch all pipeline shaders at first draw time. */
3654 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
3655
3656 if ((cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI10 ||
3657 cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI12 ||
3658 cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI14) &&
3659 cmd_buffer->state.emitted_pipeline &&
3660 radv_pipeline_has_ngg(cmd_buffer->state.emitted_pipeline) &&
3661 !radv_pipeline_has_ngg(cmd_buffer->state.pipeline)) {
3662 /* Transitioning from NGG to legacy GS requires
3663 * VGT_FLUSH on Navi10-14. VGT_FLUSH is also emitted
3664 * at the beginning of IBs when legacy GS ring pointers
3665 * are set.
3666 */
3667 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
3668 }
3669
3670 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
3671 radv_bind_streamout_state(cmd_buffer, pipeline);
3672
3673 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
3674 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
3675 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
3676 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
3677
3678 if (radv_pipeline_has_tess(pipeline))
3679 cmd_buffer->tess_rings_needed = true;
3680 break;
3681 default:
3682 assert(!"invalid bind point");
3683 break;
3684 }
3685 }
3686
3687 void radv_CmdSetViewport(
3688 VkCommandBuffer commandBuffer,
3689 uint32_t firstViewport,
3690 uint32_t viewportCount,
3691 const VkViewport* pViewports)
3692 {
3693 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3694 struct radv_cmd_state *state = &cmd_buffer->state;
3695 ASSERTED const uint32_t total_count = firstViewport + viewportCount;
3696
3697 assert(firstViewport < MAX_VIEWPORTS);
3698 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
3699
3700 if (!memcmp(state->dynamic.viewport.viewports + firstViewport,
3701 pViewports, viewportCount * sizeof(*pViewports))) {
3702 return;
3703 }
3704
3705 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
3706 viewportCount * sizeof(*pViewports));
3707
3708 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
3709 }
3710
3711 void radv_CmdSetScissor(
3712 VkCommandBuffer commandBuffer,
3713 uint32_t firstScissor,
3714 uint32_t scissorCount,
3715 const VkRect2D* pScissors)
3716 {
3717 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3718 struct radv_cmd_state *state = &cmd_buffer->state;
3719 ASSERTED const uint32_t total_count = firstScissor + scissorCount;
3720
3721 assert(firstScissor < MAX_SCISSORS);
3722 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
3723
3724 if (!memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
3725 scissorCount * sizeof(*pScissors))) {
3726 return;
3727 }
3728
3729 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
3730 scissorCount * sizeof(*pScissors));
3731
3732 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
3733 }
3734
3735 void radv_CmdSetLineWidth(
3736 VkCommandBuffer commandBuffer,
3737 float lineWidth)
3738 {
3739 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3740
3741 if (cmd_buffer->state.dynamic.line_width == lineWidth)
3742 return;
3743
3744 cmd_buffer->state.dynamic.line_width = lineWidth;
3745 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
3746 }
3747
3748 void radv_CmdSetDepthBias(
3749 VkCommandBuffer commandBuffer,
3750 float depthBiasConstantFactor,
3751 float depthBiasClamp,
3752 float depthBiasSlopeFactor)
3753 {
3754 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3755 struct radv_cmd_state *state = &cmd_buffer->state;
3756
3757 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
3758 state->dynamic.depth_bias.clamp == depthBiasClamp &&
3759 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
3760 return;
3761 }
3762
3763 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
3764 state->dynamic.depth_bias.clamp = depthBiasClamp;
3765 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
3766
3767 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
3768 }
3769
3770 void radv_CmdSetBlendConstants(
3771 VkCommandBuffer commandBuffer,
3772 const float blendConstants[4])
3773 {
3774 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3775 struct radv_cmd_state *state = &cmd_buffer->state;
3776
3777 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
3778 return;
3779
3780 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
3781
3782 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
3783 }
3784
3785 void radv_CmdSetDepthBounds(
3786 VkCommandBuffer commandBuffer,
3787 float minDepthBounds,
3788 float maxDepthBounds)
3789 {
3790 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3791 struct radv_cmd_state *state = &cmd_buffer->state;
3792
3793 if (state->dynamic.depth_bounds.min == minDepthBounds &&
3794 state->dynamic.depth_bounds.max == maxDepthBounds) {
3795 return;
3796 }
3797
3798 state->dynamic.depth_bounds.min = minDepthBounds;
3799 state->dynamic.depth_bounds.max = maxDepthBounds;
3800
3801 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
3802 }
3803
3804 void radv_CmdSetStencilCompareMask(
3805 VkCommandBuffer commandBuffer,
3806 VkStencilFaceFlags faceMask,
3807 uint32_t compareMask)
3808 {
3809 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3810 struct radv_cmd_state *state = &cmd_buffer->state;
3811 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
3812 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
3813
3814 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3815 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3816 return;
3817 }
3818
3819 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3820 state->dynamic.stencil_compare_mask.front = compareMask;
3821 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3822 state->dynamic.stencil_compare_mask.back = compareMask;
3823
3824 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
3825 }
3826
3827 void radv_CmdSetStencilWriteMask(
3828 VkCommandBuffer commandBuffer,
3829 VkStencilFaceFlags faceMask,
3830 uint32_t writeMask)
3831 {
3832 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3833 struct radv_cmd_state *state = &cmd_buffer->state;
3834 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
3835 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
3836
3837 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3838 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3839 return;
3840 }
3841
3842 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3843 state->dynamic.stencil_write_mask.front = writeMask;
3844 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3845 state->dynamic.stencil_write_mask.back = writeMask;
3846
3847 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
3848 }
3849
3850 void radv_CmdSetStencilReference(
3851 VkCommandBuffer commandBuffer,
3852 VkStencilFaceFlags faceMask,
3853 uint32_t reference)
3854 {
3855 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3856 struct radv_cmd_state *state = &cmd_buffer->state;
3857 bool front_same = state->dynamic.stencil_reference.front == reference;
3858 bool back_same = state->dynamic.stencil_reference.back == reference;
3859
3860 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3861 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3862 return;
3863 }
3864
3865 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3866 cmd_buffer->state.dynamic.stencil_reference.front = reference;
3867 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3868 cmd_buffer->state.dynamic.stencil_reference.back = reference;
3869
3870 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
3871 }
3872
3873 void radv_CmdSetDiscardRectangleEXT(
3874 VkCommandBuffer commandBuffer,
3875 uint32_t firstDiscardRectangle,
3876 uint32_t discardRectangleCount,
3877 const VkRect2D* pDiscardRectangles)
3878 {
3879 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3880 struct radv_cmd_state *state = &cmd_buffer->state;
3881 ASSERTED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
3882
3883 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
3884 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
3885
3886 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
3887 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
3888 return;
3889 }
3890
3891 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
3892 pDiscardRectangles, discardRectangleCount);
3893
3894 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
3895 }
3896
3897 void radv_CmdSetSampleLocationsEXT(
3898 VkCommandBuffer commandBuffer,
3899 const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
3900 {
3901 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3902 struct radv_cmd_state *state = &cmd_buffer->state;
3903
3904 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
3905
3906 state->dynamic.sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
3907 state->dynamic.sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
3908 state->dynamic.sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
3909 typed_memcpy(&state->dynamic.sample_location.locations[0],
3910 pSampleLocationsInfo->pSampleLocations,
3911 pSampleLocationsInfo->sampleLocationsCount);
3912
3913 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS;
3914 }
3915
3916 void radv_CmdExecuteCommands(
3917 VkCommandBuffer commandBuffer,
3918 uint32_t commandBufferCount,
3919 const VkCommandBuffer* pCmdBuffers)
3920 {
3921 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
3922
3923 assert(commandBufferCount > 0);
3924
3925 /* Emit pending flushes on primary prior to executing secondary */
3926 si_emit_cache_flush(primary);
3927
3928 for (uint32_t i = 0; i < commandBufferCount; i++) {
3929 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
3930
3931 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
3932 secondary->scratch_size_needed);
3933 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
3934 secondary->compute_scratch_size_needed);
3935
3936 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
3937 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
3938 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
3939 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
3940 if (secondary->tess_rings_needed)
3941 primary->tess_rings_needed = true;
3942 if (secondary->sample_positions_needed)
3943 primary->sample_positions_needed = true;
3944
3945 if (!secondary->state.framebuffer &&
3946 (primary->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)) {
3947 /* Emit the framebuffer state from primary if secondary
3948 * has been recorded without a framebuffer, otherwise
3949 * fast color/depth clears can't work.
3950 */
3951 radv_emit_framebuffer_state(primary);
3952 }
3953
3954 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
3955
3956
3957 /* When the secondary command buffer is compute only we don't
3958 * need to re-emit the current graphics pipeline.
3959 */
3960 if (secondary->state.emitted_pipeline) {
3961 primary->state.emitted_pipeline =
3962 secondary->state.emitted_pipeline;
3963 }
3964
3965 /* When the secondary command buffer is graphics only we don't
3966 * need to re-emit the current compute pipeline.
3967 */
3968 if (secondary->state.emitted_compute_pipeline) {
3969 primary->state.emitted_compute_pipeline =
3970 secondary->state.emitted_compute_pipeline;
3971 }
3972
3973 /* Only re-emit the draw packets when needed. */
3974 if (secondary->state.last_primitive_reset_en != -1) {
3975 primary->state.last_primitive_reset_en =
3976 secondary->state.last_primitive_reset_en;
3977 }
3978
3979 if (secondary->state.last_primitive_reset_index) {
3980 primary->state.last_primitive_reset_index =
3981 secondary->state.last_primitive_reset_index;
3982 }
3983
3984 if (secondary->state.last_ia_multi_vgt_param) {
3985 primary->state.last_ia_multi_vgt_param =
3986 secondary->state.last_ia_multi_vgt_param;
3987 }
3988
3989 primary->state.last_first_instance = secondary->state.last_first_instance;
3990 primary->state.last_num_instances = secondary->state.last_num_instances;
3991 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
3992
3993 if (secondary->state.last_index_type != -1) {
3994 primary->state.last_index_type =
3995 secondary->state.last_index_type;
3996 }
3997 }
3998
3999 /* After executing commands from secondary buffers we have to dirty
4000 * some states.
4001 */
4002 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
4003 RADV_CMD_DIRTY_INDEX_BUFFER |
4004 RADV_CMD_DIRTY_DYNAMIC_ALL;
4005 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
4006 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
4007 }
4008
4009 VkResult radv_CreateCommandPool(
4010 VkDevice _device,
4011 const VkCommandPoolCreateInfo* pCreateInfo,
4012 const VkAllocationCallbacks* pAllocator,
4013 VkCommandPool* pCmdPool)
4014 {
4015 RADV_FROM_HANDLE(radv_device, device, _device);
4016 struct radv_cmd_pool *pool;
4017
4018 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
4019 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4020 if (pool == NULL)
4021 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4022
4023 if (pAllocator)
4024 pool->alloc = *pAllocator;
4025 else
4026 pool->alloc = device->alloc;
4027
4028 list_inithead(&pool->cmd_buffers);
4029 list_inithead(&pool->free_cmd_buffers);
4030
4031 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
4032
4033 *pCmdPool = radv_cmd_pool_to_handle(pool);
4034
4035 return VK_SUCCESS;
4036
4037 }
4038
4039 void radv_DestroyCommandPool(
4040 VkDevice _device,
4041 VkCommandPool commandPool,
4042 const VkAllocationCallbacks* pAllocator)
4043 {
4044 RADV_FROM_HANDLE(radv_device, device, _device);
4045 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4046
4047 if (!pool)
4048 return;
4049
4050 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4051 &pool->cmd_buffers, pool_link) {
4052 radv_cmd_buffer_destroy(cmd_buffer);
4053 }
4054
4055 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4056 &pool->free_cmd_buffers, pool_link) {
4057 radv_cmd_buffer_destroy(cmd_buffer);
4058 }
4059
4060 vk_free2(&device->alloc, pAllocator, pool);
4061 }
4062
4063 VkResult radv_ResetCommandPool(
4064 VkDevice device,
4065 VkCommandPool commandPool,
4066 VkCommandPoolResetFlags flags)
4067 {
4068 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4069 VkResult result;
4070
4071 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
4072 &pool->cmd_buffers, pool_link) {
4073 result = radv_reset_cmd_buffer(cmd_buffer);
4074 if (result != VK_SUCCESS)
4075 return result;
4076 }
4077
4078 return VK_SUCCESS;
4079 }
4080
4081 void radv_TrimCommandPool(
4082 VkDevice device,
4083 VkCommandPool commandPool,
4084 VkCommandPoolTrimFlags flags)
4085 {
4086 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4087
4088 if (!pool)
4089 return;
4090
4091 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4092 &pool->free_cmd_buffers, pool_link) {
4093 radv_cmd_buffer_destroy(cmd_buffer);
4094 }
4095 }
4096
4097 static void
4098 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
4099 uint32_t subpass_id)
4100 {
4101 struct radv_cmd_state *state = &cmd_buffer->state;
4102 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
4103
4104 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
4105 cmd_buffer->cs, 4096);
4106
4107 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
4108
4109 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
4110
4111 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4112 const uint32_t a = subpass->attachments[i].attachment;
4113 if (a == VK_ATTACHMENT_UNUSED)
4114 continue;
4115
4116 radv_handle_subpass_image_transition(cmd_buffer,
4117 subpass->attachments[i],
4118 true);
4119 }
4120
4121 radv_cmd_buffer_clear_subpass(cmd_buffer);
4122
4123 assert(cmd_buffer->cs->cdw <= cdw_max);
4124 }
4125
4126 static void
4127 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
4128 {
4129 struct radv_cmd_state *state = &cmd_buffer->state;
4130 const struct radv_subpass *subpass = state->subpass;
4131 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
4132
4133 radv_cmd_buffer_resolve_subpass(cmd_buffer);
4134
4135 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4136 const uint32_t a = subpass->attachments[i].attachment;
4137 if (a == VK_ATTACHMENT_UNUSED)
4138 continue;
4139
4140 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
4141 continue;
4142
4143 VkImageLayout layout = state->pass->attachments[a].final_layout;
4144 struct radv_subpass_attachment att = { a, layout };
4145 radv_handle_subpass_image_transition(cmd_buffer, att, false);
4146 }
4147 }
4148
4149 void radv_CmdBeginRenderPass(
4150 VkCommandBuffer commandBuffer,
4151 const VkRenderPassBeginInfo* pRenderPassBegin,
4152 VkSubpassContents contents)
4153 {
4154 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4155 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
4156 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
4157 VkResult result;
4158
4159 cmd_buffer->state.framebuffer = framebuffer;
4160 cmd_buffer->state.pass = pass;
4161 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
4162
4163 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
4164 if (result != VK_SUCCESS)
4165 return;
4166
4167 result = radv_cmd_state_setup_sample_locations(cmd_buffer, pass, pRenderPassBegin);
4168 if (result != VK_SUCCESS)
4169 return;
4170
4171 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
4172 }
4173
4174 void radv_CmdBeginRenderPass2KHR(
4175 VkCommandBuffer commandBuffer,
4176 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
4177 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
4178 {
4179 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
4180 pSubpassBeginInfo->contents);
4181 }
4182
4183 void radv_CmdNextSubpass(
4184 VkCommandBuffer commandBuffer,
4185 VkSubpassContents contents)
4186 {
4187 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4188
4189 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
4190 radv_cmd_buffer_end_subpass(cmd_buffer);
4191 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
4192 }
4193
4194 void radv_CmdNextSubpass2KHR(
4195 VkCommandBuffer commandBuffer,
4196 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
4197 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4198 {
4199 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
4200 }
4201
4202 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
4203 {
4204 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
4205 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
4206 if (!radv_get_shader(pipeline, stage))
4207 continue;
4208
4209 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
4210 if (loc->sgpr_idx == -1)
4211 continue;
4212 uint32_t base_reg = pipeline->user_data_0[stage];
4213 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4214
4215 }
4216 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
4217 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
4218 if (loc->sgpr_idx != -1) {
4219 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
4220 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4221 }
4222 }
4223 }
4224
4225 static void
4226 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4227 uint32_t vertex_count,
4228 bool use_opaque)
4229 {
4230 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
4231 radeon_emit(cmd_buffer->cs, vertex_count);
4232 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
4233 S_0287F0_USE_OPAQUE(use_opaque));
4234 }
4235
4236 static void
4237 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
4238 uint64_t index_va,
4239 uint32_t index_count)
4240 {
4241 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
4242 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
4243 radeon_emit(cmd_buffer->cs, index_va);
4244 radeon_emit(cmd_buffer->cs, index_va >> 32);
4245 radeon_emit(cmd_buffer->cs, index_count);
4246 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
4247 }
4248
4249 static void
4250 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4251 bool indexed,
4252 uint32_t draw_count,
4253 uint64_t count_va,
4254 uint32_t stride)
4255 {
4256 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4257 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
4258 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
4259 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
4260 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
4261 bool predicating = cmd_buffer->state.predicating;
4262 assert(base_reg);
4263
4264 /* just reset draw state for vertex data */
4265 cmd_buffer->state.last_first_instance = -1;
4266 cmd_buffer->state.last_num_instances = -1;
4267 cmd_buffer->state.last_vertex_offset = -1;
4268
4269 if (draw_count == 1 && !count_va && !draw_id_enable) {
4270 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
4271 PKT3_DRAW_INDIRECT, 3, predicating));
4272 radeon_emit(cs, 0);
4273 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4274 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4275 radeon_emit(cs, di_src_sel);
4276 } else {
4277 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
4278 PKT3_DRAW_INDIRECT_MULTI,
4279 8, predicating));
4280 radeon_emit(cs, 0);
4281 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4282 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4283 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
4284 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
4285 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
4286 radeon_emit(cs, draw_count); /* count */
4287 radeon_emit(cs, count_va); /* count_addr */
4288 radeon_emit(cs, count_va >> 32);
4289 radeon_emit(cs, stride); /* stride */
4290 radeon_emit(cs, di_src_sel);
4291 }
4292 }
4293
4294 static void
4295 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
4296 const struct radv_draw_info *info)
4297 {
4298 struct radv_cmd_state *state = &cmd_buffer->state;
4299 struct radeon_winsys *ws = cmd_buffer->device->ws;
4300 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4301
4302 if (info->indirect) {
4303 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4304 uint64_t count_va = 0;
4305
4306 va += info->indirect->offset + info->indirect_offset;
4307
4308 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4309
4310 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
4311 radeon_emit(cs, 1);
4312 radeon_emit(cs, va);
4313 radeon_emit(cs, va >> 32);
4314
4315 if (info->count_buffer) {
4316 count_va = radv_buffer_get_va(info->count_buffer->bo);
4317 count_va += info->count_buffer->offset +
4318 info->count_buffer_offset;
4319
4320 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
4321 }
4322
4323 if (!state->subpass->view_mask) {
4324 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4325 info->indexed,
4326 info->count,
4327 count_va,
4328 info->stride);
4329 } else {
4330 unsigned i;
4331 for_each_bit(i, state->subpass->view_mask) {
4332 radv_emit_view_index(cmd_buffer, i);
4333
4334 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4335 info->indexed,
4336 info->count,
4337 count_va,
4338 info->stride);
4339 }
4340 }
4341 } else {
4342 assert(state->pipeline->graphics.vtx_base_sgpr);
4343
4344 if (info->vertex_offset != state->last_vertex_offset ||
4345 info->first_instance != state->last_first_instance) {
4346 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
4347 state->pipeline->graphics.vtx_emit_num);
4348
4349 radeon_emit(cs, info->vertex_offset);
4350 radeon_emit(cs, info->first_instance);
4351 if (state->pipeline->graphics.vtx_emit_num == 3)
4352 radeon_emit(cs, 0);
4353 state->last_first_instance = info->first_instance;
4354 state->last_vertex_offset = info->vertex_offset;
4355 }
4356
4357 if (state->last_num_instances != info->instance_count) {
4358 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
4359 radeon_emit(cs, info->instance_count);
4360 state->last_num_instances = info->instance_count;
4361 }
4362
4363 if (info->indexed) {
4364 int index_size = radv_get_vgt_index_size(state->index_type);
4365 uint64_t index_va;
4366
4367 /* Skip draw calls with 0-sized index buffers. They
4368 * cause a hang on some chips, like Navi10-14.
4369 */
4370 if (!cmd_buffer->state.max_index_count)
4371 return;
4372
4373 index_va = state->index_va;
4374 index_va += info->first_index * index_size;
4375
4376 if (!state->subpass->view_mask) {
4377 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4378 index_va,
4379 info->count);
4380 } else {
4381 unsigned i;
4382 for_each_bit(i, state->subpass->view_mask) {
4383 radv_emit_view_index(cmd_buffer, i);
4384
4385 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4386 index_va,
4387 info->count);
4388 }
4389 }
4390 } else {
4391 if (!state->subpass->view_mask) {
4392 radv_cs_emit_draw_packet(cmd_buffer,
4393 info->count,
4394 !!info->strmout_buffer);
4395 } else {
4396 unsigned i;
4397 for_each_bit(i, state->subpass->view_mask) {
4398 radv_emit_view_index(cmd_buffer, i);
4399
4400 radv_cs_emit_draw_packet(cmd_buffer,
4401 info->count,
4402 !!info->strmout_buffer);
4403 }
4404 }
4405 }
4406 }
4407 }
4408
4409 /*
4410 * Vega and raven have a bug which triggers if there are multiple context
4411 * register contexts active at the same time with different scissor values.
4412 *
4413 * There are two possible workarounds:
4414 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
4415 * there is only ever 1 active set of scissor values at the same time.
4416 *
4417 * 2) Whenever the hardware switches contexts we have to set the scissor
4418 * registers again even if it is a noop. That way the new context gets
4419 * the correct scissor values.
4420 *
4421 * This implements option 2. radv_need_late_scissor_emission needs to
4422 * return true on affected HW if radv_emit_all_graphics_states sets
4423 * any context registers.
4424 */
4425 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
4426 const struct radv_draw_info *info)
4427 {
4428 struct radv_cmd_state *state = &cmd_buffer->state;
4429
4430 if (!cmd_buffer->device->physical_device->has_scissor_bug)
4431 return false;
4432
4433 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
4434 return true;
4435
4436 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
4437
4438 /* Index, vertex and streamout buffers don't change context regs, and
4439 * pipeline is already handled.
4440 */
4441 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
4442 RADV_CMD_DIRTY_VERTEX_BUFFER |
4443 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
4444 RADV_CMD_DIRTY_PIPELINE);
4445
4446 if (cmd_buffer->state.dirty & used_states)
4447 return true;
4448
4449 uint32_t primitive_reset_index =
4450 radv_get_primitive_reset_index(cmd_buffer);
4451
4452 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
4453 primitive_reset_index != state->last_primitive_reset_index)
4454 return true;
4455
4456 return false;
4457 }
4458
4459 static void
4460 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
4461 const struct radv_draw_info *info)
4462 {
4463 bool late_scissor_emission;
4464
4465 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
4466 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
4467 radv_emit_rbplus_state(cmd_buffer);
4468
4469 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
4470 radv_emit_graphics_pipeline(cmd_buffer);
4471
4472 /* This should be before the cmd_buffer->state.dirty is cleared
4473 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4474 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4475 late_scissor_emission =
4476 radv_need_late_scissor_emission(cmd_buffer, info);
4477
4478 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
4479 radv_emit_framebuffer_state(cmd_buffer);
4480
4481 if (info->indexed) {
4482 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
4483 radv_emit_index_buffer(cmd_buffer);
4484 } else {
4485 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4486 * so the state must be re-emitted before the next indexed
4487 * draw.
4488 */
4489 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
4490 cmd_buffer->state.last_index_type = -1;
4491 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
4492 }
4493 }
4494
4495 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
4496
4497 radv_emit_draw_registers(cmd_buffer, info);
4498
4499 if (late_scissor_emission)
4500 radv_emit_scissor(cmd_buffer);
4501 }
4502
4503 static void
4504 radv_draw(struct radv_cmd_buffer *cmd_buffer,
4505 const struct radv_draw_info *info)
4506 {
4507 struct radeon_info *rad_info =
4508 &cmd_buffer->device->physical_device->rad_info;
4509 bool has_prefetch =
4510 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4511 bool pipeline_is_dirty =
4512 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
4513 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
4514
4515 ASSERTED unsigned cdw_max =
4516 radeon_check_space(cmd_buffer->device->ws,
4517 cmd_buffer->cs, 4096);
4518
4519 if (likely(!info->indirect)) {
4520 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4521 * no workaround for indirect draws, but we can at least skip
4522 * direct draws.
4523 */
4524 if (unlikely(!info->instance_count))
4525 return;
4526
4527 /* Handle count == 0. */
4528 if (unlikely(!info->count && !info->strmout_buffer))
4529 return;
4530 }
4531
4532 /* Use optimal packet order based on whether we need to sync the
4533 * pipeline.
4534 */
4535 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4536 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4537 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4538 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4539 /* If we have to wait for idle, set all states first, so that
4540 * all SET packets are processed in parallel with previous draw
4541 * calls. Then upload descriptors, set shader pointers, and
4542 * draw, and prefetch at the end. This ensures that the time
4543 * the CUs are idle is very short. (there are only SET_SH
4544 * packets between the wait and the draw)
4545 */
4546 radv_emit_all_graphics_states(cmd_buffer, info);
4547 si_emit_cache_flush(cmd_buffer);
4548 /* <-- CUs are idle here --> */
4549
4550 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4551
4552 radv_emit_draw_packets(cmd_buffer, info);
4553 /* <-- CUs are busy here --> */
4554
4555 /* Start prefetches after the draw has been started. Both will
4556 * run in parallel, but starting the draw first is more
4557 * important.
4558 */
4559 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4560 radv_emit_prefetch_L2(cmd_buffer,
4561 cmd_buffer->state.pipeline, false);
4562 }
4563 } else {
4564 /* If we don't wait for idle, start prefetches first, then set
4565 * states, and draw at the end.
4566 */
4567 si_emit_cache_flush(cmd_buffer);
4568
4569 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4570 /* Only prefetch the vertex shader and VBO descriptors
4571 * in order to start the draw as soon as possible.
4572 */
4573 radv_emit_prefetch_L2(cmd_buffer,
4574 cmd_buffer->state.pipeline, true);
4575 }
4576
4577 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4578
4579 radv_emit_all_graphics_states(cmd_buffer, info);
4580 radv_emit_draw_packets(cmd_buffer, info);
4581
4582 /* Prefetch the remaining shaders after the draw has been
4583 * started.
4584 */
4585 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4586 radv_emit_prefetch_L2(cmd_buffer,
4587 cmd_buffer->state.pipeline, false);
4588 }
4589 }
4590
4591 /* Workaround for a VGT hang when streamout is enabled.
4592 * It must be done after drawing.
4593 */
4594 if (cmd_buffer->state.streamout.streamout_enabled &&
4595 (rad_info->family == CHIP_HAWAII ||
4596 rad_info->family == CHIP_TONGA ||
4597 rad_info->family == CHIP_FIJI)) {
4598 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
4599 }
4600
4601 assert(cmd_buffer->cs->cdw <= cdw_max);
4602 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
4603 }
4604
4605 void radv_CmdDraw(
4606 VkCommandBuffer commandBuffer,
4607 uint32_t vertexCount,
4608 uint32_t instanceCount,
4609 uint32_t firstVertex,
4610 uint32_t firstInstance)
4611 {
4612 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4613 struct radv_draw_info info = {};
4614
4615 info.count = vertexCount;
4616 info.instance_count = instanceCount;
4617 info.first_instance = firstInstance;
4618 info.vertex_offset = firstVertex;
4619
4620 radv_draw(cmd_buffer, &info);
4621 }
4622
4623 void radv_CmdDrawIndexed(
4624 VkCommandBuffer commandBuffer,
4625 uint32_t indexCount,
4626 uint32_t instanceCount,
4627 uint32_t firstIndex,
4628 int32_t vertexOffset,
4629 uint32_t firstInstance)
4630 {
4631 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4632 struct radv_draw_info info = {};
4633
4634 info.indexed = true;
4635 info.count = indexCount;
4636 info.instance_count = instanceCount;
4637 info.first_index = firstIndex;
4638 info.vertex_offset = vertexOffset;
4639 info.first_instance = firstInstance;
4640
4641 radv_draw(cmd_buffer, &info);
4642 }
4643
4644 void radv_CmdDrawIndirect(
4645 VkCommandBuffer commandBuffer,
4646 VkBuffer _buffer,
4647 VkDeviceSize offset,
4648 uint32_t drawCount,
4649 uint32_t stride)
4650 {
4651 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4652 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4653 struct radv_draw_info info = {};
4654
4655 info.count = drawCount;
4656 info.indirect = buffer;
4657 info.indirect_offset = offset;
4658 info.stride = stride;
4659
4660 radv_draw(cmd_buffer, &info);
4661 }
4662
4663 void radv_CmdDrawIndexedIndirect(
4664 VkCommandBuffer commandBuffer,
4665 VkBuffer _buffer,
4666 VkDeviceSize offset,
4667 uint32_t drawCount,
4668 uint32_t stride)
4669 {
4670 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4671 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4672 struct radv_draw_info info = {};
4673
4674 info.indexed = true;
4675 info.count = drawCount;
4676 info.indirect = buffer;
4677 info.indirect_offset = offset;
4678 info.stride = stride;
4679
4680 radv_draw(cmd_buffer, &info);
4681 }
4682
4683 void radv_CmdDrawIndirectCountKHR(
4684 VkCommandBuffer commandBuffer,
4685 VkBuffer _buffer,
4686 VkDeviceSize offset,
4687 VkBuffer _countBuffer,
4688 VkDeviceSize countBufferOffset,
4689 uint32_t maxDrawCount,
4690 uint32_t stride)
4691 {
4692 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4693 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4694 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4695 struct radv_draw_info info = {};
4696
4697 info.count = maxDrawCount;
4698 info.indirect = buffer;
4699 info.indirect_offset = offset;
4700 info.count_buffer = count_buffer;
4701 info.count_buffer_offset = countBufferOffset;
4702 info.stride = stride;
4703
4704 radv_draw(cmd_buffer, &info);
4705 }
4706
4707 void radv_CmdDrawIndexedIndirectCountKHR(
4708 VkCommandBuffer commandBuffer,
4709 VkBuffer _buffer,
4710 VkDeviceSize offset,
4711 VkBuffer _countBuffer,
4712 VkDeviceSize countBufferOffset,
4713 uint32_t maxDrawCount,
4714 uint32_t stride)
4715 {
4716 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4717 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4718 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4719 struct radv_draw_info info = {};
4720
4721 info.indexed = true;
4722 info.count = maxDrawCount;
4723 info.indirect = buffer;
4724 info.indirect_offset = offset;
4725 info.count_buffer = count_buffer;
4726 info.count_buffer_offset = countBufferOffset;
4727 info.stride = stride;
4728
4729 radv_draw(cmd_buffer, &info);
4730 }
4731
4732 struct radv_dispatch_info {
4733 /**
4734 * Determine the layout of the grid (in block units) to be used.
4735 */
4736 uint32_t blocks[3];
4737
4738 /**
4739 * A starting offset for the grid. If unaligned is set, the offset
4740 * must still be aligned.
4741 */
4742 uint32_t offsets[3];
4743 /**
4744 * Whether it's an unaligned compute dispatch.
4745 */
4746 bool unaligned;
4747
4748 /**
4749 * Indirect compute parameters resource.
4750 */
4751 struct radv_buffer *indirect;
4752 uint64_t indirect_offset;
4753 };
4754
4755 static void
4756 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
4757 const struct radv_dispatch_info *info)
4758 {
4759 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4760 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4761 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
4762 struct radeon_winsys *ws = cmd_buffer->device->ws;
4763 bool predicating = cmd_buffer->state.predicating;
4764 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4765 struct radv_userdata_info *loc;
4766
4767 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
4768 AC_UD_CS_GRID_SIZE);
4769
4770 ASSERTED unsigned cdw_max = radeon_check_space(ws, cs, 25);
4771
4772 if (info->indirect) {
4773 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4774
4775 va += info->indirect->offset + info->indirect_offset;
4776
4777 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4778
4779 if (loc->sgpr_idx != -1) {
4780 for (unsigned i = 0; i < 3; ++i) {
4781 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
4782 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
4783 COPY_DATA_DST_SEL(COPY_DATA_REG));
4784 radeon_emit(cs, (va + 4 * i));
4785 radeon_emit(cs, (va + 4 * i) >> 32);
4786 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
4787 + loc->sgpr_idx * 4) >> 2) + i);
4788 radeon_emit(cs, 0);
4789 }
4790 }
4791
4792 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
4793 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
4794 PKT3_SHADER_TYPE_S(1));
4795 radeon_emit(cs, va);
4796 radeon_emit(cs, va >> 32);
4797 radeon_emit(cs, dispatch_initiator);
4798 } else {
4799 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
4800 PKT3_SHADER_TYPE_S(1));
4801 radeon_emit(cs, 1);
4802 radeon_emit(cs, va);
4803 radeon_emit(cs, va >> 32);
4804
4805 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
4806 PKT3_SHADER_TYPE_S(1));
4807 radeon_emit(cs, 0);
4808 radeon_emit(cs, dispatch_initiator);
4809 }
4810 } else {
4811 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
4812 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
4813
4814 if (info->unaligned) {
4815 unsigned *cs_block_size = compute_shader->info.cs.block_size;
4816 unsigned remainder[3];
4817
4818 /* If aligned, these should be an entire block size,
4819 * not 0.
4820 */
4821 remainder[0] = blocks[0] + cs_block_size[0] -
4822 align_u32_npot(blocks[0], cs_block_size[0]);
4823 remainder[1] = blocks[1] + cs_block_size[1] -
4824 align_u32_npot(blocks[1], cs_block_size[1]);
4825 remainder[2] = blocks[2] + cs_block_size[2] -
4826 align_u32_npot(blocks[2], cs_block_size[2]);
4827
4828 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
4829 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
4830 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
4831
4832 for(unsigned i = 0; i < 3; ++i) {
4833 assert(offsets[i] % cs_block_size[i] == 0);
4834 offsets[i] /= cs_block_size[i];
4835 }
4836
4837 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4838 radeon_emit(cs,
4839 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
4840 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
4841 radeon_emit(cs,
4842 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
4843 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
4844 radeon_emit(cs,
4845 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
4846 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
4847
4848 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
4849 }
4850
4851 if (loc->sgpr_idx != -1) {
4852 assert(loc->num_sgprs == 3);
4853
4854 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
4855 loc->sgpr_idx * 4, 3);
4856 radeon_emit(cs, blocks[0]);
4857 radeon_emit(cs, blocks[1]);
4858 radeon_emit(cs, blocks[2]);
4859 }
4860
4861 if (offsets[0] || offsets[1] || offsets[2]) {
4862 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
4863 radeon_emit(cs, offsets[0]);
4864 radeon_emit(cs, offsets[1]);
4865 radeon_emit(cs, offsets[2]);
4866
4867 /* The blocks in the packet are not counts but end values. */
4868 for (unsigned i = 0; i < 3; ++i)
4869 blocks[i] += offsets[i];
4870 } else {
4871 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
4872 }
4873
4874 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
4875 PKT3_SHADER_TYPE_S(1));
4876 radeon_emit(cs, blocks[0]);
4877 radeon_emit(cs, blocks[1]);
4878 radeon_emit(cs, blocks[2]);
4879 radeon_emit(cs, dispatch_initiator);
4880 }
4881
4882 assert(cmd_buffer->cs->cdw <= cdw_max);
4883 }
4884
4885 static void
4886 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
4887 {
4888 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4889 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4890 }
4891
4892 static void
4893 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
4894 const struct radv_dispatch_info *info)
4895 {
4896 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4897 bool has_prefetch =
4898 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4899 bool pipeline_is_dirty = pipeline &&
4900 pipeline != cmd_buffer->state.emitted_compute_pipeline;
4901
4902 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4903 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4904 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4905 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4906 /* If we have to wait for idle, set all states first, so that
4907 * all SET packets are processed in parallel with previous draw
4908 * calls. Then upload descriptors, set shader pointers, and
4909 * dispatch, and prefetch at the end. This ensures that the
4910 * time the CUs are idle is very short. (there are only SET_SH
4911 * packets between the wait and the draw)
4912 */
4913 radv_emit_compute_pipeline(cmd_buffer);
4914 si_emit_cache_flush(cmd_buffer);
4915 /* <-- CUs are idle here --> */
4916
4917 radv_upload_compute_shader_descriptors(cmd_buffer);
4918
4919 radv_emit_dispatch_packets(cmd_buffer, info);
4920 /* <-- CUs are busy here --> */
4921
4922 /* Start prefetches after the dispatch has been started. Both
4923 * will run in parallel, but starting the dispatch first is
4924 * more important.
4925 */
4926 if (has_prefetch && pipeline_is_dirty) {
4927 radv_emit_shader_prefetch(cmd_buffer,
4928 pipeline->shaders[MESA_SHADER_COMPUTE]);
4929 }
4930 } else {
4931 /* If we don't wait for idle, start prefetches first, then set
4932 * states, and dispatch at the end.
4933 */
4934 si_emit_cache_flush(cmd_buffer);
4935
4936 if (has_prefetch && pipeline_is_dirty) {
4937 radv_emit_shader_prefetch(cmd_buffer,
4938 pipeline->shaders[MESA_SHADER_COMPUTE]);
4939 }
4940
4941 radv_upload_compute_shader_descriptors(cmd_buffer);
4942
4943 radv_emit_compute_pipeline(cmd_buffer);
4944 radv_emit_dispatch_packets(cmd_buffer, info);
4945 }
4946
4947 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
4948 }
4949
4950 void radv_CmdDispatchBase(
4951 VkCommandBuffer commandBuffer,
4952 uint32_t base_x,
4953 uint32_t base_y,
4954 uint32_t base_z,
4955 uint32_t x,
4956 uint32_t y,
4957 uint32_t z)
4958 {
4959 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4960 struct radv_dispatch_info info = {};
4961
4962 info.blocks[0] = x;
4963 info.blocks[1] = y;
4964 info.blocks[2] = z;
4965
4966 info.offsets[0] = base_x;
4967 info.offsets[1] = base_y;
4968 info.offsets[2] = base_z;
4969 radv_dispatch(cmd_buffer, &info);
4970 }
4971
4972 void radv_CmdDispatch(
4973 VkCommandBuffer commandBuffer,
4974 uint32_t x,
4975 uint32_t y,
4976 uint32_t z)
4977 {
4978 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
4979 }
4980
4981 void radv_CmdDispatchIndirect(
4982 VkCommandBuffer commandBuffer,
4983 VkBuffer _buffer,
4984 VkDeviceSize offset)
4985 {
4986 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4987 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4988 struct radv_dispatch_info info = {};
4989
4990 info.indirect = buffer;
4991 info.indirect_offset = offset;
4992
4993 radv_dispatch(cmd_buffer, &info);
4994 }
4995
4996 void radv_unaligned_dispatch(
4997 struct radv_cmd_buffer *cmd_buffer,
4998 uint32_t x,
4999 uint32_t y,
5000 uint32_t z)
5001 {
5002 struct radv_dispatch_info info = {};
5003
5004 info.blocks[0] = x;
5005 info.blocks[1] = y;
5006 info.blocks[2] = z;
5007 info.unaligned = 1;
5008
5009 radv_dispatch(cmd_buffer, &info);
5010 }
5011
5012 void radv_CmdEndRenderPass(
5013 VkCommandBuffer commandBuffer)
5014 {
5015 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5016
5017 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
5018
5019 radv_cmd_buffer_end_subpass(cmd_buffer);
5020
5021 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
5022 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
5023
5024 cmd_buffer->state.pass = NULL;
5025 cmd_buffer->state.subpass = NULL;
5026 cmd_buffer->state.attachments = NULL;
5027 cmd_buffer->state.framebuffer = NULL;
5028 cmd_buffer->state.subpass_sample_locs = NULL;
5029 }
5030
5031 void radv_CmdEndRenderPass2KHR(
5032 VkCommandBuffer commandBuffer,
5033 const VkSubpassEndInfoKHR* pSubpassEndInfo)
5034 {
5035 radv_CmdEndRenderPass(commandBuffer);
5036 }
5037
5038 /*
5039 * For HTILE we have the following interesting clear words:
5040 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
5041 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
5042 * 0xfffffff0: Clear depth to 1.0
5043 * 0x00000000: Clear depth to 0.0
5044 */
5045 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
5046 struct radv_image *image,
5047 const VkImageSubresourceRange *range,
5048 uint32_t clear_word)
5049 {
5050 assert(range->baseMipLevel == 0);
5051 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
5052 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
5053 struct radv_cmd_state *state = &cmd_buffer->state;
5054 VkClearDepthStencilValue value = {};
5055
5056 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5057 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5058
5059 state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, clear_word);
5060
5061 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5062
5063 if (vk_format_is_stencil(image->vk_format))
5064 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
5065
5066 radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
5067
5068 if (radv_image_is_tc_compat_htile(image)) {
5069 /* Initialize the TC-compat metada value to 0 because by
5070 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
5071 * need have to conditionally update its value when performing
5072 * a fast depth clear.
5073 */
5074 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, 0);
5075 }
5076 }
5077
5078 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
5079 struct radv_image *image,
5080 VkImageLayout src_layout,
5081 bool src_render_loop,
5082 VkImageLayout dst_layout,
5083 bool dst_render_loop,
5084 unsigned src_queue_mask,
5085 unsigned dst_queue_mask,
5086 const VkImageSubresourceRange *range,
5087 struct radv_sample_locations_state *sample_locs)
5088 {
5089 if (!radv_image_has_htile(image))
5090 return;
5091
5092 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5093 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
5094
5095 if (radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop,
5096 dst_queue_mask)) {
5097 clear_value = 0;
5098 }
5099
5100 radv_initialize_htile(cmd_buffer, image, range, clear_value);
5101 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5102 radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5103 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
5104 radv_initialize_htile(cmd_buffer, image, range, clear_value);
5105 } else if (radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5106 !radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5107 VkImageSubresourceRange local_range = *range;
5108 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
5109 local_range.baseMipLevel = 0;
5110 local_range.levelCount = 1;
5111
5112 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5113 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5114
5115 radv_decompress_depth_image_inplace(cmd_buffer, image,
5116 &local_range, sample_locs);
5117
5118 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5119 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5120 }
5121 }
5122
5123 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
5124 struct radv_image *image,
5125 const VkImageSubresourceRange *range,
5126 uint32_t value)
5127 {
5128 struct radv_cmd_state *state = &cmd_buffer->state;
5129
5130 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5131 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5132
5133 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, range, value);
5134
5135 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5136 }
5137
5138 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
5139 struct radv_image *image,
5140 const VkImageSubresourceRange *range)
5141 {
5142 struct radv_cmd_state *state = &cmd_buffer->state;
5143 static const uint32_t fmask_clear_values[4] = {
5144 0x00000000,
5145 0x02020202,
5146 0xE4E4E4E4,
5147 0x76543210
5148 };
5149 uint32_t log2_samples = util_logbase2(image->info.samples);
5150 uint32_t value = fmask_clear_values[log2_samples];
5151
5152 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5153 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5154
5155 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, range, value);
5156
5157 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5158 }
5159
5160 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
5161 struct radv_image *image,
5162 const VkImageSubresourceRange *range, uint32_t value)
5163 {
5164 struct radv_cmd_state *state = &cmd_buffer->state;
5165 unsigned size = 0;
5166
5167 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5168 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5169
5170 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
5171
5172 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) {
5173 /* When DCC is enabled with mipmaps, some levels might not
5174 * support fast clears and we have to initialize them as "fully
5175 * expanded".
5176 */
5177 /* Compute the size of all fast clearable DCC levels. */
5178 for (unsigned i = 0; i < image->planes[0].surface.num_dcc_levels; i++) {
5179 struct legacy_surf_level *surf_level =
5180 &image->planes[0].surface.u.legacy.level[i];
5181 unsigned dcc_fast_clear_size =
5182 surf_level->dcc_slice_fast_clear_size * image->info.array_size;
5183
5184 if (!dcc_fast_clear_size)
5185 break;
5186
5187 size = surf_level->dcc_offset + dcc_fast_clear_size;
5188 }
5189
5190 /* Initialize the mipmap levels without DCC. */
5191 if (size != image->planes[0].surface.dcc_size) {
5192 state->flush_bits |=
5193 radv_fill_buffer(cmd_buffer, image->bo,
5194 image->offset + image->dcc_offset + size,
5195 image->planes[0].surface.dcc_size - size,
5196 0xffffffff);
5197 }
5198 }
5199
5200 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5201 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5202 }
5203
5204 /**
5205 * Initialize DCC/FMASK/CMASK metadata for a color image.
5206 */
5207 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
5208 struct radv_image *image,
5209 VkImageLayout src_layout,
5210 bool src_render_loop,
5211 VkImageLayout dst_layout,
5212 bool dst_render_loop,
5213 unsigned src_queue_mask,
5214 unsigned dst_queue_mask,
5215 const VkImageSubresourceRange *range)
5216 {
5217 if (radv_image_has_cmask(image)) {
5218 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5219
5220 /* TODO: clarify this. */
5221 if (radv_image_has_fmask(image)) {
5222 value = 0xccccccccu;
5223 }
5224
5225 radv_initialise_cmask(cmd_buffer, image, range, value);
5226 }
5227
5228 if (radv_image_has_fmask(image)) {
5229 radv_initialize_fmask(cmd_buffer, image, range);
5230 }
5231
5232 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5233 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5234 bool need_decompress_pass = false;
5235
5236 if (radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout,
5237 dst_render_loop,
5238 dst_queue_mask)) {
5239 value = 0x20202020u;
5240 need_decompress_pass = true;
5241 }
5242
5243 radv_initialize_dcc(cmd_buffer, image, range, value);
5244
5245 radv_update_fce_metadata(cmd_buffer, image, range,
5246 need_decompress_pass);
5247 }
5248
5249 if (radv_image_has_cmask(image) ||
5250 radv_dcc_enabled(image, range->baseMipLevel)) {
5251 uint32_t color_values[2] = {};
5252 radv_set_color_clear_metadata(cmd_buffer, image, range,
5253 color_values);
5254 }
5255 }
5256
5257 /**
5258 * Handle color image transitions for DCC/FMASK/CMASK.
5259 */
5260 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
5261 struct radv_image *image,
5262 VkImageLayout src_layout,
5263 bool src_render_loop,
5264 VkImageLayout dst_layout,
5265 bool dst_render_loop,
5266 unsigned src_queue_mask,
5267 unsigned dst_queue_mask,
5268 const VkImageSubresourceRange *range)
5269 {
5270 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5271 radv_init_color_image_metadata(cmd_buffer, image,
5272 src_layout, src_render_loop,
5273 dst_layout, dst_render_loop,
5274 src_queue_mask, dst_queue_mask,
5275 range);
5276 return;
5277 }
5278
5279 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5280 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
5281 radv_initialize_dcc(cmd_buffer, image, range, 0xffffffffu);
5282 } else if (radv_layout_dcc_compressed(cmd_buffer->device, image, src_layout, src_render_loop, src_queue_mask) &&
5283 !radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout, dst_render_loop, dst_queue_mask)) {
5284 radv_decompress_dcc(cmd_buffer, image, range);
5285 } else if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
5286 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5287 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5288 }
5289 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
5290 bool fce_eliminate = false, fmask_expand = false;
5291
5292 if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
5293 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5294 fce_eliminate = true;
5295 }
5296
5297 if (radv_image_has_fmask(image)) {
5298 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
5299 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
5300 /* A FMASK decompress is required before doing
5301 * a MSAA decompress using FMASK.
5302 */
5303 fmask_expand = true;
5304 }
5305 }
5306
5307 if (fce_eliminate || fmask_expand)
5308 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5309
5310 if (fmask_expand)
5311 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
5312 }
5313 }
5314
5315 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
5316 struct radv_image *image,
5317 VkImageLayout src_layout,
5318 bool src_render_loop,
5319 VkImageLayout dst_layout,
5320 bool dst_render_loop,
5321 uint32_t src_family,
5322 uint32_t dst_family,
5323 const VkImageSubresourceRange *range,
5324 struct radv_sample_locations_state *sample_locs)
5325 {
5326 if (image->exclusive && src_family != dst_family) {
5327 /* This is an acquire or a release operation and there will be
5328 * a corresponding release/acquire. Do the transition in the
5329 * most flexible queue. */
5330
5331 assert(src_family == cmd_buffer->queue_family_index ||
5332 dst_family == cmd_buffer->queue_family_index);
5333
5334 if (src_family == VK_QUEUE_FAMILY_EXTERNAL ||
5335 src_family == VK_QUEUE_FAMILY_FOREIGN_EXT)
5336 return;
5337
5338 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
5339 return;
5340
5341 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
5342 (src_family == RADV_QUEUE_GENERAL ||
5343 dst_family == RADV_QUEUE_GENERAL))
5344 return;
5345 }
5346
5347 if (src_layout == dst_layout)
5348 return;
5349
5350 unsigned src_queue_mask =
5351 radv_image_queue_family_mask(image, src_family,
5352 cmd_buffer->queue_family_index);
5353 unsigned dst_queue_mask =
5354 radv_image_queue_family_mask(image, dst_family,
5355 cmd_buffer->queue_family_index);
5356
5357 if (vk_format_is_depth(image->vk_format)) {
5358 radv_handle_depth_image_transition(cmd_buffer, image,
5359 src_layout, src_render_loop,
5360 dst_layout, dst_render_loop,
5361 src_queue_mask, dst_queue_mask,
5362 range, sample_locs);
5363 } else {
5364 radv_handle_color_image_transition(cmd_buffer, image,
5365 src_layout, src_render_loop,
5366 dst_layout, dst_render_loop,
5367 src_queue_mask, dst_queue_mask,
5368 range);
5369 }
5370 }
5371
5372 struct radv_barrier_info {
5373 uint32_t eventCount;
5374 const VkEvent *pEvents;
5375 VkPipelineStageFlags srcStageMask;
5376 VkPipelineStageFlags dstStageMask;
5377 };
5378
5379 static void
5380 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
5381 uint32_t memoryBarrierCount,
5382 const VkMemoryBarrier *pMemoryBarriers,
5383 uint32_t bufferMemoryBarrierCount,
5384 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
5385 uint32_t imageMemoryBarrierCount,
5386 const VkImageMemoryBarrier *pImageMemoryBarriers,
5387 const struct radv_barrier_info *info)
5388 {
5389 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5390 enum radv_cmd_flush_bits src_flush_bits = 0;
5391 enum radv_cmd_flush_bits dst_flush_bits = 0;
5392
5393 for (unsigned i = 0; i < info->eventCount; ++i) {
5394 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
5395 uint64_t va = radv_buffer_get_va(event->bo);
5396
5397 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5398
5399 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
5400
5401 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
5402 assert(cmd_buffer->cs->cdw <= cdw_max);
5403 }
5404
5405 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
5406 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
5407 NULL);
5408 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
5409 NULL);
5410 }
5411
5412 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
5413 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
5414 NULL);
5415 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
5416 NULL);
5417 }
5418
5419 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5420 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5421
5422 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
5423 image);
5424 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
5425 image);
5426 }
5427
5428 /* The Vulkan spec 1.1.98 says:
5429 *
5430 * "An execution dependency with only
5431 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
5432 * will only prevent that stage from executing in subsequently
5433 * submitted commands. As this stage does not perform any actual
5434 * execution, this is not observable - in effect, it does not delay
5435 * processing of subsequent commands. Similarly an execution dependency
5436 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
5437 * will effectively not wait for any prior commands to complete."
5438 */
5439 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
5440 radv_stage_flush(cmd_buffer, info->srcStageMask);
5441 cmd_buffer->state.flush_bits |= src_flush_bits;
5442
5443 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5444 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5445
5446 const struct VkSampleLocationsInfoEXT *sample_locs_info =
5447 vk_find_struct_const(pImageMemoryBarriers[i].pNext,
5448 SAMPLE_LOCATIONS_INFO_EXT);
5449 struct radv_sample_locations_state sample_locations = {};
5450
5451 if (sample_locs_info) {
5452 assert(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
5453 sample_locations.per_pixel = sample_locs_info->sampleLocationsPerPixel;
5454 sample_locations.grid_size = sample_locs_info->sampleLocationGridSize;
5455 sample_locations.count = sample_locs_info->sampleLocationsCount;
5456 typed_memcpy(&sample_locations.locations[0],
5457 sample_locs_info->pSampleLocations,
5458 sample_locs_info->sampleLocationsCount);
5459 }
5460
5461 radv_handle_image_transition(cmd_buffer, image,
5462 pImageMemoryBarriers[i].oldLayout,
5463 false, /* Outside of a renderpass we are never in a renderloop */
5464 pImageMemoryBarriers[i].newLayout,
5465 false, /* Outside of a renderpass we are never in a renderloop */
5466 pImageMemoryBarriers[i].srcQueueFamilyIndex,
5467 pImageMemoryBarriers[i].dstQueueFamilyIndex,
5468 &pImageMemoryBarriers[i].subresourceRange,
5469 sample_locs_info ? &sample_locations : NULL);
5470 }
5471
5472 /* Make sure CP DMA is idle because the driver might have performed a
5473 * DMA operation for copying or filling buffers/images.
5474 */
5475 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5476 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5477 si_cp_dma_wait_for_idle(cmd_buffer);
5478
5479 cmd_buffer->state.flush_bits |= dst_flush_bits;
5480 }
5481
5482 void radv_CmdPipelineBarrier(
5483 VkCommandBuffer commandBuffer,
5484 VkPipelineStageFlags srcStageMask,
5485 VkPipelineStageFlags destStageMask,
5486 VkBool32 byRegion,
5487 uint32_t memoryBarrierCount,
5488 const VkMemoryBarrier* pMemoryBarriers,
5489 uint32_t bufferMemoryBarrierCount,
5490 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5491 uint32_t imageMemoryBarrierCount,
5492 const VkImageMemoryBarrier* pImageMemoryBarriers)
5493 {
5494 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5495 struct radv_barrier_info info;
5496
5497 info.eventCount = 0;
5498 info.pEvents = NULL;
5499 info.srcStageMask = srcStageMask;
5500 info.dstStageMask = destStageMask;
5501
5502 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5503 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5504 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5505 }
5506
5507
5508 static void write_event(struct radv_cmd_buffer *cmd_buffer,
5509 struct radv_event *event,
5510 VkPipelineStageFlags stageMask,
5511 unsigned value)
5512 {
5513 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5514 uint64_t va = radv_buffer_get_va(event->bo);
5515
5516 si_emit_cache_flush(cmd_buffer);
5517
5518 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5519
5520 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 21);
5521
5522 /* Flags that only require a top-of-pipe event. */
5523 VkPipelineStageFlags top_of_pipe_flags =
5524 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
5525
5526 /* Flags that only require a post-index-fetch event. */
5527 VkPipelineStageFlags post_index_fetch_flags =
5528 top_of_pipe_flags |
5529 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
5530 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
5531
5532 /* Make sure CP DMA is idle because the driver might have performed a
5533 * DMA operation for copying or filling buffers/images.
5534 */
5535 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5536 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5537 si_cp_dma_wait_for_idle(cmd_buffer);
5538
5539 /* TODO: Emit EOS events for syncing PS/CS stages. */
5540
5541 if (!(stageMask & ~top_of_pipe_flags)) {
5542 /* Just need to sync the PFP engine. */
5543 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5544 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5545 S_370_WR_CONFIRM(1) |
5546 S_370_ENGINE_SEL(V_370_PFP));
5547 radeon_emit(cs, va);
5548 radeon_emit(cs, va >> 32);
5549 radeon_emit(cs, value);
5550 } else if (!(stageMask & ~post_index_fetch_flags)) {
5551 /* Sync ME because PFP reads index and indirect buffers. */
5552 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5553 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5554 S_370_WR_CONFIRM(1) |
5555 S_370_ENGINE_SEL(V_370_ME));
5556 radeon_emit(cs, va);
5557 radeon_emit(cs, va >> 32);
5558 radeon_emit(cs, value);
5559 } else {
5560 /* Otherwise, sync all prior GPU work using an EOP event. */
5561 si_cs_emit_write_event_eop(cs,
5562 cmd_buffer->device->physical_device->rad_info.chip_class,
5563 radv_cmd_buffer_uses_mec(cmd_buffer),
5564 V_028A90_BOTTOM_OF_PIPE_TS, 0,
5565 EOP_DST_SEL_MEM,
5566 EOP_DATA_SEL_VALUE_32BIT, va, value,
5567 cmd_buffer->gfx9_eop_bug_va);
5568 }
5569
5570 assert(cmd_buffer->cs->cdw <= cdw_max);
5571 }
5572
5573 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
5574 VkEvent _event,
5575 VkPipelineStageFlags stageMask)
5576 {
5577 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5578 RADV_FROM_HANDLE(radv_event, event, _event);
5579
5580 write_event(cmd_buffer, event, stageMask, 1);
5581 }
5582
5583 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
5584 VkEvent _event,
5585 VkPipelineStageFlags stageMask)
5586 {
5587 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5588 RADV_FROM_HANDLE(radv_event, event, _event);
5589
5590 write_event(cmd_buffer, event, stageMask, 0);
5591 }
5592
5593 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
5594 uint32_t eventCount,
5595 const VkEvent* pEvents,
5596 VkPipelineStageFlags srcStageMask,
5597 VkPipelineStageFlags dstStageMask,
5598 uint32_t memoryBarrierCount,
5599 const VkMemoryBarrier* pMemoryBarriers,
5600 uint32_t bufferMemoryBarrierCount,
5601 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5602 uint32_t imageMemoryBarrierCount,
5603 const VkImageMemoryBarrier* pImageMemoryBarriers)
5604 {
5605 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5606 struct radv_barrier_info info;
5607
5608 info.eventCount = eventCount;
5609 info.pEvents = pEvents;
5610 info.srcStageMask = 0;
5611
5612 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5613 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5614 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5615 }
5616
5617
5618 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
5619 uint32_t deviceMask)
5620 {
5621 /* No-op */
5622 }
5623
5624 /* VK_EXT_conditional_rendering */
5625 void radv_CmdBeginConditionalRenderingEXT(
5626 VkCommandBuffer commandBuffer,
5627 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
5628 {
5629 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5630 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
5631 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5632 bool draw_visible = true;
5633 uint64_t pred_value = 0;
5634 uint64_t va, new_va;
5635 unsigned pred_offset;
5636
5637 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
5638
5639 /* By default, if the 32-bit value at offset in buffer memory is zero,
5640 * then the rendering commands are discarded, otherwise they are
5641 * executed as normal. If the inverted flag is set, all commands are
5642 * discarded if the value is non zero.
5643 */
5644 if (pConditionalRenderingBegin->flags &
5645 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
5646 draw_visible = false;
5647 }
5648
5649 si_emit_cache_flush(cmd_buffer);
5650
5651 /* From the Vulkan spec 1.1.107:
5652 *
5653 * "If the 32-bit value at offset in buffer memory is zero, then the
5654 * rendering commands are discarded, otherwise they are executed as
5655 * normal. If the value of the predicate in buffer memory changes while
5656 * conditional rendering is active, the rendering commands may be
5657 * discarded in an implementation-dependent way. Some implementations
5658 * may latch the value of the predicate upon beginning conditional
5659 * rendering while others may read it before every rendering command."
5660 *
5661 * But, the AMD hardware treats the predicate as a 64-bit value which
5662 * means we need a workaround in the driver. Luckily, it's not required
5663 * to support if the value changes when predication is active.
5664 *
5665 * The workaround is as follows:
5666 * 1) allocate a 64-value in the upload BO and initialize it to 0
5667 * 2) copy the 32-bit predicate value to the upload BO
5668 * 3) use the new allocated VA address for predication
5669 *
5670 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
5671 * in ME (+ sync PFP) instead of PFP.
5672 */
5673 radv_cmd_buffer_upload_data(cmd_buffer, 8, 16, &pred_value, &pred_offset);
5674
5675 new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
5676
5677 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5678 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5679 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
5680 COPY_DATA_WR_CONFIRM);
5681 radeon_emit(cs, va);
5682 radeon_emit(cs, va >> 32);
5683 radeon_emit(cs, new_va);
5684 radeon_emit(cs, new_va >> 32);
5685
5686 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
5687 radeon_emit(cs, 0);
5688
5689 /* Enable predication for this command buffer. */
5690 si_emit_set_predication_state(cmd_buffer, draw_visible, new_va);
5691 cmd_buffer->state.predicating = true;
5692
5693 /* Store conditional rendering user info. */
5694 cmd_buffer->state.predication_type = draw_visible;
5695 cmd_buffer->state.predication_va = new_va;
5696 }
5697
5698 void radv_CmdEndConditionalRenderingEXT(
5699 VkCommandBuffer commandBuffer)
5700 {
5701 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5702
5703 /* Disable predication for this command buffer. */
5704 si_emit_set_predication_state(cmd_buffer, false, 0);
5705 cmd_buffer->state.predicating = false;
5706
5707 /* Reset conditional rendering user info. */
5708 cmd_buffer->state.predication_type = -1;
5709 cmd_buffer->state.predication_va = 0;
5710 }
5711
5712 /* VK_EXT_transform_feedback */
5713 void radv_CmdBindTransformFeedbackBuffersEXT(
5714 VkCommandBuffer commandBuffer,
5715 uint32_t firstBinding,
5716 uint32_t bindingCount,
5717 const VkBuffer* pBuffers,
5718 const VkDeviceSize* pOffsets,
5719 const VkDeviceSize* pSizes)
5720 {
5721 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5722 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5723 uint8_t enabled_mask = 0;
5724
5725 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
5726 for (uint32_t i = 0; i < bindingCount; i++) {
5727 uint32_t idx = firstBinding + i;
5728
5729 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
5730 sb[idx].offset = pOffsets[i];
5731 sb[idx].size = pSizes[i];
5732
5733 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
5734 sb[idx].buffer->bo);
5735
5736 enabled_mask |= 1 << idx;
5737 }
5738
5739 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
5740
5741 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
5742 }
5743
5744 static void
5745 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
5746 {
5747 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5748 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5749
5750 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
5751 radeon_emit(cs,
5752 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
5753 S_028B94_RAST_STREAM(0) |
5754 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
5755 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
5756 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
5757 radeon_emit(cs, so->hw_enabled_mask &
5758 so->enabled_stream_buffers_mask);
5759
5760 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5761 }
5762
5763 static void
5764 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
5765 {
5766 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5767 bool old_streamout_enabled = so->streamout_enabled;
5768 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
5769
5770 so->streamout_enabled = enable;
5771
5772 so->hw_enabled_mask = so->enabled_mask |
5773 (so->enabled_mask << 4) |
5774 (so->enabled_mask << 8) |
5775 (so->enabled_mask << 12);
5776
5777 if ((old_streamout_enabled != so->streamout_enabled) ||
5778 (old_hw_enabled_mask != so->hw_enabled_mask))
5779 radv_emit_streamout_enable(cmd_buffer);
5780 }
5781
5782 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
5783 {
5784 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5785 unsigned reg_strmout_cntl;
5786
5787 /* The register is at different places on different ASICs. */
5788 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
5789 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
5790 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
5791 } else {
5792 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
5793 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
5794 }
5795
5796 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
5797 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
5798
5799 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
5800 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
5801 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
5802 radeon_emit(cs, 0);
5803 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
5804 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
5805 radeon_emit(cs, 4); /* poll interval */
5806 }
5807
5808 static void
5809 radv_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
5810 uint32_t firstCounterBuffer,
5811 uint32_t counterBufferCount,
5812 const VkBuffer *pCounterBuffers,
5813 const VkDeviceSize *pCounterBufferOffsets)
5814
5815 {
5816 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5817 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5818 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5819 uint32_t i;
5820
5821 radv_flush_vgt_streamout(cmd_buffer);
5822
5823 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5824 for_each_bit(i, so->enabled_mask) {
5825 int32_t counter_buffer_idx = i - firstCounterBuffer;
5826 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5827 counter_buffer_idx = -1;
5828
5829 /* AMD GCN binds streamout buffers as shader resources.
5830 * VGT only counts primitives and tells the shader through
5831 * SGPRs what to do.
5832 */
5833 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
5834 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
5835 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
5836
5837 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5838
5839 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5840 /* The array of counter buffers is optional. */
5841 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5842 uint64_t va = radv_buffer_get_va(buffer->bo);
5843
5844 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5845
5846 /* Append */
5847 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5848 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5849 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5850 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
5851 radeon_emit(cs, 0); /* unused */
5852 radeon_emit(cs, 0); /* unused */
5853 radeon_emit(cs, va); /* src address lo */
5854 radeon_emit(cs, va >> 32); /* src address hi */
5855
5856 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5857 } else {
5858 /* Start from the beginning. */
5859 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5860 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5861 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5862 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
5863 radeon_emit(cs, 0); /* unused */
5864 radeon_emit(cs, 0); /* unused */
5865 radeon_emit(cs, 0); /* unused */
5866 radeon_emit(cs, 0); /* unused */
5867 }
5868 }
5869
5870 radv_set_streamout_enable(cmd_buffer, true);
5871 }
5872
5873 void radv_CmdBeginTransformFeedbackEXT(
5874 VkCommandBuffer commandBuffer,
5875 uint32_t firstCounterBuffer,
5876 uint32_t counterBufferCount,
5877 const VkBuffer* pCounterBuffers,
5878 const VkDeviceSize* pCounterBufferOffsets)
5879 {
5880 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5881
5882 radv_emit_streamout_begin(cmd_buffer,
5883 firstCounterBuffer, counterBufferCount,
5884 pCounterBuffers, pCounterBufferOffsets);
5885 }
5886
5887 static void
5888 radv_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
5889 uint32_t firstCounterBuffer,
5890 uint32_t counterBufferCount,
5891 const VkBuffer *pCounterBuffers,
5892 const VkDeviceSize *pCounterBufferOffsets)
5893 {
5894 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5895 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5896 uint32_t i;
5897
5898 radv_flush_vgt_streamout(cmd_buffer);
5899
5900 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5901 for_each_bit(i, so->enabled_mask) {
5902 int32_t counter_buffer_idx = i - firstCounterBuffer;
5903 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5904 counter_buffer_idx = -1;
5905
5906 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5907 /* The array of counters buffer is optional. */
5908 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5909 uint64_t va = radv_buffer_get_va(buffer->bo);
5910
5911 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5912
5913 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5914 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5915 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5916 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
5917 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
5918 radeon_emit(cs, va); /* dst address lo */
5919 radeon_emit(cs, va >> 32); /* dst address hi */
5920 radeon_emit(cs, 0); /* unused */
5921 radeon_emit(cs, 0); /* unused */
5922
5923 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5924 }
5925
5926 /* Deactivate transform feedback by zeroing the buffer size.
5927 * The counters (primitives generated, primitives emitted) may
5928 * be enabled even if there is not buffer bound. This ensures
5929 * that the primitives-emitted query won't increment.
5930 */
5931 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
5932
5933 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5934 }
5935
5936 radv_set_streamout_enable(cmd_buffer, false);
5937 }
5938
5939 void radv_CmdEndTransformFeedbackEXT(
5940 VkCommandBuffer commandBuffer,
5941 uint32_t firstCounterBuffer,
5942 uint32_t counterBufferCount,
5943 const VkBuffer* pCounterBuffers,
5944 const VkDeviceSize* pCounterBufferOffsets)
5945 {
5946 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5947
5948 radv_emit_streamout_end(cmd_buffer,
5949 firstCounterBuffer, counterBufferCount,
5950 pCounterBuffers, pCounterBufferOffsets);
5951 }
5952
5953 void radv_CmdDrawIndirectByteCountEXT(
5954 VkCommandBuffer commandBuffer,
5955 uint32_t instanceCount,
5956 uint32_t firstInstance,
5957 VkBuffer _counterBuffer,
5958 VkDeviceSize counterBufferOffset,
5959 uint32_t counterOffset,
5960 uint32_t vertexStride)
5961 {
5962 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5963 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
5964 struct radv_draw_info info = {};
5965
5966 info.instance_count = instanceCount;
5967 info.first_instance = firstInstance;
5968 info.strmout_buffer = counterBuffer;
5969 info.strmout_buffer_offset = counterBufferOffset;
5970 info.stride = vertexStride;
5971
5972 radv_draw(cmd_buffer, &info);
5973 }
5974
5975 /* VK_AMD_buffer_marker */
5976 void radv_CmdWriteBufferMarkerAMD(
5977 VkCommandBuffer commandBuffer,
5978 VkPipelineStageFlagBits pipelineStage,
5979 VkBuffer dstBuffer,
5980 VkDeviceSize dstOffset,
5981 uint32_t marker)
5982 {
5983 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5984 RADV_FROM_HANDLE(radv_buffer, buffer, dstBuffer);
5985 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5986 uint64_t va = radv_buffer_get_va(buffer->bo) + dstOffset;
5987
5988 si_emit_cache_flush(cmd_buffer);
5989
5990 if (!(pipelineStage & ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT)) {
5991 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5992 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
5993 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
5994 COPY_DATA_WR_CONFIRM);
5995 radeon_emit(cs, marker);
5996 radeon_emit(cs, 0);
5997 radeon_emit(cs, va);
5998 radeon_emit(cs, va >> 32);
5999 } else {
6000 si_cs_emit_write_event_eop(cs,
6001 cmd_buffer->device->physical_device->rad_info.chip_class,
6002 radv_cmd_buffer_uses_mec(cmd_buffer),
6003 V_028A90_BOTTOM_OF_PIPE_TS, 0,
6004 EOP_DST_SEL_MEM,
6005 EOP_DATA_SEL_VALUE_32BIT,
6006 va, marker,
6007 cmd_buffer->gfx9_eop_bug_va);
6008 }
6009 }