2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
33 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
41 RADV_PREFETCH_VBO_DESCRIPTORS
= (1 << 0),
42 RADV_PREFETCH_VS
= (1 << 1),
43 RADV_PREFETCH_TCS
= (1 << 2),
44 RADV_PREFETCH_TES
= (1 << 3),
45 RADV_PREFETCH_GS
= (1 << 4),
46 RADV_PREFETCH_PS
= (1 << 5),
47 RADV_PREFETCH_SHADERS
= (RADV_PREFETCH_VS
|
54 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
55 struct radv_image
*image
,
56 VkImageLayout src_layout
,
58 VkImageLayout dst_layout
,
62 const VkImageSubresourceRange
*range
,
63 struct radv_sample_locations_state
*sample_locs
);
65 const struct radv_dynamic_state default_dynamic_state
= {
78 .blend_constants
= { 0.0f
, 0.0f
, 0.0f
, 0.0f
},
83 .stencil_compare_mask
= {
87 .stencil_write_mask
= {
91 .stencil_reference
= {
98 radv_bind_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
,
99 const struct radv_dynamic_state
*src
)
101 struct radv_dynamic_state
*dest
= &cmd_buffer
->state
.dynamic
;
102 uint32_t copy_mask
= src
->mask
;
103 uint32_t dest_mask
= 0;
105 /* Make sure to copy the number of viewports/scissors because they can
106 * only be specified at pipeline creation time.
108 dest
->viewport
.count
= src
->viewport
.count
;
109 dest
->scissor
.count
= src
->scissor
.count
;
110 dest
->discard_rectangle
.count
= src
->discard_rectangle
.count
;
111 dest
->sample_location
.count
= src
->sample_location
.count
;
113 if (copy_mask
& RADV_DYNAMIC_VIEWPORT
) {
114 if (memcmp(&dest
->viewport
.viewports
, &src
->viewport
.viewports
,
115 src
->viewport
.count
* sizeof(VkViewport
))) {
116 typed_memcpy(dest
->viewport
.viewports
,
117 src
->viewport
.viewports
,
118 src
->viewport
.count
);
119 dest_mask
|= RADV_DYNAMIC_VIEWPORT
;
123 if (copy_mask
& RADV_DYNAMIC_SCISSOR
) {
124 if (memcmp(&dest
->scissor
.scissors
, &src
->scissor
.scissors
,
125 src
->scissor
.count
* sizeof(VkRect2D
))) {
126 typed_memcpy(dest
->scissor
.scissors
,
127 src
->scissor
.scissors
, src
->scissor
.count
);
128 dest_mask
|= RADV_DYNAMIC_SCISSOR
;
132 if (copy_mask
& RADV_DYNAMIC_LINE_WIDTH
) {
133 if (dest
->line_width
!= src
->line_width
) {
134 dest
->line_width
= src
->line_width
;
135 dest_mask
|= RADV_DYNAMIC_LINE_WIDTH
;
139 if (copy_mask
& RADV_DYNAMIC_DEPTH_BIAS
) {
140 if (memcmp(&dest
->depth_bias
, &src
->depth_bias
,
141 sizeof(src
->depth_bias
))) {
142 dest
->depth_bias
= src
->depth_bias
;
143 dest_mask
|= RADV_DYNAMIC_DEPTH_BIAS
;
147 if (copy_mask
& RADV_DYNAMIC_BLEND_CONSTANTS
) {
148 if (memcmp(&dest
->blend_constants
, &src
->blend_constants
,
149 sizeof(src
->blend_constants
))) {
150 typed_memcpy(dest
->blend_constants
,
151 src
->blend_constants
, 4);
152 dest_mask
|= RADV_DYNAMIC_BLEND_CONSTANTS
;
156 if (copy_mask
& RADV_DYNAMIC_DEPTH_BOUNDS
) {
157 if (memcmp(&dest
->depth_bounds
, &src
->depth_bounds
,
158 sizeof(src
->depth_bounds
))) {
159 dest
->depth_bounds
= src
->depth_bounds
;
160 dest_mask
|= RADV_DYNAMIC_DEPTH_BOUNDS
;
164 if (copy_mask
& RADV_DYNAMIC_STENCIL_COMPARE_MASK
) {
165 if (memcmp(&dest
->stencil_compare_mask
,
166 &src
->stencil_compare_mask
,
167 sizeof(src
->stencil_compare_mask
))) {
168 dest
->stencil_compare_mask
= src
->stencil_compare_mask
;
169 dest_mask
|= RADV_DYNAMIC_STENCIL_COMPARE_MASK
;
173 if (copy_mask
& RADV_DYNAMIC_STENCIL_WRITE_MASK
) {
174 if (memcmp(&dest
->stencil_write_mask
, &src
->stencil_write_mask
,
175 sizeof(src
->stencil_write_mask
))) {
176 dest
->stencil_write_mask
= src
->stencil_write_mask
;
177 dest_mask
|= RADV_DYNAMIC_STENCIL_WRITE_MASK
;
181 if (copy_mask
& RADV_DYNAMIC_STENCIL_REFERENCE
) {
182 if (memcmp(&dest
->stencil_reference
, &src
->stencil_reference
,
183 sizeof(src
->stencil_reference
))) {
184 dest
->stencil_reference
= src
->stencil_reference
;
185 dest_mask
|= RADV_DYNAMIC_STENCIL_REFERENCE
;
189 if (copy_mask
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
190 if (memcmp(&dest
->discard_rectangle
.rectangles
, &src
->discard_rectangle
.rectangles
,
191 src
->discard_rectangle
.count
* sizeof(VkRect2D
))) {
192 typed_memcpy(dest
->discard_rectangle
.rectangles
,
193 src
->discard_rectangle
.rectangles
,
194 src
->discard_rectangle
.count
);
195 dest_mask
|= RADV_DYNAMIC_DISCARD_RECTANGLE
;
199 if (copy_mask
& RADV_DYNAMIC_SAMPLE_LOCATIONS
) {
200 if (dest
->sample_location
.per_pixel
!= src
->sample_location
.per_pixel
||
201 dest
->sample_location
.grid_size
.width
!= src
->sample_location
.grid_size
.width
||
202 dest
->sample_location
.grid_size
.height
!= src
->sample_location
.grid_size
.height
||
203 memcmp(&dest
->sample_location
.locations
,
204 &src
->sample_location
.locations
,
205 src
->sample_location
.count
* sizeof(VkSampleLocationEXT
))) {
206 dest
->sample_location
.per_pixel
= src
->sample_location
.per_pixel
;
207 dest
->sample_location
.grid_size
= src
->sample_location
.grid_size
;
208 typed_memcpy(dest
->sample_location
.locations
,
209 src
->sample_location
.locations
,
210 src
->sample_location
.count
);
211 dest_mask
|= RADV_DYNAMIC_SAMPLE_LOCATIONS
;
215 cmd_buffer
->state
.dirty
|= dest_mask
;
219 radv_bind_streamout_state(struct radv_cmd_buffer
*cmd_buffer
,
220 struct radv_pipeline
*pipeline
)
222 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
223 struct radv_shader_info
*info
;
225 if (!pipeline
->streamout_shader
)
228 info
= &pipeline
->streamout_shader
->info
.info
;
229 for (int i
= 0; i
< MAX_SO_BUFFERS
; i
++)
230 so
->stride_in_dw
[i
] = info
->so
.strides
[i
];
232 so
->enabled_stream_buffers_mask
= info
->so
.enabled_stream_buffers_mask
;
235 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
)
237 return cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
238 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
241 enum ring_type
radv_queue_family_to_ring(int f
) {
243 case RADV_QUEUE_GENERAL
:
245 case RADV_QUEUE_COMPUTE
:
247 case RADV_QUEUE_TRANSFER
:
250 unreachable("Unknown queue family");
254 static VkResult
radv_create_cmd_buffer(
255 struct radv_device
* device
,
256 struct radv_cmd_pool
* pool
,
257 VkCommandBufferLevel level
,
258 VkCommandBuffer
* pCommandBuffer
)
260 struct radv_cmd_buffer
*cmd_buffer
;
262 cmd_buffer
= vk_zalloc(&pool
->alloc
, sizeof(*cmd_buffer
), 8,
263 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
264 if (cmd_buffer
== NULL
)
265 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
267 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
268 cmd_buffer
->device
= device
;
269 cmd_buffer
->pool
= pool
;
270 cmd_buffer
->level
= level
;
273 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
274 cmd_buffer
->queue_family_index
= pool
->queue_family_index
;
277 /* Init the pool_link so we can safely call list_del when we destroy
280 list_inithead(&cmd_buffer
->pool_link
);
281 cmd_buffer
->queue_family_index
= RADV_QUEUE_GENERAL
;
284 ring
= radv_queue_family_to_ring(cmd_buffer
->queue_family_index
);
286 cmd_buffer
->cs
= device
->ws
->cs_create(device
->ws
, ring
);
287 if (!cmd_buffer
->cs
) {
288 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
289 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
292 *pCommandBuffer
= radv_cmd_buffer_to_handle(cmd_buffer
);
294 list_inithead(&cmd_buffer
->upload
.list
);
300 radv_cmd_buffer_destroy(struct radv_cmd_buffer
*cmd_buffer
)
302 list_del(&cmd_buffer
->pool_link
);
304 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
305 &cmd_buffer
->upload
.list
, list
) {
306 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
311 if (cmd_buffer
->upload
.upload_bo
)
312 cmd_buffer
->device
->ws
->buffer_destroy(cmd_buffer
->upload
.upload_bo
);
313 cmd_buffer
->device
->ws
->cs_destroy(cmd_buffer
->cs
);
315 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++)
316 free(cmd_buffer
->descriptors
[i
].push_set
.set
.mapped_ptr
);
318 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
322 radv_reset_cmd_buffer(struct radv_cmd_buffer
*cmd_buffer
)
324 cmd_buffer
->device
->ws
->cs_reset(cmd_buffer
->cs
);
326 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
327 &cmd_buffer
->upload
.list
, list
) {
328 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
333 cmd_buffer
->push_constant_stages
= 0;
334 cmd_buffer
->scratch_size_needed
= 0;
335 cmd_buffer
->compute_scratch_size_needed
= 0;
336 cmd_buffer
->esgs_ring_size_needed
= 0;
337 cmd_buffer
->gsvs_ring_size_needed
= 0;
338 cmd_buffer
->tess_rings_needed
= false;
339 cmd_buffer
->sample_positions_needed
= false;
341 if (cmd_buffer
->upload
.upload_bo
)
342 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
343 cmd_buffer
->upload
.upload_bo
);
344 cmd_buffer
->upload
.offset
= 0;
346 cmd_buffer
->record_result
= VK_SUCCESS
;
348 memset(cmd_buffer
->vertex_bindings
, 0, sizeof(cmd_buffer
->vertex_bindings
));
350 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++) {
351 cmd_buffer
->descriptors
[i
].dirty
= 0;
352 cmd_buffer
->descriptors
[i
].valid
= 0;
353 cmd_buffer
->descriptors
[i
].push_dirty
= false;
356 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
357 cmd_buffer
->queue_family_index
== RADV_QUEUE_GENERAL
) {
358 unsigned num_db
= cmd_buffer
->device
->physical_device
->rad_info
.num_render_backends
;
359 unsigned fence_offset
, eop_bug_offset
;
362 radv_cmd_buffer_upload_alloc(cmd_buffer
, 8, 8, &fence_offset
,
365 cmd_buffer
->gfx9_fence_va
=
366 radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
367 cmd_buffer
->gfx9_fence_va
+= fence_offset
;
369 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
370 /* Allocate a buffer for the EOP bug on GFX9. */
371 radv_cmd_buffer_upload_alloc(cmd_buffer
, 16 * num_db
, 8,
372 &eop_bug_offset
, &fence_ptr
);
373 cmd_buffer
->gfx9_eop_bug_va
=
374 radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
375 cmd_buffer
->gfx9_eop_bug_va
+= eop_bug_offset
;
379 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_INITIAL
;
381 return cmd_buffer
->record_result
;
385 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer
*cmd_buffer
,
389 struct radeon_winsys_bo
*bo
;
390 struct radv_cmd_buffer_upload
*upload
;
391 struct radv_device
*device
= cmd_buffer
->device
;
393 new_size
= MAX2(min_needed
, 16 * 1024);
394 new_size
= MAX2(new_size
, 2 * cmd_buffer
->upload
.size
);
396 bo
= device
->ws
->buffer_create(device
->ws
,
399 RADEON_FLAG_CPU_ACCESS
|
400 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
402 RADV_BO_PRIORITY_UPLOAD_BUFFER
);
405 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
409 radv_cs_add_buffer(device
->ws
, cmd_buffer
->cs
, bo
);
410 if (cmd_buffer
->upload
.upload_bo
) {
411 upload
= malloc(sizeof(*upload
));
414 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
415 device
->ws
->buffer_destroy(bo
);
419 memcpy(upload
, &cmd_buffer
->upload
, sizeof(*upload
));
420 list_add(&upload
->list
, &cmd_buffer
->upload
.list
);
423 cmd_buffer
->upload
.upload_bo
= bo
;
424 cmd_buffer
->upload
.size
= new_size
;
425 cmd_buffer
->upload
.offset
= 0;
426 cmd_buffer
->upload
.map
= device
->ws
->buffer_map(cmd_buffer
->upload
.upload_bo
);
428 if (!cmd_buffer
->upload
.map
) {
429 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
437 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
440 unsigned *out_offset
,
443 assert(util_is_power_of_two_nonzero(alignment
));
445 uint64_t offset
= align(cmd_buffer
->upload
.offset
, alignment
);
446 if (offset
+ size
> cmd_buffer
->upload
.size
) {
447 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer
, size
))
452 *out_offset
= offset
;
453 *ptr
= cmd_buffer
->upload
.map
+ offset
;
455 cmd_buffer
->upload
.offset
= offset
+ size
;
460 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
461 unsigned size
, unsigned alignment
,
462 const void *data
, unsigned *out_offset
)
466 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
, alignment
,
467 out_offset
, (void **)&ptr
))
471 memcpy(ptr
, data
, size
);
477 radv_emit_write_data_packet(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
478 unsigned count
, const uint32_t *data
)
480 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
482 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 4 + count
);
484 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, 0));
485 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
486 S_370_WR_CONFIRM(1) |
487 S_370_ENGINE_SEL(V_370_ME
));
489 radeon_emit(cs
, va
>> 32);
490 radeon_emit_array(cs
, data
, count
);
493 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
)
495 struct radv_device
*device
= cmd_buffer
->device
;
496 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
499 va
= radv_buffer_get_va(device
->trace_bo
);
500 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
)
503 ++cmd_buffer
->state
.trace_id
;
504 radv_emit_write_data_packet(cmd_buffer
, va
, 1,
505 &cmd_buffer
->state
.trace_id
);
507 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 2);
509 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
510 radeon_emit(cs
, AC_ENCODE_TRACE_POINT(cmd_buffer
->state
.trace_id
));
514 radv_cmd_buffer_after_draw(struct radv_cmd_buffer
*cmd_buffer
,
515 enum radv_cmd_flush_bits flags
)
517 if (cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_SYNC_SHADERS
) {
518 assert(flags
& (RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
519 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
));
521 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 4);
523 /* Force wait for graphics or compute engines to be idle. */
524 si_cs_emit_cache_flush(cmd_buffer
->cs
,
525 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
526 &cmd_buffer
->gfx9_fence_idx
,
527 cmd_buffer
->gfx9_fence_va
,
528 radv_cmd_buffer_uses_mec(cmd_buffer
),
529 flags
, cmd_buffer
->gfx9_eop_bug_va
);
532 if (unlikely(cmd_buffer
->device
->trace_bo
))
533 radv_cmd_buffer_trace_emit(cmd_buffer
);
537 radv_save_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
538 struct radv_pipeline
*pipeline
, enum ring_type ring
)
540 struct radv_device
*device
= cmd_buffer
->device
;
544 va
= radv_buffer_get_va(device
->trace_bo
);
554 assert(!"invalid ring type");
557 data
[0] = (uintptr_t)pipeline
;
558 data
[1] = (uintptr_t)pipeline
>> 32;
560 radv_emit_write_data_packet(cmd_buffer
, va
, 2, data
);
563 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
564 VkPipelineBindPoint bind_point
,
565 struct radv_descriptor_set
*set
,
568 struct radv_descriptor_state
*descriptors_state
=
569 radv_get_descriptors_state(cmd_buffer
, bind_point
);
571 descriptors_state
->sets
[idx
] = set
;
573 descriptors_state
->valid
|= (1u << idx
); /* active descriptors */
574 descriptors_state
->dirty
|= (1u << idx
);
578 radv_save_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
579 VkPipelineBindPoint bind_point
)
581 struct radv_descriptor_state
*descriptors_state
=
582 radv_get_descriptors_state(cmd_buffer
, bind_point
);
583 struct radv_device
*device
= cmd_buffer
->device
;
584 uint32_t data
[MAX_SETS
* 2] = {};
587 va
= radv_buffer_get_va(device
->trace_bo
) + 24;
589 for_each_bit(i
, descriptors_state
->valid
) {
590 struct radv_descriptor_set
*set
= descriptors_state
->sets
[i
];
591 data
[i
* 2] = (uint64_t)(uintptr_t)set
;
592 data
[i
* 2 + 1] = (uint64_t)(uintptr_t)set
>> 32;
595 radv_emit_write_data_packet(cmd_buffer
, va
, MAX_SETS
* 2, data
);
598 struct radv_userdata_info
*
599 radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
600 gl_shader_stage stage
,
603 struct radv_shader_variant
*shader
= radv_get_shader(pipeline
, stage
);
604 return &shader
->info
.user_sgprs_locs
.shader_data
[idx
];
608 radv_emit_userdata_address(struct radv_cmd_buffer
*cmd_buffer
,
609 struct radv_pipeline
*pipeline
,
610 gl_shader_stage stage
,
611 int idx
, uint64_t va
)
613 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, idx
);
614 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
615 if (loc
->sgpr_idx
== -1)
618 assert(loc
->num_sgprs
== 1);
620 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
621 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
625 radv_emit_descriptor_pointers(struct radv_cmd_buffer
*cmd_buffer
,
626 struct radv_pipeline
*pipeline
,
627 struct radv_descriptor_state
*descriptors_state
,
628 gl_shader_stage stage
)
630 struct radv_device
*device
= cmd_buffer
->device
;
631 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
632 uint32_t sh_base
= pipeline
->user_data_0
[stage
];
633 struct radv_userdata_locations
*locs
=
634 &pipeline
->shaders
[stage
]->info
.user_sgprs_locs
;
635 unsigned mask
= locs
->descriptor_sets_enabled
;
637 mask
&= descriptors_state
->dirty
& descriptors_state
->valid
;
642 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
644 struct radv_userdata_info
*loc
= &locs
->descriptor_sets
[start
];
645 unsigned sh_offset
= sh_base
+ loc
->sgpr_idx
* 4;
647 radv_emit_shader_pointer_head(cs
, sh_offset
, count
, true);
648 for (int i
= 0; i
< count
; i
++) {
649 struct radv_descriptor_set
*set
=
650 descriptors_state
->sets
[start
+ i
];
652 radv_emit_shader_pointer_body(device
, cs
, set
->va
, true);
658 * Convert the user sample locations to hardware sample locations (the values
659 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
662 radv_convert_user_sample_locs(struct radv_sample_locations_state
*state
,
663 uint32_t x
, uint32_t y
, VkOffset2D
*sample_locs
)
665 uint32_t x_offset
= x
% state
->grid_size
.width
;
666 uint32_t y_offset
= y
% state
->grid_size
.height
;
667 uint32_t num_samples
= (uint32_t)state
->per_pixel
;
668 VkSampleLocationEXT
*user_locs
;
669 uint32_t pixel_offset
;
671 pixel_offset
= (x_offset
+ y_offset
* state
->grid_size
.width
) * num_samples
;
673 assert(pixel_offset
<= MAX_SAMPLE_LOCATIONS
);
674 user_locs
= &state
->locations
[pixel_offset
];
676 for (uint32_t i
= 0; i
< num_samples
; i
++) {
677 float shifted_pos_x
= user_locs
[i
].x
- 0.5;
678 float shifted_pos_y
= user_locs
[i
].y
- 0.5;
680 int32_t scaled_pos_x
= floor(shifted_pos_x
* 16);
681 int32_t scaled_pos_y
= floor(shifted_pos_y
* 16);
683 sample_locs
[i
].x
= CLAMP(scaled_pos_x
, -8, 7);
684 sample_locs
[i
].y
= CLAMP(scaled_pos_y
, -8, 7);
689 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
693 radv_compute_sample_locs_pixel(uint32_t num_samples
, VkOffset2D
*sample_locs
,
694 uint32_t *sample_locs_pixel
)
696 for (uint32_t i
= 0; i
< num_samples
; i
++) {
697 uint32_t sample_reg_idx
= i
/ 4;
698 uint32_t sample_loc_idx
= i
% 4;
699 int32_t pos_x
= sample_locs
[i
].x
;
700 int32_t pos_y
= sample_locs
[i
].y
;
702 uint32_t shift_x
= 8 * sample_loc_idx
;
703 uint32_t shift_y
= shift_x
+ 4;
705 sample_locs_pixel
[sample_reg_idx
] |= (pos_x
& 0xf) << shift_x
;
706 sample_locs_pixel
[sample_reg_idx
] |= (pos_y
& 0xf) << shift_y
;
711 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
715 radv_compute_centroid_priority(struct radv_cmd_buffer
*cmd_buffer
,
716 VkOffset2D
*sample_locs
,
717 uint32_t num_samples
)
719 uint32_t centroid_priorities
[num_samples
];
720 uint32_t sample_mask
= num_samples
- 1;
721 uint32_t distances
[num_samples
];
722 uint64_t centroid_priority
= 0;
724 /* Compute the distances from center for each sample. */
725 for (int i
= 0; i
< num_samples
; i
++) {
726 distances
[i
] = (sample_locs
[i
].x
* sample_locs
[i
].x
) +
727 (sample_locs
[i
].y
* sample_locs
[i
].y
);
730 /* Compute the centroid priorities by looking at the distances array. */
731 for (int i
= 0; i
< num_samples
; i
++) {
732 uint32_t min_idx
= 0;
734 for (int j
= 1; j
< num_samples
; j
++) {
735 if (distances
[j
] < distances
[min_idx
])
739 centroid_priorities
[i
] = min_idx
;
740 distances
[min_idx
] = 0xffffffff;
743 /* Compute the final centroid priority. */
744 for (int i
= 0; i
< 8; i
++) {
746 centroid_priorities
[i
& sample_mask
] << (i
* 4);
749 return centroid_priority
<< 32 | centroid_priority
;
753 * Emit the sample locations that are specified with VK_EXT_sample_locations.
756 radv_emit_sample_locations(struct radv_cmd_buffer
*cmd_buffer
)
758 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
759 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
760 struct radv_sample_locations_state
*sample_location
=
761 &cmd_buffer
->state
.dynamic
.sample_location
;
762 uint32_t num_samples
= (uint32_t)sample_location
->per_pixel
;
763 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
764 uint32_t sample_locs_pixel
[4][2] = {};
765 VkOffset2D sample_locs
[4][8]; /* 8 is the max. sample count supported */
766 uint32_t max_sample_dist
= 0;
767 uint64_t centroid_priority
;
769 if (!cmd_buffer
->state
.dynamic
.sample_location
.count
)
772 /* Convert the user sample locations to hardware sample locations. */
773 radv_convert_user_sample_locs(sample_location
, 0, 0, sample_locs
[0]);
774 radv_convert_user_sample_locs(sample_location
, 1, 0, sample_locs
[1]);
775 radv_convert_user_sample_locs(sample_location
, 0, 1, sample_locs
[2]);
776 radv_convert_user_sample_locs(sample_location
, 1, 1, sample_locs
[3]);
778 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
779 for (uint32_t i
= 0; i
< 4; i
++) {
780 radv_compute_sample_locs_pixel(num_samples
, sample_locs
[i
],
781 sample_locs_pixel
[i
]);
784 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
786 radv_compute_centroid_priority(cmd_buffer
, sample_locs
[0],
789 /* Compute the maximum sample distance from the specified locations. */
790 for (uint32_t i
= 0; i
< num_samples
; i
++) {
791 VkOffset2D offset
= sample_locs
[0][i
];
792 max_sample_dist
= MAX2(max_sample_dist
,
793 MAX2(abs(offset
.x
), abs(offset
.y
)));
796 /* Emit the specified user sample locations. */
797 switch (num_samples
) {
800 radeon_set_context_reg(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_pixel
[0][0]);
801 radeon_set_context_reg(cs
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_pixel
[1][0]);
802 radeon_set_context_reg(cs
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_pixel
[2][0]);
803 radeon_set_context_reg(cs
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_pixel
[3][0]);
806 radeon_set_context_reg(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_pixel
[0][0]);
807 radeon_set_context_reg(cs
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_pixel
[1][0]);
808 radeon_set_context_reg(cs
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_pixel
[2][0]);
809 radeon_set_context_reg(cs
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_pixel
[3][0]);
810 radeon_set_context_reg(cs
, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1
, sample_locs_pixel
[0][1]);
811 radeon_set_context_reg(cs
, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1
, sample_locs_pixel
[1][1]);
812 radeon_set_context_reg(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1
, sample_locs_pixel
[2][1]);
813 radeon_set_context_reg(cs
, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1
, sample_locs_pixel
[3][1]);
816 unreachable("invalid number of samples");
819 /* Emit the maximum sample distance and the centroid priority. */
820 uint32_t pa_sc_aa_config
= ms
->pa_sc_aa_config
;
822 pa_sc_aa_config
&= C_028BE0_MAX_SAMPLE_DIST
;
823 pa_sc_aa_config
|= S_028BE0_MAX_SAMPLE_DIST(max_sample_dist
);
825 radeon_set_context_reg_seq(cs
, R_028BE0_PA_SC_AA_CONFIG
, 1);
826 radeon_emit(cs
, pa_sc_aa_config
);
828 radeon_set_context_reg_seq(cs
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 2);
829 radeon_emit(cs
, centroid_priority
);
830 radeon_emit(cs
, centroid_priority
>> 32);
832 /* GFX9: Flush DFSM when the AA mode changes. */
833 if (cmd_buffer
->device
->dfsm_allowed
) {
834 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
835 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
838 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
842 radv_emit_inline_push_consts(struct radv_cmd_buffer
*cmd_buffer
,
843 struct radv_pipeline
*pipeline
,
844 gl_shader_stage stage
,
845 int idx
, int count
, uint32_t *values
)
847 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, idx
);
848 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
849 if (loc
->sgpr_idx
== -1)
852 assert(loc
->num_sgprs
== count
);
854 radeon_set_sh_reg_seq(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, count
);
855 radeon_emit_array(cmd_buffer
->cs
, values
, count
);
859 radv_update_multisample_state(struct radv_cmd_buffer
*cmd_buffer
,
860 struct radv_pipeline
*pipeline
)
862 int num_samples
= pipeline
->graphics
.ms
.num_samples
;
863 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
864 struct radv_pipeline
*old_pipeline
= cmd_buffer
->state
.emitted_pipeline
;
866 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.needs_sample_positions
)
867 cmd_buffer
->sample_positions_needed
= true;
869 if (old_pipeline
&& num_samples
== old_pipeline
->graphics
.ms
.num_samples
)
872 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028BDC_PA_SC_LINE_CNTL
, 2);
873 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_line_cntl
);
874 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_config
);
876 radeon_set_context_reg(cmd_buffer
->cs
, R_028A48_PA_SC_MODE_CNTL_0
, ms
->pa_sc_mode_cntl_0
);
878 radv_emit_default_sample_locations(cmd_buffer
->cs
, num_samples
);
880 /* GFX9: Flush DFSM when the AA mode changes. */
881 if (cmd_buffer
->device
->dfsm_allowed
) {
882 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
883 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
886 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
890 radv_update_binning_state(struct radv_cmd_buffer
*cmd_buffer
,
891 struct radv_pipeline
*pipeline
)
893 const struct radv_pipeline
*old_pipeline
= cmd_buffer
->state
.emitted_pipeline
;
896 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX9
)
900 old_pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
== pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
&&
901 old_pipeline
->graphics
.binning
.db_dfsm_control
== pipeline
->graphics
.binning
.db_dfsm_control
)
904 bool binning_flush
= false;
905 if (cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_VEGA12
||
906 cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_VEGA20
||
907 cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_RAVEN2
||
908 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
909 binning_flush
= !old_pipeline
||
910 G_028C44_BINNING_MODE(old_pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
) !=
911 G_028C44_BINNING_MODE(pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
);
914 radeon_set_context_reg(cmd_buffer
->cs
, R_028C44_PA_SC_BINNER_CNTL_0
,
915 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
|
916 S_028C44_FLUSH_ON_BINNING_TRANSITION(!!binning_flush
));
918 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
919 radeon_set_context_reg(cmd_buffer
->cs
, R_028038_DB_DFSM_CONTROL
,
920 pipeline
->graphics
.binning
.db_dfsm_control
);
922 radeon_set_context_reg(cmd_buffer
->cs
, R_028060_DB_DFSM_CONTROL
,
923 pipeline
->graphics
.binning
.db_dfsm_control
);
926 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
931 radv_emit_shader_prefetch(struct radv_cmd_buffer
*cmd_buffer
,
932 struct radv_shader_variant
*shader
)
939 va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
941 si_cp_dma_prefetch(cmd_buffer
, va
, shader
->code_size
);
945 radv_emit_prefetch_L2(struct radv_cmd_buffer
*cmd_buffer
,
946 struct radv_pipeline
*pipeline
,
947 bool vertex_stage_only
)
949 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
950 uint32_t mask
= state
->prefetch_L2_mask
;
952 if (vertex_stage_only
) {
953 /* Fast prefetch path for starting draws as soon as possible.
955 mask
= state
->prefetch_L2_mask
& (RADV_PREFETCH_VS
|
956 RADV_PREFETCH_VBO_DESCRIPTORS
);
959 if (mask
& RADV_PREFETCH_VS
)
960 radv_emit_shader_prefetch(cmd_buffer
,
961 pipeline
->shaders
[MESA_SHADER_VERTEX
]);
963 if (mask
& RADV_PREFETCH_VBO_DESCRIPTORS
)
964 si_cp_dma_prefetch(cmd_buffer
, state
->vb_va
, state
->vb_size
);
966 if (mask
& RADV_PREFETCH_TCS
)
967 radv_emit_shader_prefetch(cmd_buffer
,
968 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]);
970 if (mask
& RADV_PREFETCH_TES
)
971 radv_emit_shader_prefetch(cmd_buffer
,
972 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]);
974 if (mask
& RADV_PREFETCH_GS
) {
975 radv_emit_shader_prefetch(cmd_buffer
,
976 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]);
977 if (radv_pipeline_has_gs_copy_shader(pipeline
))
978 radv_emit_shader_prefetch(cmd_buffer
, pipeline
->gs_copy_shader
);
981 if (mask
& RADV_PREFETCH_PS
)
982 radv_emit_shader_prefetch(cmd_buffer
,
983 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
985 state
->prefetch_L2_mask
&= ~mask
;
989 radv_emit_rbplus_state(struct radv_cmd_buffer
*cmd_buffer
)
991 if (!cmd_buffer
->device
->physical_device
->rbplus_allowed
)
994 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
995 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
997 unsigned sx_ps_downconvert
= 0;
998 unsigned sx_blend_opt_epsilon
= 0;
999 unsigned sx_blend_opt_control
= 0;
1001 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1002 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
1003 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
1004 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
1008 int idx
= subpass
->color_attachments
[i
].attachment
;
1009 struct radv_color_buffer_info
*cb
= &cmd_buffer
->state
.attachments
[idx
].cb
;
1011 unsigned format
= G_028C70_FORMAT(cb
->cb_color_info
);
1012 unsigned swap
= G_028C70_COMP_SWAP(cb
->cb_color_info
);
1013 uint32_t spi_format
= (pipeline
->graphics
.col_format
>> (i
* 4)) & 0xf;
1014 uint32_t colormask
= (pipeline
->graphics
.cb_target_mask
>> (i
* 4)) & 0xf;
1016 bool has_alpha
, has_rgb
;
1018 /* Set if RGB and A are present. */
1019 has_alpha
= !G_028C74_FORCE_DST_ALPHA_1(cb
->cb_color_attrib
);
1021 if (format
== V_028C70_COLOR_8
||
1022 format
== V_028C70_COLOR_16
||
1023 format
== V_028C70_COLOR_32
)
1024 has_rgb
= !has_alpha
;
1028 /* Check the colormask and export format. */
1029 if (!(colormask
& 0x7))
1031 if (!(colormask
& 0x8))
1034 if (spi_format
== V_028714_SPI_SHADER_ZERO
) {
1039 /* Disable value checking for disabled channels. */
1041 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
1043 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
1045 /* Enable down-conversion for 32bpp and smaller formats. */
1047 case V_028C70_COLOR_8
:
1048 case V_028C70_COLOR_8_8
:
1049 case V_028C70_COLOR_8_8_8_8
:
1050 /* For 1 and 2-channel formats, use the superset thereof. */
1051 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
||
1052 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
1053 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
1054 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_8_8_8_8
<< (i
* 4);
1055 sx_blend_opt_epsilon
|= V_028758_8BIT_FORMAT
<< (i
* 4);
1059 case V_028C70_COLOR_5_6_5
:
1060 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1061 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_5_6_5
<< (i
* 4);
1062 sx_blend_opt_epsilon
|= V_028758_6BIT_FORMAT
<< (i
* 4);
1066 case V_028C70_COLOR_1_5_5_5
:
1067 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1068 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_1_5_5_5
<< (i
* 4);
1069 sx_blend_opt_epsilon
|= V_028758_5BIT_FORMAT
<< (i
* 4);
1073 case V_028C70_COLOR_4_4_4_4
:
1074 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1075 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_4_4_4_4
<< (i
* 4);
1076 sx_blend_opt_epsilon
|= V_028758_4BIT_FORMAT
<< (i
* 4);
1080 case V_028C70_COLOR_32
:
1081 if (swap
== V_028C70_SWAP_STD
&&
1082 spi_format
== V_028714_SPI_SHADER_32_R
)
1083 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
1084 else if (swap
== V_028C70_SWAP_ALT_REV
&&
1085 spi_format
== V_028714_SPI_SHADER_32_AR
)
1086 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_A
<< (i
* 4);
1089 case V_028C70_COLOR_16
:
1090 case V_028C70_COLOR_16_16
:
1091 /* For 1-channel formats, use the superset thereof. */
1092 if (spi_format
== V_028714_SPI_SHADER_UNORM16_ABGR
||
1093 spi_format
== V_028714_SPI_SHADER_SNORM16_ABGR
||
1094 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
1095 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
1096 if (swap
== V_028C70_SWAP_STD
||
1097 swap
== V_028C70_SWAP_STD_REV
)
1098 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_GR
<< (i
* 4);
1100 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_AR
<< (i
* 4);
1104 case V_028C70_COLOR_10_11_11
:
1105 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1106 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_10_11_11
<< (i
* 4);
1107 sx_blend_opt_epsilon
|= V_028758_11BIT_FORMAT
<< (i
* 4);
1111 case V_028C70_COLOR_2_10_10_10
:
1112 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1113 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_2_10_10_10
<< (i
* 4);
1114 sx_blend_opt_epsilon
|= V_028758_10BIT_FORMAT
<< (i
* 4);
1120 for (unsigned i
= subpass
->color_count
; i
< 8; ++i
) {
1121 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
1122 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
1124 /* TODO: avoid redundantly setting context registers */
1125 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
1126 radeon_emit(cmd_buffer
->cs
, sx_ps_downconvert
);
1127 radeon_emit(cmd_buffer
->cs
, sx_blend_opt_epsilon
);
1128 radeon_emit(cmd_buffer
->cs
, sx_blend_opt_control
);
1130 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1134 radv_emit_graphics_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
1136 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1138 if (!pipeline
|| cmd_buffer
->state
.emitted_pipeline
== pipeline
)
1141 radv_update_multisample_state(cmd_buffer
, pipeline
);
1142 radv_update_binning_state(cmd_buffer
, pipeline
);
1144 cmd_buffer
->scratch_size_needed
=
1145 MAX2(cmd_buffer
->scratch_size_needed
,
1146 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
1148 if (!cmd_buffer
->state
.emitted_pipeline
||
1149 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
!=
1150 pipeline
->graphics
.can_use_guardband
)
1151 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
1153 radeon_emit_array(cmd_buffer
->cs
, pipeline
->cs
.buf
, pipeline
->cs
.cdw
);
1155 if (!cmd_buffer
->state
.emitted_pipeline
||
1156 cmd_buffer
->state
.emitted_pipeline
->ctx_cs
.cdw
!= pipeline
->ctx_cs
.cdw
||
1157 cmd_buffer
->state
.emitted_pipeline
->ctx_cs_hash
!= pipeline
->ctx_cs_hash
||
1158 memcmp(cmd_buffer
->state
.emitted_pipeline
->ctx_cs
.buf
,
1159 pipeline
->ctx_cs
.buf
, pipeline
->ctx_cs
.cdw
* 4)) {
1160 radeon_emit_array(cmd_buffer
->cs
, pipeline
->ctx_cs
.buf
, pipeline
->ctx_cs
.cdw
);
1161 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1164 for (unsigned i
= 0; i
< MESA_SHADER_COMPUTE
; i
++) {
1165 if (!pipeline
->shaders
[i
])
1168 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
1169 pipeline
->shaders
[i
]->bo
);
1172 if (radv_pipeline_has_gs_copy_shader(pipeline
))
1173 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
1174 pipeline
->gs_copy_shader
->bo
);
1176 if (unlikely(cmd_buffer
->device
->trace_bo
))
1177 radv_save_pipeline(cmd_buffer
, pipeline
, RING_GFX
);
1179 cmd_buffer
->state
.emitted_pipeline
= pipeline
;
1181 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_PIPELINE
;
1185 radv_emit_viewport(struct radv_cmd_buffer
*cmd_buffer
)
1187 si_write_viewport(cmd_buffer
->cs
, 0, cmd_buffer
->state
.dynamic
.viewport
.count
,
1188 cmd_buffer
->state
.dynamic
.viewport
.viewports
);
1192 radv_emit_scissor(struct radv_cmd_buffer
*cmd_buffer
)
1194 uint32_t count
= cmd_buffer
->state
.dynamic
.scissor
.count
;
1196 si_write_scissors(cmd_buffer
->cs
, 0, count
,
1197 cmd_buffer
->state
.dynamic
.scissor
.scissors
,
1198 cmd_buffer
->state
.dynamic
.viewport
.viewports
,
1199 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
);
1201 cmd_buffer
->state
.context_roll_without_scissor_emitted
= false;
1205 radv_emit_discard_rectangle(struct radv_cmd_buffer
*cmd_buffer
)
1207 if (!cmd_buffer
->state
.dynamic
.discard_rectangle
.count
)
1210 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028210_PA_SC_CLIPRECT_0_TL
,
1211 cmd_buffer
->state
.dynamic
.discard_rectangle
.count
* 2);
1212 for (unsigned i
= 0; i
< cmd_buffer
->state
.dynamic
.discard_rectangle
.count
; ++i
) {
1213 VkRect2D rect
= cmd_buffer
->state
.dynamic
.discard_rectangle
.rectangles
[i
];
1214 radeon_emit(cmd_buffer
->cs
, S_028210_TL_X(rect
.offset
.x
) | S_028210_TL_Y(rect
.offset
.y
));
1215 radeon_emit(cmd_buffer
->cs
, S_028214_BR_X(rect
.offset
.x
+ rect
.extent
.width
) |
1216 S_028214_BR_Y(rect
.offset
.y
+ rect
.extent
.height
));
1221 radv_emit_line_width(struct radv_cmd_buffer
*cmd_buffer
)
1223 unsigned width
= cmd_buffer
->state
.dynamic
.line_width
* 8;
1225 radeon_set_context_reg(cmd_buffer
->cs
, R_028A08_PA_SU_LINE_CNTL
,
1226 S_028A08_WIDTH(CLAMP(width
, 0, 0xFFF)));
1230 radv_emit_blend_constants(struct radv_cmd_buffer
*cmd_buffer
)
1232 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1234 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028414_CB_BLEND_RED
, 4);
1235 radeon_emit_array(cmd_buffer
->cs
, (uint32_t *)d
->blend_constants
, 4);
1239 radv_emit_stencil(struct radv_cmd_buffer
*cmd_buffer
)
1241 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1243 radeon_set_context_reg_seq(cmd_buffer
->cs
,
1244 R_028430_DB_STENCILREFMASK
, 2);
1245 radeon_emit(cmd_buffer
->cs
,
1246 S_028430_STENCILTESTVAL(d
->stencil_reference
.front
) |
1247 S_028430_STENCILMASK(d
->stencil_compare_mask
.front
) |
1248 S_028430_STENCILWRITEMASK(d
->stencil_write_mask
.front
) |
1249 S_028430_STENCILOPVAL(1));
1250 radeon_emit(cmd_buffer
->cs
,
1251 S_028434_STENCILTESTVAL_BF(d
->stencil_reference
.back
) |
1252 S_028434_STENCILMASK_BF(d
->stencil_compare_mask
.back
) |
1253 S_028434_STENCILWRITEMASK_BF(d
->stencil_write_mask
.back
) |
1254 S_028434_STENCILOPVAL_BF(1));
1258 radv_emit_depth_bounds(struct radv_cmd_buffer
*cmd_buffer
)
1260 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1262 radeon_set_context_reg(cmd_buffer
->cs
, R_028020_DB_DEPTH_BOUNDS_MIN
,
1263 fui(d
->depth_bounds
.min
));
1264 radeon_set_context_reg(cmd_buffer
->cs
, R_028024_DB_DEPTH_BOUNDS_MAX
,
1265 fui(d
->depth_bounds
.max
));
1269 radv_emit_depth_bias(struct radv_cmd_buffer
*cmd_buffer
)
1271 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1272 unsigned slope
= fui(d
->depth_bias
.slope
* 16.0f
);
1273 unsigned bias
= fui(d
->depth_bias
.bias
* cmd_buffer
->state
.offset_scale
);
1276 radeon_set_context_reg_seq(cmd_buffer
->cs
,
1277 R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, 5);
1278 radeon_emit(cmd_buffer
->cs
, fui(d
->depth_bias
.clamp
)); /* CLAMP */
1279 radeon_emit(cmd_buffer
->cs
, slope
); /* FRONT SCALE */
1280 radeon_emit(cmd_buffer
->cs
, bias
); /* FRONT OFFSET */
1281 radeon_emit(cmd_buffer
->cs
, slope
); /* BACK SCALE */
1282 radeon_emit(cmd_buffer
->cs
, bias
); /* BACK OFFSET */
1286 radv_emit_fb_color_state(struct radv_cmd_buffer
*cmd_buffer
,
1288 struct radv_color_buffer_info
*cb
,
1289 struct radv_image_view
*iview
,
1290 VkImageLayout layout
,
1291 bool in_render_loop
)
1293 bool is_vi
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX8
;
1294 uint32_t cb_color_info
= cb
->cb_color_info
;
1295 struct radv_image
*image
= iview
->image
;
1297 if (!radv_layout_dcc_compressed(cmd_buffer
->device
, image
, layout
, in_render_loop
,
1298 radv_image_queue_family_mask(image
,
1299 cmd_buffer
->queue_family_index
,
1300 cmd_buffer
->queue_family_index
))) {
1301 cb_color_info
&= C_028C70_DCC_ENABLE
;
1304 if (radv_image_is_tc_compat_cmask(image
) &&
1305 (radv_is_fmask_decompress_pipeline(cmd_buffer
) ||
1306 radv_is_dcc_decompress_pipeline(cmd_buffer
))) {
1307 /* If this bit is set, the FMASK decompression operation
1308 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1310 cb_color_info
&= C_028C70_FMASK_COMPRESS_1FRAG_ONLY
;
1313 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
1314 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1315 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1316 radeon_emit(cmd_buffer
->cs
, 0);
1317 radeon_emit(cmd_buffer
->cs
, 0);
1318 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1319 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1320 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1321 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1322 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1323 radeon_emit(cmd_buffer
->cs
, 0);
1324 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1325 radeon_emit(cmd_buffer
->cs
, 0);
1327 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, 1);
1328 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
);
1330 radeon_set_context_reg(cmd_buffer
->cs
, R_028E40_CB_COLOR0_BASE_EXT
+ index
* 4,
1331 cb
->cb_color_base
>> 32);
1332 radeon_set_context_reg(cmd_buffer
->cs
, R_028E60_CB_COLOR0_CMASK_BASE_EXT
+ index
* 4,
1333 cb
->cb_color_cmask
>> 32);
1334 radeon_set_context_reg(cmd_buffer
->cs
, R_028E80_CB_COLOR0_FMASK_BASE_EXT
+ index
* 4,
1335 cb
->cb_color_fmask
>> 32);
1336 radeon_set_context_reg(cmd_buffer
->cs
, R_028EA0_CB_COLOR0_DCC_BASE_EXT
+ index
* 4,
1337 cb
->cb_dcc_base
>> 32);
1338 radeon_set_context_reg(cmd_buffer
->cs
, R_028EC0_CB_COLOR0_ATTRIB2
+ index
* 4,
1339 cb
->cb_color_attrib2
);
1340 radeon_set_context_reg(cmd_buffer
->cs
, R_028EE0_CB_COLOR0_ATTRIB3
+ index
* 4,
1341 cb
->cb_color_attrib3
);
1342 } else if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
1343 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1344 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1345 radeon_emit(cmd_buffer
->cs
, S_028C64_BASE_256B(cb
->cb_color_base
>> 32));
1346 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib2
);
1347 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1348 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1349 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1350 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1351 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1352 radeon_emit(cmd_buffer
->cs
, S_028C80_BASE_256B(cb
->cb_color_cmask
>> 32));
1353 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1354 radeon_emit(cmd_buffer
->cs
, S_028C88_BASE_256B(cb
->cb_color_fmask
>> 32));
1356 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, 2);
1357 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
);
1358 radeon_emit(cmd_buffer
->cs
, S_028C98_BASE_256B(cb
->cb_dcc_base
>> 32));
1360 radeon_set_context_reg(cmd_buffer
->cs
, R_0287A0_CB_MRT0_EPITCH
+ index
* 4,
1363 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1364 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1365 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_pitch
);
1366 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_slice
);
1367 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1368 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1369 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1370 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1371 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1372 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask_slice
);
1373 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1374 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask_slice
);
1376 if (is_vi
) { /* DCC BASE */
1377 radeon_set_context_reg(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, cb
->cb_dcc_base
);
1381 if (radv_dcc_enabled(image
, iview
->base_mip
)) {
1382 /* Drawing with DCC enabled also compresses colorbuffers. */
1383 VkImageSubresourceRange range
= {
1384 .aspectMask
= iview
->aspect_mask
,
1385 .baseMipLevel
= iview
->base_mip
,
1386 .levelCount
= iview
->level_count
,
1387 .baseArrayLayer
= iview
->base_layer
,
1388 .layerCount
= iview
->layer_count
,
1391 radv_update_dcc_metadata(cmd_buffer
, image
, &range
, true);
1396 radv_update_zrange_precision(struct radv_cmd_buffer
*cmd_buffer
,
1397 struct radv_ds_buffer_info
*ds
,
1398 const struct radv_image_view
*iview
,
1399 VkImageLayout layout
,
1400 bool in_render_loop
, bool requires_cond_exec
)
1402 const struct radv_image
*image
= iview
->image
;
1403 uint32_t db_z_info
= ds
->db_z_info
;
1404 uint32_t db_z_info_reg
;
1406 if (!cmd_buffer
->device
->physical_device
->has_tc_compat_zrange_bug
||
1407 !radv_image_is_tc_compat_htile(image
))
1410 if (!radv_layout_has_htile(image
, layout
, in_render_loop
,
1411 radv_image_queue_family_mask(image
,
1412 cmd_buffer
->queue_family_index
,
1413 cmd_buffer
->queue_family_index
))) {
1414 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
1417 db_z_info
&= C_028040_ZRANGE_PRECISION
;
1419 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
1420 db_z_info_reg
= R_028038_DB_Z_INFO
;
1422 db_z_info_reg
= R_028040_DB_Z_INFO
;
1425 /* When we don't know the last fast clear value we need to emit a
1426 * conditional packet that will eventually skip the following
1427 * SET_CONTEXT_REG packet.
1429 if (requires_cond_exec
) {
1430 uint64_t va
= radv_get_tc_compat_zrange_va(image
, iview
->base_mip
);
1432 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_COND_EXEC
, 3, 0));
1433 radeon_emit(cmd_buffer
->cs
, va
);
1434 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1435 radeon_emit(cmd_buffer
->cs
, 0);
1436 radeon_emit(cmd_buffer
->cs
, 3); /* SET_CONTEXT_REG size */
1439 radeon_set_context_reg(cmd_buffer
->cs
, db_z_info_reg
, db_z_info
);
1443 radv_emit_fb_ds_state(struct radv_cmd_buffer
*cmd_buffer
,
1444 struct radv_ds_buffer_info
*ds
,
1445 struct radv_image_view
*iview
,
1446 VkImageLayout layout
,
1447 bool in_render_loop
)
1449 const struct radv_image
*image
= iview
->image
;
1450 uint32_t db_z_info
= ds
->db_z_info
;
1451 uint32_t db_stencil_info
= ds
->db_stencil_info
;
1453 if (!radv_layout_has_htile(image
, layout
, in_render_loop
,
1454 radv_image_queue_family_mask(image
,
1455 cmd_buffer
->queue_family_index
,
1456 cmd_buffer
->queue_family_index
))) {
1457 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
1458 db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
1461 radeon_set_context_reg(cmd_buffer
->cs
, R_028008_DB_DEPTH_VIEW
, ds
->db_depth_view
);
1462 radeon_set_context_reg(cmd_buffer
->cs
, R_028ABC_DB_HTILE_SURFACE
, ds
->db_htile_surface
);
1464 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
1465 radeon_set_context_reg(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, ds
->db_htile_data_base
);
1466 radeon_set_context_reg(cmd_buffer
->cs
, R_02801C_DB_DEPTH_SIZE_XY
, ds
->db_depth_size
);
1468 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_02803C_DB_DEPTH_INFO
, 7);
1469 radeon_emit(cmd_buffer
->cs
, S_02803C_RESOURCE_LEVEL(1));
1470 radeon_emit(cmd_buffer
->cs
, db_z_info
);
1471 radeon_emit(cmd_buffer
->cs
, db_stencil_info
);
1472 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
);
1473 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
);
1474 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
);
1475 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
);
1477 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028068_DB_Z_READ_BASE_HI
, 5);
1478 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
>> 32);
1479 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
>> 32);
1480 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
>> 32);
1481 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
>> 32);
1482 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
>> 32);
1483 } else if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
1484 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
1485 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
);
1486 radeon_emit(cmd_buffer
->cs
, S_028018_BASE_HI(ds
->db_htile_data_base
>> 32));
1487 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
);
1489 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 10);
1490 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* DB_Z_INFO */
1491 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* DB_STENCIL_INFO */
1492 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* DB_Z_READ_BASE */
1493 radeon_emit(cmd_buffer
->cs
, S_028044_BASE_HI(ds
->db_z_read_base
>> 32)); /* DB_Z_READ_BASE_HI */
1494 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* DB_STENCIL_READ_BASE */
1495 radeon_emit(cmd_buffer
->cs
, S_02804C_BASE_HI(ds
->db_stencil_read_base
>> 32)); /* DB_STENCIL_READ_BASE_HI */
1496 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* DB_Z_WRITE_BASE */
1497 radeon_emit(cmd_buffer
->cs
, S_028054_BASE_HI(ds
->db_z_write_base
>> 32)); /* DB_Z_WRITE_BASE_HI */
1498 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* DB_STENCIL_WRITE_BASE */
1499 radeon_emit(cmd_buffer
->cs
, S_02805C_BASE_HI(ds
->db_stencil_write_base
>> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1501 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028068_DB_Z_INFO2
, 2);
1502 radeon_emit(cmd_buffer
->cs
, ds
->db_z_info2
);
1503 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_info2
);
1505 radeon_set_context_reg(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, ds
->db_htile_data_base
);
1507 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_02803C_DB_DEPTH_INFO
, 9);
1508 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_info
); /* R_02803C_DB_DEPTH_INFO */
1509 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* R_028040_DB_Z_INFO */
1510 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* R_028044_DB_STENCIL_INFO */
1511 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* R_028048_DB_Z_READ_BASE */
1512 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* R_02804C_DB_STENCIL_READ_BASE */
1513 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* R_028050_DB_Z_WRITE_BASE */
1514 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* R_028054_DB_STENCIL_WRITE_BASE */
1515 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
); /* R_028058_DB_DEPTH_SIZE */
1516 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_slice
); /* R_02805C_DB_DEPTH_SLICE */
1520 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1521 radv_update_zrange_precision(cmd_buffer
, ds
, iview
, layout
,
1522 in_render_loop
, true);
1524 radeon_set_context_reg(cmd_buffer
->cs
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1525 ds
->pa_su_poly_offset_db_fmt_cntl
);
1529 * Update the fast clear depth/stencil values if the image is bound as a
1530 * depth/stencil buffer.
1533 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer
*cmd_buffer
,
1534 const struct radv_image_view
*iview
,
1535 VkClearDepthStencilValue ds_clear_value
,
1536 VkImageAspectFlags aspects
)
1538 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1539 const struct radv_image
*image
= iview
->image
;
1540 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1543 if (!cmd_buffer
->state
.attachments
|| !subpass
)
1546 if (!subpass
->depth_stencil_attachment
)
1549 att_idx
= subpass
->depth_stencil_attachment
->attachment
;
1550 if (cmd_buffer
->state
.attachments
[att_idx
].iview
->image
!= image
)
1553 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 2);
1554 radeon_emit(cs
, ds_clear_value
.stencil
);
1555 radeon_emit(cs
, fui(ds_clear_value
.depth
));
1557 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1558 * only needed when clearing Z to 0.0.
1560 if ((aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
1561 ds_clear_value
.depth
== 0.0) {
1562 VkImageLayout layout
= subpass
->depth_stencil_attachment
->layout
;
1563 bool in_render_loop
= subpass
->depth_stencil_attachment
->in_render_loop
;
1565 radv_update_zrange_precision(cmd_buffer
, &cmd_buffer
->state
.attachments
[att_idx
].ds
,
1566 iview
, layout
, in_render_loop
, false);
1569 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1573 * Set the clear depth/stencil values to the image's metadata.
1576 radv_set_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1577 struct radv_image
*image
,
1578 VkClearDepthStencilValue ds_clear_value
,
1579 VkImageAspectFlags aspects
)
1581 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1582 uint64_t va
= radv_buffer_get_va(image
->bo
);
1583 unsigned reg_offset
= 0, reg_count
= 0;
1585 va
+= image
->offset
+ image
->clear_value_offset
;
1587 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1593 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1596 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + reg_count
, cmd_buffer
->state
.predicating
));
1597 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
1598 S_370_WR_CONFIRM(1) |
1599 S_370_ENGINE_SEL(V_370_PFP
));
1600 radeon_emit(cs
, va
);
1601 radeon_emit(cs
, va
>> 32);
1602 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)
1603 radeon_emit(cs
, ds_clear_value
.stencil
);
1604 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1605 radeon_emit(cs
, fui(ds_clear_value
.depth
));
1609 * Update the TC-compat metadata value for this image.
1612 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1613 struct radv_image
*image
,
1614 const VkImageSubresourceRange
*range
,
1617 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1619 if (!cmd_buffer
->device
->physical_device
->has_tc_compat_zrange_bug
)
1622 uint64_t va
= radv_get_tc_compat_zrange_va(image
, range
->baseMipLevel
);
1623 uint32_t level_count
= radv_get_levelCount(image
, range
);
1625 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + level_count
, cmd_buffer
->state
.predicating
));
1626 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
1627 S_370_WR_CONFIRM(1) |
1628 S_370_ENGINE_SEL(V_370_PFP
));
1629 radeon_emit(cs
, va
);
1630 radeon_emit(cs
, va
>> 32);
1632 for (uint32_t l
= 0; l
< level_count
; l
++)
1633 radeon_emit(cs
, value
);
1637 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1638 const struct radv_image_view
*iview
,
1639 VkClearDepthStencilValue ds_clear_value
)
1641 VkImageSubresourceRange range
= {
1642 .aspectMask
= iview
->aspect_mask
,
1643 .baseMipLevel
= iview
->base_mip
,
1644 .levelCount
= iview
->level_count
,
1645 .baseArrayLayer
= iview
->base_layer
,
1646 .layerCount
= iview
->layer_count
,
1650 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1651 * depth clear value is 0.0f.
1653 cond_val
= ds_clear_value
.depth
== 0.0f
? UINT_MAX
: 0;
1655 radv_set_tc_compat_zrange_metadata(cmd_buffer
, iview
->image
, &range
,
1660 * Update the clear depth/stencil values for this image.
1663 radv_update_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1664 const struct radv_image_view
*iview
,
1665 VkClearDepthStencilValue ds_clear_value
,
1666 VkImageAspectFlags aspects
)
1668 struct radv_image
*image
= iview
->image
;
1670 assert(radv_image_has_htile(image
));
1672 radv_set_ds_clear_metadata(cmd_buffer
, image
, ds_clear_value
, aspects
);
1674 if (radv_image_is_tc_compat_htile(image
) &&
1675 (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
1676 radv_update_tc_compat_zrange_metadata(cmd_buffer
, iview
,
1680 radv_update_bound_fast_clear_ds(cmd_buffer
, iview
, ds_clear_value
,
1685 * Load the clear depth/stencil values from the image's metadata.
1688 radv_load_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1689 struct radv_image
*image
)
1691 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1692 VkImageAspectFlags aspects
= vk_format_aspects(image
->vk_format
);
1693 uint64_t va
= radv_buffer_get_va(image
->bo
);
1694 unsigned reg_offset
= 0, reg_count
= 0;
1696 va
+= image
->offset
+ image
->clear_value_offset
;
1698 if (!radv_image_has_htile(image
))
1701 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1707 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1710 uint32_t reg
= R_028028_DB_STENCIL_CLEAR
+ 4 * reg_offset
;
1712 if (cmd_buffer
->device
->physical_device
->has_load_ctx_reg_pkt
) {
1713 radeon_emit(cs
, PKT3(PKT3_LOAD_CONTEXT_REG
, 3, 0));
1714 radeon_emit(cs
, va
);
1715 radeon_emit(cs
, va
>> 32);
1716 radeon_emit(cs
, (reg
- SI_CONTEXT_REG_OFFSET
) >> 2);
1717 radeon_emit(cs
, reg_count
);
1719 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
1720 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
1721 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1722 (reg_count
== 2 ? COPY_DATA_COUNT_SEL
: 0));
1723 radeon_emit(cs
, va
);
1724 radeon_emit(cs
, va
>> 32);
1725 radeon_emit(cs
, reg
>> 2);
1728 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
1734 * With DCC some colors don't require CMASK elimination before being
1735 * used as a texture. This sets a predicate value to determine if the
1736 * cmask eliminate is required.
1739 radv_update_fce_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1740 struct radv_image
*image
,
1741 const VkImageSubresourceRange
*range
, bool value
)
1743 uint64_t pred_val
= value
;
1744 uint64_t va
= radv_image_get_fce_pred_va(image
, range
->baseMipLevel
);
1745 uint32_t level_count
= radv_get_levelCount(image
, range
);
1746 uint32_t count
= 2 * level_count
;
1748 assert(radv_dcc_enabled(image
, range
->baseMipLevel
));
1750 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, 0));
1751 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM
) |
1752 S_370_WR_CONFIRM(1) |
1753 S_370_ENGINE_SEL(V_370_PFP
));
1754 radeon_emit(cmd_buffer
->cs
, va
);
1755 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1757 for (uint32_t l
= 0; l
< level_count
; l
++) {
1758 radeon_emit(cmd_buffer
->cs
, pred_val
);
1759 radeon_emit(cmd_buffer
->cs
, pred_val
>> 32);
1764 * Update the DCC predicate to reflect the compression state.
1767 radv_update_dcc_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1768 struct radv_image
*image
,
1769 const VkImageSubresourceRange
*range
, bool value
)
1771 uint64_t pred_val
= value
;
1772 uint64_t va
= radv_image_get_dcc_pred_va(image
, range
->baseMipLevel
);
1773 uint32_t level_count
= radv_get_levelCount(image
, range
);
1774 uint32_t count
= 2 * level_count
;
1776 assert(radv_dcc_enabled(image
, range
->baseMipLevel
));
1778 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, 0));
1779 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM
) |
1780 S_370_WR_CONFIRM(1) |
1781 S_370_ENGINE_SEL(V_370_PFP
));
1782 radeon_emit(cmd_buffer
->cs
, va
);
1783 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1785 for (uint32_t l
= 0; l
< level_count
; l
++) {
1786 radeon_emit(cmd_buffer
->cs
, pred_val
);
1787 radeon_emit(cmd_buffer
->cs
, pred_val
>> 32);
1792 * Update the fast clear color values if the image is bound as a color buffer.
1795 radv_update_bound_fast_clear_color(struct radv_cmd_buffer
*cmd_buffer
,
1796 struct radv_image
*image
,
1798 uint32_t color_values
[2])
1800 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1801 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1804 if (!cmd_buffer
->state
.attachments
|| !subpass
)
1807 att_idx
= subpass
->color_attachments
[cb_idx
].attachment
;
1808 if (att_idx
== VK_ATTACHMENT_UNUSED
)
1811 if (cmd_buffer
->state
.attachments
[att_idx
].iview
->image
!= image
)
1814 radeon_set_context_reg_seq(cs
, R_028C8C_CB_COLOR0_CLEAR_WORD0
+ cb_idx
* 0x3c, 2);
1815 radeon_emit(cs
, color_values
[0]);
1816 radeon_emit(cs
, color_values
[1]);
1818 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1822 * Set the clear color values to the image's metadata.
1825 radv_set_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1826 struct radv_image
*image
,
1827 const VkImageSubresourceRange
*range
,
1828 uint32_t color_values
[2])
1830 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1831 uint64_t va
= radv_image_get_fast_clear_va(image
, range
->baseMipLevel
);
1832 uint32_t level_count
= radv_get_levelCount(image
, range
);
1833 uint32_t count
= 2 * level_count
;
1835 assert(radv_image_has_cmask(image
) ||
1836 radv_dcc_enabled(image
, range
->baseMipLevel
));
1838 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, cmd_buffer
->state
.predicating
));
1839 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
1840 S_370_WR_CONFIRM(1) |
1841 S_370_ENGINE_SEL(V_370_PFP
));
1842 radeon_emit(cs
, va
);
1843 radeon_emit(cs
, va
>> 32);
1845 for (uint32_t l
= 0; l
< level_count
; l
++) {
1846 radeon_emit(cs
, color_values
[0]);
1847 radeon_emit(cs
, color_values
[1]);
1852 * Update the clear color values for this image.
1855 radv_update_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1856 const struct radv_image_view
*iview
,
1858 uint32_t color_values
[2])
1860 struct radv_image
*image
= iview
->image
;
1861 VkImageSubresourceRange range
= {
1862 .aspectMask
= iview
->aspect_mask
,
1863 .baseMipLevel
= iview
->base_mip
,
1864 .levelCount
= iview
->level_count
,
1865 .baseArrayLayer
= iview
->base_layer
,
1866 .layerCount
= iview
->layer_count
,
1869 assert(radv_image_has_cmask(image
) ||
1870 radv_dcc_enabled(image
, iview
->base_mip
));
1872 radv_set_color_clear_metadata(cmd_buffer
, image
, &range
, color_values
);
1874 radv_update_bound_fast_clear_color(cmd_buffer
, image
, cb_idx
,
1879 * Load the clear color values from the image's metadata.
1882 radv_load_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1883 struct radv_image_view
*iview
,
1886 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1887 struct radv_image
*image
= iview
->image
;
1888 uint64_t va
= radv_image_get_fast_clear_va(image
, iview
->base_mip
);
1890 if (!radv_image_has_cmask(image
) &&
1891 !radv_dcc_enabled(image
, iview
->base_mip
))
1894 uint32_t reg
= R_028C8C_CB_COLOR0_CLEAR_WORD0
+ cb_idx
* 0x3c;
1896 if (cmd_buffer
->device
->physical_device
->has_load_ctx_reg_pkt
) {
1897 radeon_emit(cs
, PKT3(PKT3_LOAD_CONTEXT_REG
, 3, cmd_buffer
->state
.predicating
));
1898 radeon_emit(cs
, va
);
1899 radeon_emit(cs
, va
>> 32);
1900 radeon_emit(cs
, (reg
- SI_CONTEXT_REG_OFFSET
) >> 2);
1903 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, cmd_buffer
->state
.predicating
));
1904 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
1905 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1906 COPY_DATA_COUNT_SEL
);
1907 radeon_emit(cs
, va
);
1908 radeon_emit(cs
, va
>> 32);
1909 radeon_emit(cs
, reg
>> 2);
1912 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, cmd_buffer
->state
.predicating
));
1918 radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer
)
1921 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1922 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1924 /* this may happen for inherited secondary recording */
1928 for (i
= 0; i
< 8; ++i
) {
1929 if (i
>= subpass
->color_count
|| subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
1930 radeon_set_context_reg(cmd_buffer
->cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
1931 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
1935 int idx
= subpass
->color_attachments
[i
].attachment
;
1936 struct radv_image_view
*iview
= cmd_buffer
->state
.attachments
[idx
].iview
;
1937 VkImageLayout layout
= subpass
->color_attachments
[i
].layout
;
1938 bool in_render_loop
= subpass
->color_attachments
[i
].in_render_loop
;
1940 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, iview
->bo
);
1942 assert(iview
->aspect_mask
& (VK_IMAGE_ASPECT_COLOR_BIT
| VK_IMAGE_ASPECT_PLANE_0_BIT
|
1943 VK_IMAGE_ASPECT_PLANE_1_BIT
| VK_IMAGE_ASPECT_PLANE_2_BIT
));
1944 radv_emit_fb_color_state(cmd_buffer
, i
, &cmd_buffer
->state
.attachments
[idx
].cb
, iview
, layout
, in_render_loop
);
1946 radv_load_color_clear_metadata(cmd_buffer
, iview
, i
);
1949 if (subpass
->depth_stencil_attachment
) {
1950 int idx
= subpass
->depth_stencil_attachment
->attachment
;
1951 VkImageLayout layout
= subpass
->depth_stencil_attachment
->layout
;
1952 bool in_render_loop
= subpass
->depth_stencil_attachment
->in_render_loop
;
1953 struct radv_image_view
*iview
= cmd_buffer
->state
.attachments
[idx
].iview
;
1954 struct radv_image
*image
= iview
->image
;
1955 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, cmd_buffer
->state
.attachments
[idx
].iview
->bo
);
1956 ASSERTED
uint32_t queue_mask
= radv_image_queue_family_mask(image
,
1957 cmd_buffer
->queue_family_index
,
1958 cmd_buffer
->queue_family_index
);
1959 /* We currently don't support writing decompressed HTILE */
1960 assert(radv_layout_has_htile(image
, layout
, in_render_loop
, queue_mask
) ==
1961 radv_layout_is_htile_compressed(image
, layout
, in_render_loop
, queue_mask
));
1963 radv_emit_fb_ds_state(cmd_buffer
, &cmd_buffer
->state
.attachments
[idx
].ds
, iview
, layout
, in_render_loop
);
1965 if (cmd_buffer
->state
.attachments
[idx
].ds
.offset_scale
!= cmd_buffer
->state
.offset_scale
) {
1966 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
1967 cmd_buffer
->state
.offset_scale
= cmd_buffer
->state
.attachments
[idx
].ds
.offset_scale
;
1969 radv_load_ds_clear_metadata(cmd_buffer
, image
);
1971 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
)
1972 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 2);
1974 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028040_DB_Z_INFO
, 2);
1976 radeon_emit(cmd_buffer
->cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
1977 radeon_emit(cmd_buffer
->cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
1979 radeon_set_context_reg(cmd_buffer
->cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
1980 S_028208_BR_X(framebuffer
->width
) |
1981 S_028208_BR_Y(framebuffer
->height
));
1983 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX8
) {
1984 bool disable_constant_encode
=
1985 cmd_buffer
->device
->physical_device
->has_dcc_constant_encode
;
1986 enum chip_class chip_class
=
1987 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
;
1988 uint8_t watermark
= chip_class
>= GFX10
? 6 : 4;
1990 radeon_set_context_reg(cmd_buffer
->cs
, R_028424_CB_DCC_CONTROL
,
1991 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class
<= GFX9
) |
1992 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark
) |
1993 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode
));
1996 if (cmd_buffer
->device
->pbb_allowed
) {
1997 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1998 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
2001 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_FRAMEBUFFER
;
2005 radv_emit_index_buffer(struct radv_cmd_buffer
*cmd_buffer
)
2007 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
2008 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2010 if (state
->index_type
!= state
->last_index_type
) {
2011 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2012 radeon_set_uconfig_reg_idx(cmd_buffer
->device
->physical_device
,
2013 cs
, R_03090C_VGT_INDEX_TYPE
,
2014 2, state
->index_type
);
2016 radeon_emit(cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
2017 radeon_emit(cs
, state
->index_type
);
2020 state
->last_index_type
= state
->index_type
;
2023 radeon_emit(cs
, PKT3(PKT3_INDEX_BASE
, 1, 0));
2024 radeon_emit(cs
, state
->index_va
);
2025 radeon_emit(cs
, state
->index_va
>> 32);
2027 radeon_emit(cs
, PKT3(PKT3_INDEX_BUFFER_SIZE
, 0, 0));
2028 radeon_emit(cs
, state
->max_index_count
);
2030 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_INDEX_BUFFER
;
2033 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
)
2035 bool has_perfect_queries
= cmd_buffer
->state
.perfect_occlusion_queries_enabled
;
2036 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
2037 uint32_t pa_sc_mode_cntl_1
=
2038 pipeline
? pipeline
->graphics
.ms
.pa_sc_mode_cntl_1
: 0;
2039 uint32_t db_count_control
;
2041 if(!cmd_buffer
->state
.active_occlusion_queries
) {
2042 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2043 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1
) &&
2044 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
&&
2045 has_perfect_queries
) {
2046 /* Re-enable out-of-order rasterization if the
2047 * bound pipeline supports it and if it's has
2048 * been disabled before starting any perfect
2049 * occlusion queries.
2051 radeon_set_context_reg(cmd_buffer
->cs
,
2052 R_028A4C_PA_SC_MODE_CNTL_1
,
2056 db_count_control
= S_028004_ZPASS_INCREMENT_DISABLE(1);
2058 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
2059 uint32_t sample_rate
= subpass
? util_logbase2(subpass
->max_sample_count
) : 0;
2060 bool gfx10_perfect
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&& has_perfect_queries
;
2062 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2064 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries
) |
2065 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect
) |
2066 S_028004_SAMPLE_RATE(sample_rate
) |
2067 S_028004_ZPASS_ENABLE(1) |
2068 S_028004_SLICE_EVEN_ENABLE(1) |
2069 S_028004_SLICE_ODD_ENABLE(1);
2071 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1
) &&
2072 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
&&
2073 has_perfect_queries
) {
2074 /* If the bound pipeline has enabled
2075 * out-of-order rasterization, we should
2076 * disable it before starting any perfect
2077 * occlusion queries.
2079 pa_sc_mode_cntl_1
&= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE
;
2081 radeon_set_context_reg(cmd_buffer
->cs
,
2082 R_028A4C_PA_SC_MODE_CNTL_1
,
2086 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(1) |
2087 S_028004_SAMPLE_RATE(sample_rate
);
2091 radeon_set_context_reg(cmd_buffer
->cs
, R_028004_DB_COUNT_CONTROL
, db_count_control
);
2093 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
2097 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
)
2099 uint32_t states
= cmd_buffer
->state
.dirty
& cmd_buffer
->state
.emitted_pipeline
->graphics
.needed_dynamic_state
;
2101 if (states
& (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
))
2102 radv_emit_viewport(cmd_buffer
);
2104 if (states
& (RADV_CMD_DIRTY_DYNAMIC_SCISSOR
| RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
) &&
2105 !cmd_buffer
->device
->physical_device
->has_scissor_bug
)
2106 radv_emit_scissor(cmd_buffer
);
2108 if (states
& RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
)
2109 radv_emit_line_width(cmd_buffer
);
2111 if (states
& RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
)
2112 radv_emit_blend_constants(cmd_buffer
);
2114 if (states
& (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
|
2115 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
|
2116 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
))
2117 radv_emit_stencil(cmd_buffer
);
2119 if (states
& RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
)
2120 radv_emit_depth_bounds(cmd_buffer
);
2122 if (states
& RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
)
2123 radv_emit_depth_bias(cmd_buffer
);
2125 if (states
& RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
)
2126 radv_emit_discard_rectangle(cmd_buffer
);
2128 if (states
& RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS
)
2129 radv_emit_sample_locations(cmd_buffer
);
2131 cmd_buffer
->state
.dirty
&= ~states
;
2135 radv_flush_push_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
2136 VkPipelineBindPoint bind_point
)
2138 struct radv_descriptor_state
*descriptors_state
=
2139 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2140 struct radv_descriptor_set
*set
= &descriptors_state
->push_set
.set
;
2143 if (!radv_cmd_buffer_upload_data(cmd_buffer
, set
->size
, 32,
2148 set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2149 set
->va
+= bo_offset
;
2153 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer
*cmd_buffer
,
2154 VkPipelineBindPoint bind_point
)
2156 struct radv_descriptor_state
*descriptors_state
=
2157 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2158 uint32_t size
= MAX_SETS
* 4;
2162 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
,
2163 256, &offset
, &ptr
))
2166 for (unsigned i
= 0; i
< MAX_SETS
; i
++) {
2167 uint32_t *uptr
= ((uint32_t *)ptr
) + i
;
2168 uint64_t set_va
= 0;
2169 struct radv_descriptor_set
*set
= descriptors_state
->sets
[i
];
2170 if (descriptors_state
->valid
& (1u << i
))
2172 uptr
[0] = set_va
& 0xffffffff;
2175 uint64_t va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2178 if (cmd_buffer
->state
.pipeline
) {
2179 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_VERTEX
])
2180 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
2181 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2183 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_FRAGMENT
])
2184 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_FRAGMENT
,
2185 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2187 if (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
))
2188 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
2189 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2191 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
2192 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_CTRL
,
2193 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2195 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
2196 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_EVAL
,
2197 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2200 if (cmd_buffer
->state
.compute_pipeline
)
2201 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
, MESA_SHADER_COMPUTE
,
2202 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2206 radv_flush_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
2207 VkShaderStageFlags stages
)
2209 VkPipelineBindPoint bind_point
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
?
2210 VK_PIPELINE_BIND_POINT_COMPUTE
:
2211 VK_PIPELINE_BIND_POINT_GRAPHICS
;
2212 struct radv_descriptor_state
*descriptors_state
=
2213 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2214 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2215 bool flush_indirect_descriptors
;
2217 if (!descriptors_state
->dirty
)
2220 if (descriptors_state
->push_dirty
)
2221 radv_flush_push_descriptors(cmd_buffer
, bind_point
);
2223 flush_indirect_descriptors
=
2224 (bind_point
== VK_PIPELINE_BIND_POINT_GRAPHICS
&&
2225 state
->pipeline
&& state
->pipeline
->need_indirect_descriptor_sets
) ||
2226 (bind_point
== VK_PIPELINE_BIND_POINT_COMPUTE
&&
2227 state
->compute_pipeline
&& state
->compute_pipeline
->need_indirect_descriptor_sets
);
2229 if (flush_indirect_descriptors
)
2230 radv_flush_indirect_descriptor_sets(cmd_buffer
, bind_point
);
2232 ASSERTED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
2234 MAX_SETS
* MESA_SHADER_STAGES
* 4);
2236 if (cmd_buffer
->state
.pipeline
) {
2237 radv_foreach_stage(stage
, stages
) {
2238 if (!cmd_buffer
->state
.pipeline
->shaders
[stage
])
2241 radv_emit_descriptor_pointers(cmd_buffer
,
2242 cmd_buffer
->state
.pipeline
,
2243 descriptors_state
, stage
);
2247 if (cmd_buffer
->state
.compute_pipeline
&&
2248 (stages
& VK_SHADER_STAGE_COMPUTE_BIT
)) {
2249 radv_emit_descriptor_pointers(cmd_buffer
,
2250 cmd_buffer
->state
.compute_pipeline
,
2252 MESA_SHADER_COMPUTE
);
2255 descriptors_state
->dirty
= 0;
2256 descriptors_state
->push_dirty
= false;
2258 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2260 if (unlikely(cmd_buffer
->device
->trace_bo
))
2261 radv_save_descriptors(cmd_buffer
, bind_point
);
2265 radv_flush_constants(struct radv_cmd_buffer
*cmd_buffer
,
2266 VkShaderStageFlags stages
)
2268 struct radv_pipeline
*pipeline
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
2269 ? cmd_buffer
->state
.compute_pipeline
2270 : cmd_buffer
->state
.pipeline
;
2271 VkPipelineBindPoint bind_point
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
?
2272 VK_PIPELINE_BIND_POINT_COMPUTE
:
2273 VK_PIPELINE_BIND_POINT_GRAPHICS
;
2274 struct radv_descriptor_state
*descriptors_state
=
2275 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2276 struct radv_pipeline_layout
*layout
= pipeline
->layout
;
2277 struct radv_shader_variant
*shader
, *prev_shader
;
2278 bool need_push_constants
= false;
2283 stages
&= cmd_buffer
->push_constant_stages
;
2285 (!layout
->push_constant_size
&& !layout
->dynamic_offset_count
))
2288 radv_foreach_stage(stage
, stages
) {
2289 if (!pipeline
->shaders
[stage
])
2292 need_push_constants
|= pipeline
->shaders
[stage
]->info
.info
.loads_push_constants
;
2293 need_push_constants
|= pipeline
->shaders
[stage
]->info
.info
.loads_dynamic_offsets
;
2295 uint8_t base
= pipeline
->shaders
[stage
]->info
.info
.base_inline_push_consts
;
2296 uint8_t count
= pipeline
->shaders
[stage
]->info
.info
.num_inline_push_consts
;
2298 radv_emit_inline_push_consts(cmd_buffer
, pipeline
, stage
,
2299 AC_UD_INLINE_PUSH_CONSTANTS
,
2301 (uint32_t *)&cmd_buffer
->push_constants
[base
* 4]);
2304 if (need_push_constants
) {
2305 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, layout
->push_constant_size
+
2306 16 * layout
->dynamic_offset_count
,
2307 256, &offset
, &ptr
))
2310 memcpy(ptr
, cmd_buffer
->push_constants
, layout
->push_constant_size
);
2311 memcpy((char*)ptr
+ layout
->push_constant_size
,
2312 descriptors_state
->dynamic_buffers
,
2313 16 * layout
->dynamic_offset_count
);
2315 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2318 ASSERTED
unsigned cdw_max
=
2319 radeon_check_space(cmd_buffer
->device
->ws
,
2320 cmd_buffer
->cs
, MESA_SHADER_STAGES
* 4);
2323 radv_foreach_stage(stage
, stages
) {
2324 shader
= radv_get_shader(pipeline
, stage
);
2326 /* Avoid redundantly emitting the address for merged stages. */
2327 if (shader
&& shader
!= prev_shader
) {
2328 radv_emit_userdata_address(cmd_buffer
, pipeline
, stage
,
2329 AC_UD_PUSH_CONSTANTS
, va
);
2331 prev_shader
= shader
;
2334 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2337 cmd_buffer
->push_constant_stages
&= ~stages
;
2341 radv_flush_vertex_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
2342 bool pipeline_is_dirty
)
2344 if ((pipeline_is_dirty
||
2345 (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_VERTEX_BUFFER
)) &&
2346 cmd_buffer
->state
.pipeline
->num_vertex_bindings
&&
2347 radv_get_shader(cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
)->info
.info
.vs
.has_vertex_buffers
) {
2348 struct radv_vertex_elements_info
*velems
= &cmd_buffer
->state
.pipeline
->vertex_elements
;
2352 uint32_t count
= cmd_buffer
->state
.pipeline
->num_vertex_bindings
;
2355 /* allocate some descriptor state for vertex buffers */
2356 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, count
* 16, 256,
2357 &vb_offset
, &vb_ptr
))
2360 for (i
= 0; i
< count
; i
++) {
2361 uint32_t *desc
= &((uint32_t *)vb_ptr
)[i
* 4];
2363 struct radv_buffer
*buffer
= cmd_buffer
->vertex_bindings
[i
].buffer
;
2364 uint32_t stride
= cmd_buffer
->state
.pipeline
->binding_stride
[i
];
2369 va
= radv_buffer_get_va(buffer
->bo
);
2371 offset
= cmd_buffer
->vertex_bindings
[i
].offset
;
2372 va
+= offset
+ buffer
->offset
;
2374 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) | S_008F04_STRIDE(stride
);
2375 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
<= GFX7
&& stride
)
2376 desc
[2] = (buffer
->size
- offset
- velems
->format_size
[i
]) / stride
+ 1;
2378 desc
[2] = buffer
->size
- offset
;
2379 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2380 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2381 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2382 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
2384 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2385 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT
) |
2386 S_008F0C_OOB_SELECT(1) |
2387 S_008F0C_RESOURCE_LEVEL(1);
2389 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT
) |
2390 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2394 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2397 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
2398 AC_UD_VS_VERTEX_BUFFERS
, va
);
2400 cmd_buffer
->state
.vb_va
= va
;
2401 cmd_buffer
->state
.vb_size
= count
* 16;
2402 cmd_buffer
->state
.prefetch_L2_mask
|= RADV_PREFETCH_VBO_DESCRIPTORS
;
2404 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_VERTEX_BUFFER
;
2408 radv_emit_streamout_buffers(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
)
2410 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
2411 struct radv_userdata_info
*loc
;
2414 for (unsigned stage
= 0; stage
< MESA_SHADER_STAGES
; ++stage
) {
2415 if (!radv_get_shader(pipeline
, stage
))
2418 loc
= radv_lookup_user_sgpr(pipeline
, stage
,
2419 AC_UD_STREAMOUT_BUFFERS
);
2420 if (loc
->sgpr_idx
== -1)
2423 base_reg
= pipeline
->user_data_0
[stage
];
2425 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
2426 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
2429 if (radv_pipeline_has_gs_copy_shader(pipeline
)) {
2430 loc
= &pipeline
->gs_copy_shader
->info
.user_sgprs_locs
.shader_data
[AC_UD_STREAMOUT_BUFFERS
];
2431 if (loc
->sgpr_idx
!= -1) {
2432 base_reg
= R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2434 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
2435 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
2441 radv_flush_streamout_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
2443 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_STREAMOUT_BUFFER
) {
2444 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
2445 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
2450 /* Allocate some descriptor state for streamout buffers. */
2451 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
,
2452 MAX_SO_BUFFERS
* 16, 256,
2453 &so_offset
, &so_ptr
))
2456 for (uint32_t i
= 0; i
< MAX_SO_BUFFERS
; i
++) {
2457 struct radv_buffer
*buffer
= sb
[i
].buffer
;
2458 uint32_t *desc
= &((uint32_t *)so_ptr
)[i
* 4];
2460 if (!(so
->enabled_mask
& (1 << i
)))
2463 va
= radv_buffer_get_va(buffer
->bo
) + buffer
->offset
;
2467 /* Set the descriptor.
2469 * On GFX8, the format must be non-INVALID, otherwise
2470 * the buffer will be considered not bound and store
2471 * instructions will be no-ops.
2474 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
2475 desc
[2] = 0xffffffff;
2476 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2477 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2478 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2479 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
2481 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2482 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2483 S_008F0C_OOB_SELECT(3) |
2484 S_008F0C_RESOURCE_LEVEL(1);
2486 desc
[3] |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2490 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2493 radv_emit_streamout_buffers(cmd_buffer
, va
);
2496 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER
;
2500 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer
*cmd_buffer
, bool pipeline_is_dirty
)
2502 radv_flush_vertex_descriptors(cmd_buffer
, pipeline_is_dirty
);
2503 radv_flush_streamout_descriptors(cmd_buffer
);
2504 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
2505 radv_flush_constants(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
2508 struct radv_draw_info
{
2510 * Number of vertices.
2515 * Index of the first vertex.
2517 int32_t vertex_offset
;
2520 * First instance id.
2522 uint32_t first_instance
;
2525 * Number of instances.
2527 uint32_t instance_count
;
2530 * First index (indexed draws only).
2532 uint32_t first_index
;
2535 * Whether it's an indexed draw.
2540 * Indirect draw parameters resource.
2542 struct radv_buffer
*indirect
;
2543 uint64_t indirect_offset
;
2547 * Draw count parameters resource.
2549 struct radv_buffer
*count_buffer
;
2550 uint64_t count_buffer_offset
;
2553 * Stream output parameters resource.
2555 struct radv_buffer
*strmout_buffer
;
2556 uint64_t strmout_buffer_offset
;
2560 radv_get_primitive_reset_index(struct radv_cmd_buffer
*cmd_buffer
)
2562 switch (cmd_buffer
->state
.index_type
) {
2563 case V_028A7C_VGT_INDEX_8
:
2565 case V_028A7C_VGT_INDEX_16
:
2567 case V_028A7C_VGT_INDEX_32
:
2570 unreachable("invalid index type");
2575 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
2576 bool instanced_draw
, bool indirect_draw
,
2577 bool count_from_stream_output
,
2578 uint32_t draw_vertex_count
)
2580 struct radeon_info
*info
= &cmd_buffer
->device
->physical_device
->rad_info
;
2581 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2582 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
2583 unsigned ia_multi_vgt_param
;
2585 ia_multi_vgt_param
=
2586 si_get_ia_multi_vgt_param(cmd_buffer
, instanced_draw
,
2588 count_from_stream_output
,
2591 if (state
->last_ia_multi_vgt_param
!= ia_multi_vgt_param
) {
2592 if (info
->chip_class
== GFX9
) {
2593 radeon_set_uconfig_reg_idx(cmd_buffer
->device
->physical_device
,
2595 R_030960_IA_MULTI_VGT_PARAM
,
2596 4, ia_multi_vgt_param
);
2597 } else if (info
->chip_class
>= GFX7
) {
2598 radeon_set_context_reg_idx(cs
,
2599 R_028AA8_IA_MULTI_VGT_PARAM
,
2600 1, ia_multi_vgt_param
);
2602 radeon_set_context_reg(cs
, R_028AA8_IA_MULTI_VGT_PARAM
,
2603 ia_multi_vgt_param
);
2605 state
->last_ia_multi_vgt_param
= ia_multi_vgt_param
;
2610 radv_emit_draw_registers(struct radv_cmd_buffer
*cmd_buffer
,
2611 const struct radv_draw_info
*draw_info
)
2613 struct radeon_info
*info
= &cmd_buffer
->device
->physical_device
->rad_info
;
2614 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2615 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
2616 int32_t primitive_reset_en
;
2619 if (info
->chip_class
< GFX10
) {
2620 si_emit_ia_multi_vgt_param(cmd_buffer
, draw_info
->instance_count
> 1,
2621 draw_info
->indirect
,
2622 !!draw_info
->strmout_buffer
,
2623 draw_info
->indirect
? 0 : draw_info
->count
);
2626 /* Primitive restart. */
2627 primitive_reset_en
=
2628 draw_info
->indexed
&& state
->pipeline
->graphics
.prim_restart_enable
;
2630 if (primitive_reset_en
!= state
->last_primitive_reset_en
) {
2631 state
->last_primitive_reset_en
= primitive_reset_en
;
2632 if (info
->chip_class
>= GFX9
) {
2633 radeon_set_uconfig_reg(cs
,
2634 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN
,
2635 primitive_reset_en
);
2637 radeon_set_context_reg(cs
,
2638 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
,
2639 primitive_reset_en
);
2643 if (primitive_reset_en
) {
2644 uint32_t primitive_reset_index
=
2645 radv_get_primitive_reset_index(cmd_buffer
);
2647 if (primitive_reset_index
!= state
->last_primitive_reset_index
) {
2648 radeon_set_context_reg(cs
,
2649 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
,
2650 primitive_reset_index
);
2651 state
->last_primitive_reset_index
= primitive_reset_index
;
2655 if (draw_info
->strmout_buffer
) {
2656 uint64_t va
= radv_buffer_get_va(draw_info
->strmout_buffer
->bo
);
2658 va
+= draw_info
->strmout_buffer
->offset
+
2659 draw_info
->strmout_buffer_offset
;
2661 radeon_set_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
,
2664 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
2665 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
2666 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
2667 COPY_DATA_WR_CONFIRM
);
2668 radeon_emit(cs
, va
);
2669 radeon_emit(cs
, va
>> 32);
2670 radeon_emit(cs
, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2);
2671 radeon_emit(cs
, 0); /* unused */
2673 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, draw_info
->strmout_buffer
->bo
);
2677 static void radv_stage_flush(struct radv_cmd_buffer
*cmd_buffer
,
2678 VkPipelineStageFlags src_stage_mask
)
2680 if (src_stage_mask
& (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT
|
2681 VK_PIPELINE_STAGE_TRANSFER_BIT
|
2682 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
2683 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
2684 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
;
2687 if (src_stage_mask
& (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT
|
2688 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT
|
2689 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT
|
2690 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
|
2691 VK_PIPELINE_STAGE_TRANSFER_BIT
|
2692 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
2693 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT
|
2694 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
2695 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
;
2696 } else if (src_stage_mask
& (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
2697 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
|
2698 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT
|
2699 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT
|
2700 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT
|
2701 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT
|
2702 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT
)) {
2703 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VS_PARTIAL_FLUSH
;
2707 static enum radv_cmd_flush_bits
2708 radv_src_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
2709 VkAccessFlags src_flags
,
2710 struct radv_image
*image
)
2712 bool flush_CB_meta
= true, flush_DB_meta
= true;
2713 enum radv_cmd_flush_bits flush_bits
= 0;
2717 if (!radv_image_has_CB_metadata(image
))
2718 flush_CB_meta
= false;
2719 if (!radv_image_has_htile(image
))
2720 flush_DB_meta
= false;
2723 for_each_bit(b
, src_flags
) {
2724 switch ((VkAccessFlagBits
)(1 << b
)) {
2725 case VK_ACCESS_SHADER_WRITE_BIT
:
2726 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT
:
2727 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT
:
2728 flush_bits
|= RADV_CMD_FLAG_WB_L2
;
2730 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
2731 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
;
2733 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2735 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
2736 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
;
2738 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2740 case VK_ACCESS_TRANSFER_WRITE_BIT
:
2741 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
2742 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
2743 RADV_CMD_FLAG_INV_L2
;
2746 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2748 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2757 static enum radv_cmd_flush_bits
2758 radv_dst_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
2759 VkAccessFlags dst_flags
,
2760 struct radv_image
*image
)
2762 bool flush_CB_meta
= true, flush_DB_meta
= true;
2763 enum radv_cmd_flush_bits flush_bits
= 0;
2764 bool flush_CB
= true, flush_DB
= true;
2765 bool image_is_coherent
= false;
2769 if (!(image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
)) {
2774 if (!radv_image_has_CB_metadata(image
))
2775 flush_CB_meta
= false;
2776 if (!radv_image_has_htile(image
))
2777 flush_DB_meta
= false;
2779 /* TODO: implement shader coherent for GFX10 */
2781 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
2782 if (image
->info
.samples
== 1 &&
2783 (image
->usage
& (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
|
2784 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
)) &&
2785 !vk_format_is_stencil(image
->vk_format
)) {
2786 /* Single-sample color and single-sample depth
2787 * (not stencil) are coherent with shaders on
2790 image_is_coherent
= true;
2795 for_each_bit(b
, dst_flags
) {
2796 switch ((VkAccessFlagBits
)(1 << b
)) {
2797 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
2798 case VK_ACCESS_INDEX_READ_BIT
:
2799 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT
:
2801 case VK_ACCESS_UNIFORM_READ_BIT
:
2802 flush_bits
|= RADV_CMD_FLAG_INV_VCACHE
| RADV_CMD_FLAG_INV_SCACHE
;
2804 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
2805 case VK_ACCESS_TRANSFER_READ_BIT
:
2806 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
2807 flush_bits
|= RADV_CMD_FLAG_INV_VCACHE
|
2808 RADV_CMD_FLAG_INV_L2
;
2810 case VK_ACCESS_SHADER_READ_BIT
:
2811 flush_bits
|= RADV_CMD_FLAG_INV_VCACHE
;
2813 if (!image_is_coherent
)
2814 flush_bits
|= RADV_CMD_FLAG_INV_L2
;
2816 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
:
2818 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
;
2820 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2822 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT
:
2824 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
;
2826 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2835 void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
,
2836 const struct radv_subpass_barrier
*barrier
)
2838 cmd_buffer
->state
.flush_bits
|= radv_src_access_flush(cmd_buffer
, barrier
->src_access_mask
,
2840 radv_stage_flush(cmd_buffer
, barrier
->src_stage_mask
);
2841 cmd_buffer
->state
.flush_bits
|= radv_dst_access_flush(cmd_buffer
, barrier
->dst_access_mask
,
2846 radv_get_subpass_id(struct radv_cmd_buffer
*cmd_buffer
)
2848 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2849 uint32_t subpass_id
= state
->subpass
- state
->pass
->subpasses
;
2851 /* The id of this subpass shouldn't exceed the number of subpasses in
2852 * this render pass minus 1.
2854 assert(subpass_id
< state
->pass
->subpass_count
);
2858 static struct radv_sample_locations_state
*
2859 radv_get_attachment_sample_locations(struct radv_cmd_buffer
*cmd_buffer
,
2863 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2864 uint32_t subpass_id
= radv_get_subpass_id(cmd_buffer
);
2865 struct radv_image_view
*view
= state
->attachments
[att_idx
].iview
;
2867 if (view
->image
->info
.samples
== 1)
2870 if (state
->pass
->attachments
[att_idx
].first_subpass_idx
== subpass_id
) {
2871 /* Return the initial sample locations if this is the initial
2872 * layout transition of the given subpass attachemnt.
2874 if (state
->attachments
[att_idx
].sample_location
.count
> 0)
2875 return &state
->attachments
[att_idx
].sample_location
;
2877 /* Otherwise return the subpass sample locations if defined. */
2878 if (state
->subpass_sample_locs
) {
2879 /* Because the driver sets the current subpass before
2880 * initial layout transitions, we should use the sample
2881 * locations from the previous subpass to avoid an
2882 * off-by-one problem. Otherwise, use the sample
2883 * locations for the current subpass for final layout
2889 for (uint32_t i
= 0; i
< state
->num_subpass_sample_locs
; i
++) {
2890 if (state
->subpass_sample_locs
[i
].subpass_idx
== subpass_id
)
2891 return &state
->subpass_sample_locs
[i
].sample_location
;
2899 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
2900 struct radv_subpass_attachment att
,
2903 unsigned idx
= att
.attachment
;
2904 struct radv_image_view
*view
= cmd_buffer
->state
.attachments
[idx
].iview
;
2905 struct radv_sample_locations_state
*sample_locs
;
2906 VkImageSubresourceRange range
;
2907 range
.aspectMask
= 0;
2908 range
.baseMipLevel
= view
->base_mip
;
2909 range
.levelCount
= 1;
2910 range
.baseArrayLayer
= view
->base_layer
;
2911 range
.layerCount
= cmd_buffer
->state
.framebuffer
->layers
;
2913 if (cmd_buffer
->state
.subpass
->view_mask
) {
2914 /* If the current subpass uses multiview, the driver might have
2915 * performed a fast color/depth clear to the whole image
2916 * (including all layers). To make sure the driver will
2917 * decompress the image correctly (if needed), we have to
2918 * account for the "real" number of layers. If the view mask is
2919 * sparse, this will decompress more layers than needed.
2921 range
.layerCount
= util_last_bit(cmd_buffer
->state
.subpass
->view_mask
);
2924 /* Get the subpass sample locations for the given attachment, if NULL
2925 * is returned the driver will use the default HW locations.
2927 sample_locs
= radv_get_attachment_sample_locations(cmd_buffer
, idx
,
2930 radv_handle_image_transition(cmd_buffer
,
2932 cmd_buffer
->state
.attachments
[idx
].current_layout
,
2933 cmd_buffer
->state
.attachments
[idx
].current_in_render_loop
,
2934 att
.layout
, att
.in_render_loop
,
2935 0, 0, &range
, sample_locs
);
2937 cmd_buffer
->state
.attachments
[idx
].current_layout
= att
.layout
;
2938 cmd_buffer
->state
.attachments
[idx
].current_in_render_loop
= att
.in_render_loop
;
2944 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
2945 const struct radv_subpass
*subpass
)
2947 cmd_buffer
->state
.subpass
= subpass
;
2949 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_FRAMEBUFFER
;
2953 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer
*cmd_buffer
,
2954 struct radv_render_pass
*pass
,
2955 const VkRenderPassBeginInfo
*info
)
2957 const struct VkRenderPassSampleLocationsBeginInfoEXT
*sample_locs
=
2958 vk_find_struct_const(info
->pNext
,
2959 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT
);
2960 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2963 state
->subpass_sample_locs
= NULL
;
2967 for (uint32_t i
= 0; i
< sample_locs
->attachmentInitialSampleLocationsCount
; i
++) {
2968 const VkAttachmentSampleLocationsEXT
*att_sample_locs
=
2969 &sample_locs
->pAttachmentInitialSampleLocations
[i
];
2970 uint32_t att_idx
= att_sample_locs
->attachmentIndex
;
2971 struct radv_image
*image
= cmd_buffer
->state
.attachments
[att_idx
].iview
->image
;
2973 assert(vk_format_is_depth_or_stencil(image
->vk_format
));
2975 /* From the Vulkan spec 1.1.108:
2977 * "If the image referenced by the framebuffer attachment at
2978 * index attachmentIndex was not created with
2979 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
2980 * then the values specified in sampleLocationsInfo are
2983 if (!(image
->flags
& VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
))
2986 const VkSampleLocationsInfoEXT
*sample_locs_info
=
2987 &att_sample_locs
->sampleLocationsInfo
;
2989 state
->attachments
[att_idx
].sample_location
.per_pixel
=
2990 sample_locs_info
->sampleLocationsPerPixel
;
2991 state
->attachments
[att_idx
].sample_location
.grid_size
=
2992 sample_locs_info
->sampleLocationGridSize
;
2993 state
->attachments
[att_idx
].sample_location
.count
=
2994 sample_locs_info
->sampleLocationsCount
;
2995 typed_memcpy(&state
->attachments
[att_idx
].sample_location
.locations
[0],
2996 sample_locs_info
->pSampleLocations
,
2997 sample_locs_info
->sampleLocationsCount
);
3000 state
->subpass_sample_locs
= vk_alloc(&cmd_buffer
->pool
->alloc
,
3001 sample_locs
->postSubpassSampleLocationsCount
*
3002 sizeof(state
->subpass_sample_locs
[0]),
3003 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3004 if (state
->subpass_sample_locs
== NULL
) {
3005 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
3006 return cmd_buffer
->record_result
;
3009 state
->num_subpass_sample_locs
= sample_locs
->postSubpassSampleLocationsCount
;
3011 for (uint32_t i
= 0; i
< sample_locs
->postSubpassSampleLocationsCount
; i
++) {
3012 const VkSubpassSampleLocationsEXT
*subpass_sample_locs_info
=
3013 &sample_locs
->pPostSubpassSampleLocations
[i
];
3014 const VkSampleLocationsInfoEXT
*sample_locs_info
=
3015 &subpass_sample_locs_info
->sampleLocationsInfo
;
3017 state
->subpass_sample_locs
[i
].subpass_idx
=
3018 subpass_sample_locs_info
->subpassIndex
;
3019 state
->subpass_sample_locs
[i
].sample_location
.per_pixel
=
3020 sample_locs_info
->sampleLocationsPerPixel
;
3021 state
->subpass_sample_locs
[i
].sample_location
.grid_size
=
3022 sample_locs_info
->sampleLocationGridSize
;
3023 state
->subpass_sample_locs
[i
].sample_location
.count
=
3024 sample_locs_info
->sampleLocationsCount
;
3025 typed_memcpy(&state
->subpass_sample_locs
[i
].sample_location
.locations
[0],
3026 sample_locs_info
->pSampleLocations
,
3027 sample_locs_info
->sampleLocationsCount
);
3034 radv_cmd_state_setup_attachments(struct radv_cmd_buffer
*cmd_buffer
,
3035 struct radv_render_pass
*pass
,
3036 const VkRenderPassBeginInfo
*info
)
3038 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3039 const struct VkRenderPassAttachmentBeginInfoKHR
*attachment_info
= NULL
;
3042 attachment_info
= vk_find_struct_const(info
->pNext
,
3043 RENDER_PASS_ATTACHMENT_BEGIN_INFO_KHR
);
3047 if (pass
->attachment_count
== 0) {
3048 state
->attachments
= NULL
;
3052 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
3053 pass
->attachment_count
*
3054 sizeof(state
->attachments
[0]),
3055 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3056 if (state
->attachments
== NULL
) {
3057 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
3058 return cmd_buffer
->record_result
;
3061 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
3062 struct radv_render_pass_attachment
*att
= &pass
->attachments
[i
];
3063 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
3064 VkImageAspectFlags clear_aspects
= 0;
3066 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
3067 /* color attachment */
3068 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
3069 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
3072 /* depthstencil attachment */
3073 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
3074 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
3075 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
3076 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
3077 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_DONT_CARE
)
3078 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
3080 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
3081 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
3082 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
3086 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
3087 state
->attachments
[i
].cleared_views
= 0;
3088 if (clear_aspects
&& info
) {
3089 assert(info
->clearValueCount
> i
);
3090 state
->attachments
[i
].clear_value
= info
->pClearValues
[i
];
3093 state
->attachments
[i
].current_layout
= att
->initial_layout
;
3094 state
->attachments
[i
].sample_location
.count
= 0;
3096 struct radv_image_view
*iview
;
3097 if (attachment_info
&& attachment_info
->attachmentCount
> i
) {
3098 iview
= radv_image_view_from_handle(attachment_info
->pAttachments
[i
]);
3100 iview
= state
->framebuffer
->attachments
[i
];
3103 state
->attachments
[i
].iview
= iview
;
3104 if (iview
->aspect_mask
& (VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3105 radv_initialise_ds_surface(cmd_buffer
->device
, &state
->attachments
[i
].ds
, iview
);
3107 radv_initialise_color_surface(cmd_buffer
->device
, &state
->attachments
[i
].cb
, iview
);
3114 VkResult
radv_AllocateCommandBuffers(
3116 const VkCommandBufferAllocateInfo
*pAllocateInfo
,
3117 VkCommandBuffer
*pCommandBuffers
)
3119 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3120 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
3122 VkResult result
= VK_SUCCESS
;
3125 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
3127 if (!list_empty(&pool
->free_cmd_buffers
)) {
3128 struct radv_cmd_buffer
*cmd_buffer
= list_first_entry(&pool
->free_cmd_buffers
, struct radv_cmd_buffer
, pool_link
);
3130 list_del(&cmd_buffer
->pool_link
);
3131 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
3133 result
= radv_reset_cmd_buffer(cmd_buffer
);
3134 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
3135 cmd_buffer
->level
= pAllocateInfo
->level
;
3137 pCommandBuffers
[i
] = radv_cmd_buffer_to_handle(cmd_buffer
);
3139 result
= radv_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
3140 &pCommandBuffers
[i
]);
3142 if (result
!= VK_SUCCESS
)
3146 if (result
!= VK_SUCCESS
) {
3147 radv_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
,
3148 i
, pCommandBuffers
);
3150 /* From the Vulkan 1.0.66 spec:
3152 * "vkAllocateCommandBuffers can be used to create multiple
3153 * command buffers. If the creation of any of those command
3154 * buffers fails, the implementation must destroy all
3155 * successfully created command buffer objects from this
3156 * command, set all entries of the pCommandBuffers array to
3157 * NULL and return the error."
3159 memset(pCommandBuffers
, 0,
3160 sizeof(*pCommandBuffers
) * pAllocateInfo
->commandBufferCount
);
3166 void radv_FreeCommandBuffers(
3168 VkCommandPool commandPool
,
3169 uint32_t commandBufferCount
,
3170 const VkCommandBuffer
*pCommandBuffers
)
3172 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
3173 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
3176 if (cmd_buffer
->pool
) {
3177 list_del(&cmd_buffer
->pool_link
);
3178 list_addtail(&cmd_buffer
->pool_link
, &cmd_buffer
->pool
->free_cmd_buffers
);
3180 radv_cmd_buffer_destroy(cmd_buffer
);
3186 VkResult
radv_ResetCommandBuffer(
3187 VkCommandBuffer commandBuffer
,
3188 VkCommandBufferResetFlags flags
)
3190 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3191 return radv_reset_cmd_buffer(cmd_buffer
);
3194 VkResult
radv_BeginCommandBuffer(
3195 VkCommandBuffer commandBuffer
,
3196 const VkCommandBufferBeginInfo
*pBeginInfo
)
3198 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3199 VkResult result
= VK_SUCCESS
;
3201 if (cmd_buffer
->status
!= RADV_CMD_BUFFER_STATUS_INITIAL
) {
3202 /* If the command buffer has already been resetted with
3203 * vkResetCommandBuffer, no need to do it again.
3205 result
= radv_reset_cmd_buffer(cmd_buffer
);
3206 if (result
!= VK_SUCCESS
)
3210 memset(&cmd_buffer
->state
, 0, sizeof(cmd_buffer
->state
));
3211 cmd_buffer
->state
.last_primitive_reset_en
= -1;
3212 cmd_buffer
->state
.last_index_type
= -1;
3213 cmd_buffer
->state
.last_num_instances
= -1;
3214 cmd_buffer
->state
.last_vertex_offset
= -1;
3215 cmd_buffer
->state
.last_first_instance
= -1;
3216 cmd_buffer
->state
.predication_type
= -1;
3217 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
3219 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
&&
3220 (pBeginInfo
->flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
)) {
3221 assert(pBeginInfo
->pInheritanceInfo
);
3222 cmd_buffer
->state
.framebuffer
= radv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
3223 cmd_buffer
->state
.pass
= radv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
3225 struct radv_subpass
*subpass
=
3226 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
3228 if (cmd_buffer
->state
.framebuffer
) {
3229 result
= radv_cmd_state_setup_attachments(cmd_buffer
, cmd_buffer
->state
.pass
, NULL
);
3230 if (result
!= VK_SUCCESS
)
3234 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
);
3237 if (unlikely(cmd_buffer
->device
->trace_bo
)) {
3238 struct radv_device
*device
= cmd_buffer
->device
;
3240 radv_cs_add_buffer(device
->ws
, cmd_buffer
->cs
,
3243 radv_cmd_buffer_trace_emit(cmd_buffer
);
3246 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_RECORDING
;
3251 void radv_CmdBindVertexBuffers(
3252 VkCommandBuffer commandBuffer
,
3253 uint32_t firstBinding
,
3254 uint32_t bindingCount
,
3255 const VkBuffer
* pBuffers
,
3256 const VkDeviceSize
* pOffsets
)
3258 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3259 struct radv_vertex_binding
*vb
= cmd_buffer
->vertex_bindings
;
3260 bool changed
= false;
3262 /* We have to defer setting up vertex buffer since we need the buffer
3263 * stride from the pipeline. */
3265 assert(firstBinding
+ bindingCount
<= MAX_VBS
);
3266 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
3267 uint32_t idx
= firstBinding
+ i
;
3270 (vb
[idx
].buffer
!= radv_buffer_from_handle(pBuffers
[i
]) ||
3271 vb
[idx
].offset
!= pOffsets
[i
])) {
3275 vb
[idx
].buffer
= radv_buffer_from_handle(pBuffers
[i
]);
3276 vb
[idx
].offset
= pOffsets
[i
];
3278 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
3279 vb
[idx
].buffer
->bo
);
3283 /* No state changes. */
3287 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_VERTEX_BUFFER
;
3291 vk_to_index_type(VkIndexType type
)
3294 case VK_INDEX_TYPE_UINT8_EXT
:
3295 return V_028A7C_VGT_INDEX_8
;
3296 case VK_INDEX_TYPE_UINT16
:
3297 return V_028A7C_VGT_INDEX_16
;
3298 case VK_INDEX_TYPE_UINT32
:
3299 return V_028A7C_VGT_INDEX_32
;
3301 unreachable("invalid index type");
3306 radv_get_vgt_index_size(uint32_t type
)
3309 case V_028A7C_VGT_INDEX_8
:
3311 case V_028A7C_VGT_INDEX_16
:
3313 case V_028A7C_VGT_INDEX_32
:
3316 unreachable("invalid index type");
3320 void radv_CmdBindIndexBuffer(
3321 VkCommandBuffer commandBuffer
,
3323 VkDeviceSize offset
,
3324 VkIndexType indexType
)
3326 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3327 RADV_FROM_HANDLE(radv_buffer
, index_buffer
, buffer
);
3329 if (cmd_buffer
->state
.index_buffer
== index_buffer
&&
3330 cmd_buffer
->state
.index_offset
== offset
&&
3331 cmd_buffer
->state
.index_type
== indexType
) {
3332 /* No state changes. */
3336 cmd_buffer
->state
.index_buffer
= index_buffer
;
3337 cmd_buffer
->state
.index_offset
= offset
;
3338 cmd_buffer
->state
.index_type
= vk_to_index_type(indexType
);
3339 cmd_buffer
->state
.index_va
= radv_buffer_get_va(index_buffer
->bo
);
3340 cmd_buffer
->state
.index_va
+= index_buffer
->offset
+ offset
;
3342 int index_size
= radv_get_vgt_index_size(vk_to_index_type(indexType
));
3343 cmd_buffer
->state
.max_index_count
= (index_buffer
->size
- offset
) / index_size
;
3344 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
3345 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, index_buffer
->bo
);
3350 radv_bind_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
3351 VkPipelineBindPoint bind_point
,
3352 struct radv_descriptor_set
*set
, unsigned idx
)
3354 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
3356 radv_set_descriptor_set(cmd_buffer
, bind_point
, set
, idx
);
3359 assert(!(set
->layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
));
3361 if (!cmd_buffer
->device
->use_global_bo_list
) {
3362 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
)
3363 if (set
->descriptors
[j
])
3364 radv_cs_add_buffer(ws
, cmd_buffer
->cs
, set
->descriptors
[j
]);
3368 radv_cs_add_buffer(ws
, cmd_buffer
->cs
, set
->bo
);
3371 void radv_CmdBindDescriptorSets(
3372 VkCommandBuffer commandBuffer
,
3373 VkPipelineBindPoint pipelineBindPoint
,
3374 VkPipelineLayout _layout
,
3376 uint32_t descriptorSetCount
,
3377 const VkDescriptorSet
* pDescriptorSets
,
3378 uint32_t dynamicOffsetCount
,
3379 const uint32_t* pDynamicOffsets
)
3381 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3382 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
3383 unsigned dyn_idx
= 0;
3385 const bool no_dynamic_bounds
= cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_NO_DYNAMIC_BOUNDS
;
3386 struct radv_descriptor_state
*descriptors_state
=
3387 radv_get_descriptors_state(cmd_buffer
, pipelineBindPoint
);
3389 for (unsigned i
= 0; i
< descriptorSetCount
; ++i
) {
3390 unsigned idx
= i
+ firstSet
;
3391 RADV_FROM_HANDLE(radv_descriptor_set
, set
, pDescriptorSets
[i
]);
3393 /* If the set is already bound we only need to update the
3394 * (potentially changed) dynamic offsets. */
3395 if (descriptors_state
->sets
[idx
] != set
||
3396 !(descriptors_state
->valid
& (1u << idx
))) {
3397 radv_bind_descriptor_set(cmd_buffer
, pipelineBindPoint
, set
, idx
);
3400 for(unsigned j
= 0; j
< set
->layout
->dynamic_offset_count
; ++j
, ++dyn_idx
) {
3401 unsigned idx
= j
+ layout
->set
[i
+ firstSet
].dynamic_offset_start
;
3402 uint32_t *dst
= descriptors_state
->dynamic_buffers
+ idx
* 4;
3403 assert(dyn_idx
< dynamicOffsetCount
);
3405 struct radv_descriptor_range
*range
= set
->dynamic_descriptors
+ j
;
3406 uint64_t va
= range
->va
+ pDynamicOffsets
[dyn_idx
];
3408 dst
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
3409 dst
[2] = no_dynamic_bounds
? 0xffffffffu
: range
->size
;
3410 dst
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3411 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3412 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3413 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3415 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3416 dst
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3417 S_008F0C_OOB_SELECT(3) |
3418 S_008F0C_RESOURCE_LEVEL(1);
3420 dst
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3421 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3424 cmd_buffer
->push_constant_stages
|=
3425 set
->layout
->dynamic_shader_stages
;
3430 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
3431 struct radv_descriptor_set
*set
,
3432 struct radv_descriptor_set_layout
*layout
,
3433 VkPipelineBindPoint bind_point
)
3435 struct radv_descriptor_state
*descriptors_state
=
3436 radv_get_descriptors_state(cmd_buffer
, bind_point
);
3437 set
->size
= layout
->size
;
3438 set
->layout
= layout
;
3440 if (descriptors_state
->push_set
.capacity
< set
->size
) {
3441 size_t new_size
= MAX2(set
->size
, 1024);
3442 new_size
= MAX2(new_size
, 2 * descriptors_state
->push_set
.capacity
);
3443 new_size
= MIN2(new_size
, 96 * MAX_PUSH_DESCRIPTORS
);
3445 free(set
->mapped_ptr
);
3446 set
->mapped_ptr
= malloc(new_size
);
3448 if (!set
->mapped_ptr
) {
3449 descriptors_state
->push_set
.capacity
= 0;
3450 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
3454 descriptors_state
->push_set
.capacity
= new_size
;
3460 void radv_meta_push_descriptor_set(
3461 struct radv_cmd_buffer
* cmd_buffer
,
3462 VkPipelineBindPoint pipelineBindPoint
,
3463 VkPipelineLayout _layout
,
3465 uint32_t descriptorWriteCount
,
3466 const VkWriteDescriptorSet
* pDescriptorWrites
)
3468 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
3469 struct radv_descriptor_set
*push_set
= &cmd_buffer
->meta_push_descriptors
;
3473 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
3475 push_set
->size
= layout
->set
[set
].layout
->size
;
3476 push_set
->layout
= layout
->set
[set
].layout
;
3478 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, push_set
->size
, 32,
3480 (void**) &push_set
->mapped_ptr
))
3483 push_set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
3484 push_set
->va
+= bo_offset
;
3486 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
3487 radv_descriptor_set_to_handle(push_set
),
3488 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
3490 radv_set_descriptor_set(cmd_buffer
, pipelineBindPoint
, push_set
, set
);
3493 void radv_CmdPushDescriptorSetKHR(
3494 VkCommandBuffer commandBuffer
,
3495 VkPipelineBindPoint pipelineBindPoint
,
3496 VkPipelineLayout _layout
,
3498 uint32_t descriptorWriteCount
,
3499 const VkWriteDescriptorSet
* pDescriptorWrites
)
3501 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3502 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
3503 struct radv_descriptor_state
*descriptors_state
=
3504 radv_get_descriptors_state(cmd_buffer
, pipelineBindPoint
);
3505 struct radv_descriptor_set
*push_set
= &descriptors_state
->push_set
.set
;
3507 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
3509 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
,
3510 layout
->set
[set
].layout
,
3514 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3515 * because it is invalid, according to Vulkan spec.
3517 for (int i
= 0; i
< descriptorWriteCount
; i
++) {
3518 ASSERTED
const VkWriteDescriptorSet
*writeset
= &pDescriptorWrites
[i
];
3519 assert(writeset
->descriptorType
!= VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
);
3522 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
3523 radv_descriptor_set_to_handle(push_set
),
3524 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
3526 radv_set_descriptor_set(cmd_buffer
, pipelineBindPoint
, push_set
, set
);
3527 descriptors_state
->push_dirty
= true;
3530 void radv_CmdPushDescriptorSetWithTemplateKHR(
3531 VkCommandBuffer commandBuffer
,
3532 VkDescriptorUpdateTemplate descriptorUpdateTemplate
,
3533 VkPipelineLayout _layout
,
3537 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3538 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
3539 RADV_FROM_HANDLE(radv_descriptor_update_template
, templ
, descriptorUpdateTemplate
);
3540 struct radv_descriptor_state
*descriptors_state
=
3541 radv_get_descriptors_state(cmd_buffer
, templ
->bind_point
);
3542 struct radv_descriptor_set
*push_set
= &descriptors_state
->push_set
.set
;
3544 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
3546 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
,
3547 layout
->set
[set
].layout
,
3551 radv_update_descriptor_set_with_template(cmd_buffer
->device
, cmd_buffer
, push_set
,
3552 descriptorUpdateTemplate
, pData
);
3554 radv_set_descriptor_set(cmd_buffer
, templ
->bind_point
, push_set
, set
);
3555 descriptors_state
->push_dirty
= true;
3558 void radv_CmdPushConstants(VkCommandBuffer commandBuffer
,
3559 VkPipelineLayout layout
,
3560 VkShaderStageFlags stageFlags
,
3563 const void* pValues
)
3565 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3566 memcpy(cmd_buffer
->push_constants
+ offset
, pValues
, size
);
3567 cmd_buffer
->push_constant_stages
|= stageFlags
;
3570 VkResult
radv_EndCommandBuffer(
3571 VkCommandBuffer commandBuffer
)
3573 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3575 if (cmd_buffer
->queue_family_index
!= RADV_QUEUE_TRANSFER
) {
3576 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX6
)
3577 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
| RADV_CMD_FLAG_WB_L2
;
3579 /* Make sure to sync all pending active queries at the end of
3582 cmd_buffer
->state
.flush_bits
|= cmd_buffer
->active_query_flush_bits
;
3584 si_emit_cache_flush(cmd_buffer
);
3587 /* Make sure CP DMA is idle at the end of IBs because the kernel
3588 * doesn't wait for it.
3590 si_cp_dma_wait_for_idle(cmd_buffer
);
3592 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
3593 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.subpass_sample_locs
);
3595 if (!cmd_buffer
->device
->ws
->cs_finalize(cmd_buffer
->cs
))
3596 return vk_error(cmd_buffer
->device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
3598 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_EXECUTABLE
;
3600 return cmd_buffer
->record_result
;
3604 radv_emit_compute_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
3606 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
3608 if (!pipeline
|| pipeline
== cmd_buffer
->state
.emitted_compute_pipeline
)
3611 assert(!pipeline
->ctx_cs
.cdw
);
3613 cmd_buffer
->state
.emitted_compute_pipeline
= pipeline
;
3615 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, pipeline
->cs
.cdw
);
3616 radeon_emit_array(cmd_buffer
->cs
, pipeline
->cs
.buf
, pipeline
->cs
.cdw
);
3618 cmd_buffer
->compute_scratch_size_needed
=
3619 MAX2(cmd_buffer
->compute_scratch_size_needed
,
3620 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
3622 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
3623 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->bo
);
3625 if (unlikely(cmd_buffer
->device
->trace_bo
))
3626 radv_save_pipeline(cmd_buffer
, pipeline
, RING_COMPUTE
);
3629 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer
*cmd_buffer
,
3630 VkPipelineBindPoint bind_point
)
3632 struct radv_descriptor_state
*descriptors_state
=
3633 radv_get_descriptors_state(cmd_buffer
, bind_point
);
3635 descriptors_state
->dirty
|= descriptors_state
->valid
;
3638 void radv_CmdBindPipeline(
3639 VkCommandBuffer commandBuffer
,
3640 VkPipelineBindPoint pipelineBindPoint
,
3641 VkPipeline _pipeline
)
3643 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3644 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
3646 switch (pipelineBindPoint
) {
3647 case VK_PIPELINE_BIND_POINT_COMPUTE
:
3648 if (cmd_buffer
->state
.compute_pipeline
== pipeline
)
3650 radv_mark_descriptor_sets_dirty(cmd_buffer
, pipelineBindPoint
);
3652 cmd_buffer
->state
.compute_pipeline
= pipeline
;
3653 cmd_buffer
->push_constant_stages
|= VK_SHADER_STAGE_COMPUTE_BIT
;
3655 case VK_PIPELINE_BIND_POINT_GRAPHICS
:
3656 if (cmd_buffer
->state
.pipeline
== pipeline
)
3658 radv_mark_descriptor_sets_dirty(cmd_buffer
, pipelineBindPoint
);
3660 cmd_buffer
->state
.pipeline
= pipeline
;
3664 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
;
3665 cmd_buffer
->push_constant_stages
|= pipeline
->active_stages
;
3667 /* the new vertex shader might not have the same user regs */
3668 cmd_buffer
->state
.last_first_instance
= -1;
3669 cmd_buffer
->state
.last_vertex_offset
= -1;
3671 /* Prefetch all pipeline shaders at first draw time. */
3672 cmd_buffer
->state
.prefetch_L2_mask
|= RADV_PREFETCH_SHADERS
;
3674 if ((cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_NAVI10
||
3675 cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_NAVI12
||
3676 cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_NAVI14
) &&
3677 cmd_buffer
->state
.emitted_pipeline
&&
3678 radv_pipeline_has_ngg(cmd_buffer
->state
.emitted_pipeline
) &&
3679 !radv_pipeline_has_ngg(cmd_buffer
->state
.pipeline
)) {
3680 /* Transitioning from NGG to legacy GS requires
3681 * VGT_FLUSH on Navi10-14. VGT_FLUSH is also emitted
3682 * at the beginning of IBs when legacy GS ring pointers
3685 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VGT_FLUSH
;
3688 radv_bind_dynamic_state(cmd_buffer
, &pipeline
->dynamic_state
);
3689 radv_bind_streamout_state(cmd_buffer
, pipeline
);
3691 if (pipeline
->graphics
.esgs_ring_size
> cmd_buffer
->esgs_ring_size_needed
)
3692 cmd_buffer
->esgs_ring_size_needed
= pipeline
->graphics
.esgs_ring_size
;
3693 if (pipeline
->graphics
.gsvs_ring_size
> cmd_buffer
->gsvs_ring_size_needed
)
3694 cmd_buffer
->gsvs_ring_size_needed
= pipeline
->graphics
.gsvs_ring_size
;
3696 if (radv_pipeline_has_tess(pipeline
))
3697 cmd_buffer
->tess_rings_needed
= true;
3700 assert(!"invalid bind point");
3705 void radv_CmdSetViewport(
3706 VkCommandBuffer commandBuffer
,
3707 uint32_t firstViewport
,
3708 uint32_t viewportCount
,
3709 const VkViewport
* pViewports
)
3711 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3712 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3713 ASSERTED
const uint32_t total_count
= firstViewport
+ viewportCount
;
3715 assert(firstViewport
< MAX_VIEWPORTS
);
3716 assert(total_count
>= 1 && total_count
<= MAX_VIEWPORTS
);
3718 if (!memcmp(state
->dynamic
.viewport
.viewports
+ firstViewport
,
3719 pViewports
, viewportCount
* sizeof(*pViewports
))) {
3723 memcpy(state
->dynamic
.viewport
.viewports
+ firstViewport
, pViewports
,
3724 viewportCount
* sizeof(*pViewports
));
3726 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
3729 void radv_CmdSetScissor(
3730 VkCommandBuffer commandBuffer
,
3731 uint32_t firstScissor
,
3732 uint32_t scissorCount
,
3733 const VkRect2D
* pScissors
)
3735 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3736 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3737 ASSERTED
const uint32_t total_count
= firstScissor
+ scissorCount
;
3739 assert(firstScissor
< MAX_SCISSORS
);
3740 assert(total_count
>= 1 && total_count
<= MAX_SCISSORS
);
3742 if (!memcmp(state
->dynamic
.scissor
.scissors
+ firstScissor
, pScissors
,
3743 scissorCount
* sizeof(*pScissors
))) {
3747 memcpy(state
->dynamic
.scissor
.scissors
+ firstScissor
, pScissors
,
3748 scissorCount
* sizeof(*pScissors
));
3750 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
3753 void radv_CmdSetLineWidth(
3754 VkCommandBuffer commandBuffer
,
3757 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3759 if (cmd_buffer
->state
.dynamic
.line_width
== lineWidth
)
3762 cmd_buffer
->state
.dynamic
.line_width
= lineWidth
;
3763 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
3766 void radv_CmdSetDepthBias(
3767 VkCommandBuffer commandBuffer
,
3768 float depthBiasConstantFactor
,
3769 float depthBiasClamp
,
3770 float depthBiasSlopeFactor
)
3772 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3773 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3775 if (state
->dynamic
.depth_bias
.bias
== depthBiasConstantFactor
&&
3776 state
->dynamic
.depth_bias
.clamp
== depthBiasClamp
&&
3777 state
->dynamic
.depth_bias
.slope
== depthBiasSlopeFactor
) {
3781 state
->dynamic
.depth_bias
.bias
= depthBiasConstantFactor
;
3782 state
->dynamic
.depth_bias
.clamp
= depthBiasClamp
;
3783 state
->dynamic
.depth_bias
.slope
= depthBiasSlopeFactor
;
3785 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
3788 void radv_CmdSetBlendConstants(
3789 VkCommandBuffer commandBuffer
,
3790 const float blendConstants
[4])
3792 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3793 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3795 if (!memcmp(state
->dynamic
.blend_constants
, blendConstants
, sizeof(float) * 4))
3798 memcpy(state
->dynamic
.blend_constants
, blendConstants
, sizeof(float) * 4);
3800 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
3803 void radv_CmdSetDepthBounds(
3804 VkCommandBuffer commandBuffer
,
3805 float minDepthBounds
,
3806 float maxDepthBounds
)
3808 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3809 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3811 if (state
->dynamic
.depth_bounds
.min
== minDepthBounds
&&
3812 state
->dynamic
.depth_bounds
.max
== maxDepthBounds
) {
3816 state
->dynamic
.depth_bounds
.min
= minDepthBounds
;
3817 state
->dynamic
.depth_bounds
.max
= maxDepthBounds
;
3819 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
3822 void radv_CmdSetStencilCompareMask(
3823 VkCommandBuffer commandBuffer
,
3824 VkStencilFaceFlags faceMask
,
3825 uint32_t compareMask
)
3827 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3828 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3829 bool front_same
= state
->dynamic
.stencil_compare_mask
.front
== compareMask
;
3830 bool back_same
= state
->dynamic
.stencil_compare_mask
.back
== compareMask
;
3832 if ((!(faceMask
& VK_STENCIL_FACE_FRONT_BIT
) || front_same
) &&
3833 (!(faceMask
& VK_STENCIL_FACE_BACK_BIT
) || back_same
)) {
3837 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
3838 state
->dynamic
.stencil_compare_mask
.front
= compareMask
;
3839 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
3840 state
->dynamic
.stencil_compare_mask
.back
= compareMask
;
3842 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
3845 void radv_CmdSetStencilWriteMask(
3846 VkCommandBuffer commandBuffer
,
3847 VkStencilFaceFlags faceMask
,
3850 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3851 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3852 bool front_same
= state
->dynamic
.stencil_write_mask
.front
== writeMask
;
3853 bool back_same
= state
->dynamic
.stencil_write_mask
.back
== writeMask
;
3855 if ((!(faceMask
& VK_STENCIL_FACE_FRONT_BIT
) || front_same
) &&
3856 (!(faceMask
& VK_STENCIL_FACE_BACK_BIT
) || back_same
)) {
3860 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
3861 state
->dynamic
.stencil_write_mask
.front
= writeMask
;
3862 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
3863 state
->dynamic
.stencil_write_mask
.back
= writeMask
;
3865 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
3868 void radv_CmdSetStencilReference(
3869 VkCommandBuffer commandBuffer
,
3870 VkStencilFaceFlags faceMask
,
3873 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3874 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3875 bool front_same
= state
->dynamic
.stencil_reference
.front
== reference
;
3876 bool back_same
= state
->dynamic
.stencil_reference
.back
== reference
;
3878 if ((!(faceMask
& VK_STENCIL_FACE_FRONT_BIT
) || front_same
) &&
3879 (!(faceMask
& VK_STENCIL_FACE_BACK_BIT
) || back_same
)) {
3883 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
3884 cmd_buffer
->state
.dynamic
.stencil_reference
.front
= reference
;
3885 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
3886 cmd_buffer
->state
.dynamic
.stencil_reference
.back
= reference
;
3888 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
3891 void radv_CmdSetDiscardRectangleEXT(
3892 VkCommandBuffer commandBuffer
,
3893 uint32_t firstDiscardRectangle
,
3894 uint32_t discardRectangleCount
,
3895 const VkRect2D
* pDiscardRectangles
)
3897 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3898 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3899 ASSERTED
const uint32_t total_count
= firstDiscardRectangle
+ discardRectangleCount
;
3901 assert(firstDiscardRectangle
< MAX_DISCARD_RECTANGLES
);
3902 assert(total_count
>= 1 && total_count
<= MAX_DISCARD_RECTANGLES
);
3904 if (!memcmp(state
->dynamic
.discard_rectangle
.rectangles
+ firstDiscardRectangle
,
3905 pDiscardRectangles
, discardRectangleCount
* sizeof(*pDiscardRectangles
))) {
3909 typed_memcpy(&state
->dynamic
.discard_rectangle
.rectangles
[firstDiscardRectangle
],
3910 pDiscardRectangles
, discardRectangleCount
);
3912 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
;
3915 void radv_CmdSetSampleLocationsEXT(
3916 VkCommandBuffer commandBuffer
,
3917 const VkSampleLocationsInfoEXT
* pSampleLocationsInfo
)
3919 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3920 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3922 assert(pSampleLocationsInfo
->sampleLocationsCount
<= MAX_SAMPLE_LOCATIONS
);
3924 state
->dynamic
.sample_location
.per_pixel
= pSampleLocationsInfo
->sampleLocationsPerPixel
;
3925 state
->dynamic
.sample_location
.grid_size
= pSampleLocationsInfo
->sampleLocationGridSize
;
3926 state
->dynamic
.sample_location
.count
= pSampleLocationsInfo
->sampleLocationsCount
;
3927 typed_memcpy(&state
->dynamic
.sample_location
.locations
[0],
3928 pSampleLocationsInfo
->pSampleLocations
,
3929 pSampleLocationsInfo
->sampleLocationsCount
);
3931 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS
;
3934 void radv_CmdExecuteCommands(
3935 VkCommandBuffer commandBuffer
,
3936 uint32_t commandBufferCount
,
3937 const VkCommandBuffer
* pCmdBuffers
)
3939 RADV_FROM_HANDLE(radv_cmd_buffer
, primary
, commandBuffer
);
3941 assert(commandBufferCount
> 0);
3943 /* Emit pending flushes on primary prior to executing secondary */
3944 si_emit_cache_flush(primary
);
3946 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
3947 RADV_FROM_HANDLE(radv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
3949 primary
->scratch_size_needed
= MAX2(primary
->scratch_size_needed
,
3950 secondary
->scratch_size_needed
);
3951 primary
->compute_scratch_size_needed
= MAX2(primary
->compute_scratch_size_needed
,
3952 secondary
->compute_scratch_size_needed
);
3954 if (secondary
->esgs_ring_size_needed
> primary
->esgs_ring_size_needed
)
3955 primary
->esgs_ring_size_needed
= secondary
->esgs_ring_size_needed
;
3956 if (secondary
->gsvs_ring_size_needed
> primary
->gsvs_ring_size_needed
)
3957 primary
->gsvs_ring_size_needed
= secondary
->gsvs_ring_size_needed
;
3958 if (secondary
->tess_rings_needed
)
3959 primary
->tess_rings_needed
= true;
3960 if (secondary
->sample_positions_needed
)
3961 primary
->sample_positions_needed
= true;
3963 if (!secondary
->state
.framebuffer
&&
3964 (primary
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
)) {
3965 /* Emit the framebuffer state from primary if secondary
3966 * has been recorded without a framebuffer, otherwise
3967 * fast color/depth clears can't work.
3969 radv_emit_framebuffer_state(primary
);
3972 primary
->device
->ws
->cs_execute_secondary(primary
->cs
, secondary
->cs
);
3975 /* When the secondary command buffer is compute only we don't
3976 * need to re-emit the current graphics pipeline.
3978 if (secondary
->state
.emitted_pipeline
) {
3979 primary
->state
.emitted_pipeline
=
3980 secondary
->state
.emitted_pipeline
;
3983 /* When the secondary command buffer is graphics only we don't
3984 * need to re-emit the current compute pipeline.
3986 if (secondary
->state
.emitted_compute_pipeline
) {
3987 primary
->state
.emitted_compute_pipeline
=
3988 secondary
->state
.emitted_compute_pipeline
;
3991 /* Only re-emit the draw packets when needed. */
3992 if (secondary
->state
.last_primitive_reset_en
!= -1) {
3993 primary
->state
.last_primitive_reset_en
=
3994 secondary
->state
.last_primitive_reset_en
;
3997 if (secondary
->state
.last_primitive_reset_index
) {
3998 primary
->state
.last_primitive_reset_index
=
3999 secondary
->state
.last_primitive_reset_index
;
4002 if (secondary
->state
.last_ia_multi_vgt_param
) {
4003 primary
->state
.last_ia_multi_vgt_param
=
4004 secondary
->state
.last_ia_multi_vgt_param
;
4007 primary
->state
.last_first_instance
= secondary
->state
.last_first_instance
;
4008 primary
->state
.last_num_instances
= secondary
->state
.last_num_instances
;
4009 primary
->state
.last_vertex_offset
= secondary
->state
.last_vertex_offset
;
4011 if (secondary
->state
.last_index_type
!= -1) {
4012 primary
->state
.last_index_type
=
4013 secondary
->state
.last_index_type
;
4017 /* After executing commands from secondary buffers we have to dirty
4020 primary
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
|
4021 RADV_CMD_DIRTY_INDEX_BUFFER
|
4022 RADV_CMD_DIRTY_DYNAMIC_ALL
;
4023 radv_mark_descriptor_sets_dirty(primary
, VK_PIPELINE_BIND_POINT_GRAPHICS
);
4024 radv_mark_descriptor_sets_dirty(primary
, VK_PIPELINE_BIND_POINT_COMPUTE
);
4027 VkResult
radv_CreateCommandPool(
4029 const VkCommandPoolCreateInfo
* pCreateInfo
,
4030 const VkAllocationCallbacks
* pAllocator
,
4031 VkCommandPool
* pCmdPool
)
4033 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4034 struct radv_cmd_pool
*pool
;
4036 pool
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pool
), 8,
4037 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4039 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4042 pool
->alloc
= *pAllocator
;
4044 pool
->alloc
= device
->alloc
;
4046 list_inithead(&pool
->cmd_buffers
);
4047 list_inithead(&pool
->free_cmd_buffers
);
4049 pool
->queue_family_index
= pCreateInfo
->queueFamilyIndex
;
4051 *pCmdPool
= radv_cmd_pool_to_handle(pool
);
4057 void radv_DestroyCommandPool(
4059 VkCommandPool commandPool
,
4060 const VkAllocationCallbacks
* pAllocator
)
4062 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4063 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
4068 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
4069 &pool
->cmd_buffers
, pool_link
) {
4070 radv_cmd_buffer_destroy(cmd_buffer
);
4073 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
4074 &pool
->free_cmd_buffers
, pool_link
) {
4075 radv_cmd_buffer_destroy(cmd_buffer
);
4078 vk_free2(&device
->alloc
, pAllocator
, pool
);
4081 VkResult
radv_ResetCommandPool(
4083 VkCommandPool commandPool
,
4084 VkCommandPoolResetFlags flags
)
4086 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
4089 list_for_each_entry(struct radv_cmd_buffer
, cmd_buffer
,
4090 &pool
->cmd_buffers
, pool_link
) {
4091 result
= radv_reset_cmd_buffer(cmd_buffer
);
4092 if (result
!= VK_SUCCESS
)
4099 void radv_TrimCommandPool(
4101 VkCommandPool commandPool
,
4102 VkCommandPoolTrimFlags flags
)
4104 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
4109 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
4110 &pool
->free_cmd_buffers
, pool_link
) {
4111 radv_cmd_buffer_destroy(cmd_buffer
);
4116 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer
*cmd_buffer
,
4117 uint32_t subpass_id
)
4119 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4120 struct radv_subpass
*subpass
= &state
->pass
->subpasses
[subpass_id
];
4122 ASSERTED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
4123 cmd_buffer
->cs
, 4096);
4125 radv_subpass_barrier(cmd_buffer
, &subpass
->start_barrier
);
4127 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
);
4129 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4130 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4131 if (a
== VK_ATTACHMENT_UNUSED
)
4134 radv_handle_subpass_image_transition(cmd_buffer
,
4135 subpass
->attachments
[i
],
4139 radv_cmd_buffer_clear_subpass(cmd_buffer
);
4141 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4145 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer
*cmd_buffer
)
4147 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4148 const struct radv_subpass
*subpass
= state
->subpass
;
4149 uint32_t subpass_id
= radv_get_subpass_id(cmd_buffer
);
4151 radv_cmd_buffer_resolve_subpass(cmd_buffer
);
4153 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4154 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4155 if (a
== VK_ATTACHMENT_UNUSED
)
4158 if (state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
4161 VkImageLayout layout
= state
->pass
->attachments
[a
].final_layout
;
4162 struct radv_subpass_attachment att
= { a
, layout
};
4163 radv_handle_subpass_image_transition(cmd_buffer
, att
, false);
4167 void radv_CmdBeginRenderPass(
4168 VkCommandBuffer commandBuffer
,
4169 const VkRenderPassBeginInfo
* pRenderPassBegin
,
4170 VkSubpassContents contents
)
4172 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4173 RADV_FROM_HANDLE(radv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
4174 RADV_FROM_HANDLE(radv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
4177 cmd_buffer
->state
.framebuffer
= framebuffer
;
4178 cmd_buffer
->state
.pass
= pass
;
4179 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
4181 result
= radv_cmd_state_setup_attachments(cmd_buffer
, pass
, pRenderPassBegin
);
4182 if (result
!= VK_SUCCESS
)
4185 result
= radv_cmd_state_setup_sample_locations(cmd_buffer
, pass
, pRenderPassBegin
);
4186 if (result
!= VK_SUCCESS
)
4189 radv_cmd_buffer_begin_subpass(cmd_buffer
, 0);
4192 void radv_CmdBeginRenderPass2KHR(
4193 VkCommandBuffer commandBuffer
,
4194 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
4195 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
)
4197 radv_CmdBeginRenderPass(commandBuffer
, pRenderPassBeginInfo
,
4198 pSubpassBeginInfo
->contents
);
4201 void radv_CmdNextSubpass(
4202 VkCommandBuffer commandBuffer
,
4203 VkSubpassContents contents
)
4205 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4207 uint32_t prev_subpass
= radv_get_subpass_id(cmd_buffer
);
4208 radv_cmd_buffer_end_subpass(cmd_buffer
);
4209 radv_cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
4212 void radv_CmdNextSubpass2KHR(
4213 VkCommandBuffer commandBuffer
,
4214 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
,
4215 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
4217 radv_CmdNextSubpass(commandBuffer
, pSubpassBeginInfo
->contents
);
4220 static void radv_emit_view_index(struct radv_cmd_buffer
*cmd_buffer
, unsigned index
)
4222 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
4223 for (unsigned stage
= 0; stage
< MESA_SHADER_STAGES
; ++stage
) {
4224 if (!radv_get_shader(pipeline
, stage
))
4227 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, AC_UD_VIEW_INDEX
);
4228 if (loc
->sgpr_idx
== -1)
4230 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
4231 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
4234 if (radv_pipeline_has_gs_copy_shader(pipeline
)) {
4235 struct radv_userdata_info
*loc
= &pipeline
->gs_copy_shader
->info
.user_sgprs_locs
.shader_data
[AC_UD_VIEW_INDEX
];
4236 if (loc
->sgpr_idx
!= -1) {
4237 uint32_t base_reg
= R_00B130_SPI_SHADER_USER_DATA_VS_0
;
4238 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
4244 radv_cs_emit_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
4245 uint32_t vertex_count
,
4248 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, cmd_buffer
->state
.predicating
));
4249 radeon_emit(cmd_buffer
->cs
, vertex_count
);
4250 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
4251 S_0287F0_USE_OPAQUE(use_opaque
));
4255 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer
*cmd_buffer
,
4257 uint32_t index_count
)
4259 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_2
, 4, cmd_buffer
->state
.predicating
));
4260 radeon_emit(cmd_buffer
->cs
, cmd_buffer
->state
.max_index_count
);
4261 radeon_emit(cmd_buffer
->cs
, index_va
);
4262 radeon_emit(cmd_buffer
->cs
, index_va
>> 32);
4263 radeon_emit(cmd_buffer
->cs
, index_count
);
4264 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_DMA
);
4268 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
4270 uint32_t draw_count
,
4274 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4275 unsigned di_src_sel
= indexed
? V_0287F0_DI_SRC_SEL_DMA
4276 : V_0287F0_DI_SRC_SEL_AUTO_INDEX
;
4277 bool draw_id_enable
= radv_get_shader(cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
)->info
.info
.vs
.needs_draw_id
;
4278 uint32_t base_reg
= cmd_buffer
->state
.pipeline
->graphics
.vtx_base_sgpr
;
4279 bool predicating
= cmd_buffer
->state
.predicating
;
4282 /* just reset draw state for vertex data */
4283 cmd_buffer
->state
.last_first_instance
= -1;
4284 cmd_buffer
->state
.last_num_instances
= -1;
4285 cmd_buffer
->state
.last_vertex_offset
= -1;
4287 if (draw_count
== 1 && !count_va
&& !draw_id_enable
) {
4288 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT
:
4289 PKT3_DRAW_INDIRECT
, 3, predicating
));
4291 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
4292 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
4293 radeon_emit(cs
, di_src_sel
);
4295 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT_MULTI
:
4296 PKT3_DRAW_INDIRECT_MULTI
,
4299 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
4300 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
4301 radeon_emit(cs
, (((base_reg
+ 8) - SI_SH_REG_OFFSET
) >> 2) |
4302 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable
) |
4303 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va
));
4304 radeon_emit(cs
, draw_count
); /* count */
4305 radeon_emit(cs
, count_va
); /* count_addr */
4306 radeon_emit(cs
, count_va
>> 32);
4307 radeon_emit(cs
, stride
); /* stride */
4308 radeon_emit(cs
, di_src_sel
);
4313 radv_emit_draw_packets(struct radv_cmd_buffer
*cmd_buffer
,
4314 const struct radv_draw_info
*info
)
4316 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4317 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
4318 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4320 if (info
->indirect
) {
4321 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
4322 uint64_t count_va
= 0;
4324 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
4326 radv_cs_add_buffer(ws
, cs
, info
->indirect
->bo
);
4328 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0));
4330 radeon_emit(cs
, va
);
4331 radeon_emit(cs
, va
>> 32);
4333 if (info
->count_buffer
) {
4334 count_va
= radv_buffer_get_va(info
->count_buffer
->bo
);
4335 count_va
+= info
->count_buffer
->offset
+
4336 info
->count_buffer_offset
;
4338 radv_cs_add_buffer(ws
, cs
, info
->count_buffer
->bo
);
4341 if (!state
->subpass
->view_mask
) {
4342 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
4349 for_each_bit(i
, state
->subpass
->view_mask
) {
4350 radv_emit_view_index(cmd_buffer
, i
);
4352 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
4360 assert(state
->pipeline
->graphics
.vtx_base_sgpr
);
4362 if (info
->vertex_offset
!= state
->last_vertex_offset
||
4363 info
->first_instance
!= state
->last_first_instance
) {
4364 radeon_set_sh_reg_seq(cs
, state
->pipeline
->graphics
.vtx_base_sgpr
,
4365 state
->pipeline
->graphics
.vtx_emit_num
);
4367 radeon_emit(cs
, info
->vertex_offset
);
4368 radeon_emit(cs
, info
->first_instance
);
4369 if (state
->pipeline
->graphics
.vtx_emit_num
== 3)
4371 state
->last_first_instance
= info
->first_instance
;
4372 state
->last_vertex_offset
= info
->vertex_offset
;
4375 if (state
->last_num_instances
!= info
->instance_count
) {
4376 radeon_emit(cs
, PKT3(PKT3_NUM_INSTANCES
, 0, false));
4377 radeon_emit(cs
, info
->instance_count
);
4378 state
->last_num_instances
= info
->instance_count
;
4381 if (info
->indexed
) {
4382 int index_size
= radv_get_vgt_index_size(state
->index_type
);
4385 /* Skip draw calls with 0-sized index buffers. They
4386 * cause a hang on some chips, like Navi10-14.
4388 if (!cmd_buffer
->state
.max_index_count
)
4391 index_va
= state
->index_va
;
4392 index_va
+= info
->first_index
* index_size
;
4394 if (!state
->subpass
->view_mask
) {
4395 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
4400 for_each_bit(i
, state
->subpass
->view_mask
) {
4401 radv_emit_view_index(cmd_buffer
, i
);
4403 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
4409 if (!state
->subpass
->view_mask
) {
4410 radv_cs_emit_draw_packet(cmd_buffer
,
4412 !!info
->strmout_buffer
);
4415 for_each_bit(i
, state
->subpass
->view_mask
) {
4416 radv_emit_view_index(cmd_buffer
, i
);
4418 radv_cs_emit_draw_packet(cmd_buffer
,
4420 !!info
->strmout_buffer
);
4428 * Vega and raven have a bug which triggers if there are multiple context
4429 * register contexts active at the same time with different scissor values.
4431 * There are two possible workarounds:
4432 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
4433 * there is only ever 1 active set of scissor values at the same time.
4435 * 2) Whenever the hardware switches contexts we have to set the scissor
4436 * registers again even if it is a noop. That way the new context gets
4437 * the correct scissor values.
4439 * This implements option 2. radv_need_late_scissor_emission needs to
4440 * return true on affected HW if radv_emit_all_graphics_states sets
4441 * any context registers.
4443 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer
*cmd_buffer
,
4444 const struct radv_draw_info
*info
)
4446 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4448 if (!cmd_buffer
->device
->physical_device
->has_scissor_bug
)
4451 if (cmd_buffer
->state
.context_roll_without_scissor_emitted
|| info
->strmout_buffer
)
4454 uint32_t used_states
= cmd_buffer
->state
.pipeline
->graphics
.needed_dynamic_state
| ~RADV_CMD_DIRTY_DYNAMIC_ALL
;
4456 /* Index, vertex and streamout buffers don't change context regs, and
4457 * pipeline is already handled.
4459 used_states
&= ~(RADV_CMD_DIRTY_INDEX_BUFFER
|
4460 RADV_CMD_DIRTY_VERTEX_BUFFER
|
4461 RADV_CMD_DIRTY_STREAMOUT_BUFFER
|
4462 RADV_CMD_DIRTY_PIPELINE
);
4464 if (cmd_buffer
->state
.dirty
& used_states
)
4467 uint32_t primitive_reset_index
=
4468 radv_get_primitive_reset_index(cmd_buffer
);
4470 if (info
->indexed
&& state
->pipeline
->graphics
.prim_restart_enable
&&
4471 primitive_reset_index
!= state
->last_primitive_reset_index
)
4478 radv_emit_all_graphics_states(struct radv_cmd_buffer
*cmd_buffer
,
4479 const struct radv_draw_info
*info
)
4481 bool late_scissor_emission
;
4483 if ((cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
) ||
4484 cmd_buffer
->state
.emitted_pipeline
!= cmd_buffer
->state
.pipeline
)
4485 radv_emit_rbplus_state(cmd_buffer
);
4487 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
)
4488 radv_emit_graphics_pipeline(cmd_buffer
);
4490 /* This should be before the cmd_buffer->state.dirty is cleared
4491 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4492 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4493 late_scissor_emission
=
4494 radv_need_late_scissor_emission(cmd_buffer
, info
);
4496 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
)
4497 radv_emit_framebuffer_state(cmd_buffer
);
4499 if (info
->indexed
) {
4500 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_INDEX_BUFFER
)
4501 radv_emit_index_buffer(cmd_buffer
);
4503 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4504 * so the state must be re-emitted before the next indexed
4507 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4508 cmd_buffer
->state
.last_index_type
= -1;
4509 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
4513 radv_cmd_buffer_flush_dynamic_state(cmd_buffer
);
4515 radv_emit_draw_registers(cmd_buffer
, info
);
4517 if (late_scissor_emission
)
4518 radv_emit_scissor(cmd_buffer
);
4522 radv_draw(struct radv_cmd_buffer
*cmd_buffer
,
4523 const struct radv_draw_info
*info
)
4525 struct radeon_info
*rad_info
=
4526 &cmd_buffer
->device
->physical_device
->rad_info
;
4528 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
4529 bool pipeline_is_dirty
=
4530 (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
) &&
4531 cmd_buffer
->state
.pipeline
!= cmd_buffer
->state
.emitted_pipeline
;
4533 ASSERTED
unsigned cdw_max
=
4534 radeon_check_space(cmd_buffer
->device
->ws
,
4535 cmd_buffer
->cs
, 4096);
4537 if (likely(!info
->indirect
)) {
4538 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4539 * no workaround for indirect draws, but we can at least skip
4542 if (unlikely(!info
->instance_count
))
4545 /* Handle count == 0. */
4546 if (unlikely(!info
->count
&& !info
->strmout_buffer
))
4550 /* Use optimal packet order based on whether we need to sync the
4553 if (cmd_buffer
->state
.flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4554 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4555 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
4556 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)) {
4557 /* If we have to wait for idle, set all states first, so that
4558 * all SET packets are processed in parallel with previous draw
4559 * calls. Then upload descriptors, set shader pointers, and
4560 * draw, and prefetch at the end. This ensures that the time
4561 * the CUs are idle is very short. (there are only SET_SH
4562 * packets between the wait and the draw)
4564 radv_emit_all_graphics_states(cmd_buffer
, info
);
4565 si_emit_cache_flush(cmd_buffer
);
4566 /* <-- CUs are idle here --> */
4568 radv_upload_graphics_shader_descriptors(cmd_buffer
, pipeline_is_dirty
);
4570 radv_emit_draw_packets(cmd_buffer
, info
);
4571 /* <-- CUs are busy here --> */
4573 /* Start prefetches after the draw has been started. Both will
4574 * run in parallel, but starting the draw first is more
4577 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
4578 radv_emit_prefetch_L2(cmd_buffer
,
4579 cmd_buffer
->state
.pipeline
, false);
4582 /* If we don't wait for idle, start prefetches first, then set
4583 * states, and draw at the end.
4585 si_emit_cache_flush(cmd_buffer
);
4587 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
4588 /* Only prefetch the vertex shader and VBO descriptors
4589 * in order to start the draw as soon as possible.
4591 radv_emit_prefetch_L2(cmd_buffer
,
4592 cmd_buffer
->state
.pipeline
, true);
4595 radv_upload_graphics_shader_descriptors(cmd_buffer
, pipeline_is_dirty
);
4597 radv_emit_all_graphics_states(cmd_buffer
, info
);
4598 radv_emit_draw_packets(cmd_buffer
, info
);
4600 /* Prefetch the remaining shaders after the draw has been
4603 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
4604 radv_emit_prefetch_L2(cmd_buffer
,
4605 cmd_buffer
->state
.pipeline
, false);
4609 /* Workaround for a VGT hang when streamout is enabled.
4610 * It must be done after drawing.
4612 if (cmd_buffer
->state
.streamout
.streamout_enabled
&&
4613 (rad_info
->family
== CHIP_HAWAII
||
4614 rad_info
->family
== CHIP_TONGA
||
4615 rad_info
->family
== CHIP_FIJI
)) {
4616 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC
;
4619 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4620 radv_cmd_buffer_after_draw(cmd_buffer
, RADV_CMD_FLAG_PS_PARTIAL_FLUSH
);
4624 VkCommandBuffer commandBuffer
,
4625 uint32_t vertexCount
,
4626 uint32_t instanceCount
,
4627 uint32_t firstVertex
,
4628 uint32_t firstInstance
)
4630 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4631 struct radv_draw_info info
= {};
4633 info
.count
= vertexCount
;
4634 info
.instance_count
= instanceCount
;
4635 info
.first_instance
= firstInstance
;
4636 info
.vertex_offset
= firstVertex
;
4638 radv_draw(cmd_buffer
, &info
);
4641 void radv_CmdDrawIndexed(
4642 VkCommandBuffer commandBuffer
,
4643 uint32_t indexCount
,
4644 uint32_t instanceCount
,
4645 uint32_t firstIndex
,
4646 int32_t vertexOffset
,
4647 uint32_t firstInstance
)
4649 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4650 struct radv_draw_info info
= {};
4652 info
.indexed
= true;
4653 info
.count
= indexCount
;
4654 info
.instance_count
= instanceCount
;
4655 info
.first_index
= firstIndex
;
4656 info
.vertex_offset
= vertexOffset
;
4657 info
.first_instance
= firstInstance
;
4659 radv_draw(cmd_buffer
, &info
);
4662 void radv_CmdDrawIndirect(
4663 VkCommandBuffer commandBuffer
,
4665 VkDeviceSize offset
,
4669 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4670 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4671 struct radv_draw_info info
= {};
4673 info
.count
= drawCount
;
4674 info
.indirect
= buffer
;
4675 info
.indirect_offset
= offset
;
4676 info
.stride
= stride
;
4678 radv_draw(cmd_buffer
, &info
);
4681 void radv_CmdDrawIndexedIndirect(
4682 VkCommandBuffer commandBuffer
,
4684 VkDeviceSize offset
,
4688 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4689 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4690 struct radv_draw_info info
= {};
4692 info
.indexed
= true;
4693 info
.count
= drawCount
;
4694 info
.indirect
= buffer
;
4695 info
.indirect_offset
= offset
;
4696 info
.stride
= stride
;
4698 radv_draw(cmd_buffer
, &info
);
4701 void radv_CmdDrawIndirectCountKHR(
4702 VkCommandBuffer commandBuffer
,
4704 VkDeviceSize offset
,
4705 VkBuffer _countBuffer
,
4706 VkDeviceSize countBufferOffset
,
4707 uint32_t maxDrawCount
,
4710 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4711 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4712 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
4713 struct radv_draw_info info
= {};
4715 info
.count
= maxDrawCount
;
4716 info
.indirect
= buffer
;
4717 info
.indirect_offset
= offset
;
4718 info
.count_buffer
= count_buffer
;
4719 info
.count_buffer_offset
= countBufferOffset
;
4720 info
.stride
= stride
;
4722 radv_draw(cmd_buffer
, &info
);
4725 void radv_CmdDrawIndexedIndirectCountKHR(
4726 VkCommandBuffer commandBuffer
,
4728 VkDeviceSize offset
,
4729 VkBuffer _countBuffer
,
4730 VkDeviceSize countBufferOffset
,
4731 uint32_t maxDrawCount
,
4734 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4735 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4736 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
4737 struct radv_draw_info info
= {};
4739 info
.indexed
= true;
4740 info
.count
= maxDrawCount
;
4741 info
.indirect
= buffer
;
4742 info
.indirect_offset
= offset
;
4743 info
.count_buffer
= count_buffer
;
4744 info
.count_buffer_offset
= countBufferOffset
;
4745 info
.stride
= stride
;
4747 radv_draw(cmd_buffer
, &info
);
4750 struct radv_dispatch_info
{
4752 * Determine the layout of the grid (in block units) to be used.
4757 * A starting offset for the grid. If unaligned is set, the offset
4758 * must still be aligned.
4760 uint32_t offsets
[3];
4762 * Whether it's an unaligned compute dispatch.
4767 * Indirect compute parameters resource.
4769 struct radv_buffer
*indirect
;
4770 uint64_t indirect_offset
;
4774 radv_emit_dispatch_packets(struct radv_cmd_buffer
*cmd_buffer
,
4775 const struct radv_dispatch_info
*info
)
4777 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
4778 struct radv_shader_variant
*compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
4779 unsigned dispatch_initiator
= cmd_buffer
->device
->dispatch_initiator
;
4780 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
4781 bool predicating
= cmd_buffer
->state
.predicating
;
4782 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4783 struct radv_userdata_info
*loc
;
4785 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_COMPUTE
,
4786 AC_UD_CS_GRID_SIZE
);
4788 ASSERTED
unsigned cdw_max
= radeon_check_space(ws
, cs
, 25);
4790 if (info
->indirect
) {
4791 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
4793 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
4795 radv_cs_add_buffer(ws
, cs
, info
->indirect
->bo
);
4797 if (loc
->sgpr_idx
!= -1) {
4798 for (unsigned i
= 0; i
< 3; ++i
) {
4799 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
4800 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
4801 COPY_DATA_DST_SEL(COPY_DATA_REG
));
4802 radeon_emit(cs
, (va
+ 4 * i
));
4803 radeon_emit(cs
, (va
+ 4 * i
) >> 32);
4804 radeon_emit(cs
, ((R_00B900_COMPUTE_USER_DATA_0
4805 + loc
->sgpr_idx
* 4) >> 2) + i
);
4810 if (radv_cmd_buffer_uses_mec(cmd_buffer
)) {
4811 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 2, predicating
) |
4812 PKT3_SHADER_TYPE_S(1));
4813 radeon_emit(cs
, va
);
4814 radeon_emit(cs
, va
>> 32);
4815 radeon_emit(cs
, dispatch_initiator
);
4817 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0) |
4818 PKT3_SHADER_TYPE_S(1));
4820 radeon_emit(cs
, va
);
4821 radeon_emit(cs
, va
>> 32);
4823 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 1, predicating
) |
4824 PKT3_SHADER_TYPE_S(1));
4826 radeon_emit(cs
, dispatch_initiator
);
4829 unsigned blocks
[3] = { info
->blocks
[0], info
->blocks
[1], info
->blocks
[2] };
4830 unsigned offsets
[3] = { info
->offsets
[0], info
->offsets
[1], info
->offsets
[2] };
4832 if (info
->unaligned
) {
4833 unsigned *cs_block_size
= compute_shader
->info
.cs
.block_size
;
4834 unsigned remainder
[3];
4836 /* If aligned, these should be an entire block size,
4839 remainder
[0] = blocks
[0] + cs_block_size
[0] -
4840 align_u32_npot(blocks
[0], cs_block_size
[0]);
4841 remainder
[1] = blocks
[1] + cs_block_size
[1] -
4842 align_u32_npot(blocks
[1], cs_block_size
[1]);
4843 remainder
[2] = blocks
[2] + cs_block_size
[2] -
4844 align_u32_npot(blocks
[2], cs_block_size
[2]);
4846 blocks
[0] = round_up_u32(blocks
[0], cs_block_size
[0]);
4847 blocks
[1] = round_up_u32(blocks
[1], cs_block_size
[1]);
4848 blocks
[2] = round_up_u32(blocks
[2], cs_block_size
[2]);
4850 for(unsigned i
= 0; i
< 3; ++i
) {
4851 assert(offsets
[i
] % cs_block_size
[i
] == 0);
4852 offsets
[i
] /= cs_block_size
[i
];
4855 radeon_set_sh_reg_seq(cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
4857 S_00B81C_NUM_THREAD_FULL(cs_block_size
[0]) |
4858 S_00B81C_NUM_THREAD_PARTIAL(remainder
[0]));
4860 S_00B81C_NUM_THREAD_FULL(cs_block_size
[1]) |
4861 S_00B81C_NUM_THREAD_PARTIAL(remainder
[1]));
4863 S_00B81C_NUM_THREAD_FULL(cs_block_size
[2]) |
4864 S_00B81C_NUM_THREAD_PARTIAL(remainder
[2]));
4866 dispatch_initiator
|= S_00B800_PARTIAL_TG_EN(1);
4869 if (loc
->sgpr_idx
!= -1) {
4870 assert(loc
->num_sgprs
== 3);
4872 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
+
4873 loc
->sgpr_idx
* 4, 3);
4874 radeon_emit(cs
, blocks
[0]);
4875 radeon_emit(cs
, blocks
[1]);
4876 radeon_emit(cs
, blocks
[2]);
4879 if (offsets
[0] || offsets
[1] || offsets
[2]) {
4880 radeon_set_sh_reg_seq(cs
, R_00B810_COMPUTE_START_X
, 3);
4881 radeon_emit(cs
, offsets
[0]);
4882 radeon_emit(cs
, offsets
[1]);
4883 radeon_emit(cs
, offsets
[2]);
4885 /* The blocks in the packet are not counts but end values. */
4886 for (unsigned i
= 0; i
< 3; ++i
)
4887 blocks
[i
] += offsets
[i
];
4889 dispatch_initiator
|= S_00B800_FORCE_START_AT_000(1);
4892 radeon_emit(cs
, PKT3(PKT3_DISPATCH_DIRECT
, 3, predicating
) |
4893 PKT3_SHADER_TYPE_S(1));
4894 radeon_emit(cs
, blocks
[0]);
4895 radeon_emit(cs
, blocks
[1]);
4896 radeon_emit(cs
, blocks
[2]);
4897 radeon_emit(cs
, dispatch_initiator
);
4900 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4904 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
4906 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
4907 radv_flush_constants(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
4911 radv_dispatch(struct radv_cmd_buffer
*cmd_buffer
,
4912 const struct radv_dispatch_info
*info
)
4914 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
4916 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
4917 bool pipeline_is_dirty
= pipeline
&&
4918 pipeline
!= cmd_buffer
->state
.emitted_compute_pipeline
;
4920 if (cmd_buffer
->state
.flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4921 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4922 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
4923 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)) {
4924 /* If we have to wait for idle, set all states first, so that
4925 * all SET packets are processed in parallel with previous draw
4926 * calls. Then upload descriptors, set shader pointers, and
4927 * dispatch, and prefetch at the end. This ensures that the
4928 * time the CUs are idle is very short. (there are only SET_SH
4929 * packets between the wait and the draw)
4931 radv_emit_compute_pipeline(cmd_buffer
);
4932 si_emit_cache_flush(cmd_buffer
);
4933 /* <-- CUs are idle here --> */
4935 radv_upload_compute_shader_descriptors(cmd_buffer
);
4937 radv_emit_dispatch_packets(cmd_buffer
, info
);
4938 /* <-- CUs are busy here --> */
4940 /* Start prefetches after the dispatch has been started. Both
4941 * will run in parallel, but starting the dispatch first is
4944 if (has_prefetch
&& pipeline_is_dirty
) {
4945 radv_emit_shader_prefetch(cmd_buffer
,
4946 pipeline
->shaders
[MESA_SHADER_COMPUTE
]);
4949 /* If we don't wait for idle, start prefetches first, then set
4950 * states, and dispatch at the end.
4952 si_emit_cache_flush(cmd_buffer
);
4954 if (has_prefetch
&& pipeline_is_dirty
) {
4955 radv_emit_shader_prefetch(cmd_buffer
,
4956 pipeline
->shaders
[MESA_SHADER_COMPUTE
]);
4959 radv_upload_compute_shader_descriptors(cmd_buffer
);
4961 radv_emit_compute_pipeline(cmd_buffer
);
4962 radv_emit_dispatch_packets(cmd_buffer
, info
);
4965 radv_cmd_buffer_after_draw(cmd_buffer
, RADV_CMD_FLAG_CS_PARTIAL_FLUSH
);
4968 void radv_CmdDispatchBase(
4969 VkCommandBuffer commandBuffer
,
4977 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4978 struct radv_dispatch_info info
= {};
4984 info
.offsets
[0] = base_x
;
4985 info
.offsets
[1] = base_y
;
4986 info
.offsets
[2] = base_z
;
4987 radv_dispatch(cmd_buffer
, &info
);
4990 void radv_CmdDispatch(
4991 VkCommandBuffer commandBuffer
,
4996 radv_CmdDispatchBase(commandBuffer
, 0, 0, 0, x
, y
, z
);
4999 void radv_CmdDispatchIndirect(
5000 VkCommandBuffer commandBuffer
,
5002 VkDeviceSize offset
)
5004 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5005 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
5006 struct radv_dispatch_info info
= {};
5008 info
.indirect
= buffer
;
5009 info
.indirect_offset
= offset
;
5011 radv_dispatch(cmd_buffer
, &info
);
5014 void radv_unaligned_dispatch(
5015 struct radv_cmd_buffer
*cmd_buffer
,
5020 struct radv_dispatch_info info
= {};
5027 radv_dispatch(cmd_buffer
, &info
);
5030 void radv_CmdEndRenderPass(
5031 VkCommandBuffer commandBuffer
)
5033 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5035 radv_subpass_barrier(cmd_buffer
, &cmd_buffer
->state
.pass
->end_barrier
);
5037 radv_cmd_buffer_end_subpass(cmd_buffer
);
5039 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
5040 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.subpass_sample_locs
);
5042 cmd_buffer
->state
.pass
= NULL
;
5043 cmd_buffer
->state
.subpass
= NULL
;
5044 cmd_buffer
->state
.attachments
= NULL
;
5045 cmd_buffer
->state
.framebuffer
= NULL
;
5046 cmd_buffer
->state
.subpass_sample_locs
= NULL
;
5049 void radv_CmdEndRenderPass2KHR(
5050 VkCommandBuffer commandBuffer
,
5051 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
5053 radv_CmdEndRenderPass(commandBuffer
);
5057 * For HTILE we have the following interesting clear words:
5058 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
5059 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
5060 * 0xfffffff0: Clear depth to 1.0
5061 * 0x00000000: Clear depth to 0.0
5063 static void radv_initialize_htile(struct radv_cmd_buffer
*cmd_buffer
,
5064 struct radv_image
*image
,
5065 const VkImageSubresourceRange
*range
,
5066 uint32_t clear_word
)
5068 assert(range
->baseMipLevel
== 0);
5069 assert(range
->levelCount
== 1 || range
->levelCount
== VK_REMAINING_ARRAY_LAYERS
);
5070 VkImageAspectFlags aspects
= VK_IMAGE_ASPECT_DEPTH_BIT
;
5071 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
5072 VkClearDepthStencilValue value
= {};
5074 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
5075 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
5077 state
->flush_bits
|= radv_clear_htile(cmd_buffer
, image
, range
, clear_word
);
5079 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
5081 if (vk_format_is_stencil(image
->vk_format
))
5082 aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
5084 radv_set_ds_clear_metadata(cmd_buffer
, image
, value
, aspects
);
5086 if (radv_image_is_tc_compat_htile(image
)) {
5087 /* Initialize the TC-compat metada value to 0 because by
5088 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
5089 * need have to conditionally update its value when performing
5090 * a fast depth clear.
5092 radv_set_tc_compat_zrange_metadata(cmd_buffer
, image
, range
, 0);
5096 static void radv_handle_depth_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
5097 struct radv_image
*image
,
5098 VkImageLayout src_layout
,
5099 bool src_render_loop
,
5100 VkImageLayout dst_layout
,
5101 bool dst_render_loop
,
5102 unsigned src_queue_mask
,
5103 unsigned dst_queue_mask
,
5104 const VkImageSubresourceRange
*range
,
5105 struct radv_sample_locations_state
*sample_locs
)
5107 if (!radv_image_has_htile(image
))
5110 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
5111 uint32_t clear_value
= vk_format_is_stencil(image
->vk_format
) ? 0xfffff30f : 0xfffc000f;
5113 if (radv_layout_is_htile_compressed(image
, dst_layout
, dst_render_loop
,
5118 radv_initialize_htile(cmd_buffer
, image
, range
, clear_value
);
5119 } else if (!radv_layout_is_htile_compressed(image
, src_layout
, src_render_loop
, src_queue_mask
) &&
5120 radv_layout_is_htile_compressed(image
, dst_layout
, dst_render_loop
, dst_queue_mask
)) {
5121 uint32_t clear_value
= vk_format_is_stencil(image
->vk_format
) ? 0xfffff30f : 0xfffc000f;
5122 radv_initialize_htile(cmd_buffer
, image
, range
, clear_value
);
5123 } else if (radv_layout_is_htile_compressed(image
, src_layout
, src_render_loop
, src_queue_mask
) &&
5124 !radv_layout_is_htile_compressed(image
, dst_layout
, dst_render_loop
, dst_queue_mask
)) {
5125 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
5126 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
5128 radv_decompress_depth_image_inplace(cmd_buffer
, image
, range
,
5131 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
5132 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
5136 static void radv_initialise_cmask(struct radv_cmd_buffer
*cmd_buffer
,
5137 struct radv_image
*image
,
5138 const VkImageSubresourceRange
*range
,
5141 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
5143 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
5144 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5146 state
->flush_bits
|= radv_clear_cmask(cmd_buffer
, image
, range
, value
);
5148 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5151 void radv_initialize_fmask(struct radv_cmd_buffer
*cmd_buffer
,
5152 struct radv_image
*image
,
5153 const VkImageSubresourceRange
*range
)
5155 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
5156 static const uint32_t fmask_clear_values
[4] = {
5162 uint32_t log2_samples
= util_logbase2(image
->info
.samples
);
5163 uint32_t value
= fmask_clear_values
[log2_samples
];
5165 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
5166 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5168 state
->flush_bits
|= radv_clear_fmask(cmd_buffer
, image
, range
, value
);
5170 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5173 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
5174 struct radv_image
*image
,
5175 const VkImageSubresourceRange
*range
, uint32_t value
)
5177 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
5180 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
5181 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5183 state
->flush_bits
|= radv_clear_dcc(cmd_buffer
, image
, range
, value
);
5185 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX8
) {
5186 /* When DCC is enabled with mipmaps, some levels might not
5187 * support fast clears and we have to initialize them as "fully
5190 /* Compute the size of all fast clearable DCC levels. */
5191 for (unsigned i
= 0; i
< image
->planes
[0].surface
.num_dcc_levels
; i
++) {
5192 struct legacy_surf_level
*surf_level
=
5193 &image
->planes
[0].surface
.u
.legacy
.level
[i
];
5194 unsigned dcc_fast_clear_size
=
5195 surf_level
->dcc_slice_fast_clear_size
* image
->info
.array_size
;
5197 if (!dcc_fast_clear_size
)
5200 size
= surf_level
->dcc_offset
+ dcc_fast_clear_size
;
5203 /* Initialize the mipmap levels without DCC. */
5204 if (size
!= image
->planes
[0].surface
.dcc_size
) {
5205 state
->flush_bits
|=
5206 radv_fill_buffer(cmd_buffer
, image
->bo
,
5207 image
->offset
+ image
->dcc_offset
+ size
,
5208 image
->planes
[0].surface
.dcc_size
- size
,
5213 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
5214 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5218 * Initialize DCC/FMASK/CMASK metadata for a color image.
5220 static void radv_init_color_image_metadata(struct radv_cmd_buffer
*cmd_buffer
,
5221 struct radv_image
*image
,
5222 VkImageLayout src_layout
,
5223 bool src_render_loop
,
5224 VkImageLayout dst_layout
,
5225 bool dst_render_loop
,
5226 unsigned src_queue_mask
,
5227 unsigned dst_queue_mask
,
5228 const VkImageSubresourceRange
*range
)
5230 if (radv_image_has_cmask(image
)) {
5231 uint32_t value
= 0xffffffffu
; /* Fully expanded mode. */
5233 /* TODO: clarify this. */
5234 if (radv_image_has_fmask(image
)) {
5235 value
= 0xccccccccu
;
5238 radv_initialise_cmask(cmd_buffer
, image
, range
, value
);
5241 if (radv_image_has_fmask(image
)) {
5242 radv_initialize_fmask(cmd_buffer
, image
, range
);
5245 if (radv_dcc_enabled(image
, range
->baseMipLevel
)) {
5246 uint32_t value
= 0xffffffffu
; /* Fully expanded mode. */
5247 bool need_decompress_pass
= false;
5249 if (radv_layout_dcc_compressed(cmd_buffer
->device
, image
, dst_layout
,
5252 value
= 0x20202020u
;
5253 need_decompress_pass
= true;
5256 radv_initialize_dcc(cmd_buffer
, image
, range
, value
);
5258 radv_update_fce_metadata(cmd_buffer
, image
, range
,
5259 need_decompress_pass
);
5262 if (radv_image_has_cmask(image
) ||
5263 radv_dcc_enabled(image
, range
->baseMipLevel
)) {
5264 uint32_t color_values
[2] = {};
5265 radv_set_color_clear_metadata(cmd_buffer
, image
, range
,
5271 * Handle color image transitions for DCC/FMASK/CMASK.
5273 static void radv_handle_color_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
5274 struct radv_image
*image
,
5275 VkImageLayout src_layout
,
5276 bool src_render_loop
,
5277 VkImageLayout dst_layout
,
5278 bool dst_render_loop
,
5279 unsigned src_queue_mask
,
5280 unsigned dst_queue_mask
,
5281 const VkImageSubresourceRange
*range
)
5283 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
5284 radv_init_color_image_metadata(cmd_buffer
, image
,
5285 src_layout
, src_render_loop
,
5286 dst_layout
, dst_render_loop
,
5287 src_queue_mask
, dst_queue_mask
,
5292 if (radv_dcc_enabled(image
, range
->baseMipLevel
)) {
5293 if (src_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
5294 radv_initialize_dcc(cmd_buffer
, image
, range
, 0xffffffffu
);
5295 } else if (radv_layout_dcc_compressed(cmd_buffer
->device
, image
, src_layout
, src_render_loop
, src_queue_mask
) &&
5296 !radv_layout_dcc_compressed(cmd_buffer
->device
, image
, dst_layout
, dst_render_loop
, dst_queue_mask
)) {
5297 radv_decompress_dcc(cmd_buffer
, image
, range
);
5298 } else if (radv_layout_can_fast_clear(image
, src_layout
, src_render_loop
, src_queue_mask
) &&
5299 !radv_layout_can_fast_clear(image
, dst_layout
, dst_render_loop
, dst_queue_mask
)) {
5300 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
5302 } else if (radv_image_has_cmask(image
) || radv_image_has_fmask(image
)) {
5303 bool fce_eliminate
= false, fmask_expand
= false;
5305 if (radv_layout_can_fast_clear(image
, src_layout
, src_render_loop
, src_queue_mask
) &&
5306 !radv_layout_can_fast_clear(image
, dst_layout
, dst_render_loop
, dst_queue_mask
)) {
5307 fce_eliminate
= true;
5310 if (radv_image_has_fmask(image
)) {
5311 if (src_layout
!= VK_IMAGE_LAYOUT_GENERAL
&&
5312 dst_layout
== VK_IMAGE_LAYOUT_GENERAL
) {
5313 /* A FMASK decompress is required before doing
5314 * a MSAA decompress using FMASK.
5316 fmask_expand
= true;
5320 if (fce_eliminate
|| fmask_expand
)
5321 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
5324 radv_expand_fmask_image_inplace(cmd_buffer
, image
, range
);
5328 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
5329 struct radv_image
*image
,
5330 VkImageLayout src_layout
,
5331 bool src_render_loop
,
5332 VkImageLayout dst_layout
,
5333 bool dst_render_loop
,
5334 uint32_t src_family
,
5335 uint32_t dst_family
,
5336 const VkImageSubresourceRange
*range
,
5337 struct radv_sample_locations_state
*sample_locs
)
5339 if (image
->exclusive
&& src_family
!= dst_family
) {
5340 /* This is an acquire or a release operation and there will be
5341 * a corresponding release/acquire. Do the transition in the
5342 * most flexible queue. */
5344 assert(src_family
== cmd_buffer
->queue_family_index
||
5345 dst_family
== cmd_buffer
->queue_family_index
);
5347 if (src_family
== VK_QUEUE_FAMILY_EXTERNAL
||
5348 src_family
== VK_QUEUE_FAMILY_FOREIGN_EXT
)
5351 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_TRANSFER
)
5354 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
5355 (src_family
== RADV_QUEUE_GENERAL
||
5356 dst_family
== RADV_QUEUE_GENERAL
))
5360 if (src_layout
== dst_layout
)
5363 unsigned src_queue_mask
=
5364 radv_image_queue_family_mask(image
, src_family
,
5365 cmd_buffer
->queue_family_index
);
5366 unsigned dst_queue_mask
=
5367 radv_image_queue_family_mask(image
, dst_family
,
5368 cmd_buffer
->queue_family_index
);
5370 if (vk_format_is_depth(image
->vk_format
)) {
5371 radv_handle_depth_image_transition(cmd_buffer
, image
,
5372 src_layout
, src_render_loop
,
5373 dst_layout
, dst_render_loop
,
5374 src_queue_mask
, dst_queue_mask
,
5375 range
, sample_locs
);
5377 radv_handle_color_image_transition(cmd_buffer
, image
,
5378 src_layout
, src_render_loop
,
5379 dst_layout
, dst_render_loop
,
5380 src_queue_mask
, dst_queue_mask
,
5385 struct radv_barrier_info
{
5386 uint32_t eventCount
;
5387 const VkEvent
*pEvents
;
5388 VkPipelineStageFlags srcStageMask
;
5389 VkPipelineStageFlags dstStageMask
;
5393 radv_barrier(struct radv_cmd_buffer
*cmd_buffer
,
5394 uint32_t memoryBarrierCount
,
5395 const VkMemoryBarrier
*pMemoryBarriers
,
5396 uint32_t bufferMemoryBarrierCount
,
5397 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
5398 uint32_t imageMemoryBarrierCount
,
5399 const VkImageMemoryBarrier
*pImageMemoryBarriers
,
5400 const struct radv_barrier_info
*info
)
5402 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5403 enum radv_cmd_flush_bits src_flush_bits
= 0;
5404 enum radv_cmd_flush_bits dst_flush_bits
= 0;
5406 for (unsigned i
= 0; i
< info
->eventCount
; ++i
) {
5407 RADV_FROM_HANDLE(radv_event
, event
, info
->pEvents
[i
]);
5408 uint64_t va
= radv_buffer_get_va(event
->bo
);
5410 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, event
->bo
);
5412 ASSERTED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 7);
5414 radv_cp_wait_mem(cs
, WAIT_REG_MEM_EQUAL
, va
, 1, 0xffffffff);
5415 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
5418 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
5419 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pMemoryBarriers
[i
].srcAccessMask
,
5421 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pMemoryBarriers
[i
].dstAccessMask
,
5425 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
5426 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].srcAccessMask
,
5428 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].dstAccessMask
,
5432 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
5433 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
5435 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].srcAccessMask
,
5437 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].dstAccessMask
,
5441 /* The Vulkan spec 1.1.98 says:
5443 * "An execution dependency with only
5444 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
5445 * will only prevent that stage from executing in subsequently
5446 * submitted commands. As this stage does not perform any actual
5447 * execution, this is not observable - in effect, it does not delay
5448 * processing of subsequent commands. Similarly an execution dependency
5449 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
5450 * will effectively not wait for any prior commands to complete."
5452 if (info
->dstStageMask
!= VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
)
5453 radv_stage_flush(cmd_buffer
, info
->srcStageMask
);
5454 cmd_buffer
->state
.flush_bits
|= src_flush_bits
;
5456 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
5457 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
5459 const struct VkSampleLocationsInfoEXT
*sample_locs_info
=
5460 vk_find_struct_const(pImageMemoryBarriers
[i
].pNext
,
5461 SAMPLE_LOCATIONS_INFO_EXT
);
5462 struct radv_sample_locations_state sample_locations
= {};
5464 if (sample_locs_info
) {
5465 assert(image
->flags
& VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
);
5466 sample_locations
.per_pixel
= sample_locs_info
->sampleLocationsPerPixel
;
5467 sample_locations
.grid_size
= sample_locs_info
->sampleLocationGridSize
;
5468 sample_locations
.count
= sample_locs_info
->sampleLocationsCount
;
5469 typed_memcpy(&sample_locations
.locations
[0],
5470 sample_locs_info
->pSampleLocations
,
5471 sample_locs_info
->sampleLocationsCount
);
5474 radv_handle_image_transition(cmd_buffer
, image
,
5475 pImageMemoryBarriers
[i
].oldLayout
,
5476 false, /* Outside of a renderpass we are never in a renderloop */
5477 pImageMemoryBarriers
[i
].newLayout
,
5478 false, /* Outside of a renderpass we are never in a renderloop */
5479 pImageMemoryBarriers
[i
].srcQueueFamilyIndex
,
5480 pImageMemoryBarriers
[i
].dstQueueFamilyIndex
,
5481 &pImageMemoryBarriers
[i
].subresourceRange
,
5482 sample_locs_info
? &sample_locations
: NULL
);
5485 /* Make sure CP DMA is idle because the driver might have performed a
5486 * DMA operation for copying or filling buffers/images.
5488 if (info
->srcStageMask
& (VK_PIPELINE_STAGE_TRANSFER_BIT
|
5489 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
))
5490 si_cp_dma_wait_for_idle(cmd_buffer
);
5492 cmd_buffer
->state
.flush_bits
|= dst_flush_bits
;
5495 void radv_CmdPipelineBarrier(
5496 VkCommandBuffer commandBuffer
,
5497 VkPipelineStageFlags srcStageMask
,
5498 VkPipelineStageFlags destStageMask
,
5500 uint32_t memoryBarrierCount
,
5501 const VkMemoryBarrier
* pMemoryBarriers
,
5502 uint32_t bufferMemoryBarrierCount
,
5503 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
5504 uint32_t imageMemoryBarrierCount
,
5505 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
5507 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5508 struct radv_barrier_info info
;
5510 info
.eventCount
= 0;
5511 info
.pEvents
= NULL
;
5512 info
.srcStageMask
= srcStageMask
;
5513 info
.dstStageMask
= destStageMask
;
5515 radv_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
5516 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
5517 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
5521 static void write_event(struct radv_cmd_buffer
*cmd_buffer
,
5522 struct radv_event
*event
,
5523 VkPipelineStageFlags stageMask
,
5526 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5527 uint64_t va
= radv_buffer_get_va(event
->bo
);
5529 si_emit_cache_flush(cmd_buffer
);
5531 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, event
->bo
);
5533 ASSERTED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 21);
5535 /* Flags that only require a top-of-pipe event. */
5536 VkPipelineStageFlags top_of_pipe_flags
=
5537 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
;
5539 /* Flags that only require a post-index-fetch event. */
5540 VkPipelineStageFlags post_index_fetch_flags
=
5542 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
5543 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
;
5545 /* Make sure CP DMA is idle because the driver might have performed a
5546 * DMA operation for copying or filling buffers/images.
5548 if (stageMask
& (VK_PIPELINE_STAGE_TRANSFER_BIT
|
5549 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
))
5550 si_cp_dma_wait_for_idle(cmd_buffer
);
5552 /* TODO: Emit EOS events for syncing PS/CS stages. */
5554 if (!(stageMask
& ~top_of_pipe_flags
)) {
5555 /* Just need to sync the PFP engine. */
5556 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
5557 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
5558 S_370_WR_CONFIRM(1) |
5559 S_370_ENGINE_SEL(V_370_PFP
));
5560 radeon_emit(cs
, va
);
5561 radeon_emit(cs
, va
>> 32);
5562 radeon_emit(cs
, value
);
5563 } else if (!(stageMask
& ~post_index_fetch_flags
)) {
5564 /* Sync ME because PFP reads index and indirect buffers. */
5565 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
5566 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
5567 S_370_WR_CONFIRM(1) |
5568 S_370_ENGINE_SEL(V_370_ME
));
5569 radeon_emit(cs
, va
);
5570 radeon_emit(cs
, va
>> 32);
5571 radeon_emit(cs
, value
);
5573 /* Otherwise, sync all prior GPU work using an EOP event. */
5574 si_cs_emit_write_event_eop(cs
,
5575 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
5576 radv_cmd_buffer_uses_mec(cmd_buffer
),
5577 V_028A90_BOTTOM_OF_PIPE_TS
, 0,
5579 EOP_DATA_SEL_VALUE_32BIT
, va
, value
,
5580 cmd_buffer
->gfx9_eop_bug_va
);
5583 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
5586 void radv_CmdSetEvent(VkCommandBuffer commandBuffer
,
5588 VkPipelineStageFlags stageMask
)
5590 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5591 RADV_FROM_HANDLE(radv_event
, event
, _event
);
5593 write_event(cmd_buffer
, event
, stageMask
, 1);
5596 void radv_CmdResetEvent(VkCommandBuffer commandBuffer
,
5598 VkPipelineStageFlags stageMask
)
5600 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5601 RADV_FROM_HANDLE(radv_event
, event
, _event
);
5603 write_event(cmd_buffer
, event
, stageMask
, 0);
5606 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer
,
5607 uint32_t eventCount
,
5608 const VkEvent
* pEvents
,
5609 VkPipelineStageFlags srcStageMask
,
5610 VkPipelineStageFlags dstStageMask
,
5611 uint32_t memoryBarrierCount
,
5612 const VkMemoryBarrier
* pMemoryBarriers
,
5613 uint32_t bufferMemoryBarrierCount
,
5614 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
5615 uint32_t imageMemoryBarrierCount
,
5616 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
5618 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5619 struct radv_barrier_info info
;
5621 info
.eventCount
= eventCount
;
5622 info
.pEvents
= pEvents
;
5623 info
.srcStageMask
= 0;
5625 radv_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
5626 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
5627 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
5631 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer
,
5632 uint32_t deviceMask
)
5637 /* VK_EXT_conditional_rendering */
5638 void radv_CmdBeginConditionalRenderingEXT(
5639 VkCommandBuffer commandBuffer
,
5640 const VkConditionalRenderingBeginInfoEXT
* pConditionalRenderingBegin
)
5642 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5643 RADV_FROM_HANDLE(radv_buffer
, buffer
, pConditionalRenderingBegin
->buffer
);
5644 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5645 bool draw_visible
= true;
5646 uint64_t pred_value
= 0;
5647 uint64_t va
, new_va
;
5648 unsigned pred_offset
;
5650 va
= radv_buffer_get_va(buffer
->bo
) + pConditionalRenderingBegin
->offset
;
5652 /* By default, if the 32-bit value at offset in buffer memory is zero,
5653 * then the rendering commands are discarded, otherwise they are
5654 * executed as normal. If the inverted flag is set, all commands are
5655 * discarded if the value is non zero.
5657 if (pConditionalRenderingBegin
->flags
&
5658 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT
) {
5659 draw_visible
= false;
5662 si_emit_cache_flush(cmd_buffer
);
5664 /* From the Vulkan spec 1.1.107:
5666 * "If the 32-bit value at offset in buffer memory is zero, then the
5667 * rendering commands are discarded, otherwise they are executed as
5668 * normal. If the value of the predicate in buffer memory changes while
5669 * conditional rendering is active, the rendering commands may be
5670 * discarded in an implementation-dependent way. Some implementations
5671 * may latch the value of the predicate upon beginning conditional
5672 * rendering while others may read it before every rendering command."
5674 * But, the AMD hardware treats the predicate as a 64-bit value which
5675 * means we need a workaround in the driver. Luckily, it's not required
5676 * to support if the value changes when predication is active.
5678 * The workaround is as follows:
5679 * 1) allocate a 64-value in the upload BO and initialize it to 0
5680 * 2) copy the 32-bit predicate value to the upload BO
5681 * 3) use the new allocated VA address for predication
5683 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
5684 * in ME (+ sync PFP) instead of PFP.
5686 radv_cmd_buffer_upload_data(cmd_buffer
, 8, 16, &pred_value
, &pred_offset
);
5688 new_va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
) + pred_offset
;
5690 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
5691 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
5692 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM
) |
5693 COPY_DATA_WR_CONFIRM
);
5694 radeon_emit(cs
, va
);
5695 radeon_emit(cs
, va
>> 32);
5696 radeon_emit(cs
, new_va
);
5697 radeon_emit(cs
, new_va
>> 32);
5699 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
5702 /* Enable predication for this command buffer. */
5703 si_emit_set_predication_state(cmd_buffer
, draw_visible
, new_va
);
5704 cmd_buffer
->state
.predicating
= true;
5706 /* Store conditional rendering user info. */
5707 cmd_buffer
->state
.predication_type
= draw_visible
;
5708 cmd_buffer
->state
.predication_va
= new_va
;
5711 void radv_CmdEndConditionalRenderingEXT(
5712 VkCommandBuffer commandBuffer
)
5714 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5716 /* Disable predication for this command buffer. */
5717 si_emit_set_predication_state(cmd_buffer
, false, 0);
5718 cmd_buffer
->state
.predicating
= false;
5720 /* Reset conditional rendering user info. */
5721 cmd_buffer
->state
.predication_type
= -1;
5722 cmd_buffer
->state
.predication_va
= 0;
5725 /* VK_EXT_transform_feedback */
5726 void radv_CmdBindTransformFeedbackBuffersEXT(
5727 VkCommandBuffer commandBuffer
,
5728 uint32_t firstBinding
,
5729 uint32_t bindingCount
,
5730 const VkBuffer
* pBuffers
,
5731 const VkDeviceSize
* pOffsets
,
5732 const VkDeviceSize
* pSizes
)
5734 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5735 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
5736 uint8_t enabled_mask
= 0;
5738 assert(firstBinding
+ bindingCount
<= MAX_SO_BUFFERS
);
5739 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
5740 uint32_t idx
= firstBinding
+ i
;
5742 sb
[idx
].buffer
= radv_buffer_from_handle(pBuffers
[i
]);
5743 sb
[idx
].offset
= pOffsets
[i
];
5744 sb
[idx
].size
= pSizes
[i
];
5746 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
5747 sb
[idx
].buffer
->bo
);
5749 enabled_mask
|= 1 << idx
;
5752 cmd_buffer
->state
.streamout
.enabled_mask
|= enabled_mask
;
5754 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_STREAMOUT_BUFFER
;
5758 radv_emit_streamout_enable(struct radv_cmd_buffer
*cmd_buffer
)
5760 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
5761 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5763 radeon_set_context_reg_seq(cs
, R_028B94_VGT_STRMOUT_CONFIG
, 2);
5765 S_028B94_STREAMOUT_0_EN(so
->streamout_enabled
) |
5766 S_028B94_RAST_STREAM(0) |
5767 S_028B94_STREAMOUT_1_EN(so
->streamout_enabled
) |
5768 S_028B94_STREAMOUT_2_EN(so
->streamout_enabled
) |
5769 S_028B94_STREAMOUT_3_EN(so
->streamout_enabled
));
5770 radeon_emit(cs
, so
->hw_enabled_mask
&
5771 so
->enabled_stream_buffers_mask
);
5773 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
5777 radv_set_streamout_enable(struct radv_cmd_buffer
*cmd_buffer
, bool enable
)
5779 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
5780 bool old_streamout_enabled
= so
->streamout_enabled
;
5781 uint32_t old_hw_enabled_mask
= so
->hw_enabled_mask
;
5783 so
->streamout_enabled
= enable
;
5785 so
->hw_enabled_mask
= so
->enabled_mask
|
5786 (so
->enabled_mask
<< 4) |
5787 (so
->enabled_mask
<< 8) |
5788 (so
->enabled_mask
<< 12);
5790 if ((old_streamout_enabled
!= so
->streamout_enabled
) ||
5791 (old_hw_enabled_mask
!= so
->hw_enabled_mask
))
5792 radv_emit_streamout_enable(cmd_buffer
);
5795 static void radv_flush_vgt_streamout(struct radv_cmd_buffer
*cmd_buffer
)
5797 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5798 unsigned reg_strmout_cntl
;
5800 /* The register is at different places on different ASICs. */
5801 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
5802 reg_strmout_cntl
= R_0300FC_CP_STRMOUT_CNTL
;
5803 radeon_set_uconfig_reg(cs
, reg_strmout_cntl
, 0);
5805 reg_strmout_cntl
= R_0084FC_CP_STRMOUT_CNTL
;
5806 radeon_set_config_reg(cs
, reg_strmout_cntl
, 0);
5809 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
5810 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH
) | EVENT_INDEX(0));
5812 radeon_emit(cs
, PKT3(PKT3_WAIT_REG_MEM
, 5, 0));
5813 radeon_emit(cs
, WAIT_REG_MEM_EQUAL
); /* wait until the register is equal to the reference value */
5814 radeon_emit(cs
, reg_strmout_cntl
>> 2); /* register */
5816 radeon_emit(cs
, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
5817 radeon_emit(cs
, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
5818 radeon_emit(cs
, 4); /* poll interval */
5822 radv_emit_streamout_begin(struct radv_cmd_buffer
*cmd_buffer
,
5823 uint32_t firstCounterBuffer
,
5824 uint32_t counterBufferCount
,
5825 const VkBuffer
*pCounterBuffers
,
5826 const VkDeviceSize
*pCounterBufferOffsets
)
5829 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
5830 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
5831 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5834 radv_flush_vgt_streamout(cmd_buffer
);
5836 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
5837 for_each_bit(i
, so
->enabled_mask
) {
5838 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
5839 if (counter_buffer_idx
>= 0 && counter_buffer_idx
>= counterBufferCount
)
5840 counter_buffer_idx
= -1;
5842 /* AMD GCN binds streamout buffers as shader resources.
5843 * VGT only counts primitives and tells the shader through
5846 radeon_set_context_reg_seq(cs
, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0
+ 16*i
, 2);
5847 radeon_emit(cs
, sb
[i
].size
>> 2); /* BUFFER_SIZE (in DW) */
5848 radeon_emit(cs
, so
->stride_in_dw
[i
]); /* VTX_STRIDE (in DW) */
5850 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
5852 if (counter_buffer_idx
>= 0 && pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
]) {
5853 /* The array of counter buffers is optional. */
5854 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
5855 uint64_t va
= radv_buffer_get_va(buffer
->bo
);
5857 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
5860 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
5861 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
5862 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5863 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM
)); /* control */
5864 radeon_emit(cs
, 0); /* unused */
5865 radeon_emit(cs
, 0); /* unused */
5866 radeon_emit(cs
, va
); /* src address lo */
5867 radeon_emit(cs
, va
>> 32); /* src address hi */
5869 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, buffer
->bo
);
5871 /* Start from the beginning. */
5872 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
5873 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
5874 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5875 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET
)); /* control */
5876 radeon_emit(cs
, 0); /* unused */
5877 radeon_emit(cs
, 0); /* unused */
5878 radeon_emit(cs
, 0); /* unused */
5879 radeon_emit(cs
, 0); /* unused */
5883 radv_set_streamout_enable(cmd_buffer
, true);
5886 void radv_CmdBeginTransformFeedbackEXT(
5887 VkCommandBuffer commandBuffer
,
5888 uint32_t firstCounterBuffer
,
5889 uint32_t counterBufferCount
,
5890 const VkBuffer
* pCounterBuffers
,
5891 const VkDeviceSize
* pCounterBufferOffsets
)
5893 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5895 radv_emit_streamout_begin(cmd_buffer
,
5896 firstCounterBuffer
, counterBufferCount
,
5897 pCounterBuffers
, pCounterBufferOffsets
);
5901 radv_emit_streamout_end(struct radv_cmd_buffer
*cmd_buffer
,
5902 uint32_t firstCounterBuffer
,
5903 uint32_t counterBufferCount
,
5904 const VkBuffer
*pCounterBuffers
,
5905 const VkDeviceSize
*pCounterBufferOffsets
)
5907 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
5908 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5911 radv_flush_vgt_streamout(cmd_buffer
);
5913 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
5914 for_each_bit(i
, so
->enabled_mask
) {
5915 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
5916 if (counter_buffer_idx
>= 0 && counter_buffer_idx
>= counterBufferCount
)
5917 counter_buffer_idx
= -1;
5919 if (counter_buffer_idx
>= 0 && pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
]) {
5920 /* The array of counters buffer is optional. */
5921 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
5922 uint64_t va
= radv_buffer_get_va(buffer
->bo
);
5924 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
5926 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
5927 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
5928 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5929 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE
) |
5930 STRMOUT_STORE_BUFFER_FILLED_SIZE
); /* control */
5931 radeon_emit(cs
, va
); /* dst address lo */
5932 radeon_emit(cs
, va
>> 32); /* dst address hi */
5933 radeon_emit(cs
, 0); /* unused */
5934 radeon_emit(cs
, 0); /* unused */
5936 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, buffer
->bo
);
5939 /* Deactivate transform feedback by zeroing the buffer size.
5940 * The counters (primitives generated, primitives emitted) may
5941 * be enabled even if there is not buffer bound. This ensures
5942 * that the primitives-emitted query won't increment.
5944 radeon_set_context_reg(cs
, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0
+ 16*i
, 0);
5946 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
5949 radv_set_streamout_enable(cmd_buffer
, false);
5952 void radv_CmdEndTransformFeedbackEXT(
5953 VkCommandBuffer commandBuffer
,
5954 uint32_t firstCounterBuffer
,
5955 uint32_t counterBufferCount
,
5956 const VkBuffer
* pCounterBuffers
,
5957 const VkDeviceSize
* pCounterBufferOffsets
)
5959 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5961 radv_emit_streamout_end(cmd_buffer
,
5962 firstCounterBuffer
, counterBufferCount
,
5963 pCounterBuffers
, pCounterBufferOffsets
);
5966 void radv_CmdDrawIndirectByteCountEXT(
5967 VkCommandBuffer commandBuffer
,
5968 uint32_t instanceCount
,
5969 uint32_t firstInstance
,
5970 VkBuffer _counterBuffer
,
5971 VkDeviceSize counterBufferOffset
,
5972 uint32_t counterOffset
,
5973 uint32_t vertexStride
)
5975 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5976 RADV_FROM_HANDLE(radv_buffer
, counterBuffer
, _counterBuffer
);
5977 struct radv_draw_info info
= {};
5979 info
.instance_count
= instanceCount
;
5980 info
.first_instance
= firstInstance
;
5981 info
.strmout_buffer
= counterBuffer
;
5982 info
.strmout_buffer_offset
= counterBufferOffset
;
5983 info
.stride
= vertexStride
;
5985 radv_draw(cmd_buffer
, &info
);
5988 /* VK_AMD_buffer_marker */
5989 void radv_CmdWriteBufferMarkerAMD(
5990 VkCommandBuffer commandBuffer
,
5991 VkPipelineStageFlagBits pipelineStage
,
5993 VkDeviceSize dstOffset
,
5996 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5997 RADV_FROM_HANDLE(radv_buffer
, buffer
, dstBuffer
);
5998 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5999 uint64_t va
= radv_buffer_get_va(buffer
->bo
) + dstOffset
;
6001 si_emit_cache_flush(cmd_buffer
);
6003 if (!(pipelineStage
& ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
)) {
6004 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
6005 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_IMM
) |
6006 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM
) |
6007 COPY_DATA_WR_CONFIRM
);
6008 radeon_emit(cs
, marker
);
6010 radeon_emit(cs
, va
);
6011 radeon_emit(cs
, va
>> 32);
6013 si_cs_emit_write_event_eop(cs
,
6014 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
6015 radv_cmd_buffer_uses_mec(cmd_buffer
),
6016 V_028A90_BOTTOM_OF_PIPE_TS
, 0,
6018 EOP_DATA_SEL_VALUE_32BIT
,
6020 cmd_buffer
->gfx9_eop_bug_va
);