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radv/gfx10: enable wave32 for compute based on shader's wavesize
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 bool src_render_loop,
58 VkImageLayout dst_layout,
59 bool dst_render_loop,
60 uint32_t src_family,
61 uint32_t dst_family,
62 const VkImageSubresourceRange *range,
63 struct radv_sample_locations_state *sample_locs);
64
65 const struct radv_dynamic_state default_dynamic_state = {
66 .viewport = {
67 .count = 0,
68 },
69 .scissor = {
70 .count = 0,
71 },
72 .line_width = 1.0f,
73 .depth_bias = {
74 .bias = 0.0f,
75 .clamp = 0.0f,
76 .slope = 0.0f,
77 },
78 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
79 .depth_bounds = {
80 .min = 0.0f,
81 .max = 1.0f,
82 },
83 .stencil_compare_mask = {
84 .front = ~0u,
85 .back = ~0u,
86 },
87 .stencil_write_mask = {
88 .front = ~0u,
89 .back = ~0u,
90 },
91 .stencil_reference = {
92 .front = 0u,
93 .back = 0u,
94 },
95 };
96
97 static void
98 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
99 const struct radv_dynamic_state *src)
100 {
101 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
102 uint32_t copy_mask = src->mask;
103 uint32_t dest_mask = 0;
104
105 /* Make sure to copy the number of viewports/scissors because they can
106 * only be specified at pipeline creation time.
107 */
108 dest->viewport.count = src->viewport.count;
109 dest->scissor.count = src->scissor.count;
110 dest->discard_rectangle.count = src->discard_rectangle.count;
111 dest->sample_location.count = src->sample_location.count;
112
113 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
114 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
115 src->viewport.count * sizeof(VkViewport))) {
116 typed_memcpy(dest->viewport.viewports,
117 src->viewport.viewports,
118 src->viewport.count);
119 dest_mask |= RADV_DYNAMIC_VIEWPORT;
120 }
121 }
122
123 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
124 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
125 src->scissor.count * sizeof(VkRect2D))) {
126 typed_memcpy(dest->scissor.scissors,
127 src->scissor.scissors, src->scissor.count);
128 dest_mask |= RADV_DYNAMIC_SCISSOR;
129 }
130 }
131
132 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
133 if (dest->line_width != src->line_width) {
134 dest->line_width = src->line_width;
135 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
136 }
137 }
138
139 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
140 if (memcmp(&dest->depth_bias, &src->depth_bias,
141 sizeof(src->depth_bias))) {
142 dest->depth_bias = src->depth_bias;
143 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
144 }
145 }
146
147 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
148 if (memcmp(&dest->blend_constants, &src->blend_constants,
149 sizeof(src->blend_constants))) {
150 typed_memcpy(dest->blend_constants,
151 src->blend_constants, 4);
152 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
153 }
154 }
155
156 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
157 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
158 sizeof(src->depth_bounds))) {
159 dest->depth_bounds = src->depth_bounds;
160 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
161 }
162 }
163
164 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
165 if (memcmp(&dest->stencil_compare_mask,
166 &src->stencil_compare_mask,
167 sizeof(src->stencil_compare_mask))) {
168 dest->stencil_compare_mask = src->stencil_compare_mask;
169 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
170 }
171 }
172
173 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
174 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
175 sizeof(src->stencil_write_mask))) {
176 dest->stencil_write_mask = src->stencil_write_mask;
177 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
178 }
179 }
180
181 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
182 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
183 sizeof(src->stencil_reference))) {
184 dest->stencil_reference = src->stencil_reference;
185 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
186 }
187 }
188
189 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
190 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
191 src->discard_rectangle.count * sizeof(VkRect2D))) {
192 typed_memcpy(dest->discard_rectangle.rectangles,
193 src->discard_rectangle.rectangles,
194 src->discard_rectangle.count);
195 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
196 }
197 }
198
199 if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
200 if (dest->sample_location.per_pixel != src->sample_location.per_pixel ||
201 dest->sample_location.grid_size.width != src->sample_location.grid_size.width ||
202 dest->sample_location.grid_size.height != src->sample_location.grid_size.height ||
203 memcmp(&dest->sample_location.locations,
204 &src->sample_location.locations,
205 src->sample_location.count * sizeof(VkSampleLocationEXT))) {
206 dest->sample_location.per_pixel = src->sample_location.per_pixel;
207 dest->sample_location.grid_size = src->sample_location.grid_size;
208 typed_memcpy(dest->sample_location.locations,
209 src->sample_location.locations,
210 src->sample_location.count);
211 dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
212 }
213 }
214
215 cmd_buffer->state.dirty |= dest_mask;
216 }
217
218 static void
219 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
220 struct radv_pipeline *pipeline)
221 {
222 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
223 struct radv_shader_info *info;
224
225 if (!pipeline->streamout_shader ||
226 cmd_buffer->device->physical_device->use_ngg_streamout)
227 return;
228
229 info = &pipeline->streamout_shader->info;
230 for (int i = 0; i < MAX_SO_BUFFERS; i++)
231 so->stride_in_dw[i] = info->so.strides[i];
232
233 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
234 }
235
236 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
237 {
238 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
239 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
240 }
241
242 enum ring_type radv_queue_family_to_ring(int f) {
243 switch (f) {
244 case RADV_QUEUE_GENERAL:
245 return RING_GFX;
246 case RADV_QUEUE_COMPUTE:
247 return RING_COMPUTE;
248 case RADV_QUEUE_TRANSFER:
249 return RING_DMA;
250 default:
251 unreachable("Unknown queue family");
252 }
253 }
254
255 static VkResult radv_create_cmd_buffer(
256 struct radv_device * device,
257 struct radv_cmd_pool * pool,
258 VkCommandBufferLevel level,
259 VkCommandBuffer* pCommandBuffer)
260 {
261 struct radv_cmd_buffer *cmd_buffer;
262 unsigned ring;
263 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
264 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
265 if (cmd_buffer == NULL)
266 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
267
268 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
269 cmd_buffer->device = device;
270 cmd_buffer->pool = pool;
271 cmd_buffer->level = level;
272
273 if (pool) {
274 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
275 cmd_buffer->queue_family_index = pool->queue_family_index;
276
277 } else {
278 /* Init the pool_link so we can safely call list_del when we destroy
279 * the command buffer
280 */
281 list_inithead(&cmd_buffer->pool_link);
282 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
283 }
284
285 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
286
287 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
288 if (!cmd_buffer->cs) {
289 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
290 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
291 }
292
293 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
294
295 list_inithead(&cmd_buffer->upload.list);
296
297 return VK_SUCCESS;
298 }
299
300 static void
301 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
302 {
303 list_del(&cmd_buffer->pool_link);
304
305 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
306 &cmd_buffer->upload.list, list) {
307 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
308 list_del(&up->list);
309 free(up);
310 }
311
312 if (cmd_buffer->upload.upload_bo)
313 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
314 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
315
316 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
317 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
318
319 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
320 }
321
322 static VkResult
323 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
324 {
325 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
326
327 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
328 &cmd_buffer->upload.list, list) {
329 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
330 list_del(&up->list);
331 free(up);
332 }
333
334 cmd_buffer->push_constant_stages = 0;
335 cmd_buffer->scratch_size_needed = 0;
336 cmd_buffer->compute_scratch_size_needed = 0;
337 cmd_buffer->esgs_ring_size_needed = 0;
338 cmd_buffer->gsvs_ring_size_needed = 0;
339 cmd_buffer->tess_rings_needed = false;
340 cmd_buffer->gds_needed = false;
341 cmd_buffer->sample_positions_needed = false;
342
343 if (cmd_buffer->upload.upload_bo)
344 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
345 cmd_buffer->upload.upload_bo);
346 cmd_buffer->upload.offset = 0;
347
348 cmd_buffer->record_result = VK_SUCCESS;
349
350 memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
351
352 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
353 cmd_buffer->descriptors[i].dirty = 0;
354 cmd_buffer->descriptors[i].valid = 0;
355 cmd_buffer->descriptors[i].push_dirty = false;
356 }
357
358 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
359 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
360 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
361 unsigned fence_offset, eop_bug_offset;
362 void *fence_ptr;
363
364 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
365 &fence_ptr);
366
367 cmd_buffer->gfx9_fence_va =
368 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
369 cmd_buffer->gfx9_fence_va += fence_offset;
370
371 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
372 /* Allocate a buffer for the EOP bug on GFX9. */
373 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
374 &eop_bug_offset, &fence_ptr);
375 cmd_buffer->gfx9_eop_bug_va =
376 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
377 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
378 }
379 }
380
381 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
382
383 return cmd_buffer->record_result;
384 }
385
386 static bool
387 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
388 uint64_t min_needed)
389 {
390 uint64_t new_size;
391 struct radeon_winsys_bo *bo;
392 struct radv_cmd_buffer_upload *upload;
393 struct radv_device *device = cmd_buffer->device;
394
395 new_size = MAX2(min_needed, 16 * 1024);
396 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
397
398 bo = device->ws->buffer_create(device->ws,
399 new_size, 4096,
400 RADEON_DOMAIN_GTT,
401 RADEON_FLAG_CPU_ACCESS|
402 RADEON_FLAG_NO_INTERPROCESS_SHARING |
403 RADEON_FLAG_32BIT,
404 RADV_BO_PRIORITY_UPLOAD_BUFFER);
405
406 if (!bo) {
407 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
408 return false;
409 }
410
411 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
412 if (cmd_buffer->upload.upload_bo) {
413 upload = malloc(sizeof(*upload));
414
415 if (!upload) {
416 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
417 device->ws->buffer_destroy(bo);
418 return false;
419 }
420
421 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
422 list_add(&upload->list, &cmd_buffer->upload.list);
423 }
424
425 cmd_buffer->upload.upload_bo = bo;
426 cmd_buffer->upload.size = new_size;
427 cmd_buffer->upload.offset = 0;
428 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
429
430 if (!cmd_buffer->upload.map) {
431 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
432 return false;
433 }
434
435 return true;
436 }
437
438 bool
439 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
440 unsigned size,
441 unsigned alignment,
442 unsigned *out_offset,
443 void **ptr)
444 {
445 assert(util_is_power_of_two_nonzero(alignment));
446
447 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
448 if (offset + size > cmd_buffer->upload.size) {
449 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
450 return false;
451 offset = 0;
452 }
453
454 *out_offset = offset;
455 *ptr = cmd_buffer->upload.map + offset;
456
457 cmd_buffer->upload.offset = offset + size;
458 return true;
459 }
460
461 bool
462 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
463 unsigned size, unsigned alignment,
464 const void *data, unsigned *out_offset)
465 {
466 uint8_t *ptr;
467
468 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
469 out_offset, (void **)&ptr))
470 return false;
471
472 if (ptr)
473 memcpy(ptr, data, size);
474
475 return true;
476 }
477
478 static void
479 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
480 unsigned count, const uint32_t *data)
481 {
482 struct radeon_cmdbuf *cs = cmd_buffer->cs;
483
484 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
485
486 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
487 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
488 S_370_WR_CONFIRM(1) |
489 S_370_ENGINE_SEL(V_370_ME));
490 radeon_emit(cs, va);
491 radeon_emit(cs, va >> 32);
492 radeon_emit_array(cs, data, count);
493 }
494
495 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
496 {
497 struct radv_device *device = cmd_buffer->device;
498 struct radeon_cmdbuf *cs = cmd_buffer->cs;
499 uint64_t va;
500
501 va = radv_buffer_get_va(device->trace_bo);
502 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
503 va += 4;
504
505 ++cmd_buffer->state.trace_id;
506 radv_emit_write_data_packet(cmd_buffer, va, 1,
507 &cmd_buffer->state.trace_id);
508
509 radeon_check_space(cmd_buffer->device->ws, cs, 2);
510
511 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
512 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
513 }
514
515 static void
516 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
517 enum radv_cmd_flush_bits flags)
518 {
519 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
520 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
521 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
522
523 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
524
525 /* Force wait for graphics or compute engines to be idle. */
526 si_cs_emit_cache_flush(cmd_buffer->cs,
527 cmd_buffer->device->physical_device->rad_info.chip_class,
528 &cmd_buffer->gfx9_fence_idx,
529 cmd_buffer->gfx9_fence_va,
530 radv_cmd_buffer_uses_mec(cmd_buffer),
531 flags, cmd_buffer->gfx9_eop_bug_va);
532 }
533
534 if (unlikely(cmd_buffer->device->trace_bo))
535 radv_cmd_buffer_trace_emit(cmd_buffer);
536 }
537
538 static void
539 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
540 struct radv_pipeline *pipeline, enum ring_type ring)
541 {
542 struct radv_device *device = cmd_buffer->device;
543 uint32_t data[2];
544 uint64_t va;
545
546 va = radv_buffer_get_va(device->trace_bo);
547
548 switch (ring) {
549 case RING_GFX:
550 va += 8;
551 break;
552 case RING_COMPUTE:
553 va += 16;
554 break;
555 default:
556 assert(!"invalid ring type");
557 }
558
559 uint64_t pipeline_address = (uintptr_t)pipeline;
560 data[0] = pipeline_address;
561 data[1] = pipeline_address >> 32;
562
563 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
564 }
565
566 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
567 VkPipelineBindPoint bind_point,
568 struct radv_descriptor_set *set,
569 unsigned idx)
570 {
571 struct radv_descriptor_state *descriptors_state =
572 radv_get_descriptors_state(cmd_buffer, bind_point);
573
574 descriptors_state->sets[idx] = set;
575
576 descriptors_state->valid |= (1u << idx); /* active descriptors */
577 descriptors_state->dirty |= (1u << idx);
578 }
579
580 static void
581 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
582 VkPipelineBindPoint bind_point)
583 {
584 struct radv_descriptor_state *descriptors_state =
585 radv_get_descriptors_state(cmd_buffer, bind_point);
586 struct radv_device *device = cmd_buffer->device;
587 uint32_t data[MAX_SETS * 2] = {};
588 uint64_t va;
589 unsigned i;
590 va = radv_buffer_get_va(device->trace_bo) + 24;
591
592 for_each_bit(i, descriptors_state->valid) {
593 struct radv_descriptor_set *set = descriptors_state->sets[i];
594 data[i * 2] = (uint64_t)(uintptr_t)set;
595 data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
596 }
597
598 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
599 }
600
601 struct radv_userdata_info *
602 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
603 gl_shader_stage stage,
604 int idx)
605 {
606 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
607 return &shader->info.user_sgprs_locs.shader_data[idx];
608 }
609
610 static void
611 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
612 struct radv_pipeline *pipeline,
613 gl_shader_stage stage,
614 int idx, uint64_t va)
615 {
616 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
617 uint32_t base_reg = pipeline->user_data_0[stage];
618 if (loc->sgpr_idx == -1)
619 return;
620
621 assert(loc->num_sgprs == 1);
622
623 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
624 base_reg + loc->sgpr_idx * 4, va, false);
625 }
626
627 static void
628 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
629 struct radv_pipeline *pipeline,
630 struct radv_descriptor_state *descriptors_state,
631 gl_shader_stage stage)
632 {
633 struct radv_device *device = cmd_buffer->device;
634 struct radeon_cmdbuf *cs = cmd_buffer->cs;
635 uint32_t sh_base = pipeline->user_data_0[stage];
636 struct radv_userdata_locations *locs =
637 &pipeline->shaders[stage]->info.user_sgprs_locs;
638 unsigned mask = locs->descriptor_sets_enabled;
639
640 mask &= descriptors_state->dirty & descriptors_state->valid;
641
642 while (mask) {
643 int start, count;
644
645 u_bit_scan_consecutive_range(&mask, &start, &count);
646
647 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
648 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
649
650 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
651 for (int i = 0; i < count; i++) {
652 struct radv_descriptor_set *set =
653 descriptors_state->sets[start + i];
654
655 radv_emit_shader_pointer_body(device, cs, set->va, true);
656 }
657 }
658 }
659
660 /**
661 * Convert the user sample locations to hardware sample locations (the values
662 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
663 */
664 static void
665 radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
666 uint32_t x, uint32_t y, VkOffset2D *sample_locs)
667 {
668 uint32_t x_offset = x % state->grid_size.width;
669 uint32_t y_offset = y % state->grid_size.height;
670 uint32_t num_samples = (uint32_t)state->per_pixel;
671 VkSampleLocationEXT *user_locs;
672 uint32_t pixel_offset;
673
674 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
675
676 assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
677 user_locs = &state->locations[pixel_offset];
678
679 for (uint32_t i = 0; i < num_samples; i++) {
680 float shifted_pos_x = user_locs[i].x - 0.5;
681 float shifted_pos_y = user_locs[i].y - 0.5;
682
683 int32_t scaled_pos_x = floor(shifted_pos_x * 16);
684 int32_t scaled_pos_y = floor(shifted_pos_y * 16);
685
686 sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
687 sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
688 }
689 }
690
691 /**
692 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
693 * locations.
694 */
695 static void
696 radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
697 uint32_t *sample_locs_pixel)
698 {
699 for (uint32_t i = 0; i < num_samples; i++) {
700 uint32_t sample_reg_idx = i / 4;
701 uint32_t sample_loc_idx = i % 4;
702 int32_t pos_x = sample_locs[i].x;
703 int32_t pos_y = sample_locs[i].y;
704
705 uint32_t shift_x = 8 * sample_loc_idx;
706 uint32_t shift_y = shift_x + 4;
707
708 sample_locs_pixel[sample_reg_idx] |= (pos_x & 0xf) << shift_x;
709 sample_locs_pixel[sample_reg_idx] |= (pos_y & 0xf) << shift_y;
710 }
711 }
712
713 /**
714 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
715 * sample locations.
716 */
717 static uint64_t
718 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer,
719 VkOffset2D *sample_locs,
720 uint32_t num_samples)
721 {
722 uint32_t centroid_priorities[num_samples];
723 uint32_t sample_mask = num_samples - 1;
724 uint32_t distances[num_samples];
725 uint64_t centroid_priority = 0;
726
727 /* Compute the distances from center for each sample. */
728 for (int i = 0; i < num_samples; i++) {
729 distances[i] = (sample_locs[i].x * sample_locs[i].x) +
730 (sample_locs[i].y * sample_locs[i].y);
731 }
732
733 /* Compute the centroid priorities by looking at the distances array. */
734 for (int i = 0; i < num_samples; i++) {
735 uint32_t min_idx = 0;
736
737 for (int j = 1; j < num_samples; j++) {
738 if (distances[j] < distances[min_idx])
739 min_idx = j;
740 }
741
742 centroid_priorities[i] = min_idx;
743 distances[min_idx] = 0xffffffff;
744 }
745
746 /* Compute the final centroid priority. */
747 for (int i = 0; i < 8; i++) {
748 centroid_priority |=
749 centroid_priorities[i & sample_mask] << (i * 4);
750 }
751
752 return centroid_priority << 32 | centroid_priority;
753 }
754
755 /**
756 * Emit the sample locations that are specified with VK_EXT_sample_locations.
757 */
758 static void
759 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
760 {
761 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
762 struct radv_multisample_state *ms = &pipeline->graphics.ms;
763 struct radv_sample_locations_state *sample_location =
764 &cmd_buffer->state.dynamic.sample_location;
765 uint32_t num_samples = (uint32_t)sample_location->per_pixel;
766 struct radeon_cmdbuf *cs = cmd_buffer->cs;
767 uint32_t sample_locs_pixel[4][2] = {};
768 VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
769 uint32_t max_sample_dist = 0;
770 uint64_t centroid_priority;
771
772 if (!cmd_buffer->state.dynamic.sample_location.count)
773 return;
774
775 /* Convert the user sample locations to hardware sample locations. */
776 radv_convert_user_sample_locs(sample_location, 0, 0, sample_locs[0]);
777 radv_convert_user_sample_locs(sample_location, 1, 0, sample_locs[1]);
778 radv_convert_user_sample_locs(sample_location, 0, 1, sample_locs[2]);
779 radv_convert_user_sample_locs(sample_location, 1, 1, sample_locs[3]);
780
781 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
782 for (uint32_t i = 0; i < 4; i++) {
783 radv_compute_sample_locs_pixel(num_samples, sample_locs[i],
784 sample_locs_pixel[i]);
785 }
786
787 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
788 centroid_priority =
789 radv_compute_centroid_priority(cmd_buffer, sample_locs[0],
790 num_samples);
791
792 /* Compute the maximum sample distance from the specified locations. */
793 for (uint32_t i = 0; i < num_samples; i++) {
794 VkOffset2D offset = sample_locs[0][i];
795 max_sample_dist = MAX2(max_sample_dist,
796 MAX2(abs(offset.x), abs(offset.y)));
797 }
798
799 /* Emit the specified user sample locations. */
800 switch (num_samples) {
801 case 2:
802 case 4:
803 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
804 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
805 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
806 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
807 break;
808 case 8:
809 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
810 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
811 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
812 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
813 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs_pixel[0][1]);
814 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs_pixel[1][1]);
815 radeon_set_context_reg(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs_pixel[2][1]);
816 radeon_set_context_reg(cs, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs_pixel[3][1]);
817 break;
818 default:
819 unreachable("invalid number of samples");
820 }
821
822 /* Emit the maximum sample distance and the centroid priority. */
823 uint32_t pa_sc_aa_config = ms->pa_sc_aa_config;
824
825 pa_sc_aa_config &= C_028BE0_MAX_SAMPLE_DIST;
826 pa_sc_aa_config |= S_028BE0_MAX_SAMPLE_DIST(max_sample_dist);
827
828 radeon_set_context_reg_seq(cs, R_028BE0_PA_SC_AA_CONFIG, 1);
829 radeon_emit(cs, pa_sc_aa_config);
830
831 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
832 radeon_emit(cs, centroid_priority);
833 radeon_emit(cs, centroid_priority >> 32);
834
835 /* GFX9: Flush DFSM when the AA mode changes. */
836 if (cmd_buffer->device->dfsm_allowed) {
837 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
838 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
839 }
840
841 cmd_buffer->state.context_roll_without_scissor_emitted = true;
842 }
843
844 static void
845 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
846 struct radv_pipeline *pipeline,
847 gl_shader_stage stage,
848 int idx, int count, uint32_t *values)
849 {
850 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
851 uint32_t base_reg = pipeline->user_data_0[stage];
852 if (loc->sgpr_idx == -1)
853 return;
854
855 assert(loc->num_sgprs == count);
856
857 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
858 radeon_emit_array(cmd_buffer->cs, values, count);
859 }
860
861 static void
862 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
863 struct radv_pipeline *pipeline)
864 {
865 int num_samples = pipeline->graphics.ms.num_samples;
866 struct radv_multisample_state *ms = &pipeline->graphics.ms;
867 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
868
869 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.needs_sample_positions)
870 cmd_buffer->sample_positions_needed = true;
871
872 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
873 return;
874
875 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
876 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
877 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
878
879 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
880
881 radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
882
883 /* GFX9: Flush DFSM when the AA mode changes. */
884 if (cmd_buffer->device->dfsm_allowed) {
885 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
886 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
887 }
888
889 cmd_buffer->state.context_roll_without_scissor_emitted = true;
890 }
891
892 static void
893 radv_update_binning_state(struct radv_cmd_buffer *cmd_buffer,
894 struct radv_pipeline *pipeline)
895 {
896 const struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
897
898
899 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
900 return;
901
902 if (old_pipeline &&
903 old_pipeline->graphics.binning.pa_sc_binner_cntl_0 == pipeline->graphics.binning.pa_sc_binner_cntl_0 &&
904 old_pipeline->graphics.binning.db_dfsm_control == pipeline->graphics.binning.db_dfsm_control)
905 return;
906
907 bool binning_flush = false;
908 if (cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA12 ||
909 cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA20 ||
910 cmd_buffer->device->physical_device->rad_info.family == CHIP_RAVEN2 ||
911 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
912 binning_flush = !old_pipeline ||
913 G_028C44_BINNING_MODE(old_pipeline->graphics.binning.pa_sc_binner_cntl_0) !=
914 G_028C44_BINNING_MODE(pipeline->graphics.binning.pa_sc_binner_cntl_0);
915 }
916
917 radeon_set_context_reg(cmd_buffer->cs, R_028C44_PA_SC_BINNER_CNTL_0,
918 pipeline->graphics.binning.pa_sc_binner_cntl_0 |
919 S_028C44_FLUSH_ON_BINNING_TRANSITION(!!binning_flush));
920
921 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
922 radeon_set_context_reg(cmd_buffer->cs, R_028038_DB_DFSM_CONTROL,
923 pipeline->graphics.binning.db_dfsm_control);
924 } else {
925 radeon_set_context_reg(cmd_buffer->cs, R_028060_DB_DFSM_CONTROL,
926 pipeline->graphics.binning.db_dfsm_control);
927 }
928
929 cmd_buffer->state.context_roll_without_scissor_emitted = true;
930 }
931
932
933 static void
934 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
935 struct radv_shader_variant *shader)
936 {
937 uint64_t va;
938
939 if (!shader)
940 return;
941
942 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
943
944 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
945 }
946
947 static void
948 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
949 struct radv_pipeline *pipeline,
950 bool vertex_stage_only)
951 {
952 struct radv_cmd_state *state = &cmd_buffer->state;
953 uint32_t mask = state->prefetch_L2_mask;
954
955 if (vertex_stage_only) {
956 /* Fast prefetch path for starting draws as soon as possible.
957 */
958 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
959 RADV_PREFETCH_VBO_DESCRIPTORS);
960 }
961
962 if (mask & RADV_PREFETCH_VS)
963 radv_emit_shader_prefetch(cmd_buffer,
964 pipeline->shaders[MESA_SHADER_VERTEX]);
965
966 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
967 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
968
969 if (mask & RADV_PREFETCH_TCS)
970 radv_emit_shader_prefetch(cmd_buffer,
971 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
972
973 if (mask & RADV_PREFETCH_TES)
974 radv_emit_shader_prefetch(cmd_buffer,
975 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
976
977 if (mask & RADV_PREFETCH_GS) {
978 radv_emit_shader_prefetch(cmd_buffer,
979 pipeline->shaders[MESA_SHADER_GEOMETRY]);
980 if (radv_pipeline_has_gs_copy_shader(pipeline))
981 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
982 }
983
984 if (mask & RADV_PREFETCH_PS)
985 radv_emit_shader_prefetch(cmd_buffer,
986 pipeline->shaders[MESA_SHADER_FRAGMENT]);
987
988 state->prefetch_L2_mask &= ~mask;
989 }
990
991 static void
992 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
993 {
994 if (!cmd_buffer->device->physical_device->rad_info.rbplus_allowed)
995 return;
996
997 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
998 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
999
1000 unsigned sx_ps_downconvert = 0;
1001 unsigned sx_blend_opt_epsilon = 0;
1002 unsigned sx_blend_opt_control = 0;
1003
1004 if (!cmd_buffer->state.attachments || !subpass)
1005 return;
1006
1007 for (unsigned i = 0; i < subpass->color_count; ++i) {
1008 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1009 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1010 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1011 continue;
1012 }
1013
1014 int idx = subpass->color_attachments[i].attachment;
1015 struct radv_color_buffer_info *cb = &cmd_buffer->state.attachments[idx].cb;
1016
1017 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
1018 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
1019 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
1020 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
1021
1022 bool has_alpha, has_rgb;
1023
1024 /* Set if RGB and A are present. */
1025 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
1026
1027 if (format == V_028C70_COLOR_8 ||
1028 format == V_028C70_COLOR_16 ||
1029 format == V_028C70_COLOR_32)
1030 has_rgb = !has_alpha;
1031 else
1032 has_rgb = true;
1033
1034 /* Check the colormask and export format. */
1035 if (!(colormask & 0x7))
1036 has_rgb = false;
1037 if (!(colormask & 0x8))
1038 has_alpha = false;
1039
1040 if (spi_format == V_028714_SPI_SHADER_ZERO) {
1041 has_rgb = false;
1042 has_alpha = false;
1043 }
1044
1045 /* Disable value checking for disabled channels. */
1046 if (!has_rgb)
1047 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1048 if (!has_alpha)
1049 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1050
1051 /* Enable down-conversion for 32bpp and smaller formats. */
1052 switch (format) {
1053 case V_028C70_COLOR_8:
1054 case V_028C70_COLOR_8_8:
1055 case V_028C70_COLOR_8_8_8_8:
1056 /* For 1 and 2-channel formats, use the superset thereof. */
1057 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
1058 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1059 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1060 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
1061 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
1062 }
1063 break;
1064
1065 case V_028C70_COLOR_5_6_5:
1066 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1067 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
1068 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
1069 }
1070 break;
1071
1072 case V_028C70_COLOR_1_5_5_5:
1073 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1074 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
1075 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
1076 }
1077 break;
1078
1079 case V_028C70_COLOR_4_4_4_4:
1080 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1081 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
1082 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
1083 }
1084 break;
1085
1086 case V_028C70_COLOR_32:
1087 if (swap == V_028C70_SWAP_STD &&
1088 spi_format == V_028714_SPI_SHADER_32_R)
1089 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1090 else if (swap == V_028C70_SWAP_ALT_REV &&
1091 spi_format == V_028714_SPI_SHADER_32_AR)
1092 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
1093 break;
1094
1095 case V_028C70_COLOR_16:
1096 case V_028C70_COLOR_16_16:
1097 /* For 1-channel formats, use the superset thereof. */
1098 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
1099 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
1100 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1101 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1102 if (swap == V_028C70_SWAP_STD ||
1103 swap == V_028C70_SWAP_STD_REV)
1104 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
1105 else
1106 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
1107 }
1108 break;
1109
1110 case V_028C70_COLOR_10_11_11:
1111 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1112 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
1113 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
1114 }
1115 break;
1116
1117 case V_028C70_COLOR_2_10_10_10:
1118 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1119 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
1120 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
1121 }
1122 break;
1123 }
1124 }
1125
1126 for (unsigned i = subpass->color_count; i < 8; ++i) {
1127 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1128 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1129 }
1130 /* TODO: avoid redundantly setting context registers */
1131 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
1132 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
1133 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
1134 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
1135
1136 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1137 }
1138
1139 static void
1140 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1141 {
1142 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1143
1144 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1145 return;
1146
1147 radv_update_multisample_state(cmd_buffer, pipeline);
1148 radv_update_binning_state(cmd_buffer, pipeline);
1149
1150 cmd_buffer->scratch_size_needed =
1151 MAX2(cmd_buffer->scratch_size_needed,
1152 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1153
1154 if (!cmd_buffer->state.emitted_pipeline ||
1155 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1156 pipeline->graphics.can_use_guardband)
1157 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1158
1159 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
1160
1161 if (!cmd_buffer->state.emitted_pipeline ||
1162 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
1163 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
1164 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
1165 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
1166 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
1167 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1168 }
1169
1170 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
1171 if (!pipeline->shaders[i])
1172 continue;
1173
1174 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1175 pipeline->shaders[i]->bo);
1176 }
1177
1178 if (radv_pipeline_has_gs_copy_shader(pipeline))
1179 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1180 pipeline->gs_copy_shader->bo);
1181
1182 if (unlikely(cmd_buffer->device->trace_bo))
1183 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1184
1185 cmd_buffer->state.emitted_pipeline = pipeline;
1186
1187 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1188 }
1189
1190 static void
1191 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1192 {
1193 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1194 cmd_buffer->state.dynamic.viewport.viewports);
1195 }
1196
1197 static void
1198 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1199 {
1200 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1201
1202 si_write_scissors(cmd_buffer->cs, 0, count,
1203 cmd_buffer->state.dynamic.scissor.scissors,
1204 cmd_buffer->state.dynamic.viewport.viewports,
1205 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1206
1207 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1208 }
1209
1210 static void
1211 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1212 {
1213 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1214 return;
1215
1216 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1217 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1218 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1219 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1220 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1221 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1222 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1223 }
1224 }
1225
1226 static void
1227 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1228 {
1229 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1230
1231 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1232 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1233 }
1234
1235 static void
1236 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1237 {
1238 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1239
1240 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1241 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1242 }
1243
1244 static void
1245 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1246 {
1247 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1248
1249 radeon_set_context_reg_seq(cmd_buffer->cs,
1250 R_028430_DB_STENCILREFMASK, 2);
1251 radeon_emit(cmd_buffer->cs,
1252 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1253 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1254 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1255 S_028430_STENCILOPVAL(1));
1256 radeon_emit(cmd_buffer->cs,
1257 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1258 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1259 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1260 S_028434_STENCILOPVAL_BF(1));
1261 }
1262
1263 static void
1264 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1265 {
1266 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1267
1268 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1269 fui(d->depth_bounds.min));
1270 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1271 fui(d->depth_bounds.max));
1272 }
1273
1274 static void
1275 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1276 {
1277 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1278 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1279 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1280
1281
1282 radeon_set_context_reg_seq(cmd_buffer->cs,
1283 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1284 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1285 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1286 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1287 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1288 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1289 }
1290
1291 static void
1292 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1293 int index,
1294 struct radv_color_buffer_info *cb,
1295 struct radv_image_view *iview,
1296 VkImageLayout layout,
1297 bool in_render_loop)
1298 {
1299 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
1300 uint32_t cb_color_info = cb->cb_color_info;
1301 struct radv_image *image = iview->image;
1302
1303 if (!radv_layout_dcc_compressed(cmd_buffer->device, image, layout, in_render_loop,
1304 radv_image_queue_family_mask(image,
1305 cmd_buffer->queue_family_index,
1306 cmd_buffer->queue_family_index))) {
1307 cb_color_info &= C_028C70_DCC_ENABLE;
1308 }
1309
1310 if (radv_image_is_tc_compat_cmask(image) &&
1311 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1312 radv_is_dcc_decompress_pipeline(cmd_buffer))) {
1313 /* If this bit is set, the FMASK decompression operation
1314 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1315 */
1316 cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
1317 }
1318
1319 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1320 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1321 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1322 radeon_emit(cmd_buffer->cs, 0);
1323 radeon_emit(cmd_buffer->cs, 0);
1324 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1325 radeon_emit(cmd_buffer->cs, cb_color_info);
1326 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1327 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1328 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1329 radeon_emit(cmd_buffer->cs, 0);
1330 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1331 radeon_emit(cmd_buffer->cs, 0);
1332
1333 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 1);
1334 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1335
1336 radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4,
1337 cb->cb_color_base >> 32);
1338 radeon_set_context_reg(cmd_buffer->cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + index * 4,
1339 cb->cb_color_cmask >> 32);
1340 radeon_set_context_reg(cmd_buffer->cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + index * 4,
1341 cb->cb_color_fmask >> 32);
1342 radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4,
1343 cb->cb_dcc_base >> 32);
1344 radeon_set_context_reg(cmd_buffer->cs, R_028EC0_CB_COLOR0_ATTRIB2 + index * 4,
1345 cb->cb_color_attrib2);
1346 radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4,
1347 cb->cb_color_attrib3);
1348 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1349 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1350 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1351 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1352 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1353 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1354 radeon_emit(cmd_buffer->cs, cb_color_info);
1355 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1356 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1357 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1358 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1359 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1360 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1361
1362 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1363 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1364 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1365
1366 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1367 cb->cb_mrt_epitch);
1368 } else {
1369 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1370 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1371 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1372 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1373 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1374 radeon_emit(cmd_buffer->cs, cb_color_info);
1375 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1376 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1377 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1378 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1379 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1380 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1381
1382 if (is_vi) { /* DCC BASE */
1383 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1384 }
1385 }
1386
1387 if (radv_dcc_enabled(image, iview->base_mip)) {
1388 /* Drawing with DCC enabled also compresses colorbuffers. */
1389 VkImageSubresourceRange range = {
1390 .aspectMask = iview->aspect_mask,
1391 .baseMipLevel = iview->base_mip,
1392 .levelCount = iview->level_count,
1393 .baseArrayLayer = iview->base_layer,
1394 .layerCount = iview->layer_count,
1395 };
1396
1397 radv_update_dcc_metadata(cmd_buffer, image, &range, true);
1398 }
1399 }
1400
1401 static void
1402 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1403 struct radv_ds_buffer_info *ds,
1404 const struct radv_image_view *iview,
1405 VkImageLayout layout,
1406 bool in_render_loop, bool requires_cond_exec)
1407 {
1408 const struct radv_image *image = iview->image;
1409 uint32_t db_z_info = ds->db_z_info;
1410 uint32_t db_z_info_reg;
1411
1412 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug ||
1413 !radv_image_is_tc_compat_htile(image))
1414 return;
1415
1416 if (!radv_layout_has_htile(image, layout, in_render_loop,
1417 radv_image_queue_family_mask(image,
1418 cmd_buffer->queue_family_index,
1419 cmd_buffer->queue_family_index))) {
1420 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1421 }
1422
1423 db_z_info &= C_028040_ZRANGE_PRECISION;
1424
1425 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1426 db_z_info_reg = R_028038_DB_Z_INFO;
1427 } else {
1428 db_z_info_reg = R_028040_DB_Z_INFO;
1429 }
1430
1431 /* When we don't know the last fast clear value we need to emit a
1432 * conditional packet that will eventually skip the following
1433 * SET_CONTEXT_REG packet.
1434 */
1435 if (requires_cond_exec) {
1436 uint64_t va = radv_get_tc_compat_zrange_va(image, iview->base_mip);
1437
1438 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1439 radeon_emit(cmd_buffer->cs, va);
1440 radeon_emit(cmd_buffer->cs, va >> 32);
1441 radeon_emit(cmd_buffer->cs, 0);
1442 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1443 }
1444
1445 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1446 }
1447
1448 static void
1449 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1450 struct radv_ds_buffer_info *ds,
1451 struct radv_image_view *iview,
1452 VkImageLayout layout,
1453 bool in_render_loop)
1454 {
1455 const struct radv_image *image = iview->image;
1456 uint32_t db_z_info = ds->db_z_info;
1457 uint32_t db_stencil_info = ds->db_stencil_info;
1458
1459 if (!radv_layout_has_htile(image, layout, in_render_loop,
1460 radv_image_queue_family_mask(image,
1461 cmd_buffer->queue_family_index,
1462 cmd_buffer->queue_family_index))) {
1463 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1464 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1465 }
1466
1467 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1468 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1469
1470 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1471 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1472 radeon_set_context_reg(cmd_buffer->cs, R_02801C_DB_DEPTH_SIZE_XY, ds->db_depth_size);
1473
1474 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 7);
1475 radeon_emit(cmd_buffer->cs, S_02803C_RESOURCE_LEVEL(1));
1476 radeon_emit(cmd_buffer->cs, db_z_info);
1477 radeon_emit(cmd_buffer->cs, db_stencil_info);
1478 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1479 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1480 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1481 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1482
1483 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_READ_BASE_HI, 5);
1484 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1485 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1486 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1487 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1488 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1489 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1490 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1491 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1492 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1493 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1494
1495 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1496 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1497 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1498 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1499 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1500 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1501 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1502 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1503 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1504 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1505 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1506
1507 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1508 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1509 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1510 } else {
1511 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1512
1513 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1514 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1515 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1516 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1517 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1518 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1519 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1520 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1521 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1522 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1523
1524 }
1525
1526 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1527 radv_update_zrange_precision(cmd_buffer, ds, iview, layout,
1528 in_render_loop, true);
1529
1530 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1531 ds->pa_su_poly_offset_db_fmt_cntl);
1532 }
1533
1534 /**
1535 * Update the fast clear depth/stencil values if the image is bound as a
1536 * depth/stencil buffer.
1537 */
1538 static void
1539 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1540 const struct radv_image_view *iview,
1541 VkClearDepthStencilValue ds_clear_value,
1542 VkImageAspectFlags aspects)
1543 {
1544 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1545 const struct radv_image *image = iview->image;
1546 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1547 uint32_t att_idx;
1548
1549 if (!cmd_buffer->state.attachments || !subpass)
1550 return;
1551
1552 if (!subpass->depth_stencil_attachment)
1553 return;
1554
1555 att_idx = subpass->depth_stencil_attachment->attachment;
1556 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1557 return;
1558
1559 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1560 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1561 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1562 radeon_emit(cs, ds_clear_value.stencil);
1563 radeon_emit(cs, fui(ds_clear_value.depth));
1564 } else if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1565 radeon_set_context_reg_seq(cs, R_02802C_DB_DEPTH_CLEAR, 1);
1566 radeon_emit(cs, fui(ds_clear_value.depth));
1567 } else {
1568 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1569 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 1);
1570 radeon_emit(cs, ds_clear_value.stencil);
1571 }
1572
1573 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1574 * only needed when clearing Z to 0.0.
1575 */
1576 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1577 ds_clear_value.depth == 0.0) {
1578 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1579 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
1580
1581 radv_update_zrange_precision(cmd_buffer, &cmd_buffer->state.attachments[att_idx].ds,
1582 iview, layout, in_render_loop, false);
1583 }
1584
1585 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1586 }
1587
1588 /**
1589 * Set the clear depth/stencil values to the image's metadata.
1590 */
1591 static void
1592 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1593 struct radv_image *image,
1594 const VkImageSubresourceRange *range,
1595 VkClearDepthStencilValue ds_clear_value,
1596 VkImageAspectFlags aspects)
1597 {
1598 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1599 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel);
1600 uint32_t level_count = radv_get_levelCount(image, range);
1601
1602 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1603 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1604 /* Use the fastest way when both aspects are used. */
1605 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + 2 * level_count, cmd_buffer->state.predicating));
1606 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1607 S_370_WR_CONFIRM(1) |
1608 S_370_ENGINE_SEL(V_370_PFP));
1609 radeon_emit(cs, va);
1610 radeon_emit(cs, va >> 32);
1611
1612 for (uint32_t l = 0; l < level_count; l++) {
1613 radeon_emit(cs, ds_clear_value.stencil);
1614 radeon_emit(cs, fui(ds_clear_value.depth));
1615 }
1616 } else {
1617 /* Otherwise we need one WRITE_DATA packet per level. */
1618 for (uint32_t l = 0; l < level_count; l++) {
1619 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel + l);
1620 unsigned value;
1621
1622 if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1623 value = fui(ds_clear_value.depth);
1624 va += 4;
1625 } else {
1626 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1627 value = ds_clear_value.stencil;
1628 }
1629
1630 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1631 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1632 S_370_WR_CONFIRM(1) |
1633 S_370_ENGINE_SEL(V_370_PFP));
1634 radeon_emit(cs, va);
1635 radeon_emit(cs, va >> 32);
1636 radeon_emit(cs, value);
1637 }
1638 }
1639 }
1640
1641 /**
1642 * Update the TC-compat metadata value for this image.
1643 */
1644 static void
1645 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1646 struct radv_image *image,
1647 const VkImageSubresourceRange *range,
1648 uint32_t value)
1649 {
1650 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1651
1652 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug)
1653 return;
1654
1655 uint64_t va = radv_get_tc_compat_zrange_va(image, range->baseMipLevel);
1656 uint32_t level_count = radv_get_levelCount(image, range);
1657
1658 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + level_count, cmd_buffer->state.predicating));
1659 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1660 S_370_WR_CONFIRM(1) |
1661 S_370_ENGINE_SEL(V_370_PFP));
1662 radeon_emit(cs, va);
1663 radeon_emit(cs, va >> 32);
1664
1665 for (uint32_t l = 0; l < level_count; l++)
1666 radeon_emit(cs, value);
1667 }
1668
1669 static void
1670 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1671 const struct radv_image_view *iview,
1672 VkClearDepthStencilValue ds_clear_value)
1673 {
1674 VkImageSubresourceRange range = {
1675 .aspectMask = iview->aspect_mask,
1676 .baseMipLevel = iview->base_mip,
1677 .levelCount = iview->level_count,
1678 .baseArrayLayer = iview->base_layer,
1679 .layerCount = iview->layer_count,
1680 };
1681 uint32_t cond_val;
1682
1683 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1684 * depth clear value is 0.0f.
1685 */
1686 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1687
1688 radv_set_tc_compat_zrange_metadata(cmd_buffer, iview->image, &range,
1689 cond_val);
1690 }
1691
1692 /**
1693 * Update the clear depth/stencil values for this image.
1694 */
1695 void
1696 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1697 const struct radv_image_view *iview,
1698 VkClearDepthStencilValue ds_clear_value,
1699 VkImageAspectFlags aspects)
1700 {
1701 VkImageSubresourceRange range = {
1702 .aspectMask = iview->aspect_mask,
1703 .baseMipLevel = iview->base_mip,
1704 .levelCount = iview->level_count,
1705 .baseArrayLayer = iview->base_layer,
1706 .layerCount = iview->layer_count,
1707 };
1708 struct radv_image *image = iview->image;
1709
1710 assert(radv_image_has_htile(image));
1711
1712 radv_set_ds_clear_metadata(cmd_buffer, iview->image, &range,
1713 ds_clear_value, aspects);
1714
1715 if (radv_image_is_tc_compat_htile(image) &&
1716 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1717 radv_update_tc_compat_zrange_metadata(cmd_buffer, iview,
1718 ds_clear_value);
1719 }
1720
1721 radv_update_bound_fast_clear_ds(cmd_buffer, iview, ds_clear_value,
1722 aspects);
1723 }
1724
1725 /**
1726 * Load the clear depth/stencil values from the image's metadata.
1727 */
1728 static void
1729 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1730 const struct radv_image_view *iview)
1731 {
1732 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1733 const struct radv_image *image = iview->image;
1734 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1735 uint64_t va = radv_get_ds_clear_value_va(image, iview->base_mip);
1736 unsigned reg_offset = 0, reg_count = 0;
1737
1738 if (!radv_image_has_htile(image))
1739 return;
1740
1741 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1742 ++reg_count;
1743 } else {
1744 ++reg_offset;
1745 va += 4;
1746 }
1747 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1748 ++reg_count;
1749
1750 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1751
1752 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
1753 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1754 radeon_emit(cs, va);
1755 radeon_emit(cs, va >> 32);
1756 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1757 radeon_emit(cs, reg_count);
1758 } else {
1759 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1760 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1761 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1762 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1763 radeon_emit(cs, va);
1764 radeon_emit(cs, va >> 32);
1765 radeon_emit(cs, reg >> 2);
1766 radeon_emit(cs, 0);
1767
1768 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1769 radeon_emit(cs, 0);
1770 }
1771 }
1772
1773 /*
1774 * With DCC some colors don't require CMASK elimination before being
1775 * used as a texture. This sets a predicate value to determine if the
1776 * cmask eliminate is required.
1777 */
1778 void
1779 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1780 struct radv_image *image,
1781 const VkImageSubresourceRange *range, bool value)
1782 {
1783 uint64_t pred_val = value;
1784 uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
1785 uint32_t level_count = radv_get_levelCount(image, range);
1786 uint32_t count = 2 * level_count;
1787
1788 assert(radv_dcc_enabled(image, range->baseMipLevel));
1789
1790 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1791 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1792 S_370_WR_CONFIRM(1) |
1793 S_370_ENGINE_SEL(V_370_PFP));
1794 radeon_emit(cmd_buffer->cs, va);
1795 radeon_emit(cmd_buffer->cs, va >> 32);
1796
1797 for (uint32_t l = 0; l < level_count; l++) {
1798 radeon_emit(cmd_buffer->cs, pred_val);
1799 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1800 }
1801 }
1802
1803 /**
1804 * Update the DCC predicate to reflect the compression state.
1805 */
1806 void
1807 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1808 struct radv_image *image,
1809 const VkImageSubresourceRange *range, bool value)
1810 {
1811 uint64_t pred_val = value;
1812 uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
1813 uint32_t level_count = radv_get_levelCount(image, range);
1814 uint32_t count = 2 * level_count;
1815
1816 assert(radv_dcc_enabled(image, range->baseMipLevel));
1817
1818 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1819 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1820 S_370_WR_CONFIRM(1) |
1821 S_370_ENGINE_SEL(V_370_PFP));
1822 radeon_emit(cmd_buffer->cs, va);
1823 radeon_emit(cmd_buffer->cs, va >> 32);
1824
1825 for (uint32_t l = 0; l < level_count; l++) {
1826 radeon_emit(cmd_buffer->cs, pred_val);
1827 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1828 }
1829 }
1830
1831 /**
1832 * Update the fast clear color values if the image is bound as a color buffer.
1833 */
1834 static void
1835 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1836 struct radv_image *image,
1837 int cb_idx,
1838 uint32_t color_values[2])
1839 {
1840 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1841 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1842 uint32_t att_idx;
1843
1844 if (!cmd_buffer->state.attachments || !subpass)
1845 return;
1846
1847 att_idx = subpass->color_attachments[cb_idx].attachment;
1848 if (att_idx == VK_ATTACHMENT_UNUSED)
1849 return;
1850
1851 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1852 return;
1853
1854 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1855 radeon_emit(cs, color_values[0]);
1856 radeon_emit(cs, color_values[1]);
1857
1858 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1859 }
1860
1861 /**
1862 * Set the clear color values to the image's metadata.
1863 */
1864 static void
1865 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1866 struct radv_image *image,
1867 const VkImageSubresourceRange *range,
1868 uint32_t color_values[2])
1869 {
1870 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1871 uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
1872 uint32_t level_count = radv_get_levelCount(image, range);
1873 uint32_t count = 2 * level_count;
1874
1875 assert(radv_image_has_cmask(image) ||
1876 radv_dcc_enabled(image, range->baseMipLevel));
1877
1878 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
1879 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1880 S_370_WR_CONFIRM(1) |
1881 S_370_ENGINE_SEL(V_370_PFP));
1882 radeon_emit(cs, va);
1883 radeon_emit(cs, va >> 32);
1884
1885 for (uint32_t l = 0; l < level_count; l++) {
1886 radeon_emit(cs, color_values[0]);
1887 radeon_emit(cs, color_values[1]);
1888 }
1889 }
1890
1891 /**
1892 * Update the clear color values for this image.
1893 */
1894 void
1895 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1896 const struct radv_image_view *iview,
1897 int cb_idx,
1898 uint32_t color_values[2])
1899 {
1900 struct radv_image *image = iview->image;
1901 VkImageSubresourceRange range = {
1902 .aspectMask = iview->aspect_mask,
1903 .baseMipLevel = iview->base_mip,
1904 .levelCount = iview->level_count,
1905 .baseArrayLayer = iview->base_layer,
1906 .layerCount = iview->layer_count,
1907 };
1908
1909 assert(radv_image_has_cmask(image) ||
1910 radv_dcc_enabled(image, iview->base_mip));
1911
1912 radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
1913
1914 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1915 color_values);
1916 }
1917
1918 /**
1919 * Load the clear color values from the image's metadata.
1920 */
1921 static void
1922 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1923 struct radv_image_view *iview,
1924 int cb_idx)
1925 {
1926 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1927 struct radv_image *image = iview->image;
1928 uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
1929
1930 if (!radv_image_has_cmask(image) &&
1931 !radv_dcc_enabled(image, iview->base_mip))
1932 return;
1933
1934 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1935
1936 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
1937 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1938 radeon_emit(cs, va);
1939 radeon_emit(cs, va >> 32);
1940 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1941 radeon_emit(cs, 2);
1942 } else {
1943 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1944 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1945 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1946 COPY_DATA_COUNT_SEL);
1947 radeon_emit(cs, va);
1948 radeon_emit(cs, va >> 32);
1949 radeon_emit(cs, reg >> 2);
1950 radeon_emit(cs, 0);
1951
1952 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1953 radeon_emit(cs, 0);
1954 }
1955 }
1956
1957 static void
1958 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1959 {
1960 int i;
1961 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1962 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1963
1964 /* this may happen for inherited secondary recording */
1965 if (!framebuffer)
1966 return;
1967
1968 for (i = 0; i < 8; ++i) {
1969 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1970 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1971 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1972 continue;
1973 }
1974
1975 int idx = subpass->color_attachments[i].attachment;
1976 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
1977 VkImageLayout layout = subpass->color_attachments[i].layout;
1978 bool in_render_loop = subpass->color_attachments[i].in_render_loop;
1979
1980 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, iview->bo);
1981
1982 assert(iview->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
1983 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
1984 radv_emit_fb_color_state(cmd_buffer, i, &cmd_buffer->state.attachments[idx].cb, iview, layout, in_render_loop);
1985
1986 radv_load_color_clear_metadata(cmd_buffer, iview, i);
1987 }
1988
1989 if (subpass->depth_stencil_attachment) {
1990 int idx = subpass->depth_stencil_attachment->attachment;
1991 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1992 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
1993 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
1994 struct radv_image *image = iview->image;
1995 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, cmd_buffer->state.attachments[idx].iview->bo);
1996 ASSERTED uint32_t queue_mask = radv_image_queue_family_mask(image,
1997 cmd_buffer->queue_family_index,
1998 cmd_buffer->queue_family_index);
1999 /* We currently don't support writing decompressed HTILE */
2000 assert(radv_layout_has_htile(image, layout, in_render_loop, queue_mask) ==
2001 radv_layout_is_htile_compressed(image, layout, in_render_loop, queue_mask));
2002
2003 radv_emit_fb_ds_state(cmd_buffer, &cmd_buffer->state.attachments[idx].ds, iview, layout, in_render_loop);
2004
2005 if (cmd_buffer->state.attachments[idx].ds.offset_scale != cmd_buffer->state.offset_scale) {
2006 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2007 cmd_buffer->state.offset_scale = cmd_buffer->state.attachments[idx].ds.offset_scale;
2008 }
2009 radv_load_ds_clear_metadata(cmd_buffer, iview);
2010 } else {
2011 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9)
2012 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
2013 else
2014 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
2015
2016 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
2017 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
2018 }
2019 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2020 S_028208_BR_X(framebuffer->width) |
2021 S_028208_BR_Y(framebuffer->height));
2022
2023 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
2024 bool disable_constant_encode =
2025 cmd_buffer->device->physical_device->rad_info.has_dcc_constant_encode;
2026 enum chip_class chip_class =
2027 cmd_buffer->device->physical_device->rad_info.chip_class;
2028 uint8_t watermark = chip_class >= GFX10 ? 6 : 4;
2029
2030 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
2031 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class <= GFX9) |
2032 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
2033 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
2034 }
2035
2036 if (cmd_buffer->device->dfsm_allowed) {
2037 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2038 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
2039 }
2040
2041 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
2042 }
2043
2044 static void
2045 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
2046 {
2047 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2048 struct radv_cmd_state *state = &cmd_buffer->state;
2049
2050 if (state->index_type != state->last_index_type) {
2051 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2052 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2053 cs, R_03090C_VGT_INDEX_TYPE,
2054 2, state->index_type);
2055 } else {
2056 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2057 radeon_emit(cs, state->index_type);
2058 }
2059
2060 state->last_index_type = state->index_type;
2061 }
2062
2063 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2064 radeon_emit(cs, state->index_va);
2065 radeon_emit(cs, state->index_va >> 32);
2066
2067 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2068 radeon_emit(cs, state->max_index_count);
2069
2070 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
2071 }
2072
2073 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
2074 {
2075 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
2076 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2077 uint32_t pa_sc_mode_cntl_1 =
2078 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
2079 uint32_t db_count_control;
2080
2081 if(!cmd_buffer->state.active_occlusion_queries) {
2082 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2083 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2084 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2085 has_perfect_queries) {
2086 /* Re-enable out-of-order rasterization if the
2087 * bound pipeline supports it and if it's has
2088 * been disabled before starting any perfect
2089 * occlusion queries.
2090 */
2091 radeon_set_context_reg(cmd_buffer->cs,
2092 R_028A4C_PA_SC_MODE_CNTL_1,
2093 pa_sc_mode_cntl_1);
2094 }
2095 }
2096 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
2097 } else {
2098 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2099 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
2100 bool gfx10_perfect = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10 && has_perfect_queries;
2101
2102 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2103 db_count_control =
2104 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
2105 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
2106 S_028004_SAMPLE_RATE(sample_rate) |
2107 S_028004_ZPASS_ENABLE(1) |
2108 S_028004_SLICE_EVEN_ENABLE(1) |
2109 S_028004_SLICE_ODD_ENABLE(1);
2110
2111 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2112 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2113 has_perfect_queries) {
2114 /* If the bound pipeline has enabled
2115 * out-of-order rasterization, we should
2116 * disable it before starting any perfect
2117 * occlusion queries.
2118 */
2119 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
2120
2121 radeon_set_context_reg(cmd_buffer->cs,
2122 R_028A4C_PA_SC_MODE_CNTL_1,
2123 pa_sc_mode_cntl_1);
2124 }
2125 } else {
2126 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
2127 S_028004_SAMPLE_RATE(sample_rate);
2128 }
2129 }
2130
2131 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
2132
2133 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2134 }
2135
2136 static void
2137 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
2138 {
2139 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
2140
2141 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
2142 radv_emit_viewport(cmd_buffer);
2143
2144 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
2145 !cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
2146 radv_emit_scissor(cmd_buffer);
2147
2148 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
2149 radv_emit_line_width(cmd_buffer);
2150
2151 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
2152 radv_emit_blend_constants(cmd_buffer);
2153
2154 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
2155 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
2156 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
2157 radv_emit_stencil(cmd_buffer);
2158
2159 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
2160 radv_emit_depth_bounds(cmd_buffer);
2161
2162 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
2163 radv_emit_depth_bias(cmd_buffer);
2164
2165 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
2166 radv_emit_discard_rectangle(cmd_buffer);
2167
2168 if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)
2169 radv_emit_sample_locations(cmd_buffer);
2170
2171 cmd_buffer->state.dirty &= ~states;
2172 }
2173
2174 static void
2175 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
2176 VkPipelineBindPoint bind_point)
2177 {
2178 struct radv_descriptor_state *descriptors_state =
2179 radv_get_descriptors_state(cmd_buffer, bind_point);
2180 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
2181 unsigned bo_offset;
2182
2183 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
2184 set->mapped_ptr,
2185 &bo_offset))
2186 return;
2187
2188 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2189 set->va += bo_offset;
2190 }
2191
2192 static void
2193 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
2194 VkPipelineBindPoint bind_point)
2195 {
2196 struct radv_descriptor_state *descriptors_state =
2197 radv_get_descriptors_state(cmd_buffer, bind_point);
2198 uint32_t size = MAX_SETS * 4;
2199 uint32_t offset;
2200 void *ptr;
2201
2202 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
2203 256, &offset, &ptr))
2204 return;
2205
2206 for (unsigned i = 0; i < MAX_SETS; i++) {
2207 uint32_t *uptr = ((uint32_t *)ptr) + i;
2208 uint64_t set_va = 0;
2209 struct radv_descriptor_set *set = descriptors_state->sets[i];
2210 if (descriptors_state->valid & (1u << i))
2211 set_va = set->va;
2212 uptr[0] = set_va & 0xffffffff;
2213 }
2214
2215 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2216 va += offset;
2217
2218 if (cmd_buffer->state.pipeline) {
2219 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
2220 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2221 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2222
2223 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
2224 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
2225 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2226
2227 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
2228 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2229 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2230
2231 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2232 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
2233 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2234
2235 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2236 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
2237 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2238 }
2239
2240 if (cmd_buffer->state.compute_pipeline)
2241 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
2242 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2243 }
2244
2245 static void
2246 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
2247 VkShaderStageFlags stages)
2248 {
2249 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2250 VK_PIPELINE_BIND_POINT_COMPUTE :
2251 VK_PIPELINE_BIND_POINT_GRAPHICS;
2252 struct radv_descriptor_state *descriptors_state =
2253 radv_get_descriptors_state(cmd_buffer, bind_point);
2254 struct radv_cmd_state *state = &cmd_buffer->state;
2255 bool flush_indirect_descriptors;
2256
2257 if (!descriptors_state->dirty)
2258 return;
2259
2260 if (descriptors_state->push_dirty)
2261 radv_flush_push_descriptors(cmd_buffer, bind_point);
2262
2263 flush_indirect_descriptors =
2264 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
2265 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
2266 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
2267 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
2268
2269 if (flush_indirect_descriptors)
2270 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
2271
2272 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2273 cmd_buffer->cs,
2274 MAX_SETS * MESA_SHADER_STAGES * 4);
2275
2276 if (cmd_buffer->state.pipeline) {
2277 radv_foreach_stage(stage, stages) {
2278 if (!cmd_buffer->state.pipeline->shaders[stage])
2279 continue;
2280
2281 radv_emit_descriptor_pointers(cmd_buffer,
2282 cmd_buffer->state.pipeline,
2283 descriptors_state, stage);
2284 }
2285 }
2286
2287 if (cmd_buffer->state.compute_pipeline &&
2288 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
2289 radv_emit_descriptor_pointers(cmd_buffer,
2290 cmd_buffer->state.compute_pipeline,
2291 descriptors_state,
2292 MESA_SHADER_COMPUTE);
2293 }
2294
2295 descriptors_state->dirty = 0;
2296 descriptors_state->push_dirty = false;
2297
2298 assert(cmd_buffer->cs->cdw <= cdw_max);
2299
2300 if (unlikely(cmd_buffer->device->trace_bo))
2301 radv_save_descriptors(cmd_buffer, bind_point);
2302 }
2303
2304 static void
2305 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
2306 VkShaderStageFlags stages)
2307 {
2308 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
2309 ? cmd_buffer->state.compute_pipeline
2310 : cmd_buffer->state.pipeline;
2311 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2312 VK_PIPELINE_BIND_POINT_COMPUTE :
2313 VK_PIPELINE_BIND_POINT_GRAPHICS;
2314 struct radv_descriptor_state *descriptors_state =
2315 radv_get_descriptors_state(cmd_buffer, bind_point);
2316 struct radv_pipeline_layout *layout = pipeline->layout;
2317 struct radv_shader_variant *shader, *prev_shader;
2318 bool need_push_constants = false;
2319 unsigned offset;
2320 void *ptr;
2321 uint64_t va;
2322
2323 stages &= cmd_buffer->push_constant_stages;
2324 if (!stages ||
2325 (!layout->push_constant_size && !layout->dynamic_offset_count))
2326 return;
2327
2328 radv_foreach_stage(stage, stages) {
2329 shader = radv_get_shader(pipeline, stage);
2330 if (!shader)
2331 continue;
2332
2333 need_push_constants |= shader->info.loads_push_constants;
2334 need_push_constants |= shader->info.loads_dynamic_offsets;
2335
2336 uint8_t base = shader->info.base_inline_push_consts;
2337 uint8_t count = shader->info.num_inline_push_consts;
2338
2339 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
2340 AC_UD_INLINE_PUSH_CONSTANTS,
2341 count,
2342 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
2343 }
2344
2345 if (need_push_constants) {
2346 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
2347 16 * layout->dynamic_offset_count,
2348 256, &offset, &ptr))
2349 return;
2350
2351 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
2352 memcpy((char*)ptr + layout->push_constant_size,
2353 descriptors_state->dynamic_buffers,
2354 16 * layout->dynamic_offset_count);
2355
2356 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2357 va += offset;
2358
2359 ASSERTED unsigned cdw_max =
2360 radeon_check_space(cmd_buffer->device->ws,
2361 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
2362
2363 prev_shader = NULL;
2364 radv_foreach_stage(stage, stages) {
2365 shader = radv_get_shader(pipeline, stage);
2366
2367 /* Avoid redundantly emitting the address for merged stages. */
2368 if (shader && shader != prev_shader) {
2369 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
2370 AC_UD_PUSH_CONSTANTS, va);
2371
2372 prev_shader = shader;
2373 }
2374 }
2375 assert(cmd_buffer->cs->cdw <= cdw_max);
2376 }
2377
2378 cmd_buffer->push_constant_stages &= ~stages;
2379 }
2380
2381 static void
2382 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
2383 bool pipeline_is_dirty)
2384 {
2385 if ((pipeline_is_dirty ||
2386 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
2387 cmd_buffer->state.pipeline->num_vertex_bindings &&
2388 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.has_vertex_buffers) {
2389 unsigned vb_offset;
2390 void *vb_ptr;
2391 uint32_t i = 0;
2392 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
2393 uint64_t va;
2394
2395 /* allocate some descriptor state for vertex buffers */
2396 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2397 &vb_offset, &vb_ptr))
2398 return;
2399
2400 for (i = 0; i < count; i++) {
2401 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2402 uint32_t offset;
2403 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2404 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[i];
2405 unsigned num_records;
2406
2407 if (!buffer)
2408 continue;
2409
2410 va = radv_buffer_get_va(buffer->bo);
2411
2412 offset = cmd_buffer->vertex_bindings[i].offset;
2413 va += offset + buffer->offset;
2414
2415 num_records = buffer->size - offset;
2416 if (cmd_buffer->device->physical_device->rad_info.chip_class != GFX8 && stride)
2417 num_records /= stride;
2418
2419 desc[0] = va;
2420 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2421 desc[2] = num_records;
2422 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2423 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2424 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2425 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2426
2427 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2428 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT) |
2429 S_008F0C_OOB_SELECT(1) |
2430 S_008F0C_RESOURCE_LEVEL(1);
2431 } else {
2432 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2433 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2434 }
2435 }
2436
2437 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2438 va += vb_offset;
2439
2440 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2441 AC_UD_VS_VERTEX_BUFFERS, va);
2442
2443 cmd_buffer->state.vb_va = va;
2444 cmd_buffer->state.vb_size = count * 16;
2445 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2446 }
2447 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2448 }
2449
2450 static void
2451 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2452 {
2453 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2454 struct radv_userdata_info *loc;
2455 uint32_t base_reg;
2456
2457 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2458 if (!radv_get_shader(pipeline, stage))
2459 continue;
2460
2461 loc = radv_lookup_user_sgpr(pipeline, stage,
2462 AC_UD_STREAMOUT_BUFFERS);
2463 if (loc->sgpr_idx == -1)
2464 continue;
2465
2466 base_reg = pipeline->user_data_0[stage];
2467
2468 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2469 base_reg + loc->sgpr_idx * 4, va, false);
2470 }
2471
2472 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
2473 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2474 if (loc->sgpr_idx != -1) {
2475 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2476
2477 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2478 base_reg + loc->sgpr_idx * 4, va, false);
2479 }
2480 }
2481 }
2482
2483 static void
2484 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2485 {
2486 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2487 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2488 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2489 unsigned so_offset;
2490 void *so_ptr;
2491 uint64_t va;
2492
2493 /* Allocate some descriptor state for streamout buffers. */
2494 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2495 MAX_SO_BUFFERS * 16, 256,
2496 &so_offset, &so_ptr))
2497 return;
2498
2499 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2500 struct radv_buffer *buffer = sb[i].buffer;
2501 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2502
2503 if (!(so->enabled_mask & (1 << i)))
2504 continue;
2505
2506 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2507
2508 va += sb[i].offset;
2509
2510 /* Set the descriptor.
2511 *
2512 * On GFX8, the format must be non-INVALID, otherwise
2513 * the buffer will be considered not bound and store
2514 * instructions will be no-ops.
2515 */
2516 uint32_t size = 0xffffffff;
2517
2518 /* Compute the correct buffer size for NGG streamout
2519 * because it's used to determine the max emit per
2520 * buffer.
2521 */
2522 if (cmd_buffer->device->physical_device->use_ngg_streamout)
2523 size = buffer->size - sb[i].offset;
2524
2525 desc[0] = va;
2526 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2527 desc[2] = size;
2528 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2529 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2530 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2531 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2532
2533 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2534 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2535 S_008F0C_OOB_SELECT(3) |
2536 S_008F0C_RESOURCE_LEVEL(1);
2537 } else {
2538 desc[3] |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2539 }
2540 }
2541
2542 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2543 va += so_offset;
2544
2545 radv_emit_streamout_buffers(cmd_buffer, va);
2546 }
2547
2548 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2549 }
2550
2551 static void
2552 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2553 {
2554 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2555 radv_flush_streamout_descriptors(cmd_buffer);
2556 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2557 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2558 }
2559
2560 struct radv_draw_info {
2561 /**
2562 * Number of vertices.
2563 */
2564 uint32_t count;
2565
2566 /**
2567 * Index of the first vertex.
2568 */
2569 int32_t vertex_offset;
2570
2571 /**
2572 * First instance id.
2573 */
2574 uint32_t first_instance;
2575
2576 /**
2577 * Number of instances.
2578 */
2579 uint32_t instance_count;
2580
2581 /**
2582 * First index (indexed draws only).
2583 */
2584 uint32_t first_index;
2585
2586 /**
2587 * Whether it's an indexed draw.
2588 */
2589 bool indexed;
2590
2591 /**
2592 * Indirect draw parameters resource.
2593 */
2594 struct radv_buffer *indirect;
2595 uint64_t indirect_offset;
2596 uint32_t stride;
2597
2598 /**
2599 * Draw count parameters resource.
2600 */
2601 struct radv_buffer *count_buffer;
2602 uint64_t count_buffer_offset;
2603
2604 /**
2605 * Stream output parameters resource.
2606 */
2607 struct radv_buffer *strmout_buffer;
2608 uint64_t strmout_buffer_offset;
2609 };
2610
2611 static uint32_t
2612 radv_get_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
2613 {
2614 switch (cmd_buffer->state.index_type) {
2615 case V_028A7C_VGT_INDEX_8:
2616 return 0xffu;
2617 case V_028A7C_VGT_INDEX_16:
2618 return 0xffffu;
2619 case V_028A7C_VGT_INDEX_32:
2620 return 0xffffffffu;
2621 default:
2622 unreachable("invalid index type");
2623 }
2624 }
2625
2626 static void
2627 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
2628 bool instanced_draw, bool indirect_draw,
2629 bool count_from_stream_output,
2630 uint32_t draw_vertex_count)
2631 {
2632 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2633 struct radv_cmd_state *state = &cmd_buffer->state;
2634 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2635 unsigned ia_multi_vgt_param;
2636
2637 ia_multi_vgt_param =
2638 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
2639 indirect_draw,
2640 count_from_stream_output,
2641 draw_vertex_count);
2642
2643 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2644 if (info->chip_class == GFX9) {
2645 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2646 cs,
2647 R_030960_IA_MULTI_VGT_PARAM,
2648 4, ia_multi_vgt_param);
2649 } else if (info->chip_class >= GFX7) {
2650 radeon_set_context_reg_idx(cs,
2651 R_028AA8_IA_MULTI_VGT_PARAM,
2652 1, ia_multi_vgt_param);
2653 } else {
2654 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2655 ia_multi_vgt_param);
2656 }
2657 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2658 }
2659 }
2660
2661 static void
2662 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2663 const struct radv_draw_info *draw_info)
2664 {
2665 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2666 struct radv_cmd_state *state = &cmd_buffer->state;
2667 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2668 int32_t primitive_reset_en;
2669
2670 /* Draw state. */
2671 if (info->chip_class < GFX10) {
2672 si_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2673 draw_info->indirect,
2674 !!draw_info->strmout_buffer,
2675 draw_info->indirect ? 0 : draw_info->count);
2676 }
2677
2678 /* Primitive restart. */
2679 primitive_reset_en =
2680 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2681
2682 if (primitive_reset_en != state->last_primitive_reset_en) {
2683 state->last_primitive_reset_en = primitive_reset_en;
2684 if (info->chip_class >= GFX9) {
2685 radeon_set_uconfig_reg(cs,
2686 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2687 primitive_reset_en);
2688 } else {
2689 radeon_set_context_reg(cs,
2690 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2691 primitive_reset_en);
2692 }
2693 }
2694
2695 if (primitive_reset_en) {
2696 uint32_t primitive_reset_index =
2697 radv_get_primitive_reset_index(cmd_buffer);
2698
2699 if (primitive_reset_index != state->last_primitive_reset_index) {
2700 radeon_set_context_reg(cs,
2701 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2702 primitive_reset_index);
2703 state->last_primitive_reset_index = primitive_reset_index;
2704 }
2705 }
2706
2707 if (draw_info->strmout_buffer) {
2708 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2709
2710 va += draw_info->strmout_buffer->offset +
2711 draw_info->strmout_buffer_offset;
2712
2713 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2714 draw_info->stride);
2715
2716 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2717 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2718 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2719 COPY_DATA_WR_CONFIRM);
2720 radeon_emit(cs, va);
2721 radeon_emit(cs, va >> 32);
2722 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2723 radeon_emit(cs, 0); /* unused */
2724
2725 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2726 }
2727 }
2728
2729 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2730 VkPipelineStageFlags src_stage_mask)
2731 {
2732 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2733 VK_PIPELINE_STAGE_TRANSFER_BIT |
2734 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2735 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2736 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2737 }
2738
2739 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2740 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2741 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2742 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2743 VK_PIPELINE_STAGE_TRANSFER_BIT |
2744 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2745 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2746 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2747 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2748 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2749 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2750 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2751 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2752 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2753 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2754 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2755 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2756 }
2757 }
2758
2759 static enum radv_cmd_flush_bits
2760 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2761 VkAccessFlags src_flags,
2762 struct radv_image *image)
2763 {
2764 bool flush_CB_meta = true, flush_DB_meta = true;
2765 enum radv_cmd_flush_bits flush_bits = 0;
2766 uint32_t b;
2767
2768 if (image) {
2769 if (!radv_image_has_CB_metadata(image))
2770 flush_CB_meta = false;
2771 if (!radv_image_has_htile(image))
2772 flush_DB_meta = false;
2773 }
2774
2775 for_each_bit(b, src_flags) {
2776 switch ((VkAccessFlagBits)(1 << b)) {
2777 case VK_ACCESS_SHADER_WRITE_BIT:
2778 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2779 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2780 flush_bits |= RADV_CMD_FLAG_WB_L2;
2781 break;
2782 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2783 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2784 if (flush_CB_meta)
2785 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2786 break;
2787 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2788 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2789 if (flush_DB_meta)
2790 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2791 break;
2792 case VK_ACCESS_TRANSFER_WRITE_BIT:
2793 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2794 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2795 RADV_CMD_FLAG_INV_L2;
2796
2797 if (flush_CB_meta)
2798 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2799 if (flush_DB_meta)
2800 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2801 break;
2802 default:
2803 break;
2804 }
2805 }
2806 return flush_bits;
2807 }
2808
2809 static enum radv_cmd_flush_bits
2810 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2811 VkAccessFlags dst_flags,
2812 struct radv_image *image)
2813 {
2814 bool flush_CB_meta = true, flush_DB_meta = true;
2815 enum radv_cmd_flush_bits flush_bits = 0;
2816 bool flush_CB = true, flush_DB = true;
2817 bool image_is_coherent = false;
2818 uint32_t b;
2819
2820 if (image) {
2821 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2822 flush_CB = false;
2823 flush_DB = false;
2824 }
2825
2826 if (!radv_image_has_CB_metadata(image))
2827 flush_CB_meta = false;
2828 if (!radv_image_has_htile(image))
2829 flush_DB_meta = false;
2830
2831 /* TODO: implement shader coherent for GFX10 */
2832
2833 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
2834 if (image->info.samples == 1 &&
2835 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2836 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2837 !vk_format_is_stencil(image->vk_format)) {
2838 /* Single-sample color and single-sample depth
2839 * (not stencil) are coherent with shaders on
2840 * GFX9.
2841 */
2842 image_is_coherent = true;
2843 }
2844 }
2845 }
2846
2847 for_each_bit(b, dst_flags) {
2848 switch ((VkAccessFlagBits)(1 << b)) {
2849 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2850 case VK_ACCESS_INDEX_READ_BIT:
2851 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2852 break;
2853 case VK_ACCESS_UNIFORM_READ_BIT:
2854 flush_bits |= RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_SCACHE;
2855 break;
2856 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2857 case VK_ACCESS_TRANSFER_READ_BIT:
2858 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2859 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
2860 RADV_CMD_FLAG_INV_L2;
2861 break;
2862 case VK_ACCESS_SHADER_READ_BIT:
2863 flush_bits |= RADV_CMD_FLAG_INV_VCACHE;
2864 /* Unlike LLVM, ACO uses SMEM for SSBOs and we have to
2865 * invalidate the scalar cache. */
2866 if (cmd_buffer->device->physical_device->use_aco)
2867 flush_bits |= RADV_CMD_FLAG_INV_SCACHE;
2868
2869 if (!image_is_coherent)
2870 flush_bits |= RADV_CMD_FLAG_INV_L2;
2871 break;
2872 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2873 if (flush_CB)
2874 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2875 if (flush_CB_meta)
2876 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2877 break;
2878 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2879 if (flush_DB)
2880 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2881 if (flush_DB_meta)
2882 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2883 break;
2884 default:
2885 break;
2886 }
2887 }
2888 return flush_bits;
2889 }
2890
2891 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2892 const struct radv_subpass_barrier *barrier)
2893 {
2894 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2895 NULL);
2896 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2897 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2898 NULL);
2899 }
2900
2901 uint32_t
2902 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
2903 {
2904 struct radv_cmd_state *state = &cmd_buffer->state;
2905 uint32_t subpass_id = state->subpass - state->pass->subpasses;
2906
2907 /* The id of this subpass shouldn't exceed the number of subpasses in
2908 * this render pass minus 1.
2909 */
2910 assert(subpass_id < state->pass->subpass_count);
2911 return subpass_id;
2912 }
2913
2914 static struct radv_sample_locations_state *
2915 radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer,
2916 uint32_t att_idx,
2917 bool begin_subpass)
2918 {
2919 struct radv_cmd_state *state = &cmd_buffer->state;
2920 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
2921 struct radv_image_view *view = state->attachments[att_idx].iview;
2922
2923 if (view->image->info.samples == 1)
2924 return NULL;
2925
2926 if (state->pass->attachments[att_idx].first_subpass_idx == subpass_id) {
2927 /* Return the initial sample locations if this is the initial
2928 * layout transition of the given subpass attachemnt.
2929 */
2930 if (state->attachments[att_idx].sample_location.count > 0)
2931 return &state->attachments[att_idx].sample_location;
2932 } else {
2933 /* Otherwise return the subpass sample locations if defined. */
2934 if (state->subpass_sample_locs) {
2935 /* Because the driver sets the current subpass before
2936 * initial layout transitions, we should use the sample
2937 * locations from the previous subpass to avoid an
2938 * off-by-one problem. Otherwise, use the sample
2939 * locations for the current subpass for final layout
2940 * transitions.
2941 */
2942 if (begin_subpass)
2943 subpass_id--;
2944
2945 for (uint32_t i = 0; i < state->num_subpass_sample_locs; i++) {
2946 if (state->subpass_sample_locs[i].subpass_idx == subpass_id)
2947 return &state->subpass_sample_locs[i].sample_location;
2948 }
2949 }
2950 }
2951
2952 return NULL;
2953 }
2954
2955 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2956 struct radv_subpass_attachment att,
2957 bool begin_subpass)
2958 {
2959 unsigned idx = att.attachment;
2960 struct radv_image_view *view = cmd_buffer->state.attachments[idx].iview;
2961 struct radv_sample_locations_state *sample_locs;
2962 VkImageSubresourceRange range;
2963 range.aspectMask = 0;
2964 range.baseMipLevel = view->base_mip;
2965 range.levelCount = 1;
2966 range.baseArrayLayer = view->base_layer;
2967 range.layerCount = cmd_buffer->state.framebuffer->layers;
2968
2969 if (cmd_buffer->state.subpass->view_mask) {
2970 /* If the current subpass uses multiview, the driver might have
2971 * performed a fast color/depth clear to the whole image
2972 * (including all layers). To make sure the driver will
2973 * decompress the image correctly (if needed), we have to
2974 * account for the "real" number of layers. If the view mask is
2975 * sparse, this will decompress more layers than needed.
2976 */
2977 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
2978 }
2979
2980 /* Get the subpass sample locations for the given attachment, if NULL
2981 * is returned the driver will use the default HW locations.
2982 */
2983 sample_locs = radv_get_attachment_sample_locations(cmd_buffer, idx,
2984 begin_subpass);
2985
2986 radv_handle_image_transition(cmd_buffer,
2987 view->image,
2988 cmd_buffer->state.attachments[idx].current_layout,
2989 cmd_buffer->state.attachments[idx].current_in_render_loop,
2990 att.layout, att.in_render_loop,
2991 0, 0, &range, sample_locs);
2992
2993 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2994 cmd_buffer->state.attachments[idx].current_in_render_loop = att.in_render_loop;
2995
2996
2997 }
2998
2999 void
3000 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
3001 const struct radv_subpass *subpass)
3002 {
3003 cmd_buffer->state.subpass = subpass;
3004
3005 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
3006 }
3007
3008 static VkResult
3009 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
3010 struct radv_render_pass *pass,
3011 const VkRenderPassBeginInfo *info)
3012 {
3013 const struct VkRenderPassSampleLocationsBeginInfoEXT *sample_locs =
3014 vk_find_struct_const(info->pNext,
3015 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT);
3016 struct radv_cmd_state *state = &cmd_buffer->state;
3017
3018 if (!sample_locs) {
3019 state->subpass_sample_locs = NULL;
3020 return VK_SUCCESS;
3021 }
3022
3023 for (uint32_t i = 0; i < sample_locs->attachmentInitialSampleLocationsCount; i++) {
3024 const VkAttachmentSampleLocationsEXT *att_sample_locs =
3025 &sample_locs->pAttachmentInitialSampleLocations[i];
3026 uint32_t att_idx = att_sample_locs->attachmentIndex;
3027 struct radv_image *image = cmd_buffer->state.attachments[att_idx].iview->image;
3028
3029 assert(vk_format_is_depth_or_stencil(image->vk_format));
3030
3031 /* From the Vulkan spec 1.1.108:
3032 *
3033 * "If the image referenced by the framebuffer attachment at
3034 * index attachmentIndex was not created with
3035 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
3036 * then the values specified in sampleLocationsInfo are
3037 * ignored."
3038 */
3039 if (!(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT))
3040 continue;
3041
3042 const VkSampleLocationsInfoEXT *sample_locs_info =
3043 &att_sample_locs->sampleLocationsInfo;
3044
3045 state->attachments[att_idx].sample_location.per_pixel =
3046 sample_locs_info->sampleLocationsPerPixel;
3047 state->attachments[att_idx].sample_location.grid_size =
3048 sample_locs_info->sampleLocationGridSize;
3049 state->attachments[att_idx].sample_location.count =
3050 sample_locs_info->sampleLocationsCount;
3051 typed_memcpy(&state->attachments[att_idx].sample_location.locations[0],
3052 sample_locs_info->pSampleLocations,
3053 sample_locs_info->sampleLocationsCount);
3054 }
3055
3056 state->subpass_sample_locs = vk_alloc(&cmd_buffer->pool->alloc,
3057 sample_locs->postSubpassSampleLocationsCount *
3058 sizeof(state->subpass_sample_locs[0]),
3059 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3060 if (state->subpass_sample_locs == NULL) {
3061 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3062 return cmd_buffer->record_result;
3063 }
3064
3065 state->num_subpass_sample_locs = sample_locs->postSubpassSampleLocationsCount;
3066
3067 for (uint32_t i = 0; i < sample_locs->postSubpassSampleLocationsCount; i++) {
3068 const VkSubpassSampleLocationsEXT *subpass_sample_locs_info =
3069 &sample_locs->pPostSubpassSampleLocations[i];
3070 const VkSampleLocationsInfoEXT *sample_locs_info =
3071 &subpass_sample_locs_info->sampleLocationsInfo;
3072
3073 state->subpass_sample_locs[i].subpass_idx =
3074 subpass_sample_locs_info->subpassIndex;
3075 state->subpass_sample_locs[i].sample_location.per_pixel =
3076 sample_locs_info->sampleLocationsPerPixel;
3077 state->subpass_sample_locs[i].sample_location.grid_size =
3078 sample_locs_info->sampleLocationGridSize;
3079 state->subpass_sample_locs[i].sample_location.count =
3080 sample_locs_info->sampleLocationsCount;
3081 typed_memcpy(&state->subpass_sample_locs[i].sample_location.locations[0],
3082 sample_locs_info->pSampleLocations,
3083 sample_locs_info->sampleLocationsCount);
3084 }
3085
3086 return VK_SUCCESS;
3087 }
3088
3089 static VkResult
3090 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
3091 struct radv_render_pass *pass,
3092 const VkRenderPassBeginInfo *info)
3093 {
3094 struct radv_cmd_state *state = &cmd_buffer->state;
3095 const struct VkRenderPassAttachmentBeginInfoKHR *attachment_info = NULL;
3096
3097 if (info) {
3098 attachment_info = vk_find_struct_const(info->pNext,
3099 RENDER_PASS_ATTACHMENT_BEGIN_INFO_KHR);
3100 }
3101
3102
3103 if (pass->attachment_count == 0) {
3104 state->attachments = NULL;
3105 return VK_SUCCESS;
3106 }
3107
3108 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
3109 pass->attachment_count *
3110 sizeof(state->attachments[0]),
3111 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3112 if (state->attachments == NULL) {
3113 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3114 return cmd_buffer->record_result;
3115 }
3116
3117 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
3118 struct radv_render_pass_attachment *att = &pass->attachments[i];
3119 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
3120 VkImageAspectFlags clear_aspects = 0;
3121
3122 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
3123 /* color attachment */
3124 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3125 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
3126 }
3127 } else {
3128 /* depthstencil attachment */
3129 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
3130 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3131 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
3132 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3133 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
3134 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3135 }
3136 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3137 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3138 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3139 }
3140 }
3141
3142 state->attachments[i].pending_clear_aspects = clear_aspects;
3143 state->attachments[i].cleared_views = 0;
3144 if (clear_aspects && info) {
3145 assert(info->clearValueCount > i);
3146 state->attachments[i].clear_value = info->pClearValues[i];
3147 }
3148
3149 state->attachments[i].current_layout = att->initial_layout;
3150 state->attachments[i].sample_location.count = 0;
3151
3152 struct radv_image_view *iview;
3153 if (attachment_info && attachment_info->attachmentCount > i) {
3154 iview = radv_image_view_from_handle(attachment_info->pAttachments[i]);
3155 } else {
3156 iview = state->framebuffer->attachments[i];
3157 }
3158
3159 state->attachments[i].iview = iview;
3160 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3161 radv_initialise_ds_surface(cmd_buffer->device, &state->attachments[i].ds, iview);
3162 } else {
3163 radv_initialise_color_surface(cmd_buffer->device, &state->attachments[i].cb, iview);
3164 }
3165 }
3166
3167 return VK_SUCCESS;
3168 }
3169
3170 VkResult radv_AllocateCommandBuffers(
3171 VkDevice _device,
3172 const VkCommandBufferAllocateInfo *pAllocateInfo,
3173 VkCommandBuffer *pCommandBuffers)
3174 {
3175 RADV_FROM_HANDLE(radv_device, device, _device);
3176 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
3177
3178 VkResult result = VK_SUCCESS;
3179 uint32_t i;
3180
3181 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
3182
3183 if (!list_is_empty(&pool->free_cmd_buffers)) {
3184 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
3185
3186 list_del(&cmd_buffer->pool_link);
3187 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
3188
3189 result = radv_reset_cmd_buffer(cmd_buffer);
3190 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
3191 cmd_buffer->level = pAllocateInfo->level;
3192
3193 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
3194 } else {
3195 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
3196 &pCommandBuffers[i]);
3197 }
3198 if (result != VK_SUCCESS)
3199 break;
3200 }
3201
3202 if (result != VK_SUCCESS) {
3203 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
3204 i, pCommandBuffers);
3205
3206 /* From the Vulkan 1.0.66 spec:
3207 *
3208 * "vkAllocateCommandBuffers can be used to create multiple
3209 * command buffers. If the creation of any of those command
3210 * buffers fails, the implementation must destroy all
3211 * successfully created command buffer objects from this
3212 * command, set all entries of the pCommandBuffers array to
3213 * NULL and return the error."
3214 */
3215 memset(pCommandBuffers, 0,
3216 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
3217 }
3218
3219 return result;
3220 }
3221
3222 void radv_FreeCommandBuffers(
3223 VkDevice device,
3224 VkCommandPool commandPool,
3225 uint32_t commandBufferCount,
3226 const VkCommandBuffer *pCommandBuffers)
3227 {
3228 for (uint32_t i = 0; i < commandBufferCount; i++) {
3229 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
3230
3231 if (cmd_buffer) {
3232 if (cmd_buffer->pool) {
3233 list_del(&cmd_buffer->pool_link);
3234 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
3235 } else
3236 radv_cmd_buffer_destroy(cmd_buffer);
3237
3238 }
3239 }
3240 }
3241
3242 VkResult radv_ResetCommandBuffer(
3243 VkCommandBuffer commandBuffer,
3244 VkCommandBufferResetFlags flags)
3245 {
3246 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3247 return radv_reset_cmd_buffer(cmd_buffer);
3248 }
3249
3250 VkResult radv_BeginCommandBuffer(
3251 VkCommandBuffer commandBuffer,
3252 const VkCommandBufferBeginInfo *pBeginInfo)
3253 {
3254 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3255 VkResult result = VK_SUCCESS;
3256
3257 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
3258 /* If the command buffer has already been resetted with
3259 * vkResetCommandBuffer, no need to do it again.
3260 */
3261 result = radv_reset_cmd_buffer(cmd_buffer);
3262 if (result != VK_SUCCESS)
3263 return result;
3264 }
3265
3266 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
3267 cmd_buffer->state.last_primitive_reset_en = -1;
3268 cmd_buffer->state.last_index_type = -1;
3269 cmd_buffer->state.last_num_instances = -1;
3270 cmd_buffer->state.last_vertex_offset = -1;
3271 cmd_buffer->state.last_first_instance = -1;
3272 cmd_buffer->state.predication_type = -1;
3273 cmd_buffer->usage_flags = pBeginInfo->flags;
3274
3275 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
3276 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
3277 assert(pBeginInfo->pInheritanceInfo);
3278 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
3279 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
3280
3281 struct radv_subpass *subpass =
3282 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
3283
3284 if (cmd_buffer->state.framebuffer) {
3285 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
3286 if (result != VK_SUCCESS)
3287 return result;
3288 }
3289
3290 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3291 }
3292
3293 if (unlikely(cmd_buffer->device->trace_bo)) {
3294 struct radv_device *device = cmd_buffer->device;
3295
3296 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
3297 device->trace_bo);
3298
3299 radv_cmd_buffer_trace_emit(cmd_buffer);
3300 }
3301
3302 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
3303
3304 return result;
3305 }
3306
3307 void radv_CmdBindVertexBuffers(
3308 VkCommandBuffer commandBuffer,
3309 uint32_t firstBinding,
3310 uint32_t bindingCount,
3311 const VkBuffer* pBuffers,
3312 const VkDeviceSize* pOffsets)
3313 {
3314 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3315 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
3316 bool changed = false;
3317
3318 /* We have to defer setting up vertex buffer since we need the buffer
3319 * stride from the pipeline. */
3320
3321 assert(firstBinding + bindingCount <= MAX_VBS);
3322 for (uint32_t i = 0; i < bindingCount; i++) {
3323 uint32_t idx = firstBinding + i;
3324
3325 if (!changed &&
3326 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
3327 vb[idx].offset != pOffsets[i])) {
3328 changed = true;
3329 }
3330
3331 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
3332 vb[idx].offset = pOffsets[i];
3333
3334 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3335 vb[idx].buffer->bo);
3336 }
3337
3338 if (!changed) {
3339 /* No state changes. */
3340 return;
3341 }
3342
3343 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
3344 }
3345
3346 static uint32_t
3347 vk_to_index_type(VkIndexType type)
3348 {
3349 switch (type) {
3350 case VK_INDEX_TYPE_UINT8_EXT:
3351 return V_028A7C_VGT_INDEX_8;
3352 case VK_INDEX_TYPE_UINT16:
3353 return V_028A7C_VGT_INDEX_16;
3354 case VK_INDEX_TYPE_UINT32:
3355 return V_028A7C_VGT_INDEX_32;
3356 default:
3357 unreachable("invalid index type");
3358 }
3359 }
3360
3361 static uint32_t
3362 radv_get_vgt_index_size(uint32_t type)
3363 {
3364 switch (type) {
3365 case V_028A7C_VGT_INDEX_8:
3366 return 1;
3367 case V_028A7C_VGT_INDEX_16:
3368 return 2;
3369 case V_028A7C_VGT_INDEX_32:
3370 return 4;
3371 default:
3372 unreachable("invalid index type");
3373 }
3374 }
3375
3376 void radv_CmdBindIndexBuffer(
3377 VkCommandBuffer commandBuffer,
3378 VkBuffer buffer,
3379 VkDeviceSize offset,
3380 VkIndexType indexType)
3381 {
3382 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3383 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
3384
3385 if (cmd_buffer->state.index_buffer == index_buffer &&
3386 cmd_buffer->state.index_offset == offset &&
3387 cmd_buffer->state.index_type == indexType) {
3388 /* No state changes. */
3389 return;
3390 }
3391
3392 cmd_buffer->state.index_buffer = index_buffer;
3393 cmd_buffer->state.index_offset = offset;
3394 cmd_buffer->state.index_type = vk_to_index_type(indexType);
3395 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
3396 cmd_buffer->state.index_va += index_buffer->offset + offset;
3397
3398 int index_size = radv_get_vgt_index_size(vk_to_index_type(indexType));
3399 cmd_buffer->state.max_index_count = (index_buffer->size - offset) / index_size;
3400 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3401 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
3402 }
3403
3404
3405 static void
3406 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3407 VkPipelineBindPoint bind_point,
3408 struct radv_descriptor_set *set, unsigned idx)
3409 {
3410 struct radeon_winsys *ws = cmd_buffer->device->ws;
3411
3412 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
3413
3414 assert(set);
3415 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
3416
3417 if (!cmd_buffer->device->use_global_bo_list) {
3418 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3419 if (set->descriptors[j])
3420 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
3421 }
3422
3423 if(set->bo)
3424 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
3425 }
3426
3427 void radv_CmdBindDescriptorSets(
3428 VkCommandBuffer commandBuffer,
3429 VkPipelineBindPoint pipelineBindPoint,
3430 VkPipelineLayout _layout,
3431 uint32_t firstSet,
3432 uint32_t descriptorSetCount,
3433 const VkDescriptorSet* pDescriptorSets,
3434 uint32_t dynamicOffsetCount,
3435 const uint32_t* pDynamicOffsets)
3436 {
3437 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3438 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3439 unsigned dyn_idx = 0;
3440
3441 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
3442 struct radv_descriptor_state *descriptors_state =
3443 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3444
3445 for (unsigned i = 0; i < descriptorSetCount; ++i) {
3446 unsigned idx = i + firstSet;
3447 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
3448
3449 /* If the set is already bound we only need to update the
3450 * (potentially changed) dynamic offsets. */
3451 if (descriptors_state->sets[idx] != set ||
3452 !(descriptors_state->valid & (1u << idx))) {
3453 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
3454 }
3455
3456 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
3457 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
3458 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
3459 assert(dyn_idx < dynamicOffsetCount);
3460
3461 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
3462 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
3463 dst[0] = va;
3464 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
3465 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
3466 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3467 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3468 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3469 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3470
3471 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
3472 dst[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3473 S_008F0C_OOB_SELECT(3) |
3474 S_008F0C_RESOURCE_LEVEL(1);
3475 } else {
3476 dst[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3477 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3478 }
3479
3480 cmd_buffer->push_constant_stages |=
3481 set->layout->dynamic_shader_stages;
3482 }
3483 }
3484 }
3485
3486 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3487 struct radv_descriptor_set *set,
3488 struct radv_descriptor_set_layout *layout,
3489 VkPipelineBindPoint bind_point)
3490 {
3491 struct radv_descriptor_state *descriptors_state =
3492 radv_get_descriptors_state(cmd_buffer, bind_point);
3493 set->size = layout->size;
3494 set->layout = layout;
3495
3496 if (descriptors_state->push_set.capacity < set->size) {
3497 size_t new_size = MAX2(set->size, 1024);
3498 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
3499 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
3500
3501 free(set->mapped_ptr);
3502 set->mapped_ptr = malloc(new_size);
3503
3504 if (!set->mapped_ptr) {
3505 descriptors_state->push_set.capacity = 0;
3506 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3507 return false;
3508 }
3509
3510 descriptors_state->push_set.capacity = new_size;
3511 }
3512
3513 return true;
3514 }
3515
3516 void radv_meta_push_descriptor_set(
3517 struct radv_cmd_buffer* cmd_buffer,
3518 VkPipelineBindPoint pipelineBindPoint,
3519 VkPipelineLayout _layout,
3520 uint32_t set,
3521 uint32_t descriptorWriteCount,
3522 const VkWriteDescriptorSet* pDescriptorWrites)
3523 {
3524 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3525 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
3526 unsigned bo_offset;
3527
3528 assert(set == 0);
3529 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3530
3531 push_set->size = layout->set[set].layout->size;
3532 push_set->layout = layout->set[set].layout;
3533
3534 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
3535 &bo_offset,
3536 (void**) &push_set->mapped_ptr))
3537 return;
3538
3539 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
3540 push_set->va += bo_offset;
3541
3542 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3543 radv_descriptor_set_to_handle(push_set),
3544 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3545
3546 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3547 }
3548
3549 void radv_CmdPushDescriptorSetKHR(
3550 VkCommandBuffer commandBuffer,
3551 VkPipelineBindPoint pipelineBindPoint,
3552 VkPipelineLayout _layout,
3553 uint32_t set,
3554 uint32_t descriptorWriteCount,
3555 const VkWriteDescriptorSet* pDescriptorWrites)
3556 {
3557 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3558 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3559 struct radv_descriptor_state *descriptors_state =
3560 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3561 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3562
3563 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3564
3565 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3566 layout->set[set].layout,
3567 pipelineBindPoint))
3568 return;
3569
3570 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3571 * because it is invalid, according to Vulkan spec.
3572 */
3573 for (int i = 0; i < descriptorWriteCount; i++) {
3574 ASSERTED const VkWriteDescriptorSet *writeset = &pDescriptorWrites[i];
3575 assert(writeset->descriptorType != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT);
3576 }
3577
3578 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3579 radv_descriptor_set_to_handle(push_set),
3580 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3581
3582 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3583 descriptors_state->push_dirty = true;
3584 }
3585
3586 void radv_CmdPushDescriptorSetWithTemplateKHR(
3587 VkCommandBuffer commandBuffer,
3588 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
3589 VkPipelineLayout _layout,
3590 uint32_t set,
3591 const void* pData)
3592 {
3593 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3594 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3595 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
3596 struct radv_descriptor_state *descriptors_state =
3597 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
3598 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3599
3600 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3601
3602 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3603 layout->set[set].layout,
3604 templ->bind_point))
3605 return;
3606
3607 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
3608 descriptorUpdateTemplate, pData);
3609
3610 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
3611 descriptors_state->push_dirty = true;
3612 }
3613
3614 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
3615 VkPipelineLayout layout,
3616 VkShaderStageFlags stageFlags,
3617 uint32_t offset,
3618 uint32_t size,
3619 const void* pValues)
3620 {
3621 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3622 memcpy(cmd_buffer->push_constants + offset, pValues, size);
3623 cmd_buffer->push_constant_stages |= stageFlags;
3624 }
3625
3626 VkResult radv_EndCommandBuffer(
3627 VkCommandBuffer commandBuffer)
3628 {
3629 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3630
3631 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
3632 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6)
3633 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WB_L2;
3634
3635 /* Make sure to sync all pending active queries at the end of
3636 * command buffer.
3637 */
3638 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
3639
3640 /* Since NGG streamout uses GDS, we need to make GDS idle when
3641 * we leave the IB, otherwise another process might overwrite
3642 * it while our shaders are busy.
3643 */
3644 if (cmd_buffer->gds_needed)
3645 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
3646
3647 si_emit_cache_flush(cmd_buffer);
3648 }
3649
3650 /* Make sure CP DMA is idle at the end of IBs because the kernel
3651 * doesn't wait for it.
3652 */
3653 si_cp_dma_wait_for_idle(cmd_buffer);
3654
3655 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3656 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
3657
3658 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
3659 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3660
3661 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
3662
3663 return cmd_buffer->record_result;
3664 }
3665
3666 static void
3667 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
3668 {
3669 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3670
3671 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
3672 return;
3673
3674 assert(!pipeline->ctx_cs.cdw);
3675
3676 cmd_buffer->state.emitted_compute_pipeline = pipeline;
3677
3678 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
3679 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
3680
3681 cmd_buffer->compute_scratch_size_needed =
3682 MAX2(cmd_buffer->compute_scratch_size_needed,
3683 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
3684
3685 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3686 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
3687
3688 if (unlikely(cmd_buffer->device->trace_bo))
3689 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
3690 }
3691
3692 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
3693 VkPipelineBindPoint bind_point)
3694 {
3695 struct radv_descriptor_state *descriptors_state =
3696 radv_get_descriptors_state(cmd_buffer, bind_point);
3697
3698 descriptors_state->dirty |= descriptors_state->valid;
3699 }
3700
3701 void radv_CmdBindPipeline(
3702 VkCommandBuffer commandBuffer,
3703 VkPipelineBindPoint pipelineBindPoint,
3704 VkPipeline _pipeline)
3705 {
3706 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3707 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
3708
3709 switch (pipelineBindPoint) {
3710 case VK_PIPELINE_BIND_POINT_COMPUTE:
3711 if (cmd_buffer->state.compute_pipeline == pipeline)
3712 return;
3713 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3714
3715 cmd_buffer->state.compute_pipeline = pipeline;
3716 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
3717 break;
3718 case VK_PIPELINE_BIND_POINT_GRAPHICS:
3719 if (cmd_buffer->state.pipeline == pipeline)
3720 return;
3721 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3722
3723 cmd_buffer->state.pipeline = pipeline;
3724 if (!pipeline)
3725 break;
3726
3727 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
3728 cmd_buffer->push_constant_stages |= pipeline->active_stages;
3729
3730 /* the new vertex shader might not have the same user regs */
3731 cmd_buffer->state.last_first_instance = -1;
3732 cmd_buffer->state.last_vertex_offset = -1;
3733
3734 /* Prefetch all pipeline shaders at first draw time. */
3735 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
3736
3737 if ((cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI10 ||
3738 cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI12 ||
3739 cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI14) &&
3740 cmd_buffer->state.emitted_pipeline &&
3741 radv_pipeline_has_ngg(cmd_buffer->state.emitted_pipeline) &&
3742 !radv_pipeline_has_ngg(cmd_buffer->state.pipeline)) {
3743 /* Transitioning from NGG to legacy GS requires
3744 * VGT_FLUSH on Navi10-14. VGT_FLUSH is also emitted
3745 * at the beginning of IBs when legacy GS ring pointers
3746 * are set.
3747 */
3748 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
3749 }
3750
3751 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
3752 radv_bind_streamout_state(cmd_buffer, pipeline);
3753
3754 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
3755 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
3756 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
3757 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
3758
3759 if (radv_pipeline_has_tess(pipeline))
3760 cmd_buffer->tess_rings_needed = true;
3761 break;
3762 default:
3763 assert(!"invalid bind point");
3764 break;
3765 }
3766 }
3767
3768 void radv_CmdSetViewport(
3769 VkCommandBuffer commandBuffer,
3770 uint32_t firstViewport,
3771 uint32_t viewportCount,
3772 const VkViewport* pViewports)
3773 {
3774 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3775 struct radv_cmd_state *state = &cmd_buffer->state;
3776 ASSERTED const uint32_t total_count = firstViewport + viewportCount;
3777
3778 assert(firstViewport < MAX_VIEWPORTS);
3779 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
3780
3781 if (!memcmp(state->dynamic.viewport.viewports + firstViewport,
3782 pViewports, viewportCount * sizeof(*pViewports))) {
3783 return;
3784 }
3785
3786 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
3787 viewportCount * sizeof(*pViewports));
3788
3789 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
3790 }
3791
3792 void radv_CmdSetScissor(
3793 VkCommandBuffer commandBuffer,
3794 uint32_t firstScissor,
3795 uint32_t scissorCount,
3796 const VkRect2D* pScissors)
3797 {
3798 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3799 struct radv_cmd_state *state = &cmd_buffer->state;
3800 ASSERTED const uint32_t total_count = firstScissor + scissorCount;
3801
3802 assert(firstScissor < MAX_SCISSORS);
3803 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
3804
3805 if (!memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
3806 scissorCount * sizeof(*pScissors))) {
3807 return;
3808 }
3809
3810 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
3811 scissorCount * sizeof(*pScissors));
3812
3813 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
3814 }
3815
3816 void radv_CmdSetLineWidth(
3817 VkCommandBuffer commandBuffer,
3818 float lineWidth)
3819 {
3820 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3821
3822 if (cmd_buffer->state.dynamic.line_width == lineWidth)
3823 return;
3824
3825 cmd_buffer->state.dynamic.line_width = lineWidth;
3826 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
3827 }
3828
3829 void radv_CmdSetDepthBias(
3830 VkCommandBuffer commandBuffer,
3831 float depthBiasConstantFactor,
3832 float depthBiasClamp,
3833 float depthBiasSlopeFactor)
3834 {
3835 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3836 struct radv_cmd_state *state = &cmd_buffer->state;
3837
3838 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
3839 state->dynamic.depth_bias.clamp == depthBiasClamp &&
3840 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
3841 return;
3842 }
3843
3844 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
3845 state->dynamic.depth_bias.clamp = depthBiasClamp;
3846 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
3847
3848 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
3849 }
3850
3851 void radv_CmdSetBlendConstants(
3852 VkCommandBuffer commandBuffer,
3853 const float blendConstants[4])
3854 {
3855 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3856 struct radv_cmd_state *state = &cmd_buffer->state;
3857
3858 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
3859 return;
3860
3861 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
3862
3863 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
3864 }
3865
3866 void radv_CmdSetDepthBounds(
3867 VkCommandBuffer commandBuffer,
3868 float minDepthBounds,
3869 float maxDepthBounds)
3870 {
3871 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3872 struct radv_cmd_state *state = &cmd_buffer->state;
3873
3874 if (state->dynamic.depth_bounds.min == minDepthBounds &&
3875 state->dynamic.depth_bounds.max == maxDepthBounds) {
3876 return;
3877 }
3878
3879 state->dynamic.depth_bounds.min = minDepthBounds;
3880 state->dynamic.depth_bounds.max = maxDepthBounds;
3881
3882 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
3883 }
3884
3885 void radv_CmdSetStencilCompareMask(
3886 VkCommandBuffer commandBuffer,
3887 VkStencilFaceFlags faceMask,
3888 uint32_t compareMask)
3889 {
3890 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3891 struct radv_cmd_state *state = &cmd_buffer->state;
3892 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
3893 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
3894
3895 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3896 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3897 return;
3898 }
3899
3900 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3901 state->dynamic.stencil_compare_mask.front = compareMask;
3902 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3903 state->dynamic.stencil_compare_mask.back = compareMask;
3904
3905 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
3906 }
3907
3908 void radv_CmdSetStencilWriteMask(
3909 VkCommandBuffer commandBuffer,
3910 VkStencilFaceFlags faceMask,
3911 uint32_t writeMask)
3912 {
3913 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3914 struct radv_cmd_state *state = &cmd_buffer->state;
3915 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
3916 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
3917
3918 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3919 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3920 return;
3921 }
3922
3923 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3924 state->dynamic.stencil_write_mask.front = writeMask;
3925 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3926 state->dynamic.stencil_write_mask.back = writeMask;
3927
3928 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
3929 }
3930
3931 void radv_CmdSetStencilReference(
3932 VkCommandBuffer commandBuffer,
3933 VkStencilFaceFlags faceMask,
3934 uint32_t reference)
3935 {
3936 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3937 struct radv_cmd_state *state = &cmd_buffer->state;
3938 bool front_same = state->dynamic.stencil_reference.front == reference;
3939 bool back_same = state->dynamic.stencil_reference.back == reference;
3940
3941 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3942 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3943 return;
3944 }
3945
3946 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3947 cmd_buffer->state.dynamic.stencil_reference.front = reference;
3948 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3949 cmd_buffer->state.dynamic.stencil_reference.back = reference;
3950
3951 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
3952 }
3953
3954 void radv_CmdSetDiscardRectangleEXT(
3955 VkCommandBuffer commandBuffer,
3956 uint32_t firstDiscardRectangle,
3957 uint32_t discardRectangleCount,
3958 const VkRect2D* pDiscardRectangles)
3959 {
3960 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3961 struct radv_cmd_state *state = &cmd_buffer->state;
3962 ASSERTED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
3963
3964 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
3965 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
3966
3967 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
3968 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
3969 return;
3970 }
3971
3972 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
3973 pDiscardRectangles, discardRectangleCount);
3974
3975 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
3976 }
3977
3978 void radv_CmdSetSampleLocationsEXT(
3979 VkCommandBuffer commandBuffer,
3980 const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
3981 {
3982 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3983 struct radv_cmd_state *state = &cmd_buffer->state;
3984
3985 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
3986
3987 state->dynamic.sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
3988 state->dynamic.sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
3989 state->dynamic.sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
3990 typed_memcpy(&state->dynamic.sample_location.locations[0],
3991 pSampleLocationsInfo->pSampleLocations,
3992 pSampleLocationsInfo->sampleLocationsCount);
3993
3994 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS;
3995 }
3996
3997 void radv_CmdExecuteCommands(
3998 VkCommandBuffer commandBuffer,
3999 uint32_t commandBufferCount,
4000 const VkCommandBuffer* pCmdBuffers)
4001 {
4002 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
4003
4004 assert(commandBufferCount > 0);
4005
4006 /* Emit pending flushes on primary prior to executing secondary */
4007 si_emit_cache_flush(primary);
4008
4009 for (uint32_t i = 0; i < commandBufferCount; i++) {
4010 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
4011
4012 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
4013 secondary->scratch_size_needed);
4014 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
4015 secondary->compute_scratch_size_needed);
4016
4017 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
4018 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
4019 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
4020 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
4021 if (secondary->tess_rings_needed)
4022 primary->tess_rings_needed = true;
4023 if (secondary->sample_positions_needed)
4024 primary->sample_positions_needed = true;
4025
4026 if (!secondary->state.framebuffer &&
4027 (primary->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)) {
4028 /* Emit the framebuffer state from primary if secondary
4029 * has been recorded without a framebuffer, otherwise
4030 * fast color/depth clears can't work.
4031 */
4032 radv_emit_framebuffer_state(primary);
4033 }
4034
4035 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
4036
4037
4038 /* When the secondary command buffer is compute only we don't
4039 * need to re-emit the current graphics pipeline.
4040 */
4041 if (secondary->state.emitted_pipeline) {
4042 primary->state.emitted_pipeline =
4043 secondary->state.emitted_pipeline;
4044 }
4045
4046 /* When the secondary command buffer is graphics only we don't
4047 * need to re-emit the current compute pipeline.
4048 */
4049 if (secondary->state.emitted_compute_pipeline) {
4050 primary->state.emitted_compute_pipeline =
4051 secondary->state.emitted_compute_pipeline;
4052 }
4053
4054 /* Only re-emit the draw packets when needed. */
4055 if (secondary->state.last_primitive_reset_en != -1) {
4056 primary->state.last_primitive_reset_en =
4057 secondary->state.last_primitive_reset_en;
4058 }
4059
4060 if (secondary->state.last_primitive_reset_index) {
4061 primary->state.last_primitive_reset_index =
4062 secondary->state.last_primitive_reset_index;
4063 }
4064
4065 if (secondary->state.last_ia_multi_vgt_param) {
4066 primary->state.last_ia_multi_vgt_param =
4067 secondary->state.last_ia_multi_vgt_param;
4068 }
4069
4070 primary->state.last_first_instance = secondary->state.last_first_instance;
4071 primary->state.last_num_instances = secondary->state.last_num_instances;
4072 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
4073
4074 if (secondary->state.last_index_type != -1) {
4075 primary->state.last_index_type =
4076 secondary->state.last_index_type;
4077 }
4078 }
4079
4080 /* After executing commands from secondary buffers we have to dirty
4081 * some states.
4082 */
4083 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
4084 RADV_CMD_DIRTY_INDEX_BUFFER |
4085 RADV_CMD_DIRTY_DYNAMIC_ALL;
4086 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
4087 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
4088 }
4089
4090 VkResult radv_CreateCommandPool(
4091 VkDevice _device,
4092 const VkCommandPoolCreateInfo* pCreateInfo,
4093 const VkAllocationCallbacks* pAllocator,
4094 VkCommandPool* pCmdPool)
4095 {
4096 RADV_FROM_HANDLE(radv_device, device, _device);
4097 struct radv_cmd_pool *pool;
4098
4099 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
4100 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4101 if (pool == NULL)
4102 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4103
4104 if (pAllocator)
4105 pool->alloc = *pAllocator;
4106 else
4107 pool->alloc = device->alloc;
4108
4109 list_inithead(&pool->cmd_buffers);
4110 list_inithead(&pool->free_cmd_buffers);
4111
4112 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
4113
4114 *pCmdPool = radv_cmd_pool_to_handle(pool);
4115
4116 return VK_SUCCESS;
4117
4118 }
4119
4120 void radv_DestroyCommandPool(
4121 VkDevice _device,
4122 VkCommandPool commandPool,
4123 const VkAllocationCallbacks* pAllocator)
4124 {
4125 RADV_FROM_HANDLE(radv_device, device, _device);
4126 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4127
4128 if (!pool)
4129 return;
4130
4131 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4132 &pool->cmd_buffers, pool_link) {
4133 radv_cmd_buffer_destroy(cmd_buffer);
4134 }
4135
4136 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4137 &pool->free_cmd_buffers, pool_link) {
4138 radv_cmd_buffer_destroy(cmd_buffer);
4139 }
4140
4141 vk_free2(&device->alloc, pAllocator, pool);
4142 }
4143
4144 VkResult radv_ResetCommandPool(
4145 VkDevice device,
4146 VkCommandPool commandPool,
4147 VkCommandPoolResetFlags flags)
4148 {
4149 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4150 VkResult result;
4151
4152 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
4153 &pool->cmd_buffers, pool_link) {
4154 result = radv_reset_cmd_buffer(cmd_buffer);
4155 if (result != VK_SUCCESS)
4156 return result;
4157 }
4158
4159 return VK_SUCCESS;
4160 }
4161
4162 void radv_TrimCommandPool(
4163 VkDevice device,
4164 VkCommandPool commandPool,
4165 VkCommandPoolTrimFlags flags)
4166 {
4167 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4168
4169 if (!pool)
4170 return;
4171
4172 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4173 &pool->free_cmd_buffers, pool_link) {
4174 radv_cmd_buffer_destroy(cmd_buffer);
4175 }
4176 }
4177
4178 static void
4179 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
4180 uint32_t subpass_id)
4181 {
4182 struct radv_cmd_state *state = &cmd_buffer->state;
4183 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
4184
4185 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
4186 cmd_buffer->cs, 4096);
4187
4188 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
4189
4190 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
4191
4192 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4193 const uint32_t a = subpass->attachments[i].attachment;
4194 if (a == VK_ATTACHMENT_UNUSED)
4195 continue;
4196
4197 radv_handle_subpass_image_transition(cmd_buffer,
4198 subpass->attachments[i],
4199 true);
4200 }
4201
4202 radv_cmd_buffer_clear_subpass(cmd_buffer);
4203
4204 assert(cmd_buffer->cs->cdw <= cdw_max);
4205 }
4206
4207 static void
4208 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
4209 {
4210 struct radv_cmd_state *state = &cmd_buffer->state;
4211 const struct radv_subpass *subpass = state->subpass;
4212 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
4213
4214 radv_cmd_buffer_resolve_subpass(cmd_buffer);
4215
4216 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4217 const uint32_t a = subpass->attachments[i].attachment;
4218 if (a == VK_ATTACHMENT_UNUSED)
4219 continue;
4220
4221 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
4222 continue;
4223
4224 VkImageLayout layout = state->pass->attachments[a].final_layout;
4225 struct radv_subpass_attachment att = { a, layout };
4226 radv_handle_subpass_image_transition(cmd_buffer, att, false);
4227 }
4228 }
4229
4230 void radv_CmdBeginRenderPass(
4231 VkCommandBuffer commandBuffer,
4232 const VkRenderPassBeginInfo* pRenderPassBegin,
4233 VkSubpassContents contents)
4234 {
4235 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4236 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
4237 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
4238 VkResult result;
4239
4240 cmd_buffer->state.framebuffer = framebuffer;
4241 cmd_buffer->state.pass = pass;
4242 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
4243
4244 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
4245 if (result != VK_SUCCESS)
4246 return;
4247
4248 result = radv_cmd_state_setup_sample_locations(cmd_buffer, pass, pRenderPassBegin);
4249 if (result != VK_SUCCESS)
4250 return;
4251
4252 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
4253 }
4254
4255 void radv_CmdBeginRenderPass2KHR(
4256 VkCommandBuffer commandBuffer,
4257 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
4258 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
4259 {
4260 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
4261 pSubpassBeginInfo->contents);
4262 }
4263
4264 void radv_CmdNextSubpass(
4265 VkCommandBuffer commandBuffer,
4266 VkSubpassContents contents)
4267 {
4268 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4269
4270 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
4271 radv_cmd_buffer_end_subpass(cmd_buffer);
4272 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
4273 }
4274
4275 void radv_CmdNextSubpass2KHR(
4276 VkCommandBuffer commandBuffer,
4277 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
4278 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4279 {
4280 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
4281 }
4282
4283 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
4284 {
4285 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
4286 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
4287 if (!radv_get_shader(pipeline, stage))
4288 continue;
4289
4290 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
4291 if (loc->sgpr_idx == -1)
4292 continue;
4293 uint32_t base_reg = pipeline->user_data_0[stage];
4294 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4295
4296 }
4297 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
4298 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
4299 if (loc->sgpr_idx != -1) {
4300 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
4301 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4302 }
4303 }
4304 }
4305
4306 static void
4307 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4308 uint32_t vertex_count,
4309 bool use_opaque)
4310 {
4311 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
4312 radeon_emit(cmd_buffer->cs, vertex_count);
4313 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
4314 S_0287F0_USE_OPAQUE(use_opaque));
4315 }
4316
4317 static void
4318 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
4319 uint64_t index_va,
4320 uint32_t index_count)
4321 {
4322 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
4323 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
4324 radeon_emit(cmd_buffer->cs, index_va);
4325 radeon_emit(cmd_buffer->cs, index_va >> 32);
4326 radeon_emit(cmd_buffer->cs, index_count);
4327 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
4328 }
4329
4330 static void
4331 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4332 bool indexed,
4333 uint32_t draw_count,
4334 uint64_t count_va,
4335 uint32_t stride)
4336 {
4337 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4338 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
4339 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
4340 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id;
4341 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
4342 bool predicating = cmd_buffer->state.predicating;
4343 assert(base_reg);
4344
4345 /* just reset draw state for vertex data */
4346 cmd_buffer->state.last_first_instance = -1;
4347 cmd_buffer->state.last_num_instances = -1;
4348 cmd_buffer->state.last_vertex_offset = -1;
4349
4350 if (draw_count == 1 && !count_va && !draw_id_enable) {
4351 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
4352 PKT3_DRAW_INDIRECT, 3, predicating));
4353 radeon_emit(cs, 0);
4354 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4355 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4356 radeon_emit(cs, di_src_sel);
4357 } else {
4358 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
4359 PKT3_DRAW_INDIRECT_MULTI,
4360 8, predicating));
4361 radeon_emit(cs, 0);
4362 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4363 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4364 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
4365 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
4366 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
4367 radeon_emit(cs, draw_count); /* count */
4368 radeon_emit(cs, count_va); /* count_addr */
4369 radeon_emit(cs, count_va >> 32);
4370 radeon_emit(cs, stride); /* stride */
4371 radeon_emit(cs, di_src_sel);
4372 }
4373 }
4374
4375 static void
4376 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
4377 const struct radv_draw_info *info)
4378 {
4379 struct radv_cmd_state *state = &cmd_buffer->state;
4380 struct radeon_winsys *ws = cmd_buffer->device->ws;
4381 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4382
4383 if (info->indirect) {
4384 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4385 uint64_t count_va = 0;
4386
4387 va += info->indirect->offset + info->indirect_offset;
4388
4389 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4390
4391 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
4392 radeon_emit(cs, 1);
4393 radeon_emit(cs, va);
4394 radeon_emit(cs, va >> 32);
4395
4396 if (info->count_buffer) {
4397 count_va = radv_buffer_get_va(info->count_buffer->bo);
4398 count_va += info->count_buffer->offset +
4399 info->count_buffer_offset;
4400
4401 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
4402 }
4403
4404 if (!state->subpass->view_mask) {
4405 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4406 info->indexed,
4407 info->count,
4408 count_va,
4409 info->stride);
4410 } else {
4411 unsigned i;
4412 for_each_bit(i, state->subpass->view_mask) {
4413 radv_emit_view_index(cmd_buffer, i);
4414
4415 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4416 info->indexed,
4417 info->count,
4418 count_va,
4419 info->stride);
4420 }
4421 }
4422 } else {
4423 assert(state->pipeline->graphics.vtx_base_sgpr);
4424
4425 if (info->vertex_offset != state->last_vertex_offset ||
4426 info->first_instance != state->last_first_instance) {
4427 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
4428 state->pipeline->graphics.vtx_emit_num);
4429
4430 radeon_emit(cs, info->vertex_offset);
4431 radeon_emit(cs, info->first_instance);
4432 if (state->pipeline->graphics.vtx_emit_num == 3)
4433 radeon_emit(cs, 0);
4434 state->last_first_instance = info->first_instance;
4435 state->last_vertex_offset = info->vertex_offset;
4436 }
4437
4438 if (state->last_num_instances != info->instance_count) {
4439 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
4440 radeon_emit(cs, info->instance_count);
4441 state->last_num_instances = info->instance_count;
4442 }
4443
4444 if (info->indexed) {
4445 int index_size = radv_get_vgt_index_size(state->index_type);
4446 uint64_t index_va;
4447
4448 /* Skip draw calls with 0-sized index buffers. They
4449 * cause a hang on some chips, like Navi10-14.
4450 */
4451 if (!cmd_buffer->state.max_index_count)
4452 return;
4453
4454 index_va = state->index_va;
4455 index_va += info->first_index * index_size;
4456
4457 if (!state->subpass->view_mask) {
4458 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4459 index_va,
4460 info->count);
4461 } else {
4462 unsigned i;
4463 for_each_bit(i, state->subpass->view_mask) {
4464 radv_emit_view_index(cmd_buffer, i);
4465
4466 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4467 index_va,
4468 info->count);
4469 }
4470 }
4471 } else {
4472 if (!state->subpass->view_mask) {
4473 radv_cs_emit_draw_packet(cmd_buffer,
4474 info->count,
4475 !!info->strmout_buffer);
4476 } else {
4477 unsigned i;
4478 for_each_bit(i, state->subpass->view_mask) {
4479 radv_emit_view_index(cmd_buffer, i);
4480
4481 radv_cs_emit_draw_packet(cmd_buffer,
4482 info->count,
4483 !!info->strmout_buffer);
4484 }
4485 }
4486 }
4487 }
4488 }
4489
4490 /*
4491 * Vega and raven have a bug which triggers if there are multiple context
4492 * register contexts active at the same time with different scissor values.
4493 *
4494 * There are two possible workarounds:
4495 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
4496 * there is only ever 1 active set of scissor values at the same time.
4497 *
4498 * 2) Whenever the hardware switches contexts we have to set the scissor
4499 * registers again even if it is a noop. That way the new context gets
4500 * the correct scissor values.
4501 *
4502 * This implements option 2. radv_need_late_scissor_emission needs to
4503 * return true on affected HW if radv_emit_all_graphics_states sets
4504 * any context registers.
4505 */
4506 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
4507 const struct radv_draw_info *info)
4508 {
4509 struct radv_cmd_state *state = &cmd_buffer->state;
4510
4511 if (!cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
4512 return false;
4513
4514 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
4515 return true;
4516
4517 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
4518
4519 /* Index, vertex and streamout buffers don't change context regs, and
4520 * pipeline is already handled.
4521 */
4522 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
4523 RADV_CMD_DIRTY_VERTEX_BUFFER |
4524 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
4525 RADV_CMD_DIRTY_PIPELINE);
4526
4527 if (cmd_buffer->state.dirty & used_states)
4528 return true;
4529
4530 uint32_t primitive_reset_index =
4531 radv_get_primitive_reset_index(cmd_buffer);
4532
4533 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
4534 primitive_reset_index != state->last_primitive_reset_index)
4535 return true;
4536
4537 return false;
4538 }
4539
4540 static void
4541 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
4542 const struct radv_draw_info *info)
4543 {
4544 bool late_scissor_emission;
4545
4546 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
4547 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
4548 radv_emit_rbplus_state(cmd_buffer);
4549
4550 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
4551 radv_emit_graphics_pipeline(cmd_buffer);
4552
4553 /* This should be before the cmd_buffer->state.dirty is cleared
4554 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4555 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4556 late_scissor_emission =
4557 radv_need_late_scissor_emission(cmd_buffer, info);
4558
4559 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
4560 radv_emit_framebuffer_state(cmd_buffer);
4561
4562 if (info->indexed) {
4563 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
4564 radv_emit_index_buffer(cmd_buffer);
4565 } else {
4566 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4567 * so the state must be re-emitted before the next indexed
4568 * draw.
4569 */
4570 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
4571 cmd_buffer->state.last_index_type = -1;
4572 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
4573 }
4574 }
4575
4576 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
4577
4578 radv_emit_draw_registers(cmd_buffer, info);
4579
4580 if (late_scissor_emission)
4581 radv_emit_scissor(cmd_buffer);
4582 }
4583
4584 static void
4585 radv_draw(struct radv_cmd_buffer *cmd_buffer,
4586 const struct radv_draw_info *info)
4587 {
4588 struct radeon_info *rad_info =
4589 &cmd_buffer->device->physical_device->rad_info;
4590 bool has_prefetch =
4591 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4592 bool pipeline_is_dirty =
4593 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
4594 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
4595
4596 ASSERTED unsigned cdw_max =
4597 radeon_check_space(cmd_buffer->device->ws,
4598 cmd_buffer->cs, 4096);
4599
4600 if (likely(!info->indirect)) {
4601 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4602 * no workaround for indirect draws, but we can at least skip
4603 * direct draws.
4604 */
4605 if (unlikely(!info->instance_count))
4606 return;
4607
4608 /* Handle count == 0. */
4609 if (unlikely(!info->count && !info->strmout_buffer))
4610 return;
4611 }
4612
4613 /* Use optimal packet order based on whether we need to sync the
4614 * pipeline.
4615 */
4616 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4617 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4618 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4619 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4620 /* If we have to wait for idle, set all states first, so that
4621 * all SET packets are processed in parallel with previous draw
4622 * calls. Then upload descriptors, set shader pointers, and
4623 * draw, and prefetch at the end. This ensures that the time
4624 * the CUs are idle is very short. (there are only SET_SH
4625 * packets between the wait and the draw)
4626 */
4627 radv_emit_all_graphics_states(cmd_buffer, info);
4628 si_emit_cache_flush(cmd_buffer);
4629 /* <-- CUs are idle here --> */
4630
4631 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4632
4633 radv_emit_draw_packets(cmd_buffer, info);
4634 /* <-- CUs are busy here --> */
4635
4636 /* Start prefetches after the draw has been started. Both will
4637 * run in parallel, but starting the draw first is more
4638 * important.
4639 */
4640 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4641 radv_emit_prefetch_L2(cmd_buffer,
4642 cmd_buffer->state.pipeline, false);
4643 }
4644 } else {
4645 /* If we don't wait for idle, start prefetches first, then set
4646 * states, and draw at the end.
4647 */
4648 si_emit_cache_flush(cmd_buffer);
4649
4650 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4651 /* Only prefetch the vertex shader and VBO descriptors
4652 * in order to start the draw as soon as possible.
4653 */
4654 radv_emit_prefetch_L2(cmd_buffer,
4655 cmd_buffer->state.pipeline, true);
4656 }
4657
4658 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4659
4660 radv_emit_all_graphics_states(cmd_buffer, info);
4661 radv_emit_draw_packets(cmd_buffer, info);
4662
4663 /* Prefetch the remaining shaders after the draw has been
4664 * started.
4665 */
4666 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4667 radv_emit_prefetch_L2(cmd_buffer,
4668 cmd_buffer->state.pipeline, false);
4669 }
4670 }
4671
4672 /* Workaround for a VGT hang when streamout is enabled.
4673 * It must be done after drawing.
4674 */
4675 if (cmd_buffer->state.streamout.streamout_enabled &&
4676 (rad_info->family == CHIP_HAWAII ||
4677 rad_info->family == CHIP_TONGA ||
4678 rad_info->family == CHIP_FIJI)) {
4679 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
4680 }
4681
4682 assert(cmd_buffer->cs->cdw <= cdw_max);
4683 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
4684 }
4685
4686 void radv_CmdDraw(
4687 VkCommandBuffer commandBuffer,
4688 uint32_t vertexCount,
4689 uint32_t instanceCount,
4690 uint32_t firstVertex,
4691 uint32_t firstInstance)
4692 {
4693 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4694 struct radv_draw_info info = {};
4695
4696 info.count = vertexCount;
4697 info.instance_count = instanceCount;
4698 info.first_instance = firstInstance;
4699 info.vertex_offset = firstVertex;
4700
4701 radv_draw(cmd_buffer, &info);
4702 }
4703
4704 void radv_CmdDrawIndexed(
4705 VkCommandBuffer commandBuffer,
4706 uint32_t indexCount,
4707 uint32_t instanceCount,
4708 uint32_t firstIndex,
4709 int32_t vertexOffset,
4710 uint32_t firstInstance)
4711 {
4712 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4713 struct radv_draw_info info = {};
4714
4715 info.indexed = true;
4716 info.count = indexCount;
4717 info.instance_count = instanceCount;
4718 info.first_index = firstIndex;
4719 info.vertex_offset = vertexOffset;
4720 info.first_instance = firstInstance;
4721
4722 radv_draw(cmd_buffer, &info);
4723 }
4724
4725 void radv_CmdDrawIndirect(
4726 VkCommandBuffer commandBuffer,
4727 VkBuffer _buffer,
4728 VkDeviceSize offset,
4729 uint32_t drawCount,
4730 uint32_t stride)
4731 {
4732 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4733 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4734 struct radv_draw_info info = {};
4735
4736 info.count = drawCount;
4737 info.indirect = buffer;
4738 info.indirect_offset = offset;
4739 info.stride = stride;
4740
4741 radv_draw(cmd_buffer, &info);
4742 }
4743
4744 void radv_CmdDrawIndexedIndirect(
4745 VkCommandBuffer commandBuffer,
4746 VkBuffer _buffer,
4747 VkDeviceSize offset,
4748 uint32_t drawCount,
4749 uint32_t stride)
4750 {
4751 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4752 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4753 struct radv_draw_info info = {};
4754
4755 info.indexed = true;
4756 info.count = drawCount;
4757 info.indirect = buffer;
4758 info.indirect_offset = offset;
4759 info.stride = stride;
4760
4761 radv_draw(cmd_buffer, &info);
4762 }
4763
4764 void radv_CmdDrawIndirectCountKHR(
4765 VkCommandBuffer commandBuffer,
4766 VkBuffer _buffer,
4767 VkDeviceSize offset,
4768 VkBuffer _countBuffer,
4769 VkDeviceSize countBufferOffset,
4770 uint32_t maxDrawCount,
4771 uint32_t stride)
4772 {
4773 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4774 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4775 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4776 struct radv_draw_info info = {};
4777
4778 info.count = maxDrawCount;
4779 info.indirect = buffer;
4780 info.indirect_offset = offset;
4781 info.count_buffer = count_buffer;
4782 info.count_buffer_offset = countBufferOffset;
4783 info.stride = stride;
4784
4785 radv_draw(cmd_buffer, &info);
4786 }
4787
4788 void radv_CmdDrawIndexedIndirectCountKHR(
4789 VkCommandBuffer commandBuffer,
4790 VkBuffer _buffer,
4791 VkDeviceSize offset,
4792 VkBuffer _countBuffer,
4793 VkDeviceSize countBufferOffset,
4794 uint32_t maxDrawCount,
4795 uint32_t stride)
4796 {
4797 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4798 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4799 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4800 struct radv_draw_info info = {};
4801
4802 info.indexed = true;
4803 info.count = maxDrawCount;
4804 info.indirect = buffer;
4805 info.indirect_offset = offset;
4806 info.count_buffer = count_buffer;
4807 info.count_buffer_offset = countBufferOffset;
4808 info.stride = stride;
4809
4810 radv_draw(cmd_buffer, &info);
4811 }
4812
4813 struct radv_dispatch_info {
4814 /**
4815 * Determine the layout of the grid (in block units) to be used.
4816 */
4817 uint32_t blocks[3];
4818
4819 /**
4820 * A starting offset for the grid. If unaligned is set, the offset
4821 * must still be aligned.
4822 */
4823 uint32_t offsets[3];
4824 /**
4825 * Whether it's an unaligned compute dispatch.
4826 */
4827 bool unaligned;
4828
4829 /**
4830 * Indirect compute parameters resource.
4831 */
4832 struct radv_buffer *indirect;
4833 uint64_t indirect_offset;
4834 };
4835
4836 static void
4837 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
4838 const struct radv_dispatch_info *info)
4839 {
4840 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4841 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4842 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
4843 struct radeon_winsys *ws = cmd_buffer->device->ws;
4844 bool predicating = cmd_buffer->state.predicating;
4845 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4846 struct radv_userdata_info *loc;
4847
4848 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
4849 AC_UD_CS_GRID_SIZE);
4850
4851 ASSERTED unsigned cdw_max = radeon_check_space(ws, cs, 25);
4852
4853 if (compute_shader->info.wave_size == 32) {
4854 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
4855 dispatch_initiator |= S_00B800_CS_W32_EN(1);
4856 }
4857
4858 if (info->indirect) {
4859 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4860
4861 va += info->indirect->offset + info->indirect_offset;
4862
4863 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4864
4865 if (loc->sgpr_idx != -1) {
4866 for (unsigned i = 0; i < 3; ++i) {
4867 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
4868 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
4869 COPY_DATA_DST_SEL(COPY_DATA_REG));
4870 radeon_emit(cs, (va + 4 * i));
4871 radeon_emit(cs, (va + 4 * i) >> 32);
4872 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
4873 + loc->sgpr_idx * 4) >> 2) + i);
4874 radeon_emit(cs, 0);
4875 }
4876 }
4877
4878 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
4879 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
4880 PKT3_SHADER_TYPE_S(1));
4881 radeon_emit(cs, va);
4882 radeon_emit(cs, va >> 32);
4883 radeon_emit(cs, dispatch_initiator);
4884 } else {
4885 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
4886 PKT3_SHADER_TYPE_S(1));
4887 radeon_emit(cs, 1);
4888 radeon_emit(cs, va);
4889 radeon_emit(cs, va >> 32);
4890
4891 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
4892 PKT3_SHADER_TYPE_S(1));
4893 radeon_emit(cs, 0);
4894 radeon_emit(cs, dispatch_initiator);
4895 }
4896 } else {
4897 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
4898 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
4899
4900 if (info->unaligned) {
4901 unsigned *cs_block_size = compute_shader->info.cs.block_size;
4902 unsigned remainder[3];
4903
4904 /* If aligned, these should be an entire block size,
4905 * not 0.
4906 */
4907 remainder[0] = blocks[0] + cs_block_size[0] -
4908 align_u32_npot(blocks[0], cs_block_size[0]);
4909 remainder[1] = blocks[1] + cs_block_size[1] -
4910 align_u32_npot(blocks[1], cs_block_size[1]);
4911 remainder[2] = blocks[2] + cs_block_size[2] -
4912 align_u32_npot(blocks[2], cs_block_size[2]);
4913
4914 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
4915 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
4916 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
4917
4918 for(unsigned i = 0; i < 3; ++i) {
4919 assert(offsets[i] % cs_block_size[i] == 0);
4920 offsets[i] /= cs_block_size[i];
4921 }
4922
4923 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4924 radeon_emit(cs,
4925 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
4926 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
4927 radeon_emit(cs,
4928 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
4929 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
4930 radeon_emit(cs,
4931 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
4932 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
4933
4934 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
4935 }
4936
4937 if (loc->sgpr_idx != -1) {
4938 assert(loc->num_sgprs == 3);
4939
4940 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
4941 loc->sgpr_idx * 4, 3);
4942 radeon_emit(cs, blocks[0]);
4943 radeon_emit(cs, blocks[1]);
4944 radeon_emit(cs, blocks[2]);
4945 }
4946
4947 if (offsets[0] || offsets[1] || offsets[2]) {
4948 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
4949 radeon_emit(cs, offsets[0]);
4950 radeon_emit(cs, offsets[1]);
4951 radeon_emit(cs, offsets[2]);
4952
4953 /* The blocks in the packet are not counts but end values. */
4954 for (unsigned i = 0; i < 3; ++i)
4955 blocks[i] += offsets[i];
4956 } else {
4957 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
4958 }
4959
4960 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
4961 PKT3_SHADER_TYPE_S(1));
4962 radeon_emit(cs, blocks[0]);
4963 radeon_emit(cs, blocks[1]);
4964 radeon_emit(cs, blocks[2]);
4965 radeon_emit(cs, dispatch_initiator);
4966 }
4967
4968 assert(cmd_buffer->cs->cdw <= cdw_max);
4969 }
4970
4971 static void
4972 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
4973 {
4974 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4975 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4976 }
4977
4978 static void
4979 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
4980 const struct radv_dispatch_info *info)
4981 {
4982 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4983 bool has_prefetch =
4984 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4985 bool pipeline_is_dirty = pipeline &&
4986 pipeline != cmd_buffer->state.emitted_compute_pipeline;
4987
4988 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4989 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4990 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4991 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4992 /* If we have to wait for idle, set all states first, so that
4993 * all SET packets are processed in parallel with previous draw
4994 * calls. Then upload descriptors, set shader pointers, and
4995 * dispatch, and prefetch at the end. This ensures that the
4996 * time the CUs are idle is very short. (there are only SET_SH
4997 * packets between the wait and the draw)
4998 */
4999 radv_emit_compute_pipeline(cmd_buffer);
5000 si_emit_cache_flush(cmd_buffer);
5001 /* <-- CUs are idle here --> */
5002
5003 radv_upload_compute_shader_descriptors(cmd_buffer);
5004
5005 radv_emit_dispatch_packets(cmd_buffer, info);
5006 /* <-- CUs are busy here --> */
5007
5008 /* Start prefetches after the dispatch has been started. Both
5009 * will run in parallel, but starting the dispatch first is
5010 * more important.
5011 */
5012 if (has_prefetch && pipeline_is_dirty) {
5013 radv_emit_shader_prefetch(cmd_buffer,
5014 pipeline->shaders[MESA_SHADER_COMPUTE]);
5015 }
5016 } else {
5017 /* If we don't wait for idle, start prefetches first, then set
5018 * states, and dispatch at the end.
5019 */
5020 si_emit_cache_flush(cmd_buffer);
5021
5022 if (has_prefetch && pipeline_is_dirty) {
5023 radv_emit_shader_prefetch(cmd_buffer,
5024 pipeline->shaders[MESA_SHADER_COMPUTE]);
5025 }
5026
5027 radv_upload_compute_shader_descriptors(cmd_buffer);
5028
5029 radv_emit_compute_pipeline(cmd_buffer);
5030 radv_emit_dispatch_packets(cmd_buffer, info);
5031 }
5032
5033 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
5034 }
5035
5036 void radv_CmdDispatchBase(
5037 VkCommandBuffer commandBuffer,
5038 uint32_t base_x,
5039 uint32_t base_y,
5040 uint32_t base_z,
5041 uint32_t x,
5042 uint32_t y,
5043 uint32_t z)
5044 {
5045 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5046 struct radv_dispatch_info info = {};
5047
5048 info.blocks[0] = x;
5049 info.blocks[1] = y;
5050 info.blocks[2] = z;
5051
5052 info.offsets[0] = base_x;
5053 info.offsets[1] = base_y;
5054 info.offsets[2] = base_z;
5055 radv_dispatch(cmd_buffer, &info);
5056 }
5057
5058 void radv_CmdDispatch(
5059 VkCommandBuffer commandBuffer,
5060 uint32_t x,
5061 uint32_t y,
5062 uint32_t z)
5063 {
5064 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
5065 }
5066
5067 void radv_CmdDispatchIndirect(
5068 VkCommandBuffer commandBuffer,
5069 VkBuffer _buffer,
5070 VkDeviceSize offset)
5071 {
5072 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5073 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5074 struct radv_dispatch_info info = {};
5075
5076 info.indirect = buffer;
5077 info.indirect_offset = offset;
5078
5079 radv_dispatch(cmd_buffer, &info);
5080 }
5081
5082 void radv_unaligned_dispatch(
5083 struct radv_cmd_buffer *cmd_buffer,
5084 uint32_t x,
5085 uint32_t y,
5086 uint32_t z)
5087 {
5088 struct radv_dispatch_info info = {};
5089
5090 info.blocks[0] = x;
5091 info.blocks[1] = y;
5092 info.blocks[2] = z;
5093 info.unaligned = 1;
5094
5095 radv_dispatch(cmd_buffer, &info);
5096 }
5097
5098 void radv_CmdEndRenderPass(
5099 VkCommandBuffer commandBuffer)
5100 {
5101 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5102
5103 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
5104
5105 radv_cmd_buffer_end_subpass(cmd_buffer);
5106
5107 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
5108 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
5109
5110 cmd_buffer->state.pass = NULL;
5111 cmd_buffer->state.subpass = NULL;
5112 cmd_buffer->state.attachments = NULL;
5113 cmd_buffer->state.framebuffer = NULL;
5114 cmd_buffer->state.subpass_sample_locs = NULL;
5115 }
5116
5117 void radv_CmdEndRenderPass2KHR(
5118 VkCommandBuffer commandBuffer,
5119 const VkSubpassEndInfoKHR* pSubpassEndInfo)
5120 {
5121 radv_CmdEndRenderPass(commandBuffer);
5122 }
5123
5124 /*
5125 * For HTILE we have the following interesting clear words:
5126 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
5127 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
5128 * 0xfffffff0: Clear depth to 1.0
5129 * 0x00000000: Clear depth to 0.0
5130 */
5131 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
5132 struct radv_image *image,
5133 const VkImageSubresourceRange *range,
5134 uint32_t clear_word)
5135 {
5136 assert(range->baseMipLevel == 0);
5137 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
5138 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
5139 struct radv_cmd_state *state = &cmd_buffer->state;
5140 VkClearDepthStencilValue value = {};
5141
5142 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5143 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5144
5145 state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, clear_word);
5146
5147 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5148
5149 if (vk_format_is_stencil(image->vk_format))
5150 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
5151
5152 radv_set_ds_clear_metadata(cmd_buffer, image, range, value, aspects);
5153
5154 if (radv_image_is_tc_compat_htile(image)) {
5155 /* Initialize the TC-compat metada value to 0 because by
5156 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
5157 * need have to conditionally update its value when performing
5158 * a fast depth clear.
5159 */
5160 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, range, 0);
5161 }
5162 }
5163
5164 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
5165 struct radv_image *image,
5166 VkImageLayout src_layout,
5167 bool src_render_loop,
5168 VkImageLayout dst_layout,
5169 bool dst_render_loop,
5170 unsigned src_queue_mask,
5171 unsigned dst_queue_mask,
5172 const VkImageSubresourceRange *range,
5173 struct radv_sample_locations_state *sample_locs)
5174 {
5175 if (!radv_image_has_htile(image))
5176 return;
5177
5178 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5179 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
5180
5181 if (radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop,
5182 dst_queue_mask)) {
5183 clear_value = 0;
5184 }
5185
5186 radv_initialize_htile(cmd_buffer, image, range, clear_value);
5187 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5188 radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5189 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
5190 radv_initialize_htile(cmd_buffer, image, range, clear_value);
5191 } else if (radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5192 !radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5193 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5194 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5195
5196 radv_decompress_depth_image_inplace(cmd_buffer, image, range,
5197 sample_locs);
5198
5199 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5200 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5201 }
5202 }
5203
5204 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
5205 struct radv_image *image,
5206 const VkImageSubresourceRange *range,
5207 uint32_t value)
5208 {
5209 struct radv_cmd_state *state = &cmd_buffer->state;
5210
5211 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5212 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5213
5214 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, range, value);
5215
5216 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5217 }
5218
5219 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
5220 struct radv_image *image,
5221 const VkImageSubresourceRange *range)
5222 {
5223 struct radv_cmd_state *state = &cmd_buffer->state;
5224 static const uint32_t fmask_clear_values[4] = {
5225 0x00000000,
5226 0x02020202,
5227 0xE4E4E4E4,
5228 0x76543210
5229 };
5230 uint32_t log2_samples = util_logbase2(image->info.samples);
5231 uint32_t value = fmask_clear_values[log2_samples];
5232
5233 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5234 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5235
5236 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, range, value);
5237
5238 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5239 }
5240
5241 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
5242 struct radv_image *image,
5243 const VkImageSubresourceRange *range, uint32_t value)
5244 {
5245 struct radv_cmd_state *state = &cmd_buffer->state;
5246 unsigned size = 0;
5247
5248 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5249 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5250
5251 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
5252
5253 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) {
5254 /* When DCC is enabled with mipmaps, some levels might not
5255 * support fast clears and we have to initialize them as "fully
5256 * expanded".
5257 */
5258 /* Compute the size of all fast clearable DCC levels. */
5259 for (unsigned i = 0; i < image->planes[0].surface.num_dcc_levels; i++) {
5260 struct legacy_surf_level *surf_level =
5261 &image->planes[0].surface.u.legacy.level[i];
5262 unsigned dcc_fast_clear_size =
5263 surf_level->dcc_slice_fast_clear_size * image->info.array_size;
5264
5265 if (!dcc_fast_clear_size)
5266 break;
5267
5268 size = surf_level->dcc_offset + dcc_fast_clear_size;
5269 }
5270
5271 /* Initialize the mipmap levels without DCC. */
5272 if (size != image->planes[0].surface.dcc_size) {
5273 state->flush_bits |=
5274 radv_fill_buffer(cmd_buffer, image->bo,
5275 image->offset + image->dcc_offset + size,
5276 image->planes[0].surface.dcc_size - size,
5277 0xffffffff);
5278 }
5279 }
5280
5281 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5282 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5283 }
5284
5285 /**
5286 * Initialize DCC/FMASK/CMASK metadata for a color image.
5287 */
5288 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
5289 struct radv_image *image,
5290 VkImageLayout src_layout,
5291 bool src_render_loop,
5292 VkImageLayout dst_layout,
5293 bool dst_render_loop,
5294 unsigned src_queue_mask,
5295 unsigned dst_queue_mask,
5296 const VkImageSubresourceRange *range)
5297 {
5298 if (radv_image_has_cmask(image)) {
5299 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5300
5301 /* TODO: clarify this. */
5302 if (radv_image_has_fmask(image)) {
5303 value = 0xccccccccu;
5304 }
5305
5306 radv_initialise_cmask(cmd_buffer, image, range, value);
5307 }
5308
5309 if (radv_image_has_fmask(image)) {
5310 radv_initialize_fmask(cmd_buffer, image, range);
5311 }
5312
5313 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5314 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5315 bool need_decompress_pass = false;
5316
5317 if (radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout,
5318 dst_render_loop,
5319 dst_queue_mask)) {
5320 value = 0x20202020u;
5321 need_decompress_pass = true;
5322 }
5323
5324 radv_initialize_dcc(cmd_buffer, image, range, value);
5325
5326 radv_update_fce_metadata(cmd_buffer, image, range,
5327 need_decompress_pass);
5328 }
5329
5330 if (radv_image_has_cmask(image) ||
5331 radv_dcc_enabled(image, range->baseMipLevel)) {
5332 uint32_t color_values[2] = {};
5333 radv_set_color_clear_metadata(cmd_buffer, image, range,
5334 color_values);
5335 }
5336 }
5337
5338 /**
5339 * Handle color image transitions for DCC/FMASK/CMASK.
5340 */
5341 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
5342 struct radv_image *image,
5343 VkImageLayout src_layout,
5344 bool src_render_loop,
5345 VkImageLayout dst_layout,
5346 bool dst_render_loop,
5347 unsigned src_queue_mask,
5348 unsigned dst_queue_mask,
5349 const VkImageSubresourceRange *range)
5350 {
5351 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5352 radv_init_color_image_metadata(cmd_buffer, image,
5353 src_layout, src_render_loop,
5354 dst_layout, dst_render_loop,
5355 src_queue_mask, dst_queue_mask,
5356 range);
5357 return;
5358 }
5359
5360 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5361 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
5362 radv_initialize_dcc(cmd_buffer, image, range, 0xffffffffu);
5363 } else if (radv_layout_dcc_compressed(cmd_buffer->device, image, src_layout, src_render_loop, src_queue_mask) &&
5364 !radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout, dst_render_loop, dst_queue_mask)) {
5365 radv_decompress_dcc(cmd_buffer, image, range);
5366 } else if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
5367 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5368 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5369 }
5370 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
5371 bool fce_eliminate = false, fmask_expand = false;
5372
5373 if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
5374 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5375 fce_eliminate = true;
5376 }
5377
5378 if (radv_image_has_fmask(image)) {
5379 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
5380 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
5381 /* A FMASK decompress is required before doing
5382 * a MSAA decompress using FMASK.
5383 */
5384 fmask_expand = true;
5385 }
5386 }
5387
5388 if (fce_eliminate || fmask_expand)
5389 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5390
5391 if (fmask_expand)
5392 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
5393 }
5394 }
5395
5396 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
5397 struct radv_image *image,
5398 VkImageLayout src_layout,
5399 bool src_render_loop,
5400 VkImageLayout dst_layout,
5401 bool dst_render_loop,
5402 uint32_t src_family,
5403 uint32_t dst_family,
5404 const VkImageSubresourceRange *range,
5405 struct radv_sample_locations_state *sample_locs)
5406 {
5407 if (image->exclusive && src_family != dst_family) {
5408 /* This is an acquire or a release operation and there will be
5409 * a corresponding release/acquire. Do the transition in the
5410 * most flexible queue. */
5411
5412 assert(src_family == cmd_buffer->queue_family_index ||
5413 dst_family == cmd_buffer->queue_family_index);
5414
5415 if (src_family == VK_QUEUE_FAMILY_EXTERNAL ||
5416 src_family == VK_QUEUE_FAMILY_FOREIGN_EXT)
5417 return;
5418
5419 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
5420 return;
5421
5422 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
5423 (src_family == RADV_QUEUE_GENERAL ||
5424 dst_family == RADV_QUEUE_GENERAL))
5425 return;
5426 }
5427
5428 if (src_layout == dst_layout)
5429 return;
5430
5431 unsigned src_queue_mask =
5432 radv_image_queue_family_mask(image, src_family,
5433 cmd_buffer->queue_family_index);
5434 unsigned dst_queue_mask =
5435 radv_image_queue_family_mask(image, dst_family,
5436 cmd_buffer->queue_family_index);
5437
5438 if (vk_format_is_depth(image->vk_format)) {
5439 radv_handle_depth_image_transition(cmd_buffer, image,
5440 src_layout, src_render_loop,
5441 dst_layout, dst_render_loop,
5442 src_queue_mask, dst_queue_mask,
5443 range, sample_locs);
5444 } else {
5445 radv_handle_color_image_transition(cmd_buffer, image,
5446 src_layout, src_render_loop,
5447 dst_layout, dst_render_loop,
5448 src_queue_mask, dst_queue_mask,
5449 range);
5450 }
5451 }
5452
5453 struct radv_barrier_info {
5454 uint32_t eventCount;
5455 const VkEvent *pEvents;
5456 VkPipelineStageFlags srcStageMask;
5457 VkPipelineStageFlags dstStageMask;
5458 };
5459
5460 static void
5461 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
5462 uint32_t memoryBarrierCount,
5463 const VkMemoryBarrier *pMemoryBarriers,
5464 uint32_t bufferMemoryBarrierCount,
5465 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
5466 uint32_t imageMemoryBarrierCount,
5467 const VkImageMemoryBarrier *pImageMemoryBarriers,
5468 const struct radv_barrier_info *info)
5469 {
5470 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5471 enum radv_cmd_flush_bits src_flush_bits = 0;
5472 enum radv_cmd_flush_bits dst_flush_bits = 0;
5473
5474 for (unsigned i = 0; i < info->eventCount; ++i) {
5475 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
5476 uint64_t va = radv_buffer_get_va(event->bo);
5477
5478 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5479
5480 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
5481
5482 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
5483 assert(cmd_buffer->cs->cdw <= cdw_max);
5484 }
5485
5486 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
5487 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
5488 NULL);
5489 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
5490 NULL);
5491 }
5492
5493 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
5494 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
5495 NULL);
5496 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
5497 NULL);
5498 }
5499
5500 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5501 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5502
5503 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
5504 image);
5505 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
5506 image);
5507 }
5508
5509 /* The Vulkan spec 1.1.98 says:
5510 *
5511 * "An execution dependency with only
5512 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
5513 * will only prevent that stage from executing in subsequently
5514 * submitted commands. As this stage does not perform any actual
5515 * execution, this is not observable - in effect, it does not delay
5516 * processing of subsequent commands. Similarly an execution dependency
5517 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
5518 * will effectively not wait for any prior commands to complete."
5519 */
5520 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
5521 radv_stage_flush(cmd_buffer, info->srcStageMask);
5522 cmd_buffer->state.flush_bits |= src_flush_bits;
5523
5524 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5525 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5526
5527 const struct VkSampleLocationsInfoEXT *sample_locs_info =
5528 vk_find_struct_const(pImageMemoryBarriers[i].pNext,
5529 SAMPLE_LOCATIONS_INFO_EXT);
5530 struct radv_sample_locations_state sample_locations = {};
5531
5532 if (sample_locs_info) {
5533 assert(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
5534 sample_locations.per_pixel = sample_locs_info->sampleLocationsPerPixel;
5535 sample_locations.grid_size = sample_locs_info->sampleLocationGridSize;
5536 sample_locations.count = sample_locs_info->sampleLocationsCount;
5537 typed_memcpy(&sample_locations.locations[0],
5538 sample_locs_info->pSampleLocations,
5539 sample_locs_info->sampleLocationsCount);
5540 }
5541
5542 radv_handle_image_transition(cmd_buffer, image,
5543 pImageMemoryBarriers[i].oldLayout,
5544 false, /* Outside of a renderpass we are never in a renderloop */
5545 pImageMemoryBarriers[i].newLayout,
5546 false, /* Outside of a renderpass we are never in a renderloop */
5547 pImageMemoryBarriers[i].srcQueueFamilyIndex,
5548 pImageMemoryBarriers[i].dstQueueFamilyIndex,
5549 &pImageMemoryBarriers[i].subresourceRange,
5550 sample_locs_info ? &sample_locations : NULL);
5551 }
5552
5553 /* Make sure CP DMA is idle because the driver might have performed a
5554 * DMA operation for copying or filling buffers/images.
5555 */
5556 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5557 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5558 si_cp_dma_wait_for_idle(cmd_buffer);
5559
5560 cmd_buffer->state.flush_bits |= dst_flush_bits;
5561 }
5562
5563 void radv_CmdPipelineBarrier(
5564 VkCommandBuffer commandBuffer,
5565 VkPipelineStageFlags srcStageMask,
5566 VkPipelineStageFlags destStageMask,
5567 VkBool32 byRegion,
5568 uint32_t memoryBarrierCount,
5569 const VkMemoryBarrier* pMemoryBarriers,
5570 uint32_t bufferMemoryBarrierCount,
5571 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5572 uint32_t imageMemoryBarrierCount,
5573 const VkImageMemoryBarrier* pImageMemoryBarriers)
5574 {
5575 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5576 struct radv_barrier_info info;
5577
5578 info.eventCount = 0;
5579 info.pEvents = NULL;
5580 info.srcStageMask = srcStageMask;
5581 info.dstStageMask = destStageMask;
5582
5583 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5584 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5585 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5586 }
5587
5588
5589 static void write_event(struct radv_cmd_buffer *cmd_buffer,
5590 struct radv_event *event,
5591 VkPipelineStageFlags stageMask,
5592 unsigned value)
5593 {
5594 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5595 uint64_t va = radv_buffer_get_va(event->bo);
5596
5597 si_emit_cache_flush(cmd_buffer);
5598
5599 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5600
5601 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 21);
5602
5603 /* Flags that only require a top-of-pipe event. */
5604 VkPipelineStageFlags top_of_pipe_flags =
5605 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
5606
5607 /* Flags that only require a post-index-fetch event. */
5608 VkPipelineStageFlags post_index_fetch_flags =
5609 top_of_pipe_flags |
5610 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
5611 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
5612
5613 /* Make sure CP DMA is idle because the driver might have performed a
5614 * DMA operation for copying or filling buffers/images.
5615 */
5616 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5617 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5618 si_cp_dma_wait_for_idle(cmd_buffer);
5619
5620 /* TODO: Emit EOS events for syncing PS/CS stages. */
5621
5622 if (!(stageMask & ~top_of_pipe_flags)) {
5623 /* Just need to sync the PFP engine. */
5624 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5625 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5626 S_370_WR_CONFIRM(1) |
5627 S_370_ENGINE_SEL(V_370_PFP));
5628 radeon_emit(cs, va);
5629 radeon_emit(cs, va >> 32);
5630 radeon_emit(cs, value);
5631 } else if (!(stageMask & ~post_index_fetch_flags)) {
5632 /* Sync ME because PFP reads index and indirect buffers. */
5633 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5634 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5635 S_370_WR_CONFIRM(1) |
5636 S_370_ENGINE_SEL(V_370_ME));
5637 radeon_emit(cs, va);
5638 radeon_emit(cs, va >> 32);
5639 radeon_emit(cs, value);
5640 } else {
5641 /* Otherwise, sync all prior GPU work using an EOP event. */
5642 si_cs_emit_write_event_eop(cs,
5643 cmd_buffer->device->physical_device->rad_info.chip_class,
5644 radv_cmd_buffer_uses_mec(cmd_buffer),
5645 V_028A90_BOTTOM_OF_PIPE_TS, 0,
5646 EOP_DST_SEL_MEM,
5647 EOP_DATA_SEL_VALUE_32BIT, va, value,
5648 cmd_buffer->gfx9_eop_bug_va);
5649 }
5650
5651 assert(cmd_buffer->cs->cdw <= cdw_max);
5652 }
5653
5654 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
5655 VkEvent _event,
5656 VkPipelineStageFlags stageMask)
5657 {
5658 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5659 RADV_FROM_HANDLE(radv_event, event, _event);
5660
5661 write_event(cmd_buffer, event, stageMask, 1);
5662 }
5663
5664 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
5665 VkEvent _event,
5666 VkPipelineStageFlags stageMask)
5667 {
5668 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5669 RADV_FROM_HANDLE(radv_event, event, _event);
5670
5671 write_event(cmd_buffer, event, stageMask, 0);
5672 }
5673
5674 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
5675 uint32_t eventCount,
5676 const VkEvent* pEvents,
5677 VkPipelineStageFlags srcStageMask,
5678 VkPipelineStageFlags dstStageMask,
5679 uint32_t memoryBarrierCount,
5680 const VkMemoryBarrier* pMemoryBarriers,
5681 uint32_t bufferMemoryBarrierCount,
5682 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5683 uint32_t imageMemoryBarrierCount,
5684 const VkImageMemoryBarrier* pImageMemoryBarriers)
5685 {
5686 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5687 struct radv_barrier_info info;
5688
5689 info.eventCount = eventCount;
5690 info.pEvents = pEvents;
5691 info.srcStageMask = 0;
5692
5693 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5694 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5695 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5696 }
5697
5698
5699 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
5700 uint32_t deviceMask)
5701 {
5702 /* No-op */
5703 }
5704
5705 /* VK_EXT_conditional_rendering */
5706 void radv_CmdBeginConditionalRenderingEXT(
5707 VkCommandBuffer commandBuffer,
5708 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
5709 {
5710 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5711 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
5712 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5713 bool draw_visible = true;
5714 uint64_t pred_value = 0;
5715 uint64_t va, new_va;
5716 unsigned pred_offset;
5717
5718 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
5719
5720 /* By default, if the 32-bit value at offset in buffer memory is zero,
5721 * then the rendering commands are discarded, otherwise they are
5722 * executed as normal. If the inverted flag is set, all commands are
5723 * discarded if the value is non zero.
5724 */
5725 if (pConditionalRenderingBegin->flags &
5726 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
5727 draw_visible = false;
5728 }
5729
5730 si_emit_cache_flush(cmd_buffer);
5731
5732 /* From the Vulkan spec 1.1.107:
5733 *
5734 * "If the 32-bit value at offset in buffer memory is zero, then the
5735 * rendering commands are discarded, otherwise they are executed as
5736 * normal. If the value of the predicate in buffer memory changes while
5737 * conditional rendering is active, the rendering commands may be
5738 * discarded in an implementation-dependent way. Some implementations
5739 * may latch the value of the predicate upon beginning conditional
5740 * rendering while others may read it before every rendering command."
5741 *
5742 * But, the AMD hardware treats the predicate as a 64-bit value which
5743 * means we need a workaround in the driver. Luckily, it's not required
5744 * to support if the value changes when predication is active.
5745 *
5746 * The workaround is as follows:
5747 * 1) allocate a 64-value in the upload BO and initialize it to 0
5748 * 2) copy the 32-bit predicate value to the upload BO
5749 * 3) use the new allocated VA address for predication
5750 *
5751 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
5752 * in ME (+ sync PFP) instead of PFP.
5753 */
5754 radv_cmd_buffer_upload_data(cmd_buffer, 8, 16, &pred_value, &pred_offset);
5755
5756 new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
5757
5758 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5759 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5760 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
5761 COPY_DATA_WR_CONFIRM);
5762 radeon_emit(cs, va);
5763 radeon_emit(cs, va >> 32);
5764 radeon_emit(cs, new_va);
5765 radeon_emit(cs, new_va >> 32);
5766
5767 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
5768 radeon_emit(cs, 0);
5769
5770 /* Enable predication for this command buffer. */
5771 si_emit_set_predication_state(cmd_buffer, draw_visible, new_va);
5772 cmd_buffer->state.predicating = true;
5773
5774 /* Store conditional rendering user info. */
5775 cmd_buffer->state.predication_type = draw_visible;
5776 cmd_buffer->state.predication_va = new_va;
5777 }
5778
5779 void radv_CmdEndConditionalRenderingEXT(
5780 VkCommandBuffer commandBuffer)
5781 {
5782 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5783
5784 /* Disable predication for this command buffer. */
5785 si_emit_set_predication_state(cmd_buffer, false, 0);
5786 cmd_buffer->state.predicating = false;
5787
5788 /* Reset conditional rendering user info. */
5789 cmd_buffer->state.predication_type = -1;
5790 cmd_buffer->state.predication_va = 0;
5791 }
5792
5793 /* VK_EXT_transform_feedback */
5794 void radv_CmdBindTransformFeedbackBuffersEXT(
5795 VkCommandBuffer commandBuffer,
5796 uint32_t firstBinding,
5797 uint32_t bindingCount,
5798 const VkBuffer* pBuffers,
5799 const VkDeviceSize* pOffsets,
5800 const VkDeviceSize* pSizes)
5801 {
5802 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5803 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5804 uint8_t enabled_mask = 0;
5805
5806 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
5807 for (uint32_t i = 0; i < bindingCount; i++) {
5808 uint32_t idx = firstBinding + i;
5809
5810 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
5811 sb[idx].offset = pOffsets[i];
5812 sb[idx].size = pSizes[i];
5813
5814 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
5815 sb[idx].buffer->bo);
5816
5817 enabled_mask |= 1 << idx;
5818 }
5819
5820 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
5821
5822 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
5823 }
5824
5825 static void
5826 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
5827 {
5828 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5829 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5830
5831 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
5832 radeon_emit(cs,
5833 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
5834 S_028B94_RAST_STREAM(0) |
5835 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
5836 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
5837 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
5838 radeon_emit(cs, so->hw_enabled_mask &
5839 so->enabled_stream_buffers_mask);
5840
5841 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5842 }
5843
5844 static void
5845 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
5846 {
5847 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5848 bool old_streamout_enabled = so->streamout_enabled;
5849 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
5850
5851 so->streamout_enabled = enable;
5852
5853 so->hw_enabled_mask = so->enabled_mask |
5854 (so->enabled_mask << 4) |
5855 (so->enabled_mask << 8) |
5856 (so->enabled_mask << 12);
5857
5858 if (!cmd_buffer->device->physical_device->use_ngg_streamout &&
5859 ((old_streamout_enabled != so->streamout_enabled) ||
5860 (old_hw_enabled_mask != so->hw_enabled_mask)))
5861 radv_emit_streamout_enable(cmd_buffer);
5862
5863 if (cmd_buffer->device->physical_device->use_ngg_streamout)
5864 cmd_buffer->gds_needed = true;
5865 }
5866
5867 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
5868 {
5869 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5870 unsigned reg_strmout_cntl;
5871
5872 /* The register is at different places on different ASICs. */
5873 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
5874 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
5875 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
5876 } else {
5877 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
5878 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
5879 }
5880
5881 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
5882 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
5883
5884 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
5885 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
5886 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
5887 radeon_emit(cs, 0);
5888 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
5889 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
5890 radeon_emit(cs, 4); /* poll interval */
5891 }
5892
5893 static void
5894 radv_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
5895 uint32_t firstCounterBuffer,
5896 uint32_t counterBufferCount,
5897 const VkBuffer *pCounterBuffers,
5898 const VkDeviceSize *pCounterBufferOffsets)
5899
5900 {
5901 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5902 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5903 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5904 uint32_t i;
5905
5906 radv_flush_vgt_streamout(cmd_buffer);
5907
5908 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5909 for_each_bit(i, so->enabled_mask) {
5910 int32_t counter_buffer_idx = i - firstCounterBuffer;
5911 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5912 counter_buffer_idx = -1;
5913
5914 /* AMD GCN binds streamout buffers as shader resources.
5915 * VGT only counts primitives and tells the shader through
5916 * SGPRs what to do.
5917 */
5918 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
5919 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
5920 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
5921
5922 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5923
5924 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5925 /* The array of counter buffers is optional. */
5926 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5927 uint64_t va = radv_buffer_get_va(buffer->bo);
5928
5929 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5930
5931 /* Append */
5932 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5933 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5934 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5935 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
5936 radeon_emit(cs, 0); /* unused */
5937 radeon_emit(cs, 0); /* unused */
5938 radeon_emit(cs, va); /* src address lo */
5939 radeon_emit(cs, va >> 32); /* src address hi */
5940
5941 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5942 } else {
5943 /* Start from the beginning. */
5944 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5945 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5946 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5947 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
5948 radeon_emit(cs, 0); /* unused */
5949 radeon_emit(cs, 0); /* unused */
5950 radeon_emit(cs, 0); /* unused */
5951 radeon_emit(cs, 0); /* unused */
5952 }
5953 }
5954
5955 radv_set_streamout_enable(cmd_buffer, true);
5956 }
5957
5958 static void
5959 gfx10_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
5960 uint32_t firstCounterBuffer,
5961 uint32_t counterBufferCount,
5962 const VkBuffer *pCounterBuffers,
5963 const VkDeviceSize *pCounterBufferOffsets)
5964 {
5965 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5966 unsigned last_target = util_last_bit(so->enabled_mask) - 1;
5967 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5968 uint32_t i;
5969
5970 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
5971 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5972
5973 /* Sync because the next streamout operation will overwrite GDS and we
5974 * have to make sure it's idle.
5975 * TODO: Improve by tracking if there is a streamout operation in
5976 * flight.
5977 */
5978 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
5979 si_emit_cache_flush(cmd_buffer);
5980
5981 for_each_bit(i, so->enabled_mask) {
5982 int32_t counter_buffer_idx = i - firstCounterBuffer;
5983 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5984 counter_buffer_idx = -1;
5985
5986 bool append = counter_buffer_idx >= 0 &&
5987 pCounterBuffers && pCounterBuffers[counter_buffer_idx];
5988 uint64_t va = 0;
5989
5990 if (append) {
5991 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5992
5993 va += radv_buffer_get_va(buffer->bo);
5994 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5995
5996 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5997 }
5998
5999 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
6000 radeon_emit(cs, S_411_SRC_SEL(append ? V_411_SRC_ADDR_TC_L2 : V_411_DATA) |
6001 S_411_DST_SEL(V_411_GDS) |
6002 S_411_CP_SYNC(i == last_target));
6003 radeon_emit(cs, va);
6004 radeon_emit(cs, va >> 32);
6005 radeon_emit(cs, 4 * i); /* destination in GDS */
6006 radeon_emit(cs, 0);
6007 radeon_emit(cs, S_414_BYTE_COUNT_GFX9(4) |
6008 S_414_DISABLE_WR_CONFIRM_GFX9(i != last_target));
6009 }
6010
6011 radv_set_streamout_enable(cmd_buffer, true);
6012 }
6013
6014 void radv_CmdBeginTransformFeedbackEXT(
6015 VkCommandBuffer commandBuffer,
6016 uint32_t firstCounterBuffer,
6017 uint32_t counterBufferCount,
6018 const VkBuffer* pCounterBuffers,
6019 const VkDeviceSize* pCounterBufferOffsets)
6020 {
6021 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6022
6023 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6024 gfx10_emit_streamout_begin(cmd_buffer,
6025 firstCounterBuffer, counterBufferCount,
6026 pCounterBuffers, pCounterBufferOffsets);
6027 } else {
6028 radv_emit_streamout_begin(cmd_buffer,
6029 firstCounterBuffer, counterBufferCount,
6030 pCounterBuffers, pCounterBufferOffsets);
6031 }
6032 }
6033
6034 static void
6035 radv_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6036 uint32_t firstCounterBuffer,
6037 uint32_t counterBufferCount,
6038 const VkBuffer *pCounterBuffers,
6039 const VkDeviceSize *pCounterBufferOffsets)
6040 {
6041 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6042 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6043 uint32_t i;
6044
6045 radv_flush_vgt_streamout(cmd_buffer);
6046
6047 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6048 for_each_bit(i, so->enabled_mask) {
6049 int32_t counter_buffer_idx = i - firstCounterBuffer;
6050 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6051 counter_buffer_idx = -1;
6052
6053 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6054 /* The array of counters buffer is optional. */
6055 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6056 uint64_t va = radv_buffer_get_va(buffer->bo);
6057
6058 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6059
6060 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6061 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6062 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6063 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
6064 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
6065 radeon_emit(cs, va); /* dst address lo */
6066 radeon_emit(cs, va >> 32); /* dst address hi */
6067 radeon_emit(cs, 0); /* unused */
6068 radeon_emit(cs, 0); /* unused */
6069
6070 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6071 }
6072
6073 /* Deactivate transform feedback by zeroing the buffer size.
6074 * The counters (primitives generated, primitives emitted) may
6075 * be enabled even if there is not buffer bound. This ensures
6076 * that the primitives-emitted query won't increment.
6077 */
6078 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
6079
6080 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6081 }
6082
6083 radv_set_streamout_enable(cmd_buffer, false);
6084 }
6085
6086 static void
6087 gfx10_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6088 uint32_t firstCounterBuffer,
6089 uint32_t counterBufferCount,
6090 const VkBuffer *pCounterBuffers,
6091 const VkDeviceSize *pCounterBufferOffsets)
6092 {
6093 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6094 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6095 uint32_t i;
6096
6097 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6098 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6099
6100 for_each_bit(i, so->enabled_mask) {
6101 int32_t counter_buffer_idx = i - firstCounterBuffer;
6102 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6103 counter_buffer_idx = -1;
6104
6105 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6106 /* The array of counters buffer is optional. */
6107 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6108 uint64_t va = radv_buffer_get_va(buffer->bo);
6109
6110 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6111
6112 si_cs_emit_write_event_eop(cs,
6113 cmd_buffer->device->physical_device->rad_info.chip_class,
6114 radv_cmd_buffer_uses_mec(cmd_buffer),
6115 V_028A90_PS_DONE, 0,
6116 EOP_DST_SEL_TC_L2,
6117 EOP_DATA_SEL_GDS,
6118 va, EOP_DATA_GDS(i, 1), 0);
6119
6120 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6121 }
6122 }
6123
6124 radv_set_streamout_enable(cmd_buffer, false);
6125 }
6126
6127 void radv_CmdEndTransformFeedbackEXT(
6128 VkCommandBuffer commandBuffer,
6129 uint32_t firstCounterBuffer,
6130 uint32_t counterBufferCount,
6131 const VkBuffer* pCounterBuffers,
6132 const VkDeviceSize* pCounterBufferOffsets)
6133 {
6134 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6135
6136 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6137 gfx10_emit_streamout_end(cmd_buffer,
6138 firstCounterBuffer, counterBufferCount,
6139 pCounterBuffers, pCounterBufferOffsets);
6140 } else {
6141 radv_emit_streamout_end(cmd_buffer,
6142 firstCounterBuffer, counterBufferCount,
6143 pCounterBuffers, pCounterBufferOffsets);
6144 }
6145 }
6146
6147 void radv_CmdDrawIndirectByteCountEXT(
6148 VkCommandBuffer commandBuffer,
6149 uint32_t instanceCount,
6150 uint32_t firstInstance,
6151 VkBuffer _counterBuffer,
6152 VkDeviceSize counterBufferOffset,
6153 uint32_t counterOffset,
6154 uint32_t vertexStride)
6155 {
6156 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6157 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
6158 struct radv_draw_info info = {};
6159
6160 info.instance_count = instanceCount;
6161 info.first_instance = firstInstance;
6162 info.strmout_buffer = counterBuffer;
6163 info.strmout_buffer_offset = counterBufferOffset;
6164 info.stride = vertexStride;
6165
6166 radv_draw(cmd_buffer, &info);
6167 }
6168
6169 /* VK_AMD_buffer_marker */
6170 void radv_CmdWriteBufferMarkerAMD(
6171 VkCommandBuffer commandBuffer,
6172 VkPipelineStageFlagBits pipelineStage,
6173 VkBuffer dstBuffer,
6174 VkDeviceSize dstOffset,
6175 uint32_t marker)
6176 {
6177 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6178 RADV_FROM_HANDLE(radv_buffer, buffer, dstBuffer);
6179 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6180 uint64_t va = radv_buffer_get_va(buffer->bo) + dstOffset;
6181
6182 si_emit_cache_flush(cmd_buffer);
6183
6184 if (!(pipelineStage & ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT)) {
6185 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
6186 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
6187 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
6188 COPY_DATA_WR_CONFIRM);
6189 radeon_emit(cs, marker);
6190 radeon_emit(cs, 0);
6191 radeon_emit(cs, va);
6192 radeon_emit(cs, va >> 32);
6193 } else {
6194 si_cs_emit_write_event_eop(cs,
6195 cmd_buffer->device->physical_device->rad_info.chip_class,
6196 radv_cmd_buffer_uses_mec(cmd_buffer),
6197 V_028A90_BOTTOM_OF_PIPE_TS, 0,
6198 EOP_DST_SEL_MEM,
6199 EOP_DATA_SEL_VALUE_32BIT,
6200 va, marker,
6201 cmd_buffer->gfx9_eop_bug_va);
6202 }
6203 }