projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: simplify checking for Navi1x chips
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 bool src_render_loop,
58 VkImageLayout dst_layout,
59 bool dst_render_loop,
60 uint32_t src_family,
61 uint32_t dst_family,
62 const VkImageSubresourceRange *range,
63 struct radv_sample_locations_state *sample_locs);
64
65 const struct radv_dynamic_state default_dynamic_state = {
66 .viewport = {
67 .count = 0,
68 },
69 .scissor = {
70 .count = 0,
71 },
72 .line_width = 1.0f,
73 .depth_bias = {
74 .bias = 0.0f,
75 .clamp = 0.0f,
76 .slope = 0.0f,
77 },
78 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
79 .depth_bounds = {
80 .min = 0.0f,
81 .max = 1.0f,
82 },
83 .stencil_compare_mask = {
84 .front = ~0u,
85 .back = ~0u,
86 },
87 .stencil_write_mask = {
88 .front = ~0u,
89 .back = ~0u,
90 },
91 .stencil_reference = {
92 .front = 0u,
93 .back = 0u,
94 },
95 .line_stipple = {
96 .factor = 0u,
97 .pattern = 0u,
98 },
99 };
100
101 static void
102 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
103 const struct radv_dynamic_state *src)
104 {
105 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
106 uint32_t copy_mask = src->mask;
107 uint32_t dest_mask = 0;
108
109 /* Make sure to copy the number of viewports/scissors because they can
110 * only be specified at pipeline creation time.
111 */
112 dest->viewport.count = src->viewport.count;
113 dest->scissor.count = src->scissor.count;
114 dest->discard_rectangle.count = src->discard_rectangle.count;
115 dest->sample_location.count = src->sample_location.count;
116
117 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
118 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
119 src->viewport.count * sizeof(VkViewport))) {
120 typed_memcpy(dest->viewport.viewports,
121 src->viewport.viewports,
122 src->viewport.count);
123 dest_mask |= RADV_DYNAMIC_VIEWPORT;
124 }
125 }
126
127 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
128 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
129 src->scissor.count * sizeof(VkRect2D))) {
130 typed_memcpy(dest->scissor.scissors,
131 src->scissor.scissors, src->scissor.count);
132 dest_mask |= RADV_DYNAMIC_SCISSOR;
133 }
134 }
135
136 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
137 if (dest->line_width != src->line_width) {
138 dest->line_width = src->line_width;
139 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
140 }
141 }
142
143 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
144 if (memcmp(&dest->depth_bias, &src->depth_bias,
145 sizeof(src->depth_bias))) {
146 dest->depth_bias = src->depth_bias;
147 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
148 }
149 }
150
151 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
152 if (memcmp(&dest->blend_constants, &src->blend_constants,
153 sizeof(src->blend_constants))) {
154 typed_memcpy(dest->blend_constants,
155 src->blend_constants, 4);
156 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
157 }
158 }
159
160 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
161 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
162 sizeof(src->depth_bounds))) {
163 dest->depth_bounds = src->depth_bounds;
164 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
165 }
166 }
167
168 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
169 if (memcmp(&dest->stencil_compare_mask,
170 &src->stencil_compare_mask,
171 sizeof(src->stencil_compare_mask))) {
172 dest->stencil_compare_mask = src->stencil_compare_mask;
173 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
174 }
175 }
176
177 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
178 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
179 sizeof(src->stencil_write_mask))) {
180 dest->stencil_write_mask = src->stencil_write_mask;
181 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
182 }
183 }
184
185 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
186 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
187 sizeof(src->stencil_reference))) {
188 dest->stencil_reference = src->stencil_reference;
189 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
190 }
191 }
192
193 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
194 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
195 src->discard_rectangle.count * sizeof(VkRect2D))) {
196 typed_memcpy(dest->discard_rectangle.rectangles,
197 src->discard_rectangle.rectangles,
198 src->discard_rectangle.count);
199 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
200 }
201 }
202
203 if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
204 if (dest->sample_location.per_pixel != src->sample_location.per_pixel ||
205 dest->sample_location.grid_size.width != src->sample_location.grid_size.width ||
206 dest->sample_location.grid_size.height != src->sample_location.grid_size.height ||
207 memcmp(&dest->sample_location.locations,
208 &src->sample_location.locations,
209 src->sample_location.count * sizeof(VkSampleLocationEXT))) {
210 dest->sample_location.per_pixel = src->sample_location.per_pixel;
211 dest->sample_location.grid_size = src->sample_location.grid_size;
212 typed_memcpy(dest->sample_location.locations,
213 src->sample_location.locations,
214 src->sample_location.count);
215 dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
216 }
217 }
218
219 if (copy_mask & RADV_DYNAMIC_LINE_STIPPLE) {
220 if (memcmp(&dest->line_stipple, &src->line_stipple,
221 sizeof(src->line_stipple))) {
222 dest->line_stipple = src->line_stipple;
223 dest_mask |= RADV_DYNAMIC_LINE_STIPPLE;
224 }
225 }
226
227 cmd_buffer->state.dirty |= dest_mask;
228 }
229
230 static void
231 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
232 struct radv_pipeline *pipeline)
233 {
234 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
235 struct radv_shader_info *info;
236
237 if (!pipeline->streamout_shader ||
238 cmd_buffer->device->physical_device->use_ngg_streamout)
239 return;
240
241 info = &pipeline->streamout_shader->info;
242 for (int i = 0; i < MAX_SO_BUFFERS; i++)
243 so->stride_in_dw[i] = info->so.strides[i];
244
245 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
246 }
247
248 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
249 {
250 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
251 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
252 }
253
254 enum ring_type radv_queue_family_to_ring(int f) {
255 switch (f) {
256 case RADV_QUEUE_GENERAL:
257 return RING_GFX;
258 case RADV_QUEUE_COMPUTE:
259 return RING_COMPUTE;
260 case RADV_QUEUE_TRANSFER:
261 return RING_DMA;
262 default:
263 unreachable("Unknown queue family");
264 }
265 }
266
267 static VkResult radv_create_cmd_buffer(
268 struct radv_device * device,
269 struct radv_cmd_pool * pool,
270 VkCommandBufferLevel level,
271 VkCommandBuffer* pCommandBuffer)
272 {
273 struct radv_cmd_buffer *cmd_buffer;
274 unsigned ring;
275 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
276 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
277 if (cmd_buffer == NULL)
278 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
279
280 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
281 cmd_buffer->device = device;
282 cmd_buffer->pool = pool;
283 cmd_buffer->level = level;
284
285 if (pool) {
286 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
287 cmd_buffer->queue_family_index = pool->queue_family_index;
288
289 } else {
290 /* Init the pool_link so we can safely call list_del when we destroy
291 * the command buffer
292 */
293 list_inithead(&cmd_buffer->pool_link);
294 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
295 }
296
297 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
298
299 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
300 if (!cmd_buffer->cs) {
301 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
302 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
303 }
304
305 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
306
307 list_inithead(&cmd_buffer->upload.list);
308
309 return VK_SUCCESS;
310 }
311
312 static void
313 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
314 {
315 list_del(&cmd_buffer->pool_link);
316
317 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
318 &cmd_buffer->upload.list, list) {
319 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
320 list_del(&up->list);
321 free(up);
322 }
323
324 if (cmd_buffer->upload.upload_bo)
325 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
326 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
327
328 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
329 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
330
331 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
332 }
333
334 static VkResult
335 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
336 {
337 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
338
339 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
340 &cmd_buffer->upload.list, list) {
341 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
342 list_del(&up->list);
343 free(up);
344 }
345
346 cmd_buffer->push_constant_stages = 0;
347 cmd_buffer->scratch_size_per_wave_needed = 0;
348 cmd_buffer->scratch_waves_wanted = 0;
349 cmd_buffer->compute_scratch_size_per_wave_needed = 0;
350 cmd_buffer->compute_scratch_waves_wanted = 0;
351 cmd_buffer->esgs_ring_size_needed = 0;
352 cmd_buffer->gsvs_ring_size_needed = 0;
353 cmd_buffer->tess_rings_needed = false;
354 cmd_buffer->gds_needed = false;
355 cmd_buffer->gds_oa_needed = false;
356 cmd_buffer->sample_positions_needed = false;
357
358 if (cmd_buffer->upload.upload_bo)
359 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
360 cmd_buffer->upload.upload_bo);
361 cmd_buffer->upload.offset = 0;
362
363 cmd_buffer->record_result = VK_SUCCESS;
364
365 memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
366
367 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
368 cmd_buffer->descriptors[i].dirty = 0;
369 cmd_buffer->descriptors[i].valid = 0;
370 cmd_buffer->descriptors[i].push_dirty = false;
371 }
372
373 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
374 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
375 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
376 unsigned fence_offset, eop_bug_offset;
377 void *fence_ptr;
378
379 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
380 &fence_ptr);
381
382 cmd_buffer->gfx9_fence_va =
383 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
384 cmd_buffer->gfx9_fence_va += fence_offset;
385
386 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
387 /* Allocate a buffer for the EOP bug on GFX9. */
388 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
389 &eop_bug_offset, &fence_ptr);
390 cmd_buffer->gfx9_eop_bug_va =
391 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
392 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
393 }
394 }
395
396 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
397
398 return cmd_buffer->record_result;
399 }
400
401 static bool
402 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
403 uint64_t min_needed)
404 {
405 uint64_t new_size;
406 struct radeon_winsys_bo *bo;
407 struct radv_cmd_buffer_upload *upload;
408 struct radv_device *device = cmd_buffer->device;
409
410 new_size = MAX2(min_needed, 16 * 1024);
411 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
412
413 bo = device->ws->buffer_create(device->ws,
414 new_size, 4096,
415 RADEON_DOMAIN_GTT,
416 RADEON_FLAG_CPU_ACCESS|
417 RADEON_FLAG_NO_INTERPROCESS_SHARING |
418 RADEON_FLAG_32BIT,
419 RADV_BO_PRIORITY_UPLOAD_BUFFER);
420
421 if (!bo) {
422 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
423 return false;
424 }
425
426 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
427 if (cmd_buffer->upload.upload_bo) {
428 upload = malloc(sizeof(*upload));
429
430 if (!upload) {
431 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
432 device->ws->buffer_destroy(bo);
433 return false;
434 }
435
436 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
437 list_add(&upload->list, &cmd_buffer->upload.list);
438 }
439
440 cmd_buffer->upload.upload_bo = bo;
441 cmd_buffer->upload.size = new_size;
442 cmd_buffer->upload.offset = 0;
443 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
444
445 if (!cmd_buffer->upload.map) {
446 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
447 return false;
448 }
449
450 return true;
451 }
452
453 bool
454 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
455 unsigned size,
456 unsigned alignment,
457 unsigned *out_offset,
458 void **ptr)
459 {
460 assert(util_is_power_of_two_nonzero(alignment));
461
462 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
463 if (offset + size > cmd_buffer->upload.size) {
464 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
465 return false;
466 offset = 0;
467 }
468
469 *out_offset = offset;
470 *ptr = cmd_buffer->upload.map + offset;
471
472 cmd_buffer->upload.offset = offset + size;
473 return true;
474 }
475
476 bool
477 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
478 unsigned size, unsigned alignment,
479 const void *data, unsigned *out_offset)
480 {
481 uint8_t *ptr;
482
483 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
484 out_offset, (void **)&ptr))
485 return false;
486
487 if (ptr)
488 memcpy(ptr, data, size);
489
490 return true;
491 }
492
493 static void
494 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
495 unsigned count, const uint32_t *data)
496 {
497 struct radeon_cmdbuf *cs = cmd_buffer->cs;
498
499 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
500
501 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
502 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
503 S_370_WR_CONFIRM(1) |
504 S_370_ENGINE_SEL(V_370_ME));
505 radeon_emit(cs, va);
506 radeon_emit(cs, va >> 32);
507 radeon_emit_array(cs, data, count);
508 }
509
510 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
511 {
512 struct radv_device *device = cmd_buffer->device;
513 struct radeon_cmdbuf *cs = cmd_buffer->cs;
514 uint64_t va;
515
516 va = radv_buffer_get_va(device->trace_bo);
517 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
518 va += 4;
519
520 ++cmd_buffer->state.trace_id;
521 radv_emit_write_data_packet(cmd_buffer, va, 1,
522 &cmd_buffer->state.trace_id);
523
524 radeon_check_space(cmd_buffer->device->ws, cs, 2);
525
526 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
527 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
528 }
529
530 static void
531 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
532 enum radv_cmd_flush_bits flags)
533 {
534 if (unlikely(cmd_buffer->device->thread_trace_bo)) {
535 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
536 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_THREAD_TRACE_MARKER) | EVENT_INDEX(0));
537 }
538
539 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
540 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
541 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
542
543 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
544
545 /* Force wait for graphics or compute engines to be idle. */
546 si_cs_emit_cache_flush(cmd_buffer->cs,
547 cmd_buffer->device->physical_device->rad_info.chip_class,
548 &cmd_buffer->gfx9_fence_idx,
549 cmd_buffer->gfx9_fence_va,
550 radv_cmd_buffer_uses_mec(cmd_buffer),
551 flags, cmd_buffer->gfx9_eop_bug_va);
552 }
553
554 if (unlikely(cmd_buffer->device->trace_bo))
555 radv_cmd_buffer_trace_emit(cmd_buffer);
556 }
557
558 static void
559 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
560 struct radv_pipeline *pipeline, enum ring_type ring)
561 {
562 struct radv_device *device = cmd_buffer->device;
563 uint32_t data[2];
564 uint64_t va;
565
566 va = radv_buffer_get_va(device->trace_bo);
567
568 switch (ring) {
569 case RING_GFX:
570 va += 8;
571 break;
572 case RING_COMPUTE:
573 va += 16;
574 break;
575 default:
576 assert(!"invalid ring type");
577 }
578
579 uint64_t pipeline_address = (uintptr_t)pipeline;
580 data[0] = pipeline_address;
581 data[1] = pipeline_address >> 32;
582
583 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
584 }
585
586 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
587 VkPipelineBindPoint bind_point,
588 struct radv_descriptor_set *set,
589 unsigned idx)
590 {
591 struct radv_descriptor_state *descriptors_state =
592 radv_get_descriptors_state(cmd_buffer, bind_point);
593
594 descriptors_state->sets[idx] = set;
595
596 descriptors_state->valid |= (1u << idx); /* active descriptors */
597 descriptors_state->dirty |= (1u << idx);
598 }
599
600 static void
601 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
602 VkPipelineBindPoint bind_point)
603 {
604 struct radv_descriptor_state *descriptors_state =
605 radv_get_descriptors_state(cmd_buffer, bind_point);
606 struct radv_device *device = cmd_buffer->device;
607 uint32_t data[MAX_SETS * 2] = {};
608 uint64_t va;
609 unsigned i;
610 va = radv_buffer_get_va(device->trace_bo) + 24;
611
612 for_each_bit(i, descriptors_state->valid) {
613 struct radv_descriptor_set *set = descriptors_state->sets[i];
614 data[i * 2] = (uint64_t)(uintptr_t)set;
615 data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
616 }
617
618 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
619 }
620
621 struct radv_userdata_info *
622 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
623 gl_shader_stage stage,
624 int idx)
625 {
626 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
627 return &shader->info.user_sgprs_locs.shader_data[idx];
628 }
629
630 static void
631 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
632 struct radv_pipeline *pipeline,
633 gl_shader_stage stage,
634 int idx, uint64_t va)
635 {
636 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
637 uint32_t base_reg = pipeline->user_data_0[stage];
638 if (loc->sgpr_idx == -1)
639 return;
640
641 assert(loc->num_sgprs == 1);
642
643 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
644 base_reg + loc->sgpr_idx * 4, va, false);
645 }
646
647 static void
648 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
649 struct radv_pipeline *pipeline,
650 struct radv_descriptor_state *descriptors_state,
651 gl_shader_stage stage)
652 {
653 struct radv_device *device = cmd_buffer->device;
654 struct radeon_cmdbuf *cs = cmd_buffer->cs;
655 uint32_t sh_base = pipeline->user_data_0[stage];
656 struct radv_userdata_locations *locs =
657 &pipeline->shaders[stage]->info.user_sgprs_locs;
658 unsigned mask = locs->descriptor_sets_enabled;
659
660 mask &= descriptors_state->dirty & descriptors_state->valid;
661
662 while (mask) {
663 int start, count;
664
665 u_bit_scan_consecutive_range(&mask, &start, &count);
666
667 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
668 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
669
670 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
671 for (int i = 0; i < count; i++) {
672 struct radv_descriptor_set *set =
673 descriptors_state->sets[start + i];
674
675 radv_emit_shader_pointer_body(device, cs, set->va, true);
676 }
677 }
678 }
679
680 /**
681 * Convert the user sample locations to hardware sample locations (the values
682 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
683 */
684 static void
685 radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
686 uint32_t x, uint32_t y, VkOffset2D *sample_locs)
687 {
688 uint32_t x_offset = x % state->grid_size.width;
689 uint32_t y_offset = y % state->grid_size.height;
690 uint32_t num_samples = (uint32_t)state->per_pixel;
691 VkSampleLocationEXT *user_locs;
692 uint32_t pixel_offset;
693
694 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
695
696 assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
697 user_locs = &state->locations[pixel_offset];
698
699 for (uint32_t i = 0; i < num_samples; i++) {
700 float shifted_pos_x = user_locs[i].x - 0.5;
701 float shifted_pos_y = user_locs[i].y - 0.5;
702
703 int32_t scaled_pos_x = floorf(shifted_pos_x * 16);
704 int32_t scaled_pos_y = floorf(shifted_pos_y * 16);
705
706 sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
707 sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
708 }
709 }
710
711 /**
712 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
713 * locations.
714 */
715 static void
716 radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
717 uint32_t *sample_locs_pixel)
718 {
719 for (uint32_t i = 0; i < num_samples; i++) {
720 uint32_t sample_reg_idx = i / 4;
721 uint32_t sample_loc_idx = i % 4;
722 int32_t pos_x = sample_locs[i].x;
723 int32_t pos_y = sample_locs[i].y;
724
725 uint32_t shift_x = 8 * sample_loc_idx;
726 uint32_t shift_y = shift_x + 4;
727
728 sample_locs_pixel[sample_reg_idx] |= (pos_x & 0xf) << shift_x;
729 sample_locs_pixel[sample_reg_idx] |= (pos_y & 0xf) << shift_y;
730 }
731 }
732
733 /**
734 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
735 * sample locations.
736 */
737 static uint64_t
738 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer,
739 VkOffset2D *sample_locs,
740 uint32_t num_samples)
741 {
742 uint32_t centroid_priorities[num_samples];
743 uint32_t sample_mask = num_samples - 1;
744 uint32_t distances[num_samples];
745 uint64_t centroid_priority = 0;
746
747 /* Compute the distances from center for each sample. */
748 for (int i = 0; i < num_samples; i++) {
749 distances[i] = (sample_locs[i].x * sample_locs[i].x) +
750 (sample_locs[i].y * sample_locs[i].y);
751 }
752
753 /* Compute the centroid priorities by looking at the distances array. */
754 for (int i = 0; i < num_samples; i++) {
755 uint32_t min_idx = 0;
756
757 for (int j = 1; j < num_samples; j++) {
758 if (distances[j] < distances[min_idx])
759 min_idx = j;
760 }
761
762 centroid_priorities[i] = min_idx;
763 distances[min_idx] = 0xffffffff;
764 }
765
766 /* Compute the final centroid priority. */
767 for (int i = 0; i < 8; i++) {
768 centroid_priority |=
769 centroid_priorities[i & sample_mask] << (i * 4);
770 }
771
772 return centroid_priority << 32 | centroid_priority;
773 }
774
775 /**
776 * Emit the sample locations that are specified with VK_EXT_sample_locations.
777 */
778 static void
779 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
780 {
781 struct radv_sample_locations_state *sample_location =
782 &cmd_buffer->state.dynamic.sample_location;
783 uint32_t num_samples = (uint32_t)sample_location->per_pixel;
784 struct radeon_cmdbuf *cs = cmd_buffer->cs;
785 uint32_t sample_locs_pixel[4][2] = {};
786 VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
787 uint32_t max_sample_dist = 0;
788 uint64_t centroid_priority;
789
790 if (!cmd_buffer->state.dynamic.sample_location.count)
791 return;
792
793 /* Convert the user sample locations to hardware sample locations. */
794 radv_convert_user_sample_locs(sample_location, 0, 0, sample_locs[0]);
795 radv_convert_user_sample_locs(sample_location, 1, 0, sample_locs[1]);
796 radv_convert_user_sample_locs(sample_location, 0, 1, sample_locs[2]);
797 radv_convert_user_sample_locs(sample_location, 1, 1, sample_locs[3]);
798
799 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
800 for (uint32_t i = 0; i < 4; i++) {
801 radv_compute_sample_locs_pixel(num_samples, sample_locs[i],
802 sample_locs_pixel[i]);
803 }
804
805 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
806 centroid_priority =
807 radv_compute_centroid_priority(cmd_buffer, sample_locs[0],
808 num_samples);
809
810 /* Compute the maximum sample distance from the specified locations. */
811 for (unsigned i = 0; i < 4; ++i) {
812 for (uint32_t j = 0; j < num_samples; j++) {
813 VkOffset2D offset = sample_locs[i][j];
814 max_sample_dist = MAX2(max_sample_dist,
815 MAX2(abs(offset.x), abs(offset.y)));
816 }
817 }
818
819 /* Emit the specified user sample locations. */
820 switch (num_samples) {
821 case 2:
822 case 4:
823 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
824 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
825 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
826 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
827 break;
828 case 8:
829 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
830 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
831 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
832 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
833 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs_pixel[0][1]);
834 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs_pixel[1][1]);
835 radeon_set_context_reg(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs_pixel[2][1]);
836 radeon_set_context_reg(cs, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs_pixel[3][1]);
837 break;
838 default:
839 unreachable("invalid number of samples");
840 }
841
842 /* Emit the maximum sample distance and the centroid priority. */
843 radeon_set_context_reg_rmw(cs, R_028BE0_PA_SC_AA_CONFIG,
844 S_028BE0_MAX_SAMPLE_DIST(max_sample_dist),
845 ~C_028BE0_MAX_SAMPLE_DIST);
846
847 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
848 radeon_emit(cs, centroid_priority);
849 radeon_emit(cs, centroid_priority >> 32);
850
851 /* GFX9: Flush DFSM when the AA mode changes. */
852 if (cmd_buffer->device->dfsm_allowed) {
853 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
854 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
855 }
856
857 cmd_buffer->state.context_roll_without_scissor_emitted = true;
858 }
859
860 static void
861 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
862 struct radv_pipeline *pipeline,
863 gl_shader_stage stage,
864 int idx, int count, uint32_t *values)
865 {
866 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
867 uint32_t base_reg = pipeline->user_data_0[stage];
868 if (loc->sgpr_idx == -1)
869 return;
870
871 assert(loc->num_sgprs == count);
872
873 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
874 radeon_emit_array(cmd_buffer->cs, values, count);
875 }
876
877 static void
878 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
879 struct radv_pipeline *pipeline)
880 {
881 int num_samples = pipeline->graphics.ms.num_samples;
882 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
883
884 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.needs_sample_positions)
885 cmd_buffer->sample_positions_needed = true;
886
887 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
888 return;
889
890 radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
891
892 cmd_buffer->state.context_roll_without_scissor_emitted = true;
893 }
894
895 static void
896 radv_update_binning_state(struct radv_cmd_buffer *cmd_buffer,
897 struct radv_pipeline *pipeline)
898 {
899 const struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
900
901
902 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
903 return;
904
905 if (old_pipeline &&
906 old_pipeline->graphics.binning.pa_sc_binner_cntl_0 == pipeline->graphics.binning.pa_sc_binner_cntl_0 &&
907 old_pipeline->graphics.binning.db_dfsm_control == pipeline->graphics.binning.db_dfsm_control)
908 return;
909
910 bool binning_flush = false;
911 if (cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA12 ||
912 cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA20 ||
913 cmd_buffer->device->physical_device->rad_info.family == CHIP_RAVEN2 ||
914 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
915 binning_flush = !old_pipeline ||
916 G_028C44_BINNING_MODE(old_pipeline->graphics.binning.pa_sc_binner_cntl_0) !=
917 G_028C44_BINNING_MODE(pipeline->graphics.binning.pa_sc_binner_cntl_0);
918 }
919
920 radeon_set_context_reg(cmd_buffer->cs, R_028C44_PA_SC_BINNER_CNTL_0,
921 pipeline->graphics.binning.pa_sc_binner_cntl_0 |
922 S_028C44_FLUSH_ON_BINNING_TRANSITION(!!binning_flush));
923
924 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
925 radeon_set_context_reg(cmd_buffer->cs, R_028038_DB_DFSM_CONTROL,
926 pipeline->graphics.binning.db_dfsm_control);
927 } else {
928 radeon_set_context_reg(cmd_buffer->cs, R_028060_DB_DFSM_CONTROL,
929 pipeline->graphics.binning.db_dfsm_control);
930 }
931
932 cmd_buffer->state.context_roll_without_scissor_emitted = true;
933 }
934
935
936 static void
937 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
938 struct radv_shader_variant *shader)
939 {
940 uint64_t va;
941
942 if (!shader)
943 return;
944
945 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
946
947 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
948 }
949
950 static void
951 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
952 struct radv_pipeline *pipeline,
953 bool vertex_stage_only)
954 {
955 struct radv_cmd_state *state = &cmd_buffer->state;
956 uint32_t mask = state->prefetch_L2_mask;
957
958 if (vertex_stage_only) {
959 /* Fast prefetch path for starting draws as soon as possible.
960 */
961 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
962 RADV_PREFETCH_VBO_DESCRIPTORS);
963 }
964
965 if (mask & RADV_PREFETCH_VS)
966 radv_emit_shader_prefetch(cmd_buffer,
967 pipeline->shaders[MESA_SHADER_VERTEX]);
968
969 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
970 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
971
972 if (mask & RADV_PREFETCH_TCS)
973 radv_emit_shader_prefetch(cmd_buffer,
974 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
975
976 if (mask & RADV_PREFETCH_TES)
977 radv_emit_shader_prefetch(cmd_buffer,
978 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
979
980 if (mask & RADV_PREFETCH_GS) {
981 radv_emit_shader_prefetch(cmd_buffer,
982 pipeline->shaders[MESA_SHADER_GEOMETRY]);
983 if (radv_pipeline_has_gs_copy_shader(pipeline))
984 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
985 }
986
987 if (mask & RADV_PREFETCH_PS)
988 radv_emit_shader_prefetch(cmd_buffer,
989 pipeline->shaders[MESA_SHADER_FRAGMENT]);
990
991 state->prefetch_L2_mask &= ~mask;
992 }
993
994 static void
995 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
996 {
997 if (!cmd_buffer->device->physical_device->rad_info.rbplus_allowed)
998 return;
999
1000 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1001 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1002
1003 unsigned sx_ps_downconvert = 0;
1004 unsigned sx_blend_opt_epsilon = 0;
1005 unsigned sx_blend_opt_control = 0;
1006
1007 if (!cmd_buffer->state.attachments || !subpass)
1008 return;
1009
1010 for (unsigned i = 0; i < subpass->color_count; ++i) {
1011 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1012 /* We don't set the DISABLE bits, because the HW can't have holes,
1013 * so the SPI color format is set to 32-bit 1-component. */
1014 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1015 continue;
1016 }
1017
1018 int idx = subpass->color_attachments[i].attachment;
1019 struct radv_color_buffer_info *cb = &cmd_buffer->state.attachments[idx].cb;
1020
1021 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
1022 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
1023 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
1024 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
1025
1026 bool has_alpha, has_rgb;
1027
1028 /* Set if RGB and A are present. */
1029 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
1030
1031 if (format == V_028C70_COLOR_8 ||
1032 format == V_028C70_COLOR_16 ||
1033 format == V_028C70_COLOR_32)
1034 has_rgb = !has_alpha;
1035 else
1036 has_rgb = true;
1037
1038 /* Check the colormask and export format. */
1039 if (!(colormask & 0x7))
1040 has_rgb = false;
1041 if (!(colormask & 0x8))
1042 has_alpha = false;
1043
1044 if (spi_format == V_028714_SPI_SHADER_ZERO) {
1045 has_rgb = false;
1046 has_alpha = false;
1047 }
1048
1049 /* Disable value checking for disabled channels. */
1050 if (!has_rgb)
1051 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1052 if (!has_alpha)
1053 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1054
1055 /* Enable down-conversion for 32bpp and smaller formats. */
1056 switch (format) {
1057 case V_028C70_COLOR_8:
1058 case V_028C70_COLOR_8_8:
1059 case V_028C70_COLOR_8_8_8_8:
1060 /* For 1 and 2-channel formats, use the superset thereof. */
1061 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
1062 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1063 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1064 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
1065 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
1066 }
1067 break;
1068
1069 case V_028C70_COLOR_5_6_5:
1070 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1071 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
1072 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
1073 }
1074 break;
1075
1076 case V_028C70_COLOR_1_5_5_5:
1077 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1078 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
1079 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
1080 }
1081 break;
1082
1083 case V_028C70_COLOR_4_4_4_4:
1084 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1085 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
1086 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
1087 }
1088 break;
1089
1090 case V_028C70_COLOR_32:
1091 if (swap == V_028C70_SWAP_STD &&
1092 spi_format == V_028714_SPI_SHADER_32_R)
1093 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1094 else if (swap == V_028C70_SWAP_ALT_REV &&
1095 spi_format == V_028714_SPI_SHADER_32_AR)
1096 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
1097 break;
1098
1099 case V_028C70_COLOR_16:
1100 case V_028C70_COLOR_16_16:
1101 /* For 1-channel formats, use the superset thereof. */
1102 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
1103 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
1104 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1105 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1106 if (swap == V_028C70_SWAP_STD ||
1107 swap == V_028C70_SWAP_STD_REV)
1108 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
1109 else
1110 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
1111 }
1112 break;
1113
1114 case V_028C70_COLOR_10_11_11:
1115 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1116 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
1117 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
1118 }
1119 break;
1120
1121 case V_028C70_COLOR_2_10_10_10:
1122 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1123 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
1124 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
1125 }
1126 break;
1127 }
1128 }
1129
1130 /* Do not set the DISABLE bits for the unused attachments, as that
1131 * breaks dual source blending in SkQP and does not seem to improve
1132 * performance. */
1133
1134 if (sx_ps_downconvert == cmd_buffer->state.last_sx_ps_downconvert &&
1135 sx_blend_opt_epsilon == cmd_buffer->state.last_sx_blend_opt_epsilon &&
1136 sx_blend_opt_control == cmd_buffer->state.last_sx_blend_opt_control)
1137 return;
1138
1139 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
1140 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
1141 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
1142 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
1143
1144 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1145
1146 cmd_buffer->state.last_sx_ps_downconvert = sx_ps_downconvert;
1147 cmd_buffer->state.last_sx_blend_opt_epsilon = sx_blend_opt_epsilon;
1148 cmd_buffer->state.last_sx_blend_opt_control = sx_blend_opt_control;
1149 }
1150
1151 static void
1152 radv_emit_batch_break_on_new_ps(struct radv_cmd_buffer *cmd_buffer)
1153 {
1154 if (!cmd_buffer->device->pbb_allowed)
1155 return;
1156
1157 struct radv_binning_settings settings =
1158 radv_get_binning_settings(cmd_buffer->device->physical_device);
1159 bool break_for_new_ps =
1160 (!cmd_buffer->state.emitted_pipeline ||
1161 cmd_buffer->state.emitted_pipeline->shaders[MESA_SHADER_FRAGMENT] !=
1162 cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT]) &&
1163 (settings.context_states_per_bin > 1 ||
1164 settings.persistent_states_per_bin > 1);
1165 bool break_for_new_cb_target_mask =
1166 (!cmd_buffer->state.emitted_pipeline ||
1167 cmd_buffer->state.emitted_pipeline->graphics.cb_target_mask !=
1168 cmd_buffer->state.pipeline->graphics.cb_target_mask) &&
1169 settings.context_states_per_bin > 1;
1170
1171 if (!break_for_new_ps && !break_for_new_cb_target_mask)
1172 return;
1173
1174 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1175 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1176 }
1177
1178 static void
1179 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1180 {
1181 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1182
1183 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1184 return;
1185
1186 radv_update_multisample_state(cmd_buffer, pipeline);
1187 radv_update_binning_state(cmd_buffer, pipeline);
1188
1189 cmd_buffer->scratch_size_per_wave_needed = MAX2(cmd_buffer->scratch_size_per_wave_needed,
1190 pipeline->scratch_bytes_per_wave);
1191 cmd_buffer->scratch_waves_wanted = MAX2(cmd_buffer->scratch_waves_wanted,
1192 pipeline->max_waves);
1193
1194 if (!cmd_buffer->state.emitted_pipeline ||
1195 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1196 pipeline->graphics.can_use_guardband)
1197 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1198
1199 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
1200
1201 if (!cmd_buffer->state.emitted_pipeline ||
1202 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
1203 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
1204 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
1205 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
1206 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
1207 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1208 }
1209
1210 radv_emit_batch_break_on_new_ps(cmd_buffer);
1211
1212 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
1213 if (!pipeline->shaders[i])
1214 continue;
1215
1216 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1217 pipeline->shaders[i]->bo);
1218 }
1219
1220 if (radv_pipeline_has_gs_copy_shader(pipeline))
1221 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1222 pipeline->gs_copy_shader->bo);
1223
1224 if (unlikely(cmd_buffer->device->trace_bo))
1225 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1226
1227 cmd_buffer->state.emitted_pipeline = pipeline;
1228
1229 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1230 }
1231
1232 static void
1233 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1234 {
1235 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1236 cmd_buffer->state.dynamic.viewport.viewports);
1237 }
1238
1239 static void
1240 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1241 {
1242 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1243
1244 si_write_scissors(cmd_buffer->cs, 0, count,
1245 cmd_buffer->state.dynamic.scissor.scissors,
1246 cmd_buffer->state.dynamic.viewport.viewports,
1247 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1248
1249 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1250 }
1251
1252 static void
1253 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1254 {
1255 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1256 return;
1257
1258 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1259 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1260 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1261 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1262 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1263 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1264 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1265 }
1266 }
1267
1268 static void
1269 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1270 {
1271 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1272
1273 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1274 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1275 }
1276
1277 static void
1278 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1279 {
1280 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1281
1282 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1283 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1284 }
1285
1286 static void
1287 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1288 {
1289 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1290
1291 radeon_set_context_reg_seq(cmd_buffer->cs,
1292 R_028430_DB_STENCILREFMASK, 2);
1293 radeon_emit(cmd_buffer->cs,
1294 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1295 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1296 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1297 S_028430_STENCILOPVAL(1));
1298 radeon_emit(cmd_buffer->cs,
1299 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1300 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1301 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1302 S_028434_STENCILOPVAL_BF(1));
1303 }
1304
1305 static void
1306 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1307 {
1308 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1309
1310 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1311 fui(d->depth_bounds.min));
1312 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1313 fui(d->depth_bounds.max));
1314 }
1315
1316 static void
1317 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1318 {
1319 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1320 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1321 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1322
1323
1324 radeon_set_context_reg_seq(cmd_buffer->cs,
1325 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1326 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1327 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1328 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1329 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1330 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1331 }
1332
1333 static void
1334 radv_emit_line_stipple(struct radv_cmd_buffer *cmd_buffer)
1335 {
1336 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1337 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1338 uint32_t auto_reset_cntl = 1;
1339
1340 if (pipeline->graphics.topology == VK_PRIMITIVE_TOPOLOGY_LINE_STRIP)
1341 auto_reset_cntl = 2;
1342
1343 radeon_set_context_reg(cmd_buffer->cs, R_028A0C_PA_SC_LINE_STIPPLE,
1344 S_028A0C_LINE_PATTERN(d->line_stipple.pattern) |
1345 S_028A0C_REPEAT_COUNT(d->line_stipple.factor - 1) |
1346 S_028A0C_AUTO_RESET_CNTL(auto_reset_cntl));
1347 }
1348
1349 static void
1350 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1351 int index,
1352 struct radv_color_buffer_info *cb,
1353 struct radv_image_view *iview,
1354 VkImageLayout layout,
1355 bool in_render_loop)
1356 {
1357 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
1358 uint32_t cb_color_info = cb->cb_color_info;
1359 struct radv_image *image = iview->image;
1360
1361 if (!radv_layout_dcc_compressed(cmd_buffer->device, image, layout, in_render_loop,
1362 radv_image_queue_family_mask(image,
1363 cmd_buffer->queue_family_index,
1364 cmd_buffer->queue_family_index))) {
1365 cb_color_info &= C_028C70_DCC_ENABLE;
1366 }
1367
1368 if (radv_image_is_tc_compat_cmask(image) &&
1369 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1370 radv_is_dcc_decompress_pipeline(cmd_buffer))) {
1371 /* If this bit is set, the FMASK decompression operation
1372 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1373 */
1374 cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
1375 }
1376
1377 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1378 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1379 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1380 radeon_emit(cmd_buffer->cs, 0);
1381 radeon_emit(cmd_buffer->cs, 0);
1382 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1383 radeon_emit(cmd_buffer->cs, cb_color_info);
1384 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1385 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1386 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1387 radeon_emit(cmd_buffer->cs, 0);
1388 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1389 radeon_emit(cmd_buffer->cs, 0);
1390
1391 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 1);
1392 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1393
1394 radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4,
1395 cb->cb_color_base >> 32);
1396 radeon_set_context_reg(cmd_buffer->cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + index * 4,
1397 cb->cb_color_cmask >> 32);
1398 radeon_set_context_reg(cmd_buffer->cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + index * 4,
1399 cb->cb_color_fmask >> 32);
1400 radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4,
1401 cb->cb_dcc_base >> 32);
1402 radeon_set_context_reg(cmd_buffer->cs, R_028EC0_CB_COLOR0_ATTRIB2 + index * 4,
1403 cb->cb_color_attrib2);
1404 radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4,
1405 cb->cb_color_attrib3);
1406 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1407 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1408 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1409 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1410 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1411 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1412 radeon_emit(cmd_buffer->cs, cb_color_info);
1413 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1414 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1415 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1416 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1417 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1418 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1419
1420 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1421 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1422 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1423
1424 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1425 cb->cb_mrt_epitch);
1426 } else {
1427 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1428 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1429 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1430 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1431 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1432 radeon_emit(cmd_buffer->cs, cb_color_info);
1433 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1434 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1435 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1436 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1437 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1438 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1439
1440 if (is_vi) { /* DCC BASE */
1441 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1442 }
1443 }
1444
1445 if (radv_dcc_enabled(image, iview->base_mip)) {
1446 /* Drawing with DCC enabled also compresses colorbuffers. */
1447 VkImageSubresourceRange range = {
1448 .aspectMask = iview->aspect_mask,
1449 .baseMipLevel = iview->base_mip,
1450 .levelCount = iview->level_count,
1451 .baseArrayLayer = iview->base_layer,
1452 .layerCount = iview->layer_count,
1453 };
1454
1455 radv_update_dcc_metadata(cmd_buffer, image, &range, true);
1456 }
1457 }
1458
1459 static void
1460 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1461 struct radv_ds_buffer_info *ds,
1462 const struct radv_image_view *iview,
1463 VkImageLayout layout,
1464 bool in_render_loop, bool requires_cond_exec)
1465 {
1466 const struct radv_image *image = iview->image;
1467 uint32_t db_z_info = ds->db_z_info;
1468 uint32_t db_z_info_reg;
1469
1470 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug ||
1471 !radv_image_is_tc_compat_htile(image))
1472 return;
1473
1474 if (!radv_layout_is_htile_compressed(image, layout, in_render_loop,
1475 radv_image_queue_family_mask(image,
1476 cmd_buffer->queue_family_index,
1477 cmd_buffer->queue_family_index))) {
1478 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1479 }
1480
1481 db_z_info &= C_028040_ZRANGE_PRECISION;
1482
1483 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1484 db_z_info_reg = R_028038_DB_Z_INFO;
1485 } else {
1486 db_z_info_reg = R_028040_DB_Z_INFO;
1487 }
1488
1489 /* When we don't know the last fast clear value we need to emit a
1490 * conditional packet that will eventually skip the following
1491 * SET_CONTEXT_REG packet.
1492 */
1493 if (requires_cond_exec) {
1494 uint64_t va = radv_get_tc_compat_zrange_va(image, iview->base_mip);
1495
1496 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1497 radeon_emit(cmd_buffer->cs, va);
1498 radeon_emit(cmd_buffer->cs, va >> 32);
1499 radeon_emit(cmd_buffer->cs, 0);
1500 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1501 }
1502
1503 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1504 }
1505
1506 static void
1507 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1508 struct radv_ds_buffer_info *ds,
1509 struct radv_image_view *iview,
1510 VkImageLayout layout,
1511 bool in_render_loop)
1512 {
1513 const struct radv_image *image = iview->image;
1514 uint32_t db_z_info = ds->db_z_info;
1515 uint32_t db_stencil_info = ds->db_stencil_info;
1516
1517 if (!radv_layout_is_htile_compressed(image, layout, in_render_loop,
1518 radv_image_queue_family_mask(image,
1519 cmd_buffer->queue_family_index,
1520 cmd_buffer->queue_family_index))) {
1521 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1522 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1523 }
1524
1525 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1526 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1527
1528 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1529 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1530 radeon_set_context_reg(cmd_buffer->cs, R_02801C_DB_DEPTH_SIZE_XY, ds->db_depth_size);
1531
1532 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 7);
1533 radeon_emit(cmd_buffer->cs, S_02803C_RESOURCE_LEVEL(1));
1534 radeon_emit(cmd_buffer->cs, db_z_info);
1535 radeon_emit(cmd_buffer->cs, db_stencil_info);
1536 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1537 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1538 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1539 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1540
1541 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_READ_BASE_HI, 5);
1542 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1543 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1544 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1545 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1546 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1547 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1548 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1549 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1550 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1551 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1552
1553 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1554 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1555 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1556 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1557 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1558 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1559 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1560 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1561 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1562 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1563 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1564
1565 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1566 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1567 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1568 } else {
1569 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1570
1571 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1572 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1573 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1574 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1575 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1576 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1577 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1578 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1579 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1580 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1581
1582 }
1583
1584 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1585 radv_update_zrange_precision(cmd_buffer, ds, iview, layout,
1586 in_render_loop, true);
1587
1588 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1589 ds->pa_su_poly_offset_db_fmt_cntl);
1590 }
1591
1592 /**
1593 * Update the fast clear depth/stencil values if the image is bound as a
1594 * depth/stencil buffer.
1595 */
1596 static void
1597 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1598 const struct radv_image_view *iview,
1599 VkClearDepthStencilValue ds_clear_value,
1600 VkImageAspectFlags aspects)
1601 {
1602 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1603 const struct radv_image *image = iview->image;
1604 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1605 uint32_t att_idx;
1606
1607 if (!cmd_buffer->state.attachments || !subpass)
1608 return;
1609
1610 if (!subpass->depth_stencil_attachment)
1611 return;
1612
1613 att_idx = subpass->depth_stencil_attachment->attachment;
1614 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1615 return;
1616
1617 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1618 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1619 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1620 radeon_emit(cs, ds_clear_value.stencil);
1621 radeon_emit(cs, fui(ds_clear_value.depth));
1622 } else if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1623 radeon_set_context_reg_seq(cs, R_02802C_DB_DEPTH_CLEAR, 1);
1624 radeon_emit(cs, fui(ds_clear_value.depth));
1625 } else {
1626 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1627 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 1);
1628 radeon_emit(cs, ds_clear_value.stencil);
1629 }
1630
1631 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1632 * only needed when clearing Z to 0.0.
1633 */
1634 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1635 ds_clear_value.depth == 0.0) {
1636 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1637 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
1638
1639 radv_update_zrange_precision(cmd_buffer, &cmd_buffer->state.attachments[att_idx].ds,
1640 iview, layout, in_render_loop, false);
1641 }
1642
1643 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1644 }
1645
1646 /**
1647 * Set the clear depth/stencil values to the image's metadata.
1648 */
1649 static void
1650 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1651 struct radv_image *image,
1652 const VkImageSubresourceRange *range,
1653 VkClearDepthStencilValue ds_clear_value,
1654 VkImageAspectFlags aspects)
1655 {
1656 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1657 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel);
1658 uint32_t level_count = radv_get_levelCount(image, range);
1659
1660 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1661 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1662 /* Use the fastest way when both aspects are used. */
1663 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + 2 * level_count, cmd_buffer->state.predicating));
1664 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1665 S_370_WR_CONFIRM(1) |
1666 S_370_ENGINE_SEL(V_370_PFP));
1667 radeon_emit(cs, va);
1668 radeon_emit(cs, va >> 32);
1669
1670 for (uint32_t l = 0; l < level_count; l++) {
1671 radeon_emit(cs, ds_clear_value.stencil);
1672 radeon_emit(cs, fui(ds_clear_value.depth));
1673 }
1674 } else {
1675 /* Otherwise we need one WRITE_DATA packet per level. */
1676 for (uint32_t l = 0; l < level_count; l++) {
1677 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel + l);
1678 unsigned value;
1679
1680 if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1681 value = fui(ds_clear_value.depth);
1682 va += 4;
1683 } else {
1684 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1685 value = ds_clear_value.stencil;
1686 }
1687
1688 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1689 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1690 S_370_WR_CONFIRM(1) |
1691 S_370_ENGINE_SEL(V_370_PFP));
1692 radeon_emit(cs, va);
1693 radeon_emit(cs, va >> 32);
1694 radeon_emit(cs, value);
1695 }
1696 }
1697 }
1698
1699 /**
1700 * Update the TC-compat metadata value for this image.
1701 */
1702 static void
1703 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1704 struct radv_image *image,
1705 const VkImageSubresourceRange *range,
1706 uint32_t value)
1707 {
1708 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1709
1710 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug)
1711 return;
1712
1713 uint64_t va = radv_get_tc_compat_zrange_va(image, range->baseMipLevel);
1714 uint32_t level_count = radv_get_levelCount(image, range);
1715
1716 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + level_count, cmd_buffer->state.predicating));
1717 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1718 S_370_WR_CONFIRM(1) |
1719 S_370_ENGINE_SEL(V_370_PFP));
1720 radeon_emit(cs, va);
1721 radeon_emit(cs, va >> 32);
1722
1723 for (uint32_t l = 0; l < level_count; l++)
1724 radeon_emit(cs, value);
1725 }
1726
1727 static void
1728 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1729 const struct radv_image_view *iview,
1730 VkClearDepthStencilValue ds_clear_value)
1731 {
1732 VkImageSubresourceRange range = {
1733 .aspectMask = iview->aspect_mask,
1734 .baseMipLevel = iview->base_mip,
1735 .levelCount = iview->level_count,
1736 .baseArrayLayer = iview->base_layer,
1737 .layerCount = iview->layer_count,
1738 };
1739 uint32_t cond_val;
1740
1741 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1742 * depth clear value is 0.0f.
1743 */
1744 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1745
1746 radv_set_tc_compat_zrange_metadata(cmd_buffer, iview->image, &range,
1747 cond_val);
1748 }
1749
1750 /**
1751 * Update the clear depth/stencil values for this image.
1752 */
1753 void
1754 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1755 const struct radv_image_view *iview,
1756 VkClearDepthStencilValue ds_clear_value,
1757 VkImageAspectFlags aspects)
1758 {
1759 VkImageSubresourceRange range = {
1760 .aspectMask = iview->aspect_mask,
1761 .baseMipLevel = iview->base_mip,
1762 .levelCount = iview->level_count,
1763 .baseArrayLayer = iview->base_layer,
1764 .layerCount = iview->layer_count,
1765 };
1766 struct radv_image *image = iview->image;
1767
1768 assert(radv_image_has_htile(image));
1769
1770 radv_set_ds_clear_metadata(cmd_buffer, iview->image, &range,
1771 ds_clear_value, aspects);
1772
1773 if (radv_image_is_tc_compat_htile(image) &&
1774 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1775 radv_update_tc_compat_zrange_metadata(cmd_buffer, iview,
1776 ds_clear_value);
1777 }
1778
1779 radv_update_bound_fast_clear_ds(cmd_buffer, iview, ds_clear_value,
1780 aspects);
1781 }
1782
1783 /**
1784 * Load the clear depth/stencil values from the image's metadata.
1785 */
1786 static void
1787 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1788 const struct radv_image_view *iview)
1789 {
1790 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1791 const struct radv_image *image = iview->image;
1792 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1793 uint64_t va = radv_get_ds_clear_value_va(image, iview->base_mip);
1794 unsigned reg_offset = 0, reg_count = 0;
1795
1796 if (!radv_image_has_htile(image))
1797 return;
1798
1799 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1800 ++reg_count;
1801 } else {
1802 ++reg_offset;
1803 va += 4;
1804 }
1805 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1806 ++reg_count;
1807
1808 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1809
1810 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
1811 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1812 radeon_emit(cs, va);
1813 radeon_emit(cs, va >> 32);
1814 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1815 radeon_emit(cs, reg_count);
1816 } else {
1817 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1818 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1819 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1820 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1821 radeon_emit(cs, va);
1822 radeon_emit(cs, va >> 32);
1823 radeon_emit(cs, reg >> 2);
1824 radeon_emit(cs, 0);
1825
1826 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1827 radeon_emit(cs, 0);
1828 }
1829 }
1830
1831 /*
1832 * With DCC some colors don't require CMASK elimination before being
1833 * used as a texture. This sets a predicate value to determine if the
1834 * cmask eliminate is required.
1835 */
1836 void
1837 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1838 struct radv_image *image,
1839 const VkImageSubresourceRange *range, bool value)
1840 {
1841 uint64_t pred_val = value;
1842 uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
1843 uint32_t level_count = radv_get_levelCount(image, range);
1844 uint32_t count = 2 * level_count;
1845
1846 assert(radv_dcc_enabled(image, range->baseMipLevel));
1847
1848 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1849 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1850 S_370_WR_CONFIRM(1) |
1851 S_370_ENGINE_SEL(V_370_PFP));
1852 radeon_emit(cmd_buffer->cs, va);
1853 radeon_emit(cmd_buffer->cs, va >> 32);
1854
1855 for (uint32_t l = 0; l < level_count; l++) {
1856 radeon_emit(cmd_buffer->cs, pred_val);
1857 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1858 }
1859 }
1860
1861 /**
1862 * Update the DCC predicate to reflect the compression state.
1863 */
1864 void
1865 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1866 struct radv_image *image,
1867 const VkImageSubresourceRange *range, bool value)
1868 {
1869 uint64_t pred_val = value;
1870 uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
1871 uint32_t level_count = radv_get_levelCount(image, range);
1872 uint32_t count = 2 * level_count;
1873
1874 assert(radv_dcc_enabled(image, range->baseMipLevel));
1875
1876 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1877 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1878 S_370_WR_CONFIRM(1) |
1879 S_370_ENGINE_SEL(V_370_PFP));
1880 radeon_emit(cmd_buffer->cs, va);
1881 radeon_emit(cmd_buffer->cs, va >> 32);
1882
1883 for (uint32_t l = 0; l < level_count; l++) {
1884 radeon_emit(cmd_buffer->cs, pred_val);
1885 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1886 }
1887 }
1888
1889 /**
1890 * Update the fast clear color values if the image is bound as a color buffer.
1891 */
1892 static void
1893 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1894 struct radv_image *image,
1895 int cb_idx,
1896 uint32_t color_values[2])
1897 {
1898 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1899 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1900 uint32_t att_idx;
1901
1902 if (!cmd_buffer->state.attachments || !subpass)
1903 return;
1904
1905 att_idx = subpass->color_attachments[cb_idx].attachment;
1906 if (att_idx == VK_ATTACHMENT_UNUSED)
1907 return;
1908
1909 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1910 return;
1911
1912 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1913 radeon_emit(cs, color_values[0]);
1914 radeon_emit(cs, color_values[1]);
1915
1916 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1917 }
1918
1919 /**
1920 * Set the clear color values to the image's metadata.
1921 */
1922 static void
1923 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1924 struct radv_image *image,
1925 const VkImageSubresourceRange *range,
1926 uint32_t color_values[2])
1927 {
1928 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1929 uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
1930 uint32_t level_count = radv_get_levelCount(image, range);
1931 uint32_t count = 2 * level_count;
1932
1933 assert(radv_image_has_cmask(image) ||
1934 radv_dcc_enabled(image, range->baseMipLevel));
1935
1936 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
1937 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1938 S_370_WR_CONFIRM(1) |
1939 S_370_ENGINE_SEL(V_370_PFP));
1940 radeon_emit(cs, va);
1941 radeon_emit(cs, va >> 32);
1942
1943 for (uint32_t l = 0; l < level_count; l++) {
1944 radeon_emit(cs, color_values[0]);
1945 radeon_emit(cs, color_values[1]);
1946 }
1947 }
1948
1949 /**
1950 * Update the clear color values for this image.
1951 */
1952 void
1953 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1954 const struct radv_image_view *iview,
1955 int cb_idx,
1956 uint32_t color_values[2])
1957 {
1958 struct radv_image *image = iview->image;
1959 VkImageSubresourceRange range = {
1960 .aspectMask = iview->aspect_mask,
1961 .baseMipLevel = iview->base_mip,
1962 .levelCount = iview->level_count,
1963 .baseArrayLayer = iview->base_layer,
1964 .layerCount = iview->layer_count,
1965 };
1966
1967 assert(radv_image_has_cmask(image) ||
1968 radv_dcc_enabled(image, iview->base_mip));
1969
1970 radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
1971
1972 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1973 color_values);
1974 }
1975
1976 /**
1977 * Load the clear color values from the image's metadata.
1978 */
1979 static void
1980 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1981 struct radv_image_view *iview,
1982 int cb_idx)
1983 {
1984 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1985 struct radv_image *image = iview->image;
1986 uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
1987
1988 if (!radv_image_has_cmask(image) &&
1989 !radv_dcc_enabled(image, iview->base_mip))
1990 return;
1991
1992 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1993
1994 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
1995 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1996 radeon_emit(cs, va);
1997 radeon_emit(cs, va >> 32);
1998 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1999 radeon_emit(cs, 2);
2000 } else {
2001 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
2002 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2003 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2004 COPY_DATA_COUNT_SEL);
2005 radeon_emit(cs, va);
2006 radeon_emit(cs, va >> 32);
2007 radeon_emit(cs, reg >> 2);
2008 radeon_emit(cs, 0);
2009
2010 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
2011 radeon_emit(cs, 0);
2012 }
2013 }
2014
2015 static void
2016 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
2017 {
2018 int i;
2019 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
2020 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2021
2022 /* this may happen for inherited secondary recording */
2023 if (!framebuffer)
2024 return;
2025
2026 for (i = 0; i < 8; ++i) {
2027 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
2028 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2029 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2030 continue;
2031 }
2032
2033 int idx = subpass->color_attachments[i].attachment;
2034 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
2035 VkImageLayout layout = subpass->color_attachments[i].layout;
2036 bool in_render_loop = subpass->color_attachments[i].in_render_loop;
2037
2038 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, iview->bo);
2039
2040 assert(iview->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
2041 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
2042 radv_emit_fb_color_state(cmd_buffer, i, &cmd_buffer->state.attachments[idx].cb, iview, layout, in_render_loop);
2043
2044 radv_load_color_clear_metadata(cmd_buffer, iview, i);
2045 }
2046
2047 if (subpass->depth_stencil_attachment) {
2048 int idx = subpass->depth_stencil_attachment->attachment;
2049 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
2050 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
2051 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
2052 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, cmd_buffer->state.attachments[idx].iview->bo);
2053
2054 radv_emit_fb_ds_state(cmd_buffer, &cmd_buffer->state.attachments[idx].ds, iview, layout, in_render_loop);
2055
2056 if (cmd_buffer->state.attachments[idx].ds.offset_scale != cmd_buffer->state.offset_scale) {
2057 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2058 cmd_buffer->state.offset_scale = cmd_buffer->state.attachments[idx].ds.offset_scale;
2059 }
2060 radv_load_ds_clear_metadata(cmd_buffer, iview);
2061 } else {
2062 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9)
2063 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
2064 else
2065 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
2066
2067 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
2068 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
2069 }
2070 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2071 S_028208_BR_X(framebuffer->width) |
2072 S_028208_BR_Y(framebuffer->height));
2073
2074 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
2075 bool disable_constant_encode =
2076 cmd_buffer->device->physical_device->rad_info.has_dcc_constant_encode;
2077 enum chip_class chip_class =
2078 cmd_buffer->device->physical_device->rad_info.chip_class;
2079 uint8_t watermark = chip_class >= GFX10 ? 6 : 4;
2080
2081 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
2082 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class <= GFX9) |
2083 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
2084 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
2085 }
2086
2087 if (cmd_buffer->device->dfsm_allowed) {
2088 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2089 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
2090 }
2091
2092 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
2093 }
2094
2095 static void
2096 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer, bool indirect)
2097 {
2098 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2099 struct radv_cmd_state *state = &cmd_buffer->state;
2100
2101 if (state->index_type != state->last_index_type) {
2102 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2103 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2104 cs, R_03090C_VGT_INDEX_TYPE,
2105 2, state->index_type);
2106 } else {
2107 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2108 radeon_emit(cs, state->index_type);
2109 }
2110
2111 state->last_index_type = state->index_type;
2112 }
2113
2114 /* For the direct indexed draws we use DRAW_INDEX_2, which includes
2115 * the index_va and max_index_count already. */
2116 if (!indirect)
2117 return;
2118
2119 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2120 radeon_emit(cs, state->index_va);
2121 radeon_emit(cs, state->index_va >> 32);
2122
2123 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2124 radeon_emit(cs, state->max_index_count);
2125
2126 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
2127 }
2128
2129 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
2130 {
2131 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
2132 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2133 uint32_t pa_sc_mode_cntl_1 =
2134 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
2135 uint32_t db_count_control;
2136
2137 if(!cmd_buffer->state.active_occlusion_queries) {
2138 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2139 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2140 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2141 has_perfect_queries) {
2142 /* Re-enable out-of-order rasterization if the
2143 * bound pipeline supports it and if it's has
2144 * been disabled before starting any perfect
2145 * occlusion queries.
2146 */
2147 radeon_set_context_reg(cmd_buffer->cs,
2148 R_028A4C_PA_SC_MODE_CNTL_1,
2149 pa_sc_mode_cntl_1);
2150 }
2151 }
2152 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
2153 } else {
2154 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2155 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
2156 bool gfx10_perfect = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10 && has_perfect_queries;
2157
2158 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2159 db_count_control =
2160 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
2161 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
2162 S_028004_SAMPLE_RATE(sample_rate) |
2163 S_028004_ZPASS_ENABLE(1) |
2164 S_028004_SLICE_EVEN_ENABLE(1) |
2165 S_028004_SLICE_ODD_ENABLE(1);
2166
2167 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2168 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2169 has_perfect_queries) {
2170 /* If the bound pipeline has enabled
2171 * out-of-order rasterization, we should
2172 * disable it before starting any perfect
2173 * occlusion queries.
2174 */
2175 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
2176
2177 radeon_set_context_reg(cmd_buffer->cs,
2178 R_028A4C_PA_SC_MODE_CNTL_1,
2179 pa_sc_mode_cntl_1);
2180 }
2181 } else {
2182 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
2183 S_028004_SAMPLE_RATE(sample_rate);
2184 }
2185 }
2186
2187 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
2188
2189 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2190 }
2191
2192 static void
2193 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
2194 {
2195 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
2196
2197 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
2198 radv_emit_viewport(cmd_buffer);
2199
2200 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
2201 !cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
2202 radv_emit_scissor(cmd_buffer);
2203
2204 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
2205 radv_emit_line_width(cmd_buffer);
2206
2207 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
2208 radv_emit_blend_constants(cmd_buffer);
2209
2210 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
2211 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
2212 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
2213 radv_emit_stencil(cmd_buffer);
2214
2215 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
2216 radv_emit_depth_bounds(cmd_buffer);
2217
2218 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
2219 radv_emit_depth_bias(cmd_buffer);
2220
2221 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
2222 radv_emit_discard_rectangle(cmd_buffer);
2223
2224 if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)
2225 radv_emit_sample_locations(cmd_buffer);
2226
2227 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE)
2228 radv_emit_line_stipple(cmd_buffer);
2229
2230 cmd_buffer->state.dirty &= ~states;
2231 }
2232
2233 static void
2234 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
2235 VkPipelineBindPoint bind_point)
2236 {
2237 struct radv_descriptor_state *descriptors_state =
2238 radv_get_descriptors_state(cmd_buffer, bind_point);
2239 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
2240 unsigned bo_offset;
2241
2242 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
2243 set->mapped_ptr,
2244 &bo_offset))
2245 return;
2246
2247 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2248 set->va += bo_offset;
2249 }
2250
2251 static void
2252 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
2253 VkPipelineBindPoint bind_point)
2254 {
2255 struct radv_descriptor_state *descriptors_state =
2256 radv_get_descriptors_state(cmd_buffer, bind_point);
2257 uint32_t size = MAX_SETS * 4;
2258 uint32_t offset;
2259 void *ptr;
2260
2261 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
2262 256, &offset, &ptr))
2263 return;
2264
2265 for (unsigned i = 0; i < MAX_SETS; i++) {
2266 uint32_t *uptr = ((uint32_t *)ptr) + i;
2267 uint64_t set_va = 0;
2268 struct radv_descriptor_set *set = descriptors_state->sets[i];
2269 if (descriptors_state->valid & (1u << i))
2270 set_va = set->va;
2271 uptr[0] = set_va & 0xffffffff;
2272 }
2273
2274 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2275 va += offset;
2276
2277 if (cmd_buffer->state.pipeline) {
2278 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
2279 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2280 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2281
2282 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
2283 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
2284 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2285
2286 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
2287 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2288 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2289
2290 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2291 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
2292 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2293
2294 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2295 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
2296 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2297 }
2298
2299 if (cmd_buffer->state.compute_pipeline)
2300 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
2301 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2302 }
2303
2304 static void
2305 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
2306 VkShaderStageFlags stages)
2307 {
2308 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2309 VK_PIPELINE_BIND_POINT_COMPUTE :
2310 VK_PIPELINE_BIND_POINT_GRAPHICS;
2311 struct radv_descriptor_state *descriptors_state =
2312 radv_get_descriptors_state(cmd_buffer, bind_point);
2313 struct radv_cmd_state *state = &cmd_buffer->state;
2314 bool flush_indirect_descriptors;
2315
2316 if (!descriptors_state->dirty)
2317 return;
2318
2319 if (descriptors_state->push_dirty)
2320 radv_flush_push_descriptors(cmd_buffer, bind_point);
2321
2322 flush_indirect_descriptors =
2323 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
2324 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
2325 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
2326 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
2327
2328 if (flush_indirect_descriptors)
2329 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
2330
2331 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2332 cmd_buffer->cs,
2333 MAX_SETS * MESA_SHADER_STAGES * 4);
2334
2335 if (cmd_buffer->state.pipeline) {
2336 radv_foreach_stage(stage, stages) {
2337 if (!cmd_buffer->state.pipeline->shaders[stage])
2338 continue;
2339
2340 radv_emit_descriptor_pointers(cmd_buffer,
2341 cmd_buffer->state.pipeline,
2342 descriptors_state, stage);
2343 }
2344 }
2345
2346 if (cmd_buffer->state.compute_pipeline &&
2347 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
2348 radv_emit_descriptor_pointers(cmd_buffer,
2349 cmd_buffer->state.compute_pipeline,
2350 descriptors_state,
2351 MESA_SHADER_COMPUTE);
2352 }
2353
2354 descriptors_state->dirty = 0;
2355 descriptors_state->push_dirty = false;
2356
2357 assert(cmd_buffer->cs->cdw <= cdw_max);
2358
2359 if (unlikely(cmd_buffer->device->trace_bo))
2360 radv_save_descriptors(cmd_buffer, bind_point);
2361 }
2362
2363 static void
2364 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
2365 VkShaderStageFlags stages)
2366 {
2367 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
2368 ? cmd_buffer->state.compute_pipeline
2369 : cmd_buffer->state.pipeline;
2370 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2371 VK_PIPELINE_BIND_POINT_COMPUTE :
2372 VK_PIPELINE_BIND_POINT_GRAPHICS;
2373 struct radv_descriptor_state *descriptors_state =
2374 radv_get_descriptors_state(cmd_buffer, bind_point);
2375 struct radv_pipeline_layout *layout = pipeline->layout;
2376 struct radv_shader_variant *shader, *prev_shader;
2377 bool need_push_constants = false;
2378 unsigned offset;
2379 void *ptr;
2380 uint64_t va;
2381
2382 stages &= cmd_buffer->push_constant_stages;
2383 if (!stages ||
2384 (!layout->push_constant_size && !layout->dynamic_offset_count))
2385 return;
2386
2387 radv_foreach_stage(stage, stages) {
2388 shader = radv_get_shader(pipeline, stage);
2389 if (!shader)
2390 continue;
2391
2392 need_push_constants |= shader->info.loads_push_constants;
2393 need_push_constants |= shader->info.loads_dynamic_offsets;
2394
2395 uint8_t base = shader->info.base_inline_push_consts;
2396 uint8_t count = shader->info.num_inline_push_consts;
2397
2398 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
2399 AC_UD_INLINE_PUSH_CONSTANTS,
2400 count,
2401 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
2402 }
2403
2404 if (need_push_constants) {
2405 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
2406 16 * layout->dynamic_offset_count,
2407 256, &offset, &ptr))
2408 return;
2409
2410 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
2411 memcpy((char*)ptr + layout->push_constant_size,
2412 descriptors_state->dynamic_buffers,
2413 16 * layout->dynamic_offset_count);
2414
2415 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2416 va += offset;
2417
2418 ASSERTED unsigned cdw_max =
2419 radeon_check_space(cmd_buffer->device->ws,
2420 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
2421
2422 prev_shader = NULL;
2423 radv_foreach_stage(stage, stages) {
2424 shader = radv_get_shader(pipeline, stage);
2425
2426 /* Avoid redundantly emitting the address for merged stages. */
2427 if (shader && shader != prev_shader) {
2428 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
2429 AC_UD_PUSH_CONSTANTS, va);
2430
2431 prev_shader = shader;
2432 }
2433 }
2434 assert(cmd_buffer->cs->cdw <= cdw_max);
2435 }
2436
2437 cmd_buffer->push_constant_stages &= ~stages;
2438 }
2439
2440 static void
2441 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
2442 bool pipeline_is_dirty)
2443 {
2444 if ((pipeline_is_dirty ||
2445 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
2446 cmd_buffer->state.pipeline->num_vertex_bindings &&
2447 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.has_vertex_buffers) {
2448 unsigned vb_offset;
2449 void *vb_ptr;
2450 uint32_t i = 0;
2451 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
2452 uint64_t va;
2453
2454 /* allocate some descriptor state for vertex buffers */
2455 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2456 &vb_offset, &vb_ptr))
2457 return;
2458
2459 for (i = 0; i < count; i++) {
2460 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2461 uint32_t offset;
2462 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2463 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[i];
2464 unsigned num_records;
2465
2466 if (!buffer)
2467 continue;
2468
2469 va = radv_buffer_get_va(buffer->bo);
2470
2471 offset = cmd_buffer->vertex_bindings[i].offset;
2472 va += offset + buffer->offset;
2473
2474 num_records = buffer->size - offset;
2475 if (cmd_buffer->device->physical_device->rad_info.chip_class != GFX8 && stride)
2476 num_records /= stride;
2477
2478 desc[0] = va;
2479 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2480 desc[2] = num_records;
2481 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2482 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2483 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2484 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2485
2486 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2487 /* OOB_SELECT chooses the out-of-bounds check:
2488 * - 1: index >= NUM_RECORDS (Structured)
2489 * - 3: offset >= NUM_RECORDS (Raw)
2490 */
2491 int oob_select = stride ? V_008F0C_OOB_SELECT_STRUCTURED : V_008F0C_OOB_SELECT_RAW;
2492
2493 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT) |
2494 S_008F0C_OOB_SELECT(oob_select) |
2495 S_008F0C_RESOURCE_LEVEL(1);
2496 } else {
2497 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2498 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2499 }
2500 }
2501
2502 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2503 va += vb_offset;
2504
2505 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2506 AC_UD_VS_VERTEX_BUFFERS, va);
2507
2508 cmd_buffer->state.vb_va = va;
2509 cmd_buffer->state.vb_size = count * 16;
2510 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2511 }
2512 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2513 }
2514
2515 static void
2516 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2517 {
2518 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2519 struct radv_userdata_info *loc;
2520 uint32_t base_reg;
2521
2522 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2523 if (!radv_get_shader(pipeline, stage))
2524 continue;
2525
2526 loc = radv_lookup_user_sgpr(pipeline, stage,
2527 AC_UD_STREAMOUT_BUFFERS);
2528 if (loc->sgpr_idx == -1)
2529 continue;
2530
2531 base_reg = pipeline->user_data_0[stage];
2532
2533 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2534 base_reg + loc->sgpr_idx * 4, va, false);
2535 }
2536
2537 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
2538 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2539 if (loc->sgpr_idx != -1) {
2540 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2541
2542 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2543 base_reg + loc->sgpr_idx * 4, va, false);
2544 }
2545 }
2546 }
2547
2548 static void
2549 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2550 {
2551 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2552 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2553 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2554 unsigned so_offset;
2555 void *so_ptr;
2556 uint64_t va;
2557
2558 /* Allocate some descriptor state for streamout buffers. */
2559 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2560 MAX_SO_BUFFERS * 16, 256,
2561 &so_offset, &so_ptr))
2562 return;
2563
2564 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2565 struct radv_buffer *buffer = sb[i].buffer;
2566 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2567
2568 if (!(so->enabled_mask & (1 << i)))
2569 continue;
2570
2571 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2572
2573 va += sb[i].offset;
2574
2575 /* Set the descriptor.
2576 *
2577 * On GFX8, the format must be non-INVALID, otherwise
2578 * the buffer will be considered not bound and store
2579 * instructions will be no-ops.
2580 */
2581 uint32_t size = 0xffffffff;
2582
2583 /* Compute the correct buffer size for NGG streamout
2584 * because it's used to determine the max emit per
2585 * buffer.
2586 */
2587 if (cmd_buffer->device->physical_device->use_ngg_streamout)
2588 size = buffer->size - sb[i].offset;
2589
2590 desc[0] = va;
2591 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2592 desc[2] = size;
2593 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2594 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2595 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2596 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2597
2598 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2599 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2600 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
2601 S_008F0C_RESOURCE_LEVEL(1);
2602 } else {
2603 desc[3] |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2604 }
2605 }
2606
2607 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2608 va += so_offset;
2609
2610 radv_emit_streamout_buffers(cmd_buffer, va);
2611 }
2612
2613 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2614 }
2615
2616 static void
2617 radv_flush_ngg_gs_state(struct radv_cmd_buffer *cmd_buffer)
2618 {
2619 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2620 struct radv_userdata_info *loc;
2621 uint32_t ngg_gs_state = 0;
2622 uint32_t base_reg;
2623
2624 if (!radv_pipeline_has_gs(pipeline) ||
2625 !radv_pipeline_has_ngg(pipeline))
2626 return;
2627
2628 /* By default NGG GS queries are disabled but they are enabled if the
2629 * command buffer has active GDS queries or if it's a secondary command
2630 * buffer that inherits the number of generated primitives.
2631 */
2632 if (cmd_buffer->state.active_pipeline_gds_queries ||
2633 (cmd_buffer->state.inherited_pipeline_statistics & VK_QUERY_PIPELINE_STATISTIC_GEOMETRY_SHADER_PRIMITIVES_BIT))
2634 ngg_gs_state = 1;
2635
2636 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_GEOMETRY,
2637 AC_UD_NGG_GS_STATE);
2638 base_reg = pipeline->user_data_0[MESA_SHADER_GEOMETRY];
2639 assert(loc->sgpr_idx != -1);
2640
2641 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
2642 ngg_gs_state);
2643 }
2644
2645 static void
2646 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2647 {
2648 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2649 radv_flush_streamout_descriptors(cmd_buffer);
2650 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2651 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2652 radv_flush_ngg_gs_state(cmd_buffer);
2653 }
2654
2655 struct radv_draw_info {
2656 /**
2657 * Number of vertices.
2658 */
2659 uint32_t count;
2660
2661 /**
2662 * Index of the first vertex.
2663 */
2664 int32_t vertex_offset;
2665
2666 /**
2667 * First instance id.
2668 */
2669 uint32_t first_instance;
2670
2671 /**
2672 * Number of instances.
2673 */
2674 uint32_t instance_count;
2675
2676 /**
2677 * First index (indexed draws only).
2678 */
2679 uint32_t first_index;
2680
2681 /**
2682 * Whether it's an indexed draw.
2683 */
2684 bool indexed;
2685
2686 /**
2687 * Indirect draw parameters resource.
2688 */
2689 struct radv_buffer *indirect;
2690 uint64_t indirect_offset;
2691 uint32_t stride;
2692
2693 /**
2694 * Draw count parameters resource.
2695 */
2696 struct radv_buffer *count_buffer;
2697 uint64_t count_buffer_offset;
2698
2699 /**
2700 * Stream output parameters resource.
2701 */
2702 struct radv_buffer *strmout_buffer;
2703 uint64_t strmout_buffer_offset;
2704 };
2705
2706 static uint32_t
2707 radv_get_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
2708 {
2709 switch (cmd_buffer->state.index_type) {
2710 case V_028A7C_VGT_INDEX_8:
2711 return 0xffu;
2712 case V_028A7C_VGT_INDEX_16:
2713 return 0xffffu;
2714 case V_028A7C_VGT_INDEX_32:
2715 return 0xffffffffu;
2716 default:
2717 unreachable("invalid index type");
2718 }
2719 }
2720
2721 static void
2722 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
2723 bool instanced_draw, bool indirect_draw,
2724 bool count_from_stream_output,
2725 uint32_t draw_vertex_count)
2726 {
2727 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2728 struct radv_cmd_state *state = &cmd_buffer->state;
2729 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2730 unsigned ia_multi_vgt_param;
2731
2732 ia_multi_vgt_param =
2733 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
2734 indirect_draw,
2735 count_from_stream_output,
2736 draw_vertex_count);
2737
2738 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2739 if (info->chip_class == GFX9) {
2740 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2741 cs,
2742 R_030960_IA_MULTI_VGT_PARAM,
2743 4, ia_multi_vgt_param);
2744 } else if (info->chip_class >= GFX7) {
2745 radeon_set_context_reg_idx(cs,
2746 R_028AA8_IA_MULTI_VGT_PARAM,
2747 1, ia_multi_vgt_param);
2748 } else {
2749 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2750 ia_multi_vgt_param);
2751 }
2752 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2753 }
2754 }
2755
2756 static void
2757 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2758 const struct radv_draw_info *draw_info)
2759 {
2760 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2761 struct radv_cmd_state *state = &cmd_buffer->state;
2762 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2763 int32_t primitive_reset_en;
2764
2765 /* Draw state. */
2766 if (info->chip_class < GFX10) {
2767 si_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2768 draw_info->indirect,
2769 !!draw_info->strmout_buffer,
2770 draw_info->indirect ? 0 : draw_info->count);
2771 }
2772
2773 /* Primitive restart. */
2774 primitive_reset_en =
2775 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2776
2777 if (primitive_reset_en != state->last_primitive_reset_en) {
2778 state->last_primitive_reset_en = primitive_reset_en;
2779 if (info->chip_class >= GFX9) {
2780 radeon_set_uconfig_reg(cs,
2781 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2782 primitive_reset_en);
2783 } else {
2784 radeon_set_context_reg(cs,
2785 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2786 primitive_reset_en);
2787 }
2788 }
2789
2790 if (primitive_reset_en) {
2791 uint32_t primitive_reset_index =
2792 radv_get_primitive_reset_index(cmd_buffer);
2793
2794 if (primitive_reset_index != state->last_primitive_reset_index) {
2795 radeon_set_context_reg(cs,
2796 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2797 primitive_reset_index);
2798 state->last_primitive_reset_index = primitive_reset_index;
2799 }
2800 }
2801
2802 if (draw_info->strmout_buffer) {
2803 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2804
2805 va += draw_info->strmout_buffer->offset +
2806 draw_info->strmout_buffer_offset;
2807
2808 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2809 draw_info->stride);
2810
2811 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2812 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2813 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2814 COPY_DATA_WR_CONFIRM);
2815 radeon_emit(cs, va);
2816 radeon_emit(cs, va >> 32);
2817 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2818 radeon_emit(cs, 0); /* unused */
2819
2820 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2821 }
2822 }
2823
2824 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2825 VkPipelineStageFlags src_stage_mask)
2826 {
2827 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2828 VK_PIPELINE_STAGE_TRANSFER_BIT |
2829 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2830 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2831 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2832 }
2833
2834 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2835 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2836 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2837 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2838 VK_PIPELINE_STAGE_TRANSFER_BIT |
2839 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2840 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2841 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2842 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2843 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2844 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2845 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2846 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2847 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2848 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2849 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2850 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2851 }
2852 }
2853
2854 static enum radv_cmd_flush_bits
2855 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2856 VkAccessFlags src_flags,
2857 struct radv_image *image)
2858 {
2859 bool flush_CB_meta = true, flush_DB_meta = true;
2860 enum radv_cmd_flush_bits flush_bits = 0;
2861 uint32_t b;
2862
2863 if (image) {
2864 if (!radv_image_has_CB_metadata(image))
2865 flush_CB_meta = false;
2866 if (!radv_image_has_htile(image))
2867 flush_DB_meta = false;
2868 }
2869
2870 for_each_bit(b, src_flags) {
2871 switch ((VkAccessFlagBits)(1 << b)) {
2872 case VK_ACCESS_SHADER_WRITE_BIT:
2873 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2874 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2875 flush_bits |= RADV_CMD_FLAG_WB_L2;
2876 break;
2877 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2878 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2879 if (flush_CB_meta)
2880 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2881 break;
2882 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2883 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2884 if (flush_DB_meta)
2885 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2886 break;
2887 case VK_ACCESS_TRANSFER_WRITE_BIT:
2888 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2889 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2890 RADV_CMD_FLAG_INV_L2;
2891
2892 if (flush_CB_meta)
2893 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2894 if (flush_DB_meta)
2895 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2896 break;
2897 default:
2898 break;
2899 }
2900 }
2901 return flush_bits;
2902 }
2903
2904 static enum radv_cmd_flush_bits
2905 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2906 VkAccessFlags dst_flags,
2907 struct radv_image *image)
2908 {
2909 bool flush_CB_meta = true, flush_DB_meta = true;
2910 enum radv_cmd_flush_bits flush_bits = 0;
2911 bool flush_CB = true, flush_DB = true;
2912 bool image_is_coherent = false;
2913 uint32_t b;
2914
2915 if (image) {
2916 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2917 flush_CB = false;
2918 flush_DB = false;
2919 }
2920
2921 if (!radv_image_has_CB_metadata(image))
2922 flush_CB_meta = false;
2923 if (!radv_image_has_htile(image))
2924 flush_DB_meta = false;
2925
2926 /* TODO: implement shader coherent for GFX10 */
2927
2928 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
2929 if (image->info.samples == 1 &&
2930 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2931 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2932 !vk_format_is_stencil(image->vk_format)) {
2933 /* Single-sample color and single-sample depth
2934 * (not stencil) are coherent with shaders on
2935 * GFX9.
2936 */
2937 image_is_coherent = true;
2938 }
2939 }
2940 }
2941
2942 for_each_bit(b, dst_flags) {
2943 switch ((VkAccessFlagBits)(1 << b)) {
2944 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2945 case VK_ACCESS_INDEX_READ_BIT:
2946 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2947 break;
2948 case VK_ACCESS_UNIFORM_READ_BIT:
2949 flush_bits |= RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_SCACHE;
2950 break;
2951 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2952 case VK_ACCESS_TRANSFER_READ_BIT:
2953 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2954 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
2955 RADV_CMD_FLAG_INV_L2;
2956 break;
2957 case VK_ACCESS_SHADER_READ_BIT:
2958 flush_bits |= RADV_CMD_FLAG_INV_VCACHE;
2959 /* Unlike LLVM, ACO uses SMEM for SSBOs and we have to
2960 * invalidate the scalar cache. */
2961 if (cmd_buffer->device->physical_device->use_aco &&
2962 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8)
2963 flush_bits |= RADV_CMD_FLAG_INV_SCACHE;
2964
2965 if (!image_is_coherent)
2966 flush_bits |= RADV_CMD_FLAG_INV_L2;
2967 break;
2968 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2969 if (flush_CB)
2970 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2971 if (flush_CB_meta)
2972 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2973 break;
2974 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2975 if (flush_DB)
2976 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2977 if (flush_DB_meta)
2978 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2979 break;
2980 default:
2981 break;
2982 }
2983 }
2984 return flush_bits;
2985 }
2986
2987 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2988 const struct radv_subpass_barrier *barrier)
2989 {
2990 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2991 NULL);
2992 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2993 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2994 NULL);
2995 }
2996
2997 uint32_t
2998 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
2999 {
3000 struct radv_cmd_state *state = &cmd_buffer->state;
3001 uint32_t subpass_id = state->subpass - state->pass->subpasses;
3002
3003 /* The id of this subpass shouldn't exceed the number of subpasses in
3004 * this render pass minus 1.
3005 */
3006 assert(subpass_id < state->pass->subpass_count);
3007 return subpass_id;
3008 }
3009
3010 static struct radv_sample_locations_state *
3011 radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer,
3012 uint32_t att_idx,
3013 bool begin_subpass)
3014 {
3015 struct radv_cmd_state *state = &cmd_buffer->state;
3016 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
3017 struct radv_image_view *view = state->attachments[att_idx].iview;
3018
3019 if (view->image->info.samples == 1)
3020 return NULL;
3021
3022 if (state->pass->attachments[att_idx].first_subpass_idx == subpass_id) {
3023 /* Return the initial sample locations if this is the initial
3024 * layout transition of the given subpass attachemnt.
3025 */
3026 if (state->attachments[att_idx].sample_location.count > 0)
3027 return &state->attachments[att_idx].sample_location;
3028 } else {
3029 /* Otherwise return the subpass sample locations if defined. */
3030 if (state->subpass_sample_locs) {
3031 /* Because the driver sets the current subpass before
3032 * initial layout transitions, we should use the sample
3033 * locations from the previous subpass to avoid an
3034 * off-by-one problem. Otherwise, use the sample
3035 * locations for the current subpass for final layout
3036 * transitions.
3037 */
3038 if (begin_subpass)
3039 subpass_id--;
3040
3041 for (uint32_t i = 0; i < state->num_subpass_sample_locs; i++) {
3042 if (state->subpass_sample_locs[i].subpass_idx == subpass_id)
3043 return &state->subpass_sample_locs[i].sample_location;
3044 }
3045 }
3046 }
3047
3048 return NULL;
3049 }
3050
3051 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
3052 struct radv_subpass_attachment att,
3053 bool begin_subpass)
3054 {
3055 unsigned idx = att.attachment;
3056 struct radv_image_view *view = cmd_buffer->state.attachments[idx].iview;
3057 struct radv_sample_locations_state *sample_locs;
3058 VkImageSubresourceRange range;
3059 range.aspectMask = view->aspect_mask;
3060 range.baseMipLevel = view->base_mip;
3061 range.levelCount = 1;
3062 range.baseArrayLayer = view->base_layer;
3063 range.layerCount = cmd_buffer->state.framebuffer->layers;
3064
3065 if (cmd_buffer->state.subpass->view_mask) {
3066 /* If the current subpass uses multiview, the driver might have
3067 * performed a fast color/depth clear to the whole image
3068 * (including all layers). To make sure the driver will
3069 * decompress the image correctly (if needed), we have to
3070 * account for the "real" number of layers. If the view mask is
3071 * sparse, this will decompress more layers than needed.
3072 */
3073 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
3074 }
3075
3076 /* Get the subpass sample locations for the given attachment, if NULL
3077 * is returned the driver will use the default HW locations.
3078 */
3079 sample_locs = radv_get_attachment_sample_locations(cmd_buffer, idx,
3080 begin_subpass);
3081
3082 /* Determine if the subpass uses separate depth/stencil layouts. */
3083 bool uses_separate_depth_stencil_layouts = false;
3084 if ((cmd_buffer->state.attachments[idx].current_layout !=
3085 cmd_buffer->state.attachments[idx].current_stencil_layout) ||
3086 (att.layout != att.stencil_layout)) {
3087 uses_separate_depth_stencil_layouts = true;
3088 }
3089
3090 /* For separate layouts, perform depth and stencil transitions
3091 * separately.
3092 */
3093 if (uses_separate_depth_stencil_layouts &&
3094 (range.aspectMask == (VK_IMAGE_ASPECT_DEPTH_BIT |
3095 VK_IMAGE_ASPECT_STENCIL_BIT))) {
3096 /* Depth-only transitions. */
3097 range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3098 radv_handle_image_transition(cmd_buffer,
3099 view->image,
3100 cmd_buffer->state.attachments[idx].current_layout,
3101 cmd_buffer->state.attachments[idx].current_in_render_loop,
3102 att.layout, att.in_render_loop,
3103 0, 0, &range, sample_locs);
3104
3105 /* Stencil-only transitions. */
3106 range.aspectMask = VK_IMAGE_ASPECT_STENCIL_BIT;
3107 radv_handle_image_transition(cmd_buffer,
3108 view->image,
3109 cmd_buffer->state.attachments[idx].current_stencil_layout,
3110 cmd_buffer->state.attachments[idx].current_in_render_loop,
3111 att.stencil_layout, att.in_render_loop,
3112 0, 0, &range, sample_locs);
3113 } else {
3114 radv_handle_image_transition(cmd_buffer,
3115 view->image,
3116 cmd_buffer->state.attachments[idx].current_layout,
3117 cmd_buffer->state.attachments[idx].current_in_render_loop,
3118 att.layout, att.in_render_loop,
3119 0, 0, &range, sample_locs);
3120 }
3121
3122 cmd_buffer->state.attachments[idx].current_layout = att.layout;
3123 cmd_buffer->state.attachments[idx].current_stencil_layout = att.stencil_layout;
3124 cmd_buffer->state.attachments[idx].current_in_render_loop = att.in_render_loop;
3125
3126
3127 }
3128
3129 void
3130 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
3131 const struct radv_subpass *subpass)
3132 {
3133 cmd_buffer->state.subpass = subpass;
3134
3135 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
3136 }
3137
3138 static VkResult
3139 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
3140 struct radv_render_pass *pass,
3141 const VkRenderPassBeginInfo *info)
3142 {
3143 const struct VkRenderPassSampleLocationsBeginInfoEXT *sample_locs =
3144 vk_find_struct_const(info->pNext,
3145 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT);
3146 struct radv_cmd_state *state = &cmd_buffer->state;
3147
3148 if (!sample_locs) {
3149 state->subpass_sample_locs = NULL;
3150 return VK_SUCCESS;
3151 }
3152
3153 for (uint32_t i = 0; i < sample_locs->attachmentInitialSampleLocationsCount; i++) {
3154 const VkAttachmentSampleLocationsEXT *att_sample_locs =
3155 &sample_locs->pAttachmentInitialSampleLocations[i];
3156 uint32_t att_idx = att_sample_locs->attachmentIndex;
3157 struct radv_image *image = cmd_buffer->state.attachments[att_idx].iview->image;
3158
3159 assert(vk_format_is_depth_or_stencil(image->vk_format));
3160
3161 /* From the Vulkan spec 1.1.108:
3162 *
3163 * "If the image referenced by the framebuffer attachment at
3164 * index attachmentIndex was not created with
3165 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
3166 * then the values specified in sampleLocationsInfo are
3167 * ignored."
3168 */
3169 if (!(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT))
3170 continue;
3171
3172 const VkSampleLocationsInfoEXT *sample_locs_info =
3173 &att_sample_locs->sampleLocationsInfo;
3174
3175 state->attachments[att_idx].sample_location.per_pixel =
3176 sample_locs_info->sampleLocationsPerPixel;
3177 state->attachments[att_idx].sample_location.grid_size =
3178 sample_locs_info->sampleLocationGridSize;
3179 state->attachments[att_idx].sample_location.count =
3180 sample_locs_info->sampleLocationsCount;
3181 typed_memcpy(&state->attachments[att_idx].sample_location.locations[0],
3182 sample_locs_info->pSampleLocations,
3183 sample_locs_info->sampleLocationsCount);
3184 }
3185
3186 state->subpass_sample_locs = vk_alloc(&cmd_buffer->pool->alloc,
3187 sample_locs->postSubpassSampleLocationsCount *
3188 sizeof(state->subpass_sample_locs[0]),
3189 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3190 if (state->subpass_sample_locs == NULL) {
3191 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3192 return cmd_buffer->record_result;
3193 }
3194
3195 state->num_subpass_sample_locs = sample_locs->postSubpassSampleLocationsCount;
3196
3197 for (uint32_t i = 0; i < sample_locs->postSubpassSampleLocationsCount; i++) {
3198 const VkSubpassSampleLocationsEXT *subpass_sample_locs_info =
3199 &sample_locs->pPostSubpassSampleLocations[i];
3200 const VkSampleLocationsInfoEXT *sample_locs_info =
3201 &subpass_sample_locs_info->sampleLocationsInfo;
3202
3203 state->subpass_sample_locs[i].subpass_idx =
3204 subpass_sample_locs_info->subpassIndex;
3205 state->subpass_sample_locs[i].sample_location.per_pixel =
3206 sample_locs_info->sampleLocationsPerPixel;
3207 state->subpass_sample_locs[i].sample_location.grid_size =
3208 sample_locs_info->sampleLocationGridSize;
3209 state->subpass_sample_locs[i].sample_location.count =
3210 sample_locs_info->sampleLocationsCount;
3211 typed_memcpy(&state->subpass_sample_locs[i].sample_location.locations[0],
3212 sample_locs_info->pSampleLocations,
3213 sample_locs_info->sampleLocationsCount);
3214 }
3215
3216 return VK_SUCCESS;
3217 }
3218
3219 static VkResult
3220 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
3221 struct radv_render_pass *pass,
3222 const VkRenderPassBeginInfo *info)
3223 {
3224 struct radv_cmd_state *state = &cmd_buffer->state;
3225 const struct VkRenderPassAttachmentBeginInfo *attachment_info = NULL;
3226
3227 if (info) {
3228 attachment_info = vk_find_struct_const(info->pNext,
3229 RENDER_PASS_ATTACHMENT_BEGIN_INFO);
3230 }
3231
3232
3233 if (pass->attachment_count == 0) {
3234 state->attachments = NULL;
3235 return VK_SUCCESS;
3236 }
3237
3238 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
3239 pass->attachment_count *
3240 sizeof(state->attachments[0]),
3241 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3242 if (state->attachments == NULL) {
3243 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3244 return cmd_buffer->record_result;
3245 }
3246
3247 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
3248 struct radv_render_pass_attachment *att = &pass->attachments[i];
3249 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
3250 VkImageAspectFlags clear_aspects = 0;
3251
3252 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
3253 /* color attachment */
3254 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3255 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
3256 }
3257 } else {
3258 /* depthstencil attachment */
3259 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
3260 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3261 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
3262 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3263 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
3264 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3265 }
3266 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3267 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3268 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3269 }
3270 }
3271
3272 state->attachments[i].pending_clear_aspects = clear_aspects;
3273 state->attachments[i].cleared_views = 0;
3274 if (clear_aspects && info) {
3275 assert(info->clearValueCount > i);
3276 state->attachments[i].clear_value = info->pClearValues[i];
3277 }
3278
3279 state->attachments[i].current_layout = att->initial_layout;
3280 state->attachments[i].current_stencil_layout = att->stencil_initial_layout;
3281 state->attachments[i].sample_location.count = 0;
3282
3283 struct radv_image_view *iview;
3284 if (attachment_info && attachment_info->attachmentCount > i) {
3285 iview = radv_image_view_from_handle(attachment_info->pAttachments[i]);
3286 } else {
3287 iview = state->framebuffer->attachments[i];
3288 }
3289
3290 state->attachments[i].iview = iview;
3291 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3292 radv_initialise_ds_surface(cmd_buffer->device, &state->attachments[i].ds, iview);
3293 } else {
3294 radv_initialise_color_surface(cmd_buffer->device, &state->attachments[i].cb, iview);
3295 }
3296 }
3297
3298 return VK_SUCCESS;
3299 }
3300
3301 VkResult radv_AllocateCommandBuffers(
3302 VkDevice _device,
3303 const VkCommandBufferAllocateInfo *pAllocateInfo,
3304 VkCommandBuffer *pCommandBuffers)
3305 {
3306 RADV_FROM_HANDLE(radv_device, device, _device);
3307 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
3308
3309 VkResult result = VK_SUCCESS;
3310 uint32_t i;
3311
3312 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
3313
3314 if (!list_is_empty(&pool->free_cmd_buffers)) {
3315 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
3316
3317 list_del(&cmd_buffer->pool_link);
3318 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
3319
3320 result = radv_reset_cmd_buffer(cmd_buffer);
3321 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
3322 cmd_buffer->level = pAllocateInfo->level;
3323
3324 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
3325 } else {
3326 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
3327 &pCommandBuffers[i]);
3328 }
3329 if (result != VK_SUCCESS)
3330 break;
3331 }
3332
3333 if (result != VK_SUCCESS) {
3334 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
3335 i, pCommandBuffers);
3336
3337 /* From the Vulkan 1.0.66 spec:
3338 *
3339 * "vkAllocateCommandBuffers can be used to create multiple
3340 * command buffers. If the creation of any of those command
3341 * buffers fails, the implementation must destroy all
3342 * successfully created command buffer objects from this
3343 * command, set all entries of the pCommandBuffers array to
3344 * NULL and return the error."
3345 */
3346 memset(pCommandBuffers, 0,
3347 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
3348 }
3349
3350 return result;
3351 }
3352
3353 void radv_FreeCommandBuffers(
3354 VkDevice device,
3355 VkCommandPool commandPool,
3356 uint32_t commandBufferCount,
3357 const VkCommandBuffer *pCommandBuffers)
3358 {
3359 for (uint32_t i = 0; i < commandBufferCount; i++) {
3360 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
3361
3362 if (cmd_buffer) {
3363 if (cmd_buffer->pool) {
3364 list_del(&cmd_buffer->pool_link);
3365 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
3366 } else
3367 radv_cmd_buffer_destroy(cmd_buffer);
3368
3369 }
3370 }
3371 }
3372
3373 VkResult radv_ResetCommandBuffer(
3374 VkCommandBuffer commandBuffer,
3375 VkCommandBufferResetFlags flags)
3376 {
3377 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3378 return radv_reset_cmd_buffer(cmd_buffer);
3379 }
3380
3381 VkResult radv_BeginCommandBuffer(
3382 VkCommandBuffer commandBuffer,
3383 const VkCommandBufferBeginInfo *pBeginInfo)
3384 {
3385 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3386 VkResult result = VK_SUCCESS;
3387
3388 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
3389 /* If the command buffer has already been resetted with
3390 * vkResetCommandBuffer, no need to do it again.
3391 */
3392 result = radv_reset_cmd_buffer(cmd_buffer);
3393 if (result != VK_SUCCESS)
3394 return result;
3395 }
3396
3397 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
3398 cmd_buffer->state.last_primitive_reset_en = -1;
3399 cmd_buffer->state.last_index_type = -1;
3400 cmd_buffer->state.last_num_instances = -1;
3401 cmd_buffer->state.last_vertex_offset = -1;
3402 cmd_buffer->state.last_first_instance = -1;
3403 cmd_buffer->state.predication_type = -1;
3404 cmd_buffer->state.last_sx_ps_downconvert = -1;
3405 cmd_buffer->state.last_sx_blend_opt_epsilon = -1;
3406 cmd_buffer->state.last_sx_blend_opt_control = -1;
3407 cmd_buffer->usage_flags = pBeginInfo->flags;
3408
3409 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
3410 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
3411 assert(pBeginInfo->pInheritanceInfo);
3412 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
3413 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
3414
3415 struct radv_subpass *subpass =
3416 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
3417
3418 if (cmd_buffer->state.framebuffer) {
3419 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
3420 if (result != VK_SUCCESS)
3421 return result;
3422 }
3423
3424 cmd_buffer->state.inherited_pipeline_statistics =
3425 pBeginInfo->pInheritanceInfo->pipelineStatistics;
3426
3427 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3428 }
3429
3430 if (unlikely(cmd_buffer->device->trace_bo))
3431 radv_cmd_buffer_trace_emit(cmd_buffer);
3432
3433 radv_describe_begin_cmd_buffer(cmd_buffer);
3434
3435 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
3436
3437 return result;
3438 }
3439
3440 void radv_CmdBindVertexBuffers(
3441 VkCommandBuffer commandBuffer,
3442 uint32_t firstBinding,
3443 uint32_t bindingCount,
3444 const VkBuffer* pBuffers,
3445 const VkDeviceSize* pOffsets)
3446 {
3447 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3448 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
3449 bool changed = false;
3450
3451 /* We have to defer setting up vertex buffer since we need the buffer
3452 * stride from the pipeline. */
3453
3454 assert(firstBinding + bindingCount <= MAX_VBS);
3455 for (uint32_t i = 0; i < bindingCount; i++) {
3456 uint32_t idx = firstBinding + i;
3457
3458 if (!changed &&
3459 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
3460 vb[idx].offset != pOffsets[i])) {
3461 changed = true;
3462 }
3463
3464 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
3465 vb[idx].offset = pOffsets[i];
3466
3467 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3468 vb[idx].buffer->bo);
3469 }
3470
3471 if (!changed) {
3472 /* No state changes. */
3473 return;
3474 }
3475
3476 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
3477 }
3478
3479 static uint32_t
3480 vk_to_index_type(VkIndexType type)
3481 {
3482 switch (type) {
3483 case VK_INDEX_TYPE_UINT8_EXT:
3484 return V_028A7C_VGT_INDEX_8;
3485 case VK_INDEX_TYPE_UINT16:
3486 return V_028A7C_VGT_INDEX_16;
3487 case VK_INDEX_TYPE_UINT32:
3488 return V_028A7C_VGT_INDEX_32;
3489 default:
3490 unreachable("invalid index type");
3491 }
3492 }
3493
3494 static uint32_t
3495 radv_get_vgt_index_size(uint32_t type)
3496 {
3497 switch (type) {
3498 case V_028A7C_VGT_INDEX_8:
3499 return 1;
3500 case V_028A7C_VGT_INDEX_16:
3501 return 2;
3502 case V_028A7C_VGT_INDEX_32:
3503 return 4;
3504 default:
3505 unreachable("invalid index type");
3506 }
3507 }
3508
3509 void radv_CmdBindIndexBuffer(
3510 VkCommandBuffer commandBuffer,
3511 VkBuffer buffer,
3512 VkDeviceSize offset,
3513 VkIndexType indexType)
3514 {
3515 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3516 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
3517
3518 if (cmd_buffer->state.index_buffer == index_buffer &&
3519 cmd_buffer->state.index_offset == offset &&
3520 cmd_buffer->state.index_type == indexType) {
3521 /* No state changes. */
3522 return;
3523 }
3524
3525 cmd_buffer->state.index_buffer = index_buffer;
3526 cmd_buffer->state.index_offset = offset;
3527 cmd_buffer->state.index_type = vk_to_index_type(indexType);
3528 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
3529 cmd_buffer->state.index_va += index_buffer->offset + offset;
3530
3531 int index_size = radv_get_vgt_index_size(vk_to_index_type(indexType));
3532 cmd_buffer->state.max_index_count = (index_buffer->size - offset) / index_size;
3533 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3534 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
3535 }
3536
3537
3538 static void
3539 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3540 VkPipelineBindPoint bind_point,
3541 struct radv_descriptor_set *set, unsigned idx)
3542 {
3543 struct radeon_winsys *ws = cmd_buffer->device->ws;
3544
3545 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
3546
3547 assert(set);
3548 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
3549
3550 if (!cmd_buffer->device->use_global_bo_list) {
3551 for (unsigned j = 0; j < set->buffer_count; ++j)
3552 if (set->descriptors[j])
3553 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
3554 }
3555
3556 if(set->bo)
3557 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
3558 }
3559
3560 void radv_CmdBindDescriptorSets(
3561 VkCommandBuffer commandBuffer,
3562 VkPipelineBindPoint pipelineBindPoint,
3563 VkPipelineLayout _layout,
3564 uint32_t firstSet,
3565 uint32_t descriptorSetCount,
3566 const VkDescriptorSet* pDescriptorSets,
3567 uint32_t dynamicOffsetCount,
3568 const uint32_t* pDynamicOffsets)
3569 {
3570 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3571 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3572 unsigned dyn_idx = 0;
3573
3574 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
3575 struct radv_descriptor_state *descriptors_state =
3576 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3577
3578 for (unsigned i = 0; i < descriptorSetCount; ++i) {
3579 unsigned idx = i + firstSet;
3580 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
3581
3582 /* If the set is already bound we only need to update the
3583 * (potentially changed) dynamic offsets. */
3584 if (descriptors_state->sets[idx] != set ||
3585 !(descriptors_state->valid & (1u << idx))) {
3586 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
3587 }
3588
3589 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
3590 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
3591 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
3592 assert(dyn_idx < dynamicOffsetCount);
3593
3594 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
3595 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
3596 dst[0] = va;
3597 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
3598 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
3599 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3600 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3601 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3602 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3603
3604 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
3605 dst[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3606 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3607 S_008F0C_RESOURCE_LEVEL(1);
3608 } else {
3609 dst[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3610 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3611 }
3612
3613 cmd_buffer->push_constant_stages |=
3614 set->layout->dynamic_shader_stages;
3615 }
3616 }
3617 }
3618
3619 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3620 struct radv_descriptor_set *set,
3621 struct radv_descriptor_set_layout *layout,
3622 VkPipelineBindPoint bind_point)
3623 {
3624 struct radv_descriptor_state *descriptors_state =
3625 radv_get_descriptors_state(cmd_buffer, bind_point);
3626 set->size = layout->size;
3627 set->layout = layout;
3628
3629 if (descriptors_state->push_set.capacity < set->size) {
3630 size_t new_size = MAX2(set->size, 1024);
3631 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
3632 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
3633
3634 free(set->mapped_ptr);
3635 set->mapped_ptr = malloc(new_size);
3636
3637 if (!set->mapped_ptr) {
3638 descriptors_state->push_set.capacity = 0;
3639 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3640 return false;
3641 }
3642
3643 descriptors_state->push_set.capacity = new_size;
3644 }
3645
3646 return true;
3647 }
3648
3649 void radv_meta_push_descriptor_set(
3650 struct radv_cmd_buffer* cmd_buffer,
3651 VkPipelineBindPoint pipelineBindPoint,
3652 VkPipelineLayout _layout,
3653 uint32_t set,
3654 uint32_t descriptorWriteCount,
3655 const VkWriteDescriptorSet* pDescriptorWrites)
3656 {
3657 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3658 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
3659 unsigned bo_offset;
3660
3661 assert(set == 0);
3662 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3663
3664 push_set->size = layout->set[set].layout->size;
3665 push_set->layout = layout->set[set].layout;
3666
3667 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
3668 &bo_offset,
3669 (void**) &push_set->mapped_ptr))
3670 return;
3671
3672 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
3673 push_set->va += bo_offset;
3674
3675 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3676 radv_descriptor_set_to_handle(push_set),
3677 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3678
3679 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3680 }
3681
3682 void radv_CmdPushDescriptorSetKHR(
3683 VkCommandBuffer commandBuffer,
3684 VkPipelineBindPoint pipelineBindPoint,
3685 VkPipelineLayout _layout,
3686 uint32_t set,
3687 uint32_t descriptorWriteCount,
3688 const VkWriteDescriptorSet* pDescriptorWrites)
3689 {
3690 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3691 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3692 struct radv_descriptor_state *descriptors_state =
3693 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3694 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3695
3696 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3697
3698 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3699 layout->set[set].layout,
3700 pipelineBindPoint))
3701 return;
3702
3703 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3704 * because it is invalid, according to Vulkan spec.
3705 */
3706 for (int i = 0; i < descriptorWriteCount; i++) {
3707 ASSERTED const VkWriteDescriptorSet *writeset = &pDescriptorWrites[i];
3708 assert(writeset->descriptorType != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT);
3709 }
3710
3711 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3712 radv_descriptor_set_to_handle(push_set),
3713 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3714
3715 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3716 descriptors_state->push_dirty = true;
3717 }
3718
3719 void radv_CmdPushDescriptorSetWithTemplateKHR(
3720 VkCommandBuffer commandBuffer,
3721 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
3722 VkPipelineLayout _layout,
3723 uint32_t set,
3724 const void* pData)
3725 {
3726 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3727 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3728 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
3729 struct radv_descriptor_state *descriptors_state =
3730 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
3731 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3732
3733 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3734
3735 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3736 layout->set[set].layout,
3737 templ->bind_point))
3738 return;
3739
3740 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
3741 descriptorUpdateTemplate, pData);
3742
3743 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
3744 descriptors_state->push_dirty = true;
3745 }
3746
3747 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
3748 VkPipelineLayout layout,
3749 VkShaderStageFlags stageFlags,
3750 uint32_t offset,
3751 uint32_t size,
3752 const void* pValues)
3753 {
3754 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3755 memcpy(cmd_buffer->push_constants + offset, pValues, size);
3756 cmd_buffer->push_constant_stages |= stageFlags;
3757 }
3758
3759 VkResult radv_EndCommandBuffer(
3760 VkCommandBuffer commandBuffer)
3761 {
3762 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3763
3764 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
3765 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6)
3766 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WB_L2;
3767
3768 /* Make sure to sync all pending active queries at the end of
3769 * command buffer.
3770 */
3771 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
3772
3773 /* Since NGG streamout uses GDS, we need to make GDS idle when
3774 * we leave the IB, otherwise another process might overwrite
3775 * it while our shaders are busy.
3776 */
3777 if (cmd_buffer->gds_needed)
3778 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
3779
3780 si_emit_cache_flush(cmd_buffer);
3781 }
3782
3783 /* Make sure CP DMA is idle at the end of IBs because the kernel
3784 * doesn't wait for it.
3785 */
3786 si_cp_dma_wait_for_idle(cmd_buffer);
3787
3788 radv_describe_end_cmd_buffer(cmd_buffer);
3789
3790 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3791 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
3792
3793 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
3794 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3795
3796 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
3797
3798 return cmd_buffer->record_result;
3799 }
3800
3801 static void
3802 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
3803 {
3804 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3805
3806 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
3807 return;
3808
3809 assert(!pipeline->ctx_cs.cdw);
3810
3811 cmd_buffer->state.emitted_compute_pipeline = pipeline;
3812
3813 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
3814 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
3815
3816 cmd_buffer->compute_scratch_size_per_wave_needed = MAX2(cmd_buffer->compute_scratch_size_per_wave_needed,
3817 pipeline->scratch_bytes_per_wave);
3818 cmd_buffer->compute_scratch_waves_wanted = MAX2(cmd_buffer->compute_scratch_waves_wanted,
3819 pipeline->max_waves);
3820
3821 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3822 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
3823
3824 if (unlikely(cmd_buffer->device->trace_bo))
3825 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
3826 }
3827
3828 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
3829 VkPipelineBindPoint bind_point)
3830 {
3831 struct radv_descriptor_state *descriptors_state =
3832 radv_get_descriptors_state(cmd_buffer, bind_point);
3833
3834 descriptors_state->dirty |= descriptors_state->valid;
3835 }
3836
3837 void radv_CmdBindPipeline(
3838 VkCommandBuffer commandBuffer,
3839 VkPipelineBindPoint pipelineBindPoint,
3840 VkPipeline _pipeline)
3841 {
3842 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3843 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
3844
3845 switch (pipelineBindPoint) {
3846 case VK_PIPELINE_BIND_POINT_COMPUTE:
3847 if (cmd_buffer->state.compute_pipeline == pipeline)
3848 return;
3849 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3850
3851 cmd_buffer->state.compute_pipeline = pipeline;
3852 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
3853 break;
3854 case VK_PIPELINE_BIND_POINT_GRAPHICS:
3855 if (cmd_buffer->state.pipeline == pipeline)
3856 return;
3857 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3858
3859 cmd_buffer->state.pipeline = pipeline;
3860 if (!pipeline)
3861 break;
3862
3863 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
3864 cmd_buffer->push_constant_stages |= pipeline->active_stages;
3865
3866 /* the new vertex shader might not have the same user regs */
3867 cmd_buffer->state.last_first_instance = -1;
3868 cmd_buffer->state.last_vertex_offset = -1;
3869
3870 /* Prefetch all pipeline shaders at first draw time. */
3871 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
3872
3873 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX10 &&
3874 cmd_buffer->state.emitted_pipeline &&
3875 radv_pipeline_has_ngg(cmd_buffer->state.emitted_pipeline) &&
3876 !radv_pipeline_has_ngg(cmd_buffer->state.pipeline)) {
3877 /* Transitioning from NGG to legacy GS requires
3878 * VGT_FLUSH on Navi10-14. VGT_FLUSH is also emitted
3879 * at the beginning of IBs when legacy GS ring pointers
3880 * are set.
3881 */
3882 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
3883 }
3884
3885 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
3886 radv_bind_streamout_state(cmd_buffer, pipeline);
3887
3888 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
3889 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
3890 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
3891 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
3892
3893 if (radv_pipeline_has_tess(pipeline))
3894 cmd_buffer->tess_rings_needed = true;
3895 break;
3896 default:
3897 assert(!"invalid bind point");
3898 break;
3899 }
3900 }
3901
3902 void radv_CmdSetViewport(
3903 VkCommandBuffer commandBuffer,
3904 uint32_t firstViewport,
3905 uint32_t viewportCount,
3906 const VkViewport* pViewports)
3907 {
3908 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3909 struct radv_cmd_state *state = &cmd_buffer->state;
3910 ASSERTED const uint32_t total_count = firstViewport + viewportCount;
3911
3912 assert(firstViewport < MAX_VIEWPORTS);
3913 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
3914
3915 if (!memcmp(state->dynamic.viewport.viewports + firstViewport,
3916 pViewports, viewportCount * sizeof(*pViewports))) {
3917 return;
3918 }
3919
3920 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
3921 viewportCount * sizeof(*pViewports));
3922
3923 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
3924 }
3925
3926 void radv_CmdSetScissor(
3927 VkCommandBuffer commandBuffer,
3928 uint32_t firstScissor,
3929 uint32_t scissorCount,
3930 const VkRect2D* pScissors)
3931 {
3932 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3933 struct radv_cmd_state *state = &cmd_buffer->state;
3934 ASSERTED const uint32_t total_count = firstScissor + scissorCount;
3935
3936 assert(firstScissor < MAX_SCISSORS);
3937 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
3938
3939 if (!memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
3940 scissorCount * sizeof(*pScissors))) {
3941 return;
3942 }
3943
3944 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
3945 scissorCount * sizeof(*pScissors));
3946
3947 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
3948 }
3949
3950 void radv_CmdSetLineWidth(
3951 VkCommandBuffer commandBuffer,
3952 float lineWidth)
3953 {
3954 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3955
3956 if (cmd_buffer->state.dynamic.line_width == lineWidth)
3957 return;
3958
3959 cmd_buffer->state.dynamic.line_width = lineWidth;
3960 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
3961 }
3962
3963 void radv_CmdSetDepthBias(
3964 VkCommandBuffer commandBuffer,
3965 float depthBiasConstantFactor,
3966 float depthBiasClamp,
3967 float depthBiasSlopeFactor)
3968 {
3969 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3970 struct radv_cmd_state *state = &cmd_buffer->state;
3971
3972 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
3973 state->dynamic.depth_bias.clamp == depthBiasClamp &&
3974 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
3975 return;
3976 }
3977
3978 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
3979 state->dynamic.depth_bias.clamp = depthBiasClamp;
3980 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
3981
3982 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
3983 }
3984
3985 void radv_CmdSetBlendConstants(
3986 VkCommandBuffer commandBuffer,
3987 const float blendConstants[4])
3988 {
3989 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3990 struct radv_cmd_state *state = &cmd_buffer->state;
3991
3992 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
3993 return;
3994
3995 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
3996
3997 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
3998 }
3999
4000 void radv_CmdSetDepthBounds(
4001 VkCommandBuffer commandBuffer,
4002 float minDepthBounds,
4003 float maxDepthBounds)
4004 {
4005 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4006 struct radv_cmd_state *state = &cmd_buffer->state;
4007
4008 if (state->dynamic.depth_bounds.min == minDepthBounds &&
4009 state->dynamic.depth_bounds.max == maxDepthBounds) {
4010 return;
4011 }
4012
4013 state->dynamic.depth_bounds.min = minDepthBounds;
4014 state->dynamic.depth_bounds.max = maxDepthBounds;
4015
4016 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
4017 }
4018
4019 void radv_CmdSetStencilCompareMask(
4020 VkCommandBuffer commandBuffer,
4021 VkStencilFaceFlags faceMask,
4022 uint32_t compareMask)
4023 {
4024 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4025 struct radv_cmd_state *state = &cmd_buffer->state;
4026 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
4027 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
4028
4029 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4030 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4031 return;
4032 }
4033
4034 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4035 state->dynamic.stencil_compare_mask.front = compareMask;
4036 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4037 state->dynamic.stencil_compare_mask.back = compareMask;
4038
4039 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
4040 }
4041
4042 void radv_CmdSetStencilWriteMask(
4043 VkCommandBuffer commandBuffer,
4044 VkStencilFaceFlags faceMask,
4045 uint32_t writeMask)
4046 {
4047 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4048 struct radv_cmd_state *state = &cmd_buffer->state;
4049 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
4050 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
4051
4052 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4053 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4054 return;
4055 }
4056
4057 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4058 state->dynamic.stencil_write_mask.front = writeMask;
4059 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4060 state->dynamic.stencil_write_mask.back = writeMask;
4061
4062 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
4063 }
4064
4065 void radv_CmdSetStencilReference(
4066 VkCommandBuffer commandBuffer,
4067 VkStencilFaceFlags faceMask,
4068 uint32_t reference)
4069 {
4070 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4071 struct radv_cmd_state *state = &cmd_buffer->state;
4072 bool front_same = state->dynamic.stencil_reference.front == reference;
4073 bool back_same = state->dynamic.stencil_reference.back == reference;
4074
4075 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4076 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4077 return;
4078 }
4079
4080 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4081 cmd_buffer->state.dynamic.stencil_reference.front = reference;
4082 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4083 cmd_buffer->state.dynamic.stencil_reference.back = reference;
4084
4085 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
4086 }
4087
4088 void radv_CmdSetDiscardRectangleEXT(
4089 VkCommandBuffer commandBuffer,
4090 uint32_t firstDiscardRectangle,
4091 uint32_t discardRectangleCount,
4092 const VkRect2D* pDiscardRectangles)
4093 {
4094 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4095 struct radv_cmd_state *state = &cmd_buffer->state;
4096 ASSERTED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
4097
4098 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
4099 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
4100
4101 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
4102 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
4103 return;
4104 }
4105
4106 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
4107 pDiscardRectangles, discardRectangleCount);
4108
4109 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
4110 }
4111
4112 void radv_CmdSetSampleLocationsEXT(
4113 VkCommandBuffer commandBuffer,
4114 const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
4115 {
4116 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4117 struct radv_cmd_state *state = &cmd_buffer->state;
4118
4119 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
4120
4121 state->dynamic.sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
4122 state->dynamic.sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
4123 state->dynamic.sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
4124 typed_memcpy(&state->dynamic.sample_location.locations[0],
4125 pSampleLocationsInfo->pSampleLocations,
4126 pSampleLocationsInfo->sampleLocationsCount);
4127
4128 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS;
4129 }
4130
4131 void radv_CmdSetLineStippleEXT(
4132 VkCommandBuffer commandBuffer,
4133 uint32_t lineStippleFactor,
4134 uint16_t lineStipplePattern)
4135 {
4136 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4137 struct radv_cmd_state *state = &cmd_buffer->state;
4138
4139 state->dynamic.line_stipple.factor = lineStippleFactor;
4140 state->dynamic.line_stipple.pattern = lineStipplePattern;
4141
4142 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE;
4143 }
4144
4145 void radv_CmdExecuteCommands(
4146 VkCommandBuffer commandBuffer,
4147 uint32_t commandBufferCount,
4148 const VkCommandBuffer* pCmdBuffers)
4149 {
4150 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
4151
4152 assert(commandBufferCount > 0);
4153
4154 /* Emit pending flushes on primary prior to executing secondary */
4155 si_emit_cache_flush(primary);
4156
4157 for (uint32_t i = 0; i < commandBufferCount; i++) {
4158 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
4159
4160 primary->scratch_size_per_wave_needed = MAX2(primary->scratch_size_per_wave_needed,
4161 secondary->scratch_size_per_wave_needed);
4162 primary->scratch_waves_wanted = MAX2(primary->scratch_waves_wanted,
4163 secondary->scratch_waves_wanted);
4164 primary->compute_scratch_size_per_wave_needed = MAX2(primary->compute_scratch_size_per_wave_needed,
4165 secondary->compute_scratch_size_per_wave_needed);
4166 primary->compute_scratch_waves_wanted = MAX2(primary->compute_scratch_waves_wanted,
4167 secondary->compute_scratch_waves_wanted);
4168
4169 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
4170 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
4171 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
4172 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
4173 if (secondary->tess_rings_needed)
4174 primary->tess_rings_needed = true;
4175 if (secondary->sample_positions_needed)
4176 primary->sample_positions_needed = true;
4177 if (secondary->gds_needed)
4178 primary->gds_needed = true;
4179
4180 if (!secondary->state.framebuffer &&
4181 (primary->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)) {
4182 /* Emit the framebuffer state from primary if secondary
4183 * has been recorded without a framebuffer, otherwise
4184 * fast color/depth clears can't work.
4185 */
4186 radv_emit_framebuffer_state(primary);
4187 }
4188
4189 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
4190
4191
4192 /* When the secondary command buffer is compute only we don't
4193 * need to re-emit the current graphics pipeline.
4194 */
4195 if (secondary->state.emitted_pipeline) {
4196 primary->state.emitted_pipeline =
4197 secondary->state.emitted_pipeline;
4198 }
4199
4200 /* When the secondary command buffer is graphics only we don't
4201 * need to re-emit the current compute pipeline.
4202 */
4203 if (secondary->state.emitted_compute_pipeline) {
4204 primary->state.emitted_compute_pipeline =
4205 secondary->state.emitted_compute_pipeline;
4206 }
4207
4208 /* Only re-emit the draw packets when needed. */
4209 if (secondary->state.last_primitive_reset_en != -1) {
4210 primary->state.last_primitive_reset_en =
4211 secondary->state.last_primitive_reset_en;
4212 }
4213
4214 if (secondary->state.last_primitive_reset_index) {
4215 primary->state.last_primitive_reset_index =
4216 secondary->state.last_primitive_reset_index;
4217 }
4218
4219 if (secondary->state.last_ia_multi_vgt_param) {
4220 primary->state.last_ia_multi_vgt_param =
4221 secondary->state.last_ia_multi_vgt_param;
4222 }
4223
4224 primary->state.last_first_instance = secondary->state.last_first_instance;
4225 primary->state.last_num_instances = secondary->state.last_num_instances;
4226 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
4227 primary->state.last_sx_ps_downconvert = secondary->state.last_sx_ps_downconvert;
4228 primary->state.last_sx_blend_opt_epsilon = secondary->state.last_sx_blend_opt_epsilon;
4229 primary->state.last_sx_blend_opt_control = secondary->state.last_sx_blend_opt_control;
4230
4231 if (secondary->state.last_index_type != -1) {
4232 primary->state.last_index_type =
4233 secondary->state.last_index_type;
4234 }
4235 }
4236
4237 /* After executing commands from secondary buffers we have to dirty
4238 * some states.
4239 */
4240 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
4241 RADV_CMD_DIRTY_INDEX_BUFFER |
4242 RADV_CMD_DIRTY_DYNAMIC_ALL;
4243 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
4244 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
4245 }
4246
4247 VkResult radv_CreateCommandPool(
4248 VkDevice _device,
4249 const VkCommandPoolCreateInfo* pCreateInfo,
4250 const VkAllocationCallbacks* pAllocator,
4251 VkCommandPool* pCmdPool)
4252 {
4253 RADV_FROM_HANDLE(radv_device, device, _device);
4254 struct radv_cmd_pool *pool;
4255
4256 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
4257 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4258 if (pool == NULL)
4259 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4260
4261 if (pAllocator)
4262 pool->alloc = *pAllocator;
4263 else
4264 pool->alloc = device->alloc;
4265
4266 list_inithead(&pool->cmd_buffers);
4267 list_inithead(&pool->free_cmd_buffers);
4268
4269 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
4270
4271 *pCmdPool = radv_cmd_pool_to_handle(pool);
4272
4273 return VK_SUCCESS;
4274
4275 }
4276
4277 void radv_DestroyCommandPool(
4278 VkDevice _device,
4279 VkCommandPool commandPool,
4280 const VkAllocationCallbacks* pAllocator)
4281 {
4282 RADV_FROM_HANDLE(radv_device, device, _device);
4283 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4284
4285 if (!pool)
4286 return;
4287
4288 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4289 &pool->cmd_buffers, pool_link) {
4290 radv_cmd_buffer_destroy(cmd_buffer);
4291 }
4292
4293 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4294 &pool->free_cmd_buffers, pool_link) {
4295 radv_cmd_buffer_destroy(cmd_buffer);
4296 }
4297
4298 vk_free2(&device->alloc, pAllocator, pool);
4299 }
4300
4301 VkResult radv_ResetCommandPool(
4302 VkDevice device,
4303 VkCommandPool commandPool,
4304 VkCommandPoolResetFlags flags)
4305 {
4306 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4307 VkResult result;
4308
4309 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
4310 &pool->cmd_buffers, pool_link) {
4311 result = radv_reset_cmd_buffer(cmd_buffer);
4312 if (result != VK_SUCCESS)
4313 return result;
4314 }
4315
4316 return VK_SUCCESS;
4317 }
4318
4319 void radv_TrimCommandPool(
4320 VkDevice device,
4321 VkCommandPool commandPool,
4322 VkCommandPoolTrimFlags flags)
4323 {
4324 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4325
4326 if (!pool)
4327 return;
4328
4329 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4330 &pool->free_cmd_buffers, pool_link) {
4331 radv_cmd_buffer_destroy(cmd_buffer);
4332 }
4333 }
4334
4335 static void
4336 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
4337 uint32_t subpass_id)
4338 {
4339 struct radv_cmd_state *state = &cmd_buffer->state;
4340 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
4341
4342 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
4343 cmd_buffer->cs, 4096);
4344
4345 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
4346
4347 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
4348
4349 radv_describe_barrier_start(cmd_buffer, RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC);
4350
4351 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4352 const uint32_t a = subpass->attachments[i].attachment;
4353 if (a == VK_ATTACHMENT_UNUSED)
4354 continue;
4355
4356 radv_handle_subpass_image_transition(cmd_buffer,
4357 subpass->attachments[i],
4358 true);
4359 }
4360
4361 radv_describe_barrier_end(cmd_buffer);
4362
4363 radv_cmd_buffer_clear_subpass(cmd_buffer);
4364
4365 assert(cmd_buffer->cs->cdw <= cdw_max);
4366 }
4367
4368 static void
4369 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
4370 {
4371 struct radv_cmd_state *state = &cmd_buffer->state;
4372 const struct radv_subpass *subpass = state->subpass;
4373 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
4374
4375 radv_cmd_buffer_resolve_subpass(cmd_buffer);
4376
4377 radv_describe_barrier_start(cmd_buffer, RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC);
4378
4379 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4380 const uint32_t a = subpass->attachments[i].attachment;
4381 if (a == VK_ATTACHMENT_UNUSED)
4382 continue;
4383
4384 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
4385 continue;
4386
4387 VkImageLayout layout = state->pass->attachments[a].final_layout;
4388 VkImageLayout stencil_layout = state->pass->attachments[a].stencil_final_layout;
4389 struct radv_subpass_attachment att = { a, layout, stencil_layout };
4390 radv_handle_subpass_image_transition(cmd_buffer, att, false);
4391 }
4392
4393 radv_describe_barrier_end(cmd_buffer);
4394 }
4395
4396 void
4397 radv_cmd_buffer_begin_render_pass(struct radv_cmd_buffer *cmd_buffer,
4398 const VkRenderPassBeginInfo *pRenderPassBegin)
4399 {
4400 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
4401 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
4402 VkResult result;
4403
4404 cmd_buffer->state.framebuffer = framebuffer;
4405 cmd_buffer->state.pass = pass;
4406 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
4407
4408 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
4409 if (result != VK_SUCCESS)
4410 return;
4411
4412 result = radv_cmd_state_setup_sample_locations(cmd_buffer, pass, pRenderPassBegin);
4413 if (result != VK_SUCCESS)
4414 return;
4415 }
4416
4417 void radv_CmdBeginRenderPass(
4418 VkCommandBuffer commandBuffer,
4419 const VkRenderPassBeginInfo* pRenderPassBegin,
4420 VkSubpassContents contents)
4421 {
4422 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4423
4424 radv_cmd_buffer_begin_render_pass(cmd_buffer, pRenderPassBegin);
4425
4426 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
4427 }
4428
4429 void radv_CmdBeginRenderPass2(
4430 VkCommandBuffer commandBuffer,
4431 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
4432 const VkSubpassBeginInfo* pSubpassBeginInfo)
4433 {
4434 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
4435 pSubpassBeginInfo->contents);
4436 }
4437
4438 void radv_CmdNextSubpass(
4439 VkCommandBuffer commandBuffer,
4440 VkSubpassContents contents)
4441 {
4442 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4443
4444 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
4445 radv_cmd_buffer_end_subpass(cmd_buffer);
4446 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
4447 }
4448
4449 void radv_CmdNextSubpass2(
4450 VkCommandBuffer commandBuffer,
4451 const VkSubpassBeginInfo* pSubpassBeginInfo,
4452 const VkSubpassEndInfo* pSubpassEndInfo)
4453 {
4454 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
4455 }
4456
4457 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
4458 {
4459 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
4460 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
4461 if (!radv_get_shader(pipeline, stage))
4462 continue;
4463
4464 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
4465 if (loc->sgpr_idx == -1)
4466 continue;
4467 uint32_t base_reg = pipeline->user_data_0[stage];
4468 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4469
4470 }
4471 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
4472 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
4473 if (loc->sgpr_idx != -1) {
4474 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
4475 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4476 }
4477 }
4478 }
4479
4480 static void
4481 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4482 uint32_t vertex_count,
4483 bool use_opaque)
4484 {
4485 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
4486 radeon_emit(cmd_buffer->cs, vertex_count);
4487 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
4488 S_0287F0_USE_OPAQUE(use_opaque));
4489 }
4490
4491 static void
4492 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
4493 uint64_t index_va,
4494 uint32_t index_count)
4495 {
4496 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
4497 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
4498 radeon_emit(cmd_buffer->cs, index_va);
4499 radeon_emit(cmd_buffer->cs, index_va >> 32);
4500 radeon_emit(cmd_buffer->cs, index_count);
4501 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
4502 }
4503
4504 static void
4505 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4506 bool indexed,
4507 uint32_t draw_count,
4508 uint64_t count_va,
4509 uint32_t stride)
4510 {
4511 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4512 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
4513 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
4514 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id;
4515 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
4516 bool predicating = cmd_buffer->state.predicating;
4517 assert(base_reg);
4518
4519 /* just reset draw state for vertex data */
4520 cmd_buffer->state.last_first_instance = -1;
4521 cmd_buffer->state.last_num_instances = -1;
4522 cmd_buffer->state.last_vertex_offset = -1;
4523
4524 if (draw_count == 1 && !count_va && !draw_id_enable) {
4525 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
4526 PKT3_DRAW_INDIRECT, 3, predicating));
4527 radeon_emit(cs, 0);
4528 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4529 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4530 radeon_emit(cs, di_src_sel);
4531 } else {
4532 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
4533 PKT3_DRAW_INDIRECT_MULTI,
4534 8, predicating));
4535 radeon_emit(cs, 0);
4536 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4537 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4538 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
4539 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
4540 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
4541 radeon_emit(cs, draw_count); /* count */
4542 radeon_emit(cs, count_va); /* count_addr */
4543 radeon_emit(cs, count_va >> 32);
4544 radeon_emit(cs, stride); /* stride */
4545 radeon_emit(cs, di_src_sel);
4546 }
4547 }
4548
4549 static void
4550 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
4551 const struct radv_draw_info *info)
4552 {
4553 struct radv_cmd_state *state = &cmd_buffer->state;
4554 struct radeon_winsys *ws = cmd_buffer->device->ws;
4555 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4556
4557 if (info->indirect) {
4558 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4559 uint64_t count_va = 0;
4560
4561 va += info->indirect->offset + info->indirect_offset;
4562
4563 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4564
4565 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
4566 radeon_emit(cs, 1);
4567 radeon_emit(cs, va);
4568 radeon_emit(cs, va >> 32);
4569
4570 if (info->count_buffer) {
4571 count_va = radv_buffer_get_va(info->count_buffer->bo);
4572 count_va += info->count_buffer->offset +
4573 info->count_buffer_offset;
4574
4575 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
4576 }
4577
4578 if (!state->subpass->view_mask) {
4579 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4580 info->indexed,
4581 info->count,
4582 count_va,
4583 info->stride);
4584 } else {
4585 unsigned i;
4586 for_each_bit(i, state->subpass->view_mask) {
4587 radv_emit_view_index(cmd_buffer, i);
4588
4589 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4590 info->indexed,
4591 info->count,
4592 count_va,
4593 info->stride);
4594 }
4595 }
4596 } else {
4597 assert(state->pipeline->graphics.vtx_base_sgpr);
4598
4599 if (info->vertex_offset != state->last_vertex_offset ||
4600 info->first_instance != state->last_first_instance) {
4601 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
4602 state->pipeline->graphics.vtx_emit_num);
4603
4604 radeon_emit(cs, info->vertex_offset);
4605 radeon_emit(cs, info->first_instance);
4606 if (state->pipeline->graphics.vtx_emit_num == 3)
4607 radeon_emit(cs, 0);
4608 state->last_first_instance = info->first_instance;
4609 state->last_vertex_offset = info->vertex_offset;
4610 }
4611
4612 if (state->last_num_instances != info->instance_count) {
4613 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
4614 radeon_emit(cs, info->instance_count);
4615 state->last_num_instances = info->instance_count;
4616 }
4617
4618 if (info->indexed) {
4619 int index_size = radv_get_vgt_index_size(state->index_type);
4620 uint64_t index_va;
4621
4622 /* Skip draw calls with 0-sized index buffers. They
4623 * cause a hang on some chips, like Navi10-14.
4624 */
4625 if (!cmd_buffer->state.max_index_count)
4626 return;
4627
4628 index_va = state->index_va;
4629 index_va += info->first_index * index_size;
4630
4631 if (!state->subpass->view_mask) {
4632 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4633 index_va,
4634 info->count);
4635 } else {
4636 unsigned i;
4637 for_each_bit(i, state->subpass->view_mask) {
4638 radv_emit_view_index(cmd_buffer, i);
4639
4640 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4641 index_va,
4642 info->count);
4643 }
4644 }
4645 } else {
4646 if (!state->subpass->view_mask) {
4647 radv_cs_emit_draw_packet(cmd_buffer,
4648 info->count,
4649 !!info->strmout_buffer);
4650 } else {
4651 unsigned i;
4652 for_each_bit(i, state->subpass->view_mask) {
4653 radv_emit_view_index(cmd_buffer, i);
4654
4655 radv_cs_emit_draw_packet(cmd_buffer,
4656 info->count,
4657 !!info->strmout_buffer);
4658 }
4659 }
4660 }
4661 }
4662 }
4663
4664 /*
4665 * Vega and raven have a bug which triggers if there are multiple context
4666 * register contexts active at the same time with different scissor values.
4667 *
4668 * There are two possible workarounds:
4669 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
4670 * there is only ever 1 active set of scissor values at the same time.
4671 *
4672 * 2) Whenever the hardware switches contexts we have to set the scissor
4673 * registers again even if it is a noop. That way the new context gets
4674 * the correct scissor values.
4675 *
4676 * This implements option 2. radv_need_late_scissor_emission needs to
4677 * return true on affected HW if radv_emit_all_graphics_states sets
4678 * any context registers.
4679 */
4680 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
4681 const struct radv_draw_info *info)
4682 {
4683 struct radv_cmd_state *state = &cmd_buffer->state;
4684
4685 if (!cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
4686 return false;
4687
4688 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
4689 return true;
4690
4691 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
4692
4693 /* Index, vertex and streamout buffers don't change context regs, and
4694 * pipeline is already handled.
4695 */
4696 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
4697 RADV_CMD_DIRTY_VERTEX_BUFFER |
4698 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
4699 RADV_CMD_DIRTY_PIPELINE);
4700
4701 if (cmd_buffer->state.dirty & used_states)
4702 return true;
4703
4704 uint32_t primitive_reset_index =
4705 radv_get_primitive_reset_index(cmd_buffer);
4706
4707 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
4708 primitive_reset_index != state->last_primitive_reset_index)
4709 return true;
4710
4711 return false;
4712 }
4713
4714 static void
4715 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
4716 const struct radv_draw_info *info)
4717 {
4718 bool late_scissor_emission;
4719
4720 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
4721 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
4722 radv_emit_rbplus_state(cmd_buffer);
4723
4724 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
4725 radv_emit_graphics_pipeline(cmd_buffer);
4726
4727 /* This should be before the cmd_buffer->state.dirty is cleared
4728 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4729 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4730 late_scissor_emission =
4731 radv_need_late_scissor_emission(cmd_buffer, info);
4732
4733 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
4734 radv_emit_framebuffer_state(cmd_buffer);
4735
4736 if (info->indexed) {
4737 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
4738 radv_emit_index_buffer(cmd_buffer, info->indirect);
4739 } else {
4740 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4741 * so the state must be re-emitted before the next indexed
4742 * draw.
4743 */
4744 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
4745 cmd_buffer->state.last_index_type = -1;
4746 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
4747 }
4748 }
4749
4750 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
4751
4752 radv_emit_draw_registers(cmd_buffer, info);
4753
4754 if (late_scissor_emission)
4755 radv_emit_scissor(cmd_buffer);
4756 }
4757
4758 static void
4759 radv_draw(struct radv_cmd_buffer *cmd_buffer,
4760 const struct radv_draw_info *info)
4761 {
4762 struct radeon_info *rad_info =
4763 &cmd_buffer->device->physical_device->rad_info;
4764 bool has_prefetch =
4765 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4766 bool pipeline_is_dirty =
4767 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
4768 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
4769
4770 ASSERTED unsigned cdw_max =
4771 radeon_check_space(cmd_buffer->device->ws,
4772 cmd_buffer->cs, 4096);
4773
4774 if (likely(!info->indirect)) {
4775 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4776 * no workaround for indirect draws, but we can at least skip
4777 * direct draws.
4778 */
4779 if (unlikely(!info->instance_count))
4780 return;
4781
4782 /* Handle count == 0. */
4783 if (unlikely(!info->count && !info->strmout_buffer))
4784 return;
4785 }
4786
4787 radv_describe_draw(cmd_buffer);
4788
4789 /* Use optimal packet order based on whether we need to sync the
4790 * pipeline.
4791 */
4792 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4793 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4794 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4795 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4796 /* If we have to wait for idle, set all states first, so that
4797 * all SET packets are processed in parallel with previous draw
4798 * calls. Then upload descriptors, set shader pointers, and
4799 * draw, and prefetch at the end. This ensures that the time
4800 * the CUs are idle is very short. (there are only SET_SH
4801 * packets between the wait and the draw)
4802 */
4803 radv_emit_all_graphics_states(cmd_buffer, info);
4804 si_emit_cache_flush(cmd_buffer);
4805 /* <-- CUs are idle here --> */
4806
4807 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4808
4809 radv_emit_draw_packets(cmd_buffer, info);
4810 /* <-- CUs are busy here --> */
4811
4812 /* Start prefetches after the draw has been started. Both will
4813 * run in parallel, but starting the draw first is more
4814 * important.
4815 */
4816 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4817 radv_emit_prefetch_L2(cmd_buffer,
4818 cmd_buffer->state.pipeline, false);
4819 }
4820 } else {
4821 /* If we don't wait for idle, start prefetches first, then set
4822 * states, and draw at the end.
4823 */
4824 si_emit_cache_flush(cmd_buffer);
4825
4826 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4827 /* Only prefetch the vertex shader and VBO descriptors
4828 * in order to start the draw as soon as possible.
4829 */
4830 radv_emit_prefetch_L2(cmd_buffer,
4831 cmd_buffer->state.pipeline, true);
4832 }
4833
4834 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4835
4836 radv_emit_all_graphics_states(cmd_buffer, info);
4837 radv_emit_draw_packets(cmd_buffer, info);
4838
4839 /* Prefetch the remaining shaders after the draw has been
4840 * started.
4841 */
4842 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4843 radv_emit_prefetch_L2(cmd_buffer,
4844 cmd_buffer->state.pipeline, false);
4845 }
4846 }
4847
4848 /* Workaround for a VGT hang when streamout is enabled.
4849 * It must be done after drawing.
4850 */
4851 if (cmd_buffer->state.streamout.streamout_enabled &&
4852 (rad_info->family == CHIP_HAWAII ||
4853 rad_info->family == CHIP_TONGA ||
4854 rad_info->family == CHIP_FIJI)) {
4855 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
4856 }
4857
4858 assert(cmd_buffer->cs->cdw <= cdw_max);
4859 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
4860 }
4861
4862 void radv_CmdDraw(
4863 VkCommandBuffer commandBuffer,
4864 uint32_t vertexCount,
4865 uint32_t instanceCount,
4866 uint32_t firstVertex,
4867 uint32_t firstInstance)
4868 {
4869 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4870 struct radv_draw_info info = {};
4871
4872 info.count = vertexCount;
4873 info.instance_count = instanceCount;
4874 info.first_instance = firstInstance;
4875 info.vertex_offset = firstVertex;
4876
4877 radv_draw(cmd_buffer, &info);
4878 }
4879
4880 void radv_CmdDrawIndexed(
4881 VkCommandBuffer commandBuffer,
4882 uint32_t indexCount,
4883 uint32_t instanceCount,
4884 uint32_t firstIndex,
4885 int32_t vertexOffset,
4886 uint32_t firstInstance)
4887 {
4888 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4889 struct radv_draw_info info = {};
4890
4891 info.indexed = true;
4892 info.count = indexCount;
4893 info.instance_count = instanceCount;
4894 info.first_index = firstIndex;
4895 info.vertex_offset = vertexOffset;
4896 info.first_instance = firstInstance;
4897
4898 radv_draw(cmd_buffer, &info);
4899 }
4900
4901 void radv_CmdDrawIndirect(
4902 VkCommandBuffer commandBuffer,
4903 VkBuffer _buffer,
4904 VkDeviceSize offset,
4905 uint32_t drawCount,
4906 uint32_t stride)
4907 {
4908 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4909 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4910 struct radv_draw_info info = {};
4911
4912 info.count = drawCount;
4913 info.indirect = buffer;
4914 info.indirect_offset = offset;
4915 info.stride = stride;
4916
4917 radv_draw(cmd_buffer, &info);
4918 }
4919
4920 void radv_CmdDrawIndexedIndirect(
4921 VkCommandBuffer commandBuffer,
4922 VkBuffer _buffer,
4923 VkDeviceSize offset,
4924 uint32_t drawCount,
4925 uint32_t stride)
4926 {
4927 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4928 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4929 struct radv_draw_info info = {};
4930
4931 info.indexed = true;
4932 info.count = drawCount;
4933 info.indirect = buffer;
4934 info.indirect_offset = offset;
4935 info.stride = stride;
4936
4937 radv_draw(cmd_buffer, &info);
4938 }
4939
4940 void radv_CmdDrawIndirectCount(
4941 VkCommandBuffer commandBuffer,
4942 VkBuffer _buffer,
4943 VkDeviceSize offset,
4944 VkBuffer _countBuffer,
4945 VkDeviceSize countBufferOffset,
4946 uint32_t maxDrawCount,
4947 uint32_t stride)
4948 {
4949 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4950 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4951 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4952 struct radv_draw_info info = {};
4953
4954 info.count = maxDrawCount;
4955 info.indirect = buffer;
4956 info.indirect_offset = offset;
4957 info.count_buffer = count_buffer;
4958 info.count_buffer_offset = countBufferOffset;
4959 info.stride = stride;
4960
4961 radv_draw(cmd_buffer, &info);
4962 }
4963
4964 void radv_CmdDrawIndexedIndirectCount(
4965 VkCommandBuffer commandBuffer,
4966 VkBuffer _buffer,
4967 VkDeviceSize offset,
4968 VkBuffer _countBuffer,
4969 VkDeviceSize countBufferOffset,
4970 uint32_t maxDrawCount,
4971 uint32_t stride)
4972 {
4973 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4974 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4975 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4976 struct radv_draw_info info = {};
4977
4978 info.indexed = true;
4979 info.count = maxDrawCount;
4980 info.indirect = buffer;
4981 info.indirect_offset = offset;
4982 info.count_buffer = count_buffer;
4983 info.count_buffer_offset = countBufferOffset;
4984 info.stride = stride;
4985
4986 radv_draw(cmd_buffer, &info);
4987 }
4988
4989 struct radv_dispatch_info {
4990 /**
4991 * Determine the layout of the grid (in block units) to be used.
4992 */
4993 uint32_t blocks[3];
4994
4995 /**
4996 * A starting offset for the grid. If unaligned is set, the offset
4997 * must still be aligned.
4998 */
4999 uint32_t offsets[3];
5000 /**
5001 * Whether it's an unaligned compute dispatch.
5002 */
5003 bool unaligned;
5004
5005 /**
5006 * Indirect compute parameters resource.
5007 */
5008 struct radv_buffer *indirect;
5009 uint64_t indirect_offset;
5010 };
5011
5012 static void
5013 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
5014 const struct radv_dispatch_info *info)
5015 {
5016 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
5017 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
5018 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
5019 struct radeon_winsys *ws = cmd_buffer->device->ws;
5020 bool predicating = cmd_buffer->state.predicating;
5021 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5022 struct radv_userdata_info *loc;
5023
5024 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
5025 AC_UD_CS_GRID_SIZE);
5026
5027 ASSERTED unsigned cdw_max = radeon_check_space(ws, cs, 25);
5028
5029 if (compute_shader->info.wave_size == 32) {
5030 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
5031 dispatch_initiator |= S_00B800_CS_W32_EN(1);
5032 }
5033
5034 if (info->indirect) {
5035 uint64_t va = radv_buffer_get_va(info->indirect->bo);
5036
5037 va += info->indirect->offset + info->indirect_offset;
5038
5039 radv_cs_add_buffer(ws, cs, info->indirect->bo);
5040
5041 if (loc->sgpr_idx != -1) {
5042 for (unsigned i = 0; i < 3; ++i) {
5043 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5044 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5045 COPY_DATA_DST_SEL(COPY_DATA_REG));
5046 radeon_emit(cs, (va + 4 * i));
5047 radeon_emit(cs, (va + 4 * i) >> 32);
5048 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
5049 + loc->sgpr_idx * 4) >> 2) + i);
5050 radeon_emit(cs, 0);
5051 }
5052 }
5053
5054 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
5055 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
5056 PKT3_SHADER_TYPE_S(1));
5057 radeon_emit(cs, va);
5058 radeon_emit(cs, va >> 32);
5059 radeon_emit(cs, dispatch_initiator);
5060 } else {
5061 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
5062 PKT3_SHADER_TYPE_S(1));
5063 radeon_emit(cs, 1);
5064 radeon_emit(cs, va);
5065 radeon_emit(cs, va >> 32);
5066
5067 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
5068 PKT3_SHADER_TYPE_S(1));
5069 radeon_emit(cs, 0);
5070 radeon_emit(cs, dispatch_initiator);
5071 }
5072 } else {
5073 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
5074 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
5075
5076 if (info->unaligned) {
5077 unsigned *cs_block_size = compute_shader->info.cs.block_size;
5078 unsigned remainder[3];
5079
5080 /* If aligned, these should be an entire block size,
5081 * not 0.
5082 */
5083 remainder[0] = blocks[0] + cs_block_size[0] -
5084 align_u32_npot(blocks[0], cs_block_size[0]);
5085 remainder[1] = blocks[1] + cs_block_size[1] -
5086 align_u32_npot(blocks[1], cs_block_size[1]);
5087 remainder[2] = blocks[2] + cs_block_size[2] -
5088 align_u32_npot(blocks[2], cs_block_size[2]);
5089
5090 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
5091 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
5092 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
5093
5094 for(unsigned i = 0; i < 3; ++i) {
5095 assert(offsets[i] % cs_block_size[i] == 0);
5096 offsets[i] /= cs_block_size[i];
5097 }
5098
5099 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
5100 radeon_emit(cs,
5101 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
5102 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
5103 radeon_emit(cs,
5104 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
5105 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
5106 radeon_emit(cs,
5107 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
5108 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
5109
5110 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
5111 }
5112
5113 if (loc->sgpr_idx != -1) {
5114 assert(loc->num_sgprs == 3);
5115
5116 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
5117 loc->sgpr_idx * 4, 3);
5118 radeon_emit(cs, blocks[0]);
5119 radeon_emit(cs, blocks[1]);
5120 radeon_emit(cs, blocks[2]);
5121 }
5122
5123 if (offsets[0] || offsets[1] || offsets[2]) {
5124 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
5125 radeon_emit(cs, offsets[0]);
5126 radeon_emit(cs, offsets[1]);
5127 radeon_emit(cs, offsets[2]);
5128
5129 /* The blocks in the packet are not counts but end values. */
5130 for (unsigned i = 0; i < 3; ++i)
5131 blocks[i] += offsets[i];
5132 } else {
5133 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
5134 }
5135
5136 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
5137 PKT3_SHADER_TYPE_S(1));
5138 radeon_emit(cs, blocks[0]);
5139 radeon_emit(cs, blocks[1]);
5140 radeon_emit(cs, blocks[2]);
5141 radeon_emit(cs, dispatch_initiator);
5142 }
5143
5144 assert(cmd_buffer->cs->cdw <= cdw_max);
5145 }
5146
5147 static void
5148 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
5149 {
5150 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
5151 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
5152 }
5153
5154 static void
5155 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
5156 const struct radv_dispatch_info *info)
5157 {
5158 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
5159 bool has_prefetch =
5160 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
5161 bool pipeline_is_dirty = pipeline &&
5162 pipeline != cmd_buffer->state.emitted_compute_pipeline;
5163
5164 radv_describe_dispatch(cmd_buffer, 8, 8, 8);
5165
5166 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5167 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5168 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
5169 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
5170 /* If we have to wait for idle, set all states first, so that
5171 * all SET packets are processed in parallel with previous draw
5172 * calls. Then upload descriptors, set shader pointers, and
5173 * dispatch, and prefetch at the end. This ensures that the
5174 * time the CUs are idle is very short. (there are only SET_SH
5175 * packets between the wait and the draw)
5176 */
5177 radv_emit_compute_pipeline(cmd_buffer);
5178 si_emit_cache_flush(cmd_buffer);
5179 /* <-- CUs are idle here --> */
5180
5181 radv_upload_compute_shader_descriptors(cmd_buffer);
5182
5183 radv_emit_dispatch_packets(cmd_buffer, info);
5184 /* <-- CUs are busy here --> */
5185
5186 /* Start prefetches after the dispatch has been started. Both
5187 * will run in parallel, but starting the dispatch first is
5188 * more important.
5189 */
5190 if (has_prefetch && pipeline_is_dirty) {
5191 radv_emit_shader_prefetch(cmd_buffer,
5192 pipeline->shaders[MESA_SHADER_COMPUTE]);
5193 }
5194 } else {
5195 /* If we don't wait for idle, start prefetches first, then set
5196 * states, and dispatch at the end.
5197 */
5198 si_emit_cache_flush(cmd_buffer);
5199
5200 if (has_prefetch && pipeline_is_dirty) {
5201 radv_emit_shader_prefetch(cmd_buffer,
5202 pipeline->shaders[MESA_SHADER_COMPUTE]);
5203 }
5204
5205 radv_upload_compute_shader_descriptors(cmd_buffer);
5206
5207 radv_emit_compute_pipeline(cmd_buffer);
5208 radv_emit_dispatch_packets(cmd_buffer, info);
5209 }
5210
5211 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
5212 }
5213
5214 void radv_CmdDispatchBase(
5215 VkCommandBuffer commandBuffer,
5216 uint32_t base_x,
5217 uint32_t base_y,
5218 uint32_t base_z,
5219 uint32_t x,
5220 uint32_t y,
5221 uint32_t z)
5222 {
5223 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5224 struct radv_dispatch_info info = {};
5225
5226 info.blocks[0] = x;
5227 info.blocks[1] = y;
5228 info.blocks[2] = z;
5229
5230 info.offsets[0] = base_x;
5231 info.offsets[1] = base_y;
5232 info.offsets[2] = base_z;
5233 radv_dispatch(cmd_buffer, &info);
5234 }
5235
5236 void radv_CmdDispatch(
5237 VkCommandBuffer commandBuffer,
5238 uint32_t x,
5239 uint32_t y,
5240 uint32_t z)
5241 {
5242 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
5243 }
5244
5245 void radv_CmdDispatchIndirect(
5246 VkCommandBuffer commandBuffer,
5247 VkBuffer _buffer,
5248 VkDeviceSize offset)
5249 {
5250 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5251 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5252 struct radv_dispatch_info info = {};
5253
5254 info.indirect = buffer;
5255 info.indirect_offset = offset;
5256
5257 radv_dispatch(cmd_buffer, &info);
5258 }
5259
5260 void radv_unaligned_dispatch(
5261 struct radv_cmd_buffer *cmd_buffer,
5262 uint32_t x,
5263 uint32_t y,
5264 uint32_t z)
5265 {
5266 struct radv_dispatch_info info = {};
5267
5268 info.blocks[0] = x;
5269 info.blocks[1] = y;
5270 info.blocks[2] = z;
5271 info.unaligned = 1;
5272
5273 radv_dispatch(cmd_buffer, &info);
5274 }
5275
5276 void
5277 radv_cmd_buffer_end_render_pass(struct radv_cmd_buffer *cmd_buffer)
5278 {
5279 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
5280 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
5281
5282 cmd_buffer->state.pass = NULL;
5283 cmd_buffer->state.subpass = NULL;
5284 cmd_buffer->state.attachments = NULL;
5285 cmd_buffer->state.framebuffer = NULL;
5286 cmd_buffer->state.subpass_sample_locs = NULL;
5287 }
5288
5289 void radv_CmdEndRenderPass(
5290 VkCommandBuffer commandBuffer)
5291 {
5292 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5293
5294 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
5295
5296 radv_cmd_buffer_end_subpass(cmd_buffer);
5297
5298 radv_cmd_buffer_end_render_pass(cmd_buffer);
5299 }
5300
5301 void radv_CmdEndRenderPass2(
5302 VkCommandBuffer commandBuffer,
5303 const VkSubpassEndInfo* pSubpassEndInfo)
5304 {
5305 radv_CmdEndRenderPass(commandBuffer);
5306 }
5307
5308 /*
5309 * For HTILE we have the following interesting clear words:
5310 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
5311 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
5312 * 0xfffffff0: Clear depth to 1.0
5313 * 0x00000000: Clear depth to 0.0
5314 */
5315 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
5316 struct radv_image *image,
5317 const VkImageSubresourceRange *range)
5318 {
5319 assert(range->baseMipLevel == 0);
5320 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
5321 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
5322 struct radv_cmd_state *state = &cmd_buffer->state;
5323 uint32_t htile_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
5324 VkClearDepthStencilValue value = {};
5325 struct radv_barrier_data barrier = {};
5326
5327 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5328 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5329
5330 barrier.layout_transitions.init_mask_ram = 1;
5331 radv_describe_layout_transition(cmd_buffer, &barrier);
5332
5333 state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, htile_value);
5334
5335 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5336
5337 if (vk_format_is_stencil(image->vk_format))
5338 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
5339
5340 radv_set_ds_clear_metadata(cmd_buffer, image, range, value, aspects);
5341
5342 if (radv_image_is_tc_compat_htile(image)) {
5343 /* Initialize the TC-compat metada value to 0 because by
5344 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
5345 * need have to conditionally update its value when performing
5346 * a fast depth clear.
5347 */
5348 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, range, 0);
5349 }
5350 }
5351
5352 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
5353 struct radv_image *image,
5354 VkImageLayout src_layout,
5355 bool src_render_loop,
5356 VkImageLayout dst_layout,
5357 bool dst_render_loop,
5358 unsigned src_queue_mask,
5359 unsigned dst_queue_mask,
5360 const VkImageSubresourceRange *range,
5361 struct radv_sample_locations_state *sample_locs)
5362 {
5363 if (!radv_image_has_htile(image))
5364 return;
5365
5366 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5367 radv_initialize_htile(cmd_buffer, image, range);
5368 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5369 radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5370 radv_initialize_htile(cmd_buffer, image, range);
5371 } else if (radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5372 !radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5373 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5374 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5375
5376 radv_decompress_depth_stencil(cmd_buffer, image, range,
5377 sample_locs);
5378
5379 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5380 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5381 }
5382 }
5383
5384 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
5385 struct radv_image *image,
5386 const VkImageSubresourceRange *range,
5387 uint32_t value)
5388 {
5389 struct radv_cmd_state *state = &cmd_buffer->state;
5390 struct radv_barrier_data barrier = {};
5391
5392 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5393 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5394
5395 barrier.layout_transitions.init_mask_ram = 1;
5396 radv_describe_layout_transition(cmd_buffer, &barrier);
5397
5398 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, range, value);
5399
5400 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5401 }
5402
5403 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
5404 struct radv_image *image,
5405 const VkImageSubresourceRange *range)
5406 {
5407 struct radv_cmd_state *state = &cmd_buffer->state;
5408 static const uint32_t fmask_clear_values[4] = {
5409 0x00000000,
5410 0x02020202,
5411 0xE4E4E4E4,
5412 0x76543210
5413 };
5414 uint32_t log2_samples = util_logbase2(image->info.samples);
5415 uint32_t value = fmask_clear_values[log2_samples];
5416 struct radv_barrier_data barrier = {};
5417
5418 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5419 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5420
5421 barrier.layout_transitions.init_mask_ram = 1;
5422 radv_describe_layout_transition(cmd_buffer, &barrier);
5423
5424 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, range, value);
5425
5426 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5427 }
5428
5429 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
5430 struct radv_image *image,
5431 const VkImageSubresourceRange *range, uint32_t value)
5432 {
5433 struct radv_cmd_state *state = &cmd_buffer->state;
5434 struct radv_barrier_data barrier = {};
5435 unsigned size = 0;
5436
5437 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5438 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5439
5440 barrier.layout_transitions.init_mask_ram = 1;
5441 radv_describe_layout_transition(cmd_buffer, &barrier);
5442
5443 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
5444
5445 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) {
5446 /* When DCC is enabled with mipmaps, some levels might not
5447 * support fast clears and we have to initialize them as "fully
5448 * expanded".
5449 */
5450 /* Compute the size of all fast clearable DCC levels. */
5451 for (unsigned i = 0; i < image->planes[0].surface.num_dcc_levels; i++) {
5452 struct legacy_surf_level *surf_level =
5453 &image->planes[0].surface.u.legacy.level[i];
5454 unsigned dcc_fast_clear_size =
5455 surf_level->dcc_slice_fast_clear_size * image->info.array_size;
5456
5457 if (!dcc_fast_clear_size)
5458 break;
5459
5460 size = surf_level->dcc_offset + dcc_fast_clear_size;
5461 }
5462
5463 /* Initialize the mipmap levels without DCC. */
5464 if (size != image->planes[0].surface.dcc_size) {
5465 state->flush_bits |=
5466 radv_fill_buffer(cmd_buffer, image->bo,
5467 image->offset + image->dcc_offset + size,
5468 image->planes[0].surface.dcc_size - size,
5469 0xffffffff);
5470 }
5471 }
5472
5473 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5474 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5475 }
5476
5477 /**
5478 * Initialize DCC/FMASK/CMASK metadata for a color image.
5479 */
5480 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
5481 struct radv_image *image,
5482 VkImageLayout src_layout,
5483 bool src_render_loop,
5484 VkImageLayout dst_layout,
5485 bool dst_render_loop,
5486 unsigned src_queue_mask,
5487 unsigned dst_queue_mask,
5488 const VkImageSubresourceRange *range)
5489 {
5490 if (radv_image_has_cmask(image)) {
5491 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5492
5493 /* TODO: clarify this. */
5494 if (radv_image_has_fmask(image)) {
5495 value = 0xccccccccu;
5496 }
5497
5498 radv_initialise_cmask(cmd_buffer, image, range, value);
5499 }
5500
5501 if (radv_image_has_fmask(image)) {
5502 radv_initialize_fmask(cmd_buffer, image, range);
5503 }
5504
5505 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5506 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5507 bool need_decompress_pass = false;
5508
5509 if (radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout,
5510 dst_render_loop,
5511 dst_queue_mask)) {
5512 value = 0x20202020u;
5513 need_decompress_pass = true;
5514 }
5515
5516 radv_initialize_dcc(cmd_buffer, image, range, value);
5517
5518 radv_update_fce_metadata(cmd_buffer, image, range,
5519 need_decompress_pass);
5520 }
5521
5522 if (radv_image_has_cmask(image) ||
5523 radv_dcc_enabled(image, range->baseMipLevel)) {
5524 uint32_t color_values[2] = {};
5525 radv_set_color_clear_metadata(cmd_buffer, image, range,
5526 color_values);
5527 }
5528 }
5529
5530 /**
5531 * Handle color image transitions for DCC/FMASK/CMASK.
5532 */
5533 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
5534 struct radv_image *image,
5535 VkImageLayout src_layout,
5536 bool src_render_loop,
5537 VkImageLayout dst_layout,
5538 bool dst_render_loop,
5539 unsigned src_queue_mask,
5540 unsigned dst_queue_mask,
5541 const VkImageSubresourceRange *range)
5542 {
5543 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5544 radv_init_color_image_metadata(cmd_buffer, image,
5545 src_layout, src_render_loop,
5546 dst_layout, dst_render_loop,
5547 src_queue_mask, dst_queue_mask,
5548 range);
5549 return;
5550 }
5551
5552 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5553 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
5554 radv_initialize_dcc(cmd_buffer, image, range, 0xffffffffu);
5555 } else if (radv_layout_dcc_compressed(cmd_buffer->device, image, src_layout, src_render_loop, src_queue_mask) &&
5556 !radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout, dst_render_loop, dst_queue_mask)) {
5557 radv_decompress_dcc(cmd_buffer, image, range);
5558 } else if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
5559 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5560 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5561 }
5562 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
5563 bool fce_eliminate = false, fmask_expand = false;
5564
5565 if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
5566 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5567 fce_eliminate = true;
5568 }
5569
5570 if (radv_image_has_fmask(image)) {
5571 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
5572 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
5573 /* A FMASK decompress is required before doing
5574 * a MSAA decompress using FMASK.
5575 */
5576 fmask_expand = true;
5577 }
5578 }
5579
5580 if (fce_eliminate || fmask_expand)
5581 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5582
5583 if (fmask_expand) {
5584 struct radv_barrier_data barrier = {};
5585 barrier.layout_transitions.fmask_color_expand = 1;
5586 radv_describe_layout_transition(cmd_buffer, &barrier);
5587
5588 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
5589 }
5590 }
5591 }
5592
5593 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
5594 struct radv_image *image,
5595 VkImageLayout src_layout,
5596 bool src_render_loop,
5597 VkImageLayout dst_layout,
5598 bool dst_render_loop,
5599 uint32_t src_family,
5600 uint32_t dst_family,
5601 const VkImageSubresourceRange *range,
5602 struct radv_sample_locations_state *sample_locs)
5603 {
5604 if (image->exclusive && src_family != dst_family) {
5605 /* This is an acquire or a release operation and there will be
5606 * a corresponding release/acquire. Do the transition in the
5607 * most flexible queue. */
5608
5609 assert(src_family == cmd_buffer->queue_family_index ||
5610 dst_family == cmd_buffer->queue_family_index);
5611
5612 if (src_family == VK_QUEUE_FAMILY_EXTERNAL ||
5613 src_family == VK_QUEUE_FAMILY_FOREIGN_EXT)
5614 return;
5615
5616 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
5617 return;
5618
5619 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
5620 (src_family == RADV_QUEUE_GENERAL ||
5621 dst_family == RADV_QUEUE_GENERAL))
5622 return;
5623 }
5624
5625 if (src_layout == dst_layout)
5626 return;
5627
5628 unsigned src_queue_mask =
5629 radv_image_queue_family_mask(image, src_family,
5630 cmd_buffer->queue_family_index);
5631 unsigned dst_queue_mask =
5632 radv_image_queue_family_mask(image, dst_family,
5633 cmd_buffer->queue_family_index);
5634
5635 if (vk_format_is_depth(image->vk_format)) {
5636 radv_handle_depth_image_transition(cmd_buffer, image,
5637 src_layout, src_render_loop,
5638 dst_layout, dst_render_loop,
5639 src_queue_mask, dst_queue_mask,
5640 range, sample_locs);
5641 } else {
5642 radv_handle_color_image_transition(cmd_buffer, image,
5643 src_layout, src_render_loop,
5644 dst_layout, dst_render_loop,
5645 src_queue_mask, dst_queue_mask,
5646 range);
5647 }
5648 }
5649
5650 struct radv_barrier_info {
5651 enum rgp_barrier_reason reason;
5652 uint32_t eventCount;
5653 const VkEvent *pEvents;
5654 VkPipelineStageFlags srcStageMask;
5655 VkPipelineStageFlags dstStageMask;
5656 };
5657
5658 static void
5659 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
5660 uint32_t memoryBarrierCount,
5661 const VkMemoryBarrier *pMemoryBarriers,
5662 uint32_t bufferMemoryBarrierCount,
5663 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
5664 uint32_t imageMemoryBarrierCount,
5665 const VkImageMemoryBarrier *pImageMemoryBarriers,
5666 const struct radv_barrier_info *info)
5667 {
5668 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5669 enum radv_cmd_flush_bits src_flush_bits = 0;
5670 enum radv_cmd_flush_bits dst_flush_bits = 0;
5671
5672 radv_describe_barrier_start(cmd_buffer, info->reason);
5673
5674 for (unsigned i = 0; i < info->eventCount; ++i) {
5675 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
5676 uint64_t va = radv_buffer_get_va(event->bo);
5677
5678 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5679
5680 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
5681
5682 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
5683 assert(cmd_buffer->cs->cdw <= cdw_max);
5684 }
5685
5686 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
5687 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
5688 NULL);
5689 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
5690 NULL);
5691 }
5692
5693 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
5694 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
5695 NULL);
5696 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
5697 NULL);
5698 }
5699
5700 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5701 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5702
5703 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
5704 image);
5705 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
5706 image);
5707 }
5708
5709 /* The Vulkan spec 1.1.98 says:
5710 *
5711 * "An execution dependency with only
5712 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
5713 * will only prevent that stage from executing in subsequently
5714 * submitted commands. As this stage does not perform any actual
5715 * execution, this is not observable - in effect, it does not delay
5716 * processing of subsequent commands. Similarly an execution dependency
5717 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
5718 * will effectively not wait for any prior commands to complete."
5719 */
5720 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
5721 radv_stage_flush(cmd_buffer, info->srcStageMask);
5722 cmd_buffer->state.flush_bits |= src_flush_bits;
5723
5724 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5725 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5726
5727 const struct VkSampleLocationsInfoEXT *sample_locs_info =
5728 vk_find_struct_const(pImageMemoryBarriers[i].pNext,
5729 SAMPLE_LOCATIONS_INFO_EXT);
5730 struct radv_sample_locations_state sample_locations = {};
5731
5732 if (sample_locs_info) {
5733 assert(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
5734 sample_locations.per_pixel = sample_locs_info->sampleLocationsPerPixel;
5735 sample_locations.grid_size = sample_locs_info->sampleLocationGridSize;
5736 sample_locations.count = sample_locs_info->sampleLocationsCount;
5737 typed_memcpy(&sample_locations.locations[0],
5738 sample_locs_info->pSampleLocations,
5739 sample_locs_info->sampleLocationsCount);
5740 }
5741
5742 radv_handle_image_transition(cmd_buffer, image,
5743 pImageMemoryBarriers[i].oldLayout,
5744 false, /* Outside of a renderpass we are never in a renderloop */
5745 pImageMemoryBarriers[i].newLayout,
5746 false, /* Outside of a renderpass we are never in a renderloop */
5747 pImageMemoryBarriers[i].srcQueueFamilyIndex,
5748 pImageMemoryBarriers[i].dstQueueFamilyIndex,
5749 &pImageMemoryBarriers[i].subresourceRange,
5750 sample_locs_info ? &sample_locations : NULL);
5751 }
5752
5753 /* Make sure CP DMA is idle because the driver might have performed a
5754 * DMA operation for copying or filling buffers/images.
5755 */
5756 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5757 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5758 si_cp_dma_wait_for_idle(cmd_buffer);
5759
5760 cmd_buffer->state.flush_bits |= dst_flush_bits;
5761
5762 radv_describe_barrier_end(cmd_buffer);
5763 }
5764
5765 void radv_CmdPipelineBarrier(
5766 VkCommandBuffer commandBuffer,
5767 VkPipelineStageFlags srcStageMask,
5768 VkPipelineStageFlags destStageMask,
5769 VkBool32 byRegion,
5770 uint32_t memoryBarrierCount,
5771 const VkMemoryBarrier* pMemoryBarriers,
5772 uint32_t bufferMemoryBarrierCount,
5773 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5774 uint32_t imageMemoryBarrierCount,
5775 const VkImageMemoryBarrier* pImageMemoryBarriers)
5776 {
5777 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5778 struct radv_barrier_info info;
5779
5780 info.reason = RGP_BARRIER_EXTERNAL_CMD_PIPELINE_BARRIER;
5781 info.eventCount = 0;
5782 info.pEvents = NULL;
5783 info.srcStageMask = srcStageMask;
5784 info.dstStageMask = destStageMask;
5785
5786 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5787 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5788 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5789 }
5790
5791
5792 static void write_event(struct radv_cmd_buffer *cmd_buffer,
5793 struct radv_event *event,
5794 VkPipelineStageFlags stageMask,
5795 unsigned value)
5796 {
5797 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5798 uint64_t va = radv_buffer_get_va(event->bo);
5799
5800 si_emit_cache_flush(cmd_buffer);
5801
5802 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5803
5804 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 21);
5805
5806 /* Flags that only require a top-of-pipe event. */
5807 VkPipelineStageFlags top_of_pipe_flags =
5808 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
5809
5810 /* Flags that only require a post-index-fetch event. */
5811 VkPipelineStageFlags post_index_fetch_flags =
5812 top_of_pipe_flags |
5813 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
5814 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
5815
5816 /* Make sure CP DMA is idle because the driver might have performed a
5817 * DMA operation for copying or filling buffers/images.
5818 */
5819 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5820 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5821 si_cp_dma_wait_for_idle(cmd_buffer);
5822
5823 /* TODO: Emit EOS events for syncing PS/CS stages. */
5824
5825 if (!(stageMask & ~top_of_pipe_flags)) {
5826 /* Just need to sync the PFP engine. */
5827 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5828 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5829 S_370_WR_CONFIRM(1) |
5830 S_370_ENGINE_SEL(V_370_PFP));
5831 radeon_emit(cs, va);
5832 radeon_emit(cs, va >> 32);
5833 radeon_emit(cs, value);
5834 } else if (!(stageMask & ~post_index_fetch_flags)) {
5835 /* Sync ME because PFP reads index and indirect buffers. */
5836 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5837 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5838 S_370_WR_CONFIRM(1) |
5839 S_370_ENGINE_SEL(V_370_ME));
5840 radeon_emit(cs, va);
5841 radeon_emit(cs, va >> 32);
5842 radeon_emit(cs, value);
5843 } else {
5844 /* Otherwise, sync all prior GPU work using an EOP event. */
5845 si_cs_emit_write_event_eop(cs,
5846 cmd_buffer->device->physical_device->rad_info.chip_class,
5847 radv_cmd_buffer_uses_mec(cmd_buffer),
5848 V_028A90_BOTTOM_OF_PIPE_TS, 0,
5849 EOP_DST_SEL_MEM,
5850 EOP_DATA_SEL_VALUE_32BIT, va, value,
5851 cmd_buffer->gfx9_eop_bug_va);
5852 }
5853
5854 assert(cmd_buffer->cs->cdw <= cdw_max);
5855 }
5856
5857 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
5858 VkEvent _event,
5859 VkPipelineStageFlags stageMask)
5860 {
5861 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5862 RADV_FROM_HANDLE(radv_event, event, _event);
5863
5864 write_event(cmd_buffer, event, stageMask, 1);
5865 }
5866
5867 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
5868 VkEvent _event,
5869 VkPipelineStageFlags stageMask)
5870 {
5871 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5872 RADV_FROM_HANDLE(radv_event, event, _event);
5873
5874 write_event(cmd_buffer, event, stageMask, 0);
5875 }
5876
5877 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
5878 uint32_t eventCount,
5879 const VkEvent* pEvents,
5880 VkPipelineStageFlags srcStageMask,
5881 VkPipelineStageFlags dstStageMask,
5882 uint32_t memoryBarrierCount,
5883 const VkMemoryBarrier* pMemoryBarriers,
5884 uint32_t bufferMemoryBarrierCount,
5885 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5886 uint32_t imageMemoryBarrierCount,
5887 const VkImageMemoryBarrier* pImageMemoryBarriers)
5888 {
5889 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5890 struct radv_barrier_info info;
5891
5892 info.reason = RGP_BARRIER_EXTERNAL_CMD_WAIT_EVENTS;
5893 info.eventCount = eventCount;
5894 info.pEvents = pEvents;
5895 info.srcStageMask = 0;
5896
5897 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5898 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5899 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5900 }
5901
5902
5903 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
5904 uint32_t deviceMask)
5905 {
5906 /* No-op */
5907 }
5908
5909 /* VK_EXT_conditional_rendering */
5910 void radv_CmdBeginConditionalRenderingEXT(
5911 VkCommandBuffer commandBuffer,
5912 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
5913 {
5914 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5915 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
5916 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5917 bool draw_visible = true;
5918 uint64_t pred_value = 0;
5919 uint64_t va, new_va;
5920 unsigned pred_offset;
5921
5922 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
5923
5924 /* By default, if the 32-bit value at offset in buffer memory is zero,
5925 * then the rendering commands are discarded, otherwise they are
5926 * executed as normal. If the inverted flag is set, all commands are
5927 * discarded if the value is non zero.
5928 */
5929 if (pConditionalRenderingBegin->flags &
5930 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
5931 draw_visible = false;
5932 }
5933
5934 si_emit_cache_flush(cmd_buffer);
5935
5936 /* From the Vulkan spec 1.1.107:
5937 *
5938 * "If the 32-bit value at offset in buffer memory is zero, then the
5939 * rendering commands are discarded, otherwise they are executed as
5940 * normal. If the value of the predicate in buffer memory changes while
5941 * conditional rendering is active, the rendering commands may be
5942 * discarded in an implementation-dependent way. Some implementations
5943 * may latch the value of the predicate upon beginning conditional
5944 * rendering while others may read it before every rendering command."
5945 *
5946 * But, the AMD hardware treats the predicate as a 64-bit value which
5947 * means we need a workaround in the driver. Luckily, it's not required
5948 * to support if the value changes when predication is active.
5949 *
5950 * The workaround is as follows:
5951 * 1) allocate a 64-value in the upload BO and initialize it to 0
5952 * 2) copy the 32-bit predicate value to the upload BO
5953 * 3) use the new allocated VA address for predication
5954 *
5955 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
5956 * in ME (+ sync PFP) instead of PFP.
5957 */
5958 radv_cmd_buffer_upload_data(cmd_buffer, 8, 16, &pred_value, &pred_offset);
5959
5960 new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
5961
5962 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5963 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5964 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
5965 COPY_DATA_WR_CONFIRM);
5966 radeon_emit(cs, va);
5967 radeon_emit(cs, va >> 32);
5968 radeon_emit(cs, new_va);
5969 radeon_emit(cs, new_va >> 32);
5970
5971 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
5972 radeon_emit(cs, 0);
5973
5974 /* Enable predication for this command buffer. */
5975 si_emit_set_predication_state(cmd_buffer, draw_visible, new_va);
5976 cmd_buffer->state.predicating = true;
5977
5978 /* Store conditional rendering user info. */
5979 cmd_buffer->state.predication_type = draw_visible;
5980 cmd_buffer->state.predication_va = new_va;
5981 }
5982
5983 void radv_CmdEndConditionalRenderingEXT(
5984 VkCommandBuffer commandBuffer)
5985 {
5986 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5987
5988 /* Disable predication for this command buffer. */
5989 si_emit_set_predication_state(cmd_buffer, false, 0);
5990 cmd_buffer->state.predicating = false;
5991
5992 /* Reset conditional rendering user info. */
5993 cmd_buffer->state.predication_type = -1;
5994 cmd_buffer->state.predication_va = 0;
5995 }
5996
5997 /* VK_EXT_transform_feedback */
5998 void radv_CmdBindTransformFeedbackBuffersEXT(
5999 VkCommandBuffer commandBuffer,
6000 uint32_t firstBinding,
6001 uint32_t bindingCount,
6002 const VkBuffer* pBuffers,
6003 const VkDeviceSize* pOffsets,
6004 const VkDeviceSize* pSizes)
6005 {
6006 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6007 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
6008 uint8_t enabled_mask = 0;
6009
6010 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
6011 for (uint32_t i = 0; i < bindingCount; i++) {
6012 uint32_t idx = firstBinding + i;
6013
6014 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
6015 sb[idx].offset = pOffsets[i];
6016
6017 if (!pSizes || pSizes[i] == VK_WHOLE_SIZE) {
6018 sb[idx].size = sb[idx].buffer->size - sb[idx].offset;
6019 } else {
6020 sb[idx].size = pSizes[i];
6021 }
6022
6023 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
6024 sb[idx].buffer->bo);
6025
6026 enabled_mask |= 1 << idx;
6027 }
6028
6029 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
6030
6031 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
6032 }
6033
6034 static void
6035 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
6036 {
6037 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6038 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6039
6040 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
6041 radeon_emit(cs,
6042 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
6043 S_028B94_RAST_STREAM(0) |
6044 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
6045 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
6046 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
6047 radeon_emit(cs, so->hw_enabled_mask &
6048 so->enabled_stream_buffers_mask);
6049
6050 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6051 }
6052
6053 static void
6054 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
6055 {
6056 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6057 bool old_streamout_enabled = so->streamout_enabled;
6058 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
6059
6060 so->streamout_enabled = enable;
6061
6062 so->hw_enabled_mask = so->enabled_mask |
6063 (so->enabled_mask << 4) |
6064 (so->enabled_mask << 8) |
6065 (so->enabled_mask << 12);
6066
6067 if (!cmd_buffer->device->physical_device->use_ngg_streamout &&
6068 ((old_streamout_enabled != so->streamout_enabled) ||
6069 (old_hw_enabled_mask != so->hw_enabled_mask)))
6070 radv_emit_streamout_enable(cmd_buffer);
6071
6072 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6073 cmd_buffer->gds_needed = true;
6074 cmd_buffer->gds_oa_needed = true;
6075 }
6076 }
6077
6078 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
6079 {
6080 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6081 unsigned reg_strmout_cntl;
6082
6083 /* The register is at different places on different ASICs. */
6084 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
6085 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
6086 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
6087 } else {
6088 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
6089 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
6090 }
6091
6092 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
6093 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
6094
6095 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
6096 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
6097 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
6098 radeon_emit(cs, 0);
6099 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
6100 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
6101 radeon_emit(cs, 4); /* poll interval */
6102 }
6103
6104 static void
6105 radv_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
6106 uint32_t firstCounterBuffer,
6107 uint32_t counterBufferCount,
6108 const VkBuffer *pCounterBuffers,
6109 const VkDeviceSize *pCounterBufferOffsets)
6110
6111 {
6112 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
6113 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6114 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6115 uint32_t i;
6116
6117 radv_flush_vgt_streamout(cmd_buffer);
6118
6119 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6120 for_each_bit(i, so->enabled_mask) {
6121 int32_t counter_buffer_idx = i - firstCounterBuffer;
6122 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6123 counter_buffer_idx = -1;
6124
6125 /* AMD GCN binds streamout buffers as shader resources.
6126 * VGT only counts primitives and tells the shader through
6127 * SGPRs what to do.
6128 */
6129 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
6130 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
6131 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
6132
6133 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6134
6135 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6136 /* The array of counter buffers is optional. */
6137 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6138 uint64_t va = radv_buffer_get_va(buffer->bo);
6139
6140 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6141
6142 /* Append */
6143 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6144 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6145 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6146 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
6147 radeon_emit(cs, 0); /* unused */
6148 radeon_emit(cs, 0); /* unused */
6149 radeon_emit(cs, va); /* src address lo */
6150 radeon_emit(cs, va >> 32); /* src address hi */
6151
6152 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6153 } else {
6154 /* Start from the beginning. */
6155 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6156 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6157 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6158 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
6159 radeon_emit(cs, 0); /* unused */
6160 radeon_emit(cs, 0); /* unused */
6161 radeon_emit(cs, 0); /* unused */
6162 radeon_emit(cs, 0); /* unused */
6163 }
6164 }
6165
6166 radv_set_streamout_enable(cmd_buffer, true);
6167 }
6168
6169 static void
6170 gfx10_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
6171 uint32_t firstCounterBuffer,
6172 uint32_t counterBufferCount,
6173 const VkBuffer *pCounterBuffers,
6174 const VkDeviceSize *pCounterBufferOffsets)
6175 {
6176 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6177 unsigned last_target = util_last_bit(so->enabled_mask) - 1;
6178 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6179 uint32_t i;
6180
6181 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6182 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6183
6184 /* Sync because the next streamout operation will overwrite GDS and we
6185 * have to make sure it's idle.
6186 * TODO: Improve by tracking if there is a streamout operation in
6187 * flight.
6188 */
6189 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
6190 si_emit_cache_flush(cmd_buffer);
6191
6192 for_each_bit(i, so->enabled_mask) {
6193 int32_t counter_buffer_idx = i - firstCounterBuffer;
6194 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6195 counter_buffer_idx = -1;
6196
6197 bool append = counter_buffer_idx >= 0 &&
6198 pCounterBuffers && pCounterBuffers[counter_buffer_idx];
6199 uint64_t va = 0;
6200
6201 if (append) {
6202 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6203
6204 va += radv_buffer_get_va(buffer->bo);
6205 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6206
6207 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6208 }
6209
6210 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
6211 radeon_emit(cs, S_411_SRC_SEL(append ? V_411_SRC_ADDR_TC_L2 : V_411_DATA) |
6212 S_411_DST_SEL(V_411_GDS) |
6213 S_411_CP_SYNC(i == last_target));
6214 radeon_emit(cs, va);
6215 radeon_emit(cs, va >> 32);
6216 radeon_emit(cs, 4 * i); /* destination in GDS */
6217 radeon_emit(cs, 0);
6218 radeon_emit(cs, S_414_BYTE_COUNT_GFX9(4) |
6219 S_414_DISABLE_WR_CONFIRM_GFX9(i != last_target));
6220 }
6221
6222 radv_set_streamout_enable(cmd_buffer, true);
6223 }
6224
6225 void radv_CmdBeginTransformFeedbackEXT(
6226 VkCommandBuffer commandBuffer,
6227 uint32_t firstCounterBuffer,
6228 uint32_t counterBufferCount,
6229 const VkBuffer* pCounterBuffers,
6230 const VkDeviceSize* pCounterBufferOffsets)
6231 {
6232 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6233
6234 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6235 gfx10_emit_streamout_begin(cmd_buffer,
6236 firstCounterBuffer, counterBufferCount,
6237 pCounterBuffers, pCounterBufferOffsets);
6238 } else {
6239 radv_emit_streamout_begin(cmd_buffer,
6240 firstCounterBuffer, counterBufferCount,
6241 pCounterBuffers, pCounterBufferOffsets);
6242 }
6243 }
6244
6245 static void
6246 radv_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6247 uint32_t firstCounterBuffer,
6248 uint32_t counterBufferCount,
6249 const VkBuffer *pCounterBuffers,
6250 const VkDeviceSize *pCounterBufferOffsets)
6251 {
6252 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6253 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6254 uint32_t i;
6255
6256 radv_flush_vgt_streamout(cmd_buffer);
6257
6258 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6259 for_each_bit(i, so->enabled_mask) {
6260 int32_t counter_buffer_idx = i - firstCounterBuffer;
6261 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6262 counter_buffer_idx = -1;
6263
6264 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6265 /* The array of counters buffer is optional. */
6266 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6267 uint64_t va = radv_buffer_get_va(buffer->bo);
6268
6269 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6270
6271 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6272 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6273 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6274 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
6275 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
6276 radeon_emit(cs, va); /* dst address lo */
6277 radeon_emit(cs, va >> 32); /* dst address hi */
6278 radeon_emit(cs, 0); /* unused */
6279 radeon_emit(cs, 0); /* unused */
6280
6281 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6282 }
6283
6284 /* Deactivate transform feedback by zeroing the buffer size.
6285 * The counters (primitives generated, primitives emitted) may
6286 * be enabled even if there is not buffer bound. This ensures
6287 * that the primitives-emitted query won't increment.
6288 */
6289 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
6290
6291 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6292 }
6293
6294 radv_set_streamout_enable(cmd_buffer, false);
6295 }
6296
6297 static void
6298 gfx10_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6299 uint32_t firstCounterBuffer,
6300 uint32_t counterBufferCount,
6301 const VkBuffer *pCounterBuffers,
6302 const VkDeviceSize *pCounterBufferOffsets)
6303 {
6304 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6305 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6306 uint32_t i;
6307
6308 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6309 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6310
6311 for_each_bit(i, so->enabled_mask) {
6312 int32_t counter_buffer_idx = i - firstCounterBuffer;
6313 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6314 counter_buffer_idx = -1;
6315
6316 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6317 /* The array of counters buffer is optional. */
6318 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6319 uint64_t va = radv_buffer_get_va(buffer->bo);
6320
6321 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6322
6323 si_cs_emit_write_event_eop(cs,
6324 cmd_buffer->device->physical_device->rad_info.chip_class,
6325 radv_cmd_buffer_uses_mec(cmd_buffer),
6326 V_028A90_PS_DONE, 0,
6327 EOP_DST_SEL_TC_L2,
6328 EOP_DATA_SEL_GDS,
6329 va, EOP_DATA_GDS(i, 1), 0);
6330
6331 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6332 }
6333 }
6334
6335 radv_set_streamout_enable(cmd_buffer, false);
6336 }
6337
6338 void radv_CmdEndTransformFeedbackEXT(
6339 VkCommandBuffer commandBuffer,
6340 uint32_t firstCounterBuffer,
6341 uint32_t counterBufferCount,
6342 const VkBuffer* pCounterBuffers,
6343 const VkDeviceSize* pCounterBufferOffsets)
6344 {
6345 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6346
6347 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6348 gfx10_emit_streamout_end(cmd_buffer,
6349 firstCounterBuffer, counterBufferCount,
6350 pCounterBuffers, pCounterBufferOffsets);
6351 } else {
6352 radv_emit_streamout_end(cmd_buffer,
6353 firstCounterBuffer, counterBufferCount,
6354 pCounterBuffers, pCounterBufferOffsets);
6355 }
6356 }
6357
6358 void radv_CmdDrawIndirectByteCountEXT(
6359 VkCommandBuffer commandBuffer,
6360 uint32_t instanceCount,
6361 uint32_t firstInstance,
6362 VkBuffer _counterBuffer,
6363 VkDeviceSize counterBufferOffset,
6364 uint32_t counterOffset,
6365 uint32_t vertexStride)
6366 {
6367 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6368 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
6369 struct radv_draw_info info = {};
6370
6371 info.instance_count = instanceCount;
6372 info.first_instance = firstInstance;
6373 info.strmout_buffer = counterBuffer;
6374 info.strmout_buffer_offset = counterBufferOffset;
6375 info.stride = vertexStride;
6376
6377 radv_draw(cmd_buffer, &info);
6378 }
6379
6380 /* VK_AMD_buffer_marker */
6381 void radv_CmdWriteBufferMarkerAMD(
6382 VkCommandBuffer commandBuffer,
6383 VkPipelineStageFlagBits pipelineStage,
6384 VkBuffer dstBuffer,
6385 VkDeviceSize dstOffset,
6386 uint32_t marker)
6387 {
6388 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6389 RADV_FROM_HANDLE(radv_buffer, buffer, dstBuffer);
6390 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6391 uint64_t va = radv_buffer_get_va(buffer->bo) + dstOffset;
6392
6393 si_emit_cache_flush(cmd_buffer);
6394
6395 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 12);
6396
6397 if (!(pipelineStage & ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT)) {
6398 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
6399 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
6400 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
6401 COPY_DATA_WR_CONFIRM);
6402 radeon_emit(cs, marker);
6403 radeon_emit(cs, 0);
6404 radeon_emit(cs, va);
6405 radeon_emit(cs, va >> 32);
6406 } else {
6407 si_cs_emit_write_event_eop(cs,
6408 cmd_buffer->device->physical_device->rad_info.chip_class,
6409 radv_cmd_buffer_uses_mec(cmd_buffer),
6410 V_028A90_BOTTOM_OF_PIPE_TS, 0,
6411 EOP_DST_SEL_MEM,
6412 EOP_DATA_SEL_VALUE_32BIT,
6413 va, marker,
6414 cmd_buffer->gfx9_eop_bug_va);
6415 }
6416
6417 assert(cmd_buffer->cs->cdw <= cdw_max);
6418 }