2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include <sys/utsname.h>
32 #include "util/mesa-sha1.h"
35 #include "radv_debug.h"
36 #include "radv_shader.h"
38 #define TRACE_BO_SIZE 4096
39 #define TMA_BO_SIZE 4096
41 #define COLOR_RESET "\033[0m"
42 #define COLOR_RED "\033[31m"
43 #define COLOR_GREEN "\033[1;32m"
44 #define COLOR_YELLOW "\033[1;33m"
45 #define COLOR_CYAN "\033[1;36m"
47 /* Trace BO layout (offsets are 4 bytes):
49 * [0]: primary trace ID
50 * [1]: secondary trace ID
51 * [2-3]: 64-bit GFX pipeline pointer
52 * [4-5]: 64-bit COMPUTE pipeline pointer
53 * [6-7]: 64-bit descriptor set #0 pointer
55 * [68-69]: 64-bit descriptor set #31 pointer
59 radv_init_trace(struct radv_device
*device
)
61 struct radeon_winsys
*ws
= device
->ws
;
63 device
->trace_bo
= ws
->buffer_create(ws
, TRACE_BO_SIZE
, 8,
65 RADEON_FLAG_CPU_ACCESS
|
66 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
67 RADEON_FLAG_ZERO_VRAM
,
68 RADV_BO_PRIORITY_UPLOAD_BUFFER
);
69 if (!device
->trace_bo
)
72 device
->trace_id_ptr
= ws
->buffer_map(device
->trace_bo
);
73 if (!device
->trace_id_ptr
)
76 ac_vm_fault_occured(device
->physical_device
->rad_info
.chip_class
,
77 &device
->dmesg_timestamp
, NULL
);
83 radv_dump_trace(struct radv_device
*device
, struct radeon_cmdbuf
*cs
)
85 const char *filename
= getenv("RADV_TRACE_FILE");
86 FILE *f
= fopen(filename
, "w");
89 fprintf(stderr
, "Failed to write trace dump to %s\n", filename
);
93 fprintf(f
, "Trace ID: %x\n", *device
->trace_id_ptr
);
94 device
->ws
->cs_dump(cs
, f
, (const int*)device
->trace_id_ptr
, 2);
99 radv_dump_mmapped_reg(struct radv_device
*device
, FILE *f
, unsigned offset
)
101 struct radeon_winsys
*ws
= device
->ws
;
104 if (ws
->read_registers(ws
, offset
, 1, &value
))
105 ac_dump_reg(f
, device
->physical_device
->rad_info
.chip_class
,
110 radv_dump_debug_registers(struct radv_device
*device
, FILE *f
)
112 struct radeon_info
*info
= &device
->physical_device
->rad_info
;
114 fprintf(f
, "Memory-mapped registers:\n");
115 radv_dump_mmapped_reg(device
, f
, R_008010_GRBM_STATUS
);
117 /* No other registers can be read on DRM < 3.1.0. */
118 if (info
->drm_minor
< 1) {
123 radv_dump_mmapped_reg(device
, f
, R_008008_GRBM_STATUS2
);
124 radv_dump_mmapped_reg(device
, f
, R_008014_GRBM_STATUS_SE0
);
125 radv_dump_mmapped_reg(device
, f
, R_008018_GRBM_STATUS_SE1
);
126 radv_dump_mmapped_reg(device
, f
, R_008038_GRBM_STATUS_SE2
);
127 radv_dump_mmapped_reg(device
, f
, R_00803C_GRBM_STATUS_SE3
);
128 radv_dump_mmapped_reg(device
, f
, R_00D034_SDMA0_STATUS_REG
);
129 radv_dump_mmapped_reg(device
, f
, R_00D834_SDMA1_STATUS_REG
);
130 if (info
->chip_class
<= GFX8
) {
131 radv_dump_mmapped_reg(device
, f
, R_000E50_SRBM_STATUS
);
132 radv_dump_mmapped_reg(device
, f
, R_000E4C_SRBM_STATUS2
);
133 radv_dump_mmapped_reg(device
, f
, R_000E54_SRBM_STATUS3
);
135 radv_dump_mmapped_reg(device
, f
, R_008680_CP_STAT
);
136 radv_dump_mmapped_reg(device
, f
, R_008674_CP_STALLED_STAT1
);
137 radv_dump_mmapped_reg(device
, f
, R_008678_CP_STALLED_STAT2
);
138 radv_dump_mmapped_reg(device
, f
, R_008670_CP_STALLED_STAT3
);
139 radv_dump_mmapped_reg(device
, f
, R_008210_CP_CPC_STATUS
);
140 radv_dump_mmapped_reg(device
, f
, R_008214_CP_CPC_BUSY_STAT
);
141 radv_dump_mmapped_reg(device
, f
, R_008218_CP_CPC_STALLED_STAT1
);
142 radv_dump_mmapped_reg(device
, f
, R_00821C_CP_CPF_STATUS
);
143 radv_dump_mmapped_reg(device
, f
, R_008220_CP_CPF_BUSY_STAT
);
144 radv_dump_mmapped_reg(device
, f
, R_008224_CP_CPF_STALLED_STAT1
);
149 radv_dump_buffer_descriptor(enum chip_class chip_class
, const uint32_t *desc
,
152 fprintf(f
, COLOR_CYAN
" Buffer:" COLOR_RESET
"\n");
153 for (unsigned j
= 0; j
< 4; j
++)
154 ac_dump_reg(f
, chip_class
, R_008F00_SQ_BUF_RSRC_WORD0
+ j
* 4,
155 desc
[j
], 0xffffffff);
159 radv_dump_image_descriptor(enum chip_class chip_class
, const uint32_t *desc
,
162 unsigned sq_img_rsrc_word0
= chip_class
>= GFX10
? R_00A000_SQ_IMG_RSRC_WORD0
163 : R_008F10_SQ_IMG_RSRC_WORD0
;
165 fprintf(f
, COLOR_CYAN
" Image:" COLOR_RESET
"\n");
166 for (unsigned j
= 0; j
< 8; j
++)
167 ac_dump_reg(f
, chip_class
, sq_img_rsrc_word0
+ j
* 4,
168 desc
[j
], 0xffffffff);
170 fprintf(f
, COLOR_CYAN
" FMASK:" COLOR_RESET
"\n");
171 for (unsigned j
= 0; j
< 8; j
++)
172 ac_dump_reg(f
, chip_class
, sq_img_rsrc_word0
+ j
* 4,
173 desc
[8 + j
], 0xffffffff);
177 radv_dump_sampler_descriptor(enum chip_class chip_class
, const uint32_t *desc
,
180 fprintf(f
, COLOR_CYAN
" Sampler state:" COLOR_RESET
"\n");
181 for (unsigned j
= 0; j
< 4; j
++) {
182 ac_dump_reg(f
, chip_class
, R_008F30_SQ_IMG_SAMP_WORD0
+ j
* 4,
183 desc
[j
], 0xffffffff);
188 radv_dump_combined_image_sampler_descriptor(enum chip_class chip_class
,
189 const uint32_t *desc
, FILE *f
)
191 radv_dump_image_descriptor(chip_class
, desc
, f
);
192 radv_dump_sampler_descriptor(chip_class
, desc
+ 16, f
);
196 radv_dump_descriptor_set(struct radv_device
*device
,
197 struct radv_descriptor_set
*set
, unsigned id
, FILE *f
)
199 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
200 const struct radv_descriptor_set_layout
*layout
;
205 layout
= set
->layout
;
207 for (i
= 0; i
< set
->layout
->binding_count
; i
++) {
209 set
->mapped_ptr
+ layout
->binding
[i
].offset
/ 4;
211 switch (layout
->binding
[i
].type
) {
212 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
213 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
214 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
215 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
216 radv_dump_buffer_descriptor(chip_class
, desc
, f
);
218 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
:
219 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
:
220 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
221 radv_dump_image_descriptor(chip_class
, desc
, f
);
223 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
224 radv_dump_combined_image_sampler_descriptor(chip_class
, desc
, f
);
226 case VK_DESCRIPTOR_TYPE_SAMPLER
:
227 radv_dump_sampler_descriptor(chip_class
, desc
, f
);
229 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
230 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
:
234 assert(!"unknown descriptor type");
243 radv_dump_descriptors(struct radv_device
*device
, FILE *f
)
245 uint64_t *ptr
= (uint64_t *)device
->trace_id_ptr
;
248 fprintf(f
, "Descriptors:\n");
249 for (i
= 0; i
< MAX_SETS
; i
++) {
250 struct radv_descriptor_set
*set
=
251 *(struct radv_descriptor_set
**)(ptr
+ i
+ 3);
253 radv_dump_descriptor_set(device
, set
, i
, f
);
257 struct radv_shader_inst
{
258 char text
[160]; /* one disasm line */
259 unsigned offset
; /* instruction offset */
260 unsigned size
; /* instruction size = 4 or 8 */
263 /* Split a disassembly string into lines and add them to the array pointed
264 * to by "instructions". */
265 static void si_add_split_disasm(const char *disasm
,
268 struct radv_shader_inst
*instructions
)
270 struct radv_shader_inst
*last_inst
= *num
? &instructions
[*num
- 1] : NULL
;
273 while ((next
= strchr(disasm
, '\n'))) {
274 struct radv_shader_inst
*inst
= &instructions
[*num
];
275 unsigned len
= next
- disasm
;
277 if (!memchr(disasm
, ';', len
)) {
278 /* Ignore everything that is not an instruction. */
283 assert(len
< ARRAY_SIZE(inst
->text
));
284 memcpy(inst
->text
, disasm
, len
);
286 inst
->offset
= last_inst
? last_inst
->offset
+ last_inst
->size
: 0;
288 const char *semicolon
= strchr(disasm
, ';');
290 /* More than 16 chars after ";" means the instruction is 8 bytes long. */
291 inst
->size
= next
- semicolon
> 16 ? 8 : 4;
293 snprintf(inst
->text
+ len
, ARRAY_SIZE(inst
->text
) - len
,
294 " [PC=0x%"PRIx64
", off=%u, size=%u]",
295 start_addr
+ inst
->offset
, inst
->offset
, inst
->size
);
304 radv_dump_annotated_shader(struct radv_shader_variant
*shader
,
305 gl_shader_stage stage
, struct ac_wave_info
*waves
,
306 unsigned num_waves
, FILE *f
)
308 uint64_t start_addr
, end_addr
;
314 start_addr
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
315 end_addr
= start_addr
+ shader
->code_size
;
317 /* See if any wave executes the shader. */
318 for (i
= 0; i
< num_waves
; i
++) {
319 if (start_addr
<= waves
[i
].pc
&& waves
[i
].pc
<= end_addr
)
324 return; /* the shader is not being executed */
326 /* Remember the first found wave. The waves are sorted according to PC. */
330 /* Get the list of instructions.
331 * Buffer size / 4 is the upper bound of the instruction count.
333 unsigned num_inst
= 0;
334 struct radv_shader_inst
*instructions
=
335 calloc(shader
->code_size
/ 4, sizeof(struct radv_shader_inst
));
337 si_add_split_disasm(shader
->disasm_string
,
338 start_addr
, &num_inst
, instructions
);
340 fprintf(f
, COLOR_YELLOW
"%s - annotated disassembly:" COLOR_RESET
"\n",
341 radv_get_shader_name(&shader
->info
, stage
));
343 /* Print instructions with annotations. */
344 for (i
= 0; i
< num_inst
; i
++) {
345 struct radv_shader_inst
*inst
= &instructions
[i
];
347 fprintf(f
, "%s\n", inst
->text
);
349 /* Print which waves execute the instruction right now. */
350 while (num_waves
&& start_addr
+ inst
->offset
== waves
->pc
) {
352 " " COLOR_GREEN
"^ SE%u SH%u CU%u "
353 "SIMD%u WAVE%u EXEC=%016"PRIx64
" ",
354 waves
->se
, waves
->sh
, waves
->cu
, waves
->simd
,
355 waves
->wave
, waves
->exec
);
357 if (inst
->size
== 4) {
358 fprintf(f
, "INST32=%08X" COLOR_RESET
"\n",
361 fprintf(f
, "INST64=%08X %08X" COLOR_RESET
"\n",
362 waves
->inst_dw0
, waves
->inst_dw1
);
365 waves
->matched
= true;
376 radv_dump_annotated_shaders(struct radv_pipeline
*pipeline
,
377 VkShaderStageFlagBits active_stages
, FILE *f
)
379 struct ac_wave_info waves
[AC_MAX_WAVES_PER_CHIP
];
380 enum chip_class chip_class
= pipeline
->device
->physical_device
->rad_info
.chip_class
;
381 unsigned num_waves
= ac_get_wave_info(chip_class
, waves
);
383 fprintf(f
, COLOR_CYAN
"The number of active waves = %u" COLOR_RESET
386 /* Dump annotated active graphics shaders. */
387 while (active_stages
) {
388 int stage
= u_bit_scan(&active_stages
);
390 radv_dump_annotated_shader(pipeline
->shaders
[stage
],
391 stage
, waves
, num_waves
, f
);
394 /* Print waves executing shaders that are not currently bound. */
397 for (i
= 0; i
< num_waves
; i
++) {
398 if (waves
[i
].matched
)
402 fprintf(f
, COLOR_CYAN
403 "Waves not executing currently-bound shaders:"
407 fprintf(f
, " SE%u SH%u CU%u SIMD%u WAVE%u EXEC=%016"PRIx64
408 " INST=%08X %08X PC=%"PRIx64
"\n",
409 waves
[i
].se
, waves
[i
].sh
, waves
[i
].cu
, waves
[i
].simd
,
410 waves
[i
].wave
, waves
[i
].exec
, waves
[i
].inst_dw0
,
411 waves
[i
].inst_dw1
, waves
[i
].pc
);
418 radv_dump_shader(struct radv_pipeline
*pipeline
,
419 struct radv_shader_variant
*shader
, gl_shader_stage stage
,
425 fprintf(f
, "%s:\n\n", radv_get_shader_name(&shader
->info
, stage
));
428 unsigned char sha1
[21];
431 _mesa_sha1_compute(shader
->spirv
, shader
->spirv_size
, sha1
);
432 _mesa_sha1_format(sha1buf
, sha1
);
434 fprintf(f
, "SPIRV (sha1: %s):\n", sha1buf
);
435 radv_print_spirv(shader
->spirv
, shader
->spirv_size
, f
);
438 if (shader
->nir_string
) {
439 fprintf(f
, "NIR:\n%s\n", shader
->nir_string
);
442 fprintf(f
, "%s IR:\n%s\n",
443 pipeline
->device
->physical_device
->use_llvm
? "LLVM" : "ACO",
445 fprintf(f
, "DISASM:\n%s\n", shader
->disasm_string
);
447 radv_shader_dump_stats(pipeline
->device
, shader
, stage
, f
);
451 radv_dump_shaders(struct radv_pipeline
*pipeline
,
452 VkShaderStageFlagBits active_stages
, FILE *f
)
454 /* Dump active graphics shaders. */
455 while (active_stages
) {
456 int stage
= u_bit_scan(&active_stages
);
458 radv_dump_shader(pipeline
, pipeline
->shaders
[stage
], stage
, f
);
463 radv_dump_pipeline_state(struct radv_pipeline
*pipeline
,
464 VkShaderStageFlagBits active_stages
, FILE *f
)
466 radv_dump_shaders(pipeline
, active_stages
, f
);
467 radv_dump_annotated_shaders(pipeline
, active_stages
, f
);
471 radv_dump_graphics_state(struct radv_device
*device
,
472 struct radv_pipeline
*graphics_pipeline
,
473 struct radv_pipeline
*compute_pipeline
, FILE *f
)
475 VkShaderStageFlagBits active_stages
;
477 if (graphics_pipeline
) {
478 active_stages
= graphics_pipeline
->active_stages
;
479 radv_dump_pipeline_state(graphics_pipeline
, active_stages
, f
);
482 if (compute_pipeline
) {
483 active_stages
= VK_SHADER_STAGE_COMPUTE_BIT
;
484 radv_dump_pipeline_state(compute_pipeline
, active_stages
, f
);
487 radv_dump_descriptors(device
, f
);
491 radv_dump_compute_state(struct radv_device
*device
,
492 struct radv_pipeline
*compute_pipeline
, FILE *f
)
494 VkShaderStageFlagBits active_stages
= VK_SHADER_STAGE_COMPUTE_BIT
;
496 if (!compute_pipeline
)
499 radv_dump_pipeline_state(compute_pipeline
, active_stages
, f
);
500 radv_dump_descriptors(device
, f
);
503 static struct radv_pipeline
*
504 radv_get_saved_graphics_pipeline(struct radv_device
*device
)
506 uint64_t *ptr
= (uint64_t *)device
->trace_id_ptr
;
508 return *(struct radv_pipeline
**)(ptr
+ 1);
511 static struct radv_pipeline
*
512 radv_get_saved_compute_pipeline(struct radv_device
*device
)
514 uint64_t *ptr
= (uint64_t *)device
->trace_id_ptr
;
516 return *(struct radv_pipeline
**)(ptr
+ 2);
520 radv_dump_dmesg(FILE *f
)
525 p
= popen("dmesg | tail -n60", "r");
529 fprintf(f
, "\nLast 60 lines of dmesg:\n\n");
530 while (fgets(line
, sizeof(line
), p
))
538 radv_dump_enabled_options(struct radv_device
*device
, FILE *f
)
542 if (device
->instance
->debug_flags
) {
543 fprintf(f
, "Enabled debug options: ");
545 mask
= device
->instance
->debug_flags
;
547 int i
= u_bit_scan64(&mask
);
548 fprintf(f
, "%s, ", radv_get_debug_option_name(i
));
553 if (device
->instance
->perftest_flags
) {
554 fprintf(f
, "Enabled perftest options: ");
556 mask
= device
->instance
->perftest_flags
;
558 int i
= u_bit_scan64(&mask
);
559 fprintf(f
, "%s, ", radv_get_perftest_option_name(i
));
566 radv_dump_device_name(struct radv_device
*device
, FILE *f
)
568 struct radeon_info
*info
= &device
->physical_device
->rad_info
;
569 char kernel_version
[128] = {};
570 struct utsname uname_data
;
571 const char *chip_name
;
573 chip_name
= device
->ws
->get_chip_name(device
->ws
);
575 if (uname(&uname_data
) == 0)
576 snprintf(kernel_version
, sizeof(kernel_version
),
577 " / %s", uname_data
.release
);
579 fprintf(f
, "Device name: %s (%s / DRM %i.%i.%i%s)\n\n",
580 chip_name
, device
->physical_device
->name
,
581 info
->drm_major
, info
->drm_minor
, info
->drm_patchlevel
,
586 radv_gpu_hang_occured(struct radv_queue
*queue
, enum ring_type ring
)
588 struct radeon_winsys
*ws
= queue
->device
->ws
;
590 if (!ws
->ctx_wait_idle(queue
->hw_ctx
, ring
, queue
->queue_idx
))
597 radv_check_gpu_hangs(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
)
599 struct radv_pipeline
*graphics_pipeline
, *compute_pipeline
;
600 struct radv_device
*device
= queue
->device
;
604 ring
= radv_queue_family_to_ring(queue
->queue_family_index
);
606 bool hang_occurred
= radv_gpu_hang_occured(queue
, ring
);
607 bool vm_fault_occurred
= false;
608 if (queue
->device
->instance
->debug_flags
& RADV_DEBUG_VM_FAULTS
)
609 vm_fault_occurred
= ac_vm_fault_occured(device
->physical_device
->rad_info
.chip_class
,
610 &device
->dmesg_timestamp
, &addr
);
611 if (!hang_occurred
&& !vm_fault_occurred
)
614 graphics_pipeline
= radv_get_saved_graphics_pipeline(device
);
615 compute_pipeline
= radv_get_saved_compute_pipeline(device
);
617 radv_dump_trace(queue
->device
, cs
);
619 fprintf(stderr
, "GPU hang report:\n\n");
620 radv_dump_device_name(device
, stderr
);
622 radv_dump_enabled_options(device
, stderr
);
623 radv_dump_dmesg(stderr
);
625 if (vm_fault_occurred
) {
626 fprintf(stderr
, "VM fault report.\n\n");
627 fprintf(stderr
, "Failing VM page: 0x%08"PRIx64
"\n\n", addr
);
630 radv_dump_debug_registers(device
, stderr
);
634 fprintf(stderr
, "RING_GFX:\n");
635 radv_dump_graphics_state(queue
->device
,
636 graphics_pipeline
, compute_pipeline
,
640 fprintf(stderr
, "RING_COMPUTE:\n");
641 radv_dump_compute_state(queue
->device
,
642 compute_pipeline
, stderr
);
653 radv_print_spirv(const char *data
, uint32_t size
, FILE *fp
)
655 char path
[] = "/tmp/fileXXXXXX";
656 char line
[2048], command
[128];
660 /* Dump the binary into a temporary file. */
665 if (write(fd
, data
, size
) == -1)
668 sprintf(command
, "spirv-dis %s", path
);
670 /* Disassemble using spirv-dis if installed. */
671 p
= popen(command
, "r");
673 while (fgets(line
, sizeof(line
), p
))
674 fprintf(fp
, "%s", line
);
684 radv_trap_handler_init(struct radv_device
*device
)
686 struct radeon_winsys
*ws
= device
->ws
;
688 /* Create the trap handler shader and upload it like other shaders. */
689 device
->trap_handler_shader
= radv_create_trap_handler_shader(device
);
690 if (!device
->trap_handler_shader
) {
691 fprintf(stderr
, "radv: failed to create the trap handler shader.\n");
695 device
->tma_bo
= ws
->buffer_create(ws
, TMA_BO_SIZE
, 256,
697 RADEON_FLAG_CPU_ACCESS
|
698 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
699 RADEON_FLAG_ZERO_VRAM
|
701 RADV_BO_PRIORITY_SCRATCH
);
705 device
->tma_ptr
= ws
->buffer_map(device
->tma_bo
);
706 if (!device
->tma_ptr
)
709 /* Upload a buffer descriptor to store various info from the trap. */
710 uint64_t tma_va
= radv_buffer_get_va(device
->tma_bo
) + 16;
714 desc
[1] = S_008F04_BASE_ADDRESS_HI(tma_va
>> 32);
715 desc
[2] = TMA_BO_SIZE
;
716 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
717 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
718 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
719 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
720 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
722 memcpy(device
->tma_ptr
, desc
, sizeof(desc
));
728 radv_trap_handler_finish(struct radv_device
*device
)
730 struct radeon_winsys
*ws
= device
->ws
;
732 if (unlikely(device
->trap_handler_shader
))
733 radv_shader_variant_destroy(device
, device
->trap_handler_shader
);
735 if (unlikely(device
->tma_bo
))
736 ws
->buffer_destroy(device
->tma_bo
);
739 static struct radv_shader_variant
*
740 radv_get_faulty_shader(struct radv_device
*device
, uint64_t faulty_pc
)
742 struct radv_shader_variant
*shader
= NULL
;
744 mtx_lock(&device
->shader_slab_mutex
);
745 list_for_each_entry(struct radv_shader_slab
, slab
, &device
->shader_slabs
, slabs
) {
746 list_for_each_entry(struct radv_shader_variant
, s
, &slab
->shaders
, slab_list
) {
747 uint64_t offset
= align_u64(s
->bo_offset
+ s
->code_size
, 256);
748 uint64_t va
= radv_buffer_get_va(s
->bo
);
750 if (faulty_pc
>= va
+ s
->bo_offset
&& faulty_pc
< va
+ offset
) {
751 mtx_unlock(&device
->shader_slab_mutex
);
756 mtx_unlock(&device
->shader_slab_mutex
);
762 radv_dump_faulty_shader(struct radv_device
*device
, uint64_t faulty_pc
)
764 struct radv_shader_variant
*shader
;
765 uint64_t start_addr
, end_addr
;
766 uint32_t instr_offset
;
768 shader
= radv_get_faulty_shader(device
, faulty_pc
);
772 start_addr
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
773 end_addr
= start_addr
+ shader
->code_size
;
774 instr_offset
= faulty_pc
- start_addr
;
776 fprintf(stderr
, "Faulty shader found "
777 "VA=[0x%"PRIx64
"-0x%"PRIx64
"], instr_offset=%d\n",
778 start_addr
, end_addr
, instr_offset
);
780 /* Get the list of instructions.
781 * Buffer size / 4 is the upper bound of the instruction count.
783 unsigned num_inst
= 0;
784 struct radv_shader_inst
*instructions
=
785 calloc(shader
->code_size
/ 4, sizeof(struct radv_shader_inst
));
787 /* Split the disassembly string into instructions. */
788 si_add_split_disasm(shader
->disasm_string
, start_addr
, &num_inst
, instructions
);
790 /* Print instructions with annotations. */
791 for (unsigned i
= 0; i
< num_inst
; i
++) {
792 struct radv_shader_inst
*inst
= &instructions
[i
];
794 if (start_addr
+ inst
->offset
== faulty_pc
) {
795 fprintf(stderr
, "\n!!! Faulty instruction below !!!\n");
796 fprintf(stderr
, "%s\n", inst
->text
);
797 fprintf(stderr
, "\n");
799 fprintf(stderr
, "%s\n", inst
->text
);
806 struct radv_sq_hw_reg
{
814 radv_dump_sq_hw_regs(struct radv_device
*device
)
816 struct radv_sq_hw_reg
*regs
= (struct radv_sq_hw_reg
*)&device
->tma_ptr
[6];
818 fprintf(stderr
, "\nHardware registers:\n");
819 ac_dump_reg(stderr
, device
->physical_device
->rad_info
.chip_class
,
820 R_000002_SQ_HW_REG_STATUS
, regs
->status
, ~0);
821 ac_dump_reg(stderr
, device
->physical_device
->rad_info
.chip_class
,
822 R_000003_SQ_HW_REG_TRAP_STS
, regs
->trap_sts
, ~0);
823 ac_dump_reg(stderr
, device
->physical_device
->rad_info
.chip_class
,
824 R_000004_SQ_HW_REG_HW_ID
, regs
->hw_id
, ~0);
825 ac_dump_reg(stderr
, device
->physical_device
->rad_info
.chip_class
,
826 R_000007_SQ_HW_REG_IB_STS
, regs
->ib_sts
, ~0);
827 fprintf(stderr
, "\n\n");
831 radv_check_trap_handler(struct radv_queue
*queue
)
833 enum ring_type ring
= radv_queue_family_to_ring(queue
->queue_family_index
);
834 struct radv_device
*device
= queue
->device
;
835 struct radeon_winsys
*ws
= device
->ws
;
837 /* Wait for the context to be idle in a finite time. */
838 ws
->ctx_wait_idle(queue
->hw_ctx
, ring
, queue
->queue_idx
);
840 /* Try to detect if the trap handler has been reached by the hw by
841 * looking at ttmp0 which should be non-zero if a shader exception
844 if (!device
->tma_ptr
[4])
848 fprintf(stderr
, "tma_ptr:\n");
849 for (unsigned i
= 0; i
< 10; i
++)
850 fprintf(stderr
, "tma_ptr[%d]=0x%x\n", i
, device
->tma_ptr
[i
]);
853 radv_dump_sq_hw_regs(device
);
855 uint32_t ttmp0
= device
->tma_ptr
[4];
856 uint32_t ttmp1
= device
->tma_ptr
[5];
858 /* According to the ISA docs, 3.10 Trap and Exception Registers:
860 * "{ttmp1, ttmp0} = {3'h0, pc_rewind[3:0], HT[0], trapID[7:0], PC[47:0]}"
862 * "When the trap handler is entered, the PC of the faulting
863 * instruction is: (PC - PC_rewind * 4)."
865 uint8_t trap_id
= (ttmp1
>> 16) & 0xff;
866 uint8_t ht
= (ttmp1
>> 24) & 0x1;
867 uint8_t pc_rewind
= (ttmp1
>> 25) & 0xf;
868 uint64_t pc
= (ttmp0
| ((ttmp1
& 0x0000ffffull
) << 32)) - (pc_rewind
* 4);
870 fprintf(stderr
, "PC=0x%"PRIx64
", trapID=%d, HT=%d, PC_rewind=%d\n",
871 pc
, trap_id
, ht
, pc_rewind
);
873 radv_dump_faulty_shader(device
, pc
);