src/amd/vulkan/radv_debug.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #include <stdlib.h>
  29 #include <stdio.h>
  30 #include <sys/utsname.h>
  31
  32 #include "util/mesa-sha1.h"
  33 #include "sid.h"
  34 #include "ac_debug.h"
  35 #include "radv_debug.h"
  36 #include "radv_shader.h"
  37
  38 #define TRACE_BO_SIZE 4096
  39 #define TMA_BO_SIZE 4096
  40
  41 #define COLOR_RESET     "\033[0m"
  42 #define COLOR_RED       "\033[31m"
  43 #define COLOR_GREEN     "\033[1;32m"
  44 #define COLOR_YELLOW    "\033[1;33m"
  45 #define COLOR_CYAN      "\033[1;36m"
  46
  47 /* Trace BO layout (offsets are 4 bytes):
  48  *
  49  * [0]: primary trace ID
  50  * [1]: secondary trace ID
  51  * [2-3]: 64-bit GFX pipeline pointer
  52  * [4-5]: 64-bit COMPUTE pipeline pointer
  53  * [6-7]: 64-bit descriptor set #0 pointer
  54  * ...
  55  * [68-69]: 64-bit descriptor set #31 pointer
  56  */
  57
  58 bool
  59 radv_init_trace(struct radv_device *device)
  60 {
  61         struct radeon_winsys *ws = device->ws;
  62
  63         device->trace_bo = ws->buffer_create(ws, TRACE_BO_SIZE, 8,
  64                                              RADEON_DOMAIN_VRAM,
  65                                              RADEON_FLAG_CPU_ACCESS|
  66                                              RADEON_FLAG_NO_INTERPROCESS_SHARING |
  67                                              RADEON_FLAG_ZERO_VRAM,
  68                                              RADV_BO_PRIORITY_UPLOAD_BUFFER);
  69         if (!device->trace_bo)
  70                 return false;
  71
  72         device->trace_id_ptr = ws->buffer_map(device->trace_bo);
  73         if (!device->trace_id_ptr)
  74                 return false;
  75
  76         ac_vm_fault_occured(device->physical_device->rad_info.chip_class,
  77                             &device->dmesg_timestamp, NULL);
  78
  79         return true;
  80 }
  81
  82 static void
  83 radv_dump_trace(struct radv_device *device, struct radeon_cmdbuf *cs)
  84 {
  85         const char *filename = getenv("RADV_TRACE_FILE");
  86         FILE *f = fopen(filename, "w");
  87
  88         if (!f) {
  89                 fprintf(stderr, "Failed to write trace dump to %s\n", filename);
  90                 return;
  91         }
  92
  93         fprintf(f, "Trace ID: %x\n", *device->trace_id_ptr);
  94         device->ws->cs_dump(cs, f, (const int*)device->trace_id_ptr, 2);
  95         fclose(f);
  96 }
  97
  98 static void
  99 radv_dump_mmapped_reg(struct radv_device *device, FILE *f, unsigned offset)
 100 {
 101         struct radeon_winsys *ws = device->ws;
 102         uint32_t value;
 103
 104         if (ws->read_registers(ws, offset, 1, &value))
 105                 ac_dump_reg(f, device->physical_device->rad_info.chip_class,
 106                             offset, value, ~0);
 107 }
 108
 109 static void
 110 radv_dump_debug_registers(struct radv_device *device, FILE *f)
 111 {
 112         struct radeon_info *info = &device->physical_device->rad_info;
 113
 114         fprintf(f, "Memory-mapped registers:\n");
 115         radv_dump_mmapped_reg(device, f, R_008010_GRBM_STATUS);
 116
 117         /* No other registers can be read on DRM < 3.1.0. */
 118         if (info->drm_minor < 1) {
 119                 fprintf(f, "\n");
 120                 return;
 121         }
 122
 123         radv_dump_mmapped_reg(device, f, R_008008_GRBM_STATUS2);
 124         radv_dump_mmapped_reg(device, f, R_008014_GRBM_STATUS_SE0);
 125         radv_dump_mmapped_reg(device, f, R_008018_GRBM_STATUS_SE1);
 126         radv_dump_mmapped_reg(device, f, R_008038_GRBM_STATUS_SE2);
 127         radv_dump_mmapped_reg(device, f, R_00803C_GRBM_STATUS_SE3);
 128         radv_dump_mmapped_reg(device, f, R_00D034_SDMA0_STATUS_REG);
 129         radv_dump_mmapped_reg(device, f, R_00D834_SDMA1_STATUS_REG);
 130         if (info->chip_class <= GFX8) {
 131                 radv_dump_mmapped_reg(device, f, R_000E50_SRBM_STATUS);
 132                 radv_dump_mmapped_reg(device, f, R_000E4C_SRBM_STATUS2);
 133                 radv_dump_mmapped_reg(device, f, R_000E54_SRBM_STATUS3);
 134         }
 135         radv_dump_mmapped_reg(device, f, R_008680_CP_STAT);
 136         radv_dump_mmapped_reg(device, f, R_008674_CP_STALLED_STAT1);
 137         radv_dump_mmapped_reg(device, f, R_008678_CP_STALLED_STAT2);
 138         radv_dump_mmapped_reg(device, f, R_008670_CP_STALLED_STAT3);
 139         radv_dump_mmapped_reg(device, f, R_008210_CP_CPC_STATUS);
 140         radv_dump_mmapped_reg(device, f, R_008214_CP_CPC_BUSY_STAT);
 141         radv_dump_mmapped_reg(device, f, R_008218_CP_CPC_STALLED_STAT1);
 142         radv_dump_mmapped_reg(device, f, R_00821C_CP_CPF_STATUS);
 143         radv_dump_mmapped_reg(device, f, R_008220_CP_CPF_BUSY_STAT);
 144         radv_dump_mmapped_reg(device, f, R_008224_CP_CPF_STALLED_STAT1);
 145         fprintf(f, "\n");
 146 }
 147
 148 static void
 149 radv_dump_buffer_descriptor(enum chip_class chip_class, const uint32_t *desc,
 150                             FILE *f)
 151 {
 152         fprintf(f, COLOR_CYAN "    Buffer:" COLOR_RESET "\n");
 153         for (unsigned j = 0; j < 4; j++)
 154                 ac_dump_reg(f, chip_class, R_008F00_SQ_BUF_RSRC_WORD0 + j * 4,
 155                             desc[j], 0xffffffff);
 156 }
 157
 158 static void
 159 radv_dump_image_descriptor(enum chip_class chip_class, const uint32_t *desc,
 160                            FILE *f)
 161 {
 162         unsigned sq_img_rsrc_word0 = chip_class >= GFX10 ? R_00A000_SQ_IMG_RSRC_WORD0
 163                                                          : R_008F10_SQ_IMG_RSRC_WORD0;
 164
 165         fprintf(f, COLOR_CYAN "    Image:" COLOR_RESET "\n");
 166         for (unsigned j = 0; j < 8; j++)
 167                 ac_dump_reg(f, chip_class, sq_img_rsrc_word0 + j * 4,
 168                             desc[j], 0xffffffff);
 169
 170         fprintf(f, COLOR_CYAN "    FMASK:" COLOR_RESET "\n");
 171         for (unsigned j = 0; j < 8; j++)
 172                 ac_dump_reg(f, chip_class, sq_img_rsrc_word0 + j * 4,
 173                             desc[8 + j], 0xffffffff);
 174 }
 175
 176 static void
 177 radv_dump_sampler_descriptor(enum chip_class chip_class, const uint32_t *desc,
 178                              FILE *f)
 179 {
 180         fprintf(f, COLOR_CYAN "    Sampler state:" COLOR_RESET "\n");
 181         for (unsigned j = 0; j < 4; j++) {
 182                 ac_dump_reg(f, chip_class, R_008F30_SQ_IMG_SAMP_WORD0 + j * 4,
 183                             desc[j], 0xffffffff);
 184         }
 185 }
 186
 187 static void
 188 radv_dump_combined_image_sampler_descriptor(enum chip_class chip_class,
 189                                             const uint32_t *desc, FILE *f)
 190 {
 191         radv_dump_image_descriptor(chip_class, desc, f);
 192         radv_dump_sampler_descriptor(chip_class, desc + 16, f);
 193 }
 194
 195 static void
 196 radv_dump_descriptor_set(struct radv_device *device,
 197                          struct radv_descriptor_set *set, unsigned id, FILE *f)
 198 {
 199         enum chip_class chip_class = device->physical_device->rad_info.chip_class;
 200         const struct radv_descriptor_set_layout *layout;
 201         int i;
 202
 203         if (!set)
 204                 return;
 205         layout = set->layout;
 206
 207         for (i = 0; i < set->layout->binding_count; i++) {
 208                 uint32_t *desc =
 209                         set->mapped_ptr + layout->binding[i].offset / 4;
 210
 211                 switch (layout->binding[i].type) {
 212                 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
 213                 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
 214                 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
 215                 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
 216                         radv_dump_buffer_descriptor(chip_class, desc, f);
 217                         break;
 218                 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
 219                 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
 220                 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
 221                         radv_dump_image_descriptor(chip_class, desc, f);
 222                         break;
 223                 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
 224                         radv_dump_combined_image_sampler_descriptor(chip_class, desc, f);
 225                         break;
 226                 case VK_DESCRIPTOR_TYPE_SAMPLER:
 227                         radv_dump_sampler_descriptor(chip_class, desc, f);
 228                         break;
 229                 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
 230                 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
 231                         /* todo */
 232                         break;
 233                 default:
 234                         assert(!"unknown descriptor type");
 235                         break;
 236                 }
 237                 fprintf(f, "\n");
 238         }
 239         fprintf(f, "\n\n");
 240 }
 241
 242 static void
 243 radv_dump_descriptors(struct radv_device *device, FILE *f)
 244 {
 245         uint64_t *ptr = (uint64_t *)device->trace_id_ptr;
 246         int i;
 247
 248         fprintf(f, "Descriptors:\n");
 249         for (i = 0; i < MAX_SETS; i++) {
 250                 struct radv_descriptor_set *set =
 251                         *(struct radv_descriptor_set **)(ptr + i + 3);
 252
 253                 radv_dump_descriptor_set(device, set, i, f);
 254         }
 255 }
 256
 257 struct radv_shader_inst {
 258         char text[160];  /* one disasm line */
 259         unsigned offset; /* instruction offset */
 260         unsigned size;   /* instruction size = 4 or 8 */
 261 };
 262
 263 /* Split a disassembly string into lines and add them to the array pointed
 264  * to by "instructions". */
 265 static void si_add_split_disasm(const char *disasm,
 266                                 uint64_t start_addr,
 267                                 unsigned *num,
 268                                 struct radv_shader_inst *instructions)
 269 {
 270         struct radv_shader_inst *last_inst = *num ? &instructions[*num - 1] : NULL;
 271         char *next;
 272
 273         while ((next = strchr(disasm, '\n'))) {
 274                 struct radv_shader_inst *inst = &instructions[*num];
 275                 unsigned len = next - disasm;
 276
 277                 if (!memchr(disasm, ';', len)) {
 278                         /* Ignore everything that is not an instruction. */
 279                         disasm = next + 1;
 280                         continue;
 281                 }
 282
 283                 assert(len < ARRAY_SIZE(inst->text));
 284                 memcpy(inst->text, disasm, len);
 285                 inst->text[len] = 0;
 286                 inst->offset = last_inst ? last_inst->offset + last_inst->size : 0;
 287
 288                 const char *semicolon = strchr(disasm, ';');
 289                 assert(semicolon);
 290                 /* More than 16 chars after ";" means the instruction is 8 bytes long. */
 291                 inst->size = next - semicolon > 16 ? 8 : 4;
 292
 293                 snprintf(inst->text + len, ARRAY_SIZE(inst->text) - len,
 294                         " [PC=0x%"PRIx64", off=%u, size=%u]",
 295                         start_addr + inst->offset, inst->offset, inst->size);
 296
 297                 last_inst = inst;
 298                 (*num)++;
 299                 disasm = next + 1;
 300         }
 301 }
 302
 303 static void
 304 radv_dump_annotated_shader(struct radv_shader_variant *shader,
 305                            gl_shader_stage stage, struct ac_wave_info *waves,
 306                            unsigned num_waves, FILE *f)
 307 {
 308         uint64_t start_addr, end_addr;
 309         unsigned i;
 310
 311         if (!shader)
 312                 return;
 313
 314         start_addr = radv_buffer_get_va(shader->bo) + shader->bo_offset;
 315         end_addr = start_addr + shader->code_size;
 316
 317         /* See if any wave executes the shader. */
 318         for (i = 0; i < num_waves; i++) {
 319                 if (start_addr <= waves[i].pc && waves[i].pc <= end_addr)
 320                         break;
 321         }
 322
 323         if (i == num_waves)
 324                 return; /* the shader is not being executed */
 325
 326         /* Remember the first found wave. The waves are sorted according to PC. */
 327         waves = &waves[i];
 328         num_waves -= i;
 329
 330         /* Get the list of instructions.
 331          * Buffer size / 4 is the upper bound of the instruction count.
 332          */
 333         unsigned num_inst = 0;
 334         struct radv_shader_inst *instructions =
 335                 calloc(shader->code_size / 4, sizeof(struct radv_shader_inst));
 336
 337         si_add_split_disasm(shader->disasm_string,
 338                             start_addr, &num_inst, instructions);
 339
 340         fprintf(f, COLOR_YELLOW "%s - annotated disassembly:" COLOR_RESET "\n",
 341                 radv_get_shader_name(&shader->info, stage));
 342
 343         /* Print instructions with annotations. */
 344         for (i = 0; i < num_inst; i++) {
 345                 struct radv_shader_inst *inst = &instructions[i];
 346
 347                 fprintf(f, "%s\n", inst->text);
 348
 349                 /* Print which waves execute the instruction right now. */
 350                 while (num_waves && start_addr + inst->offset == waves->pc) {
 351                         fprintf(f,
 352                                 "          " COLOR_GREEN "^ SE%u SH%u CU%u "
 353                                 "SIMD%u WAVE%u  EXEC=%016"PRIx64 "  ",
 354                                 waves->se, waves->sh, waves->cu, waves->simd,
 355                                 waves->wave, waves->exec);
 356
 357                         if (inst->size == 4) {
 358                                 fprintf(f, "INST32=%08X" COLOR_RESET "\n",
 359                                         waves->inst_dw0);
 360                         } else {
 361                                 fprintf(f, "INST64=%08X %08X" COLOR_RESET "\n",
 362                                         waves->inst_dw0, waves->inst_dw1);
 363                         }
 364
 365                         waves->matched = true;
 366                         waves = &waves[1];
 367                         num_waves--;
 368                 }
 369         }
 370
 371         fprintf(f, "\n\n");
 372         free(instructions);
 373 }
 374
 375 static void
 376 radv_dump_annotated_shaders(struct radv_pipeline *pipeline,
 377                             VkShaderStageFlagBits active_stages, FILE *f)
 378 {
 379         struct ac_wave_info waves[AC_MAX_WAVES_PER_CHIP];
 380         enum chip_class chip_class = pipeline->device->physical_device->rad_info.chip_class;
 381         unsigned num_waves = ac_get_wave_info(chip_class, waves);
 382
 383         fprintf(f, COLOR_CYAN "The number of active waves = %u" COLOR_RESET
 384                 "\n\n", num_waves);
 385
 386         /* Dump annotated active graphics shaders. */
 387         while (active_stages) {
 388                 int stage = u_bit_scan(&active_stages);
 389
 390                 radv_dump_annotated_shader(pipeline->shaders[stage],
 391                                            stage, waves, num_waves, f);
 392         }
 393
 394         /* Print waves executing shaders that are not currently bound. */
 395         unsigned i;
 396         bool found = false;
 397         for (i = 0; i < num_waves; i++) {
 398                 if (waves[i].matched)
 399                         continue;
 400
 401                 if (!found) {
 402                         fprintf(f, COLOR_CYAN
 403                                 "Waves not executing currently-bound shaders:"
 404                                 COLOR_RESET "\n");
 405                         found = true;
 406                 }
 407                 fprintf(f, "    SE%u SH%u CU%u SIMD%u WAVE%u  EXEC=%016"PRIx64
 408                         "  INST=%08X %08X  PC=%"PRIx64"\n",
 409                         waves[i].se, waves[i].sh, waves[i].cu, waves[i].simd,
 410                         waves[i].wave, waves[i].exec, waves[i].inst_dw0,
 411                         waves[i].inst_dw1, waves[i].pc);
 412         }
 413         if (found)
 414                 fprintf(f, "\n\n");
 415 }
 416
 417 static void
 418 radv_dump_shader(struct radv_pipeline *pipeline,
 419                  struct radv_shader_variant *shader, gl_shader_stage stage,
 420                  FILE *f)
 421 {
 422         if (!shader)
 423                 return;
 424
 425         fprintf(f, "%s:\n\n", radv_get_shader_name(&shader->info, stage));
 426
 427         if (shader->spirv) {
 428                 unsigned char sha1[21];
 429                 char sha1buf[41];
 430
 431                 _mesa_sha1_compute(shader->spirv, shader->spirv_size, sha1);
 432                 _mesa_sha1_format(sha1buf, sha1);
 433
 434                 fprintf(f, "SPIRV (sha1: %s):\n", sha1buf);
 435                 radv_print_spirv(shader->spirv, shader->spirv_size, f);
 436         }
 437
 438         if (shader->nir_string) {
 439                 fprintf(f, "NIR:\n%s\n", shader->nir_string);
 440         }
 441
 442         fprintf(f, "%s IR:\n%s\n",
 443                 pipeline->device->physical_device->use_llvm ? "LLVM" : "ACO",
 444                 shader->ir_string);
 445         fprintf(f, "DISASM:\n%s\n", shader->disasm_string);
 446
 447         radv_shader_dump_stats(pipeline->device, shader, stage, f);
 448 }
 449
 450 static void
 451 radv_dump_shaders(struct radv_pipeline *pipeline,
 452                   VkShaderStageFlagBits active_stages, FILE *f)
 453 {
 454         /* Dump active graphics shaders. */
 455         while (active_stages) {
 456                 int stage = u_bit_scan(&active_stages);
 457
 458                 radv_dump_shader(pipeline, pipeline->shaders[stage], stage, f);
 459         }
 460 }
 461
 462 static void
 463 radv_dump_pipeline_state(struct radv_pipeline *pipeline,
 464                          VkShaderStageFlagBits active_stages, FILE *f)
 465 {
 466         radv_dump_shaders(pipeline, active_stages, f);
 467         radv_dump_annotated_shaders(pipeline, active_stages, f);
 468 }
 469
 470 static void
 471 radv_dump_graphics_state(struct radv_device *device,
 472                          struct radv_pipeline *graphics_pipeline,
 473                          struct radv_pipeline *compute_pipeline, FILE *f)
 474 {
 475         VkShaderStageFlagBits active_stages;
 476
 477         if (graphics_pipeline) {
 478                 active_stages = graphics_pipeline->active_stages;
 479                 radv_dump_pipeline_state(graphics_pipeline, active_stages, f);
 480         }
 481
 482         if (compute_pipeline) {
 483                 active_stages = VK_SHADER_STAGE_COMPUTE_BIT;
 484                 radv_dump_pipeline_state(compute_pipeline, active_stages, f);
 485         }
 486
 487         radv_dump_descriptors(device, f);
 488 }
 489
 490 static void
 491 radv_dump_compute_state(struct radv_device *device,
 492                         struct radv_pipeline *compute_pipeline, FILE *f)
 493 {
 494         VkShaderStageFlagBits active_stages = VK_SHADER_STAGE_COMPUTE_BIT;
 495
 496         if (!compute_pipeline)
 497                 return;
 498
 499         radv_dump_pipeline_state(compute_pipeline, active_stages, f);
 500         radv_dump_descriptors(device, f);
 501 }
 502
 503 static struct radv_pipeline *
 504 radv_get_saved_graphics_pipeline(struct radv_device *device)
 505 {
 506         uint64_t *ptr = (uint64_t *)device->trace_id_ptr;
 507
 508         return *(struct radv_pipeline **)(ptr + 1);
 509 }
 510
 511 static struct radv_pipeline *
 512 radv_get_saved_compute_pipeline(struct radv_device *device)
 513 {
 514         uint64_t *ptr = (uint64_t *)device->trace_id_ptr;
 515
 516         return *(struct radv_pipeline **)(ptr + 2);
 517 }
 518
 519 static void
 520 radv_dump_dmesg(FILE *f)
 521 {
 522         char line[2000];
 523         FILE *p;
 524
 525         p = popen("dmesg | tail -n60", "r");
 526         if (!p)
 527                 return;
 528
 529         fprintf(f, "\nLast 60 lines of dmesg:\n\n");
 530         while (fgets(line, sizeof(line), p))
 531                 fputs(line, f);
 532         fprintf(f, "\n");
 533
 534         pclose(p);
 535 }
 536
 537 void
 538 radv_dump_enabled_options(struct radv_device *device, FILE *f)
 539 {
 540         uint64_t mask;
 541
 542         if (device->instance->debug_flags) {
 543                 fprintf(f, "Enabled debug options: ");
 544
 545                 mask = device->instance->debug_flags;
 546                 while (mask) {
 547                         int i = u_bit_scan64(&mask);
 548                         fprintf(f, "%s, ", radv_get_debug_option_name(i));
 549                 }
 550                 fprintf(f, "\n");
 551         }
 552
 553         if (device->instance->perftest_flags) {
 554                 fprintf(f, "Enabled perftest options: ");
 555
 556                 mask = device->instance->perftest_flags;
 557                 while (mask) {
 558                         int i = u_bit_scan64(&mask);
 559                         fprintf(f, "%s, ", radv_get_perftest_option_name(i));
 560                 }
 561                 fprintf(f, "\n");
 562         }
 563 }
 564
 565 static void
 566 radv_dump_device_name(struct radv_device *device, FILE *f)
 567 {
 568         struct radeon_info *info = &device->physical_device->rad_info;
 569         char kernel_version[128] = {};
 570         struct utsname uname_data;
 571         const char *chip_name;
 572
 573         chip_name = device->ws->get_chip_name(device->ws);
 574
 575         if (uname(&uname_data) == 0)
 576                 snprintf(kernel_version, sizeof(kernel_version),
 577                          " / %s", uname_data.release);
 578
 579         fprintf(f, "Device name: %s (%s / DRM %i.%i.%i%s)\n\n",
 580                 chip_name, device->physical_device->name,
 581                 info->drm_major, info->drm_minor, info->drm_patchlevel,
 582                 kernel_version);
 583 }
 584
 585 static bool
 586 radv_gpu_hang_occured(struct radv_queue *queue, enum ring_type ring)
 587 {
 588         struct radeon_winsys *ws = queue->device->ws;
 589
 590         if (!ws->ctx_wait_idle(queue->hw_ctx, ring, queue->queue_idx))
 591                 return true;
 592
 593         return false;
 594 }
 595
 596 void
 597 radv_check_gpu_hangs(struct radv_queue *queue, struct radeon_cmdbuf *cs)
 598 {
 599         struct radv_pipeline *graphics_pipeline, *compute_pipeline;
 600         struct radv_device *device = queue->device;
 601         enum ring_type ring;
 602         uint64_t addr;
 603
 604         ring = radv_queue_family_to_ring(queue->queue_family_index);
 605
 606         bool hang_occurred = radv_gpu_hang_occured(queue, ring);
 607         bool vm_fault_occurred = false;
 608         if (queue->device->instance->debug_flags & RADV_DEBUG_VM_FAULTS)
 609                 vm_fault_occurred = ac_vm_fault_occured(device->physical_device->rad_info.chip_class,
 610                                                         &device->dmesg_timestamp, &addr);
 611         if (!hang_occurred && !vm_fault_occurred)
 612                 return;
 613
 614         graphics_pipeline = radv_get_saved_graphics_pipeline(device);
 615         compute_pipeline = radv_get_saved_compute_pipeline(device);
 616
 617         radv_dump_trace(queue->device, cs);
 618
 619         fprintf(stderr, "GPU hang report:\n\n");
 620         radv_dump_device_name(device, stderr);
 621
 622         radv_dump_enabled_options(device, stderr);
 623         radv_dump_dmesg(stderr);
 624
 625         if (vm_fault_occurred) {
 626                 fprintf(stderr, "VM fault report.\n\n");
 627                 fprintf(stderr, "Failing VM page: 0x%08"PRIx64"\n\n", addr);
 628         }
 629
 630         radv_dump_debug_registers(device, stderr);
 631
 632         switch (ring) {
 633         case RING_GFX:
 634                 fprintf(stderr, "RING_GFX:\n");
 635                 radv_dump_graphics_state(queue->device,
 636                                          graphics_pipeline, compute_pipeline,
 637                                          stderr);
 638                 break;
 639         case RING_COMPUTE:
 640                 fprintf(stderr, "RING_COMPUTE:\n");
 641                 radv_dump_compute_state(queue->device,
 642                                         compute_pipeline, stderr);
 643                 break;
 644         default:
 645                 assert(0);
 646                 break;
 647         }
 648
 649         abort();
 650 }
 651
 652 void
 653 radv_print_spirv(const char *data, uint32_t size, FILE *fp)
 654 {
 655         char path[] = "/tmp/fileXXXXXX";
 656         char line[2048], command[128];
 657         FILE *p;
 658         int fd;
 659
 660         /* Dump the binary into a temporary file. */
 661         fd = mkstemp(path);
 662         if (fd < 0)
 663                 return;
 664
 665         if (write(fd, data, size) == -1)
 666                 goto fail;
 667
 668         sprintf(command, "spirv-dis %s", path);
 669
 670         /* Disassemble using spirv-dis if installed. */
 671         p = popen(command, "r");
 672         if (p) {
 673                 while (fgets(line, sizeof(line), p))
 674                         fprintf(fp, "%s", line);
 675                 pclose(p);
 676         }
 677
 678 fail:
 679         close(fd);
 680         unlink(path);
 681 }
 682
 683 bool
 684 radv_trap_handler_init(struct radv_device *device)
 685 {
 686         struct radeon_winsys *ws = device->ws;
 687
 688         /* Create the trap handler shader and upload it like other shaders. */
 689         device->trap_handler_shader = radv_create_trap_handler_shader(device);
 690         if (!device->trap_handler_shader) {
 691                 fprintf(stderr, "radv: failed to create the trap handler shader.\n");
 692                 return false;
 693         }
 694
 695         device->tma_bo = ws->buffer_create(ws, TMA_BO_SIZE, 256,
 696                                            RADEON_DOMAIN_VRAM,
 697                                            RADEON_FLAG_CPU_ACCESS |
 698                                            RADEON_FLAG_NO_INTERPROCESS_SHARING |
 699                                            RADEON_FLAG_ZERO_VRAM |
 700                                            RADEON_FLAG_32BIT,
 701                                            RADV_BO_PRIORITY_SCRATCH);
 702         if (!device->tma_bo)
 703                 return false;
 704
 705         device->tma_ptr = ws->buffer_map(device->tma_bo);
 706         if (!device->tma_ptr)
 707                 return false;
 708
 709         /* Upload a buffer descriptor to store various info from the trap. */
 710         uint64_t tma_va = radv_buffer_get_va(device->tma_bo) + 16;
 711         uint32_t desc[4];
 712
 713         desc[0] = tma_va;
 714         desc[1] = S_008F04_BASE_ADDRESS_HI(tma_va >> 32);
 715         desc[2] = TMA_BO_SIZE;
 716         desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
 717                   S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
 718                   S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
 719                   S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
 720                   S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
 721
 722         memcpy(device->tma_ptr, desc, sizeof(desc));
 723
 724         return true;
 725 }
 726
 727 void
 728 radv_trap_handler_finish(struct radv_device *device)
 729 {
 730         struct radeon_winsys *ws = device->ws;
 731
 732         if (unlikely(device->trap_handler_shader))
 733                 radv_shader_variant_destroy(device, device->trap_handler_shader);
 734
 735         if (unlikely(device->tma_bo))
 736                 ws->buffer_destroy(device->tma_bo);
 737 }
 738
 739 static struct radv_shader_variant *
 740 radv_get_faulty_shader(struct radv_device *device, uint64_t faulty_pc)
 741 {
 742         struct radv_shader_variant *shader = NULL;
 743
 744         mtx_lock(&device->shader_slab_mutex);
 745         list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
 746                 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
 747                         uint64_t offset = align_u64(s->bo_offset + s->code_size, 256);
 748                         uint64_t va = radv_buffer_get_va(s->bo);
 749
 750                         if (faulty_pc >= va + s->bo_offset && faulty_pc < va + offset) {
 751                                 mtx_unlock(&device->shader_slab_mutex);
 752                                 return s;
 753                         }
 754                 }
 755         }
 756         mtx_unlock(&device->shader_slab_mutex);
 757
 758         return shader;
 759 }
 760
 761 static void
 762 radv_dump_faulty_shader(struct radv_device *device, uint64_t faulty_pc)
 763 {
 764         struct radv_shader_variant *shader;
 765         uint64_t start_addr, end_addr;
 766         uint32_t instr_offset;
 767
 768         shader = radv_get_faulty_shader(device, faulty_pc);
 769         if (!shader)
 770                 return;
 771
 772         start_addr = radv_buffer_get_va(shader->bo) + shader->bo_offset;
 773         end_addr = start_addr + shader->code_size;
 774         instr_offset = faulty_pc - start_addr;
 775
 776         fprintf(stderr, "Faulty shader found "
 777                         "VA=[0x%"PRIx64"-0x%"PRIx64"], instr_offset=%d\n",
 778                 start_addr, end_addr, instr_offset);
 779
 780         /* Get the list of instructions.
 781          * Buffer size / 4 is the upper bound of the instruction count.
 782          */
 783         unsigned num_inst = 0;
 784         struct radv_shader_inst *instructions =
 785                 calloc(shader->code_size / 4, sizeof(struct radv_shader_inst));
 786
 787         /* Split the disassembly string into instructions. */
 788         si_add_split_disasm(shader->disasm_string, start_addr, &num_inst, instructions);
 789
 790         /* Print instructions with annotations. */
 791         for (unsigned i = 0; i < num_inst; i++) {
 792                 struct radv_shader_inst *inst = &instructions[i];
 793
 794                 if (start_addr + inst->offset == faulty_pc) {
 795                         fprintf(stderr, "\n!!! Faulty instruction below !!!\n");
 796                         fprintf(stderr, "%s\n", inst->text);
 797                         fprintf(stderr, "\n");
 798                 } else {
 799                         fprintf(stderr, "%s\n", inst->text);
 800                 }
 801         }
 802
 803         free(instructions);
 804 }
 805
 806 struct radv_sq_hw_reg {
 807         uint32_t status;
 808         uint32_t trap_sts;
 809         uint32_t hw_id;
 810         uint32_t ib_sts;
 811 };
 812
 813 static void
 814 radv_dump_sq_hw_regs(struct radv_device *device)
 815 {
 816         struct radv_sq_hw_reg *regs = (struct radv_sq_hw_reg *)&device->tma_ptr[6];
 817
 818         fprintf(stderr, "\nHardware registers:\n");
 819         ac_dump_reg(stderr, device->physical_device->rad_info.chip_class,
 820                     R_000002_SQ_HW_REG_STATUS, regs->status, ~0);
 821         ac_dump_reg(stderr, device->physical_device->rad_info.chip_class,
 822                     R_000003_SQ_HW_REG_TRAP_STS, regs->trap_sts, ~0);
 823         ac_dump_reg(stderr, device->physical_device->rad_info.chip_class,
 824                     R_000004_SQ_HW_REG_HW_ID, regs->hw_id, ~0);
 825         ac_dump_reg(stderr, device->physical_device->rad_info.chip_class,
 826                     R_000007_SQ_HW_REG_IB_STS, regs->ib_sts, ~0);
 827         fprintf(stderr, "\n\n");
 828 }
 829
 830 void
 831 radv_check_trap_handler(struct radv_queue *queue)
 832 {
 833         enum ring_type ring = radv_queue_family_to_ring(queue->queue_family_index);
 834         struct radv_device *device = queue->device;
 835         struct radeon_winsys *ws = device->ws;
 836
 837         /* Wait for the context to be idle in a finite time. */
 838         ws->ctx_wait_idle(queue->hw_ctx, ring, queue->queue_idx);
 839
 840         /* Try to detect if the trap handler has been reached by the hw by
 841          * looking at ttmp0 which should be non-zero if a shader exception
 842          * happened.
 843          */
 844         if (!device->tma_ptr[4])
 845                 return;
 846
 847 #if 0
 848         fprintf(stderr, "tma_ptr:\n");
 849         for (unsigned i = 0; i < 10; i++)
 850                 fprintf(stderr, "tma_ptr[%d]=0x%x\n", i, device->tma_ptr[i]);
 851 #endif
 852
 853         radv_dump_sq_hw_regs(device);
 854
 855         uint32_t ttmp0 = device->tma_ptr[4];
 856         uint32_t ttmp1 = device->tma_ptr[5];
 857
 858         /* According to the ISA docs, 3.10 Trap and Exception Registers:
 859          *
 860          * "{ttmp1, ttmp0} = {3'h0, pc_rewind[3:0], HT[0], trapID[7:0], PC[47:0]}"
 861          *
 862          * "When the trap handler is entered, the PC of the faulting
 863          *  instruction is: (PC - PC_rewind * 4)."
 864          * */
 865         uint8_t trap_id = (ttmp1 >> 16) & 0xff;
 866         uint8_t ht = (ttmp1 >> 24) & 0x1;
 867         uint8_t pc_rewind = (ttmp1 >> 25) & 0xf;
 868         uint64_t pc = (ttmp0 | ((ttmp1 & 0x0000ffffull) << 32)) - (pc_rewind * 4);
 869
 870         fprintf(stderr, "PC=0x%"PRIx64", trapID=%d, HT=%d, PC_rewind=%d\n",
 871                 pc, trap_id, ht, pc_rewind);
 872
 873         radv_dump_faulty_shader(device, pc);
 874
 875         abort();
 876 }