src/amd/vulkan/radv_debug.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #include <stdlib.h>
  29 #include <stdio.h>
  30 #include <sys/utsname.h>
  31
  32 #include "util/mesa-sha1.h"
  33 #include "sid.h"
  34 #include "ac_debug.h"
  35 #include "radv_debug.h"
  36 #include "radv_shader.h"
  37
  38 #define TRACE_BO_SIZE 4096
  39
  40 #define COLOR_RESET     "\033[0m"
  41 #define COLOR_RED       "\033[31m"
  42 #define COLOR_GREEN     "\033[1;32m"
  43 #define COLOR_YELLOW    "\033[1;33m"
  44 #define COLOR_CYAN      "\033[1;36m"
  45
  46 /* Trace BO layout (offsets are 4 bytes):
  47  *
  48  * [0]: primary trace ID
  49  * [1]: secondary trace ID
  50  * [2-3]: 64-bit GFX pipeline pointer
  51  * [4-5]: 64-bit COMPUTE pipeline pointer
  52  * [6-7]: 64-bit descriptor set #0 pointer
  53  * ...
  54  * [68-69]: 64-bit descriptor set #31 pointer
  55  */
  56
  57 bool
  58 radv_init_trace(struct radv_device *device)
  59 {
  60         struct radeon_winsys *ws = device->ws;
  61
  62         device->trace_bo = ws->buffer_create(ws, TRACE_BO_SIZE, 8,
  63                                              RADEON_DOMAIN_VRAM,
  64                                              RADEON_FLAG_CPU_ACCESS|
  65                                              RADEON_FLAG_NO_INTERPROCESS_SHARING,
  66                                              RADV_BO_PRIORITY_UPLOAD_BUFFER);
  67         if (!device->trace_bo)
  68                 return false;
  69
  70         device->trace_id_ptr = ws->buffer_map(device->trace_bo);
  71         if (!device->trace_id_ptr)
  72                 return false;
  73
  74         memset(device->trace_id_ptr, 0, TRACE_BO_SIZE);
  75
  76         ac_vm_fault_occured(device->physical_device->rad_info.chip_class,
  77                             &device->dmesg_timestamp, NULL);
  78
  79         return true;
  80 }
  81
  82 static void
  83 radv_dump_trace(struct radv_device *device, struct radeon_cmdbuf *cs)
  84 {
  85         const char *filename = getenv("RADV_TRACE_FILE");
  86         FILE *f = fopen(filename, "w");
  87
  88         if (!f) {
  89                 fprintf(stderr, "Failed to write trace dump to %s\n", filename);
  90                 return;
  91         }
  92
  93         fprintf(f, "Trace ID: %x\n", *device->trace_id_ptr);
  94         device->ws->cs_dump(cs, f, (const int*)device->trace_id_ptr, 2);
  95         fclose(f);
  96 }
  97
  98 static void
  99 radv_dump_mmapped_reg(struct radv_device *device, FILE *f, unsigned offset)
 100 {
 101         struct radeon_winsys *ws = device->ws;
 102         uint32_t value;
 103
 104         if (ws->read_registers(ws, offset, 1, &value))
 105                 ac_dump_reg(f, device->physical_device->rad_info.chip_class,
 106                             offset, value, ~0);
 107 }
 108
 109 static void
 110 radv_dump_debug_registers(struct radv_device *device, FILE *f)
 111 {
 112         struct radeon_info *info = &device->physical_device->rad_info;
 113
 114         fprintf(f, "Memory-mapped registers:\n");
 115         radv_dump_mmapped_reg(device, f, R_008010_GRBM_STATUS);
 116
 117         /* No other registers can be read on DRM < 3.1.0. */
 118         if (info->drm_minor < 1) {
 119                 fprintf(f, "\n");
 120                 return;
 121         }
 122
 123         radv_dump_mmapped_reg(device, f, R_008008_GRBM_STATUS2);
 124         radv_dump_mmapped_reg(device, f, R_008014_GRBM_STATUS_SE0);
 125         radv_dump_mmapped_reg(device, f, R_008018_GRBM_STATUS_SE1);
 126         radv_dump_mmapped_reg(device, f, R_008038_GRBM_STATUS_SE2);
 127         radv_dump_mmapped_reg(device, f, R_00803C_GRBM_STATUS_SE3);
 128         radv_dump_mmapped_reg(device, f, R_00D034_SDMA0_STATUS_REG);
 129         radv_dump_mmapped_reg(device, f, R_00D834_SDMA1_STATUS_REG);
 130         if (info->chip_class <= GFX8) {
 131                 radv_dump_mmapped_reg(device, f, R_000E50_SRBM_STATUS);
 132                 radv_dump_mmapped_reg(device, f, R_000E4C_SRBM_STATUS2);
 133                 radv_dump_mmapped_reg(device, f, R_000E54_SRBM_STATUS3);
 134         }
 135         radv_dump_mmapped_reg(device, f, R_008680_CP_STAT);
 136         radv_dump_mmapped_reg(device, f, R_008674_CP_STALLED_STAT1);
 137         radv_dump_mmapped_reg(device, f, R_008678_CP_STALLED_STAT2);
 138         radv_dump_mmapped_reg(device, f, R_008670_CP_STALLED_STAT3);
 139         radv_dump_mmapped_reg(device, f, R_008210_CP_CPC_STATUS);
 140         radv_dump_mmapped_reg(device, f, R_008214_CP_CPC_BUSY_STAT);
 141         radv_dump_mmapped_reg(device, f, R_008218_CP_CPC_STALLED_STAT1);
 142         radv_dump_mmapped_reg(device, f, R_00821C_CP_CPF_STATUS);
 143         radv_dump_mmapped_reg(device, f, R_008220_CP_CPF_BUSY_STAT);
 144         radv_dump_mmapped_reg(device, f, R_008224_CP_CPF_STALLED_STAT1);
 145         fprintf(f, "\n");
 146 }
 147
 148 static void
 149 radv_dump_buffer_descriptor(enum chip_class chip_class, const uint32_t *desc,
 150                             FILE *f)
 151 {
 152         fprintf(f, COLOR_CYAN "    Buffer:" COLOR_RESET "\n");
 153         for (unsigned j = 0; j < 4; j++)
 154                 ac_dump_reg(f, chip_class, R_008F00_SQ_BUF_RSRC_WORD0 + j * 4,
 155                             desc[j], 0xffffffff);
 156 }
 157
 158 static void
 159 radv_dump_image_descriptor(enum chip_class chip_class, const uint32_t *desc,
 160                            FILE *f)
 161 {
 162         unsigned sq_img_rsrc_word0 = chip_class >= GFX10 ? R_00A000_SQ_IMG_RSRC_WORD0
 163                                                          : R_008F10_SQ_IMG_RSRC_WORD0;
 164
 165         fprintf(f, COLOR_CYAN "    Image:" COLOR_RESET "\n");
 166         for (unsigned j = 0; j < 8; j++)
 167                 ac_dump_reg(f, chip_class, sq_img_rsrc_word0 + j * 4,
 168                             desc[j], 0xffffffff);
 169
 170         fprintf(f, COLOR_CYAN "    FMASK:" COLOR_RESET "\n");
 171         for (unsigned j = 0; j < 8; j++)
 172                 ac_dump_reg(f, chip_class, sq_img_rsrc_word0 + j * 4,
 173                             desc[8 + j], 0xffffffff);
 174 }
 175
 176 static void
 177 radv_dump_sampler_descriptor(enum chip_class chip_class, const uint32_t *desc,
 178                              FILE *f)
 179 {
 180         fprintf(f, COLOR_CYAN "    Sampler state:" COLOR_RESET "\n");
 181         for (unsigned j = 0; j < 4; j++) {
 182                 ac_dump_reg(f, chip_class, R_008F30_SQ_IMG_SAMP_WORD0 + j * 4,
 183                             desc[j], 0xffffffff);
 184         }
 185 }
 186
 187 static void
 188 radv_dump_combined_image_sampler_descriptor(enum chip_class chip_class,
 189                                             const uint32_t *desc, FILE *f)
 190 {
 191         radv_dump_image_descriptor(chip_class, desc, f);
 192         radv_dump_sampler_descriptor(chip_class, desc + 16, f);
 193 }
 194
 195 static void
 196 radv_dump_descriptor_set(struct radv_device *device,
 197                          struct radv_descriptor_set *set, unsigned id, FILE *f)
 198 {
 199         enum chip_class chip_class = device->physical_device->rad_info.chip_class;
 200         const struct radv_descriptor_set_layout *layout;
 201         int i;
 202
 203         if (!set)
 204                 return;
 205         layout = set->layout;
 206
 207         for (i = 0; i < set->layout->binding_count; i++) {
 208                 uint32_t *desc =
 209                         set->mapped_ptr + layout->binding[i].offset / 4;
 210
 211                 switch (layout->binding[i].type) {
 212                 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
 213                 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
 214                 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
 215                 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
 216                         radv_dump_buffer_descriptor(chip_class, desc, f);
 217                         break;
 218                 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
 219                 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
 220                 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
 221                         radv_dump_image_descriptor(chip_class, desc, f);
 222                         break;
 223                 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
 224                         radv_dump_combined_image_sampler_descriptor(chip_class, desc, f);
 225                         break;
 226                 case VK_DESCRIPTOR_TYPE_SAMPLER:
 227                         radv_dump_sampler_descriptor(chip_class, desc, f);
 228                         break;
 229                 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
 230                 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
 231                         /* todo */
 232                         break;
 233                 default:
 234                         assert(!"unknown descriptor type");
 235                         break;
 236                 }
 237                 fprintf(f, "\n");
 238         }
 239         fprintf(f, "\n\n");
 240 }
 241
 242 static void
 243 radv_dump_descriptors(struct radv_device *device, FILE *f)
 244 {
 245         uint64_t *ptr = (uint64_t *)device->trace_id_ptr;
 246         int i;
 247
 248         fprintf(f, "Descriptors:\n");
 249         for (i = 0; i < MAX_SETS; i++) {
 250                 struct radv_descriptor_set *set =
 251                         *(struct radv_descriptor_set **)(ptr + i + 3);
 252
 253                 radv_dump_descriptor_set(device, set, i, f);
 254         }
 255 }
 256
 257 struct radv_shader_inst {
 258         char text[160];  /* one disasm line */
 259         unsigned offset; /* instruction offset */
 260         unsigned size;   /* instruction size = 4 or 8 */
 261 };
 262
 263 /* Split a disassembly string into lines and add them to the array pointed
 264  * to by "instructions". */
 265 static void si_add_split_disasm(const char *disasm,
 266                                 uint64_t start_addr,
 267                                 unsigned *num,
 268                                 struct radv_shader_inst *instructions)
 269 {
 270         struct radv_shader_inst *last_inst = *num ? &instructions[*num - 1] : NULL;
 271         char *next;
 272
 273         while ((next = strchr(disasm, '\n'))) {
 274                 struct radv_shader_inst *inst = &instructions[*num];
 275                 unsigned len = next - disasm;
 276
 277                 assert(len < ARRAY_SIZE(inst->text));
 278                 memcpy(inst->text, disasm, len);
 279                 inst->text[len] = 0;
 280                 inst->offset = last_inst ? last_inst->offset + last_inst->size : 0;
 281
 282                 const char *semicolon = strchr(disasm, ';');
 283                 assert(semicolon);
 284                 /* More than 16 chars after ";" means the instruction is 8 bytes long. */
 285                 inst->size = next - semicolon > 16 ? 8 : 4;
 286
 287                 snprintf(inst->text + len, ARRAY_SIZE(inst->text) - len,
 288                         " [PC=0x%"PRIx64", off=%u, size=%u]",
 289                         start_addr + inst->offset, inst->offset, inst->size);
 290
 291                 last_inst = inst;
 292                 (*num)++;
 293                 disasm = next + 1;
 294         }
 295 }
 296
 297 static void
 298 radv_dump_annotated_shader(struct radv_shader_variant *shader,
 299                            gl_shader_stage stage, struct ac_wave_info *waves,
 300                            unsigned num_waves, FILE *f)
 301 {
 302         uint64_t start_addr, end_addr;
 303         unsigned i;
 304
 305         if (!shader)
 306                 return;
 307
 308         start_addr = radv_buffer_get_va(shader->bo) + shader->bo_offset;
 309         end_addr = start_addr + shader->code_size;
 310
 311         /* See if any wave executes the shader. */
 312         for (i = 0; i < num_waves; i++) {
 313                 if (start_addr <= waves[i].pc && waves[i].pc <= end_addr)
 314                         break;
 315         }
 316
 317         if (i == num_waves)
 318                 return; /* the shader is not being executed */
 319
 320         /* Remember the first found wave. The waves are sorted according to PC. */
 321         waves = &waves[i];
 322         num_waves -= i;
 323
 324         /* Get the list of instructions.
 325          * Buffer size / 4 is the upper bound of the instruction count.
 326          */
 327         unsigned num_inst = 0;
 328         struct radv_shader_inst *instructions =
 329                 calloc(shader->code_size / 4, sizeof(struct radv_shader_inst));
 330
 331         si_add_split_disasm(shader->disasm_string,
 332                             start_addr, &num_inst, instructions);
 333
 334         fprintf(f, COLOR_YELLOW "%s - annotated disassembly:" COLOR_RESET "\n",
 335                 radv_get_shader_name(&shader->info, stage));
 336
 337         /* Print instructions with annotations. */
 338         for (i = 0; i < num_inst; i++) {
 339                 struct radv_shader_inst *inst = &instructions[i];
 340
 341                 fprintf(f, "%s\n", inst->text);
 342
 343                 /* Print which waves execute the instruction right now. */
 344                 while (num_waves && start_addr + inst->offset == waves->pc) {
 345                         fprintf(f,
 346                                 "          " COLOR_GREEN "^ SE%u SH%u CU%u "
 347                                 "SIMD%u WAVE%u  EXEC=%016"PRIx64 "  ",
 348                                 waves->se, waves->sh, waves->cu, waves->simd,
 349                                 waves->wave, waves->exec);
 350
 351                         if (inst->size == 4) {
 352                                 fprintf(f, "INST32=%08X" COLOR_RESET "\n",
 353                                         waves->inst_dw0);
 354                         } else {
 355                                 fprintf(f, "INST64=%08X %08X" COLOR_RESET "\n",
 356                                         waves->inst_dw0, waves->inst_dw1);
 357                         }
 358
 359                         waves->matched = true;
 360                         waves = &waves[1];
 361                         num_waves--;
 362                 }
 363         }
 364
 365         fprintf(f, "\n\n");
 366         free(instructions);
 367 }
 368
 369 static void
 370 radv_dump_annotated_shaders(struct radv_pipeline *pipeline,
 371                             VkShaderStageFlagBits active_stages, FILE *f)
 372 {
 373         struct ac_wave_info waves[AC_MAX_WAVES_PER_CHIP];
 374         enum chip_class chip_class = pipeline->device->physical_device->rad_info.chip_class;
 375         unsigned num_waves = ac_get_wave_info(chip_class, waves);
 376
 377         fprintf(f, COLOR_CYAN "The number of active waves = %u" COLOR_RESET
 378                 "\n\n", num_waves);
 379
 380         /* Dump annotated active graphics shaders. */
 381         while (active_stages) {
 382                 int stage = u_bit_scan(&active_stages);
 383
 384                 radv_dump_annotated_shader(pipeline->shaders[stage],
 385                                            stage, waves, num_waves, f);
 386         }
 387
 388         /* Print waves executing shaders that are not currently bound. */
 389         unsigned i;
 390         bool found = false;
 391         for (i = 0; i < num_waves; i++) {
 392                 if (waves[i].matched)
 393                         continue;
 394
 395                 if (!found) {
 396                         fprintf(f, COLOR_CYAN
 397                                 "Waves not executing currently-bound shaders:"
 398                                 COLOR_RESET "\n");
 399                         found = true;
 400                 }
 401                 fprintf(f, "    SE%u SH%u CU%u SIMD%u WAVE%u  EXEC=%016"PRIx64
 402                         "  INST=%08X %08X  PC=%"PRIx64"\n",
 403                         waves[i].se, waves[i].sh, waves[i].cu, waves[i].simd,
 404                         waves[i].wave, waves[i].exec, waves[i].inst_dw0,
 405                         waves[i].inst_dw1, waves[i].pc);
 406         }
 407         if (found)
 408                 fprintf(f, "\n\n");
 409 }
 410
 411 static void
 412 radv_dump_shader(struct radv_pipeline *pipeline,
 413                  struct radv_shader_variant *shader, gl_shader_stage stage,
 414                  FILE *f)
 415 {
 416         if (!shader)
 417                 return;
 418
 419         fprintf(f, "%s:\n\n", radv_get_shader_name(&shader->info, stage));
 420
 421         if (shader->spirv) {
 422                 unsigned char sha1[21];
 423                 char sha1buf[41];
 424
 425                 _mesa_sha1_compute(shader->spirv, shader->spirv_size, sha1);
 426                 _mesa_sha1_format(sha1buf, sha1);
 427
 428                 fprintf(f, "SPIRV (sha1: %s):\n", sha1buf);
 429                 radv_print_spirv(shader->spirv, shader->spirv_size, f);
 430         }
 431
 432         if (shader->nir_string) {
 433                 fprintf(f, "NIR:\n%s\n", shader->nir_string);
 434         }
 435
 436         fprintf(f, "LLVM IR:\n%s\n", shader->ir_string);
 437         fprintf(f, "DISASM:\n%s\n", shader->disasm_string);
 438
 439         radv_shader_dump_stats(pipeline->device, shader, stage, f);
 440 }
 441
 442 static void
 443 radv_dump_shaders(struct radv_pipeline *pipeline,
 444                   VkShaderStageFlagBits active_stages, FILE *f)
 445 {
 446         /* Dump active graphics shaders. */
 447         while (active_stages) {
 448                 int stage = u_bit_scan(&active_stages);
 449
 450                 radv_dump_shader(pipeline, pipeline->shaders[stage], stage, f);
 451         }
 452 }
 453
 454 static void
 455 radv_dump_pipeline_state(struct radv_pipeline *pipeline,
 456                          VkShaderStageFlagBits active_stages, FILE *f)
 457 {
 458         radv_dump_shaders(pipeline, active_stages, f);
 459         radv_dump_annotated_shaders(pipeline, active_stages, f);
 460 }
 461
 462 static void
 463 radv_dump_graphics_state(struct radv_device *device,
 464                          struct radv_pipeline *graphics_pipeline,
 465                          struct radv_pipeline *compute_pipeline, FILE *f)
 466 {
 467         VkShaderStageFlagBits active_stages;
 468
 469         if (graphics_pipeline) {
 470                 active_stages = graphics_pipeline->active_stages;
 471                 radv_dump_pipeline_state(graphics_pipeline, active_stages, f);
 472         }
 473
 474         if (compute_pipeline) {
 475                 active_stages = VK_SHADER_STAGE_COMPUTE_BIT;
 476                 radv_dump_pipeline_state(compute_pipeline, active_stages, f);
 477         }
 478
 479         radv_dump_descriptors(device, f);
 480 }
 481
 482 static void
 483 radv_dump_compute_state(struct radv_device *device,
 484                         struct radv_pipeline *compute_pipeline, FILE *f)
 485 {
 486         VkShaderStageFlagBits active_stages = VK_SHADER_STAGE_COMPUTE_BIT;
 487
 488         if (!compute_pipeline)
 489                 return;
 490
 491         radv_dump_pipeline_state(compute_pipeline, active_stages, f);
 492         radv_dump_descriptors(device, f);
 493 }
 494
 495 static struct radv_pipeline *
 496 radv_get_saved_graphics_pipeline(struct radv_device *device)
 497 {
 498         uint64_t *ptr = (uint64_t *)device->trace_id_ptr;
 499
 500         return *(struct radv_pipeline **)(ptr + 1);
 501 }
 502
 503 static struct radv_pipeline *
 504 radv_get_saved_compute_pipeline(struct radv_device *device)
 505 {
 506         uint64_t *ptr = (uint64_t *)device->trace_id_ptr;
 507
 508         return *(struct radv_pipeline **)(ptr + 2);
 509 }
 510
 511 static void
 512 radv_dump_dmesg(FILE *f)
 513 {
 514         char line[2000];
 515         FILE *p;
 516
 517         p = popen("dmesg | tail -n60", "r");
 518         if (!p)
 519                 return;
 520
 521         fprintf(f, "\nLast 60 lines of dmesg:\n\n");
 522         while (fgets(line, sizeof(line), p))
 523                 fputs(line, f);
 524         fprintf(f, "\n");
 525
 526         pclose(p);
 527 }
 528
 529 void
 530 radv_dump_enabled_options(struct radv_device *device, FILE *f)
 531 {
 532         uint64_t mask;
 533
 534         if (device->instance->debug_flags) {
 535                 fprintf(f, "Enabled debug options: ");
 536
 537                 mask = device->instance->debug_flags;
 538                 while (mask) {
 539                         int i = u_bit_scan64(&mask);
 540                         fprintf(f, "%s, ", radv_get_debug_option_name(i));
 541                 }
 542                 fprintf(f, "\n");
 543         }
 544
 545         if (device->instance->perftest_flags) {
 546                 fprintf(f, "Enabled perftest options: ");
 547
 548                 mask = device->instance->perftest_flags;
 549                 while (mask) {
 550                         int i = u_bit_scan64(&mask);
 551                         fprintf(f, "%s, ", radv_get_perftest_option_name(i));
 552                 }
 553                 fprintf(f, "\n");
 554         }
 555 }
 556
 557 static void
 558 radv_dump_device_name(struct radv_device *device, FILE *f)
 559 {
 560         struct radeon_info *info = &device->physical_device->rad_info;
 561         char kernel_version[128] = {};
 562         struct utsname uname_data;
 563         const char *chip_name;
 564
 565         chip_name = device->ws->get_chip_name(device->ws);
 566
 567         if (uname(&uname_data) == 0)
 568                 snprintf(kernel_version, sizeof(kernel_version),
 569                          " / %s", uname_data.release);
 570
 571         fprintf(f, "Device name: %s (%s DRM %i.%i.%i%s, LLVM "
 572                 MESA_LLVM_VERSION_STRING ")\n\n",
 573                 chip_name, device->physical_device->name,
 574                 info->drm_major, info->drm_minor, info->drm_patchlevel,
 575                 kernel_version);
 576 }
 577
 578 static bool
 579 radv_gpu_hang_occured(struct radv_queue *queue, enum ring_type ring)
 580 {
 581         struct radeon_winsys *ws = queue->device->ws;
 582
 583         if (!ws->ctx_wait_idle(queue->hw_ctx, ring, queue->queue_idx))
 584                 return true;
 585
 586         return false;
 587 }
 588
 589 void
 590 radv_check_gpu_hangs(struct radv_queue *queue, struct radeon_cmdbuf *cs)
 591 {
 592         struct radv_pipeline *graphics_pipeline, *compute_pipeline;
 593         struct radv_device *device = queue->device;
 594         enum ring_type ring;
 595         uint64_t addr;
 596
 597         ring = radv_queue_family_to_ring(queue->queue_family_index);
 598
 599         bool hang_occurred = radv_gpu_hang_occured(queue, ring);
 600         bool vm_fault_occurred = false;
 601         if (queue->device->instance->debug_flags & RADV_DEBUG_VM_FAULTS)
 602                 vm_fault_occurred = ac_vm_fault_occured(device->physical_device->rad_info.chip_class,
 603                                                         &device->dmesg_timestamp, &addr);
 604         if (!hang_occurred && !vm_fault_occurred)
 605                 return;
 606
 607         graphics_pipeline = radv_get_saved_graphics_pipeline(device);
 608         compute_pipeline = radv_get_saved_compute_pipeline(device);
 609
 610         radv_dump_trace(queue->device, cs);
 611
 612         fprintf(stderr, "GPU hang report:\n\n");
 613         radv_dump_device_name(device, stderr);
 614
 615         radv_dump_enabled_options(device, stderr);
 616         radv_dump_dmesg(stderr);
 617
 618         if (vm_fault_occurred) {
 619                 fprintf(stderr, "VM fault report.\n\n");
 620                 fprintf(stderr, "Failing VM page: 0x%08"PRIx64"\n\n", addr);
 621         }
 622
 623         radv_dump_debug_registers(device, stderr);
 624
 625         switch (ring) {
 626         case RING_GFX:
 627                 fprintf(stderr, "RING_GFX:\n");
 628                 radv_dump_graphics_state(queue->device,
 629                                          graphics_pipeline, compute_pipeline,
 630                                          stderr);
 631                 break;
 632         case RING_COMPUTE:
 633                 fprintf(stderr, "RING_COMPUTE:\n");
 634                 radv_dump_compute_state(queue->device,
 635                                         compute_pipeline, stderr);
 636                 break;
 637         default:
 638                 assert(0);
 639                 break;
 640         }
 641
 642         abort();
 643 }
 644
 645 void
 646 radv_print_spirv(const char *data, uint32_t size, FILE *fp)
 647 {
 648         char path[] = "/tmp/fileXXXXXX";
 649         char line[2048], command[128];
 650         FILE *p;
 651         int fd;
 652
 653         /* Dump the binary into a temporary file. */
 654         fd = mkstemp(path);
 655         if (fd < 0)
 656                 return;
 657
 658         if (write(fd, data, size) == -1)
 659                 goto fail;
 660
 661         sprintf(command, "spirv-dis %s", path);
 662
 663         /* Disassemble using spirv-dis if installed. */
 664         p = popen(command, "r");
 665         if (p) {
 666                 while (fgets(line, sizeof(line), p))
 667                         fprintf(fp, "%s", line);
 668                 pclose(p);
 669         }
 670
 671 fail:
 672         close(fd);
 673         unlink(path);
 674 }