src/amd/vulkan/radv_debug.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #include <stdlib.h>
  29 #include <stdio.h>
  30
  31 #include "sid.h"
  32 #include "gfx9d.h"
  33 #include "ac_debug.h"
  34 #include "radv_debug.h"
  35 #include "radv_shader.h"
  36
  37 #define TRACE_BO_SIZE 4096
  38
  39 #define COLOR_RESET     "\033[0m"
  40 #define COLOR_RED       "\033[31m"
  41 #define COLOR_GREEN     "\033[1;32m"
  42 #define COLOR_YELLOW    "\033[1;33m"
  43 #define COLOR_CYAN      "\033[1;36m"
  44
  45 /* Trace BO layout (offsets are 4 bytes):
  46  *
  47  * [0]: primary trace ID
  48  * [1]: secondary trace ID
  49  * [2-3]: 64-bit GFX pipeline pointer
  50  * [4-5]: 64-bit COMPUTE pipeline pointer
  51  * [6-7]: 64-bit descriptor set #0 pointer
  52  * ...
  53  * [68-69]: 64-bit descriptor set #31 pointer
  54  */
  55
  56 bool
  57 radv_init_trace(struct radv_device *device)
  58 {
  59         struct radeon_winsys *ws = device->ws;
  60
  61         device->trace_bo = ws->buffer_create(ws, TRACE_BO_SIZE, 8,
  62                                              RADEON_DOMAIN_VRAM,
  63                                              RADEON_FLAG_CPU_ACCESS);
  64         if (!device->trace_bo)
  65                 return false;
  66
  67         device->trace_id_ptr = ws->buffer_map(device->trace_bo);
  68         if (!device->trace_id_ptr)
  69                 return false;
  70
  71         memset(device->trace_id_ptr, 0, TRACE_BO_SIZE);
  72
  73         ac_vm_fault_occured(device->physical_device->rad_info.chip_class,
  74                             &device->dmesg_timestamp, NULL);
  75
  76         return true;
  77 }
  78
  79 static void
  80 radv_dump_trace(struct radv_device *device, struct radeon_winsys_cs *cs)
  81 {
  82         const char *filename = getenv("RADV_TRACE_FILE");
  83         FILE *f = fopen(filename, "w");
  84
  85         if (!f) {
  86                 fprintf(stderr, "Failed to write trace dump to %s\n", filename);
  87                 return;
  88         }
  89
  90         fprintf(f, "Trace ID: %x\n", *device->trace_id_ptr);
  91         device->ws->cs_dump(cs, f, (const int*)device->trace_id_ptr, 2);
  92         fclose(f);
  93 }
  94
  95 static void
  96 radv_dump_mmapped_reg(struct radv_device *device, FILE *f, unsigned offset)
  97 {
  98         struct radeon_winsys *ws = device->ws;
  99         uint32_t value;
 100
 101         if (ws->read_registers(ws, offset, 1, &value))
 102                 ac_dump_reg(f, device->physical_device->rad_info.chip_class,
 103                             offset, value, ~0);
 104 }
 105
 106 static void
 107 radv_dump_debug_registers(struct radv_device *device, FILE *f)
 108 {
 109         struct radeon_info *info = &device->physical_device->rad_info;
 110
 111         if (info->drm_major == 2 && info->drm_minor < 42)
 112                 return; /* no radeon support */
 113
 114         fprintf(f, "Memory-mapped registers:\n");
 115         radv_dump_mmapped_reg(device, f, R_008010_GRBM_STATUS);
 116
 117         /* No other registers can be read on DRM < 3.1.0. */
 118         if (info->drm_major < 3 || info->drm_minor < 1) {
 119                 fprintf(f, "\n");
 120                 return;
 121         }
 122
 123         radv_dump_mmapped_reg(device, f, R_008008_GRBM_STATUS2);
 124         radv_dump_mmapped_reg(device, f, R_008014_GRBM_STATUS_SE0);
 125         radv_dump_mmapped_reg(device, f, R_008018_GRBM_STATUS_SE1);
 126         radv_dump_mmapped_reg(device, f, R_008038_GRBM_STATUS_SE2);
 127         radv_dump_mmapped_reg(device, f, R_00803C_GRBM_STATUS_SE3);
 128         radv_dump_mmapped_reg(device, f, R_00D034_SDMA0_STATUS_REG);
 129         radv_dump_mmapped_reg(device, f, R_00D834_SDMA1_STATUS_REG);
 130         if (info->chip_class <= VI) {
 131                 radv_dump_mmapped_reg(device, f, R_000E50_SRBM_STATUS);
 132                 radv_dump_mmapped_reg(device, f, R_000E4C_SRBM_STATUS2);
 133                 radv_dump_mmapped_reg(device, f, R_000E54_SRBM_STATUS3);
 134         }
 135         radv_dump_mmapped_reg(device, f, R_008680_CP_STAT);
 136         radv_dump_mmapped_reg(device, f, R_008674_CP_STALLED_STAT1);
 137         radv_dump_mmapped_reg(device, f, R_008678_CP_STALLED_STAT2);
 138         radv_dump_mmapped_reg(device, f, R_008670_CP_STALLED_STAT3);
 139         radv_dump_mmapped_reg(device, f, R_008210_CP_CPC_STATUS);
 140         radv_dump_mmapped_reg(device, f, R_008214_CP_CPC_BUSY_STAT);
 141         radv_dump_mmapped_reg(device, f, R_008218_CP_CPC_STALLED_STAT1);
 142         radv_dump_mmapped_reg(device, f, R_00821C_CP_CPF_STATUS);
 143         radv_dump_mmapped_reg(device, f, R_008220_CP_CPF_BUSY_STAT);
 144         radv_dump_mmapped_reg(device, f, R_008224_CP_CPF_STALLED_STAT1);
 145         fprintf(f, "\n");
 146 }
 147
 148 static const char *
 149 radv_get_descriptor_name(enum VkDescriptorType type)
 150 {
 151         switch (type) {
 152         case VK_DESCRIPTOR_TYPE_SAMPLER:
 153                 return "SAMPLER";
 154         case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
 155                 return "COMBINED_IMAGE_SAMPLER";
 156         case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
 157                 return "SAMPLED_IMAGE";
 158         case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
 159                 return "STORAGE_IMAGE";
 160         case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
 161                 return "UNIFORM_TEXEL_BUFFER";
 162         case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
 163                 return "STORAGE_TEXEL_BUFFER";
 164         case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
 165                 return "UNIFORM_BUFFER";
 166         case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
 167                 return "STORAGE_BUFFER";
 168         case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
 169                 return "UNIFORM_BUFFER_DYNAMIC";
 170         case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
 171                 return "STORAGE_BUFFER_DYNAMIC";
 172         case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
 173                 return "INPUT_ATTACHMENT";
 174         default:
 175                 return "UNKNOWN";
 176         }
 177 }
 178
 179 static void
 180 radv_dump_buffer_descriptor(enum chip_class chip_class, const uint32_t *desc,
 181                             FILE *f)
 182 {
 183         fprintf(f, COLOR_CYAN "    Buffer:" COLOR_RESET "\n");
 184         for (unsigned j = 0; j < 4; j++)
 185                 ac_dump_reg(f, chip_class, R_008F00_SQ_BUF_RSRC_WORD0 + j * 4,
 186                             desc[j], 0xffffffff);
 187 }
 188
 189 static void
 190 radv_dump_image_descriptor(enum chip_class chip_class, const uint32_t *desc,
 191                            FILE *f)
 192 {
 193         fprintf(f, COLOR_CYAN "    Image:" COLOR_RESET "\n");
 194         for (unsigned j = 0; j < 8; j++)
 195                 ac_dump_reg(f, chip_class, R_008F10_SQ_IMG_RSRC_WORD0 + j * 4,
 196                             desc[j], 0xffffffff);
 197
 198         fprintf(f, COLOR_CYAN "    FMASK:" COLOR_RESET "\n");
 199         for (unsigned j = 0; j < 8; j++)
 200                 ac_dump_reg(f, chip_class, R_008F10_SQ_IMG_RSRC_WORD0 + j * 4,
 201                             desc[8 + j], 0xffffffff);
 202 }
 203
 204 static void
 205 radv_dump_sampler_descriptor(enum chip_class chip_class, const uint32_t *desc,
 206                              FILE *f)
 207 {
 208         fprintf(f, COLOR_CYAN "    Sampler state:" COLOR_RESET "\n");
 209         for (unsigned j = 0; j < 4; j++) {
 210                 ac_dump_reg(f, chip_class, R_008F30_SQ_IMG_SAMP_WORD0 + j * 4,
 211                             desc[j], 0xffffffff);
 212         }
 213 }
 214
 215 static void
 216 radv_dump_combined_image_sampler_descriptor(enum chip_class chip_class,
 217                                             const uint32_t *desc, FILE *f)
 218 {
 219         radv_dump_image_descriptor(chip_class, desc, f);
 220         radv_dump_sampler_descriptor(chip_class, desc + 16, f);
 221 }
 222
 223 static void
 224 radv_dump_descriptor_set(enum chip_class chip_class,
 225                          struct radv_descriptor_set *set, unsigned id, FILE *f)
 226 {
 227         const struct radv_descriptor_set_layout *layout;
 228         int i;
 229
 230         if (!set)
 231                 return;
 232         layout = set->layout;
 233
 234         fprintf(f, "** descriptor set (%d) **\n", id);
 235         fprintf(f, "va: 0x%"PRIx64"\n", set->va);
 236         fprintf(f, "size: %d\n", set->size);
 237         fprintf(f, "mapped_ptr:\n");
 238
 239         for (i = 0; i < set->size / 4; i++) {
 240                 fprintf(f, "\t[0x%x] = 0x%08x\n", i, set->mapped_ptr[i]);
 241         }
 242         fprintf(f, "\n");
 243
 244         fprintf(f, "\t*** layout ***\n");
 245         fprintf(f, "\tbinding_count: %d\n", layout->binding_count);
 246         fprintf(f, "\tsize: %d\n", layout->size);
 247         fprintf(f, "\tshader_stages: %x\n", layout->shader_stages);
 248         fprintf(f, "\tdynamic_shader_stages: %x\n",
 249                 layout->dynamic_shader_stages);
 250         fprintf(f, "\tbuffer_count: %d\n", layout->buffer_count);
 251         fprintf(f, "\tdynamic_offset_count: %d\n",
 252                 layout->dynamic_offset_count);
 253         fprintf(f, "\n");
 254
 255         for (i = 0; i < set->layout->binding_count; i++) {
 256                 uint32_t *desc =
 257                         set->mapped_ptr + layout->binding[i].offset / 4;
 258
 259                 fprintf(f, "\t\t**** binding layout (%d) ****\n", i);
 260                 fprintf(f, "\t\ttype: %s\n",
 261                         radv_get_descriptor_name(layout->binding[i].type));
 262                 fprintf(f, "\t\tarray_size: %d\n",
 263                         layout->binding[i].array_size);
 264                 fprintf(f, "\t\toffset: %d\n",
 265                         layout->binding[i].offset);
 266                 fprintf(f, "\t\tbuffer_offset: %d\n",
 267                         layout->binding[i].buffer_offset);
 268                 fprintf(f, "\t\tdynamic_offset_offset: %d\n",
 269                         layout->binding[i].dynamic_offset_offset);
 270                 fprintf(f, "\t\tdynamic_offset_count: %d\n",
 271                         layout->binding[i].dynamic_offset_count);
 272                 fprintf(f, "\t\tsize: %d\n",
 273                         layout->binding[i].size);
 274                 fprintf(f, "\t\timmutable_samplers_offset: %d\n",
 275                         layout->binding[i].immutable_samplers_offset);
 276                 fprintf(f, "\t\timmutable_samplers_equal: %d\n",
 277                         layout->binding[i].immutable_samplers_equal);
 278                 fprintf(f, "\n");
 279
 280                 switch (layout->binding[i].type) {
 281                 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
 282                 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
 283                 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
 284                 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
 285                         radv_dump_buffer_descriptor(chip_class, desc, f);
 286                         break;
 287                 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
 288                 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
 289                 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
 290                         radv_dump_image_descriptor(chip_class, desc, f);
 291                         break;
 292                 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
 293                         radv_dump_combined_image_sampler_descriptor(chip_class, desc, f);
 294                         break;
 295                 case VK_DESCRIPTOR_TYPE_SAMPLER:
 296                         radv_dump_sampler_descriptor(chip_class, desc, f);
 297                         break;
 298                 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
 299                 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
 300                         /* todo */
 301                         break;
 302                 default:
 303                         assert(!"unknown descriptor type");
 304                         break;
 305                 }
 306                 fprintf(f, "\n");
 307         }
 308         fprintf(f, "\n\n");
 309 }
 310
 311 static void
 312 radv_dump_descriptors(struct radv_pipeline *pipeline, FILE *f)
 313 {
 314         struct radv_device *device = pipeline->device;
 315         enum chip_class chip_class = device->physical_device->rad_info.chip_class;
 316         uint64_t *ptr = (uint64_t *)device->trace_id_ptr;
 317         int i;
 318
 319         fprintf(f, "List of descriptors:\n");
 320         for (i = 0; i < MAX_SETS; i++) {
 321                 struct radv_descriptor_set *set =
 322                         (struct radv_descriptor_set *)ptr[i + 3];
 323
 324                 radv_dump_descriptor_set(chip_class, set, i, f);
 325         }
 326 }
 327
 328 struct radv_shader_inst {
 329         char text[160];  /* one disasm line */
 330         unsigned offset; /* instruction offset */
 331         unsigned size;   /* instruction size = 4 or 8 */
 332 };
 333
 334 /* Split a disassembly string into lines and add them to the array pointed
 335  * to by "instructions". */
 336 static void si_add_split_disasm(const char *disasm,
 337                                 uint64_t start_addr,
 338                                 unsigned *num,
 339                                 struct radv_shader_inst *instructions)
 340 {
 341         struct radv_shader_inst *last_inst = *num ? &instructions[*num - 1] : NULL;
 342         char *next;
 343
 344         while ((next = strchr(disasm, '\n'))) {
 345                 struct radv_shader_inst *inst = &instructions[*num];
 346                 unsigned len = next - disasm;
 347
 348                 assert(len < ARRAY_SIZE(inst->text));
 349                 memcpy(inst->text, disasm, len);
 350                 inst->text[len] = 0;
 351                 inst->offset = last_inst ? last_inst->offset + last_inst->size : 0;
 352
 353                 const char *semicolon = strchr(disasm, ';');
 354                 assert(semicolon);
 355                 /* More than 16 chars after ";" means the instruction is 8 bytes long. */
 356                 inst->size = next - semicolon > 16 ? 8 : 4;
 357
 358                 snprintf(inst->text + len, ARRAY_SIZE(inst->text) - len,
 359                         " [PC=0x%"PRIx64", off=%u, size=%u]",
 360                         start_addr + inst->offset, inst->offset, inst->size);
 361
 362                 last_inst = inst;
 363                 (*num)++;
 364                 disasm = next + 1;
 365         }
 366 }
 367
 368 static void
 369 radv_dump_annotated_shader(struct radv_pipeline *pipeline,
 370                            struct radv_shader_variant *shader,
 371                            gl_shader_stage stage,
 372                            struct ac_wave_info *waves, unsigned num_waves,
 373                            FILE *f)
 374 {
 375         struct radv_device *device = pipeline->device;
 376         uint64_t start_addr, end_addr;
 377         unsigned i;
 378
 379         if (!shader)
 380                 return;
 381
 382         start_addr = device->ws->buffer_get_va(shader->bo) + shader->bo_offset;
 383         end_addr = start_addr + shader->code_size;
 384
 385         /* See if any wave executes the shader. */
 386         for (i = 0; i < num_waves; i++) {
 387                 if (start_addr <= waves[i].pc && waves[i].pc <= end_addr)
 388                         break;
 389         }
 390
 391         if (i == num_waves)
 392                 return; /* the shader is not being executed */
 393
 394         /* Remember the first found wave. The waves are sorted according to PC. */
 395         waves = &waves[i];
 396         num_waves -= i;
 397
 398         /* Get the list of instructions.
 399          * Buffer size / 4 is the upper bound of the instruction count.
 400          */
 401         unsigned num_inst = 0;
 402         struct radv_shader_inst *instructions =
 403                 calloc(shader->code_size / 4, sizeof(struct radv_shader_inst));
 404
 405         si_add_split_disasm(shader->disasm_string,
 406                             start_addr, &num_inst, instructions);
 407
 408         fprintf(f, COLOR_YELLOW "%s - annotated disassembly:" COLOR_RESET "\n",
 409                 radv_get_shader_name(shader, stage));
 410
 411         /* Print instructions with annotations. */
 412         for (i = 0; i < num_inst; i++) {
 413                 struct radv_shader_inst *inst = &instructions[i];
 414
 415                 fprintf(f, "%s\n", inst->text);
 416
 417                 /* Print which waves execute the instruction right now. */
 418                 while (num_waves && start_addr + inst->offset == waves->pc) {
 419                         fprintf(f,
 420                                 "          " COLOR_GREEN "^ SE%u SH%u CU%u "
 421                                 "SIMD%u WAVE%u  EXEC=%016"PRIx64 "  ",
 422                                 waves->se, waves->sh, waves->cu, waves->simd,
 423                                 waves->wave, waves->exec);
 424
 425                         if (inst->size == 4) {
 426                                 fprintf(f, "INST32=%08X" COLOR_RESET "\n",
 427                                         waves->inst_dw0);
 428                         } else {
 429                                 fprintf(f, "INST64=%08X %08X" COLOR_RESET "\n",
 430                                         waves->inst_dw0, waves->inst_dw1);
 431                         }
 432
 433                         waves->matched = true;
 434                         waves = &waves[1];
 435                         num_waves--;
 436                 }
 437         }
 438
 439         fprintf(f, "\n\n");
 440         free(instructions);
 441 }
 442
 443 static void
 444 radv_dump_annotated_shaders(struct radv_pipeline *pipeline,
 445                             struct radv_shader_variant *compute_shader,
 446                             FILE *f)
 447 {
 448         struct ac_wave_info waves[AC_MAX_WAVES_PER_CHIP];
 449         unsigned num_waves = ac_get_wave_info(waves);
 450         unsigned mask;
 451
 452         fprintf(f, COLOR_CYAN "The number of active waves = %u" COLOR_RESET
 453                 "\n\n", num_waves);
 454
 455         /* Dump annotated active graphics shaders. */
 456         mask = pipeline->active_stages;
 457         while (mask) {
 458                 int stage = u_bit_scan(&mask);
 459
 460                 radv_dump_annotated_shader(pipeline, pipeline->shaders[stage],
 461                                            stage, waves, num_waves, f);
 462         }
 463
 464         radv_dump_annotated_shader(pipeline, compute_shader,
 465                                    MESA_SHADER_COMPUTE, waves, num_waves, f);
 466
 467         /* Print waves executing shaders that are not currently bound. */
 468         unsigned i;
 469         bool found = false;
 470         for (i = 0; i < num_waves; i++) {
 471                 if (waves[i].matched)
 472                         continue;
 473
 474                 if (!found) {
 475                         fprintf(f, COLOR_CYAN
 476                                 "Waves not executing currently-bound shaders:"
 477                                 COLOR_RESET "\n");
 478                         found = true;
 479                 }
 480                 fprintf(f, "    SE%u SH%u CU%u SIMD%u WAVE%u  EXEC=%016"PRIx64
 481                         "  INST=%08X %08X  PC=%"PRIx64"\n",
 482                         waves[i].se, waves[i].sh, waves[i].cu, waves[i].simd,
 483                         waves[i].wave, waves[i].exec, waves[i].inst_dw0,
 484                         waves[i].inst_dw1, waves[i].pc);
 485         }
 486         if (found)
 487                 fprintf(f, "\n\n");
 488 }
 489
 490 static void
 491 radv_dump_shader(struct radv_pipeline *pipeline,
 492                  struct radv_shader_variant *shader, gl_shader_stage stage,
 493                  FILE *f)
 494 {
 495         if (!shader)
 496                 return;
 497
 498         fprintf(f, "%s:\n%s\n\n", radv_get_shader_name(shader, stage),
 499                 shader->disasm_string);
 500
 501         radv_shader_dump_stats(pipeline->device, shader, stage, f);
 502 }
 503
 504 static void
 505 radv_dump_shaders(struct radv_pipeline *pipeline,
 506                   struct radv_shader_variant *compute_shader, FILE *f)
 507 {
 508         unsigned mask;
 509
 510         /* Dump active graphics shaders. */
 511         mask = pipeline->active_stages;
 512         while (mask) {
 513                 int stage = u_bit_scan(&mask);
 514
 515                 radv_dump_shader(pipeline, pipeline->shaders[stage], stage, f);
 516         }
 517
 518         radv_dump_shader(pipeline, compute_shader, MESA_SHADER_COMPUTE, f);
 519 }
 520
 521 static void
 522 radv_dump_graphics_state(struct radv_pipeline *graphics_pipeline,
 523                          struct radv_pipeline *compute_pipeline, FILE *f)
 524 {
 525         struct radv_shader_variant *compute_shader =
 526                 compute_pipeline ? compute_pipeline->shaders[MESA_SHADER_COMPUTE] : NULL;
 527
 528         if (!graphics_pipeline)
 529                 return;
 530
 531         radv_dump_shaders(graphics_pipeline, compute_shader, f);
 532         radv_dump_annotated_shaders(graphics_pipeline, compute_shader, f);
 533         radv_dump_descriptors(graphics_pipeline, f);
 534 }
 535
 536 static void
 537 radv_dump_compute_state(struct radv_pipeline *compute_pipeline, FILE *f)
 538 {
 539         if (!compute_pipeline)
 540                 return;
 541
 542         radv_dump_shaders(compute_pipeline,
 543                           compute_pipeline->shaders[MESA_SHADER_COMPUTE], f);
 544         radv_dump_annotated_shaders(compute_pipeline,
 545                                     compute_pipeline->shaders[MESA_SHADER_COMPUTE],
 546                                     f);
 547         radv_dump_descriptors(compute_pipeline, f);
 548 }
 549
 550 static struct radv_pipeline *
 551 radv_get_saved_graphics_pipeline(struct radv_device *device)
 552 {
 553         uint64_t *ptr = (uint64_t *)device->trace_id_ptr;
 554
 555         return (struct radv_pipeline *)ptr[1];
 556 }
 557
 558 static struct radv_pipeline *
 559 radv_get_saved_compute_pipeline(struct radv_device *device)
 560 {
 561         uint64_t *ptr = (uint64_t *)device->trace_id_ptr;
 562
 563         return (struct radv_pipeline *)ptr[2];
 564 }
 565
 566 static void
 567 radv_dump_dmesg(FILE *f)
 568 {
 569         char line[2000];
 570         FILE *p;
 571
 572         p = popen("dmesg | tail -n60", "r");
 573         if (!p)
 574                 return;
 575
 576         fprintf(f, "\nLast 60 lines of dmesg:\n\n");
 577         while (fgets(line, sizeof(line), p))
 578                 fputs(line, f);
 579         fprintf(f, "\n");
 580
 581         pclose(p);
 582 }
 583
 584 static void
 585 radv_dump_enabled_options(struct radv_device *device, FILE *f)
 586 {
 587         uint64_t mask;
 588
 589         fprintf(f, "Enabled debug options: ");
 590
 591         mask = device->debug_flags;
 592         while (mask) {
 593                 int i = u_bit_scan64(&mask);
 594                 fprintf(f, "%s, ", radv_get_debug_option_name(i));
 595         }
 596         fprintf(f, "\n");
 597
 598         fprintf(f, "Enabled perftest options: ");
 599
 600         mask = device->instance->perftest_flags;
 601         while (mask) {
 602                 int i = u_bit_scan64(&mask);
 603                 fprintf(f, "%s, ", radv_get_perftest_option_name(i));
 604         }
 605         fprintf(f, "\n");
 606 }
 607
 608 static bool
 609 radv_gpu_hang_occured(struct radv_queue *queue, enum ring_type ring)
 610 {
 611         struct radeon_winsys *ws = queue->device->ws;
 612
 613         if (!ws->ctx_wait_idle(queue->hw_ctx, ring, queue->queue_idx))
 614                 return true;
 615
 616         return false;
 617 }
 618
 619 void
 620 radv_check_gpu_hangs(struct radv_queue *queue, struct radeon_winsys_cs *cs)
 621 {
 622         struct radv_pipeline *graphics_pipeline, *compute_pipeline;
 623         struct radv_device *device = queue->device;
 624         enum ring_type ring;
 625         uint64_t addr;
 626
 627         ring = radv_queue_family_to_ring(queue->queue_family_index);
 628
 629         bool hang_occurred = radv_gpu_hang_occured(queue, ring);
 630         bool vm_fault_occurred = false;
 631         if (queue->device->instance->debug_flags & RADV_DEBUG_VM_FAULTS)
 632                 vm_fault_occurred = ac_vm_fault_occured(device->physical_device->rad_info.chip_class,
 633                                                         &device->dmesg_timestamp, &addr);
 634         if (!hang_occurred && !vm_fault_occurred)
 635                 return;
 636
 637         graphics_pipeline = radv_get_saved_graphics_pipeline(device);
 638         compute_pipeline = radv_get_saved_compute_pipeline(device);
 639
 640         radv_dump_enabled_options(device, stderr);
 641         radv_dump_dmesg(stderr);
 642
 643         if (vm_fault_occurred) {
 644                 fprintf(stderr, "VM fault report.\n\n");
 645                 fprintf(stderr, "Failing VM page: 0x%08"PRIx64"\n\n", addr);
 646         }
 647
 648         radv_dump_debug_registers(device, stderr);
 649
 650         switch (ring) {
 651         case RING_GFX:
 652                 radv_dump_graphics_state(graphics_pipeline, compute_pipeline,
 653                                          stderr);
 654                 break;
 655         case RING_COMPUTE:
 656                 radv_dump_compute_state(compute_pipeline, stderr);
 657                 break;
 658         default:
 659                 assert(0);
 660                 break;
 661         }
 662
 663         radv_dump_trace(queue->device, cs);
 664         abort();
 665 }
 666
 667 void
 668 radv_print_spirv(struct radv_shader_module *module, FILE *fp)
 669 {
 670         char path[] = "/tmp/fileXXXXXX";
 671         char line[2048], command[128];
 672         FILE *p;
 673         int fd;
 674
 675         /* Dump the binary into a temporary file. */
 676         fd = mkstemp(path);
 677         if (fd < 0)
 678                 return;
 679
 680         if (write(fd, module->data, module->size) == -1)
 681                 goto fail;
 682
 683         sprintf(command, "spirv-dis %s", path);
 684
 685         /* Disassemble using spirv-dis if installed. */
 686         p = popen(command, "r");
 687         if (p) {
 688                 while (fgets(line, sizeof(line), p))
 689                         fprintf(fp, "%s", line);
 690                 pclose(p);
 691         }
 692
 693 fail:
 694         close(fd);
 695         unlink(path);
 696 }