src/amd/vulkan/radv_debug.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #include <stdlib.h>
  29 #include <stdio.h>
  30 #include <sys/utsname.h>
  31
  32 #include "sid.h"
  33 #include "gfx9d.h"
  34 #include "ac_debug.h"
  35 #include "radv_debug.h"
  36 #include "radv_shader.h"
  37
  38 #define TRACE_BO_SIZE 4096
  39
  40 #define COLOR_RESET     "\033[0m"
  41 #define COLOR_RED       "\033[31m"
  42 #define COLOR_GREEN     "\033[1;32m"
  43 #define COLOR_YELLOW    "\033[1;33m"
  44 #define COLOR_CYAN      "\033[1;36m"
  45
  46 /* Trace BO layout (offsets are 4 bytes):
  47  *
  48  * [0]: primary trace ID
  49  * [1]: secondary trace ID
  50  * [2-3]: 64-bit GFX pipeline pointer
  51  * [4-5]: 64-bit COMPUTE pipeline pointer
  52  * [6-7]: 64-bit descriptor set #0 pointer
  53  * ...
  54  * [68-69]: 64-bit descriptor set #31 pointer
  55  */
  56
  57 bool
  58 radv_init_trace(struct radv_device *device)
  59 {
  60         struct radeon_winsys *ws = device->ws;
  61
  62         device->trace_bo = ws->buffer_create(ws, TRACE_BO_SIZE, 8,
  63                                              RADEON_DOMAIN_VRAM,
  64                                              RADEON_FLAG_CPU_ACCESS);
  65         if (!device->trace_bo)
  66                 return false;
  67
  68         device->trace_id_ptr = ws->buffer_map(device->trace_bo);
  69         if (!device->trace_id_ptr)
  70                 return false;
  71
  72         memset(device->trace_id_ptr, 0, TRACE_BO_SIZE);
  73
  74         ac_vm_fault_occured(device->physical_device->rad_info.chip_class,
  75                             &device->dmesg_timestamp, NULL);
  76
  77         return true;
  78 }
  79
  80 static void
  81 radv_dump_trace(struct radv_device *device, struct radeon_winsys_cs *cs)
  82 {
  83         const char *filename = getenv("RADV_TRACE_FILE");
  84         FILE *f = fopen(filename, "w");
  85
  86         if (!f) {
  87                 fprintf(stderr, "Failed to write trace dump to %s\n", filename);
  88                 return;
  89         }
  90
  91         fprintf(f, "Trace ID: %x\n", *device->trace_id_ptr);
  92         device->ws->cs_dump(cs, f, (const int*)device->trace_id_ptr, 2);
  93         fclose(f);
  94 }
  95
  96 static void
  97 radv_dump_mmapped_reg(struct radv_device *device, FILE *f, unsigned offset)
  98 {
  99         struct radeon_winsys *ws = device->ws;
 100         uint32_t value;
 101
 102         if (ws->read_registers(ws, offset, 1, &value))
 103                 ac_dump_reg(f, device->physical_device->rad_info.chip_class,
 104                             offset, value, ~0);
 105 }
 106
 107 static void
 108 radv_dump_debug_registers(struct radv_device *device, FILE *f)
 109 {
 110         struct radeon_info *info = &device->physical_device->rad_info;
 111
 112         if (info->drm_major == 2 && info->drm_minor < 42)
 113                 return; /* no radeon support */
 114
 115         fprintf(f, "Memory-mapped registers:\n");
 116         radv_dump_mmapped_reg(device, f, R_008010_GRBM_STATUS);
 117
 118         /* No other registers can be read on DRM < 3.1.0. */
 119         if (info->drm_major < 3 || info->drm_minor < 1) {
 120                 fprintf(f, "\n");
 121                 return;
 122         }
 123
 124         radv_dump_mmapped_reg(device, f, R_008008_GRBM_STATUS2);
 125         radv_dump_mmapped_reg(device, f, R_008014_GRBM_STATUS_SE0);
 126         radv_dump_mmapped_reg(device, f, R_008018_GRBM_STATUS_SE1);
 127         radv_dump_mmapped_reg(device, f, R_008038_GRBM_STATUS_SE2);
 128         radv_dump_mmapped_reg(device, f, R_00803C_GRBM_STATUS_SE3);
 129         radv_dump_mmapped_reg(device, f, R_00D034_SDMA0_STATUS_REG);
 130         radv_dump_mmapped_reg(device, f, R_00D834_SDMA1_STATUS_REG);
 131         if (info->chip_class <= VI) {
 132                 radv_dump_mmapped_reg(device, f, R_000E50_SRBM_STATUS);
 133                 radv_dump_mmapped_reg(device, f, R_000E4C_SRBM_STATUS2);
 134                 radv_dump_mmapped_reg(device, f, R_000E54_SRBM_STATUS3);
 135         }
 136         radv_dump_mmapped_reg(device, f, R_008680_CP_STAT);
 137         radv_dump_mmapped_reg(device, f, R_008674_CP_STALLED_STAT1);
 138         radv_dump_mmapped_reg(device, f, R_008678_CP_STALLED_STAT2);
 139         radv_dump_mmapped_reg(device, f, R_008670_CP_STALLED_STAT3);
 140         radv_dump_mmapped_reg(device, f, R_008210_CP_CPC_STATUS);
 141         radv_dump_mmapped_reg(device, f, R_008214_CP_CPC_BUSY_STAT);
 142         radv_dump_mmapped_reg(device, f, R_008218_CP_CPC_STALLED_STAT1);
 143         radv_dump_mmapped_reg(device, f, R_00821C_CP_CPF_STATUS);
 144         radv_dump_mmapped_reg(device, f, R_008220_CP_CPF_BUSY_STAT);
 145         radv_dump_mmapped_reg(device, f, R_008224_CP_CPF_STALLED_STAT1);
 146         fprintf(f, "\n");
 147 }
 148
 149 static const char *
 150 radv_get_descriptor_name(enum VkDescriptorType type)
 151 {
 152         switch (type) {
 153         case VK_DESCRIPTOR_TYPE_SAMPLER:
 154                 return "SAMPLER";
 155         case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
 156                 return "COMBINED_IMAGE_SAMPLER";
 157         case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
 158                 return "SAMPLED_IMAGE";
 159         case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
 160                 return "STORAGE_IMAGE";
 161         case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
 162                 return "UNIFORM_TEXEL_BUFFER";
 163         case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
 164                 return "STORAGE_TEXEL_BUFFER";
 165         case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
 166                 return "UNIFORM_BUFFER";
 167         case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
 168                 return "STORAGE_BUFFER";
 169         case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
 170                 return "UNIFORM_BUFFER_DYNAMIC";
 171         case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
 172                 return "STORAGE_BUFFER_DYNAMIC";
 173         case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
 174                 return "INPUT_ATTACHMENT";
 175         default:
 176                 return "UNKNOWN";
 177         }
 178 }
 179
 180 static void
 181 radv_dump_buffer_descriptor(enum chip_class chip_class, const uint32_t *desc,
 182                             FILE *f)
 183 {
 184         fprintf(f, COLOR_CYAN "    Buffer:" COLOR_RESET "\n");
 185         for (unsigned j = 0; j < 4; j++)
 186                 ac_dump_reg(f, chip_class, R_008F00_SQ_BUF_RSRC_WORD0 + j * 4,
 187                             desc[j], 0xffffffff);
 188 }
 189
 190 static void
 191 radv_dump_image_descriptor(enum chip_class chip_class, const uint32_t *desc,
 192                            FILE *f)
 193 {
 194         fprintf(f, COLOR_CYAN "    Image:" COLOR_RESET "\n");
 195         for (unsigned j = 0; j < 8; j++)
 196                 ac_dump_reg(f, chip_class, R_008F10_SQ_IMG_RSRC_WORD0 + j * 4,
 197                             desc[j], 0xffffffff);
 198
 199         fprintf(f, COLOR_CYAN "    FMASK:" COLOR_RESET "\n");
 200         for (unsigned j = 0; j < 8; j++)
 201                 ac_dump_reg(f, chip_class, R_008F10_SQ_IMG_RSRC_WORD0 + j * 4,
 202                             desc[8 + j], 0xffffffff);
 203 }
 204
 205 static void
 206 radv_dump_sampler_descriptor(enum chip_class chip_class, const uint32_t *desc,
 207                              FILE *f)
 208 {
 209         fprintf(f, COLOR_CYAN "    Sampler state:" COLOR_RESET "\n");
 210         for (unsigned j = 0; j < 4; j++) {
 211                 ac_dump_reg(f, chip_class, R_008F30_SQ_IMG_SAMP_WORD0 + j * 4,
 212                             desc[j], 0xffffffff);
 213         }
 214 }
 215
 216 static void
 217 radv_dump_combined_image_sampler_descriptor(enum chip_class chip_class,
 218                                             const uint32_t *desc, FILE *f)
 219 {
 220         radv_dump_image_descriptor(chip_class, desc, f);
 221         radv_dump_sampler_descriptor(chip_class, desc + 16, f);
 222 }
 223
 224 static void
 225 radv_dump_descriptor_set(enum chip_class chip_class,
 226                          struct radv_descriptor_set *set, unsigned id, FILE *f)
 227 {
 228         const struct radv_descriptor_set_layout *layout;
 229         int i;
 230
 231         if (!set)
 232                 return;
 233         layout = set->layout;
 234
 235         fprintf(f, "** descriptor set (%d) **\n", id);
 236         fprintf(f, "va: 0x%"PRIx64"\n", set->va);
 237         fprintf(f, "size: %d\n", set->size);
 238         fprintf(f, "mapped_ptr:\n");
 239
 240         for (i = 0; i < set->size / 4; i++) {
 241                 fprintf(f, "\t[0x%x] = 0x%08x\n", i, set->mapped_ptr[i]);
 242         }
 243         fprintf(f, "\n");
 244
 245         fprintf(f, "\t*** layout ***\n");
 246         fprintf(f, "\tbinding_count: %d\n", layout->binding_count);
 247         fprintf(f, "\tsize: %d\n", layout->size);
 248         fprintf(f, "\tshader_stages: %x\n", layout->shader_stages);
 249         fprintf(f, "\tdynamic_shader_stages: %x\n",
 250                 layout->dynamic_shader_stages);
 251         fprintf(f, "\tbuffer_count: %d\n", layout->buffer_count);
 252         fprintf(f, "\tdynamic_offset_count: %d\n",
 253                 layout->dynamic_offset_count);
 254         fprintf(f, "\n");
 255
 256         for (i = 0; i < set->layout->binding_count; i++) {
 257                 uint32_t *desc =
 258                         set->mapped_ptr + layout->binding[i].offset / 4;
 259
 260                 fprintf(f, "\t\t**** binding layout (%d) ****\n", i);
 261                 fprintf(f, "\t\ttype: %s\n",
 262                         radv_get_descriptor_name(layout->binding[i].type));
 263                 fprintf(f, "\t\tarray_size: %d\n",
 264                         layout->binding[i].array_size);
 265                 fprintf(f, "\t\toffset: %d\n",
 266                         layout->binding[i].offset);
 267                 fprintf(f, "\t\tbuffer_offset: %d\n",
 268                         layout->binding[i].buffer_offset);
 269                 fprintf(f, "\t\tdynamic_offset_offset: %d\n",
 270                         layout->binding[i].dynamic_offset_offset);
 271                 fprintf(f, "\t\tdynamic_offset_count: %d\n",
 272                         layout->binding[i].dynamic_offset_count);
 273                 fprintf(f, "\t\tsize: %d\n",
 274                         layout->binding[i].size);
 275                 fprintf(f, "\t\timmutable_samplers_offset: %d\n",
 276                         layout->binding[i].immutable_samplers_offset);
 277                 fprintf(f, "\t\timmutable_samplers_equal: %d\n",
 278                         layout->binding[i].immutable_samplers_equal);
 279                 fprintf(f, "\n");
 280
 281                 switch (layout->binding[i].type) {
 282                 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
 283                 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
 284                 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
 285                 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
 286                         radv_dump_buffer_descriptor(chip_class, desc, f);
 287                         break;
 288                 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
 289                 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
 290                 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
 291                         radv_dump_image_descriptor(chip_class, desc, f);
 292                         break;
 293                 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
 294                         radv_dump_combined_image_sampler_descriptor(chip_class, desc, f);
 295                         break;
 296                 case VK_DESCRIPTOR_TYPE_SAMPLER:
 297                         radv_dump_sampler_descriptor(chip_class, desc, f);
 298                         break;
 299                 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
 300                 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
 301                         /* todo */
 302                         break;
 303                 default:
 304                         assert(!"unknown descriptor type");
 305                         break;
 306                 }
 307                 fprintf(f, "\n");
 308         }
 309         fprintf(f, "\n\n");
 310 }
 311
 312 static void
 313 radv_dump_descriptors(struct radv_pipeline *pipeline, FILE *f)
 314 {
 315         struct radv_device *device = pipeline->device;
 316         enum chip_class chip_class = device->physical_device->rad_info.chip_class;
 317         uint64_t *ptr = (uint64_t *)device->trace_id_ptr;
 318         int i;
 319
 320         fprintf(f, "List of descriptors:\n");
 321         for (i = 0; i < MAX_SETS; i++) {
 322                 struct radv_descriptor_set *set =
 323                         (struct radv_descriptor_set *)ptr[i + 3];
 324
 325                 radv_dump_descriptor_set(chip_class, set, i, f);
 326         }
 327 }
 328
 329 struct radv_shader_inst {
 330         char text[160];  /* one disasm line */
 331         unsigned offset; /* instruction offset */
 332         unsigned size;   /* instruction size = 4 or 8 */
 333 };
 334
 335 /* Split a disassembly string into lines and add them to the array pointed
 336  * to by "instructions". */
 337 static void si_add_split_disasm(const char *disasm,
 338                                 uint64_t start_addr,
 339                                 unsigned *num,
 340                                 struct radv_shader_inst *instructions)
 341 {
 342         struct radv_shader_inst *last_inst = *num ? &instructions[*num - 1] : NULL;
 343         char *next;
 344
 345         while ((next = strchr(disasm, '\n'))) {
 346                 struct radv_shader_inst *inst = &instructions[*num];
 347                 unsigned len = next - disasm;
 348
 349                 assert(len < ARRAY_SIZE(inst->text));
 350                 memcpy(inst->text, disasm, len);
 351                 inst->text[len] = 0;
 352                 inst->offset = last_inst ? last_inst->offset + last_inst->size : 0;
 353
 354                 const char *semicolon = strchr(disasm, ';');
 355                 assert(semicolon);
 356                 /* More than 16 chars after ";" means the instruction is 8 bytes long. */
 357                 inst->size = next - semicolon > 16 ? 8 : 4;
 358
 359                 snprintf(inst->text + len, ARRAY_SIZE(inst->text) - len,
 360                         " [PC=0x%"PRIx64", off=%u, size=%u]",
 361                         start_addr + inst->offset, inst->offset, inst->size);
 362
 363                 last_inst = inst;
 364                 (*num)++;
 365                 disasm = next + 1;
 366         }
 367 }
 368
 369 static void
 370 radv_dump_annotated_shader(struct radv_pipeline *pipeline,
 371                            struct radv_shader_variant *shader,
 372                            gl_shader_stage stage,
 373                            struct ac_wave_info *waves, unsigned num_waves,
 374                            FILE *f)
 375 {
 376         uint64_t start_addr, end_addr;
 377         unsigned i;
 378
 379         if (!shader)
 380                 return;
 381
 382         start_addr = radv_buffer_get_va(shader->bo) + shader->bo_offset;
 383         end_addr = start_addr + shader->code_size;
 384
 385         /* See if any wave executes the shader. */
 386         for (i = 0; i < num_waves; i++) {
 387                 if (start_addr <= waves[i].pc && waves[i].pc <= end_addr)
 388                         break;
 389         }
 390
 391         if (i == num_waves)
 392                 return; /* the shader is not being executed */
 393
 394         /* Remember the first found wave. The waves are sorted according to PC. */
 395         waves = &waves[i];
 396         num_waves -= i;
 397
 398         /* Get the list of instructions.
 399          * Buffer size / 4 is the upper bound of the instruction count.
 400          */
 401         unsigned num_inst = 0;
 402         struct radv_shader_inst *instructions =
 403                 calloc(shader->code_size / 4, sizeof(struct radv_shader_inst));
 404
 405         si_add_split_disasm(shader->disasm_string,
 406                             start_addr, &num_inst, instructions);
 407
 408         fprintf(f, COLOR_YELLOW "%s - annotated disassembly:" COLOR_RESET "\n",
 409                 radv_get_shader_name(shader, stage));
 410
 411         /* Print instructions with annotations. */
 412         for (i = 0; i < num_inst; i++) {
 413                 struct radv_shader_inst *inst = &instructions[i];
 414
 415                 fprintf(f, "%s\n", inst->text);
 416
 417                 /* Print which waves execute the instruction right now. */
 418                 while (num_waves && start_addr + inst->offset == waves->pc) {
 419                         fprintf(f,
 420                                 "          " COLOR_GREEN "^ SE%u SH%u CU%u "
 421                                 "SIMD%u WAVE%u  EXEC=%016"PRIx64 "  ",
 422                                 waves->se, waves->sh, waves->cu, waves->simd,
 423                                 waves->wave, waves->exec);
 424
 425                         if (inst->size == 4) {
 426                                 fprintf(f, "INST32=%08X" COLOR_RESET "\n",
 427                                         waves->inst_dw0);
 428                         } else {
 429                                 fprintf(f, "INST64=%08X %08X" COLOR_RESET "\n",
 430                                         waves->inst_dw0, waves->inst_dw1);
 431                         }
 432
 433                         waves->matched = true;
 434                         waves = &waves[1];
 435                         num_waves--;
 436                 }
 437         }
 438
 439         fprintf(f, "\n\n");
 440         free(instructions);
 441 }
 442
 443 static void
 444 radv_dump_annotated_shaders(struct radv_pipeline *pipeline,
 445                             struct radv_shader_variant *compute_shader,
 446                             FILE *f)
 447 {
 448         struct ac_wave_info waves[AC_MAX_WAVES_PER_CHIP];
 449         unsigned num_waves = ac_get_wave_info(waves);
 450         unsigned mask;
 451
 452         fprintf(f, COLOR_CYAN "The number of active waves = %u" COLOR_RESET
 453                 "\n\n", num_waves);
 454
 455         /* Dump annotated active graphics shaders. */
 456         mask = pipeline->active_stages;
 457         while (mask) {
 458                 int stage = u_bit_scan(&mask);
 459
 460                 radv_dump_annotated_shader(pipeline, pipeline->shaders[stage],
 461                                            stage, waves, num_waves, f);
 462         }
 463
 464         radv_dump_annotated_shader(pipeline, compute_shader,
 465                                    MESA_SHADER_COMPUTE, waves, num_waves, f);
 466
 467         /* Print waves executing shaders that are not currently bound. */
 468         unsigned i;
 469         bool found = false;
 470         for (i = 0; i < num_waves; i++) {
 471                 if (waves[i].matched)
 472                         continue;
 473
 474                 if (!found) {
 475                         fprintf(f, COLOR_CYAN
 476                                 "Waves not executing currently-bound shaders:"
 477                                 COLOR_RESET "\n");
 478                         found = true;
 479                 }
 480                 fprintf(f, "    SE%u SH%u CU%u SIMD%u WAVE%u  EXEC=%016"PRIx64
 481                         "  INST=%08X %08X  PC=%"PRIx64"\n",
 482                         waves[i].se, waves[i].sh, waves[i].cu, waves[i].simd,
 483                         waves[i].wave, waves[i].exec, waves[i].inst_dw0,
 484                         waves[i].inst_dw1, waves[i].pc);
 485         }
 486         if (found)
 487                 fprintf(f, "\n\n");
 488 }
 489
 490 static void
 491 radv_dump_shader(struct radv_pipeline *pipeline,
 492                  struct radv_shader_variant *shader, gl_shader_stage stage,
 493                  FILE *f)
 494 {
 495         if (!shader)
 496                 return;
 497
 498         fprintf(f, "%s:\n\n", radv_get_shader_name(shader, stage));
 499
 500         if (shader->spirv) {
 501                 fprintf(f, "SPIRV:\n");
 502                 radv_print_spirv(shader->spirv, shader->spirv_size, f);
 503         }
 504
 505         if (shader->nir) {
 506                 fprintf(f, "NIR:\n");
 507                 nir_print_shader(shader->nir, f);
 508         }
 509
 510         fprintf(stderr, "DISASM:\n%s\n", shader->disasm_string);
 511
 512         radv_shader_dump_stats(pipeline->device, shader, stage, f);
 513 }
 514
 515 static void
 516 radv_dump_shaders(struct radv_pipeline *pipeline,
 517                   struct radv_shader_variant *compute_shader, FILE *f)
 518 {
 519         unsigned mask;
 520
 521         /* Dump active graphics shaders. */
 522         mask = pipeline->active_stages;
 523         while (mask) {
 524                 int stage = u_bit_scan(&mask);
 525
 526                 radv_dump_shader(pipeline, pipeline->shaders[stage], stage, f);
 527         }
 528
 529         radv_dump_shader(pipeline, compute_shader, MESA_SHADER_COMPUTE, f);
 530 }
 531
 532 static void
 533 radv_dump_graphics_state(struct radv_pipeline *graphics_pipeline,
 534                          struct radv_pipeline *compute_pipeline, FILE *f)
 535 {
 536         struct radv_shader_variant *compute_shader =
 537                 compute_pipeline ? compute_pipeline->shaders[MESA_SHADER_COMPUTE] : NULL;
 538
 539         if (!graphics_pipeline)
 540                 return;
 541
 542         radv_dump_shaders(graphics_pipeline, compute_shader, f);
 543         radv_dump_annotated_shaders(graphics_pipeline, compute_shader, f);
 544         radv_dump_descriptors(graphics_pipeline, f);
 545 }
 546
 547 static void
 548 radv_dump_compute_state(struct radv_pipeline *compute_pipeline, FILE *f)
 549 {
 550         if (!compute_pipeline)
 551                 return;
 552
 553         radv_dump_shaders(compute_pipeline,
 554                           compute_pipeline->shaders[MESA_SHADER_COMPUTE], f);
 555         radv_dump_annotated_shaders(compute_pipeline,
 556                                     compute_pipeline->shaders[MESA_SHADER_COMPUTE],
 557                                     f);
 558         radv_dump_descriptors(compute_pipeline, f);
 559 }
 560
 561 static struct radv_pipeline *
 562 radv_get_saved_graphics_pipeline(struct radv_device *device)
 563 {
 564         uint64_t *ptr = (uint64_t *)device->trace_id_ptr;
 565
 566         return (struct radv_pipeline *)ptr[1];
 567 }
 568
 569 static struct radv_pipeline *
 570 radv_get_saved_compute_pipeline(struct radv_device *device)
 571 {
 572         uint64_t *ptr = (uint64_t *)device->trace_id_ptr;
 573
 574         return (struct radv_pipeline *)ptr[2];
 575 }
 576
 577 static void
 578 radv_dump_dmesg(FILE *f)
 579 {
 580         char line[2000];
 581         FILE *p;
 582
 583         p = popen("dmesg | tail -n60", "r");
 584         if (!p)
 585                 return;
 586
 587         fprintf(f, "\nLast 60 lines of dmesg:\n\n");
 588         while (fgets(line, sizeof(line), p))
 589                 fputs(line, f);
 590         fprintf(f, "\n");
 591
 592         pclose(p);
 593 }
 594
 595 static void
 596 radv_dump_enabled_options(struct radv_device *device, FILE *f)
 597 {
 598         uint64_t mask;
 599
 600         fprintf(f, "Enabled debug options: ");
 601
 602         mask = device->debug_flags;
 603         while (mask) {
 604                 int i = u_bit_scan64(&mask);
 605                 fprintf(f, "%s, ", radv_get_debug_option_name(i));
 606         }
 607         fprintf(f, "\n");
 608
 609         fprintf(f, "Enabled perftest options: ");
 610
 611         mask = device->instance->perftest_flags;
 612         while (mask) {
 613                 int i = u_bit_scan64(&mask);
 614                 fprintf(f, "%s, ", radv_get_perftest_option_name(i));
 615         }
 616         fprintf(f, "\n");
 617 }
 618
 619 static void
 620 radv_dump_device_name(struct radv_device *device, FILE *f)
 621 {
 622         struct radeon_info *info = &device->physical_device->rad_info;
 623         char llvm_string[32] = {}, kernel_version[128] = {};
 624         struct utsname uname_data;
 625         const char *chip_name;
 626
 627         chip_name = device->ws->get_chip_name(device->ws);
 628
 629         if (uname(&uname_data) == 0)
 630                 snprintf(kernel_version, sizeof(kernel_version),
 631                          " / %s", uname_data.release);
 632
 633         if (HAVE_LLVM > 0) {
 634                 snprintf(llvm_string, sizeof(llvm_string),
 635                          ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
 636                          HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
 637         }
 638
 639         fprintf(f, "Device name: %s (%s DRM %i.%i.%i%s%s)\n\n",
 640                 chip_name, device->physical_device->name,
 641                 info->drm_major, info->drm_minor, info->drm_patchlevel,
 642                 kernel_version, llvm_string);
 643 }
 644
 645 static bool
 646 radv_gpu_hang_occured(struct radv_queue *queue, enum ring_type ring)
 647 {
 648         struct radeon_winsys *ws = queue->device->ws;
 649
 650         if (!ws->ctx_wait_idle(queue->hw_ctx, ring, queue->queue_idx))
 651                 return true;
 652
 653         return false;
 654 }
 655
 656 void
 657 radv_check_gpu_hangs(struct radv_queue *queue, struct radeon_winsys_cs *cs)
 658 {
 659         struct radv_pipeline *graphics_pipeline, *compute_pipeline;
 660         struct radv_device *device = queue->device;
 661         enum ring_type ring;
 662         uint64_t addr;
 663
 664         ring = radv_queue_family_to_ring(queue->queue_family_index);
 665
 666         bool hang_occurred = radv_gpu_hang_occured(queue, ring);
 667         bool vm_fault_occurred = false;
 668         if (queue->device->instance->debug_flags & RADV_DEBUG_VM_FAULTS)
 669                 vm_fault_occurred = ac_vm_fault_occured(device->physical_device->rad_info.chip_class,
 670                                                         &device->dmesg_timestamp, &addr);
 671         if (!hang_occurred && !vm_fault_occurred)
 672                 return;
 673
 674         graphics_pipeline = radv_get_saved_graphics_pipeline(device);
 675         compute_pipeline = radv_get_saved_compute_pipeline(device);
 676
 677         fprintf(stderr, "GPU hang report:\n\n");
 678         radv_dump_device_name(device, stderr);
 679
 680         radv_dump_enabled_options(device, stderr);
 681         radv_dump_dmesg(stderr);
 682
 683         if (vm_fault_occurred) {
 684                 fprintf(stderr, "VM fault report.\n\n");
 685                 fprintf(stderr, "Failing VM page: 0x%08"PRIx64"\n\n", addr);
 686         }
 687
 688         radv_dump_debug_registers(device, stderr);
 689
 690         switch (ring) {
 691         case RING_GFX:
 692                 radv_dump_graphics_state(graphics_pipeline, compute_pipeline,
 693                                          stderr);
 694                 break;
 695         case RING_COMPUTE:
 696                 radv_dump_compute_state(compute_pipeline, stderr);
 697                 break;
 698         default:
 699                 assert(0);
 700                 break;
 701         }
 702
 703         radv_dump_trace(queue->device, cs);
 704         abort();
 705 }
 706
 707 void
 708 radv_print_spirv(uint32_t *data, uint32_t size, FILE *fp)
 709 {
 710         char path[] = "/tmp/fileXXXXXX";
 711         char line[2048], command[128];
 712         FILE *p;
 713         int fd;
 714
 715         /* Dump the binary into a temporary file. */
 716         fd = mkstemp(path);
 717         if (fd < 0)
 718                 return;
 719
 720         if (write(fd, data, size) == -1)
 721                 goto fail;
 722
 723         sprintf(command, "spirv-dis %s", path);
 724
 725         /* Disassemble using spirv-dis if installed. */
 726         p = popen(command, "r");
 727         if (p) {
 728                 while (fgets(line, sizeof(line), p))
 729                         fprintf(fp, "%s", line);
 730                 pclose(p);
 731         }
 732
 733 fail:
 734         close(fd);
 735         unlink(path);
 736 }