src/amd/vulkan/radv_debug.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #include <stdlib.h>
  29 #include <stdio.h>
  30 #include <sys/utsname.h>
  31
  32 #include "sid.h"
  33 #include "gfx9d.h"
  34 #include "ac_debug.h"
  35 #include "radv_debug.h"
  36 #include "radv_shader.h"
  37
  38 #define TRACE_BO_SIZE 4096
  39
  40 #define COLOR_RESET     "\033[0m"
  41 #define COLOR_RED       "\033[31m"
  42 #define COLOR_GREEN     "\033[1;32m"
  43 #define COLOR_YELLOW    "\033[1;33m"
  44 #define COLOR_CYAN      "\033[1;36m"
  45
  46 /* Trace BO layout (offsets are 4 bytes):
  47  *
  48  * [0]: primary trace ID
  49  * [1]: secondary trace ID
  50  * [2-3]: 64-bit GFX pipeline pointer
  51  * [4-5]: 64-bit COMPUTE pipeline pointer
  52  * [6-7]: 64-bit descriptor set #0 pointer
  53  * ...
  54  * [68-69]: 64-bit descriptor set #31 pointer
  55  */
  56
  57 bool
  58 radv_init_trace(struct radv_device *device)
  59 {
  60         struct radeon_winsys *ws = device->ws;
  61
  62         device->trace_bo = ws->buffer_create(ws, TRACE_BO_SIZE, 8,
  63                                              RADEON_DOMAIN_VRAM,
  64                                              RADEON_FLAG_CPU_ACCESS);
  65         if (!device->trace_bo)
  66                 return false;
  67
  68         device->trace_id_ptr = ws->buffer_map(device->trace_bo);
  69         if (!device->trace_id_ptr)
  70                 return false;
  71
  72         memset(device->trace_id_ptr, 0, TRACE_BO_SIZE);
  73
  74         ac_vm_fault_occured(device->physical_device->rad_info.chip_class,
  75                             &device->dmesg_timestamp, NULL);
  76
  77         return true;
  78 }
  79
  80 static void
  81 radv_dump_trace(struct radv_device *device, struct radeon_winsys_cs *cs)
  82 {
  83         const char *filename = getenv("RADV_TRACE_FILE");
  84         FILE *f = fopen(filename, "w");
  85
  86         if (!f) {
  87                 fprintf(stderr, "Failed to write trace dump to %s\n", filename);
  88                 return;
  89         }
  90
  91         fprintf(f, "Trace ID: %x\n", *device->trace_id_ptr);
  92         device->ws->cs_dump(cs, f, (const int*)device->trace_id_ptr, 2);
  93         fclose(f);
  94 }
  95
  96 static void
  97 radv_dump_mmapped_reg(struct radv_device *device, FILE *f, unsigned offset)
  98 {
  99         struct radeon_winsys *ws = device->ws;
 100         uint32_t value;
 101
 102         if (ws->read_registers(ws, offset, 1, &value))
 103                 ac_dump_reg(f, device->physical_device->rad_info.chip_class,
 104                             offset, value, ~0);
 105 }
 106
 107 static void
 108 radv_dump_debug_registers(struct radv_device *device, FILE *f)
 109 {
 110         struct radeon_info *info = &device->physical_device->rad_info;
 111
 112         if (info->drm_major == 2 && info->drm_minor < 42)
 113                 return; /* no radeon support */
 114
 115         fprintf(f, "Memory-mapped registers:\n");
 116         radv_dump_mmapped_reg(device, f, R_008010_GRBM_STATUS);
 117
 118         /* No other registers can be read on DRM < 3.1.0. */
 119         if (info->drm_major < 3 || info->drm_minor < 1) {
 120                 fprintf(f, "\n");
 121                 return;
 122         }
 123
 124         radv_dump_mmapped_reg(device, f, R_008008_GRBM_STATUS2);
 125         radv_dump_mmapped_reg(device, f, R_008014_GRBM_STATUS_SE0);
 126         radv_dump_mmapped_reg(device, f, R_008018_GRBM_STATUS_SE1);
 127         radv_dump_mmapped_reg(device, f, R_008038_GRBM_STATUS_SE2);
 128         radv_dump_mmapped_reg(device, f, R_00803C_GRBM_STATUS_SE3);
 129         radv_dump_mmapped_reg(device, f, R_00D034_SDMA0_STATUS_REG);
 130         radv_dump_mmapped_reg(device, f, R_00D834_SDMA1_STATUS_REG);
 131         if (info->chip_class <= VI) {
 132                 radv_dump_mmapped_reg(device, f, R_000E50_SRBM_STATUS);
 133                 radv_dump_mmapped_reg(device, f, R_000E4C_SRBM_STATUS2);
 134                 radv_dump_mmapped_reg(device, f, R_000E54_SRBM_STATUS3);
 135         }
 136         radv_dump_mmapped_reg(device, f, R_008680_CP_STAT);
 137         radv_dump_mmapped_reg(device, f, R_008674_CP_STALLED_STAT1);
 138         radv_dump_mmapped_reg(device, f, R_008678_CP_STALLED_STAT2);
 139         radv_dump_mmapped_reg(device, f, R_008670_CP_STALLED_STAT3);
 140         radv_dump_mmapped_reg(device, f, R_008210_CP_CPC_STATUS);
 141         radv_dump_mmapped_reg(device, f, R_008214_CP_CPC_BUSY_STAT);
 142         radv_dump_mmapped_reg(device, f, R_008218_CP_CPC_STALLED_STAT1);
 143         radv_dump_mmapped_reg(device, f, R_00821C_CP_CPF_STATUS);
 144         radv_dump_mmapped_reg(device, f, R_008220_CP_CPF_BUSY_STAT);
 145         radv_dump_mmapped_reg(device, f, R_008224_CP_CPF_STALLED_STAT1);
 146         fprintf(f, "\n");
 147 }
 148
 149 static const char *
 150 radv_get_descriptor_name(enum VkDescriptorType type)
 151 {
 152         switch (type) {
 153         case VK_DESCRIPTOR_TYPE_SAMPLER:
 154                 return "SAMPLER";
 155         case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
 156                 return "COMBINED_IMAGE_SAMPLER";
 157         case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
 158                 return "SAMPLED_IMAGE";
 159         case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
 160                 return "STORAGE_IMAGE";
 161         case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
 162                 return "UNIFORM_TEXEL_BUFFER";
 163         case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
 164                 return "STORAGE_TEXEL_BUFFER";
 165         case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
 166                 return "UNIFORM_BUFFER";
 167         case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
 168                 return "STORAGE_BUFFER";
 169         case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
 170                 return "UNIFORM_BUFFER_DYNAMIC";
 171         case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
 172                 return "STORAGE_BUFFER_DYNAMIC";
 173         case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
 174                 return "INPUT_ATTACHMENT";
 175         default:
 176                 return "UNKNOWN";
 177         }
 178 }
 179
 180 static void
 181 radv_dump_buffer_descriptor(enum chip_class chip_class, const uint32_t *desc,
 182                             FILE *f)
 183 {
 184         fprintf(f, COLOR_CYAN "    Buffer:" COLOR_RESET "\n");
 185         for (unsigned j = 0; j < 4; j++)
 186                 ac_dump_reg(f, chip_class, R_008F00_SQ_BUF_RSRC_WORD0 + j * 4,
 187                             desc[j], 0xffffffff);
 188 }
 189
 190 static void
 191 radv_dump_image_descriptor(enum chip_class chip_class, const uint32_t *desc,
 192                            FILE *f)
 193 {
 194         fprintf(f, COLOR_CYAN "    Image:" COLOR_RESET "\n");
 195         for (unsigned j = 0; j < 8; j++)
 196                 ac_dump_reg(f, chip_class, R_008F10_SQ_IMG_RSRC_WORD0 + j * 4,
 197                             desc[j], 0xffffffff);
 198
 199         fprintf(f, COLOR_CYAN "    FMASK:" COLOR_RESET "\n");
 200         for (unsigned j = 0; j < 8; j++)
 201                 ac_dump_reg(f, chip_class, R_008F10_SQ_IMG_RSRC_WORD0 + j * 4,
 202                             desc[8 + j], 0xffffffff);
 203 }
 204
 205 static void
 206 radv_dump_sampler_descriptor(enum chip_class chip_class, const uint32_t *desc,
 207                              FILE *f)
 208 {
 209         fprintf(f, COLOR_CYAN "    Sampler state:" COLOR_RESET "\n");
 210         for (unsigned j = 0; j < 4; j++) {
 211                 ac_dump_reg(f, chip_class, R_008F30_SQ_IMG_SAMP_WORD0 + j * 4,
 212                             desc[j], 0xffffffff);
 213         }
 214 }
 215
 216 static void
 217 radv_dump_combined_image_sampler_descriptor(enum chip_class chip_class,
 218                                             const uint32_t *desc, FILE *f)
 219 {
 220         radv_dump_image_descriptor(chip_class, desc, f);
 221         radv_dump_sampler_descriptor(chip_class, desc + 16, f);
 222 }
 223
 224 static void
 225 radv_dump_descriptor_set(enum chip_class chip_class,
 226                          struct radv_descriptor_set *set, unsigned id, FILE *f)
 227 {
 228         const struct radv_descriptor_set_layout *layout;
 229         int i;
 230
 231         if (!set)
 232                 return;
 233         layout = set->layout;
 234
 235         fprintf(f, "** descriptor set (%d) **\n", id);
 236         fprintf(f, "va: 0x%"PRIx64"\n", set->va);
 237         fprintf(f, "size: %d\n", set->size);
 238         fprintf(f, "mapped_ptr:\n");
 239
 240         for (i = 0; i < set->size / 4; i++) {
 241                 fprintf(f, "\t[0x%x] = 0x%08x\n", i, set->mapped_ptr[i]);
 242         }
 243         fprintf(f, "\n");
 244
 245         fprintf(f, "\t*** layout ***\n");
 246         fprintf(f, "\tbinding_count: %d\n", layout->binding_count);
 247         fprintf(f, "\tsize: %d\n", layout->size);
 248         fprintf(f, "\tshader_stages: %x\n", layout->shader_stages);
 249         fprintf(f, "\tdynamic_shader_stages: %x\n",
 250                 layout->dynamic_shader_stages);
 251         fprintf(f, "\tbuffer_count: %d\n", layout->buffer_count);
 252         fprintf(f, "\tdynamic_offset_count: %d\n",
 253                 layout->dynamic_offset_count);
 254         fprintf(f, "\n");
 255
 256         for (i = 0; i < set->layout->binding_count; i++) {
 257                 uint32_t *desc =
 258                         set->mapped_ptr + layout->binding[i].offset / 4;
 259
 260                 fprintf(f, "\t\t**** binding layout (%d) ****\n", i);
 261                 fprintf(f, "\t\ttype: %s\n",
 262                         radv_get_descriptor_name(layout->binding[i].type));
 263                 fprintf(f, "\t\tarray_size: %d\n",
 264                         layout->binding[i].array_size);
 265                 fprintf(f, "\t\toffset: %d\n",
 266                         layout->binding[i].offset);
 267                 fprintf(f, "\t\tbuffer_offset: %d\n",
 268                         layout->binding[i].buffer_offset);
 269                 fprintf(f, "\t\tdynamic_offset_offset: %d\n",
 270                         layout->binding[i].dynamic_offset_offset);
 271                 fprintf(f, "\t\tdynamic_offset_count: %d\n",
 272                         layout->binding[i].dynamic_offset_count);
 273                 fprintf(f, "\t\tsize: %d\n",
 274                         layout->binding[i].size);
 275                 fprintf(f, "\t\timmutable_samplers_offset: %d\n",
 276                         layout->binding[i].immutable_samplers_offset);
 277                 fprintf(f, "\t\timmutable_samplers_equal: %d\n",
 278                         layout->binding[i].immutable_samplers_equal);
 279                 fprintf(f, "\n");
 280
 281                 switch (layout->binding[i].type) {
 282                 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
 283                 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
 284                 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
 285                 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
 286                         radv_dump_buffer_descriptor(chip_class, desc, f);
 287                         break;
 288                 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
 289                 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
 290                 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
 291                         radv_dump_image_descriptor(chip_class, desc, f);
 292                         break;
 293                 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
 294                         radv_dump_combined_image_sampler_descriptor(chip_class, desc, f);
 295                         break;
 296                 case VK_DESCRIPTOR_TYPE_SAMPLER:
 297                         radv_dump_sampler_descriptor(chip_class, desc, f);
 298                         break;
 299                 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
 300                 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
 301                         /* todo */
 302                         break;
 303                 default:
 304                         assert(!"unknown descriptor type");
 305                         break;
 306                 }
 307                 fprintf(f, "\n");
 308         }
 309         fprintf(f, "\n\n");
 310 }
 311
 312 static void
 313 radv_dump_descriptors(struct radv_pipeline *pipeline, FILE *f)
 314 {
 315         struct radv_device *device = pipeline->device;
 316         enum chip_class chip_class = device->physical_device->rad_info.chip_class;
 317         uint64_t *ptr = (uint64_t *)device->trace_id_ptr;
 318         int i;
 319
 320         fprintf(f, "List of descriptors:\n");
 321         for (i = 0; i < MAX_SETS; i++) {
 322                 struct radv_descriptor_set *set =
 323                         (struct radv_descriptor_set *)ptr[i + 3];
 324
 325                 radv_dump_descriptor_set(chip_class, set, i, f);
 326         }
 327 }
 328
 329 struct radv_shader_inst {
 330         char text[160];  /* one disasm line */
 331         unsigned offset; /* instruction offset */
 332         unsigned size;   /* instruction size = 4 or 8 */
 333 };
 334
 335 /* Split a disassembly string into lines and add them to the array pointed
 336  * to by "instructions". */
 337 static void si_add_split_disasm(const char *disasm,
 338                                 uint64_t start_addr,
 339                                 unsigned *num,
 340                                 struct radv_shader_inst *instructions)
 341 {
 342         struct radv_shader_inst *last_inst = *num ? &instructions[*num - 1] : NULL;
 343         char *next;
 344
 345         while ((next = strchr(disasm, '\n'))) {
 346                 struct radv_shader_inst *inst = &instructions[*num];
 347                 unsigned len = next - disasm;
 348
 349                 assert(len < ARRAY_SIZE(inst->text));
 350                 memcpy(inst->text, disasm, len);
 351                 inst->text[len] = 0;
 352                 inst->offset = last_inst ? last_inst->offset + last_inst->size : 0;
 353
 354                 const char *semicolon = strchr(disasm, ';');
 355                 assert(semicolon);
 356                 /* More than 16 chars after ";" means the instruction is 8 bytes long. */
 357                 inst->size = next - semicolon > 16 ? 8 : 4;
 358
 359                 snprintf(inst->text + len, ARRAY_SIZE(inst->text) - len,
 360                         " [PC=0x%"PRIx64", off=%u, size=%u]",
 361                         start_addr + inst->offset, inst->offset, inst->size);
 362
 363                 last_inst = inst;
 364                 (*num)++;
 365                 disasm = next + 1;
 366         }
 367 }
 368
 369 static void
 370 radv_dump_annotated_shader(struct radv_pipeline *pipeline,
 371                            struct radv_shader_variant *shader,
 372                            gl_shader_stage stage,
 373                            struct ac_wave_info *waves, unsigned num_waves,
 374                            FILE *f)
 375 {
 376         struct radv_device *device = pipeline->device;
 377         uint64_t start_addr, end_addr;
 378         unsigned i;
 379
 380         if (!shader)
 381                 return;
 382
 383         start_addr = device->ws->buffer_get_va(shader->bo) + shader->bo_offset;
 384         end_addr = start_addr + shader->code_size;
 385
 386         /* See if any wave executes the shader. */
 387         for (i = 0; i < num_waves; i++) {
 388                 if (start_addr <= waves[i].pc && waves[i].pc <= end_addr)
 389                         break;
 390         }
 391
 392         if (i == num_waves)
 393                 return; /* the shader is not being executed */
 394
 395         /* Remember the first found wave. The waves are sorted according to PC. */
 396         waves = &waves[i];
 397         num_waves -= i;
 398
 399         /* Get the list of instructions.
 400          * Buffer size / 4 is the upper bound of the instruction count.
 401          */
 402         unsigned num_inst = 0;
 403         struct radv_shader_inst *instructions =
 404                 calloc(shader->code_size / 4, sizeof(struct radv_shader_inst));
 405
 406         si_add_split_disasm(shader->disasm_string,
 407                             start_addr, &num_inst, instructions);
 408
 409         fprintf(f, COLOR_YELLOW "%s - annotated disassembly:" COLOR_RESET "\n",
 410                 radv_get_shader_name(shader, stage));
 411
 412         /* Print instructions with annotations. */
 413         for (i = 0; i < num_inst; i++) {
 414                 struct radv_shader_inst *inst = &instructions[i];
 415
 416                 fprintf(f, "%s\n", inst->text);
 417
 418                 /* Print which waves execute the instruction right now. */
 419                 while (num_waves && start_addr + inst->offset == waves->pc) {
 420                         fprintf(f,
 421                                 "          " COLOR_GREEN "^ SE%u SH%u CU%u "
 422                                 "SIMD%u WAVE%u  EXEC=%016"PRIx64 "  ",
 423                                 waves->se, waves->sh, waves->cu, waves->simd,
 424                                 waves->wave, waves->exec);
 425
 426                         if (inst->size == 4) {
 427                                 fprintf(f, "INST32=%08X" COLOR_RESET "\n",
 428                                         waves->inst_dw0);
 429                         } else {
 430                                 fprintf(f, "INST64=%08X %08X" COLOR_RESET "\n",
 431                                         waves->inst_dw0, waves->inst_dw1);
 432                         }
 433
 434                         waves->matched = true;
 435                         waves = &waves[1];
 436                         num_waves--;
 437                 }
 438         }
 439
 440         fprintf(f, "\n\n");
 441         free(instructions);
 442 }
 443
 444 static void
 445 radv_dump_annotated_shaders(struct radv_pipeline *pipeline,
 446                             struct radv_shader_variant *compute_shader,
 447                             FILE *f)
 448 {
 449         struct ac_wave_info waves[AC_MAX_WAVES_PER_CHIP];
 450         unsigned num_waves = ac_get_wave_info(waves);
 451         unsigned mask;
 452
 453         fprintf(f, COLOR_CYAN "The number of active waves = %u" COLOR_RESET
 454                 "\n\n", num_waves);
 455
 456         /* Dump annotated active graphics shaders. */
 457         mask = pipeline->active_stages;
 458         while (mask) {
 459                 int stage = u_bit_scan(&mask);
 460
 461                 radv_dump_annotated_shader(pipeline, pipeline->shaders[stage],
 462                                            stage, waves, num_waves, f);
 463         }
 464
 465         radv_dump_annotated_shader(pipeline, compute_shader,
 466                                    MESA_SHADER_COMPUTE, waves, num_waves, f);
 467
 468         /* Print waves executing shaders that are not currently bound. */
 469         unsigned i;
 470         bool found = false;
 471         for (i = 0; i < num_waves; i++) {
 472                 if (waves[i].matched)
 473                         continue;
 474
 475                 if (!found) {
 476                         fprintf(f, COLOR_CYAN
 477                                 "Waves not executing currently-bound shaders:"
 478                                 COLOR_RESET "\n");
 479                         found = true;
 480                 }
 481                 fprintf(f, "    SE%u SH%u CU%u SIMD%u WAVE%u  EXEC=%016"PRIx64
 482                         "  INST=%08X %08X  PC=%"PRIx64"\n",
 483                         waves[i].se, waves[i].sh, waves[i].cu, waves[i].simd,
 484                         waves[i].wave, waves[i].exec, waves[i].inst_dw0,
 485                         waves[i].inst_dw1, waves[i].pc);
 486         }
 487         if (found)
 488                 fprintf(f, "\n\n");
 489 }
 490
 491 static void
 492 radv_dump_shader(struct radv_pipeline *pipeline,
 493                  struct radv_shader_variant *shader, gl_shader_stage stage,
 494                  FILE *f)
 495 {
 496         if (!shader)
 497                 return;
 498
 499         fprintf(f, "%s:\n%s\n\n", radv_get_shader_name(shader, stage),
 500                 shader->disasm_string);
 501
 502         radv_shader_dump_stats(pipeline->device, shader, stage, f);
 503 }
 504
 505 static void
 506 radv_dump_shaders(struct radv_pipeline *pipeline,
 507                   struct radv_shader_variant *compute_shader, FILE *f)
 508 {
 509         unsigned mask;
 510
 511         /* Dump active graphics shaders. */
 512         mask = pipeline->active_stages;
 513         while (mask) {
 514                 int stage = u_bit_scan(&mask);
 515
 516                 radv_dump_shader(pipeline, pipeline->shaders[stage], stage, f);
 517         }
 518
 519         radv_dump_shader(pipeline, compute_shader, MESA_SHADER_COMPUTE, f);
 520 }
 521
 522 static void
 523 radv_dump_graphics_state(struct radv_pipeline *graphics_pipeline,
 524                          struct radv_pipeline *compute_pipeline, FILE *f)
 525 {
 526         struct radv_shader_variant *compute_shader =
 527                 compute_pipeline ? compute_pipeline->shaders[MESA_SHADER_COMPUTE] : NULL;
 528
 529         if (!graphics_pipeline)
 530                 return;
 531
 532         radv_dump_shaders(graphics_pipeline, compute_shader, f);
 533         radv_dump_annotated_shaders(graphics_pipeline, compute_shader, f);
 534         radv_dump_descriptors(graphics_pipeline, f);
 535 }
 536
 537 static void
 538 radv_dump_compute_state(struct radv_pipeline *compute_pipeline, FILE *f)
 539 {
 540         if (!compute_pipeline)
 541                 return;
 542
 543         radv_dump_shaders(compute_pipeline,
 544                           compute_pipeline->shaders[MESA_SHADER_COMPUTE], f);
 545         radv_dump_annotated_shaders(compute_pipeline,
 546                                     compute_pipeline->shaders[MESA_SHADER_COMPUTE],
 547                                     f);
 548         radv_dump_descriptors(compute_pipeline, f);
 549 }
 550
 551 static struct radv_pipeline *
 552 radv_get_saved_graphics_pipeline(struct radv_device *device)
 553 {
 554         uint64_t *ptr = (uint64_t *)device->trace_id_ptr;
 555
 556         return (struct radv_pipeline *)ptr[1];
 557 }
 558
 559 static struct radv_pipeline *
 560 radv_get_saved_compute_pipeline(struct radv_device *device)
 561 {
 562         uint64_t *ptr = (uint64_t *)device->trace_id_ptr;
 563
 564         return (struct radv_pipeline *)ptr[2];
 565 }
 566
 567 static void
 568 radv_dump_dmesg(FILE *f)
 569 {
 570         char line[2000];
 571         FILE *p;
 572
 573         p = popen("dmesg | tail -n60", "r");
 574         if (!p)
 575                 return;
 576
 577         fprintf(f, "\nLast 60 lines of dmesg:\n\n");
 578         while (fgets(line, sizeof(line), p))
 579                 fputs(line, f);
 580         fprintf(f, "\n");
 581
 582         pclose(p);
 583 }
 584
 585 static void
 586 radv_dump_enabled_options(struct radv_device *device, FILE *f)
 587 {
 588         uint64_t mask;
 589
 590         fprintf(f, "Enabled debug options: ");
 591
 592         mask = device->debug_flags;
 593         while (mask) {
 594                 int i = u_bit_scan64(&mask);
 595                 fprintf(f, "%s, ", radv_get_debug_option_name(i));
 596         }
 597         fprintf(f, "\n");
 598
 599         fprintf(f, "Enabled perftest options: ");
 600
 601         mask = device->instance->perftest_flags;
 602         while (mask) {
 603                 int i = u_bit_scan64(&mask);
 604                 fprintf(f, "%s, ", radv_get_perftest_option_name(i));
 605         }
 606         fprintf(f, "\n");
 607 }
 608
 609 static void
 610 radv_dump_device_name(struct radv_device *device, FILE *f)
 611 {
 612         struct radeon_info *info = &device->physical_device->rad_info;
 613         char llvm_string[32] = {}, kernel_version[128] = {};
 614         struct utsname uname_data;
 615         const char *chip_name;
 616
 617         chip_name = device->ws->get_chip_name(device->ws);
 618
 619         if (uname(&uname_data) == 0)
 620                 snprintf(kernel_version, sizeof(kernel_version),
 621                          " / %s", uname_data.release);
 622
 623         if (HAVE_LLVM > 0) {
 624                 snprintf(llvm_string, sizeof(llvm_string),
 625                          ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
 626                          HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
 627         }
 628
 629         fprintf(f, "Device name: %s (%s DRM %i.%i.%i%s%s)\n\n",
 630                 chip_name, device->physical_device->name,
 631                 info->drm_major, info->drm_minor, info->drm_patchlevel,
 632                 kernel_version, llvm_string);
 633 }
 634
 635 static bool
 636 radv_gpu_hang_occured(struct radv_queue *queue, enum ring_type ring)
 637 {
 638         struct radeon_winsys *ws = queue->device->ws;
 639
 640         if (!ws->ctx_wait_idle(queue->hw_ctx, ring, queue->queue_idx))
 641                 return true;
 642
 643         return false;
 644 }
 645
 646 void
 647 radv_check_gpu_hangs(struct radv_queue *queue, struct radeon_winsys_cs *cs)
 648 {
 649         struct radv_pipeline *graphics_pipeline, *compute_pipeline;
 650         struct radv_device *device = queue->device;
 651         enum ring_type ring;
 652         uint64_t addr;
 653
 654         ring = radv_queue_family_to_ring(queue->queue_family_index);
 655
 656         bool hang_occurred = radv_gpu_hang_occured(queue, ring);
 657         bool vm_fault_occurred = false;
 658         if (queue->device->instance->debug_flags & RADV_DEBUG_VM_FAULTS)
 659                 vm_fault_occurred = ac_vm_fault_occured(device->physical_device->rad_info.chip_class,
 660                                                         &device->dmesg_timestamp, &addr);
 661         if (!hang_occurred && !vm_fault_occurred)
 662                 return;
 663
 664         graphics_pipeline = radv_get_saved_graphics_pipeline(device);
 665         compute_pipeline = radv_get_saved_compute_pipeline(device);
 666
 667         fprintf(stderr, "GPU hang report:\n\n");
 668         radv_dump_device_name(device, stderr);
 669
 670         radv_dump_enabled_options(device, stderr);
 671         radv_dump_dmesg(stderr);
 672
 673         if (vm_fault_occurred) {
 674                 fprintf(stderr, "VM fault report.\n\n");
 675                 fprintf(stderr, "Failing VM page: 0x%08"PRIx64"\n\n", addr);
 676         }
 677
 678         radv_dump_debug_registers(device, stderr);
 679
 680         switch (ring) {
 681         case RING_GFX:
 682                 radv_dump_graphics_state(graphics_pipeline, compute_pipeline,
 683                                          stderr);
 684                 break;
 685         case RING_COMPUTE:
 686                 radv_dump_compute_state(compute_pipeline, stderr);
 687                 break;
 688         default:
 689                 assert(0);
 690                 break;
 691         }
 692
 693         radv_dump_trace(queue->device, cs);
 694         abort();
 695 }
 696
 697 void
 698 radv_print_spirv(struct radv_shader_module *module, FILE *fp)
 699 {
 700         char path[] = "/tmp/fileXXXXXX";
 701         char line[2048], command[128];
 702         FILE *p;
 703         int fd;
 704
 705         /* Dump the binary into a temporary file. */
 706         fd = mkstemp(path);
 707         if (fd < 0)
 708                 return;
 709
 710         if (write(fd, module->data, module->size) == -1)
 711                 goto fail;
 712
 713         sprintf(command, "spirv-dis %s", path);
 714
 715         /* Disassemble using spirv-dis if installed. */
 716         p = popen(command, "r");
 717         if (p) {
 718                 while (fgets(line, sizeof(line), p))
 719                         fprintf(fp, "%s", line);
 720                 pclose(p);
 721         }
 722
 723 fail:
 724         close(fd);
 725         unlink(path);
 726 }