2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include <sys/utsname.h>
32 #include "util/mesa-sha1.h"
35 #include "radv_debug.h"
36 #include "radv_shader.h"
38 #define TRACE_BO_SIZE 4096
40 #define COLOR_RESET "\033[0m"
41 #define COLOR_RED "\033[31m"
42 #define COLOR_GREEN "\033[1;32m"
43 #define COLOR_YELLOW "\033[1;33m"
44 #define COLOR_CYAN "\033[1;36m"
46 /* Trace BO layout (offsets are 4 bytes):
48 * [0]: primary trace ID
49 * [1]: secondary trace ID
50 * [2-3]: 64-bit GFX pipeline pointer
51 * [4-5]: 64-bit COMPUTE pipeline pointer
52 * [6-7]: 64-bit descriptor set #0 pointer
54 * [68-69]: 64-bit descriptor set #31 pointer
58 radv_init_trace(struct radv_device
*device
)
60 struct radeon_winsys
*ws
= device
->ws
;
62 device
->trace_bo
= ws
->buffer_create(ws
, TRACE_BO_SIZE
, 8,
64 RADEON_FLAG_CPU_ACCESS
|
65 RADEON_FLAG_NO_INTERPROCESS_SHARING
,
66 RADV_BO_PRIORITY_UPLOAD_BUFFER
);
67 if (!device
->trace_bo
)
70 device
->trace_id_ptr
= ws
->buffer_map(device
->trace_bo
);
71 if (!device
->trace_id_ptr
)
74 memset(device
->trace_id_ptr
, 0, TRACE_BO_SIZE
);
76 ac_vm_fault_occured(device
->physical_device
->rad_info
.chip_class
,
77 &device
->dmesg_timestamp
, NULL
);
83 radv_dump_trace(struct radv_device
*device
, struct radeon_cmdbuf
*cs
)
85 const char *filename
= getenv("RADV_TRACE_FILE");
86 FILE *f
= fopen(filename
, "w");
89 fprintf(stderr
, "Failed to write trace dump to %s\n", filename
);
93 fprintf(f
, "Trace ID: %x\n", *device
->trace_id_ptr
);
94 device
->ws
->cs_dump(cs
, f
, (const int*)device
->trace_id_ptr
, 2);
99 radv_dump_mmapped_reg(struct radv_device
*device
, FILE *f
, unsigned offset
)
101 struct radeon_winsys
*ws
= device
->ws
;
104 if (ws
->read_registers(ws
, offset
, 1, &value
))
105 ac_dump_reg(f
, device
->physical_device
->rad_info
.chip_class
,
110 radv_dump_debug_registers(struct radv_device
*device
, FILE *f
)
112 struct radeon_info
*info
= &device
->physical_device
->rad_info
;
114 fprintf(f
, "Memory-mapped registers:\n");
115 radv_dump_mmapped_reg(device
, f
, R_008010_GRBM_STATUS
);
117 /* No other registers can be read on DRM < 3.1.0. */
118 if (info
->drm_minor
< 1) {
123 radv_dump_mmapped_reg(device
, f
, R_008008_GRBM_STATUS2
);
124 radv_dump_mmapped_reg(device
, f
, R_008014_GRBM_STATUS_SE0
);
125 radv_dump_mmapped_reg(device
, f
, R_008018_GRBM_STATUS_SE1
);
126 radv_dump_mmapped_reg(device
, f
, R_008038_GRBM_STATUS_SE2
);
127 radv_dump_mmapped_reg(device
, f
, R_00803C_GRBM_STATUS_SE3
);
128 radv_dump_mmapped_reg(device
, f
, R_00D034_SDMA0_STATUS_REG
);
129 radv_dump_mmapped_reg(device
, f
, R_00D834_SDMA1_STATUS_REG
);
130 if (info
->chip_class
<= GFX8
) {
131 radv_dump_mmapped_reg(device
, f
, R_000E50_SRBM_STATUS
);
132 radv_dump_mmapped_reg(device
, f
, R_000E4C_SRBM_STATUS2
);
133 radv_dump_mmapped_reg(device
, f
, R_000E54_SRBM_STATUS3
);
135 radv_dump_mmapped_reg(device
, f
, R_008680_CP_STAT
);
136 radv_dump_mmapped_reg(device
, f
, R_008674_CP_STALLED_STAT1
);
137 radv_dump_mmapped_reg(device
, f
, R_008678_CP_STALLED_STAT2
);
138 radv_dump_mmapped_reg(device
, f
, R_008670_CP_STALLED_STAT3
);
139 radv_dump_mmapped_reg(device
, f
, R_008210_CP_CPC_STATUS
);
140 radv_dump_mmapped_reg(device
, f
, R_008214_CP_CPC_BUSY_STAT
);
141 radv_dump_mmapped_reg(device
, f
, R_008218_CP_CPC_STALLED_STAT1
);
142 radv_dump_mmapped_reg(device
, f
, R_00821C_CP_CPF_STATUS
);
143 radv_dump_mmapped_reg(device
, f
, R_008220_CP_CPF_BUSY_STAT
);
144 radv_dump_mmapped_reg(device
, f
, R_008224_CP_CPF_STALLED_STAT1
);
149 radv_get_descriptor_name(enum VkDescriptorType type
)
152 case VK_DESCRIPTOR_TYPE_SAMPLER
:
154 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
155 return "COMBINED_IMAGE_SAMPLER";
156 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
:
157 return "SAMPLED_IMAGE";
158 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
:
159 return "STORAGE_IMAGE";
160 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
161 return "UNIFORM_TEXEL_BUFFER";
162 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
163 return "STORAGE_TEXEL_BUFFER";
164 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
165 return "UNIFORM_BUFFER";
166 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
167 return "STORAGE_BUFFER";
168 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
169 return "UNIFORM_BUFFER_DYNAMIC";
170 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
:
171 return "STORAGE_BUFFER_DYNAMIC";
172 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
173 return "INPUT_ATTACHMENT";
180 radv_dump_buffer_descriptor(enum chip_class chip_class
, const uint32_t *desc
,
183 fprintf(f
, COLOR_CYAN
" Buffer:" COLOR_RESET
"\n");
184 for (unsigned j
= 0; j
< 4; j
++)
185 ac_dump_reg(f
, chip_class
, R_008F00_SQ_BUF_RSRC_WORD0
+ j
* 4,
186 desc
[j
], 0xffffffff);
190 radv_dump_image_descriptor(enum chip_class chip_class
, const uint32_t *desc
,
193 fprintf(f
, COLOR_CYAN
" Image:" COLOR_RESET
"\n");
194 for (unsigned j
= 0; j
< 8; j
++)
195 ac_dump_reg(f
, chip_class
, R_008F10_SQ_IMG_RSRC_WORD0
+ j
* 4,
196 desc
[j
], 0xffffffff);
198 fprintf(f
, COLOR_CYAN
" FMASK:" COLOR_RESET
"\n");
199 for (unsigned j
= 0; j
< 8; j
++)
200 ac_dump_reg(f
, chip_class
, R_008F10_SQ_IMG_RSRC_WORD0
+ j
* 4,
201 desc
[8 + j
], 0xffffffff);
205 radv_dump_sampler_descriptor(enum chip_class chip_class
, const uint32_t *desc
,
208 fprintf(f
, COLOR_CYAN
" Sampler state:" COLOR_RESET
"\n");
209 for (unsigned j
= 0; j
< 4; j
++) {
210 ac_dump_reg(f
, chip_class
, R_008F30_SQ_IMG_SAMP_WORD0
+ j
* 4,
211 desc
[j
], 0xffffffff);
216 radv_dump_combined_image_sampler_descriptor(enum chip_class chip_class
,
217 const uint32_t *desc
, FILE *f
)
219 radv_dump_image_descriptor(chip_class
, desc
, f
);
220 radv_dump_sampler_descriptor(chip_class
, desc
+ 16, f
);
224 radv_dump_descriptor_set(enum chip_class chip_class
,
225 struct radv_descriptor_set
*set
, unsigned id
, FILE *f
)
227 const struct radv_descriptor_set_layout
*layout
;
232 layout
= set
->layout
;
234 fprintf(f
, "** descriptor set (%d) **\n", id
);
235 fprintf(f
, "va: 0x%"PRIx64
"\n", set
->va
);
236 fprintf(f
, "size: %d\n", set
->size
);
237 fprintf(f
, "mapped_ptr:\n");
239 for (i
= 0; i
< set
->size
/ 4; i
++) {
240 fprintf(f
, "\t[0x%x] = 0x%08x\n", i
, set
->mapped_ptr
[i
]);
244 fprintf(f
, "\t*** layout ***\n");
245 fprintf(f
, "\tbinding_count: %d\n", layout
->binding_count
);
246 fprintf(f
, "\tsize: %d\n", layout
->size
);
247 fprintf(f
, "\tshader_stages: %x\n", layout
->shader_stages
);
248 fprintf(f
, "\tdynamic_shader_stages: %x\n",
249 layout
->dynamic_shader_stages
);
250 fprintf(f
, "\tbuffer_count: %d\n", layout
->buffer_count
);
251 fprintf(f
, "\tdynamic_offset_count: %d\n",
252 layout
->dynamic_offset_count
);
255 for (i
= 0; i
< set
->layout
->binding_count
; i
++) {
257 set
->mapped_ptr
+ layout
->binding
[i
].offset
/ 4;
259 fprintf(f
, "\t\t**** binding layout (%d) ****\n", i
);
260 fprintf(f
, "\t\ttype: %s\n",
261 radv_get_descriptor_name(layout
->binding
[i
].type
));
262 fprintf(f
, "\t\tarray_size: %d\n",
263 layout
->binding
[i
].array_size
);
264 fprintf(f
, "\t\toffset: %d\n",
265 layout
->binding
[i
].offset
);
266 fprintf(f
, "\t\tbuffer_offset: %d\n",
267 layout
->binding
[i
].buffer_offset
);
268 fprintf(f
, "\t\tdynamic_offset_offset: %d\n",
269 layout
->binding
[i
].dynamic_offset_offset
);
270 fprintf(f
, "\t\tdynamic_offset_count: %d\n",
271 layout
->binding
[i
].dynamic_offset_count
);
272 fprintf(f
, "\t\tsize: %d\n",
273 layout
->binding
[i
].size
);
274 fprintf(f
, "\t\timmutable_samplers_offset: %d\n",
275 layout
->binding
[i
].immutable_samplers_offset
);
276 fprintf(f
, "\t\timmutable_samplers_equal: %d\n",
277 layout
->binding
[i
].immutable_samplers_equal
);
280 switch (layout
->binding
[i
].type
) {
281 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
282 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
283 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
284 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
285 radv_dump_buffer_descriptor(chip_class
, desc
, f
);
287 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
:
288 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
:
289 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
290 radv_dump_image_descriptor(chip_class
, desc
, f
);
292 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
293 radv_dump_combined_image_sampler_descriptor(chip_class
, desc
, f
);
295 case VK_DESCRIPTOR_TYPE_SAMPLER
:
296 radv_dump_sampler_descriptor(chip_class
, desc
, f
);
298 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
299 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
:
303 assert(!"unknown descriptor type");
312 radv_dump_descriptors(struct radv_pipeline
*pipeline
, FILE *f
)
314 struct radv_device
*device
= pipeline
->device
;
315 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
316 uint64_t *ptr
= (uint64_t *)device
->trace_id_ptr
;
319 fprintf(f
, "List of descriptors:\n");
320 for (i
= 0; i
< MAX_SETS
; i
++) {
321 struct radv_descriptor_set
*set
=
322 (struct radv_descriptor_set
*)ptr
[i
+ 3];
324 radv_dump_descriptor_set(chip_class
, set
, i
, f
);
328 struct radv_shader_inst
{
329 char text
[160]; /* one disasm line */
330 unsigned offset
; /* instruction offset */
331 unsigned size
; /* instruction size = 4 or 8 */
334 /* Split a disassembly string into lines and add them to the array pointed
335 * to by "instructions". */
336 static void si_add_split_disasm(const char *disasm
,
339 struct radv_shader_inst
*instructions
)
341 struct radv_shader_inst
*last_inst
= *num
? &instructions
[*num
- 1] : NULL
;
344 while ((next
= strchr(disasm
, '\n'))) {
345 struct radv_shader_inst
*inst
= &instructions
[*num
];
346 unsigned len
= next
- disasm
;
348 assert(len
< ARRAY_SIZE(inst
->text
));
349 memcpy(inst
->text
, disasm
, len
);
351 inst
->offset
= last_inst
? last_inst
->offset
+ last_inst
->size
: 0;
353 const char *semicolon
= strchr(disasm
, ';');
355 /* More than 16 chars after ";" means the instruction is 8 bytes long. */
356 inst
->size
= next
- semicolon
> 16 ? 8 : 4;
358 snprintf(inst
->text
+ len
, ARRAY_SIZE(inst
->text
) - len
,
359 " [PC=0x%"PRIx64
", off=%u, size=%u]",
360 start_addr
+ inst
->offset
, inst
->offset
, inst
->size
);
369 radv_dump_annotated_shader(struct radv_shader_variant
*shader
,
370 gl_shader_stage stage
, struct ac_wave_info
*waves
,
371 unsigned num_waves
, FILE *f
)
373 uint64_t start_addr
, end_addr
;
379 start_addr
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
380 end_addr
= start_addr
+ shader
->code_size
;
382 /* See if any wave executes the shader. */
383 for (i
= 0; i
< num_waves
; i
++) {
384 if (start_addr
<= waves
[i
].pc
&& waves
[i
].pc
<= end_addr
)
389 return; /* the shader is not being executed */
391 /* Remember the first found wave. The waves are sorted according to PC. */
395 /* Get the list of instructions.
396 * Buffer size / 4 is the upper bound of the instruction count.
398 unsigned num_inst
= 0;
399 struct radv_shader_inst
*instructions
=
400 calloc(shader
->code_size
/ 4, sizeof(struct radv_shader_inst
));
402 si_add_split_disasm(shader
->disasm_string
,
403 start_addr
, &num_inst
, instructions
);
405 fprintf(f
, COLOR_YELLOW
"%s - annotated disassembly:" COLOR_RESET
"\n",
406 radv_get_shader_name(shader
, stage
));
408 /* Print instructions with annotations. */
409 for (i
= 0; i
< num_inst
; i
++) {
410 struct radv_shader_inst
*inst
= &instructions
[i
];
412 fprintf(f
, "%s\n", inst
->text
);
414 /* Print which waves execute the instruction right now. */
415 while (num_waves
&& start_addr
+ inst
->offset
== waves
->pc
) {
417 " " COLOR_GREEN
"^ SE%u SH%u CU%u "
418 "SIMD%u WAVE%u EXEC=%016"PRIx64
" ",
419 waves
->se
, waves
->sh
, waves
->cu
, waves
->simd
,
420 waves
->wave
, waves
->exec
);
422 if (inst
->size
== 4) {
423 fprintf(f
, "INST32=%08X" COLOR_RESET
"\n",
426 fprintf(f
, "INST64=%08X %08X" COLOR_RESET
"\n",
427 waves
->inst_dw0
, waves
->inst_dw1
);
430 waves
->matched
= true;
441 radv_dump_annotated_shaders(struct radv_pipeline
*pipeline
,
442 VkShaderStageFlagBits active_stages
, FILE *f
)
444 struct ac_wave_info waves
[AC_MAX_WAVES_PER_CHIP
];
445 unsigned num_waves
= ac_get_wave_info(waves
);
447 fprintf(f
, COLOR_CYAN
"The number of active waves = %u" COLOR_RESET
450 /* Dump annotated active graphics shaders. */
451 while (active_stages
) {
452 int stage
= u_bit_scan(&active_stages
);
454 radv_dump_annotated_shader(pipeline
->shaders
[stage
],
455 stage
, waves
, num_waves
, f
);
458 /* Print waves executing shaders that are not currently bound. */
461 for (i
= 0; i
< num_waves
; i
++) {
462 if (waves
[i
].matched
)
466 fprintf(f
, COLOR_CYAN
467 "Waves not executing currently-bound shaders:"
471 fprintf(f
, " SE%u SH%u CU%u SIMD%u WAVE%u EXEC=%016"PRIx64
472 " INST=%08X %08X PC=%"PRIx64
"\n",
473 waves
[i
].se
, waves
[i
].sh
, waves
[i
].cu
, waves
[i
].simd
,
474 waves
[i
].wave
, waves
[i
].exec
, waves
[i
].inst_dw0
,
475 waves
[i
].inst_dw1
, waves
[i
].pc
);
482 radv_dump_shader(struct radv_pipeline
*pipeline
,
483 struct radv_shader_variant
*shader
, gl_shader_stage stage
,
489 fprintf(f
, "%s:\n\n", radv_get_shader_name(shader
, stage
));
492 unsigned char sha1
[21];
495 _mesa_sha1_compute(shader
->spirv
, shader
->spirv_size
, sha1
);
496 _mesa_sha1_format(sha1buf
, sha1
);
498 fprintf(f
, "SPIRV (sha1: %s):\n", sha1buf
);
499 radv_print_spirv(shader
->spirv
, shader
->spirv_size
, f
);
503 fprintf(f
, "NIR:\n");
504 nir_print_shader(shader
->nir
, f
);
507 fprintf(f
, "LLVM IR:\n%s\n", shader
->llvm_ir_string
);
508 fprintf(f
, "DISASM:\n%s\n", shader
->disasm_string
);
510 radv_shader_dump_stats(pipeline
->device
, shader
, stage
, f
);
514 radv_dump_shaders(struct radv_pipeline
*pipeline
,
515 VkShaderStageFlagBits active_stages
, FILE *f
)
517 /* Dump active graphics shaders. */
518 while (active_stages
) {
519 int stage
= u_bit_scan(&active_stages
);
521 radv_dump_shader(pipeline
, pipeline
->shaders
[stage
], stage
, f
);
526 radv_dump_pipeline_state(struct radv_pipeline
*pipeline
,
527 VkShaderStageFlagBits active_stages
, FILE *f
)
529 radv_dump_shaders(pipeline
, active_stages
, f
);
530 radv_dump_annotated_shaders(pipeline
, active_stages
, f
);
531 radv_dump_descriptors(pipeline
, f
);
535 radv_dump_graphics_state(struct radv_pipeline
*graphics_pipeline
,
536 struct radv_pipeline
*compute_pipeline
, FILE *f
)
538 VkShaderStageFlagBits active_stages
;
540 if (graphics_pipeline
) {
541 active_stages
= graphics_pipeline
->active_stages
;
542 radv_dump_pipeline_state(graphics_pipeline
, active_stages
, f
);
545 if (compute_pipeline
) {
546 active_stages
= VK_SHADER_STAGE_COMPUTE_BIT
;
547 radv_dump_pipeline_state(compute_pipeline
, active_stages
, f
);
552 radv_dump_compute_state(struct radv_pipeline
*compute_pipeline
, FILE *f
)
554 VkShaderStageFlagBits active_stages
= VK_SHADER_STAGE_COMPUTE_BIT
;
556 if (!compute_pipeline
)
559 radv_dump_pipeline_state(compute_pipeline
, active_stages
, f
);
562 static struct radv_pipeline
*
563 radv_get_saved_graphics_pipeline(struct radv_device
*device
)
565 uint64_t *ptr
= (uint64_t *)device
->trace_id_ptr
;
567 return (struct radv_pipeline
*)ptr
[1];
570 static struct radv_pipeline
*
571 radv_get_saved_compute_pipeline(struct radv_device
*device
)
573 uint64_t *ptr
= (uint64_t *)device
->trace_id_ptr
;
575 return (struct radv_pipeline
*)ptr
[2];
579 radv_dump_dmesg(FILE *f
)
584 p
= popen("dmesg | tail -n60", "r");
588 fprintf(f
, "\nLast 60 lines of dmesg:\n\n");
589 while (fgets(line
, sizeof(line
), p
))
597 radv_dump_enabled_options(struct radv_device
*device
, FILE *f
)
601 if (device
->instance
->debug_flags
) {
602 fprintf(f
, "Enabled debug options: ");
604 mask
= device
->instance
->debug_flags
;
606 int i
= u_bit_scan64(&mask
);
607 fprintf(f
, "%s, ", radv_get_debug_option_name(i
));
612 if (device
->instance
->perftest_flags
) {
613 fprintf(f
, "Enabled perftest options: ");
615 mask
= device
->instance
->perftest_flags
;
617 int i
= u_bit_scan64(&mask
);
618 fprintf(f
, "%s, ", radv_get_perftest_option_name(i
));
625 radv_dump_device_name(struct radv_device
*device
, FILE *f
)
627 struct radeon_info
*info
= &device
->physical_device
->rad_info
;
628 char kernel_version
[128] = {};
629 struct utsname uname_data
;
630 const char *chip_name
;
632 chip_name
= device
->ws
->get_chip_name(device
->ws
);
634 if (uname(&uname_data
) == 0)
635 snprintf(kernel_version
, sizeof(kernel_version
),
636 " / %s", uname_data
.release
);
638 fprintf(f
, "Device name: %s (%s DRM %i.%i.%i%s, LLVM "
639 MESA_LLVM_VERSION_STRING
")\n\n",
640 chip_name
, device
->physical_device
->name
,
641 info
->drm_major
, info
->drm_minor
, info
->drm_patchlevel
,
646 radv_gpu_hang_occured(struct radv_queue
*queue
, enum ring_type ring
)
648 struct radeon_winsys
*ws
= queue
->device
->ws
;
650 if (!ws
->ctx_wait_idle(queue
->hw_ctx
, ring
, queue
->queue_idx
))
657 radv_check_gpu_hangs(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
)
659 struct radv_pipeline
*graphics_pipeline
, *compute_pipeline
;
660 struct radv_device
*device
= queue
->device
;
664 ring
= radv_queue_family_to_ring(queue
->queue_family_index
);
666 bool hang_occurred
= radv_gpu_hang_occured(queue
, ring
);
667 bool vm_fault_occurred
= false;
668 if (queue
->device
->instance
->debug_flags
& RADV_DEBUG_VM_FAULTS
)
669 vm_fault_occurred
= ac_vm_fault_occured(device
->physical_device
->rad_info
.chip_class
,
670 &device
->dmesg_timestamp
, &addr
);
671 if (!hang_occurred
&& !vm_fault_occurred
)
674 graphics_pipeline
= radv_get_saved_graphics_pipeline(device
);
675 compute_pipeline
= radv_get_saved_compute_pipeline(device
);
677 fprintf(stderr
, "GPU hang report:\n\n");
678 radv_dump_device_name(device
, stderr
);
680 radv_dump_enabled_options(device
, stderr
);
681 radv_dump_dmesg(stderr
);
683 if (vm_fault_occurred
) {
684 fprintf(stderr
, "VM fault report.\n\n");
685 fprintf(stderr
, "Failing VM page: 0x%08"PRIx64
"\n\n", addr
);
688 radv_dump_debug_registers(device
, stderr
);
692 radv_dump_graphics_state(graphics_pipeline
, compute_pipeline
,
696 radv_dump_compute_state(compute_pipeline
, stderr
);
703 radv_dump_trace(queue
->device
, cs
);
708 radv_print_spirv(uint32_t *data
, uint32_t size
, FILE *fp
)
710 char path
[] = "/tmp/fileXXXXXX";
711 char line
[2048], command
[128];
715 /* Dump the binary into a temporary file. */
720 if (write(fd
, data
, size
) == -1)
723 sprintf(command
, "spirv-dis %s", path
);
725 /* Disassemble using spirv-dis if installed. */
726 p
= popen(command
, "r");
728 while (fgets(line
, sizeof(line
), p
))
729 fprintf(fp
, "%s", line
);