src/amd/vulkan/radv_debug.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #include <stdlib.h>
  29 #include <stdio.h>
  30 #include <sys/utsname.h>
  31
  32 #include "util/mesa-sha1.h"
  33 #include "sid.h"
  34 #include "ac_debug.h"
  35 #include "radv_debug.h"
  36 #include "radv_shader.h"
  37
  38 #define TRACE_BO_SIZE 4096
  39
  40 #define COLOR_RESET     "\033[0m"
  41 #define COLOR_RED       "\033[31m"
  42 #define COLOR_GREEN     "\033[1;32m"
  43 #define COLOR_YELLOW    "\033[1;33m"
  44 #define COLOR_CYAN      "\033[1;36m"
  45
  46 /* Trace BO layout (offsets are 4 bytes):
  47  *
  48  * [0]: primary trace ID
  49  * [1]: secondary trace ID
  50  * [2-3]: 64-bit GFX pipeline pointer
  51  * [4-5]: 64-bit COMPUTE pipeline pointer
  52  * [6-7]: 64-bit descriptor set #0 pointer
  53  * ...
  54  * [68-69]: 64-bit descriptor set #31 pointer
  55  */
  56
  57 bool
  58 radv_init_trace(struct radv_device *device)
  59 {
  60         struct radeon_winsys *ws = device->ws;
  61
  62         device->trace_bo = ws->buffer_create(ws, TRACE_BO_SIZE, 8,
  63                                              RADEON_DOMAIN_VRAM,
  64                                              RADEON_FLAG_CPU_ACCESS|
  65                                              RADEON_FLAG_NO_INTERPROCESS_SHARING,
  66                                              RADV_BO_PRIORITY_UPLOAD_BUFFER);
  67         if (!device->trace_bo)
  68                 return false;
  69
  70         device->trace_id_ptr = ws->buffer_map(device->trace_bo);
  71         if (!device->trace_id_ptr)
  72                 return false;
  73
  74         memset(device->trace_id_ptr, 0, TRACE_BO_SIZE);
  75
  76         ac_vm_fault_occured(device->physical_device->rad_info.chip_class,
  77                             &device->dmesg_timestamp, NULL);
  78
  79         return true;
  80 }
  81
  82 static void
  83 radv_dump_trace(struct radv_device *device, struct radeon_cmdbuf *cs)
  84 {
  85         const char *filename = getenv("RADV_TRACE_FILE");
  86         FILE *f = fopen(filename, "w");
  87
  88         if (!f) {
  89                 fprintf(stderr, "Failed to write trace dump to %s\n", filename);
  90                 return;
  91         }
  92
  93         fprintf(f, "Trace ID: %x\n", *device->trace_id_ptr);
  94         device->ws->cs_dump(cs, f, (const int*)device->trace_id_ptr, 2);
  95         fclose(f);
  96 }
  97
  98 static void
  99 radv_dump_mmapped_reg(struct radv_device *device, FILE *f, unsigned offset)
 100 {
 101         struct radeon_winsys *ws = device->ws;
 102         uint32_t value;
 103
 104         if (ws->read_registers(ws, offset, 1, &value))
 105                 ac_dump_reg(f, device->physical_device->rad_info.chip_class,
 106                             offset, value, ~0);
 107 }
 108
 109 static void
 110 radv_dump_debug_registers(struct radv_device *device, FILE *f)
 111 {
 112         struct radeon_info *info = &device->physical_device->rad_info;
 113
 114         fprintf(f, "Memory-mapped registers:\n");
 115         radv_dump_mmapped_reg(device, f, R_008010_GRBM_STATUS);
 116
 117         /* No other registers can be read on DRM < 3.1.0. */
 118         if (info->drm_minor < 1) {
 119                 fprintf(f, "\n");
 120                 return;
 121         }
 122
 123         radv_dump_mmapped_reg(device, f, R_008008_GRBM_STATUS2);
 124         radv_dump_mmapped_reg(device, f, R_008014_GRBM_STATUS_SE0);
 125         radv_dump_mmapped_reg(device, f, R_008018_GRBM_STATUS_SE1);
 126         radv_dump_mmapped_reg(device, f, R_008038_GRBM_STATUS_SE2);
 127         radv_dump_mmapped_reg(device, f, R_00803C_GRBM_STATUS_SE3);
 128         radv_dump_mmapped_reg(device, f, R_00D034_SDMA0_STATUS_REG);
 129         radv_dump_mmapped_reg(device, f, R_00D834_SDMA1_STATUS_REG);
 130         if (info->chip_class <= GFX8) {
 131                 radv_dump_mmapped_reg(device, f, R_000E50_SRBM_STATUS);
 132                 radv_dump_mmapped_reg(device, f, R_000E4C_SRBM_STATUS2);
 133                 radv_dump_mmapped_reg(device, f, R_000E54_SRBM_STATUS3);
 134         }
 135         radv_dump_mmapped_reg(device, f, R_008680_CP_STAT);
 136         radv_dump_mmapped_reg(device, f, R_008674_CP_STALLED_STAT1);
 137         radv_dump_mmapped_reg(device, f, R_008678_CP_STALLED_STAT2);
 138         radv_dump_mmapped_reg(device, f, R_008670_CP_STALLED_STAT3);
 139         radv_dump_mmapped_reg(device, f, R_008210_CP_CPC_STATUS);
 140         radv_dump_mmapped_reg(device, f, R_008214_CP_CPC_BUSY_STAT);
 141         radv_dump_mmapped_reg(device, f, R_008218_CP_CPC_STALLED_STAT1);
 142         radv_dump_mmapped_reg(device, f, R_00821C_CP_CPF_STATUS);
 143         radv_dump_mmapped_reg(device, f, R_008220_CP_CPF_BUSY_STAT);
 144         radv_dump_mmapped_reg(device, f, R_008224_CP_CPF_STALLED_STAT1);
 145         fprintf(f, "\n");
 146 }
 147
 148 static void
 149 radv_dump_buffer_descriptor(enum chip_class chip_class, const uint32_t *desc,
 150                             FILE *f)
 151 {
 152         fprintf(f, COLOR_CYAN "    Buffer:" COLOR_RESET "\n");
 153         for (unsigned j = 0; j < 4; j++)
 154                 ac_dump_reg(f, chip_class, R_008F00_SQ_BUF_RSRC_WORD0 + j * 4,
 155                             desc[j], 0xffffffff);
 156 }
 157
 158 static void
 159 radv_dump_image_descriptor(enum chip_class chip_class, const uint32_t *desc,
 160                            FILE *f)
 161 {
 162         unsigned sq_img_rsrc_word0 = chip_class >= GFX10 ? R_00A000_SQ_IMG_RSRC_WORD0
 163                                                          : R_008F10_SQ_IMG_RSRC_WORD0;
 164
 165         fprintf(f, COLOR_CYAN "    Image:" COLOR_RESET "\n");
 166         for (unsigned j = 0; j < 8; j++)
 167                 ac_dump_reg(f, chip_class, sq_img_rsrc_word0 + j * 4,
 168                             desc[j], 0xffffffff);
 169
 170         fprintf(f, COLOR_CYAN "    FMASK:" COLOR_RESET "\n");
 171         for (unsigned j = 0; j < 8; j++)
 172                 ac_dump_reg(f, chip_class, sq_img_rsrc_word0 + j * 4,
 173                             desc[8 + j], 0xffffffff);
 174 }
 175
 176 static void
 177 radv_dump_sampler_descriptor(enum chip_class chip_class, const uint32_t *desc,
 178                              FILE *f)
 179 {
 180         fprintf(f, COLOR_CYAN "    Sampler state:" COLOR_RESET "\n");
 181         for (unsigned j = 0; j < 4; j++) {
 182                 ac_dump_reg(f, chip_class, R_008F30_SQ_IMG_SAMP_WORD0 + j * 4,
 183                             desc[j], 0xffffffff);
 184         }
 185 }
 186
 187 static void
 188 radv_dump_combined_image_sampler_descriptor(enum chip_class chip_class,
 189                                             const uint32_t *desc, FILE *f)
 190 {
 191         radv_dump_image_descriptor(chip_class, desc, f);
 192         radv_dump_sampler_descriptor(chip_class, desc + 16, f);
 193 }
 194
 195 static void
 196 radv_dump_descriptor_set(enum chip_class chip_class,
 197                          struct radv_descriptor_set *set, unsigned id, FILE *f)
 198 {
 199         const struct radv_descriptor_set_layout *layout;
 200         int i;
 201
 202         if (!set)
 203                 return;
 204         layout = set->layout;
 205
 206         for (i = 0; i < set->layout->binding_count; i++) {
 207                 uint32_t *desc =
 208                         set->mapped_ptr + layout->binding[i].offset / 4;
 209
 210                 switch (layout->binding[i].type) {
 211                 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
 212                 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
 213                 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
 214                 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
 215                         radv_dump_buffer_descriptor(chip_class, desc, f);
 216                         break;
 217                 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
 218                 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
 219                 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
 220                         radv_dump_image_descriptor(chip_class, desc, f);
 221                         break;
 222                 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
 223                         radv_dump_combined_image_sampler_descriptor(chip_class, desc, f);
 224                         break;
 225                 case VK_DESCRIPTOR_TYPE_SAMPLER:
 226                         radv_dump_sampler_descriptor(chip_class, desc, f);
 227                         break;
 228                 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
 229                 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
 230                         /* todo */
 231                         break;
 232                 default:
 233                         assert(!"unknown descriptor type");
 234                         break;
 235                 }
 236                 fprintf(f, "\n");
 237         }
 238         fprintf(f, "\n\n");
 239 }
 240
 241 static void
 242 radv_dump_descriptors(struct radv_pipeline *pipeline, FILE *f)
 243 {
 244         struct radv_device *device = pipeline->device;
 245         enum chip_class chip_class = device->physical_device->rad_info.chip_class;
 246         uint64_t *ptr = (uint64_t *)device->trace_id_ptr;
 247         int i;
 248
 249         fprintf(f, "Descriptors:\n");
 250         for (i = 0; i < MAX_SETS; i++) {
 251                 struct radv_descriptor_set *set =
 252                         (struct radv_descriptor_set *)ptr[i + 3];
 253
 254                 radv_dump_descriptor_set(chip_class, set, i, f);
 255         }
 256 }
 257
 258 struct radv_shader_inst {
 259         char text[160];  /* one disasm line */
 260         unsigned offset; /* instruction offset */
 261         unsigned size;   /* instruction size = 4 or 8 */
 262 };
 263
 264 /* Split a disassembly string into lines and add them to the array pointed
 265  * to by "instructions". */
 266 static void si_add_split_disasm(const char *disasm,
 267                                 uint64_t start_addr,
 268                                 unsigned *num,
 269                                 struct radv_shader_inst *instructions)
 270 {
 271         struct radv_shader_inst *last_inst = *num ? &instructions[*num - 1] : NULL;
 272         char *next;
 273
 274         while ((next = strchr(disasm, '\n'))) {
 275                 struct radv_shader_inst *inst = &instructions[*num];
 276                 unsigned len = next - disasm;
 277
 278                 assert(len < ARRAY_SIZE(inst->text));
 279                 memcpy(inst->text, disasm, len);
 280                 inst->text[len] = 0;
 281                 inst->offset = last_inst ? last_inst->offset + last_inst->size : 0;
 282
 283                 const char *semicolon = strchr(disasm, ';');
 284                 assert(semicolon);
 285                 /* More than 16 chars after ";" means the instruction is 8 bytes long. */
 286                 inst->size = next - semicolon > 16 ? 8 : 4;
 287
 288                 snprintf(inst->text + len, ARRAY_SIZE(inst->text) - len,
 289                         " [PC=0x%"PRIx64", off=%u, size=%u]",
 290                         start_addr + inst->offset, inst->offset, inst->size);
 291
 292                 last_inst = inst;
 293                 (*num)++;
 294                 disasm = next + 1;
 295         }
 296 }
 297
 298 static void
 299 radv_dump_annotated_shader(struct radv_shader_variant *shader,
 300                            gl_shader_stage stage, struct ac_wave_info *waves,
 301                            unsigned num_waves, FILE *f)
 302 {
 303         uint64_t start_addr, end_addr;
 304         unsigned i;
 305
 306         if (!shader)
 307                 return;
 308
 309         start_addr = radv_buffer_get_va(shader->bo) + shader->bo_offset;
 310         end_addr = start_addr + shader->code_size;
 311
 312         /* See if any wave executes the shader. */
 313         for (i = 0; i < num_waves; i++) {
 314                 if (start_addr <= waves[i].pc && waves[i].pc <= end_addr)
 315                         break;
 316         }
 317
 318         if (i == num_waves)
 319                 return; /* the shader is not being executed */
 320
 321         /* Remember the first found wave. The waves are sorted according to PC. */
 322         waves = &waves[i];
 323         num_waves -= i;
 324
 325         /* Get the list of instructions.
 326          * Buffer size / 4 is the upper bound of the instruction count.
 327          */
 328         unsigned num_inst = 0;
 329         struct radv_shader_inst *instructions =
 330                 calloc(shader->code_size / 4, sizeof(struct radv_shader_inst));
 331
 332         si_add_split_disasm(shader->disasm_string,
 333                             start_addr, &num_inst, instructions);
 334
 335         fprintf(f, COLOR_YELLOW "%s - annotated disassembly:" COLOR_RESET "\n",
 336                 radv_get_shader_name(&shader->info, stage));
 337
 338         /* Print instructions with annotations. */
 339         for (i = 0; i < num_inst; i++) {
 340                 struct radv_shader_inst *inst = &instructions[i];
 341
 342                 fprintf(f, "%s\n", inst->text);
 343
 344                 /* Print which waves execute the instruction right now. */
 345                 while (num_waves && start_addr + inst->offset == waves->pc) {
 346                         fprintf(f,
 347                                 "          " COLOR_GREEN "^ SE%u SH%u CU%u "
 348                                 "SIMD%u WAVE%u  EXEC=%016"PRIx64 "  ",
 349                                 waves->se, waves->sh, waves->cu, waves->simd,
 350                                 waves->wave, waves->exec);
 351
 352                         if (inst->size == 4) {
 353                                 fprintf(f, "INST32=%08X" COLOR_RESET "\n",
 354                                         waves->inst_dw0);
 355                         } else {
 356                                 fprintf(f, "INST64=%08X %08X" COLOR_RESET "\n",
 357                                         waves->inst_dw0, waves->inst_dw1);
 358                         }
 359
 360                         waves->matched = true;
 361                         waves = &waves[1];
 362                         num_waves--;
 363                 }
 364         }
 365
 366         fprintf(f, "\n\n");
 367         free(instructions);
 368 }
 369
 370 static void
 371 radv_dump_annotated_shaders(struct radv_pipeline *pipeline,
 372                             VkShaderStageFlagBits active_stages, FILE *f)
 373 {
 374         struct ac_wave_info waves[AC_MAX_WAVES_PER_CHIP];
 375         enum chip_class chip_class = pipeline->device->physical_device->rad_info.chip_class;
 376         unsigned num_waves = ac_get_wave_info(chip_class, waves);
 377
 378         fprintf(f, COLOR_CYAN "The number of active waves = %u" COLOR_RESET
 379                 "\n\n", num_waves);
 380
 381         /* Dump annotated active graphics shaders. */
 382         while (active_stages) {
 383                 int stage = u_bit_scan(&active_stages);
 384
 385                 radv_dump_annotated_shader(pipeline->shaders[stage],
 386                                            stage, waves, num_waves, f);
 387         }
 388
 389         /* Print waves executing shaders that are not currently bound. */
 390         unsigned i;
 391         bool found = false;
 392         for (i = 0; i < num_waves; i++) {
 393                 if (waves[i].matched)
 394                         continue;
 395
 396                 if (!found) {
 397                         fprintf(f, COLOR_CYAN
 398                                 "Waves not executing currently-bound shaders:"
 399                                 COLOR_RESET "\n");
 400                         found = true;
 401                 }
 402                 fprintf(f, "    SE%u SH%u CU%u SIMD%u WAVE%u  EXEC=%016"PRIx64
 403                         "  INST=%08X %08X  PC=%"PRIx64"\n",
 404                         waves[i].se, waves[i].sh, waves[i].cu, waves[i].simd,
 405                         waves[i].wave, waves[i].exec, waves[i].inst_dw0,
 406                         waves[i].inst_dw1, waves[i].pc);
 407         }
 408         if (found)
 409                 fprintf(f, "\n\n");
 410 }
 411
 412 static void
 413 radv_dump_shader(struct radv_pipeline *pipeline,
 414                  struct radv_shader_variant *shader, gl_shader_stage stage,
 415                  FILE *f)
 416 {
 417         if (!shader)
 418                 return;
 419
 420         fprintf(f, "%s:\n\n", radv_get_shader_name(&shader->info, stage));
 421
 422         if (shader->spirv) {
 423                 unsigned char sha1[21];
 424                 char sha1buf[41];
 425
 426                 _mesa_sha1_compute(shader->spirv, shader->spirv_size, sha1);
 427                 _mesa_sha1_format(sha1buf, sha1);
 428
 429                 fprintf(f, "SPIRV (sha1: %s):\n", sha1buf);
 430                 radv_print_spirv(shader->spirv, shader->spirv_size, f);
 431         }
 432
 433         if (shader->nir_string) {
 434                 fprintf(f, "NIR:\n%s\n", shader->nir_string);
 435         }
 436
 437         fprintf(f, "LLVM IR:\n%s\n", shader->ir_string);
 438         fprintf(f, "DISASM:\n%s\n", shader->disasm_string);
 439
 440         radv_shader_dump_stats(pipeline->device, shader, stage, f);
 441 }
 442
 443 static void
 444 radv_dump_shaders(struct radv_pipeline *pipeline,
 445                   VkShaderStageFlagBits active_stages, FILE *f)
 446 {
 447         /* Dump active graphics shaders. */
 448         while (active_stages) {
 449                 int stage = u_bit_scan(&active_stages);
 450
 451                 radv_dump_shader(pipeline, pipeline->shaders[stage], stage, f);
 452         }
 453 }
 454
 455 static void
 456 radv_dump_pipeline_state(struct radv_pipeline *pipeline,
 457                          VkShaderStageFlagBits active_stages, FILE *f)
 458 {
 459         radv_dump_shaders(pipeline, active_stages, f);
 460         radv_dump_annotated_shaders(pipeline, active_stages, f);
 461         radv_dump_descriptors(pipeline, f);
 462 }
 463
 464 static void
 465 radv_dump_graphics_state(struct radv_pipeline *graphics_pipeline,
 466                          struct radv_pipeline *compute_pipeline, FILE *f)
 467 {
 468         VkShaderStageFlagBits active_stages;
 469
 470         if (graphics_pipeline) {
 471                 active_stages = graphics_pipeline->active_stages;
 472                 radv_dump_pipeline_state(graphics_pipeline, active_stages, f);
 473         }
 474
 475         if (compute_pipeline) {
 476                 active_stages = VK_SHADER_STAGE_COMPUTE_BIT;
 477                 radv_dump_pipeline_state(compute_pipeline, active_stages, f);
 478         }
 479 }
 480
 481 static void
 482 radv_dump_compute_state(struct radv_pipeline *compute_pipeline, FILE *f)
 483 {
 484         VkShaderStageFlagBits active_stages = VK_SHADER_STAGE_COMPUTE_BIT;
 485
 486         if (!compute_pipeline)
 487                 return;
 488
 489         radv_dump_pipeline_state(compute_pipeline, active_stages, f);
 490 }
 491
 492 static struct radv_pipeline *
 493 radv_get_saved_graphics_pipeline(struct radv_device *device)
 494 {
 495         uint64_t *ptr = (uint64_t *)device->trace_id_ptr;
 496
 497         return (struct radv_pipeline *)ptr[1];
 498 }
 499
 500 static struct radv_pipeline *
 501 radv_get_saved_compute_pipeline(struct radv_device *device)
 502 {
 503         uint64_t *ptr = (uint64_t *)device->trace_id_ptr;
 504
 505         return (struct radv_pipeline *)ptr[2];
 506 }
 507
 508 static void
 509 radv_dump_dmesg(FILE *f)
 510 {
 511         char line[2000];
 512         FILE *p;
 513
 514         p = popen("dmesg | tail -n60", "r");
 515         if (!p)
 516                 return;
 517
 518         fprintf(f, "\nLast 60 lines of dmesg:\n\n");
 519         while (fgets(line, sizeof(line), p))
 520                 fputs(line, f);
 521         fprintf(f, "\n");
 522
 523         pclose(p);
 524 }
 525
 526 void
 527 radv_dump_enabled_options(struct radv_device *device, FILE *f)
 528 {
 529         uint64_t mask;
 530
 531         if (device->instance->debug_flags) {
 532                 fprintf(f, "Enabled debug options: ");
 533
 534                 mask = device->instance->debug_flags;
 535                 while (mask) {
 536                         int i = u_bit_scan64(&mask);
 537                         fprintf(f, "%s, ", radv_get_debug_option_name(i));
 538                 }
 539                 fprintf(f, "\n");
 540         }
 541
 542         if (device->instance->perftest_flags) {
 543                 fprintf(f, "Enabled perftest options: ");
 544
 545                 mask = device->instance->perftest_flags;
 546                 while (mask) {
 547                         int i = u_bit_scan64(&mask);
 548                         fprintf(f, "%s, ", radv_get_perftest_option_name(i));
 549                 }
 550                 fprintf(f, "\n");
 551         }
 552 }
 553
 554 static void
 555 radv_dump_device_name(struct radv_device *device, FILE *f)
 556 {
 557         struct radeon_info *info = &device->physical_device->rad_info;
 558         char kernel_version[128] = {};
 559         struct utsname uname_data;
 560         const char *chip_name;
 561
 562         chip_name = device->ws->get_chip_name(device->ws);
 563
 564         if (uname(&uname_data) == 0)
 565                 snprintf(kernel_version, sizeof(kernel_version),
 566                          " / %s", uname_data.release);
 567
 568         fprintf(f, "Device name: %s (%s DRM %i.%i.%i%s, LLVM "
 569                 MESA_LLVM_VERSION_STRING ")\n\n",
 570                 chip_name, device->physical_device->name,
 571                 info->drm_major, info->drm_minor, info->drm_patchlevel,
 572                 kernel_version);
 573 }
 574
 575 static bool
 576 radv_gpu_hang_occured(struct radv_queue *queue, enum ring_type ring)
 577 {
 578         struct radeon_winsys *ws = queue->device->ws;
 579
 580         if (!ws->ctx_wait_idle(queue->hw_ctx, ring, queue->queue_idx))
 581                 return true;
 582
 583         return false;
 584 }
 585
 586 void
 587 radv_check_gpu_hangs(struct radv_queue *queue, struct radeon_cmdbuf *cs)
 588 {
 589         struct radv_pipeline *graphics_pipeline, *compute_pipeline;
 590         struct radv_device *device = queue->device;
 591         enum ring_type ring;
 592         uint64_t addr;
 593
 594         ring = radv_queue_family_to_ring(queue->queue_family_index);
 595
 596         bool hang_occurred = radv_gpu_hang_occured(queue, ring);
 597         bool vm_fault_occurred = false;
 598         if (queue->device->instance->debug_flags & RADV_DEBUG_VM_FAULTS)
 599                 vm_fault_occurred = ac_vm_fault_occured(device->physical_device->rad_info.chip_class,
 600                                                         &device->dmesg_timestamp, &addr);
 601         if (!hang_occurred && !vm_fault_occurred)
 602                 return;
 603
 604         graphics_pipeline = radv_get_saved_graphics_pipeline(device);
 605         compute_pipeline = radv_get_saved_compute_pipeline(device);
 606
 607         radv_dump_trace(queue->device, cs);
 608
 609         fprintf(stderr, "GPU hang report:\n\n");
 610         radv_dump_device_name(device, stderr);
 611
 612         radv_dump_enabled_options(device, stderr);
 613         radv_dump_dmesg(stderr);
 614
 615         if (vm_fault_occurred) {
 616                 fprintf(stderr, "VM fault report.\n\n");
 617                 fprintf(stderr, "Failing VM page: 0x%08"PRIx64"\n\n", addr);
 618         }
 619
 620         radv_dump_debug_registers(device, stderr);
 621
 622         switch (ring) {
 623         case RING_GFX:
 624                 fprintf(stderr, "RING_GFX:\n");
 625                 radv_dump_graphics_state(graphics_pipeline, compute_pipeline,
 626                                          stderr);
 627                 break;
 628         case RING_COMPUTE:
 629                 fprintf(stderr, "RING_COMPUTE:\n");
 630                 radv_dump_compute_state(compute_pipeline, stderr);
 631                 break;
 632         default:
 633                 assert(0);
 634                 break;
 635         }
 636
 637         abort();
 638 }
 639
 640 void
 641 radv_print_spirv(uint32_t *data, uint32_t size, FILE *fp)
 642 {
 643         char path[] = "/tmp/fileXXXXXX";
 644         char line[2048], command[128];
 645         FILE *p;
 646         int fd;
 647
 648         /* Dump the binary into a temporary file. */
 649         fd = mkstemp(path);
 650         if (fd < 0)
 651                 return;
 652
 653         if (write(fd, data, size) == -1)
 654                 goto fail;
 655
 656         sprintf(command, "spirv-dis %s", path);
 657
 658         /* Disassemble using spirv-dis if installed. */
 659         p = popen(command, "r");
 660         if (p) {
 661                 while (fgets(line, sizeof(line), p))
 662                         fprintf(fp, "%s", line);
 663                 pclose(p);
 664         }
 665
 666 fail:
 667         close(fd);
 668         unlink(path);
 669 }