2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include <sys/utsname.h>
32 #include "util/mesa-sha1.h"
36 #include "radv_debug.h"
37 #include "radv_shader.h"
39 #define TRACE_BO_SIZE 4096
41 #define COLOR_RESET "\033[0m"
42 #define COLOR_RED "\033[31m"
43 #define COLOR_GREEN "\033[1;32m"
44 #define COLOR_YELLOW "\033[1;33m"
45 #define COLOR_CYAN "\033[1;36m"
47 /* Trace BO layout (offsets are 4 bytes):
49 * [0]: primary trace ID
50 * [1]: secondary trace ID
51 * [2-3]: 64-bit GFX pipeline pointer
52 * [4-5]: 64-bit COMPUTE pipeline pointer
53 * [6-7]: 64-bit descriptor set #0 pointer
55 * [68-69]: 64-bit descriptor set #31 pointer
59 radv_init_trace(struct radv_device
*device
)
61 struct radeon_winsys
*ws
= device
->ws
;
63 device
->trace_bo
= ws
->buffer_create(ws
, TRACE_BO_SIZE
, 8,
65 RADEON_FLAG_CPU_ACCESS
|
66 RADEON_FLAG_NO_INTERPROCESS_SHARING
);
67 if (!device
->trace_bo
)
70 device
->trace_id_ptr
= ws
->buffer_map(device
->trace_bo
);
71 if (!device
->trace_id_ptr
)
74 memset(device
->trace_id_ptr
, 0, TRACE_BO_SIZE
);
76 ac_vm_fault_occured(device
->physical_device
->rad_info
.chip_class
,
77 &device
->dmesg_timestamp
, NULL
);
83 radv_dump_trace(struct radv_device
*device
, struct radeon_winsys_cs
*cs
)
85 const char *filename
= getenv("RADV_TRACE_FILE");
86 FILE *f
= fopen(filename
, "w");
89 fprintf(stderr
, "Failed to write trace dump to %s\n", filename
);
93 fprintf(f
, "Trace ID: %x\n", *device
->trace_id_ptr
);
94 device
->ws
->cs_dump(cs
, f
, (const int*)device
->trace_id_ptr
, 2);
99 radv_dump_mmapped_reg(struct radv_device
*device
, FILE *f
, unsigned offset
)
101 struct radeon_winsys
*ws
= device
->ws
;
104 if (ws
->read_registers(ws
, offset
, 1, &value
))
105 ac_dump_reg(f
, device
->physical_device
->rad_info
.chip_class
,
110 radv_dump_debug_registers(struct radv_device
*device
, FILE *f
)
112 struct radeon_info
*info
= &device
->physical_device
->rad_info
;
114 if (info
->drm_major
== 2 && info
->drm_minor
< 42)
115 return; /* no radeon support */
117 fprintf(f
, "Memory-mapped registers:\n");
118 radv_dump_mmapped_reg(device
, f
, R_008010_GRBM_STATUS
);
120 /* No other registers can be read on DRM < 3.1.0. */
121 if (info
->drm_major
< 3 || info
->drm_minor
< 1) {
126 radv_dump_mmapped_reg(device
, f
, R_008008_GRBM_STATUS2
);
127 radv_dump_mmapped_reg(device
, f
, R_008014_GRBM_STATUS_SE0
);
128 radv_dump_mmapped_reg(device
, f
, R_008018_GRBM_STATUS_SE1
);
129 radv_dump_mmapped_reg(device
, f
, R_008038_GRBM_STATUS_SE2
);
130 radv_dump_mmapped_reg(device
, f
, R_00803C_GRBM_STATUS_SE3
);
131 radv_dump_mmapped_reg(device
, f
, R_00D034_SDMA0_STATUS_REG
);
132 radv_dump_mmapped_reg(device
, f
, R_00D834_SDMA1_STATUS_REG
);
133 if (info
->chip_class
<= VI
) {
134 radv_dump_mmapped_reg(device
, f
, R_000E50_SRBM_STATUS
);
135 radv_dump_mmapped_reg(device
, f
, R_000E4C_SRBM_STATUS2
);
136 radv_dump_mmapped_reg(device
, f
, R_000E54_SRBM_STATUS3
);
138 radv_dump_mmapped_reg(device
, f
, R_008680_CP_STAT
);
139 radv_dump_mmapped_reg(device
, f
, R_008674_CP_STALLED_STAT1
);
140 radv_dump_mmapped_reg(device
, f
, R_008678_CP_STALLED_STAT2
);
141 radv_dump_mmapped_reg(device
, f
, R_008670_CP_STALLED_STAT3
);
142 radv_dump_mmapped_reg(device
, f
, R_008210_CP_CPC_STATUS
);
143 radv_dump_mmapped_reg(device
, f
, R_008214_CP_CPC_BUSY_STAT
);
144 radv_dump_mmapped_reg(device
, f
, R_008218_CP_CPC_STALLED_STAT1
);
145 radv_dump_mmapped_reg(device
, f
, R_00821C_CP_CPF_STATUS
);
146 radv_dump_mmapped_reg(device
, f
, R_008220_CP_CPF_BUSY_STAT
);
147 radv_dump_mmapped_reg(device
, f
, R_008224_CP_CPF_STALLED_STAT1
);
152 radv_get_descriptor_name(enum VkDescriptorType type
)
155 case VK_DESCRIPTOR_TYPE_SAMPLER
:
157 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
158 return "COMBINED_IMAGE_SAMPLER";
159 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
:
160 return "SAMPLED_IMAGE";
161 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
:
162 return "STORAGE_IMAGE";
163 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
164 return "UNIFORM_TEXEL_BUFFER";
165 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
166 return "STORAGE_TEXEL_BUFFER";
167 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
168 return "UNIFORM_BUFFER";
169 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
170 return "STORAGE_BUFFER";
171 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
172 return "UNIFORM_BUFFER_DYNAMIC";
173 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
:
174 return "STORAGE_BUFFER_DYNAMIC";
175 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
176 return "INPUT_ATTACHMENT";
183 radv_dump_buffer_descriptor(enum chip_class chip_class
, const uint32_t *desc
,
186 fprintf(f
, COLOR_CYAN
" Buffer:" COLOR_RESET
"\n");
187 for (unsigned j
= 0; j
< 4; j
++)
188 ac_dump_reg(f
, chip_class
, R_008F00_SQ_BUF_RSRC_WORD0
+ j
* 4,
189 desc
[j
], 0xffffffff);
193 radv_dump_image_descriptor(enum chip_class chip_class
, const uint32_t *desc
,
196 fprintf(f
, COLOR_CYAN
" Image:" COLOR_RESET
"\n");
197 for (unsigned j
= 0; j
< 8; j
++)
198 ac_dump_reg(f
, chip_class
, R_008F10_SQ_IMG_RSRC_WORD0
+ j
* 4,
199 desc
[j
], 0xffffffff);
201 fprintf(f
, COLOR_CYAN
" FMASK:" COLOR_RESET
"\n");
202 for (unsigned j
= 0; j
< 8; j
++)
203 ac_dump_reg(f
, chip_class
, R_008F10_SQ_IMG_RSRC_WORD0
+ j
* 4,
204 desc
[8 + j
], 0xffffffff);
208 radv_dump_sampler_descriptor(enum chip_class chip_class
, const uint32_t *desc
,
211 fprintf(f
, COLOR_CYAN
" Sampler state:" COLOR_RESET
"\n");
212 for (unsigned j
= 0; j
< 4; j
++) {
213 ac_dump_reg(f
, chip_class
, R_008F30_SQ_IMG_SAMP_WORD0
+ j
* 4,
214 desc
[j
], 0xffffffff);
219 radv_dump_combined_image_sampler_descriptor(enum chip_class chip_class
,
220 const uint32_t *desc
, FILE *f
)
222 radv_dump_image_descriptor(chip_class
, desc
, f
);
223 radv_dump_sampler_descriptor(chip_class
, desc
+ 16, f
);
227 radv_dump_descriptor_set(enum chip_class chip_class
,
228 struct radv_descriptor_set
*set
, unsigned id
, FILE *f
)
230 const struct radv_descriptor_set_layout
*layout
;
235 layout
= set
->layout
;
237 fprintf(f
, "** descriptor set (%d) **\n", id
);
238 fprintf(f
, "va: 0x%"PRIx64
"\n", set
->va
);
239 fprintf(f
, "size: %d\n", set
->size
);
240 fprintf(f
, "mapped_ptr:\n");
242 for (i
= 0; i
< set
->size
/ 4; i
++) {
243 fprintf(f
, "\t[0x%x] = 0x%08x\n", i
, set
->mapped_ptr
[i
]);
247 fprintf(f
, "\t*** layout ***\n");
248 fprintf(f
, "\tbinding_count: %d\n", layout
->binding_count
);
249 fprintf(f
, "\tsize: %d\n", layout
->size
);
250 fprintf(f
, "\tshader_stages: %x\n", layout
->shader_stages
);
251 fprintf(f
, "\tdynamic_shader_stages: %x\n",
252 layout
->dynamic_shader_stages
);
253 fprintf(f
, "\tbuffer_count: %d\n", layout
->buffer_count
);
254 fprintf(f
, "\tdynamic_offset_count: %d\n",
255 layout
->dynamic_offset_count
);
258 for (i
= 0; i
< set
->layout
->binding_count
; i
++) {
260 set
->mapped_ptr
+ layout
->binding
[i
].offset
/ 4;
262 fprintf(f
, "\t\t**** binding layout (%d) ****\n", i
);
263 fprintf(f
, "\t\ttype: %s\n",
264 radv_get_descriptor_name(layout
->binding
[i
].type
));
265 fprintf(f
, "\t\tarray_size: %d\n",
266 layout
->binding
[i
].array_size
);
267 fprintf(f
, "\t\toffset: %d\n",
268 layout
->binding
[i
].offset
);
269 fprintf(f
, "\t\tbuffer_offset: %d\n",
270 layout
->binding
[i
].buffer_offset
);
271 fprintf(f
, "\t\tdynamic_offset_offset: %d\n",
272 layout
->binding
[i
].dynamic_offset_offset
);
273 fprintf(f
, "\t\tdynamic_offset_count: %d\n",
274 layout
->binding
[i
].dynamic_offset_count
);
275 fprintf(f
, "\t\tsize: %d\n",
276 layout
->binding
[i
].size
);
277 fprintf(f
, "\t\timmutable_samplers_offset: %d\n",
278 layout
->binding
[i
].immutable_samplers_offset
);
279 fprintf(f
, "\t\timmutable_samplers_equal: %d\n",
280 layout
->binding
[i
].immutable_samplers_equal
);
283 switch (layout
->binding
[i
].type
) {
284 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
285 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
286 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
287 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
288 radv_dump_buffer_descriptor(chip_class
, desc
, f
);
290 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
:
291 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
:
292 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
293 radv_dump_image_descriptor(chip_class
, desc
, f
);
295 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
296 radv_dump_combined_image_sampler_descriptor(chip_class
, desc
, f
);
298 case VK_DESCRIPTOR_TYPE_SAMPLER
:
299 radv_dump_sampler_descriptor(chip_class
, desc
, f
);
301 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
302 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
:
306 assert(!"unknown descriptor type");
315 radv_dump_descriptors(struct radv_pipeline
*pipeline
, FILE *f
)
317 struct radv_device
*device
= pipeline
->device
;
318 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
319 uint64_t *ptr
= (uint64_t *)device
->trace_id_ptr
;
322 fprintf(f
, "List of descriptors:\n");
323 for (i
= 0; i
< MAX_SETS
; i
++) {
324 struct radv_descriptor_set
*set
=
325 (struct radv_descriptor_set
*)ptr
[i
+ 3];
327 radv_dump_descriptor_set(chip_class
, set
, i
, f
);
331 struct radv_shader_inst
{
332 char text
[160]; /* one disasm line */
333 unsigned offset
; /* instruction offset */
334 unsigned size
; /* instruction size = 4 or 8 */
337 /* Split a disassembly string into lines and add them to the array pointed
338 * to by "instructions". */
339 static void si_add_split_disasm(const char *disasm
,
342 struct radv_shader_inst
*instructions
)
344 struct radv_shader_inst
*last_inst
= *num
? &instructions
[*num
- 1] : NULL
;
347 while ((next
= strchr(disasm
, '\n'))) {
348 struct radv_shader_inst
*inst
= &instructions
[*num
];
349 unsigned len
= next
- disasm
;
351 assert(len
< ARRAY_SIZE(inst
->text
));
352 memcpy(inst
->text
, disasm
, len
);
354 inst
->offset
= last_inst
? last_inst
->offset
+ last_inst
->size
: 0;
356 const char *semicolon
= strchr(disasm
, ';');
358 /* More than 16 chars after ";" means the instruction is 8 bytes long. */
359 inst
->size
= next
- semicolon
> 16 ? 8 : 4;
361 snprintf(inst
->text
+ len
, ARRAY_SIZE(inst
->text
) - len
,
362 " [PC=0x%"PRIx64
", off=%u, size=%u]",
363 start_addr
+ inst
->offset
, inst
->offset
, inst
->size
);
372 radv_dump_annotated_shader(struct radv_pipeline
*pipeline
,
373 struct radv_shader_variant
*shader
,
374 gl_shader_stage stage
,
375 struct ac_wave_info
*waves
, unsigned num_waves
,
378 uint64_t start_addr
, end_addr
;
384 start_addr
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
385 end_addr
= start_addr
+ shader
->code_size
;
387 /* See if any wave executes the shader. */
388 for (i
= 0; i
< num_waves
; i
++) {
389 if (start_addr
<= waves
[i
].pc
&& waves
[i
].pc
<= end_addr
)
394 return; /* the shader is not being executed */
396 /* Remember the first found wave. The waves are sorted according to PC. */
400 /* Get the list of instructions.
401 * Buffer size / 4 is the upper bound of the instruction count.
403 unsigned num_inst
= 0;
404 struct radv_shader_inst
*instructions
=
405 calloc(shader
->code_size
/ 4, sizeof(struct radv_shader_inst
));
407 si_add_split_disasm(shader
->disasm_string
,
408 start_addr
, &num_inst
, instructions
);
410 fprintf(f
, COLOR_YELLOW
"%s - annotated disassembly:" COLOR_RESET
"\n",
411 radv_get_shader_name(shader
, stage
));
413 /* Print instructions with annotations. */
414 for (i
= 0; i
< num_inst
; i
++) {
415 struct radv_shader_inst
*inst
= &instructions
[i
];
417 fprintf(f
, "%s\n", inst
->text
);
419 /* Print which waves execute the instruction right now. */
420 while (num_waves
&& start_addr
+ inst
->offset
== waves
->pc
) {
422 " " COLOR_GREEN
"^ SE%u SH%u CU%u "
423 "SIMD%u WAVE%u EXEC=%016"PRIx64
" ",
424 waves
->se
, waves
->sh
, waves
->cu
, waves
->simd
,
425 waves
->wave
, waves
->exec
);
427 if (inst
->size
== 4) {
428 fprintf(f
, "INST32=%08X" COLOR_RESET
"\n",
431 fprintf(f
, "INST64=%08X %08X" COLOR_RESET
"\n",
432 waves
->inst_dw0
, waves
->inst_dw1
);
435 waves
->matched
= true;
446 radv_dump_annotated_shaders(struct radv_pipeline
*pipeline
,
447 struct radv_shader_variant
*compute_shader
,
450 struct ac_wave_info waves
[AC_MAX_WAVES_PER_CHIP
];
451 unsigned num_waves
= ac_get_wave_info(waves
);
454 fprintf(f
, COLOR_CYAN
"The number of active waves = %u" COLOR_RESET
457 /* Dump annotated active graphics shaders. */
458 mask
= pipeline
->active_stages
;
460 int stage
= u_bit_scan(&mask
);
462 radv_dump_annotated_shader(pipeline
, pipeline
->shaders
[stage
],
463 stage
, waves
, num_waves
, f
);
466 radv_dump_annotated_shader(pipeline
, compute_shader
,
467 MESA_SHADER_COMPUTE
, waves
, num_waves
, f
);
469 /* Print waves executing shaders that are not currently bound. */
472 for (i
= 0; i
< num_waves
; i
++) {
473 if (waves
[i
].matched
)
477 fprintf(f
, COLOR_CYAN
478 "Waves not executing currently-bound shaders:"
482 fprintf(f
, " SE%u SH%u CU%u SIMD%u WAVE%u EXEC=%016"PRIx64
483 " INST=%08X %08X PC=%"PRIx64
"\n",
484 waves
[i
].se
, waves
[i
].sh
, waves
[i
].cu
, waves
[i
].simd
,
485 waves
[i
].wave
, waves
[i
].exec
, waves
[i
].inst_dw0
,
486 waves
[i
].inst_dw1
, waves
[i
].pc
);
493 radv_dump_shader(struct radv_pipeline
*pipeline
,
494 struct radv_shader_variant
*shader
, gl_shader_stage stage
,
500 fprintf(f
, "%s:\n\n", radv_get_shader_name(shader
, stage
));
503 unsigned char sha1
[21];
506 _mesa_sha1_compute(shader
->spirv
, shader
->spirv_size
, sha1
);
507 _mesa_sha1_format(sha1buf
, sha1
);
509 fprintf(f
, "SPIRV (sha1: %s):\n", sha1buf
);
510 radv_print_spirv(shader
->spirv
, shader
->spirv_size
, f
);
514 fprintf(f
, "NIR:\n");
515 nir_print_shader(shader
->nir
, f
);
518 fprintf(f
, "LLVM IR:\n%s\n", shader
->llvm_ir_string
);
519 fprintf(f
, "DISASM:\n%s\n", shader
->disasm_string
);
521 radv_shader_dump_stats(pipeline
->device
, shader
, stage
, f
);
525 radv_dump_shaders(struct radv_pipeline
*pipeline
,
526 struct radv_shader_variant
*compute_shader
, FILE *f
)
530 /* Dump active graphics shaders. */
531 mask
= pipeline
->active_stages
;
533 int stage
= u_bit_scan(&mask
);
535 radv_dump_shader(pipeline
, pipeline
->shaders
[stage
], stage
, f
);
538 radv_dump_shader(pipeline
, compute_shader
, MESA_SHADER_COMPUTE
, f
);
542 radv_dump_graphics_state(struct radv_pipeline
*graphics_pipeline
,
543 struct radv_pipeline
*compute_pipeline
, FILE *f
)
545 struct radv_shader_variant
*compute_shader
=
546 compute_pipeline
? compute_pipeline
->shaders
[MESA_SHADER_COMPUTE
] : NULL
;
548 if (!graphics_pipeline
)
551 radv_dump_shaders(graphics_pipeline
, compute_shader
, f
);
552 radv_dump_annotated_shaders(graphics_pipeline
, compute_shader
, f
);
553 radv_dump_descriptors(graphics_pipeline
, f
);
557 radv_dump_compute_state(struct radv_pipeline
*compute_pipeline
, FILE *f
)
559 if (!compute_pipeline
)
562 radv_dump_shaders(compute_pipeline
,
563 compute_pipeline
->shaders
[MESA_SHADER_COMPUTE
], f
);
564 radv_dump_annotated_shaders(compute_pipeline
,
565 compute_pipeline
->shaders
[MESA_SHADER_COMPUTE
],
567 radv_dump_descriptors(compute_pipeline
, f
);
570 static struct radv_pipeline
*
571 radv_get_saved_graphics_pipeline(struct radv_device
*device
)
573 uint64_t *ptr
= (uint64_t *)device
->trace_id_ptr
;
575 return (struct radv_pipeline
*)ptr
[1];
578 static struct radv_pipeline
*
579 radv_get_saved_compute_pipeline(struct radv_device
*device
)
581 uint64_t *ptr
= (uint64_t *)device
->trace_id_ptr
;
583 return (struct radv_pipeline
*)ptr
[2];
587 radv_dump_dmesg(FILE *f
)
592 p
= popen("dmesg | tail -n60", "r");
596 fprintf(f
, "\nLast 60 lines of dmesg:\n\n");
597 while (fgets(line
, sizeof(line
), p
))
605 radv_dump_enabled_options(struct radv_device
*device
, FILE *f
)
609 if (device
->instance
->debug_flags
) {
610 fprintf(f
, "Enabled debug options: ");
612 mask
= device
->instance
->debug_flags
;
614 int i
= u_bit_scan64(&mask
);
615 fprintf(f
, "%s, ", radv_get_debug_option_name(i
));
620 if (device
->instance
->perftest_flags
) {
621 fprintf(f
, "Enabled perftest options: ");
623 mask
= device
->instance
->perftest_flags
;
625 int i
= u_bit_scan64(&mask
);
626 fprintf(f
, "%s, ", radv_get_perftest_option_name(i
));
633 radv_dump_device_name(struct radv_device
*device
, FILE *f
)
635 struct radeon_info
*info
= &device
->physical_device
->rad_info
;
636 char llvm_string
[32] = {}, kernel_version
[128] = {};
637 struct utsname uname_data
;
638 const char *chip_name
;
640 chip_name
= device
->ws
->get_chip_name(device
->ws
);
642 if (uname(&uname_data
) == 0)
643 snprintf(kernel_version
, sizeof(kernel_version
),
644 " / %s", uname_data
.release
);
646 snprintf(llvm_string
, sizeof(llvm_string
),
647 ", LLVM %i.%i.%i", (HAVE_LLVM
>> 8) & 0xff,
648 HAVE_LLVM
& 0xff, MESA_LLVM_VERSION_PATCH
);
650 fprintf(f
, "Device name: %s (%s DRM %i.%i.%i%s%s)\n\n",
651 chip_name
, device
->physical_device
->name
,
652 info
->drm_major
, info
->drm_minor
, info
->drm_patchlevel
,
653 kernel_version
, llvm_string
);
657 radv_gpu_hang_occured(struct radv_queue
*queue
, enum ring_type ring
)
659 struct radeon_winsys
*ws
= queue
->device
->ws
;
661 if (!ws
->ctx_wait_idle(queue
->hw_ctx
, ring
, queue
->queue_idx
))
668 radv_check_gpu_hangs(struct radv_queue
*queue
, struct radeon_winsys_cs
*cs
)
670 struct radv_pipeline
*graphics_pipeline
, *compute_pipeline
;
671 struct radv_device
*device
= queue
->device
;
675 ring
= radv_queue_family_to_ring(queue
->queue_family_index
);
677 bool hang_occurred
= radv_gpu_hang_occured(queue
, ring
);
678 bool vm_fault_occurred
= false;
679 if (queue
->device
->instance
->debug_flags
& RADV_DEBUG_VM_FAULTS
)
680 vm_fault_occurred
= ac_vm_fault_occured(device
->physical_device
->rad_info
.chip_class
,
681 &device
->dmesg_timestamp
, &addr
);
682 if (!hang_occurred
&& !vm_fault_occurred
)
685 graphics_pipeline
= radv_get_saved_graphics_pipeline(device
);
686 compute_pipeline
= radv_get_saved_compute_pipeline(device
);
688 fprintf(stderr
, "GPU hang report:\n\n");
689 radv_dump_device_name(device
, stderr
);
691 radv_dump_enabled_options(device
, stderr
);
692 radv_dump_dmesg(stderr
);
694 if (vm_fault_occurred
) {
695 fprintf(stderr
, "VM fault report.\n\n");
696 fprintf(stderr
, "Failing VM page: 0x%08"PRIx64
"\n\n", addr
);
699 radv_dump_debug_registers(device
, stderr
);
703 radv_dump_graphics_state(graphics_pipeline
, compute_pipeline
,
707 radv_dump_compute_state(compute_pipeline
, stderr
);
714 radv_dump_trace(queue
->device
, cs
);
719 radv_print_spirv(uint32_t *data
, uint32_t size
, FILE *fp
)
721 char path
[] = "/tmp/fileXXXXXX";
722 char line
[2048], command
[128];
726 /* Dump the binary into a temporary file. */
731 if (write(fd
, data
, size
) == -1)
734 sprintf(command
, "spirv-dis %s", path
);
736 /* Disassemble using spirv-dis if installed. */
737 p
= popen(command
, "r");
739 while (fgets(line
, sizeof(line
), p
))
740 fprintf(fp
, "%s", line
);