2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include <linux/audit.h>
32 #include <linux/bpf.h>
33 #include <linux/filter.h>
34 #include <linux/seccomp.h>
35 #include <linux/unistd.h>
40 #include <sys/prctl.h>
45 #include "radv_debug.h"
46 #include "radv_private.h"
47 #include "radv_shader.h"
49 #include "util/disk_cache.h"
53 #include <amdgpu_drm.h>
54 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
55 #include "winsys/null/radv_null_winsys_public.h"
56 #include "ac_llvm_util.h"
57 #include "vk_format.h"
60 #include "util/build_id.h"
61 #include "util/debug.h"
62 #include "util/mesa-sha1.h"
63 #include "util/timespec.h"
64 #include "util/u_atomic.h"
65 #include "compiler/glsl_types.h"
66 #include "util/xmlpool.h"
68 static struct radv_timeline_point
*
69 radv_timeline_find_point_at_least_locked(struct radv_device
*device
,
70 struct radv_timeline
*timeline
,
73 static struct radv_timeline_point
*
74 radv_timeline_add_point_locked(struct radv_device
*device
,
75 struct radv_timeline
*timeline
,
79 radv_timeline_trigger_waiters_locked(struct radv_timeline
*timeline
,
80 struct list_head
*processing_list
);
83 void radv_destroy_semaphore_part(struct radv_device
*device
,
84 struct radv_semaphore_part
*part
);
87 radv_device_get_cache_uuid(enum radeon_family family
, void *uuid
)
90 unsigned char sha1
[20];
91 unsigned ptr_size
= sizeof(void*);
93 memset(uuid
, 0, VK_UUID_SIZE
);
94 _mesa_sha1_init(&ctx
);
96 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid
, &ctx
) ||
97 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo
, &ctx
))
100 _mesa_sha1_update(&ctx
, &family
, sizeof(family
));
101 _mesa_sha1_update(&ctx
, &ptr_size
, sizeof(ptr_size
));
102 _mesa_sha1_final(&ctx
, sha1
);
104 memcpy(uuid
, sha1
, VK_UUID_SIZE
);
109 radv_get_driver_uuid(void *uuid
)
111 ac_compute_driver_uuid(uuid
, VK_UUID_SIZE
);
115 radv_get_device_uuid(struct radeon_info
*info
, void *uuid
)
117 ac_compute_device_uuid(info
, uuid
, VK_UUID_SIZE
);
121 radv_get_visible_vram_size(struct radv_physical_device
*device
)
123 return MIN2(device
->rad_info
.vram_size
, device
->rad_info
.vram_vis_size
);
127 radv_get_vram_size(struct radv_physical_device
*device
)
129 return device
->rad_info
.vram_size
- radv_get_visible_vram_size(device
);
133 radv_is_mem_type_vram(enum radv_mem_type type
)
135 return type
== RADV_MEM_TYPE_VRAM
||
136 type
== RADV_MEM_TYPE_VRAM_UNCACHED
;
140 radv_is_mem_type_vram_visible(enum radv_mem_type type
)
142 return type
== RADV_MEM_TYPE_VRAM_CPU_ACCESS
||
143 type
== RADV_MEM_TYPE_VRAM_CPU_ACCESS_UNCACHED
;
146 radv_is_mem_type_gtt_wc(enum radv_mem_type type
)
148 return type
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
||
149 type
== RADV_MEM_TYPE_GTT_WRITE_COMBINE_VRAM_UNCACHED
;
153 radv_is_mem_type_gtt_cached(enum radv_mem_type type
)
155 return type
== RADV_MEM_TYPE_GTT_CACHED
||
156 type
== RADV_MEM_TYPE_GTT_CACHED_VRAM_UNCACHED
;
160 radv_is_mem_type_uncached(enum radv_mem_type type
)
162 return type
== RADV_MEM_TYPE_VRAM_UNCACHED
||
163 type
== RADV_MEM_TYPE_VRAM_CPU_ACCESS_UNCACHED
||
164 type
== RADV_MEM_TYPE_GTT_WRITE_COMBINE_VRAM_UNCACHED
||
165 type
== RADV_MEM_TYPE_GTT_CACHED_VRAM_UNCACHED
;
169 radv_physical_device_init_mem_types(struct radv_physical_device
*device
)
171 STATIC_ASSERT(RADV_MEM_HEAP_COUNT
<= VK_MAX_MEMORY_HEAPS
);
172 uint64_t visible_vram_size
= radv_get_visible_vram_size(device
);
173 uint64_t vram_size
= radv_get_vram_size(device
);
174 int vram_index
= -1, visible_vram_index
= -1, gart_index
= -1;
175 device
->memory_properties
.memoryHeapCount
= 0;
177 vram_index
= device
->memory_properties
.memoryHeapCount
++;
178 device
->memory_properties
.memoryHeaps
[vram_index
] = (VkMemoryHeap
) {
180 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
183 if (visible_vram_size
) {
184 visible_vram_index
= device
->memory_properties
.memoryHeapCount
++;
185 device
->memory_properties
.memoryHeaps
[visible_vram_index
] = (VkMemoryHeap
) {
186 .size
= visible_vram_size
,
187 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
190 if (device
->rad_info
.gart_size
> 0) {
191 gart_index
= device
->memory_properties
.memoryHeapCount
++;
192 device
->memory_properties
.memoryHeaps
[gart_index
] = (VkMemoryHeap
) {
193 .size
= device
->rad_info
.gart_size
,
194 .flags
= device
->rad_info
.has_dedicated_vram
? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
198 STATIC_ASSERT(RADV_MEM_TYPE_COUNT
<= VK_MAX_MEMORY_TYPES
);
199 unsigned type_count
= 0;
200 if (vram_index
>= 0) {
201 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_VRAM
;
202 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
203 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
,
204 .heapIndex
= vram_index
,
207 if (gart_index
>= 0 && device
->rad_info
.has_dedicated_vram
) {
208 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_WRITE_COMBINE
;
209 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
210 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
211 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
212 .heapIndex
= gart_index
,
215 if (visible_vram_index
>= 0) {
216 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_VRAM_CPU_ACCESS
;
217 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
218 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
|
219 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
220 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
221 .heapIndex
= visible_vram_index
,
224 if (gart_index
>= 0 && !device
->rad_info
.has_dedicated_vram
) {
225 /* Put GTT after visible VRAM for GPUs without dedicated VRAM
226 * as they have identical property flags, and according to the
227 * spec, for types with identical flags, the one with greater
228 * performance must be given a lower index. */
229 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_WRITE_COMBINE
;
230 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
231 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
|
232 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
233 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
234 .heapIndex
= gart_index
,
237 if (gart_index
>= 0) {
238 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_CACHED
;
239 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
240 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
241 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
242 VK_MEMORY_PROPERTY_HOST_CACHED_BIT
|
243 (device
->rad_info
.has_dedicated_vram
? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
),
244 .heapIndex
= gart_index
,
247 device
->memory_properties
.memoryTypeCount
= type_count
;
249 if (device
->rad_info
.has_l2_uncached
) {
250 for (int i
= 0; i
< device
->memory_properties
.memoryTypeCount
; i
++) {
251 VkMemoryType mem_type
= device
->memory_properties
.memoryTypes
[i
];
253 if ((mem_type
.propertyFlags
& (VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
254 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
)) ||
255 mem_type
.propertyFlags
== VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
) {
256 enum radv_mem_type mem_type_id
;
258 switch (device
->mem_type_indices
[i
]) {
259 case RADV_MEM_TYPE_VRAM
:
260 mem_type_id
= RADV_MEM_TYPE_VRAM_UNCACHED
;
262 case RADV_MEM_TYPE_VRAM_CPU_ACCESS
:
263 mem_type_id
= RADV_MEM_TYPE_VRAM_CPU_ACCESS_UNCACHED
;
265 case RADV_MEM_TYPE_GTT_WRITE_COMBINE
:
266 mem_type_id
= RADV_MEM_TYPE_GTT_WRITE_COMBINE_VRAM_UNCACHED
;
268 case RADV_MEM_TYPE_GTT_CACHED
:
269 mem_type_id
= RADV_MEM_TYPE_GTT_CACHED_VRAM_UNCACHED
;
272 unreachable("invalid memory type");
275 VkMemoryPropertyFlags property_flags
= mem_type
.propertyFlags
|
276 VK_MEMORY_PROPERTY_DEVICE_COHERENT_BIT_AMD
|
277 VK_MEMORY_PROPERTY_DEVICE_UNCACHED_BIT_AMD
;
279 device
->mem_type_indices
[type_count
] = mem_type_id
;
280 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
281 .propertyFlags
= property_flags
,
282 .heapIndex
= mem_type
.heapIndex
,
286 device
->memory_properties
.memoryTypeCount
= type_count
;
291 radv_physical_device_init(struct radv_physical_device
*device
,
292 struct radv_instance
*instance
,
293 drmDevicePtr drm_device
)
300 const char *path
= drm_device
->nodes
[DRM_NODE_RENDER
];
301 drmVersionPtr version
;
303 fd
= open(path
, O_RDWR
| O_CLOEXEC
);
305 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
306 radv_logi("Could not open device '%s'", path
);
308 return vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
311 version
= drmGetVersion(fd
);
315 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
316 radv_logi("Could not get the kernel driver version for device '%s'", path
);
318 return vk_errorf(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
,
319 "failed to get version %s: %m", path
);
322 if (strcmp(version
->name
, "amdgpu")) {
323 drmFreeVersion(version
);
326 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
327 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path
);
329 return VK_ERROR_INCOMPATIBLE_DRIVER
;
331 drmFreeVersion(version
);
333 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
334 radv_logi("Found compatible device '%s'.", path
);
337 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
338 device
->instance
= instance
;
341 device
->ws
= radv_amdgpu_winsys_create(fd
, instance
->debug_flags
,
342 instance
->perftest_flags
);
344 device
->ws
= radv_null_winsys_create();
348 result
= vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
352 if (drm_device
&& instance
->enabled_extensions
.KHR_display
) {
353 master_fd
= open(drm_device
->nodes
[DRM_NODE_PRIMARY
], O_RDWR
| O_CLOEXEC
);
354 if (master_fd
>= 0) {
355 uint32_t accel_working
= 0;
356 struct drm_amdgpu_info request
= {
357 .return_pointer
= (uintptr_t)&accel_working
,
358 .return_size
= sizeof(accel_working
),
359 .query
= AMDGPU_INFO_ACCEL_WORKING
362 if (drmCommandWrite(master_fd
, DRM_AMDGPU_INFO
, &request
, sizeof (struct drm_amdgpu_info
)) < 0 || !accel_working
) {
369 device
->master_fd
= master_fd
;
370 device
->local_fd
= fd
;
371 device
->ws
->query_info(device
->ws
, &device
->rad_info
);
373 device
->use_aco
= instance
->perftest_flags
& RADV_PERFTEST_ACO
;
375 snprintf(device
->name
, sizeof(device
->name
),
376 "AMD RADV%s %s (LLVM " MESA_LLVM_VERSION_STRING
")", device
->use_aco
? "/ACO" : "",
377 device
->rad_info
.name
);
379 if (radv_device_get_cache_uuid(device
->rad_info
.family
, device
->cache_uuid
)) {
380 device
->ws
->destroy(device
->ws
);
381 result
= vk_errorf(instance
, VK_ERROR_INITIALIZATION_FAILED
,
382 "cannot generate UUID");
386 /* These flags affect shader compilation. */
387 uint64_t shader_env_flags
= (device
->use_aco
? 0x2 : 0);
389 /* The gpu id is already embedded in the uuid so we just pass "radv"
390 * when creating the cache.
392 char buf
[VK_UUID_SIZE
* 2 + 1];
393 disk_cache_format_hex_id(buf
, device
->cache_uuid
, VK_UUID_SIZE
* 2);
394 device
->disk_cache
= disk_cache_create(device
->name
, buf
, shader_env_flags
);
396 if (device
->rad_info
.chip_class
< GFX8
)
397 fprintf(stderr
, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
399 radv_get_driver_uuid(&device
->driver_uuid
);
400 radv_get_device_uuid(&device
->rad_info
, &device
->device_uuid
);
402 device
->out_of_order_rast_allowed
= device
->rad_info
.has_out_of_order_rast
&&
403 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_OUT_OF_ORDER
);
405 device
->dcc_msaa_allowed
=
406 (device
->instance
->perftest_flags
& RADV_PERFTEST_DCC_MSAA
);
408 device
->use_shader_ballot
= (device
->use_aco
&& device
->rad_info
.chip_class
>= GFX8
) ||
409 (device
->instance
->perftest_flags
& RADV_PERFTEST_SHADER_BALLOT
);
411 device
->use_ngg
= device
->rad_info
.chip_class
>= GFX10
&&
412 device
->rad_info
.family
!= CHIP_NAVI14
&&
413 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_NGG
);
415 device
->use_ngg_streamout
= false;
417 /* Determine the number of threads per wave for all stages. */
418 device
->cs_wave_size
= 64;
419 device
->ps_wave_size
= 64;
420 device
->ge_wave_size
= 64;
422 if (device
->rad_info
.chip_class
>= GFX10
) {
423 if (device
->instance
->perftest_flags
& RADV_PERFTEST_CS_WAVE_32
)
424 device
->cs_wave_size
= 32;
426 /* For pixel shaders, wave64 is recommanded. */
427 if (device
->instance
->perftest_flags
& RADV_PERFTEST_PS_WAVE_32
)
428 device
->ps_wave_size
= 32;
430 if (device
->instance
->perftest_flags
& RADV_PERFTEST_GE_WAVE_32
)
431 device
->ge_wave_size
= 32;
434 radv_physical_device_init_mem_types(device
);
435 radv_fill_device_extension_table(device
, &device
->supported_extensions
);
438 device
->bus_info
= *drm_device
->businfo
.pci
;
440 if ((device
->instance
->debug_flags
& RADV_DEBUG_INFO
))
441 ac_print_gpu_info(&device
->rad_info
);
443 /* The WSI is structured as a layer on top of the driver, so this has
444 * to be the last part of initialization (at least until we get other
447 result
= radv_init_wsi(device
);
448 if (result
!= VK_SUCCESS
) {
449 device
->ws
->destroy(device
->ws
);
450 vk_error(instance
, result
);
464 radv_physical_device_finish(struct radv_physical_device
*device
)
466 radv_finish_wsi(device
);
467 device
->ws
->destroy(device
->ws
);
468 disk_cache_destroy(device
->disk_cache
);
469 close(device
->local_fd
);
470 if (device
->master_fd
!= -1)
471 close(device
->master_fd
);
475 default_alloc_func(void *pUserData
, size_t size
, size_t align
,
476 VkSystemAllocationScope allocationScope
)
482 default_realloc_func(void *pUserData
, void *pOriginal
, size_t size
,
483 size_t align
, VkSystemAllocationScope allocationScope
)
485 return realloc(pOriginal
, size
);
489 default_free_func(void *pUserData
, void *pMemory
)
494 static const VkAllocationCallbacks default_alloc
= {
496 .pfnAllocation
= default_alloc_func
,
497 .pfnReallocation
= default_realloc_func
,
498 .pfnFree
= default_free_func
,
501 static const struct debug_control radv_debug_options
[] = {
502 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS
},
503 {"nodcc", RADV_DEBUG_NO_DCC
},
504 {"shaders", RADV_DEBUG_DUMP_SHADERS
},
505 {"nocache", RADV_DEBUG_NO_CACHE
},
506 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS
},
507 {"nohiz", RADV_DEBUG_NO_HIZ
},
508 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE
},
509 {"allbos", RADV_DEBUG_ALL_BOS
},
510 {"noibs", RADV_DEBUG_NO_IBS
},
511 {"spirv", RADV_DEBUG_DUMP_SPIRV
},
512 {"vmfaults", RADV_DEBUG_VM_FAULTS
},
513 {"zerovram", RADV_DEBUG_ZERO_VRAM
},
514 {"syncshaders", RADV_DEBUG_SYNC_SHADERS
},
515 {"preoptir", RADV_DEBUG_PREOPTIR
},
516 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS
},
517 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER
},
518 {"info", RADV_DEBUG_INFO
},
519 {"errors", RADV_DEBUG_ERRORS
},
520 {"startup", RADV_DEBUG_STARTUP
},
521 {"checkir", RADV_DEBUG_CHECKIR
},
522 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM
},
523 {"nobinning", RADV_DEBUG_NOBINNING
},
524 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT
},
525 {"nongg", RADV_DEBUG_NO_NGG
},
526 {"noshaderballot", RADV_DEBUG_NO_SHADER_BALLOT
},
527 {"allentrypoints", RADV_DEBUG_ALL_ENTRYPOINTS
},
528 {"metashaders", RADV_DEBUG_DUMP_META_SHADERS
},
529 {"nomemorycache", RADV_DEBUG_NO_MEMORY_CACHE
},
534 radv_get_debug_option_name(int id
)
536 assert(id
< ARRAY_SIZE(radv_debug_options
) - 1);
537 return radv_debug_options
[id
].string
;
540 static const struct debug_control radv_perftest_options
[] = {
541 {"localbos", RADV_PERFTEST_LOCAL_BOS
},
542 {"dccmsaa", RADV_PERFTEST_DCC_MSAA
},
543 {"bolist", RADV_PERFTEST_BO_LIST
},
544 {"shader_ballot", RADV_PERFTEST_SHADER_BALLOT
},
545 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK
},
546 {"cswave32", RADV_PERFTEST_CS_WAVE_32
},
547 {"pswave32", RADV_PERFTEST_PS_WAVE_32
},
548 {"gewave32", RADV_PERFTEST_GE_WAVE_32
},
549 {"dfsm", RADV_PERFTEST_DFSM
},
550 {"aco", RADV_PERFTEST_ACO
},
555 radv_get_perftest_option_name(int id
)
557 assert(id
< ARRAY_SIZE(radv_perftest_options
) - 1);
558 return radv_perftest_options
[id
].string
;
562 radv_handle_per_app_options(struct radv_instance
*instance
,
563 const VkApplicationInfo
*info
)
565 const char *name
= info
? info
->pApplicationName
: NULL
;
570 if (!strcmp(name
, "DOOM_VFR")) {
571 /* Work around a Doom VFR game bug */
572 instance
->debug_flags
|= RADV_DEBUG_NO_DYNAMIC_BOUNDS
;
573 } else if (!strcmp(name
, "MonsterHunterWorld.exe")) {
574 /* Workaround for a WaW hazard when LLVM moves/merges
575 * load/store memory operations.
576 * See https://reviews.llvm.org/D61313
578 if (LLVM_VERSION_MAJOR
< 9)
579 instance
->debug_flags
|= RADV_DEBUG_NO_LOAD_STORE_OPT
;
580 } else if (!strcmp(name
, "Wolfenstein: Youngblood")) {
581 if (!(instance
->debug_flags
& RADV_DEBUG_NO_SHADER_BALLOT
) &&
582 !(instance
->perftest_flags
& RADV_PERFTEST_ACO
)) {
583 /* Force enable VK_AMD_shader_ballot because it looks
584 * safe and it gives a nice boost (+20% on Vega 56 at
585 * this time). It also prevents corruption on LLVM.
587 instance
->perftest_flags
|= RADV_PERFTEST_SHADER_BALLOT
;
589 } else if (!strcmp(name
, "Fledge")) {
591 * Zero VRAM for "The Surge 2"
593 * This avoid a hang when when rendering any level. Likely
594 * uninitialized data in an indirect draw.
596 instance
->debug_flags
|= RADV_DEBUG_ZERO_VRAM
;
597 } else if (!strcmp(name
, "No Man's Sky")) {
598 /* Work around a NMS game bug */
599 instance
->debug_flags
|= RADV_DEBUG_DISCARD_TO_DEMOTE
;
603 static int radv_get_instance_extension_index(const char *name
)
605 for (unsigned i
= 0; i
< RADV_INSTANCE_EXTENSION_COUNT
; ++i
) {
606 if (strcmp(name
, radv_instance_extensions
[i
].extensionName
) == 0)
612 static const char radv_dri_options_xml
[] =
614 DRI_CONF_SECTION_PERFORMANCE
615 DRI_CONF_ADAPTIVE_SYNC("true")
616 DRI_CONF_VK_X11_OVERRIDE_MIN_IMAGE_COUNT(0)
617 DRI_CONF_VK_X11_STRICT_IMAGE_COUNT("false")
620 DRI_CONF_SECTION_DEBUG
621 DRI_CONF_VK_WSI_FORCE_BGRA8_UNORM_FIRST("false")
625 static void radv_init_dri_options(struct radv_instance
*instance
)
627 driParseOptionInfo(&instance
->available_dri_options
, radv_dri_options_xml
);
628 driParseConfigFiles(&instance
->dri_options
,
629 &instance
->available_dri_options
,
631 instance
->engineName
,
632 instance
->engineVersion
);
635 VkResult
radv_CreateInstance(
636 const VkInstanceCreateInfo
* pCreateInfo
,
637 const VkAllocationCallbacks
* pAllocator
,
638 VkInstance
* pInstance
)
640 struct radv_instance
*instance
;
643 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO
);
645 uint32_t client_version
;
646 if (pCreateInfo
->pApplicationInfo
&&
647 pCreateInfo
->pApplicationInfo
->apiVersion
!= 0) {
648 client_version
= pCreateInfo
->pApplicationInfo
->apiVersion
;
650 client_version
= VK_API_VERSION_1_0
;
653 const char *engine_name
= NULL
;
654 uint32_t engine_version
= 0;
655 if (pCreateInfo
->pApplicationInfo
) {
656 engine_name
= pCreateInfo
->pApplicationInfo
->pEngineName
;
657 engine_version
= pCreateInfo
->pApplicationInfo
->engineVersion
;
660 instance
= vk_zalloc2(&default_alloc
, pAllocator
, sizeof(*instance
), 8,
661 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
663 return vk_error(NULL
, VK_ERROR_OUT_OF_HOST_MEMORY
);
665 instance
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
668 instance
->alloc
= *pAllocator
;
670 instance
->alloc
= default_alloc
;
672 instance
->apiVersion
= client_version
;
673 instance
->physicalDeviceCount
= -1;
675 /* Get secure compile thread count. NOTE: We cap this at 32 */
676 #define MAX_SC_PROCS 32
677 char *num_sc_threads
= getenv("RADV_SECURE_COMPILE_THREADS");
679 instance
->num_sc_threads
= MIN2(strtoul(num_sc_threads
, NULL
, 10), MAX_SC_PROCS
);
681 instance
->debug_flags
= parse_debug_string(getenv("RADV_DEBUG"),
684 /* Disable memory cache when secure compile is set */
685 if (radv_device_use_secure_compile(instance
))
686 instance
->debug_flags
|= RADV_DEBUG_NO_MEMORY_CACHE
;
688 instance
->perftest_flags
= parse_debug_string(getenv("RADV_PERFTEST"),
689 radv_perftest_options
);
691 if (instance
->perftest_flags
& RADV_PERFTEST_ACO
)
692 fprintf(stderr
, "WARNING: Experimental compiler backend enabled. Here be dragons! Incorrect rendering, GPU hangs and/or resets are likely\n");
694 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
695 radv_logi("Created an instance");
697 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
698 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
699 int index
= radv_get_instance_extension_index(ext_name
);
701 if (index
< 0 || !radv_supported_instance_extensions
.extensions
[index
]) {
702 vk_free2(&default_alloc
, pAllocator
, instance
);
703 return vk_error(instance
, VK_ERROR_EXTENSION_NOT_PRESENT
);
706 instance
->enabled_extensions
.extensions
[index
] = true;
709 bool unchecked
= instance
->debug_flags
& RADV_DEBUG_ALL_ENTRYPOINTS
;
711 for (unsigned i
= 0; i
< ARRAY_SIZE(instance
->dispatch
.entrypoints
); i
++) {
712 /* Vulkan requires that entrypoints for extensions which have
713 * not been enabled must not be advertised.
716 !radv_instance_entrypoint_is_enabled(i
, instance
->apiVersion
,
717 &instance
->enabled_extensions
)) {
718 instance
->dispatch
.entrypoints
[i
] = NULL
;
720 instance
->dispatch
.entrypoints
[i
] =
721 radv_instance_dispatch_table
.entrypoints
[i
];
725 for (unsigned i
= 0; i
< ARRAY_SIZE(instance
->physical_device_dispatch
.entrypoints
); i
++) {
726 /* Vulkan requires that entrypoints for extensions which have
727 * not been enabled must not be advertised.
730 !radv_physical_device_entrypoint_is_enabled(i
, instance
->apiVersion
,
731 &instance
->enabled_extensions
)) {
732 instance
->physical_device_dispatch
.entrypoints
[i
] = NULL
;
734 instance
->physical_device_dispatch
.entrypoints
[i
] =
735 radv_physical_device_dispatch_table
.entrypoints
[i
];
739 for (unsigned i
= 0; i
< ARRAY_SIZE(instance
->device_dispatch
.entrypoints
); i
++) {
740 /* Vulkan requires that entrypoints for extensions which have
741 * not been enabled must not be advertised.
744 !radv_device_entrypoint_is_enabled(i
, instance
->apiVersion
,
745 &instance
->enabled_extensions
, NULL
)) {
746 instance
->device_dispatch
.entrypoints
[i
] = NULL
;
748 instance
->device_dispatch
.entrypoints
[i
] =
749 radv_device_dispatch_table
.entrypoints
[i
];
753 result
= vk_debug_report_instance_init(&instance
->debug_report_callbacks
);
754 if (result
!= VK_SUCCESS
) {
755 vk_free2(&default_alloc
, pAllocator
, instance
);
756 return vk_error(instance
, result
);
759 instance
->engineName
= vk_strdup(&instance
->alloc
, engine_name
,
760 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
761 instance
->engineVersion
= engine_version
;
763 glsl_type_singleton_init_or_ref();
765 VG(VALGRIND_CREATE_MEMPOOL(instance
, 0, false));
767 radv_init_dri_options(instance
);
768 radv_handle_per_app_options(instance
, pCreateInfo
->pApplicationInfo
);
770 *pInstance
= radv_instance_to_handle(instance
);
775 void radv_DestroyInstance(
776 VkInstance _instance
,
777 const VkAllocationCallbacks
* pAllocator
)
779 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
784 for (int i
= 0; i
< instance
->physicalDeviceCount
; ++i
) {
785 radv_physical_device_finish(instance
->physicalDevices
+ i
);
788 vk_free(&instance
->alloc
, instance
->engineName
);
790 VG(VALGRIND_DESTROY_MEMPOOL(instance
));
792 glsl_type_singleton_decref();
794 driDestroyOptionCache(&instance
->dri_options
);
795 driDestroyOptionInfo(&instance
->available_dri_options
);
797 vk_debug_report_instance_destroy(&instance
->debug_report_callbacks
);
799 vk_free(&instance
->alloc
, instance
);
803 radv_enumerate_devices(struct radv_instance
*instance
)
805 /* TODO: Check for more devices ? */
806 drmDevicePtr devices
[8];
807 VkResult result
= VK_ERROR_INCOMPATIBLE_DRIVER
;
810 instance
->physicalDeviceCount
= 0;
812 if (getenv("RADV_FORCE_FAMILY")) {
813 /* When RADV_FORCE_FAMILY is set, the driver creates a nul
814 * device that allows to test the compiler without having an
817 result
= radv_physical_device_init(instance
->physicalDevices
+
818 instance
->physicalDeviceCount
,
821 ++instance
->physicalDeviceCount
;
825 max_devices
= drmGetDevices2(0, devices
, ARRAY_SIZE(devices
));
827 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
828 radv_logi("Found %d drm nodes", max_devices
);
831 return vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
833 for (unsigned i
= 0; i
< (unsigned)max_devices
; i
++) {
834 if (devices
[i
]->available_nodes
& 1 << DRM_NODE_RENDER
&&
835 devices
[i
]->bustype
== DRM_BUS_PCI
&&
836 devices
[i
]->deviceinfo
.pci
->vendor_id
== ATI_VENDOR_ID
) {
838 result
= radv_physical_device_init(instance
->physicalDevices
+
839 instance
->physicalDeviceCount
,
842 if (result
== VK_SUCCESS
)
843 ++instance
->physicalDeviceCount
;
844 else if (result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
848 drmFreeDevices(devices
, max_devices
);
853 VkResult
radv_EnumeratePhysicalDevices(
854 VkInstance _instance
,
855 uint32_t* pPhysicalDeviceCount
,
856 VkPhysicalDevice
* pPhysicalDevices
)
858 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
861 if (instance
->physicalDeviceCount
< 0) {
862 result
= radv_enumerate_devices(instance
);
863 if (result
!= VK_SUCCESS
&&
864 result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
868 if (!pPhysicalDevices
) {
869 *pPhysicalDeviceCount
= instance
->physicalDeviceCount
;
871 *pPhysicalDeviceCount
= MIN2(*pPhysicalDeviceCount
, instance
->physicalDeviceCount
);
872 for (unsigned i
= 0; i
< *pPhysicalDeviceCount
; ++i
)
873 pPhysicalDevices
[i
] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
876 return *pPhysicalDeviceCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
880 VkResult
radv_EnumeratePhysicalDeviceGroups(
881 VkInstance _instance
,
882 uint32_t* pPhysicalDeviceGroupCount
,
883 VkPhysicalDeviceGroupProperties
* pPhysicalDeviceGroupProperties
)
885 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
888 if (instance
->physicalDeviceCount
< 0) {
889 result
= radv_enumerate_devices(instance
);
890 if (result
!= VK_SUCCESS
&&
891 result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
895 if (!pPhysicalDeviceGroupProperties
) {
896 *pPhysicalDeviceGroupCount
= instance
->physicalDeviceCount
;
898 *pPhysicalDeviceGroupCount
= MIN2(*pPhysicalDeviceGroupCount
, instance
->physicalDeviceCount
);
899 for (unsigned i
= 0; i
< *pPhysicalDeviceGroupCount
; ++i
) {
900 pPhysicalDeviceGroupProperties
[i
].physicalDeviceCount
= 1;
901 pPhysicalDeviceGroupProperties
[i
].physicalDevices
[0] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
902 pPhysicalDeviceGroupProperties
[i
].subsetAllocation
= false;
905 return *pPhysicalDeviceGroupCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
909 void radv_GetPhysicalDeviceFeatures(
910 VkPhysicalDevice physicalDevice
,
911 VkPhysicalDeviceFeatures
* pFeatures
)
913 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
914 memset(pFeatures
, 0, sizeof(*pFeatures
));
916 *pFeatures
= (VkPhysicalDeviceFeatures
) {
917 .robustBufferAccess
= true,
918 .fullDrawIndexUint32
= true,
919 .imageCubeArray
= true,
920 .independentBlend
= true,
921 .geometryShader
= true,
922 .tessellationShader
= true,
923 .sampleRateShading
= true,
924 .dualSrcBlend
= true,
926 .multiDrawIndirect
= true,
927 .drawIndirectFirstInstance
= true,
929 .depthBiasClamp
= true,
930 .fillModeNonSolid
= true,
935 .multiViewport
= true,
936 .samplerAnisotropy
= true,
937 .textureCompressionETC2
= radv_device_supports_etc(pdevice
),
938 .textureCompressionASTC_LDR
= false,
939 .textureCompressionBC
= true,
940 .occlusionQueryPrecise
= true,
941 .pipelineStatisticsQuery
= true,
942 .vertexPipelineStoresAndAtomics
= true,
943 .fragmentStoresAndAtomics
= true,
944 .shaderTessellationAndGeometryPointSize
= true,
945 .shaderImageGatherExtended
= true,
946 .shaderStorageImageExtendedFormats
= true,
947 .shaderStorageImageMultisample
= true,
948 .shaderUniformBufferArrayDynamicIndexing
= true,
949 .shaderSampledImageArrayDynamicIndexing
= true,
950 .shaderStorageBufferArrayDynamicIndexing
= true,
951 .shaderStorageImageArrayDynamicIndexing
= true,
952 .shaderStorageImageReadWithoutFormat
= true,
953 .shaderStorageImageWriteWithoutFormat
= true,
954 .shaderClipDistance
= true,
955 .shaderCullDistance
= true,
956 .shaderFloat64
= true,
958 .shaderInt16
= pdevice
->rad_info
.chip_class
>= GFX9
&& !pdevice
->use_aco
,
959 .sparseBinding
= true,
960 .variableMultisampleRate
= true,
961 .inheritedQueries
= true,
965 void radv_GetPhysicalDeviceFeatures2(
966 VkPhysicalDevice physicalDevice
,
967 VkPhysicalDeviceFeatures2
*pFeatures
)
969 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
970 vk_foreach_struct(ext
, pFeatures
->pNext
) {
971 switch (ext
->sType
) {
972 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES
: {
973 VkPhysicalDeviceVariablePointersFeatures
*features
= (void *)ext
;
974 features
->variablePointersStorageBuffer
= true;
975 features
->variablePointers
= true;
978 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES
: {
979 VkPhysicalDeviceMultiviewFeatures
*features
= (VkPhysicalDeviceMultiviewFeatures
*)ext
;
980 features
->multiview
= true;
981 features
->multiviewGeometryShader
= true;
982 features
->multiviewTessellationShader
= true;
985 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES
: {
986 VkPhysicalDeviceShaderDrawParametersFeatures
*features
=
987 (VkPhysicalDeviceShaderDrawParametersFeatures
*)ext
;
988 features
->shaderDrawParameters
= true;
991 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES
: {
992 VkPhysicalDeviceProtectedMemoryFeatures
*features
=
993 (VkPhysicalDeviceProtectedMemoryFeatures
*)ext
;
994 features
->protectedMemory
= false;
997 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES
: {
998 VkPhysicalDevice16BitStorageFeatures
*features
=
999 (VkPhysicalDevice16BitStorageFeatures
*)ext
;
1000 features
->storageBuffer16BitAccess
= !pdevice
->use_aco
;
1001 features
->uniformAndStorageBuffer16BitAccess
= !pdevice
->use_aco
;
1002 features
->storagePushConstant16
= !pdevice
->use_aco
;
1003 features
->storageInputOutput16
= pdevice
->rad_info
.has_double_rate_fp16
&& !pdevice
->use_aco
&& LLVM_VERSION_MAJOR
>= 9;
1006 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES
: {
1007 VkPhysicalDeviceSamplerYcbcrConversionFeatures
*features
=
1008 (VkPhysicalDeviceSamplerYcbcrConversionFeatures
*)ext
;
1009 features
->samplerYcbcrConversion
= true;
1012 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES
: {
1013 VkPhysicalDeviceDescriptorIndexingFeatures
*features
=
1014 (VkPhysicalDeviceDescriptorIndexingFeatures
*)ext
;
1015 features
->shaderInputAttachmentArrayDynamicIndexing
= true;
1016 features
->shaderUniformTexelBufferArrayDynamicIndexing
= true;
1017 features
->shaderStorageTexelBufferArrayDynamicIndexing
= true;
1018 features
->shaderUniformBufferArrayNonUniformIndexing
= true;
1019 features
->shaderSampledImageArrayNonUniformIndexing
= true;
1020 features
->shaderStorageBufferArrayNonUniformIndexing
= true;
1021 features
->shaderStorageImageArrayNonUniformIndexing
= true;
1022 features
->shaderInputAttachmentArrayNonUniformIndexing
= true;
1023 features
->shaderUniformTexelBufferArrayNonUniformIndexing
= true;
1024 features
->shaderStorageTexelBufferArrayNonUniformIndexing
= true;
1025 features
->descriptorBindingUniformBufferUpdateAfterBind
= true;
1026 features
->descriptorBindingSampledImageUpdateAfterBind
= true;
1027 features
->descriptorBindingStorageImageUpdateAfterBind
= true;
1028 features
->descriptorBindingStorageBufferUpdateAfterBind
= true;
1029 features
->descriptorBindingUniformTexelBufferUpdateAfterBind
= true;
1030 features
->descriptorBindingStorageTexelBufferUpdateAfterBind
= true;
1031 features
->descriptorBindingUpdateUnusedWhilePending
= true;
1032 features
->descriptorBindingPartiallyBound
= true;
1033 features
->descriptorBindingVariableDescriptorCount
= true;
1034 features
->runtimeDescriptorArray
= true;
1037 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT
: {
1038 VkPhysicalDeviceConditionalRenderingFeaturesEXT
*features
=
1039 (VkPhysicalDeviceConditionalRenderingFeaturesEXT
*)ext
;
1040 features
->conditionalRendering
= true;
1041 features
->inheritedConditionalRendering
= false;
1044 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT
: {
1045 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT
*features
=
1046 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT
*)ext
;
1047 features
->vertexAttributeInstanceRateDivisor
= true;
1048 features
->vertexAttributeInstanceRateZeroDivisor
= true;
1051 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT
: {
1052 VkPhysicalDeviceTransformFeedbackFeaturesEXT
*features
=
1053 (VkPhysicalDeviceTransformFeedbackFeaturesEXT
*)ext
;
1054 features
->transformFeedback
= true;
1055 features
->geometryStreams
= !pdevice
->use_ngg_streamout
;
1058 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES
: {
1059 VkPhysicalDeviceScalarBlockLayoutFeatures
*features
=
1060 (VkPhysicalDeviceScalarBlockLayoutFeatures
*)ext
;
1061 features
->scalarBlockLayout
= pdevice
->rad_info
.chip_class
>= GFX7
;
1064 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT
: {
1065 VkPhysicalDeviceMemoryPriorityFeaturesEXT
*features
=
1066 (VkPhysicalDeviceMemoryPriorityFeaturesEXT
*)ext
;
1067 features
->memoryPriority
= true;
1070 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT
: {
1071 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT
*features
=
1072 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT
*)ext
;
1073 features
->bufferDeviceAddress
= true;
1074 features
->bufferDeviceAddressCaptureReplay
= false;
1075 features
->bufferDeviceAddressMultiDevice
= false;
1078 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES
: {
1079 VkPhysicalDeviceBufferDeviceAddressFeatures
*features
=
1080 (VkPhysicalDeviceBufferDeviceAddressFeatures
*)ext
;
1081 features
->bufferDeviceAddress
= true;
1082 features
->bufferDeviceAddressCaptureReplay
= false;
1083 features
->bufferDeviceAddressMultiDevice
= false;
1086 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT
: {
1087 VkPhysicalDeviceDepthClipEnableFeaturesEXT
*features
=
1088 (VkPhysicalDeviceDepthClipEnableFeaturesEXT
*)ext
;
1089 features
->depthClipEnable
= true;
1092 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES
: {
1093 VkPhysicalDeviceHostQueryResetFeatures
*features
=
1094 (VkPhysicalDeviceHostQueryResetFeatures
*)ext
;
1095 features
->hostQueryReset
= true;
1098 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES
: {
1099 VkPhysicalDevice8BitStorageFeatures
*features
=
1100 (VkPhysicalDevice8BitStorageFeatures
*)ext
;
1101 features
->storageBuffer8BitAccess
= !pdevice
->use_aco
;
1102 features
->uniformAndStorageBuffer8BitAccess
= !pdevice
->use_aco
;
1103 features
->storagePushConstant8
= !pdevice
->use_aco
;
1106 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_FLOAT16_INT8_FEATURES
: {
1107 VkPhysicalDeviceShaderFloat16Int8Features
*features
=
1108 (VkPhysicalDeviceShaderFloat16Int8Features
*)ext
;
1109 features
->shaderFloat16
= pdevice
->rad_info
.has_double_rate_fp16
&& !pdevice
->use_aco
;
1110 features
->shaderInt8
= !pdevice
->use_aco
;
1113 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES
: {
1114 VkPhysicalDeviceShaderAtomicInt64Features
*features
=
1115 (VkPhysicalDeviceShaderAtomicInt64Features
*)ext
;
1116 features
->shaderBufferInt64Atomics
= LLVM_VERSION_MAJOR
>= 9;
1117 features
->shaderSharedInt64Atomics
= LLVM_VERSION_MAJOR
>= 9;
1120 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DEMOTE_TO_HELPER_INVOCATION_FEATURES_EXT
: {
1121 VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT
*features
=
1122 (VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT
*)ext
;
1123 features
->shaderDemoteToHelperInvocation
= pdevice
->use_aco
;
1126 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT
: {
1127 VkPhysicalDeviceInlineUniformBlockFeaturesEXT
*features
=
1128 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT
*)ext
;
1130 features
->inlineUniformBlock
= true;
1131 features
->descriptorBindingInlineUniformBlockUpdateAfterBind
= true;
1134 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV
: {
1135 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV
*features
=
1136 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV
*)ext
;
1137 features
->computeDerivativeGroupQuads
= false;
1138 features
->computeDerivativeGroupLinear
= true;
1141 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT
: {
1142 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT
*features
=
1143 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT
*)ext
;
1144 features
->ycbcrImageArrays
= true;
1147 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES
: {
1148 VkPhysicalDeviceUniformBufferStandardLayoutFeatures
*features
=
1149 (VkPhysicalDeviceUniformBufferStandardLayoutFeatures
*)ext
;
1150 features
->uniformBufferStandardLayout
= true;
1153 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT
: {
1154 VkPhysicalDeviceIndexTypeUint8FeaturesEXT
*features
=
1155 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT
*)ext
;
1156 features
->indexTypeUint8
= pdevice
->rad_info
.chip_class
>= GFX8
;
1159 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGELESS_FRAMEBUFFER_FEATURES
: {
1160 VkPhysicalDeviceImagelessFramebufferFeatures
*features
=
1161 (VkPhysicalDeviceImagelessFramebufferFeatures
*)ext
;
1162 features
->imagelessFramebuffer
= true;
1165 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR
: {
1166 VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR
*features
=
1167 (VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR
*)ext
;
1168 features
->pipelineExecutableInfo
= true;
1171 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CLOCK_FEATURES_KHR
: {
1172 VkPhysicalDeviceShaderClockFeaturesKHR
*features
=
1173 (VkPhysicalDeviceShaderClockFeaturesKHR
*)ext
;
1174 features
->shaderSubgroupClock
= true;
1175 features
->shaderDeviceClock
= false;
1178 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_FEATURES_EXT
: {
1179 VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT
*features
=
1180 (VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT
*)ext
;
1181 features
->texelBufferAlignment
= true;
1184 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_FEATURES
: {
1185 VkPhysicalDeviceTimelineSemaphoreFeatures
*features
=
1186 (VkPhysicalDeviceTimelineSemaphoreFeatures
*) ext
;
1187 features
->timelineSemaphore
= true;
1190 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_FEATURES_EXT
: {
1191 VkPhysicalDeviceSubgroupSizeControlFeaturesEXT
*features
=
1192 (VkPhysicalDeviceSubgroupSizeControlFeaturesEXT
*)ext
;
1193 features
->subgroupSizeControl
= true;
1194 features
->computeFullSubgroups
= true;
1197 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COHERENT_MEMORY_FEATURES_AMD
: {
1198 VkPhysicalDeviceCoherentMemoryFeaturesAMD
*features
=
1199 (VkPhysicalDeviceCoherentMemoryFeaturesAMD
*)ext
;
1200 features
->deviceCoherentMemory
= pdevice
->rad_info
.has_l2_uncached
;
1203 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_SUBGROUP_EXTENDED_TYPES_FEATURES
: {
1204 VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures
*features
=
1205 (VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures
*)ext
;
1206 features
->shaderSubgroupExtendedTypes
= !pdevice
->use_aco
;
1209 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SEPARATE_DEPTH_STENCIL_LAYOUTS_FEATURES_KHR
: {
1210 VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR
*features
=
1211 (VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR
*)ext
;
1212 features
->separateDepthStencilLayouts
= true;
1215 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES
: {
1216 VkPhysicalDeviceVulkan11Features
*features
=
1217 (VkPhysicalDeviceVulkan11Features
*)ext
;
1218 features
->storageBuffer16BitAccess
= !pdevice
->use_aco
;
1219 features
->uniformAndStorageBuffer16BitAccess
= !pdevice
->use_aco
;
1220 features
->storagePushConstant16
= !pdevice
->use_aco
;
1221 features
->storageInputOutput16
= pdevice
->rad_info
.has_double_rate_fp16
&& !pdevice
->use_aco
&& LLVM_VERSION_MAJOR
>= 9;
1222 features
->multiview
= true;
1223 features
->multiviewGeometryShader
= true;
1224 features
->multiviewTessellationShader
= true;
1225 features
->variablePointersStorageBuffer
= true;
1226 features
->variablePointers
= true;
1227 features
->protectedMemory
= false;
1228 features
->samplerYcbcrConversion
= true;
1229 features
->shaderDrawParameters
= true;
1232 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES
: {
1233 VkPhysicalDeviceVulkan12Features
*features
=
1234 (VkPhysicalDeviceVulkan12Features
*)ext
;
1235 features
->samplerMirrorClampToEdge
= true;
1236 features
->drawIndirectCount
= true;
1237 features
->storageBuffer8BitAccess
= !pdevice
->use_aco
;
1238 features
->uniformAndStorageBuffer8BitAccess
= !pdevice
->use_aco
;
1239 features
->storagePushConstant8
= !pdevice
->use_aco
;
1240 features
->shaderBufferInt64Atomics
= LLVM_VERSION_MAJOR
>= 9;
1241 features
->shaderSharedInt64Atomics
= LLVM_VERSION_MAJOR
>= 9;
1242 features
->shaderFloat16
= pdevice
->rad_info
.has_double_rate_fp16
&& !pdevice
->use_aco
;
1243 features
->shaderInt8
= !pdevice
->use_aco
;
1244 features
->descriptorIndexing
= true;
1245 features
->shaderInputAttachmentArrayDynamicIndexing
= true;
1246 features
->shaderUniformTexelBufferArrayDynamicIndexing
= true;
1247 features
->shaderStorageTexelBufferArrayDynamicIndexing
= true;
1248 features
->shaderUniformBufferArrayNonUniformIndexing
= true;
1249 features
->shaderSampledImageArrayNonUniformIndexing
= true;
1250 features
->shaderStorageBufferArrayNonUniformIndexing
= true;
1251 features
->shaderStorageImageArrayNonUniformIndexing
= true;
1252 features
->shaderInputAttachmentArrayNonUniformIndexing
= true;
1253 features
->shaderUniformTexelBufferArrayNonUniformIndexing
= true;
1254 features
->shaderStorageTexelBufferArrayNonUniformIndexing
= true;
1255 features
->descriptorBindingUniformBufferUpdateAfterBind
= true;
1256 features
->descriptorBindingSampledImageUpdateAfterBind
= true;
1257 features
->descriptorBindingStorageImageUpdateAfterBind
= true;
1258 features
->descriptorBindingStorageBufferUpdateAfterBind
= true;
1259 features
->descriptorBindingUniformTexelBufferUpdateAfterBind
= true;
1260 features
->descriptorBindingStorageTexelBufferUpdateAfterBind
= true;
1261 features
->descriptorBindingUpdateUnusedWhilePending
= true;
1262 features
->descriptorBindingPartiallyBound
= true;
1263 features
->descriptorBindingVariableDescriptorCount
= true;
1264 features
->runtimeDescriptorArray
= true;
1265 features
->samplerFilterMinmax
= true;
1266 features
->scalarBlockLayout
= pdevice
->rad_info
.chip_class
>= GFX7
;
1267 features
->imagelessFramebuffer
= true;
1268 features
->uniformBufferStandardLayout
= true;
1269 features
->shaderSubgroupExtendedTypes
= !pdevice
->use_aco
;
1270 features
->separateDepthStencilLayouts
= true;
1271 features
->hostQueryReset
= true;
1272 features
->timelineSemaphore
= pdevice
->rad_info
.has_syncobj_wait_for_submit
;
1273 features
->bufferDeviceAddress
= true;
1274 features
->bufferDeviceAddressCaptureReplay
= false;
1275 features
->bufferDeviceAddressMultiDevice
= false;
1276 features
->vulkanMemoryModel
= false;
1277 features
->vulkanMemoryModelDeviceScope
= false;
1278 features
->vulkanMemoryModelAvailabilityVisibilityChains
= false;
1279 features
->shaderOutputViewportIndex
= true;
1280 features
->shaderOutputLayer
= true;
1281 features
->subgroupBroadcastDynamicId
= true;
1284 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_FEATURES_EXT
: {
1285 VkPhysicalDeviceLineRasterizationFeaturesEXT
*features
=
1286 (VkPhysicalDeviceLineRasterizationFeaturesEXT
*)ext
;
1287 features
->rectangularLines
= false;
1288 features
->bresenhamLines
= true;
1289 features
->smoothLines
= false;
1290 features
->stippledRectangularLines
= false;
1291 features
->stippledBresenhamLines
= true;
1292 features
->stippledSmoothLines
= false;
1299 return radv_GetPhysicalDeviceFeatures(physicalDevice
, &pFeatures
->features
);
1303 radv_max_descriptor_set_size()
1305 /* make sure that the entire descriptor set is addressable with a signed
1306 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1307 * be at most 2 GiB. the combined image & samples object count as one of
1308 * both. This limit is for the pipeline layout, not for the set layout, but
1309 * there is no set limit, so we just set a pipeline limit. I don't think
1310 * any app is going to hit this soon. */
1311 return ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
1312 - MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_INLINE_UNIFORM_BLOCK_COUNT
) /
1313 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1314 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1315 32 /* sampler, largest when combined with image */ +
1316 64 /* sampled image */ +
1317 64 /* storage image */);
1320 void radv_GetPhysicalDeviceProperties(
1321 VkPhysicalDevice physicalDevice
,
1322 VkPhysicalDeviceProperties
* pProperties
)
1324 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1325 VkSampleCountFlags sample_counts
= 0xf;
1327 size_t max_descriptor_set_size
= radv_max_descriptor_set_size();
1329 VkPhysicalDeviceLimits limits
= {
1330 .maxImageDimension1D
= (1 << 14),
1331 .maxImageDimension2D
= (1 << 14),
1332 .maxImageDimension3D
= (1 << 11),
1333 .maxImageDimensionCube
= (1 << 14),
1334 .maxImageArrayLayers
= (1 << 11),
1335 .maxTexelBufferElements
= 128 * 1024 * 1024,
1336 .maxUniformBufferRange
= UINT32_MAX
,
1337 .maxStorageBufferRange
= UINT32_MAX
,
1338 .maxPushConstantsSize
= MAX_PUSH_CONSTANTS_SIZE
,
1339 .maxMemoryAllocationCount
= UINT32_MAX
,
1340 .maxSamplerAllocationCount
= 64 * 1024,
1341 .bufferImageGranularity
= 64, /* A cache line */
1342 .sparseAddressSpaceSize
= RADV_MAX_MEMORY_ALLOCATION_SIZE
, /* buffer max size */
1343 .maxBoundDescriptorSets
= MAX_SETS
,
1344 .maxPerStageDescriptorSamplers
= max_descriptor_set_size
,
1345 .maxPerStageDescriptorUniformBuffers
= max_descriptor_set_size
,
1346 .maxPerStageDescriptorStorageBuffers
= max_descriptor_set_size
,
1347 .maxPerStageDescriptorSampledImages
= max_descriptor_set_size
,
1348 .maxPerStageDescriptorStorageImages
= max_descriptor_set_size
,
1349 .maxPerStageDescriptorInputAttachments
= max_descriptor_set_size
,
1350 .maxPerStageResources
= max_descriptor_set_size
,
1351 .maxDescriptorSetSamplers
= max_descriptor_set_size
,
1352 .maxDescriptorSetUniformBuffers
= max_descriptor_set_size
,
1353 .maxDescriptorSetUniformBuffersDynamic
= MAX_DYNAMIC_UNIFORM_BUFFERS
,
1354 .maxDescriptorSetStorageBuffers
= max_descriptor_set_size
,
1355 .maxDescriptorSetStorageBuffersDynamic
= MAX_DYNAMIC_STORAGE_BUFFERS
,
1356 .maxDescriptorSetSampledImages
= max_descriptor_set_size
,
1357 .maxDescriptorSetStorageImages
= max_descriptor_set_size
,
1358 .maxDescriptorSetInputAttachments
= max_descriptor_set_size
,
1359 .maxVertexInputAttributes
= MAX_VERTEX_ATTRIBS
,
1360 .maxVertexInputBindings
= MAX_VBS
,
1361 .maxVertexInputAttributeOffset
= 2047,
1362 .maxVertexInputBindingStride
= 2048,
1363 .maxVertexOutputComponents
= 128,
1364 .maxTessellationGenerationLevel
= 64,
1365 .maxTessellationPatchSize
= 32,
1366 .maxTessellationControlPerVertexInputComponents
= 128,
1367 .maxTessellationControlPerVertexOutputComponents
= 128,
1368 .maxTessellationControlPerPatchOutputComponents
= 120,
1369 .maxTessellationControlTotalOutputComponents
= 4096,
1370 .maxTessellationEvaluationInputComponents
= 128,
1371 .maxTessellationEvaluationOutputComponents
= 128,
1372 .maxGeometryShaderInvocations
= 127,
1373 .maxGeometryInputComponents
= 64,
1374 .maxGeometryOutputComponents
= 128,
1375 .maxGeometryOutputVertices
= 256,
1376 .maxGeometryTotalOutputComponents
= 1024,
1377 .maxFragmentInputComponents
= 128,
1378 .maxFragmentOutputAttachments
= 8,
1379 .maxFragmentDualSrcAttachments
= 1,
1380 .maxFragmentCombinedOutputResources
= 8,
1381 .maxComputeSharedMemorySize
= 32768,
1382 .maxComputeWorkGroupCount
= { 65535, 65535, 65535 },
1383 .maxComputeWorkGroupInvocations
= 1024,
1384 .maxComputeWorkGroupSize
= {
1389 .subPixelPrecisionBits
= 8,
1390 .subTexelPrecisionBits
= 8,
1391 .mipmapPrecisionBits
= 8,
1392 .maxDrawIndexedIndexValue
= UINT32_MAX
,
1393 .maxDrawIndirectCount
= UINT32_MAX
,
1394 .maxSamplerLodBias
= 16,
1395 .maxSamplerAnisotropy
= 16,
1396 .maxViewports
= MAX_VIEWPORTS
,
1397 .maxViewportDimensions
= { (1 << 14), (1 << 14) },
1398 .viewportBoundsRange
= { INT16_MIN
, INT16_MAX
},
1399 .viewportSubPixelBits
= 8,
1400 .minMemoryMapAlignment
= 4096, /* A page */
1401 .minTexelBufferOffsetAlignment
= 4,
1402 .minUniformBufferOffsetAlignment
= 4,
1403 .minStorageBufferOffsetAlignment
= 4,
1404 .minTexelOffset
= -32,
1405 .maxTexelOffset
= 31,
1406 .minTexelGatherOffset
= -32,
1407 .maxTexelGatherOffset
= 31,
1408 .minInterpolationOffset
= -2,
1409 .maxInterpolationOffset
= 2,
1410 .subPixelInterpolationOffsetBits
= 8,
1411 .maxFramebufferWidth
= (1 << 14),
1412 .maxFramebufferHeight
= (1 << 14),
1413 .maxFramebufferLayers
= (1 << 10),
1414 .framebufferColorSampleCounts
= sample_counts
,
1415 .framebufferDepthSampleCounts
= sample_counts
,
1416 .framebufferStencilSampleCounts
= sample_counts
,
1417 .framebufferNoAttachmentsSampleCounts
= sample_counts
,
1418 .maxColorAttachments
= MAX_RTS
,
1419 .sampledImageColorSampleCounts
= sample_counts
,
1420 .sampledImageIntegerSampleCounts
= sample_counts
,
1421 .sampledImageDepthSampleCounts
= sample_counts
,
1422 .sampledImageStencilSampleCounts
= sample_counts
,
1423 .storageImageSampleCounts
= sample_counts
,
1424 .maxSampleMaskWords
= 1,
1425 .timestampComputeAndGraphics
= true,
1426 .timestampPeriod
= 1000000.0 / pdevice
->rad_info
.clock_crystal_freq
,
1427 .maxClipDistances
= 8,
1428 .maxCullDistances
= 8,
1429 .maxCombinedClipAndCullDistances
= 8,
1430 .discreteQueuePriorities
= 2,
1431 .pointSizeRange
= { 0.0, 8192.0 },
1432 .lineWidthRange
= { 0.0, 8192.0 },
1433 .pointSizeGranularity
= (1.0 / 8.0),
1434 .lineWidthGranularity
= (1.0 / 8.0),
1435 .strictLines
= false, /* FINISHME */
1436 .standardSampleLocations
= true,
1437 .optimalBufferCopyOffsetAlignment
= 128,
1438 .optimalBufferCopyRowPitchAlignment
= 128,
1439 .nonCoherentAtomSize
= 64,
1442 *pProperties
= (VkPhysicalDeviceProperties
) {
1443 .apiVersion
= radv_physical_device_api_version(pdevice
),
1444 .driverVersion
= vk_get_driver_version(),
1445 .vendorID
= ATI_VENDOR_ID
,
1446 .deviceID
= pdevice
->rad_info
.pci_id
,
1447 .deviceType
= pdevice
->rad_info
.has_dedicated_vram
? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU
: VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU
,
1449 .sparseProperties
= {0},
1452 strcpy(pProperties
->deviceName
, pdevice
->name
);
1453 memcpy(pProperties
->pipelineCacheUUID
, pdevice
->cache_uuid
, VK_UUID_SIZE
);
1457 radv_get_physical_device_properties_1_1(struct radv_physical_device
*pdevice
,
1458 VkPhysicalDeviceVulkan11Properties
*p
)
1460 assert(p
->sType
== VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES
);
1462 memcpy(p
->deviceUUID
, pdevice
->device_uuid
, VK_UUID_SIZE
);
1463 memcpy(p
->driverUUID
, pdevice
->driver_uuid
, VK_UUID_SIZE
);
1464 memset(p
->deviceLUID
, 0, VK_LUID_SIZE
);
1465 /* The LUID is for Windows. */
1466 p
->deviceLUIDValid
= false;
1467 p
->deviceNodeMask
= 0;
1469 p
->subgroupSize
= RADV_SUBGROUP_SIZE
;
1470 p
->subgroupSupportedStages
= VK_SHADER_STAGE_ALL
;
1471 p
->subgroupSupportedOperations
= VK_SUBGROUP_FEATURE_BASIC_BIT
|
1472 VK_SUBGROUP_FEATURE_VOTE_BIT
|
1473 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT
|
1474 VK_SUBGROUP_FEATURE_BALLOT_BIT
|
1475 VK_SUBGROUP_FEATURE_CLUSTERED_BIT
|
1476 VK_SUBGROUP_FEATURE_QUAD_BIT
;
1478 if (((pdevice
->rad_info
.chip_class
== GFX6
||
1479 pdevice
->rad_info
.chip_class
== GFX7
) && !pdevice
->use_aco
) ||
1480 pdevice
->rad_info
.chip_class
>= GFX8
) {
1481 p
->subgroupSupportedOperations
|= VK_SUBGROUP_FEATURE_SHUFFLE_BIT
|
1482 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT
;
1484 p
->subgroupQuadOperationsInAllStages
= true;
1486 p
->pointClippingBehavior
= VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES
;
1487 p
->maxMultiviewViewCount
= MAX_VIEWS
;
1488 p
->maxMultiviewInstanceIndex
= INT_MAX
;
1489 p
->protectedNoFault
= false;
1490 p
->maxPerSetDescriptors
= RADV_MAX_PER_SET_DESCRIPTORS
;
1491 p
->maxMemoryAllocationSize
= RADV_MAX_MEMORY_ALLOCATION_SIZE
;
1495 radv_get_physical_device_properties_1_2(struct radv_physical_device
*pdevice
,
1496 VkPhysicalDeviceVulkan12Properties
*p
)
1498 assert(p
->sType
== VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES
);
1500 p
->driverID
= VK_DRIVER_ID_MESA_RADV
;
1501 snprintf(p
->driverName
, VK_MAX_DRIVER_NAME_SIZE
, "radv");
1502 snprintf(p
->driverInfo
, VK_MAX_DRIVER_INFO_SIZE
,
1503 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1504 " (LLVM " MESA_LLVM_VERSION_STRING
")");
1505 p
->conformanceVersion
= (VkConformanceVersion
) {
1512 /* On AMD hardware, denormals and rounding modes for fp16/fp64 are
1513 * controlled by the same config register.
1515 if (pdevice
->rad_info
.has_double_rate_fp16
) {
1516 p
->denormBehaviorIndependence
= VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR
;
1517 p
->roundingModeIndependence
= VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR
;
1519 p
->denormBehaviorIndependence
= VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL_KHR
;
1520 p
->roundingModeIndependence
= VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL_KHR
;
1523 /* Do not allow both preserving and flushing denorms because different
1524 * shaders in the same pipeline can have different settings and this
1525 * won't work for merged shaders. To make it work, this requires LLVM
1526 * support for changing the register. The same logic applies for the
1527 * rounding modes because they are configured with the same config
1528 * register. TODO: we can enable a lot of these for ACO when it
1529 * supports all stages.
1531 p
->shaderDenormFlushToZeroFloat32
= true;
1532 p
->shaderDenormPreserveFloat32
= false;
1533 p
->shaderRoundingModeRTEFloat32
= true;
1534 p
->shaderRoundingModeRTZFloat32
= false;
1535 p
->shaderSignedZeroInfNanPreserveFloat32
= true;
1537 p
->shaderDenormFlushToZeroFloat16
= false;
1538 p
->shaderDenormPreserveFloat16
= pdevice
->rad_info
.has_double_rate_fp16
;
1539 p
->shaderRoundingModeRTEFloat16
= pdevice
->rad_info
.has_double_rate_fp16
;
1540 p
->shaderRoundingModeRTZFloat16
= false;
1541 p
->shaderSignedZeroInfNanPreserveFloat16
= pdevice
->rad_info
.has_double_rate_fp16
;
1543 p
->shaderDenormFlushToZeroFloat64
= false;
1544 p
->shaderDenormPreserveFloat64
= pdevice
->rad_info
.chip_class
>= GFX8
;
1545 p
->shaderRoundingModeRTEFloat64
= pdevice
->rad_info
.chip_class
>= GFX8
;
1546 p
->shaderRoundingModeRTZFloat64
= false;
1547 p
->shaderSignedZeroInfNanPreserveFloat64
= pdevice
->rad_info
.chip_class
>= GFX8
;
1549 p
->maxUpdateAfterBindDescriptorsInAllPools
= UINT32_MAX
/ 64;
1550 p
->shaderUniformBufferArrayNonUniformIndexingNative
= false;
1551 p
->shaderSampledImageArrayNonUniformIndexingNative
= false;
1552 p
->shaderStorageBufferArrayNonUniformIndexingNative
= false;
1553 p
->shaderStorageImageArrayNonUniformIndexingNative
= false;
1554 p
->shaderInputAttachmentArrayNonUniformIndexingNative
= false;
1555 p
->robustBufferAccessUpdateAfterBind
= false;
1556 p
->quadDivergentImplicitLod
= false;
1558 size_t max_descriptor_set_size
= ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
-
1559 MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_INLINE_UNIFORM_BLOCK_COUNT
) /
1560 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1561 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1562 32 /* sampler, largest when combined with image */ +
1563 64 /* sampled image */ +
1564 64 /* storage image */);
1565 p
->maxPerStageDescriptorUpdateAfterBindSamplers
= max_descriptor_set_size
;
1566 p
->maxPerStageDescriptorUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1567 p
->maxPerStageDescriptorUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1568 p
->maxPerStageDescriptorUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1569 p
->maxPerStageDescriptorUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1570 p
->maxPerStageDescriptorUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1571 p
->maxPerStageUpdateAfterBindResources
= max_descriptor_set_size
;
1572 p
->maxDescriptorSetUpdateAfterBindSamplers
= max_descriptor_set_size
;
1573 p
->maxDescriptorSetUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1574 p
->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic
= MAX_DYNAMIC_UNIFORM_BUFFERS
;
1575 p
->maxDescriptorSetUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1576 p
->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic
= MAX_DYNAMIC_STORAGE_BUFFERS
;
1577 p
->maxDescriptorSetUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1578 p
->maxDescriptorSetUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1579 p
->maxDescriptorSetUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1581 /* We support all of the depth resolve modes */
1582 p
->supportedDepthResolveModes
= VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
|
1583 VK_RESOLVE_MODE_AVERAGE_BIT_KHR
|
1584 VK_RESOLVE_MODE_MIN_BIT_KHR
|
1585 VK_RESOLVE_MODE_MAX_BIT_KHR
;
1587 /* Average doesn't make sense for stencil so we don't support that */
1588 p
->supportedStencilResolveModes
= VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
|
1589 VK_RESOLVE_MODE_MIN_BIT_KHR
|
1590 VK_RESOLVE_MODE_MAX_BIT_KHR
;
1592 p
->independentResolveNone
= true;
1593 p
->independentResolve
= true;
1595 /* GFX6-8 only support single channel min/max filter. */
1596 p
->filterMinmaxImageComponentMapping
= pdevice
->rad_info
.chip_class
>= GFX9
;
1597 p
->filterMinmaxSingleComponentFormats
= true;
1599 p
->maxTimelineSemaphoreValueDifference
= UINT64_MAX
;
1601 p
->framebufferIntegerColorSampleCounts
= VK_SAMPLE_COUNT_1_BIT
;
1604 void radv_GetPhysicalDeviceProperties2(
1605 VkPhysicalDevice physicalDevice
,
1606 VkPhysicalDeviceProperties2
*pProperties
)
1608 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1609 radv_GetPhysicalDeviceProperties(physicalDevice
, &pProperties
->properties
);
1611 VkPhysicalDeviceVulkan11Properties core_1_1
= {
1612 .sType
= VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES
,
1614 radv_get_physical_device_properties_1_1(pdevice
, &core_1_1
);
1616 VkPhysicalDeviceVulkan12Properties core_1_2
= {
1617 .sType
= VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES
,
1619 radv_get_physical_device_properties_1_2(pdevice
, &core_1_2
);
1621 #define CORE_RENAMED_PROPERTY(major, minor, ext_property, core_property) \
1622 memcpy(&properties->ext_property, &core_##major##_##minor.core_property, \
1623 sizeof(core_##major##_##minor.core_property))
1625 #define CORE_PROPERTY(major, minor, property) \
1626 CORE_RENAMED_PROPERTY(major, minor, property, property)
1628 vk_foreach_struct(ext
, pProperties
->pNext
) {
1629 switch (ext
->sType
) {
1630 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR
: {
1631 VkPhysicalDevicePushDescriptorPropertiesKHR
*properties
=
1632 (VkPhysicalDevicePushDescriptorPropertiesKHR
*) ext
;
1633 properties
->maxPushDescriptors
= MAX_PUSH_DESCRIPTORS
;
1636 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES
: {
1637 VkPhysicalDeviceIDProperties
*properties
= (VkPhysicalDeviceIDProperties
*)ext
;
1638 CORE_PROPERTY(1, 1, deviceUUID
);
1639 CORE_PROPERTY(1, 1, driverUUID
);
1640 CORE_PROPERTY(1, 1, deviceLUID
);
1641 CORE_PROPERTY(1, 1, deviceLUIDValid
);
1644 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES
: {
1645 VkPhysicalDeviceMultiviewProperties
*properties
= (VkPhysicalDeviceMultiviewProperties
*)ext
;
1646 CORE_PROPERTY(1, 1, maxMultiviewViewCount
);
1647 CORE_PROPERTY(1, 1, maxMultiviewInstanceIndex
);
1650 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES
: {
1651 VkPhysicalDevicePointClippingProperties
*properties
=
1652 (VkPhysicalDevicePointClippingProperties
*)ext
;
1653 CORE_PROPERTY(1, 1, pointClippingBehavior
);
1656 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT
: {
1657 VkPhysicalDeviceDiscardRectanglePropertiesEXT
*properties
=
1658 (VkPhysicalDeviceDiscardRectanglePropertiesEXT
*)ext
;
1659 properties
->maxDiscardRectangles
= MAX_DISCARD_RECTANGLES
;
1662 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT
: {
1663 VkPhysicalDeviceExternalMemoryHostPropertiesEXT
*properties
=
1664 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT
*) ext
;
1665 properties
->minImportedHostPointerAlignment
= 4096;
1668 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES
: {
1669 VkPhysicalDeviceSubgroupProperties
*properties
=
1670 (VkPhysicalDeviceSubgroupProperties
*)ext
;
1671 CORE_PROPERTY(1, 1, subgroupSize
);
1672 CORE_RENAMED_PROPERTY(1, 1, supportedStages
,
1673 subgroupSupportedStages
);
1674 CORE_RENAMED_PROPERTY(1, 1, supportedOperations
,
1675 subgroupSupportedOperations
);
1676 CORE_RENAMED_PROPERTY(1, 1, quadOperationsInAllStages
,
1677 subgroupQuadOperationsInAllStages
);
1680 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES
: {
1681 VkPhysicalDeviceMaintenance3Properties
*properties
=
1682 (VkPhysicalDeviceMaintenance3Properties
*)ext
;
1683 CORE_PROPERTY(1, 1, maxPerSetDescriptors
);
1684 CORE_PROPERTY(1, 1, maxMemoryAllocationSize
);
1687 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES
: {
1688 VkPhysicalDeviceSamplerFilterMinmaxProperties
*properties
=
1689 (VkPhysicalDeviceSamplerFilterMinmaxProperties
*)ext
;
1690 CORE_PROPERTY(1, 2, filterMinmaxImageComponentMapping
);
1691 CORE_PROPERTY(1, 2, filterMinmaxSingleComponentFormats
);
1694 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD
: {
1695 VkPhysicalDeviceShaderCorePropertiesAMD
*properties
=
1696 (VkPhysicalDeviceShaderCorePropertiesAMD
*)ext
;
1698 /* Shader engines. */
1699 properties
->shaderEngineCount
=
1700 pdevice
->rad_info
.max_se
;
1701 properties
->shaderArraysPerEngineCount
=
1702 pdevice
->rad_info
.max_sh_per_se
;
1703 properties
->computeUnitsPerShaderArray
=
1704 pdevice
->rad_info
.num_good_cu_per_sh
;
1705 properties
->simdPerComputeUnit
=
1706 pdevice
->rad_info
.num_simd_per_compute_unit
;
1707 properties
->wavefrontsPerSimd
=
1708 pdevice
->rad_info
.max_wave64_per_simd
;
1709 properties
->wavefrontSize
= 64;
1712 properties
->sgprsPerSimd
=
1713 pdevice
->rad_info
.num_physical_sgprs_per_simd
;
1714 properties
->minSgprAllocation
=
1715 pdevice
->rad_info
.min_sgpr_alloc
;
1716 properties
->maxSgprAllocation
=
1717 pdevice
->rad_info
.max_sgpr_alloc
;
1718 properties
->sgprAllocationGranularity
=
1719 pdevice
->rad_info
.sgpr_alloc_granularity
;
1722 properties
->vgprsPerSimd
=
1723 pdevice
->rad_info
.num_physical_wave64_vgprs_per_simd
;
1724 properties
->minVgprAllocation
=
1725 pdevice
->rad_info
.min_wave64_vgpr_alloc
;
1726 properties
->maxVgprAllocation
=
1727 pdevice
->rad_info
.max_vgpr_alloc
;
1728 properties
->vgprAllocationGranularity
=
1729 pdevice
->rad_info
.wave64_vgpr_alloc_granularity
;
1732 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_2_AMD
: {
1733 VkPhysicalDeviceShaderCoreProperties2AMD
*properties
=
1734 (VkPhysicalDeviceShaderCoreProperties2AMD
*)ext
;
1736 properties
->shaderCoreFeatures
= 0;
1737 properties
->activeComputeUnitCount
=
1738 pdevice
->rad_info
.num_good_compute_units
;
1741 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT
: {
1742 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT
*properties
=
1743 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT
*)ext
;
1744 properties
->maxVertexAttribDivisor
= UINT32_MAX
;
1747 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES
: {
1748 VkPhysicalDeviceDescriptorIndexingProperties
*properties
=
1749 (VkPhysicalDeviceDescriptorIndexingProperties
*)ext
;
1750 CORE_PROPERTY(1, 2, maxUpdateAfterBindDescriptorsInAllPools
);
1751 CORE_PROPERTY(1, 2, shaderUniformBufferArrayNonUniformIndexingNative
);
1752 CORE_PROPERTY(1, 2, shaderSampledImageArrayNonUniformIndexingNative
);
1753 CORE_PROPERTY(1, 2, shaderStorageBufferArrayNonUniformIndexingNative
);
1754 CORE_PROPERTY(1, 2, shaderStorageImageArrayNonUniformIndexingNative
);
1755 CORE_PROPERTY(1, 2, shaderInputAttachmentArrayNonUniformIndexingNative
);
1756 CORE_PROPERTY(1, 2, robustBufferAccessUpdateAfterBind
);
1757 CORE_PROPERTY(1, 2, quadDivergentImplicitLod
);
1758 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSamplers
);
1759 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindUniformBuffers
);
1760 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageBuffers
);
1761 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSampledImages
);
1762 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageImages
);
1763 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindInputAttachments
);
1764 CORE_PROPERTY(1, 2, maxPerStageUpdateAfterBindResources
);
1765 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSamplers
);
1766 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffers
);
1767 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffersDynamic
);
1768 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffers
);
1769 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffersDynamic
);
1770 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSampledImages
);
1771 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageImages
);
1772 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindInputAttachments
);
1775 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES
: {
1776 VkPhysicalDeviceProtectedMemoryProperties
*properties
=
1777 (VkPhysicalDeviceProtectedMemoryProperties
*)ext
;
1778 CORE_PROPERTY(1, 1, protectedNoFault
);
1781 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT
: {
1782 VkPhysicalDeviceConservativeRasterizationPropertiesEXT
*properties
=
1783 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT
*)ext
;
1784 properties
->primitiveOverestimationSize
= 0;
1785 properties
->maxExtraPrimitiveOverestimationSize
= 0;
1786 properties
->extraPrimitiveOverestimationSizeGranularity
= 0;
1787 properties
->primitiveUnderestimation
= false;
1788 properties
->conservativePointAndLineRasterization
= false;
1789 properties
->degenerateTrianglesRasterized
= false;
1790 properties
->degenerateLinesRasterized
= false;
1791 properties
->fullyCoveredFragmentShaderInputVariable
= false;
1792 properties
->conservativeRasterizationPostDepthCoverage
= false;
1795 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT
: {
1796 VkPhysicalDevicePCIBusInfoPropertiesEXT
*properties
=
1797 (VkPhysicalDevicePCIBusInfoPropertiesEXT
*)ext
;
1798 properties
->pciDomain
= pdevice
->bus_info
.domain
;
1799 properties
->pciBus
= pdevice
->bus_info
.bus
;
1800 properties
->pciDevice
= pdevice
->bus_info
.dev
;
1801 properties
->pciFunction
= pdevice
->bus_info
.func
;
1804 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES
: {
1805 VkPhysicalDeviceDriverProperties
*properties
=
1806 (VkPhysicalDeviceDriverProperties
*) ext
;
1807 CORE_PROPERTY(1, 2, driverID
);
1808 CORE_PROPERTY(1, 2, driverName
);
1809 CORE_PROPERTY(1, 2, driverInfo
);
1810 CORE_PROPERTY(1, 2, conformanceVersion
);
1813 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT
: {
1814 VkPhysicalDeviceTransformFeedbackPropertiesEXT
*properties
=
1815 (VkPhysicalDeviceTransformFeedbackPropertiesEXT
*)ext
;
1816 properties
->maxTransformFeedbackStreams
= MAX_SO_STREAMS
;
1817 properties
->maxTransformFeedbackBuffers
= MAX_SO_BUFFERS
;
1818 properties
->maxTransformFeedbackBufferSize
= UINT32_MAX
;
1819 properties
->maxTransformFeedbackStreamDataSize
= 512;
1820 properties
->maxTransformFeedbackBufferDataSize
= UINT32_MAX
;
1821 properties
->maxTransformFeedbackBufferDataStride
= 512;
1822 properties
->transformFeedbackQueries
= !pdevice
->use_ngg_streamout
;
1823 properties
->transformFeedbackStreamsLinesTriangles
= !pdevice
->use_ngg_streamout
;
1824 properties
->transformFeedbackRasterizationStreamSelect
= false;
1825 properties
->transformFeedbackDraw
= true;
1828 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT
: {
1829 VkPhysicalDeviceInlineUniformBlockPropertiesEXT
*props
=
1830 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT
*)ext
;
1832 props
->maxInlineUniformBlockSize
= MAX_INLINE_UNIFORM_BLOCK_SIZE
;
1833 props
->maxPerStageDescriptorInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_SETS
;
1834 props
->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_SETS
;
1835 props
->maxDescriptorSetInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_COUNT
;
1836 props
->maxDescriptorSetUpdateAfterBindInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_COUNT
;
1839 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT
: {
1840 VkPhysicalDeviceSampleLocationsPropertiesEXT
*properties
=
1841 (VkPhysicalDeviceSampleLocationsPropertiesEXT
*)ext
;
1842 properties
->sampleLocationSampleCounts
= VK_SAMPLE_COUNT_2_BIT
|
1843 VK_SAMPLE_COUNT_4_BIT
|
1844 VK_SAMPLE_COUNT_8_BIT
;
1845 properties
->maxSampleLocationGridSize
= (VkExtent2D
){ 2 , 2 };
1846 properties
->sampleLocationCoordinateRange
[0] = 0.0f
;
1847 properties
->sampleLocationCoordinateRange
[1] = 0.9375f
;
1848 properties
->sampleLocationSubPixelBits
= 4;
1849 properties
->variableSampleLocations
= false;
1852 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES
: {
1853 VkPhysicalDeviceDepthStencilResolveProperties
*properties
=
1854 (VkPhysicalDeviceDepthStencilResolveProperties
*)ext
;
1855 CORE_PROPERTY(1, 2, supportedDepthResolveModes
);
1856 CORE_PROPERTY(1, 2, supportedStencilResolveModes
);
1857 CORE_PROPERTY(1, 2, independentResolveNone
);
1858 CORE_PROPERTY(1, 2, independentResolve
);
1861 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_PROPERTIES_EXT
: {
1862 VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT
*properties
=
1863 (VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT
*)ext
;
1864 properties
->storageTexelBufferOffsetAlignmentBytes
= 4;
1865 properties
->storageTexelBufferOffsetSingleTexelAlignment
= true;
1866 properties
->uniformTexelBufferOffsetAlignmentBytes
= 4;
1867 properties
->uniformTexelBufferOffsetSingleTexelAlignment
= true;
1870 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT_CONTROLS_PROPERTIES
: {
1871 VkPhysicalDeviceFloatControlsProperties
*properties
=
1872 (VkPhysicalDeviceFloatControlsProperties
*)ext
;
1873 CORE_PROPERTY(1, 2, denormBehaviorIndependence
);
1874 CORE_PROPERTY(1, 2, roundingModeIndependence
);
1875 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat16
);
1876 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat16
);
1877 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat16
);
1878 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat16
);
1879 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat16
);
1880 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat32
);
1881 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat32
);
1882 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat32
);
1883 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat32
);
1884 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat32
);
1885 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat64
);
1886 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat64
);
1887 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat64
);
1888 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat64
);
1889 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat64
);
1892 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_PROPERTIES
: {
1893 VkPhysicalDeviceTimelineSemaphoreProperties
*properties
=
1894 (VkPhysicalDeviceTimelineSemaphoreProperties
*) ext
;
1895 CORE_PROPERTY(1, 2, maxTimelineSemaphoreValueDifference
);
1898 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_PROPERTIES_EXT
: {
1899 VkPhysicalDeviceSubgroupSizeControlPropertiesEXT
*props
=
1900 (VkPhysicalDeviceSubgroupSizeControlPropertiesEXT
*)ext
;
1901 props
->minSubgroupSize
= 64;
1902 props
->maxSubgroupSize
= 64;
1903 props
->maxComputeWorkgroupSubgroups
= UINT32_MAX
;
1904 props
->requiredSubgroupSizeStages
= 0;
1906 if (pdevice
->rad_info
.chip_class
>= GFX10
) {
1907 /* Only GFX10+ supports wave32. */
1908 props
->minSubgroupSize
= 32;
1909 props
->requiredSubgroupSizeStages
= VK_SHADER_STAGE_COMPUTE_BIT
;
1913 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES
:
1914 radv_get_physical_device_properties_1_1(pdevice
, (void *)ext
);
1916 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES
:
1917 radv_get_physical_device_properties_1_2(pdevice
, (void *)ext
);
1919 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_PROPERTIES_EXT
: {
1920 VkPhysicalDeviceLineRasterizationPropertiesEXT
*props
=
1921 (VkPhysicalDeviceLineRasterizationPropertiesEXT
*)ext
;
1922 props
->lineSubPixelPrecisionBits
= 4;
1931 static void radv_get_physical_device_queue_family_properties(
1932 struct radv_physical_device
* pdevice
,
1934 VkQueueFamilyProperties
** pQueueFamilyProperties
)
1936 int num_queue_families
= 1;
1938 if (pdevice
->rad_info
.num_rings
[RING_COMPUTE
] > 0 &&
1939 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
))
1940 num_queue_families
++;
1942 if (pQueueFamilyProperties
== NULL
) {
1943 *pCount
= num_queue_families
;
1952 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
1953 .queueFlags
= VK_QUEUE_GRAPHICS_BIT
|
1954 VK_QUEUE_COMPUTE_BIT
|
1955 VK_QUEUE_TRANSFER_BIT
|
1956 VK_QUEUE_SPARSE_BINDING_BIT
,
1958 .timestampValidBits
= 64,
1959 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
1964 if (pdevice
->rad_info
.num_rings
[RING_COMPUTE
] > 0 &&
1965 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
)) {
1966 if (*pCount
> idx
) {
1967 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
1968 .queueFlags
= VK_QUEUE_COMPUTE_BIT
|
1969 VK_QUEUE_TRANSFER_BIT
|
1970 VK_QUEUE_SPARSE_BINDING_BIT
,
1971 .queueCount
= pdevice
->rad_info
.num_rings
[RING_COMPUTE
],
1972 .timestampValidBits
= 64,
1973 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
1981 void radv_GetPhysicalDeviceQueueFamilyProperties(
1982 VkPhysicalDevice physicalDevice
,
1984 VkQueueFamilyProperties
* pQueueFamilyProperties
)
1986 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1987 if (!pQueueFamilyProperties
) {
1988 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
1991 VkQueueFamilyProperties
*properties
[] = {
1992 pQueueFamilyProperties
+ 0,
1993 pQueueFamilyProperties
+ 1,
1994 pQueueFamilyProperties
+ 2,
1996 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
1997 assert(*pCount
<= 3);
2000 void radv_GetPhysicalDeviceQueueFamilyProperties2(
2001 VkPhysicalDevice physicalDevice
,
2003 VkQueueFamilyProperties2
*pQueueFamilyProperties
)
2005 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
2006 if (!pQueueFamilyProperties
) {
2007 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
2010 VkQueueFamilyProperties
*properties
[] = {
2011 &pQueueFamilyProperties
[0].queueFamilyProperties
,
2012 &pQueueFamilyProperties
[1].queueFamilyProperties
,
2013 &pQueueFamilyProperties
[2].queueFamilyProperties
,
2015 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
2016 assert(*pCount
<= 3);
2019 void radv_GetPhysicalDeviceMemoryProperties(
2020 VkPhysicalDevice physicalDevice
,
2021 VkPhysicalDeviceMemoryProperties
*pMemoryProperties
)
2023 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
2025 *pMemoryProperties
= physical_device
->memory_properties
;
2029 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice
,
2030 VkPhysicalDeviceMemoryBudgetPropertiesEXT
*memoryBudget
)
2032 RADV_FROM_HANDLE(radv_physical_device
, device
, physicalDevice
);
2033 VkPhysicalDeviceMemoryProperties
*memory_properties
= &device
->memory_properties
;
2034 uint64_t visible_vram_size
= radv_get_visible_vram_size(device
);
2035 uint64_t vram_size
= radv_get_vram_size(device
);
2036 uint64_t gtt_size
= device
->rad_info
.gart_size
;
2037 uint64_t heap_budget
, heap_usage
;
2039 /* For all memory heaps, the computation of budget is as follow:
2040 * heap_budget = heap_size - global_heap_usage + app_heap_usage
2042 * The Vulkan spec 1.1.97 says that the budget should include any
2043 * currently allocated device memory.
2045 * Note that the application heap usages are not really accurate (eg.
2046 * in presence of shared buffers).
2048 for (int i
= 0; i
< device
->memory_properties
.memoryTypeCount
; i
++) {
2049 uint32_t heap_index
= device
->memory_properties
.memoryTypes
[i
].heapIndex
;
2051 if (radv_is_mem_type_vram(device
->mem_type_indices
[i
])) {
2052 heap_usage
= device
->ws
->query_value(device
->ws
,
2053 RADEON_ALLOCATED_VRAM
);
2055 heap_budget
= vram_size
-
2056 device
->ws
->query_value(device
->ws
, RADEON_VRAM_USAGE
) +
2059 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
2060 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
2061 } else if (radv_is_mem_type_vram_visible(device
->mem_type_indices
[i
])) {
2062 heap_usage
= device
->ws
->query_value(device
->ws
,
2063 RADEON_ALLOCATED_VRAM_VIS
);
2065 heap_budget
= visible_vram_size
-
2066 device
->ws
->query_value(device
->ws
, RADEON_VRAM_VIS_USAGE
) +
2069 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
2070 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
2071 } else if (radv_is_mem_type_gtt_wc(device
->mem_type_indices
[i
])) {
2072 heap_usage
= device
->ws
->query_value(device
->ws
,
2073 RADEON_ALLOCATED_GTT
);
2075 heap_budget
= gtt_size
-
2076 device
->ws
->query_value(device
->ws
, RADEON_GTT_USAGE
) +
2079 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
2080 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
2084 /* The heapBudget and heapUsage values must be zero for array elements
2085 * greater than or equal to
2086 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
2088 for (uint32_t i
= memory_properties
->memoryHeapCount
; i
< VK_MAX_MEMORY_HEAPS
; i
++) {
2089 memoryBudget
->heapBudget
[i
] = 0;
2090 memoryBudget
->heapUsage
[i
] = 0;
2094 void radv_GetPhysicalDeviceMemoryProperties2(
2095 VkPhysicalDevice physicalDevice
,
2096 VkPhysicalDeviceMemoryProperties2
*pMemoryProperties
)
2098 radv_GetPhysicalDeviceMemoryProperties(physicalDevice
,
2099 &pMemoryProperties
->memoryProperties
);
2101 VkPhysicalDeviceMemoryBudgetPropertiesEXT
*memory_budget
=
2102 vk_find_struct(pMemoryProperties
->pNext
,
2103 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT
);
2105 radv_get_memory_budget_properties(physicalDevice
, memory_budget
);
2108 VkResult
radv_GetMemoryHostPointerPropertiesEXT(
2110 VkExternalMemoryHandleTypeFlagBits handleType
,
2111 const void *pHostPointer
,
2112 VkMemoryHostPointerPropertiesEXT
*pMemoryHostPointerProperties
)
2114 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2118 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT
: {
2119 const struct radv_physical_device
*physical_device
= device
->physical_device
;
2120 uint32_t memoryTypeBits
= 0;
2121 for (int i
= 0; i
< physical_device
->memory_properties
.memoryTypeCount
; i
++) {
2122 if (radv_is_mem_type_gtt_cached(physical_device
->mem_type_indices
[i
])) {
2123 memoryTypeBits
= (1 << i
);
2127 pMemoryHostPointerProperties
->memoryTypeBits
= memoryTypeBits
;
2131 return VK_ERROR_INVALID_EXTERNAL_HANDLE
;
2135 static enum radeon_ctx_priority
2136 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT
*pObj
)
2138 /* Default to MEDIUM when a specific global priority isn't requested */
2140 return RADEON_CTX_PRIORITY_MEDIUM
;
2142 switch(pObj
->globalPriority
) {
2143 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT
:
2144 return RADEON_CTX_PRIORITY_REALTIME
;
2145 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT
:
2146 return RADEON_CTX_PRIORITY_HIGH
;
2147 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT
:
2148 return RADEON_CTX_PRIORITY_MEDIUM
;
2149 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT
:
2150 return RADEON_CTX_PRIORITY_LOW
;
2152 unreachable("Illegal global priority value");
2153 return RADEON_CTX_PRIORITY_INVALID
;
2158 radv_queue_init(struct radv_device
*device
, struct radv_queue
*queue
,
2159 uint32_t queue_family_index
, int idx
,
2160 VkDeviceQueueCreateFlags flags
,
2161 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
)
2163 queue
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
2164 queue
->device
= device
;
2165 queue
->queue_family_index
= queue_family_index
;
2166 queue
->queue_idx
= idx
;
2167 queue
->priority
= radv_get_queue_global_priority(global_priority
);
2168 queue
->flags
= flags
;
2170 queue
->hw_ctx
= device
->ws
->ctx_create(device
->ws
, queue
->priority
);
2172 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2174 list_inithead(&queue
->pending_submissions
);
2175 pthread_mutex_init(&queue
->pending_mutex
, NULL
);
2181 radv_queue_finish(struct radv_queue
*queue
)
2183 pthread_mutex_destroy(&queue
->pending_mutex
);
2186 queue
->device
->ws
->ctx_destroy(queue
->hw_ctx
);
2188 if (queue
->initial_full_flush_preamble_cs
)
2189 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
2190 if (queue
->initial_preamble_cs
)
2191 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
2192 if (queue
->continue_preamble_cs
)
2193 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
2194 if (queue
->descriptor_bo
)
2195 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
2196 if (queue
->scratch_bo
)
2197 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
2198 if (queue
->esgs_ring_bo
)
2199 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
2200 if (queue
->gsvs_ring_bo
)
2201 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
2202 if (queue
->tess_rings_bo
)
2203 queue
->device
->ws
->buffer_destroy(queue
->tess_rings_bo
);
2205 queue
->device
->ws
->buffer_destroy(queue
->gds_bo
);
2206 if (queue
->gds_oa_bo
)
2207 queue
->device
->ws
->buffer_destroy(queue
->gds_oa_bo
);
2208 if (queue
->compute_scratch_bo
)
2209 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
2213 radv_bo_list_init(struct radv_bo_list
*bo_list
)
2215 pthread_mutex_init(&bo_list
->mutex
, NULL
);
2216 bo_list
->list
.count
= bo_list
->capacity
= 0;
2217 bo_list
->list
.bos
= NULL
;
2221 radv_bo_list_finish(struct radv_bo_list
*bo_list
)
2223 free(bo_list
->list
.bos
);
2224 pthread_mutex_destroy(&bo_list
->mutex
);
2227 static VkResult
radv_bo_list_add(struct radv_device
*device
,
2228 struct radeon_winsys_bo
*bo
)
2230 struct radv_bo_list
*bo_list
= &device
->bo_list
;
2235 if (unlikely(!device
->use_global_bo_list
))
2238 pthread_mutex_lock(&bo_list
->mutex
);
2239 if (bo_list
->list
.count
== bo_list
->capacity
) {
2240 unsigned capacity
= MAX2(4, bo_list
->capacity
* 2);
2241 void *data
= realloc(bo_list
->list
.bos
, capacity
* sizeof(struct radeon_winsys_bo
*));
2244 pthread_mutex_unlock(&bo_list
->mutex
);
2245 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2248 bo_list
->list
.bos
= (struct radeon_winsys_bo
**)data
;
2249 bo_list
->capacity
= capacity
;
2252 bo_list
->list
.bos
[bo_list
->list
.count
++] = bo
;
2253 pthread_mutex_unlock(&bo_list
->mutex
);
2257 static void radv_bo_list_remove(struct radv_device
*device
,
2258 struct radeon_winsys_bo
*bo
)
2260 struct radv_bo_list
*bo_list
= &device
->bo_list
;
2265 if (unlikely(!device
->use_global_bo_list
))
2268 pthread_mutex_lock(&bo_list
->mutex
);
2269 for(unsigned i
= 0; i
< bo_list
->list
.count
; ++i
) {
2270 if (bo_list
->list
.bos
[i
] == bo
) {
2271 bo_list
->list
.bos
[i
] = bo_list
->list
.bos
[bo_list
->list
.count
- 1];
2272 --bo_list
->list
.count
;
2276 pthread_mutex_unlock(&bo_list
->mutex
);
2280 radv_device_init_gs_info(struct radv_device
*device
)
2282 device
->gs_table_depth
= ac_get_gs_table_depth(device
->physical_device
->rad_info
.chip_class
,
2283 device
->physical_device
->rad_info
.family
);
2286 static int radv_get_device_extension_index(const char *name
)
2288 for (unsigned i
= 0; i
< RADV_DEVICE_EXTENSION_COUNT
; ++i
) {
2289 if (strcmp(name
, radv_device_extensions
[i
].extensionName
) == 0)
2296 radv_get_int_debug_option(const char *name
, int default_value
)
2303 result
= default_value
;
2307 result
= strtol(str
, &endptr
, 0);
2308 if (str
== endptr
) {
2309 /* No digits founs. */
2310 result
= default_value
;
2317 static int install_seccomp_filter() {
2319 struct sock_filter filter
[] = {
2320 /* Check arch is 64bit x86 */
2321 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, arch
))),
2322 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, AUDIT_ARCH_X86_64
, 0, 12),
2324 /* Futex is required for mutex locks */
2325 #if defined __NR__newselect
2326 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2327 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR__newselect
, 11, 0),
2328 #elif defined __NR_select
2329 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2330 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_select
, 11, 0),
2332 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2333 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_pselect6
, 11, 0),
2336 /* Allow system exit calls for the forked process */
2337 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2338 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_exit_group
, 9, 0),
2340 /* Allow system read calls */
2341 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2342 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_read
, 7, 0),
2344 /* Allow system write calls */
2345 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2346 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_write
, 5, 0),
2348 /* Allow system brk calls (we need this for malloc) */
2349 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2350 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_brk
, 3, 0),
2352 /* Futex is required for mutex locks */
2353 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2354 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_futex
, 1, 0),
2356 /* Return error if we hit a system call not on the whitelist */
2357 BPF_STMT(BPF_RET
+ BPF_K
, SECCOMP_RET_ERRNO
| (EPERM
& SECCOMP_RET_DATA
)),
2359 /* Allow whitelisted system calls */
2360 BPF_STMT(BPF_RET
+ BPF_K
, SECCOMP_RET_ALLOW
),
2363 struct sock_fprog prog
= {
2364 .len
= (unsigned short)(sizeof(filter
) / sizeof(filter
[0])),
2368 if (prctl(PR_SET_NO_NEW_PRIVS
, 1, 0, 0, 0))
2371 if (prctl(PR_SET_SECCOMP
, SECCOMP_MODE_FILTER
, &prog
))
2377 /* Helper function with timeout support for reading from the pipe between
2378 * processes used for secure compile.
2380 bool radv_sc_read(int fd
, void *buf
, size_t size
, bool timeout
)
2389 /* We can't rely on the value of tv after calling select() so
2390 * we must reset it on each iteration of the loop.
2395 int rval
= select(fd
+ 1, &fds
, NULL
, NULL
, timeout
? &tv
: NULL
);
2401 ssize_t bytes_read
= read(fd
, buf
, size
);
2410 /* select timeout */
2416 static bool radv_close_all_fds(const int *keep_fds
, int keep_fd_count
)
2420 d
= opendir("/proc/self/fd");
2423 int dir_fd
= dirfd(d
);
2425 while ((dir
= readdir(d
)) != NULL
) {
2426 if (dir
->d_name
[0] == '.')
2429 int fd
= atoi(dir
->d_name
);
2434 for (int i
= 0; !keep
&& i
< keep_fd_count
; ++i
)
2435 if (keep_fds
[i
] == fd
)
2447 static bool secure_compile_open_fifo_fds(struct radv_secure_compile_state
*sc
,
2448 int *fd_server
, int *fd_client
,
2449 unsigned process
, bool make_fifo
)
2451 bool result
= false;
2452 char *fifo_server_path
= NULL
;
2453 char *fifo_client_path
= NULL
;
2455 if (asprintf(&fifo_server_path
, "/tmp/radv_server_%s_%u", sc
->uid
, process
) == -1)
2456 goto open_fifo_exit
;
2458 if (asprintf(&fifo_client_path
, "/tmp/radv_client_%s_%u", sc
->uid
, process
) == -1)
2459 goto open_fifo_exit
;
2462 int file1
= mkfifo(fifo_server_path
, 0666);
2464 goto open_fifo_exit
;
2466 int file2
= mkfifo(fifo_client_path
, 0666);
2468 goto open_fifo_exit
;
2471 *fd_server
= open(fifo_server_path
, O_RDWR
);
2473 goto open_fifo_exit
;
2475 *fd_client
= open(fifo_client_path
, O_RDWR
);
2476 if(*fd_client
< 1) {
2478 goto open_fifo_exit
;
2484 free(fifo_server_path
);
2485 free(fifo_client_path
);
2490 static void run_secure_compile_device(struct radv_device
*device
, unsigned process
,
2491 int fd_idle_device_output
)
2493 int fd_secure_input
;
2494 int fd_secure_output
;
2495 bool fifo_result
= secure_compile_open_fifo_fds(device
->sc_state
,
2500 enum radv_secure_compile_type sc_type
;
2502 const int needed_fds
[] = {
2505 fd_idle_device_output
,
2508 if (!fifo_result
|| !radv_close_all_fds(needed_fds
, ARRAY_SIZE(needed_fds
)) ||
2509 install_seccomp_filter() == -1) {
2510 sc_type
= RADV_SC_TYPE_INIT_FAILURE
;
2512 sc_type
= RADV_SC_TYPE_INIT_SUCCESS
;
2513 device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
= fd_secure_input
;
2514 device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
= fd_secure_output
;
2517 write(fd_idle_device_output
, &sc_type
, sizeof(sc_type
));
2519 if (sc_type
== RADV_SC_TYPE_INIT_FAILURE
)
2520 goto secure_compile_exit
;
2523 radv_sc_read(fd_secure_input
, &sc_type
, sizeof(sc_type
), false);
2525 if (sc_type
== RADV_SC_TYPE_COMPILE_PIPELINE
) {
2526 struct radv_pipeline
*pipeline
;
2527 bool sc_read
= true;
2529 pipeline
= vk_zalloc2(&device
->alloc
, NULL
, sizeof(*pipeline
), 8,
2530 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2532 pipeline
->device
= device
;
2534 /* Read pipeline layout */
2535 struct radv_pipeline_layout layout
;
2536 sc_read
= radv_sc_read(fd_secure_input
, &layout
, sizeof(struct radv_pipeline_layout
), true);
2537 sc_read
&= radv_sc_read(fd_secure_input
, &layout
.num_sets
, sizeof(uint32_t), true);
2539 goto secure_compile_exit
;
2541 for (uint32_t set
= 0; set
< layout
.num_sets
; set
++) {
2542 uint32_t layout_size
;
2543 sc_read
&= radv_sc_read(fd_secure_input
, &layout_size
, sizeof(uint32_t), true);
2545 goto secure_compile_exit
;
2547 layout
.set
[set
].layout
= malloc(layout_size
);
2548 layout
.set
[set
].layout
->layout_size
= layout_size
;
2549 sc_read
&= radv_sc_read(fd_secure_input
, layout
.set
[set
].layout
,
2550 layout
.set
[set
].layout
->layout_size
, true);
2553 pipeline
->layout
= &layout
;
2555 /* Read pipeline key */
2556 struct radv_pipeline_key key
;
2557 sc_read
&= radv_sc_read(fd_secure_input
, &key
, sizeof(struct radv_pipeline_key
), true);
2559 /* Read pipeline create flags */
2560 VkPipelineCreateFlags flags
;
2561 sc_read
&= radv_sc_read(fd_secure_input
, &flags
, sizeof(VkPipelineCreateFlags
), true);
2563 /* Read stage and shader information */
2564 uint32_t num_stages
;
2565 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
2566 sc_read
&= radv_sc_read(fd_secure_input
, &num_stages
, sizeof(uint32_t), true);
2568 goto secure_compile_exit
;
2570 for (uint32_t i
= 0; i
< num_stages
; i
++) {
2573 gl_shader_stage stage
;
2574 sc_read
&= radv_sc_read(fd_secure_input
, &stage
, sizeof(gl_shader_stage
), true);
2576 VkPipelineShaderStageCreateInfo
*pStage
= calloc(1, sizeof(VkPipelineShaderStageCreateInfo
));
2578 /* Read entry point name */
2580 sc_read
&= radv_sc_read(fd_secure_input
, &name_size
, sizeof(size_t), true);
2582 goto secure_compile_exit
;
2584 char *ep_name
= malloc(name_size
);
2585 sc_read
&= radv_sc_read(fd_secure_input
, ep_name
, name_size
, true);
2586 pStage
->pName
= ep_name
;
2588 /* Read shader module */
2590 sc_read
&= radv_sc_read(fd_secure_input
, &module_size
, sizeof(size_t), true);
2592 goto secure_compile_exit
;
2594 struct radv_shader_module
*module
= malloc(module_size
);
2595 sc_read
&= radv_sc_read(fd_secure_input
, module
, module_size
, true);
2596 pStage
->module
= radv_shader_module_to_handle(module
);
2598 /* Read specialization info */
2600 sc_read
&= radv_sc_read(fd_secure_input
, &has_spec_info
, sizeof(bool), true);
2602 goto secure_compile_exit
;
2604 if (has_spec_info
) {
2605 VkSpecializationInfo
*specInfo
= malloc(sizeof(VkSpecializationInfo
));
2606 pStage
->pSpecializationInfo
= specInfo
;
2608 sc_read
&= radv_sc_read(fd_secure_input
, &specInfo
->dataSize
, sizeof(size_t), true);
2610 goto secure_compile_exit
;
2612 void *si_data
= malloc(specInfo
->dataSize
);
2613 sc_read
&= radv_sc_read(fd_secure_input
, si_data
, specInfo
->dataSize
, true);
2614 specInfo
->pData
= si_data
;
2616 sc_read
&= radv_sc_read(fd_secure_input
, &specInfo
->mapEntryCount
, sizeof(uint32_t), true);
2618 goto secure_compile_exit
;
2620 VkSpecializationMapEntry
*mapEntries
= malloc(sizeof(VkSpecializationMapEntry
) * specInfo
->mapEntryCount
);
2621 for (uint32_t j
= 0; j
< specInfo
->mapEntryCount
; j
++) {
2622 sc_read
&= radv_sc_read(fd_secure_input
, &mapEntries
[j
], sizeof(VkSpecializationMapEntry
), true);
2624 goto secure_compile_exit
;
2627 specInfo
->pMapEntries
= mapEntries
;
2630 pStages
[stage
] = pStage
;
2633 /* Compile the shaders */
2634 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
2635 radv_create_shaders(pipeline
, device
, NULL
, &key
, pStages
, flags
, NULL
, stage_feedbacks
);
2637 /* free memory allocated above */
2638 for (uint32_t set
= 0; set
< layout
.num_sets
; set
++)
2639 free(layout
.set
[set
].layout
);
2641 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2645 free((void *) pStages
[i
]->pName
);
2646 free(radv_shader_module_from_handle(pStages
[i
]->module
));
2647 if (pStages
[i
]->pSpecializationInfo
) {
2648 free((void *) pStages
[i
]->pSpecializationInfo
->pData
);
2649 free((void *) pStages
[i
]->pSpecializationInfo
->pMapEntries
);
2650 free((void *) pStages
[i
]->pSpecializationInfo
);
2652 free((void *) pStages
[i
]);
2655 vk_free(&device
->alloc
, pipeline
);
2657 sc_type
= RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED
;
2658 write(fd_secure_output
, &sc_type
, sizeof(sc_type
));
2660 } else if (sc_type
== RADV_SC_TYPE_DESTROY_DEVICE
) {
2661 goto secure_compile_exit
;
2665 secure_compile_exit
:
2666 close(fd_secure_input
);
2667 close(fd_secure_output
);
2668 close(fd_idle_device_output
);
2672 static enum radv_secure_compile_type
fork_secure_compile_device(struct radv_device
*device
, unsigned process
)
2674 int fd_secure_input
[2];
2675 int fd_secure_output
[2];
2677 /* create pipe descriptors (used to communicate between processes) */
2678 if (pipe(fd_secure_input
) == -1 || pipe(fd_secure_output
) == -1)
2679 return RADV_SC_TYPE_INIT_FAILURE
;
2683 if ((sc_pid
= fork()) == 0) {
2684 device
->sc_state
->secure_compile_thread_counter
= process
;
2685 run_secure_compile_device(device
, process
, fd_secure_output
[1]);
2688 return RADV_SC_TYPE_INIT_FAILURE
;
2690 /* Read the init result returned from the secure process */
2691 enum radv_secure_compile_type sc_type
;
2692 bool sc_read
= radv_sc_read(fd_secure_output
[0], &sc_type
, sizeof(sc_type
), true);
2694 if (sc_type
== RADV_SC_TYPE_INIT_FAILURE
|| !sc_read
) {
2695 close(fd_secure_input
[0]);
2696 close(fd_secure_input
[1]);
2697 close(fd_secure_output
[1]);
2698 close(fd_secure_output
[0]);
2700 waitpid(sc_pid
, &status
, 0);
2702 return RADV_SC_TYPE_INIT_FAILURE
;
2704 assert(sc_type
== RADV_SC_TYPE_INIT_SUCCESS
);
2705 write(device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
, &sc_type
, sizeof(sc_type
));
2707 close(fd_secure_input
[0]);
2708 close(fd_secure_input
[1]);
2709 close(fd_secure_output
[1]);
2710 close(fd_secure_output
[0]);
2713 waitpid(sc_pid
, &status
, 0);
2717 return RADV_SC_TYPE_INIT_SUCCESS
;
2720 /* Run a bare bones fork of a device that was forked right after its creation.
2721 * This device will have low overhead when it is forked again before each
2722 * pipeline compilation. This device sits idle and its only job is to fork
2725 static void run_secure_compile_idle_device(struct radv_device
*device
, unsigned process
,
2726 int fd_secure_input
, int fd_secure_output
)
2728 enum radv_secure_compile_type sc_type
= RADV_SC_TYPE_INIT_SUCCESS
;
2729 device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
= fd_secure_input
;
2730 device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
= fd_secure_output
;
2732 write(fd_secure_output
, &sc_type
, sizeof(sc_type
));
2735 radv_sc_read(fd_secure_input
, &sc_type
, sizeof(sc_type
), false);
2737 if (sc_type
== RADV_SC_TYPE_FORK_DEVICE
) {
2738 sc_type
= fork_secure_compile_device(device
, process
);
2740 if (sc_type
== RADV_SC_TYPE_INIT_FAILURE
)
2741 goto secure_compile_exit
;
2743 } else if (sc_type
== RADV_SC_TYPE_DESTROY_DEVICE
) {
2744 goto secure_compile_exit
;
2748 secure_compile_exit
:
2749 close(fd_secure_input
);
2750 close(fd_secure_output
);
2754 static void destroy_secure_compile_device(struct radv_device
*device
, unsigned process
)
2756 int fd_secure_input
= device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
;
2758 enum radv_secure_compile_type sc_type
= RADV_SC_TYPE_DESTROY_DEVICE
;
2759 write(fd_secure_input
, &sc_type
, sizeof(sc_type
));
2761 close(device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
);
2762 close(device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
);
2765 waitpid(device
->sc_state
->secure_compile_processes
[process
].sc_pid
, &status
, 0);
2768 static VkResult
fork_secure_compile_idle_device(struct radv_device
*device
)
2770 device
->sc_state
= vk_zalloc(&device
->alloc
,
2771 sizeof(struct radv_secure_compile_state
),
2772 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
2774 mtx_init(&device
->sc_state
->secure_compile_mutex
, mtx_plain
);
2776 pid_t upid
= getpid();
2777 time_t seconds
= time(NULL
);
2780 if (asprintf(&uid
, "%ld_%ld", (long) upid
, (long) seconds
) == -1)
2781 return VK_ERROR_INITIALIZATION_FAILED
;
2783 device
->sc_state
->uid
= uid
;
2785 uint8_t sc_threads
= device
->instance
->num_sc_threads
;
2786 int fd_secure_input
[MAX_SC_PROCS
][2];
2787 int fd_secure_output
[MAX_SC_PROCS
][2];
2789 /* create pipe descriptors (used to communicate between processes) */
2790 for (unsigned i
= 0; i
< sc_threads
; i
++) {
2791 if (pipe(fd_secure_input
[i
]) == -1 ||
2792 pipe(fd_secure_output
[i
]) == -1) {
2793 return VK_ERROR_INITIALIZATION_FAILED
;
2797 device
->sc_state
->secure_compile_processes
= vk_zalloc(&device
->alloc
,
2798 sizeof(struct radv_secure_compile_process
) * sc_threads
, 8,
2799 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
2801 for (unsigned process
= 0; process
< sc_threads
; process
++) {
2802 if ((device
->sc_state
->secure_compile_processes
[process
].sc_pid
= fork()) == 0) {
2803 device
->sc_state
->secure_compile_thread_counter
= process
;
2804 run_secure_compile_idle_device(device
, process
, fd_secure_input
[process
][0], fd_secure_output
[process
][1]);
2806 if (device
->sc_state
->secure_compile_processes
[process
].sc_pid
== -1)
2807 return VK_ERROR_INITIALIZATION_FAILED
;
2809 /* Read the init result returned from the secure process */
2810 enum radv_secure_compile_type sc_type
;
2811 bool sc_read
= radv_sc_read(fd_secure_output
[process
][0], &sc_type
, sizeof(sc_type
), true);
2814 if (sc_read
&& sc_type
== RADV_SC_TYPE_INIT_SUCCESS
) {
2815 fifo_result
= secure_compile_open_fifo_fds(device
->sc_state
,
2816 &device
->sc_state
->secure_compile_processes
[process
].fd_server
,
2817 &device
->sc_state
->secure_compile_processes
[process
].fd_client
,
2820 device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
= fd_secure_input
[process
][1];
2821 device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
= fd_secure_output
[process
][0];
2824 if (sc_type
== RADV_SC_TYPE_INIT_FAILURE
|| !sc_read
|| !fifo_result
) {
2825 close(fd_secure_input
[process
][0]);
2826 close(fd_secure_input
[process
][1]);
2827 close(fd_secure_output
[process
][1]);
2828 close(fd_secure_output
[process
][0]);
2830 waitpid(device
->sc_state
->secure_compile_processes
[process
].sc_pid
, &status
, 0);
2832 /* Destroy any forks that were created sucessfully */
2833 for (unsigned i
= 0; i
< process
; i
++) {
2834 destroy_secure_compile_device(device
, i
);
2837 return VK_ERROR_INITIALIZATION_FAILED
;
2845 radv_device_init_dispatch(struct radv_device
*device
)
2847 const struct radv_instance
*instance
= device
->physical_device
->instance
;
2848 const struct radv_device_dispatch_table
*dispatch_table_layer
= NULL
;
2849 bool unchecked
= instance
->debug_flags
& RADV_DEBUG_ALL_ENTRYPOINTS
;
2850 int radv_thread_trace
= radv_get_int_debug_option("RADV_THREAD_TRACE", -1);
2852 if (radv_thread_trace
>= 0) {
2853 /* Use device entrypoints from the SQTT layer if enabled. */
2854 dispatch_table_layer
= &sqtt_device_dispatch_table
;
2857 for (unsigned i
= 0; i
< ARRAY_SIZE(device
->dispatch
.entrypoints
); i
++) {
2858 /* Vulkan requires that entrypoints for extensions which have not been
2859 * enabled must not be advertised.
2862 !radv_device_entrypoint_is_enabled(i
, instance
->apiVersion
,
2863 &instance
->enabled_extensions
,
2864 &device
->enabled_extensions
)) {
2865 device
->dispatch
.entrypoints
[i
] = NULL
;
2866 } else if (dispatch_table_layer
&&
2867 dispatch_table_layer
->entrypoints
[i
]) {
2868 device
->dispatch
.entrypoints
[i
] =
2869 dispatch_table_layer
->entrypoints
[i
];
2871 device
->dispatch
.entrypoints
[i
] =
2872 radv_device_dispatch_table
.entrypoints
[i
];
2878 radv_create_pthread_cond(pthread_cond_t
*cond
)
2880 pthread_condattr_t condattr
;
2881 if (pthread_condattr_init(&condattr
)) {
2882 return VK_ERROR_INITIALIZATION_FAILED
;
2885 if (pthread_condattr_setclock(&condattr
, CLOCK_MONOTONIC
)) {
2886 pthread_condattr_destroy(&condattr
);
2887 return VK_ERROR_INITIALIZATION_FAILED
;
2889 if (pthread_cond_init(cond
, &condattr
)) {
2890 pthread_condattr_destroy(&condattr
);
2891 return VK_ERROR_INITIALIZATION_FAILED
;
2893 pthread_condattr_destroy(&condattr
);
2897 VkResult
radv_CreateDevice(
2898 VkPhysicalDevice physicalDevice
,
2899 const VkDeviceCreateInfo
* pCreateInfo
,
2900 const VkAllocationCallbacks
* pAllocator
,
2903 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
2905 struct radv_device
*device
;
2907 bool keep_shader_info
= false;
2909 /* Check enabled features */
2910 if (pCreateInfo
->pEnabledFeatures
) {
2911 VkPhysicalDeviceFeatures supported_features
;
2912 radv_GetPhysicalDeviceFeatures(physicalDevice
, &supported_features
);
2913 VkBool32
*supported_feature
= (VkBool32
*)&supported_features
;
2914 VkBool32
*enabled_feature
= (VkBool32
*)pCreateInfo
->pEnabledFeatures
;
2915 unsigned num_features
= sizeof(VkPhysicalDeviceFeatures
) / sizeof(VkBool32
);
2916 for (uint32_t i
= 0; i
< num_features
; i
++) {
2917 if (enabled_feature
[i
] && !supported_feature
[i
])
2918 return vk_error(physical_device
->instance
, VK_ERROR_FEATURE_NOT_PRESENT
);
2922 device
= vk_zalloc2(&physical_device
->instance
->alloc
, pAllocator
,
2924 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
2926 return vk_error(physical_device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2928 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
2929 device
->instance
= physical_device
->instance
;
2930 device
->physical_device
= physical_device
;
2932 device
->ws
= physical_device
->ws
;
2934 device
->alloc
= *pAllocator
;
2936 device
->alloc
= physical_device
->instance
->alloc
;
2938 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
2939 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
2940 int index
= radv_get_device_extension_index(ext_name
);
2941 if (index
< 0 || !physical_device
->supported_extensions
.extensions
[index
]) {
2942 vk_free(&device
->alloc
, device
);
2943 return vk_error(physical_device
->instance
, VK_ERROR_EXTENSION_NOT_PRESENT
);
2946 device
->enabled_extensions
.extensions
[index
] = true;
2949 radv_device_init_dispatch(device
);
2951 keep_shader_info
= device
->enabled_extensions
.AMD_shader_info
;
2953 /* With update after bind we can't attach bo's to the command buffer
2954 * from the descriptor set anymore, so we have to use a global BO list.
2956 device
->use_global_bo_list
=
2957 (device
->instance
->perftest_flags
& RADV_PERFTEST_BO_LIST
) ||
2958 device
->enabled_extensions
.EXT_descriptor_indexing
||
2959 device
->enabled_extensions
.EXT_buffer_device_address
||
2960 device
->enabled_extensions
.KHR_buffer_device_address
;
2962 device
->robust_buffer_access
= pCreateInfo
->pEnabledFeatures
&&
2963 pCreateInfo
->pEnabledFeatures
->robustBufferAccess
;
2965 mtx_init(&device
->shader_slab_mutex
, mtx_plain
);
2966 list_inithead(&device
->shader_slabs
);
2968 radv_bo_list_init(&device
->bo_list
);
2970 for (unsigned i
= 0; i
< pCreateInfo
->queueCreateInfoCount
; i
++) {
2971 const VkDeviceQueueCreateInfo
*queue_create
= &pCreateInfo
->pQueueCreateInfos
[i
];
2972 uint32_t qfi
= queue_create
->queueFamilyIndex
;
2973 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
=
2974 vk_find_struct_const(queue_create
->pNext
, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT
);
2976 assert(!global_priority
|| device
->physical_device
->rad_info
.has_ctx_priority
);
2978 device
->queues
[qfi
] = vk_alloc(&device
->alloc
,
2979 queue_create
->queueCount
* sizeof(struct radv_queue
), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
2980 if (!device
->queues
[qfi
]) {
2981 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2985 memset(device
->queues
[qfi
], 0, queue_create
->queueCount
* sizeof(struct radv_queue
));
2987 device
->queue_count
[qfi
] = queue_create
->queueCount
;
2989 for (unsigned q
= 0; q
< queue_create
->queueCount
; q
++) {
2990 result
= radv_queue_init(device
, &device
->queues
[qfi
][q
],
2991 qfi
, q
, queue_create
->flags
,
2993 if (result
!= VK_SUCCESS
)
2998 device
->pbb_allowed
= device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2999 !(device
->instance
->debug_flags
& RADV_DEBUG_NOBINNING
);
3001 /* Disable DFSM by default. As of 2019-09-15 Talos on Low is still 3% slower on Raven. */
3002 device
->dfsm_allowed
= device
->pbb_allowed
&&
3003 (device
->instance
->perftest_flags
& RADV_PERFTEST_DFSM
);
3005 device
->always_use_syncobj
= device
->physical_device
->rad_info
.has_syncobj_wait_for_submit
;
3007 /* The maximum number of scratch waves. Scratch space isn't divided
3008 * evenly between CUs. The number is only a function of the number of CUs.
3009 * We can decrease the constant to decrease the scratch buffer size.
3011 * sctx->scratch_waves must be >= the maximum possible size of
3012 * 1 threadgroup, so that the hw doesn't hang from being unable
3015 * The recommended value is 4 per CU at most. Higher numbers don't
3016 * bring much benefit, but they still occupy chip resources (think
3017 * async compute). I've seen ~2% performance difference between 4 and 32.
3019 uint32_t max_threads_per_block
= 2048;
3020 device
->scratch_waves
= MAX2(32 * physical_device
->rad_info
.num_good_compute_units
,
3021 max_threads_per_block
/ 64);
3023 device
->dispatch_initiator
= S_00B800_COMPUTE_SHADER_EN(1);
3025 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
3026 /* If the KMD allows it (there is a KMD hw register for it),
3027 * allow launching waves out-of-order.
3029 device
->dispatch_initiator
|= S_00B800_ORDER_MODE(1);
3032 radv_device_init_gs_info(device
);
3034 device
->tess_offchip_block_dw_size
=
3035 device
->physical_device
->rad_info
.family
== CHIP_HAWAII
? 4096 : 8192;
3037 if (getenv("RADV_TRACE_FILE")) {
3038 const char *filename
= getenv("RADV_TRACE_FILE");
3040 keep_shader_info
= true;
3042 if (!radv_init_trace(device
))
3045 fprintf(stderr
, "*****************************************************************************\n");
3046 fprintf(stderr
, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
3047 fprintf(stderr
, "*****************************************************************************\n");
3049 fprintf(stderr
, "Trace file will be dumped to %s\n", filename
);
3050 radv_dump_enabled_options(device
, stderr
);
3053 int radv_thread_trace
= radv_get_int_debug_option("RADV_THREAD_TRACE", -1);
3054 if (radv_thread_trace
>= 0) {
3055 fprintf(stderr
, "*************************************************\n");
3056 fprintf(stderr
, "* WARNING: Thread trace support is experimental *\n");
3057 fprintf(stderr
, "*************************************************\n");
3059 if (device
->physical_device
->rad_info
.chip_class
< GFX8
) {
3060 fprintf(stderr
, "GPU hardware not supported: refer to "
3061 "the RGP documentation for the list of "
3062 "supported GPUs!\n");
3066 /* Default buffer size set to 1MB per SE. */
3067 device
->thread_trace_buffer_size
=
3068 radv_get_int_debug_option("RADV_THREAD_TRACE_BUFFER_SIZE", 1024 * 1024);
3069 device
->thread_trace_start_frame
= radv_thread_trace
;
3071 if (!radv_thread_trace_init(device
))
3075 /* Temporarily disable secure compile while we create meta shaders, etc */
3076 uint8_t sc_threads
= device
->instance
->num_sc_threads
;
3078 device
->instance
->num_sc_threads
= 0;
3080 device
->keep_shader_info
= keep_shader_info
;
3081 result
= radv_device_init_meta(device
);
3082 if (result
!= VK_SUCCESS
)
3085 radv_device_init_msaa(device
);
3087 for (int family
= 0; family
< RADV_MAX_QUEUE_FAMILIES
; ++family
) {
3088 device
->empty_cs
[family
] = device
->ws
->cs_create(device
->ws
, family
);
3090 case RADV_QUEUE_GENERAL
:
3091 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
3092 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_LOAD_ENABLE(1));
3093 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_SHADOW_ENABLE(1));
3095 case RADV_QUEUE_COMPUTE
:
3096 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_NOP
, 0, 0));
3097 radeon_emit(device
->empty_cs
[family
], 0);
3100 device
->ws
->cs_finalize(device
->empty_cs
[family
]);
3103 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
3104 cik_create_gfx_config(device
);
3106 VkPipelineCacheCreateInfo ci
;
3107 ci
.sType
= VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO
;
3110 ci
.pInitialData
= NULL
;
3111 ci
.initialDataSize
= 0;
3113 result
= radv_CreatePipelineCache(radv_device_to_handle(device
),
3115 if (result
!= VK_SUCCESS
)
3118 device
->mem_cache
= radv_pipeline_cache_from_handle(pc
);
3120 result
= radv_create_pthread_cond(&device
->timeline_cond
);
3121 if (result
!= VK_SUCCESS
)
3122 goto fail_mem_cache
;
3124 device
->force_aniso
=
3125 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
3126 if (device
->force_aniso
>= 0) {
3127 fprintf(stderr
, "radv: Forcing anisotropy filter to %ix\n",
3128 1 << util_logbase2(device
->force_aniso
));
3131 /* Fork device for secure compile as required */
3132 device
->instance
->num_sc_threads
= sc_threads
;
3133 if (radv_device_use_secure_compile(device
->instance
)) {
3135 result
= fork_secure_compile_idle_device(device
);
3136 if (result
!= VK_SUCCESS
)
3140 *pDevice
= radv_device_to_handle(device
);
3144 radv_DestroyPipelineCache(radv_device_to_handle(device
), pc
, NULL
);
3146 radv_device_finish_meta(device
);
3148 radv_bo_list_finish(&device
->bo_list
);
3150 radv_thread_trace_finish(device
);
3152 if (device
->trace_bo
)
3153 device
->ws
->buffer_destroy(device
->trace_bo
);
3155 if (device
->gfx_init
)
3156 device
->ws
->buffer_destroy(device
->gfx_init
);
3158 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
3159 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
3160 radv_queue_finish(&device
->queues
[i
][q
]);
3161 if (device
->queue_count
[i
])
3162 vk_free(&device
->alloc
, device
->queues
[i
]);
3165 vk_free(&device
->alloc
, device
);
3169 void radv_DestroyDevice(
3171 const VkAllocationCallbacks
* pAllocator
)
3173 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3178 if (device
->trace_bo
)
3179 device
->ws
->buffer_destroy(device
->trace_bo
);
3181 if (device
->gfx_init
)
3182 device
->ws
->buffer_destroy(device
->gfx_init
);
3184 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
3185 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
3186 radv_queue_finish(&device
->queues
[i
][q
]);
3187 if (device
->queue_count
[i
])
3188 vk_free(&device
->alloc
, device
->queues
[i
]);
3189 if (device
->empty_cs
[i
])
3190 device
->ws
->cs_destroy(device
->empty_cs
[i
]);
3192 radv_device_finish_meta(device
);
3194 VkPipelineCache pc
= radv_pipeline_cache_to_handle(device
->mem_cache
);
3195 radv_DestroyPipelineCache(radv_device_to_handle(device
), pc
, NULL
);
3197 radv_destroy_shader_slabs(device
);
3199 pthread_cond_destroy(&device
->timeline_cond
);
3200 radv_bo_list_finish(&device
->bo_list
);
3202 radv_thread_trace_finish(device
);
3204 if (radv_device_use_secure_compile(device
->instance
)) {
3205 for (unsigned i
= 0; i
< device
->instance
->num_sc_threads
; i
++ ) {
3206 destroy_secure_compile_device(device
, i
);
3210 if (device
->sc_state
) {
3211 free(device
->sc_state
->uid
);
3212 vk_free(&device
->alloc
, device
->sc_state
->secure_compile_processes
);
3214 vk_free(&device
->alloc
, device
->sc_state
);
3215 vk_free(&device
->alloc
, device
);
3218 VkResult
radv_EnumerateInstanceLayerProperties(
3219 uint32_t* pPropertyCount
,
3220 VkLayerProperties
* pProperties
)
3222 if (pProperties
== NULL
) {
3223 *pPropertyCount
= 0;
3227 /* None supported at this time */
3228 return vk_error(NULL
, VK_ERROR_LAYER_NOT_PRESENT
);
3231 VkResult
radv_EnumerateDeviceLayerProperties(
3232 VkPhysicalDevice physicalDevice
,
3233 uint32_t* pPropertyCount
,
3234 VkLayerProperties
* pProperties
)
3236 if (pProperties
== NULL
) {
3237 *pPropertyCount
= 0;
3241 /* None supported at this time */
3242 return vk_error(NULL
, VK_ERROR_LAYER_NOT_PRESENT
);
3245 void radv_GetDeviceQueue2(
3247 const VkDeviceQueueInfo2
* pQueueInfo
,
3250 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3251 struct radv_queue
*queue
;
3253 queue
= &device
->queues
[pQueueInfo
->queueFamilyIndex
][pQueueInfo
->queueIndex
];
3254 if (pQueueInfo
->flags
!= queue
->flags
) {
3255 /* From the Vulkan 1.1.70 spec:
3257 * "The queue returned by vkGetDeviceQueue2 must have the same
3258 * flags value from this structure as that used at device
3259 * creation time in a VkDeviceQueueCreateInfo instance. If no
3260 * matching flags were specified at device creation time then
3261 * pQueue will return VK_NULL_HANDLE."
3263 *pQueue
= VK_NULL_HANDLE
;
3267 *pQueue
= radv_queue_to_handle(queue
);
3270 void radv_GetDeviceQueue(
3272 uint32_t queueFamilyIndex
,
3273 uint32_t queueIndex
,
3276 const VkDeviceQueueInfo2 info
= (VkDeviceQueueInfo2
) {
3277 .sType
= VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2
,
3278 .queueFamilyIndex
= queueFamilyIndex
,
3279 .queueIndex
= queueIndex
3282 radv_GetDeviceQueue2(_device
, &info
, pQueue
);
3286 fill_geom_tess_rings(struct radv_queue
*queue
,
3288 bool add_sample_positions
,
3289 uint32_t esgs_ring_size
,
3290 struct radeon_winsys_bo
*esgs_ring_bo
,
3291 uint32_t gsvs_ring_size
,
3292 struct radeon_winsys_bo
*gsvs_ring_bo
,
3293 uint32_t tess_factor_ring_size
,
3294 uint32_t tess_offchip_ring_offset
,
3295 uint32_t tess_offchip_ring_size
,
3296 struct radeon_winsys_bo
*tess_rings_bo
)
3298 uint32_t *desc
= &map
[4];
3301 uint64_t esgs_va
= radv_buffer_get_va(esgs_ring_bo
);
3303 /* stride 0, num records - size, add tid, swizzle, elsize4,
3306 desc
[1] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32) |
3307 S_008F04_SWIZZLE_ENABLE(true);
3308 desc
[2] = esgs_ring_size
;
3309 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3310 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3311 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3312 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
3313 S_008F0C_INDEX_STRIDE(3) |
3314 S_008F0C_ADD_TID_ENABLE(1);
3316 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3317 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3318 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) |
3319 S_008F0C_RESOURCE_LEVEL(1);
3321 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3322 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
3323 S_008F0C_ELEMENT_SIZE(1);
3326 /* GS entry for ES->GS ring */
3327 /* stride 0, num records - size, elsize0,
3330 desc
[5] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32);
3331 desc
[6] = esgs_ring_size
;
3332 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3333 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3334 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3335 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3337 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3338 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3339 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) |
3340 S_008F0C_RESOURCE_LEVEL(1);
3342 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3343 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3350 uint64_t gsvs_va
= radv_buffer_get_va(gsvs_ring_bo
);
3352 /* VS entry for GS->VS ring */
3353 /* stride 0, num records - size, elsize0,
3356 desc
[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32);
3357 desc
[2] = gsvs_ring_size
;
3358 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3359 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3360 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3361 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3363 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3364 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3365 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) |
3366 S_008F0C_RESOURCE_LEVEL(1);
3368 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3369 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3372 /* stride gsvs_itemsize, num records 64
3373 elsize 4, index stride 16 */
3374 /* shader will patch stride and desc[2] */
3376 desc
[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32) |
3377 S_008F04_SWIZZLE_ENABLE(1);
3379 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3380 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3381 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3382 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
3383 S_008F0C_INDEX_STRIDE(1) |
3384 S_008F0C_ADD_TID_ENABLE(true);
3386 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3387 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3388 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) |
3389 S_008F0C_RESOURCE_LEVEL(1);
3391 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3392 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
3393 S_008F0C_ELEMENT_SIZE(1);
3400 if (tess_rings_bo
) {
3401 uint64_t tess_va
= radv_buffer_get_va(tess_rings_bo
);
3402 uint64_t tess_offchip_va
= tess_va
+ tess_offchip_ring_offset
;
3405 desc
[1] = S_008F04_BASE_ADDRESS_HI(tess_va
>> 32);
3406 desc
[2] = tess_factor_ring_size
;
3407 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3408 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3409 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3410 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3412 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3413 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3414 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
3415 S_008F0C_RESOURCE_LEVEL(1);
3417 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3418 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3421 desc
[4] = tess_offchip_va
;
3422 desc
[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va
>> 32);
3423 desc
[6] = tess_offchip_ring_size
;
3424 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3425 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3426 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3427 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3429 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3430 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3431 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
3432 S_008F0C_RESOURCE_LEVEL(1);
3434 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3435 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3441 if (add_sample_positions
) {
3442 /* add sample positions after all rings */
3443 memcpy(desc
, queue
->device
->sample_locations_1x
, 8);
3445 memcpy(desc
, queue
->device
->sample_locations_2x
, 16);
3447 memcpy(desc
, queue
->device
->sample_locations_4x
, 32);
3449 memcpy(desc
, queue
->device
->sample_locations_8x
, 64);
3454 radv_get_hs_offchip_param(struct radv_device
*device
, uint32_t *max_offchip_buffers_p
)
3456 bool double_offchip_buffers
= device
->physical_device
->rad_info
.chip_class
>= GFX7
&&
3457 device
->physical_device
->rad_info
.family
!= CHIP_CARRIZO
&&
3458 device
->physical_device
->rad_info
.family
!= CHIP_STONEY
;
3459 unsigned max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
3460 unsigned max_offchip_buffers
;
3461 unsigned offchip_granularity
;
3462 unsigned hs_offchip_param
;
3466 * This must be one less than the maximum number due to a hw limitation.
3467 * Various hardware bugs need thGFX7
3470 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
3471 * Gfx7 should limit max_offchip_buffers to 508
3472 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
3474 * Follow AMDVLK here.
3476 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3477 max_offchip_buffers_per_se
= 256;
3478 } else if (device
->physical_device
->rad_info
.family
== CHIP_VEGA10
||
3479 device
->physical_device
->rad_info
.chip_class
== GFX7
||
3480 device
->physical_device
->rad_info
.chip_class
== GFX6
)
3481 --max_offchip_buffers_per_se
;
3483 max_offchip_buffers
= max_offchip_buffers_per_se
*
3484 device
->physical_device
->rad_info
.max_se
;
3486 /* Hawaii has a bug with offchip buffers > 256 that can be worked
3487 * around by setting 4K granularity.
3489 if (device
->tess_offchip_block_dw_size
== 4096) {
3490 assert(device
->physical_device
->rad_info
.family
== CHIP_HAWAII
);
3491 offchip_granularity
= V_03093C_X_4K_DWORDS
;
3493 assert(device
->tess_offchip_block_dw_size
== 8192);
3494 offchip_granularity
= V_03093C_X_8K_DWORDS
;
3497 switch (device
->physical_device
->rad_info
.chip_class
) {
3499 max_offchip_buffers
= MIN2(max_offchip_buffers
, 126);
3504 max_offchip_buffers
= MIN2(max_offchip_buffers
, 508);
3512 *max_offchip_buffers_p
= max_offchip_buffers
;
3513 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
3514 if (device
->physical_device
->rad_info
.chip_class
>= GFX8
)
3515 --max_offchip_buffers
;
3517 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
3518 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
);
3521 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
);
3523 return hs_offchip_param
;
3527 radv_emit_gs_ring_sizes(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
3528 struct radeon_winsys_bo
*esgs_ring_bo
,
3529 uint32_t esgs_ring_size
,
3530 struct radeon_winsys_bo
*gsvs_ring_bo
,
3531 uint32_t gsvs_ring_size
)
3533 if (!esgs_ring_bo
&& !gsvs_ring_bo
)
3537 radv_cs_add_buffer(queue
->device
->ws
, cs
, esgs_ring_bo
);
3540 radv_cs_add_buffer(queue
->device
->ws
, cs
, gsvs_ring_bo
);
3542 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
3543 radeon_set_uconfig_reg_seq(cs
, R_030900_VGT_ESGS_RING_SIZE
, 2);
3544 radeon_emit(cs
, esgs_ring_size
>> 8);
3545 radeon_emit(cs
, gsvs_ring_size
>> 8);
3547 radeon_set_config_reg_seq(cs
, R_0088C8_VGT_ESGS_RING_SIZE
, 2);
3548 radeon_emit(cs
, esgs_ring_size
>> 8);
3549 radeon_emit(cs
, gsvs_ring_size
>> 8);
3554 radv_emit_tess_factor_ring(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
3555 unsigned hs_offchip_param
, unsigned tf_ring_size
,
3556 struct radeon_winsys_bo
*tess_rings_bo
)
3563 tf_va
= radv_buffer_get_va(tess_rings_bo
);
3565 radv_cs_add_buffer(queue
->device
->ws
, cs
, tess_rings_bo
);
3567 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
3568 radeon_set_uconfig_reg(cs
, R_030938_VGT_TF_RING_SIZE
,
3569 S_030938_SIZE(tf_ring_size
/ 4));
3570 radeon_set_uconfig_reg(cs
, R_030940_VGT_TF_MEMORY_BASE
,
3573 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3574 radeon_set_uconfig_reg(cs
, R_030984_VGT_TF_MEMORY_BASE_HI_UMD
,
3575 S_030984_BASE_HI(tf_va
>> 40));
3576 } else if (queue
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
3577 radeon_set_uconfig_reg(cs
, R_030944_VGT_TF_MEMORY_BASE_HI
,
3578 S_030944_BASE_HI(tf_va
>> 40));
3580 radeon_set_uconfig_reg(cs
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
3583 radeon_set_config_reg(cs
, R_008988_VGT_TF_RING_SIZE
,
3584 S_008988_SIZE(tf_ring_size
/ 4));
3585 radeon_set_config_reg(cs
, R_0089B8_VGT_TF_MEMORY_BASE
,
3587 radeon_set_config_reg(cs
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
3593 radv_emit_graphics_scratch(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
3594 uint32_t size_per_wave
, uint32_t waves
,
3595 struct radeon_winsys_bo
*scratch_bo
)
3597 if (queue
->queue_family_index
!= RADV_QUEUE_GENERAL
)
3603 radv_cs_add_buffer(queue
->device
->ws
, cs
, scratch_bo
);
3605 radeon_set_context_reg(cs
, R_0286E8_SPI_TMPRING_SIZE
,
3606 S_0286E8_WAVES(waves
) |
3607 S_0286E8_WAVESIZE(round_up_u32(size_per_wave
, 1024)));
3611 radv_emit_compute_scratch(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
3612 uint32_t size_per_wave
, uint32_t waves
,
3613 struct radeon_winsys_bo
*compute_scratch_bo
)
3615 uint64_t scratch_va
;
3617 if (!compute_scratch_bo
)
3620 scratch_va
= radv_buffer_get_va(compute_scratch_bo
);
3622 radv_cs_add_buffer(queue
->device
->ws
, cs
, compute_scratch_bo
);
3624 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
, 2);
3625 radeon_emit(cs
, scratch_va
);
3626 radeon_emit(cs
, S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
3627 S_008F04_SWIZZLE_ENABLE(1));
3629 radeon_set_sh_reg(cs
, R_00B860_COMPUTE_TMPRING_SIZE
,
3630 S_00B860_WAVES(waves
) |
3631 S_00B860_WAVESIZE(round_up_u32(size_per_wave
, 1024)));
3635 radv_emit_global_shader_pointers(struct radv_queue
*queue
,
3636 struct radeon_cmdbuf
*cs
,
3637 struct radeon_winsys_bo
*descriptor_bo
)
3644 va
= radv_buffer_get_va(descriptor_bo
);
3646 radv_cs_add_buffer(queue
->device
->ws
, cs
, descriptor_bo
);
3648 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3649 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
3650 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
3651 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
,
3652 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
};
3654 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
3655 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
3658 } else if (queue
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
3659 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
3660 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
3661 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
,
3662 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
};
3664 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
3665 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
3669 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
3670 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
3671 R_00B230_SPI_SHADER_USER_DATA_GS_0
,
3672 R_00B330_SPI_SHADER_USER_DATA_ES_0
,
3673 R_00B430_SPI_SHADER_USER_DATA_HS_0
,
3674 R_00B530_SPI_SHADER_USER_DATA_LS_0
};
3676 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
3677 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
3684 radv_init_graphics_state(struct radeon_cmdbuf
*cs
, struct radv_queue
*queue
)
3686 struct radv_device
*device
= queue
->device
;
3688 if (device
->gfx_init
) {
3689 uint64_t va
= radv_buffer_get_va(device
->gfx_init
);
3691 radeon_emit(cs
, PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0));
3692 radeon_emit(cs
, va
);
3693 radeon_emit(cs
, va
>> 32);
3694 radeon_emit(cs
, device
->gfx_init_size_dw
& 0xffff);
3696 radv_cs_add_buffer(device
->ws
, cs
, device
->gfx_init
);
3698 struct radv_physical_device
*physical_device
= device
->physical_device
;
3699 si_emit_graphics(physical_device
, cs
);
3704 radv_init_compute_state(struct radeon_cmdbuf
*cs
, struct radv_queue
*queue
)
3706 struct radv_physical_device
*physical_device
= queue
->device
->physical_device
;
3707 si_emit_compute(physical_device
, cs
);
3711 radv_get_preamble_cs(struct radv_queue
*queue
,
3712 uint32_t scratch_size_per_wave
,
3713 uint32_t scratch_waves
,
3714 uint32_t compute_scratch_size_per_wave
,
3715 uint32_t compute_scratch_waves
,
3716 uint32_t esgs_ring_size
,
3717 uint32_t gsvs_ring_size
,
3718 bool needs_tess_rings
,
3721 bool needs_sample_positions
,
3722 struct radeon_cmdbuf
**initial_full_flush_preamble_cs
,
3723 struct radeon_cmdbuf
**initial_preamble_cs
,
3724 struct radeon_cmdbuf
**continue_preamble_cs
)
3726 struct radeon_winsys_bo
*scratch_bo
= NULL
;
3727 struct radeon_winsys_bo
*descriptor_bo
= NULL
;
3728 struct radeon_winsys_bo
*compute_scratch_bo
= NULL
;
3729 struct radeon_winsys_bo
*esgs_ring_bo
= NULL
;
3730 struct radeon_winsys_bo
*gsvs_ring_bo
= NULL
;
3731 struct radeon_winsys_bo
*tess_rings_bo
= NULL
;
3732 struct radeon_winsys_bo
*gds_bo
= NULL
;
3733 struct radeon_winsys_bo
*gds_oa_bo
= NULL
;
3734 struct radeon_cmdbuf
*dest_cs
[3] = {0};
3735 bool add_tess_rings
= false, add_gds
= false, add_gds_oa
= false, add_sample_positions
= false;
3736 unsigned tess_factor_ring_size
= 0, tess_offchip_ring_size
= 0;
3737 unsigned max_offchip_buffers
;
3738 unsigned hs_offchip_param
= 0;
3739 unsigned tess_offchip_ring_offset
;
3740 uint32_t ring_bo_flags
= RADEON_FLAG_NO_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
;
3741 if (!queue
->has_tess_rings
) {
3742 if (needs_tess_rings
)
3743 add_tess_rings
= true;
3745 if (!queue
->has_gds
) {
3749 if (!queue
->has_gds_oa
) {
3753 if (!queue
->has_sample_positions
) {
3754 if (needs_sample_positions
)
3755 add_sample_positions
= true;
3757 tess_factor_ring_size
= 32768 * queue
->device
->physical_device
->rad_info
.max_se
;
3758 hs_offchip_param
= radv_get_hs_offchip_param(queue
->device
,
3759 &max_offchip_buffers
);
3760 tess_offchip_ring_offset
= align(tess_factor_ring_size
, 64 * 1024);
3761 tess_offchip_ring_size
= max_offchip_buffers
*
3762 queue
->device
->tess_offchip_block_dw_size
* 4;
3764 scratch_size_per_wave
= MAX2(scratch_size_per_wave
, queue
->scratch_size_per_wave
);
3765 if (scratch_size_per_wave
)
3766 scratch_waves
= MIN2(scratch_waves
, UINT32_MAX
/ scratch_size_per_wave
);
3770 compute_scratch_size_per_wave
= MAX2(compute_scratch_size_per_wave
, queue
->compute_scratch_size_per_wave
);
3771 if (compute_scratch_size_per_wave
)
3772 compute_scratch_waves
= MIN2(compute_scratch_waves
, UINT32_MAX
/ compute_scratch_size_per_wave
);
3774 compute_scratch_waves
= 0;
3776 if (scratch_size_per_wave
<= queue
->scratch_size_per_wave
&&
3777 scratch_waves
<= queue
->scratch_waves
&&
3778 compute_scratch_size_per_wave
<= queue
->compute_scratch_size_per_wave
&&
3779 compute_scratch_waves
<= queue
->compute_scratch_waves
&&
3780 esgs_ring_size
<= queue
->esgs_ring_size
&&
3781 gsvs_ring_size
<= queue
->gsvs_ring_size
&&
3782 !add_tess_rings
&& !add_gds
&& !add_gds_oa
&& !add_sample_positions
&&
3783 queue
->initial_preamble_cs
) {
3784 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
3785 *initial_preamble_cs
= queue
->initial_preamble_cs
;
3786 *continue_preamble_cs
= queue
->continue_preamble_cs
;
3787 if (!scratch_size_per_wave
&& !compute_scratch_size_per_wave
&&
3788 !esgs_ring_size
&& !gsvs_ring_size
&& !needs_tess_rings
&&
3789 !needs_gds
&& !needs_gds_oa
&& !needs_sample_positions
)
3790 *continue_preamble_cs
= NULL
;
3794 uint32_t scratch_size
= scratch_size_per_wave
* scratch_waves
;
3795 uint32_t queue_scratch_size
= queue
->scratch_size_per_wave
* queue
->scratch_waves
;
3796 if (scratch_size
> queue_scratch_size
) {
3797 scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3802 RADV_BO_PRIORITY_SCRATCH
);
3806 scratch_bo
= queue
->scratch_bo
;
3808 uint32_t compute_scratch_size
= compute_scratch_size_per_wave
* compute_scratch_waves
;
3809 uint32_t compute_queue_scratch_size
= queue
->compute_scratch_size_per_wave
* queue
->compute_scratch_waves
;
3810 if (compute_scratch_size
> compute_queue_scratch_size
) {
3811 compute_scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3812 compute_scratch_size
,
3816 RADV_BO_PRIORITY_SCRATCH
);
3817 if (!compute_scratch_bo
)
3821 compute_scratch_bo
= queue
->compute_scratch_bo
;
3823 if (esgs_ring_size
> queue
->esgs_ring_size
) {
3824 esgs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3829 RADV_BO_PRIORITY_SCRATCH
);
3833 esgs_ring_bo
= queue
->esgs_ring_bo
;
3834 esgs_ring_size
= queue
->esgs_ring_size
;
3837 if (gsvs_ring_size
> queue
->gsvs_ring_size
) {
3838 gsvs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3843 RADV_BO_PRIORITY_SCRATCH
);
3847 gsvs_ring_bo
= queue
->gsvs_ring_bo
;
3848 gsvs_ring_size
= queue
->gsvs_ring_size
;
3851 if (add_tess_rings
) {
3852 tess_rings_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3853 tess_offchip_ring_offset
+ tess_offchip_ring_size
,
3857 RADV_BO_PRIORITY_SCRATCH
);
3861 tess_rings_bo
= queue
->tess_rings_bo
;
3865 assert(queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
);
3867 /* 4 streamout GDS counters.
3868 * We need 256B (64 dw) of GDS, otherwise streamout hangs.
3870 gds_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3874 RADV_BO_PRIORITY_SCRATCH
);
3878 gds_bo
= queue
->gds_bo
;
3882 assert(queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
);
3884 gds_oa_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3888 RADV_BO_PRIORITY_SCRATCH
);
3892 gds_oa_bo
= queue
->gds_oa_bo
;
3895 if (scratch_bo
!= queue
->scratch_bo
||
3896 esgs_ring_bo
!= queue
->esgs_ring_bo
||
3897 gsvs_ring_bo
!= queue
->gsvs_ring_bo
||
3898 tess_rings_bo
!= queue
->tess_rings_bo
||
3899 add_sample_positions
) {
3901 if (gsvs_ring_bo
|| esgs_ring_bo
||
3902 tess_rings_bo
|| add_sample_positions
) {
3903 size
= 112; /* 2 dword + 2 padding + 4 dword * 6 */
3904 if (add_sample_positions
)
3905 size
+= 128; /* 64+32+16+8 = 120 bytes */
3907 else if (scratch_bo
)
3908 size
= 8; /* 2 dword */
3910 descriptor_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3914 RADEON_FLAG_CPU_ACCESS
|
3915 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
3916 RADEON_FLAG_READ_ONLY
,
3917 RADV_BO_PRIORITY_DESCRIPTOR
);
3921 descriptor_bo
= queue
->descriptor_bo
;
3923 if (descriptor_bo
!= queue
->descriptor_bo
) {
3924 uint32_t *map
= (uint32_t*)queue
->device
->ws
->buffer_map(descriptor_bo
);
3927 uint64_t scratch_va
= radv_buffer_get_va(scratch_bo
);
3928 uint32_t rsrc1
= S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
3929 S_008F04_SWIZZLE_ENABLE(1);
3930 map
[0] = scratch_va
;
3934 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_rings_bo
|| add_sample_positions
)
3935 fill_geom_tess_rings(queue
, map
, add_sample_positions
,
3936 esgs_ring_size
, esgs_ring_bo
,
3937 gsvs_ring_size
, gsvs_ring_bo
,
3938 tess_factor_ring_size
,
3939 tess_offchip_ring_offset
,
3940 tess_offchip_ring_size
,
3943 queue
->device
->ws
->buffer_unmap(descriptor_bo
);
3946 for(int i
= 0; i
< 3; ++i
) {
3947 struct radeon_cmdbuf
*cs
= NULL
;
3948 cs
= queue
->device
->ws
->cs_create(queue
->device
->ws
,
3949 queue
->queue_family_index
? RING_COMPUTE
: RING_GFX
);
3956 radv_cs_add_buffer(queue
->device
->ws
, cs
, scratch_bo
);
3958 /* Emit initial configuration. */
3959 switch (queue
->queue_family_index
) {
3960 case RADV_QUEUE_GENERAL
:
3961 radv_init_graphics_state(cs
, queue
);
3963 case RADV_QUEUE_COMPUTE
:
3964 radv_init_compute_state(cs
, queue
);
3966 case RADV_QUEUE_TRANSFER
:
3970 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_rings_bo
) {
3971 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3972 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
3974 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3975 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
3978 radv_emit_gs_ring_sizes(queue
, cs
, esgs_ring_bo
, esgs_ring_size
,
3979 gsvs_ring_bo
, gsvs_ring_size
);
3980 radv_emit_tess_factor_ring(queue
, cs
, hs_offchip_param
,
3981 tess_factor_ring_size
, tess_rings_bo
);
3982 radv_emit_global_shader_pointers(queue
, cs
, descriptor_bo
);
3983 radv_emit_compute_scratch(queue
, cs
, compute_scratch_size_per_wave
,
3984 compute_scratch_waves
, compute_scratch_bo
);
3985 radv_emit_graphics_scratch(queue
, cs
, scratch_size_per_wave
,
3986 scratch_waves
, scratch_bo
);
3989 radv_cs_add_buffer(queue
->device
->ws
, cs
, gds_bo
);
3991 radv_cs_add_buffer(queue
->device
->ws
, cs
, gds_oa_bo
);
3993 if (queue
->device
->trace_bo
)
3994 radv_cs_add_buffer(queue
->device
->ws
, cs
, queue
->device
->trace_bo
);
3997 si_cs_emit_cache_flush(cs
,
3998 queue
->device
->physical_device
->rad_info
.chip_class
,
4000 queue
->queue_family_index
== RING_COMPUTE
&&
4001 queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
,
4002 (queue
->queue_family_index
== RADV_QUEUE_COMPUTE
? RADV_CMD_FLAG_CS_PARTIAL_FLUSH
: (RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
)) |
4003 RADV_CMD_FLAG_INV_ICACHE
|
4004 RADV_CMD_FLAG_INV_SCACHE
|
4005 RADV_CMD_FLAG_INV_VCACHE
|
4006 RADV_CMD_FLAG_INV_L2
|
4007 RADV_CMD_FLAG_START_PIPELINE_STATS
, 0);
4008 } else if (i
== 1) {
4009 si_cs_emit_cache_flush(cs
,
4010 queue
->device
->physical_device
->rad_info
.chip_class
,
4012 queue
->queue_family_index
== RING_COMPUTE
&&
4013 queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
,
4014 RADV_CMD_FLAG_INV_ICACHE
|
4015 RADV_CMD_FLAG_INV_SCACHE
|
4016 RADV_CMD_FLAG_INV_VCACHE
|
4017 RADV_CMD_FLAG_INV_L2
|
4018 RADV_CMD_FLAG_START_PIPELINE_STATS
, 0);
4021 if (!queue
->device
->ws
->cs_finalize(cs
))
4025 if (queue
->initial_full_flush_preamble_cs
)
4026 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
4028 if (queue
->initial_preamble_cs
)
4029 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
4031 if (queue
->continue_preamble_cs
)
4032 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
4034 queue
->initial_full_flush_preamble_cs
= dest_cs
[0];
4035 queue
->initial_preamble_cs
= dest_cs
[1];
4036 queue
->continue_preamble_cs
= dest_cs
[2];
4038 if (scratch_bo
!= queue
->scratch_bo
) {
4039 if (queue
->scratch_bo
)
4040 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
4041 queue
->scratch_bo
= scratch_bo
;
4043 queue
->scratch_size_per_wave
= scratch_size_per_wave
;
4044 queue
->scratch_waves
= scratch_waves
;
4046 if (compute_scratch_bo
!= queue
->compute_scratch_bo
) {
4047 if (queue
->compute_scratch_bo
)
4048 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
4049 queue
->compute_scratch_bo
= compute_scratch_bo
;
4051 queue
->compute_scratch_size_per_wave
= compute_scratch_size_per_wave
;
4052 queue
->compute_scratch_waves
= compute_scratch_waves
;
4054 if (esgs_ring_bo
!= queue
->esgs_ring_bo
) {
4055 if (queue
->esgs_ring_bo
)
4056 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
4057 queue
->esgs_ring_bo
= esgs_ring_bo
;
4058 queue
->esgs_ring_size
= esgs_ring_size
;
4061 if (gsvs_ring_bo
!= queue
->gsvs_ring_bo
) {
4062 if (queue
->gsvs_ring_bo
)
4063 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
4064 queue
->gsvs_ring_bo
= gsvs_ring_bo
;
4065 queue
->gsvs_ring_size
= gsvs_ring_size
;
4068 if (tess_rings_bo
!= queue
->tess_rings_bo
) {
4069 queue
->tess_rings_bo
= tess_rings_bo
;
4070 queue
->has_tess_rings
= true;
4073 if (gds_bo
!= queue
->gds_bo
) {
4074 queue
->gds_bo
= gds_bo
;
4075 queue
->has_gds
= true;
4078 if (gds_oa_bo
!= queue
->gds_oa_bo
) {
4079 queue
->gds_oa_bo
= gds_oa_bo
;
4080 queue
->has_gds_oa
= true;
4083 if (descriptor_bo
!= queue
->descriptor_bo
) {
4084 if (queue
->descriptor_bo
)
4085 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
4087 queue
->descriptor_bo
= descriptor_bo
;
4090 if (add_sample_positions
)
4091 queue
->has_sample_positions
= true;
4093 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
4094 *initial_preamble_cs
= queue
->initial_preamble_cs
;
4095 *continue_preamble_cs
= queue
->continue_preamble_cs
;
4096 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
4097 *continue_preamble_cs
= NULL
;
4100 for (int i
= 0; i
< ARRAY_SIZE(dest_cs
); ++i
)
4102 queue
->device
->ws
->cs_destroy(dest_cs
[i
]);
4103 if (descriptor_bo
&& descriptor_bo
!= queue
->descriptor_bo
)
4104 queue
->device
->ws
->buffer_destroy(descriptor_bo
);
4105 if (scratch_bo
&& scratch_bo
!= queue
->scratch_bo
)
4106 queue
->device
->ws
->buffer_destroy(scratch_bo
);
4107 if (compute_scratch_bo
&& compute_scratch_bo
!= queue
->compute_scratch_bo
)
4108 queue
->device
->ws
->buffer_destroy(compute_scratch_bo
);
4109 if (esgs_ring_bo
&& esgs_ring_bo
!= queue
->esgs_ring_bo
)
4110 queue
->device
->ws
->buffer_destroy(esgs_ring_bo
);
4111 if (gsvs_ring_bo
&& gsvs_ring_bo
!= queue
->gsvs_ring_bo
)
4112 queue
->device
->ws
->buffer_destroy(gsvs_ring_bo
);
4113 if (tess_rings_bo
&& tess_rings_bo
!= queue
->tess_rings_bo
)
4114 queue
->device
->ws
->buffer_destroy(tess_rings_bo
);
4115 if (gds_bo
&& gds_bo
!= queue
->gds_bo
)
4116 queue
->device
->ws
->buffer_destroy(gds_bo
);
4117 if (gds_oa_bo
&& gds_oa_bo
!= queue
->gds_oa_bo
)
4118 queue
->device
->ws
->buffer_destroy(gds_oa_bo
);
4120 return vk_error(queue
->device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
4123 static VkResult
radv_alloc_sem_counts(struct radv_device
*device
,
4124 struct radv_winsys_sem_counts
*counts
,
4126 struct radv_semaphore_part
**sems
,
4127 const uint64_t *timeline_values
,
4131 int syncobj_idx
= 0, sem_idx
= 0;
4133 if (num_sems
== 0 && _fence
== VK_NULL_HANDLE
)
4136 for (uint32_t i
= 0; i
< num_sems
; i
++) {
4137 switch(sems
[i
]->kind
) {
4138 case RADV_SEMAPHORE_SYNCOBJ
:
4139 counts
->syncobj_count
++;
4141 case RADV_SEMAPHORE_WINSYS
:
4142 counts
->sem_count
++;
4144 case RADV_SEMAPHORE_NONE
:
4146 case RADV_SEMAPHORE_TIMELINE
:
4147 counts
->syncobj_count
++;
4152 if (_fence
!= VK_NULL_HANDLE
) {
4153 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
4154 if (fence
->temp_syncobj
|| fence
->syncobj
)
4155 counts
->syncobj_count
++;
4158 if (counts
->syncobj_count
) {
4159 counts
->syncobj
= (uint32_t *)malloc(sizeof(uint32_t) * counts
->syncobj_count
);
4160 if (!counts
->syncobj
)
4161 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4164 if (counts
->sem_count
) {
4165 counts
->sem
= (struct radeon_winsys_sem
**)malloc(sizeof(struct radeon_winsys_sem
*) * counts
->sem_count
);
4167 free(counts
->syncobj
);
4168 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4172 for (uint32_t i
= 0; i
< num_sems
; i
++) {
4173 switch(sems
[i
]->kind
) {
4174 case RADV_SEMAPHORE_NONE
:
4175 unreachable("Empty semaphore");
4177 case RADV_SEMAPHORE_SYNCOBJ
:
4178 counts
->syncobj
[syncobj_idx
++] = sems
[i
]->syncobj
;
4180 case RADV_SEMAPHORE_WINSYS
:
4181 counts
->sem
[sem_idx
++] = sems
[i
]->ws_sem
;
4183 case RADV_SEMAPHORE_TIMELINE
: {
4184 pthread_mutex_lock(&sems
[i
]->timeline
.mutex
);
4185 struct radv_timeline_point
*point
= NULL
;
4187 point
= radv_timeline_add_point_locked(device
, &sems
[i
]->timeline
, timeline_values
[i
]);
4189 point
= radv_timeline_find_point_at_least_locked(device
, &sems
[i
]->timeline
, timeline_values
[i
]);
4192 pthread_mutex_unlock(&sems
[i
]->timeline
.mutex
);
4195 counts
->syncobj
[syncobj_idx
++] = point
->syncobj
;
4197 /* Explicitly remove the semaphore so we might not find
4198 * a point later post-submit. */
4206 if (_fence
!= VK_NULL_HANDLE
) {
4207 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
4208 if (fence
->temp_syncobj
)
4209 counts
->syncobj
[syncobj_idx
++] = fence
->temp_syncobj
;
4210 else if (fence
->syncobj
)
4211 counts
->syncobj
[syncobj_idx
++] = fence
->syncobj
;
4214 assert(syncobj_idx
<= counts
->syncobj_count
);
4215 counts
->syncobj_count
= syncobj_idx
;
4221 radv_free_sem_info(struct radv_winsys_sem_info
*sem_info
)
4223 free(sem_info
->wait
.syncobj
);
4224 free(sem_info
->wait
.sem
);
4225 free(sem_info
->signal
.syncobj
);
4226 free(sem_info
->signal
.sem
);
4230 static void radv_free_temp_syncobjs(struct radv_device
*device
,
4232 struct radv_semaphore_part
*sems
)
4234 for (uint32_t i
= 0; i
< num_sems
; i
++) {
4235 radv_destroy_semaphore_part(device
, sems
+ i
);
4240 radv_alloc_sem_info(struct radv_device
*device
,
4241 struct radv_winsys_sem_info
*sem_info
,
4243 struct radv_semaphore_part
**wait_sems
,
4244 const uint64_t *wait_values
,
4245 int num_signal_sems
,
4246 struct radv_semaphore_part
**signal_sems
,
4247 const uint64_t *signal_values
,
4251 memset(sem_info
, 0, sizeof(*sem_info
));
4253 ret
= radv_alloc_sem_counts(device
, &sem_info
->wait
, num_wait_sems
, wait_sems
, wait_values
, VK_NULL_HANDLE
, false);
4256 ret
= radv_alloc_sem_counts(device
, &sem_info
->signal
, num_signal_sems
, signal_sems
, signal_values
, fence
, true);
4258 radv_free_sem_info(sem_info
);
4260 /* caller can override these */
4261 sem_info
->cs_emit_wait
= true;
4262 sem_info
->cs_emit_signal
= true;
4267 radv_finalize_timelines(struct radv_device
*device
,
4268 uint32_t num_wait_sems
,
4269 struct radv_semaphore_part
**wait_sems
,
4270 const uint64_t *wait_values
,
4271 uint32_t num_signal_sems
,
4272 struct radv_semaphore_part
**signal_sems
,
4273 const uint64_t *signal_values
,
4274 struct list_head
*processing_list
)
4276 for (uint32_t i
= 0; i
< num_wait_sems
; ++i
) {
4277 if (wait_sems
[i
] && wait_sems
[i
]->kind
== RADV_SEMAPHORE_TIMELINE
) {
4278 pthread_mutex_lock(&wait_sems
[i
]->timeline
.mutex
);
4279 struct radv_timeline_point
*point
=
4280 radv_timeline_find_point_at_least_locked(device
, &wait_sems
[i
]->timeline
, wait_values
[i
]);
4281 point
->wait_count
-= 2;
4282 pthread_mutex_unlock(&wait_sems
[i
]->timeline
.mutex
);
4285 for (uint32_t i
= 0; i
< num_signal_sems
; ++i
) {
4286 if (signal_sems
[i
] && signal_sems
[i
]->kind
== RADV_SEMAPHORE_TIMELINE
) {
4287 pthread_mutex_lock(&signal_sems
[i
]->timeline
.mutex
);
4288 struct radv_timeline_point
*point
=
4289 radv_timeline_find_point_at_least_locked(device
, &signal_sems
[i
]->timeline
, signal_values
[i
]);
4290 signal_sems
[i
]->timeline
.highest_submitted
=
4291 MAX2(signal_sems
[i
]->timeline
.highest_submitted
, point
->value
);
4292 point
->wait_count
-= 2;
4293 radv_timeline_trigger_waiters_locked(&signal_sems
[i
]->timeline
, processing_list
);
4294 pthread_mutex_unlock(&signal_sems
[i
]->timeline
.mutex
);
4300 radv_sparse_buffer_bind_memory(struct radv_device
*device
,
4301 const VkSparseBufferMemoryBindInfo
*bind
)
4303 RADV_FROM_HANDLE(radv_buffer
, buffer
, bind
->buffer
);
4305 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
4306 struct radv_device_memory
*mem
= NULL
;
4308 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
4309 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
4311 device
->ws
->buffer_virtual_bind(buffer
->bo
,
4312 bind
->pBinds
[i
].resourceOffset
,
4313 bind
->pBinds
[i
].size
,
4314 mem
? mem
->bo
: NULL
,
4315 bind
->pBinds
[i
].memoryOffset
);
4320 radv_sparse_image_opaque_bind_memory(struct radv_device
*device
,
4321 const VkSparseImageOpaqueMemoryBindInfo
*bind
)
4323 RADV_FROM_HANDLE(radv_image
, image
, bind
->image
);
4325 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
4326 struct radv_device_memory
*mem
= NULL
;
4328 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
4329 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
4331 device
->ws
->buffer_virtual_bind(image
->bo
,
4332 bind
->pBinds
[i
].resourceOffset
,
4333 bind
->pBinds
[i
].size
,
4334 mem
? mem
->bo
: NULL
,
4335 bind
->pBinds
[i
].memoryOffset
);
4340 radv_get_preambles(struct radv_queue
*queue
,
4341 const VkCommandBuffer
*cmd_buffers
,
4342 uint32_t cmd_buffer_count
,
4343 struct radeon_cmdbuf
**initial_full_flush_preamble_cs
,
4344 struct radeon_cmdbuf
**initial_preamble_cs
,
4345 struct radeon_cmdbuf
**continue_preamble_cs
)
4347 uint32_t scratch_size_per_wave
= 0, waves_wanted
= 0;
4348 uint32_t compute_scratch_size_per_wave
= 0, compute_waves_wanted
= 0;
4349 uint32_t esgs_ring_size
= 0, gsvs_ring_size
= 0;
4350 bool tess_rings_needed
= false;
4351 bool gds_needed
= false;
4352 bool gds_oa_needed
= false;
4353 bool sample_positions_needed
= false;
4355 for (uint32_t j
= 0; j
< cmd_buffer_count
; j
++) {
4356 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
4359 scratch_size_per_wave
= MAX2(scratch_size_per_wave
, cmd_buffer
->scratch_size_per_wave_needed
);
4360 waves_wanted
= MAX2(waves_wanted
, cmd_buffer
->scratch_waves_wanted
);
4361 compute_scratch_size_per_wave
= MAX2(compute_scratch_size_per_wave
,
4362 cmd_buffer
->compute_scratch_size_per_wave_needed
);
4363 compute_waves_wanted
= MAX2(compute_waves_wanted
,
4364 cmd_buffer
->compute_scratch_waves_wanted
);
4365 esgs_ring_size
= MAX2(esgs_ring_size
, cmd_buffer
->esgs_ring_size_needed
);
4366 gsvs_ring_size
= MAX2(gsvs_ring_size
, cmd_buffer
->gsvs_ring_size_needed
);
4367 tess_rings_needed
|= cmd_buffer
->tess_rings_needed
;
4368 gds_needed
|= cmd_buffer
->gds_needed
;
4369 gds_oa_needed
|= cmd_buffer
->gds_oa_needed
;
4370 sample_positions_needed
|= cmd_buffer
->sample_positions_needed
;
4373 return radv_get_preamble_cs(queue
, scratch_size_per_wave
, waves_wanted
,
4374 compute_scratch_size_per_wave
, compute_waves_wanted
,
4375 esgs_ring_size
, gsvs_ring_size
, tess_rings_needed
,
4376 gds_needed
, gds_oa_needed
, sample_positions_needed
,
4377 initial_full_flush_preamble_cs
,
4378 initial_preamble_cs
, continue_preamble_cs
);
4381 struct radv_deferred_queue_submission
{
4382 struct radv_queue
*queue
;
4383 VkCommandBuffer
*cmd_buffers
;
4384 uint32_t cmd_buffer_count
;
4386 /* Sparse bindings that happen on a queue. */
4387 VkSparseBufferMemoryBindInfo
*buffer_binds
;
4388 uint32_t buffer_bind_count
;
4389 VkSparseImageOpaqueMemoryBindInfo
*image_opaque_binds
;
4390 uint32_t image_opaque_bind_count
;
4393 VkShaderStageFlags wait_dst_stage_mask
;
4394 struct radv_semaphore_part
**wait_semaphores
;
4395 uint32_t wait_semaphore_count
;
4396 struct radv_semaphore_part
**signal_semaphores
;
4397 uint32_t signal_semaphore_count
;
4400 uint64_t *wait_values
;
4401 uint64_t *signal_values
;
4403 struct radv_semaphore_part
*temporary_semaphore_parts
;
4404 uint32_t temporary_semaphore_part_count
;
4406 struct list_head queue_pending_list
;
4407 uint32_t submission_wait_count
;
4408 struct radv_timeline_waiter
*wait_nodes
;
4410 struct list_head processing_list
;
4413 struct radv_queue_submission
{
4414 const VkCommandBuffer
*cmd_buffers
;
4415 uint32_t cmd_buffer_count
;
4417 /* Sparse bindings that happen on a queue. */
4418 const VkSparseBufferMemoryBindInfo
*buffer_binds
;
4419 uint32_t buffer_bind_count
;
4420 const VkSparseImageOpaqueMemoryBindInfo
*image_opaque_binds
;
4421 uint32_t image_opaque_bind_count
;
4424 VkPipelineStageFlags wait_dst_stage_mask
;
4425 const VkSemaphore
*wait_semaphores
;
4426 uint32_t wait_semaphore_count
;
4427 const VkSemaphore
*signal_semaphores
;
4428 uint32_t signal_semaphore_count
;
4431 const uint64_t *wait_values
;
4432 uint32_t wait_value_count
;
4433 const uint64_t *signal_values
;
4434 uint32_t signal_value_count
;
4438 radv_create_deferred_submission(struct radv_queue
*queue
,
4439 const struct radv_queue_submission
*submission
,
4440 struct radv_deferred_queue_submission
**out
)
4442 struct radv_deferred_queue_submission
*deferred
= NULL
;
4443 size_t size
= sizeof(struct radv_deferred_queue_submission
);
4445 uint32_t temporary_count
= 0;
4446 for (uint32_t i
= 0; i
< submission
->wait_semaphore_count
; ++i
) {
4447 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, submission
->wait_semaphores
[i
]);
4448 if (semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
)
4452 size
+= submission
->cmd_buffer_count
* sizeof(VkCommandBuffer
);
4453 size
+= submission
->buffer_bind_count
* sizeof(VkSparseBufferMemoryBindInfo
);
4454 size
+= submission
->image_opaque_bind_count
* sizeof(VkSparseImageOpaqueMemoryBindInfo
);
4455 size
+= submission
->wait_semaphore_count
* sizeof(struct radv_semaphore_part
*);
4456 size
+= temporary_count
* sizeof(struct radv_semaphore_part
);
4457 size
+= submission
->signal_semaphore_count
* sizeof(struct radv_semaphore_part
*);
4458 size
+= submission
->wait_value_count
* sizeof(uint64_t);
4459 size
+= submission
->signal_value_count
* sizeof(uint64_t);
4460 size
+= submission
->wait_semaphore_count
* sizeof(struct radv_timeline_waiter
);
4462 deferred
= calloc(1, size
);
4464 return VK_ERROR_OUT_OF_HOST_MEMORY
;
4466 deferred
->queue
= queue
;
4468 deferred
->cmd_buffers
= (void*)(deferred
+ 1);
4469 deferred
->cmd_buffer_count
= submission
->cmd_buffer_count
;
4470 memcpy(deferred
->cmd_buffers
, submission
->cmd_buffers
,
4471 submission
->cmd_buffer_count
* sizeof(*deferred
->cmd_buffers
));
4473 deferred
->buffer_binds
= (void*)(deferred
->cmd_buffers
+ submission
->cmd_buffer_count
);
4474 deferred
->buffer_bind_count
= submission
->buffer_bind_count
;
4475 memcpy(deferred
->buffer_binds
, submission
->buffer_binds
,
4476 submission
->buffer_bind_count
* sizeof(*deferred
->buffer_binds
));
4478 deferred
->image_opaque_binds
= (void*)(deferred
->buffer_binds
+ submission
->buffer_bind_count
);
4479 deferred
->image_opaque_bind_count
= submission
->image_opaque_bind_count
;
4480 memcpy(deferred
->image_opaque_binds
, submission
->image_opaque_binds
,
4481 submission
->image_opaque_bind_count
* sizeof(*deferred
->image_opaque_binds
));
4483 deferred
->flush_caches
= submission
->flush_caches
;
4484 deferred
->wait_dst_stage_mask
= submission
->wait_dst_stage_mask
;
4486 deferred
->wait_semaphores
= (void*)(deferred
->image_opaque_binds
+ deferred
->image_opaque_bind_count
);
4487 deferred
->wait_semaphore_count
= submission
->wait_semaphore_count
;
4489 deferred
->signal_semaphores
= (void*)(deferred
->wait_semaphores
+ deferred
->wait_semaphore_count
);
4490 deferred
->signal_semaphore_count
= submission
->signal_semaphore_count
;
4492 deferred
->fence
= submission
->fence
;
4494 deferred
->temporary_semaphore_parts
= (void*)(deferred
->signal_semaphores
+ deferred
->signal_semaphore_count
);
4495 deferred
->temporary_semaphore_part_count
= temporary_count
;
4497 uint32_t temporary_idx
= 0;
4498 for (uint32_t i
= 0; i
< submission
->wait_semaphore_count
; ++i
) {
4499 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, submission
->wait_semaphores
[i
]);
4500 if (semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
) {
4501 deferred
->wait_semaphores
[i
] = &deferred
->temporary_semaphore_parts
[temporary_idx
];
4502 deferred
->temporary_semaphore_parts
[temporary_idx
] = semaphore
->temporary
;
4503 semaphore
->temporary
.kind
= RADV_SEMAPHORE_NONE
;
4506 deferred
->wait_semaphores
[i
] = &semaphore
->permanent
;
4509 for (uint32_t i
= 0; i
< submission
->signal_semaphore_count
; ++i
) {
4510 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, submission
->signal_semaphores
[i
]);
4511 if (semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
) {
4512 deferred
->signal_semaphores
[i
] = &semaphore
->temporary
;
4514 deferred
->signal_semaphores
[i
] = &semaphore
->permanent
;
4518 deferred
->wait_values
= (void*)(deferred
->temporary_semaphore_parts
+ temporary_count
);
4519 memcpy(deferred
->wait_values
, submission
->wait_values
, submission
->wait_value_count
* sizeof(uint64_t));
4520 deferred
->signal_values
= deferred
->wait_values
+ submission
->wait_value_count
;
4521 memcpy(deferred
->signal_values
, submission
->signal_values
, submission
->signal_value_count
* sizeof(uint64_t));
4523 deferred
->wait_nodes
= (void*)(deferred
->signal_values
+ submission
->signal_value_count
);
4524 /* This is worst-case. radv_queue_enqueue_submission will fill in further, but this
4525 * ensure the submission is not accidentally triggered early when adding wait timelines. */
4526 deferred
->submission_wait_count
= 1 + submission
->wait_semaphore_count
;
4533 radv_queue_enqueue_submission(struct radv_deferred_queue_submission
*submission
,
4534 struct list_head
*processing_list
)
4536 uint32_t wait_cnt
= 0;
4537 struct radv_timeline_waiter
*waiter
= submission
->wait_nodes
;
4538 for (uint32_t i
= 0; i
< submission
->wait_semaphore_count
; ++i
) {
4539 if (submission
->wait_semaphores
[i
]->kind
== RADV_SEMAPHORE_TIMELINE
) {
4540 pthread_mutex_lock(&submission
->wait_semaphores
[i
]->timeline
.mutex
);
4541 if (submission
->wait_semaphores
[i
]->timeline
.highest_submitted
< submission
->wait_values
[i
]) {
4543 waiter
->value
= submission
->wait_values
[i
];
4544 waiter
->submission
= submission
;
4545 list_addtail(&waiter
->list
, &submission
->wait_semaphores
[i
]->timeline
.waiters
);
4548 pthread_mutex_unlock(&submission
->wait_semaphores
[i
]->timeline
.mutex
);
4552 pthread_mutex_lock(&submission
->queue
->pending_mutex
);
4554 bool is_first
= list_is_empty(&submission
->queue
->pending_submissions
);
4555 list_addtail(&submission
->queue_pending_list
, &submission
->queue
->pending_submissions
);
4557 pthread_mutex_unlock(&submission
->queue
->pending_mutex
);
4559 /* If there is already a submission in the queue, that will decrement the counter by 1 when
4560 * submitted, but if the queue was empty, we decrement ourselves as there is no previous
4562 uint32_t decrement
= submission
->wait_semaphore_count
- wait_cnt
+ (is_first
? 1 : 0);
4563 if (__atomic_sub_fetch(&submission
->submission_wait_count
, decrement
, __ATOMIC_ACQ_REL
) == 0) {
4564 list_addtail(&submission
->processing_list
, processing_list
);
4569 radv_queue_submission_update_queue(struct radv_deferred_queue_submission
*submission
,
4570 struct list_head
*processing_list
)
4572 pthread_mutex_lock(&submission
->queue
->pending_mutex
);
4573 list_del(&submission
->queue_pending_list
);
4575 /* trigger the next submission in the queue. */
4576 if (!list_is_empty(&submission
->queue
->pending_submissions
)) {
4577 struct radv_deferred_queue_submission
*next_submission
=
4578 list_first_entry(&submission
->queue
->pending_submissions
,
4579 struct radv_deferred_queue_submission
,
4580 queue_pending_list
);
4581 if (p_atomic_dec_zero(&next_submission
->submission_wait_count
)) {
4582 list_addtail(&next_submission
->processing_list
, processing_list
);
4585 pthread_mutex_unlock(&submission
->queue
->pending_mutex
);
4587 pthread_cond_broadcast(&submission
->queue
->device
->timeline_cond
);
4591 radv_queue_submit_deferred(struct radv_deferred_queue_submission
*submission
,
4592 struct list_head
*processing_list
)
4594 RADV_FROM_HANDLE(radv_fence
, fence
, submission
->fence
);
4595 struct radv_queue
*queue
= submission
->queue
;
4596 struct radeon_winsys_ctx
*ctx
= queue
->hw_ctx
;
4597 uint32_t max_cs_submission
= queue
->device
->trace_bo
? 1 : RADV_MAX_IBS_PER_SUBMIT
;
4598 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
4599 bool do_flush
= submission
->flush_caches
|| submission
->wait_dst_stage_mask
;
4600 bool can_patch
= true;
4602 struct radv_winsys_sem_info sem_info
;
4605 struct radeon_cmdbuf
*initial_preamble_cs
= NULL
;
4606 struct radeon_cmdbuf
*initial_flush_preamble_cs
= NULL
;
4607 struct radeon_cmdbuf
*continue_preamble_cs
= NULL
;
4609 result
= radv_get_preambles(queue
, submission
->cmd_buffers
,
4610 submission
->cmd_buffer_count
,
4611 &initial_preamble_cs
,
4612 &initial_flush_preamble_cs
,
4613 &continue_preamble_cs
);
4614 if (result
!= VK_SUCCESS
)
4617 result
= radv_alloc_sem_info(queue
->device
,
4619 submission
->wait_semaphore_count
,
4620 submission
->wait_semaphores
,
4621 submission
->wait_values
,
4622 submission
->signal_semaphore_count
,
4623 submission
->signal_semaphores
,
4624 submission
->signal_values
,
4626 if (result
!= VK_SUCCESS
)
4629 for (uint32_t i
= 0; i
< submission
->buffer_bind_count
; ++i
) {
4630 radv_sparse_buffer_bind_memory(queue
->device
,
4631 submission
->buffer_binds
+ i
);
4634 for (uint32_t i
= 0; i
< submission
->image_opaque_bind_count
; ++i
) {
4635 radv_sparse_image_opaque_bind_memory(queue
->device
,
4636 submission
->image_opaque_binds
+ i
);
4639 if (!submission
->cmd_buffer_count
) {
4640 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
,
4641 &queue
->device
->empty_cs
[queue
->queue_family_index
],
4646 radv_loge("failed to submit CS\n");
4652 struct radeon_cmdbuf
**cs_array
= malloc(sizeof(struct radeon_cmdbuf
*) *
4653 (submission
->cmd_buffer_count
));
4655 for (uint32_t j
= 0; j
< submission
->cmd_buffer_count
; j
++) {
4656 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, submission
->cmd_buffers
[j
]);
4657 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
4659 cs_array
[j
] = cmd_buffer
->cs
;
4660 if ((cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT
))
4663 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_PENDING
;
4666 for (uint32_t j
= 0; j
< submission
->cmd_buffer_count
; j
+= advance
) {
4667 struct radeon_cmdbuf
*initial_preamble
= (do_flush
&& !j
) ? initial_flush_preamble_cs
: initial_preamble_cs
;
4668 const struct radv_winsys_bo_list
*bo_list
= NULL
;
4670 advance
= MIN2(max_cs_submission
,
4671 submission
->cmd_buffer_count
- j
);
4673 if (queue
->device
->trace_bo
)
4674 *queue
->device
->trace_id_ptr
= 0;
4676 sem_info
.cs_emit_wait
= j
== 0;
4677 sem_info
.cs_emit_signal
= j
+ advance
== submission
->cmd_buffer_count
;
4679 if (unlikely(queue
->device
->use_global_bo_list
)) {
4680 pthread_mutex_lock(&queue
->device
->bo_list
.mutex
);
4681 bo_list
= &queue
->device
->bo_list
.list
;
4684 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
, cs_array
+ j
,
4685 advance
, initial_preamble
, continue_preamble_cs
,
4687 can_patch
, base_fence
);
4689 if (unlikely(queue
->device
->use_global_bo_list
))
4690 pthread_mutex_unlock(&queue
->device
->bo_list
.mutex
);
4693 radv_loge("failed to submit CS\n");
4696 if (queue
->device
->trace_bo
) {
4697 radv_check_gpu_hangs(queue
, cs_array
[j
]);
4705 radv_free_temp_syncobjs(queue
->device
,
4706 submission
->temporary_semaphore_part_count
,
4707 submission
->temporary_semaphore_parts
);
4708 radv_finalize_timelines(queue
->device
,
4709 submission
->wait_semaphore_count
,
4710 submission
->wait_semaphores
,
4711 submission
->wait_values
,
4712 submission
->signal_semaphore_count
,
4713 submission
->signal_semaphores
,
4714 submission
->signal_values
,
4716 /* Has to happen after timeline finalization to make sure the
4717 * condition variable is only triggered when timelines and queue have
4719 radv_queue_submission_update_queue(submission
, processing_list
);
4720 radv_free_sem_info(&sem_info
);
4725 radv_free_temp_syncobjs(queue
->device
,
4726 submission
->temporary_semaphore_part_count
,
4727 submission
->temporary_semaphore_parts
);
4729 return VK_ERROR_DEVICE_LOST
;
4733 radv_process_submissions(struct list_head
*processing_list
)
4735 while(!list_is_empty(processing_list
)) {
4736 struct radv_deferred_queue_submission
*submission
=
4737 list_first_entry(processing_list
, struct radv_deferred_queue_submission
, processing_list
);
4738 list_del(&submission
->processing_list
);
4740 VkResult result
= radv_queue_submit_deferred(submission
, processing_list
);
4741 if (result
!= VK_SUCCESS
)
4747 static VkResult
radv_queue_submit(struct radv_queue
*queue
,
4748 const struct radv_queue_submission
*submission
)
4750 struct radv_deferred_queue_submission
*deferred
= NULL
;
4752 VkResult result
= radv_create_deferred_submission(queue
, submission
, &deferred
);
4753 if (result
!= VK_SUCCESS
)
4756 struct list_head processing_list
;
4757 list_inithead(&processing_list
);
4759 radv_queue_enqueue_submission(deferred
, &processing_list
);
4760 return radv_process_submissions(&processing_list
);
4764 radv_queue_internal_submit(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
)
4766 struct radeon_winsys_ctx
*ctx
= queue
->hw_ctx
;
4767 struct radv_winsys_sem_info sem_info
;
4771 result
= radv_alloc_sem_info(queue
->device
, &sem_info
, 0, NULL
, 0, 0,
4772 0, NULL
, VK_NULL_HANDLE
);
4773 if (result
!= VK_SUCCESS
)
4776 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
, &cs
, 1, NULL
,
4777 NULL
, &sem_info
, NULL
, false, NULL
);
4778 radv_free_sem_info(&sem_info
);
4782 /* Signals fence as soon as all the work currently put on queue is done. */
4783 static VkResult
radv_signal_fence(struct radv_queue
*queue
,
4786 return radv_queue_submit(queue
, &(struct radv_queue_submission
) {
4791 static bool radv_submit_has_effects(const VkSubmitInfo
*info
)
4793 return info
->commandBufferCount
||
4794 info
->waitSemaphoreCount
||
4795 info
->signalSemaphoreCount
;
4798 VkResult
radv_QueueSubmit(
4800 uint32_t submitCount
,
4801 const VkSubmitInfo
* pSubmits
,
4804 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
4806 uint32_t fence_idx
= 0;
4807 bool flushed_caches
= false;
4809 if (fence
!= VK_NULL_HANDLE
) {
4810 for (uint32_t i
= 0; i
< submitCount
; ++i
)
4811 if (radv_submit_has_effects(pSubmits
+ i
))
4814 fence_idx
= UINT32_MAX
;
4816 for (uint32_t i
= 0; i
< submitCount
; i
++) {
4817 if (!radv_submit_has_effects(pSubmits
+ i
) && fence_idx
!= i
)
4820 VkPipelineStageFlags wait_dst_stage_mask
= 0;
4821 for (unsigned j
= 0; j
< pSubmits
[i
].waitSemaphoreCount
; ++j
) {
4822 wait_dst_stage_mask
|= pSubmits
[i
].pWaitDstStageMask
[j
];
4825 const VkTimelineSemaphoreSubmitInfo
*timeline_info
=
4826 vk_find_struct_const(pSubmits
[i
].pNext
, TIMELINE_SEMAPHORE_SUBMIT_INFO
);
4828 result
= radv_queue_submit(queue
, &(struct radv_queue_submission
) {
4829 .cmd_buffers
= pSubmits
[i
].pCommandBuffers
,
4830 .cmd_buffer_count
= pSubmits
[i
].commandBufferCount
,
4831 .wait_dst_stage_mask
= wait_dst_stage_mask
,
4832 .flush_caches
= !flushed_caches
,
4833 .wait_semaphores
= pSubmits
[i
].pWaitSemaphores
,
4834 .wait_semaphore_count
= pSubmits
[i
].waitSemaphoreCount
,
4835 .signal_semaphores
= pSubmits
[i
].pSignalSemaphores
,
4836 .signal_semaphore_count
= pSubmits
[i
].signalSemaphoreCount
,
4837 .fence
= i
== fence_idx
? fence
: VK_NULL_HANDLE
,
4838 .wait_values
= timeline_info
? timeline_info
->pWaitSemaphoreValues
: NULL
,
4839 .wait_value_count
= timeline_info
&& timeline_info
->pWaitSemaphoreValues
? timeline_info
->waitSemaphoreValueCount
: 0,
4840 .signal_values
= timeline_info
? timeline_info
->pSignalSemaphoreValues
: NULL
,
4841 .signal_value_count
= timeline_info
&& timeline_info
->pSignalSemaphoreValues
? timeline_info
->signalSemaphoreValueCount
: 0,
4843 if (result
!= VK_SUCCESS
)
4846 flushed_caches
= true;
4849 if (fence
!= VK_NULL_HANDLE
&& !submitCount
) {
4850 result
= radv_signal_fence(queue
, fence
);
4851 if (result
!= VK_SUCCESS
)
4858 VkResult
radv_QueueWaitIdle(
4861 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
4863 pthread_mutex_lock(&queue
->pending_mutex
);
4864 while (!list_is_empty(&queue
->pending_submissions
)) {
4865 pthread_cond_wait(&queue
->device
->timeline_cond
, &queue
->pending_mutex
);
4867 pthread_mutex_unlock(&queue
->pending_mutex
);
4869 queue
->device
->ws
->ctx_wait_idle(queue
->hw_ctx
,
4870 radv_queue_family_to_ring(queue
->queue_family_index
),
4875 VkResult
radv_DeviceWaitIdle(
4878 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4880 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
4881 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++) {
4882 radv_QueueWaitIdle(radv_queue_to_handle(&device
->queues
[i
][q
]));
4888 VkResult
radv_EnumerateInstanceExtensionProperties(
4889 const char* pLayerName
,
4890 uint32_t* pPropertyCount
,
4891 VkExtensionProperties
* pProperties
)
4893 VK_OUTARRAY_MAKE(out
, pProperties
, pPropertyCount
);
4895 for (int i
= 0; i
< RADV_INSTANCE_EXTENSION_COUNT
; i
++) {
4896 if (radv_supported_instance_extensions
.extensions
[i
]) {
4897 vk_outarray_append(&out
, prop
) {
4898 *prop
= radv_instance_extensions
[i
];
4903 return vk_outarray_status(&out
);
4906 VkResult
radv_EnumerateDeviceExtensionProperties(
4907 VkPhysicalDevice physicalDevice
,
4908 const char* pLayerName
,
4909 uint32_t* pPropertyCount
,
4910 VkExtensionProperties
* pProperties
)
4912 RADV_FROM_HANDLE(radv_physical_device
, device
, physicalDevice
);
4913 VK_OUTARRAY_MAKE(out
, pProperties
, pPropertyCount
);
4915 for (int i
= 0; i
< RADV_DEVICE_EXTENSION_COUNT
; i
++) {
4916 if (device
->supported_extensions
.extensions
[i
]) {
4917 vk_outarray_append(&out
, prop
) {
4918 *prop
= radv_device_extensions
[i
];
4923 return vk_outarray_status(&out
);
4926 PFN_vkVoidFunction
radv_GetInstanceProcAddr(
4927 VkInstance _instance
,
4930 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
4932 /* The Vulkan 1.0 spec for vkGetInstanceProcAddr has a table of exactly
4933 * when we have to return valid function pointers, NULL, or it's left
4934 * undefined. See the table for exact details.
4939 #define LOOKUP_RADV_ENTRYPOINT(entrypoint) \
4940 if (strcmp(pName, "vk" #entrypoint) == 0) \
4941 return (PFN_vkVoidFunction)radv_##entrypoint
4943 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceExtensionProperties
);
4944 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceLayerProperties
);
4945 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceVersion
);
4946 LOOKUP_RADV_ENTRYPOINT(CreateInstance
);
4948 #undef LOOKUP_RADV_ENTRYPOINT
4950 if (instance
== NULL
)
4953 int idx
= radv_get_instance_entrypoint_index(pName
);
4955 return instance
->dispatch
.entrypoints
[idx
];
4957 idx
= radv_get_physical_device_entrypoint_index(pName
);
4959 return instance
->physical_device_dispatch
.entrypoints
[idx
];
4961 idx
= radv_get_device_entrypoint_index(pName
);
4963 return instance
->device_dispatch
.entrypoints
[idx
];
4968 /* The loader wants us to expose a second GetInstanceProcAddr function
4969 * to work around certain LD_PRELOAD issues seen in apps.
4972 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
4973 VkInstance instance
,
4977 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
4978 VkInstance instance
,
4981 return radv_GetInstanceProcAddr(instance
, pName
);
4985 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetPhysicalDeviceProcAddr(
4986 VkInstance _instance
,
4990 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetPhysicalDeviceProcAddr(
4991 VkInstance _instance
,
4994 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
4996 if (!pName
|| !instance
)
4999 int idx
= radv_get_physical_device_entrypoint_index(pName
);
5003 return instance
->physical_device_dispatch
.entrypoints
[idx
];
5006 PFN_vkVoidFunction
radv_GetDeviceProcAddr(
5010 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5012 if (!device
|| !pName
)
5015 int idx
= radv_get_device_entrypoint_index(pName
);
5019 return device
->dispatch
.entrypoints
[idx
];
5022 bool radv_get_memory_fd(struct radv_device
*device
,
5023 struct radv_device_memory
*memory
,
5026 struct radeon_bo_metadata metadata
;
5028 if (memory
->image
) {
5029 if (memory
->image
->tiling
!= VK_IMAGE_TILING_LINEAR
)
5030 radv_init_metadata(device
, memory
->image
, &metadata
);
5031 device
->ws
->buffer_set_metadata(memory
->bo
, &metadata
);
5034 return device
->ws
->buffer_get_fd(device
->ws
, memory
->bo
,
5039 static void radv_free_memory(struct radv_device
*device
,
5040 const VkAllocationCallbacks
* pAllocator
,
5041 struct radv_device_memory
*mem
)
5046 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
5047 if (mem
->android_hardware_buffer
)
5048 AHardwareBuffer_release(mem
->android_hardware_buffer
);
5052 radv_bo_list_remove(device
, mem
->bo
);
5053 device
->ws
->buffer_destroy(mem
->bo
);
5057 vk_free2(&device
->alloc
, pAllocator
, mem
);
5060 static VkResult
radv_alloc_memory(struct radv_device
*device
,
5061 const VkMemoryAllocateInfo
* pAllocateInfo
,
5062 const VkAllocationCallbacks
* pAllocator
,
5063 VkDeviceMemory
* pMem
)
5065 struct radv_device_memory
*mem
;
5067 enum radeon_bo_domain domain
;
5069 enum radv_mem_type mem_type_index
= device
->physical_device
->mem_type_indices
[pAllocateInfo
->memoryTypeIndex
];
5071 assert(pAllocateInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO
);
5073 const VkImportMemoryFdInfoKHR
*import_info
=
5074 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_FD_INFO_KHR
);
5075 const VkMemoryDedicatedAllocateInfo
*dedicate_info
=
5076 vk_find_struct_const(pAllocateInfo
->pNext
, MEMORY_DEDICATED_ALLOCATE_INFO
);
5077 const VkExportMemoryAllocateInfo
*export_info
=
5078 vk_find_struct_const(pAllocateInfo
->pNext
, EXPORT_MEMORY_ALLOCATE_INFO
);
5079 const struct VkImportAndroidHardwareBufferInfoANDROID
*ahb_import_info
=
5080 vk_find_struct_const(pAllocateInfo
->pNext
,
5081 IMPORT_ANDROID_HARDWARE_BUFFER_INFO_ANDROID
);
5082 const VkImportMemoryHostPointerInfoEXT
*host_ptr_info
=
5083 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_HOST_POINTER_INFO_EXT
);
5085 const struct wsi_memory_allocate_info
*wsi_info
=
5086 vk_find_struct_const(pAllocateInfo
->pNext
, WSI_MEMORY_ALLOCATE_INFO_MESA
);
5088 if (pAllocateInfo
->allocationSize
== 0 && !ahb_import_info
&&
5089 !(export_info
&& (export_info
->handleTypes
& VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID
))) {
5090 /* Apparently, this is allowed */
5091 *pMem
= VK_NULL_HANDLE
;
5095 mem
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*mem
), 8,
5096 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5098 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5100 if (wsi_info
&& wsi_info
->implicit_sync
)
5101 flags
|= RADEON_FLAG_IMPLICIT_SYNC
;
5103 if (dedicate_info
) {
5104 mem
->image
= radv_image_from_handle(dedicate_info
->image
);
5105 mem
->buffer
= radv_buffer_from_handle(dedicate_info
->buffer
);
5111 float priority_float
= 0.5;
5112 const struct VkMemoryPriorityAllocateInfoEXT
*priority_ext
=
5113 vk_find_struct_const(pAllocateInfo
->pNext
,
5114 MEMORY_PRIORITY_ALLOCATE_INFO_EXT
);
5116 priority_float
= priority_ext
->priority
;
5118 unsigned priority
= MIN2(RADV_BO_PRIORITY_APPLICATION_MAX
- 1,
5119 (int)(priority_float
* RADV_BO_PRIORITY_APPLICATION_MAX
));
5121 mem
->user_ptr
= NULL
;
5124 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
5125 mem
->android_hardware_buffer
= NULL
;
5128 if (ahb_import_info
) {
5129 result
= radv_import_ahb_memory(device
, mem
, priority
, ahb_import_info
);
5130 if (result
!= VK_SUCCESS
)
5132 } else if(export_info
&& (export_info
->handleTypes
& VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID
)) {
5133 result
= radv_create_ahb_memory(device
, mem
, priority
, pAllocateInfo
);
5134 if (result
!= VK_SUCCESS
)
5136 } else if (import_info
) {
5137 assert(import_info
->handleType
==
5138 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT
||
5139 import_info
->handleType
==
5140 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
5141 mem
->bo
= device
->ws
->buffer_from_fd(device
->ws
, import_info
->fd
,
5144 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE
;
5147 close(import_info
->fd
);
5149 } else if (host_ptr_info
) {
5150 assert(host_ptr_info
->handleType
== VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT
);
5151 assert(radv_is_mem_type_gtt_cached(mem_type_index
));
5152 mem
->bo
= device
->ws
->buffer_from_ptr(device
->ws
, host_ptr_info
->pHostPointer
,
5153 pAllocateInfo
->allocationSize
,
5156 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE
;
5159 mem
->user_ptr
= host_ptr_info
->pHostPointer
;
5162 uint64_t alloc_size
= align_u64(pAllocateInfo
->allocationSize
, 4096);
5163 if (radv_is_mem_type_gtt_wc(mem_type_index
) ||
5164 radv_is_mem_type_gtt_cached(mem_type_index
))
5165 domain
= RADEON_DOMAIN_GTT
;
5167 domain
= RADEON_DOMAIN_VRAM
;
5169 if (radv_is_mem_type_vram(mem_type_index
))
5170 flags
|= RADEON_FLAG_NO_CPU_ACCESS
;
5172 flags
|= RADEON_FLAG_CPU_ACCESS
;
5174 if (radv_is_mem_type_gtt_wc(mem_type_index
))
5175 flags
|= RADEON_FLAG_GTT_WC
;
5177 if (!dedicate_info
&& !import_info
&& (!export_info
|| !export_info
->handleTypes
)) {
5178 flags
|= RADEON_FLAG_NO_INTERPROCESS_SHARING
;
5179 if (device
->use_global_bo_list
) {
5180 flags
|= RADEON_FLAG_PREFER_LOCAL_BO
;
5184 if (radv_is_mem_type_uncached(mem_type_index
)) {
5185 assert(device
->physical_device
->rad_info
.has_l2_uncached
);
5186 flags
|= RADEON_FLAG_VA_UNCACHED
;
5189 mem
->bo
= device
->ws
->buffer_create(device
->ws
, alloc_size
, device
->physical_device
->rad_info
.max_alignment
,
5190 domain
, flags
, priority
);
5193 result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
5196 mem
->type_index
= mem_type_index
;
5199 result
= radv_bo_list_add(device
, mem
->bo
);
5200 if (result
!= VK_SUCCESS
)
5203 *pMem
= radv_device_memory_to_handle(mem
);
5208 radv_free_memory(device
, pAllocator
,mem
);
5213 VkResult
radv_AllocateMemory(
5215 const VkMemoryAllocateInfo
* pAllocateInfo
,
5216 const VkAllocationCallbacks
* pAllocator
,
5217 VkDeviceMemory
* pMem
)
5219 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5220 return radv_alloc_memory(device
, pAllocateInfo
, pAllocator
, pMem
);
5223 void radv_FreeMemory(
5225 VkDeviceMemory _mem
,
5226 const VkAllocationCallbacks
* pAllocator
)
5228 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5229 RADV_FROM_HANDLE(radv_device_memory
, mem
, _mem
);
5231 radv_free_memory(device
, pAllocator
, mem
);
5234 VkResult
radv_MapMemory(
5236 VkDeviceMemory _memory
,
5237 VkDeviceSize offset
,
5239 VkMemoryMapFlags flags
,
5242 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5243 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
5251 *ppData
= mem
->user_ptr
;
5253 *ppData
= device
->ws
->buffer_map(mem
->bo
);
5260 return vk_error(device
->instance
, VK_ERROR_MEMORY_MAP_FAILED
);
5263 void radv_UnmapMemory(
5265 VkDeviceMemory _memory
)
5267 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5268 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
5273 if (mem
->user_ptr
== NULL
)
5274 device
->ws
->buffer_unmap(mem
->bo
);
5277 VkResult
radv_FlushMappedMemoryRanges(
5279 uint32_t memoryRangeCount
,
5280 const VkMappedMemoryRange
* pMemoryRanges
)
5285 VkResult
radv_InvalidateMappedMemoryRanges(
5287 uint32_t memoryRangeCount
,
5288 const VkMappedMemoryRange
* pMemoryRanges
)
5293 void radv_GetBufferMemoryRequirements(
5296 VkMemoryRequirements
* pMemoryRequirements
)
5298 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5299 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
5301 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
5303 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
5304 pMemoryRequirements
->alignment
= 4096;
5306 pMemoryRequirements
->alignment
= 16;
5308 pMemoryRequirements
->size
= align64(buffer
->size
, pMemoryRequirements
->alignment
);
5311 void radv_GetBufferMemoryRequirements2(
5313 const VkBufferMemoryRequirementsInfo2
*pInfo
,
5314 VkMemoryRequirements2
*pMemoryRequirements
)
5316 radv_GetBufferMemoryRequirements(device
, pInfo
->buffer
,
5317 &pMemoryRequirements
->memoryRequirements
);
5318 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
5319 switch (ext
->sType
) {
5320 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS
: {
5321 VkMemoryDedicatedRequirements
*req
=
5322 (VkMemoryDedicatedRequirements
*) ext
;
5323 req
->requiresDedicatedAllocation
= false;
5324 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
5333 void radv_GetImageMemoryRequirements(
5336 VkMemoryRequirements
* pMemoryRequirements
)
5338 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5339 RADV_FROM_HANDLE(radv_image
, image
, _image
);
5341 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
5343 pMemoryRequirements
->size
= image
->size
;
5344 pMemoryRequirements
->alignment
= image
->alignment
;
5347 void radv_GetImageMemoryRequirements2(
5349 const VkImageMemoryRequirementsInfo2
*pInfo
,
5350 VkMemoryRequirements2
*pMemoryRequirements
)
5352 radv_GetImageMemoryRequirements(device
, pInfo
->image
,
5353 &pMemoryRequirements
->memoryRequirements
);
5355 RADV_FROM_HANDLE(radv_image
, image
, pInfo
->image
);
5357 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
5358 switch (ext
->sType
) {
5359 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS
: {
5360 VkMemoryDedicatedRequirements
*req
=
5361 (VkMemoryDedicatedRequirements
*) ext
;
5362 req
->requiresDedicatedAllocation
= image
->shareable
&&
5363 image
->tiling
!= VK_IMAGE_TILING_LINEAR
;
5364 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
5373 void radv_GetImageSparseMemoryRequirements(
5376 uint32_t* pSparseMemoryRequirementCount
,
5377 VkSparseImageMemoryRequirements
* pSparseMemoryRequirements
)
5382 void radv_GetImageSparseMemoryRequirements2(
5384 const VkImageSparseMemoryRequirementsInfo2
*pInfo
,
5385 uint32_t* pSparseMemoryRequirementCount
,
5386 VkSparseImageMemoryRequirements2
*pSparseMemoryRequirements
)
5391 void radv_GetDeviceMemoryCommitment(
5393 VkDeviceMemory memory
,
5394 VkDeviceSize
* pCommittedMemoryInBytes
)
5396 *pCommittedMemoryInBytes
= 0;
5399 VkResult
radv_BindBufferMemory2(VkDevice device
,
5400 uint32_t bindInfoCount
,
5401 const VkBindBufferMemoryInfo
*pBindInfos
)
5403 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
5404 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
5405 RADV_FROM_HANDLE(radv_buffer
, buffer
, pBindInfos
[i
].buffer
);
5408 buffer
->bo
= mem
->bo
;
5409 buffer
->offset
= pBindInfos
[i
].memoryOffset
;
5417 VkResult
radv_BindBufferMemory(
5420 VkDeviceMemory memory
,
5421 VkDeviceSize memoryOffset
)
5423 const VkBindBufferMemoryInfo info
= {
5424 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO
,
5427 .memoryOffset
= memoryOffset
5430 return radv_BindBufferMemory2(device
, 1, &info
);
5433 VkResult
radv_BindImageMemory2(VkDevice device
,
5434 uint32_t bindInfoCount
,
5435 const VkBindImageMemoryInfo
*pBindInfos
)
5437 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
5438 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
5439 RADV_FROM_HANDLE(radv_image
, image
, pBindInfos
[i
].image
);
5442 image
->bo
= mem
->bo
;
5443 image
->offset
= pBindInfos
[i
].memoryOffset
;
5453 VkResult
radv_BindImageMemory(
5456 VkDeviceMemory memory
,
5457 VkDeviceSize memoryOffset
)
5459 const VkBindImageMemoryInfo info
= {
5460 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO
,
5463 .memoryOffset
= memoryOffset
5466 return radv_BindImageMemory2(device
, 1, &info
);
5469 static bool radv_sparse_bind_has_effects(const VkBindSparseInfo
*info
)
5471 return info
->bufferBindCount
||
5472 info
->imageOpaqueBindCount
||
5473 info
->imageBindCount
||
5474 info
->waitSemaphoreCount
||
5475 info
->signalSemaphoreCount
;
5478 VkResult
radv_QueueBindSparse(
5480 uint32_t bindInfoCount
,
5481 const VkBindSparseInfo
* pBindInfo
,
5484 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
5486 uint32_t fence_idx
= 0;
5488 if (fence
!= VK_NULL_HANDLE
) {
5489 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
)
5490 if (radv_sparse_bind_has_effects(pBindInfo
+ i
))
5493 fence_idx
= UINT32_MAX
;
5495 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
5496 if (i
!= fence_idx
&& !radv_sparse_bind_has_effects(pBindInfo
+ i
))
5499 const VkTimelineSemaphoreSubmitInfo
*timeline_info
=
5500 vk_find_struct_const(pBindInfo
[i
].pNext
, TIMELINE_SEMAPHORE_SUBMIT_INFO
);
5502 VkResult result
= radv_queue_submit(queue
, &(struct radv_queue_submission
) {
5503 .buffer_binds
= pBindInfo
[i
].pBufferBinds
,
5504 .buffer_bind_count
= pBindInfo
[i
].bufferBindCount
,
5505 .image_opaque_binds
= pBindInfo
[i
].pImageOpaqueBinds
,
5506 .image_opaque_bind_count
= pBindInfo
[i
].imageOpaqueBindCount
,
5507 .wait_semaphores
= pBindInfo
[i
].pWaitSemaphores
,
5508 .wait_semaphore_count
= pBindInfo
[i
].waitSemaphoreCount
,
5509 .signal_semaphores
= pBindInfo
[i
].pSignalSemaphores
,
5510 .signal_semaphore_count
= pBindInfo
[i
].signalSemaphoreCount
,
5511 .fence
= i
== fence_idx
? fence
: VK_NULL_HANDLE
,
5512 .wait_values
= timeline_info
? timeline_info
->pWaitSemaphoreValues
: NULL
,
5513 .wait_value_count
= timeline_info
&& timeline_info
->pWaitSemaphoreValues
? timeline_info
->waitSemaphoreValueCount
: 0,
5514 .signal_values
= timeline_info
? timeline_info
->pSignalSemaphoreValues
: NULL
,
5515 .signal_value_count
= timeline_info
&& timeline_info
->pSignalSemaphoreValues
? timeline_info
->signalSemaphoreValueCount
: 0,
5518 if (result
!= VK_SUCCESS
)
5522 if (fence
!= VK_NULL_HANDLE
&& !bindInfoCount
) {
5523 result
= radv_signal_fence(queue
, fence
);
5524 if (result
!= VK_SUCCESS
)
5531 VkResult
radv_CreateFence(
5533 const VkFenceCreateInfo
* pCreateInfo
,
5534 const VkAllocationCallbacks
* pAllocator
,
5537 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5538 const VkExportFenceCreateInfo
*export
=
5539 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_FENCE_CREATE_INFO
);
5540 VkExternalFenceHandleTypeFlags handleTypes
=
5541 export
? export
->handleTypes
: 0;
5543 struct radv_fence
*fence
= vk_alloc2(&device
->alloc
, pAllocator
,
5545 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5548 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5550 fence
->fence_wsi
= NULL
;
5551 fence
->temp_syncobj
= 0;
5552 if (device
->always_use_syncobj
|| handleTypes
) {
5553 int ret
= device
->ws
->create_syncobj(device
->ws
, &fence
->syncobj
);
5555 vk_free2(&device
->alloc
, pAllocator
, fence
);
5556 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5558 if (pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
) {
5559 device
->ws
->signal_syncobj(device
->ws
, fence
->syncobj
);
5561 fence
->fence
= NULL
;
5563 fence
->fence
= device
->ws
->create_fence();
5564 if (!fence
->fence
) {
5565 vk_free2(&device
->alloc
, pAllocator
, fence
);
5566 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5569 if (pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
)
5570 device
->ws
->signal_fence(fence
->fence
);
5573 *pFence
= radv_fence_to_handle(fence
);
5578 void radv_DestroyFence(
5581 const VkAllocationCallbacks
* pAllocator
)
5583 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5584 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
5589 if (fence
->temp_syncobj
)
5590 device
->ws
->destroy_syncobj(device
->ws
, fence
->temp_syncobj
);
5592 device
->ws
->destroy_syncobj(device
->ws
, fence
->syncobj
);
5594 device
->ws
->destroy_fence(fence
->fence
);
5595 if (fence
->fence_wsi
)
5596 fence
->fence_wsi
->destroy(fence
->fence_wsi
);
5597 vk_free2(&device
->alloc
, pAllocator
, fence
);
5601 uint64_t radv_get_current_time(void)
5604 clock_gettime(CLOCK_MONOTONIC
, &tv
);
5605 return tv
.tv_nsec
+ tv
.tv_sec
*1000000000ull;
5608 static uint64_t radv_get_absolute_timeout(uint64_t timeout
)
5610 uint64_t current_time
= radv_get_current_time();
5612 timeout
= MIN2(UINT64_MAX
- current_time
, timeout
);
5614 return current_time
+ timeout
;
5618 static bool radv_all_fences_plain_and_submitted(struct radv_device
*device
,
5619 uint32_t fenceCount
, const VkFence
*pFences
)
5621 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5622 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5623 if (fence
->fence
== NULL
|| fence
->syncobj
||
5624 fence
->temp_syncobj
|| fence
->fence_wsi
||
5625 (!device
->ws
->is_fence_waitable(fence
->fence
)))
5631 static bool radv_all_fences_syncobj(uint32_t fenceCount
, const VkFence
*pFences
)
5633 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5634 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5635 if (fence
->syncobj
== 0 && fence
->temp_syncobj
== 0)
5641 VkResult
radv_WaitForFences(
5643 uint32_t fenceCount
,
5644 const VkFence
* pFences
,
5648 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5649 timeout
= radv_get_absolute_timeout(timeout
);
5651 if (device
->always_use_syncobj
&&
5652 radv_all_fences_syncobj(fenceCount
, pFences
))
5654 uint32_t *handles
= malloc(sizeof(uint32_t) * fenceCount
);
5656 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5658 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5659 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5660 handles
[i
] = fence
->temp_syncobj
? fence
->temp_syncobj
: fence
->syncobj
;
5663 bool success
= device
->ws
->wait_syncobj(device
->ws
, handles
, fenceCount
, waitAll
, timeout
);
5666 return success
? VK_SUCCESS
: VK_TIMEOUT
;
5669 if (!waitAll
&& fenceCount
> 1) {
5670 /* Not doing this by default for waitAll, due to needing to allocate twice. */
5671 if (device
->physical_device
->rad_info
.drm_minor
>= 10 && radv_all_fences_plain_and_submitted(device
, fenceCount
, pFences
)) {
5672 uint32_t wait_count
= 0;
5673 struct radeon_winsys_fence
**fences
= malloc(sizeof(struct radeon_winsys_fence
*) * fenceCount
);
5675 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5677 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5678 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5680 if (device
->ws
->fence_wait(device
->ws
, fence
->fence
, false, 0)) {
5685 fences
[wait_count
++] = fence
->fence
;
5688 bool success
= device
->ws
->fences_wait(device
->ws
, fences
, wait_count
,
5689 waitAll
, timeout
- radv_get_current_time());
5692 return success
? VK_SUCCESS
: VK_TIMEOUT
;
5695 while(radv_get_current_time() <= timeout
) {
5696 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5697 if (radv_GetFenceStatus(_device
, pFences
[i
]) == VK_SUCCESS
)
5704 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5705 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5706 bool expired
= false;
5708 if (fence
->temp_syncobj
) {
5709 if (!device
->ws
->wait_syncobj(device
->ws
, &fence
->temp_syncobj
, 1, true, timeout
))
5714 if (fence
->syncobj
) {
5715 if (!device
->ws
->wait_syncobj(device
->ws
, &fence
->syncobj
, 1, true, timeout
))
5721 if (!device
->ws
->is_fence_waitable(fence
->fence
)) {
5722 while(!device
->ws
->is_fence_waitable(fence
->fence
) &&
5723 radv_get_current_time() <= timeout
)
5727 expired
= device
->ws
->fence_wait(device
->ws
,
5734 if (fence
->fence_wsi
) {
5735 VkResult result
= fence
->fence_wsi
->wait(fence
->fence_wsi
, timeout
);
5736 if (result
!= VK_SUCCESS
)
5744 VkResult
radv_ResetFences(VkDevice _device
,
5745 uint32_t fenceCount
,
5746 const VkFence
*pFences
)
5748 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5750 for (unsigned i
= 0; i
< fenceCount
; ++i
) {
5751 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5753 device
->ws
->reset_fence(fence
->fence
);
5755 /* Per spec, we first restore the permanent payload, and then reset, so
5756 * having a temp syncobj should not skip resetting the permanent syncobj. */
5757 if (fence
->temp_syncobj
) {
5758 device
->ws
->destroy_syncobj(device
->ws
, fence
->temp_syncobj
);
5759 fence
->temp_syncobj
= 0;
5762 if (fence
->syncobj
) {
5763 device
->ws
->reset_syncobj(device
->ws
, fence
->syncobj
);
5770 VkResult
radv_GetFenceStatus(VkDevice _device
, VkFence _fence
)
5772 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5773 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
5775 if (fence
->temp_syncobj
) {
5776 bool success
= device
->ws
->wait_syncobj(device
->ws
, &fence
->temp_syncobj
, 1, true, 0);
5777 return success
? VK_SUCCESS
: VK_NOT_READY
;
5780 if (fence
->syncobj
) {
5781 bool success
= device
->ws
->wait_syncobj(device
->ws
, &fence
->syncobj
, 1, true, 0);
5782 return success
? VK_SUCCESS
: VK_NOT_READY
;
5786 if (!device
->ws
->fence_wait(device
->ws
, fence
->fence
, false, 0))
5787 return VK_NOT_READY
;
5789 if (fence
->fence_wsi
) {
5790 VkResult result
= fence
->fence_wsi
->wait(fence
->fence_wsi
, 0);
5792 if (result
!= VK_SUCCESS
) {
5793 if (result
== VK_TIMEOUT
)
5794 return VK_NOT_READY
;
5802 // Queue semaphore functions
5805 radv_create_timeline(struct radv_timeline
*timeline
, uint64_t value
)
5807 timeline
->highest_signaled
= value
;
5808 timeline
->highest_submitted
= value
;
5809 list_inithead(&timeline
->points
);
5810 list_inithead(&timeline
->free_points
);
5811 list_inithead(&timeline
->waiters
);
5812 pthread_mutex_init(&timeline
->mutex
, NULL
);
5816 radv_destroy_timeline(struct radv_device
*device
,
5817 struct radv_timeline
*timeline
)
5819 list_for_each_entry_safe(struct radv_timeline_point
, point
,
5820 &timeline
->free_points
, list
) {
5821 list_del(&point
->list
);
5822 device
->ws
->destroy_syncobj(device
->ws
, point
->syncobj
);
5825 list_for_each_entry_safe(struct radv_timeline_point
, point
,
5826 &timeline
->points
, list
) {
5827 list_del(&point
->list
);
5828 device
->ws
->destroy_syncobj(device
->ws
, point
->syncobj
);
5831 pthread_mutex_destroy(&timeline
->mutex
);
5835 radv_timeline_gc_locked(struct radv_device
*device
,
5836 struct radv_timeline
*timeline
)
5838 list_for_each_entry_safe(struct radv_timeline_point
, point
,
5839 &timeline
->points
, list
) {
5840 if (point
->wait_count
|| point
->value
> timeline
->highest_submitted
)
5843 if (device
->ws
->wait_syncobj(device
->ws
, &point
->syncobj
, 1, true, 0)) {
5844 timeline
->highest_signaled
= point
->value
;
5845 list_del(&point
->list
);
5846 list_add(&point
->list
, &timeline
->free_points
);
5851 static struct radv_timeline_point
*
5852 radv_timeline_find_point_at_least_locked(struct radv_device
*device
,
5853 struct radv_timeline
*timeline
,
5856 radv_timeline_gc_locked(device
, timeline
);
5858 if (p
<= timeline
->highest_signaled
)
5861 list_for_each_entry(struct radv_timeline_point
, point
,
5862 &timeline
->points
, list
) {
5863 if (point
->value
>= p
) {
5864 ++point
->wait_count
;
5871 static struct radv_timeline_point
*
5872 radv_timeline_add_point_locked(struct radv_device
*device
,
5873 struct radv_timeline
*timeline
,
5876 radv_timeline_gc_locked(device
, timeline
);
5878 struct radv_timeline_point
*ret
= NULL
;
5879 struct radv_timeline_point
*prev
= NULL
;
5881 if (p
<= timeline
->highest_signaled
)
5884 list_for_each_entry(struct radv_timeline_point
, point
,
5885 &timeline
->points
, list
) {
5886 if (point
->value
== p
) {
5890 if (point
->value
< p
)
5894 if (list_is_empty(&timeline
->free_points
)) {
5895 ret
= malloc(sizeof(struct radv_timeline_point
));
5896 device
->ws
->create_syncobj(device
->ws
, &ret
->syncobj
);
5898 ret
= list_first_entry(&timeline
->free_points
, struct radv_timeline_point
, list
);
5899 list_del(&ret
->list
);
5901 device
->ws
->reset_syncobj(device
->ws
, ret
->syncobj
);
5905 ret
->wait_count
= 1;
5908 list_add(&ret
->list
, &prev
->list
);
5910 list_addtail(&ret
->list
, &timeline
->points
);
5917 radv_timeline_wait_locked(struct radv_device
*device
,
5918 struct radv_timeline
*timeline
,
5920 uint64_t abs_timeout
)
5922 while(timeline
->highest_submitted
< value
) {
5923 struct timespec abstime
;
5924 timespec_from_nsec(&abstime
, abs_timeout
);
5926 pthread_cond_timedwait(&device
->timeline_cond
, &timeline
->mutex
, &abstime
);
5928 if (radv_get_current_time() >= abs_timeout
&& timeline
->highest_submitted
< value
)
5932 struct radv_timeline_point
*point
= radv_timeline_find_point_at_least_locked(device
, timeline
, value
);
5936 pthread_mutex_unlock(&timeline
->mutex
);
5938 bool success
= device
->ws
->wait_syncobj(device
->ws
, &point
->syncobj
, 1, true, abs_timeout
);
5940 pthread_mutex_lock(&timeline
->mutex
);
5941 point
->wait_count
--;
5942 return success
? VK_SUCCESS
: VK_TIMEOUT
;
5946 radv_timeline_trigger_waiters_locked(struct radv_timeline
*timeline
,
5947 struct list_head
*processing_list
)
5949 list_for_each_entry_safe(struct radv_timeline_waiter
, waiter
,
5950 &timeline
->waiters
, list
) {
5951 if (waiter
->value
> timeline
->highest_submitted
)
5954 if (p_atomic_dec_zero(&waiter
->submission
->submission_wait_count
)) {
5955 list_addtail(&waiter
->submission
->processing_list
, processing_list
);
5957 list_del(&waiter
->list
);
5962 void radv_destroy_semaphore_part(struct radv_device
*device
,
5963 struct radv_semaphore_part
*part
)
5965 switch(part
->kind
) {
5966 case RADV_SEMAPHORE_NONE
:
5968 case RADV_SEMAPHORE_WINSYS
:
5969 device
->ws
->destroy_sem(part
->ws_sem
);
5971 case RADV_SEMAPHORE_TIMELINE
:
5972 radv_destroy_timeline(device
, &part
->timeline
);
5974 case RADV_SEMAPHORE_SYNCOBJ
:
5975 device
->ws
->destroy_syncobj(device
->ws
, part
->syncobj
);
5978 part
->kind
= RADV_SEMAPHORE_NONE
;
5981 static VkSemaphoreTypeKHR
5982 radv_get_semaphore_type(const void *pNext
, uint64_t *initial_value
)
5984 const VkSemaphoreTypeCreateInfo
*type_info
=
5985 vk_find_struct_const(pNext
, SEMAPHORE_TYPE_CREATE_INFO
);
5988 return VK_SEMAPHORE_TYPE_BINARY
;
5991 *initial_value
= type_info
->initialValue
;
5992 return type_info
->semaphoreType
;
5995 VkResult
radv_CreateSemaphore(
5997 const VkSemaphoreCreateInfo
* pCreateInfo
,
5998 const VkAllocationCallbacks
* pAllocator
,
5999 VkSemaphore
* pSemaphore
)
6001 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6002 const VkExportSemaphoreCreateInfo
*export
=
6003 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_SEMAPHORE_CREATE_INFO
);
6004 VkExternalSemaphoreHandleTypeFlags handleTypes
=
6005 export
? export
->handleTypes
: 0;
6006 uint64_t initial_value
= 0;
6007 VkSemaphoreTypeKHR type
= radv_get_semaphore_type(pCreateInfo
->pNext
, &initial_value
);
6009 struct radv_semaphore
*sem
= vk_alloc2(&device
->alloc
, pAllocator
,
6011 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
6013 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6015 sem
->temporary
.kind
= RADV_SEMAPHORE_NONE
;
6016 sem
->permanent
.kind
= RADV_SEMAPHORE_NONE
;
6018 if (type
== VK_SEMAPHORE_TYPE_TIMELINE
) {
6019 radv_create_timeline(&sem
->permanent
.timeline
, initial_value
);
6020 sem
->permanent
.kind
= RADV_SEMAPHORE_TIMELINE
;
6021 } else if (device
->always_use_syncobj
|| handleTypes
) {
6022 assert (device
->physical_device
->rad_info
.has_syncobj
);
6023 int ret
= device
->ws
->create_syncobj(device
->ws
, &sem
->permanent
.syncobj
);
6025 vk_free2(&device
->alloc
, pAllocator
, sem
);
6026 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6028 sem
->permanent
.kind
= RADV_SEMAPHORE_SYNCOBJ
;
6030 sem
->permanent
.ws_sem
= device
->ws
->create_sem(device
->ws
);
6031 if (!sem
->permanent
.ws_sem
) {
6032 vk_free2(&device
->alloc
, pAllocator
, sem
);
6033 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6035 sem
->permanent
.kind
= RADV_SEMAPHORE_WINSYS
;
6038 *pSemaphore
= radv_semaphore_to_handle(sem
);
6042 void radv_DestroySemaphore(
6044 VkSemaphore _semaphore
,
6045 const VkAllocationCallbacks
* pAllocator
)
6047 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6048 RADV_FROM_HANDLE(radv_semaphore
, sem
, _semaphore
);
6052 radv_destroy_semaphore_part(device
, &sem
->temporary
);
6053 radv_destroy_semaphore_part(device
, &sem
->permanent
);
6054 vk_free2(&device
->alloc
, pAllocator
, sem
);
6058 radv_GetSemaphoreCounterValue(VkDevice _device
,
6059 VkSemaphore _semaphore
,
6062 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6063 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, _semaphore
);
6065 struct radv_semaphore_part
*part
=
6066 semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
? &semaphore
->temporary
: &semaphore
->permanent
;
6068 switch (part
->kind
) {
6069 case RADV_SEMAPHORE_TIMELINE
: {
6070 pthread_mutex_lock(&part
->timeline
.mutex
);
6071 radv_timeline_gc_locked(device
, &part
->timeline
);
6072 *pValue
= part
->timeline
.highest_signaled
;
6073 pthread_mutex_unlock(&part
->timeline
.mutex
);
6076 case RADV_SEMAPHORE_NONE
:
6077 case RADV_SEMAPHORE_SYNCOBJ
:
6078 case RADV_SEMAPHORE_WINSYS
:
6079 unreachable("Invalid semaphore type");
6081 unreachable("Unhandled semaphore type");
6086 radv_wait_timelines(struct radv_device
*device
,
6087 const VkSemaphoreWaitInfo
* pWaitInfo
,
6088 uint64_t abs_timeout
)
6090 if ((pWaitInfo
->flags
& VK_SEMAPHORE_WAIT_ANY_BIT_KHR
) && pWaitInfo
->semaphoreCount
> 1) {
6092 for(uint32_t i
= 0; i
< pWaitInfo
->semaphoreCount
; ++i
) {
6093 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, pWaitInfo
->pSemaphores
[i
]);
6094 pthread_mutex_lock(&semaphore
->permanent
.timeline
.mutex
);
6095 VkResult result
= radv_timeline_wait_locked(device
, &semaphore
->permanent
.timeline
, pWaitInfo
->pValues
[i
], 0);
6096 pthread_mutex_unlock(&semaphore
->permanent
.timeline
.mutex
);
6098 if (result
== VK_SUCCESS
)
6101 if (radv_get_current_time() > abs_timeout
)
6106 for(uint32_t i
= 0; i
< pWaitInfo
->semaphoreCount
; ++i
) {
6107 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, pWaitInfo
->pSemaphores
[i
]);
6108 pthread_mutex_lock(&semaphore
->permanent
.timeline
.mutex
);
6109 VkResult result
= radv_timeline_wait_locked(device
, &semaphore
->permanent
.timeline
, pWaitInfo
->pValues
[i
], abs_timeout
);
6110 pthread_mutex_unlock(&semaphore
->permanent
.timeline
.mutex
);
6112 if (result
!= VK_SUCCESS
)
6118 radv_WaitSemaphores(VkDevice _device
,
6119 const VkSemaphoreWaitInfo
* pWaitInfo
,
6122 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6123 uint64_t abs_timeout
= radv_get_absolute_timeout(timeout
);
6124 return radv_wait_timelines(device
, pWaitInfo
, abs_timeout
);
6128 radv_SignalSemaphore(VkDevice _device
,
6129 const VkSemaphoreSignalInfo
* pSignalInfo
)
6131 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6132 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, pSignalInfo
->semaphore
);
6134 struct radv_semaphore_part
*part
=
6135 semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
? &semaphore
->temporary
: &semaphore
->permanent
;
6137 switch(part
->kind
) {
6138 case RADV_SEMAPHORE_TIMELINE
: {
6139 pthread_mutex_lock(&part
->timeline
.mutex
);
6140 radv_timeline_gc_locked(device
, &part
->timeline
);
6141 part
->timeline
.highest_submitted
= MAX2(part
->timeline
.highest_submitted
, pSignalInfo
->value
);
6142 part
->timeline
.highest_signaled
= MAX2(part
->timeline
.highest_signaled
, pSignalInfo
->value
);
6144 struct list_head processing_list
;
6145 list_inithead(&processing_list
);
6146 radv_timeline_trigger_waiters_locked(&part
->timeline
, &processing_list
);
6147 pthread_mutex_unlock(&part
->timeline
.mutex
);
6149 return radv_process_submissions(&processing_list
);
6151 case RADV_SEMAPHORE_NONE
:
6152 case RADV_SEMAPHORE_SYNCOBJ
:
6153 case RADV_SEMAPHORE_WINSYS
:
6154 unreachable("Invalid semaphore type");
6161 VkResult
radv_CreateEvent(
6163 const VkEventCreateInfo
* pCreateInfo
,
6164 const VkAllocationCallbacks
* pAllocator
,
6167 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6168 struct radv_event
*event
= vk_alloc2(&device
->alloc
, pAllocator
,
6170 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
6173 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6175 event
->bo
= device
->ws
->buffer_create(device
->ws
, 8, 8,
6177 RADEON_FLAG_VA_UNCACHED
| RADEON_FLAG_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
,
6178 RADV_BO_PRIORITY_FENCE
);
6180 vk_free2(&device
->alloc
, pAllocator
, event
);
6181 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
6184 event
->map
= (uint64_t*)device
->ws
->buffer_map(event
->bo
);
6186 *pEvent
= radv_event_to_handle(event
);
6191 void radv_DestroyEvent(
6194 const VkAllocationCallbacks
* pAllocator
)
6196 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6197 RADV_FROM_HANDLE(radv_event
, event
, _event
);
6201 device
->ws
->buffer_destroy(event
->bo
);
6202 vk_free2(&device
->alloc
, pAllocator
, event
);
6205 VkResult
radv_GetEventStatus(
6209 RADV_FROM_HANDLE(radv_event
, event
, _event
);
6211 if (*event
->map
== 1)
6212 return VK_EVENT_SET
;
6213 return VK_EVENT_RESET
;
6216 VkResult
radv_SetEvent(
6220 RADV_FROM_HANDLE(radv_event
, event
, _event
);
6226 VkResult
radv_ResetEvent(
6230 RADV_FROM_HANDLE(radv_event
, event
, _event
);
6236 VkResult
radv_CreateBuffer(
6238 const VkBufferCreateInfo
* pCreateInfo
,
6239 const VkAllocationCallbacks
* pAllocator
,
6242 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6243 struct radv_buffer
*buffer
;
6245 if (pCreateInfo
->size
> RADV_MAX_MEMORY_ALLOCATION_SIZE
)
6246 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
6248 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO
);
6250 buffer
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*buffer
), 8,
6251 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
6253 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6255 buffer
->size
= pCreateInfo
->size
;
6256 buffer
->usage
= pCreateInfo
->usage
;
6259 buffer
->flags
= pCreateInfo
->flags
;
6261 buffer
->shareable
= vk_find_struct_const(pCreateInfo
->pNext
,
6262 EXTERNAL_MEMORY_BUFFER_CREATE_INFO
) != NULL
;
6264 if (pCreateInfo
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
) {
6265 buffer
->bo
= device
->ws
->buffer_create(device
->ws
,
6266 align64(buffer
->size
, 4096),
6267 4096, 0, RADEON_FLAG_VIRTUAL
,
6268 RADV_BO_PRIORITY_VIRTUAL
);
6270 vk_free2(&device
->alloc
, pAllocator
, buffer
);
6271 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
6275 *pBuffer
= radv_buffer_to_handle(buffer
);
6280 void radv_DestroyBuffer(
6283 const VkAllocationCallbacks
* pAllocator
)
6285 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6286 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
6291 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
6292 device
->ws
->buffer_destroy(buffer
->bo
);
6294 vk_free2(&device
->alloc
, pAllocator
, buffer
);
6297 VkDeviceAddress
radv_GetBufferDeviceAddress(
6299 const VkBufferDeviceAddressInfo
* pInfo
)
6301 RADV_FROM_HANDLE(radv_buffer
, buffer
, pInfo
->buffer
);
6302 return radv_buffer_get_va(buffer
->bo
) + buffer
->offset
;
6306 uint64_t radv_GetBufferOpaqueCaptureAddress(VkDevice device
,
6307 const VkBufferDeviceAddressInfo
* pInfo
)
6312 uint64_t radv_GetDeviceMemoryOpaqueCaptureAddress(VkDevice device
,
6313 const VkDeviceMemoryOpaqueCaptureAddressInfo
* pInfo
)
6318 static inline unsigned
6319 si_tile_mode_index(const struct radv_image_plane
*plane
, unsigned level
, bool stencil
)
6322 return plane
->surface
.u
.legacy
.stencil_tiling_index
[level
];
6324 return plane
->surface
.u
.legacy
.tiling_index
[level
];
6327 static uint32_t radv_surface_max_layer_count(struct radv_image_view
*iview
)
6329 return iview
->type
== VK_IMAGE_VIEW_TYPE_3D
? iview
->extent
.depth
: (iview
->base_layer
+ iview
->layer_count
);
6333 radv_init_dcc_control_reg(struct radv_device
*device
,
6334 struct radv_image_view
*iview
)
6336 unsigned max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_256B
;
6337 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
6338 unsigned max_compressed_block_size
;
6339 unsigned independent_128b_blocks
;
6340 unsigned independent_64b_blocks
;
6342 if (!radv_dcc_enabled(iview
->image
, iview
->base_mip
))
6345 if (!device
->physical_device
->rad_info
.has_dedicated_vram
) {
6346 /* amdvlk: [min-compressed-block-size] should be set to 32 for
6347 * dGPU and 64 for APU because all of our APUs to date use
6348 * DIMMs which have a request granularity size of 64B while all
6349 * other chips have a 32B request size.
6351 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
6354 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6355 max_compressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
6356 independent_64b_blocks
= 0;
6357 independent_128b_blocks
= 1;
6359 independent_128b_blocks
= 0;
6361 if (iview
->image
->info
.samples
> 1) {
6362 if (iview
->image
->planes
[0].surface
.bpe
== 1)
6363 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
6364 else if (iview
->image
->planes
[0].surface
.bpe
== 2)
6365 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
6368 if (iview
->image
->usage
& (VK_IMAGE_USAGE_SAMPLED_BIT
|
6369 VK_IMAGE_USAGE_TRANSFER_SRC_BIT
|
6370 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
)) {
6371 /* If this DCC image is potentially going to be used in texture
6372 * fetches, we need some special settings.
6374 independent_64b_blocks
= 1;
6375 max_compressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
6377 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
6378 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
6379 * big as possible for better compression state.
6381 independent_64b_blocks
= 0;
6382 max_compressed_block_size
= max_uncompressed_block_size
;
6386 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
6387 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size
) |
6388 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
6389 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks
) |
6390 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks
);
6394 radv_initialise_color_surface(struct radv_device
*device
,
6395 struct radv_color_buffer_info
*cb
,
6396 struct radv_image_view
*iview
)
6398 const struct vk_format_description
*desc
;
6399 unsigned ntype
, format
, swap
, endian
;
6400 unsigned blend_clamp
= 0, blend_bypass
= 0;
6402 const struct radv_image_plane
*plane
= &iview
->image
->planes
[iview
->plane_id
];
6403 const struct radeon_surf
*surf
= &plane
->surface
;
6405 desc
= vk_format_description(iview
->vk_format
);
6407 memset(cb
, 0, sizeof(*cb
));
6409 /* Intensity is implemented as Red, so treat it that way. */
6410 cb
->cb_color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == VK_SWIZZLE_1
);
6412 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+ plane
->offset
;
6414 cb
->cb_color_base
= va
>> 8;
6416 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
6417 struct gfx9_surf_meta_flags meta
;
6418 if (iview
->image
->dcc_offset
)
6419 meta
= surf
->u
.gfx9
.dcc
;
6421 meta
= surf
->u
.gfx9
.cmask
;
6423 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6424 cb
->cb_color_attrib3
|= S_028EE0_COLOR_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
6425 S_028EE0_FMASK_SW_MODE(surf
->u
.gfx9
.fmask
.swizzle_mode
) |
6426 S_028EE0_CMASK_PIPE_ALIGNED(surf
->u
.gfx9
.cmask
.pipe_aligned
) |
6427 S_028EE0_DCC_PIPE_ALIGNED(surf
->u
.gfx9
.dcc
.pipe_aligned
);
6429 cb
->cb_color_attrib
|= S_028C74_COLOR_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
6430 S_028C74_FMASK_SW_MODE(surf
->u
.gfx9
.fmask
.swizzle_mode
) |
6431 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
6432 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
6433 cb
->cb_mrt_epitch
= S_0287A0_EPITCH(surf
->u
.gfx9
.surf
.epitch
);
6436 cb
->cb_color_base
+= surf
->u
.gfx9
.surf_offset
>> 8;
6437 cb
->cb_color_base
|= surf
->tile_swizzle
;
6439 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[iview
->base_mip
];
6440 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
6442 cb
->cb_color_base
+= level_info
->offset
>> 8;
6443 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
6444 cb
->cb_color_base
|= surf
->tile_swizzle
;
6446 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
6447 slice_tile_max
= (level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1;
6448 tile_mode_index
= si_tile_mode_index(plane
, iview
->base_mip
, false);
6450 cb
->cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
6451 cb
->cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
6452 cb
->cb_color_cmask_slice
= surf
->u
.legacy
.cmask_slice_tile_max
;
6454 cb
->cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
6456 if (radv_image_has_fmask(iview
->image
)) {
6457 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
6458 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(surf
->u
.legacy
.fmask
.pitch_in_pixels
/ 8 - 1);
6459 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(surf
->u
.legacy
.fmask
.tiling_index
);
6460 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(surf
->u
.legacy
.fmask
.slice_tile_max
);
6462 /* This must be set for fast clear to work without FMASK. */
6463 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
6464 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
6465 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
6466 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
6470 /* CMASK variables */
6471 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
6472 va
+= iview
->image
->cmask_offset
;
6473 cb
->cb_color_cmask
= va
>> 8;
6475 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
6476 va
+= iview
->image
->dcc_offset
;
6478 if (radv_dcc_enabled(iview
->image
, iview
->base_mip
) &&
6479 device
->physical_device
->rad_info
.chip_class
<= GFX8
)
6480 va
+= plane
->surface
.u
.legacy
.level
[iview
->base_mip
].dcc_offset
;
6482 unsigned dcc_tile_swizzle
= surf
->tile_swizzle
;
6483 dcc_tile_swizzle
&= (surf
->dcc_alignment
- 1) >> 8;
6485 cb
->cb_dcc_base
= va
>> 8;
6486 cb
->cb_dcc_base
|= dcc_tile_swizzle
;
6488 /* GFX10 field has the same base shift as the GFX6 field. */
6489 uint32_t max_slice
= radv_surface_max_layer_count(iview
) - 1;
6490 cb
->cb_color_view
= S_028C6C_SLICE_START(iview
->base_layer
) |
6491 S_028C6C_SLICE_MAX_GFX10(max_slice
);
6493 if (iview
->image
->info
.samples
> 1) {
6494 unsigned log_samples
= util_logbase2(iview
->image
->info
.samples
);
6496 cb
->cb_color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
6497 S_028C74_NUM_FRAGMENTS(log_samples
);
6500 if (radv_image_has_fmask(iview
->image
)) {
6501 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+ iview
->image
->fmask_offset
;
6502 cb
->cb_color_fmask
= va
>> 8;
6503 cb
->cb_color_fmask
|= surf
->fmask_tile_swizzle
;
6505 cb
->cb_color_fmask
= cb
->cb_color_base
;
6508 ntype
= radv_translate_color_numformat(iview
->vk_format
,
6510 vk_format_get_first_non_void_channel(iview
->vk_format
));
6511 format
= radv_translate_colorformat(iview
->vk_format
);
6512 if (format
== V_028C70_COLOR_INVALID
|| ntype
== ~0u)
6513 radv_finishme("Illegal color\n");
6514 swap
= radv_translate_colorswap(iview
->vk_format
, false);
6515 endian
= radv_colorformat_endian_swap(format
);
6517 /* blend clamp should be set for all NORM/SRGB types */
6518 if (ntype
== V_028C70_NUMBER_UNORM
||
6519 ntype
== V_028C70_NUMBER_SNORM
||
6520 ntype
== V_028C70_NUMBER_SRGB
)
6523 /* set blend bypass according to docs if SINT/UINT or
6524 8/24 COLOR variants */
6525 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
6526 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
6527 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
6532 if ((ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) &&
6533 (format
== V_028C70_COLOR_8
||
6534 format
== V_028C70_COLOR_8_8
||
6535 format
== V_028C70_COLOR_8_8_8_8
))
6536 ->color_is_int8
= true;
6538 cb
->cb_color_info
= S_028C70_FORMAT(format
) |
6539 S_028C70_COMP_SWAP(swap
) |
6540 S_028C70_BLEND_CLAMP(blend_clamp
) |
6541 S_028C70_BLEND_BYPASS(blend_bypass
) |
6542 S_028C70_SIMPLE_FLOAT(1) |
6543 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
6544 ntype
!= V_028C70_NUMBER_SNORM
&&
6545 ntype
!= V_028C70_NUMBER_SRGB
&&
6546 format
!= V_028C70_COLOR_8_24
&&
6547 format
!= V_028C70_COLOR_24_8
) |
6548 S_028C70_NUMBER_TYPE(ntype
) |
6549 S_028C70_ENDIAN(endian
);
6550 if (radv_image_has_fmask(iview
->image
)) {
6551 cb
->cb_color_info
|= S_028C70_COMPRESSION(1);
6552 if (device
->physical_device
->rad_info
.chip_class
== GFX6
) {
6553 unsigned fmask_bankh
= util_logbase2(surf
->u
.legacy
.fmask
.bankh
);
6554 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
6557 if (radv_image_is_tc_compat_cmask(iview
->image
)) {
6558 /* Allow the texture block to read FMASK directly
6559 * without decompressing it. This bit must be cleared
6560 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
6561 * otherwise the operation doesn't happen.
6563 cb
->cb_color_info
|= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
6565 /* Set CMASK into a tiling format that allows the
6566 * texture block to read it.
6568 cb
->cb_color_info
|= S_028C70_CMASK_ADDR_TYPE(2);
6572 if (radv_image_has_cmask(iview
->image
) &&
6573 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_FAST_CLEARS
))
6574 cb
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
6576 if (radv_dcc_enabled(iview
->image
, iview
->base_mip
))
6577 cb
->cb_color_info
|= S_028C70_DCC_ENABLE(1);
6579 cb
->cb_dcc_control
= radv_init_dcc_control_reg(device
, iview
);
6581 /* This must be set for fast clear to work without FMASK. */
6582 if (!radv_image_has_fmask(iview
->image
) &&
6583 device
->physical_device
->rad_info
.chip_class
== GFX6
) {
6584 unsigned bankh
= util_logbase2(surf
->u
.legacy
.bankh
);
6585 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
6588 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
6589 const struct vk_format_description
*format_desc
= vk_format_description(iview
->image
->vk_format
);
6591 unsigned mip0_depth
= iview
->image
->type
== VK_IMAGE_TYPE_3D
?
6592 (iview
->extent
.depth
- 1) : (iview
->image
->info
.array_size
- 1);
6593 unsigned width
= iview
->extent
.width
/ (iview
->plane_id
? format_desc
->width_divisor
: 1);
6594 unsigned height
= iview
->extent
.height
/ (iview
->plane_id
? format_desc
->height_divisor
: 1);
6596 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6597 cb
->cb_color_view
|= S_028C6C_MIP_LEVEL_GFX10(iview
->base_mip
);
6599 cb
->cb_color_attrib3
|= S_028EE0_MIP0_DEPTH(mip0_depth
) |
6600 S_028EE0_RESOURCE_TYPE(surf
->u
.gfx9
.resource_type
) |
6601 S_028EE0_RESOURCE_LEVEL(1);
6603 cb
->cb_color_view
|= S_028C6C_MIP_LEVEL_GFX9(iview
->base_mip
);
6604 cb
->cb_color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
6605 S_028C74_RESOURCE_TYPE(surf
->u
.gfx9
.resource_type
);
6608 cb
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(width
- 1) |
6609 S_028C68_MIP0_HEIGHT(height
- 1) |
6610 S_028C68_MAX_MIP(iview
->image
->info
.levels
- 1);
6615 radv_calc_decompress_on_z_planes(struct radv_device
*device
,
6616 struct radv_image_view
*iview
)
6618 unsigned max_zplanes
= 0;
6620 assert(radv_image_is_tc_compat_htile(iview
->image
));
6622 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
6623 /* Default value for 32-bit depth surfaces. */
6626 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
&&
6627 iview
->image
->info
.samples
> 1)
6630 max_zplanes
= max_zplanes
+ 1;
6632 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
) {
6633 /* Do not enable Z plane compression for 16-bit depth
6634 * surfaces because isn't supported on GFX8. Only
6635 * 32-bit depth surfaces are supported by the hardware.
6636 * This allows to maintain shader compatibility and to
6637 * reduce the number of depth decompressions.
6641 if (iview
->image
->info
.samples
<= 1)
6643 else if (iview
->image
->info
.samples
<= 4)
6654 radv_initialise_ds_surface(struct radv_device
*device
,
6655 struct radv_ds_buffer_info
*ds
,
6656 struct radv_image_view
*iview
)
6658 unsigned level
= iview
->base_mip
;
6659 unsigned format
, stencil_format
;
6660 uint64_t va
, s_offs
, z_offs
;
6661 bool stencil_only
= false;
6662 const struct radv_image_plane
*plane
= &iview
->image
->planes
[0];
6663 const struct radeon_surf
*surf
= &plane
->surface
;
6665 assert(vk_format_get_plane_count(iview
->image
->vk_format
) == 1);
6667 memset(ds
, 0, sizeof(*ds
));
6668 switch (iview
->image
->vk_format
) {
6669 case VK_FORMAT_D24_UNORM_S8_UINT
:
6670 case VK_FORMAT_X8_D24_UNORM_PACK32
:
6671 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
6672 ds
->offset_scale
= 2.0f
;
6674 case VK_FORMAT_D16_UNORM
:
6675 case VK_FORMAT_D16_UNORM_S8_UINT
:
6676 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
6677 ds
->offset_scale
= 4.0f
;
6679 case VK_FORMAT_D32_SFLOAT
:
6680 case VK_FORMAT_D32_SFLOAT_S8_UINT
:
6681 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
6682 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
6683 ds
->offset_scale
= 1.0f
;
6685 case VK_FORMAT_S8_UINT
:
6686 stencil_only
= true;
6692 format
= radv_translate_dbformat(iview
->image
->vk_format
);
6693 stencil_format
= surf
->has_stencil
?
6694 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
6696 uint32_t max_slice
= radv_surface_max_layer_count(iview
) - 1;
6697 ds
->db_depth_view
= S_028008_SLICE_START(iview
->base_layer
) |
6698 S_028008_SLICE_MAX(max_slice
);
6699 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6700 ds
->db_depth_view
|= S_028008_SLICE_START_HI(iview
->base_layer
>> 11) |
6701 S_028008_SLICE_MAX_HI(max_slice
>> 11);
6704 ds
->db_htile_data_base
= 0;
6705 ds
->db_htile_surface
= 0;
6707 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
6708 s_offs
= z_offs
= va
;
6710 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
6711 assert(surf
->u
.gfx9
.surf_offset
== 0);
6712 s_offs
+= surf
->u
.gfx9
.stencil_offset
;
6714 ds
->db_z_info
= S_028038_FORMAT(format
) |
6715 S_028038_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
)) |
6716 S_028038_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
6717 S_028038_MAXMIP(iview
->image
->info
.levels
- 1) |
6718 S_028038_ZRANGE_PRECISION(1);
6719 ds
->db_stencil_info
= S_02803C_FORMAT(stencil_format
) |
6720 S_02803C_SW_MODE(surf
->u
.gfx9
.stencil
.swizzle_mode
);
6722 if (device
->physical_device
->rad_info
.chip_class
== GFX9
) {
6723 ds
->db_z_info2
= S_028068_EPITCH(surf
->u
.gfx9
.surf
.epitch
);
6724 ds
->db_stencil_info2
= S_02806C_EPITCH(surf
->u
.gfx9
.stencil
.epitch
);
6727 ds
->db_depth_view
|= S_028008_MIPID(level
);
6728 ds
->db_depth_size
= S_02801C_X_MAX(iview
->image
->info
.width
- 1) |
6729 S_02801C_Y_MAX(iview
->image
->info
.height
- 1);
6731 if (radv_htile_enabled(iview
->image
, level
)) {
6732 ds
->db_z_info
|= S_028038_TILE_SURFACE_ENABLE(1);
6734 if (radv_image_is_tc_compat_htile(iview
->image
)) {
6735 unsigned max_zplanes
=
6736 radv_calc_decompress_on_z_planes(device
, iview
);
6738 ds
->db_z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
);
6740 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6741 ds
->db_z_info
|= S_028040_ITERATE_FLUSH(1);
6742 ds
->db_stencil_info
|= S_028044_ITERATE_FLUSH(1);
6744 ds
->db_z_info
|= S_028038_ITERATE_FLUSH(1);
6745 ds
->db_stencil_info
|= S_02803C_ITERATE_FLUSH(1);
6749 if (!surf
->has_stencil
)
6750 /* Use all of the htile_buffer for depth if there's no stencil. */
6751 ds
->db_stencil_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
6752 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
6753 iview
->image
->htile_offset
;
6754 ds
->db_htile_data_base
= va
>> 8;
6755 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1) |
6756 S_028ABC_PIPE_ALIGNED(surf
->u
.gfx9
.htile
.pipe_aligned
);
6758 if (device
->physical_device
->rad_info
.chip_class
== GFX9
) {
6759 ds
->db_htile_surface
|= S_028ABC_RB_ALIGNED(surf
->u
.gfx9
.htile
.rb_aligned
);
6763 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[level
];
6766 level_info
= &surf
->u
.legacy
.stencil_level
[level
];
6768 z_offs
+= surf
->u
.legacy
.level
[level
].offset
;
6769 s_offs
+= surf
->u
.legacy
.stencil_level
[level
].offset
;
6771 ds
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview
->image
));
6772 ds
->db_z_info
= S_028040_FORMAT(format
) | S_028040_ZRANGE_PRECISION(1);
6773 ds
->db_stencil_info
= S_028044_FORMAT(stencil_format
);
6775 if (iview
->image
->info
.samples
> 1)
6776 ds
->db_z_info
|= S_028040_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
));
6778 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
6779 struct radeon_info
*info
= &device
->physical_device
->rad_info
;
6780 unsigned tiling_index
= surf
->u
.legacy
.tiling_index
[level
];
6781 unsigned stencil_index
= surf
->u
.legacy
.stencil_tiling_index
[level
];
6782 unsigned macro_index
= surf
->u
.legacy
.macro_tile_index
;
6783 unsigned tile_mode
= info
->si_tile_mode_array
[tiling_index
];
6784 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
6785 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
6788 tile_mode
= stencil_tile_mode
;
6790 ds
->db_depth_info
|=
6791 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
6792 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
6793 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
6794 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
6795 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
6796 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
6797 ds
->db_z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
6798 ds
->db_stencil_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
6800 unsigned tile_mode_index
= si_tile_mode_index(&iview
->image
->planes
[0], level
, false);
6801 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
6802 tile_mode_index
= si_tile_mode_index(&iview
->image
->planes
[0], level
, true);
6803 ds
->db_stencil_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
6805 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
6808 ds
->db_depth_size
= S_028058_PITCH_TILE_MAX((level_info
->nblk_x
/ 8) - 1) |
6809 S_028058_HEIGHT_TILE_MAX((level_info
->nblk_y
/ 8) - 1);
6810 ds
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1);
6812 if (radv_htile_enabled(iview
->image
, level
)) {
6813 ds
->db_z_info
|= S_028040_TILE_SURFACE_ENABLE(1);
6815 if (!surf
->has_stencil
&&
6816 !radv_image_is_tc_compat_htile(iview
->image
))
6817 /* Use all of the htile_buffer for depth if there's no stencil. */
6818 ds
->db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
6820 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
6821 iview
->image
->htile_offset
;
6822 ds
->db_htile_data_base
= va
>> 8;
6823 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
6825 if (radv_image_is_tc_compat_htile(iview
->image
)) {
6826 unsigned max_zplanes
=
6827 radv_calc_decompress_on_z_planes(device
, iview
);
6829 ds
->db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
6830 ds
->db_z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes
);
6835 ds
->db_z_read_base
= ds
->db_z_write_base
= z_offs
>> 8;
6836 ds
->db_stencil_read_base
= ds
->db_stencil_write_base
= s_offs
>> 8;
6839 VkResult
radv_CreateFramebuffer(
6841 const VkFramebufferCreateInfo
* pCreateInfo
,
6842 const VkAllocationCallbacks
* pAllocator
,
6843 VkFramebuffer
* pFramebuffer
)
6845 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6846 struct radv_framebuffer
*framebuffer
;
6847 const VkFramebufferAttachmentsCreateInfo
*imageless_create_info
=
6848 vk_find_struct_const(pCreateInfo
->pNext
,
6849 FRAMEBUFFER_ATTACHMENTS_CREATE_INFO
);
6851 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
);
6853 size_t size
= sizeof(*framebuffer
);
6854 if (!imageless_create_info
)
6855 size
+= sizeof(struct radv_image_view
*) * pCreateInfo
->attachmentCount
;
6856 framebuffer
= vk_alloc2(&device
->alloc
, pAllocator
, size
, 8,
6857 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
6858 if (framebuffer
== NULL
)
6859 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6861 framebuffer
->attachment_count
= pCreateInfo
->attachmentCount
;
6862 framebuffer
->width
= pCreateInfo
->width
;
6863 framebuffer
->height
= pCreateInfo
->height
;
6864 framebuffer
->layers
= pCreateInfo
->layers
;
6865 if (imageless_create_info
) {
6866 for (unsigned i
= 0; i
< imageless_create_info
->attachmentImageInfoCount
; ++i
) {
6867 const VkFramebufferAttachmentImageInfo
*attachment
=
6868 imageless_create_info
->pAttachmentImageInfos
+ i
;
6869 framebuffer
->width
= MIN2(framebuffer
->width
, attachment
->width
);
6870 framebuffer
->height
= MIN2(framebuffer
->height
, attachment
->height
);
6871 framebuffer
->layers
= MIN2(framebuffer
->layers
, attachment
->layerCount
);
6874 for (uint32_t i
= 0; i
< pCreateInfo
->attachmentCount
; i
++) {
6875 VkImageView _iview
= pCreateInfo
->pAttachments
[i
];
6876 struct radv_image_view
*iview
= radv_image_view_from_handle(_iview
);
6877 framebuffer
->attachments
[i
] = iview
;
6878 framebuffer
->width
= MIN2(framebuffer
->width
, iview
->extent
.width
);
6879 framebuffer
->height
= MIN2(framebuffer
->height
, iview
->extent
.height
);
6880 framebuffer
->layers
= MIN2(framebuffer
->layers
, radv_surface_max_layer_count(iview
));
6884 *pFramebuffer
= radv_framebuffer_to_handle(framebuffer
);
6888 void radv_DestroyFramebuffer(
6891 const VkAllocationCallbacks
* pAllocator
)
6893 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6894 RADV_FROM_HANDLE(radv_framebuffer
, fb
, _fb
);
6898 vk_free2(&device
->alloc
, pAllocator
, fb
);
6901 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode
)
6903 switch (address_mode
) {
6904 case VK_SAMPLER_ADDRESS_MODE_REPEAT
:
6905 return V_008F30_SQ_TEX_WRAP
;
6906 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT
:
6907 return V_008F30_SQ_TEX_MIRROR
;
6908 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE
:
6909 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
6910 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER
:
6911 return V_008F30_SQ_TEX_CLAMP_BORDER
;
6912 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE
:
6913 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
6915 unreachable("illegal tex wrap mode");
6921 radv_tex_compare(VkCompareOp op
)
6924 case VK_COMPARE_OP_NEVER
:
6925 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
6926 case VK_COMPARE_OP_LESS
:
6927 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
6928 case VK_COMPARE_OP_EQUAL
:
6929 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
6930 case VK_COMPARE_OP_LESS_OR_EQUAL
:
6931 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
6932 case VK_COMPARE_OP_GREATER
:
6933 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
6934 case VK_COMPARE_OP_NOT_EQUAL
:
6935 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
6936 case VK_COMPARE_OP_GREATER_OR_EQUAL
:
6937 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
6938 case VK_COMPARE_OP_ALWAYS
:
6939 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
6941 unreachable("illegal compare mode");
6947 radv_tex_filter(VkFilter filter
, unsigned max_ansio
)
6950 case VK_FILTER_NEAREST
:
6951 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
:
6952 V_008F38_SQ_TEX_XY_FILTER_POINT
);
6953 case VK_FILTER_LINEAR
:
6954 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
:
6955 V_008F38_SQ_TEX_XY_FILTER_BILINEAR
);
6956 case VK_FILTER_CUBIC_IMG
:
6958 fprintf(stderr
, "illegal texture filter");
6964 radv_tex_mipfilter(VkSamplerMipmapMode mode
)
6967 case VK_SAMPLER_MIPMAP_MODE_NEAREST
:
6968 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
6969 case VK_SAMPLER_MIPMAP_MODE_LINEAR
:
6970 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
6972 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
6977 radv_tex_bordercolor(VkBorderColor bcolor
)
6980 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK
:
6981 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK
:
6982 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
6983 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK
:
6984 case VK_BORDER_COLOR_INT_OPAQUE_BLACK
:
6985 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK
;
6986 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE
:
6987 case VK_BORDER_COLOR_INT_OPAQUE_WHITE
:
6988 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE
;
6996 radv_tex_aniso_filter(unsigned filter
)
7010 radv_tex_filter_mode(VkSamplerReductionMode mode
)
7013 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT
:
7014 return V_008F30_SQ_IMG_FILTER_MODE_BLEND
;
7015 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT
:
7016 return V_008F30_SQ_IMG_FILTER_MODE_MIN
;
7017 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT
:
7018 return V_008F30_SQ_IMG_FILTER_MODE_MAX
;
7026 radv_get_max_anisotropy(struct radv_device
*device
,
7027 const VkSamplerCreateInfo
*pCreateInfo
)
7029 if (device
->force_aniso
>= 0)
7030 return device
->force_aniso
;
7032 if (pCreateInfo
->anisotropyEnable
&&
7033 pCreateInfo
->maxAnisotropy
> 1.0f
)
7034 return (uint32_t)pCreateInfo
->maxAnisotropy
;
7039 static inline int S_FIXED(float value
, unsigned frac_bits
)
7041 return value
* (1 << frac_bits
);
7045 radv_init_sampler(struct radv_device
*device
,
7046 struct radv_sampler
*sampler
,
7047 const VkSamplerCreateInfo
*pCreateInfo
)
7049 uint32_t max_aniso
= radv_get_max_anisotropy(device
, pCreateInfo
);
7050 uint32_t max_aniso_ratio
= radv_tex_aniso_filter(max_aniso
);
7051 bool compat_mode
= device
->physical_device
->rad_info
.chip_class
== GFX8
||
7052 device
->physical_device
->rad_info
.chip_class
== GFX9
;
7053 unsigned filter_mode
= V_008F30_SQ_IMG_FILTER_MODE_BLEND
;
7054 unsigned depth_compare_func
= V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
7056 const struct VkSamplerReductionModeCreateInfo
*sampler_reduction
=
7057 vk_find_struct_const(pCreateInfo
->pNext
,
7058 SAMPLER_REDUCTION_MODE_CREATE_INFO
);
7059 if (sampler_reduction
)
7060 filter_mode
= radv_tex_filter_mode(sampler_reduction
->reductionMode
);
7062 if (pCreateInfo
->compareEnable
)
7063 depth_compare_func
= radv_tex_compare(pCreateInfo
->compareOp
);
7065 sampler
->state
[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo
->addressModeU
)) |
7066 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo
->addressModeV
)) |
7067 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo
->addressModeW
)) |
7068 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
7069 S_008F30_DEPTH_COMPARE_FUNC(depth_compare_func
) |
7070 S_008F30_FORCE_UNNORMALIZED(pCreateInfo
->unnormalizedCoordinates
? 1 : 0) |
7071 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
7072 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
7073 S_008F30_DISABLE_CUBE_WRAP(0) |
7074 S_008F30_COMPAT_MODE(compat_mode
) |
7075 S_008F30_FILTER_MODE(filter_mode
));
7076 sampler
->state
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo
->minLod
, 0, 15), 8)) |
7077 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo
->maxLod
, 0, 15), 8)) |
7078 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
7079 sampler
->state
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo
->mipLodBias
, -16, 16), 8)) |
7080 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo
->magFilter
, max_aniso
)) |
7081 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo
->minFilter
, max_aniso
)) |
7082 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo
->mipmapMode
)) |
7083 S_008F38_MIP_POINT_PRECLAMP(0));
7084 sampler
->state
[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
7085 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo
->borderColor
)));
7087 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
7088 sampler
->state
[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
7090 sampler
->state
[2] |=
7091 S_008F38_DISABLE_LSB_CEIL(device
->physical_device
->rad_info
.chip_class
<= GFX8
) |
7092 S_008F38_FILTER_PREC_FIX(1) |
7093 S_008F38_ANISO_OVERRIDE_GFX6(device
->physical_device
->rad_info
.chip_class
>= GFX8
);
7097 VkResult
radv_CreateSampler(
7099 const VkSamplerCreateInfo
* pCreateInfo
,
7100 const VkAllocationCallbacks
* pAllocator
,
7101 VkSampler
* pSampler
)
7103 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7104 struct radv_sampler
*sampler
;
7106 const struct VkSamplerYcbcrConversionInfo
*ycbcr_conversion
=
7107 vk_find_struct_const(pCreateInfo
->pNext
,
7108 SAMPLER_YCBCR_CONVERSION_INFO
);
7110 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO
);
7112 sampler
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*sampler
), 8,
7113 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
7115 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
7117 radv_init_sampler(device
, sampler
, pCreateInfo
);
7119 sampler
->ycbcr_sampler
= ycbcr_conversion
? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion
->conversion
): NULL
;
7120 *pSampler
= radv_sampler_to_handle(sampler
);
7125 void radv_DestroySampler(
7128 const VkAllocationCallbacks
* pAllocator
)
7130 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7131 RADV_FROM_HANDLE(radv_sampler
, sampler
, _sampler
);
7135 vk_free2(&device
->alloc
, pAllocator
, sampler
);
7138 /* vk_icd.h does not declare this function, so we declare it here to
7139 * suppress Wmissing-prototypes.
7141 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
7142 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
);
7144 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
7145 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
)
7147 /* For the full details on loader interface versioning, see
7148 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
7149 * What follows is a condensed summary, to help you navigate the large and
7150 * confusing official doc.
7152 * - Loader interface v0 is incompatible with later versions. We don't
7155 * - In loader interface v1:
7156 * - The first ICD entrypoint called by the loader is
7157 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
7159 * - The ICD must statically expose no other Vulkan symbol unless it is
7160 * linked with -Bsymbolic.
7161 * - Each dispatchable Vulkan handle created by the ICD must be
7162 * a pointer to a struct whose first member is VK_LOADER_DATA. The
7163 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
7164 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
7165 * vkDestroySurfaceKHR(). The ICD must be capable of working with
7166 * such loader-managed surfaces.
7168 * - Loader interface v2 differs from v1 in:
7169 * - The first ICD entrypoint called by the loader is
7170 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
7171 * statically expose this entrypoint.
7173 * - Loader interface v3 differs from v2 in:
7174 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
7175 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
7176 * because the loader no longer does so.
7178 *pSupportedVersion
= MIN2(*pSupportedVersion
, 4u);
7182 VkResult
radv_GetMemoryFdKHR(VkDevice _device
,
7183 const VkMemoryGetFdInfoKHR
*pGetFdInfo
,
7186 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7187 RADV_FROM_HANDLE(radv_device_memory
, memory
, pGetFdInfo
->memory
);
7189 assert(pGetFdInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR
);
7191 /* At the moment, we support only the below handle types. */
7192 assert(pGetFdInfo
->handleType
==
7193 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT
||
7194 pGetFdInfo
->handleType
==
7195 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
7197 bool ret
= radv_get_memory_fd(device
, memory
, pFD
);
7199 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
7203 VkResult
radv_GetMemoryFdPropertiesKHR(VkDevice _device
,
7204 VkExternalMemoryHandleTypeFlagBits handleType
,
7206 VkMemoryFdPropertiesKHR
*pMemoryFdProperties
)
7208 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7210 switch (handleType
) {
7211 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
:
7212 pMemoryFdProperties
->memoryTypeBits
= (1 << RADV_MEM_TYPE_COUNT
) - 1;
7216 /* The valid usage section for this function says:
7218 * "handleType must not be one of the handle types defined as
7221 * So opaque handle types fall into the default "unsupported" case.
7223 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7227 static VkResult
radv_import_opaque_fd(struct radv_device
*device
,
7231 uint32_t syncobj_handle
= 0;
7232 int ret
= device
->ws
->import_syncobj(device
->ws
, fd
, &syncobj_handle
);
7234 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7237 device
->ws
->destroy_syncobj(device
->ws
, *syncobj
);
7239 *syncobj
= syncobj_handle
;
7245 static VkResult
radv_import_sync_fd(struct radv_device
*device
,
7249 /* If we create a syncobj we do it locally so that if we have an error, we don't
7250 * leave a syncobj in an undetermined state in the fence. */
7251 uint32_t syncobj_handle
= *syncobj
;
7252 if (!syncobj_handle
) {
7253 int ret
= device
->ws
->create_syncobj(device
->ws
, &syncobj_handle
);
7255 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7260 device
->ws
->signal_syncobj(device
->ws
, syncobj_handle
);
7262 int ret
= device
->ws
->import_syncobj_from_sync_file(device
->ws
, syncobj_handle
, fd
);
7264 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7267 *syncobj
= syncobj_handle
;
7274 VkResult
radv_ImportSemaphoreFdKHR(VkDevice _device
,
7275 const VkImportSemaphoreFdInfoKHR
*pImportSemaphoreFdInfo
)
7277 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7278 RADV_FROM_HANDLE(radv_semaphore
, sem
, pImportSemaphoreFdInfo
->semaphore
);
7280 struct radv_semaphore_part
*dst
= NULL
;
7282 if (pImportSemaphoreFdInfo
->flags
& VK_SEMAPHORE_IMPORT_TEMPORARY_BIT
) {
7283 dst
= &sem
->temporary
;
7285 dst
= &sem
->permanent
;
7288 uint32_t syncobj
= dst
->kind
== RADV_SEMAPHORE_SYNCOBJ
? dst
->syncobj
: 0;
7290 switch(pImportSemaphoreFdInfo
->handleType
) {
7291 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
:
7292 result
= radv_import_opaque_fd(device
, pImportSemaphoreFdInfo
->fd
, &syncobj
);
7294 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
:
7295 result
= radv_import_sync_fd(device
, pImportSemaphoreFdInfo
->fd
, &syncobj
);
7298 unreachable("Unhandled semaphore handle type");
7301 if (result
== VK_SUCCESS
) {
7302 dst
->syncobj
= syncobj
;
7303 dst
->kind
= RADV_SEMAPHORE_SYNCOBJ
;
7309 VkResult
radv_GetSemaphoreFdKHR(VkDevice _device
,
7310 const VkSemaphoreGetFdInfoKHR
*pGetFdInfo
,
7313 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7314 RADV_FROM_HANDLE(radv_semaphore
, sem
, pGetFdInfo
->semaphore
);
7316 uint32_t syncobj_handle
;
7318 if (sem
->temporary
.kind
!= RADV_SEMAPHORE_NONE
) {
7319 assert(sem
->temporary
.kind
== RADV_SEMAPHORE_SYNCOBJ
);
7320 syncobj_handle
= sem
->temporary
.syncobj
;
7322 assert(sem
->permanent
.kind
== RADV_SEMAPHORE_SYNCOBJ
);
7323 syncobj_handle
= sem
->permanent
.syncobj
;
7326 switch(pGetFdInfo
->handleType
) {
7327 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
:
7328 ret
= device
->ws
->export_syncobj(device
->ws
, syncobj_handle
, pFd
);
7330 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
:
7331 ret
= device
->ws
->export_syncobj_to_sync_file(device
->ws
, syncobj_handle
, pFd
);
7333 if (sem
->temporary
.kind
!= RADV_SEMAPHORE_NONE
) {
7334 radv_destroy_semaphore_part(device
, &sem
->temporary
);
7336 device
->ws
->reset_syncobj(device
->ws
, syncobj_handle
);
7341 unreachable("Unhandled semaphore handle type");
7345 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7349 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
7350 VkPhysicalDevice physicalDevice
,
7351 const VkPhysicalDeviceExternalSemaphoreInfo
*pExternalSemaphoreInfo
,
7352 VkExternalSemaphoreProperties
*pExternalSemaphoreProperties
)
7354 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
7355 VkSemaphoreTypeKHR type
= radv_get_semaphore_type(pExternalSemaphoreInfo
->pNext
, NULL
);
7357 if (type
== VK_SEMAPHORE_TYPE_TIMELINE
) {
7358 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= 0;
7359 pExternalSemaphoreProperties
->compatibleHandleTypes
= 0;
7360 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= 0;
7362 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
7363 } else if (pdevice
->rad_info
.has_syncobj_wait_for_submit
&&
7364 (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
||
7365 pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
)) {
7366 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
;
7367 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
;
7368 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT
|
7369 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
7370 } else if (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
) {
7371 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
7372 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
7373 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT
|
7374 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
7376 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= 0;
7377 pExternalSemaphoreProperties
->compatibleHandleTypes
= 0;
7378 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= 0;
7382 VkResult
radv_ImportFenceFdKHR(VkDevice _device
,
7383 const VkImportFenceFdInfoKHR
*pImportFenceFdInfo
)
7385 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7386 RADV_FROM_HANDLE(radv_fence
, fence
, pImportFenceFdInfo
->fence
);
7387 uint32_t *syncobj_dst
= NULL
;
7390 if (pImportFenceFdInfo
->flags
& VK_FENCE_IMPORT_TEMPORARY_BIT
) {
7391 syncobj_dst
= &fence
->temp_syncobj
;
7393 syncobj_dst
= &fence
->syncobj
;
7396 switch(pImportFenceFdInfo
->handleType
) {
7397 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
:
7398 return radv_import_opaque_fd(device
, pImportFenceFdInfo
->fd
, syncobj_dst
);
7399 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
:
7400 return radv_import_sync_fd(device
, pImportFenceFdInfo
->fd
, syncobj_dst
);
7402 unreachable("Unhandled fence handle type");
7406 VkResult
radv_GetFenceFdKHR(VkDevice _device
,
7407 const VkFenceGetFdInfoKHR
*pGetFdInfo
,
7410 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7411 RADV_FROM_HANDLE(radv_fence
, fence
, pGetFdInfo
->fence
);
7413 uint32_t syncobj_handle
;
7415 if (fence
->temp_syncobj
)
7416 syncobj_handle
= fence
->temp_syncobj
;
7418 syncobj_handle
= fence
->syncobj
;
7420 switch(pGetFdInfo
->handleType
) {
7421 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
:
7422 ret
= device
->ws
->export_syncobj(device
->ws
, syncobj_handle
, pFd
);
7424 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
:
7425 ret
= device
->ws
->export_syncobj_to_sync_file(device
->ws
, syncobj_handle
, pFd
);
7427 if (fence
->temp_syncobj
) {
7428 close (fence
->temp_syncobj
);
7429 fence
->temp_syncobj
= 0;
7431 device
->ws
->reset_syncobj(device
->ws
, syncobj_handle
);
7436 unreachable("Unhandled fence handle type");
7440 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7444 void radv_GetPhysicalDeviceExternalFenceProperties(
7445 VkPhysicalDevice physicalDevice
,
7446 const VkPhysicalDeviceExternalFenceInfo
*pExternalFenceInfo
,
7447 VkExternalFenceProperties
*pExternalFenceProperties
)
7449 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
7451 if (pdevice
->rad_info
.has_syncobj_wait_for_submit
&&
7452 (pExternalFenceInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
||
7453 pExternalFenceInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
)) {
7454 pExternalFenceProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
;
7455 pExternalFenceProperties
->compatibleHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
;
7456 pExternalFenceProperties
->externalFenceFeatures
= VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT
|
7457 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
7459 pExternalFenceProperties
->exportFromImportedHandleTypes
= 0;
7460 pExternalFenceProperties
->compatibleHandleTypes
= 0;
7461 pExternalFenceProperties
->externalFenceFeatures
= 0;
7466 radv_CreateDebugReportCallbackEXT(VkInstance _instance
,
7467 const VkDebugReportCallbackCreateInfoEXT
* pCreateInfo
,
7468 const VkAllocationCallbacks
* pAllocator
,
7469 VkDebugReportCallbackEXT
* pCallback
)
7471 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
7472 return vk_create_debug_report_callback(&instance
->debug_report_callbacks
,
7473 pCreateInfo
, pAllocator
, &instance
->alloc
,
7478 radv_DestroyDebugReportCallbackEXT(VkInstance _instance
,
7479 VkDebugReportCallbackEXT _callback
,
7480 const VkAllocationCallbacks
* pAllocator
)
7482 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
7483 vk_destroy_debug_report_callback(&instance
->debug_report_callbacks
,
7484 _callback
, pAllocator
, &instance
->alloc
);
7488 radv_DebugReportMessageEXT(VkInstance _instance
,
7489 VkDebugReportFlagsEXT flags
,
7490 VkDebugReportObjectTypeEXT objectType
,
7493 int32_t messageCode
,
7494 const char* pLayerPrefix
,
7495 const char* pMessage
)
7497 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
7498 vk_debug_report(&instance
->debug_report_callbacks
, flags
, objectType
,
7499 object
, location
, messageCode
, pLayerPrefix
, pMessage
);
7503 radv_GetDeviceGroupPeerMemoryFeatures(
7506 uint32_t localDeviceIndex
,
7507 uint32_t remoteDeviceIndex
,
7508 VkPeerMemoryFeatureFlags
* pPeerMemoryFeatures
)
7510 assert(localDeviceIndex
== remoteDeviceIndex
);
7512 *pPeerMemoryFeatures
= VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT
|
7513 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT
|
7514 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT
|
7515 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT
;
7518 static const VkTimeDomainEXT radv_time_domains
[] = {
7519 VK_TIME_DOMAIN_DEVICE_EXT
,
7520 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT
,
7521 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT
,
7524 VkResult
radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
7525 VkPhysicalDevice physicalDevice
,
7526 uint32_t *pTimeDomainCount
,
7527 VkTimeDomainEXT
*pTimeDomains
)
7530 VK_OUTARRAY_MAKE(out
, pTimeDomains
, pTimeDomainCount
);
7532 for (d
= 0; d
< ARRAY_SIZE(radv_time_domains
); d
++) {
7533 vk_outarray_append(&out
, i
) {
7534 *i
= radv_time_domains
[d
];
7538 return vk_outarray_status(&out
);
7542 radv_clock_gettime(clockid_t clock_id
)
7544 struct timespec current
;
7547 ret
= clock_gettime(clock_id
, ¤t
);
7548 if (ret
< 0 && clock_id
== CLOCK_MONOTONIC_RAW
)
7549 ret
= clock_gettime(CLOCK_MONOTONIC
, ¤t
);
7553 return (uint64_t) current
.tv_sec
* 1000000000ULL + current
.tv_nsec
;
7556 VkResult
radv_GetCalibratedTimestampsEXT(
7558 uint32_t timestampCount
,
7559 const VkCalibratedTimestampInfoEXT
*pTimestampInfos
,
7560 uint64_t *pTimestamps
,
7561 uint64_t *pMaxDeviation
)
7563 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7564 uint32_t clock_crystal_freq
= device
->physical_device
->rad_info
.clock_crystal_freq
;
7566 uint64_t begin
, end
;
7567 uint64_t max_clock_period
= 0;
7569 begin
= radv_clock_gettime(CLOCK_MONOTONIC_RAW
);
7571 for (d
= 0; d
< timestampCount
; d
++) {
7572 switch (pTimestampInfos
[d
].timeDomain
) {
7573 case VK_TIME_DOMAIN_DEVICE_EXT
:
7574 pTimestamps
[d
] = device
->ws
->query_value(device
->ws
,
7576 uint64_t device_period
= DIV_ROUND_UP(1000000, clock_crystal_freq
);
7577 max_clock_period
= MAX2(max_clock_period
, device_period
);
7579 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT
:
7580 pTimestamps
[d
] = radv_clock_gettime(CLOCK_MONOTONIC
);
7581 max_clock_period
= MAX2(max_clock_period
, 1);
7584 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT
:
7585 pTimestamps
[d
] = begin
;
7593 end
= radv_clock_gettime(CLOCK_MONOTONIC_RAW
);
7596 * The maximum deviation is the sum of the interval over which we
7597 * perform the sampling and the maximum period of any sampled
7598 * clock. That's because the maximum skew between any two sampled
7599 * clock edges is when the sampled clock with the largest period is
7600 * sampled at the end of that period but right at the beginning of the
7601 * sampling interval and some other clock is sampled right at the
7602 * begining of its sampling period and right at the end of the
7603 * sampling interval. Let's assume the GPU has the longest clock
7604 * period and that the application is sampling GPU and monotonic:
7607 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
7608 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
7612 * GPU -----_____-----_____-----_____-----_____
7615 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
7616 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
7618 * Interval <----------------->
7619 * Deviation <-------------------------->
7623 * m = read(monotonic) 2
7626 * We round the sample interval up by one tick to cover sampling error
7627 * in the interval clock
7630 uint64_t sample_interval
= end
- begin
+ 1;
7632 *pMaxDeviation
= sample_interval
+ max_clock_period
;
7637 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
7638 VkPhysicalDevice physicalDevice
,
7639 VkSampleCountFlagBits samples
,
7640 VkMultisamplePropertiesEXT
* pMultisampleProperties
)
7642 if (samples
& (VK_SAMPLE_COUNT_2_BIT
|
7643 VK_SAMPLE_COUNT_4_BIT
|
7644 VK_SAMPLE_COUNT_8_BIT
)) {
7645 pMultisampleProperties
->maxSampleLocationGridSize
= (VkExtent2D
){ 2, 2 };
7647 pMultisampleProperties
->maxSampleLocationGridSize
= (VkExtent2D
){ 0, 0 };