0f40db2cceb468ae16012a2904401e49e42b4b4a
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "dirent.h"
29 #include <errno.h>
30 #include <fcntl.h>
31 #include <linux/audit.h>
32 #include <linux/bpf.h>
33 #include <linux/filter.h>
34 #include <linux/seccomp.h>
35 #include <linux/unistd.h>
36 #include <stdatomic.h>
37 #include <stdbool.h>
38 #include <stddef.h>
39 #include <stdio.h>
40 #include <string.h>
41 #include <sys/prctl.h>
42 #include <sys/wait.h>
43 #include <unistd.h>
44 #include <fcntl.h>
45
46 #include "radv_debug.h"
47 #include "radv_private.h"
48 #include "radv_shader.h"
49 #include "radv_cs.h"
50 #include "util/disk_cache.h"
51 #include "vk_util.h"
52 #include <xf86drm.h>
53 #include <amdgpu.h>
54 #include "drm-uapi/amdgpu_drm.h"
55 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
56 #include "winsys/null/radv_null_winsys_public.h"
57 #include "ac_llvm_util.h"
58 #include "vk_format.h"
59 #include "sid.h"
60 #include "git_sha1.h"
61 #include "util/build_id.h"
62 #include "util/debug.h"
63 #include "util/mesa-sha1.h"
64 #include "util/timespec.h"
65 #include "util/u_atomic.h"
66 #include "compiler/glsl_types.h"
67 #include "util/driconf.h"
68
69 static struct radv_timeline_point *
70 radv_timeline_find_point_at_least_locked(struct radv_device *device,
71 struct radv_timeline *timeline,
72 uint64_t p);
73
74 static struct radv_timeline_point *
75 radv_timeline_add_point_locked(struct radv_device *device,
76 struct radv_timeline *timeline,
77 uint64_t p);
78
79 static void
80 radv_timeline_trigger_waiters_locked(struct radv_timeline *timeline,
81 struct list_head *processing_list);
82
83 static
84 void radv_destroy_semaphore_part(struct radv_device *device,
85 struct radv_semaphore_part *part);
86
87 static VkResult
88 radv_create_pthread_cond(pthread_cond_t *cond);
89
90 uint64_t radv_get_current_time(void)
91 {
92 struct timespec tv;
93 clock_gettime(CLOCK_MONOTONIC, &tv);
94 return tv.tv_nsec + tv.tv_sec*1000000000ull;
95 }
96
97 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
98 {
99 uint64_t current_time = radv_get_current_time();
100
101 timeout = MIN2(UINT64_MAX - current_time, timeout);
102
103 return current_time + timeout;
104 }
105
106 static int
107 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
108 {
109 struct mesa_sha1 ctx;
110 unsigned char sha1[20];
111 unsigned ptr_size = sizeof(void*);
112
113 memset(uuid, 0, VK_UUID_SIZE);
114 _mesa_sha1_init(&ctx);
115
116 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
117 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
118 return -1;
119
120 _mesa_sha1_update(&ctx, &family, sizeof(family));
121 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
122 _mesa_sha1_final(&ctx, sha1);
123
124 memcpy(uuid, sha1, VK_UUID_SIZE);
125 return 0;
126 }
127
128 static void
129 radv_get_driver_uuid(void *uuid)
130 {
131 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
132 }
133
134 static void
135 radv_get_device_uuid(struct radeon_info *info, void *uuid)
136 {
137 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
138 }
139
140 static uint64_t
141 radv_get_visible_vram_size(struct radv_physical_device *device)
142 {
143 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
144 }
145
146 static uint64_t
147 radv_get_vram_size(struct radv_physical_device *device)
148 {
149 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
150 }
151
152 static void
153 radv_physical_device_init_mem_types(struct radv_physical_device *device)
154 {
155 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
156 uint64_t vram_size = radv_get_vram_size(device);
157 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
158 device->memory_properties.memoryHeapCount = 0;
159 if (vram_size > 0) {
160 vram_index = device->memory_properties.memoryHeapCount++;
161 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
162 .size = vram_size,
163 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
164 };
165 }
166
167 if (device->rad_info.gart_size > 0) {
168 gart_index = device->memory_properties.memoryHeapCount++;
169 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
170 .size = device->rad_info.gart_size,
171 .flags = 0,
172 };
173 }
174
175 if (visible_vram_size) {
176 visible_vram_index = device->memory_properties.memoryHeapCount++;
177 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
178 .size = visible_vram_size,
179 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
180 };
181 }
182
183 unsigned type_count = 0;
184
185 if (vram_index >= 0 || visible_vram_index >= 0) {
186 device->memory_domains[type_count] = RADEON_DOMAIN_VRAM;
187 device->memory_flags[type_count] = RADEON_FLAG_NO_CPU_ACCESS;
188 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
189 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
190 .heapIndex = vram_index >= 0 ? vram_index : visible_vram_index,
191 };
192 }
193
194 if (gart_index >= 0) {
195 device->memory_domains[type_count] = RADEON_DOMAIN_GTT;
196 device->memory_flags[type_count] = RADEON_FLAG_GTT_WC | RADEON_FLAG_CPU_ACCESS;
197 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
198 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
199 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
200 .heapIndex = gart_index,
201 };
202 }
203 if (visible_vram_index >= 0) {
204 device->memory_domains[type_count] = RADEON_DOMAIN_VRAM;
205 device->memory_flags[type_count] = RADEON_FLAG_CPU_ACCESS;
206 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
207 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
208 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
209 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
210 .heapIndex = visible_vram_index,
211 };
212 }
213
214 if (gart_index >= 0) {
215 device->memory_domains[type_count] = RADEON_DOMAIN_GTT;
216 device->memory_flags[type_count] = RADEON_FLAG_CPU_ACCESS;
217 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
218 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
219 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
220 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
221 .heapIndex = gart_index,
222 };
223 }
224 device->memory_properties.memoryTypeCount = type_count;
225
226 if (device->rad_info.has_l2_uncached) {
227 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
228 VkMemoryType mem_type = device->memory_properties.memoryTypes[i];
229
230 if ((mem_type.propertyFlags & (VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
231 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT)) ||
232 mem_type.propertyFlags == VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT) {
233
234 VkMemoryPropertyFlags property_flags = mem_type.propertyFlags |
235 VK_MEMORY_PROPERTY_DEVICE_COHERENT_BIT_AMD |
236 VK_MEMORY_PROPERTY_DEVICE_UNCACHED_BIT_AMD;
237
238 device->memory_domains[type_count] = device->memory_domains[i];
239 device->memory_flags[type_count] = device->memory_flags[i] | RADEON_FLAG_VA_UNCACHED;
240 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
241 .propertyFlags = property_flags,
242 .heapIndex = mem_type.heapIndex,
243 };
244 }
245 }
246 device->memory_properties.memoryTypeCount = type_count;
247 }
248 }
249
250 static const char *
251 radv_get_compiler_string(struct radv_physical_device *pdevice)
252 {
253 if (!pdevice->use_llvm) {
254 /* Some games like SotTR apply shader workarounds if the LLVM
255 * version is too old or if the LLVM version string is
256 * missing. This gives 2-5% performance with SotTR and ACO.
257 */
258 if (driQueryOptionb(&pdevice->instance->dri_options,
259 "radv_report_llvm9_version_string")) {
260 return "ACO/LLVM 9.0.1";
261 }
262
263 return "ACO";
264 }
265
266 return "LLVM " MESA_LLVM_VERSION_STRING;
267 }
268
269 static VkResult
270 radv_physical_device_try_create(struct radv_instance *instance,
271 drmDevicePtr drm_device,
272 struct radv_physical_device **device_out)
273 {
274 VkResult result;
275 int fd = -1;
276 int master_fd = -1;
277
278 if (drm_device) {
279 const char *path = drm_device->nodes[DRM_NODE_RENDER];
280 drmVersionPtr version;
281
282 fd = open(path, O_RDWR | O_CLOEXEC);
283 if (fd < 0) {
284 if (instance->debug_flags & RADV_DEBUG_STARTUP)
285 radv_logi("Could not open device '%s'", path);
286
287 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
288 }
289
290 version = drmGetVersion(fd);
291 if (!version) {
292 close(fd);
293
294 if (instance->debug_flags & RADV_DEBUG_STARTUP)
295 radv_logi("Could not get the kernel driver version for device '%s'", path);
296
297 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
298 "failed to get version %s: %m", path);
299 }
300
301 if (strcmp(version->name, "amdgpu")) {
302 drmFreeVersion(version);
303 close(fd);
304
305 if (instance->debug_flags & RADV_DEBUG_STARTUP)
306 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
307
308 return VK_ERROR_INCOMPATIBLE_DRIVER;
309 }
310 drmFreeVersion(version);
311
312 if (instance->debug_flags & RADV_DEBUG_STARTUP)
313 radv_logi("Found compatible device '%s'.", path);
314 }
315
316 struct radv_physical_device *device =
317 vk_zalloc2(&instance->alloc, NULL, sizeof(*device), 8,
318 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
319 if (!device) {
320 result = vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
321 goto fail_fd;
322 }
323
324 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
325 device->instance = instance;
326
327 if (drm_device) {
328 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
329 instance->perftest_flags);
330 } else {
331 device->ws = radv_null_winsys_create();
332 }
333
334 if (!device->ws) {
335 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
336 "failed to initialize winsys");
337 goto fail_alloc;
338 }
339
340 if (drm_device && instance->enabled_extensions.KHR_display) {
341 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
342 if (master_fd >= 0) {
343 uint32_t accel_working = 0;
344 struct drm_amdgpu_info request = {
345 .return_pointer = (uintptr_t)&accel_working,
346 .return_size = sizeof(accel_working),
347 .query = AMDGPU_INFO_ACCEL_WORKING
348 };
349
350 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
351 close(master_fd);
352 master_fd = -1;
353 }
354 }
355 }
356
357 device->master_fd = master_fd;
358 device->local_fd = fd;
359 device->ws->query_info(device->ws, &device->rad_info);
360
361 device->use_llvm = instance->debug_flags & RADV_DEBUG_LLVM;
362
363 snprintf(device->name, sizeof(device->name),
364 "AMD RADV %s (%s)",
365 device->rad_info.name, radv_get_compiler_string(device));
366
367 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
368 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
369 "cannot generate UUID");
370 goto fail_wsi;
371 }
372
373 /* These flags affect shader compilation. */
374 uint64_t shader_env_flags = (device->use_llvm ? 0 : 0x2);
375
376 /* The gpu id is already embedded in the uuid so we just pass "radv"
377 * when creating the cache.
378 */
379 char buf[VK_UUID_SIZE * 2 + 1];
380 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
381 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
382
383 if (device->rad_info.chip_class < GFX8 || !device->use_llvm)
384 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
385
386 radv_get_driver_uuid(&device->driver_uuid);
387 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
388
389 device->out_of_order_rast_allowed = device->rad_info.has_out_of_order_rast &&
390 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
391
392 device->dcc_msaa_allowed =
393 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
394
395 device->use_ngg = device->rad_info.chip_class >= GFX10 &&
396 device->rad_info.family != CHIP_NAVI14 &&
397 !(device->instance->debug_flags & RADV_DEBUG_NO_NGG);
398
399 /* TODO: Implement NGG GS with ACO. */
400 device->use_ngg_gs = device->use_ngg && device->use_llvm;
401 device->use_ngg_streamout = false;
402
403 /* Determine the number of threads per wave for all stages. */
404 device->cs_wave_size = 64;
405 device->ps_wave_size = 64;
406 device->ge_wave_size = 64;
407
408 if (device->rad_info.chip_class >= GFX10) {
409 if (device->instance->perftest_flags & RADV_PERFTEST_CS_WAVE_32)
410 device->cs_wave_size = 32;
411
412 /* For pixel shaders, wave64 is recommanded. */
413 if (device->instance->perftest_flags & RADV_PERFTEST_PS_WAVE_32)
414 device->ps_wave_size = 32;
415
416 if (device->instance->perftest_flags & RADV_PERFTEST_GE_WAVE_32)
417 device->ge_wave_size = 32;
418 }
419
420 radv_physical_device_init_mem_types(device);
421
422 radv_physical_device_get_supported_extensions(device,
423 &device->supported_extensions);
424
425 if (drm_device)
426 device->bus_info = *drm_device->businfo.pci;
427
428 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
429 ac_print_gpu_info(&device->rad_info);
430
431 /* The WSI is structured as a layer on top of the driver, so this has
432 * to be the last part of initialization (at least until we get other
433 * semi-layers).
434 */
435 result = radv_init_wsi(device);
436 if (result != VK_SUCCESS) {
437 vk_error(instance, result);
438 goto fail_disk_cache;
439 }
440
441 *device_out = device;
442
443 return VK_SUCCESS;
444
445 fail_disk_cache:
446 disk_cache_destroy(device->disk_cache);
447 fail_wsi:
448 device->ws->destroy(device->ws);
449 fail_alloc:
450 vk_free(&instance->alloc, device);
451 fail_fd:
452 if (fd != -1)
453 close(fd);
454 if (master_fd != -1)
455 close(master_fd);
456 return result;
457 }
458
459 static void
460 radv_physical_device_destroy(struct radv_physical_device *device)
461 {
462 radv_finish_wsi(device);
463 device->ws->destroy(device->ws);
464 disk_cache_destroy(device->disk_cache);
465 close(device->local_fd);
466 if (device->master_fd != -1)
467 close(device->master_fd);
468 vk_free(&device->instance->alloc, device);
469 }
470
471 static void *
472 default_alloc_func(void *pUserData, size_t size, size_t align,
473 VkSystemAllocationScope allocationScope)
474 {
475 return malloc(size);
476 }
477
478 static void *
479 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
480 size_t align, VkSystemAllocationScope allocationScope)
481 {
482 return realloc(pOriginal, size);
483 }
484
485 static void
486 default_free_func(void *pUserData, void *pMemory)
487 {
488 free(pMemory);
489 }
490
491 static const VkAllocationCallbacks default_alloc = {
492 .pUserData = NULL,
493 .pfnAllocation = default_alloc_func,
494 .pfnReallocation = default_realloc_func,
495 .pfnFree = default_free_func,
496 };
497
498 static const struct debug_control radv_debug_options[] = {
499 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
500 {"nodcc", RADV_DEBUG_NO_DCC},
501 {"shaders", RADV_DEBUG_DUMP_SHADERS},
502 {"nocache", RADV_DEBUG_NO_CACHE},
503 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
504 {"nohiz", RADV_DEBUG_NO_HIZ},
505 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
506 {"allbos", RADV_DEBUG_ALL_BOS},
507 {"noibs", RADV_DEBUG_NO_IBS},
508 {"spirv", RADV_DEBUG_DUMP_SPIRV},
509 {"vmfaults", RADV_DEBUG_VM_FAULTS},
510 {"zerovram", RADV_DEBUG_ZERO_VRAM},
511 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
512 {"preoptir", RADV_DEBUG_PREOPTIR},
513 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
514 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
515 {"info", RADV_DEBUG_INFO},
516 {"errors", RADV_DEBUG_ERRORS},
517 {"startup", RADV_DEBUG_STARTUP},
518 {"checkir", RADV_DEBUG_CHECKIR},
519 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
520 {"nobinning", RADV_DEBUG_NOBINNING},
521 {"nongg", RADV_DEBUG_NO_NGG},
522 {"allentrypoints", RADV_DEBUG_ALL_ENTRYPOINTS},
523 {"metashaders", RADV_DEBUG_DUMP_META_SHADERS},
524 {"nomemorycache", RADV_DEBUG_NO_MEMORY_CACHE},
525 {"llvm", RADV_DEBUG_LLVM},
526 {"forcecompress", RADV_DEBUG_FORCE_COMPRESS},
527 {NULL, 0}
528 };
529
530 const char *
531 radv_get_debug_option_name(int id)
532 {
533 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
534 return radv_debug_options[id].string;
535 }
536
537 static const struct debug_control radv_perftest_options[] = {
538 {"localbos", RADV_PERFTEST_LOCAL_BOS},
539 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
540 {"bolist", RADV_PERFTEST_BO_LIST},
541 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
542 {"cswave32", RADV_PERFTEST_CS_WAVE_32},
543 {"pswave32", RADV_PERFTEST_PS_WAVE_32},
544 {"gewave32", RADV_PERFTEST_GE_WAVE_32},
545 {"dfsm", RADV_PERFTEST_DFSM},
546 {NULL, 0}
547 };
548
549 const char *
550 radv_get_perftest_option_name(int id)
551 {
552 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
553 return radv_perftest_options[id].string;
554 }
555
556 static void
557 radv_handle_per_app_options(struct radv_instance *instance,
558 const VkApplicationInfo *info)
559 {
560 const char *name = info ? info->pApplicationName : NULL;
561 const char *engine_name = info ? info->pEngineName : NULL;
562
563 if (name) {
564 if (!strcmp(name, "DOOM_VFR")) {
565 /* Work around a Doom VFR game bug */
566 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
567 } else if (!strcmp(name, "Fledge")) {
568 /*
569 * Zero VRAM for "The Surge 2"
570 *
571 * This avoid a hang when when rendering any level. Likely
572 * uninitialized data in an indirect draw.
573 */
574 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
575 } else if (!strcmp(name, "No Man's Sky")) {
576 /* Work around a NMS game bug */
577 instance->debug_flags |= RADV_DEBUG_DISCARD_TO_DEMOTE;
578 } else if (!strcmp(name, "DOOMEternal")) {
579 /* Zero VRAM for Doom Eternal to fix rendering issues. */
580 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
581 } else if (!strcmp(name, "Red Dead Redemption 2")) {
582 /* Work around a RDR2 game bug */
583 instance->debug_flags |= RADV_DEBUG_DISCARD_TO_DEMOTE;
584 }
585 }
586
587 if (engine_name) {
588 if (!strcmp(engine_name, "vkd3d")) {
589 /* Zero VRAM for all VKD3D (DX12->VK) games to fix
590 * rendering issues.
591 */
592 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
593 } else if (!strcmp(engine_name, "Quantic Dream Engine")) {
594 /* Fix various artifacts in Detroit: Become Human */
595 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM |
596 RADV_DEBUG_DISCARD_TO_DEMOTE;
597 }
598 }
599
600 instance->enable_mrt_output_nan_fixup =
601 driQueryOptionb(&instance->dri_options,
602 "radv_enable_mrt_output_nan_fixup");
603
604 if (driQueryOptionb(&instance->dri_options, "radv_no_dynamic_bounds"))
605 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
606 }
607
608 static const char radv_dri_options_xml[] =
609 DRI_CONF_BEGIN
610 DRI_CONF_SECTION_PERFORMANCE
611 DRI_CONF_ADAPTIVE_SYNC("true")
612 DRI_CONF_VK_X11_OVERRIDE_MIN_IMAGE_COUNT(0)
613 DRI_CONF_VK_X11_STRICT_IMAGE_COUNT("false")
614 DRI_CONF_VK_X11_ENSURE_MIN_IMAGE_COUNT("false")
615 DRI_CONF_RADV_REPORT_LLVM9_VERSION_STRING("false")
616 DRI_CONF_RADV_ENABLE_MRT_OUTPUT_NAN_FIXUP("false")
617 DRI_CONF_RADV_NO_DYNAMIC_BOUNDS("false")
618 DRI_CONF_SECTION_END
619
620 DRI_CONF_SECTION_DEBUG
621 DRI_CONF_VK_WSI_FORCE_BGRA8_UNORM_FIRST("false")
622 DRI_CONF_SECTION_END
623 DRI_CONF_END;
624
625 static void radv_init_dri_options(struct radv_instance *instance)
626 {
627 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
628 driParseConfigFiles(&instance->dri_options,
629 &instance->available_dri_options,
630 0, "radv", NULL,
631 instance->applicationName,
632 instance->applicationVersion,
633 instance->engineName,
634 instance->engineVersion);
635 }
636
637 VkResult radv_CreateInstance(
638 const VkInstanceCreateInfo* pCreateInfo,
639 const VkAllocationCallbacks* pAllocator,
640 VkInstance* pInstance)
641 {
642 struct radv_instance *instance;
643 VkResult result;
644
645 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
646 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
647 if (!instance)
648 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
649
650 vk_object_base_init(NULL, &instance->base, VK_OBJECT_TYPE_INSTANCE);
651
652 if (pAllocator)
653 instance->alloc = *pAllocator;
654 else
655 instance->alloc = default_alloc;
656
657 if (pCreateInfo->pApplicationInfo) {
658 const VkApplicationInfo *app = pCreateInfo->pApplicationInfo;
659
660 instance->applicationName =
661 vk_strdup(&instance->alloc, app->pApplicationName,
662 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
663 instance->applicationVersion = app->applicationVersion;
664
665 instance->engineName =
666 vk_strdup(&instance->alloc, app->pEngineName,
667 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
668 instance->engineVersion = app->engineVersion;
669 instance->apiVersion = app->apiVersion;
670 }
671
672 if (instance->apiVersion == 0)
673 instance->apiVersion = VK_API_VERSION_1_0;
674
675 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
676 radv_debug_options);
677
678 const char *radv_perftest_str = getenv("RADV_PERFTEST");
679 instance->perftest_flags = parse_debug_string(radv_perftest_str,
680 radv_perftest_options);
681
682 if (radv_perftest_str) {
683 /* Output warnings for famous RADV_PERFTEST options that no
684 * longer exist or are deprecated.
685 */
686 if (strstr(radv_perftest_str, "aco")) {
687 fprintf(stderr, "*******************************************************************************\n");
688 fprintf(stderr, "* WARNING: Unknown option RADV_PERFTEST='aco'. ACO is enabled by default now. *\n");
689 fprintf(stderr, "*******************************************************************************\n");
690 }
691 if (strstr(radv_perftest_str, "llvm")) {
692 fprintf(stderr, "*********************************************************************************\n");
693 fprintf(stderr, "* WARNING: Unknown option 'RADV_PERFTEST=llvm'. Did you mean 'RADV_DEBUG=llvm'? *\n");
694 fprintf(stderr, "*********************************************************************************\n");
695 abort();
696 }
697 }
698
699 if (instance->debug_flags & RADV_DEBUG_STARTUP)
700 radv_logi("Created an instance");
701
702 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
703 int idx;
704 for (idx = 0; idx < RADV_INSTANCE_EXTENSION_COUNT; idx++) {
705 if (!strcmp(pCreateInfo->ppEnabledExtensionNames[i],
706 radv_instance_extensions[idx].extensionName))
707 break;
708 }
709
710 if (idx >= RADV_INSTANCE_EXTENSION_COUNT ||
711 !radv_instance_extensions_supported.extensions[idx]) {
712 vk_object_base_finish(&instance->base);
713 vk_free2(&default_alloc, pAllocator, instance);
714 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
715 }
716
717 instance->enabled_extensions.extensions[idx] = true;
718 }
719
720 bool unchecked = instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS;
721
722 for (unsigned i = 0; i < ARRAY_SIZE(instance->dispatch.entrypoints); i++) {
723 /* Vulkan requires that entrypoints for extensions which have
724 * not been enabled must not be advertised.
725 */
726 if (!unchecked &&
727 !radv_instance_entrypoint_is_enabled(i, instance->apiVersion,
728 &instance->enabled_extensions)) {
729 instance->dispatch.entrypoints[i] = NULL;
730 } else {
731 instance->dispatch.entrypoints[i] =
732 radv_instance_dispatch_table.entrypoints[i];
733 }
734 }
735
736 for (unsigned i = 0; i < ARRAY_SIZE(instance->physical_device_dispatch.entrypoints); i++) {
737 /* Vulkan requires that entrypoints for extensions which have
738 * not been enabled must not be advertised.
739 */
740 if (!unchecked &&
741 !radv_physical_device_entrypoint_is_enabled(i, instance->apiVersion,
742 &instance->enabled_extensions)) {
743 instance->physical_device_dispatch.entrypoints[i] = NULL;
744 } else {
745 instance->physical_device_dispatch.entrypoints[i] =
746 radv_physical_device_dispatch_table.entrypoints[i];
747 }
748 }
749
750 for (unsigned i = 0; i < ARRAY_SIZE(instance->device_dispatch.entrypoints); i++) {
751 /* Vulkan requires that entrypoints for extensions which have
752 * not been enabled must not be advertised.
753 */
754 if (!unchecked &&
755 !radv_device_entrypoint_is_enabled(i, instance->apiVersion,
756 &instance->enabled_extensions, NULL)) {
757 instance->device_dispatch.entrypoints[i] = NULL;
758 } else {
759 instance->device_dispatch.entrypoints[i] =
760 radv_device_dispatch_table.entrypoints[i];
761 }
762 }
763
764 instance->physical_devices_enumerated = false;
765 list_inithead(&instance->physical_devices);
766
767 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
768 if (result != VK_SUCCESS) {
769 vk_object_base_finish(&instance->base);
770 vk_free2(&default_alloc, pAllocator, instance);
771 return vk_error(instance, result);
772 }
773
774 glsl_type_singleton_init_or_ref();
775
776 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
777
778 radv_init_dri_options(instance);
779 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
780
781 *pInstance = radv_instance_to_handle(instance);
782
783 return VK_SUCCESS;
784 }
785
786 void radv_DestroyInstance(
787 VkInstance _instance,
788 const VkAllocationCallbacks* pAllocator)
789 {
790 RADV_FROM_HANDLE(radv_instance, instance, _instance);
791
792 if (!instance)
793 return;
794
795 list_for_each_entry_safe(struct radv_physical_device, pdevice,
796 &instance->physical_devices, link) {
797 radv_physical_device_destroy(pdevice);
798 }
799
800 vk_free(&instance->alloc, instance->engineName);
801 vk_free(&instance->alloc, instance->applicationName);
802
803 VG(VALGRIND_DESTROY_MEMPOOL(instance));
804
805 glsl_type_singleton_decref();
806
807 driDestroyOptionCache(&instance->dri_options);
808 driDestroyOptionInfo(&instance->available_dri_options);
809
810 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
811
812 vk_object_base_finish(&instance->base);
813 vk_free(&instance->alloc, instance);
814 }
815
816 static VkResult
817 radv_enumerate_physical_devices(struct radv_instance *instance)
818 {
819 if (instance->physical_devices_enumerated)
820 return VK_SUCCESS;
821
822 instance->physical_devices_enumerated = true;
823
824 /* TODO: Check for more devices ? */
825 drmDevicePtr devices[8];
826 VkResult result = VK_SUCCESS;
827 int max_devices;
828
829 if (getenv("RADV_FORCE_FAMILY")) {
830 /* When RADV_FORCE_FAMILY is set, the driver creates a nul
831 * device that allows to test the compiler without having an
832 * AMDGPU instance.
833 */
834 struct radv_physical_device *pdevice;
835
836 result = radv_physical_device_try_create(instance, NULL, &pdevice);
837 if (result != VK_SUCCESS)
838 return result;
839
840 list_addtail(&pdevice->link, &instance->physical_devices);
841 return VK_SUCCESS;
842 }
843
844 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
845
846 if (instance->debug_flags & RADV_DEBUG_STARTUP)
847 radv_logi("Found %d drm nodes", max_devices);
848
849 if (max_devices < 1)
850 return vk_error(instance, VK_SUCCESS);
851
852 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
853 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
854 devices[i]->bustype == DRM_BUS_PCI &&
855 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
856
857 struct radv_physical_device *pdevice;
858 result = radv_physical_device_try_create(instance, devices[i],
859 &pdevice);
860 /* Incompatible DRM device, skip. */
861 if (result == VK_ERROR_INCOMPATIBLE_DRIVER) {
862 result = VK_SUCCESS;
863 continue;
864 }
865
866 /* Error creating the physical device, report the error. */
867 if (result != VK_SUCCESS)
868 break;
869
870 list_addtail(&pdevice->link, &instance->physical_devices);
871 }
872 }
873 drmFreeDevices(devices, max_devices);
874
875 /* If we successfully enumerated any devices, call it success */
876 return result;
877 }
878
879 VkResult radv_EnumeratePhysicalDevices(
880 VkInstance _instance,
881 uint32_t* pPhysicalDeviceCount,
882 VkPhysicalDevice* pPhysicalDevices)
883 {
884 RADV_FROM_HANDLE(radv_instance, instance, _instance);
885 VK_OUTARRAY_MAKE(out, pPhysicalDevices, pPhysicalDeviceCount);
886
887 VkResult result = radv_enumerate_physical_devices(instance);
888 if (result != VK_SUCCESS)
889 return result;
890
891 list_for_each_entry(struct radv_physical_device, pdevice,
892 &instance->physical_devices, link) {
893 vk_outarray_append(&out, i) {
894 *i = radv_physical_device_to_handle(pdevice);
895 }
896 }
897
898 return vk_outarray_status(&out);
899 }
900
901 VkResult radv_EnumeratePhysicalDeviceGroups(
902 VkInstance _instance,
903 uint32_t* pPhysicalDeviceGroupCount,
904 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
905 {
906 RADV_FROM_HANDLE(radv_instance, instance, _instance);
907 VK_OUTARRAY_MAKE(out, pPhysicalDeviceGroupProperties,
908 pPhysicalDeviceGroupCount);
909
910 VkResult result = radv_enumerate_physical_devices(instance);
911 if (result != VK_SUCCESS)
912 return result;
913
914 list_for_each_entry(struct radv_physical_device, pdevice,
915 &instance->physical_devices, link) {
916 vk_outarray_append(&out, p) {
917 p->physicalDeviceCount = 1;
918 memset(p->physicalDevices, 0, sizeof(p->physicalDevices));
919 p->physicalDevices[0] = radv_physical_device_to_handle(pdevice);
920 p->subsetAllocation = false;
921 }
922 }
923
924 return vk_outarray_status(&out);
925 }
926
927 void radv_GetPhysicalDeviceFeatures(
928 VkPhysicalDevice physicalDevice,
929 VkPhysicalDeviceFeatures* pFeatures)
930 {
931 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
932 memset(pFeatures, 0, sizeof(*pFeatures));
933
934 *pFeatures = (VkPhysicalDeviceFeatures) {
935 .robustBufferAccess = true,
936 .fullDrawIndexUint32 = true,
937 .imageCubeArray = true,
938 .independentBlend = true,
939 .geometryShader = true,
940 .tessellationShader = true,
941 .sampleRateShading = true,
942 .dualSrcBlend = true,
943 .logicOp = true,
944 .multiDrawIndirect = true,
945 .drawIndirectFirstInstance = true,
946 .depthClamp = true,
947 .depthBiasClamp = true,
948 .fillModeNonSolid = true,
949 .depthBounds = true,
950 .wideLines = true,
951 .largePoints = true,
952 .alphaToOne = true,
953 .multiViewport = true,
954 .samplerAnisotropy = true,
955 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
956 .textureCompressionASTC_LDR = false,
957 .textureCompressionBC = true,
958 .occlusionQueryPrecise = true,
959 .pipelineStatisticsQuery = true,
960 .vertexPipelineStoresAndAtomics = true,
961 .fragmentStoresAndAtomics = true,
962 .shaderTessellationAndGeometryPointSize = true,
963 .shaderImageGatherExtended = true,
964 .shaderStorageImageExtendedFormats = true,
965 .shaderStorageImageMultisample = true,
966 .shaderUniformBufferArrayDynamicIndexing = true,
967 .shaderSampledImageArrayDynamicIndexing = true,
968 .shaderStorageBufferArrayDynamicIndexing = true,
969 .shaderStorageImageArrayDynamicIndexing = true,
970 .shaderStorageImageReadWithoutFormat = true,
971 .shaderStorageImageWriteWithoutFormat = true,
972 .shaderClipDistance = true,
973 .shaderCullDistance = true,
974 .shaderFloat64 = true,
975 .shaderInt64 = true,
976 .shaderInt16 = true,
977 .sparseBinding = true,
978 .variableMultisampleRate = true,
979 .shaderResourceMinLod = true,
980 .inheritedQueries = true,
981 };
982 }
983
984 static void
985 radv_get_physical_device_features_1_1(struct radv_physical_device *pdevice,
986 VkPhysicalDeviceVulkan11Features *f)
987 {
988 assert(f->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES);
989
990 f->storageBuffer16BitAccess = true;
991 f->uniformAndStorageBuffer16BitAccess = true;
992 f->storagePushConstant16 = true;
993 f->storageInputOutput16 = pdevice->rad_info.has_packed_math_16bit && (LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm);
994 f->multiview = true;
995 f->multiviewGeometryShader = true;
996 f->multiviewTessellationShader = true;
997 f->variablePointersStorageBuffer = true;
998 f->variablePointers = true;
999 f->protectedMemory = false;
1000 f->samplerYcbcrConversion = true;
1001 f->shaderDrawParameters = true;
1002 }
1003
1004 static void
1005 radv_get_physical_device_features_1_2(struct radv_physical_device *pdevice,
1006 VkPhysicalDeviceVulkan12Features *f)
1007 {
1008 assert(f->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES);
1009
1010 f->samplerMirrorClampToEdge = true;
1011 f->drawIndirectCount = true;
1012 f->storageBuffer8BitAccess = true;
1013 f->uniformAndStorageBuffer8BitAccess = true;
1014 f->storagePushConstant8 = true;
1015 f->shaderBufferInt64Atomics = LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm;
1016 f->shaderSharedInt64Atomics = LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm;
1017 f->shaderFloat16 = pdevice->rad_info.has_packed_math_16bit;
1018 f->shaderInt8 = true;
1019
1020 f->descriptorIndexing = true;
1021 f->shaderInputAttachmentArrayDynamicIndexing = true;
1022 f->shaderUniformTexelBufferArrayDynamicIndexing = true;
1023 f->shaderStorageTexelBufferArrayDynamicIndexing = true;
1024 f->shaderUniformBufferArrayNonUniformIndexing = true;
1025 f->shaderSampledImageArrayNonUniformIndexing = true;
1026 f->shaderStorageBufferArrayNonUniformIndexing = true;
1027 f->shaderStorageImageArrayNonUniformIndexing = true;
1028 f->shaderInputAttachmentArrayNonUniformIndexing = true;
1029 f->shaderUniformTexelBufferArrayNonUniformIndexing = true;
1030 f->shaderStorageTexelBufferArrayNonUniformIndexing = true;
1031 f->descriptorBindingUniformBufferUpdateAfterBind = true;
1032 f->descriptorBindingSampledImageUpdateAfterBind = true;
1033 f->descriptorBindingStorageImageUpdateAfterBind = true;
1034 f->descriptorBindingStorageBufferUpdateAfterBind = true;
1035 f->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
1036 f->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
1037 f->descriptorBindingUpdateUnusedWhilePending = true;
1038 f->descriptorBindingPartiallyBound = true;
1039 f->descriptorBindingVariableDescriptorCount = true;
1040 f->runtimeDescriptorArray = true;
1041
1042 f->samplerFilterMinmax = true;
1043 f->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
1044 f->imagelessFramebuffer = true;
1045 f->uniformBufferStandardLayout = true;
1046 f->shaderSubgroupExtendedTypes = true;
1047 f->separateDepthStencilLayouts = true;
1048 f->hostQueryReset = true;
1049 f->timelineSemaphore = pdevice->rad_info.has_syncobj_wait_for_submit;
1050 f->bufferDeviceAddress = true;
1051 f->bufferDeviceAddressCaptureReplay = false;
1052 f->bufferDeviceAddressMultiDevice = false;
1053 f->vulkanMemoryModel = true;
1054 f->vulkanMemoryModelDeviceScope = true;
1055 f->vulkanMemoryModelAvailabilityVisibilityChains = false;
1056 f->shaderOutputViewportIndex = true;
1057 f->shaderOutputLayer = true;
1058 f->subgroupBroadcastDynamicId = true;
1059 }
1060
1061 void radv_GetPhysicalDeviceFeatures2(
1062 VkPhysicalDevice physicalDevice,
1063 VkPhysicalDeviceFeatures2 *pFeatures)
1064 {
1065 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1066 radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
1067
1068 VkPhysicalDeviceVulkan11Features core_1_1 = {
1069 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES,
1070 };
1071 radv_get_physical_device_features_1_1(pdevice, &core_1_1);
1072
1073 VkPhysicalDeviceVulkan12Features core_1_2 = {
1074 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES,
1075 };
1076 radv_get_physical_device_features_1_2(pdevice, &core_1_2);
1077
1078 #define CORE_FEATURE(major, minor, feature) \
1079 features->feature = core_##major##_##minor.feature
1080
1081 vk_foreach_struct(ext, pFeatures->pNext) {
1082 switch (ext->sType) {
1083 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
1084 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
1085 CORE_FEATURE(1, 1, variablePointersStorageBuffer);
1086 CORE_FEATURE(1, 1, variablePointers);
1087 break;
1088 }
1089 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
1090 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
1091 CORE_FEATURE(1, 1, multiview);
1092 CORE_FEATURE(1, 1, multiviewGeometryShader);
1093 CORE_FEATURE(1, 1, multiviewTessellationShader);
1094 break;
1095 }
1096 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
1097 VkPhysicalDeviceShaderDrawParametersFeatures *features =
1098 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
1099 CORE_FEATURE(1, 1, shaderDrawParameters);
1100 break;
1101 }
1102 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
1103 VkPhysicalDeviceProtectedMemoryFeatures *features =
1104 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
1105 CORE_FEATURE(1, 1, protectedMemory);
1106 break;
1107 }
1108 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
1109 VkPhysicalDevice16BitStorageFeatures *features =
1110 (VkPhysicalDevice16BitStorageFeatures*)ext;
1111 CORE_FEATURE(1, 1, storageBuffer16BitAccess);
1112 CORE_FEATURE(1, 1, uniformAndStorageBuffer16BitAccess);
1113 CORE_FEATURE(1, 1, storagePushConstant16);
1114 CORE_FEATURE(1, 1, storageInputOutput16);
1115 break;
1116 }
1117 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
1118 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
1119 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
1120 CORE_FEATURE(1, 1, samplerYcbcrConversion);
1121 break;
1122 }
1123 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES: {
1124 VkPhysicalDeviceDescriptorIndexingFeatures *features =
1125 (VkPhysicalDeviceDescriptorIndexingFeatures*)ext;
1126 CORE_FEATURE(1, 2, shaderInputAttachmentArrayDynamicIndexing);
1127 CORE_FEATURE(1, 2, shaderUniformTexelBufferArrayDynamicIndexing);
1128 CORE_FEATURE(1, 2, shaderStorageTexelBufferArrayDynamicIndexing);
1129 CORE_FEATURE(1, 2, shaderUniformBufferArrayNonUniformIndexing);
1130 CORE_FEATURE(1, 2, shaderSampledImageArrayNonUniformIndexing);
1131 CORE_FEATURE(1, 2, shaderStorageBufferArrayNonUniformIndexing);
1132 CORE_FEATURE(1, 2, shaderStorageImageArrayNonUniformIndexing);
1133 CORE_FEATURE(1, 2, shaderInputAttachmentArrayNonUniformIndexing);
1134 CORE_FEATURE(1, 2, shaderUniformTexelBufferArrayNonUniformIndexing);
1135 CORE_FEATURE(1, 2, shaderStorageTexelBufferArrayNonUniformIndexing);
1136 CORE_FEATURE(1, 2, descriptorBindingUniformBufferUpdateAfterBind);
1137 CORE_FEATURE(1, 2, descriptorBindingSampledImageUpdateAfterBind);
1138 CORE_FEATURE(1, 2, descriptorBindingStorageImageUpdateAfterBind);
1139 CORE_FEATURE(1, 2, descriptorBindingStorageBufferUpdateAfterBind);
1140 CORE_FEATURE(1, 2, descriptorBindingUniformTexelBufferUpdateAfterBind);
1141 CORE_FEATURE(1, 2, descriptorBindingStorageTexelBufferUpdateAfterBind);
1142 CORE_FEATURE(1, 2, descriptorBindingUpdateUnusedWhilePending);
1143 CORE_FEATURE(1, 2, descriptorBindingPartiallyBound);
1144 CORE_FEATURE(1, 2, descriptorBindingVariableDescriptorCount);
1145 CORE_FEATURE(1, 2, runtimeDescriptorArray);
1146 break;
1147 }
1148 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
1149 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
1150 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
1151 features->conditionalRendering = true;
1152 features->inheritedConditionalRendering = false;
1153 break;
1154 }
1155 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
1156 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
1157 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
1158 features->vertexAttributeInstanceRateDivisor = true;
1159 features->vertexAttributeInstanceRateZeroDivisor = true;
1160 break;
1161 }
1162 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
1163 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
1164 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
1165 features->transformFeedback = true;
1166 features->geometryStreams = !pdevice->use_ngg_streamout;
1167 break;
1168 }
1169 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES: {
1170 VkPhysicalDeviceScalarBlockLayoutFeatures *features =
1171 (VkPhysicalDeviceScalarBlockLayoutFeatures *)ext;
1172 CORE_FEATURE(1, 2, scalarBlockLayout);
1173 break;
1174 }
1175 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
1176 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
1177 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
1178 features->memoryPriority = true;
1179 break;
1180 }
1181 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
1182 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
1183 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
1184 features->bufferDeviceAddress = true;
1185 features->bufferDeviceAddressCaptureReplay = false;
1186 features->bufferDeviceAddressMultiDevice = false;
1187 break;
1188 }
1189 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES: {
1190 VkPhysicalDeviceBufferDeviceAddressFeatures *features =
1191 (VkPhysicalDeviceBufferDeviceAddressFeatures *)ext;
1192 CORE_FEATURE(1, 2, bufferDeviceAddress);
1193 CORE_FEATURE(1, 2, bufferDeviceAddressCaptureReplay);
1194 CORE_FEATURE(1, 2, bufferDeviceAddressMultiDevice);
1195 break;
1196 }
1197 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
1198 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
1199 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
1200 features->depthClipEnable = true;
1201 break;
1202 }
1203 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES: {
1204 VkPhysicalDeviceHostQueryResetFeatures *features =
1205 (VkPhysicalDeviceHostQueryResetFeatures *)ext;
1206 CORE_FEATURE(1, 2, hostQueryReset);
1207 break;
1208 }
1209 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES: {
1210 VkPhysicalDevice8BitStorageFeatures *features =
1211 (VkPhysicalDevice8BitStorageFeatures *)ext;
1212 CORE_FEATURE(1, 2, storageBuffer8BitAccess);
1213 CORE_FEATURE(1, 2, uniformAndStorageBuffer8BitAccess);
1214 CORE_FEATURE(1, 2, storagePushConstant8);
1215 break;
1216 }
1217 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_FLOAT16_INT8_FEATURES: {
1218 VkPhysicalDeviceShaderFloat16Int8Features *features =
1219 (VkPhysicalDeviceShaderFloat16Int8Features*)ext;
1220 CORE_FEATURE(1, 2, shaderFloat16);
1221 CORE_FEATURE(1, 2, shaderInt8);
1222 break;
1223 }
1224 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES: {
1225 VkPhysicalDeviceShaderAtomicInt64Features *features =
1226 (VkPhysicalDeviceShaderAtomicInt64Features *)ext;
1227 CORE_FEATURE(1, 2, shaderBufferInt64Atomics);
1228 CORE_FEATURE(1, 2, shaderSharedInt64Atomics);
1229 break;
1230 }
1231 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DEMOTE_TO_HELPER_INVOCATION_FEATURES_EXT: {
1232 VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT *features =
1233 (VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT *)ext;
1234 features->shaderDemoteToHelperInvocation = LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm;
1235 break;
1236 }
1237 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
1238 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
1239 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
1240
1241 features->inlineUniformBlock = true;
1242 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
1243 break;
1244 }
1245 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
1246 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
1247 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
1248 features->computeDerivativeGroupQuads = false;
1249 features->computeDerivativeGroupLinear = true;
1250 break;
1251 }
1252 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
1253 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
1254 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
1255 features->ycbcrImageArrays = true;
1256 break;
1257 }
1258 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES: {
1259 VkPhysicalDeviceUniformBufferStandardLayoutFeatures *features =
1260 (VkPhysicalDeviceUniformBufferStandardLayoutFeatures *)ext;
1261 CORE_FEATURE(1, 2, uniformBufferStandardLayout);
1262 break;
1263 }
1264 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT: {
1265 VkPhysicalDeviceIndexTypeUint8FeaturesEXT *features =
1266 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT *)ext;
1267 features->indexTypeUint8 = pdevice->rad_info.chip_class >= GFX8;
1268 break;
1269 }
1270 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGELESS_FRAMEBUFFER_FEATURES: {
1271 VkPhysicalDeviceImagelessFramebufferFeatures *features =
1272 (VkPhysicalDeviceImagelessFramebufferFeatures *)ext;
1273 CORE_FEATURE(1, 2, imagelessFramebuffer);
1274 break;
1275 }
1276 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR: {
1277 VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *features =
1278 (VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *)ext;
1279 features->pipelineExecutableInfo = true;
1280 break;
1281 }
1282 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CLOCK_FEATURES_KHR: {
1283 VkPhysicalDeviceShaderClockFeaturesKHR *features =
1284 (VkPhysicalDeviceShaderClockFeaturesKHR *)ext;
1285 features->shaderSubgroupClock = true;
1286 features->shaderDeviceClock = pdevice->rad_info.chip_class >= GFX8;
1287 break;
1288 }
1289 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_FEATURES_EXT: {
1290 VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT *features =
1291 (VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT *)ext;
1292 features->texelBufferAlignment = true;
1293 break;
1294 }
1295 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_FEATURES: {
1296 VkPhysicalDeviceTimelineSemaphoreFeatures *features =
1297 (VkPhysicalDeviceTimelineSemaphoreFeatures *) ext;
1298 CORE_FEATURE(1, 2, timelineSemaphore);
1299 break;
1300 }
1301 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_FEATURES_EXT: {
1302 VkPhysicalDeviceSubgroupSizeControlFeaturesEXT *features =
1303 (VkPhysicalDeviceSubgroupSizeControlFeaturesEXT *)ext;
1304 features->subgroupSizeControl = true;
1305 features->computeFullSubgroups = true;
1306 break;
1307 }
1308 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COHERENT_MEMORY_FEATURES_AMD: {
1309 VkPhysicalDeviceCoherentMemoryFeaturesAMD *features =
1310 (VkPhysicalDeviceCoherentMemoryFeaturesAMD *)ext;
1311 features->deviceCoherentMemory = pdevice->rad_info.has_l2_uncached;
1312 break;
1313 }
1314 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_SUBGROUP_EXTENDED_TYPES_FEATURES: {
1315 VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures *features =
1316 (VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures *)ext;
1317 CORE_FEATURE(1, 2, shaderSubgroupExtendedTypes);
1318 break;
1319 }
1320 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SEPARATE_DEPTH_STENCIL_LAYOUTS_FEATURES_KHR: {
1321 VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR *features =
1322 (VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR *)ext;
1323 CORE_FEATURE(1, 2, separateDepthStencilLayouts);
1324 break;
1325 }
1326 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES: {
1327 radv_get_physical_device_features_1_1(pdevice, (void *)ext);
1328 break;
1329 }
1330 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES: {
1331 radv_get_physical_device_features_1_2(pdevice, (void *)ext);
1332 break;
1333 }
1334 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_FEATURES_EXT: {
1335 VkPhysicalDeviceLineRasterizationFeaturesEXT *features =
1336 (VkPhysicalDeviceLineRasterizationFeaturesEXT *)ext;
1337 features->rectangularLines = false;
1338 features->bresenhamLines = true;
1339 features->smoothLines = false;
1340 features->stippledRectangularLines = false;
1341 features->stippledBresenhamLines = true;
1342 features->stippledSmoothLines = false;
1343 break;
1344 }
1345 case VK_STRUCTURE_TYPE_DEVICE_MEMORY_OVERALLOCATION_CREATE_INFO_AMD: {
1346 VkDeviceMemoryOverallocationCreateInfoAMD *features =
1347 (VkDeviceMemoryOverallocationCreateInfoAMD *)ext;
1348 features->overallocationBehavior = true;
1349 break;
1350 }
1351 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ROBUSTNESS_2_FEATURES_EXT: {
1352 VkPhysicalDeviceRobustness2FeaturesEXT *features =
1353 (VkPhysicalDeviceRobustness2FeaturesEXT *)ext;
1354 features->robustBufferAccess2 = true;
1355 features->robustImageAccess2 = true;
1356 features->nullDescriptor = true;
1357 break;
1358 }
1359 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_FEATURES_EXT: {
1360 VkPhysicalDeviceCustomBorderColorFeaturesEXT *features =
1361 (VkPhysicalDeviceCustomBorderColorFeaturesEXT *)ext;
1362 features->customBorderColors = true;
1363 features->customBorderColorWithoutFormat = true;
1364 break;
1365 }
1366 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PRIVATE_DATA_FEATURES_EXT: {
1367 VkPhysicalDevicePrivateDataFeaturesEXT *features =
1368 (VkPhysicalDevicePrivateDataFeaturesEXT *)ext;
1369 features->privateData = true;
1370 break;
1371 }
1372 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_CREATION_CACHE_CONTROL_FEATURES_EXT: {
1373 VkPhysicalDevicePipelineCreationCacheControlFeaturesEXT *features =
1374 (VkPhysicalDevicePipelineCreationCacheControlFeaturesEXT *)ext;
1375 features-> pipelineCreationCacheControl = true;
1376 break;
1377 }
1378 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_MEMORY_MODEL_FEATURES_KHR: {
1379 VkPhysicalDeviceVulkanMemoryModelFeaturesKHR *features =
1380 (VkPhysicalDeviceVulkanMemoryModelFeaturesKHR *)ext;
1381 CORE_FEATURE(1, 2, vulkanMemoryModel);
1382 CORE_FEATURE(1, 2, vulkanMemoryModelDeviceScope);
1383 CORE_FEATURE(1, 2, vulkanMemoryModelAvailabilityVisibilityChains);
1384 break;
1385 }
1386 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTENDED_DYNAMIC_STATE_FEATURES_EXT: {
1387 VkPhysicalDeviceExtendedDynamicStateFeaturesEXT *features =
1388 (VkPhysicalDeviceExtendedDynamicStateFeaturesEXT *) ext;
1389 features->extendedDynamicState = true;
1390 break;
1391 }
1392 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGE_ROBUSTNESS_FEATURES_EXT: {
1393 VkPhysicalDeviceImageRobustnessFeaturesEXT *features =
1394 (VkPhysicalDeviceImageRobustnessFeaturesEXT *)ext;
1395 features->robustImageAccess = true;
1396 break;
1397 }
1398 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_FLOAT_FEATURES_EXT: {
1399 VkPhysicalDeviceShaderAtomicFloatFeaturesEXT *features =
1400 (VkPhysicalDeviceShaderAtomicFloatFeaturesEXT *)ext;
1401 features->shaderBufferFloat32Atomics = true;
1402 features->shaderBufferFloat32AtomicAdd = false;
1403 features->shaderBufferFloat64Atomics = true;
1404 features->shaderBufferFloat64AtomicAdd = false;
1405 features->shaderSharedFloat32Atomics = true;
1406 features->shaderSharedFloat32AtomicAdd = pdevice->rad_info.chip_class >= GFX8 &&
1407 (!pdevice->use_llvm || LLVM_VERSION_MAJOR >= 10);
1408 features->shaderSharedFloat64Atomics = true;
1409 features->shaderSharedFloat64AtomicAdd = false;
1410 features->shaderImageFloat32Atomics = true;
1411 features->shaderImageFloat32AtomicAdd = false;
1412 features->sparseImageFloat32Atomics = false;
1413 features->sparseImageFloat32AtomicAdd = false;
1414 break;
1415 }
1416 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_4444_FORMATS_FEATURES_EXT: {
1417 VkPhysicalDevice4444FormatsFeaturesEXT *features =
1418 (VkPhysicalDevice4444FormatsFeaturesEXT *)ext;
1419 features->formatA4R4G4B4 = true;
1420 features->formatA4B4G4R4 = true;
1421 break;
1422 }
1423 default:
1424 break;
1425 }
1426 }
1427 #undef CORE_FEATURE
1428 }
1429
1430 static size_t
1431 radv_max_descriptor_set_size()
1432 {
1433 /* make sure that the entire descriptor set is addressable with a signed
1434 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1435 * be at most 2 GiB. the combined image & samples object count as one of
1436 * both. This limit is for the pipeline layout, not for the set layout, but
1437 * there is no set limit, so we just set a pipeline limit. I don't think
1438 * any app is going to hit this soon. */
1439 return ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
1440 - MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1441 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1442 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1443 32 /* sampler, largest when combined with image */ +
1444 64 /* sampled image */ +
1445 64 /* storage image */);
1446 }
1447
1448 void radv_GetPhysicalDeviceProperties(
1449 VkPhysicalDevice physicalDevice,
1450 VkPhysicalDeviceProperties* pProperties)
1451 {
1452 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1453 VkSampleCountFlags sample_counts = 0xf;
1454
1455 size_t max_descriptor_set_size = radv_max_descriptor_set_size();
1456
1457 VkPhysicalDeviceLimits limits = {
1458 .maxImageDimension1D = (1 << 14),
1459 .maxImageDimension2D = (1 << 14),
1460 .maxImageDimension3D = (1 << 11),
1461 .maxImageDimensionCube = (1 << 14),
1462 .maxImageArrayLayers = (1 << 11),
1463 .maxTexelBufferElements = UINT32_MAX,
1464 .maxUniformBufferRange = UINT32_MAX,
1465 .maxStorageBufferRange = UINT32_MAX,
1466 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1467 .maxMemoryAllocationCount = UINT32_MAX,
1468 .maxSamplerAllocationCount = 64 * 1024,
1469 .bufferImageGranularity = 64, /* A cache line */
1470 .sparseAddressSpaceSize = RADV_MAX_MEMORY_ALLOCATION_SIZE, /* buffer max size */
1471 .maxBoundDescriptorSets = MAX_SETS,
1472 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1473 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1474 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1475 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1476 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1477 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1478 .maxPerStageResources = max_descriptor_set_size,
1479 .maxDescriptorSetSamplers = max_descriptor_set_size,
1480 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1481 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1482 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1483 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1484 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1485 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1486 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1487 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1488 .maxVertexInputBindings = MAX_VBS,
1489 .maxVertexInputAttributeOffset = 2047,
1490 .maxVertexInputBindingStride = 2048,
1491 .maxVertexOutputComponents = 128,
1492 .maxTessellationGenerationLevel = 64,
1493 .maxTessellationPatchSize = 32,
1494 .maxTessellationControlPerVertexInputComponents = 128,
1495 .maxTessellationControlPerVertexOutputComponents = 128,
1496 .maxTessellationControlPerPatchOutputComponents = 120,
1497 .maxTessellationControlTotalOutputComponents = 4096,
1498 .maxTessellationEvaluationInputComponents = 128,
1499 .maxTessellationEvaluationOutputComponents = 128,
1500 .maxGeometryShaderInvocations = 127,
1501 .maxGeometryInputComponents = 64,
1502 .maxGeometryOutputComponents = 128,
1503 .maxGeometryOutputVertices = 256,
1504 .maxGeometryTotalOutputComponents = 1024,
1505 .maxFragmentInputComponents = 128,
1506 .maxFragmentOutputAttachments = 8,
1507 .maxFragmentDualSrcAttachments = 1,
1508 .maxFragmentCombinedOutputResources = 8,
1509 .maxComputeSharedMemorySize = 32768,
1510 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1511 .maxComputeWorkGroupInvocations = 1024,
1512 .maxComputeWorkGroupSize = {
1513 1024,
1514 1024,
1515 1024
1516 },
1517 .subPixelPrecisionBits = 8,
1518 .subTexelPrecisionBits = 8,
1519 .mipmapPrecisionBits = 8,
1520 .maxDrawIndexedIndexValue = UINT32_MAX,
1521 .maxDrawIndirectCount = UINT32_MAX,
1522 .maxSamplerLodBias = 16,
1523 .maxSamplerAnisotropy = 16,
1524 .maxViewports = MAX_VIEWPORTS,
1525 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1526 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1527 .viewportSubPixelBits = 8,
1528 .minMemoryMapAlignment = 4096, /* A page */
1529 .minTexelBufferOffsetAlignment = 4,
1530 .minUniformBufferOffsetAlignment = 4,
1531 .minStorageBufferOffsetAlignment = 4,
1532 .minTexelOffset = -32,
1533 .maxTexelOffset = 31,
1534 .minTexelGatherOffset = -32,
1535 .maxTexelGatherOffset = 31,
1536 .minInterpolationOffset = -2,
1537 .maxInterpolationOffset = 2,
1538 .subPixelInterpolationOffsetBits = 8,
1539 .maxFramebufferWidth = (1 << 14),
1540 .maxFramebufferHeight = (1 << 14),
1541 .maxFramebufferLayers = (1 << 10),
1542 .framebufferColorSampleCounts = sample_counts,
1543 .framebufferDepthSampleCounts = sample_counts,
1544 .framebufferStencilSampleCounts = sample_counts,
1545 .framebufferNoAttachmentsSampleCounts = sample_counts,
1546 .maxColorAttachments = MAX_RTS,
1547 .sampledImageColorSampleCounts = sample_counts,
1548 .sampledImageIntegerSampleCounts = sample_counts,
1549 .sampledImageDepthSampleCounts = sample_counts,
1550 .sampledImageStencilSampleCounts = sample_counts,
1551 .storageImageSampleCounts = sample_counts,
1552 .maxSampleMaskWords = 1,
1553 .timestampComputeAndGraphics = true,
1554 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1555 .maxClipDistances = 8,
1556 .maxCullDistances = 8,
1557 .maxCombinedClipAndCullDistances = 8,
1558 .discreteQueuePriorities = 2,
1559 .pointSizeRange = { 0.0, 8191.875 },
1560 .lineWidthRange = { 0.0, 8191.875 },
1561 .pointSizeGranularity = (1.0 / 8.0),
1562 .lineWidthGranularity = (1.0 / 8.0),
1563 .strictLines = false, /* FINISHME */
1564 .standardSampleLocations = true,
1565 .optimalBufferCopyOffsetAlignment = 128,
1566 .optimalBufferCopyRowPitchAlignment = 128,
1567 .nonCoherentAtomSize = 64,
1568 };
1569
1570 *pProperties = (VkPhysicalDeviceProperties) {
1571 .apiVersion = radv_physical_device_api_version(pdevice),
1572 .driverVersion = vk_get_driver_version(),
1573 .vendorID = ATI_VENDOR_ID,
1574 .deviceID = pdevice->rad_info.pci_id,
1575 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1576 .limits = limits,
1577 .sparseProperties = {0},
1578 };
1579
1580 strcpy(pProperties->deviceName, pdevice->name);
1581 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1582 }
1583
1584 static void
1585 radv_get_physical_device_properties_1_1(struct radv_physical_device *pdevice,
1586 VkPhysicalDeviceVulkan11Properties *p)
1587 {
1588 assert(p->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES);
1589
1590 memcpy(p->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1591 memcpy(p->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1592 memset(p->deviceLUID, 0, VK_LUID_SIZE);
1593 /* The LUID is for Windows. */
1594 p->deviceLUIDValid = false;
1595 p->deviceNodeMask = 0;
1596
1597 p->subgroupSize = RADV_SUBGROUP_SIZE;
1598 p->subgroupSupportedStages = VK_SHADER_STAGE_ALL_GRAPHICS |
1599 VK_SHADER_STAGE_COMPUTE_BIT;
1600 p->subgroupSupportedOperations = VK_SUBGROUP_FEATURE_BASIC_BIT |
1601 VK_SUBGROUP_FEATURE_VOTE_BIT |
1602 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1603 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1604 VK_SUBGROUP_FEATURE_CLUSTERED_BIT |
1605 VK_SUBGROUP_FEATURE_QUAD_BIT |
1606 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1607 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1608 p->subgroupQuadOperationsInAllStages = true;
1609
1610 p->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1611 p->maxMultiviewViewCount = MAX_VIEWS;
1612 p->maxMultiviewInstanceIndex = INT_MAX;
1613 p->protectedNoFault = false;
1614 p->maxPerSetDescriptors = RADV_MAX_PER_SET_DESCRIPTORS;
1615 p->maxMemoryAllocationSize = RADV_MAX_MEMORY_ALLOCATION_SIZE;
1616 }
1617
1618 static void
1619 radv_get_physical_device_properties_1_2(struct radv_physical_device *pdevice,
1620 VkPhysicalDeviceVulkan12Properties *p)
1621 {
1622 assert(p->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES);
1623
1624 p->driverID = VK_DRIVER_ID_MESA_RADV;
1625 snprintf(p->driverName, VK_MAX_DRIVER_NAME_SIZE, "radv");
1626 snprintf(p->driverInfo, VK_MAX_DRIVER_INFO_SIZE,
1627 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1 " (%s)",
1628 radv_get_compiler_string(pdevice));
1629 p->conformanceVersion = (VkConformanceVersion) {
1630 .major = 1,
1631 .minor = 2,
1632 .subminor = 0,
1633 .patch = 0,
1634 };
1635
1636 /* On AMD hardware, denormals and rounding modes for fp16/fp64 are
1637 * controlled by the same config register.
1638 */
1639 if (pdevice->rad_info.has_packed_math_16bit) {
1640 p->denormBehaviorIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
1641 p->roundingModeIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
1642 } else {
1643 p->denormBehaviorIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL_KHR;
1644 p->roundingModeIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL_KHR;
1645 }
1646
1647 /* With LLVM, do not allow both preserving and flushing denorms because
1648 * different shaders in the same pipeline can have different settings and
1649 * this won't work for merged shaders. To make it work, this requires LLVM
1650 * support for changing the register. The same logic applies for the
1651 * rounding modes because they are configured with the same config
1652 * register.
1653 */
1654 p->shaderDenormFlushToZeroFloat32 = true;
1655 p->shaderDenormPreserveFloat32 = !pdevice->use_llvm;
1656 p->shaderRoundingModeRTEFloat32 = true;
1657 p->shaderRoundingModeRTZFloat32 = !pdevice->use_llvm;
1658 p->shaderSignedZeroInfNanPreserveFloat32 = true;
1659
1660 p->shaderDenormFlushToZeroFloat16 = pdevice->rad_info.has_packed_math_16bit && !pdevice->use_llvm;
1661 p->shaderDenormPreserveFloat16 = pdevice->rad_info.has_packed_math_16bit;
1662 p->shaderRoundingModeRTEFloat16 = pdevice->rad_info.has_packed_math_16bit;
1663 p->shaderRoundingModeRTZFloat16 = pdevice->rad_info.has_packed_math_16bit && !pdevice->use_llvm;
1664 p->shaderSignedZeroInfNanPreserveFloat16 = pdevice->rad_info.has_packed_math_16bit;
1665
1666 p->shaderDenormFlushToZeroFloat64 = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_llvm;
1667 p->shaderDenormPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8;
1668 p->shaderRoundingModeRTEFloat64 = pdevice->rad_info.chip_class >= GFX8;
1669 p->shaderRoundingModeRTZFloat64 = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_llvm;
1670 p->shaderSignedZeroInfNanPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8;
1671
1672 p->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1673 p->shaderUniformBufferArrayNonUniformIndexingNative = false;
1674 p->shaderSampledImageArrayNonUniformIndexingNative = false;
1675 p->shaderStorageBufferArrayNonUniformIndexingNative = false;
1676 p->shaderStorageImageArrayNonUniformIndexingNative = false;
1677 p->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1678 p->robustBufferAccessUpdateAfterBind = false;
1679 p->quadDivergentImplicitLod = false;
1680
1681 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1682 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1683 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1684 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1685 32 /* sampler, largest when combined with image */ +
1686 64 /* sampled image */ +
1687 64 /* storage image */);
1688 p->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1689 p->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1690 p->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1691 p->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1692 p->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1693 p->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1694 p->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1695 p->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1696 p->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1697 p->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1698 p->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1699 p->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1700 p->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1701 p->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1702 p->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1703
1704 /* We support all of the depth resolve modes */
1705 p->supportedDepthResolveModes = VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1706 VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
1707 VK_RESOLVE_MODE_MIN_BIT_KHR |
1708 VK_RESOLVE_MODE_MAX_BIT_KHR;
1709
1710 /* Average doesn't make sense for stencil so we don't support that */
1711 p->supportedStencilResolveModes = VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1712 VK_RESOLVE_MODE_MIN_BIT_KHR |
1713 VK_RESOLVE_MODE_MAX_BIT_KHR;
1714
1715 p->independentResolveNone = true;
1716 p->independentResolve = true;
1717
1718 /* GFX6-8 only support single channel min/max filter. */
1719 p->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1720 p->filterMinmaxSingleComponentFormats = true;
1721
1722 p->maxTimelineSemaphoreValueDifference = UINT64_MAX;
1723
1724 p->framebufferIntegerColorSampleCounts = VK_SAMPLE_COUNT_1_BIT;
1725 }
1726
1727 void radv_GetPhysicalDeviceProperties2(
1728 VkPhysicalDevice physicalDevice,
1729 VkPhysicalDeviceProperties2 *pProperties)
1730 {
1731 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1732 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1733
1734 VkPhysicalDeviceVulkan11Properties core_1_1 = {
1735 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES,
1736 };
1737 radv_get_physical_device_properties_1_1(pdevice, &core_1_1);
1738
1739 VkPhysicalDeviceVulkan12Properties core_1_2 = {
1740 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES,
1741 };
1742 radv_get_physical_device_properties_1_2(pdevice, &core_1_2);
1743
1744 #define CORE_RENAMED_PROPERTY(major, minor, ext_property, core_property) \
1745 memcpy(&properties->ext_property, &core_##major##_##minor.core_property, \
1746 sizeof(core_##major##_##minor.core_property))
1747
1748 #define CORE_PROPERTY(major, minor, property) \
1749 CORE_RENAMED_PROPERTY(major, minor, property, property)
1750
1751 vk_foreach_struct(ext, pProperties->pNext) {
1752 switch (ext->sType) {
1753 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1754 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1755 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1756 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1757 break;
1758 }
1759 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1760 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1761 CORE_PROPERTY(1, 1, deviceUUID);
1762 CORE_PROPERTY(1, 1, driverUUID);
1763 CORE_PROPERTY(1, 1, deviceLUID);
1764 CORE_PROPERTY(1, 1, deviceLUIDValid);
1765 break;
1766 }
1767 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1768 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1769 CORE_PROPERTY(1, 1, maxMultiviewViewCount);
1770 CORE_PROPERTY(1, 1, maxMultiviewInstanceIndex);
1771 break;
1772 }
1773 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1774 VkPhysicalDevicePointClippingProperties *properties =
1775 (VkPhysicalDevicePointClippingProperties*)ext;
1776 CORE_PROPERTY(1, 1, pointClippingBehavior);
1777 break;
1778 }
1779 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1780 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1781 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1782 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1783 break;
1784 }
1785 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1786 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1787 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1788 properties->minImportedHostPointerAlignment = 4096;
1789 break;
1790 }
1791 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1792 VkPhysicalDeviceSubgroupProperties *properties =
1793 (VkPhysicalDeviceSubgroupProperties*)ext;
1794 CORE_PROPERTY(1, 1, subgroupSize);
1795 CORE_RENAMED_PROPERTY(1, 1, supportedStages,
1796 subgroupSupportedStages);
1797 CORE_RENAMED_PROPERTY(1, 1, supportedOperations,
1798 subgroupSupportedOperations);
1799 CORE_RENAMED_PROPERTY(1, 1, quadOperationsInAllStages,
1800 subgroupQuadOperationsInAllStages);
1801 break;
1802 }
1803 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1804 VkPhysicalDeviceMaintenance3Properties *properties =
1805 (VkPhysicalDeviceMaintenance3Properties*)ext;
1806 CORE_PROPERTY(1, 1, maxPerSetDescriptors);
1807 CORE_PROPERTY(1, 1, maxMemoryAllocationSize);
1808 break;
1809 }
1810 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES: {
1811 VkPhysicalDeviceSamplerFilterMinmaxProperties *properties =
1812 (VkPhysicalDeviceSamplerFilterMinmaxProperties *)ext;
1813 CORE_PROPERTY(1, 2, filterMinmaxImageComponentMapping);
1814 CORE_PROPERTY(1, 2, filterMinmaxSingleComponentFormats);
1815 break;
1816 }
1817 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1818 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1819 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1820
1821 /* Shader engines. */
1822 properties->shaderEngineCount =
1823 pdevice->rad_info.max_se;
1824 properties->shaderArraysPerEngineCount =
1825 pdevice->rad_info.max_sh_per_se;
1826 properties->computeUnitsPerShaderArray =
1827 pdevice->rad_info.min_good_cu_per_sa;
1828 properties->simdPerComputeUnit =
1829 pdevice->rad_info.num_simd_per_compute_unit;
1830 properties->wavefrontsPerSimd =
1831 pdevice->rad_info.max_wave64_per_simd;
1832 properties->wavefrontSize = 64;
1833
1834 /* SGPR. */
1835 properties->sgprsPerSimd =
1836 pdevice->rad_info.num_physical_sgprs_per_simd;
1837 properties->minSgprAllocation =
1838 pdevice->rad_info.min_sgpr_alloc;
1839 properties->maxSgprAllocation =
1840 pdevice->rad_info.max_sgpr_alloc;
1841 properties->sgprAllocationGranularity =
1842 pdevice->rad_info.sgpr_alloc_granularity;
1843
1844 /* VGPR. */
1845 properties->vgprsPerSimd =
1846 pdevice->rad_info.num_physical_wave64_vgprs_per_simd;
1847 properties->minVgprAllocation =
1848 pdevice->rad_info.min_wave64_vgpr_alloc;
1849 properties->maxVgprAllocation =
1850 pdevice->rad_info.max_vgpr_alloc;
1851 properties->vgprAllocationGranularity =
1852 pdevice->rad_info.wave64_vgpr_alloc_granularity;
1853 break;
1854 }
1855 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_2_AMD: {
1856 VkPhysicalDeviceShaderCoreProperties2AMD *properties =
1857 (VkPhysicalDeviceShaderCoreProperties2AMD *)ext;
1858
1859 properties->shaderCoreFeatures = 0;
1860 properties->activeComputeUnitCount =
1861 pdevice->rad_info.num_good_compute_units;
1862 break;
1863 }
1864 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1865 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1866 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1867 properties->maxVertexAttribDivisor = UINT32_MAX;
1868 break;
1869 }
1870 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES: {
1871 VkPhysicalDeviceDescriptorIndexingProperties *properties =
1872 (VkPhysicalDeviceDescriptorIndexingProperties*)ext;
1873 CORE_PROPERTY(1, 2, maxUpdateAfterBindDescriptorsInAllPools);
1874 CORE_PROPERTY(1, 2, shaderUniformBufferArrayNonUniformIndexingNative);
1875 CORE_PROPERTY(1, 2, shaderSampledImageArrayNonUniformIndexingNative);
1876 CORE_PROPERTY(1, 2, shaderStorageBufferArrayNonUniformIndexingNative);
1877 CORE_PROPERTY(1, 2, shaderStorageImageArrayNonUniformIndexingNative);
1878 CORE_PROPERTY(1, 2, shaderInputAttachmentArrayNonUniformIndexingNative);
1879 CORE_PROPERTY(1, 2, robustBufferAccessUpdateAfterBind);
1880 CORE_PROPERTY(1, 2, quadDivergentImplicitLod);
1881 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSamplers);
1882 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindUniformBuffers);
1883 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageBuffers);
1884 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSampledImages);
1885 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageImages);
1886 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindInputAttachments);
1887 CORE_PROPERTY(1, 2, maxPerStageUpdateAfterBindResources);
1888 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSamplers);
1889 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffers);
1890 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffersDynamic);
1891 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffers);
1892 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffersDynamic);
1893 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSampledImages);
1894 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageImages);
1895 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindInputAttachments);
1896 break;
1897 }
1898 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1899 VkPhysicalDeviceProtectedMemoryProperties *properties =
1900 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1901 CORE_PROPERTY(1, 1, protectedNoFault);
1902 break;
1903 }
1904 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1905 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1906 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1907 properties->primitiveOverestimationSize = 0;
1908 properties->maxExtraPrimitiveOverestimationSize = 0;
1909 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1910 properties->primitiveUnderestimation = false;
1911 properties->conservativePointAndLineRasterization = false;
1912 properties->degenerateTrianglesRasterized = false;
1913 properties->degenerateLinesRasterized = false;
1914 properties->fullyCoveredFragmentShaderInputVariable = false;
1915 properties->conservativeRasterizationPostDepthCoverage = false;
1916 break;
1917 }
1918 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1919 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1920 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1921 properties->pciDomain = pdevice->bus_info.domain;
1922 properties->pciBus = pdevice->bus_info.bus;
1923 properties->pciDevice = pdevice->bus_info.dev;
1924 properties->pciFunction = pdevice->bus_info.func;
1925 break;
1926 }
1927 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES: {
1928 VkPhysicalDeviceDriverProperties *properties =
1929 (VkPhysicalDeviceDriverProperties *) ext;
1930 CORE_PROPERTY(1, 2, driverID);
1931 CORE_PROPERTY(1, 2, driverName);
1932 CORE_PROPERTY(1, 2, driverInfo);
1933 CORE_PROPERTY(1, 2, conformanceVersion);
1934 break;
1935 }
1936 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1937 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1938 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1939 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1940 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1941 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1942 properties->maxTransformFeedbackStreamDataSize = 512;
1943 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1944 properties->maxTransformFeedbackBufferDataStride = 512;
1945 properties->transformFeedbackQueries = !pdevice->use_ngg_streamout;
1946 properties->transformFeedbackStreamsLinesTriangles = !pdevice->use_ngg_streamout;
1947 properties->transformFeedbackRasterizationStreamSelect = false;
1948 properties->transformFeedbackDraw = true;
1949 break;
1950 }
1951 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1952 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1953 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1954
1955 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1956 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1957 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1958 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1959 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1960 break;
1961 }
1962 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT: {
1963 VkPhysicalDeviceSampleLocationsPropertiesEXT *properties =
1964 (VkPhysicalDeviceSampleLocationsPropertiesEXT *)ext;
1965 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_2_BIT |
1966 VK_SAMPLE_COUNT_4_BIT |
1967 VK_SAMPLE_COUNT_8_BIT;
1968 properties->maxSampleLocationGridSize = (VkExtent2D){ 2 , 2 };
1969 properties->sampleLocationCoordinateRange[0] = 0.0f;
1970 properties->sampleLocationCoordinateRange[1] = 0.9375f;
1971 properties->sampleLocationSubPixelBits = 4;
1972 properties->variableSampleLocations = false;
1973 break;
1974 }
1975 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES: {
1976 VkPhysicalDeviceDepthStencilResolveProperties *properties =
1977 (VkPhysicalDeviceDepthStencilResolveProperties *)ext;
1978 CORE_PROPERTY(1, 2, supportedDepthResolveModes);
1979 CORE_PROPERTY(1, 2, supportedStencilResolveModes);
1980 CORE_PROPERTY(1, 2, independentResolveNone);
1981 CORE_PROPERTY(1, 2, independentResolve);
1982 break;
1983 }
1984 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_PROPERTIES_EXT: {
1985 VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT *properties =
1986 (VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT *)ext;
1987 properties->storageTexelBufferOffsetAlignmentBytes = 4;
1988 properties->storageTexelBufferOffsetSingleTexelAlignment = true;
1989 properties->uniformTexelBufferOffsetAlignmentBytes = 4;
1990 properties->uniformTexelBufferOffsetSingleTexelAlignment = true;
1991 break;
1992 }
1993 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT_CONTROLS_PROPERTIES : {
1994 VkPhysicalDeviceFloatControlsProperties *properties =
1995 (VkPhysicalDeviceFloatControlsProperties *)ext;
1996 CORE_PROPERTY(1, 2, denormBehaviorIndependence);
1997 CORE_PROPERTY(1, 2, roundingModeIndependence);
1998 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat16);
1999 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat16);
2000 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat16);
2001 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat16);
2002 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat16);
2003 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat32);
2004 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat32);
2005 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat32);
2006 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat32);
2007 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat32);
2008 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat64);
2009 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat64);
2010 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat64);
2011 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat64);
2012 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat64);
2013 break;
2014 }
2015 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_PROPERTIES: {
2016 VkPhysicalDeviceTimelineSemaphoreProperties *properties =
2017 (VkPhysicalDeviceTimelineSemaphoreProperties *) ext;
2018 CORE_PROPERTY(1, 2, maxTimelineSemaphoreValueDifference);
2019 break;
2020 }
2021 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_PROPERTIES_EXT: {
2022 VkPhysicalDeviceSubgroupSizeControlPropertiesEXT *props =
2023 (VkPhysicalDeviceSubgroupSizeControlPropertiesEXT *)ext;
2024 props->minSubgroupSize = 64;
2025 props->maxSubgroupSize = 64;
2026 props->maxComputeWorkgroupSubgroups = UINT32_MAX;
2027 props->requiredSubgroupSizeStages = 0;
2028
2029 if (pdevice->rad_info.chip_class >= GFX10) {
2030 /* Only GFX10+ supports wave32. */
2031 props->minSubgroupSize = 32;
2032 props->requiredSubgroupSizeStages = VK_SHADER_STAGE_COMPUTE_BIT;
2033 }
2034 break;
2035 }
2036 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES:
2037 radv_get_physical_device_properties_1_1(pdevice, (void *)ext);
2038 break;
2039 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES:
2040 radv_get_physical_device_properties_1_2(pdevice, (void *)ext);
2041 break;
2042 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_PROPERTIES_EXT: {
2043 VkPhysicalDeviceLineRasterizationPropertiesEXT *props =
2044 (VkPhysicalDeviceLineRasterizationPropertiesEXT *)ext;
2045 props->lineSubPixelPrecisionBits = 4;
2046 break;
2047 }
2048 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ROBUSTNESS_2_PROPERTIES_EXT: {
2049 VkPhysicalDeviceRobustness2PropertiesEXT *properties =
2050 (VkPhysicalDeviceRobustness2PropertiesEXT *)ext;
2051 properties->robustStorageBufferAccessSizeAlignment = 4;
2052 properties->robustUniformBufferAccessSizeAlignment = 4;
2053 break;
2054 }
2055 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_PROPERTIES_EXT: {
2056 VkPhysicalDeviceCustomBorderColorPropertiesEXT *props =
2057 (VkPhysicalDeviceCustomBorderColorPropertiesEXT *)ext;
2058 props->maxCustomBorderColorSamplers = RADV_BORDER_COLOR_COUNT;
2059 break;
2060 }
2061 default:
2062 break;
2063 }
2064 }
2065 }
2066
2067 static void radv_get_physical_device_queue_family_properties(
2068 struct radv_physical_device* pdevice,
2069 uint32_t* pCount,
2070 VkQueueFamilyProperties** pQueueFamilyProperties)
2071 {
2072 int num_queue_families = 1;
2073 int idx;
2074 if (pdevice->rad_info.num_rings[RING_COMPUTE] > 0 &&
2075 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
2076 num_queue_families++;
2077
2078 if (pQueueFamilyProperties == NULL) {
2079 *pCount = num_queue_families;
2080 return;
2081 }
2082
2083 if (!*pCount)
2084 return;
2085
2086 idx = 0;
2087 if (*pCount >= 1) {
2088 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
2089 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
2090 VK_QUEUE_COMPUTE_BIT |
2091 VK_QUEUE_TRANSFER_BIT |
2092 VK_QUEUE_SPARSE_BINDING_BIT,
2093 .queueCount = 1,
2094 .timestampValidBits = 64,
2095 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
2096 };
2097 idx++;
2098 }
2099
2100 if (pdevice->rad_info.num_rings[RING_COMPUTE] > 0 &&
2101 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
2102 if (*pCount > idx) {
2103 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
2104 .queueFlags = VK_QUEUE_COMPUTE_BIT |
2105 VK_QUEUE_TRANSFER_BIT |
2106 VK_QUEUE_SPARSE_BINDING_BIT,
2107 .queueCount = pdevice->rad_info.num_rings[RING_COMPUTE],
2108 .timestampValidBits = 64,
2109 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
2110 };
2111 idx++;
2112 }
2113 }
2114 *pCount = idx;
2115 }
2116
2117 void radv_GetPhysicalDeviceQueueFamilyProperties(
2118 VkPhysicalDevice physicalDevice,
2119 uint32_t* pCount,
2120 VkQueueFamilyProperties* pQueueFamilyProperties)
2121 {
2122 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
2123 if (!pQueueFamilyProperties) {
2124 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
2125 return;
2126 }
2127 VkQueueFamilyProperties *properties[] = {
2128 pQueueFamilyProperties + 0,
2129 pQueueFamilyProperties + 1,
2130 pQueueFamilyProperties + 2,
2131 };
2132 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
2133 assert(*pCount <= 3);
2134 }
2135
2136 void radv_GetPhysicalDeviceQueueFamilyProperties2(
2137 VkPhysicalDevice physicalDevice,
2138 uint32_t* pCount,
2139 VkQueueFamilyProperties2 *pQueueFamilyProperties)
2140 {
2141 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
2142 if (!pQueueFamilyProperties) {
2143 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
2144 return;
2145 }
2146 VkQueueFamilyProperties *properties[] = {
2147 &pQueueFamilyProperties[0].queueFamilyProperties,
2148 &pQueueFamilyProperties[1].queueFamilyProperties,
2149 &pQueueFamilyProperties[2].queueFamilyProperties,
2150 };
2151 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
2152 assert(*pCount <= 3);
2153 }
2154
2155 void radv_GetPhysicalDeviceMemoryProperties(
2156 VkPhysicalDevice physicalDevice,
2157 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
2158 {
2159 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2160
2161 *pMemoryProperties = physical_device->memory_properties;
2162 }
2163
2164 static void
2165 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
2166 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
2167 {
2168 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2169 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
2170 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
2171 uint64_t vram_size = radv_get_vram_size(device);
2172 uint64_t gtt_size = device->rad_info.gart_size;
2173 uint64_t heap_budget, heap_usage;
2174
2175 /* For all memory heaps, the computation of budget is as follow:
2176 * heap_budget = heap_size - global_heap_usage + app_heap_usage
2177 *
2178 * The Vulkan spec 1.1.97 says that the budget should include any
2179 * currently allocated device memory.
2180 *
2181 * Note that the application heap usages are not really accurate (eg.
2182 * in presence of shared buffers).
2183 */
2184 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
2185 uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;
2186
2187 if ((device->memory_domains[i] & RADEON_DOMAIN_VRAM) && (device->memory_flags[i] & RADEON_FLAG_NO_CPU_ACCESS)) {
2188 heap_usage = device->ws->query_value(device->ws,
2189 RADEON_ALLOCATED_VRAM);
2190
2191 heap_budget = vram_size -
2192 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
2193 heap_usage;
2194
2195 memoryBudget->heapBudget[heap_index] = heap_budget;
2196 memoryBudget->heapUsage[heap_index] = heap_usage;
2197 } else if (device->memory_domains[i] & RADEON_DOMAIN_VRAM) {
2198 heap_usage = device->ws->query_value(device->ws,
2199 RADEON_ALLOCATED_VRAM_VIS);
2200
2201 heap_budget = visible_vram_size -
2202 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
2203 heap_usage;
2204
2205 memoryBudget->heapBudget[heap_index] = heap_budget;
2206 memoryBudget->heapUsage[heap_index] = heap_usage;
2207 } else {
2208 assert(device->memory_domains[i] & RADEON_DOMAIN_GTT);
2209
2210 heap_usage = device->ws->query_value(device->ws,
2211 RADEON_ALLOCATED_GTT);
2212
2213 heap_budget = gtt_size -
2214 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
2215 heap_usage;
2216
2217 memoryBudget->heapBudget[heap_index] = heap_budget;
2218 memoryBudget->heapUsage[heap_index] = heap_usage;
2219 }
2220 }
2221
2222 /* The heapBudget and heapUsage values must be zero for array elements
2223 * greater than or equal to
2224 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
2225 */
2226 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
2227 memoryBudget->heapBudget[i] = 0;
2228 memoryBudget->heapUsage[i] = 0;
2229 }
2230 }
2231
2232 void radv_GetPhysicalDeviceMemoryProperties2(
2233 VkPhysicalDevice physicalDevice,
2234 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
2235 {
2236 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
2237 &pMemoryProperties->memoryProperties);
2238
2239 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
2240 vk_find_struct(pMemoryProperties->pNext,
2241 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
2242 if (memory_budget)
2243 radv_get_memory_budget_properties(physicalDevice, memory_budget);
2244 }
2245
2246 VkResult radv_GetMemoryHostPointerPropertiesEXT(
2247 VkDevice _device,
2248 VkExternalMemoryHandleTypeFlagBits handleType,
2249 const void *pHostPointer,
2250 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
2251 {
2252 RADV_FROM_HANDLE(radv_device, device, _device);
2253
2254 switch (handleType)
2255 {
2256 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
2257 const struct radv_physical_device *physical_device = device->physical_device;
2258 uint32_t memoryTypeBits = 0;
2259 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
2260 if (physical_device->memory_domains[i] == RADEON_DOMAIN_GTT &&
2261 !(physical_device->memory_flags[i] & RADEON_FLAG_GTT_WC)) {
2262 memoryTypeBits = (1 << i);
2263 break;
2264 }
2265 }
2266 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
2267 return VK_SUCCESS;
2268 }
2269 default:
2270 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
2271 }
2272 }
2273
2274 static enum radeon_ctx_priority
2275 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
2276 {
2277 /* Default to MEDIUM when a specific global priority isn't requested */
2278 if (!pObj)
2279 return RADEON_CTX_PRIORITY_MEDIUM;
2280
2281 switch(pObj->globalPriority) {
2282 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
2283 return RADEON_CTX_PRIORITY_REALTIME;
2284 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
2285 return RADEON_CTX_PRIORITY_HIGH;
2286 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
2287 return RADEON_CTX_PRIORITY_MEDIUM;
2288 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
2289 return RADEON_CTX_PRIORITY_LOW;
2290 default:
2291 unreachable("Illegal global priority value");
2292 return RADEON_CTX_PRIORITY_INVALID;
2293 }
2294 }
2295
2296 static int
2297 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
2298 uint32_t queue_family_index, int idx,
2299 VkDeviceQueueCreateFlags flags,
2300 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
2301 {
2302 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2303 queue->device = device;
2304 queue->queue_family_index = queue_family_index;
2305 queue->queue_idx = idx;
2306 queue->priority = radv_get_queue_global_priority(global_priority);
2307 queue->flags = flags;
2308 queue->hw_ctx = NULL;
2309
2310 VkResult result = device->ws->ctx_create(device->ws, queue->priority, &queue->hw_ctx);
2311 if (result != VK_SUCCESS)
2312 return vk_error(device->instance, result);
2313
2314 list_inithead(&queue->pending_submissions);
2315 pthread_mutex_init(&queue->pending_mutex, NULL);
2316
2317 pthread_mutex_init(&queue->thread_mutex, NULL);
2318 queue->thread_submission = NULL;
2319 queue->thread_running = queue->thread_exit = false;
2320 result = radv_create_pthread_cond(&queue->thread_cond);
2321 if (result != VK_SUCCESS)
2322 return vk_error(device->instance, result);
2323
2324 return VK_SUCCESS;
2325 }
2326
2327 static void
2328 radv_queue_finish(struct radv_queue *queue)
2329 {
2330 if (queue->thread_running) {
2331 p_atomic_set(&queue->thread_exit, true);
2332 pthread_cond_broadcast(&queue->thread_cond);
2333 pthread_join(queue->submission_thread, NULL);
2334 }
2335 pthread_cond_destroy(&queue->thread_cond);
2336 pthread_mutex_destroy(&queue->pending_mutex);
2337 pthread_mutex_destroy(&queue->thread_mutex);
2338
2339 if (queue->hw_ctx)
2340 queue->device->ws->ctx_destroy(queue->hw_ctx);
2341
2342 if (queue->initial_full_flush_preamble_cs)
2343 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2344 if (queue->initial_preamble_cs)
2345 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2346 if (queue->continue_preamble_cs)
2347 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2348 if (queue->descriptor_bo)
2349 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2350 if (queue->scratch_bo)
2351 queue->device->ws->buffer_destroy(queue->scratch_bo);
2352 if (queue->esgs_ring_bo)
2353 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2354 if (queue->gsvs_ring_bo)
2355 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2356 if (queue->tess_rings_bo)
2357 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
2358 if (queue->gds_bo)
2359 queue->device->ws->buffer_destroy(queue->gds_bo);
2360 if (queue->gds_oa_bo)
2361 queue->device->ws->buffer_destroy(queue->gds_oa_bo);
2362 if (queue->compute_scratch_bo)
2363 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2364 }
2365
2366 static void
2367 radv_bo_list_init(struct radv_bo_list *bo_list)
2368 {
2369 pthread_mutex_init(&bo_list->mutex, NULL);
2370 bo_list->list.count = bo_list->capacity = 0;
2371 bo_list->list.bos = NULL;
2372 }
2373
2374 static void
2375 radv_bo_list_finish(struct radv_bo_list *bo_list)
2376 {
2377 free(bo_list->list.bos);
2378 pthread_mutex_destroy(&bo_list->mutex);
2379 }
2380
2381 VkResult radv_bo_list_add(struct radv_device *device,
2382 struct radeon_winsys_bo *bo)
2383 {
2384 struct radv_bo_list *bo_list = &device->bo_list;
2385
2386 if (bo->is_local)
2387 return VK_SUCCESS;
2388
2389 if (unlikely(!device->use_global_bo_list))
2390 return VK_SUCCESS;
2391
2392 pthread_mutex_lock(&bo_list->mutex);
2393 if (bo_list->list.count == bo_list->capacity) {
2394 unsigned capacity = MAX2(4, bo_list->capacity * 2);
2395 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
2396
2397 if (!data) {
2398 pthread_mutex_unlock(&bo_list->mutex);
2399 return VK_ERROR_OUT_OF_HOST_MEMORY;
2400 }
2401
2402 bo_list->list.bos = (struct radeon_winsys_bo**)data;
2403 bo_list->capacity = capacity;
2404 }
2405
2406 bo_list->list.bos[bo_list->list.count++] = bo;
2407 pthread_mutex_unlock(&bo_list->mutex);
2408 return VK_SUCCESS;
2409 }
2410
2411 void radv_bo_list_remove(struct radv_device *device,
2412 struct radeon_winsys_bo *bo)
2413 {
2414 struct radv_bo_list *bo_list = &device->bo_list;
2415
2416 if (bo->is_local)
2417 return;
2418
2419 if (unlikely(!device->use_global_bo_list))
2420 return;
2421
2422 pthread_mutex_lock(&bo_list->mutex);
2423 /* Loop the list backwards so we find the most recently added
2424 * memory first. */
2425 for(unsigned i = bo_list->list.count; i-- > 0;) {
2426 if (bo_list->list.bos[i] == bo) {
2427 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
2428 --bo_list->list.count;
2429 break;
2430 }
2431 }
2432 pthread_mutex_unlock(&bo_list->mutex);
2433 }
2434
2435 static void
2436 radv_device_init_gs_info(struct radv_device *device)
2437 {
2438 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
2439 device->physical_device->rad_info.family);
2440 }
2441
2442 static int radv_get_device_extension_index(const char *name)
2443 {
2444 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
2445 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
2446 return i;
2447 }
2448 return -1;
2449 }
2450
2451 static int
2452 radv_get_int_debug_option(const char *name, int default_value)
2453 {
2454 const char *str;
2455 int result;
2456
2457 str = getenv(name);
2458 if (!str) {
2459 result = default_value;
2460 } else {
2461 char *endptr;
2462
2463 result = strtol(str, &endptr, 0);
2464 if (str == endptr) {
2465 /* No digits founs. */
2466 result = default_value;
2467 }
2468 }
2469
2470 return result;
2471 }
2472
2473 static void
2474 radv_device_init_dispatch(struct radv_device *device)
2475 {
2476 const struct radv_instance *instance = device->physical_device->instance;
2477 const struct radv_device_dispatch_table *dispatch_table_layer = NULL;
2478 bool unchecked = instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS;
2479 int radv_thread_trace = radv_get_int_debug_option("RADV_THREAD_TRACE", -1);
2480
2481 if (radv_thread_trace >= 0) {
2482 /* Use device entrypoints from the SQTT layer if enabled. */
2483 dispatch_table_layer = &sqtt_device_dispatch_table;
2484 }
2485
2486 for (unsigned i = 0; i < ARRAY_SIZE(device->dispatch.entrypoints); i++) {
2487 /* Vulkan requires that entrypoints for extensions which have not been
2488 * enabled must not be advertised.
2489 */
2490 if (!unchecked &&
2491 !radv_device_entrypoint_is_enabled(i, instance->apiVersion,
2492 &instance->enabled_extensions,
2493 &device->enabled_extensions)) {
2494 device->dispatch.entrypoints[i] = NULL;
2495 } else if (dispatch_table_layer &&
2496 dispatch_table_layer->entrypoints[i]) {
2497 device->dispatch.entrypoints[i] =
2498 dispatch_table_layer->entrypoints[i];
2499 } else {
2500 device->dispatch.entrypoints[i] =
2501 radv_device_dispatch_table.entrypoints[i];
2502 }
2503 }
2504 }
2505
2506 static VkResult
2507 radv_create_pthread_cond(pthread_cond_t *cond)
2508 {
2509 pthread_condattr_t condattr;
2510 if (pthread_condattr_init(&condattr)) {
2511 return VK_ERROR_INITIALIZATION_FAILED;
2512 }
2513
2514 if (pthread_condattr_setclock(&condattr, CLOCK_MONOTONIC)) {
2515 pthread_condattr_destroy(&condattr);
2516 return VK_ERROR_INITIALIZATION_FAILED;
2517 }
2518 if (pthread_cond_init(cond, &condattr)) {
2519 pthread_condattr_destroy(&condattr);
2520 return VK_ERROR_INITIALIZATION_FAILED;
2521 }
2522 pthread_condattr_destroy(&condattr);
2523 return VK_SUCCESS;
2524 }
2525
2526 static VkResult
2527 check_physical_device_features(VkPhysicalDevice physicalDevice,
2528 const VkPhysicalDeviceFeatures *features)
2529 {
2530 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2531 VkPhysicalDeviceFeatures supported_features;
2532 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
2533 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
2534 VkBool32 *enabled_feature = (VkBool32 *)features;
2535 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
2536 for (uint32_t i = 0; i < num_features; i++) {
2537 if (enabled_feature[i] && !supported_feature[i])
2538 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
2539 }
2540
2541 return VK_SUCCESS;
2542 }
2543
2544 static VkResult radv_device_init_border_color(struct radv_device *device)
2545 {
2546 device->border_color_data.bo =
2547 device->ws->buffer_create(device->ws,
2548 RADV_BORDER_COLOR_BUFFER_SIZE,
2549 4096,
2550 RADEON_DOMAIN_VRAM,
2551 RADEON_FLAG_CPU_ACCESS |
2552 RADEON_FLAG_READ_ONLY |
2553 RADEON_FLAG_NO_INTERPROCESS_SHARING,
2554 RADV_BO_PRIORITY_SHADER);
2555
2556 if (device->border_color_data.bo == NULL)
2557 return vk_error(device->physical_device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2558
2559 device->border_color_data.colors_gpu_ptr =
2560 device->ws->buffer_map(device->border_color_data.bo);
2561 if (!device->border_color_data.colors_gpu_ptr)
2562 return vk_error(device->physical_device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2563 pthread_mutex_init(&device->border_color_data.mutex, NULL);
2564
2565 return VK_SUCCESS;
2566 }
2567
2568 static void radv_device_finish_border_color(struct radv_device *device)
2569 {
2570 if (device->border_color_data.bo) {
2571 device->ws->buffer_destroy(device->border_color_data.bo);
2572
2573 pthread_mutex_destroy(&device->border_color_data.mutex);
2574 }
2575 }
2576
2577 VkResult radv_CreateDevice(
2578 VkPhysicalDevice physicalDevice,
2579 const VkDeviceCreateInfo* pCreateInfo,
2580 const VkAllocationCallbacks* pAllocator,
2581 VkDevice* pDevice)
2582 {
2583 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2584 VkResult result;
2585 struct radv_device *device;
2586
2587 bool keep_shader_info = false;
2588 bool robust_buffer_access = false;
2589 bool overallocation_disallowed = false;
2590 bool custom_border_colors = false;
2591
2592 /* Check enabled features */
2593 if (pCreateInfo->pEnabledFeatures) {
2594 result = check_physical_device_features(physicalDevice,
2595 pCreateInfo->pEnabledFeatures);
2596 if (result != VK_SUCCESS)
2597 return result;
2598
2599 if (pCreateInfo->pEnabledFeatures->robustBufferAccess)
2600 robust_buffer_access = true;
2601 }
2602
2603 vk_foreach_struct_const(ext, pCreateInfo->pNext) {
2604 switch (ext->sType) {
2605 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FEATURES_2: {
2606 const VkPhysicalDeviceFeatures2 *features = (const void *)ext;
2607 result = check_physical_device_features(physicalDevice,
2608 &features->features);
2609 if (result != VK_SUCCESS)
2610 return result;
2611
2612 if (features->features.robustBufferAccess)
2613 robust_buffer_access = true;
2614 break;
2615 }
2616 case VK_STRUCTURE_TYPE_DEVICE_MEMORY_OVERALLOCATION_CREATE_INFO_AMD: {
2617 const VkDeviceMemoryOverallocationCreateInfoAMD *overallocation = (const void *)ext;
2618 if (overallocation->overallocationBehavior == VK_MEMORY_OVERALLOCATION_BEHAVIOR_DISALLOWED_AMD)
2619 overallocation_disallowed = true;
2620 break;
2621 }
2622 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_FEATURES_EXT: {
2623 const VkPhysicalDeviceCustomBorderColorFeaturesEXT *border_color_features = (const void *)ext;
2624 custom_border_colors = border_color_features->customBorderColors;
2625 break;
2626 }
2627 default:
2628 break;
2629 }
2630 }
2631
2632 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
2633 sizeof(*device), 8,
2634 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2635 if (!device)
2636 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2637
2638 vk_device_init(&device->vk, pCreateInfo,
2639 &physical_device->instance->alloc, pAllocator);
2640
2641 device->instance = physical_device->instance;
2642 device->physical_device = physical_device;
2643
2644 device->ws = physical_device->ws;
2645
2646 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
2647 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
2648 int index = radv_get_device_extension_index(ext_name);
2649 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
2650 vk_free(&device->vk.alloc, device);
2651 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
2652 }
2653
2654 device->enabled_extensions.extensions[index] = true;
2655 }
2656
2657 radv_device_init_dispatch(device);
2658
2659 keep_shader_info = device->enabled_extensions.AMD_shader_info;
2660
2661 /* With update after bind we can't attach bo's to the command buffer
2662 * from the descriptor set anymore, so we have to use a global BO list.
2663 */
2664 device->use_global_bo_list =
2665 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
2666 device->enabled_extensions.EXT_descriptor_indexing ||
2667 device->enabled_extensions.EXT_buffer_device_address ||
2668 device->enabled_extensions.KHR_buffer_device_address;
2669
2670 device->robust_buffer_access = robust_buffer_access;
2671
2672 mtx_init(&device->shader_slab_mutex, mtx_plain);
2673 list_inithead(&device->shader_slabs);
2674
2675 device->overallocation_disallowed = overallocation_disallowed;
2676 mtx_init(&device->overallocation_mutex, mtx_plain);
2677
2678 radv_bo_list_init(&device->bo_list);
2679
2680 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
2681 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
2682 uint32_t qfi = queue_create->queueFamilyIndex;
2683 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
2684 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
2685
2686 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
2687
2688 device->queues[qfi] = vk_alloc(&device->vk.alloc,
2689 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2690 if (!device->queues[qfi]) {
2691 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2692 goto fail;
2693 }
2694
2695 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
2696
2697 device->queue_count[qfi] = queue_create->queueCount;
2698
2699 for (unsigned q = 0; q < queue_create->queueCount; q++) {
2700 result = radv_queue_init(device, &device->queues[qfi][q],
2701 qfi, q, queue_create->flags,
2702 global_priority);
2703 if (result != VK_SUCCESS)
2704 goto fail;
2705 }
2706 }
2707
2708 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
2709 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
2710
2711 /* Disable DFSM by default. As of 2019-09-15 Talos on Low is still 3% slower on Raven. */
2712 device->dfsm_allowed = device->pbb_allowed &&
2713 (device->instance->perftest_flags & RADV_PERFTEST_DFSM);
2714
2715 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
2716
2717 /* The maximum number of scratch waves. Scratch space isn't divided
2718 * evenly between CUs. The number is only a function of the number of CUs.
2719 * We can decrease the constant to decrease the scratch buffer size.
2720 *
2721 * sctx->scratch_waves must be >= the maximum possible size of
2722 * 1 threadgroup, so that the hw doesn't hang from being unable
2723 * to start any.
2724 *
2725 * The recommended value is 4 per CU at most. Higher numbers don't
2726 * bring much benefit, but they still occupy chip resources (think
2727 * async compute). I've seen ~2% performance difference between 4 and 32.
2728 */
2729 uint32_t max_threads_per_block = 2048;
2730 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
2731 max_threads_per_block / 64);
2732
2733 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
2734
2735 if (device->physical_device->rad_info.chip_class >= GFX7) {
2736 /* If the KMD allows it (there is a KMD hw register for it),
2737 * allow launching waves out-of-order.
2738 */
2739 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
2740 }
2741
2742 radv_device_init_gs_info(device);
2743
2744 device->tess_offchip_block_dw_size =
2745 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
2746
2747 if (getenv("RADV_TRACE_FILE")) {
2748 const char *filename = getenv("RADV_TRACE_FILE");
2749
2750 keep_shader_info = true;
2751
2752 if (!radv_init_trace(device))
2753 goto fail;
2754
2755 fprintf(stderr, "*****************************************************************************\n");
2756 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
2757 fprintf(stderr, "*****************************************************************************\n");
2758
2759 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
2760 radv_dump_enabled_options(device, stderr);
2761 }
2762
2763 int radv_thread_trace = radv_get_int_debug_option("RADV_THREAD_TRACE", -1);
2764 if (radv_thread_trace >= 0) {
2765 fprintf(stderr, "*************************************************\n");
2766 fprintf(stderr, "* WARNING: Thread trace support is experimental *\n");
2767 fprintf(stderr, "*************************************************\n");
2768
2769 if (device->physical_device->rad_info.chip_class < GFX8) {
2770 fprintf(stderr, "GPU hardware not supported: refer to "
2771 "the RGP documentation for the list of "
2772 "supported GPUs!\n");
2773 abort();
2774 }
2775
2776 /* Default buffer size set to 1MB per SE. */
2777 device->thread_trace_buffer_size =
2778 radv_get_int_debug_option("RADV_THREAD_TRACE_BUFFER_SIZE", 1024 * 1024);
2779 device->thread_trace_start_frame = radv_thread_trace;
2780
2781 if (!radv_thread_trace_init(device))
2782 goto fail;
2783 }
2784
2785 device->keep_shader_info = keep_shader_info;
2786 result = radv_device_init_meta(device);
2787 if (result != VK_SUCCESS)
2788 goto fail;
2789
2790 radv_device_init_msaa(device);
2791
2792 /* If the border color extension is enabled, let's create the buffer we need. */
2793 if (custom_border_colors) {
2794 result = radv_device_init_border_color(device);
2795 if (result != VK_SUCCESS)
2796 goto fail;
2797 }
2798
2799 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
2800 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
2801 if (!device->empty_cs[family])
2802 goto fail;
2803
2804 switch (family) {
2805 case RADV_QUEUE_GENERAL:
2806 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2807 radeon_emit(device->empty_cs[family], CC0_UPDATE_LOAD_ENABLES(1));
2808 radeon_emit(device->empty_cs[family], CC1_UPDATE_SHADOW_ENABLES(1));
2809 break;
2810 case RADV_QUEUE_COMPUTE:
2811 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
2812 radeon_emit(device->empty_cs[family], 0);
2813 break;
2814 }
2815
2816 result = device->ws->cs_finalize(device->empty_cs[family]);
2817 if (result != VK_SUCCESS)
2818 goto fail;
2819 }
2820
2821 if (device->physical_device->rad_info.chip_class >= GFX7)
2822 cik_create_gfx_config(device);
2823
2824 VkPipelineCacheCreateInfo ci;
2825 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
2826 ci.pNext = NULL;
2827 ci.flags = 0;
2828 ci.pInitialData = NULL;
2829 ci.initialDataSize = 0;
2830 VkPipelineCache pc;
2831 result = radv_CreatePipelineCache(radv_device_to_handle(device),
2832 &ci, NULL, &pc);
2833 if (result != VK_SUCCESS)
2834 goto fail_meta;
2835
2836 device->mem_cache = radv_pipeline_cache_from_handle(pc);
2837
2838 result = radv_create_pthread_cond(&device->timeline_cond);
2839 if (result != VK_SUCCESS)
2840 goto fail_mem_cache;
2841
2842 device->force_aniso =
2843 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
2844 if (device->force_aniso >= 0) {
2845 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
2846 1 << util_logbase2(device->force_aniso));
2847 }
2848
2849 *pDevice = radv_device_to_handle(device);
2850 return VK_SUCCESS;
2851
2852 fail_mem_cache:
2853 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2854 fail_meta:
2855 radv_device_finish_meta(device);
2856 fail:
2857 radv_bo_list_finish(&device->bo_list);
2858
2859 radv_thread_trace_finish(device);
2860
2861 if (device->trace_bo)
2862 device->ws->buffer_destroy(device->trace_bo);
2863
2864 if (device->gfx_init)
2865 device->ws->buffer_destroy(device->gfx_init);
2866
2867 radv_device_finish_border_color(device);
2868
2869 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2870 for (unsigned q = 0; q < device->queue_count[i]; q++)
2871 radv_queue_finish(&device->queues[i][q]);
2872 if (device->queue_count[i])
2873 vk_free(&device->vk.alloc, device->queues[i]);
2874 }
2875
2876 vk_free(&device->vk.alloc, device);
2877 return result;
2878 }
2879
2880 void radv_DestroyDevice(
2881 VkDevice _device,
2882 const VkAllocationCallbacks* pAllocator)
2883 {
2884 RADV_FROM_HANDLE(radv_device, device, _device);
2885
2886 if (!device)
2887 return;
2888
2889 if (device->trace_bo)
2890 device->ws->buffer_destroy(device->trace_bo);
2891
2892 if (device->gfx_init)
2893 device->ws->buffer_destroy(device->gfx_init);
2894
2895 radv_device_finish_border_color(device);
2896
2897 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2898 for (unsigned q = 0; q < device->queue_count[i]; q++)
2899 radv_queue_finish(&device->queues[i][q]);
2900 if (device->queue_count[i])
2901 vk_free(&device->vk.alloc, device->queues[i]);
2902 if (device->empty_cs[i])
2903 device->ws->cs_destroy(device->empty_cs[i]);
2904 }
2905 radv_device_finish_meta(device);
2906
2907 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
2908 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2909
2910 radv_destroy_shader_slabs(device);
2911
2912 pthread_cond_destroy(&device->timeline_cond);
2913 radv_bo_list_finish(&device->bo_list);
2914
2915 radv_thread_trace_finish(device);
2916
2917 vk_free(&device->vk.alloc, device);
2918 }
2919
2920 VkResult radv_EnumerateInstanceLayerProperties(
2921 uint32_t* pPropertyCount,
2922 VkLayerProperties* pProperties)
2923 {
2924 if (pProperties == NULL) {
2925 *pPropertyCount = 0;
2926 return VK_SUCCESS;
2927 }
2928
2929 /* None supported at this time */
2930 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2931 }
2932
2933 VkResult radv_EnumerateDeviceLayerProperties(
2934 VkPhysicalDevice physicalDevice,
2935 uint32_t* pPropertyCount,
2936 VkLayerProperties* pProperties)
2937 {
2938 if (pProperties == NULL) {
2939 *pPropertyCount = 0;
2940 return VK_SUCCESS;
2941 }
2942
2943 /* None supported at this time */
2944 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2945 }
2946
2947 void radv_GetDeviceQueue2(
2948 VkDevice _device,
2949 const VkDeviceQueueInfo2* pQueueInfo,
2950 VkQueue* pQueue)
2951 {
2952 RADV_FROM_HANDLE(radv_device, device, _device);
2953 struct radv_queue *queue;
2954
2955 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
2956 if (pQueueInfo->flags != queue->flags) {
2957 /* From the Vulkan 1.1.70 spec:
2958 *
2959 * "The queue returned by vkGetDeviceQueue2 must have the same
2960 * flags value from this structure as that used at device
2961 * creation time in a VkDeviceQueueCreateInfo instance. If no
2962 * matching flags were specified at device creation time then
2963 * pQueue will return VK_NULL_HANDLE."
2964 */
2965 *pQueue = VK_NULL_HANDLE;
2966 return;
2967 }
2968
2969 *pQueue = radv_queue_to_handle(queue);
2970 }
2971
2972 void radv_GetDeviceQueue(
2973 VkDevice _device,
2974 uint32_t queueFamilyIndex,
2975 uint32_t queueIndex,
2976 VkQueue* pQueue)
2977 {
2978 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
2979 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
2980 .queueFamilyIndex = queueFamilyIndex,
2981 .queueIndex = queueIndex
2982 };
2983
2984 radv_GetDeviceQueue2(_device, &info, pQueue);
2985 }
2986
2987 static void
2988 fill_geom_tess_rings(struct radv_queue *queue,
2989 uint32_t *map,
2990 bool add_sample_positions,
2991 uint32_t esgs_ring_size,
2992 struct radeon_winsys_bo *esgs_ring_bo,
2993 uint32_t gsvs_ring_size,
2994 struct radeon_winsys_bo *gsvs_ring_bo,
2995 uint32_t tess_factor_ring_size,
2996 uint32_t tess_offchip_ring_offset,
2997 uint32_t tess_offchip_ring_size,
2998 struct radeon_winsys_bo *tess_rings_bo)
2999 {
3000 uint32_t *desc = &map[4];
3001
3002 if (esgs_ring_bo) {
3003 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
3004
3005 /* stride 0, num records - size, add tid, swizzle, elsize4,
3006 index stride 64 */
3007 desc[0] = esgs_va;
3008 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
3009 S_008F04_SWIZZLE_ENABLE(true);
3010 desc[2] = esgs_ring_size;
3011 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3012 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3013 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3014 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
3015 S_008F0C_INDEX_STRIDE(3) |
3016 S_008F0C_ADD_TID_ENABLE(1);
3017
3018 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3019 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3020 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3021 S_008F0C_RESOURCE_LEVEL(1);
3022 } else {
3023 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3024 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
3025 S_008F0C_ELEMENT_SIZE(1);
3026 }
3027
3028 /* GS entry for ES->GS ring */
3029 /* stride 0, num records - size, elsize0,
3030 index stride 0 */
3031 desc[4] = esgs_va;
3032 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32);
3033 desc[6] = esgs_ring_size;
3034 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3035 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3036 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3037 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3038
3039 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3040 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3041 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3042 S_008F0C_RESOURCE_LEVEL(1);
3043 } else {
3044 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3045 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3046 }
3047 }
3048
3049 desc += 8;
3050
3051 if (gsvs_ring_bo) {
3052 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
3053
3054 /* VS entry for GS->VS ring */
3055 /* stride 0, num records - size, elsize0,
3056 index stride 0 */
3057 desc[0] = gsvs_va;
3058 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32);
3059 desc[2] = gsvs_ring_size;
3060 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3061 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3062 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3063 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3064
3065 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3066 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3067 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3068 S_008F0C_RESOURCE_LEVEL(1);
3069 } else {
3070 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3071 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3072 }
3073
3074 /* stride gsvs_itemsize, num records 64
3075 elsize 4, index stride 16 */
3076 /* shader will patch stride and desc[2] */
3077 desc[4] = gsvs_va;
3078 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32) |
3079 S_008F04_SWIZZLE_ENABLE(1);
3080 desc[6] = 0;
3081 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3082 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3083 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3084 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
3085 S_008F0C_INDEX_STRIDE(1) |
3086 S_008F0C_ADD_TID_ENABLE(true);
3087
3088 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3089 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3090 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3091 S_008F0C_RESOURCE_LEVEL(1);
3092 } else {
3093 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3094 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
3095 S_008F0C_ELEMENT_SIZE(1);
3096 }
3097
3098 }
3099
3100 desc += 8;
3101
3102 if (tess_rings_bo) {
3103 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
3104 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
3105
3106 desc[0] = tess_va;
3107 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32);
3108 desc[2] = tess_factor_ring_size;
3109 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3110 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3111 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3112 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3113
3114 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3115 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3116 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3117 S_008F0C_RESOURCE_LEVEL(1);
3118 } else {
3119 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3120 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3121 }
3122
3123 desc[4] = tess_offchip_va;
3124 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32);
3125 desc[6] = tess_offchip_ring_size;
3126 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3127 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3128 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3129 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3130
3131 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3132 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3133 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3134 S_008F0C_RESOURCE_LEVEL(1);
3135 } else {
3136 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3137 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3138 }
3139 }
3140
3141 desc += 8;
3142
3143 if (add_sample_positions) {
3144 /* add sample positions after all rings */
3145 memcpy(desc, queue->device->sample_locations_1x, 8);
3146 desc += 2;
3147 memcpy(desc, queue->device->sample_locations_2x, 16);
3148 desc += 4;
3149 memcpy(desc, queue->device->sample_locations_4x, 32);
3150 desc += 8;
3151 memcpy(desc, queue->device->sample_locations_8x, 64);
3152 }
3153 }
3154
3155 static unsigned
3156 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
3157 {
3158 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 &&
3159 device->physical_device->rad_info.family != CHIP_CARRIZO &&
3160 device->physical_device->rad_info.family != CHIP_STONEY;
3161 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
3162 unsigned max_offchip_buffers;
3163 unsigned offchip_granularity;
3164 unsigned hs_offchip_param;
3165
3166 /*
3167 * Per RadeonSI:
3168 * This must be one less than the maximum number due to a hw limitation.
3169 * Various hardware bugs need thGFX7
3170 *
3171 * Per AMDVLK:
3172 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
3173 * Gfx7 should limit max_offchip_buffers to 508
3174 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
3175 *
3176 * Follow AMDVLK here.
3177 */
3178 if (device->physical_device->rad_info.chip_class >= GFX10) {
3179 max_offchip_buffers_per_se = 256;
3180 } else if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
3181 device->physical_device->rad_info.chip_class == GFX7 ||
3182 device->physical_device->rad_info.chip_class == GFX6)
3183 --max_offchip_buffers_per_se;
3184
3185 max_offchip_buffers = max_offchip_buffers_per_se *
3186 device->physical_device->rad_info.max_se;
3187
3188 /* Hawaii has a bug with offchip buffers > 256 that can be worked
3189 * around by setting 4K granularity.
3190 */
3191 if (device->tess_offchip_block_dw_size == 4096) {
3192 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
3193 offchip_granularity = V_03093C_X_4K_DWORDS;
3194 } else {
3195 assert(device->tess_offchip_block_dw_size == 8192);
3196 offchip_granularity = V_03093C_X_8K_DWORDS;
3197 }
3198
3199 switch (device->physical_device->rad_info.chip_class) {
3200 case GFX6:
3201 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
3202 break;
3203 case GFX7:
3204 case GFX8:
3205 case GFX9:
3206 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
3207 break;
3208 case GFX10:
3209 break;
3210 default:
3211 break;
3212 }
3213
3214 *max_offchip_buffers_p = max_offchip_buffers;
3215 if (device->physical_device->rad_info.chip_class >= GFX10_3) {
3216 hs_offchip_param = S_03093C_OFFCHIP_BUFFERING_GFX103(max_offchip_buffers - 1) |
3217 S_03093C_OFFCHIP_GRANULARITY_GFX103(offchip_granularity);
3218 } else if (device->physical_device->rad_info.chip_class >= GFX7) {
3219 if (device->physical_device->rad_info.chip_class >= GFX8)
3220 --max_offchip_buffers;
3221 hs_offchip_param =
3222 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
3223 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
3224 } else {
3225 hs_offchip_param =
3226 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
3227 }
3228 return hs_offchip_param;
3229 }
3230
3231 static void
3232 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3233 struct radeon_winsys_bo *esgs_ring_bo,
3234 uint32_t esgs_ring_size,
3235 struct radeon_winsys_bo *gsvs_ring_bo,
3236 uint32_t gsvs_ring_size)
3237 {
3238 if (!esgs_ring_bo && !gsvs_ring_bo)
3239 return;
3240
3241 if (esgs_ring_bo)
3242 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
3243
3244 if (gsvs_ring_bo)
3245 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
3246
3247 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
3248 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
3249 radeon_emit(cs, esgs_ring_size >> 8);
3250 radeon_emit(cs, gsvs_ring_size >> 8);
3251 } else {
3252 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
3253 radeon_emit(cs, esgs_ring_size >> 8);
3254 radeon_emit(cs, gsvs_ring_size >> 8);
3255 }
3256 }
3257
3258 static void
3259 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3260 unsigned hs_offchip_param, unsigned tf_ring_size,
3261 struct radeon_winsys_bo *tess_rings_bo)
3262 {
3263 uint64_t tf_va;
3264
3265 if (!tess_rings_bo)
3266 return;
3267
3268 tf_va = radv_buffer_get_va(tess_rings_bo);
3269
3270 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
3271
3272 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
3273 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
3274 S_030938_SIZE(tf_ring_size / 4));
3275 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
3276 tf_va >> 8);
3277
3278 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3279 radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3280 S_030984_BASE_HI(tf_va >> 40));
3281 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
3282 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
3283 S_030944_BASE_HI(tf_va >> 40));
3284 }
3285 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
3286 hs_offchip_param);
3287 } else {
3288 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
3289 S_008988_SIZE(tf_ring_size / 4));
3290 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
3291 tf_va >> 8);
3292 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3293 hs_offchip_param);
3294 }
3295 }
3296
3297 static void
3298 radv_emit_graphics_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3299 uint32_t size_per_wave, uint32_t waves,
3300 struct radeon_winsys_bo *scratch_bo)
3301 {
3302 if (queue->queue_family_index != RADV_QUEUE_GENERAL)
3303 return;
3304
3305 if (!scratch_bo)
3306 return;
3307
3308 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
3309
3310 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
3311 S_0286E8_WAVES(waves) |
3312 S_0286E8_WAVESIZE(round_up_u32(size_per_wave, 1024)));
3313 }
3314
3315 static void
3316 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3317 uint32_t size_per_wave, uint32_t waves,
3318 struct radeon_winsys_bo *compute_scratch_bo)
3319 {
3320 uint64_t scratch_va;
3321
3322 if (!compute_scratch_bo)
3323 return;
3324
3325 scratch_va = radv_buffer_get_va(compute_scratch_bo);
3326
3327 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
3328
3329 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
3330 radeon_emit(cs, scratch_va);
3331 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
3332 S_008F04_SWIZZLE_ENABLE(1));
3333
3334 radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
3335 S_00B860_WAVES(waves) |
3336 S_00B860_WAVESIZE(round_up_u32(size_per_wave, 1024)));
3337 }
3338
3339 static void
3340 radv_emit_global_shader_pointers(struct radv_queue *queue,
3341 struct radeon_cmdbuf *cs,
3342 struct radeon_winsys_bo *descriptor_bo)
3343 {
3344 uint64_t va;
3345
3346 if (!descriptor_bo)
3347 return;
3348
3349 va = radv_buffer_get_va(descriptor_bo);
3350
3351 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
3352
3353 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3354 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3355 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3356 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
3357 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
3358
3359 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3360 radv_emit_shader_pointer(queue->device, cs, regs[i],
3361 va, true);
3362 }
3363 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
3364 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3365 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3366 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
3367 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
3368
3369 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3370 radv_emit_shader_pointer(queue->device, cs, regs[i],
3371 va, true);
3372 }
3373 } else {
3374 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3375 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3376 R_00B230_SPI_SHADER_USER_DATA_GS_0,
3377 R_00B330_SPI_SHADER_USER_DATA_ES_0,
3378 R_00B430_SPI_SHADER_USER_DATA_HS_0,
3379 R_00B530_SPI_SHADER_USER_DATA_LS_0};
3380
3381 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3382 radv_emit_shader_pointer(queue->device, cs, regs[i],
3383 va, true);
3384 }
3385 }
3386 }
3387
3388 static void
3389 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
3390 {
3391 struct radv_device *device = queue->device;
3392
3393 if (device->gfx_init) {
3394 uint64_t va = radv_buffer_get_va(device->gfx_init);
3395
3396 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
3397 radeon_emit(cs, va);
3398 radeon_emit(cs, va >> 32);
3399 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
3400
3401 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
3402 } else {
3403 si_emit_graphics(device, cs);
3404 }
3405 }
3406
3407 static void
3408 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
3409 {
3410 si_emit_compute(queue->device, cs);
3411 }
3412
3413 static VkResult
3414 radv_get_preamble_cs(struct radv_queue *queue,
3415 uint32_t scratch_size_per_wave,
3416 uint32_t scratch_waves,
3417 uint32_t compute_scratch_size_per_wave,
3418 uint32_t compute_scratch_waves,
3419 uint32_t esgs_ring_size,
3420 uint32_t gsvs_ring_size,
3421 bool needs_tess_rings,
3422 bool needs_gds,
3423 bool needs_gds_oa,
3424 bool needs_sample_positions,
3425 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
3426 struct radeon_cmdbuf **initial_preamble_cs,
3427 struct radeon_cmdbuf **continue_preamble_cs)
3428 {
3429 struct radeon_winsys_bo *scratch_bo = NULL;
3430 struct radeon_winsys_bo *descriptor_bo = NULL;
3431 struct radeon_winsys_bo *compute_scratch_bo = NULL;
3432 struct radeon_winsys_bo *esgs_ring_bo = NULL;
3433 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
3434 struct radeon_winsys_bo *tess_rings_bo = NULL;
3435 struct radeon_winsys_bo *gds_bo = NULL;
3436 struct radeon_winsys_bo *gds_oa_bo = NULL;
3437 struct radeon_cmdbuf *dest_cs[3] = {0};
3438 bool add_tess_rings = false, add_gds = false, add_gds_oa = false, add_sample_positions = false;
3439 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
3440 unsigned max_offchip_buffers;
3441 unsigned hs_offchip_param = 0;
3442 unsigned tess_offchip_ring_offset;
3443 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
3444 if (!queue->has_tess_rings) {
3445 if (needs_tess_rings)
3446 add_tess_rings = true;
3447 }
3448 if (!queue->has_gds) {
3449 if (needs_gds)
3450 add_gds = true;
3451 }
3452 if (!queue->has_gds_oa) {
3453 if (needs_gds_oa)
3454 add_gds_oa = true;
3455 }
3456 if (!queue->has_sample_positions) {
3457 if (needs_sample_positions)
3458 add_sample_positions = true;
3459 }
3460 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
3461 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
3462 &max_offchip_buffers);
3463 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
3464 tess_offchip_ring_size = max_offchip_buffers *
3465 queue->device->tess_offchip_block_dw_size * 4;
3466
3467 scratch_size_per_wave = MAX2(scratch_size_per_wave, queue->scratch_size_per_wave);
34