4dac1be049554c6bd02332548a983fcfae274c6d
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "dirent.h"
29 #include <errno.h>
30 #include <fcntl.h>
31 #include <linux/audit.h>
32 #include <linux/bpf.h>
33 #include <linux/filter.h>
34 #include <linux/seccomp.h>
35 #include <linux/unistd.h>
36 #include <stdatomic.h>
37 #include <stdbool.h>
38 #include <stddef.h>
39 #include <stdio.h>
40 #include <string.h>
41 #include <sys/prctl.h>
42 #include <sys/wait.h>
43 #include <unistd.h>
44 #include <fcntl.h>
45
46 #include "radv_debug.h"
47 #include "radv_private.h"
48 #include "radv_shader.h"
49 #include "radv_cs.h"
50 #include "util/disk_cache.h"
51 #include "vk_util.h"
52 #include <xf86drm.h>
53 #include <amdgpu.h>
54 #include "drm-uapi/amdgpu_drm.h"
55 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
56 #include "winsys/null/radv_null_winsys_public.h"
57 #include "ac_llvm_util.h"
58 #include "vk_format.h"
59 #include "sid.h"
60 #include "git_sha1.h"
61 #include "util/build_id.h"
62 #include "util/debug.h"
63 #include "util/mesa-sha1.h"
64 #include "util/timespec.h"
65 #include "util/u_atomic.h"
66 #include "compiler/glsl_types.h"
67 #include "util/driconf.h"
68
69 static struct radv_timeline_point *
70 radv_timeline_find_point_at_least_locked(struct radv_device *device,
71 struct radv_timeline *timeline,
72 uint64_t p);
73
74 static struct radv_timeline_point *
75 radv_timeline_add_point_locked(struct radv_device *device,
76 struct radv_timeline *timeline,
77 uint64_t p);
78
79 static void
80 radv_timeline_trigger_waiters_locked(struct radv_timeline *timeline,
81 struct list_head *processing_list);
82
83 static
84 void radv_destroy_semaphore_part(struct radv_device *device,
85 struct radv_semaphore_part *part);
86
87 static VkResult
88 radv_create_pthread_cond(pthread_cond_t *cond);
89
90 uint64_t radv_get_current_time(void)
91 {
92 struct timespec tv;
93 clock_gettime(CLOCK_MONOTONIC, &tv);
94 return tv.tv_nsec + tv.tv_sec*1000000000ull;
95 }
96
97 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
98 {
99 uint64_t current_time = radv_get_current_time();
100
101 timeout = MIN2(UINT64_MAX - current_time, timeout);
102
103 return current_time + timeout;
104 }
105
106 static int
107 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
108 {
109 struct mesa_sha1 ctx;
110 unsigned char sha1[20];
111 unsigned ptr_size = sizeof(void*);
112
113 memset(uuid, 0, VK_UUID_SIZE);
114 _mesa_sha1_init(&ctx);
115
116 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
117 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
118 return -1;
119
120 _mesa_sha1_update(&ctx, &family, sizeof(family));
121 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
122 _mesa_sha1_final(&ctx, sha1);
123
124 memcpy(uuid, sha1, VK_UUID_SIZE);
125 return 0;
126 }
127
128 static void
129 radv_get_driver_uuid(void *uuid)
130 {
131 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
132 }
133
134 static void
135 radv_get_device_uuid(struct radeon_info *info, void *uuid)
136 {
137 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
138 }
139
140 static uint64_t
141 radv_get_visible_vram_size(struct radv_physical_device *device)
142 {
143 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
144 }
145
146 static uint64_t
147 radv_get_vram_size(struct radv_physical_device *device)
148 {
149 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
150 }
151
152 static void
153 radv_physical_device_init_mem_types(struct radv_physical_device *device)
154 {
155 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
156 uint64_t vram_size = radv_get_vram_size(device);
157 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
158 device->memory_properties.memoryHeapCount = 0;
159 if (vram_size > 0) {
160 vram_index = device->memory_properties.memoryHeapCount++;
161 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
162 .size = vram_size,
163 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
164 };
165 }
166
167 if (device->rad_info.gart_size > 0) {
168 gart_index = device->memory_properties.memoryHeapCount++;
169 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
170 .size = device->rad_info.gart_size,
171 .flags = 0,
172 };
173 }
174
175 if (visible_vram_size) {
176 visible_vram_index = device->memory_properties.memoryHeapCount++;
177 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
178 .size = visible_vram_size,
179 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
180 };
181 }
182
183 unsigned type_count = 0;
184
185 if (vram_index >= 0 || visible_vram_index >= 0) {
186 device->memory_domains[type_count] = RADEON_DOMAIN_VRAM;
187 device->memory_flags[type_count] = RADEON_FLAG_NO_CPU_ACCESS;
188 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
189 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
190 .heapIndex = vram_index >= 0 ? vram_index : visible_vram_index,
191 };
192 }
193
194 if (gart_index >= 0) {
195 device->memory_domains[type_count] = RADEON_DOMAIN_GTT;
196 device->memory_flags[type_count] = RADEON_FLAG_GTT_WC | RADEON_FLAG_CPU_ACCESS;
197 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
198 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
199 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
200 .heapIndex = gart_index,
201 };
202 }
203 if (visible_vram_index >= 0) {
204 device->memory_domains[type_count] = RADEON_DOMAIN_VRAM;
205 device->memory_flags[type_count] = RADEON_FLAG_CPU_ACCESS;
206 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
207 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
208 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
209 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
210 .heapIndex = visible_vram_index,
211 };
212 }
213
214 if (gart_index >= 0) {
215 device->memory_domains[type_count] = RADEON_DOMAIN_GTT;
216 device->memory_flags[type_count] = RADEON_FLAG_CPU_ACCESS;
217 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
218 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
219 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
220 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
221 .heapIndex = gart_index,
222 };
223 }
224 device->memory_properties.memoryTypeCount = type_count;
225
226 if (device->rad_info.has_l2_uncached) {
227 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
228 VkMemoryType mem_type = device->memory_properties.memoryTypes[i];
229
230 if ((mem_type.propertyFlags & (VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
231 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT)) ||
232 mem_type.propertyFlags == VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT) {
233
234 VkMemoryPropertyFlags property_flags = mem_type.propertyFlags |
235 VK_MEMORY_PROPERTY_DEVICE_COHERENT_BIT_AMD |
236 VK_MEMORY_PROPERTY_DEVICE_UNCACHED_BIT_AMD;
237
238 device->memory_domains[type_count] = device->memory_domains[i];
239 device->memory_flags[type_count] = device->memory_flags[i] | RADEON_FLAG_VA_UNCACHED;
240 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
241 .propertyFlags = property_flags,
242 .heapIndex = mem_type.heapIndex,
243 };
244 }
245 }
246 device->memory_properties.memoryTypeCount = type_count;
247 }
248 }
249
250 static const char *
251 radv_get_compiler_string(struct radv_physical_device *pdevice)
252 {
253 if (!pdevice->use_llvm) {
254 /* Some games like SotTR apply shader workarounds if the LLVM
255 * version is too old or if the LLVM version string is
256 * missing. This gives 2-5% performance with SotTR and ACO.
257 */
258 if (driQueryOptionb(&pdevice->instance->dri_options,
259 "radv_report_llvm9_version_string")) {
260 return "ACO/LLVM 9.0.1";
261 }
262
263 return "ACO";
264 }
265
266 return "LLVM " MESA_LLVM_VERSION_STRING;
267 }
268
269 static VkResult
270 radv_physical_device_try_create(struct radv_instance *instance,
271 drmDevicePtr drm_device,
272 struct radv_physical_device **device_out)
273 {
274 VkResult result;
275 int fd = -1;
276 int master_fd = -1;
277
278 if (drm_device) {
279 const char *path = drm_device->nodes[DRM_NODE_RENDER];
280 drmVersionPtr version;
281
282 fd = open(path, O_RDWR | O_CLOEXEC);
283 if (fd < 0) {
284 if (instance->debug_flags & RADV_DEBUG_STARTUP)
285 radv_logi("Could not open device '%s'", path);
286
287 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
288 }
289
290 version = drmGetVersion(fd);
291 if (!version) {
292 close(fd);
293
294 if (instance->debug_flags & RADV_DEBUG_STARTUP)
295 radv_logi("Could not get the kernel driver version for device '%s'", path);
296
297 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
298 "failed to get version %s: %m", path);
299 }
300
301 if (strcmp(version->name, "amdgpu")) {
302 drmFreeVersion(version);
303 close(fd);
304
305 if (instance->debug_flags & RADV_DEBUG_STARTUP)
306 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
307
308 return VK_ERROR_INCOMPATIBLE_DRIVER;
309 }
310 drmFreeVersion(version);
311
312 if (instance->debug_flags & RADV_DEBUG_STARTUP)
313 radv_logi("Found compatible device '%s'.", path);
314 }
315
316 struct radv_physical_device *device =
317 vk_zalloc2(&instance->alloc, NULL, sizeof(*device), 8,
318 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
319 if (!device) {
320 result = vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
321 goto fail_fd;
322 }
323
324 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
325 device->instance = instance;
326
327 if (drm_device) {
328 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
329 instance->perftest_flags);
330 } else {
331 device->ws = radv_null_winsys_create();
332 }
333
334 if (!device->ws) {
335 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
336 "failed to initialize winsys");
337 goto fail_alloc;
338 }
339
340 if (drm_device && instance->enabled_extensions.KHR_display) {
341 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
342 if (master_fd >= 0) {
343 uint32_t accel_working = 0;
344 struct drm_amdgpu_info request = {
345 .return_pointer = (uintptr_t)&accel_working,
346 .return_size = sizeof(accel_working),
347 .query = AMDGPU_INFO_ACCEL_WORKING
348 };
349
350 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
351 close(master_fd);
352 master_fd = -1;
353 }
354 }
355 }
356
357 device->master_fd = master_fd;
358 device->local_fd = fd;
359 device->ws->query_info(device->ws, &device->rad_info);
360
361 device->use_llvm = instance->debug_flags & RADV_DEBUG_LLVM;
362
363 snprintf(device->name, sizeof(device->name),
364 "AMD RADV %s (%s)",
365 device->rad_info.name, radv_get_compiler_string(device));
366
367 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
368 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
369 "cannot generate UUID");
370 goto fail_wsi;
371 }
372
373 /* These flags affect shader compilation. */
374 uint64_t shader_env_flags = (device->use_llvm ? 0 : 0x2);
375
376 /* The gpu id is already embedded in the uuid so we just pass "radv"
377 * when creating the cache.
378 */
379 char buf[VK_UUID_SIZE * 2 + 1];
380 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
381 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
382
383 if (device->rad_info.chip_class < GFX8 || !device->use_llvm)
384 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
385
386 radv_get_driver_uuid(&device->driver_uuid);
387 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
388
389 device->out_of_order_rast_allowed = device->rad_info.has_out_of_order_rast &&
390 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
391
392 device->dcc_msaa_allowed =
393 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
394
395 device->use_ngg = device->rad_info.chip_class >= GFX10 &&
396 device->rad_info.family != CHIP_NAVI14 &&
397 !(device->instance->debug_flags & RADV_DEBUG_NO_NGG);
398
399 /* TODO: Implement NGG GS with ACO. */
400 device->use_ngg_gs = device->use_ngg && device->use_llvm;
401 device->use_ngg_streamout = false;
402
403 /* Determine the number of threads per wave for all stages. */
404 device->cs_wave_size = 64;
405 device->ps_wave_size = 64;
406 device->ge_wave_size = 64;
407
408 if (device->rad_info.chip_class >= GFX10) {
409 if (device->instance->perftest_flags & RADV_PERFTEST_CS_WAVE_32)
410 device->cs_wave_size = 32;
411
412 /* For pixel shaders, wave64 is recommanded. */
413 if (device->instance->perftest_flags & RADV_PERFTEST_PS_WAVE_32)
414 device->ps_wave_size = 32;
415
416 if (device->instance->perftest_flags & RADV_PERFTEST_GE_WAVE_32)
417 device->ge_wave_size = 32;
418 }
419
420 radv_physical_device_init_mem_types(device);
421
422 radv_physical_device_get_supported_extensions(device,
423 &device->supported_extensions);
424
425 if (drm_device)
426 device->bus_info = *drm_device->businfo.pci;
427
428 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
429 ac_print_gpu_info(&device->rad_info);
430
431 /* The WSI is structured as a layer on top of the driver, so this has
432 * to be the last part of initialization (at least until we get other
433 * semi-layers).
434 */
435 result = radv_init_wsi(device);
436 if (result != VK_SUCCESS) {
437 vk_error(instance, result);
438 goto fail_disk_cache;
439 }
440
441 *device_out = device;
442
443 return VK_SUCCESS;
444
445 fail_disk_cache:
446 disk_cache_destroy(device->disk_cache);
447 fail_wsi:
448 device->ws->destroy(device->ws);
449 fail_alloc:
450 vk_free(&instance->alloc, device);
451 fail_fd:
452 if (fd != -1)
453 close(fd);
454 if (master_fd != -1)
455 close(master_fd);
456 return result;
457 }
458
459 static void
460 radv_physical_device_destroy(struct radv_physical_device *device)
461 {
462 radv_finish_wsi(device);
463 device->ws->destroy(device->ws);
464 disk_cache_destroy(device->disk_cache);
465 close(device->local_fd);
466 if (device->master_fd != -1)
467 close(device->master_fd);
468 vk_free(&device->instance->alloc, device);
469 }
470
471 static void *
472 default_alloc_func(void *pUserData, size_t size, size_t align,
473 VkSystemAllocationScope allocationScope)
474 {
475 return malloc(size);
476 }
477
478 static void *
479 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
480 size_t align, VkSystemAllocationScope allocationScope)
481 {
482 return realloc(pOriginal, size);
483 }
484
485 static void
486 default_free_func(void *pUserData, void *pMemory)
487 {
488 free(pMemory);
489 }
490
491 static const VkAllocationCallbacks default_alloc = {
492 .pUserData = NULL,
493 .pfnAllocation = default_alloc_func,
494 .pfnReallocation = default_realloc_func,
495 .pfnFree = default_free_func,
496 };
497
498 static const struct debug_control radv_debug_options[] = {
499 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
500 {"nodcc", RADV_DEBUG_NO_DCC},
501 {"shaders", RADV_DEBUG_DUMP_SHADERS},
502 {"nocache", RADV_DEBUG_NO_CACHE},
503 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
504 {"nohiz", RADV_DEBUG_NO_HIZ},
505 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
506 {"allbos", RADV_DEBUG_ALL_BOS},
507 {"noibs", RADV_DEBUG_NO_IBS},
508 {"spirv", RADV_DEBUG_DUMP_SPIRV},
509 {"vmfaults", RADV_DEBUG_VM_FAULTS},
510 {"zerovram", RADV_DEBUG_ZERO_VRAM},
511 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
512 {"preoptir", RADV_DEBUG_PREOPTIR},
513 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
514 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
515 {"info", RADV_DEBUG_INFO},
516 {"errors", RADV_DEBUG_ERRORS},
517 {"startup", RADV_DEBUG_STARTUP},
518 {"checkir", RADV_DEBUG_CHECKIR},
519 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
520 {"nobinning", RADV_DEBUG_NOBINNING},
521 {"nongg", RADV_DEBUG_NO_NGG},
522 {"allentrypoints", RADV_DEBUG_ALL_ENTRYPOINTS},
523 {"metashaders", RADV_DEBUG_DUMP_META_SHADERS},
524 {"nomemorycache", RADV_DEBUG_NO_MEMORY_CACHE},
525 {"llvm", RADV_DEBUG_LLVM},
526 {NULL, 0}
527 };
528
529 const char *
530 radv_get_debug_option_name(int id)
531 {
532 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
533 return radv_debug_options[id].string;
534 }
535
536 static const struct debug_control radv_perftest_options[] = {
537 {"localbos", RADV_PERFTEST_LOCAL_BOS},
538 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
539 {"bolist", RADV_PERFTEST_BO_LIST},
540 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
541 {"cswave32", RADV_PERFTEST_CS_WAVE_32},
542 {"pswave32", RADV_PERFTEST_PS_WAVE_32},
543 {"gewave32", RADV_PERFTEST_GE_WAVE_32},
544 {"dfsm", RADV_PERFTEST_DFSM},
545 {NULL, 0}
546 };
547
548 const char *
549 radv_get_perftest_option_name(int id)
550 {
551 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
552 return radv_perftest_options[id].string;
553 }
554
555 static void
556 radv_handle_per_app_options(struct radv_instance *instance,
557 const VkApplicationInfo *info)
558 {
559 const char *name = info ? info->pApplicationName : NULL;
560 const char *engine_name = info ? info->pEngineName : NULL;
561
562 if (name) {
563 if (!strcmp(name, "DOOM_VFR")) {
564 /* Work around a Doom VFR game bug */
565 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
566 } else if (!strcmp(name, "Fledge")) {
567 /*
568 * Zero VRAM for "The Surge 2"
569 *
570 * This avoid a hang when when rendering any level. Likely
571 * uninitialized data in an indirect draw.
572 */
573 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
574 } else if (!strcmp(name, "No Man's Sky")) {
575 /* Work around a NMS game bug */
576 instance->debug_flags |= RADV_DEBUG_DISCARD_TO_DEMOTE;
577 } else if (!strcmp(name, "DOOMEternal")) {
578 /* Zero VRAM for Doom Eternal to fix rendering issues. */
579 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
580 } else if (!strcmp(name, "Red Dead Redemption 2")) {
581 /* Work around a RDR2 game bug */
582 instance->debug_flags |= RADV_DEBUG_DISCARD_TO_DEMOTE;
583 }
584 }
585
586 if (engine_name) {
587 if (!strcmp(engine_name, "vkd3d")) {
588 /* Zero VRAM for all VKD3D (DX12->VK) games to fix
589 * rendering issues.
590 */
591 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
592 } else if (!strcmp(engine_name, "Quantic Dream Engine")) {
593 /* Fix various artifacts in Detroit: Become Human */
594 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM |
595 RADV_DEBUG_DISCARD_TO_DEMOTE;
596 }
597 }
598
599 instance->enable_mrt_output_nan_fixup =
600 driQueryOptionb(&instance->dri_options,
601 "radv_enable_mrt_output_nan_fixup");
602
603 if (driQueryOptionb(&instance->dri_options, "radv_no_dynamic_bounds"))
604 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
605 }
606
607 static const char radv_dri_options_xml[] =
608 DRI_CONF_BEGIN
609 DRI_CONF_SECTION_PERFORMANCE
610 DRI_CONF_ADAPTIVE_SYNC("true")
611 DRI_CONF_VK_X11_OVERRIDE_MIN_IMAGE_COUNT(0)
612 DRI_CONF_VK_X11_STRICT_IMAGE_COUNT("false")
613 DRI_CONF_VK_X11_ENSURE_MIN_IMAGE_COUNT("false")
614 DRI_CONF_RADV_REPORT_LLVM9_VERSION_STRING("false")
615 DRI_CONF_RADV_ENABLE_MRT_OUTPUT_NAN_FIXUP("false")
616 DRI_CONF_RADV_NO_DYNAMIC_BOUNDS("false")
617 DRI_CONF_SECTION_END
618
619 DRI_CONF_SECTION_DEBUG
620 DRI_CONF_VK_WSI_FORCE_BGRA8_UNORM_FIRST("false")
621 DRI_CONF_SECTION_END
622 DRI_CONF_END;
623
624 static void radv_init_dri_options(struct radv_instance *instance)
625 {
626 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
627 driParseConfigFiles(&instance->dri_options,
628 &instance->available_dri_options,
629 0, "radv", NULL,
630 instance->engineName,
631 instance->engineVersion);
632 }
633
634 VkResult radv_CreateInstance(
635 const VkInstanceCreateInfo* pCreateInfo,
636 const VkAllocationCallbacks* pAllocator,
637 VkInstance* pInstance)
638 {
639 struct radv_instance *instance;
640 VkResult result;
641
642 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
643 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
644 if (!instance)
645 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
646
647 vk_object_base_init(NULL, &instance->base, VK_OBJECT_TYPE_INSTANCE);
648
649 if (pAllocator)
650 instance->alloc = *pAllocator;
651 else
652 instance->alloc = default_alloc;
653
654 if (pCreateInfo->pApplicationInfo) {
655 const VkApplicationInfo *app = pCreateInfo->pApplicationInfo;
656
657 instance->engineName =
658 vk_strdup(&instance->alloc, app->pEngineName,
659 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
660 instance->engineVersion = app->engineVersion;
661 instance->apiVersion = app->apiVersion;
662 }
663
664 if (instance->apiVersion == 0)
665 instance->apiVersion = VK_API_VERSION_1_0;
666
667 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
668 radv_debug_options);
669
670 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
671 radv_perftest_options);
672
673 if (instance->debug_flags & RADV_DEBUG_STARTUP)
674 radv_logi("Created an instance");
675
676 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
677 int idx;
678 for (idx = 0; idx < RADV_INSTANCE_EXTENSION_COUNT; idx++) {
679 if (!strcmp(pCreateInfo->ppEnabledExtensionNames[i],
680 radv_instance_extensions[idx].extensionName))
681 break;
682 }
683
684 if (idx >= RADV_INSTANCE_EXTENSION_COUNT ||
685 !radv_instance_extensions_supported.extensions[idx]) {
686 vk_object_base_finish(&instance->base);
687 vk_free2(&default_alloc, pAllocator, instance);
688 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
689 }
690
691 instance->enabled_extensions.extensions[idx] = true;
692 }
693
694 bool unchecked = instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS;
695
696 for (unsigned i = 0; i < ARRAY_SIZE(instance->dispatch.entrypoints); i++) {
697 /* Vulkan requires that entrypoints for extensions which have
698 * not been enabled must not be advertised.
699 */
700 if (!unchecked &&
701 !radv_instance_entrypoint_is_enabled(i, instance->apiVersion,
702 &instance->enabled_extensions)) {
703 instance->dispatch.entrypoints[i] = NULL;
704 } else {
705 instance->dispatch.entrypoints[i] =
706 radv_instance_dispatch_table.entrypoints[i];
707 }
708 }
709
710 for (unsigned i = 0; i < ARRAY_SIZE(instance->physical_device_dispatch.entrypoints); i++) {
711 /* Vulkan requires that entrypoints for extensions which have
712 * not been enabled must not be advertised.
713 */
714 if (!unchecked &&
715 !radv_physical_device_entrypoint_is_enabled(i, instance->apiVersion,
716 &instance->enabled_extensions)) {
717 instance->physical_device_dispatch.entrypoints[i] = NULL;
718 } else {
719 instance->physical_device_dispatch.entrypoints[i] =
720 radv_physical_device_dispatch_table.entrypoints[i];
721 }
722 }
723
724 for (unsigned i = 0; i < ARRAY_SIZE(instance->device_dispatch.entrypoints); i++) {
725 /* Vulkan requires that entrypoints for extensions which have
726 * not been enabled must not be advertised.
727 */
728 if (!unchecked &&
729 !radv_device_entrypoint_is_enabled(i, instance->apiVersion,
730 &instance->enabled_extensions, NULL)) {
731 instance->device_dispatch.entrypoints[i] = NULL;
732 } else {
733 instance->device_dispatch.entrypoints[i] =
734 radv_device_dispatch_table.entrypoints[i];
735 }
736 }
737
738 instance->physical_devices_enumerated = false;
739 list_inithead(&instance->physical_devices);
740
741 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
742 if (result != VK_SUCCESS) {
743 vk_object_base_finish(&instance->base);
744 vk_free2(&default_alloc, pAllocator, instance);
745 return vk_error(instance, result);
746 }
747
748 glsl_type_singleton_init_or_ref();
749
750 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
751
752 radv_init_dri_options(instance);
753 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
754
755 *pInstance = radv_instance_to_handle(instance);
756
757 return VK_SUCCESS;
758 }
759
760 void radv_DestroyInstance(
761 VkInstance _instance,
762 const VkAllocationCallbacks* pAllocator)
763 {
764 RADV_FROM_HANDLE(radv_instance, instance, _instance);
765
766 if (!instance)
767 return;
768
769 list_for_each_entry_safe(struct radv_physical_device, pdevice,
770 &instance->physical_devices, link) {
771 radv_physical_device_destroy(pdevice);
772 }
773
774 vk_free(&instance->alloc, instance->engineName);
775
776 VG(VALGRIND_DESTROY_MEMPOOL(instance));
777
778 glsl_type_singleton_decref();
779
780 driDestroyOptionCache(&instance->dri_options);
781 driDestroyOptionInfo(&instance->available_dri_options);
782
783 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
784
785 vk_object_base_finish(&instance->base);
786 vk_free(&instance->alloc, instance);
787 }
788
789 static VkResult
790 radv_enumerate_physical_devices(struct radv_instance *instance)
791 {
792 if (instance->physical_devices_enumerated)
793 return VK_SUCCESS;
794
795 instance->physical_devices_enumerated = true;
796
797 /* TODO: Check for more devices ? */
798 drmDevicePtr devices[8];
799 VkResult result = VK_SUCCESS;
800 int max_devices;
801
802 if (getenv("RADV_FORCE_FAMILY")) {
803 /* When RADV_FORCE_FAMILY is set, the driver creates a nul
804 * device that allows to test the compiler without having an
805 * AMDGPU instance.
806 */
807 struct radv_physical_device *pdevice;
808
809 result = radv_physical_device_try_create(instance, NULL, &pdevice);
810 if (result != VK_SUCCESS)
811 return result;
812
813 list_addtail(&pdevice->link, &instance->physical_devices);
814 return VK_SUCCESS;
815 }
816
817 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
818
819 if (instance->debug_flags & RADV_DEBUG_STARTUP)
820 radv_logi("Found %d drm nodes", max_devices);
821
822 if (max_devices < 1)
823 return vk_error(instance, VK_SUCCESS);
824
825 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
826 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
827 devices[i]->bustype == DRM_BUS_PCI &&
828 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
829
830 struct radv_physical_device *pdevice;
831 result = radv_physical_device_try_create(instance, devices[i],
832 &pdevice);
833 /* Incompatible DRM device, skip. */
834 if (result == VK_ERROR_INCOMPATIBLE_DRIVER) {
835 result = VK_SUCCESS;
836 continue;
837 }
838
839 /* Error creating the physical device, report the error. */
840 if (result != VK_SUCCESS)
841 break;
842
843 list_addtail(&pdevice->link, &instance->physical_devices);
844 }
845 }
846 drmFreeDevices(devices, max_devices);
847
848 /* If we successfully enumerated any devices, call it success */
849 return result;
850 }
851
852 VkResult radv_EnumeratePhysicalDevices(
853 VkInstance _instance,
854 uint32_t* pPhysicalDeviceCount,
855 VkPhysicalDevice* pPhysicalDevices)
856 {
857 RADV_FROM_HANDLE(radv_instance, instance, _instance);
858 VK_OUTARRAY_MAKE(out, pPhysicalDevices, pPhysicalDeviceCount);
859
860 VkResult result = radv_enumerate_physical_devices(instance);
861 if (result != VK_SUCCESS)
862 return result;
863
864 list_for_each_entry(struct radv_physical_device, pdevice,
865 &instance->physical_devices, link) {
866 vk_outarray_append(&out, i) {
867 *i = radv_physical_device_to_handle(pdevice);
868 }
869 }
870
871 return vk_outarray_status(&out);
872 }
873
874 VkResult radv_EnumeratePhysicalDeviceGroups(
875 VkInstance _instance,
876 uint32_t* pPhysicalDeviceGroupCount,
877 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
878 {
879 RADV_FROM_HANDLE(radv_instance, instance, _instance);
880 VK_OUTARRAY_MAKE(out, pPhysicalDeviceGroupProperties,
881 pPhysicalDeviceGroupCount);
882
883 VkResult result = radv_enumerate_physical_devices(instance);
884 if (result != VK_SUCCESS)
885 return result;
886
887 list_for_each_entry(struct radv_physical_device, pdevice,
888 &instance->physical_devices, link) {
889 vk_outarray_append(&out, p) {
890 p->physicalDeviceCount = 1;
891 memset(p->physicalDevices, 0, sizeof(p->physicalDevices));
892 p->physicalDevices[0] = radv_physical_device_to_handle(pdevice);
893 p->subsetAllocation = false;
894 }
895 }
896
897 return vk_outarray_status(&out);
898 }
899
900 void radv_GetPhysicalDeviceFeatures(
901 VkPhysicalDevice physicalDevice,
902 VkPhysicalDeviceFeatures* pFeatures)
903 {
904 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
905 memset(pFeatures, 0, sizeof(*pFeatures));
906
907 *pFeatures = (VkPhysicalDeviceFeatures) {
908 .robustBufferAccess = true,
909 .fullDrawIndexUint32 = true,
910 .imageCubeArray = true,
911 .independentBlend = true,
912 .geometryShader = true,
913 .tessellationShader = true,
914 .sampleRateShading = true,
915 .dualSrcBlend = true,
916 .logicOp = true,
917 .multiDrawIndirect = true,
918 .drawIndirectFirstInstance = true,
919 .depthClamp = true,
920 .depthBiasClamp = true,
921 .fillModeNonSolid = true,
922 .depthBounds = true,
923 .wideLines = true,
924 .largePoints = true,
925 .alphaToOne = true,
926 .multiViewport = true,
927 .samplerAnisotropy = true,
928 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
929 .textureCompressionASTC_LDR = false,
930 .textureCompressionBC = true,
931 .occlusionQueryPrecise = true,
932 .pipelineStatisticsQuery = true,
933 .vertexPipelineStoresAndAtomics = true,
934 .fragmentStoresAndAtomics = true,
935 .shaderTessellationAndGeometryPointSize = true,
936 .shaderImageGatherExtended = true,
937 .shaderStorageImageExtendedFormats = true,
938 .shaderStorageImageMultisample = true,
939 .shaderUniformBufferArrayDynamicIndexing = true,
940 .shaderSampledImageArrayDynamicIndexing = true,
941 .shaderStorageBufferArrayDynamicIndexing = true,
942 .shaderStorageImageArrayDynamicIndexing = true,
943 .shaderStorageImageReadWithoutFormat = true,
944 .shaderStorageImageWriteWithoutFormat = true,
945 .shaderClipDistance = true,
946 .shaderCullDistance = true,
947 .shaderFloat64 = true,
948 .shaderInt64 = true,
949 .shaderInt16 = true,
950 .sparseBinding = true,
951 .variableMultisampleRate = true,
952 .shaderResourceMinLod = true,
953 .inheritedQueries = true,
954 };
955 }
956
957 static void
958 radv_get_physical_device_features_1_1(struct radv_physical_device *pdevice,
959 VkPhysicalDeviceVulkan11Features *f)
960 {
961 assert(f->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES);
962
963 f->storageBuffer16BitAccess = true;
964 f->uniformAndStorageBuffer16BitAccess = true;
965 f->storagePushConstant16 = true;
966 f->storageInputOutput16 = pdevice->rad_info.has_packed_math_16bit && (LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm);
967 f->multiview = true;
968 f->multiviewGeometryShader = true;
969 f->multiviewTessellationShader = true;
970 f->variablePointersStorageBuffer = true;
971 f->variablePointers = true;
972 f->protectedMemory = false;
973 f->samplerYcbcrConversion = true;
974 f->shaderDrawParameters = true;
975 }
976
977 static void
978 radv_get_physical_device_features_1_2(struct radv_physical_device *pdevice,
979 VkPhysicalDeviceVulkan12Features *f)
980 {
981 assert(f->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES);
982
983 f->samplerMirrorClampToEdge = true;
984 f->drawIndirectCount = true;
985 f->storageBuffer8BitAccess = true;
986 f->uniformAndStorageBuffer8BitAccess = true;
987 f->storagePushConstant8 = true;
988 f->shaderBufferInt64Atomics = LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm;
989 f->shaderSharedInt64Atomics = LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm;
990 f->shaderFloat16 = pdevice->rad_info.has_packed_math_16bit;
991 f->shaderInt8 = true;
992
993 f->descriptorIndexing = true;
994 f->shaderInputAttachmentArrayDynamicIndexing = true;
995 f->shaderUniformTexelBufferArrayDynamicIndexing = true;
996 f->shaderStorageTexelBufferArrayDynamicIndexing = true;
997 f->shaderUniformBufferArrayNonUniformIndexing = true;
998 f->shaderSampledImageArrayNonUniformIndexing = true;
999 f->shaderStorageBufferArrayNonUniformIndexing = true;
1000 f->shaderStorageImageArrayNonUniformIndexing = true;
1001 f->shaderInputAttachmentArrayNonUniformIndexing = true;
1002 f->shaderUniformTexelBufferArrayNonUniformIndexing = true;
1003 f->shaderStorageTexelBufferArrayNonUniformIndexing = true;
1004 f->descriptorBindingUniformBufferUpdateAfterBind = true;
1005 f->descriptorBindingSampledImageUpdateAfterBind = true;
1006 f->descriptorBindingStorageImageUpdateAfterBind = true;
1007 f->descriptorBindingStorageBufferUpdateAfterBind = true;
1008 f->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
1009 f->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
1010 f->descriptorBindingUpdateUnusedWhilePending = true;
1011 f->descriptorBindingPartiallyBound = true;
1012 f->descriptorBindingVariableDescriptorCount = true;
1013 f->runtimeDescriptorArray = true;
1014
1015 f->samplerFilterMinmax = true;
1016 f->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
1017 f->imagelessFramebuffer = true;
1018 f->uniformBufferStandardLayout = true;
1019 f->shaderSubgroupExtendedTypes = true;
1020 f->separateDepthStencilLayouts = true;
1021 f->hostQueryReset = true;
1022 f->timelineSemaphore = pdevice->rad_info.has_syncobj_wait_for_submit;
1023 f->bufferDeviceAddress = true;
1024 f->bufferDeviceAddressCaptureReplay = false;
1025 f->bufferDeviceAddressMultiDevice = false;
1026 f->vulkanMemoryModel = false;
1027 f->vulkanMemoryModelDeviceScope = false;
1028 f->vulkanMemoryModelAvailabilityVisibilityChains = false;
1029 f->shaderOutputViewportIndex = true;
1030 f->shaderOutputLayer = true;
1031 f->subgroupBroadcastDynamicId = true;
1032 }
1033
1034 void radv_GetPhysicalDeviceFeatures2(
1035 VkPhysicalDevice physicalDevice,
1036 VkPhysicalDeviceFeatures2 *pFeatures)
1037 {
1038 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1039 radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
1040
1041 VkPhysicalDeviceVulkan11Features core_1_1 = {
1042 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES,
1043 };
1044 radv_get_physical_device_features_1_1(pdevice, &core_1_1);
1045
1046 VkPhysicalDeviceVulkan12Features core_1_2 = {
1047 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES,
1048 };
1049 radv_get_physical_device_features_1_2(pdevice, &core_1_2);
1050
1051 #define CORE_FEATURE(major, minor, feature) \
1052 features->feature = core_##major##_##minor.feature
1053
1054 vk_foreach_struct(ext, pFeatures->pNext) {
1055 switch (ext->sType) {
1056 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
1057 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
1058 CORE_FEATURE(1, 1, variablePointersStorageBuffer);
1059 CORE_FEATURE(1, 1, variablePointers);
1060 break;
1061 }
1062 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
1063 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
1064 CORE_FEATURE(1, 1, multiview);
1065 CORE_FEATURE(1, 1, multiviewGeometryShader);
1066 CORE_FEATURE(1, 1, multiviewTessellationShader);
1067 break;
1068 }
1069 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
1070 VkPhysicalDeviceShaderDrawParametersFeatures *features =
1071 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
1072 CORE_FEATURE(1, 1, shaderDrawParameters);
1073 break;
1074 }
1075 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
1076 VkPhysicalDeviceProtectedMemoryFeatures *features =
1077 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
1078 CORE_FEATURE(1, 1, protectedMemory);
1079 break;
1080 }
1081 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
1082 VkPhysicalDevice16BitStorageFeatures *features =
1083 (VkPhysicalDevice16BitStorageFeatures*)ext;
1084 CORE_FEATURE(1, 1, storageBuffer16BitAccess);
1085 CORE_FEATURE(1, 1, uniformAndStorageBuffer16BitAccess);
1086 CORE_FEATURE(1, 1, storagePushConstant16);
1087 CORE_FEATURE(1, 1, storageInputOutput16);
1088 break;
1089 }
1090 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
1091 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
1092 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
1093 CORE_FEATURE(1, 1, samplerYcbcrConversion);
1094 break;
1095 }
1096 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES: {
1097 VkPhysicalDeviceDescriptorIndexingFeatures *features =
1098 (VkPhysicalDeviceDescriptorIndexingFeatures*)ext;
1099 CORE_FEATURE(1, 2, shaderInputAttachmentArrayDynamicIndexing);
1100 CORE_FEATURE(1, 2, shaderUniformTexelBufferArrayDynamicIndexing);
1101 CORE_FEATURE(1, 2, shaderStorageTexelBufferArrayDynamicIndexing);
1102 CORE_FEATURE(1, 2, shaderUniformBufferArrayNonUniformIndexing);
1103 CORE_FEATURE(1, 2, shaderSampledImageArrayNonUniformIndexing);
1104 CORE_FEATURE(1, 2, shaderStorageBufferArrayNonUniformIndexing);
1105 CORE_FEATURE(1, 2, shaderStorageImageArrayNonUniformIndexing);
1106 CORE_FEATURE(1, 2, shaderInputAttachmentArrayNonUniformIndexing);
1107 CORE_FEATURE(1, 2, shaderUniformTexelBufferArrayNonUniformIndexing);
1108 CORE_FEATURE(1, 2, shaderStorageTexelBufferArrayNonUniformIndexing);
1109 CORE_FEATURE(1, 2, descriptorBindingUniformBufferUpdateAfterBind);
1110 CORE_FEATURE(1, 2, descriptorBindingSampledImageUpdateAfterBind);
1111 CORE_FEATURE(1, 2, descriptorBindingStorageImageUpdateAfterBind);
1112 CORE_FEATURE(1, 2, descriptorBindingStorageBufferUpdateAfterBind);
1113 CORE_FEATURE(1, 2, descriptorBindingUniformTexelBufferUpdateAfterBind);
1114 CORE_FEATURE(1, 2, descriptorBindingStorageTexelBufferUpdateAfterBind);
1115 CORE_FEATURE(1, 2, descriptorBindingUpdateUnusedWhilePending);
1116 CORE_FEATURE(1, 2, descriptorBindingPartiallyBound);
1117 CORE_FEATURE(1, 2, descriptorBindingVariableDescriptorCount);
1118 CORE_FEATURE(1, 2, runtimeDescriptorArray);
1119 break;
1120 }
1121 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
1122 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
1123 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
1124 features->conditionalRendering = true;
1125 features->inheritedConditionalRendering = false;
1126 break;
1127 }
1128 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
1129 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
1130 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
1131 features->vertexAttributeInstanceRateDivisor = true;
1132 features->vertexAttributeInstanceRateZeroDivisor = true;
1133 break;
1134 }
1135 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
1136 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
1137 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
1138 features->transformFeedback = true;
1139 features->geometryStreams = !pdevice->use_ngg_streamout;
1140 break;
1141 }
1142 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES: {
1143 VkPhysicalDeviceScalarBlockLayoutFeatures *features =
1144 (VkPhysicalDeviceScalarBlockLayoutFeatures *)ext;
1145 CORE_FEATURE(1, 2, scalarBlockLayout);
1146 break;
1147 }
1148 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
1149 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
1150 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
1151 features->memoryPriority = true;
1152 break;
1153 }
1154 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
1155 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
1156 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
1157 features->bufferDeviceAddress = true;
1158 features->bufferDeviceAddressCaptureReplay = false;
1159 features->bufferDeviceAddressMultiDevice = false;
1160 break;
1161 }
1162 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES: {
1163 VkPhysicalDeviceBufferDeviceAddressFeatures *features =
1164 (VkPhysicalDeviceBufferDeviceAddressFeatures *)ext;
1165 CORE_FEATURE(1, 2, bufferDeviceAddress);
1166 CORE_FEATURE(1, 2, bufferDeviceAddressCaptureReplay);
1167 CORE_FEATURE(1, 2, bufferDeviceAddressMultiDevice);
1168 break;
1169 }
1170 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
1171 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
1172 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
1173 features->depthClipEnable = true;
1174 break;
1175 }
1176 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES: {
1177 VkPhysicalDeviceHostQueryResetFeatures *features =
1178 (VkPhysicalDeviceHostQueryResetFeatures *)ext;
1179 CORE_FEATURE(1, 2, hostQueryReset);
1180 break;
1181 }
1182 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES: {
1183 VkPhysicalDevice8BitStorageFeatures *features =
1184 (VkPhysicalDevice8BitStorageFeatures *)ext;
1185 CORE_FEATURE(1, 2, storageBuffer8BitAccess);
1186 CORE_FEATURE(1, 2, uniformAndStorageBuffer8BitAccess);
1187 CORE_FEATURE(1, 2, storagePushConstant8);
1188 break;
1189 }
1190 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_FLOAT16_INT8_FEATURES: {
1191 VkPhysicalDeviceShaderFloat16Int8Features *features =
1192 (VkPhysicalDeviceShaderFloat16Int8Features*)ext;
1193 CORE_FEATURE(1, 2, shaderFloat16);
1194 CORE_FEATURE(1, 2, shaderInt8);
1195 break;
1196 }
1197 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES: {
1198 VkPhysicalDeviceShaderAtomicInt64Features *features =
1199 (VkPhysicalDeviceShaderAtomicInt64Features *)ext;
1200 CORE_FEATURE(1, 2, shaderBufferInt64Atomics);
1201 CORE_FEATURE(1, 2, shaderSharedInt64Atomics);
1202 break;
1203 }
1204 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DEMOTE_TO_HELPER_INVOCATION_FEATURES_EXT: {
1205 VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT *features =
1206 (VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT *)ext;
1207 features->shaderDemoteToHelperInvocation = LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm;
1208 break;
1209 }
1210 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
1211 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
1212 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
1213
1214 features->inlineUniformBlock = true;
1215 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
1216 break;
1217 }
1218 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
1219 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
1220 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
1221 features->computeDerivativeGroupQuads = false;
1222 features->computeDerivativeGroupLinear = true;
1223 break;
1224 }
1225 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
1226 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
1227 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
1228 features->ycbcrImageArrays = true;
1229 break;
1230 }
1231 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES: {
1232 VkPhysicalDeviceUniformBufferStandardLayoutFeatures *features =
1233 (VkPhysicalDeviceUniformBufferStandardLayoutFeatures *)ext;
1234 CORE_FEATURE(1, 2, uniformBufferStandardLayout);
1235 break;
1236 }
1237 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT: {
1238 VkPhysicalDeviceIndexTypeUint8FeaturesEXT *features =
1239 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT *)ext;
1240 features->indexTypeUint8 = pdevice->rad_info.chip_class >= GFX8;
1241 break;
1242 }
1243 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGELESS_FRAMEBUFFER_FEATURES: {
1244 VkPhysicalDeviceImagelessFramebufferFeatures *features =
1245 (VkPhysicalDeviceImagelessFramebufferFeatures *)ext;
1246 CORE_FEATURE(1, 2, imagelessFramebuffer);
1247 break;
1248 }
1249 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR: {
1250 VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *features =
1251 (VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *)ext;
1252 features->pipelineExecutableInfo = true;
1253 break;
1254 }
1255 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CLOCK_FEATURES_KHR: {
1256 VkPhysicalDeviceShaderClockFeaturesKHR *features =
1257 (VkPhysicalDeviceShaderClockFeaturesKHR *)ext;
1258 features->shaderSubgroupClock = true;
1259 features->shaderDeviceClock = pdevice->rad_info.chip_class >= GFX8;
1260 break;
1261 }
1262 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_FEATURES_EXT: {
1263 VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT *features =
1264 (VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT *)ext;
1265 features->texelBufferAlignment = true;
1266 break;
1267 }
1268 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_FEATURES: {
1269 VkPhysicalDeviceTimelineSemaphoreFeatures *features =
1270 (VkPhysicalDeviceTimelineSemaphoreFeatures *) ext;
1271 CORE_FEATURE(1, 2, timelineSemaphore);
1272 break;
1273 }
1274 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_FEATURES_EXT: {
1275 VkPhysicalDeviceSubgroupSizeControlFeaturesEXT *features =
1276 (VkPhysicalDeviceSubgroupSizeControlFeaturesEXT *)ext;
1277 features->subgroupSizeControl = true;
1278 features->computeFullSubgroups = true;
1279 break;
1280 }
1281 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COHERENT_MEMORY_FEATURES_AMD: {
1282 VkPhysicalDeviceCoherentMemoryFeaturesAMD *features =
1283 (VkPhysicalDeviceCoherentMemoryFeaturesAMD *)ext;
1284 features->deviceCoherentMemory = pdevice->rad_info.has_l2_uncached;
1285 break;
1286 }
1287 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_SUBGROUP_EXTENDED_TYPES_FEATURES: {
1288 VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures *features =
1289 (VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures *)ext;
1290 CORE_FEATURE(1, 2, shaderSubgroupExtendedTypes);
1291 break;
1292 }
1293 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SEPARATE_DEPTH_STENCIL_LAYOUTS_FEATURES_KHR: {
1294 VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR *features =
1295 (VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR *)ext;
1296 CORE_FEATURE(1, 2, separateDepthStencilLayouts);
1297 break;
1298 }
1299 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES: {
1300 radv_get_physical_device_features_1_1(pdevice, (void *)ext);
1301 break;
1302 }
1303 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES: {
1304 radv_get_physical_device_features_1_2(pdevice, (void *)ext);
1305 break;
1306 }
1307 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_FEATURES_EXT: {
1308 VkPhysicalDeviceLineRasterizationFeaturesEXT *features =
1309 (VkPhysicalDeviceLineRasterizationFeaturesEXT *)ext;
1310 features->rectangularLines = false;
1311 features->bresenhamLines = true;
1312 features->smoothLines = false;
1313 features->stippledRectangularLines = false;
1314 features->stippledBresenhamLines = true;
1315 features->stippledSmoothLines = false;
1316 break;
1317 }
1318 case VK_STRUCTURE_TYPE_DEVICE_MEMORY_OVERALLOCATION_CREATE_INFO_AMD: {
1319 VkDeviceMemoryOverallocationCreateInfoAMD *features =
1320 (VkDeviceMemoryOverallocationCreateInfoAMD *)ext;
1321 features->overallocationBehavior = true;
1322 break;
1323 }
1324 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ROBUSTNESS_2_FEATURES_EXT: {
1325 VkPhysicalDeviceRobustness2FeaturesEXT *features =
1326 (VkPhysicalDeviceRobustness2FeaturesEXT *)ext;
1327 features->robustBufferAccess2 = true;
1328 features->robustImageAccess2 = true;
1329 features->nullDescriptor = true;
1330 break;
1331 }
1332 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_FEATURES_EXT: {
1333 VkPhysicalDeviceCustomBorderColorFeaturesEXT *features =
1334 (VkPhysicalDeviceCustomBorderColorFeaturesEXT *)ext;
1335 features->customBorderColors = true;
1336 features->customBorderColorWithoutFormat = true;
1337 break;
1338 }
1339 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PRIVATE_DATA_FEATURES_EXT: {
1340 VkPhysicalDevicePrivateDataFeaturesEXT *features =
1341 (VkPhysicalDevicePrivateDataFeaturesEXT *)ext;
1342 features->privateData = true;
1343 break;
1344 }
1345 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_CREATION_CACHE_CONTROL_FEATURES_EXT: {
1346 VkPhysicalDevicePipelineCreationCacheControlFeaturesEXT *features =
1347 (VkPhysicalDevicePipelineCreationCacheControlFeaturesEXT *)ext;
1348 features-> pipelineCreationCacheControl = true;
1349 break;
1350 }
1351 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTENDED_DYNAMIC_STATE_FEATURES_EXT: {
1352 VkPhysicalDeviceExtendedDynamicStateFeaturesEXT *features =
1353 (VkPhysicalDeviceExtendedDynamicStateFeaturesEXT *) ext;
1354 features->extendedDynamicState = true;
1355 break;
1356 }
1357 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGE_ROBUSTNESS_FEATURES_EXT: {
1358 VkPhysicalDeviceImageRobustnessFeaturesEXT *features =
1359 (VkPhysicalDeviceImageRobustnessFeaturesEXT *)ext;
1360 features->robustImageAccess = true;
1361 break;
1362 }
1363 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_FLOAT_FEATURES_EXT: {
1364 VkPhysicalDeviceShaderAtomicFloatFeaturesEXT *features =
1365 (VkPhysicalDeviceShaderAtomicFloatFeaturesEXT *)ext;
1366 features->shaderBufferFloat32Atomics = true;
1367 features->shaderBufferFloat32AtomicAdd = false;
1368 features->shaderBufferFloat64Atomics = true;
1369 features->shaderBufferFloat64AtomicAdd = false;
1370 features->shaderSharedFloat32Atomics = true;
1371 features->shaderSharedFloat32AtomicAdd = pdevice->rad_info.chip_class >= GFX8 &&
1372 (!pdevice->use_llvm || LLVM_VERSION_MAJOR >= 10);
1373 features->shaderSharedFloat64Atomics = true;
1374 features->shaderSharedFloat64AtomicAdd = false;
1375 features->shaderImageFloat32Atomics = true;
1376 features->shaderImageFloat32AtomicAdd = false;
1377 features->sparseImageFloat32Atomics = false;
1378 features->sparseImageFloat32AtomicAdd = false;
1379 break;
1380 }
1381 default:
1382 break;
1383 }
1384 }
1385 #undef CORE_FEATURE
1386 }
1387
1388 static size_t
1389 radv_max_descriptor_set_size()
1390 {
1391 /* make sure that the entire descriptor set is addressable with a signed
1392 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1393 * be at most 2 GiB. the combined image & samples object count as one of
1394 * both. This limit is for the pipeline layout, not for the set layout, but
1395 * there is no set limit, so we just set a pipeline limit. I don't think
1396 * any app is going to hit this soon. */
1397 return ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
1398 - MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1399 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1400 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1401 32 /* sampler, largest when combined with image */ +
1402 64 /* sampled image */ +
1403 64 /* storage image */);
1404 }
1405
1406 void radv_GetPhysicalDeviceProperties(
1407 VkPhysicalDevice physicalDevice,
1408 VkPhysicalDeviceProperties* pProperties)
1409 {
1410 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1411 VkSampleCountFlags sample_counts = 0xf;
1412
1413 size_t max_descriptor_set_size = radv_max_descriptor_set_size();
1414
1415 VkPhysicalDeviceLimits limits = {
1416 .maxImageDimension1D = (1 << 14),
1417 .maxImageDimension2D = (1 << 14),
1418 .maxImageDimension3D = (1 << 11),
1419 .maxImageDimensionCube = (1 << 14),
1420 .maxImageArrayLayers = (1 << 11),
1421 .maxTexelBufferElements = UINT32_MAX,
1422 .maxUniformBufferRange = UINT32_MAX,
1423 .maxStorageBufferRange = UINT32_MAX,
1424 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1425 .maxMemoryAllocationCount = UINT32_MAX,
1426 .maxSamplerAllocationCount = 64 * 1024,
1427 .bufferImageGranularity = 64, /* A cache line */
1428 .sparseAddressSpaceSize = RADV_MAX_MEMORY_ALLOCATION_SIZE, /* buffer max size */
1429 .maxBoundDescriptorSets = MAX_SETS,
1430 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1431 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1432 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1433 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1434 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1435 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1436 .maxPerStageResources = max_descriptor_set_size,
1437 .maxDescriptorSetSamplers = max_descriptor_set_size,
1438 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1439 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1440 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1441 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1442 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1443 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1444 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1445 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1446 .maxVertexInputBindings = MAX_VBS,
1447 .maxVertexInputAttributeOffset = 2047,
1448 .maxVertexInputBindingStride = 2048,
1449 .maxVertexOutputComponents = 128,
1450 .maxTessellationGenerationLevel = 64,
1451 .maxTessellationPatchSize = 32,
1452 .maxTessellationControlPerVertexInputComponents = 128,
1453 .maxTessellationControlPerVertexOutputComponents = 128,
1454 .maxTessellationControlPerPatchOutputComponents = 120,
1455 .maxTessellationControlTotalOutputComponents = 4096,
1456 .maxTessellationEvaluationInputComponents = 128,
1457 .maxTessellationEvaluationOutputComponents = 128,
1458 .maxGeometryShaderInvocations = 127,
1459 .maxGeometryInputComponents = 64,
1460 .maxGeometryOutputComponents = 128,
1461 .maxGeometryOutputVertices = 256,
1462 .maxGeometryTotalOutputComponents = 1024,
1463 .maxFragmentInputComponents = 128,
1464 .maxFragmentOutputAttachments = 8,
1465 .maxFragmentDualSrcAttachments = 1,
1466 .maxFragmentCombinedOutputResources = 8,
1467 .maxComputeSharedMemorySize = 32768,
1468 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1469 .maxComputeWorkGroupInvocations = 1024,
1470 .maxComputeWorkGroupSize = {
1471 1024,
1472 1024,
1473 1024
1474 },
1475 .subPixelPrecisionBits = 8,
1476 .subTexelPrecisionBits = 8,
1477 .mipmapPrecisionBits = 8,
1478 .maxDrawIndexedIndexValue = UINT32_MAX,
1479 .maxDrawIndirectCount = UINT32_MAX,
1480 .maxSamplerLodBias = 16,
1481 .maxSamplerAnisotropy = 16,
1482 .maxViewports = MAX_VIEWPORTS,
1483 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1484 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1485 .viewportSubPixelBits = 8,
1486 .minMemoryMapAlignment = 4096, /* A page */
1487 .minTexelBufferOffsetAlignment = 4,
1488 .minUniformBufferOffsetAlignment = 4,
1489 .minStorageBufferOffsetAlignment = 4,
1490 .minTexelOffset = -32,
1491 .maxTexelOffset = 31,
1492 .minTexelGatherOffset = -32,
1493 .maxTexelGatherOffset = 31,
1494 .minInterpolationOffset = -2,
1495 .maxInterpolationOffset = 2,
1496 .subPixelInterpolationOffsetBits = 8,
1497 .maxFramebufferWidth = (1 << 14),
1498 .maxFramebufferHeight = (1 << 14),
1499 .maxFramebufferLayers = (1 << 10),
1500 .framebufferColorSampleCounts = sample_counts,
1501 .framebufferDepthSampleCounts = sample_counts,
1502 .framebufferStencilSampleCounts = sample_counts,
1503 .framebufferNoAttachmentsSampleCounts = sample_counts,
1504 .maxColorAttachments = MAX_RTS,
1505 .sampledImageColorSampleCounts = sample_counts,
1506 .sampledImageIntegerSampleCounts = sample_counts,
1507 .sampledImageDepthSampleCounts = sample_counts,
1508 .sampledImageStencilSampleCounts = sample_counts,
1509 .storageImageSampleCounts = sample_counts,
1510 .maxSampleMaskWords = 1,
1511 .timestampComputeAndGraphics = true,
1512 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1513 .maxClipDistances = 8,
1514 .maxCullDistances = 8,
1515 .maxCombinedClipAndCullDistances = 8,
1516 .discreteQueuePriorities = 2,
1517 .pointSizeRange = { 0.0, 8191.875 },
1518 .lineWidthRange = { 0.0, 8191.875 },
1519 .pointSizeGranularity = (1.0 / 8.0),
1520 .lineWidthGranularity = (1.0 / 8.0),
1521 .strictLines = false, /* FINISHME */
1522 .standardSampleLocations = true,
1523 .optimalBufferCopyOffsetAlignment = 128,
1524 .optimalBufferCopyRowPitchAlignment = 128,
1525 .nonCoherentAtomSize = 64,
1526 };
1527
1528 *pProperties = (VkPhysicalDeviceProperties) {
1529 .apiVersion = radv_physical_device_api_version(pdevice),
1530 .driverVersion = vk_get_driver_version(),
1531 .vendorID = ATI_VENDOR_ID,
1532 .deviceID = pdevice->rad_info.pci_id,
1533 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1534 .limits = limits,
1535 .sparseProperties = {0},
1536 };
1537
1538 strcpy(pProperties->deviceName, pdevice->name);
1539 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1540 }
1541
1542 static void
1543 radv_get_physical_device_properties_1_1(struct radv_physical_device *pdevice,
1544 VkPhysicalDeviceVulkan11Properties *p)
1545 {
1546 assert(p->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES);
1547
1548 memcpy(p->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1549 memcpy(p->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1550 memset(p->deviceLUID, 0, VK_LUID_SIZE);
1551 /* The LUID is for Windows. */
1552 p->deviceLUIDValid = false;
1553 p->deviceNodeMask = 0;
1554
1555 p->subgroupSize = RADV_SUBGROUP_SIZE;
1556 p->subgroupSupportedStages = VK_SHADER_STAGE_ALL_GRAPHICS |
1557 VK_SHADER_STAGE_COMPUTE_BIT;
1558 p->subgroupSupportedOperations = VK_SUBGROUP_FEATURE_BASIC_BIT |
1559 VK_SUBGROUP_FEATURE_VOTE_BIT |
1560 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1561 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1562 VK_SUBGROUP_FEATURE_CLUSTERED_BIT |
1563 VK_SUBGROUP_FEATURE_QUAD_BIT |
1564 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1565 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1566 p->subgroupQuadOperationsInAllStages = true;
1567
1568 p->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1569 p->maxMultiviewViewCount = MAX_VIEWS;
1570 p->maxMultiviewInstanceIndex = INT_MAX;
1571 p->protectedNoFault = false;
1572 p->maxPerSetDescriptors = RADV_MAX_PER_SET_DESCRIPTORS;
1573 p->maxMemoryAllocationSize = RADV_MAX_MEMORY_ALLOCATION_SIZE;
1574 }
1575
1576 static void
1577 radv_get_physical_device_properties_1_2(struct radv_physical_device *pdevice,
1578 VkPhysicalDeviceVulkan12Properties *p)
1579 {
1580 assert(p->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES);
1581
1582 p->driverID = VK_DRIVER_ID_MESA_RADV;
1583 snprintf(p->driverName, VK_MAX_DRIVER_NAME_SIZE, "radv");
1584 snprintf(p->driverInfo, VK_MAX_DRIVER_INFO_SIZE,
1585 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1 " (%s)",
1586 radv_get_compiler_string(pdevice));
1587 p->conformanceVersion = (VkConformanceVersion) {
1588 .major = 1,
1589 .minor = 2,
1590 .subminor = 0,
1591 .patch = 0,
1592 };
1593
1594 /* On AMD hardware, denormals and rounding modes for fp16/fp64 are
1595 * controlled by the same config register.
1596 */
1597 if (pdevice->rad_info.has_packed_math_16bit) {
1598 p->denormBehaviorIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
1599 p->roundingModeIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
1600 } else {
1601 p->denormBehaviorIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL_KHR;
1602 p->roundingModeIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL_KHR;
1603 }
1604
1605 /* With LLVM, do not allow both preserving and flushing denorms because
1606 * different shaders in the same pipeline can have different settings and
1607 * this won't work for merged shaders. To make it work, this requires LLVM
1608 * support for changing the register. The same logic applies for the
1609 * rounding modes because they are configured with the same config
1610 * register.
1611 */
1612 p->shaderDenormFlushToZeroFloat32 = true;
1613 p->shaderDenormPreserveFloat32 = !pdevice->use_llvm;
1614 p->shaderRoundingModeRTEFloat32 = true;
1615 p->shaderRoundingModeRTZFloat32 = !pdevice->use_llvm;
1616 p->shaderSignedZeroInfNanPreserveFloat32 = true;
1617
1618 p->shaderDenormFlushToZeroFloat16 = pdevice->rad_info.has_packed_math_16bit && !pdevice->use_llvm;
1619 p->shaderDenormPreserveFloat16 = pdevice->rad_info.has_packed_math_16bit;
1620 p->shaderRoundingModeRTEFloat16 = pdevice->rad_info.has_packed_math_16bit;
1621 p->shaderRoundingModeRTZFloat16 = pdevice->rad_info.has_packed_math_16bit && !pdevice->use_llvm;
1622 p->shaderSignedZeroInfNanPreserveFloat16 = pdevice->rad_info.has_packed_math_16bit;
1623
1624 p->shaderDenormFlushToZeroFloat64 = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_llvm;
1625 p->shaderDenormPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8;
1626 p->shaderRoundingModeRTEFloat64 = pdevice->rad_info.chip_class >= GFX8;
1627 p->shaderRoundingModeRTZFloat64 = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_llvm;
1628 p->shaderSignedZeroInfNanPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8;
1629
1630 p->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1631 p->shaderUniformBufferArrayNonUniformIndexingNative = false;
1632 p->shaderSampledImageArrayNonUniformIndexingNative = false;
1633 p->shaderStorageBufferArrayNonUniformIndexingNative = false;
1634 p->shaderStorageImageArrayNonUniformIndexingNative = false;
1635 p->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1636 p->robustBufferAccessUpdateAfterBind = false;
1637 p->quadDivergentImplicitLod = false;
1638
1639 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1640 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1641 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1642 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1643 32 /* sampler, largest when combined with image */ +
1644 64 /* sampled image */ +
1645 64 /* storage image */);
1646 p->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1647 p->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1648 p->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1649 p->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1650 p->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1651 p->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1652 p->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1653 p->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1654 p->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1655 p->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1656 p->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1657 p->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1658 p->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1659 p->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1660 p->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1661
1662 /* We support all of the depth resolve modes */
1663 p->supportedDepthResolveModes = VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1664 VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
1665 VK_RESOLVE_MODE_MIN_BIT_KHR |
1666 VK_RESOLVE_MODE_MAX_BIT_KHR;
1667
1668 /* Average doesn't make sense for stencil so we don't support that */
1669 p->supportedStencilResolveModes = VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1670 VK_RESOLVE_MODE_MIN_BIT_KHR |
1671 VK_RESOLVE_MODE_MAX_BIT_KHR;
1672
1673 p->independentResolveNone = true;
1674 p->independentResolve = true;
1675
1676 /* GFX6-8 only support single channel min/max filter. */
1677 p->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1678 p->filterMinmaxSingleComponentFormats = true;
1679
1680 p->maxTimelineSemaphoreValueDifference = UINT64_MAX;
1681
1682 p->framebufferIntegerColorSampleCounts = VK_SAMPLE_COUNT_1_BIT;
1683 }
1684
1685 void radv_GetPhysicalDeviceProperties2(
1686 VkPhysicalDevice physicalDevice,
1687 VkPhysicalDeviceProperties2 *pProperties)
1688 {
1689 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1690 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1691
1692 VkPhysicalDeviceVulkan11Properties core_1_1 = {
1693 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES,
1694 };
1695 radv_get_physical_device_properties_1_1(pdevice, &core_1_1);
1696
1697 VkPhysicalDeviceVulkan12Properties core_1_2 = {
1698 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES,
1699 };
1700 radv_get_physical_device_properties_1_2(pdevice, &core_1_2);
1701
1702 #define CORE_RENAMED_PROPERTY(major, minor, ext_property, core_property) \
1703 memcpy(&properties->ext_property, &core_##major##_##minor.core_property, \
1704 sizeof(core_##major##_##minor.core_property))
1705
1706 #define CORE_PROPERTY(major, minor, property) \
1707 CORE_RENAMED_PROPERTY(major, minor, property, property)
1708
1709 vk_foreach_struct(ext, pProperties->pNext) {
1710 switch (ext->sType) {
1711 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1712 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1713 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1714 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1715 break;
1716 }
1717 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1718 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1719 CORE_PROPERTY(1, 1, deviceUUID);
1720 CORE_PROPERTY(1, 1, driverUUID);
1721 CORE_PROPERTY(1, 1, deviceLUID);
1722 CORE_PROPERTY(1, 1, deviceLUIDValid);
1723 break;
1724 }
1725 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1726 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1727 CORE_PROPERTY(1, 1, maxMultiviewViewCount);
1728 CORE_PROPERTY(1, 1, maxMultiviewInstanceIndex);
1729 break;
1730 }
1731 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1732 VkPhysicalDevicePointClippingProperties *properties =
1733 (VkPhysicalDevicePointClippingProperties*)ext;
1734 CORE_PROPERTY(1, 1, pointClippingBehavior);
1735 break;
1736 }
1737 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1738 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1739 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1740 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1741 break;
1742 }
1743 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1744 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1745 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1746 properties->minImportedHostPointerAlignment = 4096;
1747 break;
1748 }
1749 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1750 VkPhysicalDeviceSubgroupProperties *properties =
1751 (VkPhysicalDeviceSubgroupProperties*)ext;
1752 CORE_PROPERTY(1, 1, subgroupSize);
1753 CORE_RENAMED_PROPERTY(1, 1, supportedStages,
1754 subgroupSupportedStages);
1755 CORE_RENAMED_PROPERTY(1, 1, supportedOperations,
1756 subgroupSupportedOperations);
1757 CORE_RENAMED_PROPERTY(1, 1, quadOperationsInAllStages,
1758 subgroupQuadOperationsInAllStages);
1759 break;
1760 }
1761 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1762 VkPhysicalDeviceMaintenance3Properties *properties =
1763 (VkPhysicalDeviceMaintenance3Properties*)ext;
1764 CORE_PROPERTY(1, 1, maxPerSetDescriptors);
1765 CORE_PROPERTY(1, 1, maxMemoryAllocationSize);
1766 break;
1767 }
1768 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES: {
1769 VkPhysicalDeviceSamplerFilterMinmaxProperties *properties =
1770 (VkPhysicalDeviceSamplerFilterMinmaxProperties *)ext;
1771 CORE_PROPERTY(1, 2, filterMinmaxImageComponentMapping);
1772 CORE_PROPERTY(1, 2, filterMinmaxSingleComponentFormats);
1773 break;
1774 }
1775 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1776 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1777 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1778
1779 /* Shader engines. */
1780 properties->shaderEngineCount =
1781 pdevice->rad_info.max_se;
1782 properties->shaderArraysPerEngineCount =
1783 pdevice->rad_info.max_sh_per_se;
1784 properties->computeUnitsPerShaderArray =
1785 pdevice->rad_info.min_good_cu_per_sa;
1786 properties->simdPerComputeUnit =
1787 pdevice->rad_info.num_simd_per_compute_unit;
1788 properties->wavefrontsPerSimd =
1789 pdevice->rad_info.max_wave64_per_simd;
1790 properties->wavefrontSize = 64;
1791
1792 /* SGPR. */
1793 properties->sgprsPerSimd =
1794 pdevice->rad_info.num_physical_sgprs_per_simd;
1795 properties->minSgprAllocation =
1796 pdevice->rad_info.min_sgpr_alloc;
1797 properties->maxSgprAllocation =
1798 pdevice->rad_info.max_sgpr_alloc;
1799 properties->sgprAllocationGranularity =
1800 pdevice->rad_info.sgpr_alloc_granularity;
1801
1802 /* VGPR. */
1803 properties->vgprsPerSimd =
1804 pdevice->rad_info.num_physical_wave64_vgprs_per_simd;
1805 properties->minVgprAllocation =
1806 pdevice->rad_info.min_wave64_vgpr_alloc;
1807 properties->maxVgprAllocation =
1808 pdevice->rad_info.max_vgpr_alloc;
1809 properties->vgprAllocationGranularity =
1810 pdevice->rad_info.wave64_vgpr_alloc_granularity;
1811 break;
1812 }
1813 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_2_AMD: {
1814 VkPhysicalDeviceShaderCoreProperties2AMD *properties =
1815 (VkPhysicalDeviceShaderCoreProperties2AMD *)ext;
1816
1817 properties->shaderCoreFeatures = 0;
1818 properties->activeComputeUnitCount =
1819 pdevice->rad_info.num_good_compute_units;
1820 break;
1821 }
1822 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1823 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1824 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1825 properties->maxVertexAttribDivisor = UINT32_MAX;
1826 break;
1827 }
1828 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES: {
1829 VkPhysicalDeviceDescriptorIndexingProperties *properties =
1830 (VkPhysicalDeviceDescriptorIndexingProperties*)ext;
1831 CORE_PROPERTY(1, 2, maxUpdateAfterBindDescriptorsInAllPools);
1832 CORE_PROPERTY(1, 2, shaderUniformBufferArrayNonUniformIndexingNative);
1833 CORE_PROPERTY(1, 2, shaderSampledImageArrayNonUniformIndexingNative);
1834 CORE_PROPERTY(1, 2, shaderStorageBufferArrayNonUniformIndexingNative);
1835 CORE_PROPERTY(1, 2, shaderStorageImageArrayNonUniformIndexingNative);
1836 CORE_PROPERTY(1, 2, shaderInputAttachmentArrayNonUniformIndexingNative);
1837 CORE_PROPERTY(1, 2, robustBufferAccessUpdateAfterBind);
1838 CORE_PROPERTY(1, 2, quadDivergentImplicitLod);
1839 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSamplers);
1840 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindUniformBuffers);
1841 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageBuffers);
1842 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSampledImages);
1843 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageImages);
1844 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindInputAttachments);
1845 CORE_PROPERTY(1, 2, maxPerStageUpdateAfterBindResources);
1846 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSamplers);
1847 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffers);
1848 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffersDynamic);
1849 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffers);
1850 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffersDynamic);
1851 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSampledImages);
1852 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageImages);
1853 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindInputAttachments);
1854 break;
1855 }
1856 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1857 VkPhysicalDeviceProtectedMemoryProperties *properties =
1858 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1859 CORE_PROPERTY(1, 1, protectedNoFault);
1860 break;
1861 }
1862 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1863 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1864 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1865 properties->primitiveOverestimationSize = 0;
1866 properties->maxExtraPrimitiveOverestimationSize = 0;
1867 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1868 properties->primitiveUnderestimation = false;
1869 properties->conservativePointAndLineRasterization = false;
1870 properties->degenerateTrianglesRasterized = false;
1871 properties->degenerateLinesRasterized = false;
1872 properties->fullyCoveredFragmentShaderInputVariable = false;
1873 properties->conservativeRasterizationPostDepthCoverage = false;
1874 break;
1875 }
1876 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1877 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1878 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1879 properties->pciDomain = pdevice->bus_info.domain;
1880 properties->pciBus = pdevice->bus_info.bus;
1881 properties->pciDevice = pdevice->bus_info.dev;
1882 properties->pciFunction = pdevice->bus_info.func;
1883 break;
1884 }
1885 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES: {
1886 VkPhysicalDeviceDriverProperties *properties =
1887 (VkPhysicalDeviceDriverProperties *) ext;
1888 CORE_PROPERTY(1, 2, driverID);
1889 CORE_PROPERTY(1, 2, driverName);
1890 CORE_PROPERTY(1, 2, driverInfo);
1891 CORE_PROPERTY(1, 2, conformanceVersion);
1892 break;
1893 }
1894 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1895 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1896 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1897 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1898 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1899 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1900 properties->maxTransformFeedbackStreamDataSize = 512;
1901 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1902 properties->maxTransformFeedbackBufferDataStride = 512;
1903 properties->transformFeedbackQueries = !pdevice->use_ngg_streamout;
1904 properties->transformFeedbackStreamsLinesTriangles = !pdevice->use_ngg_streamout;
1905 properties->transformFeedbackRasterizationStreamSelect = false;
1906 properties->transformFeedbackDraw = true;
1907 break;
1908 }
1909 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1910 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1911 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1912
1913 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1914 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1915 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1916 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1917 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1918 break;
1919 }
1920 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT: {
1921 VkPhysicalDeviceSampleLocationsPropertiesEXT *properties =
1922 (VkPhysicalDeviceSampleLocationsPropertiesEXT *)ext;
1923 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_2_BIT |
1924 VK_SAMPLE_COUNT_4_BIT |
1925 VK_SAMPLE_COUNT_8_BIT;
1926 properties->maxSampleLocationGridSize = (VkExtent2D){ 2 , 2 };
1927 properties->sampleLocationCoordinateRange[0] = 0.0f;
1928 properties->sampleLocationCoordinateRange[1] = 0.9375f;
1929 properties->sampleLocationSubPixelBits = 4;
1930 properties->variableSampleLocations = false;
1931 break;
1932 }
1933 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES: {
1934 VkPhysicalDeviceDepthStencilResolveProperties *properties =
1935 (VkPhysicalDeviceDepthStencilResolveProperties *)ext;
1936 CORE_PROPERTY(1, 2, supportedDepthResolveModes);
1937 CORE_PROPERTY(1, 2, supportedStencilResolveModes);
1938 CORE_PROPERTY(1, 2, independentResolveNone);
1939 CORE_PROPERTY(1, 2, independentResolve);
1940 break;
1941 }
1942 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_PROPERTIES_EXT: {
1943 VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT *properties =
1944 (VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT *)ext;
1945 properties->storageTexelBufferOffsetAlignmentBytes = 4;
1946 properties->storageTexelBufferOffsetSingleTexelAlignment = true;
1947 properties->uniformTexelBufferOffsetAlignmentBytes = 4;
1948 properties->uniformTexelBufferOffsetSingleTexelAlignment = true;
1949 break;
1950 }
1951 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT_CONTROLS_PROPERTIES : {
1952 VkPhysicalDeviceFloatControlsProperties *properties =
1953 (VkPhysicalDeviceFloatControlsProperties *)ext;
1954 CORE_PROPERTY(1, 2, denormBehaviorIndependence);
1955 CORE_PROPERTY(1, 2, roundingModeIndependence);
1956 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat16);
1957 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat16);
1958 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat16);
1959 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat16);
1960 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat16);
1961 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat32);
1962 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat32);
1963 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat32);
1964 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat32);
1965 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat32);
1966 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat64);
1967 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat64);
1968 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat64);
1969 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat64);
1970 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat64);
1971 break;
1972 }
1973 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_PROPERTIES: {
1974 VkPhysicalDeviceTimelineSemaphoreProperties *properties =
1975 (VkPhysicalDeviceTimelineSemaphoreProperties *) ext;
1976 CORE_PROPERTY(1, 2, maxTimelineSemaphoreValueDifference);
1977 break;
1978 }
1979 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_PROPERTIES_EXT: {
1980 VkPhysicalDeviceSubgroupSizeControlPropertiesEXT *props =
1981 (VkPhysicalDeviceSubgroupSizeControlPropertiesEXT *)ext;
1982 props->minSubgroupSize = 64;
1983 props->maxSubgroupSize = 64;
1984 props->maxComputeWorkgroupSubgroups = UINT32_MAX;
1985 props->requiredSubgroupSizeStages = 0;
1986
1987 if (pdevice->rad_info.chip_class >= GFX10) {
1988 /* Only GFX10+ supports wave32. */
1989 props->minSubgroupSize = 32;
1990 props->requiredSubgroupSizeStages = VK_SHADER_STAGE_COMPUTE_BIT;
1991 }
1992 break;
1993 }
1994 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES:
1995 radv_get_physical_device_properties_1_1(pdevice, (void *)ext);
1996 break;
1997 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES:
1998 radv_get_physical_device_properties_1_2(pdevice, (void *)ext);
1999 break;
2000 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_PROPERTIES_EXT: {
2001 VkPhysicalDeviceLineRasterizationPropertiesEXT *props =
2002 (VkPhysicalDeviceLineRasterizationPropertiesEXT *)ext;
2003 props->lineSubPixelPrecisionBits = 4;
2004 break;
2005 }
2006 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ROBUSTNESS_2_PROPERTIES_EXT: {
2007 VkPhysicalDeviceRobustness2PropertiesEXT *properties =
2008 (VkPhysicalDeviceRobustness2PropertiesEXT *)ext;
2009 properties->robustStorageBufferAccessSizeAlignment = 4;
2010 properties->robustUniformBufferAccessSizeAlignment = 4;
2011 break;
2012 }
2013 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_PROPERTIES_EXT: {
2014 VkPhysicalDeviceCustomBorderColorPropertiesEXT *props =
2015 (VkPhysicalDeviceCustomBorderColorPropertiesEXT *)ext;
2016 props->maxCustomBorderColorSamplers = RADV_BORDER_COLOR_COUNT;
2017 break;
2018 }
2019 default:
2020 break;
2021 }
2022 }
2023 }
2024
2025 static void radv_get_physical_device_queue_family_properties(
2026 struct radv_physical_device* pdevice,
2027 uint32_t* pCount,
2028 VkQueueFamilyProperties** pQueueFamilyProperties)
2029 {
2030 int num_queue_families = 1;
2031 int idx;
2032 if (pdevice->rad_info.num_rings[RING_COMPUTE] > 0 &&
2033 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
2034 num_queue_families++;
2035
2036 if (pQueueFamilyProperties == NULL) {
2037 *pCount = num_queue_families;
2038 return;
2039 }
2040
2041 if (!*pCount)
2042 return;
2043
2044 idx = 0;
2045 if (*pCount >= 1) {
2046 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
2047 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
2048 VK_QUEUE_COMPUTE_BIT |
2049 VK_QUEUE_TRANSFER_BIT |
2050 VK_QUEUE_SPARSE_BINDING_BIT,
2051 .queueCount = 1,
2052 .timestampValidBits = 64,
2053 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
2054 };
2055 idx++;
2056 }
2057
2058 if (pdevice->rad_info.num_rings[RING_COMPUTE] > 0 &&
2059 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
2060 if (*pCount > idx) {
2061 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
2062 .queueFlags = VK_QUEUE_COMPUTE_BIT |
2063 VK_QUEUE_TRANSFER_BIT |
2064 VK_QUEUE_SPARSE_BINDING_BIT,
2065 .queueCount = pdevice->rad_info.num_rings[RING_COMPUTE],
2066 .timestampValidBits = 64,
2067 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
2068 };
2069 idx++;
2070 }
2071 }
2072 *pCount = idx;
2073 }
2074
2075 void radv_GetPhysicalDeviceQueueFamilyProperties(
2076 VkPhysicalDevice physicalDevice,
2077 uint32_t* pCount,
2078 VkQueueFamilyProperties* pQueueFamilyProperties)
2079 {
2080 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
2081 if (!pQueueFamilyProperties) {
2082 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
2083 return;
2084 }
2085 VkQueueFamilyProperties *properties[] = {
2086 pQueueFamilyProperties + 0,
2087 pQueueFamilyProperties + 1,
2088 pQueueFamilyProperties + 2,
2089 };
2090 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
2091 assert(*pCount <= 3);
2092 }
2093
2094 void radv_GetPhysicalDeviceQueueFamilyProperties2(
2095 VkPhysicalDevice physicalDevice,
2096 uint32_t* pCount,
2097 VkQueueFamilyProperties2 *pQueueFamilyProperties)
2098 {
2099 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
2100 if (!pQueueFamilyProperties) {
2101 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
2102 return;
2103 }
2104 VkQueueFamilyProperties *properties[] = {
2105 &pQueueFamilyProperties[0].queueFamilyProperties,
2106 &pQueueFamilyProperties[1].queueFamilyProperties,
2107 &pQueueFamilyProperties[2].queueFamilyProperties,
2108 };
2109 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
2110 assert(*pCount <= 3);
2111 }
2112
2113 void radv_GetPhysicalDeviceMemoryProperties(
2114 VkPhysicalDevice physicalDevice,
2115 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
2116 {
2117 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2118
2119 *pMemoryProperties = physical_device->memory_properties;
2120 }
2121
2122 static void
2123 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
2124 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
2125 {
2126 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2127 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
2128 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
2129 uint64_t vram_size = radv_get_vram_size(device);
2130 uint64_t gtt_size = device->rad_info.gart_size;
2131 uint64_t heap_budget, heap_usage;
2132
2133 /* For all memory heaps, the computation of budget is as follow:
2134 * heap_budget = heap_size - global_heap_usage + app_heap_usage
2135 *
2136 * The Vulkan spec 1.1.97 says that the budget should include any
2137 * currently allocated device memory.
2138 *
2139 * Note that the application heap usages are not really accurate (eg.
2140 * in presence of shared buffers).
2141 */
2142 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
2143 uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;
2144
2145 if ((device->memory_domains[i] & RADEON_DOMAIN_VRAM) && (device->memory_flags[i] & RADEON_FLAG_NO_CPU_ACCESS)) {
2146 heap_usage = device->ws->query_value(device->ws,
2147 RADEON_ALLOCATED_VRAM);
2148
2149 heap_budget = vram_size -
2150 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
2151 heap_usage;
2152
2153 memoryBudget->heapBudget[heap_index] = heap_budget;
2154 memoryBudget->heapUsage[heap_index] = heap_usage;
2155 } else if (device->memory_domains[i] & RADEON_DOMAIN_VRAM) {
2156 heap_usage = device->ws->query_value(device->ws,
2157 RADEON_ALLOCATED_VRAM_VIS);
2158
2159 heap_budget = visible_vram_size -
2160 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
2161 heap_usage;
2162
2163 memoryBudget->heapBudget[heap_index] = heap_budget;
2164 memoryBudget->heapUsage[heap_index] = heap_usage;
2165 } else {
2166 assert(device->memory_domains[i] & RADEON_DOMAIN_GTT);
2167
2168 heap_usage = device->ws->query_value(device->ws,
2169 RADEON_ALLOCATED_GTT);
2170
2171 heap_budget = gtt_size -
2172 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
2173 heap_usage;
2174
2175 memoryBudget->heapBudget[heap_index] = heap_budget;
2176 memoryBudget->heapUsage[heap_index] = heap_usage;
2177 }
2178 }
2179
2180 /* The heapBudget and heapUsage values must be zero for array elements
2181 * greater than or equal to
2182 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
2183 */
2184 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
2185 memoryBudget->heapBudget[i] = 0;
2186 memoryBudget->heapUsage[i] = 0;
2187 }
2188 }
2189
2190 void radv_GetPhysicalDeviceMemoryProperties2(
2191 VkPhysicalDevice physicalDevice,
2192 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
2193 {
2194 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
2195 &pMemoryProperties->memoryProperties);
2196
2197 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
2198 vk_find_struct(pMemoryProperties->pNext,
2199 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
2200 if (memory_budget)
2201 radv_get_memory_budget_properties(physicalDevice, memory_budget);
2202 }
2203
2204 VkResult radv_GetMemoryHostPointerPropertiesEXT(
2205 VkDevice _device,
2206 VkExternalMemoryHandleTypeFlagBits handleType,
2207 const void *pHostPointer,
2208 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
2209 {
2210 RADV_FROM_HANDLE(radv_device, device, _device);
2211
2212 switch (handleType)
2213 {
2214 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
2215 const struct radv_physical_device *physical_device = device->physical_device;
2216 uint32_t memoryTypeBits = 0;
2217 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
2218 if (physical_device->memory_domains[i] == RADEON_DOMAIN_GTT &&
2219 !(physical_device->memory_flags[i] & RADEON_FLAG_GTT_WC)) {
2220 memoryTypeBits = (1 << i);
2221 break;
2222 }
2223 }
2224 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
2225 return VK_SUCCESS;
2226 }
2227 default:
2228 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
2229 }
2230 }
2231
2232 static enum radeon_ctx_priority
2233 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
2234 {
2235 /* Default to MEDIUM when a specific global priority isn't requested */
2236 if (!pObj)
2237 return RADEON_CTX_PRIORITY_MEDIUM;
2238
2239 switch(pObj->globalPriority) {
2240 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
2241 return RADEON_CTX_PRIORITY_REALTIME;
2242 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
2243 return RADEON_CTX_PRIORITY_HIGH;
2244 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
2245 return RADEON_CTX_PRIORITY_MEDIUM;
2246 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
2247 return RADEON_CTX_PRIORITY_LOW;
2248 default:
2249 unreachable("Illegal global priority value");
2250 return RADEON_CTX_PRIORITY_INVALID;
2251 }
2252 }
2253
2254 static int
2255 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
2256 uint32_t queue_family_index, int idx,
2257 VkDeviceQueueCreateFlags flags,
2258 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
2259 {
2260 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2261 queue->device = device;
2262 queue->queue_family_index = queue_family_index;
2263 queue->queue_idx = idx;
2264 queue->priority = radv_get_queue_global_priority(global_priority);
2265 queue->flags = flags;
2266 queue->hw_ctx = NULL;
2267
2268 VkResult result = device->ws->ctx_create(device->ws, queue->priority, &queue->hw_ctx);
2269 if (result != VK_SUCCESS)
2270 return vk_error(device->instance, result);
2271
2272 list_inithead(&queue->pending_submissions);
2273 pthread_mutex_init(&queue->pending_mutex, NULL);
2274
2275 pthread_mutex_init(&queue->thread_mutex, NULL);
2276 queue->thread_submission = NULL;
2277 queue->thread_running = queue->thread_exit = false;
2278 result = radv_create_pthread_cond(&queue->thread_cond);
2279 if (result != VK_SUCCESS)
2280 return vk_error(device->instance, result);
2281
2282 return VK_SUCCESS;
2283 }
2284
2285 static void
2286 radv_queue_finish(struct radv_queue *queue)
2287 {
2288 if (queue->thread_running) {
2289 p_atomic_set(&queue->thread_exit, true);
2290 pthread_cond_broadcast(&queue->thread_cond);
2291 pthread_join(queue->submission_thread, NULL);
2292 }
2293 pthread_cond_destroy(&queue->thread_cond);
2294 pthread_mutex_destroy(&queue->pending_mutex);
2295 pthread_mutex_destroy(&queue->thread_mutex);
2296
2297 if (queue->hw_ctx)
2298 queue->device->ws->ctx_destroy(queue->hw_ctx);
2299
2300 if (queue->initial_full_flush_preamble_cs)
2301 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2302 if (queue->initial_preamble_cs)
2303 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2304 if (queue->continue_preamble_cs)
2305 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2306 if (queue->descriptor_bo)
2307 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2308 if (queue->scratch_bo)
2309 queue->device->ws->buffer_destroy(queue->scratch_bo);
2310 if (queue->esgs_ring_bo)
2311 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2312 if (queue->gsvs_ring_bo)
2313 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2314 if (queue->tess_rings_bo)
2315 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
2316 if (queue->gds_bo)
2317 queue->device->ws->buffer_destroy(queue->gds_bo);
2318 if (queue->gds_oa_bo)
2319 queue->device->ws->buffer_destroy(queue->gds_oa_bo);
2320 if (queue->compute_scratch_bo)
2321 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2322 }
2323
2324 static void
2325 radv_bo_list_init(struct radv_bo_list *bo_list)
2326 {
2327 pthread_mutex_init(&bo_list->mutex, NULL);
2328 bo_list->list.count = bo_list->capacity = 0;
2329 bo_list->list.bos = NULL;
2330 }
2331
2332 static void
2333 radv_bo_list_finish(struct radv_bo_list *bo_list)
2334 {
2335 free(bo_list->list.bos);
2336 pthread_mutex_destroy(&bo_list->mutex);
2337 }
2338
2339 VkResult radv_bo_list_add(struct radv_device *device,
2340 struct radeon_winsys_bo *bo)
2341 {
2342 struct radv_bo_list *bo_list = &device->bo_list;
2343
2344 if (bo->is_local)
2345 return VK_SUCCESS;
2346
2347 if (unlikely(!device->use_global_bo_list))
2348 return VK_SUCCESS;
2349
2350 pthread_mutex_lock(&bo_list->mutex);
2351 if (bo_list->list.count == bo_list->capacity) {
2352 unsigned capacity = MAX2(4, bo_list->capacity * 2);
2353 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
2354
2355 if (!data) {
2356 pthread_mutex_unlock(&bo_list->mutex);
2357 return VK_ERROR_OUT_OF_HOST_MEMORY;
2358 }
2359
2360 bo_list->list.bos = (struct radeon_winsys_bo**)data;
2361 bo_list->capacity = capacity;
2362 }
2363
2364 bo_list->list.bos[bo_list->list.count++] = bo;
2365 pthread_mutex_unlock(&bo_list->mutex);
2366 return VK_SUCCESS;
2367 }
2368
2369 void radv_bo_list_remove(struct radv_device *device,
2370 struct radeon_winsys_bo *bo)
2371 {
2372 struct radv_bo_list *bo_list = &device->bo_list;
2373
2374 if (bo->is_local)
2375 return;
2376
2377 if (unlikely(!device->use_global_bo_list))
2378 return;
2379
2380 pthread_mutex_lock(&bo_list->mutex);
2381 /* Loop the list backwards so we find the most recently added
2382 * memory first. */
2383 for(unsigned i = bo_list->list.count; i-- > 0;) {
2384 if (bo_list->list.bos[i] == bo) {
2385 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
2386 --bo_list->list.count;
2387 break;
2388 }
2389 }
2390 pthread_mutex_unlock(&bo_list->mutex);
2391 }
2392
2393 static void
2394 radv_device_init_gs_info(struct radv_device *device)
2395 {
2396 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
2397 device->physical_device->rad_info.family);
2398 }
2399
2400 static int radv_get_device_extension_index(const char *name)
2401 {
2402 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
2403 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
2404 return i;
2405 }
2406 return -1;
2407 }
2408
2409 static int
2410 radv_get_int_debug_option(const char *name, int default_value)
2411 {
2412 const char *str;
2413 int result;
2414
2415 str = getenv(name);
2416 if (!str) {
2417 result = default_value;
2418 } else {
2419 char *endptr;
2420
2421 result = strtol(str, &endptr, 0);
2422 if (str == endptr) {
2423 /* No digits founs. */
2424 result = default_value;
2425 }
2426 }
2427
2428 return result;
2429 }
2430
2431 static void
2432 radv_device_init_dispatch(struct radv_device *device)
2433 {
2434 const struct radv_instance *instance = device->physical_device->instance;
2435 const struct radv_device_dispatch_table *dispatch_table_layer = NULL;
2436 bool unchecked = instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS;
2437 int radv_thread_trace = radv_get_int_debug_option("RADV_THREAD_TRACE", -1);
2438
2439 if (radv_thread_trace >= 0) {
2440 /* Use device entrypoints from the SQTT layer if enabled. */
2441 dispatch_table_layer = &sqtt_device_dispatch_table;
2442 }
2443
2444 for (unsigned i = 0; i < ARRAY_SIZE(device->dispatch.entrypoints); i++) {
2445 /* Vulkan requires that entrypoints for extensions which have not been
2446 * enabled must not be advertised.
2447 */
2448 if (!unchecked &&
2449 !radv_device_entrypoint_is_enabled(i, instance->apiVersion,
2450 &instance->enabled_extensions,
2451 &device->enabled_extensions)) {
2452 device->dispatch.entrypoints[i] = NULL;
2453 } else if (dispatch_table_layer &&
2454 dispatch_table_layer->entrypoints[i]) {
2455 device->dispatch.entrypoints[i] =
2456 dispatch_table_layer->entrypoints[i];
2457 } else {
2458 device->dispatch.entrypoints[i] =
2459 radv_device_dispatch_table.entrypoints[i];
2460 }
2461 }
2462 }
2463
2464 static VkResult
2465 radv_create_pthread_cond(pthread_cond_t *cond)
2466 {
2467 pthread_condattr_t condattr;
2468 if (pthread_condattr_init(&condattr)) {
2469 return VK_ERROR_INITIALIZATION_FAILED;
2470 }
2471
2472 if (pthread_condattr_setclock(&condattr, CLOCK_MONOTONIC)) {
2473 pthread_condattr_destroy(&condattr);
2474 return VK_ERROR_INITIALIZATION_FAILED;
2475 }
2476 if (pthread_cond_init(cond, &condattr)) {
2477 pthread_condattr_destroy(&condattr);
2478 return VK_ERROR_INITIALIZATION_FAILED;
2479 }
2480 pthread_condattr_destroy(&condattr);
2481 return VK_SUCCESS;
2482 }
2483
2484 static VkResult
2485 check_physical_device_features(VkPhysicalDevice physicalDevice,
2486 const VkPhysicalDeviceFeatures *features)
2487 {
2488 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2489 VkPhysicalDeviceFeatures supported_features;
2490 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
2491 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
2492 VkBool32 *enabled_feature = (VkBool32 *)features;
2493 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
2494 for (uint32_t i = 0; i < num_features; i++) {
2495 if (enabled_feature[i] && !supported_feature[i])
2496 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
2497 }
2498
2499 return VK_SUCCESS;
2500 }
2501
2502 static VkResult radv_device_init_border_color(struct radv_device *device)
2503 {
2504 device->border_color_data.bo =
2505 device->ws->buffer_create(device->ws,
2506 RADV_BORDER_COLOR_BUFFER_SIZE,
2507 4096,
2508 RADEON_DOMAIN_VRAM,
2509 RADEON_FLAG_CPU_ACCESS |
2510 RADEON_FLAG_READ_ONLY |
2511 RADEON_FLAG_NO_INTERPROCESS_SHARING,
2512 RADV_BO_PRIORITY_SHADER);
2513
2514 if (device->border_color_data.bo == NULL)
2515 return vk_error(device->physical_device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2516
2517 device->border_color_data.colors_gpu_ptr =
2518 device->ws->buffer_map(device->border_color_data.bo);
2519 if (!device->border_color_data.colors_gpu_ptr)
2520 return vk_error(device->physical_device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2521 pthread_mutex_init(&device->border_color_data.mutex, NULL);
2522
2523 return VK_SUCCESS;
2524 }
2525
2526 static void radv_device_finish_border_color(struct radv_device *device)
2527 {
2528 if (device->border_color_data.bo) {
2529 device->ws->buffer_destroy(device->border_color_data.bo);
2530
2531 pthread_mutex_destroy(&device->border_color_data.mutex);
2532 }
2533 }
2534
2535 VkResult radv_CreateDevice(
2536 VkPhysicalDevice physicalDevice,
2537 const VkDeviceCreateInfo* pCreateInfo,
2538 const VkAllocationCallbacks* pAllocator,
2539 VkDevice* pDevice)
2540 {
2541 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2542 VkResult result;
2543 struct radv_device *device;
2544
2545 bool keep_shader_info = false;
2546 bool robust_buffer_access = false;
2547 bool overallocation_disallowed = false;
2548 bool custom_border_colors = false;
2549
2550 /* Check enabled features */
2551 if (pCreateInfo->pEnabledFeatures) {
2552 result = check_physical_device_features(physicalDevice,
2553 pCreateInfo->pEnabledFeatures);
2554 if (result != VK_SUCCESS)
2555 return result;
2556
2557 if (pCreateInfo->pEnabledFeatures->robustBufferAccess)
2558 robust_buffer_access = true;
2559 }
2560
2561 vk_foreach_struct_const(ext, pCreateInfo->pNext) {
2562 switch (ext->sType) {
2563 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FEATURES_2: {
2564 const VkPhysicalDeviceFeatures2 *features = (const void *)ext;
2565 result = check_physical_device_features(physicalDevice,
2566 &features->features);
2567 if (result != VK_SUCCESS)
2568 return result;
2569
2570 if (features->features.robustBufferAccess)
2571 robust_buffer_access = true;
2572 break;
2573 }
2574 case VK_STRUCTURE_TYPE_DEVICE_MEMORY_OVERALLOCATION_CREATE_INFO_AMD: {
2575 const VkDeviceMemoryOverallocationCreateInfoAMD *overallocation = (const void *)ext;
2576 if (overallocation->overallocationBehavior == VK_MEMORY_OVERALLOCATION_BEHAVIOR_DISALLOWED_AMD)
2577 overallocation_disallowed = true;
2578 break;
2579 }
2580 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_FEATURES_EXT: {
2581 const VkPhysicalDeviceCustomBorderColorFeaturesEXT *border_color_features = (const void *)ext;
2582 custom_border_colors = border_color_features->customBorderColors;
2583 break;
2584 }
2585 default:
2586 break;
2587 }
2588 }
2589
2590 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
2591 sizeof(*device), 8,
2592 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2593 if (!device)
2594 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2595
2596 vk_device_init(&device->vk, pCreateInfo,
2597 &physical_device->instance->alloc, pAllocator);
2598
2599 device->instance = physical_device->instance;
2600 device->physical_device = physical_device;
2601
2602 device->ws = physical_device->ws;
2603
2604 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
2605 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
2606 int index = radv_get_device_extension_index(ext_name);
2607 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
2608 vk_free(&device->vk.alloc, device);
2609 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
2610 }
2611
2612 device->enabled_extensions.extensions[index] = true;
2613 }
2614
2615 radv_device_init_dispatch(device);
2616
2617 keep_shader_info = device->enabled_extensions.AMD_shader_info;
2618
2619 /* With update after bind we can't attach bo's to the command buffer
2620 * from the descriptor set anymore, so we have to use a global BO list.
2621 */
2622 device->use_global_bo_list =
2623 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
2624 device->enabled_extensions.EXT_descriptor_indexing ||
2625 device->enabled_extensions.EXT_buffer_device_address ||
2626 device->enabled_extensions.KHR_buffer_device_address;
2627
2628 device->robust_buffer_access = robust_buffer_access;
2629
2630 mtx_init(&device->shader_slab_mutex, mtx_plain);
2631 list_inithead(&device->shader_slabs);
2632
2633 device->overallocation_disallowed = overallocation_disallowed;
2634 mtx_init(&device->overallocation_mutex, mtx_plain);
2635
2636 radv_bo_list_init(&device->bo_list);
2637
2638 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
2639 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
2640 uint32_t qfi = queue_create->queueFamilyIndex;
2641 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
2642 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
2643
2644 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
2645
2646 device->queues[qfi] = vk_alloc(&device->vk.alloc,
2647 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2648 if (!device->queues[qfi]) {
2649 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2650 goto fail;
2651 }
2652
2653 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
2654
2655 device->queue_count[qfi] = queue_create->queueCount;
2656
2657 for (unsigned q = 0; q < queue_create->queueCount; q++) {
2658 result = radv_queue_init(device, &device->queues[qfi][q],
2659 qfi, q, queue_create->flags,
2660 global_priority);
2661 if (result != VK_SUCCESS)
2662 goto fail;
2663 }
2664 }
2665
2666 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
2667 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
2668
2669 /* Disable DFSM by default. As of 2019-09-15 Talos on Low is still 3% slower on Raven. */
2670 device->dfsm_allowed = device->pbb_allowed &&
2671 (device->instance->perftest_flags & RADV_PERFTEST_DFSM);
2672
2673 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
2674
2675 /* The maximum number of scratch waves. Scratch space isn't divided
2676 * evenly between CUs. The number is only a function of the number of CUs.
2677 * We can decrease the constant to decrease the scratch buffer size.
2678 *
2679 * sctx->scratch_waves must be >= the maximum possible size of
2680 * 1 threadgroup, so that the hw doesn't hang from being unable
2681 * to start any.
2682 *
2683 * The recommended value is 4 per CU at most. Higher numbers don't
2684 * bring much benefit, but they still occupy chip resources (think
2685 * async compute). I've seen ~2% performance difference between 4 and 32.
2686 */
2687 uint32_t max_threads_per_block = 2048;
2688 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
2689 max_threads_per_block / 64);
2690
2691 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
2692
2693 if (device->physical_device->rad_info.chip_class >= GFX7) {
2694 /* If the KMD allows it (there is a KMD hw register for it),
2695 * allow launching waves out-of-order.
2696 */
2697 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
2698 }
2699
2700 radv_device_init_gs_info(device);
2701
2702 device->tess_offchip_block_dw_size =
2703 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
2704
2705 if (getenv("RADV_TRACE_FILE")) {
2706 const char *filename = getenv("RADV_TRACE_FILE");
2707
2708 keep_shader_info = true;
2709
2710 if (!radv_init_trace(device))
2711 goto fail;
2712
2713 fprintf(stderr, "*****************************************************************************\n");
2714 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
2715 fprintf(stderr, "*****************************************************************************\n");
2716
2717 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
2718 radv_dump_enabled_options(device, stderr);
2719 }
2720
2721 int radv_thread_trace = radv_get_int_debug_option("RADV_THREAD_TRACE", -1);
2722 if (radv_thread_trace >= 0) {
2723 fprintf(stderr, "*************************************************\n");
2724 fprintf(stderr, "* WARNING: Thread trace support is experimental *\n");
2725 fprintf(stderr, "*************************************************\n");
2726
2727 if (device->physical_device->rad_info.chip_class < GFX8) {
2728 fprintf(stderr, "GPU hardware not supported: refer to "
2729 "the RGP documentation for the list of "
2730 "supported GPUs!\n");
2731 abort();
2732 }
2733
2734 /* Default buffer size set to 1MB per SE. */
2735 device->thread_trace_buffer_size =
2736 radv_get_int_debug_option("RADV_THREAD_TRACE_BUFFER_SIZE", 1024 * 1024);
2737 device->thread_trace_start_frame = radv_thread_trace;
2738
2739 if (!radv_thread_trace_init(device))
2740 goto fail;
2741 }
2742
2743 device->keep_shader_info = keep_shader_info;
2744 result = radv_device_init_meta(device);
2745 if (result != VK_SUCCESS)
2746 goto fail;
2747
2748 radv_device_init_msaa(device);
2749
2750 /* If the border color extension is enabled, let's create the buffer we need. */
2751 if (custom_border_colors) {
2752 result = radv_device_init_border_color(device);
2753 if (result != VK_SUCCESS)
2754 goto fail;
2755 }
2756
2757 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
2758 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
2759 if (!device->empty_cs[family])
2760 goto fail;
2761
2762 switch (family) {
2763 case RADV_QUEUE_GENERAL:
2764 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2765 radeon_emit(device->empty_cs[family], CC0_UPDATE_LOAD_ENABLES(1));
2766 radeon_emit(device->empty_cs[family], CC1_UPDATE_SHADOW_ENABLES(1));
2767 break;
2768 case RADV_QUEUE_COMPUTE:
2769 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
2770 radeon_emit(device->empty_cs[family], 0);
2771 break;
2772 }
2773
2774 result = device->ws->cs_finalize(device->empty_cs[family]);
2775 if (result != VK_SUCCESS)
2776 goto fail;
2777 }
2778
2779 if (device->physical_device->rad_info.chip_class >= GFX7)
2780 cik_create_gfx_config(device);
2781
2782 VkPipelineCacheCreateInfo ci;
2783 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
2784 ci.pNext = NULL;
2785 ci.flags = 0;
2786 ci.pInitialData = NULL;
2787 ci.initialDataSize = 0;
2788 VkPipelineCache pc;
2789 result = radv_CreatePipelineCache(radv_device_to_handle(device),
2790 &ci, NULL, &pc);
2791 if (result != VK_SUCCESS)
2792 goto fail_meta;
2793
2794 device->mem_cache = radv_pipeline_cache_from_handle(pc);
2795
2796 result = radv_create_pthread_cond(&device->timeline_cond);
2797 if (result != VK_SUCCESS)
2798 goto fail_mem_cache;
2799
2800 device->force_aniso =
2801 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
2802 if (device->force_aniso >= 0) {
2803 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
2804 1 << util_logbase2(device->force_aniso));
2805 }
2806
2807 *pDevice = radv_device_to_handle(device);
2808 return VK_SUCCESS;
2809
2810 fail_mem_cache:
2811 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2812 fail_meta:
2813 radv_device_finish_meta(device);
2814 fail:
2815 radv_bo_list_finish(&device->bo_list);
2816
2817 radv_thread_trace_finish(device);
2818
2819 if (device->trace_bo)
2820 device->ws->buffer_destroy(device->trace_bo);
2821
2822 if (device->gfx_init)
2823 device->ws->buffer_destroy(device->gfx_init);
2824
2825 radv_device_finish_border_color(device);
2826
2827 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2828 for (unsigned q = 0; q < device->queue_count[i]; q++)
2829 radv_queue_finish(&device->queues[i][q]);
2830 if (device->queue_count[i])
2831 vk_free(&device->vk.alloc, device->queues[i]);
2832 }
2833
2834 vk_free(&device->vk.alloc, device);
2835 return result;
2836 }
2837
2838 void radv_DestroyDevice(
2839 VkDevice _device,
2840 const VkAllocationCallbacks* pAllocator)
2841 {
2842 RADV_FROM_HANDLE(radv_device, device, _device);
2843
2844 if (!device)
2845 return;
2846
2847 if (device->trace_bo)
2848 device->ws->buffer_destroy(device->trace_bo);
2849
2850 if (device->gfx_init)
2851 device->ws->buffer_destroy(device->gfx_init);
2852
2853 radv_device_finish_border_color(device);
2854
2855 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2856 for (unsigned q = 0; q < device->queue_count[i]; q++)
2857 radv_queue_finish(&device->queues[i][q]);
2858 if (device->queue_count[i])
2859 vk_free(&device->vk.alloc, device->queues[i]);
2860 if (device->empty_cs[i])
2861 device->ws->cs_destroy(device->empty_cs[i]);
2862 }
2863 radv_device_finish_meta(device);
2864
2865 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
2866 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2867
2868 radv_destroy_shader_slabs(device);
2869
2870 pthread_cond_destroy(&device->timeline_cond);
2871 radv_bo_list_finish(&device->bo_list);
2872
2873 radv_thread_trace_finish(device);
2874
2875 vk_free(&device->vk.alloc, device);
2876 }
2877
2878 VkResult radv_EnumerateInstanceLayerProperties(
2879 uint32_t* pPropertyCount,
2880 VkLayerProperties* pProperties)
2881 {
2882 if (pProperties == NULL) {
2883 *pPropertyCount = 0;
2884 return VK_SUCCESS;
2885 }
2886
2887 /* None supported at this time */
2888 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2889 }
2890
2891 VkResult radv_EnumerateDeviceLayerProperties(
2892 VkPhysicalDevice physicalDevice,
2893 uint32_t* pPropertyCount,
2894 VkLayerProperties* pProperties)
2895 {
2896 if (pProperties == NULL) {
2897 *pPropertyCount = 0;
2898 return VK_SUCCESS;
2899 }
2900
2901 /* None supported at this time */
2902 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2903 }
2904
2905 void radv_GetDeviceQueue2(
2906 VkDevice _device,
2907 const VkDeviceQueueInfo2* pQueueInfo,
2908 VkQueue* pQueue)
2909 {
2910 RADV_FROM_HANDLE(radv_device, device, _device);
2911 struct radv_queue *queue;
2912
2913 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
2914 if (pQueueInfo->flags != queue->flags) {
2915 /* From the Vulkan 1.1.70 spec:
2916 *
2917 * "The queue returned by vkGetDeviceQueue2 must have the same
2918 * flags value from this structure as that used at device
2919 * creation time in a VkDeviceQueueCreateInfo instance. If no
2920 * matching flags were specified at device creation time then
2921 * pQueue will return VK_NULL_HANDLE."
2922 */
2923 *pQueue = VK_NULL_HANDLE;
2924 return;
2925 }
2926
2927 *pQueue = radv_queue_to_handle(queue);
2928 }
2929
2930 void radv_GetDeviceQueue(
2931 VkDevice _device,
2932 uint32_t queueFamilyIndex,
2933 uint32_t queueIndex,
2934 VkQueue* pQueue)
2935 {
2936 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
2937 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
2938 .queueFamilyIndex = queueFamilyIndex,
2939 .queueIndex = queueIndex
2940 };
2941
2942 radv_GetDeviceQueue2(_device, &info, pQueue);
2943 }
2944
2945 static void
2946 fill_geom_tess_rings(struct radv_queue *queue,
2947 uint32_t *map,
2948 bool add_sample_positions,
2949 uint32_t esgs_ring_size,
2950 struct radeon_winsys_bo *esgs_ring_bo,
2951 uint32_t gsvs_ring_size,
2952 struct radeon_winsys_bo *gsvs_ring_bo,
2953 uint32_t tess_factor_ring_size,
2954 uint32_t tess_offchip_ring_offset,
2955 uint32_t tess_offchip_ring_size,
2956 struct radeon_winsys_bo *tess_rings_bo)
2957 {
2958 uint32_t *desc = &map[4];
2959
2960 if (esgs_ring_bo) {
2961 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
2962
2963 /* stride 0, num records - size, add tid, swizzle, elsize4,
2964 index stride 64 */
2965 desc[0] = esgs_va;
2966 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
2967 S_008F04_SWIZZLE_ENABLE(true);
2968 desc[2] = esgs_ring_size;
2969 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2970 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2971 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2972 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2973 S_008F0C_INDEX_STRIDE(3) |
2974 S_008F0C_ADD_TID_ENABLE(1);
2975
2976 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2977 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2978 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
2979 S_008F0C_RESOURCE_LEVEL(1);
2980 } else {
2981 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2982 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2983 S_008F0C_ELEMENT_SIZE(1);
2984 }
2985
2986 /* GS entry for ES->GS ring */
2987 /* stride 0, num records - size, elsize0,
2988 index stride 0 */
2989 desc[4] = esgs_va;
2990 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32);
2991 desc[6] = esgs_ring_size;
2992 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2993 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2994 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2995 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2996
2997 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2998 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2999 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3000 S_008F0C_RESOURCE_LEVEL(1);
3001 } else {
3002 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3003 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3004 }
3005 }
3006
3007 desc += 8;
3008
3009 if (gsvs_ring_bo) {
3010 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
3011
3012 /* VS entry for GS->VS ring */
3013 /* stride 0, num records - size, elsize0,
3014 index stride 0 */
3015 desc[0] = gsvs_va;
3016 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32);
3017 desc[2] = gsvs_ring_size;
3018 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3019 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3020 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3021 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3022
3023 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3024 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3025 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3026 S_008F0C_RESOURCE_LEVEL(1);
3027 } else {
3028 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3029 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3030 }
3031
3032 /* stride gsvs_itemsize, num records 64
3033 elsize 4, index stride 16 */
3034 /* shader will patch stride and desc[2] */
3035 desc[4] = gsvs_va;
3036 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32) |
3037 S_008F04_SWIZZLE_ENABLE(1);
3038 desc[6] = 0;
3039 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3040 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3041 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3042 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
3043 S_008F0C_INDEX_STRIDE(1) |
3044 S_008F0C_ADD_TID_ENABLE(true);
3045
3046 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3047 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3048 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3049 S_008F0C_RESOURCE_LEVEL(1);
3050 } else {
3051 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3052 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
3053 S_008F0C_ELEMENT_SIZE(1);
3054 }
3055
3056 }
3057
3058 desc += 8;
3059
3060 if (tess_rings_bo) {
3061 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
3062 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
3063
3064 desc[0] = tess_va;
3065 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32);
3066 desc[2] = tess_factor_ring_size;
3067 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3068 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3069 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3070 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3071
3072 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3073 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3074 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3075 S_008F0C_RESOURCE_LEVEL(1);
3076 } else {
3077 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3078 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3079 }
3080
3081 desc[4] = tess_offchip_va;
3082 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32);
3083 desc[6] = tess_offchip_ring_size;
3084 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3085 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3086 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3087 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3088
3089 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3090 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3091 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3092 S_008F0C_RESOURCE_LEVEL(1);
3093 } else {
3094 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3095 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3096 }
3097 }
3098
3099 desc += 8;
3100
3101 if (add_sample_positions) {
3102 /* add sample positions after all rings */
3103 memcpy(desc, queue->device->sample_locations_1x, 8);
3104 desc += 2;
3105 memcpy(desc, queue->device->sample_locations_2x, 16);
3106 desc += 4;
3107 memcpy(desc, queue->device->sample_locations_4x, 32);
3108 desc += 8;
3109 memcpy(desc, queue->device->sample_locations_8x, 64);
3110 }
3111 }
3112
3113 static unsigned
3114 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
3115 {
3116 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 &&
3117 device->physical_device->rad_info.family != CHIP_CARRIZO &&
3118 device->physical_device->rad_info.family != CHIP_STONEY;
3119 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
3120 unsigned max_offchip_buffers;
3121 unsigned offchip_granularity;
3122 unsigned hs_offchip_param;
3123
3124 /*
3125 * Per RadeonSI:
3126 * This must be one less than the maximum number due to a hw limitation.
3127 * Various hardware bugs need thGFX7
3128 *
3129 * Per AMDVLK:
3130 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
3131 * Gfx7 should limit max_offchip_buffers to 508
3132 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
3133 *
3134 * Follow AMDVLK here.
3135 */
3136 if (device->physical_device->rad_info.chip_class >= GFX10) {
3137 max_offchip_buffers_per_se = 256;
3138 } else if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
3139 device->physical_device->rad_info.chip_class == GFX7 ||
3140 device->physical_device->rad_info.chip_class == GFX6)
3141 --max_offchip_buffers_per_se;
3142
3143 max_offchip_buffers = max_offchip_buffers_per_se *
3144 device->physical_device->rad_info.max_se;
3145
3146 /* Hawaii has a bug with offchip buffers > 256 that can be worked
3147 * around by setting 4K granularity.
3148 */
3149 if (device->tess_offchip_block_dw_size == 4096) {
3150 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
3151 offchip_granularity = V_03093C_X_4K_DWORDS;
3152 } else {
3153 assert(device->tess_offchip_block_dw_size == 8192);
3154 offchip_granularity = V_03093C_X_8K_DWORDS;
3155 }
3156
3157 switch (device->physical_device->rad_info.chip_class) {
3158 case GFX6:
3159 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
3160 break;
3161 case GFX7:
3162 case GFX8:
3163 case GFX9:
3164 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
3165 break;
3166 case GFX10:
3167 break;
3168 default:
3169 break;
3170 }
3171
3172 *max_offchip_buffers_p = max_offchip_buffers;
3173 if (device->physical_device->rad_info.chip_class >= GFX10_3) {
3174 hs_offchip_param = S_03093C_OFFCHIP_BUFFERING_GFX103(max_offchip_buffers - 1) |
3175 S_03093C_OFFCHIP_GRANULARITY_GFX103(offchip_granularity);
3176 } else if (device->physical_device->rad_info.chip_class >= GFX7) {
3177 if (device->physical_device->rad_info.chip_class >= GFX8)
3178 --max_offchip_buffers;
3179 hs_offchip_param =
3180 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
3181 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
3182 } else {
3183 hs_offchip_param =
3184 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
3185 }
3186 return hs_offchip_param;
3187 }
3188
3189 static void
3190 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3191 struct radeon_winsys_bo *esgs_ring_bo,
3192 uint32_t esgs_ring_size,
3193 struct radeon_winsys_bo *gsvs_ring_bo,
3194 uint32_t gsvs_ring_size)
3195 {
3196 if (!esgs_ring_bo && !gsvs_ring_bo)
3197 return;
3198
3199 if (esgs_ring_bo)
3200 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
3201
3202 if (gsvs_ring_bo)
3203 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
3204
3205 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
3206 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
3207 radeon_emit(cs, esgs_ring_size >> 8);
3208 radeon_emit(cs, gsvs_ring_size >> 8);
3209 } else {
3210 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
3211 radeon_emit(cs, esgs_ring_size >> 8);
3212 radeon_emit(cs, gsvs_ring_size >> 8);
3213 }
3214 }
3215
3216 static void
3217 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3218 unsigned hs_offchip_param, unsigned tf_ring_size,
3219 struct radeon_winsys_bo *tess_rings_bo)
3220 {
3221 uint64_t tf_va;
3222
3223 if (!tess_rings_bo)
3224 return;
3225
3226 tf_va = radv_buffer_get_va(tess_rings_bo);
3227
3228 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
3229
3230 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
3231 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
3232 S_030938_SIZE(tf_ring_size / 4));
3233 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
3234 tf_va >> 8);
3235
3236 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3237 radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3238 S_030984_BASE_HI(tf_va >> 40));
3239 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
3240 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
3241 S_030944_BASE_HI(tf_va >> 40));
3242 }
3243 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
3244 hs_offchip_param);
3245 } else {
3246 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
3247 S_008988_SIZE(tf_ring_size / 4));
3248 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
3249 tf_va >> 8);
3250 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3251 hs_offchip_param);
3252 }
3253 }
3254
3255 static void
3256 radv_emit_graphics_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3257 uint32_t size_per_wave, uint32_t waves,
3258 struct radeon_winsys_bo *scratch_bo)
3259 {
3260 if (queue->queue_family_index != RADV_QUEUE_GENERAL)
3261 return;
3262
3263 if (!scratch_bo)
3264 return;
3265
3266 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
3267
3268 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
3269 S_0286E8_WAVES(waves) |
3270 S_0286E8_WAVESIZE(round_up_u32(size_per_wave, 1024)));
3271 }
3272
3273 static void
3274 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3275 uint32_t size_per_wave, uint32_t waves,
3276 struct radeon_winsys_bo *compute_scratch_bo)
3277 {
3278 uint64_t scratch_va;
3279
3280 if (!compute_scratch_bo)
3281 return;
3282
3283 scratch_va = radv_buffer_get_va(compute_scratch_bo);
3284
3285 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
3286
3287 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
3288 radeon_emit(cs, scratch_va);
3289 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
3290 S_008F04_SWIZZLE_ENABLE(1));
3291
3292 radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
3293 S_00B860_WAVES(waves) |
3294 S_00B860_WAVESIZE(round_up_u32(size_per_wave, 1024)));
3295 }
3296
3297 static void
3298 radv_emit_global_shader_pointers(struct radv_queue *queue,
3299 struct radeon_cmdbuf *cs,
3300 struct radeon_winsys_bo *descriptor_bo)
3301 {
3302 uint64_t va;
3303
3304 if (!descriptor_bo)
3305 return;
3306
3307 va = radv_buffer_get_va(descriptor_bo);
3308
3309 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
3310
3311 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3312 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3313 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3314 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
3315 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
3316
3317 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3318 radv_emit_shader_pointer(queue->device, cs, regs[i],
3319 va, true);
3320 }
3321 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
3322 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3323 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3324 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
3325 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
3326
3327 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3328 radv_emit_shader_pointer(queue->device, cs, regs[i],
3329 va, true);
3330 }
3331 } else {
3332 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3333 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3334 R_00B230_SPI_SHADER_USER_DATA_GS_0,
3335 R_00B330_SPI_SHADER_USER_DATA_ES_0,
3336 R_00B430_SPI_SHADER_USER_DATA_HS_0,
3337 R_00B530_SPI_SHADER_USER_DATA_LS_0};
3338
3339 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3340 radv_emit_shader_pointer(queue->device, cs, regs[i],
3341 va, true);
3342 }
3343 }
3344 }
3345
3346 static void
3347 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
3348 {
3349 struct radv_device *device = queue->device;
3350
3351 if (device->gfx_init) {
3352 uint64_t va = radv_buffer_get_va(device->gfx_init);
3353
3354 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
3355 radeon_emit(cs, va);
3356 radeon_emit(cs, va >> 32);
3357 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
3358
3359 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
3360 } else {
3361 si_emit_graphics(device, cs);
3362 }
3363 }
3364
3365 static void
3366 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
3367 {
3368 struct radv_physical_device *physical_device = queue->device->physical_device;
3369 si_emit_compute(physical_device, cs);
3370 }
3371
3372 static VkResult
3373 radv_get_preamble_cs(struct radv_queue *queue,
3374 uint32_t scratch_size_per_wave,
3375 uint32_t scratch_waves,
3376 uint32_t compute_scratch_size_per_wave,
3377 uint32_t compute_scratch_waves,
3378 uint32_t esgs_ring_size,
3379 uint32_t gsvs_ring_size,
3380 bool needs_tess_rings,
3381 bool needs_gds,
3382 bool needs_gds_oa,
3383 bool needs_sample_positions,
3384 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
3385 struct radeon_cmdbuf **initial_preamble_cs,
3386 struct radeon_cmdbuf **continue_preamble_cs)
3387 {
3388 struct radeon_winsys_bo *scratch_bo = NULL;
3389 struct radeon_winsys_bo *descriptor_bo = NULL;
3390 struct radeon_winsys_bo *compute_scratch_bo = NULL;
3391 struct radeon_winsys_bo *esgs_ring_bo = NULL;
3392 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
3393 struct radeon_winsys_bo *tess_rings_bo = NULL;
3394 struct radeon_winsys_bo *gds_bo = NULL;
3395 struct radeon_winsys_bo *gds_oa_bo = NULL;
3396 struct radeon_cmdbuf *dest_cs[3] = {0};
3397 bool add_tess_rings = false, add_gds = false, add_gds_oa = false, add_sample_positions = false;
3398 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
3399 unsigned max_offchip_buffers;
3400 unsigned hs_offchip_param = 0;
3401 unsigned tess_offchip_ring_offset;
3402 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
3403 if (!queue->has_tess_rings) {
3404 if (needs_tess_rings)
3405 add_tess_rings = true;
3406 }
3407 if (!queue->has_gds) {
3408 if (needs_gds)
3409 add_gds = true;
3410 }
3411 if (!queue->has_gds_oa) {
3412 if (needs_gds_oa)
3413 add_gds_oa = true;
3414 }
3415 if (!queue->has_sample_positions) {
3416 if (needs_sample_positions)
3417 add_sample_positions = true;
3418 }
3419 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
3420 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
3421 &max_offchip_buffers);
3422 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
3423 tess_offchip_ring_size = max_offchip_buffers *
3424 queue->device->tess_offchip_block_dw_size * 4;
3425
3426 scratch_size_per_wave = MAX2(scratch_size_per_wave, queue->scratch_size_per_wave);
3427 if (scratch_size_per_wave)
3428 scratch_waves = MIN2(scratch_waves, UINT32_MAX / scratch_size_per_wave);
3429 else
3430 scratch_waves = 0;
3431
3432 compute_scratch_size_per_wave = MAX2(compute_scratch_size_per_wave, queue->compute_scratch_size_per_wave);
3433 if (compute_scratch_size_per_wave)
3434 compute_scratch_waves = MIN2(compute_scratch_waves, UINT32_MAX / compute_scratch_size_per_wave);
3435 else
3436 compute_scratch_waves = 0;
3437
3438 if (scratch_size_per_wave <= queue->scratch_size_per_wave &&
3439 scratch_waves <= queue->scratch_waves &&
3440 compute_scratch_size_per_wave <= queue->compute_scratch_size_per_wave &&
3441 compute_scratch_waves <= queue->compute_scratch_waves &&
3442 esgs_ring_size <= queue->esgs_ring_size &&
3443 gsvs_ring_size <= queue->gsvs_ring_size &&
3444 !add_tess_rings && !add_gds && !add_gds_oa && !add_sample_positions &&
3445 queue->initial_preamble_cs) {
3446 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
3447 *initial_preamble_cs = queue->initial_preamble_cs;
3448 *continue_preamble_cs = queue->continue_preamble_cs;
3449 if (!scratch_size_per_wave && !compute_scratch_size_per_wave &&
3450 !esgs_ring_size && !gsvs_ring_size && !needs_tess_rings &&
3451 !needs_gds && !needs_gds_oa && !needs_sample_positions)
3452 *continue_preamble_cs = NULL;
3453 return VK_SUCCESS;
3454 }
3455
3456 uint32_t scratch_size = scratch_size_per_wave * scratch_waves;
3457 uint32_t queue_scratch_size = queue->scratch_size_per_wave * queue->scratch_waves;
3458 if (scratch_size > queue_scratch_size) {
3459 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
3460 scratch_size,
3461 4096,
3462 RADEON_DOMAIN_VRAM,
3463 ring_bo_flags,
3464 RADV_BO_PRIORITY_SCRATCH);
3465 if (!scratch_bo)
3466 goto fail;
3467 } else
3468 scratch_bo = queue->scratch_bo;
3469
3470 uint32_t compute_scratch_size = compute_scratch_size_per_wave