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radv: track and report if a logical device is lost
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "dirent.h"
29 #include <errno.h>
30 #include <fcntl.h>
31 #include <linux/audit.h>
32 #include <linux/bpf.h>
33 #include <linux/filter.h>
34 #include <linux/seccomp.h>
35 #include <linux/unistd.h>
36 #include <stdatomic.h>
37 #include <stdbool.h>
38 #include <stddef.h>
39 #include <stdio.h>
40 #include <string.h>
41 #include <sys/prctl.h>
42 #include <sys/wait.h>
43 #include <unistd.h>
44 #include <fcntl.h>
45
46 #include "radv_debug.h"
47 #include "radv_private.h"
48 #include "radv_shader.h"
49 #include "radv_cs.h"
50 #include "util/disk_cache.h"
51 #include "vk_util.h"
52 #include <xf86drm.h>
53 #include <amdgpu.h>
54 #include "drm-uapi/amdgpu_drm.h"
55 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
56 #include "winsys/null/radv_null_winsys_public.h"
57 #include "ac_llvm_util.h"
58 #include "vk_format.h"
59 #include "sid.h"
60 #include "git_sha1.h"
61 #include "util/build_id.h"
62 #include "util/debug.h"
63 #include "util/mesa-sha1.h"
64 #include "util/timespec.h"
65 #include "util/u_atomic.h"
66 #include "compiler/glsl_types.h"
67 #include "util/driconf.h"
68
69 static struct radv_timeline_point *
70 radv_timeline_find_point_at_least_locked(struct radv_device *device,
71 struct radv_timeline *timeline,
72 uint64_t p);
73
74 static struct radv_timeline_point *
75 radv_timeline_add_point_locked(struct radv_device *device,
76 struct radv_timeline *timeline,
77 uint64_t p);
78
79 static void
80 radv_timeline_trigger_waiters_locked(struct radv_timeline *timeline,
81 struct list_head *processing_list);
82
83 static
84 void radv_destroy_semaphore_part(struct radv_device *device,
85 struct radv_semaphore_part *part);
86
87 static VkResult
88 radv_create_pthread_cond(pthread_cond_t *cond);
89
90 uint64_t radv_get_current_time(void)
91 {
92 struct timespec tv;
93 clock_gettime(CLOCK_MONOTONIC, &tv);
94 return tv.tv_nsec + tv.tv_sec*1000000000ull;
95 }
96
97 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
98 {
99 uint64_t current_time = radv_get_current_time();
100
101 timeout = MIN2(UINT64_MAX - current_time, timeout);
102
103 return current_time + timeout;
104 }
105
106 static int
107 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
108 {
109 struct mesa_sha1 ctx;
110 unsigned char sha1[20];
111 unsigned ptr_size = sizeof(void*);
112
113 memset(uuid, 0, VK_UUID_SIZE);
114 _mesa_sha1_init(&ctx);
115
116 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
117 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
118 return -1;
119
120 _mesa_sha1_update(&ctx, &family, sizeof(family));
121 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
122 _mesa_sha1_final(&ctx, sha1);
123
124 memcpy(uuid, sha1, VK_UUID_SIZE);
125 return 0;
126 }
127
128 static void
129 radv_get_driver_uuid(void *uuid)
130 {
131 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
132 }
133
134 static void
135 radv_get_device_uuid(struct radeon_info *info, void *uuid)
136 {
137 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
138 }
139
140 static uint64_t
141 radv_get_visible_vram_size(struct radv_physical_device *device)
142 {
143 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
144 }
145
146 static uint64_t
147 radv_get_vram_size(struct radv_physical_device *device)
148 {
149 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
150 }
151
152 static void
153 radv_physical_device_init_mem_types(struct radv_physical_device *device)
154 {
155 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
156 uint64_t vram_size = radv_get_vram_size(device);
157 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
158 device->memory_properties.memoryHeapCount = 0;
159 if (vram_size > 0) {
160 vram_index = device->memory_properties.memoryHeapCount++;
161 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
162 .size = vram_size,
163 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
164 };
165 }
166
167 if (device->rad_info.gart_size > 0) {
168 gart_index = device->memory_properties.memoryHeapCount++;
169 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
170 .size = device->rad_info.gart_size,
171 .flags = 0,
172 };
173 }
174
175 if (visible_vram_size) {
176 visible_vram_index = device->memory_properties.memoryHeapCount++;
177 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
178 .size = visible_vram_size,
179 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
180 };
181 }
182
183 unsigned type_count = 0;
184
185 if (vram_index >= 0 || visible_vram_index >= 0) {
186 device->memory_domains[type_count] = RADEON_DOMAIN_VRAM;
187 device->memory_flags[type_count] = RADEON_FLAG_NO_CPU_ACCESS;
188 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
189 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
190 .heapIndex = vram_index >= 0 ? vram_index : visible_vram_index,
191 };
192 }
193
194 if (gart_index >= 0) {
195 device->memory_domains[type_count] = RADEON_DOMAIN_GTT;
196 device->memory_flags[type_count] = RADEON_FLAG_GTT_WC | RADEON_FLAG_CPU_ACCESS;
197 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
198 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
199 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
200 .heapIndex = gart_index,
201 };
202 }
203 if (visible_vram_index >= 0) {
204 device->memory_domains[type_count] = RADEON_DOMAIN_VRAM;
205 device->memory_flags[type_count] = RADEON_FLAG_CPU_ACCESS;
206 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
207 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
208 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
209 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
210 .heapIndex = visible_vram_index,
211 };
212 }
213
214 if (gart_index >= 0) {
215 device->memory_domains[type_count] = RADEON_DOMAIN_GTT;
216 device->memory_flags[type_count] = RADEON_FLAG_CPU_ACCESS;
217 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
218 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
219 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
220 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
221 .heapIndex = gart_index,
222 };
223 }
224 device->memory_properties.memoryTypeCount = type_count;
225
226 if (device->rad_info.has_l2_uncached) {
227 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
228 VkMemoryType mem_type = device->memory_properties.memoryTypes[i];
229
230 if ((mem_type.propertyFlags & (VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
231 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT)) ||
232 mem_type.propertyFlags == VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT) {
233
234 VkMemoryPropertyFlags property_flags = mem_type.propertyFlags |
235 VK_MEMORY_PROPERTY_DEVICE_COHERENT_BIT_AMD |
236 VK_MEMORY_PROPERTY_DEVICE_UNCACHED_BIT_AMD;
237
238 device->memory_domains[type_count] = device->memory_domains[i];
239 device->memory_flags[type_count] = device->memory_flags[i] | RADEON_FLAG_VA_UNCACHED;
240 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
241 .propertyFlags = property_flags,
242 .heapIndex = mem_type.heapIndex,
243 };
244 }
245 }
246 device->memory_properties.memoryTypeCount = type_count;
247 }
248 }
249
250 static const char *
251 radv_get_compiler_string(struct radv_physical_device *pdevice)
252 {
253 if (!pdevice->use_llvm) {
254 /* Some games like SotTR apply shader workarounds if the LLVM
255 * version is too old or if the LLVM version string is
256 * missing. This gives 2-5% performance with SotTR and ACO.
257 */
258 if (driQueryOptionb(&pdevice->instance->dri_options,
259 "radv_report_llvm9_version_string")) {
260 return "ACO/LLVM 9.0.1";
261 }
262
263 return "ACO";
264 }
265
266 return "LLVM " MESA_LLVM_VERSION_STRING;
267 }
268
269 static VkResult
270 radv_physical_device_try_create(struct radv_instance *instance,
271 drmDevicePtr drm_device,
272 struct radv_physical_device **device_out)
273 {
274 VkResult result;
275 int fd = -1;
276 int master_fd = -1;
277
278 if (drm_device) {
279 const char *path = drm_device->nodes[DRM_NODE_RENDER];
280 drmVersionPtr version;
281
282 fd = open(path, O_RDWR | O_CLOEXEC);
283 if (fd < 0) {
284 if (instance->debug_flags & RADV_DEBUG_STARTUP)
285 radv_logi("Could not open device '%s'", path);
286
287 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
288 }
289
290 version = drmGetVersion(fd);
291 if (!version) {
292 close(fd);
293
294 if (instance->debug_flags & RADV_DEBUG_STARTUP)
295 radv_logi("Could not get the kernel driver version for device '%s'", path);
296
297 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
298 "failed to get version %s: %m", path);
299 }
300
301 if (strcmp(version->name, "amdgpu")) {
302 drmFreeVersion(version);
303 close(fd);
304
305 if (instance->debug_flags & RADV_DEBUG_STARTUP)
306 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
307
308 return VK_ERROR_INCOMPATIBLE_DRIVER;
309 }
310 drmFreeVersion(version);
311
312 if (instance->debug_flags & RADV_DEBUG_STARTUP)
313 radv_logi("Found compatible device '%s'.", path);
314 }
315
316 struct radv_physical_device *device =
317 vk_zalloc2(&instance->alloc, NULL, sizeof(*device), 8,
318 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
319 if (!device) {
320 result = vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
321 goto fail_fd;
322 }
323
324 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
325 device->instance = instance;
326
327 if (drm_device) {
328 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
329 instance->perftest_flags);
330 } else {
331 device->ws = radv_null_winsys_create();
332 }
333
334 if (!device->ws) {
335 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
336 "failed to initialize winsys");
337 goto fail_alloc;
338 }
339
340 if (drm_device && instance->enabled_extensions.KHR_display) {
341 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
342 if (master_fd >= 0) {
343 uint32_t accel_working = 0;
344 struct drm_amdgpu_info request = {
345 .return_pointer = (uintptr_t)&accel_working,
346 .return_size = sizeof(accel_working),
347 .query = AMDGPU_INFO_ACCEL_WORKING
348 };
349
350 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
351 close(master_fd);
352 master_fd = -1;
353 }
354 }
355 }
356
357 device->master_fd = master_fd;
358 device->local_fd = fd;
359 device->ws->query_info(device->ws, &device->rad_info);
360
361 device->use_llvm = instance->debug_flags & RADV_DEBUG_LLVM;
362
363 snprintf(device->name, sizeof(device->name),
364 "AMD RADV %s (%s)",
365 device->rad_info.name, radv_get_compiler_string(device));
366
367 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
368 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
369 "cannot generate UUID");
370 goto fail_wsi;
371 }
372
373 /* These flags affect shader compilation. */
374 uint64_t shader_env_flags = (device->use_llvm ? 0 : 0x2);
375
376 /* The gpu id is already embedded in the uuid so we just pass "radv"
377 * when creating the cache.
378 */
379 char buf[VK_UUID_SIZE * 2 + 1];
380 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
381 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
382
383 if (device->rad_info.chip_class < GFX8 || !device->use_llvm)
384 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
385
386 radv_get_driver_uuid(&device->driver_uuid);
387 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
388
389 device->out_of_order_rast_allowed = device->rad_info.has_out_of_order_rast &&
390 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
391
392 device->dcc_msaa_allowed =
393 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
394
395 device->use_ngg = device->rad_info.chip_class >= GFX10 &&
396 device->rad_info.family != CHIP_NAVI14 &&
397 !(device->instance->debug_flags & RADV_DEBUG_NO_NGG);
398
399 /* TODO: Implement NGG GS with ACO. */
400 device->use_ngg_gs = device->use_ngg && device->use_llvm;
401 device->use_ngg_streamout = false;
402
403 /* Determine the number of threads per wave for all stages. */
404 device->cs_wave_size = 64;
405 device->ps_wave_size = 64;
406 device->ge_wave_size = 64;
407
408 if (device->rad_info.chip_class >= GFX10) {
409 if (device->instance->perftest_flags & RADV_PERFTEST_CS_WAVE_32)
410 device->cs_wave_size = 32;
411
412 /* For pixel shaders, wave64 is recommanded. */
413 if (device->instance->perftest_flags & RADV_PERFTEST_PS_WAVE_32)
414 device->ps_wave_size = 32;
415
416 if (device->instance->perftest_flags & RADV_PERFTEST_GE_WAVE_32)
417 device->ge_wave_size = 32;
418 }
419
420 radv_physical_device_init_mem_types(device);
421
422 radv_physical_device_get_supported_extensions(device,
423 &device->supported_extensions);
424
425 if (drm_device)
426 device->bus_info = *drm_device->businfo.pci;
427
428 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
429 ac_print_gpu_info(&device->rad_info);
430
431 /* The WSI is structured as a layer on top of the driver, so this has
432 * to be the last part of initialization (at least until we get other
433 * semi-layers).
434 */
435 result = radv_init_wsi(device);
436 if (result != VK_SUCCESS) {
437 vk_error(instance, result);
438 goto fail_disk_cache;
439 }
440
441 *device_out = device;
442
443 return VK_SUCCESS;
444
445 fail_disk_cache:
446 disk_cache_destroy(device->disk_cache);
447 fail_wsi:
448 device->ws->destroy(device->ws);
449 fail_alloc:
450 vk_free(&instance->alloc, device);
451 fail_fd:
452 if (fd != -1)
453 close(fd);
454 if (master_fd != -1)
455 close(master_fd);
456 return result;
457 }
458
459 static void
460 radv_physical_device_destroy(struct radv_physical_device *device)
461 {
462 radv_finish_wsi(device);
463 device->ws->destroy(device->ws);
464 disk_cache_destroy(device->disk_cache);
465 close(device->local_fd);
466 if (device->master_fd != -1)
467 close(device->master_fd);
468 vk_free(&device->instance->alloc, device);
469 }
470
471 static void *
472 default_alloc_func(void *pUserData, size_t size, size_t align,
473 VkSystemAllocationScope allocationScope)
474 {
475 return malloc(size);
476 }
477
478 static void *
479 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
480 size_t align, VkSystemAllocationScope allocationScope)
481 {
482 return realloc(pOriginal, size);
483 }
484
485 static void
486 default_free_func(void *pUserData, void *pMemory)
487 {
488 free(pMemory);
489 }
490
491 static const VkAllocationCallbacks default_alloc = {
492 .pUserData = NULL,
493 .pfnAllocation = default_alloc_func,
494 .pfnReallocation = default_realloc_func,
495 .pfnFree = default_free_func,
496 };
497
498 static const struct debug_control radv_debug_options[] = {
499 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
500 {"nodcc", RADV_DEBUG_NO_DCC},
501 {"shaders", RADV_DEBUG_DUMP_SHADERS},
502 {"nocache", RADV_DEBUG_NO_CACHE},
503 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
504 {"nohiz", RADV_DEBUG_NO_HIZ},
505 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
506 {"allbos", RADV_DEBUG_ALL_BOS},
507 {"noibs", RADV_DEBUG_NO_IBS},
508 {"spirv", RADV_DEBUG_DUMP_SPIRV},
509 {"vmfaults", RADV_DEBUG_VM_FAULTS},
510 {"zerovram", RADV_DEBUG_ZERO_VRAM},
511 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
512 {"preoptir", RADV_DEBUG_PREOPTIR},
513 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
514 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
515 {"info", RADV_DEBUG_INFO},
516 {"errors", RADV_DEBUG_ERRORS},
517 {"startup", RADV_DEBUG_STARTUP},
518 {"checkir", RADV_DEBUG_CHECKIR},
519 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
520 {"nobinning", RADV_DEBUG_NOBINNING},
521 {"nongg", RADV_DEBUG_NO_NGG},
522 {"allentrypoints", RADV_DEBUG_ALL_ENTRYPOINTS},
523 {"metashaders", RADV_DEBUG_DUMP_META_SHADERS},
524 {"nomemorycache", RADV_DEBUG_NO_MEMORY_CACHE},
525 {"llvm", RADV_DEBUG_LLVM},
526 {"forcecompress", RADV_DEBUG_FORCE_COMPRESS},
527 {NULL, 0}
528 };
529
530 const char *
531 radv_get_debug_option_name(int id)
532 {
533 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
534 return radv_debug_options[id].string;
535 }
536
537 static const struct debug_control radv_perftest_options[] = {
538 {"localbos", RADV_PERFTEST_LOCAL_BOS},
539 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
540 {"bolist", RADV_PERFTEST_BO_LIST},
541 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
542 {"cswave32", RADV_PERFTEST_CS_WAVE_32},
543 {"pswave32", RADV_PERFTEST_PS_WAVE_32},
544 {"gewave32", RADV_PERFTEST_GE_WAVE_32},
545 {"dfsm", RADV_PERFTEST_DFSM},
546 {NULL, 0}
547 };
548
549 const char *
550 radv_get_perftest_option_name(int id)
551 {
552 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
553 return radv_perftest_options[id].string;
554 }
555
556 static void
557 radv_handle_per_app_options(struct radv_instance *instance,
558 const VkApplicationInfo *info)
559 {
560 const char *name = info ? info->pApplicationName : NULL;
561 const char *engine_name = info ? info->pEngineName : NULL;
562
563 if (name) {
564 if (!strcmp(name, "DOOM_VFR")) {
565 /* Work around a Doom VFR game bug */
566 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
567 } else if (!strcmp(name, "Fledge")) {
568 /*
569 * Zero VRAM for "The Surge 2"
570 *
571 * This avoid a hang when when rendering any level. Likely
572 * uninitialized data in an indirect draw.
573 */
574 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
575 } else if (!strcmp(name, "No Man's Sky")) {
576 /* Work around a NMS game bug */
577 instance->debug_flags |= RADV_DEBUG_DISCARD_TO_DEMOTE;
578 } else if (!strcmp(name, "DOOMEternal")) {
579 /* Zero VRAM for Doom Eternal to fix rendering issues. */
580 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
581 } else if (!strcmp(name, "Red Dead Redemption 2")) {
582 /* Work around a RDR2 game bug */
583 instance->debug_flags |= RADV_DEBUG_DISCARD_TO_DEMOTE;
584 }
585 }
586
587 if (engine_name) {
588 if (!strcmp(engine_name, "vkd3d")) {
589 /* Zero VRAM for all VKD3D (DX12->VK) games to fix
590 * rendering issues.
591 */
592 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
593 } else if (!strcmp(engine_name, "Quantic Dream Engine")) {
594 /* Fix various artifacts in Detroit: Become Human */
595 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM |
596 RADV_DEBUG_DISCARD_TO_DEMOTE;
597 }
598 }
599
600 instance->enable_mrt_output_nan_fixup =
601 driQueryOptionb(&instance->dri_options,
602 "radv_enable_mrt_output_nan_fixup");
603
604 if (driQueryOptionb(&instance->dri_options, "radv_no_dynamic_bounds"))
605 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
606 }
607
608 static const char radv_dri_options_xml[] =
609 DRI_CONF_BEGIN
610 DRI_CONF_SECTION_PERFORMANCE
611 DRI_CONF_ADAPTIVE_SYNC("true")
612 DRI_CONF_VK_X11_OVERRIDE_MIN_IMAGE_COUNT(0)
613 DRI_CONF_VK_X11_STRICT_IMAGE_COUNT("false")
614 DRI_CONF_VK_X11_ENSURE_MIN_IMAGE_COUNT("false")
615 DRI_CONF_RADV_REPORT_LLVM9_VERSION_STRING("false")
616 DRI_CONF_RADV_ENABLE_MRT_OUTPUT_NAN_FIXUP("false")
617 DRI_CONF_RADV_NO_DYNAMIC_BOUNDS("false")
618 DRI_CONF_RADV_OVERRIDE_UNIFORM_OFFSET_ALIGNMENT(0)
619 DRI_CONF_SECTION_END
620
621 DRI_CONF_SECTION_DEBUG
622 DRI_CONF_VK_WSI_FORCE_BGRA8_UNORM_FIRST("false")
623 DRI_CONF_SECTION_END
624 DRI_CONF_END;
625
626 static void radv_init_dri_options(struct radv_instance *instance)
627 {
628 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
629 driParseConfigFiles(&instance->dri_options,
630 &instance->available_dri_options,
631 0, "radv", NULL,
632 instance->applicationName,
633 instance->applicationVersion,
634 instance->engineName,
635 instance->engineVersion);
636 }
637
638 VkResult radv_CreateInstance(
639 const VkInstanceCreateInfo* pCreateInfo,
640 const VkAllocationCallbacks* pAllocator,
641 VkInstance* pInstance)
642 {
643 struct radv_instance *instance;
644 VkResult result;
645
646 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
647 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
648 if (!instance)
649 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
650
651 vk_object_base_init(NULL, &instance->base, VK_OBJECT_TYPE_INSTANCE);
652
653 if (pAllocator)
654 instance->alloc = *pAllocator;
655 else
656 instance->alloc = default_alloc;
657
658 if (pCreateInfo->pApplicationInfo) {
659 const VkApplicationInfo *app = pCreateInfo->pApplicationInfo;
660
661 instance->applicationName =
662 vk_strdup(&instance->alloc, app->pApplicationName,
663 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
664 instance->applicationVersion = app->applicationVersion;
665
666 instance->engineName =
667 vk_strdup(&instance->alloc, app->pEngineName,
668 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
669 instance->engineVersion = app->engineVersion;
670 instance->apiVersion = app->apiVersion;
671 }
672
673 if (instance->apiVersion == 0)
674 instance->apiVersion = VK_API_VERSION_1_0;
675
676 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
677 radv_debug_options);
678
679 const char *radv_perftest_str = getenv("RADV_PERFTEST");
680 instance->perftest_flags = parse_debug_string(radv_perftest_str,
681 radv_perftest_options);
682
683 if (radv_perftest_str) {
684 /* Output warnings for famous RADV_PERFTEST options that no
685 * longer exist or are deprecated.
686 */
687 if (strstr(radv_perftest_str, "aco")) {
688 fprintf(stderr, "*******************************************************************************\n");
689 fprintf(stderr, "* WARNING: Unknown option RADV_PERFTEST='aco'. ACO is enabled by default now. *\n");
690 fprintf(stderr, "*******************************************************************************\n");
691 }
692 if (strstr(radv_perftest_str, "llvm")) {
693 fprintf(stderr, "*********************************************************************************\n");
694 fprintf(stderr, "* WARNING: Unknown option 'RADV_PERFTEST=llvm'. Did you mean 'RADV_DEBUG=llvm'? *\n");
695 fprintf(stderr, "*********************************************************************************\n");
696 abort();
697 }
698 }
699
700 if (instance->debug_flags & RADV_DEBUG_STARTUP)
701 radv_logi("Created an instance");
702
703 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
704 int idx;
705 for (idx = 0; idx < RADV_INSTANCE_EXTENSION_COUNT; idx++) {
706 if (!strcmp(pCreateInfo->ppEnabledExtensionNames[i],
707 radv_instance_extensions[idx].extensionName))
708 break;
709 }
710
711 if (idx >= RADV_INSTANCE_EXTENSION_COUNT ||
712 !radv_instance_extensions_supported.extensions[idx]) {
713 vk_object_base_finish(&instance->base);
714 vk_free2(&default_alloc, pAllocator, instance);
715 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
716 }
717
718 instance->enabled_extensions.extensions[idx] = true;
719 }
720
721 bool unchecked = instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS;
722
723 for (unsigned i = 0; i < ARRAY_SIZE(instance->dispatch.entrypoints); i++) {
724 /* Vulkan requires that entrypoints for extensions which have
725 * not been enabled must not be advertised.
726 */
727 if (!unchecked &&
728 !radv_instance_entrypoint_is_enabled(i, instance->apiVersion,
729 &instance->enabled_extensions)) {
730 instance->dispatch.entrypoints[i] = NULL;
731 } else {
732 instance->dispatch.entrypoints[i] =
733 radv_instance_dispatch_table.entrypoints[i];
734 }
735 }
736
737 for (unsigned i = 0; i < ARRAY_SIZE(instance->physical_device_dispatch.entrypoints); i++) {
738 /* Vulkan requires that entrypoints for extensions which have
739 * not been enabled must not be advertised.
740 */
741 if (!unchecked &&
742 !radv_physical_device_entrypoint_is_enabled(i, instance->apiVersion,
743 &instance->enabled_extensions)) {
744 instance->physical_device_dispatch.entrypoints[i] = NULL;
745 } else {
746 instance->physical_device_dispatch.entrypoints[i] =
747 radv_physical_device_dispatch_table.entrypoints[i];
748 }
749 }
750
751 for (unsigned i = 0; i < ARRAY_SIZE(instance->device_dispatch.entrypoints); i++) {
752 /* Vulkan requires that entrypoints for extensions which have
753 * not been enabled must not be advertised.
754 */
755 if (!unchecked &&
756 !radv_device_entrypoint_is_enabled(i, instance->apiVersion,
757 &instance->enabled_extensions, NULL)) {
758 instance->device_dispatch.entrypoints[i] = NULL;
759 } else {
760 instance->device_dispatch.entrypoints[i] =
761 radv_device_dispatch_table.entrypoints[i];
762 }
763 }
764
765 instance->physical_devices_enumerated = false;
766 list_inithead(&instance->physical_devices);
767
768 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
769 if (result != VK_SUCCESS) {
770 vk_object_base_finish(&instance->base);
771 vk_free2(&default_alloc, pAllocator, instance);
772 return vk_error(instance, result);
773 }
774
775 glsl_type_singleton_init_or_ref();
776
777 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
778
779 radv_init_dri_options(instance);
780 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
781
782 *pInstance = radv_instance_to_handle(instance);
783
784 return VK_SUCCESS;
785 }
786
787 void radv_DestroyInstance(
788 VkInstance _instance,
789 const VkAllocationCallbacks* pAllocator)
790 {
791 RADV_FROM_HANDLE(radv_instance, instance, _instance);
792
793 if (!instance)
794 return;
795
796 list_for_each_entry_safe(struct radv_physical_device, pdevice,
797 &instance->physical_devices, link) {
798 radv_physical_device_destroy(pdevice);
799 }
800
801 vk_free(&instance->alloc, instance->engineName);
802 vk_free(&instance->alloc, instance->applicationName);
803
804 VG(VALGRIND_DESTROY_MEMPOOL(instance));
805
806 glsl_type_singleton_decref();
807
808 driDestroyOptionCache(&instance->dri_options);
809 driDestroyOptionInfo(&instance->available_dri_options);
810
811 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
812
813 vk_object_base_finish(&instance->base);
814 vk_free(&instance->alloc, instance);
815 }
816
817 static VkResult
818 radv_enumerate_physical_devices(struct radv_instance *instance)
819 {
820 if (instance->physical_devices_enumerated)
821 return VK_SUCCESS;
822
823 instance->physical_devices_enumerated = true;
824
825 /* TODO: Check for more devices ? */
826 drmDevicePtr devices[8];
827 VkResult result = VK_SUCCESS;
828 int max_devices;
829
830 if (getenv("RADV_FORCE_FAMILY")) {
831 /* When RADV_FORCE_FAMILY is set, the driver creates a nul
832 * device that allows to test the compiler without having an
833 * AMDGPU instance.
834 */
835 struct radv_physical_device *pdevice;
836
837 result = radv_physical_device_try_create(instance, NULL, &pdevice);
838 if (result != VK_SUCCESS)
839 return result;
840
841 list_addtail(&pdevice->link, &instance->physical_devices);
842 return VK_SUCCESS;
843 }
844
845 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
846
847 if (instance->debug_flags & RADV_DEBUG_STARTUP)
848 radv_logi("Found %d drm nodes", max_devices);
849
850 if (max_devices < 1)
851 return vk_error(instance, VK_SUCCESS);
852
853 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
854 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
855 devices[i]->bustype == DRM_BUS_PCI &&
856 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
857
858 struct radv_physical_device *pdevice;
859 result = radv_physical_device_try_create(instance, devices[i],
860 &pdevice);
861 /* Incompatible DRM device, skip. */
862 if (result == VK_ERROR_INCOMPATIBLE_DRIVER) {
863 result = VK_SUCCESS;
864 continue;
865 }
866
867 /* Error creating the physical device, report the error. */
868 if (result != VK_SUCCESS)
869 break;
870
871 list_addtail(&pdevice->link, &instance->physical_devices);
872 }
873 }
874 drmFreeDevices(devices, max_devices);
875
876 /* If we successfully enumerated any devices, call it success */
877 return result;
878 }
879
880 VkResult radv_EnumeratePhysicalDevices(
881 VkInstance _instance,
882 uint32_t* pPhysicalDeviceCount,
883 VkPhysicalDevice* pPhysicalDevices)
884 {
885 RADV_FROM_HANDLE(radv_instance, instance, _instance);
886 VK_OUTARRAY_MAKE(out, pPhysicalDevices, pPhysicalDeviceCount);
887
888 VkResult result = radv_enumerate_physical_devices(instance);
889 if (result != VK_SUCCESS)
890 return result;
891
892 list_for_each_entry(struct radv_physical_device, pdevice,
893 &instance->physical_devices, link) {
894 vk_outarray_append(&out, i) {
895 *i = radv_physical_device_to_handle(pdevice);
896 }
897 }
898
899 return vk_outarray_status(&out);
900 }
901
902 VkResult radv_EnumeratePhysicalDeviceGroups(
903 VkInstance _instance,
904 uint32_t* pPhysicalDeviceGroupCount,
905 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
906 {
907 RADV_FROM_HANDLE(radv_instance, instance, _instance);
908 VK_OUTARRAY_MAKE(out, pPhysicalDeviceGroupProperties,
909 pPhysicalDeviceGroupCount);
910
911 VkResult result = radv_enumerate_physical_devices(instance);
912 if (result != VK_SUCCESS)
913 return result;
914
915 list_for_each_entry(struct radv_physical_device, pdevice,
916 &instance->physical_devices, link) {
917 vk_outarray_append(&out, p) {
918 p->physicalDeviceCount = 1;
919 memset(p->physicalDevices, 0, sizeof(p->physicalDevices));
920 p->physicalDevices[0] = radv_physical_device_to_handle(pdevice);
921 p->subsetAllocation = false;
922 }
923 }
924
925 return vk_outarray_status(&out);
926 }
927
928 void radv_GetPhysicalDeviceFeatures(
929 VkPhysicalDevice physicalDevice,
930 VkPhysicalDeviceFeatures* pFeatures)
931 {
932 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
933 memset(pFeatures, 0, sizeof(*pFeatures));
934
935 *pFeatures = (VkPhysicalDeviceFeatures) {
936 .robustBufferAccess = true,
937 .fullDrawIndexUint32 = true,
938 .imageCubeArray = true,
939 .independentBlend = true,
940 .geometryShader = true,
941 .tessellationShader = true,
942 .sampleRateShading = true,
943 .dualSrcBlend = true,
944 .logicOp = true,
945 .multiDrawIndirect = true,
946 .drawIndirectFirstInstance = true,
947 .depthClamp = true,
948 .depthBiasClamp = true,
949 .fillModeNonSolid = true,
950 .depthBounds = true,
951 .wideLines = true,
952 .largePoints = true,
953 .alphaToOne = true,
954 .multiViewport = true,
955 .samplerAnisotropy = true,
956 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
957 .textureCompressionASTC_LDR = false,
958 .textureCompressionBC = true,
959 .occlusionQueryPrecise = true,
960 .pipelineStatisticsQuery = true,
961 .vertexPipelineStoresAndAtomics = true,
962 .fragmentStoresAndAtomics = true,
963 .shaderTessellationAndGeometryPointSize = true,
964 .shaderImageGatherExtended = true,
965 .shaderStorageImageExtendedFormats = true,
966 .shaderStorageImageMultisample = true,
967 .shaderUniformBufferArrayDynamicIndexing = true,
968 .shaderSampledImageArrayDynamicIndexing = true,
969 .shaderStorageBufferArrayDynamicIndexing = true,
970 .shaderStorageImageArrayDynamicIndexing = true,
971 .shaderStorageImageReadWithoutFormat = true,
972 .shaderStorageImageWriteWithoutFormat = true,
973 .shaderClipDistance = true,
974 .shaderCullDistance = true,
975 .shaderFloat64 = true,
976 .shaderInt64 = true,
977 .shaderInt16 = true,
978 .sparseBinding = true,
979 .variableMultisampleRate = true,
980 .shaderResourceMinLod = true,
981 .inheritedQueries = true,
982 };
983 }
984
985 static void
986 radv_get_physical_device_features_1_1(struct radv_physical_device *pdevice,
987 VkPhysicalDeviceVulkan11Features *f)
988 {
989 assert(f->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES);
990
991 f->storageBuffer16BitAccess = true;
992 f->uniformAndStorageBuffer16BitAccess = true;
993 f->storagePushConstant16 = true;
994 f->storageInputOutput16 = pdevice->rad_info.has_packed_math_16bit && (LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm);
995 f->multiview = true;
996 f->multiviewGeometryShader = true;
997 f->multiviewTessellationShader = true;
998 f->variablePointersStorageBuffer = true;
999 f->variablePointers = true;
1000 f->protectedMemory = false;
1001 f->samplerYcbcrConversion = true;
1002 f->shaderDrawParameters = true;
1003 }
1004
1005 static void
1006 radv_get_physical_device_features_1_2(struct radv_physical_device *pdevice,
1007 VkPhysicalDeviceVulkan12Features *f)
1008 {
1009 assert(f->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES);
1010
1011 f->samplerMirrorClampToEdge = true;
1012 f->drawIndirectCount = true;
1013 f->storageBuffer8BitAccess = true;
1014 f->uniformAndStorageBuffer8BitAccess = true;
1015 f->storagePushConstant8 = true;
1016 f->shaderBufferInt64Atomics = LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm;
1017 f->shaderSharedInt64Atomics = LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm;
1018 f->shaderFloat16 = pdevice->rad_info.has_packed_math_16bit;
1019 f->shaderInt8 = true;
1020
1021 f->descriptorIndexing = true;
1022 f->shaderInputAttachmentArrayDynamicIndexing = true;
1023 f->shaderUniformTexelBufferArrayDynamicIndexing = true;
1024 f->shaderStorageTexelBufferArrayDynamicIndexing = true;
1025 f->shaderUniformBufferArrayNonUniformIndexing = true;
1026 f->shaderSampledImageArrayNonUniformIndexing = true;
1027 f->shaderStorageBufferArrayNonUniformIndexing = true;
1028 f->shaderStorageImageArrayNonUniformIndexing = true;
1029 f->shaderInputAttachmentArrayNonUniformIndexing = true;
1030 f->shaderUniformTexelBufferArrayNonUniformIndexing = true;
1031 f->shaderStorageTexelBufferArrayNonUniformIndexing = true;
1032 f->descriptorBindingUniformBufferUpdateAfterBind = true;
1033 f->descriptorBindingSampledImageUpdateAfterBind = true;
1034 f->descriptorBindingStorageImageUpdateAfterBind = true;
1035 f->descriptorBindingStorageBufferUpdateAfterBind = true;
1036 f->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
1037 f->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
1038 f->descriptorBindingUpdateUnusedWhilePending = true;
1039 f->descriptorBindingPartiallyBound = true;
1040 f->descriptorBindingVariableDescriptorCount = true;
1041 f->runtimeDescriptorArray = true;
1042
1043 f->samplerFilterMinmax = true;
1044 f->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
1045 f->imagelessFramebuffer = true;
1046 f->uniformBufferStandardLayout = true;
1047 f->shaderSubgroupExtendedTypes = true;
1048 f->separateDepthStencilLayouts = true;
1049 f->hostQueryReset = true;
1050 f->timelineSemaphore = pdevice->rad_info.has_syncobj_wait_for_submit;
1051 f->bufferDeviceAddress = true;
1052 f->bufferDeviceAddressCaptureReplay = false;
1053 f->bufferDeviceAddressMultiDevice = false;
1054 f->vulkanMemoryModel = true;
1055 f->vulkanMemoryModelDeviceScope = true;
1056 f->vulkanMemoryModelAvailabilityVisibilityChains = false;
1057 f->shaderOutputViewportIndex = true;
1058 f->shaderOutputLayer = true;
1059 f->subgroupBroadcastDynamicId = true;
1060 }
1061
1062 void radv_GetPhysicalDeviceFeatures2(
1063 VkPhysicalDevice physicalDevice,
1064 VkPhysicalDeviceFeatures2 *pFeatures)
1065 {
1066 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1067 radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
1068
1069 VkPhysicalDeviceVulkan11Features core_1_1 = {
1070 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES,
1071 };
1072 radv_get_physical_device_features_1_1(pdevice, &core_1_1);
1073
1074 VkPhysicalDeviceVulkan12Features core_1_2 = {
1075 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES,
1076 };
1077 radv_get_physical_device_features_1_2(pdevice, &core_1_2);
1078
1079 #define CORE_FEATURE(major, minor, feature) \
1080 features->feature = core_##major##_##minor.feature
1081
1082 vk_foreach_struct(ext, pFeatures->pNext) {
1083 switch (ext->sType) {
1084 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
1085 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
1086 CORE_FEATURE(1, 1, variablePointersStorageBuffer);
1087 CORE_FEATURE(1, 1, variablePointers);
1088 break;
1089 }
1090 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
1091 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
1092 CORE_FEATURE(1, 1, multiview);
1093 CORE_FEATURE(1, 1, multiviewGeometryShader);
1094 CORE_FEATURE(1, 1, multiviewTessellationShader);
1095 break;
1096 }
1097 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
1098 VkPhysicalDeviceShaderDrawParametersFeatures *features =
1099 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
1100 CORE_FEATURE(1, 1, shaderDrawParameters);
1101 break;
1102 }
1103 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
1104 VkPhysicalDeviceProtectedMemoryFeatures *features =
1105 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
1106 CORE_FEATURE(1, 1, protectedMemory);
1107 break;
1108 }
1109 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
1110 VkPhysicalDevice16BitStorageFeatures *features =
1111 (VkPhysicalDevice16BitStorageFeatures*)ext;
1112 CORE_FEATURE(1, 1, storageBuffer16BitAccess);
1113 CORE_FEATURE(1, 1, uniformAndStorageBuffer16BitAccess);
1114 CORE_FEATURE(1, 1, storagePushConstant16);
1115 CORE_FEATURE(1, 1, storageInputOutput16);
1116 break;
1117 }
1118 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
1119 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
1120 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
1121 CORE_FEATURE(1, 1, samplerYcbcrConversion);
1122 break;
1123 }
1124 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES: {
1125 VkPhysicalDeviceDescriptorIndexingFeatures *features =
1126 (VkPhysicalDeviceDescriptorIndexingFeatures*)ext;
1127 CORE_FEATURE(1, 2, shaderInputAttachmentArrayDynamicIndexing);
1128 CORE_FEATURE(1, 2, shaderUniformTexelBufferArrayDynamicIndexing);
1129 CORE_FEATURE(1, 2, shaderStorageTexelBufferArrayDynamicIndexing);
1130 CORE_FEATURE(1, 2, shaderUniformBufferArrayNonUniformIndexing);
1131 CORE_FEATURE(1, 2, shaderSampledImageArrayNonUniformIndexing);
1132 CORE_FEATURE(1, 2, shaderStorageBufferArrayNonUniformIndexing);
1133 CORE_FEATURE(1, 2, shaderStorageImageArrayNonUniformIndexing);
1134 CORE_FEATURE(1, 2, shaderInputAttachmentArrayNonUniformIndexing);
1135 CORE_FEATURE(1, 2, shaderUniformTexelBufferArrayNonUniformIndexing);
1136 CORE_FEATURE(1, 2, shaderStorageTexelBufferArrayNonUniformIndexing);
1137 CORE_FEATURE(1, 2, descriptorBindingUniformBufferUpdateAfterBind);
1138 CORE_FEATURE(1, 2, descriptorBindingSampledImageUpdateAfterBind);
1139 CORE_FEATURE(1, 2, descriptorBindingStorageImageUpdateAfterBind);
1140 CORE_FEATURE(1, 2, descriptorBindingStorageBufferUpdateAfterBind);
1141 CORE_FEATURE(1, 2, descriptorBindingUniformTexelBufferUpdateAfterBind);
1142 CORE_FEATURE(1, 2, descriptorBindingStorageTexelBufferUpdateAfterBind);
1143 CORE_FEATURE(1, 2, descriptorBindingUpdateUnusedWhilePending);
1144 CORE_FEATURE(1, 2, descriptorBindingPartiallyBound);
1145 CORE_FEATURE(1, 2, descriptorBindingVariableDescriptorCount);
1146 CORE_FEATURE(1, 2, runtimeDescriptorArray);
1147 break;
1148 }
1149 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
1150 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
1151 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
1152 features->conditionalRendering = true;
1153 features->inheritedConditionalRendering = false;
1154 break;
1155 }
1156 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
1157 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
1158 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
1159 features->vertexAttributeInstanceRateDivisor = true;
1160 features->vertexAttributeInstanceRateZeroDivisor = true;
1161 break;
1162 }
1163 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
1164 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
1165 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
1166 features->transformFeedback = true;
1167 features->geometryStreams = !pdevice->use_ngg_streamout;
1168 break;
1169 }
1170 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES: {
1171 VkPhysicalDeviceScalarBlockLayoutFeatures *features =
1172 (VkPhysicalDeviceScalarBlockLayoutFeatures *)ext;
1173 CORE_FEATURE(1, 2, scalarBlockLayout);
1174 break;
1175 }
1176 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
1177 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
1178 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
1179 features->memoryPriority = true;
1180 break;
1181 }
1182 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
1183 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
1184 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
1185 features->bufferDeviceAddress = true;
1186 features->bufferDeviceAddressCaptureReplay = false;
1187 features->bufferDeviceAddressMultiDevice = false;
1188 break;
1189 }
1190 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES: {
1191 VkPhysicalDeviceBufferDeviceAddressFeatures *features =
1192 (VkPhysicalDeviceBufferDeviceAddressFeatures *)ext;
1193 CORE_FEATURE(1, 2, bufferDeviceAddress);
1194 CORE_FEATURE(1, 2, bufferDeviceAddressCaptureReplay);
1195 CORE_FEATURE(1, 2, bufferDeviceAddressMultiDevice);
1196 break;
1197 }
1198 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
1199 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
1200 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
1201 features->depthClipEnable = true;
1202 break;
1203 }
1204 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES: {
1205 VkPhysicalDeviceHostQueryResetFeatures *features =
1206 (VkPhysicalDeviceHostQueryResetFeatures *)ext;
1207 CORE_FEATURE(1, 2, hostQueryReset);
1208 break;
1209 }
1210 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES: {
1211 VkPhysicalDevice8BitStorageFeatures *features =
1212 (VkPhysicalDevice8BitStorageFeatures *)ext;
1213 CORE_FEATURE(1, 2, storageBuffer8BitAccess);
1214 CORE_FEATURE(1, 2, uniformAndStorageBuffer8BitAccess);
1215 CORE_FEATURE(1, 2, storagePushConstant8);
1216 break;
1217 }
1218 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_FLOAT16_INT8_FEATURES: {
1219 VkPhysicalDeviceShaderFloat16Int8Features *features =
1220 (VkPhysicalDeviceShaderFloat16Int8Features*)ext;
1221 CORE_FEATURE(1, 2, shaderFloat16);
1222 CORE_FEATURE(1, 2, shaderInt8);
1223 break;
1224 }
1225 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES: {
1226 VkPhysicalDeviceShaderAtomicInt64Features *features =
1227 (VkPhysicalDeviceShaderAtomicInt64Features *)ext;
1228 CORE_FEATURE(1, 2, shaderBufferInt64Atomics);
1229 CORE_FEATURE(1, 2, shaderSharedInt64Atomics);
1230 break;
1231 }
1232 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DEMOTE_TO_HELPER_INVOCATION_FEATURES_EXT: {
1233 VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT *features =
1234 (VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT *)ext;
1235 features->shaderDemoteToHelperInvocation = LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm;
1236 break;
1237 }
1238 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
1239 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
1240 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
1241
1242 features->inlineUniformBlock = true;
1243 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
1244 break;
1245 }
1246 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
1247 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
1248 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
1249 features->computeDerivativeGroupQuads = false;
1250 features->computeDerivativeGroupLinear = true;
1251 break;
1252 }
1253 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
1254 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
1255 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
1256 features->ycbcrImageArrays = true;
1257 break;
1258 }
1259 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES: {
1260 VkPhysicalDeviceUniformBufferStandardLayoutFeatures *features =
1261 (VkPhysicalDeviceUniformBufferStandardLayoutFeatures *)ext;
1262 CORE_FEATURE(1, 2, uniformBufferStandardLayout);
1263 break;
1264 }
1265 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT: {
1266 VkPhysicalDeviceIndexTypeUint8FeaturesEXT *features =
1267 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT *)ext;
1268 features->indexTypeUint8 = pdevice->rad_info.chip_class >= GFX8;
1269 break;
1270 }
1271 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGELESS_FRAMEBUFFER_FEATURES: {
1272 VkPhysicalDeviceImagelessFramebufferFeatures *features =
1273 (VkPhysicalDeviceImagelessFramebufferFeatures *)ext;
1274 CORE_FEATURE(1, 2, imagelessFramebuffer);
1275 break;
1276 }
1277 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR: {
1278 VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *features =
1279 (VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *)ext;
1280 features->pipelineExecutableInfo = true;
1281 break;
1282 }
1283 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CLOCK_FEATURES_KHR: {
1284 VkPhysicalDeviceShaderClockFeaturesKHR *features =
1285 (VkPhysicalDeviceShaderClockFeaturesKHR *)ext;
1286 features->shaderSubgroupClock = true;
1287 features->shaderDeviceClock = pdevice->rad_info.chip_class >= GFX8;
1288 break;
1289 }
1290 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_FEATURES_EXT: {
1291 VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT *features =
1292 (VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT *)ext;
1293 features->texelBufferAlignment = true;
1294 break;
1295 }
1296 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_FEATURES: {
1297 VkPhysicalDeviceTimelineSemaphoreFeatures *features =
1298 (VkPhysicalDeviceTimelineSemaphoreFeatures *) ext;
1299 CORE_FEATURE(1, 2, timelineSemaphore);
1300 break;
1301 }
1302 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_FEATURES_EXT: {
1303 VkPhysicalDeviceSubgroupSizeControlFeaturesEXT *features =
1304 (VkPhysicalDeviceSubgroupSizeControlFeaturesEXT *)ext;
1305 features->subgroupSizeControl = true;
1306 features->computeFullSubgroups = true;
1307 break;
1308 }
1309 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COHERENT_MEMORY_FEATURES_AMD: {
1310 VkPhysicalDeviceCoherentMemoryFeaturesAMD *features =
1311 (VkPhysicalDeviceCoherentMemoryFeaturesAMD *)ext;
1312 features->deviceCoherentMemory = pdevice->rad_info.has_l2_uncached;
1313 break;
1314 }
1315 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_SUBGROUP_EXTENDED_TYPES_FEATURES: {
1316 VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures *features =
1317 (VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures *)ext;
1318 CORE_FEATURE(1, 2, shaderSubgroupExtendedTypes);
1319 break;
1320 }
1321 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SEPARATE_DEPTH_STENCIL_LAYOUTS_FEATURES_KHR: {
1322 VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR *features =
1323 (VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR *)ext;
1324 CORE_FEATURE(1, 2, separateDepthStencilLayouts);
1325 break;
1326 }
1327 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES: {
1328 radv_get_physical_device_features_1_1(pdevice, (void *)ext);
1329 break;
1330 }
1331 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES: {
1332 radv_get_physical_device_features_1_2(pdevice, (void *)ext);
1333 break;
1334 }
1335 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_FEATURES_EXT: {
1336 VkPhysicalDeviceLineRasterizationFeaturesEXT *features =
1337 (VkPhysicalDeviceLineRasterizationFeaturesEXT *)ext;
1338 features->rectangularLines = false;
1339 features->bresenhamLines = true;
1340 features->smoothLines = false;
1341 features->stippledRectangularLines = false;
1342 features->stippledBresenhamLines = true;
1343 features->stippledSmoothLines = false;
1344 break;
1345 }
1346 case VK_STRUCTURE_TYPE_DEVICE_MEMORY_OVERALLOCATION_CREATE_INFO_AMD: {
1347 VkDeviceMemoryOverallocationCreateInfoAMD *features =
1348 (VkDeviceMemoryOverallocationCreateInfoAMD *)ext;
1349 features->overallocationBehavior = true;
1350 break;
1351 }
1352 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ROBUSTNESS_2_FEATURES_EXT: {
1353 VkPhysicalDeviceRobustness2FeaturesEXT *features =
1354 (VkPhysicalDeviceRobustness2FeaturesEXT *)ext;
1355 features->robustBufferAccess2 = true;
1356 features->robustImageAccess2 = true;
1357 features->nullDescriptor = true;
1358 break;
1359 }
1360 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_FEATURES_EXT: {
1361 VkPhysicalDeviceCustomBorderColorFeaturesEXT *features =
1362 (VkPhysicalDeviceCustomBorderColorFeaturesEXT *)ext;
1363 features->customBorderColors = true;
1364 features->customBorderColorWithoutFormat = true;
1365 break;
1366 }
1367 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PRIVATE_DATA_FEATURES_EXT: {
1368 VkPhysicalDevicePrivateDataFeaturesEXT *features =
1369 (VkPhysicalDevicePrivateDataFeaturesEXT *)ext;
1370 features->privateData = true;
1371 break;
1372 }
1373 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_CREATION_CACHE_CONTROL_FEATURES_EXT: {
1374 VkPhysicalDevicePipelineCreationCacheControlFeaturesEXT *features =
1375 (VkPhysicalDevicePipelineCreationCacheControlFeaturesEXT *)ext;
1376 features-> pipelineCreationCacheControl = true;
1377 break;
1378 }
1379 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_MEMORY_MODEL_FEATURES_KHR: {
1380 VkPhysicalDeviceVulkanMemoryModelFeaturesKHR *features =
1381 (VkPhysicalDeviceVulkanMemoryModelFeaturesKHR *)ext;
1382 CORE_FEATURE(1, 2, vulkanMemoryModel);
1383 CORE_FEATURE(1, 2, vulkanMemoryModelDeviceScope);
1384 CORE_FEATURE(1, 2, vulkanMemoryModelAvailabilityVisibilityChains);
1385 break;
1386 }
1387 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTENDED_DYNAMIC_STATE_FEATURES_EXT: {
1388 VkPhysicalDeviceExtendedDynamicStateFeaturesEXT *features =
1389 (VkPhysicalDeviceExtendedDynamicStateFeaturesEXT *) ext;
1390 features->extendedDynamicState = true;
1391 break;
1392 }
1393 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGE_ROBUSTNESS_FEATURES_EXT: {
1394 VkPhysicalDeviceImageRobustnessFeaturesEXT *features =
1395 (VkPhysicalDeviceImageRobustnessFeaturesEXT *)ext;
1396 features->robustImageAccess = true;
1397 break;
1398 }
1399 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_FLOAT_FEATURES_EXT: {
1400 VkPhysicalDeviceShaderAtomicFloatFeaturesEXT *features =
1401 (VkPhysicalDeviceShaderAtomicFloatFeaturesEXT *)ext;
1402 features->shaderBufferFloat32Atomics = true;
1403 features->shaderBufferFloat32AtomicAdd = false;
1404 features->shaderBufferFloat64Atomics = true;
1405 features->shaderBufferFloat64AtomicAdd = false;
1406 features->shaderSharedFloat32Atomics = true;
1407 features->shaderSharedFloat32AtomicAdd = pdevice->rad_info.chip_class >= GFX8 &&
1408 (!pdevice->use_llvm || LLVM_VERSION_MAJOR >= 10);
1409 features->shaderSharedFloat64Atomics = true;
1410 features->shaderSharedFloat64AtomicAdd = false;
1411 features->shaderImageFloat32Atomics = true;
1412 features->shaderImageFloat32AtomicAdd = false;
1413 features->sparseImageFloat32Atomics = false;
1414 features->sparseImageFloat32AtomicAdd = false;
1415 break;
1416 }
1417 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_4444_FORMATS_FEATURES_EXT: {
1418 VkPhysicalDevice4444FormatsFeaturesEXT *features =
1419 (VkPhysicalDevice4444FormatsFeaturesEXT *)ext;
1420 features->formatA4R4G4B4 = true;
1421 features->formatA4B4G4R4 = true;
1422 break;
1423 }
1424 default:
1425 break;
1426 }
1427 }
1428 #undef CORE_FEATURE
1429 }
1430
1431 static size_t
1432 radv_max_descriptor_set_size()
1433 {
1434 /* make sure that the entire descriptor set is addressable with a signed
1435 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1436 * be at most 2 GiB. the combined image & samples object count as one of
1437 * both. This limit is for the pipeline layout, not for the set layout, but
1438 * there is no set limit, so we just set a pipeline limit. I don't think
1439 * any app is going to hit this soon. */
1440 return ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
1441 - MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1442 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1443 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1444 32 /* sampler, largest when combined with image */ +
1445 64 /* sampled image */ +
1446 64 /* storage image */);
1447 }
1448
1449 static uint32_t
1450 radv_uniform_buffer_offset_alignment(const struct radv_physical_device *pdevice)
1451 {
1452 uint32_t uniform_offset_alignment = driQueryOptioni(&pdevice->instance->dri_options,
1453 "radv_override_uniform_offset_alignment");
1454 if (!util_is_power_of_two_or_zero(uniform_offset_alignment)) {
1455 fprintf(stderr, "ERROR: invalid radv_override_uniform_offset_alignment setting %d:"
1456 "not a power of two\n", uniform_offset_alignment);
1457 uniform_offset_alignment = 0;
1458 }
1459
1460 /* Take at least the hardware limit. */
1461 return MAX2(uniform_offset_alignment, 4);
1462 }
1463
1464 void radv_GetPhysicalDeviceProperties(
1465 VkPhysicalDevice physicalDevice,
1466 VkPhysicalDeviceProperties* pProperties)
1467 {
1468 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1469 VkSampleCountFlags sample_counts = 0xf;
1470
1471 size_t max_descriptor_set_size = radv_max_descriptor_set_size();
1472
1473 VkPhysicalDeviceLimits limits = {
1474 .maxImageDimension1D = (1 << 14),
1475 .maxImageDimension2D = (1 << 14),
1476 .maxImageDimension3D = (1 << 11),
1477 .maxImageDimensionCube = (1 << 14),
1478 .maxImageArrayLayers = (1 << 11),
1479 .maxTexelBufferElements = UINT32_MAX,
1480 .maxUniformBufferRange = UINT32_MAX,
1481 .maxStorageBufferRange = UINT32_MAX,
1482 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1483 .maxMemoryAllocationCount = UINT32_MAX,
1484 .maxSamplerAllocationCount = 64 * 1024,
1485 .bufferImageGranularity = 64, /* A cache line */
1486 .sparseAddressSpaceSize = RADV_MAX_MEMORY_ALLOCATION_SIZE, /* buffer max size */
1487 .maxBoundDescriptorSets = MAX_SETS,
1488 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1489 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1490 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1491 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1492 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1493 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1494 .maxPerStageResources = max_descriptor_set_size,
1495 .maxDescriptorSetSamplers = max_descriptor_set_size,
1496 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1497 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1498 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1499 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1500 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1501 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1502 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1503 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1504 .maxVertexInputBindings = MAX_VBS,
1505 .maxVertexInputAttributeOffset = 2047,
1506 .maxVertexInputBindingStride = 2048,
1507 .maxVertexOutputComponents = 128,
1508 .maxTessellationGenerationLevel = 64,
1509 .maxTessellationPatchSize = 32,
1510 .maxTessellationControlPerVertexInputComponents = 128,
1511 .maxTessellationControlPerVertexOutputComponents = 128,
1512 .maxTessellationControlPerPatchOutputComponents = 120,
1513 .maxTessellationControlTotalOutputComponents = 4096,
1514 .maxTessellationEvaluationInputComponents = 128,
1515 .maxTessellationEvaluationOutputComponents = 128,
1516 .maxGeometryShaderInvocations = 127,
1517 .maxGeometryInputComponents = 64,
1518 .maxGeometryOutputComponents = 128,
1519 .maxGeometryOutputVertices = 256,
1520 .maxGeometryTotalOutputComponents = 1024,
1521 .maxFragmentInputComponents = 128,
1522 .maxFragmentOutputAttachments = 8,
1523 .maxFragmentDualSrcAttachments = 1,
1524 .maxFragmentCombinedOutputResources = 8,
1525 .maxComputeSharedMemorySize = 32768,
1526 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1527 .maxComputeWorkGroupInvocations = 1024,
1528 .maxComputeWorkGroupSize = {
1529 1024,
1530 1024,
1531 1024
1532 },
1533 .subPixelPrecisionBits = 8,
1534 .subTexelPrecisionBits = 8,
1535 .mipmapPrecisionBits = 8,
1536 .maxDrawIndexedIndexValue = UINT32_MAX,
1537 .maxDrawIndirectCount = UINT32_MAX,
1538 .maxSamplerLodBias = 16,
1539 .maxSamplerAnisotropy = 16,
1540 .maxViewports = MAX_VIEWPORTS,
1541 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1542 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1543 .viewportSubPixelBits = 8,
1544 .minMemoryMapAlignment = 4096, /* A page */
1545 .minTexelBufferOffsetAlignment = 4,
1546 .minUniformBufferOffsetAlignment = radv_uniform_buffer_offset_alignment(pdevice),
1547 .minStorageBufferOffsetAlignment = 4,
1548 .minTexelOffset = -32,
1549 .maxTexelOffset = 31,
1550 .minTexelGatherOffset = -32,
1551 .maxTexelGatherOffset = 31,
1552 .minInterpolationOffset = -2,
1553 .maxInterpolationOffset = 2,
1554 .subPixelInterpolationOffsetBits = 8,
1555 .maxFramebufferWidth = (1 << 14),
1556 .maxFramebufferHeight = (1 << 14),
1557 .maxFramebufferLayers = (1 << 10),
1558 .framebufferColorSampleCounts = sample_counts,
1559 .framebufferDepthSampleCounts = sample_counts,
1560 .framebufferStencilSampleCounts = sample_counts,
1561 .framebufferNoAttachmentsSampleCounts = sample_counts,
1562 .maxColorAttachments = MAX_RTS,
1563 .sampledImageColorSampleCounts = sample_counts,
1564 .sampledImageIntegerSampleCounts = sample_counts,
1565 .sampledImageDepthSampleCounts = sample_counts,
1566 .sampledImageStencilSampleCounts = sample_counts,
1567 .storageImageSampleCounts = sample_counts,
1568 .maxSampleMaskWords = 1,
1569 .timestampComputeAndGraphics = true,
1570 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1571 .maxClipDistances = 8,
1572 .maxCullDistances = 8,
1573 .maxCombinedClipAndCullDistances = 8,
1574 .discreteQueuePriorities = 2,
1575 .pointSizeRange = { 0.0, 8191.875 },
1576 .lineWidthRange = { 0.0, 8191.875 },
1577 .pointSizeGranularity = (1.0 / 8.0),
1578 .lineWidthGranularity = (1.0 / 8.0),
1579 .strictLines = false, /* FINISHME */
1580 .standardSampleLocations = true,
1581 .optimalBufferCopyOffsetAlignment = 128,
1582 .optimalBufferCopyRowPitchAlignment = 128,
1583 .nonCoherentAtomSize = 64,
1584 };
1585
1586 *pProperties = (VkPhysicalDeviceProperties) {
1587 .apiVersion = radv_physical_device_api_version(pdevice),
1588 .driverVersion = vk_get_driver_version(),
1589 .vendorID = ATI_VENDOR_ID,
1590 .deviceID = pdevice->rad_info.pci_id,
1591 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1592 .limits = limits,
1593 .sparseProperties = {0},
1594 };
1595
1596 strcpy(pProperties->deviceName, pdevice->name);
1597 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1598 }
1599
1600 static void
1601 radv_get_physical_device_properties_1_1(struct radv_physical_device *pdevice,
1602 VkPhysicalDeviceVulkan11Properties *p)
1603 {
1604 assert(p->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES);
1605
1606 memcpy(p->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1607 memcpy(p->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1608 memset(p->deviceLUID, 0, VK_LUID_SIZE);
1609 /* The LUID is for Windows. */
1610 p->deviceLUIDValid = false;
1611 p->deviceNodeMask = 0;
1612
1613 p->subgroupSize = RADV_SUBGROUP_SIZE;
1614 p->subgroupSupportedStages = VK_SHADER_STAGE_ALL_GRAPHICS |
1615 VK_SHADER_STAGE_COMPUTE_BIT;
1616 p->subgroupSupportedOperations = VK_SUBGROUP_FEATURE_BASIC_BIT |
1617 VK_SUBGROUP_FEATURE_VOTE_BIT |
1618 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1619 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1620 VK_SUBGROUP_FEATURE_CLUSTERED_BIT |
1621 VK_SUBGROUP_FEATURE_QUAD_BIT |
1622 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1623 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1624 p->subgroupQuadOperationsInAllStages = true;
1625
1626 p->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1627 p->maxMultiviewViewCount = MAX_VIEWS;
1628 p->maxMultiviewInstanceIndex = INT_MAX;
1629 p->protectedNoFault = false;
1630 p->maxPerSetDescriptors = RADV_MAX_PER_SET_DESCRIPTORS;
1631 p->maxMemoryAllocationSize = RADV_MAX_MEMORY_ALLOCATION_SIZE;
1632 }
1633
1634 static void
1635 radv_get_physical_device_properties_1_2(struct radv_physical_device *pdevice,
1636 VkPhysicalDeviceVulkan12Properties *p)
1637 {
1638 assert(p->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES);
1639
1640 p->driverID = VK_DRIVER_ID_MESA_RADV;
1641 snprintf(p->driverName, VK_MAX_DRIVER_NAME_SIZE, "radv");
1642 snprintf(p->driverInfo, VK_MAX_DRIVER_INFO_SIZE,
1643 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1 " (%s)",
1644 radv_get_compiler_string(pdevice));
1645 p->conformanceVersion = (VkConformanceVersion) {
1646 .major = 1,
1647 .minor = 2,
1648 .subminor = 0,
1649 .patch = 0,
1650 };
1651
1652 /* On AMD hardware, denormals and rounding modes for fp16/fp64 are
1653 * controlled by the same config register.
1654 */
1655 if (pdevice->rad_info.has_packed_math_16bit) {
1656 p->denormBehaviorIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
1657 p->roundingModeIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
1658 } else {
1659 p->denormBehaviorIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL_KHR;
1660 p->roundingModeIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL_KHR;
1661 }
1662
1663 /* With LLVM, do not allow both preserving and flushing denorms because
1664 * different shaders in the same pipeline can have different settings and
1665 * this won't work for merged shaders. To make it work, this requires LLVM
1666 * support for changing the register. The same logic applies for the
1667 * rounding modes because they are configured with the same config
1668 * register.
1669 */
1670 p->shaderDenormFlushToZeroFloat32 = true;
1671 p->shaderDenormPreserveFloat32 = !pdevice->use_llvm;
1672 p->shaderRoundingModeRTEFloat32 = true;
1673 p->shaderRoundingModeRTZFloat32 = !pdevice->use_llvm;
1674 p->shaderSignedZeroInfNanPreserveFloat32 = true;
1675
1676 p->shaderDenormFlushToZeroFloat16 = pdevice->rad_info.has_packed_math_16bit && !pdevice->use_llvm;
1677 p->shaderDenormPreserveFloat16 = pdevice->rad_info.has_packed_math_16bit;
1678 p->shaderRoundingModeRTEFloat16 = pdevice->rad_info.has_packed_math_16bit;
1679 p->shaderRoundingModeRTZFloat16 = pdevice->rad_info.has_packed_math_16bit && !pdevice->use_llvm;
1680 p->shaderSignedZeroInfNanPreserveFloat16 = pdevice->rad_info.has_packed_math_16bit;
1681
1682 p->shaderDenormFlushToZeroFloat64 = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_llvm;
1683 p->shaderDenormPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8;
1684 p->shaderRoundingModeRTEFloat64 = pdevice->rad_info.chip_class >= GFX8;
1685 p->shaderRoundingModeRTZFloat64 = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_llvm;
1686 p->shaderSignedZeroInfNanPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8;
1687
1688 p->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1689 p->shaderUniformBufferArrayNonUniformIndexingNative = false;
1690 p->shaderSampledImageArrayNonUniformIndexingNative = false;
1691 p->shaderStorageBufferArrayNonUniformIndexingNative = false;
1692 p->shaderStorageImageArrayNonUniformIndexingNative = false;
1693 p->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1694 p->robustBufferAccessUpdateAfterBind = false;
1695 p->quadDivergentImplicitLod = false;
1696
1697 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1698 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1699 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1700 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1701 32 /* sampler, largest when combined with image */ +
1702 64 /* sampled image */ +
1703 64 /* storage image */);
1704 p->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1705 p->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1706 p->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1707 p->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1708 p->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1709 p->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1710 p->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1711 p->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1712 p->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1713 p->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1714 p->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1715 p->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1716 p->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1717 p->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1718 p->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1719
1720 /* We support all of the depth resolve modes */
1721 p->supportedDepthResolveModes = VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1722 VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
1723 VK_RESOLVE_MODE_MIN_BIT_KHR |
1724 VK_RESOLVE_MODE_MAX_BIT_KHR;
1725
1726 /* Average doesn't make sense for stencil so we don't support that */
1727 p->supportedStencilResolveModes = VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1728 VK_RESOLVE_MODE_MIN_BIT_KHR |
1729 VK_RESOLVE_MODE_MAX_BIT_KHR;
1730
1731 p->independentResolveNone = true;
1732 p->independentResolve = true;
1733
1734 /* GFX6-8 only support single channel min/max filter. */
1735 p->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1736 p->filterMinmaxSingleComponentFormats = true;
1737
1738 p->maxTimelineSemaphoreValueDifference = UINT64_MAX;
1739
1740 p->framebufferIntegerColorSampleCounts = VK_SAMPLE_COUNT_1_BIT;
1741 }
1742
1743 void radv_GetPhysicalDeviceProperties2(
1744 VkPhysicalDevice physicalDevice,
1745 VkPhysicalDeviceProperties2 *pProperties)
1746 {
1747 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1748 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1749
1750 VkPhysicalDeviceVulkan11Properties core_1_1 = {
1751 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES,
1752 };
1753 radv_get_physical_device_properties_1_1(pdevice, &core_1_1);
1754
1755 VkPhysicalDeviceVulkan12Properties core_1_2 = {
1756 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES,
1757 };
1758 radv_get_physical_device_properties_1_2(pdevice, &core_1_2);
1759
1760 #define CORE_RENAMED_PROPERTY(major, minor, ext_property, core_property) \
1761 memcpy(&properties->ext_property, &core_##major##_##minor.core_property, \
1762 sizeof(core_##major##_##minor.core_property))
1763
1764 #define CORE_PROPERTY(major, minor, property) \
1765 CORE_RENAMED_PROPERTY(major, minor, property, property)
1766
1767 vk_foreach_struct(ext, pProperties->pNext) {
1768 switch (ext->sType) {
1769 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1770 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1771 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1772 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1773 break;
1774 }
1775 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1776 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1777 CORE_PROPERTY(1, 1, deviceUUID);
1778 CORE_PROPERTY(1, 1, driverUUID);
1779 CORE_PROPERTY(1, 1, deviceLUID);
1780 CORE_PROPERTY(1, 1, deviceLUIDValid);
1781 break;
1782 }
1783 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1784 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1785 CORE_PROPERTY(1, 1, maxMultiviewViewCount);
1786 CORE_PROPERTY(1, 1, maxMultiviewInstanceIndex);
1787 break;
1788 }
1789 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1790 VkPhysicalDevicePointClippingProperties *properties =
1791 (VkPhysicalDevicePointClippingProperties*)ext;
1792 CORE_PROPERTY(1, 1, pointClippingBehavior);
1793 break;
1794 }
1795 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1796 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1797 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1798 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1799 break;
1800 }
1801 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1802 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1803 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1804 properties->minImportedHostPointerAlignment = 4096;
1805 break;
1806 }
1807 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1808 VkPhysicalDeviceSubgroupProperties *properties =
1809 (VkPhysicalDeviceSubgroupProperties*)ext;
1810 CORE_PROPERTY(1, 1, subgroupSize);
1811 CORE_RENAMED_PROPERTY(1, 1, supportedStages,
1812 subgroupSupportedStages);
1813 CORE_RENAMED_PROPERTY(1, 1, supportedOperations,
1814 subgroupSupportedOperations);
1815 CORE_RENAMED_PROPERTY(1, 1, quadOperationsInAllStages,
1816 subgroupQuadOperationsInAllStages);
1817 break;
1818 }
1819 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1820 VkPhysicalDeviceMaintenance3Properties *properties =
1821 (VkPhysicalDeviceMaintenance3Properties*)ext;
1822 CORE_PROPERTY(1, 1, maxPerSetDescriptors);
1823 CORE_PROPERTY(1, 1, maxMemoryAllocationSize);
1824 break;
1825 }
1826 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES: {
1827 VkPhysicalDeviceSamplerFilterMinmaxProperties *properties =
1828 (VkPhysicalDeviceSamplerFilterMinmaxProperties *)ext;
1829 CORE_PROPERTY(1, 2, filterMinmaxImageComponentMapping);
1830 CORE_PROPERTY(1, 2, filterMinmaxSingleComponentFormats);
1831 break;
1832 }
1833 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1834 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1835 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1836
1837 /* Shader engines. */
1838 properties->shaderEngineCount =
1839 pdevice->rad_info.max_se;
1840 properties->shaderArraysPerEngineCount =
1841 pdevice->rad_info.max_sh_per_se;
1842 properties->computeUnitsPerShaderArray =
1843 pdevice->rad_info.min_good_cu_per_sa;
1844 properties->simdPerComputeUnit =
1845 pdevice->rad_info.num_simd_per_compute_unit;
1846 properties->wavefrontsPerSimd =
1847 pdevice->rad_info.max_wave64_per_simd;
1848 properties->wavefrontSize = 64;
1849
1850 /* SGPR. */
1851 properties->sgprsPerSimd =
1852 pdevice->rad_info.num_physical_sgprs_per_simd;
1853 properties->minSgprAllocation =
1854 pdevice->rad_info.min_sgpr_alloc;
1855 properties->maxSgprAllocation =
1856 pdevice->rad_info.max_sgpr_alloc;
1857 properties->sgprAllocationGranularity =
1858 pdevice->rad_info.sgpr_alloc_granularity;
1859
1860 /* VGPR. */
1861 properties->vgprsPerSimd =
1862 pdevice->rad_info.num_physical_wave64_vgprs_per_simd;
1863 properties->minVgprAllocation =
1864 pdevice->rad_info.min_wave64_vgpr_alloc;
1865 properties->maxVgprAllocation =
1866 pdevice->rad_info.max_vgpr_alloc;
1867 properties->vgprAllocationGranularity =
1868 pdevice->rad_info.wave64_vgpr_alloc_granularity;
1869 break;
1870 }
1871 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_2_AMD: {
1872 VkPhysicalDeviceShaderCoreProperties2AMD *properties =
1873 (VkPhysicalDeviceShaderCoreProperties2AMD *)ext;
1874
1875 properties->shaderCoreFeatures = 0;
1876 properties->activeComputeUnitCount =
1877 pdevice->rad_info.num_good_compute_units;
1878 break;
1879 }
1880 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1881 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1882 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1883 properties->maxVertexAttribDivisor = UINT32_MAX;
1884 break;
1885 }
1886 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES: {
1887 VkPhysicalDeviceDescriptorIndexingProperties *properties =
1888 (VkPhysicalDeviceDescriptorIndexingProperties*)ext;
1889 CORE_PROPERTY(1, 2, maxUpdateAfterBindDescriptorsInAllPools);
1890 CORE_PROPERTY(1, 2, shaderUniformBufferArrayNonUniformIndexingNative);
1891 CORE_PROPERTY(1, 2, shaderSampledImageArrayNonUniformIndexingNative);
1892 CORE_PROPERTY(1, 2, shaderStorageBufferArrayNonUniformIndexingNative);
1893 CORE_PROPERTY(1, 2, shaderStorageImageArrayNonUniformIndexingNative);
1894 CORE_PROPERTY(1, 2, shaderInputAttachmentArrayNonUniformIndexingNative);
1895 CORE_PROPERTY(1, 2, robustBufferAccessUpdateAfterBind);
1896 CORE_PROPERTY(1, 2, quadDivergentImplicitLod);
1897 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSamplers);
1898 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindUniformBuffers);
1899 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageBuffers);
1900 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSampledImages);
1901 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageImages);
1902 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindInputAttachments);
1903 CORE_PROPERTY(1, 2, maxPerStageUpdateAfterBindResources);
1904 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSamplers);
1905 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffers);
1906 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffersDynamic);
1907 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffers);
1908 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffersDynamic);
1909 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSampledImages);
1910 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageImages);
1911 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindInputAttachments);
1912 break;
1913 }
1914 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1915 VkPhysicalDeviceProtectedMemoryProperties *properties =
1916 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1917 CORE_PROPERTY(1, 1, protectedNoFault);
1918 break;
1919 }
1920 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1921 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1922 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1923 properties->primitiveOverestimationSize = 0;
1924 properties->maxExtraPrimitiveOverestimationSize = 0;
1925 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1926 properties->primitiveUnderestimation = false;
1927 properties->conservativePointAndLineRasterization = false;
1928 properties->degenerateTrianglesRasterized = false;
1929 properties->degenerateLinesRasterized = false;
1930 properties->fullyCoveredFragmentShaderInputVariable = false;
1931 properties->conservativeRasterizationPostDepthCoverage = false;
1932 break;
1933 }
1934 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1935 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1936 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1937 properties->pciDomain = pdevice->bus_info.domain;
1938 properties->pciBus = pdevice->bus_info.bus;
1939 properties->pciDevice = pdevice->bus_info.dev;
1940 properties->pciFunction = pdevice->bus_info.func;
1941 break;
1942 }
1943 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES: {
1944 VkPhysicalDeviceDriverProperties *properties =
1945 (VkPhysicalDeviceDriverProperties *) ext;
1946 CORE_PROPERTY(1, 2, driverID);
1947 CORE_PROPERTY(1, 2, driverName);
1948 CORE_PROPERTY(1, 2, driverInfo);
1949 CORE_PROPERTY(1, 2, conformanceVersion);
1950 break;
1951 }
1952 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1953 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1954 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1955 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1956 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1957 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1958 properties->maxTransformFeedbackStreamDataSize = 512;
1959 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1960 properties->maxTransformFeedbackBufferDataStride = 512;
1961 properties->transformFeedbackQueries = !pdevice->use_ngg_streamout;
1962 properties->transformFeedbackStreamsLinesTriangles = !pdevice->use_ngg_streamout;
1963 properties->transformFeedbackRasterizationStreamSelect = false;
1964 properties->transformFeedbackDraw = true;
1965 break;
1966 }
1967 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1968 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1969 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1970
1971 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1972 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1973 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1974 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1975 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1976 break;
1977 }
1978 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT: {
1979 VkPhysicalDeviceSampleLocationsPropertiesEXT *properties =
1980 (VkPhysicalDeviceSampleLocationsPropertiesEXT *)ext;
1981 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_2_BIT |
1982 VK_SAMPLE_COUNT_4_BIT |
1983 VK_SAMPLE_COUNT_8_BIT;
1984 properties->maxSampleLocationGridSize = (VkExtent2D){ 2 , 2 };
1985 properties->sampleLocationCoordinateRange[0] = 0.0f;
1986 properties->sampleLocationCoordinateRange[1] = 0.9375f;
1987 properties->sampleLocationSubPixelBits = 4;
1988 properties->variableSampleLocations = false;
1989 break;
1990 }
1991 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES: {
1992 VkPhysicalDeviceDepthStencilResolveProperties *properties =
1993 (VkPhysicalDeviceDepthStencilResolveProperties *)ext;
1994 CORE_PROPERTY(1, 2, supportedDepthResolveModes);
1995 CORE_PROPERTY(1, 2, supportedStencilResolveModes);
1996 CORE_PROPERTY(1, 2, independentResolveNone);
1997 CORE_PROPERTY(1, 2, independentResolve);
1998 break;
1999 }
2000 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_PROPERTIES_EXT: {
2001 VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT *properties =
2002 (VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT *)ext;
2003 properties->storageTexelBufferOffsetAlignmentBytes = 4;
2004 properties->storageTexelBufferOffsetSingleTexelAlignment = true;
2005 properties->uniformTexelBufferOffsetAlignmentBytes = 4;
2006 properties->uniformTexelBufferOffsetSingleTexelAlignment = true;
2007 break;
2008 }
2009 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT_CONTROLS_PROPERTIES : {
2010 VkPhysicalDeviceFloatControlsProperties *properties =
2011 (VkPhysicalDeviceFloatControlsProperties *)ext;
2012 CORE_PROPERTY(1, 2, denormBehaviorIndependence);
2013 CORE_PROPERTY(1, 2, roundingModeIndependence);
2014 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat16);
2015 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat16);
2016 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat16);
2017 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat16);
2018 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat16);
2019 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat32);
2020 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat32);
2021 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat32);
2022 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat32);
2023 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat32);
2024 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat64);
2025 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat64);
2026 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat64);
2027 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat64);
2028 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat64);
2029 break;
2030 }
2031 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_PROPERTIES: {
2032 VkPhysicalDeviceTimelineSemaphoreProperties *properties =
2033 (VkPhysicalDeviceTimelineSemaphoreProperties *) ext;
2034 CORE_PROPERTY(1, 2, maxTimelineSemaphoreValueDifference);
2035 break;
2036 }
2037 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_PROPERTIES_EXT: {
2038 VkPhysicalDeviceSubgroupSizeControlPropertiesEXT *props =
2039 (VkPhysicalDeviceSubgroupSizeControlPropertiesEXT *)ext;
2040 props->minSubgroupSize = 64;
2041 props->maxSubgroupSize = 64;
2042 props->maxComputeWorkgroupSubgroups = UINT32_MAX;
2043 props->requiredSubgroupSizeStages = 0;
2044
2045 if (pdevice->rad_info.chip_class >= GFX10) {
2046 /* Only GFX10+ supports wave32. */
2047 props->minSubgroupSize = 32;
2048 props->requiredSubgroupSizeStages = VK_SHADER_STAGE_COMPUTE_BIT;
2049 }
2050 break;
2051 }
2052 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES:
2053 radv_get_physical_device_properties_1_1(pdevice, (void *)ext);
2054 break;
2055 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES:
2056 radv_get_physical_device_properties_1_2(pdevice, (void *)ext);
2057 break;
2058 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_PROPERTIES_EXT: {
2059 VkPhysicalDeviceLineRasterizationPropertiesEXT *props =
2060 (VkPhysicalDeviceLineRasterizationPropertiesEXT *)ext;
2061 props->lineSubPixelPrecisionBits = 4;
2062 break;
2063 }
2064 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ROBUSTNESS_2_PROPERTIES_EXT: {
2065 VkPhysicalDeviceRobustness2PropertiesEXT *properties =
2066 (VkPhysicalDeviceRobustness2PropertiesEXT *)ext;
2067 properties->robustStorageBufferAccessSizeAlignment = 4;
2068 properties->robustUniformBufferAccessSizeAlignment = 4;
2069 break;
2070 }
2071 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_PROPERTIES_EXT: {
2072 VkPhysicalDeviceCustomBorderColorPropertiesEXT *props =
2073 (VkPhysicalDeviceCustomBorderColorPropertiesEXT *)ext;
2074 props->maxCustomBorderColorSamplers = RADV_BORDER_COLOR_COUNT;
2075 break;
2076 }
2077 default:
2078 break;
2079 }
2080 }
2081 }
2082
2083 static void radv_get_physical_device_queue_family_properties(
2084 struct radv_physical_device* pdevice,
2085 uint32_t* pCount,
2086 VkQueueFamilyProperties** pQueueFamilyProperties)
2087 {
2088 int num_queue_families = 1;
2089 int idx;
2090 if (pdevice->rad_info.num_rings[RING_COMPUTE] > 0 &&
2091 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
2092 num_queue_families++;
2093
2094 if (pQueueFamilyProperties == NULL) {
2095 *pCount = num_queue_families;
2096 return;
2097 }
2098
2099 if (!*pCount)
2100 return;
2101
2102 idx = 0;
2103 if (*pCount >= 1) {
2104 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
2105 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
2106 VK_QUEUE_COMPUTE_BIT |
2107 VK_QUEUE_TRANSFER_BIT |
2108 VK_QUEUE_SPARSE_BINDING_BIT,
2109 .queueCount = 1,
2110 .timestampValidBits = 64,
2111 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
2112 };
2113 idx++;
2114 }
2115
2116 if (pdevice->rad_info.num_rings[RING_COMPUTE] > 0 &&
2117 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
2118 if (*pCount > idx) {
2119 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
2120 .queueFlags = VK_QUEUE_COMPUTE_BIT |
2121 VK_QUEUE_TRANSFER_BIT |
2122 VK_QUEUE_SPARSE_BINDING_BIT,
2123 .queueCount = pdevice->rad_info.num_rings[RING_COMPUTE],
2124 .timestampValidBits = 64,
2125 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
2126 };
2127 idx++;
2128 }
2129 }
2130 *pCount = idx;
2131 }
2132
2133 void radv_GetPhysicalDeviceQueueFamilyProperties(
2134 VkPhysicalDevice physicalDevice,
2135 uint32_t* pCount,
2136 VkQueueFamilyProperties* pQueueFamilyProperties)
2137 {
2138 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
2139 if (!pQueueFamilyProperties) {
2140 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
2141 return;
2142 }
2143 VkQueueFamilyProperties *properties[] = {
2144 pQueueFamilyProperties + 0,
2145 pQueueFamilyProperties + 1,
2146 pQueueFamilyProperties + 2,
2147 };
2148 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
2149 assert(*pCount <= 3);
2150 }
2151
2152 void radv_GetPhysicalDeviceQueueFamilyProperties2(
2153 VkPhysicalDevice physicalDevice,
2154 uint32_t* pCount,
2155 VkQueueFamilyProperties2 *pQueueFamilyProperties)
2156 {
2157 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
2158 if (!pQueueFamilyProperties) {
2159 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
2160 return;
2161 }
2162 VkQueueFamilyProperties *properties[] = {
2163 &pQueueFamilyProperties[0].queueFamilyProperties,
2164 &pQueueFamilyProperties[1].queueFamilyProperties,
2165 &pQueueFamilyProperties[2].queueFamilyProperties,
2166 };
2167 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
2168 assert(*pCount <= 3);
2169 }
2170
2171 void radv_GetPhysicalDeviceMemoryProperties(
2172 VkPhysicalDevice physicalDevice,
2173 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
2174 {
2175 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2176
2177 *pMemoryProperties = physical_device->memory_properties;
2178 }
2179
2180 static void
2181 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
2182 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
2183 {
2184 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2185 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
2186 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
2187 uint64_t vram_size = radv_get_vram_size(device);
2188 uint64_t gtt_size = device->rad_info.gart_size;
2189 uint64_t heap_budget, heap_usage;
2190
2191 /* For all memory heaps, the computation of budget is as follow:
2192 * heap_budget = heap_size - global_heap_usage + app_heap_usage
2193 *
2194 * The Vulkan spec 1.1.97 says that the budget should include any
2195 * currently allocated device memory.
2196 *
2197 * Note that the application heap usages are not really accurate (eg.
2198 * in presence of shared buffers).
2199 */
2200 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
2201 uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;
2202
2203 if ((device->memory_domains[i] & RADEON_DOMAIN_VRAM) && (device->memory_flags[i] & RADEON_FLAG_NO_CPU_ACCESS)) {
2204 heap_usage = device->ws->query_value(device->ws,
2205 RADEON_ALLOCATED_VRAM);
2206
2207 heap_budget = vram_size -
2208 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
2209 heap_usage;
2210
2211 memoryBudget->heapBudget[heap_index] = heap_budget;
2212 memoryBudget->heapUsage[heap_index] = heap_usage;
2213 } else if (device->memory_domains[i] & RADEON_DOMAIN_VRAM) {
2214 heap_usage = device->ws->query_value(device->ws,
2215 RADEON_ALLOCATED_VRAM_VIS);
2216
2217 heap_budget = visible_vram_size -
2218 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
2219 heap_usage;
2220
2221 memoryBudget->heapBudget[heap_index] = heap_budget;
2222 memoryBudget->heapUsage[heap_index] = heap_usage;
2223 } else {
2224 assert(device->memory_domains[i] & RADEON_DOMAIN_GTT);
2225
2226 heap_usage = device->ws->query_value(device->ws,
2227 RADEON_ALLOCATED_GTT);
2228
2229 heap_budget = gtt_size -
2230 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
2231 heap_usage;
2232
2233 memoryBudget->heapBudget[heap_index] = heap_budget;
2234 memoryBudget->heapUsage[heap_index] = heap_usage;
2235 }
2236 }
2237
2238 /* The heapBudget and heapUsage values must be zero for array elements
2239 * greater than or equal to
2240 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
2241 */
2242 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
2243 memoryBudget->heapBudget[i] = 0;
2244 memoryBudget->heapUsage[i] = 0;
2245 }
2246 }
2247
2248 void radv_GetPhysicalDeviceMemoryProperties2(
2249 VkPhysicalDevice physicalDevice,
2250 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
2251 {
2252 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
2253 &pMemoryProperties->memoryProperties);
2254
2255 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
2256 vk_find_struct(pMemoryProperties->pNext,
2257 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
2258 if (memory_budget)
2259 radv_get_memory_budget_properties(physicalDevice, memory_budget);
2260 }
2261
2262 VkResult radv_GetMemoryHostPointerPropertiesEXT(
2263 VkDevice _device,
2264 VkExternalMemoryHandleTypeFlagBits handleType,
2265 const void *pHostPointer,
2266 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
2267 {
2268 RADV_FROM_HANDLE(radv_device, device, _device);
2269
2270 switch (handleType)
2271 {
2272 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
2273 const struct radv_physical_device *physical_device = device->physical_device;
2274 uint32_t memoryTypeBits = 0;
2275 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
2276 if (physical_device->memory_domains[i] == RADEON_DOMAIN_GTT &&
2277 !(physical_device->memory_flags[i] & RADEON_FLAG_GTT_WC)) {
2278 memoryTypeBits = (1 << i);
2279 break;
2280 }
2281 }
2282 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
2283 return VK_SUCCESS;
2284 }
2285 default:
2286 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
2287 }
2288 }
2289
2290 static enum radeon_ctx_priority
2291 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
2292 {
2293 /* Default to MEDIUM when a specific global priority isn't requested */
2294 if (!pObj)
2295 return RADEON_CTX_PRIORITY_MEDIUM;
2296
2297 switch(pObj->globalPriority) {
2298 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
2299 return RADEON_CTX_PRIORITY_REALTIME;
2300 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
2301 return RADEON_CTX_PRIORITY_HIGH;
2302 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
2303 return RADEON_CTX_PRIORITY_MEDIUM;
2304 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
2305 return RADEON_CTX_PRIORITY_LOW;
2306 default:
2307 unreachable("Illegal global priority value");
2308 return RADEON_CTX_PRIORITY_INVALID;
2309 }
2310 }
2311
2312 static int
2313 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
2314 uint32_t queue_family_index, int idx,
2315 VkDeviceQueueCreateFlags flags,
2316 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
2317 {
2318 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2319 queue->device = device;
2320 queue->queue_family_index = queue_family_index;
2321 queue->queue_idx = idx;
2322 queue->priority = radv_get_queue_global_priority(global_priority);
2323 queue->flags = flags;
2324 queue->hw_ctx = NULL;
2325
2326 VkResult result = device->ws->ctx_create(device->ws, queue->priority, &queue->hw_ctx);
2327 if (result != VK_SUCCESS)
2328 return vk_error(device->instance, result);
2329
2330 list_inithead(&queue->pending_submissions);
2331 pthread_mutex_init(&queue->pending_mutex, NULL);
2332
2333 pthread_mutex_init(&queue->thread_mutex, NULL);
2334 queue->thread_submission = NULL;
2335 queue->thread_running = queue->thread_exit = false;
2336 result = radv_create_pthread_cond(&queue->thread_cond);
2337 if (result != VK_SUCCESS)
2338 return vk_error(device->instance, result);
2339
2340 return VK_SUCCESS;
2341 }
2342
2343 static void
2344 radv_queue_finish(struct radv_queue *queue)
2345 {
2346 if (queue->thread_running) {
2347 p_atomic_set(&queue->thread_exit, true);
2348 pthread_cond_broadcast(&queue->thread_cond);
2349 pthread_join(queue->submission_thread, NULL);
2350 }
2351 pthread_cond_destroy(&queue->thread_cond);
2352 pthread_mutex_destroy(&queue->pending_mutex);
2353 pthread_mutex_destroy(&queue->thread_mutex);
2354
2355 if (queue->hw_ctx)
2356 queue->device->ws->ctx_destroy(queue->hw_ctx);
2357
2358 if (queue->initial_full_flush_preamble_cs)
2359 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2360 if (queue->initial_preamble_cs)
2361 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2362 if (queue->continue_preamble_cs)
2363 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2364 if (queue->descriptor_bo)
2365 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2366 if (queue->scratch_bo)
2367 queue->device->ws->buffer_destroy(queue->scratch_bo);
2368 if (queue->esgs_ring_bo)
2369 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2370 if (queue->gsvs_ring_bo)
2371 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2372 if (queue->tess_rings_bo)
2373 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
2374 if (queue->gds_bo)
2375 queue->device->ws->buffer_destroy(queue->gds_bo);
2376 if (queue->gds_oa_bo)
2377 queue->device->ws->buffer_destroy(queue->gds_oa_bo);
2378 if (queue->compute_scratch_bo)
2379 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2380 }
2381
2382 static void
2383 radv_bo_list_init(struct radv_bo_list *bo_list)
2384 {
2385 pthread_mutex_init(&bo_list->mutex, NULL);
2386 bo_list->list.count = bo_list->capacity = 0;
2387 bo_list->list.bos = NULL;
2388 }
2389
2390 static void
2391 radv_bo_list_finish(struct radv_bo_list *bo_list)
2392 {
2393 free(bo_list->list.bos);
2394 pthread_mutex_destroy(&bo_list->mutex);
2395 }
2396
2397 VkResult radv_bo_list_add(struct radv_device *device,
2398 struct radeon_winsys_bo *bo)
2399 {
2400 struct radv_bo_list *bo_list = &device->bo_list;
2401
2402 if (bo->is_local)
2403 return VK_SUCCESS;
2404
2405 if (unlikely(!device->use_global_bo_list))
2406 return VK_SUCCESS;
2407
2408 pthread_mutex_lock(&bo_list->mutex);
2409 if (bo_list->list.count == bo_list->capacity) {
2410 unsigned capacity = MAX2(4, bo_list->capacity * 2);
2411 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
2412
2413 if (!data) {
2414 pthread_mutex_unlock(&bo_list->mutex);
2415 return VK_ERROR_OUT_OF_HOST_MEMORY;
2416 }
2417
2418 bo_list->list.bos = (struct radeon_winsys_bo**)data;
2419 bo_list->capacity = capacity;
2420 }
2421
2422 bo_list->list.bos[bo_list->list.count++] = bo;
2423 pthread_mutex_unlock(&bo_list->mutex);
2424 return VK_SUCCESS;
2425 }
2426
2427 void radv_bo_list_remove(struct radv_device *device,
2428 struct radeon_winsys_bo *bo)
2429 {
2430 struct radv_bo_list *bo_list = &device->bo_list;
2431
2432 if (bo->is_local)
2433 return;
2434
2435 if (unlikely(!device->use_global_bo_list))
2436 return;
2437
2438 pthread_mutex_lock(&bo_list->mutex);
2439 /* Loop the list backwards so we find the most recently added
2440 * memory first. */
2441 for(unsigned i = bo_list->list.count; i-- > 0;) {
2442 if (bo_list->list.bos[i] == bo) {
2443 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
2444 --bo_list->list.count;
2445 break;
2446 }
2447 }
2448 pthread_mutex_unlock(&bo_list->mutex);
2449 }
2450
2451 static void
2452 radv_device_init_gs_info(struct radv_device *device)
2453 {
2454 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
2455 device->physical_device->rad_info.family);
2456 }
2457
2458 static int radv_get_device_extension_index(const char *name)
2459 {
2460 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
2461 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
2462 return i;
2463 }
2464 return -1;
2465 }
2466
2467 static int
2468 radv_get_int_debug_option(const char *name, int default_value)
2469 {
2470 const char *str;
2471 int result;
2472
2473 str = getenv(name);
2474 if (!str) {
2475 result = default_value;
2476 } else {
2477 char *endptr;
2478
2479 result = strtol(str, &endptr, 0);
2480 if (str == endptr) {
2481 /* No digits founs. */
2482 result = default_value;
2483 }
2484 }
2485
2486 return result;
2487 }
2488
2489 static void
2490 radv_device_init_dispatch(struct radv_device *device)
2491 {
2492 const struct radv_instance *instance = device->physical_device->instance;
2493 const struct radv_device_dispatch_table *dispatch_table_layer = NULL;
2494 bool unchecked = instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS;
2495 int radv_thread_trace = radv_get_int_debug_option("RADV_THREAD_TRACE", -1);
2496
2497 if (radv_thread_trace >= 0) {
2498 /* Use device entrypoints from the SQTT layer if enabled. */
2499 dispatch_table_layer = &sqtt_device_dispatch_table;
2500 }
2501
2502 for (unsigned i = 0; i < ARRAY_SIZE(device->dispatch.entrypoints); i++) {
2503 /* Vulkan requires that entrypoints for extensions which have not been
2504 * enabled must not be advertised.
2505 */
2506 if (!unchecked &&
2507 !radv_device_entrypoint_is_enabled(i, instance->apiVersion,
2508 &instance->enabled_extensions,
2509 &device->enabled_extensions)) {
2510 device->dispatch.entrypoints[i] = NULL;
2511 } else if (dispatch_table_layer &&
2512 dispatch_table_layer->entrypoints[i]) {
2513 device->dispatch.entrypoints[i] =
2514 dispatch_table_layer->entrypoints[i];
2515 } else {
2516 device->dispatch.entrypoints[i] =
2517 radv_device_dispatch_table.entrypoints[i];
2518 }
2519 }
2520 }
2521
2522 static VkResult
2523 radv_create_pthread_cond(pthread_cond_t *cond)
2524 {
2525 pthread_condattr_t condattr;
2526 if (pthread_condattr_init(&condattr)) {
2527 return VK_ERROR_INITIALIZATION_FAILED;
2528 }
2529
2530 if (pthread_condattr_setclock(&condattr, CLOCK_MONOTONIC)) {
2531 pthread_condattr_destroy(&condattr);
2532 return VK_ERROR_INITIALIZATION_FAILED;
2533 }
2534 if (pthread_cond_init(cond, &condattr)) {
2535 pthread_condattr_destroy(&condattr);
2536 return VK_ERROR_INITIALIZATION_FAILED;
2537 }
2538 pthread_condattr_destroy(&condattr);
2539 return VK_SUCCESS;
2540 }
2541
2542 static VkResult
2543 check_physical_device_features(VkPhysicalDevice physicalDevice,
2544 const VkPhysicalDeviceFeatures *features)
2545 {
2546 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2547 VkPhysicalDeviceFeatures supported_features;
2548 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
2549 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
2550 VkBool32 *enabled_feature = (VkBool32 *)features;
2551 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
2552 for (uint32_t i = 0; i < num_features; i++) {
2553 if (enabled_feature[i] && !supported_feature[i])
2554 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
2555 }
2556
2557 return VK_SUCCESS;
2558 }
2559
2560 static VkResult radv_device_init_border_color(struct radv_device *device)
2561 {
2562 device->border_color_data.bo =
2563 device->ws->buffer_create(device->ws,
2564 RADV_BORDER_COLOR_BUFFER_SIZE,
2565 4096,
2566 RADEON_DOMAIN_VRAM,
2567 RADEON_FLAG_CPU_ACCESS |
2568 RADEON_FLAG_READ_ONLY |
2569 RADEON_FLAG_NO_INTERPROCESS_SHARING,
2570 RADV_BO_PRIORITY_SHADER);
2571
2572 if (device->border_color_data.bo == NULL)
2573 return vk_error(device->physical_device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2574
2575 device->border_color_data.colors_gpu_ptr =
2576 device->ws->buffer_map(device->border_color_data.bo);
2577 if (!device->border_color_data.colors_gpu_ptr)
2578 return vk_error(device->physical_device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2579 pthread_mutex_init(&device->border_color_data.mutex, NULL);
2580
2581 return VK_SUCCESS;
2582 }
2583
2584 static void radv_device_finish_border_color(struct radv_device *device)
2585 {
2586 if (device->border_color_data.bo) {
2587 device->ws->buffer_destroy(device->border_color_data.bo);
2588
2589 pthread_mutex_destroy(&device->border_color_data.mutex);
2590 }
2591 }
2592
2593 VkResult
2594 _radv_device_set_lost(struct radv_device *device,
2595 const char *file, int line,
2596 const char *msg, ...)
2597 {
2598 VkResult err;
2599 va_list ap;
2600
2601 p_atomic_inc(&device->lost);
2602
2603 va_start(ap, msg);
2604 err = __vk_errorv(device->physical_device->instance, device,
2605 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT,
2606 VK_ERROR_DEVICE_LOST, file, line, msg, ap);
2607 va_end(ap);
2608
2609 return err;
2610 }
2611
2612 VkResult radv_CreateDevice(
2613 VkPhysicalDevice physicalDevice,
2614 const VkDeviceCreateInfo* pCreateInfo,
2615 const VkAllocationCallbacks* pAllocator,
2616 VkDevice* pDevice)
2617 {
2618 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2619 VkResult result;
2620 struct radv_device *device;
2621
2622 bool keep_shader_info = false;
2623 bool robust_buffer_access = false;
2624 bool overallocation_disallowed = false;
2625 bool custom_border_colors = false;
2626
2627 /* Check enabled features */
2628 if (pCreateInfo->pEnabledFeatures) {
2629 result = check_physical_device_features(physicalDevice,
2630 pCreateInfo->pEnabledFeatures);
2631 if (result != VK_SUCCESS)
2632 return result;
2633
2634 if (pCreateInfo->pEnabledFeatures->robustBufferAccess)
2635 robust_buffer_access = true;
2636 }
2637
2638 vk_foreach_struct_const(ext, pCreateInfo->pNext) {
2639 switch (ext->sType) {
2640 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FEATURES_2: {
2641 const VkPhysicalDeviceFeatures2 *features = (const void *)ext;
2642 result = check_physical_device_features(physicalDevice,
2643 &features->features);
2644 if (result != VK_SUCCESS)
2645 return result;
2646
2647 if (features->features.robustBufferAccess)
2648 robust_buffer_access = true;
2649 break;
2650 }
2651 case VK_STRUCTURE_TYPE_DEVICE_MEMORY_OVERALLOCATION_CREATE_INFO_AMD: {
2652 const VkDeviceMemoryOverallocationCreateInfoAMD *overallocation = (const void *)ext;
2653 if (overallocation->overallocationBehavior == VK_MEMORY_OVERALLOCATION_BEHAVIOR_DISALLOWED_AMD)
2654 overallocation_disallowed = true;
2655 break;
2656 }
2657 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_FEATURES_EXT: {
2658 const VkPhysicalDeviceCustomBorderColorFeaturesEXT *border_color_features = (const void *)ext;
2659 custom_border_colors = border_color_features->customBorderColors;
2660 break;
2661 }
2662 default:
2663 break;
2664 }
2665 }
2666
2667 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
2668 sizeof(*device), 8,
2669 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2670 if (!device)
2671 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2672
2673 vk_device_init(&device->vk, pCreateInfo,
2674 &physical_device->instance->alloc, pAllocator);
2675
2676 device->instance = physical_device->instance;
2677 device->physical_device = physical_device;
2678
2679 device->ws = physical_device->ws;
2680
2681 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
2682 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
2683 int index = radv_get_device_extension_index(ext_name);
2684 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
2685 vk_free(&device->vk.alloc, device);
2686 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
2687 }
2688
2689 device->enabled_extensions.extensions[index] = true;
2690 }
2691
2692 radv_device_init_dispatch(device);
2693
2694 keep_shader_info = device->enabled_extensions.AMD_shader_info;
2695
2696 /* With update after bind we can't attach bo's to the command buffer
2697 * from the descriptor set anymore, so we have to use a global BO list.
2698 */
2699 device->use_global_bo_list =
2700 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
2701 device->enabled_extensions.EXT_descriptor_indexing ||
2702 device->enabled_extensions.EXT_buffer_device_address ||
2703 device->enabled_extensions.KHR_buffer_device_address;
2704
2705 device->robust_buffer_access = robust_buffer_access;
2706
2707 mtx_init(&device->shader_slab_mutex, mtx_plain);
2708 list_inithead(&device->shader_slabs);
2709
2710 device->overallocation_disallowed = overallocation_disallowed;
2711 mtx_init(&device->overallocation_mutex, mtx_plain);
2712
2713 radv_bo_list_init(&device->bo_list);
2714
2715 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
2716 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
2717 uint32_t qfi = queue_create->queueFamilyIndex;
2718 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
2719 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
2720
2721 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
2722
2723 device->queues[qfi] = vk_alloc(&device->vk.alloc,
2724 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2725 if (!device->queues[qfi]) {
2726 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2727 goto fail;
2728 }
2729
2730 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
2731
2732 device->queue_count[qfi] = queue_create->queueCount;
2733
2734 for (unsigned q = 0; q < queue_create->queueCount; q++) {
2735 result = radv_queue_init(device, &device->queues[qfi][q],
2736 qfi, q, queue_create->flags,
2737 global_priority);
2738 if (result != VK_SUCCESS)
2739 goto fail;
2740 }
2741 }
2742
2743 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
2744 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
2745
2746 /* Disable DFSM by default. As of 2019-09-15 Talos on Low is still 3% slower on Raven. */
2747 device->dfsm_allowed = device->pbb_allowed &&
2748 (device->instance->perftest_flags & RADV_PERFTEST_DFSM);
2749
2750 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
2751
2752 /* The maximum number of scratch waves. Scratch space isn't divided
2753 * evenly between CUs. The number is only a function of the number of CUs.
2754 * We can decrease the constant to decrease the scratch buffer size.
2755 *
2756 * sctx->scratch_waves must be >= the maximum possible size of
2757 * 1 threadgroup, so that the hw doesn't hang from being unable
2758 * to start any.
2759 *
2760 * The recommended value is 4 per CU at most. Higher numbers don't
2761 * bring much benefit, but they still occupy chip resources (think
2762 * async compute). I've seen ~2% performance difference between 4 and 32.
2763 */
2764 uint32_t max_threads_per_block = 2048;
2765 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
2766 max_threads_per_block / 64);
2767
2768 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
2769
2770 if (device->physical_device->rad_info.chip_class >= GFX7) {
2771 /* If the KMD allows it (there is a KMD hw register for it),
2772 * allow launching waves out-of-order.
2773 */
2774 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
2775 }
2776
2777 radv_device_init_gs_info(device);
2778
2779 device->tess_offchip_block_dw_size =
2780 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
2781
2782 if (getenv("RADV_TRACE_FILE")) {
2783 const char *filename = getenv("RADV_TRACE_FILE");
2784
2785 keep_shader_info = true;
2786
2787 if (!radv_init_trace(device))
2788 goto fail;
2789
2790 fprintf(stderr, "*****************************************************************************\n");
2791 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
2792 fprintf(stderr, "*****************************************************************************\n");
2793
2794 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
2795 radv_dump_enabled_options(device, stderr);
2796 }
2797
2798 int radv_thread_trace = radv_get_int_debug_option("RADV_THREAD_TRACE", -1);
2799 if (radv_thread_trace >= 0) {
2800 fprintf(stderr, "*************************************************\n");
2801 fprintf(stderr, "* WARNING: Thread trace support is experimental *\n");
2802 fprintf(stderr, "*************************************************\n");
2803
2804 if (device->physical_device->rad_info.chip_class < GFX8) {
2805 fprintf(stderr, "GPU hardware not supported: refer to "
2806 "the RGP documentation for the list of "
2807 "supported GPUs!\n");
2808 abort();
2809 }
2810
2811 /* Default buffer size set to 1MB per SE. */
2812 device->thread_trace_buffer_size =
2813 radv_get_int_debug_option("RADV_THREAD_TRACE_BUFFER_SIZE", 1024 * 1024);
2814 device->thread_trace_start_frame = radv_thread_trace;
2815
2816 if (!radv_thread_trace_init(device))
2817 goto fail;
2818 }
2819
2820 device->keep_shader_info = keep_shader_info;
2821 result = radv_device_init_meta(device);
2822 if (result != VK_SUCCESS)
2823 goto fail;
2824
2825 radv_device_init_msaa(device);
2826
2827 /* If the border color extension is enabled, let's create the buffer we need. */
2828 if (custom_border_colors) {
2829 result = radv_device_init_border_color(device);
2830 if (result != VK_SUCCESS)
2831 goto fail;
2832 }
2833
2834 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
2835 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
2836 if (!device->empty_cs[family])
2837 goto fail;
2838
2839 switch (family) {
2840 case RADV_QUEUE_GENERAL:
2841 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2842 radeon_emit(device->empty_cs[family], CC0_UPDATE_LOAD_ENABLES(1));
2843 radeon_emit(device->empty_cs[family], CC1_UPDATE_SHADOW_ENABLES(1));
2844 break;
2845 case RADV_QUEUE_COMPUTE:
2846 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
2847 radeon_emit(device->empty_cs[family], 0);
2848 break;
2849 }
2850
2851 result = device->ws->cs_finalize(device->empty_cs[family]);
2852 if (result != VK_SUCCESS)
2853 goto fail;
2854 }
2855
2856 if (device->physical_device->rad_info.chip_class >= GFX7)
2857 cik_create_gfx_config(device);
2858
2859 VkPipelineCacheCreateInfo ci;
2860 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
2861 ci.pNext = NULL;
2862 ci.flags = 0;
2863 ci.pInitialData = NULL;
2864 ci.initialDataSize = 0;
2865 VkPipelineCache pc;
2866 result = radv_CreatePipelineCache(radv_device_to_handle(device),
2867 &ci, NULL, &pc);
2868 if (result != VK_SUCCESS)
2869 goto fail_meta;
2870
2871 device->mem_cache = radv_pipeline_cache_from_handle(pc);
2872
2873 result = radv_create_pthread_cond(&device->timeline_cond);
2874 if (result != VK_SUCCESS)
2875 goto fail_mem_cache;
2876
2877 device->force_aniso =
2878 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
2879 if (device->force_aniso >= 0) {
2880 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
2881 1 << util_logbase2(device->force_aniso));
2882 }
2883
2884 *pDevice = radv_device_to_handle(device);
2885 return VK_SUCCESS;
2886
2887 fail_mem_cache:
2888 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2889 fail_meta:
2890 radv_device_finish_meta(device);
2891 fail:
2892 radv_bo_list_finish(&device->bo_list);
2893
2894 radv_thread_trace_finish(device);
2895
2896 if (device->trace_bo)
2897 device->ws->buffer_destroy(device->trace_bo);
2898
2899 if (device->gfx_init)
2900 device->ws->buffer_destroy(device->gfx_init);
2901
2902 radv_device_finish_border_color(device);
2903
2904 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2905 for (unsigned q = 0; q < device->queue_count[i]; q++)
2906 radv_queue_finish(&device->queues[i][q]);
2907 if (device->queue_count[i])
2908 vk_free(&device->vk.alloc, device->queues[i]);
2909 }
2910
2911 vk_free(&device->vk.alloc, device);
2912 return result;
2913 }
2914
2915 void radv_DestroyDevice(
2916 VkDevice _device,
2917 const VkAllocationCallbacks* pAllocator)
2918 {
2919 RADV_FROM_HANDLE(radv_device, device, _device);
2920
2921 if (!device)
2922 return;
2923
2924 if (device->trace_bo)
2925 device->ws->buffer_destroy(device->trace_bo);
2926
2927 if (device->gfx_init)
2928 device->ws->buffer_destroy(device->gfx_init);
2929
2930 radv_device_finish_border_color(device);
2931
2932 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2933 for (unsigned q = 0; q < device->queue_count[i]; q++)
2934 radv_queue_finish(&device->queues[i][q]);
2935 if (device->queue_count[i])
2936 vk_free(&device->vk.alloc, device->queues[i]);
2937 if (device->empty_cs[i])
2938 device->ws->cs_destroy(device->empty_cs[i]);
2939 }
2940 radv_device_finish_meta(device);
2941
2942 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
2943 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2944
2945 radv_destroy_shader_slabs(device);
2946
2947 pthread_cond_destroy(&device->timeline_cond);
2948 radv_bo_list_finish(&device->bo_list);
2949
2950 radv_thread_trace_finish(device);
2951
2952 vk_free(&device->vk.alloc, device);
2953 }
2954
2955 VkResult radv_EnumerateInstanceLayerProperties(
2956 uint32_t* pPropertyCount,
2957 VkLayerProperties* pProperties)
2958 {
2959 if (pProperties == NULL) {
2960 *pPropertyCount = 0;
2961 return VK_SUCCESS;
2962 }
2963
2964 /* None supported at this time */
2965 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2966 }
2967
2968 VkResult radv_EnumerateDeviceLayerProperties(
2969 VkPhysicalDevice physicalDevice,
2970 uint32_t* pPropertyCount,
2971 VkLayerProperties* pProperties)
2972 {
2973 if (pProperties == NULL) {
2974 *pPropertyCount = 0;
2975 return VK_SUCCESS;
2976 }
2977
2978 /* None supported at this time */
2979 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2980 }
2981
2982 void radv_GetDeviceQueue2(
2983 VkDevice _device,
2984 const VkDeviceQueueInfo2* pQueueInfo,
2985 VkQueue* pQueue)
2986 {
2987 RADV_FROM_HANDLE(radv_device, device, _device);
2988 struct radv_queue *queue;
2989
2990 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
2991 if (pQueueInfo->flags != queue->flags) {
2992 /* From the Vulkan 1.1.70 spec:
2993 *
2994 * "The queue returned by vkGetDeviceQueue2 must have the same
2995 * flags value from this structure as that used at device
2996 * creation time in a VkDeviceQueueCreateInfo instance. If no
2997 * matching flags were specified at device creation time then
2998 * pQueue will return VK_NULL_HANDLE."
2999 */
3000 *pQueue = VK_NULL_HANDLE;
3001 return;
3002 }
3003
3004 *pQueue = radv_queue_to_handle(queue);
3005 }
3006
3007 void radv_GetDeviceQueue(
3008 VkDevice _device,
3009 uint32_t queueFamilyIndex,
3010 uint32_t queueIndex,
3011 VkQueue* pQueue)
3012 {
3013 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
3014 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
3015 .queueFamilyIndex = queueFamilyIndex,
3016 .queueIndex = queueIndex
3017 };
3018
3019 radv_GetDeviceQueue2(_device, &info, pQueue);
3020 }
3021
3022 static void
3023 fill_geom_tess_rings(struct radv_queue *queue,
3024 uint32_t *map,
3025 bool add_sample_positions,
3026 uint32_t esgs_ring_size,
3027 struct radeon_winsys_bo *esgs_ring_bo,
3028 uint32_t gsvs_ring_size,
3029 struct radeon_winsys_bo *gsvs_ring_bo,
3030 uint32_t tess_factor_ring_size,
3031 uint32_t tess_offchip_ring_offset,
3032 uint32_t tess_offchip_ring_size,
3033 struct radeon_winsys_bo *tess_rings_bo)
3034 {
3035 uint32_t *desc = &map[4];
3036
3037 if (esgs_ring_bo) {
3038 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
3039
3040 /* stride 0, num records - size, add tid, swizzle, elsize4,
3041 index stride 64 */
3042 desc[0] = esgs_va;
3043 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
3044 S_008F04_SWIZZLE_ENABLE(true);
3045 desc[2] = esgs_ring_size;
3046 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3047 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3048 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3049 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
3050 S_008F0C_INDEX_STRIDE(3) |
3051 S_008F0C_ADD_TID_ENABLE(1);
3052
3053 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3054 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3055 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3056 S_008F0C_RESOURCE_LEVEL(1);
3057 } else {
3058 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3059 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
3060 S_008F0C_ELEMENT_SIZE(1);
3061 }
3062
3063 /* GS entry for ES->GS ring */
3064 /* stride 0, num records - size, elsize0,
3065 index stride 0 */
3066 desc[4] = esgs_va;
3067 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32);
3068 desc[6] = esgs_ring_size;
3069 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3070 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3071 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3072 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3073
3074 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3075 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3076 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3077 S_008F0C_RESOURCE_LEVEL(1);
3078 } else {
3079 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3080 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3081 }
3082 }
3083
3084 desc += 8;
3085
3086 if (gsvs_ring_bo) {
3087 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
3088
3089 /* VS entry for GS->VS ring */
3090 /* stride 0, num records - size, elsize0,
3091 index stride 0 */
3092 desc[0] = gsvs_va;
3093 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32);
3094 desc[2] = gsvs_ring_size;
3095 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3096 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3097 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3098 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3099
3100 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3101 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3102 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3103 S_008F0C_RESOURCE_LEVEL(1);
3104 } else {
3105 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3106 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3107 }
3108
3109 /* stride gsvs_itemsize, num records 64
3110 elsize 4, index stride 16 */
3111 /* shader will patch stride and desc[2] */
3112 desc[4] = gsvs_va;
3113 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32) |
3114 S_008F04_SWIZZLE_ENABLE(1);
3115 desc[6] = 0;
3116 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3117 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3118 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3119 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
3120 S_008F0C_INDEX_STRIDE(1) |
3121 S_008F0C_ADD_TID_ENABLE(true);
3122
3123 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3124 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3125 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3126 S_008F0C_RESOURCE_LEVEL(1);
3127 } else {
3128 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3129 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
3130 S_008F0C_ELEMENT_SIZE(1);
3131 }
3132
3133 }
3134
3135 desc += 8;
3136
3137 if (tess_rings_bo) {
3138 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
3139 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
3140
3141 desc[0] = tess_va;
3142 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32);
3143 desc[2] = tess_factor_ring_size;
3144 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3145 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3146 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3147 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3148
3149 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3150 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3151 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3152 S_008F0C_RESOURCE_LEVEL(1);
3153 } else {
3154 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3155 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3156 }
3157
3158 desc[4] = tess_offchip_va;
3159 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32);
3160 desc[6] = tess_offchip_ring_size;
3161 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3162 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3163 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3164 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3165
3166 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3167 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3168 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3169 S_008F0C_RESOURCE_LEVEL(1);
3170 } else {
3171 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3172 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3173 }
3174 }
3175
3176 desc += 8;
3177
3178 if (add_sample_positions) {
3179 /* add sample positions after all rings */
3180 memcpy(desc, queue->device->sample_locations_1x, 8);
3181 desc += 2;
3182 memcpy(desc, queue->device->sample_locations_2x, 16);
3183 desc += 4;
3184 memcpy(desc, queue->device->sample_locations_4x, 32);
3185 desc += 8;
3186 memcpy(desc, queue->device->sample_locations_8x, 64);
3187 }
3188 }
3189
3190 static unsigned
3191 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
3192 {
3193 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 &&
3194 device->physical_device->rad_info.family != CHIP_CARRIZO &&
3195 device->physical_device->rad_info.family != CHIP_STONEY;
3196 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
3197 unsigned max_offchip_buffers;
3198 unsigned offchip_granularity;
3199 unsigned hs_offchip_param;
3200
3201 /*
3202 * Per RadeonSI:
3203 * This must be one less than the maximum number due to a hw limitation.
3204 * Various hardware bugs need thGFX7
3205 *
3206 * Per AMDVLK:
3207 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
3208 * Gfx7 should limit max_offchip_buffers to 508
3209 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
3210 *
3211 * Follow AMDVLK here.
3212 */
3213 if (device->physical_device->rad_info.chip_class >= GFX10) {
3214 max_offchip_buffers_per_se = 256;
3215 } else if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
3216 device->physical_device->rad_info.chip_class == GFX7 ||
3217 device->physical_device->rad_info.chip_class == GFX6)
3218 --max_offchip_buffers_per_se;
3219
3220 max_offchip_buffers = max_offchip_buffers_per_se *
3221 device->physical_device->rad_info.max_se;
3222
3223 /* Hawaii has a bug with offchip buffers > 256 that can be worked
3224 * around by setting 4K granularity.
3225 */
3226 if (device->tess_offchip_block_dw_size == 4096) {
3227 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
3228 offchip_granularity = V_03093C_X_4K_DWORDS;
3229 } else {
3230 assert(device->tess_offchip_block_dw_size == 8192);
3231 offchip_granularity = V_03093C_X_8K_DWORDS;
3232 }
3233
3234 switch (device->physical_device->rad_info.chip_class) {
3235 case GFX6:
3236 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
3237 break;
3238 case GFX7:
3239 case GFX8:
3240 case GFX9:
3241 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
3242 break;
3243 case GFX10:
3244 break;
3245 default:
3246 break;
3247 }
3248
3249 *max_offchip_buffers_p = max_offchip_buffers;
3250 if (device->physical_device->rad_info.chip_class >= GFX10_3) {
3251 hs_offchip_param = S_03093C_OFFCHIP_BUFFERING_GFX103(max_offchip_buffers - 1) |
3252 S_03093C_OFFCHIP_GRANULARITY_GFX103(offchip_granularity);
3253 } else if (device->physical_device->rad_info.chip_class >= GFX7) {
3254 if (device->physical_device->rad_info.chip_class >= GFX8)
3255 --max_offchip_buffers;
3256 hs_offchip_param =
3257 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
3258 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
3259 } else {
3260 hs_offchip_param =
3261 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
3262 }
3263 return hs_offchip_param;
3264 }
3265
3266 static void
3267 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3268 struct radeon_winsys_bo *esgs_ring_bo,
3269 uint32_t esgs_ring_size,
3270 struct radeon_winsys_bo *gsvs_ring_bo,
3271 uint32_t gsvs_ring_size)
3272 {
3273 if (!esgs_ring_bo && !gsvs_ring_bo)
3274 return;
3275
3276 if (esgs_ring_bo)
3277 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
3278
3279 if (gsvs_ring_bo)
3280 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
3281
3282 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
3283 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
3284 radeon_emit(cs, esgs_ring_size >> 8);
3285 radeon_emit(cs, gsvs_ring_size >> 8);
3286 } else {
3287 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
3288 radeon_emit(cs, esgs_ring_size >> 8);
3289 radeon_emit(cs, gsvs_ring_size >> 8);
3290 }
3291 }
3292
3293 static void
3294 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3295 unsigned hs_offchip_param, unsigned tf_ring_size,
3296 struct radeon_winsys_bo *tess_rings_bo)
3297 {
3298 uint64_t tf_va;
3299
3300 if (!tess_rings_bo)
3301 return;
3302
3303 tf_va = radv_buffer_get_va(tess_rings_bo);
3304
3305 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
3306
3307 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
3308 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
3309 S_030938_SIZE(tf_ring_size / 4));
3310 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
3311 tf_va >> 8);
3312
3313 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3314 radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3315 S_030984_BASE_HI(tf_va >> 40));
3316 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
3317 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
3318 S_030944_BASE_HI(tf_va >> 40));
3319 }
3320 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
3321 hs_offchip_param);
3322 } else {
3323 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
3324 S_008988_SIZE(tf_ring_size / 4));
3325 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
3326 tf_va >> 8);
3327 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3328 hs_offchip_param);
3329 }
3330 }
3331
3332 static void
3333 radv_emit_graphics_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3334 uint32_t size_per_wave, uint32_t waves,
3335 struct radeon_winsys_bo *scratch_bo)
3336 {
3337 if (queue->queue_family_index != RADV_QUEUE_GENERAL)
3338 return;
3339
3340 if (!scratch_bo)
3341 return;
3342
3343 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
3344
3345 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
3346 S_0286E8_WAVES(waves) |
3347 S_0286E8_WAVESIZE(round_up_u32(size_per_wave, 1024)));
3348 }
3349
3350 static void
3351 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3352 uint32_t size_per_wave, uint32_t waves,
3353 struct radeon_winsys_bo *compute_scratch_bo)
3354 {
3355 uint64_t scratch_va;
3356
3357 if (!compute_scratch_bo)
3358 return;
3359
3360 scratch_va = radv_buffer_get_va(compute_scratch_bo);
3361
3362 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
3363
3364 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
3365 radeon_emit(cs, scratch_va);
3366 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
3367 S_008F04_SWIZZLE_ENABLE(1));
3368
3369 radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
3370 S_00B860_WAVES(waves) |
3371 S_00B860_WAVESIZE(round_up_u32(size_per_wave, 1024)));
3372 }
3373
3374 static void
3375 radv_emit_global_shader_pointers(struct radv_queue *queue,
3376 struct radeon_cmdbuf *cs,
3377 struct radeon_winsys_bo *descriptor_bo)
3378 {
3379 uint64_t va;
3380
3381 if (!descriptor_bo)
3382 return;
3383
3384 va = radv_buffer_get_va(descriptor_bo);
3385
3386 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
3387
3388 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3389 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3390 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3391 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
3392 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
3393
3394 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3395 radv_emit_shader_pointer(queue->device, cs, regs[i],
3396 va, true);
3397 }
3398 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
3399 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3400 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3401 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
3402 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
3403
3404 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3405 radv_emit_shader_pointer(queue->device, cs, regs[i],
3406 va, true);
3407 }
3408 } else {
3409 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3410 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3411 R_00B230_SPI_SHADER_USER_DATA_GS_0,
3412 R_00B330_SPI_SHADER_USER_DATA_ES_0,
3413 R_00B430_SPI_SHADER_USER_DATA_HS_0,
3414 R_00B530_SPI_SHADER_USER_DATA_LS_0};
3415
3416 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3417 radv_emit_shader_pointer(queue->device, cs, regs[i],
3418 va, true);
3419 }
3420 }
3421 }
3422
3423 static void
3424 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
3425 {
3426 struct radv_device *device = queue->device;
3427
3428 if (device->gfx_init) {
3429 uint64_t va = radv_buffer_get_va(device->gfx_init);
3430
3431 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
3432 radeon_emit(cs, va);
3433 radeon_emit(cs, va >> 32);
3434 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
3435
3436 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
3437 } else {
3438 si_emit_graphics(device, cs);
3439 }
3440 }
3441
3442 static void
3443 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
3444 {
3445 si_emit_compute(queue->device, cs);
3446 }
3447
3448 static VkResult
3449 radv_get_preamble_cs(struct radv_queue *queue,
3450 uint32_t scratch_size_per_wave,
3451 uint32_t scratch_waves,
3452 uint32_t compute_scratch_size_per_wave,
3453 uint32_t compute_scratch_waves,
3454 uint32_t esgs_ring_size,
3455 uint32_t gsvs_ring_size,
3456 bool needs_tess_rings,
3457 bool needs_gds,
3458 bool needs_gds_oa,
3459 bool needs_sample_positions,
3460 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
3461 struct radeon_cmdbuf **initial_preamble_cs,
3462 struct radeon_cmdbuf **continue_preamble_cs)
3463 {
3464 struct radeon_winsys_bo *scratch_bo = NULL;
3465 struct radeon_winsys_bo *descriptor_bo = NULL;
3466 struct radeon_winsys_bo *compute_scratch_bo = NULL;
3467 struct radeon_winsys_bo *esgs_ring_bo = NULL;
3468 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
3469 struct radeon_winsys_bo *tess_rings_bo = NULL;
3470 struct radeon_winsys_bo *gds_bo = NULL;
3471 struct radeon_winsys_bo *gds_oa_bo = NULL;
3472 struct radeon_cmdbuf *dest_cs[3] = {0};
3473 bool add_tess_rings = false, add_gds = false, add_gds_oa = false, add_sample_positions = false;
3474 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
3475 unsigned max_offchip_buffers;
3476 unsigned hs_offchip_param = 0;
3477 unsigned tess_offchip_ring_offset;
3478 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
3479 if (!queue->has_tess_rings) {
3480 if (needs_tess_rings)
3481 add_tess_rings = true;
3482 }
3483 if (!queue->has_gds) {
3484 if (needs_gds)
3485 add_gds = true;
3486 }
3487 if (!queue->has_gds_oa) {
3488 if (needs_gds_oa)
3489 add_gds_oa = true;
3490 }
3491 if (!queue->has_sample_positions) {
3492 if (needs_sample_positions)
3493 add_sample_positions = true;
3494 }
3495 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
3496 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
3497 &max_offchip_buffers);
3498 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
3499 tess_offchip_ring_size = max_offchip_buffers *
3500 queue->device->tess_offchip_block_dw_size * 4;
3501
3502 scratch_size_per_wave = MAX2(scratch_size_per_wave, queue->scratch_size_per_wave);
3503 if (scratch_size_per_wave)
3504 scratch_waves = MIN2(scratch_waves, UINT32_MAX / scratch_size_per_wave);
3505 else
3506 scratch_waves = 0;
3507
3508 compute_scratch_size_per_wave = MAX2(compute_scratch_size_per_wave, queue->compute_scratch_size_per_wave);
3509 if (compute_scratch_size_per_wave)
3510 compute_scratch_waves = MIN2(compute_scratch_waves, UINT32_MAX / compute_scratch_size_per_wave);
3511 else
3512 compute_scratch_waves = 0;
3513
3514 if (scratch_size_per_wave <= queue->scratch_size_per_wave &&
3515 scratch_waves <= queue->scratch_waves &&
3516 compute_scratch_size_per_wave <= queue->compute_scratch_size_per_wave &&
3517 compute_scratch_waves <= queue->compute_scratch_waves &&
3518 esgs_ring_size <= queue->esgs_ring_size &&
3519 gsvs_ring_size <= queue->gsvs_ring_size &&
3520 !add_tess_rings && !add_gds && !add_gds_oa && !add_sample_positions &&
3521 queue->initial_preamble_cs) {
3522 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
3523 *initial_preamble_cs = queue->initial_preamble_cs;
3524 *continue_preamble_cs = queue->continue_preamble_cs;
3525 if (!scratch_size_per_wave && !compute_scratch_size_per_wave &&
3526 !esgs_ring_size && !gsvs_ring_size && !needs_tess_rings &&
3527 !needs_gds && !needs_gds_oa && !needs_sample_positions)
3528 *continue_preamble_cs = NULL;
3529 return VK_SUCCESS;
3530 }
3531
3532 uint32_t scratch_size = scratch_size_per_wave * scratch_waves;
3533 uint32_t queue_scratch_size = queue->scratch_size_per_wave * queue->scratch_waves;
3534 if (scratch_size > queue_scratch_size) {
3535 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
3536 scratch_size,
3537 4096,
3538 RADEON_DOMAIN_VRAM,
3539 ring_bo_flags,
3540 RADV_BO_PRIORITY_SCRATCH);
3541 if (!scratch_bo)
3542 goto fail;
3543 } else
3544 scratch_bo = queue->scratch_bo;
3545
3546 uint32_t compute_scratch_size = compute_scratch_size_per_wave * compute_scratch_waves;
3547 uint32_t compute_queue_scratch_size = queue->compute_scratch_size_per_wave * queue->compute_scratch_waves;
3548 if (compute_scratch_size > compute_queue_scratch_size) {
3549 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
3550 compute_scratch_size,
3551 4096,
3552 RADEON_DOMAIN_VRAM,
3553 ring_bo_flags,
3554 RADV_BO_PRIORITY_SCRATCH);
3555 if (!compute_scratch_bo)
3556 goto fail;
3557
3558 } else
3559 compute_scratch_bo = queue->compute_scratch_bo;
3560
3561 if (esgs_ring_size > queue->esgs_ring_size) {
3562 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
3563 esgs_ring_size,
3564 4096,
3565 RADEON_DOMAIN_VRAM,
3566 ring_bo_flags,
3567 RADV_BO_PRIORITY_SCRATCH);
3568 if (!esgs_ring_bo)
3569 goto fail;
3570 } else {
3571 esgs_ring_bo = queue->esgs_ring_bo;
3572 esgs_ring_size = queue->esgs_ring_size;
3573 }
3574
3575 if (gsvs_ring_size > queue->gsvs_ring_size) {
3576 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
3577 gsvs_ring_size,
3578 4096,
3579 RADEON_DOMAIN_VRAM,
3580 ring_bo_flags,
3581 RADV_BO_PRIORITY_SCRATCH);
3582 if (!gsvs_ring_bo)
3583 goto fail;
3584 } else {
3585 gsvs_ring_bo = queue->gsvs_ring_bo;
3586 gsvs_ring_size = queue->gsvs_ring_size;
3587 }
3588
3589 if (add_tess_rings) {
3590 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
3591 tess_offchip_ring_offset + tess_offchip_ring_size,
3592 256,
3593 RADEON_DOMAIN_VRAM,
3594 ring_bo_flags,
3595 RADV_BO_PRIORITY_SCRATCH);
3596 if (!tess_rings_bo)
3597 goto fail;
3598 } else {
3599 tess_rings_bo = queue->tess_rings_bo;
3600 }
3601
3602 if (add_gds) {
3603 assert(queue->device->physical_device->rad_info.chip_class >= GFX10);
3604
3605 /* 4 streamout GDS counters.
3606 * We need 256B (64 dw) of GDS, otherwise streamout hangs.
3607 */
3608 gds_bo = queue->device->ws->buffer_create(queue->device->ws,
3609 256, 4,
3610 RADEON_DOMAIN_GDS,
3611 ring_bo_flags,
3612 RADV_BO_PRIORITY_SCRATCH);
3613 if (!gds_bo)
3614 goto fail;
3615 } else {
3616 gds_bo = queue->gds_bo;
3617 }
3618
3619 if (add_gds_oa) {
3620 assert(queue->device->physical_device->rad_info.chip_class >= GFX10);
3621
3622 gds_oa_bo = queue->device->ws->buffer_create(queue->device->ws,
3623 4, 1,
3624 RADEON_DOMAIN_OA,
3625 ring_bo_flags,
3626 RADV_BO_PRIORITY_SCRATCH);
3627 if (!gds_oa_bo)
3628 goto fail;
3629 } else {
3630 gds_oa_bo = queue->gds_oa_bo;
3631 }
3632
3633 if (scratch_bo != queue->scratch_bo ||
3634 esgs_ring_bo != queue->esgs_ring_bo ||
3635 gsvs_ring_bo != queue->gsvs_ring_bo ||
3636 tess_rings_bo != queue->tess_rings_bo ||
3637 add_sample_positions) {
3638 uint32_t size = 0;
3639 if (gsvs_ring_bo || esgs_ring_bo ||
3640 tess_rings_bo || add_sample_positions) {
3641 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
3642 if (add_sample_positions)
3643 size += 128; /* 64+32+16+8 = 120 bytes */
3644 }
3645 else if (scratch_bo)
3646 size = 8; /* 2 dword */
3647
3648 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
3649 size,
3650 4096,
3651 RADEON_DOMAIN_VRAM,
3652 RADEON_FLAG_CPU_ACCESS |
3653 RADEON_FLAG_NO_INTERPROCESS_SHARING |
3654 RADEON_FLAG_READ_ONLY,
3655 RADV_BO_PRIORITY_DESCRIPTOR);
3656 if (!descriptor_bo)
3657 goto fail;
3658 } else
3659 descriptor_bo = queue->descriptor_bo;
3660
3661 if (descriptor_bo != queue->descriptor_bo) {
3662 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
3663 if (!map)
3664 goto fail;
3665
3666 if (scratch_bo) {
3667 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
3668 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
3669 S_008F04_SWIZZLE_ENABLE(1);
3670 map[0] = scratch_va;
3671 map[1] = rsrc1;
3672 }
3673
3674 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
3675 fill_geom_tess_rings(queue, map, add_sample_positions,
3676 esgs_ring_size, esgs_ring_bo,
3677 gsvs_ring_size, gsvs_ring_bo,
3678 tess_factor_ring_size,
3679 tess_offchip_ring_offset,
3680 tess_offchip_ring_size,
3681 tess_rings_bo);
3682
3683 queue->device->ws->buffer_unmap(descriptor_bo);
3684 }
3685
3686 for(int i = 0; i < 3; ++i) {
3687 struct radeon_cmdbuf *cs = NULL;
3688 cs = queue->device->ws->cs_create(queue->device->ws,
3689 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
3690 if (!cs)
3691 goto fail;
3692
3693 dest_cs[i] = cs;
3694
3695 if (scratch_bo)
3696 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
3697
3698 /* Emit initial configuration. */
3699 switch (queue->queue_family_index) {
3700 case RADV_QUEUE_GENERAL:
3701 radv_init_graphics_state(cs, queue);
3702 break;
3703 case RADV_QUEUE_COMPUTE:
3704 radv_init_compute_state(cs, queue);
3705 break;
3706 case RADV_QUEUE_TRANSFER:
3707 break;
3708 }
3709
3710 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
3711 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3712 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3713
3714 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3715 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
3716 }
3717
3718 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
3719 gsvs_ring_bo, gsvs_ring_size);
3720 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
3721 tess_factor_ring_size, tess_rings_bo);
3722 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
3723 radv_emit_compute_scratch(queue, cs, compute_scratch_size_per_wave,
3724 compute_scratch_waves, compute_scratch_bo);
3725 radv_emit_graphics_scratch(queue, cs, scratch_size_per_wave,
3726 scratch_waves, scratch_bo);
3727
3728 if (gds_bo)
3729 radv_cs_add_buffer(queue->device->ws, cs, gds_bo);
3730 if (gds_oa_bo)
3731 radv_cs_add_buffer(queue->device->ws, cs, gds_oa_bo);
3732
3733 if (queue->device->trace_bo)
3734 radv_cs_add_buffer(queue->device->ws, cs, queue->device->trace_bo);
3735
3736 if (queue->device->border_color_data.bo)
3737 radv_cs_add_buffer(queue->device->ws, cs,
3738 queue->device->border_color_data.bo);
3739
3740 if (i == 0) {
3741 si_cs_emit_cache_flush(cs,
3742 queue->device->physical_device->rad_info.chip_class,
3743 NULL, 0,
3744 queue->queue_family_index == RING_COMPUTE &&
3745 queue->device->physical_device->rad_info.chip_class >= GFX7,
3746 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
3747 RADV_CMD_FLAG_INV_ICACHE |
3748 RADV_CMD_FLAG_INV_SCACHE |
3749 RADV_CMD_FLAG_INV_VCACHE |
3750 RADV_CMD_FLAG_INV_L2 |
3751 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
3752 } else if (i == 1) {
3753 si_cs_emit_cache_flush(cs,
3754 queue->device->physical_device->rad_info.chip_class,
3755 NULL, 0,
3756 queue->queue_family_index == RING_COMPUTE &&
3757 queue->device->physical_device->rad_info.chip_class >= GFX7,
3758 RADV_CMD_FLAG_INV_ICACHE |
3759 RADV_CMD_FLAG_INV_SCACHE |
3760 RADV_CMD_FLAG_INV_VCACHE |
3761 RADV_CMD_FLAG_INV_L2 |
3762 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
3763 }
3764
3765 if (queue->device->ws->cs_finalize(cs) != VK_SUCCESS)
3766 goto fail;
3767 }
3768
3769 if (queue->initial_full_flush_preamble_cs)
3770 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
3771
3772 if (queue->initial_preamble_cs)
3773 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
3774
3775 if (queue->continue_preamble_cs)
3776 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
3777
3778 queue->initial_full_flush_preamble_cs = dest_cs[0];
3779 queue->initial_preamble_cs = dest_cs[1];
3780 queue->continue_preamble_cs = dest_cs[2];
3781
3782 if (scratch_bo != queue->scratch_bo) {
3783 if (queue->scratch_bo)
3784 queue->device->ws->buffer_destroy(queue->scratch_bo);
3785 queue->scratch_bo = scratch_bo;
3786 }
3787 queue->scratch_size_per_wave = scratch_size_per_wave;
3788 queue->scratch_waves = scratch_waves;
3789
3790 if (compute_scratch_bo != queue->compute_scratch_bo) {
3791 if (queue->compute_scratch_bo)
3792 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
3793 queue->compute_scratch_bo = compute_scratch_bo;
3794 }
3795 queue->compute_scratch_size_per_wave = compute_scratch_size_per_wave;
3796 queue->compute_scratch_waves = compute_scratch_waves;
3797
3798 if (esgs_ring_bo != queue->esgs_ring_bo) {
3799 if (queue->esgs_ring_bo)
3800 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
3801 queue->esgs_ring_bo = esgs_ring_bo;
3802 queue->esgs_ring_size = esgs_ring_size;
3803 }
3804
3805 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
3806 if (queue->gsvs_ring_bo)
3807 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
3808 queue->gsvs_ring_bo = gsvs_ring_bo;
3809 queue->gsvs_ring_size = gsvs_ring_size;
3810 }
3811
3812 if (tess_rings_bo != queue->tess_rings_bo) {
3813 queue->tess_rings_bo = tess_rings_bo;
3814 queue->has_tess_rings = true;
3815 }
3816
3817 if (gds_bo != queue->gds_bo) {
3818 queue->gds_bo = gds_bo;
3819 queue->has_gds = true;
3820 }
3821
3822 if (gds_oa_bo != queue->gds_oa_bo) {
3823 queue->gds_oa_bo = gds_oa_bo;
3824 queue->has_gds_oa = true;
3825 }
3826
3827 if (descriptor_bo != queue->descriptor_bo) {
3828 if (queue->descriptor_bo)
3829 queue->device->ws->buffer_destroy(queue->descriptor_bo);
3830
3831 queue->descriptor_bo = descriptor_bo;
3832 }
3833
3834 if (add_sample_positions)
3835 queue->has_sample_positions = true;
3836
3837 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
3838 *initial_preamble_cs = queue->initial_preamble_cs;
3839 *continue_preamble_cs = queue->continue_preamble_cs;
3840 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
3841 *continue_preamble_cs = NULL;
3842 return VK_SUCCESS;
3843 fail:
3844 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
3845 if (dest_cs[i])
3846 queue->device->ws->cs_destroy(dest_cs[i]);
3847 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
3848 queue->device->ws->buffer_destroy(descriptor_bo);
3849 if (scratch_bo && scratch_bo != queue->scratch_bo)
3850 queue->device->ws->buffer_destroy(scratch_bo);
3851 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
3852 queue->device->ws->buffer_destroy(compute_scratch_bo);
3853 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
3854 queue->device->ws->buffer_destroy(esgs_ring_bo);
3855 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
3856 queue->device->ws->buffer_destroy(gsvs_ring_bo);
3857 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
3858 queue->device->ws->buffer_destroy(tess_rings_bo);
3859 if (gds_bo && gds_bo != queue->gds_bo)
3860 queue->device->ws->buffer_destroy(gds_bo);
3861 if (gds_oa_bo && gds_oa_bo != queue->gds_oa_bo)
3862 queue->device->ws->buffer_destroy(gds_oa_bo);
3863
3864 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3865 }
3866
3867 static VkResult radv_alloc_sem_counts(struct radv_device *device,
3868 struct radv_winsys_sem_counts *counts,
3869 int num_sems,
3870 struct radv_semaphore_part **sems,
3871 const uint64_t *timeline_values,
3872 VkFence _fence,
3873 bool is_signal)
3874 {
3875 int syncobj_idx = 0, non_reset_idx = 0, sem_idx = 0, timeline_idx = 0;
3876
3877 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
3878 return VK_SUCCESS;
3879
3880 for (uint32_t i = 0; i < num_sems; i++) {
3881 switch(sems[i]->kind) {
3882 case RADV_SEMAPHORE_SYNCOBJ:
3883 counts->syncobj_count++;
3884 counts->syncobj_reset_count++;
3885 break;
3886 case RADV_SEMAPHORE_WINSYS:
3887 counts->sem_count++;
3888 break;
3889 case RADV_SEMAPHORE_NONE:
3890 break;
3891 case RADV_SEMAPHORE_TIMELINE:
3892 counts->syncobj_count++;
3893 break;
3894 case RADV_SEMAPHORE_TIMELINE_SYNCOBJ:
3895 counts->timeline_syncobj_count++;
3896 break;
3897 }
3898 }
3899
3900 if (_fence != VK_NULL_HANDLE) {
3901 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3902
3903 struct radv_fence_part *part =
3904 fence->temporary.kind != RADV_FENCE_NONE ?
3905 &fence->temporary : &fence->permanent;
3906 if (part->kind == RADV_FENCE_SYNCOBJ)
3907 counts->syncobj_count++;
3908 }
3909
3910 if (counts->syncobj_count || counts->timeline_syncobj_count) {
3911 counts->points = (uint64_t *)malloc(
3912 sizeof(*counts->syncobj) * counts->syncobj_count +
3913 (sizeof(*counts->syncobj) + sizeof(*counts->points)) * counts->timeline_syncobj_count);
3914 if (!counts->points)
3915 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3916 counts->syncobj = (uint32_t*)(counts->points + counts->timeline_syncobj_count);
3917 }
3918
3919 if (counts->sem_count) {
3920 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
3921 if (!counts->sem) {
3922 free(counts->syncobj);
3923 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3924 }
3925 }
3926
3927 non_reset_idx = counts->syncobj_reset_count;
3928
3929 for (uint32_t i = 0; i < num_sems; i++) {
3930 switch(sems[i]->kind) {
3931 case RADV_SEMAPHORE_NONE:
3932 unreachable("Empty semaphore");
3933 break;
3934 case RADV_SEMAPHORE_SYNCOBJ:
3935 counts->syncobj[syncobj_idx++] = sems[i]->syncobj;
3936 break;
3937 case RADV_SEMAPHORE_WINSYS:
3938 counts->sem[sem_idx++] = sems[i]->ws_sem;
3939 break;
3940 case RADV_SEMAPHORE_TIMELINE: {
3941 pthread_mutex_lock(&sems[i]->timeline.mutex);
3942 struct radv_timeline_point *point = NULL;
3943 if (is_signal) {
3944 point = radv_timeline_add_point_locked(device, &sems[i]->timeline, timeline_values[i]);
3945 } else {
3946 point = radv_timeline_find_point_at_least_locked(device, &sems[i]->timeline, timeline_values[i]);
3947 }
3948
3949 pthread_mutex_unlock(&sems[i]->timeline.mutex);
3950
3951 if (point) {
3952 counts->syncobj[non_reset_idx++] = point->syncobj;
3953 } else {
3954 /* Explicitly remove the semaphore so we might not find
3955 * a point later post-submit. */
3956 sems[i] = NULL;
3957 }
3958 break;
3959 }
3960 case RADV_SEMAPHORE_TIMELINE_SYNCOBJ:
3961 counts->syncobj[counts->syncobj_count + timeline_idx] = sems[i]->syncobj;
3962 counts->points[timeline_idx] = timeline_values[i];
3963 ++timeline_idx;
3964 break;
3965 }
3966 }
3967
3968 if (_fence != VK_NULL_HANDLE) {
3969 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3970
3971 struct radv_fence_part *part =
3972 fence->temporary.kind != RADV_FENCE_NONE ?
3973 &fence->temporary : &fence->permanent;
3974 if (part->kind == RADV_FENCE_SYNCOBJ)
3975 counts->syncobj[non_reset_idx++] = part->syncobj;
3976 }
3977
3978 assert(MAX2(syncobj_idx, non_reset_idx) <= counts->syncobj_count);
3979 counts->syncobj_count = MAX2(syncobj_idx, non_reset_idx);
3980
3981 return VK_SUCCESS;
3982 }
3983
3984 static void
3985 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
3986 {
3987 free(sem_info->wait.points);
3988 free(sem_info->wait.sem);
3989 free(sem_info->signal.points);
3990 free(sem_info->signal.sem);
3991 }
3992
3993
3994 static void radv_free_temp_syncobjs(struct radv_device *device,
3995 int num_sems,
3996 struct radv_semaphore_part *sems)
3997 {
3998 for (uint32_t i = 0; i < num_sems; i++) {
3999 radv_destroy_semaphore_part(device, sems + i);
4000 }
4001 }
4002
4003 static VkResult
4004 radv_alloc_sem_info(struct radv_device *device,
4005 struct radv_winsys_sem_info *sem_info,
4006 int num_wait_sems,
4007 struct radv_semaphore_part **wait_sems,
4008 const uint64_t *wait_values,
4009 int num_signal_sems,
4010 struct radv_semaphore_part **signal_sems,
4011 const uint64_t *signal_values,
4012 VkFence fence)
4013 {
4014 VkResult ret;
4015 memset(sem_info, 0, sizeof(*sem_info));
4016
4017 ret = radv_alloc_sem_counts(device, &sem_info->wait, num_wait_sems, wait_sems, wait_values, VK_NULL_HANDLE, false);
4018 if (ret)
4019 return ret;
4020 ret = radv_alloc_sem_counts(device, &sem_info->signal, num_signal_sems, signal_sems, signal_values, fence, true);
4021 if (ret)
4022 radv_free_sem_info(sem_info);
4023
4024 /* caller can override these */
4025 sem_info->cs_emit_wait = true;
4026 sem_info->cs_emit_signal = true;
4027 return ret;
4028 }
4029
4030 static void
4031 radv_finalize_timelines(struct radv_device *device,
4032 uint32_t num_wait_sems,
4033 struct radv_semaphore_part **wait_sems,
4034 const uint64_t *wait_values,
4035 uint32_t num_signal_sems,
4036 struct radv_semaphore_part **signal_sems,
4037 const uint64_t *signal_values,
4038 struct list_head *processing_list)
4039 {
4040 for (uint32_t i = 0; i < num_wait_sems; ++i) {
4041 if (wait_sems[i] && wait_sems[i]->kind == RADV_SEMAPHORE_TIMELINE) {
4042 pthread_mutex_lock(&wait_sems[i]->timeline.mutex);
4043 struct radv_timeline_point *point =
4044 radv_timeline_find_point_at_least_locked(device, &wait_sems[i]->timeline, wait_values[i]);
4045 point->wait_count -= 2;
4046 pthread_mutex_unlock(&wait_sems[i]->timeline.mutex);
4047 }
4048 }
4049 for (uint32_t i = 0; i < num_signal_sems; ++i) {
4050 if (signal_sems[i] && signal_sems[i]->kind == RADV_SEMAPHORE_TIMELINE) {
4051 pthread_mutex_lock(&signal_sems[i]->timeline.mutex);
4052 struct radv_timeline_point *point =
4053 radv_timeline_find_point_at_least_locked(device, &signal_sems[i]->timeline, signal_values[i]);
4054 signal_sems[i]->timeline.highest_submitted =
4055 MAX2(signal_sems[i]->timeline.highest_submitted, point->value);
4056 point->wait_count -= 2;
4057 radv_timeline_trigger_waiters_locked(&signal_sems[i]->timeline, processing_list);
4058 pthread_mutex_unlock(&signal_sems[i]->timeline.mutex);
4059 } else if (signal_sems[i] && signal_sems[i]->kind == RADV_SEMAPHORE_TIMELINE_SYNCOBJ) {
4060 signal_sems[i]->timeline_syncobj.max_point =
4061 MAX2(signal_sems[i]->timeline_syncobj.max_point, signal_values[i]);
4062 }
4063 }
4064 }
4065
4066 static VkResult
4067 radv_sparse_buffer_bind_memory(struct radv_device *device,
4068 const VkSparseBufferMemoryBindInfo *bind)
4069 {
4070 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
4071 VkResult result;
4072
4073 for (uint32_t i = 0; i < bind->bindCount; ++i) {
4074 struct radv_device_memory *mem = NULL;
4075
4076 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
4077 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
4078
4079 result = device->ws->buffer_virtual_bind(buffer->bo,
4080 bind->pBinds[i].resourceOffset,
4081 bind->pBinds[i].size,
4082 mem ? mem->bo : NULL,
4083 bind->pBinds[i].memoryOffset);
4084 if (result != VK_SUCCESS)
4085 return result;
4086 }
4087
4088 return VK_SUCCESS;
4089 }
4090
4091 static VkResult
4092 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
4093 const VkSparseImageOpaqueMemoryBindInfo *bind)
4094 {
4095 RADV_FROM_HANDLE(radv_image, image, bind->image);
4096 VkResult result;
4097
4098 for (uint32_t i = 0; i < bind->bindCount; ++i) {
4099 struct radv_device_memory *mem = NULL;
4100
4101 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
4102 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
4103
4104 result = device->ws->buffer_virtual_bind(image->bo,
4105 bind->pBinds[i].resourceOffset,
4106 bind->pBinds[i].size,
4107 mem ? mem->bo : NULL,
4108 bind->pBinds[i].memoryOffset);
4109 if (result != VK_SUCCESS)
4110 return result;
4111 }
4112
4113 return VK_SUCCESS;
4114 }
4115
4116 static VkResult
4117 radv_get_preambles(struct radv_queue *queue,
4118 const VkCommandBuffer *cmd_buffers,
4119 uint32_t cmd_buffer_count,
4120 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
4121 struct radeon_cmdbuf **initial_preamble_cs,
4122 struct radeon_cmdbuf **continue_preamble_cs)
4123 {
4124 uint32_t scratch_size_per_wave = 0, waves_wanted = 0;
4125 uint32_t compute_scratch_size_per_wave = 0, compute_waves_wanted = 0;
4126 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
4127 bool tess_rings_needed = false;
4128 bool gds_needed = false;
4129 bool gds_oa_needed = false;
4130 bool sample_positions_needed = false;
4131
4132 for (uint32_t j = 0; j < cmd_buffer_count; j++) {
4133 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
4134 cmd_buffers[j]);
4135
4136 scratch_size_per_wave = MAX2(scratch_size_per_wave, cmd_buffer->scratch_size_per_wave_needed);
4137 waves_wanted = MAX2(waves_wanted, cmd_buffer->scratch_waves_wanted);
4138 compute_scratch_size_per_wave = MAX2(compute_scratch_size_per_wave,
4139 cmd_buffer->compute_scratch_size_per_wave_needed);
4140 compute_waves_wanted = MAX2(compute_waves_wanted,
4141 cmd_buffer->compute_scratch_waves_wanted);
4142 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
4143 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
4144 tess_rings_needed |= cmd_buffer->tess_rings_needed;
4145 gds_needed |= cmd_buffer->gds_needed;
4146 gds_oa_needed |= cmd_buffer->gds_oa_needed;
4147 sample_positions_needed |= cmd_buffer->sample_positions_needed;
4148 }
4149
4150 return radv_get_preamble_cs(queue, scratch_size_per_wave, waves_wanted,
4151 compute_scratch_size_per_wave, compute_waves_wanted,
4152 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
4153 gds_needed, gds_oa_needed, sample_positions_needed,
4154 initial_full_flush_preamble_cs,
4155 initial_preamble_cs, continue_preamble_cs);
4156 }
4157
4158 struct radv_deferred_queue_submission {
4159 struct radv_queue *queue;
4160 VkCommandBuffer *cmd_buffers;
4161 uint32_t cmd_buffer_count;
4162
4163 /* Sparse bindings that happen on a queue. */
4164 VkSparseBufferMemoryBindInfo *buffer_binds;
4165 uint32_t buffer_bind_count;
4166 VkSparseImageOpaqueMemoryBindInfo *image_opaque_binds;
4167 uint32_t image_opaque_bind_count;
4168
4169 bool flush_caches;
4170 VkShaderStageFlags wait_dst_stage_mask;
4171 struct radv_semaphore_part **wait_semaphores;
4172 uint32_t wait_semaphore_count;
4173 struct radv_semaphore_part **signal_semaphores;
4174 uint32_t signal_semaphore_count;
4175 VkFence fence;
4176
4177 uint64_t *wait_values;
4178 uint64_t *signal_values;
4179
4180 struct radv_semaphore_part *temporary_semaphore_parts;
4181 uint32_t temporary_semaphore_part_count;
4182
4183 struct list_head queue_pending_list;
4184 uint32_t submission_wait_count;
4185 struct radv_timeline_waiter *wait_nodes;
4186
4187 struct list_head processing_list;
4188 };
4189
4190 struct radv_queue_submission {
4191 const VkCommandBuffer *cmd_buffers;
4192 uint32_t cmd_buffer_count;
4193
4194 /* Sparse bindings that happen on a queue. */
4195 const VkSparseBufferMemoryBindInfo *buffer_binds;
4196 uint32_t buffer_bind_count;
4197 const VkSparseImageOpaqueMemoryBindInfo *image_opaque_binds;
4198 uint32_t image_opaque_bind_count;
4199
4200 bool flush_caches;
4201 VkPipelineStageFlags wait_dst_stage_mask;
4202 const VkSemaphore *wait_semaphores;
4203 uint32_t wait_semaphore_count;
4204 const VkSemaphore *signal_semaphores;
4205 uint32_t signal_semaphore_count;
4206 VkFence fence;
4207
4208 const uint64_t *wait_values;
4209 uint32_t wait_value_count;
4210 const uint64_t *signal_values;
4211 uint32_t signal_value_count;
4212 };
4213
4214 static VkResult
4215 radv_queue_trigger_submission(struct radv_deferred_queue_submission *submission,
4216 uint32_t decrement,
4217 struct list_head *processing_list);
4218
4219 static VkResult
4220 radv_create_deferred_submission(struct radv_queue *queue,
4221 const struct radv_queue_submission *submission,
4222 struct radv_deferred_queue_submission **out)
4223 {
4224 struct radv_deferred_queue_submission *deferred = NULL;
4225 size_t size = sizeof(struct radv_deferred_queue_submission);
4226
4227 uint32_t temporary_count = 0;
4228 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4229 RADV_FROM_HANDLE(radv_semaphore, semaphore, submission->wait_semaphores[i]);
4230 if (semaphore->temporary.kind != RADV_SEMAPHORE_NONE)
4231 ++temporary_count;
4232 }
4233
4234 size += submission->cmd_buffer_count * sizeof(VkCommandBuffer);
4235 size += submission->buffer_bind_count * sizeof(VkSparseBufferMemoryBindInfo);
4236 size += submission->image_opaque_bind_count * sizeof(VkSparseImageOpaqueMemoryBindInfo);
4237 size += submission->wait_semaphore_count * sizeof(struct radv_semaphore_part *);
4238 size += temporary_count * sizeof(struct radv_semaphore_part);
4239 size += submission->signal_semaphore_count * sizeof(struct radv_semaphore_part *);
4240 size += submission->wait_value_count * sizeof(uint64_t);
4241 size += submission->signal_value_count * sizeof(uint64_t);
4242 size += submission->wait_semaphore_count * sizeof(struct radv_timeline_waiter);
4243
4244 deferred = calloc(1, size);
4245 if (!deferred)
4246 return VK_ERROR_OUT_OF_HOST_MEMORY;
4247
4248 deferred->queue = queue;
4249
4250 deferred->cmd_buffers = (void*)(deferred + 1);
4251 deferred->cmd_buffer_count = submission->cmd_buffer_count;
4252 memcpy(deferred->cmd_buffers, submission->cmd_buffers,
4253 submission->cmd_buffer_count * sizeof(*deferred->cmd_buffers));
4254
4255 deferred->buffer_binds = (void*)(deferred->cmd_buffers + submission->cmd_buffer_count);
4256 deferred->buffer_bind_count = submission->buffer_bind_count;
4257 memcpy(deferred->buffer_binds, submission->buffer_binds,
4258 submission->buffer_bind_count * sizeof(*deferred->buffer_binds));
4259
4260 deferred->image_opaque_binds = (void*)(deferred->buffer_binds + submission->buffer_bind_count);
4261 deferred->image_opaque_bind_count = submission->image_opaque_bind_count;
4262 memcpy(deferred->image_opaque_binds, submission->image_opaque_binds,
4263 submission->image_opaque_bind_count * sizeof(*deferred->image_opaque_binds));
4264
4265 deferred->flush_caches = submission->flush_caches;
4266 deferred->wait_dst_stage_mask = submission->wait_dst_stage_mask;
4267
4268 deferred->wait_semaphores = (void*)(deferred->image_opaque_binds + deferred->image_opaque_bind_count);
4269 deferred->wait_semaphore_count = submission->wait_semaphore_count;
4270
4271 deferred->signal_semaphores = (void*)(deferred->wait_semaphores + deferred->wait_semaphore_count);
4272 deferred->signal_semaphore_count = submission->signal_semaphore_count;
4273
4274 deferred->fence = submission->fence;
4275
4276 deferred->temporary_semaphore_parts = (void*)(deferred->signal_semaphores + deferred->signal_semaphore_count);
4277 deferred->temporary_semaphore_part_count = temporary_count;
4278
4279 uint32_t temporary_idx = 0;
4280 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4281 RADV_FROM_HANDLE(radv_semaphore, semaphore, submission->wait_semaphores[i]);
4282 if (semaphore->temporary.kind != RADV_SEMAPHORE_NONE) {
4283 deferred->wait_semaphores[i] = &deferred->temporary_semaphore_parts[temporary_idx];
4284 deferred->temporary_semaphore_parts[temporary_idx] = semaphore->temporary;
4285 semaphore->temporary.kind = RADV_SEMAPHORE_NONE;
4286 ++temporary_idx;
4287 } else
4288 deferred->wait_semaphores[i] = &semaphore->permanent;
4289 }
4290
4291 for (uint32_t i = 0; i < submission->signal_semaphore_count; ++i) {
4292 RADV_FROM_HANDLE(radv_semaphore, semaphore, submission->signal_semaphores[i]);
4293 if (semaphore->temporary.kind != RADV_SEMAPHORE_NONE) {
4294 deferred->signal_semaphores[i] = &semaphore->temporary;
4295 } else {
4296 deferred->signal_semaphores[i] = &semaphore->permanent;
4297 }
4298 }
4299
4300 deferred->wait_values = (void*)(deferred->temporary_semaphore_parts + temporary_count);
4301 memcpy(deferred->wait_values, submission->wait_values, submission->wait_value_count * sizeof(uint64_t));
4302 deferred->signal_values = deferred->wait_values + submission->wait_value_count;
4303 memcpy(deferred->signal_values, submission->signal_values, submission->signal_value_count * sizeof(uint64_t));
4304
4305 deferred->wait_nodes = (void*)(deferred->signal_values + submission->signal_value_count);
4306 /* This is worst-case. radv_queue_enqueue_submission will fill in further, but this
4307 * ensure the submission is not accidentally triggered early when adding wait timelines. */
4308 deferred->submission_wait_count = 1 + submission->wait_semaphore_count;
4309
4310 *out = deferred;
4311 return VK_SUCCESS;
4312 }
4313
4314 static VkResult
4315 radv_queue_enqueue_submission(struct radv_deferred_queue_submission *submission,
4316 struct list_head *processing_list)
4317 {
4318 uint32_t wait_cnt = 0;
4319 struct radv_timeline_waiter *waiter = submission->wait_nodes;
4320 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4321 if (submission->wait_semaphores[i]->kind == RADV_SEMAPHORE_TIMELINE) {
4322 pthread_mutex_lock(&submission->wait_semaphores[i]->timeline.mutex);
4323 if (submission->wait_semaphores[i]->timeline.highest_submitted < submission->wait_values[i]) {
4324 ++wait_cnt;
4325 waiter->value = submission->wait_values[i];
4326 waiter->submission = submission;
4327 list_addtail(&waiter->list, &submission->wait_semaphores[i]->timeline.waiters);
4328 ++waiter;
4329 }
4330 pthread_mutex_unlock(&submission->wait_semaphores[i]->timeline.mutex);
4331 }
4332 }
4333
4334 pthread_mutex_lock(&submission->queue->pending_mutex);
4335
4336 bool is_first = list_is_empty(&submission->queue->pending_submissions);
4337 list_addtail(&submission->queue_pending_list, &submission->queue->pending_submissions);
4338
4339 pthread_mutex_unlock(&submission->queue->pending_mutex);
4340
4341 /* If there is already a submission in the queue, that will decrement the counter by 1 when
4342 * submitted, but if the queue was empty, we decrement ourselves as there is no previous
4343 * submission. */
4344 uint32_t decrement = submission->wait_semaphore_count - wait_cnt + (is_first ? 1 : 0);
4345 return radv_queue_trigger_submission(submission, decrement, processing_list);
4346 }
4347
4348 static void
4349 radv_queue_submission_update_queue(struct radv_deferred_queue_submission *submission,
4350 struct list_head *processing_list)
4351 {
4352 pthread_mutex_lock(&submission->queue->pending_mutex);
4353 list_del(&submission->queue_pending_list);
4354
4355 /* trigger the next submission in the queue. */
4356 if (!list_is_empty(&submission->queue->pending_submissions)) {
4357 struct radv_deferred_queue_submission *next_submission =
4358 list_first_entry(&submission->queue->pending_submissions,
4359 struct radv_deferred_queue_submission,
4360 queue_pending_list);
4361 radv_queue_trigger_submission(next_submission, 1, processing_list);
4362 }
4363 pthread_mutex_unlock(&submission->queue->pending_mutex);
4364
4365 pthread_cond_broadcast(&submission->queue->device->timeline_cond);
4366 }
4367
4368 static VkResult
4369 radv_queue_submit_deferred(struct radv_deferred_queue_submission *submission,
4370 struct list_head *processing_list)
4371 {
4372 RADV_FROM_HANDLE(radv_fence, fence, submission->fence);
4373 struct radv_queue *queue = submission->queue;
4374 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
4375 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
4376 struct radeon_winsys_fence *base_fence = NULL;
4377 bool do_flush = submission->flush_caches || submission->wait_dst_stage_mask;
4378 bool can_patch = true;
4379 uint32_t advance;
4380 struct radv_winsys_sem_info sem_info;
4381 VkResult result;
4382 struct radeon_cmdbuf *initial_preamble_cs = NULL;
4383 struct radeon_cmdbuf *initial_flush_preamble_cs = NULL;
4384 struct radeon_cmdbuf *continue_preamble_cs = NULL;
4385
4386 if (fence) {
4387 /* Under most circumstances, out fences won't be temporary.
4388 * However, the spec does allow it for opaque_fd.
4389 *
4390 * From the Vulkan 1.0.53 spec:
4391 *
4392 * "If the import is temporary, the implementation must
4393 * restore the semaphore to its prior permanent state after
4394 * submitting the next semaphore wait operation."
4395 */
4396 struct radv_fence_part *part =
4397 fence->temporary.kind != RADV_FENCE_NONE ?
4398 &fence->temporary : &fence->permanent;
4399 if (part->kind == RADV_FENCE_WINSYS)
4400 base_fence = part->fence;
4401 }
4402
4403 result = radv_get_preambles(queue, submission->cmd_buffers,
4404 submission->cmd_buffer_count,
4405 &initial_preamble_cs,
4406 &initial_flush_preamble_cs,
4407 &continue_preamble_cs);
4408 if (result != VK_SUCCESS)
4409 goto fail;
4410
4411 result = radv_alloc_sem_info(queue->device,
4412 &sem_info,
4413 submission->wait_semaphore_count,
4414 submission->wait_semaphores,
4415 submission->wait_values,
4416 submission->signal_semaphore_count,
4417 submission->signal_semaphores,
4418 submission->signal_values,
4419 submission->fence);
4420 if (result != VK_SUCCESS)
4421 goto fail;
4422
4423 for (uint32_t i = 0; i < submission->buffer_bind_count; ++i) {
4424 result = radv_sparse_buffer_bind_memory(queue->device,
4425 submission->buffer_binds + i);
4426 if (result != VK_SUCCESS)
4427 goto fail;
4428 }
4429
4430 for (uint32_t i = 0; i < submission->image_opaque_bind_count; ++i) {
4431 result = radv_sparse_image_opaque_bind_memory(queue->device,
4432 submission->image_opaque_binds + i);
4433 if (result != VK_SUCCESS)
4434 goto fail;
4435 }
4436
4437 if (!submission->cmd_buffer_count) {
4438 result = queue->device->ws->cs_submit(ctx, queue->queue_idx,
4439 &queue->device->empty_cs[queue->queue_family_index],
4440 1, NULL, NULL,
4441 &sem_info, NULL,
4442 false, base_fence);
4443 if (result != VK_SUCCESS)
4444 goto fail;
4445 } else {
4446 struct radeon_cmdbuf **cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
4447 (submission->cmd_buffer_count));
4448
4449 for (uint32_t j = 0; j < submission->cmd_buffer_count; j++) {
4450 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, submission->cmd_buffers[j]);
4451 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
4452
4453 cs_array[j] = cmd_buffer->cs;
4454 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
4455 can_patch = false;
4456
4457 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
4458 }
4459
4460 for (uint32_t j = 0; j < submission->cmd_buffer_count; j += advance) {
4461 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
4462 const struct radv_winsys_bo_list *bo_list = NULL;
4463
4464 advance = MIN2(max_cs_submission,
4465 submission->cmd_buffer_count - j);
4466
4467 if (queue->device->trace_bo)
4468 *queue->device->trace_id_ptr = 0;
4469
4470 sem_info.cs_emit_wait = j == 0;
4471 sem_info.cs_emit_signal = j + advance == submission->cmd_buffer_count;
4472
4473 if (unlikely(queue->device->use_global_bo_list)) {
4474 pthread_mutex_lock(&queue->device->bo_list.mutex);
4475 bo_list = &queue->device->bo_list.list;
4476 }
4477
4478 result = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
4479 advance, initial_preamble, continue_preamble_cs,
4480 &sem_info, bo_list,
4481 can_patch, base_fence);
4482
4483 if (unlikely(queue->device->use_global_bo_list))
4484 pthread_mutex_unlock(&queue->device->bo_list.mutex);
4485
4486 if (result != VK_SUCCESS)
4487 goto fail;
4488
4489 if (queue->device->trace_bo) {
4490 radv_check_gpu_hangs(queue, cs_array[j]);
4491 }
4492 }
4493
4494 free(cs_array);
4495 }
4496
4497 radv_free_temp_syncobjs(queue->device,
4498 submission->temporary_semaphore_part_count,
4499 submission->temporary_semaphore_parts);
4500 radv_finalize_timelines(queue->device,
4501 submission->wait_semaphore_count,
4502 submission->wait_semaphores,
4503 submission->wait_values,
4504 submission->signal_semaphore_count,
4505 submission->signal_semaphores,
4506 submission->signal_values,
4507 processing_list);
4508 /* Has to happen after timeline finalization to make sure the
4509 * condition variable is only triggered when timelines and queue have
4510 * been updated. */
4511 radv_queue_submission_update_queue(submission, processing_list);
4512 radv_free_sem_info(&sem_info);
4513 free(submission);
4514 return VK_SUCCESS;
4515
4516 fail:
4517 if (result != VK_SUCCESS && result != VK_ERROR_DEVICE_LOST) {
4518 /* When something bad happened during the submission, such as
4519 * an out of memory issue, it might be hard to recover from
4520 * this inconsistent state. To avoid this sort of problem, we
4521 * assume that we are in a really bad situation and return
4522 * VK_ERROR_DEVICE_LOST to ensure the clients do not attempt
4523 * to submit the same job again to this device.
4524 */
4525 result = radv_device_set_lost(queue->device, "vkQueueSubmit() failed");
4526 }
4527
4528 radv_free_temp_syncobjs(queue->device,
4529 submission->temporary_semaphore_part_count,
4530 submission->temporary_semaphore_parts);
4531 free(submission);
4532 return result;
4533 }
4534
4535 static VkResult
4536 radv_process_submissions(struct list_head *processing_list)
4537 {
4538 while(!list_is_empty(processing_list)) {
4539 struct radv_deferred_queue_submission *submission =
4540 list_first_entry(processing_list, struct radv_deferred_queue_submission, processing_list);
4541 list_del(&submission->processing_list);
4542
4543 VkResult result = radv_queue_submit_deferred(submission, processing_list);
4544 if (result != VK_SUCCESS)
4545 return result;
4546 }
4547 return VK_SUCCESS;
4548 }
4549
4550 static VkResult
4551 wait_for_submission_timelines_available(struct radv_deferred_queue_submission *submission,
4552 uint64_t timeout)
4553 {
4554 struct radv_device *device = submission->queue->device;
4555 uint32_t syncobj_count = 0;
4556 uint32_t syncobj_idx = 0;
4557
4558 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4559 if (submission->wait_semaphores[i]->kind != RADV_SEMAPHORE_TIMELINE_SYNCOBJ)
4560 continue;
4561
4562 if (submission->wait_semaphores[i]->timeline_syncobj.max_point >= submission->wait_values[i])
4563 continue;
4564 ++syncobj_count;
4565 }
4566
4567 if (!syncobj_count)
4568 return VK_SUCCESS;
4569
4570 uint64_t *points = malloc((sizeof(uint64_t) + sizeof(uint32_t)) * syncobj_count);
4571 if (!points)
4572 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4573
4574 uint32_t *syncobj = (uint32_t*)(points + syncobj_count);
4575
4576 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4577 if (submission->wait_semaphores[i]->kind != RADV_SEMAPHORE_TIMELINE_SYNCOBJ)
4578 continue;
4579
4580 if (submission->wait_semaphores[i]->timeline_syncobj.max_point >= submission->wait_values[i])
4581 continue;
4582
4583 syncobj[syncobj_idx] = submission->wait_semaphores[i]->syncobj;
4584 points[syncobj_idx] = submission->wait_values[i];
4585 ++syncobj_idx;
4586 }
4587 bool success = device->ws->wait_timeline_syncobj(device->ws, syncobj, points, syncobj_idx, true, true, timeout);
4588
4589 free(points);
4590 return success ? VK_SUCCESS : VK_TIMEOUT;
4591 }
4592
4593 static void* radv_queue_submission_thread_run(void *q)
4594 {
4595 struct radv_queue *queue = q;
4596
4597 pthread_mutex_lock(&queue->thread_mutex);
4598 while (!p_atomic_read(&queue->thread_exit)) {
4599 struct radv_deferred_queue_submission *submission = queue->thread_submission;
4600 struct list_head processing_list;
4601 VkResult result = VK_SUCCESS;
4602 if (!submission) {
4603 pthread_cond_wait(&queue->thread_cond, &queue->thread_mutex);
4604 continue;
4605 }
4606 pthread_mutex_unlock(&queue->thread_mutex);
4607
4608 /* Wait at most 5 seconds so we have a chance to notice shutdown when
4609 * a semaphore never gets signaled. If it takes longer we just retry
4610 * the wait next iteration. */
4611 result = wait_for_submission_timelines_available(submission,
4612 radv_get_absolute_timeout(5000000000));
4613 if (result != VK_SUCCESS) {
4614 pthread_mutex_lock(&queue->thread_mutex);
4615 continue;
4616 }
4617
4618 /* The lock isn't held but nobody will add one until we finish
4619 * the current submission. */
4620 p_atomic_set(&queue->thread_submission, NULL);
4621
4622 list_inithead(&processing_list);
4623 list_addtail(&submission->processing_list, &processing_list);
4624 result = radv_process_submissions(&processing_list);
4625
4626 pthread_mutex_lock(&queue->thread_mutex);
4627 }
4628 pthread_mutex_unlock(&queue->thread_mutex);
4629 return NULL;
4630 }
4631
4632 static VkResult
4633 radv_queue_trigger_submission(struct radv_deferred_queue_submission *submission,
4634 uint32_t decrement,
4635 struct list_head *processing_list)
4636 {
4637 struct radv_queue *queue = submission->queue;
4638 int ret;
4639 if (p_atomic_add_return(&submission->submission_wait_count, -decrement))
4640 return VK_SUCCESS;
4641
4642 if (wait_for_submission_timelines_available(submission, radv_get_absolute_timeout(0)) == VK_SUCCESS) {
4643 list_addtail(&submission->processing_list, processing_list);
4644 return VK_SUCCESS;
4645 }
4646
4647 pthread_mutex_lock(&queue->thread_mutex);
4648
4649 /* A submission can only be ready for the thread if it doesn't have
4650 * any predecessors in the same queue, so there can only be one such
4651 * submission at a time. */
4652 assert(queue->thread_submission == NULL);
4653
4654 /* Only start the thread on demand to save resources for the many games
4655 * which only use binary semaphores. */
4656 if (!queue->thread_running) {
4657 ret = pthread_create(&queue->submission_thread, NULL,
4658 radv_queue_submission_thread_run, queue);
4659 if (ret) {
4660 pthread_mutex_unlock(&queue->thread_mutex);
4661 return vk_errorf(queue->device->instance,
4662 VK_ERROR_DEVICE_LOST,
4663 "Failed to start submission thread");
4664 }
4665 queue->thread_running = true;
4666 }
4667
4668 queue->thread_submission = submission;
4669 pthread_mutex_unlock(&queue->thread_mutex);
4670
4671 pthread_cond_signal(&queue->thread_cond);
4672 return VK_SUCCESS;
4673 }
4674
4675 static VkResult radv_queue_submit(struct radv_queue *queue,
4676 const struct radv_queue_submission *submission)
4677 {
4678 struct radv_deferred_queue_submission *deferred = NULL;
4679
4680 VkResult result = radv_create_deferred_submission(queue, submission, &deferred);
4681 if (result != VK_SUCCESS)
4682 return result;
4683
4684 struct list_head processing_list;
4685 list_inithead(&processing_list);
4686
4687 result = radv_queue_enqueue_submission(deferred, &processing_list);
4688 if (result != VK_SUCCESS) {
4689 /* If anything is in the list we leak. */
4690 assert(list_is_empty(&processing_list));
4691 return result;
4692 }
4693 return radv_process_submissions(&processing_list);
4694 }
4695
4696 bool
4697 radv_queue_internal_submit(struct radv_queue *queue, struct radeon_cmdbuf *cs)
4698 {
4699 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
4700 struct radv_winsys_sem_info sem_info;
4701 VkResult result;
4702
4703 result = radv_alloc_sem_info(queue->device, &sem_info, 0, NULL, 0, 0,
4704 0, NULL, VK_NULL_HANDLE);
4705 if (result != VK_SUCCESS)
4706 return false;
4707
4708 result = queue->device->ws->cs_submit(ctx, queue->queue_idx, &cs, 1,
4709 NULL, NULL, &sem_info, NULL,
4710 false, NULL);
4711 radv_free_sem_info(&sem_info);
4712 if (result != VK_SUCCESS)
4713 return false;
4714
4715 return true;
4716
4717 }
4718
4719 /* Signals fence as soon as all the work currently put on queue is done. */
4720 static VkResult radv_signal_fence(struct radv_queue *queue,
4721 VkFence fence)
4722 {
4723 return radv_queue_submit(queue, &(struct radv_queue_submission) {
4724 .fence = fence
4725 });
4726 }
4727
4728 static bool radv_submit_has_effects(const VkSubmitInfo *info)
4729 {
4730 return info->commandBufferCount ||
4731 info->waitSemaphoreCount ||
4732 info->signalSemaphoreCount;
4733 }
4734
4735 VkResult radv_QueueSubmit(
4736 VkQueue _queue,
4737 uint32_t submitCount,
4738 const VkSubmitInfo* pSubmits,
4739 VkFence fence)
4740 {
4741 RADV_FROM_HANDLE(radv_queue, queue, _queue);
4742 VkResult result;
4743 uint32_t fence_idx = 0;
4744 bool flushed_caches = false;
4745
4746 if (radv_device_is_lost(queue->device))
4747 return VK_ERROR_DEVICE_LOST;
4748
4749 if (fence != VK_NULL_HANDLE) {
4750 for (uint32_t i = 0; i < submitCount; ++i)
4751 if (radv_submit_has_effects(pSubmits + i))
4752 fence_idx = i;
4753 } else
4754 fence_idx = UINT32_MAX;
4755
4756 for (uint32_t i = 0; i < submitCount; i++) {
4757 if (!radv_submit_has_effects(pSubmits + i) && fence_idx != i)
4758 continue;
4759
4760 VkPipelineStageFlags wait_dst_stage_mask = 0;
4761 for (unsigned j = 0; j < pSubmits[i].waitSemaphoreCount; ++j) {
4762 wait_dst_stage_mask |= pSubmits[i].pWaitDstStageMask[j];
4763 }
4764
4765 const VkTimelineSemaphoreSubmitInfo *timeline_info =
4766 vk_find_struct_const(pSubmits[i].pNext, TIMELINE_SEMAPHORE_SUBMIT_INFO);
4767
4768 result = radv_queue_submit(queue, &(struct radv_queue_submission) {
4769 .cmd_buffers = pSubmits[i].pCommandBuffers,
4770 .cmd_buffer_count = pSubmits[i].commandBufferCount,
4771 .wait_dst_stage_mask = wait_dst_stage_mask,
4772 .flush_caches = !flushed_caches,
4773 .wait_semaphores = pSubmits[i].pWaitSemaphores,
4774 .wait_semaphore_count = pSubmits[i].waitSemaphoreCount,
4775 .signal_semaphores = pSubmits[i].pSignalSemaphores,
4776 .signal_semaphore_count = pSubmits[i].signalSemaphoreCount,
4777 .fence = i == fence_idx ? fence : VK_NULL_HANDLE,
4778 .wait_values = timeline_info ? timeline_info->pWaitSemaphoreValues : NULL,
4779 .wait_value_count = timeline_info && timeline_info->pWaitSemaphoreValues ? timeline_info->waitSemaphoreValueCount : 0,
4780 .signal_values = timeline_info ? timeline_info->pSignalSemaphoreValues : NULL,
4781 .signal_value_count = timeline_info && timeline_info->pSignalSemaphoreValues ? timeline_info->signalSemaphoreValueCount : 0,
4782 });
4783 if (result != VK_SUCCESS)
4784 return result;
4785
4786 flushed_caches = true;
4787 }
4788
4789 if (fence != VK_NULL_HANDLE && !submitCount) {
4790 result = radv_signal_fence(queue, fence);
4791 if (result != VK_SUCCESS)
4792 return result;
4793 }
4794
4795 return VK_SUCCESS;
4796 }
4797
4798 static const char *
4799 radv_get_queue_family_name(struct radv_queue *queue)
4800 {
4801 switch (queue->queue_family_index) {
4802 case RADV_QUEUE_GENERAL:
4803 return "graphics";
4804 case RADV_QUEUE_COMPUTE:
4805 return "compute";
4806 case RADV_QUEUE_TRANSFER:
4807 return "transfer";
4808 default:
4809 unreachable("Unknown queue family");
4810 }
4811 }
4812
4813 VkResult radv_QueueWaitIdle(
4814 VkQueue _queue)
4815 {
4816 RADV_FROM_HANDLE(radv_queue, queue, _queue);
4817
4818 if (radv_device_is_lost(queue->device))
4819 return VK_ERROR_DEVICE_LOST;
4820
4821 pthread_mutex_lock(&queue->pending_mutex);
4822 while (!list_is_empty(&queue->pending_submissions)) {
4823 pthread_cond_wait(&queue->device->timeline_cond, &queue->pending_mutex);
4824 }
4825 pthread_mutex_unlock(&queue->pending_mutex);
4826
4827 if (!queue->device->ws->ctx_wait_idle(queue->hw_ctx,
4828 radv_queue_family_to_ring(queue->queue_family_index),
4829 queue->queue_idx)) {
4830 return radv_device_set_lost(queue->device,
4831 "Failed to wait for a '%s' queue "
4832 "to be idle. GPU hang ?",
4833 radv_get_queue_family_name(queue));
4834 }
4835
4836 return VK_SUCCESS;
4837 }
4838
4839 VkResult radv_DeviceWaitIdle(
4840 VkDevice _device)
4841 {
4842 RADV_FROM_HANDLE(radv_device, device, _device);
4843
4844 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
4845 for (unsigned q = 0; q < device->queue_count[i]; q++) {
4846 VkResult result =
4847 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
4848
4849 if (result != VK_SUCCESS)
4850 return result;
4851 }
4852 }
4853 return VK_SUCCESS;
4854 }
4855
4856 VkResult radv_EnumerateInstanceExtensionProperties(
4857 const char* pLayerName,
4858 uint32_t* pPropertyCount,
4859 VkExtensionProperties* pProperties)
4860 {
4861 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
4862
4863 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
4864 if (radv_instance_extensions_supported.extensions[i]) {
4865 vk_outarray_append(&out, prop) {
4866 *prop = radv_instance_extensions[i];
4867 }
4868 }
4869 }
4870
4871 return vk_outarray_status(&out);
4872 }
4873
4874 VkResult radv_EnumerateDeviceExtensionProperties(
4875 VkPhysicalDevice physicalDevice,
4876 const char* pLayerName,
4877 uint32_t* pPropertyCount,
4878 VkExtensionProperties* pProperties)
4879 {
4880 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
4881 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
4882
4883 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
4884 if (device->supported_extensions.extensions[i]) {
4885 vk_outarray_append(&out, prop) {
4886 *prop = radv_device_extensions[i];
4887 }
4888 }
4889 }
4890
4891 return vk_outarray_status(&out);
4892 }
4893
4894 PFN_vkVoidFunction radv_GetInstanceProcAddr(
4895 VkInstance _instance,
4896 const char* pName)
4897 {
4898 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4899
4900 /* The Vulkan 1.0 spec for vkGetInstanceProcAddr has a table of exactly
4901 * when we have to return valid function pointers, NULL, or it's left
4902 * undefined. See the table for exact details.
4903 */
4904 if (pName == NULL)
4905 return NULL;
4906
4907 #define LOOKUP_RADV_ENTRYPOINT(entrypoint) \
4908 if (strcmp(pName, "vk" #entrypoint) == 0) \
4909 return (PFN_vkVoidFunction)radv_##entrypoint
4910
4911 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceExtensionProperties);
4912 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceLayerProperties);
4913 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceVersion);
4914 LOOKUP_RADV_ENTRYPOINT(CreateInstance);
4915
4916 /* GetInstanceProcAddr() can also be called with a NULL instance.
4917 * See https://gitlab.khronos.org/vulkan/vulkan/issues/2057
4918 */
4919 LOOKUP_RADV_ENTRYPOINT(GetInstanceProcAddr);
4920
4921 #undef LOOKUP_RADV_ENTRYPOINT
4922
4923 if (instance == NULL)
4924 return NULL;
4925
4926 int idx = radv_get_instance_entrypoint_index(pName);
4927 if (idx >= 0)
4928 return instance->dispatch.entrypoints[idx];
4929
4930 idx = radv_get_physical_device_entrypoint_index(pName);
4931 if (idx >= 0)
4932 return instance->physical_device_dispatch.entrypoints[idx];
4933
4934 idx = radv_get_device_entrypoint_index(pName);
4935 if (idx >= 0)
4936 return instance->device_dispatch.entrypoints[idx];
4937
4938 return NULL;
4939 }
4940
4941 /* The loader wants us to expose a second GetInstanceProcAddr function
4942 * to work around certain LD_PRELOAD issues seen in apps.
4943 */
4944 PUBLIC
4945 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
4946 VkInstance instance,
4947 const char* pName);
4948
4949 PUBLIC
4950 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
4951 VkInstance instance,
4952 const char* pName)
4953 {
4954 return radv_GetInstanceProcAddr(instance, pName);
4955 }
4956
4957 PUBLIC
4958 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
4959 VkInstance _instance,
4960 const char* pName);
4961
4962 PUBLIC
4963 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
4964 VkInstance _instance,
4965 const char* pName)
4966 {
4967 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4968
4969 if (!pName || !instance)
4970 return NULL;
4971
4972 int idx = radv_get_physical_device_entrypoint_index(pName);
4973 if (idx < 0)
4974 return NULL;
4975
4976 return instance->physical_device_dispatch.entrypoints[idx];
4977 }
4978
4979 PFN_vkVoidFunction radv_GetDeviceProcAddr(
4980 VkDevice _device,
4981 const char* pName)
4982 {
4983 RADV_FROM_HANDLE(radv_device, device, _device);
4984
4985 if (!device || !pName)
4986 return NULL;
4987
4988 int idx = radv_get_device_entrypoint_index(pName);
4989 if (idx < 0)
4990 return NULL;
4991
4992 return device->dispatch.entrypoints[idx];
4993 }
4994
4995 bool radv_get_memory_fd(struct radv_device *device,
4996 struct radv_device_memory *memory,
4997 int *pFD)
4998 {
4999 struct radeon_bo_metadata metadata;
5000
5001 if (memory->image) {
5002 if (memory->image->tiling != VK_IMAGE_TILING_LINEAR)
5003 radv_init_metadata(device, memory->image, &metadata);
5004 device->ws->buffer_set_metadata(memory->bo, &metadata);
5005 }
5006
5007 return device->ws->buffer_get_fd(device->ws, memory->bo,
5008 pFD);
5009 }
5010
5011
5012 void
5013 radv_free_memory(struct radv_device *device,
5014 const VkAllocationCallbacks* pAllocator,
5015 struct radv_device_memory *mem)
5016 {
5017 if (mem == NULL)
5018 return;
5019
5020 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
5021 if (mem->android_hardware_buffer)
5022 AHardwareBuffer_release(mem->android_hardware_buffer);
5023 #endif
5024
5025 if (mem->bo) {
5026 if (device->overallocation_disallowed) {
5027 mtx_lock(&device->overallocation_mutex);
5028 device->allocated_memory_size[mem->heap_index] -= mem->alloc_size;
5029 mtx_unlock(&device->overallocation_mutex);
5030 }
5031
5032 radv_bo_list_remove(device, mem->bo);
5033 device->ws->buffer_destroy(mem->bo);
5034 mem->bo = NULL;
5035 }
5036
5037 vk_object_base_finish(&mem->base);
5038 vk_free2(&device->vk.alloc, pAllocator, mem);
5039 }
5040
5041 static VkResult radv_alloc_memory(struct radv_device *device,
5042 const VkMemoryAllocateInfo* pAllocateInfo,
5043 const VkAllocationCallbacks* pAllocator,
5044 VkDeviceMemory* pMem)
5045 {
5046 struct radv_device_memory *mem;
5047 VkResult result;
5048 enum radeon_bo_domain domain;
5049 uint32_t flags = 0;
5050
5051 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
5052
5053 const VkImportMemoryFdInfoKHR *import_info =
5054 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
5055 const VkMemoryDedicatedAllocateInfo *dedicate_info =
5056 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
5057 const VkExportMemoryAllocateInfo *export_info =
5058 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
5059 const struct VkImportAndroidHardwareBufferInfoANDROID *ahb_import_info =
5060 vk_find_struct_const(pAllocateInfo->pNext,
5061 IMPORT_ANDROID_HARDWARE_BUFFER_INFO_ANDROID);
5062 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
5063 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
5064
5065 const struct wsi_memory_allocate_info *wsi_info =
5066 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
5067
5068 if (pAllocateInfo->allocationSize == 0 && !ahb_import_info &&
5069 !(export_info && (export_info->handleTypes & VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID))) {
5070 /* Apparently, this is allowed */
5071 *pMem = VK_NULL_HANDLE;
5072 return VK_SUCCESS;
5073 }
5074
5075 mem = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*mem), 8,
5076 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5077 if (mem == NULL)
5078 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5079
5080 vk_object_base_init(&device->vk, &mem->base,
5081 VK_OBJECT_TYPE_DEVICE_MEMORY);
5082
5083 if (wsi_info && wsi_info->implicit_sync)
5084 flags |= RADEON_FLAG_IMPLICIT_SYNC;
5085
5086 if (dedicate_info) {
5087 mem->image = radv_image_from_handle(dedicate_info->image);
5088 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
5089 } else {
5090 mem->image = NULL;
5091 mem->buffer = NULL;
5092 }
5093
5094 float priority_float = 0.5;
5095 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
5096 vk_find_struct_const(pAllocateInfo->pNext,
5097 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
5098 if (priority_ext)
5099 priority_float = priority_ext->priority;
5100
5101 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
5102 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
5103
5104 mem->user_ptr = NULL;
5105 mem->bo = NULL;
5106
5107 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
5108 mem->android_hardware_buffer = NULL;
5109 #endif
5110
5111 if (ahb_import_info) {
5112 result = radv_import_ahb_memory(device, mem, priority, ahb_import_info);
5113 if (result != VK_SUCCESS)
5114 goto fail;
5115 } else if(export_info && (export_info->handleTypes & VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID)) {
5116 result = radv_create_ahb_memory(device, mem, priority, pAllocateInfo);
5117 if (result != VK_SUCCESS)
5118 goto fail;
5119 } else if (import_info) {
5120 assert(import_info->handleType ==
5121 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
5122 import_info->handleType ==
5123 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
5124 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
5125 priority, NULL);
5126 if (!mem->bo) {
5127 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
5128 goto fail;
5129 } else {
5130 close(import_info->fd);
5131 }
5132
5133 if (mem->image && mem->image->plane_count == 1 &&
5134 !vk_format_is_depth_or_stencil(mem->image->vk_format)) {
5135 struct radeon_bo_metadata metadata;
5136 device->ws->buffer_get_metadata(mem->bo, &metadata);
5137
5138 struct radv_image_create_info create_info = {
5139 .no_metadata_planes = true,
5140 .bo_metadata = &metadata
5141 };
5142
5143 /* This gives a basic ability to import radeonsi images
5144 * that don't have DCC. This is not guaranteed by any
5145 * spec and can be removed after we support modifiers. */
5146 result = radv_image_create_layout(device, create_info, mem->image);
5147 if (result != VK_SUCCESS) {
5148 device->ws->buffer_destroy(mem->bo);
5149 goto fail;
5150 }
5151 }
5152 } else if (host_ptr_info) {
5153 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
5154 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
5155 pAllocateInfo->allocationSize,
5156 priority);
5157 if (!mem->bo) {
5158 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
5159 goto fail;
5160 } else {
5161 mem->user_ptr = host_ptr_info->pHostPointer;
5162 }
5163 } else {
5164 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
5165 uint32_t heap_index;
5166
5167 heap_index = device->physical_device->memory_properties.memoryTypes[pAllocateInfo->memoryTypeIndex].heapIndex;
5168 domain = device->physical_device->memory_domains[pAllocateInfo->memoryTypeIndex];
5169 flags |= device->physical_device->memory_flags[pAllocateInfo->memoryTypeIndex];
5170
5171 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes)) {
5172 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
5173 if (device->use_global_bo_list) {
5174 flags |= RADEON_FLAG_PREFER_LOCAL_BO;
5175 }
5176 }
5177
5178 if (device->overallocation_disallowed) {
5179 uint64_t total_size =
5180 device->physical_device->memory_properties.memoryHeaps[heap_index].size;
5181
5182 mtx_lock(&device->overallocation_mutex);
5183 if (device->allocated_memory_size[heap_index] + alloc_size > total_size) {
5184 mtx_unlock(&device->overallocation_mutex);
5185 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
5186 goto fail;
5187 }
5188 device->allocated_memory_size[heap_index] += alloc_size;
5189 mtx_unlock(&device->overallocation_mutex);
5190 }
5191
5192 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
5193 domain, flags, priority);
5194
5195 if (!mem->bo) {
5196 if (device->overallocation_disallowed) {
5197 mtx_lock(&device->overallocation_mutex);
5198 device->allocated_memory_size[heap_index] -= alloc_size;
5199 mtx_unlock(&device->overallocation_mutex);
5200 }
5201 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
5202 goto fail;
5203 }
5204
5205 mem->heap_index = heap_index;
5206 mem->alloc_size = alloc_size;
5207 }
5208
5209 if (!wsi_info) {
5210 result = radv_bo_list_add(device, mem->bo);
5211 if (result != VK_SUCCESS)
5212 goto fail;
5213 }
5214
5215 *pMem = radv_device_memory_to_handle(mem);
5216
5217 return VK_SUCCESS;
5218
5219 fail:
5220 radv_free_memory(device, pAllocator,mem);
5221
5222 return result;
5223 }
5224
5225 VkResult radv_AllocateMemory(
5226 VkDevice _device,
5227 const VkMemoryAllocateInfo* pAllocateInfo,
5228 const VkAllocationCallbacks* pAllocator,
5229 VkDeviceMemory* pMem)
5230 {
5231 RADV_FROM_HANDLE(radv_device, device, _device);
5232 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
5233 }
5234
5235 void radv_FreeMemory(
5236 VkDevice _device,
5237 VkDeviceMemory _mem,
5238 const VkAllocationCallbacks* pAllocator)
5239 {
5240 RADV_FROM_HANDLE(radv_device, device, _device);
5241 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
5242
5243 radv_free_memory(device, pAllocator, mem);
5244 }
5245
5246 VkResult radv_MapMemory(
5247 VkDevice _device,
5248 VkDeviceMemory _memory,
5249 VkDeviceSize offset,
5250 VkDeviceSize size,
5251 VkMemoryMapFlags flags,
5252 void** ppData)
5253 {
5254 RADV_FROM_HANDLE(radv_device, device, _device);
5255 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
5256
5257 if (mem == NULL) {
5258 *ppData = NULL;
5259 return VK_SUCCESS;
5260 }
5261
5262 if (mem->user_ptr)
5263 *ppData = mem->user_ptr;
5264 else
5265 *ppData = device->ws->buffer_map(mem->bo);
5266
5267 if (*ppData) {
5268 *ppData += offset;
5269 return VK_SUCCESS;
5270 }
5271
5272 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
5273 }
5274
5275 void radv_UnmapMemory(
5276 VkDevice _device,
5277 VkDeviceMemory _memory)
5278 {
5279 RADV_FROM_HANDLE(radv_device, device, _device);
5280 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
5281
5282 if (mem == NULL)
5283 return;
5284
5285 if (mem->user_ptr == NULL)
5286 device->ws->buffer_unmap(mem->bo);
5287 }
5288
5289 VkResult radv_FlushMappedMemoryRanges(
5290 VkDevice _device,
5291 uint32_t memoryRangeCount,
5292 const VkMappedMemoryRange* pMemoryRanges)
5293 {
5294 return VK_SUCCESS;
5295 }
5296
5297 VkResult radv_InvalidateMappedMemoryRanges(
5298 VkDevice _device,
5299 uint32_t memoryRangeCount,
5300 const VkMappedMemoryRange* pMemoryRanges)
5301 {
5302 return VK_SUCCESS;
5303 }
5304
5305 void radv_GetBufferMemoryRequirements(
5306 VkDevice _device,
5307 VkBuffer _buffer,
5308 VkMemoryRequirements* pMemoryRequirements)
5309 {
5310 RADV_FROM_HANDLE(radv_device, device, _device);
5311 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5312
5313 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
5314
5315 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
5316 pMemoryRequirements->alignment = 4096;
5317 else
5318 pMemoryRequirements->alignment = 16;
5319
5320 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
5321 }
5322
5323 void radv_GetBufferMemoryRequirements2(
5324 VkDevice device,
5325 const VkBufferMemoryRequirementsInfo2 *pInfo,
5326 VkMemoryRequirements2 *pMemoryRequirements)
5327 {
5328 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
5329 &pMemoryRequirements->memoryRequirements);
5330 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
5331 switch (ext->sType) {
5332 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
5333 VkMemoryDedicatedRequirements *req =
5334 (VkMemoryDedicatedRequirements *) ext;
5335 req->requiresDedicatedAllocation = false;
5336 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
5337 break;
5338 }
5339 default:
5340 break;
5341 }
5342 }
5343 }
5344
5345 void radv_GetImageMemoryRequirements(
5346 VkDevice _device,
5347 VkImage _image,
5348 VkMemoryRequirements* pMemoryRequirements)
5349 {
5350 RADV_FROM_HANDLE(radv_device, device, _device);
5351 RADV_FROM_HANDLE(radv_image, image, _image);
5352
5353 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
5354
5355 pMemoryRequirements->size = image->size;
5356 pMemoryRequirements->alignment = image->alignment;
5357 }
5358
5359 void radv_GetImageMemoryRequirements2(
5360 VkDevice device,
5361 const VkImageMemoryRequirementsInfo2 *pInfo,
5362 VkMemoryRequirements2 *pMemoryRequirements)
5363 {
5364 radv_GetImageMemoryRequirements(device, pInfo->image,
5365 &pMemoryRequirements->memoryRequirements);
5366
5367 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
5368
5369 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
5370 switch (ext->sType) {
5371 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
5372 VkMemoryDedicatedRequirements *req =
5373 (VkMemoryDedicatedRequirements *) ext;
5374 req->requiresDedicatedAllocation = image->shareable &&
5375 image->tiling != VK_IMAGE_TILING_LINEAR;
5376 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
5377 break;
5378 }
5379 default:
5380 break;
5381 }
5382 }
5383 }
5384
5385 void radv_GetImageSparseMemoryRequirements(
5386 VkDevice device,
5387 VkImage image,
5388 uint32_t* pSparseMemoryRequirementCount,
5389 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
5390 {
5391 stub();
5392 }
5393
5394 void radv_GetImageSparseMemoryRequirements2(
5395 VkDevice device,
5396 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
5397 uint32_t* pSparseMemoryRequirementCount,
5398 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
5399 {
5400 stub();
5401 }
5402
5403 void radv_GetDeviceMemoryCommitment(
5404 VkDevice device,
5405 VkDeviceMemory memory,
5406 VkDeviceSize* pCommittedMemoryInBytes)
5407 {
5408 *pCommittedMemoryInBytes = 0;
5409 }
5410
5411 VkResult radv_BindBufferMemory2(VkDevice device,
5412 uint32_t bindInfoCount,
5413 const VkBindBufferMemoryInfo *pBindInfos)
5414 {
5415 for (uint32_t i = 0; i < bindInfoCount; ++i) {
5416 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
5417 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
5418
5419 if (mem) {
5420 buffer->bo = mem->bo;
5421 buffer->offset = pBindInfos[i].memoryOffset;
5422 } else {
5423 buffer->bo = NULL;
5424 }
5425 }
5426 return VK_SUCCESS;
5427 }
5428
5429 VkResult radv_BindBufferMemory(
5430 VkDevice device,
5431 VkBuffer buffer,
5432 VkDeviceMemory memory,
5433 VkDeviceSize memoryOffset)
5434 {
5435 const VkBindBufferMemoryInfo info = {
5436 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
5437 .buffer = buffer,
5438 .memory = memory,
5439 .memoryOffset = memoryOffset
5440 };
5441
5442 return radv_BindBufferMemory2(device, 1, &info);
5443 }
5444
5445 VkResult radv_BindImageMemory2(VkDevice device,
5446 uint32_t bindInfoCount,
5447 const VkBindImageMemoryInfo *pBindInfos)
5448 {
5449 for (uint32_t i = 0; i < bindInfoCount; ++i) {
5450 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
5451 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
5452
5453 if (mem) {
5454 image->bo = mem->bo;
5455 image->offset = pBindInfos[i].memoryOffset;
5456 } else {
5457 image->bo = NULL;
5458 image->offset = 0;
5459 }
5460 }
5461 return VK_SUCCESS;
5462 }
5463
5464
5465 VkResult radv_BindImageMemory(
5466 VkDevice device,
5467 VkImage image,
5468 VkDeviceMemory memory,
5469 VkDeviceSize memoryOffset)
5470 {
5471 const VkBindImageMemoryInfo info = {
5472 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
5473 .image = image,
5474 .memory = memory,
5475 .memoryOffset = memoryOffset
5476 };
5477
5478 return radv_BindImageMemory2(device, 1, &info);
5479 }
5480
5481 static bool radv_sparse_bind_has_effects(const VkBindSparseInfo *info)
5482 {
5483 return info->bufferBindCount ||
5484 info->imageOpaqueBindCount ||
5485 info->imageBindCount ||
5486 info->waitSemaphoreCount ||
5487 info->signalSemaphoreCount;
5488 }
5489
5490 VkResult radv_QueueBindSparse(
5491 VkQueue _queue,
5492 uint32_t bindInfoCount,
5493 const VkBindSparseInfo* pBindInfo,
5494 VkFence fence)
5495 {
5496 RADV_FROM_HANDLE(radv_queue, queue, _queue);
5497 VkResult result;
5498 uint32_t fence_idx = 0;
5499
5500 if (radv_device_is_lost(queue->device))
5501 return VK_ERROR_DEVICE_LOST;
5502
5503 if (fence != VK_NULL_HANDLE) {
5504 for (uint32_t i = 0; i < bindInfoCount; ++i)
5505 if (radv_sparse_bind_has_effects(pBindInfo + i))
5506 fence_idx = i;
5507 } else
5508 fence_idx = UINT32_MAX;
5509
5510 for (uint32_t i = 0; i < bindInfoCount; ++i) {
5511 if (i != fence_idx && !radv_sparse_bind_has_effects(pBindInfo + i))
5512 continue;
5513
5514 const VkTimelineSemaphoreSubmitInfo *timeline_info =
5515 vk_find_struct_const(pBindInfo[i].pNext, TIMELINE_SEMAPHORE_SUBMIT_INFO);
5516
5517 VkResult result = radv_queue_submit(queue, &(struct radv_queue_submission) {
5518 .buffer_binds = pBindInfo[i].pBufferBinds,
5519 .buffer_bind_count = pBindInfo[i].bufferBindCount,
5520 .image_opaque_binds = pBindInfo[i].pImageOpaqueBinds,
5521 .image_opaque_bind_count = pBindInfo[i].imageOpaqueBindCount,
5522 .wait_semaphores = pBindInfo[i].pWaitSemaphores,
5523 .wait_semaphore_count = pBindInfo[i].waitSemaphoreCount,
5524 .signal_semaphores = pBindInfo[i].pSignalSemaphores,
5525 .signal_semaphore_count = pBindInfo[i].signalSemaphoreCount,
5526 .fence = i == fence_idx ? fence : VK_NULL_HANDLE,
5527 .wait_values = timeline_info ? timeline_info->pWaitSemaphoreValues : NULL,
5528 .wait_value_count = timeline_info && timeline_info->pWaitSemaphoreValues ? timeline_info->waitSemaphoreValueCount : 0,
5529 .signal_values = timeline_info ? timeline_info->pSignalSemaphoreValues : NULL,
5530 .signal_value_count = timeline_info && timeline_info->pSignalSemaphoreValues ? timeline_info->signalSemaphoreValueCount : 0,
5531 });
5532
5533 if (result != VK_SUCCESS)
5534 return result;
5535 }
5536
5537 if (fence != VK_NULL_HANDLE && !bindInfoCount) {
5538 result = radv_signal_fence(queue, fence);
5539 if (result != VK_SUCCESS)
5540 return result;
5541 }
5542
5543 return VK_SUCCESS;
5544 }
5545
5546 static void
5547 radv_destroy_fence_part(struct radv_device *device,
5548 struct radv_fence_part *part)
5549 {
5550 switch (part->kind) {
5551 case RADV_FENCE_NONE:
5552 break;
5553 case RADV_FENCE_WINSYS:
5554 device->ws->destroy_fence(part->fence);
5555 break;
5556 case RADV_FENCE_SYNCOBJ:
5557 device->ws->destroy_syncobj(device->ws, part->syncobj);
5558 break;
5559 case RADV_FENCE_WSI:
5560 part->fence_wsi->destroy(part->fence_wsi);
5561 break;
5562 default:
5563 unreachable("Invalid fence type");
5564 }
5565
5566 part->kind = RADV_FENCE_NONE;
5567 }
5568
5569 static void
5570 radv_destroy_fence(struct radv_device *device,
5571 const VkAllocationCallbacks *pAllocator,
5572 struct radv_fence *fence)
5573 {
5574 radv_destroy_fence_part(device, &fence->temporary);
5575 radv_destroy_fence_part(device, &fence->permanent);
5576
5577 vk_object_base_finish(&fence->base);
5578 vk_free2(&device->vk.alloc, pAllocator, fence);
5579 }
5580
5581 VkResult radv_CreateFence(
5582 VkDevice _device,
5583 const VkFenceCreateInfo* pCreateInfo,
5584 const VkAllocationCallbacks* pAllocator,
5585 VkFence* pFence)
5586 {
5587 RADV_FROM_HANDLE(radv_device, device, _device);
5588 const VkExportFenceCreateInfo *export =
5589 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
5590 VkExternalFenceHandleTypeFlags handleTypes =
5591 export ? export->handleTypes : 0;
5592 struct radv_fence *fence;
5593
5594 fence = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*fence), 8,
5595 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5596 if (!fence)
5597 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5598
5599 vk_object_base_init(&device->vk, &fence->base, VK_OBJECT_TYPE_FENCE);
5600
5601 if (device->always_use_syncobj || handleTypes) {
5602 fence->permanent.kind = RADV_FENCE_SYNCOBJ;
5603
5604 bool create_signaled = false;
5605 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
5606 create_signaled = true;
5607
5608 int ret = device->ws->create_syncobj(device->ws, create_signaled,
5609 &fence->permanent.syncobj);
5610 if (ret) {
5611 radv_destroy_fence(device, pAllocator, fence);
5612 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5613 }
5614 } else {
5615 fence->permanent.kind = RADV_FENCE_WINSYS;
5616
5617 fence->permanent.fence = device->ws->create_fence();
5618 if (!fence->permanent.fence) {
5619 vk_free2(&device->vk.alloc, pAllocator, fence);
5620 radv_destroy_fence(device, pAllocator, fence);
5621 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5622 }
5623 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
5624 device->ws->signal_fence(fence->permanent.fence);
5625 }
5626
5627 *pFence = radv_fence_to_handle(fence);
5628
5629 return VK_SUCCESS;
5630 }
5631
5632
5633 void radv_DestroyFence(
5634 VkDevice _device,
5635 VkFence _fence,
5636 const VkAllocationCallbacks* pAllocator)
5637 {
5638 RADV_FROM_HANDLE(radv_device, device, _device);
5639 RADV_FROM_HANDLE(radv_fence, fence, _fence);
5640
5641 if (!fence)
5642 return;
5643
5644 radv_destroy_fence(device, pAllocator, fence);
5645 }
5646
5647 static bool radv_all_fences_plain_and_submitted(struct radv_device *device,
5648 uint32_t fenceCount, const VkFence *pFences)
5649 {
5650 for (uint32_t i = 0; i < fenceCount; ++i) {
5651 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5652
5653 struct radv_fence_part *part =
5654 fence->temporary.kind != RADV_FENCE_NONE ?
5655 &fence->temporary : &fence->permanent;
5656 if (part->kind != RADV_FENCE_WINSYS ||
5657 !device->ws->is_fence_waitable(part->fence))
5658 return false;
5659 }
5660 return true;
5661 }
5662
5663 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
5664 {
5665 for (uint32_t i = 0; i < fenceCount; ++i) {
5666 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5667
5668 struct radv_fence_part *part =
5669 fence->temporary.kind != RADV_FENCE_NONE ?
5670 &fence->temporary : &fence->permanent;
5671 if (part->kind != RADV_FENCE_SYNCOBJ)
5672 return false;
5673 }
5674 return true;
5675 }
5676
5677 VkResult radv_WaitForFences(
5678 VkDevice _device,
5679 uint32_t fenceCount,
5680 const VkFence* pFences,
5681 VkBool32 waitAll,
5682 uint64_t timeout)
5683 {
5684 RADV_FROM_HANDLE(radv_device, device, _device);
5685
5686 if (radv_device_is_lost(device))
5687 return VK_ERROR_DEVICE_LOST;
5688
5689 timeout = radv_get_absolute_timeout(timeout);
5690
5691 if (device->always_use_syncobj &&
5692 radv_all_fences_syncobj(fenceCount, pFences))
5693 {
5694 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
5695 if (!handles)
5696 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5697
5698 for (uint32_t i = 0; i < fenceCount; ++i) {
5699 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5700
5701 struct radv_fence_part *part =
5702 fence->temporary.kind != RADV_FENCE_NONE ?
5703 &fence->temporary : &fence->permanent;
5704
5705 assert(part->kind == RADV_FENCE_SYNCOBJ);
5706 handles[i] = part->syncobj;
5707 }
5708
5709 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
5710
5711 free(handles);
5712 return success ? VK_SUCCESS : VK_TIMEOUT;
5713 }
5714
5715 if (!waitAll && fenceCount > 1) {
5716 /* Not doing this by default for waitAll, due to needing to allocate twice. */
5717 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(device, fenceCount, pFences)) {
5718 uint32_t wait_count = 0;
5719 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
5720 if (!fences)
5721 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5722
5723 for (uint32_t i = 0; i < fenceCount; ++i) {
5724 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5725
5726 struct radv_fence_part *part =
5727 fence->temporary.kind != RADV_FENCE_NONE ?
5728 &fence->temporary : &fence->permanent;
5729 assert(part->kind == RADV_FENCE_WINSYS);
5730
5731 if (device->ws->fence_wait(device->ws, part->fence, false, 0)) {
5732 free(fences);
5733 return VK_SUCCESS;
5734 }
5735
5736 fences[wait_count++] = part->fence;
5737 }
5738
5739 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
5740 waitAll, timeout - radv_get_current_time());
5741
5742 free(fences);
5743 return success ? VK_SUCCESS : VK_TIMEOUT;
5744 }
5745
5746 while(radv_get_current_time() <= timeout) {
5747 for (uint32_t i = 0; i < fenceCount; ++i) {
5748 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
5749 return VK_SUCCESS;
5750 }
5751 }
5752 return VK_TIMEOUT;
5753 }
5754
5755 for (uint32_t i = 0; i < fenceCount; ++i) {
5756 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5757 bool expired = false;
5758
5759 struct radv_fence_part *part =
5760 fence->temporary.kind != RADV_FENCE_NONE ?
5761 &fence->temporary : &fence->permanent;
5762
5763 switch (part->kind) {
5764 case RADV_FENCE_NONE:
5765 break;
5766 case RADV_FENCE_WINSYS:
5767 if (!device->ws->is_fence_waitable(part->fence)) {
5768 while (!device->ws->is_fence_waitable(part->fence) &&
5769 radv_get_current_time() <= timeout)
5770 /* Do nothing */;
5771 }
5772
5773 expired = device->ws->fence_wait(device->ws,
5774 part->fence,
5775 true, timeout);
5776 if (!expired)
5777 return VK_TIMEOUT;
5778 break;
5779 case RADV_FENCE_SYNCOBJ:
5780 if (!device->ws->wait_syncobj(device->ws,
5781 &part->syncobj, 1, true,
5782 timeout))
5783 return VK_TIMEOUT;
5784 break;
5785 case RADV_FENCE_WSI: {
5786 VkResult result = part->fence_wsi->wait(part->fence_wsi, timeout);
5787 if (result != VK_SUCCESS)
5788 return result;
5789 break;
5790 }
5791 default:
5792 unreachable("Invalid fence type");
5793 }
5794 }
5795
5796 return VK_SUCCESS;
5797 }
5798
5799 VkResult radv_ResetFences(VkDevice _device,
5800 uint32_t fenceCount,
5801 const VkFence *pFences)
5802 {
5803 RADV_FROM_HANDLE(radv_device, device, _device);
5804
5805 for (unsigned i = 0; i < fenceCount; ++i) {
5806 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5807
5808 /* From the Vulkan 1.0.53 spec:
5809 *
5810 * "If any member of pFences currently has its payload
5811 * imported with temporary permanence, that fence’s prior
5812 * permanent payload is irst restored. The remaining
5813 * operations described therefore operate on the restored
5814 * payload."
5815 */
5816 if (fence->temporary.kind != RADV_FENCE_NONE)
5817 radv_destroy_fence_part(device, &fence->temporary);
5818
5819 struct radv_fence_part *part = &fence->permanent;
5820
5821 switch (part->kind) {
5822 case RADV_FENCE_WSI:
5823 device->ws->reset_fence(part->fence);
5824 break;
5825 case RADV_FENCE_SYNCOBJ:
5826 device->ws->reset_syncobj(device->ws, part->syncobj);
5827 break;
5828 default:
5829 unreachable("Invalid fence type");
5830 }
5831 }
5832
5833 return VK_SUCCESS;
5834 }
5835
5836 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
5837 {
5838 RADV_FROM_HANDLE(radv_device, device, _device);
5839 RADV_FROM_HANDLE(radv_fence, fence, _fence);
5840
5841 struct radv_fence_part *part =
5842 fence->temporary.kind != RADV_FENCE_NONE ?
5843 &fence->temporary : &fence->permanent;
5844
5845 if (radv_device_is_lost(device))
5846 return VK_ERROR_DEVICE_LOST;
5847
5848 switch (part->kind) {
5849 case RADV_FENCE_NONE:
5850 break;
5851 case RADV_FENCE_WINSYS:
5852 if (!device->ws->fence_wait(device->ws, part->fence, false, 0))
5853 return VK_NOT_READY;
5854 break;
5855 case RADV_FENCE_SYNCOBJ: {
5856 bool success = device->ws->wait_syncobj(device->ws,
5857 &part->syncobj, 1, true, 0);
5858 if (!success)
5859 return VK_NOT_READY;
5860 break;
5861 }
5862 case RADV_FENCE_WSI: {
5863 VkResult result = part->fence_wsi->wait(part->fence_wsi, 0);
5864 if (result != VK_SUCCESS) {
5865 if (result == VK_TIMEOUT)
5866 return VK_NOT_READY;
5867 return result;
5868 }
5869 break;
5870 }
5871 default:
5872 unreachable("Invalid fence type");
5873 }
5874
5875 return VK_SUCCESS;
5876 }
5877
5878
5879 // Queue semaphore functions
5880
5881 static void
5882 radv_create_timeline(struct radv_timeline *timeline, uint64_t value)
5883 {
5884 timeline->highest_signaled = value;
5885 timeline->highest_submitted = value;
5886 list_inithead(&timeline->points);
5887 list_inithead(&timeline->free_points);
5888 list_inithead(&timeline->waiters);
5889 pthread_mutex_init(&timeline->mutex, NULL);
5890 }
5891
5892 static void
5893 radv_destroy_timeline(struct radv_device *device,
5894 struct radv_timeline *timeline)
5895 {
5896 list_for_each_entry_safe(struct radv_timeline_point, point,
5897 &timeline->free_points, list) {
5898 list_del(&point->list);
5899 device->ws->destroy_syncobj(device->ws, point->syncobj);
5900 free(point);
5901 }
5902 list_for_each_entry_safe(struct radv_timeline_point, point,
5903 &timeline->points, list) {
5904 list_del(&point->list);
5905 device->ws->destroy_syncobj(device->ws, point->syncobj);
5906 free(point);
5907 }
5908 pthread_mutex_destroy(&timeline->mutex);
5909 }
5910
5911 static void
5912 radv_timeline_gc_locked(struct radv_device *device,
5913 struct radv_timeline *timeline)
5914 {
5915 list_for_each_entry_safe(struct radv_timeline_point, point,
5916 &timeline->points, list) {
5917 if (point->wait_count || point->value > timeline->highest_submitted)
5918 return;
5919
5920 if (device->ws->wait_syncobj(device->ws, &point->syncobj, 1, true, 0)) {
5921 timeline->highest_signaled = point->value;
5922 list_del(&point->list);
5923 list_add(&point->list, &timeline->free_points);
5924 }
5925 }
5926 }
5927
5928 static struct radv_timeline_point *
5929 radv_timeline_find_point_at_least_locked(struct radv_device *device,
5930 struct radv_timeline *timeline,
5931 uint64_t p)
5932 {
5933 radv_timeline_gc_locked(device, timeline);
5934
5935 if (p <= timeline->highest_signaled)
5936 return NULL;
5937
5938 list_for_each_entry(struct radv_timeline_point, point,
5939 &timeline->points, list) {
5940 if (point->value >= p) {
5941 ++point->wait_count;
5942 return point;
5943 }
5944 }
5945 return NULL;
5946 }
5947
5948 static struct radv_timeline_point *
5949 radv_timeline_add_point_locked(struct radv_device *device,
5950 struct radv_timeline *timeline,
5951 uint64_t p)
5952 {
5953 radv_timeline_gc_locked(device, timeline);
5954
5955 struct radv_timeline_point *ret = NULL;
5956 struct radv_timeline_point *prev = NULL;
5957 int r;
5958
5959 if (p <= timeline->highest_signaled)
5960 return NULL;
5961
5962 list_for_each_entry(struct radv_timeline_point, point,
5963 &timeline->points, list) {
5964 if (point->value == p) {
5965 return NULL;
5966 }
5967
5968 if (point->value < p)
5969 prev = point;
5970 }
5971
5972 if (list_is_empty(&timeline->free_points)) {
5973 ret = malloc(sizeof(struct radv_timeline_point));
5974 r = device->ws->create_syncobj(device->ws, false, &ret->syncobj);
5975 if (r) {
5976 free(ret);
5977 return NULL;
5978 }
5979 } else {
5980 ret = list_first_entry(&timeline->free_points, struct radv_timeline_point, list);
5981 list_del(&ret->list);
5982
5983 device->ws->reset_syncobj(device->ws, ret->syncobj);
5984 }
5985
5986 ret->value = p;
5987 ret->wait_count = 1;
5988
5989 if (prev) {
5990 list_add(&ret->list, &prev->list);
5991 } else {
5992 list_addtail(&ret->list, &timeline->points);
5993 }
5994 return ret;
5995 }
5996
5997
5998 static VkResult
5999 radv_timeline_wait(struct radv_device *device,
6000 struct radv_timeline *timeline,
6001 uint64_t value,
6002 uint64_t abs_timeout)
6003 {
6004 pthread_mutex_lock(&timeline->mutex);
6005
6006 while(timeline->highest_submitted < value) {
6007 struct timespec abstime;
6008 timespec_from_nsec(&abstime, abs_timeout);
6009
6010 pthread_cond_timedwait(&device->timeline_cond, &timeline->mutex, &abstime);
6011
6012 if (radv_get_current_time() >= abs_timeout && timeline->highest_submitted < value) {
6013 pthread_mutex_unlock(&timeline->mutex);
6014 return VK_TIMEOUT;
6015 }
6016 }
6017
6018 struct radv_timeline_point *point = radv_timeline_find_point_at_least_locked(device, timeline, value);
6019 pthread_mutex_unlock(&timeline->mutex);
6020 if (!point)
6021 return VK_SUCCESS;
6022
6023 bool success = device->ws->wait_syncobj(device->ws, &point->syncobj, 1, true, abs_timeout);
6024
6025 pthread_mutex_lock(&timeline->mutex);
6026 point->wait_count--;
6027 pthread_mutex_unlock(&timeline->mutex);
6028 return success ? VK_SUCCESS : VK_TIMEOUT;
6029 }
6030
6031 static void
6032 radv_timeline_trigger_waiters_locked(struct radv_timeline *timeline,
6033 struct list_head *processing_list)
6034 {
6035 list_for_each_entry_safe(struct radv_timeline_waiter, waiter,
6036 &timeline->waiters, list) {
6037 if (waiter->value > timeline->highest_submitted)
6038 continue;
6039
6040 radv_queue_trigger_submission(waiter->submission, 1, processing_list);
6041 list_del(&waiter->list);
6042 }
6043 }
6044
6045 static
6046 void radv_destroy_semaphore_part(struct radv_device *device,
6047 struct radv_semaphore_part *part)
6048 {
6049 switch(part->kind) {
6050 case RADV_SEMAPHORE_NONE:
6051 break;
6052 case RADV_SEMAPHORE_WINSYS:
6053 device->ws->destroy_sem(part->ws_sem);
6054 break;
6055 case RADV_SEMAPHORE_TIMELINE:
6056 radv_destroy_timeline(device, &part->timeline);
6057 break;
6058 case RADV_SEMAPHORE_SYNCOBJ:
6059 case RADV_SEMAPHORE_TIMELINE_SYNCOBJ:
6060 device->ws->destroy_syncobj(device->ws, part->syncobj);
6061 break;
6062 }
6063 part->kind = RADV_SEMAPHORE_NONE;
6064 }
6065
6066 static VkSemaphoreTypeKHR
6067 radv_get_semaphore_type(const void *pNext, uint64_t *initial_value)
6068 {
6069 const VkSemaphoreTypeCreateInfo *type_info =
6070 vk_find_struct_const(pNext, SEMAPHORE_TYPE_CREATE_INFO);
6071
6072 if (!type_info)
6073 return VK_SEMAPHORE_TYPE_BINARY;
6074
6075 if (initial_value)
6076 *initial_value = type_info->initialValue;
6077 return type_info->semaphoreType;
6078 }
6079
6080 static void
6081 radv_destroy_semaphore(struct radv_device *device,
6082 const VkAllocationCallbacks *pAllocator,
6083 struct radv_semaphore *sem)
6084 {
6085 radv_destroy_semaphore_part(device, &sem->temporary);
6086 radv_destroy_semaphore_part(device, &sem->permanent);
6087 vk_object_base_finish(&sem->base);
6088 vk_free2(&device->vk.alloc, pAllocator, sem);
6089 }
6090
6091 VkResult radv_CreateSemaphore(
6092 VkDevice _device,
6093 const VkSemaphoreCreateInfo* pCreateInfo,
6094 const VkAllocationCallbacks* pAllocator,
6095 VkSemaphore* pSemaphore)
6096 {
6097 RADV_FROM_HANDLE(radv_device, device, _device);
6098 const VkExportSemaphoreCreateInfo *export =
6099 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
6100 VkExternalSemaphoreHandleTypeFlags handleTypes =
6101 export ? export->handleTypes : 0;
6102 uint64_t initial_value = 0;
6103 VkSemaphoreTypeKHR type = radv_get_semaphore_type(pCreateInfo->pNext, &initial_value);
6104
6105 struct radv_semaphore *sem = vk_alloc2(&device->vk.alloc, pAllocator,
6106 sizeof(*sem), 8,
6107 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
6108 if (!sem)
6109 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6110
6111 vk_object_base_init(&device->vk, &sem->base,
6112 VK_OBJECT_TYPE_SEMAPHORE);
6113
6114 sem->temporary.kind = RADV_SEMAPHORE_NONE;
6115 sem->permanent.kind = RADV_SEMAPHORE_NONE;
6116
6117 if (type == VK_SEMAPHORE_TYPE_TIMELINE &&
6118 device->physical_device->rad_info.has_timeline_syncobj) {
6119 int ret = device->ws->create_syncobj(device->ws, false, &sem->permanent.syncobj);
6120 if (ret) {
6121 radv_destroy_semaphore(device, pAllocator, sem);
6122 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6123 }
6124 device->ws->signal_syncobj(device->ws, sem->permanent.syncobj, initial_value);
6125 sem->permanent.timeline_syncobj.max_point = initial_value;
6126 sem->permanent.kind = RADV_SEMAPHORE_TIMELINE_SYNCOBJ;
6127 } else if (type == VK_SEMAPHORE_TYPE_TIMELINE) {
6128 radv_create_timeline(&sem->permanent.timeline, initial_value);
6129 sem->permanent.kind = RADV_SEMAPHORE_TIMELINE;
6130 } else if (device->always_use_syncobj || handleTypes) {
6131 assert (device->physical_device->rad_info.has_syncobj);
6132 int ret = device->ws->create_syncobj(device->ws, false,
6133 &sem->permanent.syncobj);
6134 if (ret) {
6135 radv_destroy_semaphore(device, pAllocator, sem);
6136 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6137 }
6138 sem->permanent.kind = RADV_SEMAPHORE_SYNCOBJ;
6139 } else {
6140 sem->permanent.ws_sem = device->ws->create_sem(device->ws);
6141 if (!sem->permanent.ws_sem) {
6142 radv_destroy_semaphore(device, pAllocator, sem);
6143 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6144 }
6145 sem->permanent.kind = RADV_SEMAPHORE_WINSYS;
6146 }
6147
6148 *pSemaphore = radv_semaphore_to_handle(sem);
6149 return VK_SUCCESS;
6150 }
6151
6152 void radv_DestroySemaphore(
6153 VkDevice _device,
6154 VkSemaphore _semaphore,
6155 const VkAllocationCallbacks* pAllocator)
6156 {
6157 RADV_FROM_HANDLE(radv_device, device, _device);
6158 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
6159 if (!_semaphore)
6160 return;
6161
6162 radv_destroy_semaphore(device, pAllocator, sem);
6163 }
6164
6165 VkResult
6166 radv_GetSemaphoreCounterValue(VkDevice _device,
6167 VkSemaphore _semaphore,
6168 uint64_t* pValue)
6169 {
6170 RADV_FROM_HANDLE(radv_device, device, _device);
6171 RADV_FROM_HANDLE(radv_semaphore, semaphore, _semaphore);
6172
6173 if (radv_device_is_lost(device))
6174 return VK_ERROR_DEVICE_LOST;
6175
6176 struct radv_semaphore_part *part =
6177 semaphore->temporary.kind != RADV_SEMAPHORE_NONE ? &semaphore->temporary : &semaphore->permanent;
6178
6179 switch (part->kind) {
6180 case RADV_SEMAPHORE_TIMELINE: {
6181 pthread_mutex_lock(&part->timeline.mutex);
6182 radv_timeline_gc_locked(device, &part->timeline);
6183 *pValue = part->timeline.highest_signaled;
6184 pthread_mutex_unlock(&part->timeline.mutex);
6185 return VK_SUCCESS;
6186 }
6187 case RADV_SEMAPHORE_TIMELINE_SYNCOBJ: {
6188 return device->ws->query_syncobj(device->ws, part->syncobj, pValue);
6189 }
6190 case RADV_SEMAPHORE_NONE:
6191 case RADV_SEMAPHORE_SYNCOBJ:
6192 case RADV_SEMAPHORE_WINSYS:
6193 unreachable("Invalid semaphore type");
6194 }
6195 unreachable("Unhandled semaphore type");
6196 }
6197
6198
6199 static VkResult
6200 radv_wait_timelines(struct radv_device *device,
6201 const VkSemaphoreWaitInfo* pWaitInfo,
6202 uint64_t abs_timeout)
6203 {
6204 if ((pWaitInfo->flags & VK_SEMAPHORE_WAIT_ANY_BIT_KHR) && pWaitInfo->semaphoreCount > 1) {
6205 for (;;) {
6206 for(uint32_t i = 0; i < pWaitInfo->semaphoreCount; ++i) {
6207 RADV_FROM_HANDLE(radv_semaphore, semaphore, pWaitInfo->pSemaphores[i]);
6208 VkResult result = radv_timeline_wait(device, &semaphore->permanent.timeline, pWaitInfo->pValues[i], 0);
6209
6210 if (result == VK_SUCCESS)
6211 return VK_SUCCESS;
6212 }
6213 if (radv_get_current_time() > abs_timeout)
6214 return VK_TIMEOUT;
6215 }
6216 }
6217
6218 for(uint32_t i = 0; i < pWaitInfo->semaphoreCount; ++i) {
6219 RADV_FROM_HANDLE(radv_semaphore, semaphore, pWaitInfo->pSemaphores[i]);
6220 VkResult result = radv_timeline_wait(device, &semaphore->permanent.timeline, pWaitInfo->pValues[i], abs_timeout);
6221
6222 if (result != VK_SUCCESS)
6223 return result;
6224 }
6225 return VK_SUCCESS;
6226 }
6227 VkResult
6228 radv_WaitSemaphores(VkDevice _device,
6229 const VkSemaphoreWaitInfo* pWaitInfo,
6230 uint64_t timeout)
6231 {
6232 RADV_FROM_HANDLE(radv_device, device, _device);
6233
6234 if (radv_device_is_lost(device))
6235 return VK_ERROR_DEVICE_LOST;
6236
6237 uint64_t abs_timeout = radv_get_absolute_timeout(timeout);
6238
6239 if (radv_semaphore_from_handle(pWaitInfo->pSemaphores[0])->permanent.kind == RADV_SEMAPHORE_TIMELINE)
6240 return radv_wait_timelines(device, pWaitInfo, abs_timeout);
6241
6242 if (pWaitInfo->semaphoreCount > UINT32_MAX / sizeof(uint32_t))
6243 return vk_errorf(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY, "semaphoreCount integer overflow");
6244
6245 bool wait_all = !(pWaitInfo->flags & VK_SEMAPHORE_WAIT_ANY_BIT_KHR);
6246 uint32_t *handles = malloc(sizeof(*handles) * pWaitInfo->semaphoreCount);
6247 if (!handles)
6248 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6249
6250 for (uint32_t i = 0; i < pWaitInfo->semaphoreCount; ++i) {
6251 RADV_FROM_HANDLE(radv_semaphore, semaphore, pWaitInfo->pSemaphores[i]);
6252 handles[i] = semaphore->permanent.syncobj;
6253 }
6254
6255 bool success = device->ws->wait_timeline_syncobj(device->ws, handles, pWaitInfo->pValues,
6256 pWaitInfo->semaphoreCount, wait_all, false,
6257 abs_timeout);
6258 free(handles);
6259 return success ? VK_SUCCESS : VK_TIMEOUT;
6260 }
6261
6262 VkResult
6263 radv_SignalSemaphore(VkDevice _device,
6264 const VkSemaphoreSignalInfo* pSignalInfo)
6265 {
6266 RADV_FROM_HANDLE(radv_device, device, _device);
6267 RADV_FROM_HANDLE(radv_semaphore, semaphore, pSignalInfo->semaphore);
6268
6269 struct radv_semaphore_part *part =
6270 semaphore->temporary.kind != RADV_SEMAPHORE_NONE ? &semaphore->temporary : &semaphore->permanent;
6271
6272 switch(part->kind) {
6273 case RADV_SEMAPHORE_TIMELINE: {
6274 pthread_mutex_lock(&part->timeline.mutex);
6275 radv_timeline_gc_locked(device, &part->timeline);
6276 part->timeline.highest_submitted = MAX2(part->timeline.highest_submitted, pSignalInfo->value);
6277 part->timeline.highest_signaled = MAX2(part->timeline.highest_signaled, pSignalInfo->value);
6278
6279 struct list_head processing_list;
6280 list_inithead(&processing_list);
6281 radv_timeline_trigger_waiters_locked(&part->timeline, &processing_list);
6282 pthread_mutex_unlock(&part->timeline.mutex);
6283
6284 VkResult result = radv_process_submissions(&processing_list);
6285
6286 /* This needs to happen after radv_process_submissions, so
6287 * that any submitted submissions that are now unblocked get
6288 * processed before we wake the application. This way we
6289 * ensure that any binary semaphores that are now unblocked
6290 * are usable by the application. */
6291 pthread_cond_broadcast(&device->timeline_cond);
6292
6293 return result;
6294 }
6295 case RADV_SEMAPHORE_TIMELINE_SYNCOBJ: {
6296 part->timeline_syncobj.max_point = MAX2(part->timeline_syncobj.max_point, pSignalInfo->value);
6297 device->ws->signal_syncobj(device->ws, part->syncobj, pSignalInfo->value);
6298 break;
6299 }
6300 case RADV_SEMAPHORE_NONE:
6301 case RADV_SEMAPHORE_SYNCOBJ:
6302 case RADV_SEMAPHORE_WINSYS:
6303 unreachable("Invalid semaphore type");
6304 }
6305 return VK_SUCCESS;
6306 }
6307
6308 static void radv_destroy_event(struct radv_device *device,
6309 const VkAllocationCallbacks* pAllocator,
6310 struct radv_event *event)
6311 {
6312 if (event->bo)
6313 device->ws->buffer_destroy(event->bo);
6314
6315 vk_object_base_finish(&event->base);
6316 vk_free2(&device->vk.alloc, pAllocator, event);
6317 }
6318
6319 VkResult radv_CreateEvent(
6320 VkDevice _device,
6321 const VkEventCreateInfo* pCreateInfo,
6322 const VkAllocationCallbacks* pAllocator,
6323 VkEvent* pEvent)
6324 {
6325 RADV_FROM_HANDLE(radv_device, device, _device);
6326 struct radv_event *event = vk_alloc2(&device->vk.alloc, pAllocator,
6327 sizeof(*event), 8,
6328 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
6329
6330 if (!event)
6331 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6332
6333 vk_object_base_init(&device->vk, &event->base, VK_OBJECT_TYPE_EVENT);
6334
6335 event->bo = device->ws->buffer_create(device->ws, 8, 8,
6336 RADEON_DOMAIN_GTT,
6337 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
6338 RADV_BO_PRIORITY_FENCE);
6339 if (!event->bo) {
6340 radv_destroy_event(device, pAllocator, event);
6341 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
6342 }
6343
6344 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
6345 if (!event->map) {
6346 radv_destroy_event(device, pAllocator, event);
6347 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
6348 }
6349
6350 *pEvent = radv_event_to_handle(event);
6351
6352 return VK_SUCCESS;
6353 }
6354
6355 void radv_DestroyEvent(
6356 VkDevice _device,
6357 VkEvent _event,
6358 const VkAllocationCallbacks* pAllocator)
6359 {
6360 RADV_FROM_HANDLE(radv_device, device, _device);
6361 RADV_FROM_HANDLE(radv_event, event, _event);
6362
6363 if (!event)
6364 return;
6365
6366 radv_destroy_event(device, pAllocator, event);
6367 }
6368
6369 VkResult radv_GetEventStatus(
6370 VkDevice _device,
6371 VkEvent _event)
6372 {
6373 RADV_FROM_HANDLE(radv_device, device, _device);
6374 RADV_FROM_HANDLE(radv_event, event, _event);
6375
6376 if (radv_device_is_lost(device))
6377 return VK_ERROR_DEVICE_LOST;
6378
6379 if (*event->map == 1)
6380 return VK_EVENT_SET;
6381 return VK_EVENT_RESET;
6382 }
6383
6384 VkResult radv_SetEvent(
6385 VkDevice _device,
6386 VkEvent _event)
6387 {
6388 RADV_FROM_HANDLE(radv_event, event, _event);
6389 *event->map = 1;
6390
6391 return VK_SUCCESS;
6392 }
6393
6394 VkResult radv_ResetEvent(
6395 VkDevice _device,
6396 VkEvent _event)
6397 {
6398 RADV_FROM_HANDLE(radv_event, event, _event);
6399 *event->map = 0;
6400
6401 return VK_SUCCESS;
6402 }
6403
6404 static void
6405 radv_destroy_buffer(struct radv_device *device,
6406 const VkAllocationCallbacks *pAllocator,
6407 struct radv_buffer *buffer)
6408 {
6409 if ((buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) && buffer->bo)
6410 device->ws->buffer_destroy(buffer->bo);
6411
6412 vk_object_base_finish(&buffer->base);
6413 vk_free2(&device->vk.alloc, pAllocator, buffer);
6414 }
6415
6416 VkResult radv_CreateBuffer(
6417 VkDevice _device,
6418 const VkBufferCreateInfo* pCreateInfo,
6419 const VkAllocationCallbacks* pAllocator,
6420 VkBuffer* pBuffer)
6421 {
6422 RADV_FROM_HANDLE(radv_device, device, _device);
6423 struct radv_buffer *buffer;
6424
6425 if (pCreateInfo->size > RADV_MAX_MEMORY_ALLOCATION_SIZE)
6426 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
6427
6428 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
6429
6430 buffer = vk_alloc2(&device->vk.alloc, pAllocator, sizeof(*buffer), 8,
6431 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
6432 if (buffer == NULL)
6433 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6434
6435 vk_object_base_init(&device->vk, &buffer->base, VK_OBJECT_TYPE_BUFFER);
6436
6437 buffer->size = pCreateInfo->size;
6438 buffer->usage = pCreateInfo->usage;
6439 buffer->bo = NULL;
6440 buffer->offset = 0;
6441 buffer->flags = pCreateInfo->flags;
6442
6443 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
6444 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
6445
6446 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
6447 buffer->bo = device->ws->buffer_create(device->ws,
6448 align64(buffer->size, 4096),
6449 4096, 0, RADEON_FLAG_VIRTUAL,
6450 RADV_BO_PRIORITY_VIRTUAL);
6451 if (!buffer->bo) {
6452 radv_destroy_buffer(device, pAllocator, buffer);
6453 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
6454 }
6455 }
6456
6457 *pBuffer = radv_buffer_to_handle(buffer);
6458
6459 return VK_SUCCESS;
6460 }
6461
6462 void radv_DestroyBuffer(
6463 VkDevice _device,
6464 VkBuffer _buffer,
6465 const VkAllocationCallbacks* pAllocator)
6466 {
6467 RADV_FROM_HANDLE(radv_device, device, _device);
6468 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
6469
6470 if (!buffer)
6471 return;
6472
6473 radv_destroy_buffer(device, pAllocator, buffer);
6474 }
6475
6476 VkDeviceAddress radv_GetBufferDeviceAddress(
6477 VkDevice device,
6478 const VkBufferDeviceAddressInfo* pInfo)
6479 {
6480 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
6481 return radv_buffer_get_va(buffer->bo) + buffer->offset;
6482 }
6483
6484
6485 uint64_t radv_GetBufferOpaqueCaptureAddress(VkDevice device,
6486 const VkBufferDeviceAddressInfo* pInfo)
6487 {
6488 return 0;
6489 }
6490
6491 uint64_t radv_GetDeviceMemoryOpaqueCaptureAddress(VkDevice device,
6492 const VkDeviceMemoryOpaqueCaptureAddressInfo* pInfo)
6493 {
6494 return 0;
6495 }
6496
6497 static inline unsigned
6498 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
6499 {
6500 if (stencil)
6501 return plane->surface.u.legacy.stencil_tiling_index[level];
6502 else
6503 return plane->surface.u.legacy.tiling_index[level];
6504 }
6505
6506 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
6507 {
6508 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
6509 }
6510
6511 static uint32_t
6512 radv_init_dcc_control_reg(struct radv_device *device,
6513 struct radv_image_view *iview)
6514 {
6515 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
6516 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
6517 unsigned max_compressed_block_size;
6518 unsigned independent_128b_blocks;
6519 unsigned independent_64b_blocks;
6520
6521 if (!radv_dcc_enabled(iview->image, iview->base_mip))
6522 return 0;
6523
6524 if (!device->physical_device->rad_info.has_dedicated_vram) {
6525 /* amdvlk: [min-compressed-block-size] should be set to 32 for
6526 * dGPU and 64 for APU because all of our APUs to date use
6527 * DIMMs which have a request granularity size of 64B while all
6528 * other chips have a 32B request size.
6529 */
6530 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
6531 }
6532
6533 if (device->physical_device->rad_info.chip_class >= GFX10) {
6534 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
6535 independent_64b_blocks = 0;
6536 independent_128b_blocks = 1;
6537 } else {
6538 independent_128b_blocks = 0;
6539
6540 if (iview->image->info.samples > 1) {
6541 if (iview->image->planes[0].surface.bpe == 1)
6542 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
6543 else if (iview->image->planes[0].surface.bpe == 2)
6544 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
6545 }
6546
6547 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
6548 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
6549 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
6550 /* If this DCC image is potentially going to be used in texture
6551 * fetches, we need some special settings.
6552 */
6553 independent_64b_blocks = 1;
6554 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
6555 } else {
6556 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
6557 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
6558 * big as possible for better compression state.
6559 */
6560 independent_64b_blocks = 0;
6561 max_compressed_block_size = max_uncompressed_block_size;
6562 }
6563 }
6564
6565 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
6566 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
6567 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
6568 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks) |
6569 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks);
6570 }
6571
6572 void
6573 radv_initialise_color_surface(struct radv_device *device,
6574 struct radv_color_buffer_info *cb,
6575 struct radv_image_view *iview)
6576 {
6577 const struct vk_format_description *desc;
6578 unsigned ntype, format, swap, endian;
6579 unsigned blend_clamp = 0, blend_bypass = 0;
6580 uint64_t va;
6581 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
6582 const struct radeon_surf *surf = &plane->surface;
6583
6584 desc = vk_format_description(iview->vk_format);
6585
6586 memset(cb, 0, sizeof(*cb));
6587
6588 /* Intensity is implemented as Red, so treat it that way. */
6589 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
6590
6591 va = radv_buffer_get_va(iview->bo) + iview->image->offset + plane->offset;
6592
6593 cb->cb_color_base = va >> 8;
6594
6595 if (device->physical_device->rad_info.chip_class >= GFX9) {
6596 if (device->physical_device->rad_info.chip_class >= GFX10) {
6597 cb->cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
6598 S_028EE0_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
6599 S_028EE0_CMASK_PIPE_ALIGNED(1) |
6600 S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.dcc.pipe_aligned);
6601 } else {
6602 struct gfx9_surf_meta_flags meta = {
6603 .rb_aligned = 1,
6604 .pipe_aligned = 1,
6605 };
6606
6607 if (surf->dcc_offset)
6608 meta = surf->u.gfx9.dcc;
6609
6610 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
6611 S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
6612 S_028C74_RB_ALIGNED(meta.rb_aligned) |
6613 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
6614 cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch);
6615 }
6616
6617 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
6618 cb->cb_color_base |= surf->tile_swizzle;
6619 } else {
6620 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
6621 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
6622
6623 cb->cb_color_base += level_info->offset >> 8;
6624 if (level_info->mode == RADEON_SURF_MODE_2D)
6625 cb->cb_color_base |= surf->tile_swizzle;
6626
6627 pitch_tile_max = level_info->nblk_x / 8 - 1;
6628 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
6629 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false);
6630
6631 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
6632 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
6633 cb->cb_color_cmask_slice = surf->u.legacy.cmask_slice_tile_max;
6634
6635 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
6636
6637 if (radv_image_has_fmask(iview->image)) {
6638 if (device->physical_device->rad_info.chip_class >= GFX7)
6639 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(surf->u.legacy.fmask.pitch_in_pixels / 8 - 1);
6640 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(surf->u.legacy.fmask.tiling_index);
6641 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(surf->u.legacy.fmask.slice_tile_max);
6642 } else {
6643 /* This must be set for fast clear to work without FMASK. */
6644 if (device->physical_device->rad_info.chip_class >= GFX7)
6645 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
6646 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
6647 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
6648 }
6649 }
6650
6651 /* CMASK variables */
6652 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
6653 va += surf->cmask_offset;
6654 cb->cb_color_cmask = va >> 8;
6655
6656 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
6657 va += surf->dcc_offset;
6658
6659 if (radv_dcc_enabled(iview->image, iview->base_mip) &&
6660 device->physical_device->rad_info.chip_class <= GFX8)
6661 va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
6662
6663 unsigned dcc_tile_swizzle = surf->tile_swizzle;
6664 dcc_tile_swizzle &= (surf->dcc_alignment - 1) >> 8;
6665
6666 cb->cb_dcc_base = va >> 8;
6667 cb->cb_dcc_base |= dcc_tile_swizzle;
6668
6669 /* GFX10 field has the same base shift as the GFX6 field. */
6670 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
6671 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
6672 S_028C6C_SLICE_MAX_GFX10(max_slice);
6673
6674 if (iview->image->info.samples > 1) {
6675 unsigned log_samples = util_logbase2(iview->image->info.samples);
6676
6677 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
6678 S_028C74_NUM_FRAGMENTS(log_samples);
6679 }
6680
6681 if (radv_image_has_fmask(iview->image)) {
6682 va = radv_buffer_get_va(iview->bo) + iview->image->offset + surf->fmask_offset;
6683 cb->cb_color_fmask = va >> 8;
6684 cb->cb_color_fmask |= surf->fmask_tile_swizzle;
6685 } else {
6686 cb->cb_color_fmask = cb->cb_color_base;
6687 }
6688
6689 ntype = radv_translate_color_numformat(iview->vk_format,
6690 desc,
6691 vk_format_get_first_non_void_channel(iview->vk_format));
6692 format = radv_translate_colorformat(iview->vk_format);
6693 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
6694 radv_finishme("Illegal color\n");
6695 swap = radv_translate_colorswap(iview->vk_format, false);
6696 endian = radv_colorformat_endian_swap(format);
6697
6698 /* blend clamp should be set for all NORM/SRGB types */
6699 if (ntype == V_028C70_NUMBER_UNORM ||
6700 ntype == V_028C70_NUMBER_SNORM ||
6701 ntype == V_028C70_NUMBER_SRGB)
6702 blend_clamp = 1;
6703
6704 /* set blend bypass according to docs if SINT/UINT or
6705 8/24 COLOR variants */
6706 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
6707 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
6708 format == V_028C70_COLOR_X24_8_32_FLOAT) {
6709 blend_clamp = 0;
6710 blend_bypass = 1;
6711 }
6712 #if 0
6713 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
6714 (format == V_028C70_COLOR_8 ||
6715 format == V_028C70_COLOR_8_8 ||
6716 format == V_028C70_COLOR_8_8_8_8))
6717 ->color_is_int8 = true;
6718 #endif
6719 cb->cb_color_info = S_028C70_FORMAT(format) |
6720 S_028C70_COMP_SWAP(swap) |
6721 S_028C70_BLEND_CLAMP(blend_clamp) |
6722 S_028C70_BLEND_BYPASS(blend_bypass) |
6723 S_028C70_SIMPLE_FLOAT(1) |
6724 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
6725 ntype != V_028C70_NUMBER_SNORM &&
6726 ntype != V_028C70_NUMBER_SRGB &&
6727 format != V_028C70_COLOR_8_24 &&
6728 format != V_028C70_COLOR_24_8) |
6729 S_028C70_NUMBER_TYPE(ntype) |
6730 S_028C70_ENDIAN(endian);
6731 if (radv_image_has_fmask(iview->image)) {
6732 cb->cb_color_info |= S_028C70_COMPRESSION(1);
6733 if (device->physical_device->rad_info.chip_class == GFX6) {
6734 unsigned fmask_bankh = util_logbase2(surf->u.legacy.fmask.bankh);
6735 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
6736 }
6737
6738 if (radv_image_is_tc_compat_cmask(iview->image)) {
6739 /* Allow the texture block to read FMASK directly
6740 * without decompressing it. This bit must be cleared
6741 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
6742 * otherwise the operation doesn't happen.
6743 */
6744 cb->cb_color_info |= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
6745
6746 /* Set CMASK into a tiling format that allows the
6747 * texture block to read it.
6748 */
6749 cb->cb_color_info |= S_028C70_CMASK_ADDR_TYPE(2);
6750 }
6751 }
6752
6753 if (radv_image_has_cmask(iview->image) &&
6754 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
6755 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
6756
6757 if (radv_dcc_enabled(iview->image, iview->base_mip))
6758 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
6759
6760 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
6761
6762 /* This must be set for fast clear to work without FMASK. */
6763 if (!radv_image_has_fmask(iview->image) &&
6764 device->physical_device->rad_info.chip_class == GFX6) {
6765 unsigned bankh = util_logbase2(surf->u.legacy.bankh);
6766 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
6767 }
6768
6769 if (device->physical_device->rad_info.chip_class >= GFX9) {
6770 const struct vk_format_description *format_desc = vk_format_description(iview->image->vk_format);
6771
6772 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
6773 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
6774 unsigned width = iview->extent.width / (iview->plane_id ? format_desc->width_divisor : 1);
6775 unsigned height = iview->extent.height / (iview->plane_id ? format_desc->height_divisor : 1);
6776
6777 if (device->physical_device->rad_info.chip_class >= GFX10) {
6778 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX10(iview->base_mip);
6779
6780 cb->cb_color_attrib3 |= S_028EE0_MIP0_DEPTH(mip0_depth) |
6781 S_028EE0_RESOURCE_TYPE(surf->u.gfx9.resource_type) |
6782 S_028EE0_RESOURCE_LEVEL(1);
6783 } else {
6784 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX9(iview->base_mip);
6785 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
6786 S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
6787 }
6788
6789 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(width - 1) |
6790 S_028C68_MIP0_HEIGHT(height - 1) |
6791 S_028C68_MAX_MIP(iview->image->info.levels - 1);
6792 }
6793 }
6794
6795 static unsigned
6796 radv_calc_decompress_on_z_planes(struct radv_device *device,
6797 struct radv_image_view *iview)
6798 {
6799 unsigned max_zplanes = 0;
6800
6801 assert(radv_image_is_tc_compat_htile(iview->image));
6802
6803 if (device->physical_device->rad_info.chip_class >= GFX9) {
6804 /* Default value for 32-bit depth surfaces. */
6805 max_zplanes = 4;
6806
6807 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
6808 iview->image->info.samples > 1)
6809 max_zplanes = 2;
6810
6811 max_zplanes = max_zplanes + 1;
6812 } else {
6813 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
6814 /* Do not enable Z plane compression for 16-bit depth
6815 * surfaces because isn't supported on GFX8. Only
6816 * 32-bit depth surfaces are supported by the hardware.
6817 * This allows to maintain shader compatibility and to
6818 * reduce the number of depth decompressions.
6819 */
6820 max_zplanes = 1;
6821 } else {
6822 if (iview->image->info.samples <= 1)
6823 max_zplanes = 5;
6824 else if (iview->image->info.samples <= 4)
6825 max_zplanes = 3;
6826 else
6827 max_zplanes = 2;
6828 }
6829 }
6830
6831 return max_zplanes;
6832 }
6833
6834 void
6835 radv_initialise_ds_surface(struct radv_device *device,
6836 struct radv_ds_buffer_info *ds,
6837 struct radv_image_view *iview)
6838 {
6839 unsigned level = iview->base_mip;
6840 unsigned format, stencil_format;
6841 uint64_t va, s_offs, z_offs;
6842 bool stencil_only = false;
6843 const struct radv_image_plane *plane = &iview->image->planes[0];
6844 const struct radeon_surf *surf = &plane->surface;
6845
6846 assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
6847
6848 memset(ds, 0, sizeof(*ds));
6849 switch (iview->image->vk_format) {
6850 case VK_FORMAT_D24_UNORM_S8_UINT:
6851 case VK_FORMAT_X8_D24_UNORM_PACK32:
6852 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
6853 ds->offset_scale = 2.0f;
6854 break;
6855 case VK_FORMAT_D16_UNORM:
6856 case VK_FORMAT_D16_UNORM_S8_UINT:
6857 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
6858 ds->offset_scale = 4.0f;
6859 break;
6860 case VK_FORMAT_D32_SFLOAT:
6861 case VK_FORMAT_D32_SFLOAT_S8_UINT:
6862 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
6863 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
6864 ds->offset_scale = 1.0f;
6865 break;
6866 case VK_FORMAT_S8_UINT:
6867 stencil_only = true;
6868 break;
6869 default:
6870 break;
6871 }
6872
6873 format = radv_translate_dbformat(iview->image->vk_format);
6874 stencil_format = surf->has_stencil ?
6875 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
6876
6877 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
6878 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
6879 S_028008_SLICE_MAX(max_slice);
6880 if (device->physical_device->rad_info.chip_class >= GFX10) {
6881 ds->db_depth_view |= S_028008_SLICE_START_HI(iview->base_layer >> 11) |
6882 S_028008_SLICE_MAX_HI(max_slice >> 11);
6883 }
6884
6885 ds->db_htile_data_base = 0;
6886 ds->db_htile_surface = 0;
6887
6888 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
6889 s_offs = z_offs = va;
6890
6891 if (device->physical_device->rad_info.chip_class >= GFX9) {
6892 assert(surf->u.gfx9.surf_offset == 0);
6893 s_offs += surf->u.gfx9.stencil_offset;
6894
6895 ds->db_z_info = S_028038_FORMAT(format) |
6896 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
6897 S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
6898 S_028038_MAXMIP(iview->image->info.levels - 1) |
6899 S_028038_ZRANGE_PRECISION(1);
6900 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
6901 S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode);
6902
6903 if (device->physical_device->rad_info.chip_class == GFX9) {
6904 ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch);
6905 ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch);
6906 }
6907
6908 ds->db_depth_view |= S_028008_MIPID(level);
6909 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
6910 S_02801C_Y_MAX(iview->image->info.height - 1);
6911
6912 if (radv_htile_enabled(iview->image, level)) {
6913 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
6914
6915 if (radv_image_is_tc_compat_htile(iview->image)) {
6916 unsigned max_zplanes =
6917 radv_calc_decompress_on_z_planes(device, iview);
6918
6919 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
6920
6921 if (device->physical_device->rad_info.chip_class >= GFX10) {
6922 ds->db_z_info |= S_028040_ITERATE_FLUSH(1);
6923 ds->db_stencil_info |= S_028044_ITERATE_FLUSH(1);
6924 } else {
6925 ds->db_z_info |= S_028038_ITERATE_FLUSH(1);
6926 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
6927 }
6928 }
6929
6930 if (!surf->has_stencil)
6931 /* Use all of the htile_buffer for depth if there's no stencil. */
6932 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
6933 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
6934 surf->htile_offset;
6935 ds->db_htile_data_base = va >> 8;
6936 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
6937 S_028ABC_PIPE_ALIGNED(1);
6938
6939 if (device->physical_device->rad_info.chip_class == GFX9) {
6940 ds->db_htile_surface |= S_028ABC_RB_ALIGNED(1);
6941 }
6942 }
6943 } else {
6944 const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];
6945
6946 if (stencil_only)
6947 level_info = &surf->u.legacy.stencil_level[level];
6948
6949 z_offs += surf->u.legacy.level[level].offset;
6950 s_offs += surf->u.legacy.stencil_level[level].offset;
6951
6952 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
6953 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
6954 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
6955
6956 if (iview->image->info.samples > 1)
6957 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
6958
6959 if (device->physical_device->rad_info.chip_class >= GFX7) {
6960 struct radeon_info *info = &device->physical_device->rad_info;
6961 unsigned tiling_index = surf->u.legacy.tiling_index[level];
6962 unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level];
6963 unsigned macro_index = surf->u.legacy.macro_tile_index;
6964 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
6965 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
6966 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
6967
6968 if (stencil_only)
6969 tile_mode = stencil_tile_mode;
6970
6971 ds->db_depth_info |=
6972 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
6973 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
6974 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
6975 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
6976 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
6977 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
6978 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
6979 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
6980 } else {
6981 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false);
6982 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
6983 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true);
6984 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
6985 if (stencil_only)
6986 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
6987 }
6988
6989 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
6990 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
6991 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
6992
6993 if (radv_htile_enabled(iview->image, level)) {
6994 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
6995
6996 if (!surf->has_stencil &&
6997 !radv_image_is_tc_compat_htile(iview->image))
6998 /* Use all of the htile_buffer for depth if there's no stencil. */
6999 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
7000
7001 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
7002 surf->htile_offset;
7003 ds->db_htile_data_base = va >> 8;
7004 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
7005
7006 if (radv_image_is_tc_compat_htile(iview->image)) {
7007 unsigned max_zplanes =
7008 radv_calc_decompress_on_z_planes(device, iview);
7009
7010 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
7011 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
7012 }
7013 }
7014 }
7015
7016 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
7017 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
7018 }
7019
7020 VkResult radv_CreateFramebuffer(
7021 VkDevice _device,
7022 const VkFramebufferCreateInfo* pCreateInfo,
7023 const VkAllocationCallbacks* pAllocator,
7024 VkFramebuffer* pFramebuffer)
7025 {
7026 RADV_FROM_HANDLE(radv_device, device, _device);
7027 struct radv_framebuffer *framebuffer;
7028 const VkFramebufferAttachmentsCreateInfo *imageless_create_info =
7029 vk_find_struct_const(pCreateInfo->pNext,
7030 FRAMEBUFFER_ATTACHMENTS_CREATE_INFO);
7031
7032 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
7033
7034 size_t size = sizeof(*framebuffer);
7035 if (!imageless_create_info)
7036 size += sizeof(struct radv_image_view*) * pCreateInfo->attachmentCount;
7037 framebuffer = vk_alloc2(&device->vk.alloc, pAllocator, size, 8,
7038 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
7039 if (framebuffer == NULL)
7040 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
7041
7042 vk_object_base_init(&device->vk, &framebuffer->base,
7043 VK_OBJECT_TYPE_FRAMEBUFFER);
7044
7045 framebuffer->attachment_count = pCreateInfo->attachmentCount;
7046 framebuffer->width = pCreateInfo->width;
7047 framebuffer->height = pCreateInfo->height;
7048 framebuffer->layers = pCreateInfo->layers;
7049 if (imageless_create_info) {
7050 for (unsigned i = 0; i < imageless_create_info->attachmentImageInfoCount; ++i) {
7051 const VkFramebufferAttachmentImageInfo *attachment =
7052 imageless_create_info->pAttachmentImageInfos + i;
7053 framebuffer->width = MIN2(framebuffer->width, attachment->width);
7054 framebuffer->height = MIN2(framebuffer->height, attachment->height);
7055 framebuffer->layers = MIN2(framebuffer->layers, attachment->layerCount);
7056 }
7057 } else {
7058 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
7059 VkImageView _iview = pCreateInfo->pAttachments[i];
7060 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
7061 framebuffer->attachments[i] = iview;
7062 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
7063 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
7064 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
7065 }
7066 }
7067
7068 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
7069 return VK_SUCCESS;
7070 }
7071
7072 void radv_DestroyFramebuffer(
7073 VkDevice _device,
7074 VkFramebuffer _fb,
7075 const VkAllocationCallbacks* pAllocator)
7076 {
7077 RADV_FROM_HANDLE(radv_device, device, _device);
7078 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
7079
7080 if (!fb)
7081 return;
7082 vk_object_base_finish(&fb->base);
7083 vk_free2(&device->vk.alloc, pAllocator, fb);
7084 }
7085
7086 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
7087 {
7088 switch (address_mode) {
7089 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
7090 return V_008F30_SQ_TEX_WRAP;
7091 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
7092 return V_008F30_SQ_TEX_MIRROR;
7093 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
7094 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
7095 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
7096 return V_008F30_SQ_TEX_CLAMP_BORDER;
7097 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
7098 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
7099 default:
7100 unreachable("illegal tex wrap mode");
7101 break;
7102 }
7103 }
7104
7105 static unsigned
7106 radv_tex_compare(VkCompareOp op)
7107 {
7108 switch (op) {
7109 case VK_COMPARE_OP_NEVER:
7110 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
7111 case VK_COMPARE_OP_LESS:
7112 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
7113 case VK_COMPARE_OP_EQUAL:
7114 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
7115 case VK_COMPARE_OP_LESS_OR_EQUAL:
7116 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
7117 case VK_COMPARE_OP_GREATER:
7118 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
7119 case VK_COMPARE_OP_NOT_EQUAL:
7120 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
7121 case VK_COMPARE_OP_GREATER_OR_EQUAL:
7122 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
7123 case VK_COMPARE_OP_ALWAYS:
7124 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
7125 default:
7126 unreachable("illegal compare mode");
7127 break;
7128 }
7129 }
7130
7131 static unsigned
7132 radv_tex_filter(VkFilter filter, unsigned max_ansio)
7133 {
7134 switch (filter) {
7135 case VK_FILTER_NEAREST:
7136 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
7137 V_008F38_SQ_TEX_XY_FILTER_POINT);
7138 case VK_FILTER_LINEAR:
7139 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
7140 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
7141 case VK_FILTER_CUBIC_IMG:
7142 default:
7143 fprintf(stderr, "illegal texture filter");
7144 return 0;
7145 }
7146 }
7147
7148 static unsigned
7149 radv_tex_mipfilter(VkSamplerMipmapMode mode)
7150 {
7151 switch (mode) {
7152 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
7153 return V_008F38_SQ_TEX_Z_FILTER_POINT;
7154 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
7155 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
7156 default:
7157 return V_008F38_SQ_TEX_Z_FILTER_NONE;
7158 }
7159 }
7160
7161 static unsigned
7162 radv_tex_bordercolor(VkBorderColor bcolor)
7163 {
7164 switch (bcolor) {
7165 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
7166 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
7167 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
7168 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
7169 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
7170 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
7171 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
7172 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
7173 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
7174 case VK_BORDER_COLOR_FLOAT_CUSTOM_EXT:
7175 case VK_BORDER_COLOR_INT_CUSTOM_EXT:
7176 return V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
7177 default:
7178 break;
7179 }
7180 return 0;
7181 }
7182
7183 static unsigned
7184 radv_tex_aniso_filter(unsigned filter)
7185 {
7186 if (filter < 2)
7187 return 0;
7188 if (filter < 4)
7189 return 1;
7190 if (filter < 8)
7191 return 2;
7192 if (filter < 16)
7193 return 3;
7194 return 4;
7195 }
7196
7197 static unsigned
7198 radv_tex_filter_mode(VkSamplerReductionMode mode)
7199 {
7200 switch (mode) {
7201 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
7202 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
7203 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
7204 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
7205 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
7206 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
7207 default:
7208 break;
7209 }
7210 return 0;
7211 }
7212
7213 static uint32_t
7214 radv_get_max_anisotropy(struct radv_device *device,
7215 const VkSamplerCreateInfo *pCreateInfo)
7216 {
7217 if (device->force_aniso >= 0)
7218 return device->force_aniso;
7219
7220 if (pCreateInfo->anisotropyEnable &&
7221 pCreateInfo->maxAnisotropy > 1.0f)
7222 return (uint32_t)pCreateInfo->maxAnisotropy;
7223
7224 return 0;
7225 }
7226
7227 static inline int S_FIXED(float value, unsigned frac_bits)
7228 {
7229 return value * (1 << frac_bits);
7230 }
7231
7232 static uint32_t radv_register_border_color(struct radv_device *device,
7233 VkClearColorValue value)
7234 {
7235 uint32_t slot;
7236
7237 pthread_mutex_lock(&device->border_color_data.mutex);
7238
7239 for (slot = 0; slot < RADV_BORDER_COLOR_COUNT; slot++) {
7240 if (!device->border_color_data.used[slot]) {
7241 /* Copy to the GPU wrt endian-ness. */
7242 util_memcpy_cpu_to_le32(&device->border_color_data.colors_gpu_ptr[slot],
7243 &value,
7244 sizeof(VkClearColorValue));
7245
7246 device->border_color_data.used[slot] = true;
7247 break;
7248 }
7249 }
7250
7251 pthread_mutex_unlock(&device->border_color_data.mutex);
7252
7253 return slot;
7254 }
7255
7256 static void radv_unregister_border_color(struct radv_device *device,
7257 uint32_t slot)
7258 {
7259 pthread_mutex_lock(&device->border_color_data.mutex);
7260
7261 device->border_color_data.used[slot] = false;
7262
7263 pthread_mutex_unlock(&device->border_color_data.mutex);
7264 }
7265
7266 static void
7267 radv_init_sampler(struct radv_device *device,
7268 struct radv_sampler *sampler,
7269 const VkSamplerCreateInfo *pCreateInfo)
7270 {
7271 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
7272 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
7273 bool compat_mode = device->physical_device->rad_info.chip_class == GFX8 ||
7274 device->physical_device->rad_info.chip_class == GFX9;
7275 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
7276 unsigned depth_compare_func = V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
7277 bool trunc_coord = pCreateInfo->minFilter == VK_FILTER_NEAREST && pCreateInfo->magFilter == VK_FILTER_NEAREST;
7278 bool uses_border_color = pCreateInfo->addressModeU == VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER ||
7279 pCreateInfo->addressModeV == VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER ||
7280 pCreateInfo->addressModeW == VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER;
7281 VkBorderColor border_color = uses_border_color ? pCreateInfo->borderColor : VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK;
7282 uint32_t border_color_ptr;
7283
7284 const struct VkSamplerReductionModeCreateInfo *sampler_reduction =
7285 vk_find_struct_const(pCreateInfo->pNext,
7286 SAMPLER_REDUCTION_MODE_CREATE_INFO);
7287 if (sampler_reduction)
7288 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
7289
7290 if (pCreateInfo->compareEnable)
7291 depth_compare_func = radv_tex_compare(pCreateInfo->compareOp);
7292
7293 sampler->border_color_slot = RADV_BORDER_COLOR_COUNT;
7294
7295 if (border_color == VK_BORDER_COLOR_FLOAT_CUSTOM_EXT || border_color == VK_BORDER_COLOR_INT_CUSTOM_EXT) {
7296 const VkSamplerCustomBorderColorCreateInfoEXT *custom_border_color =
7297 vk_find_struct_const(pCreateInfo->pNext,
7298 SAMPLER_CUSTOM_BORDER_COLOR_CREATE_INFO_EXT);
7299
7300 assert(custom_border_color);
7301
7302 sampler->border_color_slot =
7303 radv_register_border_color(device, custom_border_color->customBorderColor);
7304
7305 /* Did we fail to find a slot? */
7306 if (sampler->border_color_slot == RADV_BORDER_COLOR_COUNT) {
7307 fprintf(stderr, "WARNING: no free border color slots, defaulting to TRANS_BLACK.\n");
7308 border_color = VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK;
7309 }
7310 }
7311
7312 /* If we don't have a custom color, set the ptr to 0 */
7313 border_color_ptr = sampler->border_color_slot != RADV_BORDER_COLOR_COUNT
7314 ? sampler->border_color_slot
7315 : 0;
7316
7317 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
7318 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
7319 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
7320 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
7321 S_008F30_DEPTH_COMPARE_FUNC(depth_compare_func) |
7322 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
7323 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
7324 S_008F30_ANISO_BIAS(max_aniso_ratio) |
7325 S_008F30_DISABLE_CUBE_WRAP(0) |
7326 S_008F30_COMPAT_MODE(compat_mode) |
7327 S_008F30_FILTER_MODE(filter_mode) |
7328 S_008F30_TRUNC_COORD(trunc_coord));
7329 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
7330 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
7331 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
7332 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
7333 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
7334 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
7335 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
7336 S_008F38_MIP_POINT_PRECLAMP(0));
7337 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(border_color_ptr) |
7338 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(border_color)));
7339
7340 if (device->physical_device->rad_info.chip_class >= GFX10) {
7341 sampler->state[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
7342 } else {
7343 sampler->state[2] |=
7344 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) |
7345 S_008F38_FILTER_PREC_FIX(1) |
7346 S_008F38_ANISO_OVERRIDE_GFX6(device->physical_device->rad_info.chip_class >= GFX8);
7347 }
7348 }
7349
7350 VkResult radv_CreateSampler(
7351 VkDevice _device,
7352 const VkSamplerCreateInfo* pCreateInfo,
7353 const VkAllocationCallbacks* pAllocator,
7354 VkSampler* pSampler)
7355 {
7356 RADV_FROM_HANDLE(radv_device, device, _device);
7357 struct radv_sampler *sampler;
7358
7359 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
7360 vk_find_struct_const(pCreateInfo->pNext,
7361 SAMPLER_YCBCR_CONVERSION_INFO);
7362
7363 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
7364
7365 sampler = vk_alloc2(&device->vk.alloc, pAllocator, sizeof(*sampler), 8,
7366 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
7367 if (!sampler)
7368 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
7369
7370 vk_object_base_init(&device->vk, &sampler->base,
7371 VK_OBJECT_TYPE_SAMPLER);
7372
7373 radv_init_sampler(device, sampler, pCreateInfo);
7374
7375 sampler->ycbcr_sampler = ycbcr_conversion ? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion): NULL;
7376 *pSampler = radv_sampler_to_handle(sampler);
7377
7378 return VK_SUCCESS;
7379 }
7380
7381 void radv_DestroySampler(
7382 VkDevice _device,
7383 VkSampler _sampler,
7384 const VkAllocationCallbacks* pAllocator)
7385 {
7386 RADV_FROM_HANDLE(radv_device, device, _device);
7387 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
7388
7389 if (!sampler)
7390 return;
7391
7392 if (sampler->border_color_slot != RADV_BORDER_COLOR_COUNT)
7393 radv_unregister_border_color(device, sampler->border_color_slot);
7394
7395 vk_object_base_finish(&sampler->base);
7396 vk_free2(&device->vk.alloc, pAllocator, sampler);
7397 }
7398
7399 /* vk_icd.h does not declare this function, so we declare it here to
7400 * suppress Wmissing-prototypes.
7401 */
7402 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
7403 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
7404
7405 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
7406 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
7407 {
7408 /* For the full details on loader interface versioning, see
7409 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
7410 * What follows is a condensed summary, to help you navigate the large and
7411 * confusing official doc.
7412 *
7413 * - Loader interface v0 is incompatible with later versions. We don't
7414 * support it.
7415 *
7416 * - In loader interface v1:
7417 * - The first ICD entrypoint called by the loader is
7418 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
7419 * entrypoint.
7420 * - The ICD must statically expose no other Vulkan symbol unless it is
7421 * linked with -Bsymbolic.
7422 * - Each dispatchable Vulkan handle created by the ICD must be
7423 * a pointer to a struct whose first member is VK_LOADER_DATA. The
7424 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
7425 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
7426 * vkDestroySurfaceKHR(). The ICD must be capable of working with
7427 * such loader-managed surfaces.
7428 *
7429 * - Loader interface v2 differs from v1 in:
7430 * - The first ICD entrypoint called by the loader is
7431 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
7432 * statically expose this entrypoint.
7433 *
7434 * - Loader interface v3 differs from v2 in:
7435 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
7436 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
7437 * because the loader no longer does so.
7438 */
7439 *pSupportedVersion = MIN2(*pSupportedVersion, 4u);
7440 return VK_SUCCESS;
7441 }
7442
7443 VkResult radv_GetMemoryFdKHR(VkDevice _device,
7444 const VkMemoryGetFdInfoKHR *pGetFdInfo,
7445 int *pFD)
7446 {
7447 RADV_FROM_HANDLE(radv_device, device, _device);
7448 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
7449
7450 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
7451
7452 /* At the moment, we support only the below handle types. */
7453 assert(pGetFdInfo->handleType ==
7454 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
7455 pGetFdInfo->handleType ==
7456 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
7457
7458 bool ret = radv_get_memory_fd(device, memory, pFD);
7459 if (ret == false)
7460 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
7461 return VK_SUCCESS;
7462 }
7463
7464 static uint32_t radv_compute_valid_memory_types_attempt(struct radv_physical_device *dev,
7465 enum radeon_bo_domain domains,
7466 enum radeon_bo_flag flags,
7467 enum radeon_bo_flag ignore_flags)
7468 {
7469 /* Don't count GTT/CPU as relevant:
7470 *
7471 * - We're not fully consistent between the two.
7472 * - Sometimes VRAM gets VRAM|GTT.
7473 */
7474 const enum radeon_bo_domain relevant_domains = RADEON_DOMAIN_VRAM |
7475 RADEON_DOMAIN_GDS |
7476 RADEON_DOMAIN_OA;
7477 uint32_t bits = 0;
7478 for (unsigned i = 0; i < dev->memory_properties.memoryTypeCount; ++i) {
7479 if ((domains & relevant_domains) != (dev->memory_domains[i] & relevant_domains))
7480 continue;
7481
7482 if ((flags & ~ignore_flags) != (dev->memory_flags[i] & ~ignore_flags))
7483 continue;
7484
7485 bits |= 1u << i;
7486 }
7487
7488 return bits;
7489 }
7490
7491 static uint32_t radv_compute_valid_memory_types(struct radv_physical_device *dev,
7492 enum radeon_bo_domain domains,
7493 enum radeon_bo_flag flags)
7494 {
7495 enum radeon_bo_flag ignore_flags = ~(RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_GTT_WC);
7496 uint32_t bits = radv_compute_valid_memory_types_attempt(dev, domains, flags, ignore_flags);
7497
7498 if (!bits) {
7499 ignore_flags |= RADEON_FLAG_NO_CPU_ACCESS;
7500 bits = radv_compute_valid_memory_types_attempt(dev, domains, flags, ignore_flags);
7501 }
7502
7503 return bits;
7504 }
7505 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
7506 VkExternalMemoryHandleTypeFlagBits handleType,
7507 int fd,
7508 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
7509 {
7510 RADV_FROM_HANDLE(radv_device, device, _device);
7511
7512 switch (handleType) {
7513 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT: {
7514 enum radeon_bo_domain domains;
7515 enum radeon_bo_flag flags;
7516 if (!device->ws->buffer_get_flags_from_fd(device->ws, fd, &domains, &flags))
7517 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7518
7519 pMemoryFdProperties->memoryTypeBits = radv_compute_valid_memory_types(device->physical_device, domains, flags);
7520 return VK_SUCCESS;
7521 }
7522 default:
7523 /* The valid usage section for this function says:
7524 *
7525 * "handleType must not be one of the handle types defined as
7526 * opaque."
7527 *
7528 * So opaque handle types fall into the default "unsupported" case.
7529 */
7530 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7531 }
7532 }
7533
7534 static VkResult radv_import_opaque_fd(struct radv_device *device,
7535 int fd,
7536 uint32_t *syncobj)
7537 {
7538 uint32_t syncobj_handle = 0;
7539 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
7540 if (ret != 0)
7541 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7542
7543 if (*syncobj)
7544 device->ws->destroy_syncobj(device->ws, *syncobj);
7545
7546 *syncobj = syncobj_handle;
7547 close(fd);
7548
7549 return VK_SUCCESS;
7550 }
7551
7552 static VkResult radv_import_sync_fd(struct radv_device *device,
7553 int fd,
7554 uint32_t *syncobj)
7555 {
7556 /* If we create a syncobj we do it locally so that if we have an error, we don't
7557 * leave a syncobj in an undetermined state in the fence. */
7558 uint32_t syncobj_handle = *syncobj;
7559 if (!syncobj_handle) {
7560 bool create_signaled = fd == -1 ? true : false;
7561
7562 int ret = device->ws->create_syncobj(device->ws, create_signaled,
7563 &syncobj_handle);
7564 if (ret) {
7565 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
7566 }
7567 } else {
7568 if (fd == -1)
7569 device->ws->signal_syncobj(device->ws, syncobj_handle, 0);
7570 }
7571
7572 if (fd != -1) {
7573 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
7574 if (ret)
7575 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7576 close(fd);
7577 }
7578
7579 *syncobj = syncobj_handle;
7580
7581 return VK_SUCCESS;
7582 }
7583
7584 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
7585 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
7586 {
7587 RADV_FROM_HANDLE(radv_device, device, _device);
7588 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
7589 VkResult result;
7590 struct radv_semaphore_part *dst = NULL;
7591 bool timeline = sem->permanent.kind == RADV_SEMAPHORE_TIMELINE_SYNCOBJ;
7592
7593 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
7594 assert(!timeline);
7595 dst = &sem->temporary;
7596 } else {
7597 dst = &sem->permanent;
7598 }
7599
7600 uint32_t syncobj = (dst->kind == RADV_SEMAPHORE_SYNCOBJ ||
7601 dst->kind == RADV_SEMAPHORE_TIMELINE_SYNCOBJ) ? dst->syncobj : 0;
7602
7603 switch(pImportSemaphoreFdInfo->handleType) {
7604 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
7605 result = radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, &syncobj);
7606 break;
7607 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
7608 assert(!timeline);
7609 result = radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, &syncobj);
7610 break;
7611 default:
7612 unreachable("Unhandled semaphore handle type");
7613 }
7614
7615 if (result == VK_SUCCESS) {
7616 dst->syncobj = syncobj;
7617 dst->kind = RADV_SEMAPHORE_SYNCOBJ;
7618 if (timeline) {
7619 dst->kind = RADV_SEMAPHORE_TIMELINE_SYNCOBJ;
7620 dst->timeline_syncobj.max_point = 0;
7621 }
7622 }
7623
7624 return result;
7625 }
7626
7627 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
7628 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
7629 int *pFd)
7630 {
7631 RADV_FROM_HANDLE(radv_device, device, _device);
7632 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
7633 int ret;
7634 uint32_t syncobj_handle;
7635
7636 if (sem->temporary.kind != RADV_SEMAPHORE_NONE) {
7637 assert(sem->temporary.kind == RADV_SEMAPHORE_SYNCOBJ ||
7638 sem->temporary.kind == RADV_SEMAPHORE_TIMELINE_SYNCOBJ);
7639 syncobj_handle = sem->temporary.syncobj;
7640 } else {
7641 assert(sem->permanent.kind == RADV_SEMAPHORE_SYNCOBJ ||
7642 sem->permanent.kind == RADV_SEMAPHORE_TIMELINE_SYNCOBJ);
7643 syncobj_handle = sem->permanent.syncobj;
7644 }
7645
7646 switch(pGetFdInfo->handleType) {
7647 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
7648 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
7649 if (ret)
7650 return vk_error(device->instance, VK_ERROR_TOO_MANY_OBJECTS);
7651 break;
7652 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
7653 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
7654 if (ret)
7655 return vk_error(device->instance, VK_ERROR_TOO_MANY_OBJECTS);
7656
7657 if (sem->temporary.kind != RADV_SEMAPHORE_NONE) {
7658 radv_destroy_semaphore_part(device, &sem->temporary);
7659 } else {
7660 device->ws->reset_syncobj(device->ws, syncobj_handle);
7661 }
7662 break;
7663 default:
7664 unreachable("Unhandled semaphore handle type");
7665 }
7666
7667 return VK_SUCCESS;
7668 }
7669
7670 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
7671 VkPhysicalDevice physicalDevice,
7672 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
7673 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
7674 {
7675 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
7676 VkSemaphoreTypeKHR type = radv_get_semaphore_type(pExternalSemaphoreInfo->pNext, NULL);
7677
7678 if (type == VK_SEMAPHORE_TYPE_TIMELINE && pdevice->rad_info.has_timeline_syncobj &&
7679 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
7680 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
7681 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
7682 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
7683 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
7684 } else if (type == VK_SEMAPHORE_TYPE_TIMELINE) {
7685 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
7686 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
7687 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
7688
7689 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
7690 } else if (pdevice->rad_info.has_syncobj_wait_for_submit &&
7691 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
7692 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
7693 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
7694 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
7695 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
7696 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
7697 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
7698 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
7699 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
7700 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
7701 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
7702 } else {
7703 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
7704 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
7705 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
7706 }
7707 }
7708
7709 VkResult radv_ImportFenceFdKHR(VkDevice _device,
7710 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
7711 {
7712 RADV_FROM_HANDLE(radv_device, device, _device);
7713 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
7714 struct radv_fence_part *dst = NULL;
7715 VkResult result;
7716
7717 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
7718 dst = &fence->temporary;
7719 } else {
7720 dst = &fence->permanent;
7721 }
7722
7723 uint32_t syncobj = dst->kind == RADV_FENCE_SYNCOBJ ? dst->syncobj : 0;
7724
7725 switch(pImportFenceFdInfo->handleType) {
7726 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
7727 result = radv_import_opaque_fd(device, pImportFenceFdInfo->fd, &syncobj);
7728 break;
7729 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
7730 result = radv_import_sync_fd(device, pImportFenceFdInfo->fd, &syncobj);
7731 break;
7732 default:
7733 unreachable("Unhandled fence handle type");
7734 }
7735
7736 if (result == VK_SUCCESS) {
7737 dst->syncobj = syncobj;
7738 dst->kind = RADV_FENCE_SYNCOBJ;
7739 }
7740
7741 return result;
7742 }
7743
7744 VkResult radv_GetFenceFdKHR(VkDevice _device,
7745 const VkFenceGetFdInfoKHR *pGetFdInfo,
7746 int *pFd)
7747 {
7748 RADV_FROM_HANDLE(radv_device, device, _device);
7749 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
7750 int ret;
7751
7752 struct radv_fence_part *part =
7753 fence->temporary.kind != RADV_FENCE_NONE ?
7754 &fence->temporary : &fence->permanent;
7755
7756 switch(pGetFdInfo->handleType) {
7757 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
7758 ret = device->ws->export_syncobj(device->ws, part->syncobj, pFd);
7759 if (ret)
7760 return vk_error(device->instance, VK_ERROR_TOO_MANY_OBJECTS);
7761 break;
7762 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
7763 ret = device->ws->export_syncobj_to_sync_file(device->ws,
7764 part->syncobj, pFd);
7765 if (ret)
7766 return vk_error(device->instance, VK_ERROR_TOO_MANY_OBJECTS);
7767
7768 if (part == &fence->temporary) {
7769 radv_destroy_fence_part(device, part);
7770 } else {
7771 device->ws->reset_syncobj(device->ws, part->syncobj);
7772 }
7773 break;
7774 default:
7775 unreachable("Unhandled fence handle type");
7776 }
7777
7778 return VK_SUCCESS;
7779 }
7780
7781 void radv_GetPhysicalDeviceExternalFenceProperties(
7782 VkPhysicalDevice physicalDevice,
7783 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
7784 VkExternalFenceProperties *pExternalFenceProperties)
7785 {
7786 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
7787
7788 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
7789 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
7790 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
7791 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
7792 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
7793 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
7794 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
7795 } else {
7796 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
7797 pExternalFenceProperties->compatibleHandleTypes = 0;
7798 pExternalFenceProperties->externalFenceFeatures = 0;
7799 }
7800 }
7801
7802 VkResult
7803 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
7804 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
7805 const VkAllocationCallbacks* pAllocator,
7806 VkDebugReportCallbackEXT* pCallback)
7807 {
7808 RADV_FROM_HANDLE(radv_instance, instance, _instance);
7809 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
7810 pCreateInfo, pAllocator, &instance->alloc,
7811 pCallback);
7812 }
7813
7814 void
7815 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
7816 VkDebugReportCallbackEXT _callback,
7817 const VkAllocationCallbacks* pAllocator)
7818 {
7819 RADV_FROM_HANDLE(radv_instance, instance, _instance);
7820 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
7821 _callback, pAllocator, &instance->alloc);
7822 }
7823
7824 void
7825 radv_DebugReportMessageEXT(VkInstance _instance,
7826 VkDebugReportFlagsEXT flags,
7827 VkDebugReportObjectTypeEXT objectType,
7828 uint64_t object,
7829 size_t location,
7830 int32_t messageCode,
7831 const char* pLayerPrefix,
7832 const char* pMessage)
7833 {
7834 RADV_FROM_HANDLE(radv_instance, instance, _instance);
7835 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
7836 object, location, messageCode, pLayerPrefix, pMessage);
7837 }
7838
7839 void
7840 radv_GetDeviceGroupPeerMemoryFeatures(
7841 VkDevice device,
7842 uint32_t heapIndex,
7843 uint32_t localDeviceIndex,
7844 uint32_t remoteDeviceIndex,
7845 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
7846 {
7847 assert(localDeviceIndex == remoteDeviceIndex);
7848
7849 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
7850 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
7851 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
7852 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
7853 }
7854
7855 static const VkTimeDomainEXT radv_time_domains[] = {
7856 VK_TIME_DOMAIN_DEVICE_EXT,
7857 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
7858 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
7859 };
7860
7861 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
7862 VkPhysicalDevice physicalDevice,
7863 uint32_t *pTimeDomainCount,
7864 VkTimeDomainEXT *pTimeDomains)
7865 {
7866 int d;
7867 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
7868
7869 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
7870 vk_outarray_append(&out, i) {
7871 *i = radv_time_domains[d];
7872 }
7873 }
7874
7875 return vk_outarray_status(&out);
7876 }
7877
7878 static uint64_t
7879 radv_clock_gettime(clockid_t clock_id)
7880 {
7881 struct timespec current;
7882 int ret;
7883
7884 ret = clock_gettime(clock_id, &current);
7885 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
7886 ret = clock_gettime(CLOCK_MONOTONIC, &current);
7887 if (ret < 0)
7888 return 0;
7889
7890 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
7891 }
7892
7893 VkResult radv_GetCalibratedTimestampsEXT(
7894 VkDevice _device,
7895 uint32_t timestampCount,
7896 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
7897 uint64_t *pTimestamps,
7898 uint64_t *pMaxDeviation)
7899 {
7900 RADV_FROM_HANDLE(radv_device, device, _device);
7901 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
7902 int d;
7903 uint64_t begin, end;
7904 uint64_t max_clock_period = 0;
7905
7906 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
7907
7908 for (d = 0; d < timestampCount; d++) {
7909 switch (pTimestampInfos[d].timeDomain) {
7910 case VK_TIME_DOMAIN_DEVICE_EXT:
7911 pTimestamps[d] = device->ws->query_value(device->ws,
7912 RADEON_TIMESTAMP);
7913 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
7914 max_clock_period = MAX2(max_clock_period, device_period);
7915 break;
7916 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
7917 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
7918 max_clock_period = MAX2(max_clock_period, 1);
7919 break;
7920
7921 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
7922 pTimestamps[d] = begin;
7923 break;
7924 default:
7925 pTimestamps[d] = 0;
7926 break;
7927 }
7928 }
7929
7930 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
7931
7932 /*
7933 * The maximum deviation is the sum of the interval over which we
7934 * perform the sampling and the maximum period of any sampled
7935 * clock. That's because the maximum skew between any two sampled
7936 * clock edges is when the sampled clock with the largest period is
7937 * sampled at the end of that period but right at the beginning of the
7938 * sampling interval and some other clock is sampled right at the
7939 * begining of its sampling period and right at the end of the
7940 * sampling interval. Let's assume the GPU has the longest clock
7941 * period and that the application is sampling GPU and monotonic:
7942 *
7943 * s e
7944 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
7945 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
7946 *
7947 * g
7948 * 0 1 2 3
7949 * GPU -----_____-----_____-----_____-----_____
7950 *
7951 * m
7952 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
7953 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
7954 *
7955 * Interval <----------------->
7956 * Deviation <-------------------------->
7957 *
7958 * s = read(raw) 2
7959 * g = read(GPU) 1
7960 * m = read(monotonic) 2
7961 * e = read(raw) b
7962 *
7963 * We round the sample interval up by one tick to cover sampling error
7964 * in the interval clock
7965 */
7966
7967 uint64_t sample_interval = end - begin + 1;
7968
7969 *pMaxDeviation = sample_interval + max_clock_period;
7970
7971 return VK_SUCCESS;
7972 }
7973
7974 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
7975 VkPhysicalDevice physicalDevice,
7976 VkSampleCountFlagBits samples,
7977 VkMultisamplePropertiesEXT* pMultisampleProperties)
7978 {
7979 if (samples & (VK_SAMPLE_COUNT_2_BIT |
7980 VK_SAMPLE_COUNT_4_BIT |
7981 VK_SAMPLE_COUNT_8_BIT)) {
7982 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 2, 2 };
7983 } else {
7984 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 0, 0 };
7985 }
7986 }
7987
7988 VkResult radv_CreatePrivateDataSlotEXT(
7989 VkDevice _device,
7990 const VkPrivateDataSlotCreateInfoEXT* pCreateInfo,
7991 const VkAllocationCallbacks* pAllocator,
7992 VkPrivateDataSlotEXT* pPrivateDataSlot)
7993 {
7994 RADV_FROM_HANDLE(radv_device, device, _device);
7995 return vk_private_data_slot_create(&device->vk, pCreateInfo, pAllocator,
7996 pPrivateDataSlot);
7997 }
7998
7999 void radv_DestroyPrivateDataSlotEXT(
8000 VkDevice _device,
8001 VkPrivateDataSlotEXT privateDataSlot,
8002 const VkAllocationCallbacks* pAllocator)
8003 {
8004 RADV_FROM_HANDLE(radv_device, device, _device);
8005 vk_private_data_slot_destroy(&device->vk, privateDataSlot, pAllocator);
8006 }
8007
8008 VkResult radv_SetPrivateDataEXT(
8009 VkDevice _device,
8010 VkObjectType objectType,
8011 uint64_t objectHandle,
8012 VkPrivateDataSlotEXT privateDataSlot,
8013 uint64_t data)
8014 {
8015 RADV_FROM_HANDLE(radv_device, device, _device);
8016 return vk_object_base_set_private_data(&device->vk, objectType,
8017 objectHandle, privateDataSlot,
8018 data);
8019 }
8020
8021 void radv_GetPrivateDataEXT(
8022 VkDevice _device,
8023 VkObjectType objectType,
8024 uint64_t objectHandle,
8025 VkPrivateDataSlotEXT privateDataSlot,
8026 uint64_t* pData)
8027 {
8028 RADV_FROM_HANDLE(radv_device, device, _device);
8029 vk_object_base_get_private_data(&device->vk, objectType, objectHandle,
8030 privateDataSlot, pData);
8031 }