projects / mesa.git / blob
? search:


6171408ced15b55ffbefbb120f2de3b8e7fcd758
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "amdgpu_id.h"
43 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
44 #include "ac_llvm_util.h"
45 #include "vk_format.h"
46 #include "sid.h"
47 #include "gfx9d.h"
48 #include "util/debug.h"
49
50 static int
51 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
52 {
53 uint32_t mesa_timestamp, llvm_timestamp;
54 uint16_t f = family;
55 memset(uuid, 0, VK_UUID_SIZE);
56 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
57 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
58 return -1;
59
60 memcpy(uuid, &mesa_timestamp, 4);
61 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
62 memcpy((char*)uuid + 8, &f, 2);
63 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
64 return 0;
65 }
66
67 static void
68 radv_get_driver_uuid(void *uuid)
69 {
70 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
71 }
72
73 static void
74 radv_get_device_uuid(struct radeon_info *info, void *uuid)
75 {
76 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
77 }
78
79 static const VkExtensionProperties instance_extensions[] = {
80 {
81 .extensionName = VK_KHR_SURFACE_EXTENSION_NAME,
82 .specVersion = 25,
83 },
84 #ifdef VK_USE_PLATFORM_XCB_KHR
85 {
86 .extensionName = VK_KHR_XCB_SURFACE_EXTENSION_NAME,
87 .specVersion = 6,
88 },
89 #endif
90 #ifdef VK_USE_PLATFORM_XLIB_KHR
91 {
92 .extensionName = VK_KHR_XLIB_SURFACE_EXTENSION_NAME,
93 .specVersion = 6,
94 },
95 #endif
96 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
97 {
98 .extensionName = VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME,
99 .specVersion = 6,
100 },
101 #endif
102 {
103 .extensionName = VK_KHR_GET_PHYSICAL_DEVICE_PROPERTIES_2_EXTENSION_NAME,
104 .specVersion = 1,
105 },
106 {
107 .extensionName = VK_KHR_EXTERNAL_MEMORY_CAPABILITIES_EXTENSION_NAME,
108 .specVersion = 1,
109 },
110 {
111 .extensionName = VK_KHR_EXTERNAL_SEMAPHORE_CAPABILITIES_EXTENSION_NAME,
112 .specVersion = 1,
113 },
114 };
115
116 static const VkExtensionProperties common_device_extensions[] = {
117 {
118 .extensionName = VK_KHR_DESCRIPTOR_UPDATE_TEMPLATE_EXTENSION_NAME,
119 .specVersion = 1,
120 },
121 {
122 .extensionName = VK_KHR_INCREMENTAL_PRESENT_EXTENSION_NAME,
123 .specVersion = 1,
124 },
125 {
126 .extensionName = VK_KHR_MAINTENANCE1_EXTENSION_NAME,
127 .specVersion = 1,
128 },
129 {
130 .extensionName = VK_KHR_PUSH_DESCRIPTOR_EXTENSION_NAME,
131 .specVersion = 1,
132 },
133 {
134 .extensionName = VK_KHR_SAMPLER_MIRROR_CLAMP_TO_EDGE_EXTENSION_NAME,
135 .specVersion = 1,
136 },
137 {
138 .extensionName = VK_KHR_SWAPCHAIN_EXTENSION_NAME,
139 .specVersion = 68,
140 },
141 {
142 .extensionName = VK_AMD_DRAW_INDIRECT_COUNT_EXTENSION_NAME,
143 .specVersion = 1,
144 },
145 {
146 .extensionName = VK_KHR_SHADER_DRAW_PARAMETERS_EXTENSION_NAME,
147 .specVersion = 1,
148 },
149 {
150 .extensionName = VK_KHR_GET_MEMORY_REQUIREMENTS_2_EXTENSION_NAME,
151 .specVersion = 1,
152 },
153 {
154 .extensionName = VK_KHR_DEDICATED_ALLOCATION_EXTENSION_NAME,
155 .specVersion = 1,
156 },
157 {
158 .extensionName = VK_KHR_EXTERNAL_MEMORY_EXTENSION_NAME,
159 .specVersion = 1,
160 },
161 {
162 .extensionName = VK_KHR_EXTERNAL_MEMORY_FD_EXTENSION_NAME,
163 .specVersion = 1,
164 },
165 {
166 .extensionName = VK_KHR_STORAGE_BUFFER_STORAGE_CLASS_EXTENSION_NAME,
167 .specVersion = 1,
168 },
169 {
170 .extensionName = VK_KHR_VARIABLE_POINTERS_EXTENSION_NAME,
171 .specVersion = 1,
172 },
173 {
174 .extensionName = VK_KHR_IMAGE_FORMAT_LIST_EXTENSION_NAME,
175 .specVersion = 1,
176 },
177 {
178 .extensionName = VK_KHR_BIND_MEMORY_2_EXTENSION_NAME,
179 .specVersion = 1,
180 },
181 };
182
183 static const VkExtensionProperties rasterization_order_extension[] ={
184 {
185 .extensionName = VK_AMD_RASTERIZATION_ORDER_EXTENSION_NAME,
186 .specVersion = 1,
187 },
188 };
189
190 static const VkExtensionProperties ext_sema_device_extensions[] = {
191 {
192 .extensionName = VK_KHR_EXTERNAL_SEMAPHORE_EXTENSION_NAME,
193 .specVersion = 1,
194 },
195 {
196 .extensionName = VK_KHR_EXTERNAL_SEMAPHORE_FD_EXTENSION_NAME,
197 .specVersion = 1,
198 },
199 {
200 .extensionName = VK_KHX_MULTIVIEW_EXTENSION_NAME,
201 .specVersion = 1,
202 },
203 };
204
205 static VkResult
206 radv_extensions_register(struct radv_instance *instance,
207 struct radv_extensions *extensions,
208 const VkExtensionProperties *new_ext,
209 uint32_t num_ext)
210 {
211 size_t new_size;
212 VkExtensionProperties *new_ptr;
213
214 assert(new_ext && num_ext > 0);
215
216 if (!new_ext)
217 return VK_ERROR_INITIALIZATION_FAILED;
218
219 new_size = (extensions->num_ext + num_ext) * sizeof(VkExtensionProperties);
220 new_ptr = vk_realloc(&instance->alloc, extensions->ext_array,
221 new_size, 8, VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
222
223 /* Old array continues to be valid, update nothing */
224 if (!new_ptr)
225 return VK_ERROR_OUT_OF_HOST_MEMORY;
226
227 memcpy(&new_ptr[extensions->num_ext], new_ext,
228 num_ext * sizeof(VkExtensionProperties));
229 extensions->ext_array = new_ptr;
230 extensions->num_ext += num_ext;
231
232 return VK_SUCCESS;
233 }
234
235 static void
236 radv_extensions_finish(struct radv_instance *instance,
237 struct radv_extensions *extensions)
238 {
239 assert(extensions);
240
241 if (!extensions)
242 radv_loge("Attemted to free invalid extension struct\n");
243
244 if (extensions->ext_array)
245 vk_free(&instance->alloc, extensions->ext_array);
246 }
247
248 static bool
249 is_extension_enabled(const VkExtensionProperties *extensions,
250 size_t num_ext,
251 const char *name)
252 {
253 assert(extensions && name);
254
255 for (uint32_t i = 0; i < num_ext; i++) {
256 if (strcmp(name, extensions[i].extensionName) == 0)
257 return true;
258 }
259
260 return false;
261 }
262
263 static const char *
264 get_chip_name(enum radeon_family family)
265 {
266 switch (family) {
267 case CHIP_TAHITI: return "AMD RADV TAHITI";
268 case CHIP_PITCAIRN: return "AMD RADV PITCAIRN";
269 case CHIP_VERDE: return "AMD RADV CAPE VERDE";
270 case CHIP_OLAND: return "AMD RADV OLAND";
271 case CHIP_HAINAN: return "AMD RADV HAINAN";
272 case CHIP_BONAIRE: return "AMD RADV BONAIRE";
273 case CHIP_KAVERI: return "AMD RADV KAVERI";
274 case CHIP_KABINI: return "AMD RADV KABINI";
275 case CHIP_HAWAII: return "AMD RADV HAWAII";
276 case CHIP_MULLINS: return "AMD RADV MULLINS";
277 case CHIP_TONGA: return "AMD RADV TONGA";
278 case CHIP_ICELAND: return "AMD RADV ICELAND";
279 case CHIP_CARRIZO: return "AMD RADV CARRIZO";
280 case CHIP_FIJI: return "AMD RADV FIJI";
281 case CHIP_POLARIS10: return "AMD RADV POLARIS10";
282 case CHIP_POLARIS11: return "AMD RADV POLARIS11";
283 case CHIP_POLARIS12: return "AMD RADV POLARIS12";
284 case CHIP_STONEY: return "AMD RADV STONEY";
285 case CHIP_VEGA10: return "AMD RADV VEGA";
286 case CHIP_RAVEN: return "AMD RADV RAVEN";
287 default: return "AMD RADV unknown";
288 }
289 }
290
291 static VkResult
292 radv_physical_device_init(struct radv_physical_device *device,
293 struct radv_instance *instance,
294 drmDevicePtr drm_device)
295 {
296 const char *path = drm_device->nodes[DRM_NODE_RENDER];
297 VkResult result;
298 drmVersionPtr version;
299 int fd;
300
301 fd = open(path, O_RDWR | O_CLOEXEC);
302 if (fd < 0)
303 return VK_ERROR_INCOMPATIBLE_DRIVER;
304
305 version = drmGetVersion(fd);
306 if (!version) {
307 close(fd);
308 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
309 "failed to get version %s: %m", path);
310 }
311
312 if (strcmp(version->name, "amdgpu")) {
313 drmFreeVersion(version);
314 close(fd);
315 return VK_ERROR_INCOMPATIBLE_DRIVER;
316 }
317 drmFreeVersion(version);
318
319 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
320 device->instance = instance;
321 assert(strlen(path) < ARRAY_SIZE(device->path));
322 strncpy(device->path, path, ARRAY_SIZE(device->path));
323
324 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
325 instance->perftest_flags);
326 if (!device->ws) {
327 result = VK_ERROR_INCOMPATIBLE_DRIVER;
328 goto fail;
329 }
330
331 device->local_fd = fd;
332 device->ws->query_info(device->ws, &device->rad_info);
333 result = radv_init_wsi(device);
334 if (result != VK_SUCCESS) {
335 device->ws->destroy(device->ws);
336 goto fail;
337 }
338
339 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
340 radv_finish_wsi(device);
341 device->ws->destroy(device->ws);
342 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
343 "cannot generate UUID");
344 goto fail;
345 }
346
347 result = radv_extensions_register(instance,
348 &device->extensions,
349 common_device_extensions,
350 ARRAY_SIZE(common_device_extensions));
351 if (result != VK_SUCCESS)
352 goto fail;
353
354 if (device->rad_info.chip_class >= VI && device->rad_info.max_se >= 2) {
355 result = radv_extensions_register(instance,
356 &device->extensions,
357 rasterization_order_extension,
358 ARRAY_SIZE(rasterization_order_extension));
359 if (result != VK_SUCCESS)
360 goto fail;
361 }
362
363 if (device->rad_info.has_syncobj) {
364 result = radv_extensions_register(instance,
365 &device->extensions,
366 ext_sema_device_extensions,
367 ARRAY_SIZE(ext_sema_device_extensions));
368 if (result != VK_SUCCESS)
369 goto fail;
370 }
371
372 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
373 device->name = get_chip_name(device->rad_info.family);
374
375 radv_get_driver_uuid(&device->device_uuid);
376 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
377
378 if (device->rad_info.family == CHIP_STONEY ||
379 device->rad_info.chip_class >= GFX9) {
380 device->has_rbplus = true;
381 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY;
382 }
383
384 return VK_SUCCESS;
385
386 fail:
387 close(fd);
388 return result;
389 }
390
391 static void
392 radv_physical_device_finish(struct radv_physical_device *device)
393 {
394 radv_extensions_finish(device->instance, &device->extensions);
395 radv_finish_wsi(device);
396 device->ws->destroy(device->ws);
397 close(device->local_fd);
398 }
399
400 static void *
401 default_alloc_func(void *pUserData, size_t size, size_t align,
402 VkSystemAllocationScope allocationScope)
403 {
404 return malloc(size);
405 }
406
407 static void *
408 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
409 size_t align, VkSystemAllocationScope allocationScope)
410 {
411 return realloc(pOriginal, size);
412 }
413
414 static void
415 default_free_func(void *pUserData, void *pMemory)
416 {
417 free(pMemory);
418 }
419
420 static const VkAllocationCallbacks default_alloc = {
421 .pUserData = NULL,
422 .pfnAllocation = default_alloc_func,
423 .pfnReallocation = default_realloc_func,
424 .pfnFree = default_free_func,
425 };
426
427 static const struct debug_control radv_debug_options[] = {
428 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
429 {"nodcc", RADV_DEBUG_NO_DCC},
430 {"shaders", RADV_DEBUG_DUMP_SHADERS},
431 {"nocache", RADV_DEBUG_NO_CACHE},
432 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
433 {"nohiz", RADV_DEBUG_NO_HIZ},
434 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
435 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
436 {"allbos", RADV_DEBUG_ALL_BOS},
437 {"noibs", RADV_DEBUG_NO_IBS},
438 {"spirv", RADV_DEBUG_DUMP_SPIRV},
439 {"vmfaults", RADV_DEBUG_VM_FAULTS},
440 {"zerovram", RADV_DEBUG_ZERO_VRAM},
441 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
442 {NULL, 0}
443 };
444
445 const char *
446 radv_get_debug_option_name(int id)
447 {
448 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
449 return radv_debug_options[id].string;
450 }
451
452 static const struct debug_control radv_perftest_options[] = {
453 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
454 {"sisched", RADV_PERFTEST_SISCHED},
455 {NULL, 0}
456 };
457
458 const char *
459 radv_get_perftest_option_name(int id)
460 {
461 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
462 return radv_perftest_options[id].string;
463 }
464
465 VkResult radv_CreateInstance(
466 const VkInstanceCreateInfo* pCreateInfo,
467 const VkAllocationCallbacks* pAllocator,
468 VkInstance* pInstance)
469 {
470 struct radv_instance *instance;
471
472 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
473
474 uint32_t client_version;
475 if (pCreateInfo->pApplicationInfo &&
476 pCreateInfo->pApplicationInfo->apiVersion != 0) {
477 client_version = pCreateInfo->pApplicationInfo->apiVersion;
478 } else {
479 client_version = VK_MAKE_VERSION(1, 0, 0);
480 }
481
482 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
483 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
484 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
485 "Client requested version %d.%d.%d",
486 VK_VERSION_MAJOR(client_version),
487 VK_VERSION_MINOR(client_version),
488 VK_VERSION_PATCH(client_version));
489 }
490
491 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
492 if (!is_extension_enabled(instance_extensions,
493 ARRAY_SIZE(instance_extensions),
494 pCreateInfo->ppEnabledExtensionNames[i]))
495 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
496 }
497
498 instance = vk_alloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
499 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
500 if (!instance)
501 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
502
503 memset(instance, 0, sizeof(*instance));
504
505 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
506
507 if (pAllocator)
508 instance->alloc = *pAllocator;
509 else
510 instance->alloc = default_alloc;
511
512 instance->apiVersion = client_version;
513 instance->physicalDeviceCount = -1;
514
515 _mesa_locale_init();
516
517 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
518
519 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
520 radv_debug_options);
521
522 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
523 radv_perftest_options);
524
525 *pInstance = radv_instance_to_handle(instance);
526
527 return VK_SUCCESS;
528 }
529
530 void radv_DestroyInstance(
531 VkInstance _instance,
532 const VkAllocationCallbacks* pAllocator)
533 {
534 RADV_FROM_HANDLE(radv_instance, instance, _instance);
535
536 if (!instance)
537 return;
538
539 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
540 radv_physical_device_finish(instance->physicalDevices + i);
541 }
542
543 VG(VALGRIND_DESTROY_MEMPOOL(instance));
544
545 _mesa_locale_fini();
546
547 vk_free(&instance->alloc, instance);
548 }
549
550 static VkResult
551 radv_enumerate_devices(struct radv_instance *instance)
552 {
553 /* TODO: Check for more devices ? */
554 drmDevicePtr devices[8];
555 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
556 int max_devices;
557
558 instance->physicalDeviceCount = 0;
559
560 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
561 if (max_devices < 1)
562 return VK_ERROR_INCOMPATIBLE_DRIVER;
563
564 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
565 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
566 devices[i]->bustype == DRM_BUS_PCI &&
567 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
568
569 result = radv_physical_device_init(instance->physicalDevices +
570 instance->physicalDeviceCount,
571 instance,
572 devices[i]);
573 if (result == VK_SUCCESS)
574 ++instance->physicalDeviceCount;
575 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
576 break;
577 }
578 }
579 drmFreeDevices(devices, max_devices);
580
581 return result;
582 }
583
584 VkResult radv_EnumeratePhysicalDevices(
585 VkInstance _instance,
586 uint32_t* pPhysicalDeviceCount,
587 VkPhysicalDevice* pPhysicalDevices)
588 {
589 RADV_FROM_HANDLE(radv_instance, instance, _instance);
590 VkResult result;
591
592 if (instance->physicalDeviceCount < 0) {
593 result = radv_enumerate_devices(instance);
594 if (result != VK_SUCCESS &&
595 result != VK_ERROR_INCOMPATIBLE_DRIVER)
596 return result;
597 }
598
599 if (!pPhysicalDevices) {
600 *pPhysicalDeviceCount = instance->physicalDeviceCount;
601 } else {
602 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
603 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
604 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
605 }
606
607 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
608 : VK_SUCCESS;
609 }
610
611 void radv_GetPhysicalDeviceFeatures(
612 VkPhysicalDevice physicalDevice,
613 VkPhysicalDeviceFeatures* pFeatures)
614 {
615 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
616 bool is_gfx9 = pdevice->rad_info.chip_class >= GFX9;
617 memset(pFeatures, 0, sizeof(*pFeatures));
618
619 *pFeatures = (VkPhysicalDeviceFeatures) {
620 .robustBufferAccess = true,
621 .fullDrawIndexUint32 = true,
622 .imageCubeArray = true,
623 .independentBlend = true,
624 .geometryShader = !is_gfx9,
625 .tessellationShader = !is_gfx9,
626 .sampleRateShading = true,
627 .dualSrcBlend = true,
628 .logicOp = true,
629 .multiDrawIndirect = true,
630 .drawIndirectFirstInstance = true,
631 .depthClamp = true,
632 .depthBiasClamp = true,
633 .fillModeNonSolid = true,
634 .depthBounds = true,
635 .wideLines = true,
636 .largePoints = true,
637 .alphaToOne = true,
638 .multiViewport = true,
639 .samplerAnisotropy = true,
640 .textureCompressionETC2 = false,
641 .textureCompressionASTC_LDR = false,
642 .textureCompressionBC = true,
643 .occlusionQueryPrecise = true,
644 .pipelineStatisticsQuery = true,
645 .vertexPipelineStoresAndAtomics = true,
646 .fragmentStoresAndAtomics = true,
647 .shaderTessellationAndGeometryPointSize = true,
648 .shaderImageGatherExtended = true,
649 .shaderStorageImageExtendedFormats = true,
650 .shaderStorageImageMultisample = false,
651 .shaderUniformBufferArrayDynamicIndexing = true,
652 .shaderSampledImageArrayDynamicIndexing = true,
653 .shaderStorageBufferArrayDynamicIndexing = true,
654 .shaderStorageImageArrayDynamicIndexing = true,
655 .shaderStorageImageReadWithoutFormat = true,
656 .shaderStorageImageWriteWithoutFormat = true,
657 .shaderClipDistance = true,
658 .shaderCullDistance = true,
659 .shaderFloat64 = true,
660 .shaderInt64 = true,
661 .shaderInt16 = false,
662 .sparseBinding = true,
663 .variableMultisampleRate = true,
664 .inheritedQueries = true,
665 };
666 }
667
668 void radv_GetPhysicalDeviceFeatures2KHR(
669 VkPhysicalDevice physicalDevice,
670 VkPhysicalDeviceFeatures2KHR *pFeatures)
671 {
672 vk_foreach_struct(ext, pFeatures->pNext) {
673 switch (ext->sType) {
674 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
675 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
676 features->variablePointersStorageBuffer = true;
677 features->variablePointers = false;
678 break;
679 }
680 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHX: {
681 VkPhysicalDeviceMultiviewFeaturesKHX *features = (VkPhysicalDeviceMultiviewFeaturesKHX*)ext;
682 features->multiview = true;
683 features->multiviewGeometryShader = true;
684 features->multiviewTessellationShader = true;
685 break;
686 }
687 default:
688 break;
689 }
690 }
691 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
692 }
693
694 void radv_GetPhysicalDeviceProperties(
695 VkPhysicalDevice physicalDevice,
696 VkPhysicalDeviceProperties* pProperties)
697 {
698 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
699 VkSampleCountFlags sample_counts = 0xf;
700
701 /* make sure that the entire descriptor set is addressable with a signed
702 * 32-bit int. So the sum of all limits scaled by descriptor size has to
703 * be at most 2 GiB. the combined image & samples object count as one of
704 * both. This limit is for the pipeline layout, not for the set layout, but
705 * there is no set limit, so we just set a pipeline limit. I don't think
706 * any app is going to hit this soon. */
707 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
708 (32 /* uniform buffer, 32 due to potential space wasted on alignement */ +
709 32 /* storage buffer, 32 due to potential space wasted on alignement */ +
710 32 /* sampler, largest when combined with image */ +
711 64 /* sampled image */ +
712 64 /* storage image */);
713
714 VkPhysicalDeviceLimits limits = {
715 .maxImageDimension1D = (1 << 14),
716 .maxImageDimension2D = (1 << 14),
717 .maxImageDimension3D = (1 << 11),
718 .maxImageDimensionCube = (1 << 14),
719 .maxImageArrayLayers = (1 << 11),
720 .maxTexelBufferElements = 128 * 1024 * 1024,
721 .maxUniformBufferRange = UINT32_MAX,
722 .maxStorageBufferRange = UINT32_MAX,
723 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
724 .maxMemoryAllocationCount = UINT32_MAX,
725 .maxSamplerAllocationCount = 64 * 1024,
726 .bufferImageGranularity = 64, /* A cache line */
727 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
728 .maxBoundDescriptorSets = MAX_SETS,
729 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
730 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
731 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
732 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
733 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
734 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
735 .maxPerStageResources = max_descriptor_set_size,
736 .maxDescriptorSetSamplers = max_descriptor_set_size,
737 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
738 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
739 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
740 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
741 .maxDescriptorSetSampledImages = max_descriptor_set_size,
742 .maxDescriptorSetStorageImages = max_descriptor_set_size,
743 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
744 .maxVertexInputAttributes = 32,
745 .maxVertexInputBindings = 32,
746 .maxVertexInputAttributeOffset = 2047,
747 .maxVertexInputBindingStride = 2048,
748 .maxVertexOutputComponents = 128,
749 .maxTessellationGenerationLevel = 64,
750 .maxTessellationPatchSize = 32,
751 .maxTessellationControlPerVertexInputComponents = 128,
752 .maxTessellationControlPerVertexOutputComponents = 128,
753 .maxTessellationControlPerPatchOutputComponents = 120,
754 .maxTessellationControlTotalOutputComponents = 4096,
755 .maxTessellationEvaluationInputComponents = 128,
756 .maxTessellationEvaluationOutputComponents = 128,
757 .maxGeometryShaderInvocations = 127,
758 .maxGeometryInputComponents = 64,
759 .maxGeometryOutputComponents = 128,
760 .maxGeometryOutputVertices = 256,
761 .maxGeometryTotalOutputComponents = 1024,
762 .maxFragmentInputComponents = 128,
763 .maxFragmentOutputAttachments = 8,
764 .maxFragmentDualSrcAttachments = 1,
765 .maxFragmentCombinedOutputResources = 8,
766 .maxComputeSharedMemorySize = 32768,
767 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
768 .maxComputeWorkGroupInvocations = 2048,
769 .maxComputeWorkGroupSize = {
770 2048,
771 2048,
772 2048
773 },
774 .subPixelPrecisionBits = 4 /* FIXME */,
775 .subTexelPrecisionBits = 4 /* FIXME */,
776 .mipmapPrecisionBits = 4 /* FIXME */,
777 .maxDrawIndexedIndexValue = UINT32_MAX,
778 .maxDrawIndirectCount = UINT32_MAX,
779 .maxSamplerLodBias = 16,
780 .maxSamplerAnisotropy = 16,
781 .maxViewports = MAX_VIEWPORTS,
782 .maxViewportDimensions = { (1 << 14), (1 << 14) },
783 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
784 .viewportSubPixelBits = 13, /* We take a float? */
785 .minMemoryMapAlignment = 4096, /* A page */
786 .minTexelBufferOffsetAlignment = 1,
787 .minUniformBufferOffsetAlignment = 4,
788 .minStorageBufferOffsetAlignment = 4,
789 .minTexelOffset = -32,
790 .maxTexelOffset = 31,
791 .minTexelGatherOffset = -32,
792 .maxTexelGatherOffset = 31,
793 .minInterpolationOffset = -2,
794 .maxInterpolationOffset = 2,
795 .subPixelInterpolationOffsetBits = 8,
796 .maxFramebufferWidth = (1 << 14),
797 .maxFramebufferHeight = (1 << 14),
798 .maxFramebufferLayers = (1 << 10),
799 .framebufferColorSampleCounts = sample_counts,
800 .framebufferDepthSampleCounts = sample_counts,
801 .framebufferStencilSampleCounts = sample_counts,
802 .framebufferNoAttachmentsSampleCounts = sample_counts,
803 .maxColorAttachments = MAX_RTS,
804 .sampledImageColorSampleCounts = sample_counts,
805 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
806 .sampledImageDepthSampleCounts = sample_counts,
807 .sampledImageStencilSampleCounts = sample_counts,
808 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
809 .maxSampleMaskWords = 1,
810 .timestampComputeAndGraphics = true,
811 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
812 .maxClipDistances = 8,
813 .maxCullDistances = 8,
814 .maxCombinedClipAndCullDistances = 8,
815 .discreteQueuePriorities = 1,
816 .pointSizeRange = { 0.125, 255.875 },
817 .lineWidthRange = { 0.0, 7.9921875 },
818 .pointSizeGranularity = (1.0 / 8.0),
819 .lineWidthGranularity = (1.0 / 128.0),
820 .strictLines = false, /* FINISHME */
821 .standardSampleLocations = true,
822 .optimalBufferCopyOffsetAlignment = 128,
823 .optimalBufferCopyRowPitchAlignment = 128,
824 .nonCoherentAtomSize = 64,
825 };
826
827 *pProperties = (VkPhysicalDeviceProperties) {
828 .apiVersion = VK_MAKE_VERSION(1, 0, 42),
829 .driverVersion = vk_get_driver_version(),
830 .vendorID = ATI_VENDOR_ID,
831 .deviceID = pdevice->rad_info.pci_id,
832 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
833 .limits = limits,
834 .sparseProperties = {0},
835 };
836
837 strcpy(pProperties->deviceName, pdevice->name);
838 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
839 }
840
841 void radv_GetPhysicalDeviceProperties2KHR(
842 VkPhysicalDevice physicalDevice,
843 VkPhysicalDeviceProperties2KHR *pProperties)
844 {
845 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
846 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
847
848 vk_foreach_struct(ext, pProperties->pNext) {
849 switch (ext->sType) {
850 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
851 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
852 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
853 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
854 break;
855 }
856 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
857 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
858 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
859 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
860 properties->deviceLUIDValid = false;
861 break;
862 }
863 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHX: {
864 VkPhysicalDeviceMultiviewPropertiesKHX *properties = (VkPhysicalDeviceMultiviewPropertiesKHX*)ext;
865 properties->maxMultiviewViewCount = MAX_VIEWS;
866 properties->maxMultiviewInstanceIndex = INT_MAX;
867 break;
868 }
869 default:
870 break;
871 }
872 }
873 }
874
875 static void radv_get_physical_device_queue_family_properties(
876 struct radv_physical_device* pdevice,
877 uint32_t* pCount,
878 VkQueueFamilyProperties** pQueueFamilyProperties)
879 {
880 int num_queue_families = 1;
881 int idx;
882 if (pdevice->rad_info.num_compute_rings > 0 &&
883 pdevice->rad_info.chip_class >= CIK &&
884 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
885 num_queue_families++;
886
887 if (pQueueFamilyProperties == NULL) {
888 *pCount = num_queue_families;
889 return;
890 }
891
892 if (!*pCount)
893 return;
894
895 idx = 0;
896 if (*pCount >= 1) {
897 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
898 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
899 VK_QUEUE_COMPUTE_BIT |
900 VK_QUEUE_TRANSFER_BIT |
901 VK_QUEUE_SPARSE_BINDING_BIT,
902 .queueCount = 1,
903 .timestampValidBits = 64,
904 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
905 };
906 idx++;
907 }
908
909 if (pdevice->rad_info.num_compute_rings > 0 &&
910 pdevice->rad_info.chip_class >= CIK &&
911 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
912 if (*pCount > idx) {
913 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
914 .queueFlags = VK_QUEUE_COMPUTE_BIT |
915 VK_QUEUE_TRANSFER_BIT |
916 VK_QUEUE_SPARSE_BINDING_BIT,
917 .queueCount = pdevice->rad_info.num_compute_rings,
918 .timestampValidBits = 64,
919 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
920 };
921 idx++;
922 }
923 }
924 *pCount = idx;
925 }
926
927 void radv_GetPhysicalDeviceQueueFamilyProperties(
928 VkPhysicalDevice physicalDevice,
929 uint32_t* pCount,
930 VkQueueFamilyProperties* pQueueFamilyProperties)
931 {
932 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
933 if (!pQueueFamilyProperties) {
934 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
935 return;
936 }
937 VkQueueFamilyProperties *properties[] = {
938 pQueueFamilyProperties + 0,
939 pQueueFamilyProperties + 1,
940 pQueueFamilyProperties + 2,
941 };
942 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
943 assert(*pCount <= 3);
944 }
945
946 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
947 VkPhysicalDevice physicalDevice,
948 uint32_t* pCount,
949 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
950 {
951 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
952 if (!pQueueFamilyProperties) {
953 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
954 return;
955 }
956 VkQueueFamilyProperties *properties[] = {
957 &pQueueFamilyProperties[0].queueFamilyProperties,
958 &pQueueFamilyProperties[1].queueFamilyProperties,
959 &pQueueFamilyProperties[2].queueFamilyProperties,
960 };
961 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
962 assert(*pCount <= 3);
963 }
964
965 void radv_GetPhysicalDeviceMemoryProperties(
966 VkPhysicalDevice physicalDevice,
967 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
968 {
969 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
970
971 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
972
973 pMemoryProperties->memoryTypeCount = RADV_MEM_TYPE_COUNT;
974 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM] = (VkMemoryType) {
975 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
976 .heapIndex = RADV_MEM_HEAP_VRAM,
977 };
978 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_WRITE_COMBINE] = (VkMemoryType) {
979 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
980 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
981 .heapIndex = RADV_MEM_HEAP_GTT,
982 };
983 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM_CPU_ACCESS] = (VkMemoryType) {
984 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
985 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
986 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
987 .heapIndex = RADV_MEM_HEAP_VRAM_CPU_ACCESS,
988 };
989 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_CACHED] = (VkMemoryType) {
990 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
991 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
992 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
993 .heapIndex = RADV_MEM_HEAP_GTT,
994 };
995
996 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
997 uint64_t visible_vram_size = MIN2(physical_device->rad_info.vram_size,
998 physical_device->rad_info.vram_vis_size);
999
1000 pMemoryProperties->memoryHeapCount = RADV_MEM_HEAP_COUNT;
1001 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM] = (VkMemoryHeap) {
1002 .size = physical_device->rad_info.vram_size -
1003 visible_vram_size,
1004 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
1005 };
1006 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = (VkMemoryHeap) {
1007 .size = visible_vram_size,
1008 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
1009 };
1010 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_GTT] = (VkMemoryHeap) {
1011 .size = physical_device->rad_info.gart_size,
1012 .flags = 0,
1013 };
1014 }
1015
1016 void radv_GetPhysicalDeviceMemoryProperties2KHR(
1017 VkPhysicalDevice physicalDevice,
1018 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
1019 {
1020 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1021 &pMemoryProperties->memoryProperties);
1022 }
1023
1024 static int
1025 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1026 int queue_family_index, int idx)
1027 {
1028 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1029 queue->device = device;
1030 queue->queue_family_index = queue_family_index;
1031 queue->queue_idx = idx;
1032
1033 queue->hw_ctx = device->ws->ctx_create(device->ws);
1034 if (!queue->hw_ctx)
1035 return VK_ERROR_OUT_OF_HOST_MEMORY;
1036
1037 return VK_SUCCESS;
1038 }
1039
1040 static void
1041 radv_queue_finish(struct radv_queue *queue)
1042 {
1043 if (queue->hw_ctx)
1044 queue->device->ws->ctx_destroy(queue->hw_ctx);
1045
1046 if (queue->initial_full_flush_preamble_cs)
1047 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1048 if (queue->initial_preamble_cs)
1049 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1050 if (queue->continue_preamble_cs)
1051 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1052 if (queue->descriptor_bo)
1053 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1054 if (queue->scratch_bo)
1055 queue->device->ws->buffer_destroy(queue->scratch_bo);
1056 if (queue->esgs_ring_bo)
1057 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1058 if (queue->gsvs_ring_bo)
1059 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1060 if (queue->tess_factor_ring_bo)
1061 queue->device->ws->buffer_destroy(queue->tess_factor_ring_bo);
1062 if (queue->tess_offchip_ring_bo)
1063 queue->device->ws->buffer_destroy(queue->tess_offchip_ring_bo);
1064 if (queue->compute_scratch_bo)
1065 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1066 }
1067
1068 static void
1069 radv_device_init_gs_info(struct radv_device *device)
1070 {
1071 switch (device->physical_device->rad_info.family) {
1072 case CHIP_OLAND:
1073 case CHIP_HAINAN:
1074 case CHIP_KAVERI:
1075 case CHIP_KABINI:
1076 case CHIP_MULLINS:
1077 case CHIP_ICELAND:
1078 case CHIP_CARRIZO:
1079 case CHIP_STONEY:
1080 device->gs_table_depth = 16;
1081 return;
1082 case CHIP_TAHITI:
1083 case CHIP_PITCAIRN:
1084 case CHIP_VERDE:
1085 case CHIP_BONAIRE:
1086 case CHIP_HAWAII:
1087 case CHIP_TONGA:
1088 case CHIP_FIJI:
1089 case CHIP_POLARIS10:
1090 case CHIP_POLARIS11:
1091 case CHIP_POLARIS12:
1092 case CHIP_VEGA10:
1093 case CHIP_RAVEN:
1094 device->gs_table_depth = 32;
1095 return;
1096 default:
1097 unreachable("unknown GPU");
1098 }
1099 }
1100
1101 VkResult radv_CreateDevice(
1102 VkPhysicalDevice physicalDevice,
1103 const VkDeviceCreateInfo* pCreateInfo,
1104 const VkAllocationCallbacks* pAllocator,
1105 VkDevice* pDevice)
1106 {
1107 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1108 VkResult result;
1109 struct radv_device *device;
1110
1111 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1112 if (!is_extension_enabled(physical_device->extensions.ext_array,
1113 physical_device->extensions.num_ext,
1114 pCreateInfo->ppEnabledExtensionNames[i]))
1115 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
1116 }
1117
1118 /* Check enabled features */
1119 if (pCreateInfo->pEnabledFeatures) {
1120 VkPhysicalDeviceFeatures supported_features;
1121 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1122 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1123 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1124 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1125 for (uint32_t i = 0; i < num_features; i++) {
1126 if (enabled_feature[i] && !supported_feature[i])
1127 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT);
1128 }
1129 }
1130
1131 device = vk_alloc2(&physical_device->instance->alloc, pAllocator,
1132 sizeof(*device), 8,
1133 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1134 if (!device)
1135 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1136
1137 memset(device, 0, sizeof(*device));
1138
1139 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1140 device->instance = physical_device->instance;
1141 device->physical_device = physical_device;
1142
1143 device->debug_flags = device->instance->debug_flags;
1144
1145 device->ws = physical_device->ws;
1146 if (pAllocator)
1147 device->alloc = *pAllocator;
1148 else
1149 device->alloc = physical_device->instance->alloc;
1150
1151 mtx_init(&device->shader_slab_mutex, mtx_plain);
1152 list_inithead(&device->shader_slabs);
1153
1154 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1155 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1156 uint32_t qfi = queue_create->queueFamilyIndex;
1157
1158 device->queues[qfi] = vk_alloc(&device->alloc,
1159 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1160 if (!device->queues[qfi]) {
1161 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1162 goto fail;
1163 }
1164
1165 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1166
1167 device->queue_count[qfi] = queue_create->queueCount;
1168
1169 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1170 result = radv_queue_init(device, &device->queues[qfi][q], qfi, q);
1171 if (result != VK_SUCCESS)
1172 goto fail;
1173 }
1174 }
1175
1176 #if HAVE_LLVM < 0x0400
1177 device->llvm_supports_spill = false;
1178 #else
1179 device->llvm_supports_spill = true;
1180 #endif
1181
1182 /* The maximum number of scratch waves. Scratch space isn't divided
1183 * evenly between CUs. The number is only a function of the number of CUs.
1184 * We can decrease the constant to decrease the scratch buffer size.
1185 *
1186 * sctx->scratch_waves must be >= the maximum posible size of
1187 * 1 threadgroup, so that the hw doesn't hang from being unable
1188 * to start any.
1189 *
1190 * The recommended value is 4 per CU at most. Higher numbers don't
1191 * bring much benefit, but they still occupy chip resources (think
1192 * async compute). I've seen ~2% performance difference between 4 and 32.
1193 */
1194 uint32_t max_threads_per_block = 2048;
1195 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1196 max_threads_per_block / 64);
1197
1198 radv_device_init_gs_info(device);
1199
1200 device->tess_offchip_block_dw_size =
1201 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1202 device->has_distributed_tess =
1203 device->physical_device->rad_info.chip_class >= VI &&
1204 device->physical_device->rad_info.max_se >= 2;
1205
1206 result = radv_device_init_meta(device);
1207 if (result != VK_SUCCESS)
1208 goto fail;
1209
1210 radv_device_init_msaa(device);
1211
1212 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1213 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1214 switch (family) {
1215 case RADV_QUEUE_GENERAL:
1216 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1217 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1218 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1219 break;
1220 case RADV_QUEUE_COMPUTE:
1221 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1222 radeon_emit(device->empty_cs[family], 0);
1223 break;
1224 }
1225 device->ws->cs_finalize(device->empty_cs[family]);
1226 }
1227
1228 if (getenv("RADV_TRACE_FILE")) {
1229 if (!radv_init_trace(device))
1230 goto fail;
1231 }
1232
1233 if (device->physical_device->rad_info.chip_class >= CIK)
1234 cik_create_gfx_config(device);
1235
1236 VkPipelineCacheCreateInfo ci;
1237 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1238 ci.pNext = NULL;
1239 ci.flags = 0;
1240 ci.pInitialData = NULL;
1241 ci.initialDataSize = 0;
1242 VkPipelineCache pc;
1243 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1244 &ci, NULL, &pc);
1245 if (result != VK_SUCCESS)
1246 goto fail;
1247
1248 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1249
1250 *pDevice = radv_device_to_handle(device);
1251 return VK_SUCCESS;
1252
1253 fail:
1254 if (device->trace_bo)
1255 device->ws->buffer_destroy(device->trace_bo);
1256
1257 if (device->gfx_init)
1258 device->ws->buffer_destroy(device->gfx_init);
1259
1260 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1261 for (unsigned q = 0; q < device->queue_count[i]; q++)
1262 radv_queue_finish(&device->queues[i][q]);
1263 if (device->queue_count[i])
1264 vk_free(&device->alloc, device->queues[i]);
1265 }
1266
1267 vk_free(&device->alloc, device);
1268 return result;
1269 }
1270
1271 void radv_DestroyDevice(
1272 VkDevice _device,
1273 const VkAllocationCallbacks* pAllocator)
1274 {
1275 RADV_FROM_HANDLE(radv_device, device, _device);
1276
1277 if (!device)
1278 return;
1279
1280 if (device->trace_bo)
1281 device->ws->buffer_destroy(device->trace_bo);
1282
1283 if (device->gfx_init)
1284 device->ws->buffer_destroy(device->gfx_init);
1285
1286 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1287 for (unsigned q = 0; q < device->queue_count[i]; q++)
1288 radv_queue_finish(&device->queues[i][q]);
1289 if (device->queue_count[i])
1290 vk_free(&device->alloc, device->queues[i]);
1291 if (device->empty_cs[i])
1292 device->ws->cs_destroy(device->empty_cs[i]);
1293 }
1294 radv_device_finish_meta(device);
1295
1296 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1297 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1298
1299 radv_destroy_shader_slabs(device);
1300
1301 vk_free(&device->alloc, device);
1302 }
1303
1304 VkResult radv_EnumerateInstanceExtensionProperties(
1305 const char* pLayerName,
1306 uint32_t* pPropertyCount,
1307 VkExtensionProperties* pProperties)
1308 {
1309 if (pProperties == NULL) {
1310 *pPropertyCount = ARRAY_SIZE(instance_extensions);
1311 return VK_SUCCESS;
1312 }
1313
1314 *pPropertyCount = MIN2(*pPropertyCount, ARRAY_SIZE(instance_extensions));
1315 typed_memcpy(pProperties, instance_extensions, *pPropertyCount);
1316
1317 if (*pPropertyCount < ARRAY_SIZE(instance_extensions))
1318 return VK_INCOMPLETE;
1319
1320 return VK_SUCCESS;
1321 }
1322
1323 VkResult radv_EnumerateDeviceExtensionProperties(
1324 VkPhysicalDevice physicalDevice,
1325 const char* pLayerName,
1326 uint32_t* pPropertyCount,
1327 VkExtensionProperties* pProperties)
1328 {
1329 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1330
1331 if (pProperties == NULL) {
1332 *pPropertyCount = pdevice->extensions.num_ext;
1333 return VK_SUCCESS;
1334 }
1335
1336 *pPropertyCount = MIN2(*pPropertyCount, pdevice->extensions.num_ext);
1337 typed_memcpy(pProperties, pdevice->extensions.ext_array, *pPropertyCount);
1338
1339 if (*pPropertyCount < pdevice->extensions.num_ext)
1340 return VK_INCOMPLETE;
1341
1342 return VK_SUCCESS;
1343 }
1344
1345 VkResult radv_EnumerateInstanceLayerProperties(
1346 uint32_t* pPropertyCount,
1347 VkLayerProperties* pProperties)
1348 {
1349 if (pProperties == NULL) {
1350 *pPropertyCount = 0;
1351 return VK_SUCCESS;
1352 }
1353
1354 /* None supported at this time */
1355 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1356 }
1357
1358 VkResult radv_EnumerateDeviceLayerProperties(
1359 VkPhysicalDevice physicalDevice,
1360 uint32_t* pPropertyCount,
1361 VkLayerProperties* pProperties)
1362 {
1363 if (pProperties == NULL) {
1364 *pPropertyCount = 0;
1365 return VK_SUCCESS;
1366 }
1367
1368 /* None supported at this time */
1369 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1370 }
1371
1372 void radv_GetDeviceQueue(
1373 VkDevice _device,
1374 uint32_t queueFamilyIndex,
1375 uint32_t queueIndex,
1376 VkQueue* pQueue)
1377 {
1378 RADV_FROM_HANDLE(radv_device, device, _device);
1379
1380 *pQueue = radv_queue_to_handle(&device->queues[queueFamilyIndex][queueIndex]);
1381 }
1382
1383 static void
1384 fill_geom_tess_rings(struct radv_queue *queue,
1385 uint32_t *map,
1386 bool add_sample_positions,
1387 uint32_t esgs_ring_size,
1388 struct radeon_winsys_bo *esgs_ring_bo,
1389 uint32_t gsvs_ring_size,
1390 struct radeon_winsys_bo *gsvs_ring_bo,
1391 uint32_t tess_factor_ring_size,
1392 struct radeon_winsys_bo *tess_factor_ring_bo,
1393 uint32_t tess_offchip_ring_size,
1394 struct radeon_winsys_bo *tess_offchip_ring_bo)
1395 {
1396 uint64_t esgs_va = 0, gsvs_va = 0;
1397 uint64_t tess_factor_va = 0, tess_offchip_va = 0;
1398 uint32_t *desc = &map[4];
1399
1400 if (esgs_ring_bo)
1401 esgs_va = radv_buffer_get_va(esgs_ring_bo);
1402 if (gsvs_ring_bo)
1403 gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
1404 if (tess_factor_ring_bo)
1405 tess_factor_va = radv_buffer_get_va(tess_factor_ring_bo);
1406 if (tess_offchip_ring_bo)
1407 tess_offchip_va = radv_buffer_get_va(tess_offchip_ring_bo);
1408
1409 /* stride 0, num records - size, add tid, swizzle, elsize4,
1410 index stride 64 */
1411 desc[0] = esgs_va;
1412 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1413 S_008F04_STRIDE(0) |
1414 S_008F04_SWIZZLE_ENABLE(true);
1415 desc[2] = esgs_ring_size;
1416 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1417 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1418 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1419 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1420 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1421 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1422 S_008F0C_ELEMENT_SIZE(1) |
1423 S_008F0C_INDEX_STRIDE(3) |
1424 S_008F0C_ADD_TID_ENABLE(true);
1425
1426 desc += 4;
1427 /* GS entry for ES->GS ring */
1428 /* stride 0, num records - size, elsize0,
1429 index stride 0 */
1430 desc[0] = esgs_va;
1431 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1432 S_008F04_STRIDE(0) |
1433 S_008F04_SWIZZLE_ENABLE(false);
1434 desc[2] = esgs_ring_size;
1435 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1436 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1437 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1438 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1439 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1440 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1441 S_008F0C_ELEMENT_SIZE(0) |
1442 S_008F0C_INDEX_STRIDE(0) |
1443 S_008F0C_ADD_TID_ENABLE(false);
1444
1445 desc += 4;
1446 /* VS entry for GS->VS ring */
1447 /* stride 0, num records - size, elsize0,
1448 index stride 0 */
1449 desc[0] = gsvs_va;
1450 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1451 S_008F04_STRIDE(0) |
1452 S_008F04_SWIZZLE_ENABLE(false);
1453 desc[2] = gsvs_ring_size;
1454 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1455 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1456 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1457 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1458 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1459 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1460 S_008F0C_ELEMENT_SIZE(0) |
1461 S_008F0C_INDEX_STRIDE(0) |
1462 S_008F0C_ADD_TID_ENABLE(false);
1463 desc += 4;
1464
1465 /* stride gsvs_itemsize, num records 64
1466 elsize 4, index stride 16 */
1467 /* shader will patch stride and desc[2] */
1468 desc[0] = gsvs_va;
1469 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1470 S_008F04_STRIDE(0) |
1471 S_008F04_SWIZZLE_ENABLE(true);
1472 desc[2] = 0;
1473 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1474 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1475 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1476 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1477 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1478 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1479 S_008F0C_ELEMENT_SIZE(1) |
1480 S_008F0C_INDEX_STRIDE(1) |
1481 S_008F0C_ADD_TID_ENABLE(true);
1482 desc += 4;
1483
1484 desc[0] = tess_factor_va;
1485 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_factor_va >> 32) |
1486 S_008F04_STRIDE(0) |
1487 S_008F04_SWIZZLE_ENABLE(false);
1488 desc[2] = tess_factor_ring_size;
1489 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1490 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1491 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1492 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1493 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1494 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1495 S_008F0C_ELEMENT_SIZE(0) |
1496 S_008F0C_INDEX_STRIDE(0) |
1497 S_008F0C_ADD_TID_ENABLE(false);
1498 desc += 4;
1499
1500 desc[0] = tess_offchip_va;
1501 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1502 S_008F04_STRIDE(0) |
1503 S_008F04_SWIZZLE_ENABLE(false);
1504 desc[2] = tess_offchip_ring_size;
1505 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1506 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1507 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1508 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1509 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1510 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1511 S_008F0C_ELEMENT_SIZE(0) |
1512 S_008F0C_INDEX_STRIDE(0) |
1513 S_008F0C_ADD_TID_ENABLE(false);
1514 desc += 4;
1515
1516 /* add sample positions after all rings */
1517 memcpy(desc, queue->device->sample_locations_1x, 8);
1518 desc += 2;
1519 memcpy(desc, queue->device->sample_locations_2x, 16);
1520 desc += 4;
1521 memcpy(desc, queue->device->sample_locations_4x, 32);
1522 desc += 8;
1523 memcpy(desc, queue->device->sample_locations_8x, 64);
1524 desc += 16;
1525 memcpy(desc, queue->device->sample_locations_16x, 128);
1526 }
1527
1528 static unsigned
1529 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1530 {
1531 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1532 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1533 device->physical_device->rad_info.family != CHIP_STONEY;
1534 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1535 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1536 device->physical_device->rad_info.max_se;
1537 unsigned offchip_granularity;
1538 unsigned hs_offchip_param;
1539 switch (device->tess_offchip_block_dw_size) {
1540 default:
1541 assert(0);
1542 /* fall through */
1543 case 8192:
1544 offchip_granularity = V_03093C_X_8K_DWORDS;
1545 break;
1546 case 4096:
1547 offchip_granularity = V_03093C_X_4K_DWORDS;
1548 break;
1549 }
1550
1551 switch (device->physical_device->rad_info.chip_class) {
1552 case SI:
1553 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1554 break;
1555 case CIK:
1556 case VI:
1557 case GFX9:
1558 default:
1559 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1560 break;
1561 }
1562
1563 *max_offchip_buffers_p = max_offchip_buffers;
1564 if (device->physical_device->rad_info.chip_class >= CIK) {
1565 if (device->physical_device->rad_info.chip_class >= VI)
1566 --max_offchip_buffers;
1567 hs_offchip_param =
1568 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1569 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1570 } else {
1571 hs_offchip_param =
1572 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1573 }
1574 return hs_offchip_param;
1575 }
1576
1577 static VkResult
1578 radv_get_preamble_cs(struct radv_queue *queue,
1579 uint32_t scratch_size,
1580 uint32_t compute_scratch_size,
1581 uint32_t esgs_ring_size,
1582 uint32_t gsvs_ring_size,
1583 bool needs_tess_rings,
1584 bool needs_sample_positions,
1585 struct radeon_winsys_cs **initial_full_flush_preamble_cs,
1586 struct radeon_winsys_cs **initial_preamble_cs,
1587 struct radeon_winsys_cs **continue_preamble_cs)
1588 {
1589 struct radeon_winsys_bo *scratch_bo = NULL;
1590 struct radeon_winsys_bo *descriptor_bo = NULL;
1591 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1592 struct radeon_winsys_bo *esgs_ring_bo = NULL;
1593 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
1594 struct radeon_winsys_bo *tess_factor_ring_bo = NULL;
1595 struct radeon_winsys_bo *tess_offchip_ring_bo = NULL;
1596 struct radeon_winsys_cs *dest_cs[3] = {0};
1597 bool add_tess_rings = false, add_sample_positions = false;
1598 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
1599 unsigned max_offchip_buffers;
1600 unsigned hs_offchip_param = 0;
1601 if (!queue->has_tess_rings) {
1602 if (needs_tess_rings)
1603 add_tess_rings = true;
1604 }
1605 if (!queue->has_sample_positions) {
1606 if (needs_sample_positions)
1607 add_sample_positions = true;
1608 }
1609 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
1610 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
1611 &max_offchip_buffers);
1612 tess_offchip_ring_size = max_offchip_buffers *
1613 queue->device->tess_offchip_block_dw_size * 4;
1614
1615 if (scratch_size <= queue->scratch_size &&
1616 compute_scratch_size <= queue->compute_scratch_size &&
1617 esgs_ring_size <= queue->esgs_ring_size &&
1618 gsvs_ring_size <= queue->gsvs_ring_size &&
1619 !add_tess_rings && !add_sample_positions &&
1620 queue->initial_preamble_cs) {
1621 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1622 *initial_preamble_cs = queue->initial_preamble_cs;
1623 *continue_preamble_cs = queue->continue_preamble_cs;
1624 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1625 *continue_preamble_cs = NULL;
1626 return VK_SUCCESS;
1627 }
1628
1629 if (scratch_size > queue->scratch_size) {
1630 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1631 scratch_size,
1632 4096,
1633 RADEON_DOMAIN_VRAM,
1634 RADEON_FLAG_NO_CPU_ACCESS);
1635 if (!scratch_bo)
1636 goto fail;
1637 } else
1638 scratch_bo = queue->scratch_bo;
1639
1640 if (compute_scratch_size > queue->compute_scratch_size) {
1641 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1642 compute_scratch_size,
1643 4096,
1644 RADEON_DOMAIN_VRAM,
1645 RADEON_FLAG_NO_CPU_ACCESS);
1646 if (!compute_scratch_bo)
1647 goto fail;
1648
1649 } else
1650 compute_scratch_bo = queue->compute_scratch_bo;
1651
1652 if (esgs_ring_size > queue->esgs_ring_size) {
1653 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1654 esgs_ring_size,
1655 4096,
1656 RADEON_DOMAIN_VRAM,
1657 RADEON_FLAG_NO_CPU_ACCESS);
1658 if (!esgs_ring_bo)
1659 goto fail;
1660 } else {
1661 esgs_ring_bo = queue->esgs_ring_bo;
1662 esgs_ring_size = queue->esgs_ring_size;
1663 }
1664
1665 if (gsvs_ring_size > queue->gsvs_ring_size) {
1666 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1667 gsvs_ring_size,
1668 4096,
1669 RADEON_DOMAIN_VRAM,
1670 RADEON_FLAG_NO_CPU_ACCESS);
1671 if (!gsvs_ring_bo)
1672 goto fail;
1673 } else {
1674 gsvs_ring_bo = queue->gsvs_ring_bo;
1675 gsvs_ring_size = queue->gsvs_ring_size;
1676 }
1677
1678 if (add_tess_rings) {
1679 tess_factor_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1680 tess_factor_ring_size,
1681 256,
1682 RADEON_DOMAIN_VRAM,
1683 RADEON_FLAG_NO_CPU_ACCESS);
1684 if (!tess_factor_ring_bo)
1685 goto fail;
1686 tess_offchip_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1687 tess_offchip_ring_size,
1688 256,
1689 RADEON_DOMAIN_VRAM,
1690 RADEON_FLAG_NO_CPU_ACCESS);
1691 if (!tess_offchip_ring_bo)
1692 goto fail;
1693 } else {
1694 tess_factor_ring_bo = queue->tess_factor_ring_bo;
1695 tess_offchip_ring_bo = queue->tess_offchip_ring_bo;
1696 }
1697
1698 if (scratch_bo != queue->scratch_bo ||
1699 esgs_ring_bo != queue->esgs_ring_bo ||
1700 gsvs_ring_bo != queue->gsvs_ring_bo ||
1701 tess_factor_ring_bo != queue->tess_factor_ring_bo ||
1702 tess_offchip_ring_bo != queue->tess_offchip_ring_bo || add_sample_positions) {
1703 uint32_t size = 0;
1704 if (gsvs_ring_bo || esgs_ring_bo ||
1705 tess_factor_ring_bo || tess_offchip_ring_bo || add_sample_positions) {
1706 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
1707 if (add_sample_positions)
1708 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
1709 }
1710 else if (scratch_bo)
1711 size = 8; /* 2 dword */
1712
1713 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
1714 size,
1715 4096,
1716 RADEON_DOMAIN_VRAM,
1717 RADEON_FLAG_CPU_ACCESS);
1718 if (!descriptor_bo)
1719 goto fail;
1720 } else
1721 descriptor_bo = queue->descriptor_bo;
1722
1723 for(int i = 0; i < 3; ++i) {
1724 struct radeon_winsys_cs *cs = NULL;
1725 cs = queue->device->ws->cs_create(queue->device->ws,
1726 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
1727 if (!cs)
1728 goto fail;
1729
1730 dest_cs[i] = cs;
1731
1732 if (scratch_bo)
1733 queue->device->ws->cs_add_buffer(cs, scratch_bo, 8);
1734
1735 if (esgs_ring_bo)
1736 queue->device->ws->cs_add_buffer(cs, esgs_ring_bo, 8);
1737
1738 if (gsvs_ring_bo)
1739 queue->device->ws->cs_add_buffer(cs, gsvs_ring_bo, 8);
1740
1741 if (tess_factor_ring_bo)
1742 queue->device->ws->cs_add_buffer(cs, tess_factor_ring_bo, 8);
1743
1744 if (tess_offchip_ring_bo)
1745 queue->device->ws->cs_add_buffer(cs, tess_offchip_ring_bo, 8);
1746
1747 if (descriptor_bo)
1748 queue->device->ws->cs_add_buffer(cs, descriptor_bo, 8);
1749
1750 if (descriptor_bo != queue->descriptor_bo) {
1751 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
1752
1753 if (scratch_bo) {
1754 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
1755 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1756 S_008F04_SWIZZLE_ENABLE(1);
1757 map[0] = scratch_va;
1758 map[1] = rsrc1;
1759 }
1760
1761 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo ||
1762 add_sample_positions)
1763 fill_geom_tess_rings(queue, map, add_sample_positions,
1764 esgs_ring_size, esgs_ring_bo,
1765 gsvs_ring_size, gsvs_ring_bo,
1766 tess_factor_ring_size, tess_factor_ring_bo,
1767 tess_offchip_ring_size, tess_offchip_ring_bo);
1768
1769 queue->device->ws->buffer_unmap(descriptor_bo);
1770 }
1771
1772 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo) {
1773 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1774 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1775 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1776 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1777 }
1778
1779 if (esgs_ring_bo || gsvs_ring_bo) {
1780 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1781 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1782 radeon_emit(cs, esgs_ring_size >> 8);
1783 radeon_emit(cs, gsvs_ring_size >> 8);
1784 } else {
1785 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1786 radeon_emit(cs, esgs_ring_size >> 8);
1787 radeon_emit(cs, gsvs_ring_size >> 8);
1788 }
1789 }
1790
1791 if (tess_factor_ring_bo) {
1792 uint64_t tf_va = radv_buffer_get_va(tess_factor_ring_bo);
1793 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1794 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1795 S_030938_SIZE(tess_factor_ring_size / 4));
1796 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1797 tf_va >> 8);
1798 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1799 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
1800 tf_va >> 40);
1801 }
1802 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, hs_offchip_param);
1803 } else {
1804 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
1805 S_008988_SIZE(tess_factor_ring_size / 4));
1806 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
1807 tf_va >> 8);
1808 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1809 hs_offchip_param);
1810 }
1811 }
1812
1813 if (descriptor_bo) {
1814 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1815 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1816 R_00B230_SPI_SHADER_USER_DATA_GS_0,
1817 R_00B330_SPI_SHADER_USER_DATA_ES_0,
1818 R_00B430_SPI_SHADER_USER_DATA_HS_0,
1819 R_00B530_SPI_SHADER_USER_DATA_LS_0};
1820
1821 uint64_t va = radv_buffer_get_va(descriptor_bo);
1822
1823 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1824 radeon_set_sh_reg_seq(cs, regs[i], 2);
1825 radeon_emit(cs, va);
1826 radeon_emit(cs, va >> 32);
1827 }
1828 }
1829
1830 if (compute_scratch_bo) {
1831 uint64_t scratch_va = radv_buffer_get_va(compute_scratch_bo);
1832 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1833 S_008F04_SWIZZLE_ENABLE(1);
1834
1835 queue->device->ws->cs_add_buffer(cs, compute_scratch_bo, 8);
1836
1837 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
1838 radeon_emit(cs, scratch_va);
1839 radeon_emit(cs, rsrc1);
1840 }
1841
1842 if (i == 0) {
1843 si_cs_emit_cache_flush(cs,
1844 false,
1845 queue->device->physical_device->rad_info.chip_class,
1846 NULL, 0,
1847 queue->queue_family_index == RING_COMPUTE &&
1848 queue->device->physical_device->rad_info.chip_class >= CIK,
1849 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
1850 RADV_CMD_FLAG_INV_ICACHE |
1851 RADV_CMD_FLAG_INV_SMEM_L1 |
1852 RADV_CMD_FLAG_INV_VMEM_L1 |
1853 RADV_CMD_FLAG_INV_GLOBAL_L2);
1854 } else if (i == 1) {
1855 si_cs_emit_cache_flush(cs,
1856 false,
1857 queue->device->physical_device->rad_info.chip_class,
1858 NULL, 0,
1859 queue->queue_family_index == RING_COMPUTE &&
1860 queue->device->physical_device->rad_info.chip_class >= CIK,
1861 RADV_CMD_FLAG_INV_ICACHE |
1862 RADV_CMD_FLAG_INV_SMEM_L1 |
1863 RADV_CMD_FLAG_INV_VMEM_L1 |
1864 RADV_CMD_FLAG_INV_GLOBAL_L2);
1865 }
1866
1867 if (!queue->device->ws->cs_finalize(cs))
1868 goto fail;
1869 }
1870
1871 if (queue->initial_full_flush_preamble_cs)
1872 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1873
1874 if (queue->initial_preamble_cs)
1875 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1876
1877 if (queue->continue_preamble_cs)
1878 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1879
1880 queue->initial_full_flush_preamble_cs = dest_cs[0];
1881 queue->initial_preamble_cs = dest_cs[1];
1882 queue->continue_preamble_cs = dest_cs[2];
1883
1884 if (scratch_bo != queue->scratch_bo) {
1885 if (queue->scratch_bo)
1886 queue->device->ws->buffer_destroy(queue->scratch_bo);
1887 queue->scratch_bo = scratch_bo;
1888 queue->scratch_size = scratch_size;
1889 }
1890
1891 if (compute_scratch_bo != queue->compute_scratch_bo) {
1892 if (queue->compute_scratch_bo)
1893 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1894 queue->compute_scratch_bo = compute_scratch_bo;
1895 queue->compute_scratch_size = compute_scratch_size;
1896 }
1897
1898 if (esgs_ring_bo != queue->esgs_ring_bo) {
1899 if (queue->esgs_ring_bo)
1900 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1901 queue->esgs_ring_bo = esgs_ring_bo;
1902 queue->esgs_ring_size = esgs_ring_size;
1903 }
1904
1905 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
1906 if (queue->gsvs_ring_bo)
1907 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1908 queue->gsvs_ring_bo = gsvs_ring_bo;
1909 queue->gsvs_ring_size = gsvs_ring_size;
1910 }
1911
1912 if (tess_factor_ring_bo != queue->tess_factor_ring_bo) {
1913 queue->tess_factor_ring_bo = tess_factor_ring_bo;
1914 }
1915
1916 if (tess_offchip_ring_bo != queue->tess_offchip_ring_bo) {
1917 queue->tess_offchip_ring_bo = tess_offchip_ring_bo;
1918 queue->has_tess_rings = true;
1919 }
1920
1921 if (descriptor_bo != queue->descriptor_bo) {
1922 if (queue->descriptor_bo)
1923 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1924
1925 queue->descriptor_bo = descriptor_bo;
1926 }
1927
1928 if (add_sample_positions)
1929 queue->has_sample_positions = true;
1930
1931 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1932 *initial_preamble_cs = queue->initial_preamble_cs;
1933 *continue_preamble_cs = queue->continue_preamble_cs;
1934 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1935 *continue_preamble_cs = NULL;
1936 return VK_SUCCESS;
1937 fail:
1938 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
1939 if (dest_cs[i])
1940 queue->device->ws->cs_destroy(dest_cs[i]);
1941 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
1942 queue->device->ws->buffer_destroy(descriptor_bo);
1943 if (scratch_bo && scratch_bo != queue->scratch_bo)
1944 queue->device->ws->buffer_destroy(scratch_bo);
1945 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
1946 queue->device->ws->buffer_destroy(compute_scratch_bo);
1947 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
1948 queue->device->ws->buffer_destroy(esgs_ring_bo);
1949 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
1950 queue->device->ws->buffer_destroy(gsvs_ring_bo);
1951 if (tess_factor_ring_bo && tess_factor_ring_bo != queue->tess_factor_ring_bo)
1952 queue->device->ws->buffer_destroy(tess_factor_ring_bo);
1953 if (tess_offchip_ring_bo && tess_offchip_ring_bo != queue->tess_offchip_ring_bo)
1954 queue->device->ws->buffer_destroy(tess_offchip_ring_bo);
1955 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1956 }
1957
1958 static VkResult radv_alloc_sem_counts(struct radv_winsys_sem_counts *counts,
1959 int num_sems,
1960 const VkSemaphore *sems,
1961 bool reset_temp)
1962 {
1963 int syncobj_idx = 0, sem_idx = 0;
1964
1965 if (num_sems == 0)
1966 return VK_SUCCESS;
1967 for (uint32_t i = 0; i < num_sems; i++) {
1968 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1969
1970 if (sem->temp_syncobj || sem->syncobj)
1971 counts->syncobj_count++;
1972 else
1973 counts->sem_count++;
1974 }
1975
1976 if (counts->syncobj_count) {
1977 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
1978 if (!counts->syncobj)
1979 return VK_ERROR_OUT_OF_HOST_MEMORY;
1980 }
1981
1982 if (counts->sem_count) {
1983 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
1984 if (!counts->sem) {
1985 free(counts->syncobj);
1986 return VK_ERROR_OUT_OF_HOST_MEMORY;
1987 }
1988 }
1989
1990 for (uint32_t i = 0; i < num_sems; i++) {
1991 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1992
1993 if (sem->temp_syncobj) {
1994 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
1995 if (reset_temp) {
1996 /* after we wait on a temp import - drop it */
1997 sem->temp_syncobj = 0;
1998 }
1999 }
2000 else if (sem->syncobj)
2001 counts->syncobj[syncobj_idx++] = sem->syncobj;
2002 else {
2003 assert(sem->sem);
2004 counts->sem[sem_idx++] = sem->sem;
2005 }
2006 }
2007
2008 return VK_SUCCESS;
2009 }
2010
2011 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2012 {
2013 free(sem_info->wait.syncobj);
2014 free(sem_info->wait.sem);
2015 free(sem_info->signal.syncobj);
2016 free(sem_info->signal.sem);
2017 }
2018
2019 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
2020 int num_wait_sems,
2021 const VkSemaphore *wait_sems,
2022 int num_signal_sems,
2023 const VkSemaphore *signal_sems)
2024 {
2025 VkResult ret;
2026 memset(sem_info, 0, sizeof(*sem_info));
2027
2028 ret = radv_alloc_sem_counts(&sem_info->wait, num_wait_sems, wait_sems, true);
2029 if (ret)
2030 return ret;
2031 ret = radv_alloc_sem_counts(&sem_info->signal, num_signal_sems, signal_sems, false);
2032 if (ret)
2033 radv_free_sem_info(sem_info);
2034
2035 /* caller can override these */
2036 sem_info->cs_emit_wait = true;
2037 sem_info->cs_emit_signal = true;
2038 return ret;
2039 }
2040
2041 VkResult radv_QueueSubmit(
2042 VkQueue _queue,
2043 uint32_t submitCount,
2044 const VkSubmitInfo* pSubmits,
2045 VkFence _fence)
2046 {
2047 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2048 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2049 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2050 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2051 int ret;
2052 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2053 uint32_t scratch_size = 0;
2054 uint32_t compute_scratch_size = 0;
2055 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2056 struct radeon_winsys_cs *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2057 VkResult result;
2058 bool fence_emitted = false;
2059 bool tess_rings_needed = false;
2060 bool sample_positions_needed = false;
2061
2062 /* Do this first so failing to allocate scratch buffers can't result in
2063 * partially executed submissions. */
2064 for (uint32_t i = 0; i < submitCount; i++) {
2065 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2066 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2067 pSubmits[i].pCommandBuffers[j]);
2068
2069 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2070 compute_scratch_size = MAX2(compute_scratch_size,
2071 cmd_buffer->compute_scratch_size_needed);
2072 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2073 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2074 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2075 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2076 }
2077 }
2078
2079 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2080 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2081 sample_positions_needed, &initial_flush_preamble_cs,
2082 &initial_preamble_cs, &continue_preamble_cs);
2083 if (result != VK_SUCCESS)
2084 return result;
2085
2086 for (uint32_t i = 0; i < submitCount; i++) {
2087 struct radeon_winsys_cs **cs_array;
2088 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2089 bool can_patch = true;
2090 uint32_t advance;
2091 struct radv_winsys_sem_info sem_info;
2092
2093 result = radv_alloc_sem_info(&sem_info,
2094 pSubmits[i].waitSemaphoreCount,
2095 pSubmits[i].pWaitSemaphores,
2096 pSubmits[i].signalSemaphoreCount,
2097 pSubmits[i].pSignalSemaphores);
2098 if (result != VK_SUCCESS)
2099 return result;
2100
2101 if (!pSubmits[i].commandBufferCount) {
2102 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2103 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2104 &queue->device->empty_cs[queue->queue_family_index],
2105 1, NULL, NULL,
2106 &sem_info,
2107 false, base_fence);
2108 if (ret) {
2109 radv_loge("failed to submit CS %d\n", i);
2110 abort();
2111 }
2112 fence_emitted = true;
2113 }
2114 radv_free_sem_info(&sem_info);
2115 continue;
2116 }
2117
2118 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
2119 (pSubmits[i].commandBufferCount));
2120
2121 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2122 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2123 pSubmits[i].pCommandBuffers[j]);
2124 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2125
2126 cs_array[j] = cmd_buffer->cs;
2127 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2128 can_patch = false;
2129 }
2130
2131 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2132 struct radeon_winsys_cs *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2133 advance = MIN2(max_cs_submission,
2134 pSubmits[i].commandBufferCount - j);
2135
2136 if (queue->device->trace_bo)
2137 *queue->device->trace_id_ptr = 0;
2138
2139 sem_info.cs_emit_wait = j == 0;
2140 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2141
2142 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2143 advance, initial_preamble, continue_preamble_cs,
2144 &sem_info,
2145 can_patch, base_fence);
2146
2147 if (ret) {
2148 radv_loge("failed to submit CS %d\n", i);
2149 abort();
2150 }
2151 fence_emitted = true;
2152 if (queue->device->trace_bo) {
2153 radv_check_gpu_hangs(queue, cs_array[j]);
2154 }
2155 }
2156
2157 radv_free_sem_info(&sem_info);
2158 free(cs_array);
2159 }
2160
2161 if (fence) {
2162 if (!fence_emitted) {
2163 struct radv_winsys_sem_info sem_info = {0};
2164 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2165 &queue->device->empty_cs[queue->queue_family_index],
2166 1, NULL, NULL, &sem_info,
2167 false, base_fence);
2168 }
2169 fence->submitted = true;
2170 }
2171
2172 return VK_SUCCESS;
2173 }
2174
2175 VkResult radv_QueueWaitIdle(
2176 VkQueue _queue)
2177 {
2178 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2179
2180 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2181 radv_queue_family_to_ring(queue->queue_family_index),
2182 queue->queue_idx);
2183 return VK_SUCCESS;
2184 }
2185
2186 VkResult radv_DeviceWaitIdle(
2187 VkDevice _device)
2188 {
2189 RADV_FROM_HANDLE(radv_device, device, _device);
2190
2191 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2192 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2193 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2194 }
2195 }
2196 return VK_SUCCESS;
2197 }
2198
2199 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2200 VkInstance instance,
2201 const char* pName)
2202 {
2203 return radv_lookup_entrypoint(pName);
2204 }
2205
2206 /* The loader wants us to expose a second GetInstanceProcAddr function
2207 * to work around certain LD_PRELOAD issues seen in apps.
2208 */
2209 PUBLIC
2210 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2211 VkInstance instance,
2212 const char* pName);
2213
2214 PUBLIC
2215 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2216 VkInstance instance,
2217 const char* pName)
2218 {
2219 return radv_GetInstanceProcAddr(instance, pName);
2220 }
2221
2222 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2223 VkDevice device,
2224 const char* pName)
2225 {
2226 return radv_lookup_entrypoint(pName);
2227 }
2228
2229 bool radv_get_memory_fd(struct radv_device *device,
2230 struct radv_device_memory *memory,
2231 int *pFD)
2232 {
2233 struct radeon_bo_metadata metadata;
2234
2235 if (memory->image) {
2236 radv_init_metadata(device, memory->image, &metadata);
2237 device->ws->buffer_set_metadata(memory->bo, &metadata);
2238 }
2239
2240 return device->ws->buffer_get_fd(device->ws, memory->bo,
2241 pFD);
2242 }
2243
2244 VkResult radv_AllocateMemory(
2245 VkDevice _device,
2246 const VkMemoryAllocateInfo* pAllocateInfo,
2247 const VkAllocationCallbacks* pAllocator,
2248 VkDeviceMemory* pMem)
2249 {
2250 RADV_FROM_HANDLE(radv_device, device, _device);
2251 struct radv_device_memory *mem;
2252 VkResult result;
2253 enum radeon_bo_domain domain;
2254 uint32_t flags = 0;
2255
2256 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2257
2258 if (pAllocateInfo->allocationSize == 0) {
2259 /* Apparently, this is allowed */
2260 *pMem = VK_NULL_HANDLE;
2261 return VK_SUCCESS;
2262 }
2263
2264 const VkImportMemoryFdInfoKHR *import_info =
2265 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2266 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2267 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2268
2269 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2270 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2271 if (mem == NULL)
2272 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2273
2274 if (dedicate_info) {
2275 mem->image = radv_image_from_handle(dedicate_info->image);
2276 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2277 } else {
2278 mem->image = NULL;
2279 mem->buffer = NULL;
2280 }
2281
2282 if (import_info) {
2283 assert(import_info->handleType ==
2284 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
2285 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2286 NULL, NULL);
2287 if (!mem->bo) {
2288 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2289 goto fail;
2290 } else {
2291 close(import_info->fd);
2292 goto out_success;
2293 }
2294 }
2295
2296 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2297 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2298 pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_CACHED)
2299 domain = RADEON_DOMAIN_GTT;
2300 else
2301 domain = RADEON_DOMAIN_VRAM;
2302
2303 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_VRAM)
2304 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2305 else
2306 flags |= RADEON_FLAG_CPU_ACCESS;
2307
2308 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2309 flags |= RADEON_FLAG_GTT_WC;
2310
2311 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2312 domain, flags);
2313
2314 if (!mem->bo) {
2315 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2316 goto fail;
2317 }
2318 mem->type_index = pAllocateInfo->memoryTypeIndex;
2319 out_success:
2320 *pMem = radv_device_memory_to_handle(mem);
2321
2322 return VK_SUCCESS;
2323
2324 fail:
2325 vk_free2(&device->alloc, pAllocator, mem);
2326
2327 return result;
2328 }
2329
2330 void radv_FreeMemory(
2331 VkDevice _device,
2332 VkDeviceMemory _mem,
2333 const VkAllocationCallbacks* pAllocator)
2334 {
2335 RADV_FROM_HANDLE(radv_device, device, _device);
2336 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2337
2338 if (mem == NULL)
2339 return;
2340
2341 device->ws->buffer_destroy(mem->bo);
2342 mem->bo = NULL;
2343
2344 vk_free2(&device->alloc, pAllocator, mem);
2345 }
2346
2347 VkResult radv_MapMemory(
2348 VkDevice _device,
2349 VkDeviceMemory _memory,
2350 VkDeviceSize offset,
2351 VkDeviceSize size,
2352 VkMemoryMapFlags flags,
2353 void** ppData)
2354 {
2355 RADV_FROM_HANDLE(radv_device, device, _device);
2356 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2357
2358 if (mem == NULL) {
2359 *ppData = NULL;
2360 return VK_SUCCESS;
2361 }
2362
2363 *ppData = device->ws->buffer_map(mem->bo);
2364 if (*ppData) {
2365 *ppData += offset;
2366 return VK_SUCCESS;
2367 }
2368
2369 return VK_ERROR_MEMORY_MAP_FAILED;
2370 }
2371
2372 void radv_UnmapMemory(
2373 VkDevice _device,
2374 VkDeviceMemory _memory)
2375 {
2376 RADV_FROM_HANDLE(radv_device, device, _device);
2377 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2378
2379 if (mem == NULL)
2380 return;
2381
2382 device->ws->buffer_unmap(mem->bo);
2383 }
2384
2385 VkResult radv_FlushMappedMemoryRanges(
2386 VkDevice _device,
2387 uint32_t memoryRangeCount,
2388 const VkMappedMemoryRange* pMemoryRanges)
2389 {
2390 return VK_SUCCESS;
2391 }
2392
2393 VkResult radv_InvalidateMappedMemoryRanges(
2394 VkDevice _device,
2395 uint32_t memoryRangeCount,
2396 const VkMappedMemoryRange* pMemoryRanges)
2397 {
2398 return VK_SUCCESS;
2399 }
2400
2401 void radv_GetBufferMemoryRequirements(
2402 VkDevice device,
2403 VkBuffer _buffer,
2404 VkMemoryRequirements* pMemoryRequirements)
2405 {
2406 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2407
2408 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
2409
2410 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2411 pMemoryRequirements->alignment = 4096;
2412 else
2413 pMemoryRequirements->alignment = 16;
2414
2415 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2416 }
2417
2418 void radv_GetBufferMemoryRequirements2KHR(
2419 VkDevice device,
2420 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
2421 VkMemoryRequirements2KHR* pMemoryRequirements)
2422 {
2423 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
2424 &pMemoryRequirements->memoryRequirements);
2425
2426 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2427 switch (ext->sType) {
2428 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2429 VkMemoryDedicatedRequirementsKHR *req =
2430 (VkMemoryDedicatedRequirementsKHR *) ext;
2431 req->requiresDedicatedAllocation = false;
2432 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2433 break;
2434 }
2435 default:
2436 break;
2437 }
2438 }
2439 }
2440
2441 void radv_GetImageMemoryRequirements(
2442 VkDevice device,
2443 VkImage _image,
2444 VkMemoryRequirements* pMemoryRequirements)
2445 {
2446 RADV_FROM_HANDLE(radv_image, image, _image);
2447
2448 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
2449
2450 pMemoryRequirements->size = image->size;
2451 pMemoryRequirements->alignment = image->alignment;
2452 }
2453
2454 void radv_GetImageMemoryRequirements2KHR(
2455 VkDevice device,
2456 const VkImageMemoryRequirementsInfo2KHR* pInfo,
2457 VkMemoryRequirements2KHR* pMemoryRequirements)
2458 {
2459 radv_GetImageMemoryRequirements(device, pInfo->image,
2460 &pMemoryRequirements->memoryRequirements);
2461
2462 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
2463
2464 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2465 switch (ext->sType) {
2466 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2467 VkMemoryDedicatedRequirementsKHR *req =
2468 (VkMemoryDedicatedRequirementsKHR *) ext;
2469 req->requiresDedicatedAllocation = image->shareable;
2470 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2471 break;
2472 }
2473 default:
2474 break;
2475 }
2476 }
2477 }
2478
2479 void radv_GetImageSparseMemoryRequirements(
2480 VkDevice device,
2481 VkImage image,
2482 uint32_t* pSparseMemoryRequirementCount,
2483 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
2484 {
2485 stub();
2486 }
2487
2488 void radv_GetImageSparseMemoryRequirements2KHR(
2489 VkDevice device,
2490 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
2491 uint32_t* pSparseMemoryRequirementCount,
2492 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
2493 {
2494 stub();
2495 }
2496
2497 void radv_GetDeviceMemoryCommitment(
2498 VkDevice device,
2499 VkDeviceMemory memory,
2500 VkDeviceSize* pCommittedMemoryInBytes)
2501 {
2502 *pCommittedMemoryInBytes = 0;
2503 }
2504
2505 VkResult radv_BindBufferMemory2KHR(VkDevice device,
2506 uint32_t bindInfoCount,
2507 const VkBindBufferMemoryInfoKHR *pBindInfos)
2508 {
2509 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2510 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
2511 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
2512
2513 if (mem) {
2514 buffer->bo = mem->bo;
2515 buffer->offset = pBindInfos[i].memoryOffset;
2516 } else {
2517 buffer->bo = NULL;
2518 }
2519 }
2520 return VK_SUCCESS;
2521 }
2522
2523 VkResult radv_BindBufferMemory(
2524 VkDevice device,
2525 VkBuffer buffer,
2526 VkDeviceMemory memory,
2527 VkDeviceSize memoryOffset)
2528 {
2529 const VkBindBufferMemoryInfoKHR info = {
2530 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
2531 .buffer = buffer,
2532 .memory = memory,
2533 .memoryOffset = memoryOffset
2534 };
2535
2536 return radv_BindBufferMemory2KHR(device, 1, &info);
2537 }
2538
2539 VkResult radv_BindImageMemory2KHR(VkDevice device,
2540 uint32_t bindInfoCount,
2541 const VkBindImageMemoryInfoKHR *pBindInfos)
2542 {
2543 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2544 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
2545 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
2546
2547 if (mem) {
2548 image->bo = mem->bo;
2549 image->offset = pBindInfos[i].memoryOffset;
2550 } else {
2551 image->bo = NULL;
2552 image->offset = 0;
2553 }
2554 }
2555 return VK_SUCCESS;
2556 }
2557
2558
2559 VkResult radv_BindImageMemory(
2560 VkDevice device,
2561 VkImage image,
2562 VkDeviceMemory memory,
2563 VkDeviceSize memoryOffset)
2564 {
2565 const VkBindImageMemoryInfoKHR info = {
2566 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
2567 .image = image,
2568 .memory = memory,
2569 .memoryOffset = memoryOffset
2570 };
2571
2572 return radv_BindImageMemory2KHR(device, 1, &info);
2573 }
2574
2575
2576 static void
2577 radv_sparse_buffer_bind_memory(struct radv_device *device,
2578 const VkSparseBufferMemoryBindInfo *bind)
2579 {
2580 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
2581
2582 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2583 struct radv_device_memory *mem = NULL;
2584
2585 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2586 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2587
2588 device->ws->buffer_virtual_bind(buffer->bo,
2589 bind->pBinds[i].resourceOffset,
2590 bind->pBinds[i].size,
2591 mem ? mem->bo : NULL,
2592 bind->pBinds[i].memoryOffset);
2593 }
2594 }
2595
2596 static void
2597 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
2598 const VkSparseImageOpaqueMemoryBindInfo *bind)
2599 {
2600 RADV_FROM_HANDLE(radv_image, image, bind->image);
2601
2602 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2603 struct radv_device_memory *mem = NULL;
2604
2605 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2606 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2607
2608 device->ws->buffer_virtual_bind(image->bo,
2609 bind->pBinds[i].resourceOffset,
2610 bind->pBinds[i].size,
2611 mem ? mem->bo : NULL,
2612 bind->pBinds[i].memoryOffset);
2613 }
2614 }
2615
2616 VkResult radv_QueueBindSparse(
2617 VkQueue _queue,
2618 uint32_t bindInfoCount,
2619 const VkBindSparseInfo* pBindInfo,
2620 VkFence _fence)
2621 {
2622 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2623 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2624 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2625 bool fence_emitted = false;
2626
2627 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2628 struct radv_winsys_sem_info sem_info;
2629 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
2630 radv_sparse_buffer_bind_memory(queue->device,
2631 pBindInfo[i].pBufferBinds + j);
2632 }
2633
2634 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
2635 radv_sparse_image_opaque_bind_memory(queue->device,
2636 pBindInfo[i].pImageOpaqueBinds + j);
2637 }
2638
2639 VkResult result;
2640 result = radv_alloc_sem_info(&sem_info,
2641 pBindInfo[i].waitSemaphoreCount,
2642 pBindInfo[i].pWaitSemaphores,
2643 pBindInfo[i].signalSemaphoreCount,
2644 pBindInfo[i].pSignalSemaphores);
2645 if (result != VK_SUCCESS)
2646 return result;
2647
2648 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
2649 queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2650 &queue->device->empty_cs[queue->queue_family_index],
2651 1, NULL, NULL,
2652 &sem_info,
2653 false, base_fence);
2654 fence_emitted = true;
2655 if (fence)
2656 fence->submitted = true;
2657 }
2658
2659 radv_free_sem_info(&sem_info);
2660
2661 }
2662
2663 if (fence && !fence_emitted) {
2664 fence->signalled = true;
2665 }
2666
2667 return VK_SUCCESS;
2668 }
2669
2670 VkResult radv_CreateFence(
2671 VkDevice _device,
2672 const VkFenceCreateInfo* pCreateInfo,
2673 const VkAllocationCallbacks* pAllocator,
2674 VkFence* pFence)
2675 {
2676 RADV_FROM_HANDLE(radv_device, device, _device);
2677 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
2678 sizeof(*fence), 8,
2679 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2680
2681 if (!fence)
2682 return VK_ERROR_OUT_OF_HOST_MEMORY;
2683
2684 memset(fence, 0, sizeof(*fence));
2685 fence->submitted = false;
2686 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
2687 fence->fence = device->ws->create_fence();
2688 if (!fence->fence) {
2689 vk_free2(&device->alloc, pAllocator, fence);
2690 return VK_ERROR_OUT_OF_HOST_MEMORY;
2691 }
2692
2693 *pFence = radv_fence_to_handle(fence);
2694
2695 return VK_SUCCESS;
2696 }
2697
2698 void radv_DestroyFence(
2699 VkDevice _device,
2700 VkFence _fence,
2701 const VkAllocationCallbacks* pAllocator)
2702 {
2703 RADV_FROM_HANDLE(radv_device, device, _device);
2704 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2705
2706 if (!fence)
2707 return;
2708 device->ws->destroy_fence(fence->fence);
2709 vk_free2(&device->alloc, pAllocator, fence);
2710 }
2711
2712 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
2713 {
2714 uint64_t current_time;
2715 struct timespec tv;
2716
2717 clock_gettime(CLOCK_MONOTONIC, &tv);
2718 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
2719
2720 timeout = MIN2(UINT64_MAX - current_time, timeout);
2721
2722 return current_time + timeout;
2723 }
2724
2725 VkResult radv_WaitForFences(
2726 VkDevice _device,
2727 uint32_t fenceCount,
2728 const VkFence* pFences,
2729 VkBool32 waitAll,
2730 uint64_t timeout)
2731 {
2732 RADV_FROM_HANDLE(radv_device, device, _device);
2733 timeout = radv_get_absolute_timeout(timeout);
2734
2735 if (!waitAll && fenceCount > 1) {
2736 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
2737 }
2738
2739 for (uint32_t i = 0; i < fenceCount; ++i) {
2740 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2741 bool expired = false;
2742
2743 if (fence->signalled)
2744 continue;
2745
2746 if (!fence->submitted)
2747 return VK_TIMEOUT;
2748
2749 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
2750 if (!expired)
2751 return VK_TIMEOUT;
2752
2753 fence->signalled = true;
2754 }
2755
2756 return VK_SUCCESS;
2757 }
2758
2759 VkResult radv_ResetFences(VkDevice device,
2760 uint32_t fenceCount,
2761 const VkFence *pFences)
2762 {
2763 for (unsigned i = 0; i < fenceCount; ++i) {
2764 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2765 fence->submitted = fence->signalled = false;
2766 }
2767
2768 return VK_SUCCESS;
2769 }
2770
2771 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
2772 {
2773 RADV_FROM_HANDLE(radv_device, device, _device);
2774 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2775
2776 if (fence->signalled)
2777 return VK_SUCCESS;
2778 if (!fence->submitted)
2779 return VK_NOT_READY;
2780
2781 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
2782 return VK_NOT_READY;
2783
2784 return VK_SUCCESS;
2785 }
2786
2787
2788 // Queue semaphore functions
2789
2790 VkResult radv_CreateSemaphore(
2791 VkDevice _device,
2792 const VkSemaphoreCreateInfo* pCreateInfo,
2793 const VkAllocationCallbacks* pAllocator,
2794 VkSemaphore* pSemaphore)
2795 {
2796 RADV_FROM_HANDLE(radv_device, device, _device);
2797 const VkExportSemaphoreCreateInfoKHR *export =
2798 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
2799 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
2800 export ? export->handleTypes : 0;
2801
2802 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
2803 sizeof(*sem), 8,
2804 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2805 if (!sem)
2806 return VK_ERROR_OUT_OF_HOST_MEMORY;
2807
2808 sem->temp_syncobj = 0;
2809 /* create a syncobject if we are going to export this semaphore */
2810 if (handleTypes) {
2811 assert (device->physical_device->rad_info.has_syncobj);
2812 assert (handleTypes == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
2813 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
2814 if (ret) {
2815 vk_free2(&device->alloc, pAllocator, sem);
2816 return VK_ERROR_OUT_OF_HOST_MEMORY;
2817 }
2818 sem->sem = NULL;
2819 } else {
2820 sem->sem = device->ws->create_sem(device->ws);
2821 if (!sem->sem) {
2822 vk_free2(&device->alloc, pAllocator, sem);
2823 return VK_ERROR_OUT_OF_HOST_MEMORY;
2824 }
2825 sem->syncobj = 0;
2826 }
2827
2828 *pSemaphore = radv_semaphore_to_handle(sem);
2829 return VK_SUCCESS;
2830 }
2831
2832 void radv_DestroySemaphore(
2833 VkDevice _device,
2834 VkSemaphore _semaphore,
2835 const VkAllocationCallbacks* pAllocator)
2836 {
2837 RADV_FROM_HANDLE(radv_device, device, _device);
2838 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
2839 if (!_semaphore)
2840 return;
2841
2842 if (sem->syncobj)
2843 device->ws->destroy_syncobj(device->ws, sem->syncobj);
2844 else
2845 device->ws->destroy_sem(sem->sem);
2846 vk_free2(&device->alloc, pAllocator, sem);
2847 }
2848
2849 VkResult radv_CreateEvent(
2850 VkDevice _device,
2851 const VkEventCreateInfo* pCreateInfo,
2852 const VkAllocationCallbacks* pAllocator,
2853 VkEvent* pEvent)
2854 {
2855 RADV_FROM_HANDLE(radv_device, device, _device);
2856 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
2857 sizeof(*event), 8,
2858 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2859
2860 if (!event)
2861 return VK_ERROR_OUT_OF_HOST_MEMORY;
2862
2863 event->bo = device->ws->buffer_create(device->ws, 8, 8,
2864 RADEON_DOMAIN_GTT,
2865 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS);
2866 if (!event->bo) {
2867 vk_free2(&device->alloc, pAllocator, event);
2868 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2869 }
2870
2871 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
2872
2873 *pEvent = radv_event_to_handle(event);
2874
2875 return VK_SUCCESS;
2876 }
2877
2878 void radv_DestroyEvent(
2879 VkDevice _device,
2880 VkEvent _event,
2881 const VkAllocationCallbacks* pAllocator)
2882 {
2883 RADV_FROM_HANDLE(radv_device, device, _device);
2884 RADV_FROM_HANDLE(radv_event, event, _event);
2885
2886 if (!event)
2887 return;
2888 device->ws->buffer_destroy(event->bo);
2889 vk_free2(&device->alloc, pAllocator, event);
2890 }
2891
2892 VkResult radv_GetEventStatus(
2893 VkDevice _device,
2894 VkEvent _event)
2895 {
2896 RADV_FROM_HANDLE(radv_event, event, _event);
2897
2898 if (*event->map == 1)
2899 return VK_EVENT_SET;
2900 return VK_EVENT_RESET;
2901 }
2902
2903 VkResult radv_SetEvent(
2904 VkDevice _device,
2905 VkEvent _event)
2906 {
2907 RADV_FROM_HANDLE(radv_event, event, _event);
2908 *event->map = 1;
2909
2910 return VK_SUCCESS;
2911 }
2912
2913 VkResult radv_ResetEvent(
2914 VkDevice _device,
2915 VkEvent _event)
2916 {
2917 RADV_FROM_HANDLE(radv_event, event, _event);
2918 *event->map = 0;
2919
2920 return VK_SUCCESS;
2921 }
2922
2923 VkResult radv_CreateBuffer(
2924 VkDevice _device,
2925 const VkBufferCreateInfo* pCreateInfo,
2926 const VkAllocationCallbacks* pAllocator,
2927 VkBuffer* pBuffer)
2928 {
2929 RADV_FROM_HANDLE(radv_device, device, _device);
2930 struct radv_buffer *buffer;
2931
2932 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
2933
2934 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
2935 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2936 if (buffer == NULL)
2937 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2938
2939 buffer->size = pCreateInfo->size;
2940 buffer->usage = pCreateInfo->usage;
2941 buffer->bo = NULL;
2942 buffer->offset = 0;
2943 buffer->flags = pCreateInfo->flags;
2944
2945 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
2946 buffer->bo = device->ws->buffer_create(device->ws,
2947 align64(buffer->size, 4096),
2948 4096, 0, RADEON_FLAG_VIRTUAL);
2949 if (!buffer->bo) {
2950 vk_free2(&device->alloc, pAllocator, buffer);
2951 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2952 }
2953 }
2954
2955 *pBuffer = radv_buffer_to_handle(buffer);
2956
2957 return VK_SUCCESS;
2958 }
2959
2960 void radv_DestroyBuffer(
2961 VkDevice _device,
2962 VkBuffer _buffer,
2963 const VkAllocationCallbacks* pAllocator)
2964 {
2965 RADV_FROM_HANDLE(radv_device, device, _device);
2966 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2967
2968 if (!buffer)
2969 return;
2970
2971 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2972 device->ws->buffer_destroy(buffer->bo);
2973
2974 vk_free2(&device->alloc, pAllocator, buffer);
2975 }
2976
2977 static inline unsigned
2978 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
2979 {
2980 if (stencil)
2981 return image->surface.u.legacy.stencil_tiling_index[level];
2982 else
2983 return image->surface.u.legacy.tiling_index[level];
2984 }
2985
2986 static uint32_t radv_surface_layer_count(struct radv_image_view *iview)
2987 {
2988 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : iview->layer_count;
2989 }
2990
2991 static void
2992 radv_initialise_color_surface(struct radv_device *device,
2993 struct radv_color_buffer_info *cb,
2994 struct radv_image_view *iview)
2995 {
2996 const struct vk_format_description *desc;
2997 unsigned ntype, format, swap, endian;
2998 unsigned blend_clamp = 0, blend_bypass = 0;
2999 uint64_t va;
3000 const struct radeon_surf *surf = &iview->image->surface;
3001
3002 desc = vk_format_description(iview->vk_format);
3003
3004 memset(cb, 0, sizeof(*cb));
3005
3006 /* Intensity is implemented as Red, so treat it that way. */
3007 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
3008
3009 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3010
3011 cb->cb_color_base = va >> 8;
3012
3013 if (device->physical_device->rad_info.chip_class >= GFX9) {
3014 struct gfx9_surf_meta_flags meta;
3015 if (iview->image->dcc_offset)
3016 meta = iview->image->surface.u.gfx9.dcc;
3017 else
3018 meta = iview->image->surface.u.gfx9.cmask;
3019
3020 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3021 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
3022 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3023 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3024
3025 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
3026 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3027 } else {
3028 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
3029 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3030
3031 cb->cb_color_base += level_info->offset >> 8;
3032 if (level_info->mode == RADEON_SURF_MODE_2D)
3033 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3034
3035 pitch_tile_max = level_info->nblk_x / 8 - 1;
3036 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
3037 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
3038
3039 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3040 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3041 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
3042
3043 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3044 cb->micro_tile_mode = iview->image->surface.micro_tile_mode;
3045
3046 if (iview->image->fmask.size) {
3047 if (device->physical_device->rad_info.chip_class >= CIK)
3048 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
3049 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
3050 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
3051 } else {
3052 /* This must be set for fast clear to work without FMASK. */
3053 if (device->physical_device->rad_info.chip_class >= CIK)
3054 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3055 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3056 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3057 }
3058 }
3059
3060 /* CMASK variables */
3061 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3062 va += iview->image->cmask.offset;
3063 cb->cb_color_cmask = va >> 8;
3064
3065 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3066 va += iview->image->dcc_offset;
3067 cb->cb_dcc_base = va >> 8;
3068 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
3069
3070 uint32_t max_slice = radv_surface_layer_count(iview);
3071 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
3072 S_028C6C_SLICE_MAX(iview->base_layer + max_slice - 1);
3073
3074 if (iview->image->info.samples > 1) {
3075 unsigned log_samples = util_logbase2(iview->image->info.samples);
3076
3077 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
3078 S_028C74_NUM_FRAGMENTS(log_samples);
3079 }
3080
3081 if (iview->image->fmask.size) {
3082 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
3083 cb->cb_color_fmask = va >> 8;
3084 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
3085 } else {
3086 cb->cb_color_fmask = cb->cb_color_base;
3087 }
3088
3089 ntype = radv_translate_color_numformat(iview->vk_format,
3090 desc,
3091 vk_format_get_first_non_void_channel(iview->vk_format));
3092 format = radv_translate_colorformat(iview->vk_format);
3093 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
3094 radv_finishme("Illegal color\n");
3095 swap = radv_translate_colorswap(iview->vk_format, FALSE);
3096 endian = radv_colorformat_endian_swap(format);
3097
3098 /* blend clamp should be set for all NORM/SRGB types */
3099 if (ntype == V_028C70_NUMBER_UNORM ||
3100 ntype == V_028C70_NUMBER_SNORM ||
3101 ntype == V_028C70_NUMBER_SRGB)
3102 blend_clamp = 1;
3103
3104 /* set blend bypass according to docs if SINT/UINT or
3105 8/24 COLOR variants */
3106 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
3107 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
3108 format == V_028C70_COLOR_X24_8_32_FLOAT) {
3109 blend_clamp = 0;
3110 blend_bypass = 1;
3111 }
3112 #if 0
3113 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
3114 (format == V_028C70_COLOR_8 ||
3115 format == V_028C70_COLOR_8_8 ||
3116 format == V_028C70_COLOR_8_8_8_8))
3117 ->color_is_int8 = true;
3118 #endif
3119 cb->cb_color_info = S_028C70_FORMAT(format) |
3120 S_028C70_COMP_SWAP(swap) |
3121 S_028C70_BLEND_CLAMP(blend_clamp) |
3122 S_028C70_BLEND_BYPASS(blend_bypass) |
3123 S_028C70_SIMPLE_FLOAT(1) |
3124 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
3125 ntype != V_028C70_NUMBER_SNORM &&
3126 ntype != V_028C70_NUMBER_SRGB &&
3127 format != V_028C70_COLOR_8_24 &&
3128 format != V_028C70_COLOR_24_8) |
3129 S_028C70_NUMBER_TYPE(ntype) |
3130 S_028C70_ENDIAN(endian);
3131 if ((iview->image->info.samples > 1) && iview->image->fmask.size) {
3132 cb->cb_color_info |= S_028C70_COMPRESSION(1);
3133 if (device->physical_device->rad_info.chip_class == SI) {
3134 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
3135 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
3136 }
3137 }
3138
3139 if (iview->image->cmask.size &&
3140 !(device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
3141 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
3142
3143 if (iview->image->surface.dcc_size && iview->base_mip < surf->num_dcc_levels)
3144 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
3145
3146 if (device->physical_device->rad_info.chip_class >= VI) {
3147 unsigned max_uncompressed_block_size = 2;
3148 if (iview->image->info.samples > 1) {
3149 if (iview->image->surface.bpe == 1)
3150 max_uncompressed_block_size = 0;
3151 else if (iview->image->surface.bpe == 2)
3152 max_uncompressed_block_size = 1;
3153 }
3154
3155 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3156 S_028C78_INDEPENDENT_64B_BLOCKS(1);
3157 }
3158
3159 /* This must be set for fast clear to work without FMASK. */
3160 if (!iview->image->fmask.size &&
3161 device->physical_device->rad_info.chip_class == SI) {
3162 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
3163 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
3164 }
3165
3166 if (device->physical_device->rad_info.chip_class >= GFX9) {
3167 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
3168 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
3169
3170 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
3171 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
3172 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
3173 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
3174 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
3175 S_028C68_MAX_MIP(iview->image->info.levels - 1);
3176
3177 cb->gfx9_epitch = S_0287A0_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3178
3179 }
3180 }
3181
3182 static void
3183 radv_initialise_ds_surface(struct radv_device *device,
3184 struct radv_ds_buffer_info *ds,
3185 struct radv_image_view *iview)
3186 {
3187 unsigned level = iview->base_mip;
3188 unsigned format, stencil_format;
3189 uint64_t va, s_offs, z_offs;
3190 bool stencil_only = false;
3191 memset(ds, 0, sizeof(*ds));
3192 switch (iview->image->vk_format) {
3193 case VK_FORMAT_D24_UNORM_S8_UINT:
3194 case VK_FORMAT_X8_D24_UNORM_PACK32:
3195 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
3196 ds->offset_scale = 2.0f;
3197 break;
3198 case VK_FORMAT_D16_UNORM:
3199 case VK_FORMAT_D16_UNORM_S8_UINT:
3200 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
3201 ds->offset_scale = 4.0f;
3202 break;
3203 case VK_FORMAT_D32_SFLOAT:
3204 case VK_FORMAT_D32_SFLOAT_S8_UINT:
3205 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
3206 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
3207 ds->offset_scale = 1.0f;
3208 break;
3209 case VK_FORMAT_S8_UINT:
3210 stencil_only = true;
3211 break;
3212 default:
3213 break;
3214 }
3215
3216 format = radv_translate_dbformat(iview->image->vk_format);
3217 stencil_format = iview->image->surface.has_stencil ?
3218 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
3219
3220 uint32_t max_slice = radv_surface_layer_count(iview);
3221 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
3222 S_028008_SLICE_MAX(iview->base_layer + max_slice - 1);
3223
3224 ds->db_htile_data_base = 0;
3225 ds->db_htile_surface = 0;
3226
3227 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3228 s_offs = z_offs = va;
3229
3230 if (device->physical_device->rad_info.chip_class >= GFX9) {
3231 assert(iview->image->surface.u.gfx9.surf_offset == 0);
3232 s_offs += iview->image->surface.u.gfx9.stencil_offset;
3233
3234 ds->db_z_info = S_028038_FORMAT(format) |
3235 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
3236 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3237 S_028038_MAXMIP(iview->image->info.levels - 1);
3238 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
3239 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
3240
3241 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3242 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
3243 ds->db_depth_view |= S_028008_MIPID(level);
3244
3245 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
3246 S_02801C_Y_MAX(iview->image->info.height - 1);
3247
3248 /* Only use HTILE for the first level. */
3249 if (iview->image->surface.htile_size && !level) {
3250 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
3251
3252 if (!iview->image->surface.has_stencil)
3253 /* Use all of the htile_buffer for depth if there's no stencil. */
3254 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
3255 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
3256 iview->image->htile_offset;
3257 ds->db_htile_data_base = va >> 8;
3258 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
3259 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
3260 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
3261 }
3262 } else {
3263 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
3264
3265 if (stencil_only)
3266 level_info = &iview->image->surface.u.legacy.stencil_level[level];
3267
3268 z_offs += iview->image->surface.u.legacy.level[level].offset;
3269 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
3270
3271 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
3272 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
3273 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
3274
3275 if (iview->image->info.samples > 1)
3276 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
3277
3278 if (device->physical_device->rad_info.chip_class >= CIK) {
3279 struct radeon_info *info = &device->physical_device->rad_info;
3280 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
3281 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
3282 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
3283 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
3284 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
3285 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
3286
3287 if (stencil_only)
3288 tile_mode = stencil_tile_mode;
3289
3290 ds->db_depth_info |=
3291 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
3292 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
3293 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
3294 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
3295 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
3296 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
3297 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
3298 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
3299 } else {
3300 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
3301 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3302 tile_mode_index = si_tile_mode_index(iview->image, level, true);
3303 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
3304 if (stencil_only)
3305 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3306 }
3307
3308 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
3309 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
3310 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
3311
3312 if (iview->image->surface.htile_size && !level) {
3313 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
3314
3315 if (!iview->image->surface.has_stencil)
3316 /* Use all of the htile_buffer for depth if there's no stencil. */
3317 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
3318
3319 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
3320 iview->image->htile_offset;
3321 ds->db_htile_data_base = va >> 8;
3322 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
3323 }
3324 }
3325
3326 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
3327 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
3328 }
3329
3330 VkResult radv_CreateFramebuffer(
3331 VkDevice _device,
3332 const VkFramebufferCreateInfo* pCreateInfo,
3333 const VkAllocationCallbacks* pAllocator,
3334 VkFramebuffer* pFramebuffer)
3335 {
3336 RADV_FROM_HANDLE(radv_device, device, _device);
3337 struct radv_framebuffer *framebuffer;
3338
3339 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
3340
3341 size_t size = sizeof(*framebuffer) +
3342 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
3343 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
3344 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3345 if (framebuffer == NULL)
3346 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3347
3348 framebuffer->attachment_count = pCreateInfo->attachmentCount;
3349 framebuffer->width = pCreateInfo->width;
3350 framebuffer->height = pCreateInfo->height;
3351 framebuffer->layers = pCreateInfo->layers;
3352 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
3353 VkImageView _iview = pCreateInfo->pAttachments[i];
3354 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
3355 framebuffer->attachments[i].attachment = iview;
3356 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
3357 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
3358 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3359 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
3360 }
3361 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
3362 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
3363 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_layer_count(iview));
3364 }
3365
3366 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
3367 return VK_SUCCESS;
3368 }
3369
3370 void radv_DestroyFramebuffer(
3371 VkDevice _device,
3372 VkFramebuffer _fb,
3373 const VkAllocationCallbacks* pAllocator)
3374 {
3375 RADV_FROM_HANDLE(radv_device, device, _device);
3376 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
3377
3378 if (!fb)
3379 return;
3380 vk_free2(&device->alloc, pAllocator, fb);
3381 }
3382
3383 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
3384 {
3385 switch (address_mode) {
3386 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
3387 return V_008F30_SQ_TEX_WRAP;
3388 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
3389 return V_008F30_SQ_TEX_MIRROR;
3390 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
3391 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
3392 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
3393 return V_008F30_SQ_TEX_CLAMP_BORDER;
3394 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
3395 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
3396 default:
3397 unreachable("illegal tex wrap mode");
3398 break;
3399 }
3400 }
3401
3402 static unsigned
3403 radv_tex_compare(VkCompareOp op)
3404 {
3405 switch (op) {
3406 case VK_COMPARE_OP_NEVER:
3407 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
3408 case VK_COMPARE_OP_LESS:
3409 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
3410 case VK_COMPARE_OP_EQUAL:
3411 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
3412 case VK_COMPARE_OP_LESS_OR_EQUAL:
3413 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
3414 case VK_COMPARE_OP_GREATER:
3415 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
3416 case VK_COMPARE_OP_NOT_EQUAL:
3417 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
3418 case VK_COMPARE_OP_GREATER_OR_EQUAL:
3419 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
3420 case VK_COMPARE_OP_ALWAYS:
3421 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
3422 default:
3423 unreachable("illegal compare mode");
3424 break;
3425 }
3426 }
3427
3428 static unsigned
3429 radv_tex_filter(VkFilter filter, unsigned max_ansio)
3430 {
3431 switch (filter) {
3432 case VK_FILTER_NEAREST:
3433 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
3434 V_008F38_SQ_TEX_XY_FILTER_POINT);
3435 case VK_FILTER_LINEAR:
3436 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
3437 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
3438 case VK_FILTER_CUBIC_IMG:
3439 default:
3440 fprintf(stderr, "illegal texture filter");
3441 return 0;
3442 }
3443 }
3444
3445 static unsigned
3446 radv_tex_mipfilter(VkSamplerMipmapMode mode)
3447 {
3448 switch (mode) {
3449 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
3450 return V_008F38_SQ_TEX_Z_FILTER_POINT;
3451 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
3452 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
3453 default:
3454 return V_008F38_SQ_TEX_Z_FILTER_NONE;
3455 }
3456 }
3457
3458 static unsigned
3459 radv_tex_bordercolor(VkBorderColor bcolor)
3460 {
3461 switch (bcolor) {
3462 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
3463 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
3464 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3465 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
3466 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
3467 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3468 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
3469 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
3470 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3471 default:
3472 break;
3473 }
3474 return 0;
3475 }
3476
3477 static unsigned
3478 radv_tex_aniso_filter(unsigned filter)
3479 {
3480 if (filter < 2)
3481 return 0;
3482 if (filter < 4)
3483 return 1;
3484 if (filter < 8)
3485 return 2;
3486 if (filter < 16)
3487 return 3;
3488 return 4;
3489 }
3490
3491 static void
3492 radv_init_sampler(struct radv_device *device,
3493 struct radv_sampler *sampler,
3494 const VkSamplerCreateInfo *pCreateInfo)
3495 {
3496 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
3497 (uint32_t) pCreateInfo->maxAnisotropy : 0;
3498 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
3499 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
3500
3501 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
3502 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
3503 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
3504 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3505 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
3506 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
3507 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3508 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3509 S_008F30_DISABLE_CUBE_WRAP(0) |
3510 S_008F30_COMPAT_MODE(is_vi));
3511 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
3512 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
3513 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3514 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
3515 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
3516 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
3517 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
3518 S_008F38_MIP_POINT_PRECLAMP(0) |
3519 S_008F38_DISABLE_LSB_CEIL(1) |
3520 S_008F38_FILTER_PREC_FIX(1) |
3521 S_008F38_ANISO_OVERRIDE(is_vi));
3522 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
3523 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
3524 }
3525
3526 VkResult radv_CreateSampler(
3527 VkDevice _device,
3528 const VkSamplerCreateInfo* pCreateInfo,
3529 const VkAllocationCallbacks* pAllocator,
3530 VkSampler* pSampler)
3531 {
3532 RADV_FROM_HANDLE(radv_device, device, _device);
3533 struct radv_sampler *sampler;
3534
3535 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
3536
3537 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
3538 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3539 if (!sampler)
3540 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3541
3542 radv_init_sampler(device, sampler, pCreateInfo);
3543 *pSampler = radv_sampler_to_handle(sampler);
3544
3545 return VK_SUCCESS;
3546 }
3547
3548 void radv_DestroySampler(
3549 VkDevice _device,
3550 VkSampler _sampler,
3551 const VkAllocationCallbacks* pAllocator)
3552 {
3553 RADV_FROM_HANDLE(radv_device, device, _device);
3554 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
3555
3556 if (!sampler)
3557 return;
3558 vk_free2(&device->alloc, pAllocator, sampler);
3559 }
3560
3561 /* vk_icd.h does not declare this function, so we declare it here to
3562 * suppress Wmissing-prototypes.
3563 */
3564 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3565 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
3566
3567 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3568 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
3569 {
3570 /* For the full details on loader interface versioning, see
3571 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
3572 * What follows is a condensed summary, to help you navigate the large and
3573 * confusing official doc.
3574 *
3575 * - Loader interface v0 is incompatible with later versions. We don't
3576 * support it.
3577 *
3578 * - In loader interface v1:
3579 * - The first ICD entrypoint called by the loader is
3580 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
3581 * entrypoint.
3582 * - The ICD must statically expose no other Vulkan symbol unless it is
3583 * linked with -Bsymbolic.
3584 * - Each dispatchable Vulkan handle created by the ICD must be
3585 * a pointer to a struct whose first member is VK_LOADER_DATA. The
3586 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
3587 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
3588 * vkDestroySurfaceKHR(). The ICD must be capable of working with
3589 * such loader-managed surfaces.
3590 *
3591 * - Loader interface v2 differs from v1 in:
3592 * - The first ICD entrypoint called by the loader is
3593 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
3594 * statically expose this entrypoint.
3595 *
3596 * - Loader interface v3 differs from v2 in:
3597 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
3598 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
3599 * because the loader no longer does so.
3600 */
3601 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
3602 return VK_SUCCESS;
3603 }
3604
3605 VkResult radv_GetMemoryFdKHR(VkDevice _device,
3606 const VkMemoryGetFdInfoKHR *pGetFdInfo,
3607 int *pFD)
3608 {
3609 RADV_FROM_HANDLE(radv_device, device, _device);
3610 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
3611
3612 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
3613
3614 /* We support only one handle type. */
3615 assert(pGetFdInfo->handleType ==
3616 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3617
3618 bool ret = radv_get_memory_fd(device, memory, pFD);
3619 if (ret == false)
3620 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
3621 return VK_SUCCESS;
3622 }
3623
3624 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
3625 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
3626 int fd,
3627 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
3628 {
3629 /* The valid usage section for this function says:
3630 *
3631 * "handleType must not be one of the handle types defined as opaque."
3632 *
3633 * Since we only handle opaque handles for now, there are no FD properties.
3634 */
3635 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
3636 }
3637
3638 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
3639 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
3640 {
3641 RADV_FROM_HANDLE(radv_device, device, _device);
3642 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
3643 uint32_t syncobj_handle = 0;
3644 assert(pImportSemaphoreFdInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3645
3646 int ret = device->ws->import_syncobj(device->ws, pImportSemaphoreFdInfo->fd, &syncobj_handle);
3647 if (ret != 0)
3648 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
3649
3650 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
3651 sem->temp_syncobj = syncobj_handle;
3652 } else {
3653 sem->syncobj = syncobj_handle;
3654 }
3655 close(pImportSemaphoreFdInfo->fd);
3656 return VK_SUCCESS;
3657 }
3658
3659 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
3660 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
3661 int *pFd)
3662 {
3663 RADV_FROM_HANDLE(radv_device, device, _device);
3664 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
3665 int ret;
3666 uint32_t syncobj_handle;
3667
3668 assert(pGetFdInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3669 if (sem->temp_syncobj)
3670 syncobj_handle = sem->temp_syncobj;
3671 else
3672 syncobj_handle = sem->syncobj;
3673 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
3674 if (ret)
3675 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3676 return VK_SUCCESS;
3677 }
3678
3679 void radv_GetPhysicalDeviceExternalSemaphorePropertiesKHR(
3680 VkPhysicalDevice physicalDevice,
3681 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
3682 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
3683 {
3684 if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
3685 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3686 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3687 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
3688 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
3689 } else {
3690 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
3691 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
3692 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
3693 }
3694 }