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7900ece9c8998db6fc1b64a81dd1b425f8e7fa0b
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <dlfcn.h>
29 #include <stdbool.h>
30 #include <string.h>
31 #include <unistd.h>
32 #include <fcntl.h>
33 #include <sys/stat.h>
34 #include "radv_private.h"
35 #include "radv_cs.h"
36 #include "util/strtod.h"
37
38 #include <xf86drm.h>
39 #include <amdgpu.h>
40 #include <amdgpu_drm.h>
41 #include "amdgpu_id.h"
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "util/debug.h"
47 struct radv_dispatch_table dtable;
48
49 static int
50 radv_get_function_timestamp(void *ptr, uint32_t* timestamp)
51 {
52 Dl_info info;
53 struct stat st;
54 if (!dladdr(ptr, &info) || !info.dli_fname) {
55 return -1;
56 }
57 if (stat(info.dli_fname, &st)) {
58 return -1;
59 }
60 *timestamp = st.st_mtim.tv_sec;
61 return 0;
62 }
63
64 static int
65 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
66 {
67 uint32_t mesa_timestamp, llvm_timestamp;
68 uint16_t f = family;
69 memset(uuid, 0, VK_UUID_SIZE);
70 if (radv_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
71 radv_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
72 return -1;
73
74 memcpy(uuid, &mesa_timestamp, 4);
75 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
76 memcpy((char*)uuid + 8, &f, 2);
77 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
78 return 0;
79 }
80
81 static const VkExtensionProperties instance_extensions[] = {
82 {
83 .extensionName = VK_KHR_SURFACE_EXTENSION_NAME,
84 .specVersion = 25,
85 },
86 #ifdef VK_USE_PLATFORM_XCB_KHR
87 {
88 .extensionName = VK_KHR_XCB_SURFACE_EXTENSION_NAME,
89 .specVersion = 6,
90 },
91 #endif
92 #ifdef VK_USE_PLATFORM_XLIB_KHR
93 {
94 .extensionName = VK_KHR_XLIB_SURFACE_EXTENSION_NAME,
95 .specVersion = 6,
96 },
97 #endif
98 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
99 {
100 .extensionName = VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME,
101 .specVersion = 5,
102 },
103 #endif
104 };
105
106 static const VkExtensionProperties common_device_extensions[] = {
107 {
108 .extensionName = VK_KHR_MAINTENANCE1_EXTENSION_NAME,
109 .specVersion = 1,
110 },
111 {
112 .extensionName = VK_KHR_SAMPLER_MIRROR_CLAMP_TO_EDGE_EXTENSION_NAME,
113 .specVersion = 1,
114 },
115 {
116 .extensionName = VK_KHR_SWAPCHAIN_EXTENSION_NAME,
117 .specVersion = 68,
118 },
119 {
120 .extensionName = VK_AMD_DRAW_INDIRECT_COUNT_EXTENSION_NAME,
121 .specVersion = 1,
122 },
123 {
124 .extensionName = VK_KHR_GET_PHYSICAL_DEVICE_PROPERTIES_2_EXTENSION_NAME,
125 .specVersion = 1,
126 },
127 {
128 .extensionName = VK_KHR_SHADER_DRAW_PARAMETERS_EXTENSION_NAME,
129 .specVersion = 1,
130 },
131 };
132
133 static VkResult
134 radv_extensions_register(struct radv_instance *instance,
135 struct radv_extensions *extensions,
136 const VkExtensionProperties *new_ext,
137 uint32_t num_ext)
138 {
139 size_t new_size;
140 VkExtensionProperties *new_ptr;
141
142 assert(new_ext && num_ext > 0);
143
144 if (!new_ext)
145 return VK_ERROR_INITIALIZATION_FAILED;
146
147 new_size = (extensions->num_ext + num_ext) * sizeof(VkExtensionProperties);
148 new_ptr = vk_realloc(&instance->alloc, extensions->ext_array,
149 new_size, 8, VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
150
151 /* Old array continues to be valid, update nothing */
152 if (!new_ptr)
153 return VK_ERROR_OUT_OF_HOST_MEMORY;
154
155 memcpy(&new_ptr[extensions->num_ext], new_ext,
156 num_ext * sizeof(VkExtensionProperties));
157 extensions->ext_array = new_ptr;
158 extensions->num_ext += num_ext;
159
160 return VK_SUCCESS;
161 }
162
163 static void
164 radv_extensions_finish(struct radv_instance *instance,
165 struct radv_extensions *extensions)
166 {
167 assert(extensions);
168
169 if (!extensions)
170 radv_loge("Attemted to free invalid extension struct\n");
171
172 if (extensions->ext_array)
173 vk_free(&instance->alloc, extensions->ext_array);
174 }
175
176 static bool
177 is_extension_enabled(const VkExtensionProperties *extensions,
178 size_t num_ext,
179 const char *name)
180 {
181 assert(extensions && name);
182
183 for (uint32_t i = 0; i < num_ext; i++) {
184 if (strcmp(name, extensions[i].extensionName) == 0)
185 return true;
186 }
187
188 return false;
189 }
190
191 static VkResult
192 radv_physical_device_init(struct radv_physical_device *device,
193 struct radv_instance *instance,
194 const char *path)
195 {
196 VkResult result;
197 drmVersionPtr version;
198 int fd;
199
200 fd = open(path, O_RDWR | O_CLOEXEC);
201 if (fd < 0)
202 return VK_ERROR_INCOMPATIBLE_DRIVER;
203
204 version = drmGetVersion(fd);
205 if (!version) {
206 close(fd);
207 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
208 "failed to get version %s: %m", path);
209 }
210
211 if (strcmp(version->name, "amdgpu")) {
212 drmFreeVersion(version);
213 close(fd);
214 return VK_ERROR_INCOMPATIBLE_DRIVER;
215 }
216 drmFreeVersion(version);
217
218 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
219 device->instance = instance;
220 assert(strlen(path) < ARRAY_SIZE(device->path));
221 strncpy(device->path, path, ARRAY_SIZE(device->path));
222
223 device->ws = radv_amdgpu_winsys_create(fd);
224 if (!device->ws) {
225 result = VK_ERROR_INCOMPATIBLE_DRIVER;
226 goto fail;
227 }
228 device->ws->query_info(device->ws, &device->rad_info);
229 result = radv_init_wsi(device);
230 if (result != VK_SUCCESS) {
231 device->ws->destroy(device->ws);
232 goto fail;
233 }
234
235 if (radv_device_get_cache_uuid(device->rad_info.family, device->uuid)) {
236 radv_finish_wsi(device);
237 device->ws->destroy(device->ws);
238 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
239 "cannot generate UUID");
240 goto fail;
241 }
242
243 result = radv_extensions_register(instance,
244 &device->extensions,
245 common_device_extensions,
246 ARRAY_SIZE(common_device_extensions));
247 if (result != VK_SUCCESS)
248 goto fail;
249
250 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
251 device->name = device->rad_info.name;
252 close(fd);
253 return VK_SUCCESS;
254
255 fail:
256 close(fd);
257 return result;
258 }
259
260 static void
261 radv_physical_device_finish(struct radv_physical_device *device)
262 {
263 radv_extensions_finish(device->instance, &device->extensions);
264 radv_finish_wsi(device);
265 device->ws->destroy(device->ws);
266 }
267
268
269 static void *
270 default_alloc_func(void *pUserData, size_t size, size_t align,
271 VkSystemAllocationScope allocationScope)
272 {
273 return malloc(size);
274 }
275
276 static void *
277 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
278 size_t align, VkSystemAllocationScope allocationScope)
279 {
280 return realloc(pOriginal, size);
281 }
282
283 static void
284 default_free_func(void *pUserData, void *pMemory)
285 {
286 free(pMemory);
287 }
288
289 static const VkAllocationCallbacks default_alloc = {
290 .pUserData = NULL,
291 .pfnAllocation = default_alloc_func,
292 .pfnReallocation = default_realloc_func,
293 .pfnFree = default_free_func,
294 };
295
296 static const struct debug_control radv_debug_options[] = {
297 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
298 {"nodcc", RADV_DEBUG_NO_DCC},
299 {"shaders", RADV_DEBUG_DUMP_SHADERS},
300 {"nocache", RADV_DEBUG_NO_CACHE},
301 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
302 {"nohiz", RADV_DEBUG_NO_HIZ},
303 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
304 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
305 {NULL, 0}
306 };
307
308 VkResult radv_CreateInstance(
309 const VkInstanceCreateInfo* pCreateInfo,
310 const VkAllocationCallbacks* pAllocator,
311 VkInstance* pInstance)
312 {
313 struct radv_instance *instance;
314
315 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
316
317 uint32_t client_version;
318 if (pCreateInfo->pApplicationInfo &&
319 pCreateInfo->pApplicationInfo->apiVersion != 0) {
320 client_version = pCreateInfo->pApplicationInfo->apiVersion;
321 } else {
322 client_version = VK_MAKE_VERSION(1, 0, 0);
323 }
324
325 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
326 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
327 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
328 "Client requested version %d.%d.%d",
329 VK_VERSION_MAJOR(client_version),
330 VK_VERSION_MINOR(client_version),
331 VK_VERSION_PATCH(client_version));
332 }
333
334 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
335 if (!is_extension_enabled(instance_extensions,
336 ARRAY_SIZE(instance_extensions),
337 pCreateInfo->ppEnabledExtensionNames[i]))
338 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
339 }
340
341 instance = vk_alloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
342 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
343 if (!instance)
344 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
345
346 memset(instance, 0, sizeof(*instance));
347
348 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
349
350 if (pAllocator)
351 instance->alloc = *pAllocator;
352 else
353 instance->alloc = default_alloc;
354
355 instance->apiVersion = client_version;
356 instance->physicalDeviceCount = -1;
357
358 _mesa_locale_init();
359
360 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
361
362 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
363 radv_debug_options);
364
365 *pInstance = radv_instance_to_handle(instance);
366
367 return VK_SUCCESS;
368 }
369
370 void radv_DestroyInstance(
371 VkInstance _instance,
372 const VkAllocationCallbacks* pAllocator)
373 {
374 RADV_FROM_HANDLE(radv_instance, instance, _instance);
375
376 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
377 radv_physical_device_finish(instance->physicalDevices + i);
378 }
379
380 VG(VALGRIND_DESTROY_MEMPOOL(instance));
381
382 _mesa_locale_fini();
383
384 vk_free(&instance->alloc, instance);
385 }
386
387 VkResult radv_EnumeratePhysicalDevices(
388 VkInstance _instance,
389 uint32_t* pPhysicalDeviceCount,
390 VkPhysicalDevice* pPhysicalDevices)
391 {
392 RADV_FROM_HANDLE(radv_instance, instance, _instance);
393 VkResult result;
394
395 if (instance->physicalDeviceCount < 0) {
396 char path[20];
397 instance->physicalDeviceCount = 0;
398 for (unsigned i = 0; i < RADV_MAX_DRM_DEVICES; i++) {
399 snprintf(path, sizeof(path), "/dev/dri/renderD%d", 128 + i);
400 result = radv_physical_device_init(instance->physicalDevices +
401 instance->physicalDeviceCount,
402 instance, path);
403 if (result == VK_SUCCESS)
404 ++instance->physicalDeviceCount;
405 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
406 return result;
407 }
408 }
409
410 if (!pPhysicalDevices) {
411 *pPhysicalDeviceCount = instance->physicalDeviceCount;
412 } else {
413 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
414 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
415 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
416 }
417
418 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
419 : VK_SUCCESS;
420 }
421
422 void radv_GetPhysicalDeviceFeatures(
423 VkPhysicalDevice physicalDevice,
424 VkPhysicalDeviceFeatures* pFeatures)
425 {
426 // RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
427
428 memset(pFeatures, 0, sizeof(*pFeatures));
429
430 *pFeatures = (VkPhysicalDeviceFeatures) {
431 .robustBufferAccess = true,
432 .fullDrawIndexUint32 = true,
433 .imageCubeArray = true,
434 .independentBlend = true,
435 .geometryShader = true,
436 .tessellationShader = false,
437 .sampleRateShading = false,
438 .dualSrcBlend = true,
439 .logicOp = true,
440 .multiDrawIndirect = true,
441 .drawIndirectFirstInstance = true,
442 .depthClamp = true,
443 .depthBiasClamp = true,
444 .fillModeNonSolid = true,
445 .depthBounds = true,
446 .wideLines = true,
447 .largePoints = true,
448 .alphaToOne = true,
449 .multiViewport = true,
450 .samplerAnisotropy = true,
451 .textureCompressionETC2 = false,
452 .textureCompressionASTC_LDR = false,
453 .textureCompressionBC = true,
454 .occlusionQueryPrecise = true,
455 .pipelineStatisticsQuery = false,
456 .vertexPipelineStoresAndAtomics = true,
457 .fragmentStoresAndAtomics = true,
458 .shaderTessellationAndGeometryPointSize = true,
459 .shaderImageGatherExtended = true,
460 .shaderStorageImageExtendedFormats = true,
461 .shaderStorageImageMultisample = false,
462 .shaderUniformBufferArrayDynamicIndexing = true,
463 .shaderSampledImageArrayDynamicIndexing = true,
464 .shaderStorageBufferArrayDynamicIndexing = true,
465 .shaderStorageImageArrayDynamicIndexing = true,
466 .shaderStorageImageReadWithoutFormat = true,
467 .shaderStorageImageWriteWithoutFormat = true,
468 .shaderClipDistance = true,
469 .shaderCullDistance = true,
470 .shaderFloat64 = true,
471 .shaderInt64 = false,
472 .shaderInt16 = false,
473 .alphaToOne = true,
474 .variableMultisampleRate = false,
475 .inheritedQueries = false,
476 };
477 }
478
479 void radv_GetPhysicalDeviceFeatures2KHR(
480 VkPhysicalDevice physicalDevice,
481 VkPhysicalDeviceFeatures2KHR *pFeatures)
482 {
483 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
484 }
485
486 void radv_GetPhysicalDeviceProperties(
487 VkPhysicalDevice physicalDevice,
488 VkPhysicalDeviceProperties* pProperties)
489 {
490 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
491 VkSampleCountFlags sample_counts = 0xf;
492 VkPhysicalDeviceLimits limits = {
493 .maxImageDimension1D = (1 << 14),
494 .maxImageDimension2D = (1 << 14),
495 .maxImageDimension3D = (1 << 11),
496 .maxImageDimensionCube = (1 << 14),
497 .maxImageArrayLayers = (1 << 11),
498 .maxTexelBufferElements = 128 * 1024 * 1024,
499 .maxUniformBufferRange = UINT32_MAX,
500 .maxStorageBufferRange = UINT32_MAX,
501 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
502 .maxMemoryAllocationCount = UINT32_MAX,
503 .maxSamplerAllocationCount = 64 * 1024,
504 .bufferImageGranularity = 64, /* A cache line */
505 .sparseAddressSpaceSize = 0,
506 .maxBoundDescriptorSets = MAX_SETS,
507 .maxPerStageDescriptorSamplers = 64,
508 .maxPerStageDescriptorUniformBuffers = 64,
509 .maxPerStageDescriptorStorageBuffers = 64,
510 .maxPerStageDescriptorSampledImages = 64,
511 .maxPerStageDescriptorStorageImages = 64,
512 .maxPerStageDescriptorInputAttachments = 64,
513 .maxPerStageResources = 128,
514 .maxDescriptorSetSamplers = 256,
515 .maxDescriptorSetUniformBuffers = 256,
516 .maxDescriptorSetUniformBuffersDynamic = 256,
517 .maxDescriptorSetStorageBuffers = 256,
518 .maxDescriptorSetStorageBuffersDynamic = 256,
519 .maxDescriptorSetSampledImages = 256,
520 .maxDescriptorSetStorageImages = 256,
521 .maxDescriptorSetInputAttachments = 256,
522 .maxVertexInputAttributes = 32,
523 .maxVertexInputBindings = 32,
524 .maxVertexInputAttributeOffset = 2047,
525 .maxVertexInputBindingStride = 2048,
526 .maxVertexOutputComponents = 128,
527 .maxTessellationGenerationLevel = 0,
528 .maxTessellationPatchSize = 0,
529 .maxTessellationControlPerVertexInputComponents = 0,
530 .maxTessellationControlPerVertexOutputComponents = 0,
531 .maxTessellationControlPerPatchOutputComponents = 0,
532 .maxTessellationControlTotalOutputComponents = 0,
533 .maxTessellationEvaluationInputComponents = 0,
534 .maxTessellationEvaluationOutputComponents = 0,
535 .maxGeometryShaderInvocations = 32,
536 .maxGeometryInputComponents = 64,
537 .maxGeometryOutputComponents = 128,
538 .maxGeometryOutputVertices = 256,
539 .maxGeometryTotalOutputComponents = 1024,
540 .maxFragmentInputComponents = 128,
541 .maxFragmentOutputAttachments = 8,
542 .maxFragmentDualSrcAttachments = 1,
543 .maxFragmentCombinedOutputResources = 8,
544 .maxComputeSharedMemorySize = 32768,
545 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
546 .maxComputeWorkGroupInvocations = 2048,
547 .maxComputeWorkGroupSize = {
548 2048,
549 2048,
550 2048
551 },
552 .subPixelPrecisionBits = 4 /* FIXME */,
553 .subTexelPrecisionBits = 4 /* FIXME */,
554 .mipmapPrecisionBits = 4 /* FIXME */,
555 .maxDrawIndexedIndexValue = UINT32_MAX,
556 .maxDrawIndirectCount = UINT32_MAX,
557 .maxSamplerLodBias = 16,
558 .maxSamplerAnisotropy = 16,
559 .maxViewports = MAX_VIEWPORTS,
560 .maxViewportDimensions = { (1 << 14), (1 << 14) },
561 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
562 .viewportSubPixelBits = 13, /* We take a float? */
563 .minMemoryMapAlignment = 4096, /* A page */
564 .minTexelBufferOffsetAlignment = 1,
565 .minUniformBufferOffsetAlignment = 4,
566 .minStorageBufferOffsetAlignment = 4,
567 .minTexelOffset = -32,
568 .maxTexelOffset = 31,
569 .minTexelGatherOffset = -32,
570 .maxTexelGatherOffset = 31,
571 .minInterpolationOffset = -2,
572 .maxInterpolationOffset = 2,
573 .subPixelInterpolationOffsetBits = 8,
574 .maxFramebufferWidth = (1 << 14),
575 .maxFramebufferHeight = (1 << 14),
576 .maxFramebufferLayers = (1 << 10),
577 .framebufferColorSampleCounts = sample_counts,
578 .framebufferDepthSampleCounts = sample_counts,
579 .framebufferStencilSampleCounts = sample_counts,
580 .framebufferNoAttachmentsSampleCounts = sample_counts,
581 .maxColorAttachments = MAX_RTS,
582 .sampledImageColorSampleCounts = sample_counts,
583 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
584 .sampledImageDepthSampleCounts = sample_counts,
585 .sampledImageStencilSampleCounts = sample_counts,
586 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
587 .maxSampleMaskWords = 1,
588 .timestampComputeAndGraphics = false,
589 .timestampPeriod = 100000.0 / pdevice->rad_info.clock_crystal_freq,
590 .maxClipDistances = 8,
591 .maxCullDistances = 8,
592 .maxCombinedClipAndCullDistances = 8,
593 .discreteQueuePriorities = 1,
594 .pointSizeRange = { 0.125, 255.875 },
595 .lineWidthRange = { 0.0, 7.9921875 },
596 .pointSizeGranularity = (1.0 / 8.0),
597 .lineWidthGranularity = (1.0 / 128.0),
598 .strictLines = false, /* FINISHME */
599 .standardSampleLocations = true,
600 .optimalBufferCopyOffsetAlignment = 128,
601 .optimalBufferCopyRowPitchAlignment = 128,
602 .nonCoherentAtomSize = 64,
603 };
604
605 *pProperties = (VkPhysicalDeviceProperties) {
606 .apiVersion = VK_MAKE_VERSION(1, 0, 5),
607 .driverVersion = 1,
608 .vendorID = 0x1002,
609 .deviceID = pdevice->rad_info.pci_id,
610 .deviceType = VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU,
611 .limits = limits,
612 .sparseProperties = {0}, /* Broadwell doesn't do sparse. */
613 };
614
615 strcpy(pProperties->deviceName, pdevice->name);
616 memcpy(pProperties->pipelineCacheUUID, pdevice->uuid, VK_UUID_SIZE);
617 }
618
619 void radv_GetPhysicalDeviceProperties2KHR(
620 VkPhysicalDevice physicalDevice,
621 VkPhysicalDeviceProperties2KHR *pProperties)
622 {
623 return radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
624 }
625
626 static void radv_get_physical_device_queue_family_properties(
627 struct radv_physical_device* pdevice,
628 uint32_t* pCount,
629 VkQueueFamilyProperties** pQueueFamilyProperties)
630 {
631 int num_queue_families = 1;
632 int idx;
633 if (pdevice->rad_info.compute_rings > 0 &&
634 pdevice->rad_info.chip_class >= CIK &&
635 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
636 num_queue_families++;
637
638 if (pQueueFamilyProperties == NULL) {
639 *pCount = num_queue_families;
640 return;
641 }
642
643 if (!*pCount)
644 return;
645
646 idx = 0;
647 if (*pCount >= 1) {
648 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
649 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
650 VK_QUEUE_COMPUTE_BIT |
651 VK_QUEUE_TRANSFER_BIT,
652 .queueCount = 1,
653 .timestampValidBits = 64,
654 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
655 };
656 idx++;
657 }
658
659 if (pdevice->rad_info.compute_rings > 0 &&
660 pdevice->rad_info.chip_class >= CIK &&
661 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
662 if (*pCount > idx) {
663 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
664 .queueFlags = VK_QUEUE_COMPUTE_BIT | VK_QUEUE_TRANSFER_BIT,
665 .queueCount = pdevice->rad_info.compute_rings,
666 .timestampValidBits = 64,
667 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
668 };
669 idx++;
670 }
671 }
672 *pCount = idx;
673 }
674
675 void radv_GetPhysicalDeviceQueueFamilyProperties(
676 VkPhysicalDevice physicalDevice,
677 uint32_t* pCount,
678 VkQueueFamilyProperties* pQueueFamilyProperties)
679 {
680 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
681 if (!pQueueFamilyProperties) {
682 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
683 return;
684 }
685 VkQueueFamilyProperties *properties[] = {
686 pQueueFamilyProperties + 0,
687 pQueueFamilyProperties + 1,
688 pQueueFamilyProperties + 2,
689 };
690 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
691 assert(*pCount <= 3);
692 }
693
694 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
695 VkPhysicalDevice physicalDevice,
696 uint32_t* pCount,
697 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
698 {
699 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
700 if (!pQueueFamilyProperties) {
701 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
702 return;
703 }
704 VkQueueFamilyProperties *properties[] = {
705 &pQueueFamilyProperties[0].queueFamilyProperties,
706 &pQueueFamilyProperties[1].queueFamilyProperties,
707 &pQueueFamilyProperties[2].queueFamilyProperties,
708 };
709 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
710 assert(*pCount <= 3);
711 }
712
713 void radv_GetPhysicalDeviceMemoryProperties(
714 VkPhysicalDevice physicalDevice,
715 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
716 {
717 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
718
719 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
720
721 pMemoryProperties->memoryTypeCount = RADV_MEM_TYPE_COUNT;
722 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM] = (VkMemoryType) {
723 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
724 .heapIndex = RADV_MEM_HEAP_VRAM,
725 };
726 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_WRITE_COMBINE] = (VkMemoryType) {
727 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
728 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
729 .heapIndex = RADV_MEM_HEAP_GTT,
730 };
731 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM_CPU_ACCESS] = (VkMemoryType) {
732 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
733 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
734 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
735 .heapIndex = RADV_MEM_HEAP_VRAM_CPU_ACCESS,
736 };
737 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_CACHED] = (VkMemoryType) {
738 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
739 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
740 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
741 .heapIndex = RADV_MEM_HEAP_GTT,
742 };
743
744 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
745
746 pMemoryProperties->memoryHeapCount = RADV_MEM_HEAP_COUNT;
747 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM] = (VkMemoryHeap) {
748 .size = physical_device->rad_info.vram_size -
749 physical_device->rad_info.visible_vram_size,
750 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
751 };
752 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = (VkMemoryHeap) {
753 .size = physical_device->rad_info.visible_vram_size,
754 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
755 };
756 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_GTT] = (VkMemoryHeap) {
757 .size = physical_device->rad_info.gart_size,
758 .flags = 0,
759 };
760 }
761
762 void radv_GetPhysicalDeviceMemoryProperties2KHR(
763 VkPhysicalDevice physicalDevice,
764 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
765 {
766 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
767 &pMemoryProperties->memoryProperties);
768 }
769
770 static int
771 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
772 int queue_family_index, int idx)
773 {
774 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
775 queue->device = device;
776 queue->queue_family_index = queue_family_index;
777 queue->queue_idx = idx;
778
779 queue->hw_ctx = device->ws->ctx_create(device->ws);
780 if (!queue->hw_ctx)
781 return VK_ERROR_OUT_OF_HOST_MEMORY;
782
783 return VK_SUCCESS;
784 }
785
786 static void
787 radv_queue_finish(struct radv_queue *queue)
788 {
789 if (queue->hw_ctx)
790 queue->device->ws->ctx_destroy(queue->hw_ctx);
791
792 if (queue->preamble_cs)
793 queue->device->ws->cs_destroy(queue->preamble_cs);
794 if (queue->descriptor_bo)
795 queue->device->ws->buffer_destroy(queue->descriptor_bo);
796 if (queue->scratch_bo)
797 queue->device->ws->buffer_destroy(queue->scratch_bo);
798 if (queue->esgs_ring_bo)
799 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
800 if (queue->gsvs_ring_bo)
801 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
802 if (queue->compute_scratch_bo)
803 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
804 }
805
806 static void
807 radv_device_init_gs_info(struct radv_device *device)
808 {
809 switch (device->physical_device->rad_info.family) {
810 case CHIP_OLAND:
811 case CHIP_HAINAN:
812 case CHIP_KAVERI:
813 case CHIP_KABINI:
814 case CHIP_MULLINS:
815 case CHIP_ICELAND:
816 case CHIP_CARRIZO:
817 case CHIP_STONEY:
818 device->gs_table_depth = 16;
819 return;
820 case CHIP_TAHITI:
821 case CHIP_PITCAIRN:
822 case CHIP_VERDE:
823 case CHIP_BONAIRE:
824 case CHIP_HAWAII:
825 case CHIP_TONGA:
826 case CHIP_FIJI:
827 case CHIP_POLARIS10:
828 case CHIP_POLARIS11:
829 device->gs_table_depth = 32;
830 return;
831 default:
832 unreachable("unknown GPU");
833 }
834 }
835
836 VkResult radv_CreateDevice(
837 VkPhysicalDevice physicalDevice,
838 const VkDeviceCreateInfo* pCreateInfo,
839 const VkAllocationCallbacks* pAllocator,
840 VkDevice* pDevice)
841 {
842 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
843 VkResult result;
844 struct radv_device *device;
845
846 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
847 if (!is_extension_enabled(physical_device->extensions.ext_array,
848 physical_device->extensions.num_ext,
849 pCreateInfo->ppEnabledExtensionNames[i]))
850 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
851 }
852
853 device = vk_alloc2(&physical_device->instance->alloc, pAllocator,
854 sizeof(*device), 8,
855 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
856 if (!device)
857 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
858
859 memset(device, 0, sizeof(*device));
860
861 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
862 device->instance = physical_device->instance;
863 device->physical_device = physical_device;
864
865 device->debug_flags = device->instance->debug_flags;
866
867 device->ws = physical_device->ws;
868 if (pAllocator)
869 device->alloc = *pAllocator;
870 else
871 device->alloc = physical_device->instance->alloc;
872
873 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
874 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
875 uint32_t qfi = queue_create->queueFamilyIndex;
876
877 device->queues[qfi] = vk_alloc(&device->alloc,
878 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
879 if (!device->queues[qfi]) {
880 result = VK_ERROR_OUT_OF_HOST_MEMORY;
881 goto fail;
882 }
883
884 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
885
886 device->queue_count[qfi] = queue_create->queueCount;
887
888 for (unsigned q = 0; q < queue_create->queueCount; q++) {
889 result = radv_queue_init(device, &device->queues[qfi][q], qfi, q);
890 if (result != VK_SUCCESS)
891 goto fail;
892 }
893 }
894
895 #if HAVE_LLVM < 0x0400
896 device->llvm_supports_spill = false;
897 #else
898 device->llvm_supports_spill = true;
899 #endif
900
901 /* The maximum number of scratch waves. Scratch space isn't divided
902 * evenly between CUs. The number is only a function of the number of CUs.
903 * We can decrease the constant to decrease the scratch buffer size.
904 *
905 * sctx->scratch_waves must be >= the maximum posible size of
906 * 1 threadgroup, so that the hw doesn't hang from being unable
907 * to start any.
908 *
909 * The recommended value is 4 per CU at most. Higher numbers don't
910 * bring much benefit, but they still occupy chip resources (think
911 * async compute). I've seen ~2% performance difference between 4 and 32.
912 */
913 uint32_t max_threads_per_block = 2048;
914 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
915 max_threads_per_block / 64);
916
917 radv_device_init_gs_info(device);
918
919 result = radv_device_init_meta(device);
920 if (result != VK_SUCCESS)
921 goto fail;
922
923 radv_device_init_msaa(device);
924
925 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
926 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
927 switch (family) {
928 case RADV_QUEUE_GENERAL:
929 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
930 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
931 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
932 break;
933 case RADV_QUEUE_COMPUTE:
934 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
935 radeon_emit(device->empty_cs[family], 0);
936 break;
937 }
938 device->ws->cs_finalize(device->empty_cs[family]);
939 }
940
941 if (getenv("RADV_TRACE_FILE")) {
942 device->trace_bo = device->ws->buffer_create(device->ws, 4096, 8,
943 RADEON_DOMAIN_VRAM, RADEON_FLAG_CPU_ACCESS);
944 if (!device->trace_bo)
945 goto fail;
946
947 device->trace_id_ptr = device->ws->buffer_map(device->trace_bo);
948 if (!device->trace_id_ptr)
949 goto fail;
950 }
951
952 if (device->physical_device->rad_info.chip_class >= CIK)
953 cik_create_gfx_config(device);
954
955 *pDevice = radv_device_to_handle(device);
956 return VK_SUCCESS;
957
958 fail:
959 if (device->trace_bo)
960 device->ws->buffer_destroy(device->trace_bo);
961
962 if (device->gfx_init)
963 device->ws->buffer_destroy(device->gfx_init);
964
965 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
966 for (unsigned q = 0; q < device->queue_count[i]; q++)
967 radv_queue_finish(&device->queues[i][q]);
968 if (device->queue_count[i])
969 vk_free(&device->alloc, device->queues[i]);
970 }
971
972 vk_free(&device->alloc, device);
973 return result;
974 }
975
976 void radv_DestroyDevice(
977 VkDevice _device,
978 const VkAllocationCallbacks* pAllocator)
979 {
980 RADV_FROM_HANDLE(radv_device, device, _device);
981
982 if (device->trace_bo)
983 device->ws->buffer_destroy(device->trace_bo);
984
985 if (device->gfx_init)
986 device->ws->buffer_destroy(device->gfx_init);
987
988 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
989 for (unsigned q = 0; q < device->queue_count[i]; q++)
990 radv_queue_finish(&device->queues[i][q]);
991 if (device->queue_count[i])
992 vk_free(&device->alloc, device->queues[i]);
993 }
994 radv_device_finish_meta(device);
995
996 vk_free(&device->alloc, device);
997 }
998
999 VkResult radv_EnumerateInstanceExtensionProperties(
1000 const char* pLayerName,
1001 uint32_t* pPropertyCount,
1002 VkExtensionProperties* pProperties)
1003 {
1004 if (pProperties == NULL) {
1005 *pPropertyCount = ARRAY_SIZE(instance_extensions);
1006 return VK_SUCCESS;
1007 }
1008
1009 *pPropertyCount = MIN2(*pPropertyCount, ARRAY_SIZE(instance_extensions));
1010 typed_memcpy(pProperties, instance_extensions, *pPropertyCount);
1011
1012 if (*pPropertyCount < ARRAY_SIZE(instance_extensions))
1013 return VK_INCOMPLETE;
1014
1015 return VK_SUCCESS;
1016 }
1017
1018 VkResult radv_EnumerateDeviceExtensionProperties(
1019 VkPhysicalDevice physicalDevice,
1020 const char* pLayerName,
1021 uint32_t* pPropertyCount,
1022 VkExtensionProperties* pProperties)
1023 {
1024 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1025
1026 if (pProperties == NULL) {
1027 *pPropertyCount = pdevice->extensions.num_ext;
1028 return VK_SUCCESS;
1029 }
1030
1031 *pPropertyCount = MIN2(*pPropertyCount, pdevice->extensions.num_ext);
1032 typed_memcpy(pProperties, pdevice->extensions.ext_array, *pPropertyCount);
1033
1034 if (*pPropertyCount < pdevice->extensions.num_ext)
1035 return VK_INCOMPLETE;
1036
1037 return VK_SUCCESS;
1038 }
1039
1040 VkResult radv_EnumerateInstanceLayerProperties(
1041 uint32_t* pPropertyCount,
1042 VkLayerProperties* pProperties)
1043 {
1044 if (pProperties == NULL) {
1045 *pPropertyCount = 0;
1046 return VK_SUCCESS;
1047 }
1048
1049 /* None supported at this time */
1050 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1051 }
1052
1053 VkResult radv_EnumerateDeviceLayerProperties(
1054 VkPhysicalDevice physicalDevice,
1055 uint32_t* pPropertyCount,
1056 VkLayerProperties* pProperties)
1057 {
1058 if (pProperties == NULL) {
1059 *pPropertyCount = 0;
1060 return VK_SUCCESS;
1061 }
1062
1063 /* None supported at this time */
1064 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1065 }
1066
1067 void radv_GetDeviceQueue(
1068 VkDevice _device,
1069 uint32_t queueFamilyIndex,
1070 uint32_t queueIndex,
1071 VkQueue* pQueue)
1072 {
1073 RADV_FROM_HANDLE(radv_device, device, _device);
1074
1075 *pQueue = radv_queue_to_handle(&device->queues[queueFamilyIndex][queueIndex]);
1076 }
1077
1078 static void radv_dump_trace(struct radv_device *device,
1079 struct radeon_winsys_cs *cs)
1080 {
1081 const char *filename = getenv("RADV_TRACE_FILE");
1082 FILE *f = fopen(filename, "w");
1083 if (!f) {
1084 fprintf(stderr, "Failed to write trace dump to %s\n", filename);
1085 return;
1086 }
1087
1088 fprintf(f, "Trace ID: %x\n", *device->trace_id_ptr);
1089 device->ws->cs_dump(cs, f, *device->trace_id_ptr);
1090 fclose(f);
1091 }
1092
1093 static void
1094 fill_geom_rings(struct radv_queue *queue,
1095 uint32_t *map,
1096 uint32_t esgs_ring_size,
1097 struct radeon_winsys_bo *esgs_ring_bo,
1098 uint32_t gsvs_ring_size,
1099 struct radeon_winsys_bo *gsvs_ring_bo)
1100 {
1101 uint64_t esgs_va = 0, gsvs_va = 0;
1102 uint32_t *desc = &map[4];
1103
1104 if (esgs_ring_bo)
1105 esgs_va = queue->device->ws->buffer_get_va(esgs_ring_bo);
1106 if (gsvs_ring_bo)
1107 gsvs_va = queue->device->ws->buffer_get_va(gsvs_ring_bo);
1108
1109 /* stride 0, num records - size, add tid, swizzle, elsize4,
1110 index stride 64 */
1111 desc[0] = esgs_va;
1112 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1113 S_008F04_STRIDE(0) |
1114 S_008F04_SWIZZLE_ENABLE(true);
1115 desc[2] = esgs_ring_size;
1116 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1117 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1118 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1119 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1120 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1121 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1122 S_008F0C_ELEMENT_SIZE(1) |
1123 S_008F0C_INDEX_STRIDE(3) |
1124 S_008F0C_ADD_TID_ENABLE(true);
1125
1126 desc += 4;
1127 /* GS entry for ES->GS ring */
1128 /* stride 0, num records - size, elsize0,
1129 index stride 0 */
1130 desc[0] = esgs_va;
1131 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1132 S_008F04_STRIDE(0) |
1133 S_008F04_SWIZZLE_ENABLE(false);
1134 desc[2] = esgs_ring_size;
1135 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1136 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1137 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1138 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1139 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1140 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1141 S_008F0C_ELEMENT_SIZE(0) |
1142 S_008F0C_INDEX_STRIDE(0) |
1143 S_008F0C_ADD_TID_ENABLE(false);
1144
1145 desc += 4;
1146 /* VS entry for GS->VS ring */
1147 /* stride 0, num records - size, elsize0,
1148 index stride 0 */
1149 desc[0] = gsvs_va;
1150 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1151 S_008F04_STRIDE(0) |
1152 S_008F04_SWIZZLE_ENABLE(false);
1153 desc[2] = gsvs_ring_size;
1154 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1155 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1156 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1157 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1158 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1159 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1160 S_008F0C_ELEMENT_SIZE(0) |
1161 S_008F0C_INDEX_STRIDE(0) |
1162 S_008F0C_ADD_TID_ENABLE(false);
1163 desc += 4;
1164
1165 /* stride gsvs_itemsize, num records 64
1166 elsize 4, index stride 16 */
1167 /* shader will patch stride and desc[2] */
1168 desc[0] = gsvs_va;
1169 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1170 S_008F04_STRIDE(0) |
1171 S_008F04_SWIZZLE_ENABLE(true);
1172 desc[2] = 0;
1173 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1174 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1175 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1176 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1177 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1178 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1179 S_008F0C_ELEMENT_SIZE(1) |
1180 S_008F0C_INDEX_STRIDE(1) |
1181 S_008F0C_ADD_TID_ENABLE(true);
1182 }
1183
1184 static VkResult
1185 radv_get_preamble_cs(struct radv_queue *queue,
1186 uint32_t scratch_size,
1187 uint32_t compute_scratch_size,
1188 uint32_t esgs_ring_size,
1189 uint32_t gsvs_ring_size,
1190 struct radeon_winsys_cs **preamble_cs)
1191 {
1192 struct radeon_winsys_bo *scratch_bo = NULL;
1193 struct radeon_winsys_bo *descriptor_bo = NULL;
1194 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1195 struct radeon_winsys_bo *esgs_ring_bo = NULL;
1196 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
1197 struct radeon_winsys_cs *cs = NULL;
1198
1199 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size) {
1200 *preamble_cs = NULL;
1201 return VK_SUCCESS;
1202 }
1203
1204 if (scratch_size <= queue->scratch_size &&
1205 compute_scratch_size <= queue->compute_scratch_size &&
1206 esgs_ring_size <= queue->esgs_ring_size &&
1207 gsvs_ring_size <= queue->gsvs_ring_size) {
1208 *preamble_cs = queue->preamble_cs;
1209 return VK_SUCCESS;
1210 }
1211
1212 if (scratch_size > queue->scratch_size) {
1213 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1214 scratch_size,
1215 4096,
1216 RADEON_DOMAIN_VRAM,
1217 RADEON_FLAG_NO_CPU_ACCESS);
1218 if (!scratch_bo)
1219 goto fail;
1220 } else
1221 scratch_bo = queue->scratch_bo;
1222
1223 if (compute_scratch_size > queue->compute_scratch_size) {
1224 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1225 compute_scratch_size,
1226 4096,
1227 RADEON_DOMAIN_VRAM,
1228 RADEON_FLAG_NO_CPU_ACCESS);
1229 if (!compute_scratch_bo)
1230 goto fail;
1231
1232 } else
1233 compute_scratch_bo = queue->compute_scratch_bo;
1234
1235 if (esgs_ring_size > queue->esgs_ring_size) {
1236 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1237 esgs_ring_size,
1238 4096,
1239 RADEON_DOMAIN_VRAM,
1240 RADEON_FLAG_NO_CPU_ACCESS);
1241 if (!esgs_ring_bo)
1242 goto fail;
1243 } else {
1244 esgs_ring_bo = queue->esgs_ring_bo;
1245 esgs_ring_size = queue->esgs_ring_size;
1246 }
1247
1248 if (gsvs_ring_size > queue->gsvs_ring_size) {
1249 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1250 gsvs_ring_size,
1251 4096,
1252 RADEON_DOMAIN_VRAM,
1253 RADEON_FLAG_NO_CPU_ACCESS);
1254 if (!gsvs_ring_bo)
1255 goto fail;
1256 } else {
1257 gsvs_ring_bo = queue->gsvs_ring_bo;
1258 gsvs_ring_size = queue->gsvs_ring_size;
1259 }
1260
1261 if (scratch_bo != queue->scratch_bo ||
1262 esgs_ring_bo != queue->esgs_ring_bo ||
1263 gsvs_ring_bo != queue->gsvs_ring_bo) {
1264 uint32_t size = 0;
1265 if (gsvs_ring_bo || esgs_ring_bo)
1266 size = 80; /* 2 dword + 2 padding + 4 dword * 4 */
1267 else if (scratch_bo)
1268 size = 8; /* 2 dword */
1269
1270 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
1271 size,
1272 4096,
1273 RADEON_DOMAIN_VRAM,
1274 RADEON_FLAG_CPU_ACCESS);
1275 if (!descriptor_bo)
1276 goto fail;
1277 } else
1278 descriptor_bo = queue->descriptor_bo;
1279
1280 cs = queue->device->ws->cs_create(queue->device->ws,
1281 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
1282 if (!cs)
1283 goto fail;
1284
1285
1286 if (scratch_bo)
1287 queue->device->ws->cs_add_buffer(cs, scratch_bo, 8);
1288
1289 if (esgs_ring_bo)
1290 queue->device->ws->cs_add_buffer(cs, esgs_ring_bo, 8);
1291
1292 if (gsvs_ring_bo)
1293 queue->device->ws->cs_add_buffer(cs, gsvs_ring_bo, 8);
1294
1295 if (descriptor_bo)
1296 queue->device->ws->cs_add_buffer(cs, descriptor_bo, 8);
1297
1298 if (descriptor_bo != queue->descriptor_bo) {
1299 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
1300
1301 if (scratch_bo) {
1302 uint64_t scratch_va = queue->device->ws->buffer_get_va(scratch_bo);
1303 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1304 S_008F04_SWIZZLE_ENABLE(1);
1305 map[0] = scratch_va;
1306 map[1] = rsrc1;
1307 }
1308
1309 if (esgs_ring_bo || gsvs_ring_bo)
1310 fill_geom_rings(queue, map, esgs_ring_size, esgs_ring_bo, gsvs_ring_size, gsvs_ring_bo);
1311
1312 queue->device->ws->buffer_unmap(descriptor_bo);
1313 }
1314
1315 if (esgs_ring_bo || gsvs_ring_bo) {
1316 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1317 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1318 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1319 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1320
1321 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1322 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1323 radeon_emit(cs, esgs_ring_size >> 8);
1324 radeon_emit(cs, gsvs_ring_size >> 8);
1325 } else {
1326 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1327 radeon_emit(cs, esgs_ring_size >> 8);
1328 radeon_emit(cs, gsvs_ring_size >> 8);
1329 }
1330 }
1331
1332 if (descriptor_bo) {
1333 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1334 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1335 R_00B230_SPI_SHADER_USER_DATA_GS_0,
1336 R_00B330_SPI_SHADER_USER_DATA_ES_0,
1337 R_00B430_SPI_SHADER_USER_DATA_HS_0,
1338 R_00B530_SPI_SHADER_USER_DATA_LS_0};
1339
1340 uint64_t va = queue->device->ws->buffer_get_va(descriptor_bo);
1341
1342 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1343 radeon_set_sh_reg_seq(cs, regs[i], 2);
1344 radeon_emit(cs, va);
1345 radeon_emit(cs, va >> 32);
1346 }
1347 }
1348
1349 if (compute_scratch_bo) {
1350 uint64_t scratch_va = queue->device->ws->buffer_get_va(compute_scratch_bo);
1351 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1352 S_008F04_SWIZZLE_ENABLE(1);
1353
1354 queue->device->ws->cs_add_buffer(cs, compute_scratch_bo, 8);
1355
1356 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
1357 radeon_emit(cs, scratch_va);
1358 radeon_emit(cs, rsrc1);
1359 }
1360
1361 if (!queue->device->ws->cs_finalize(cs))
1362 goto fail;
1363
1364 if (queue->preamble_cs)
1365 queue->device->ws->cs_destroy(queue->preamble_cs);
1366
1367 queue->preamble_cs = cs;
1368
1369 if (scratch_bo != queue->scratch_bo) {
1370 if (queue->scratch_bo)
1371 queue->device->ws->buffer_destroy(queue->scratch_bo);
1372 queue->scratch_bo = scratch_bo;
1373 queue->scratch_size = scratch_size;
1374 }
1375
1376 if (compute_scratch_bo != queue->compute_scratch_bo) {
1377 if (queue->compute_scratch_bo)
1378 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1379 queue->compute_scratch_bo = compute_scratch_bo;
1380 queue->compute_scratch_size = compute_scratch_size;
1381 }
1382
1383 if (esgs_ring_bo != queue->esgs_ring_bo) {
1384 if (queue->esgs_ring_bo)
1385 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1386 queue->esgs_ring_bo = esgs_ring_bo;
1387 queue->esgs_ring_size = esgs_ring_size;
1388 }
1389
1390 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
1391 if (queue->gsvs_ring_bo)
1392 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1393 queue->gsvs_ring_bo = gsvs_ring_bo;
1394 queue->gsvs_ring_size = gsvs_ring_size;
1395 }
1396
1397 if (descriptor_bo != queue->descriptor_bo) {
1398 if (queue->descriptor_bo)
1399 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1400
1401 queue->descriptor_bo = descriptor_bo;
1402 }
1403
1404 *preamble_cs = cs;
1405 return VK_SUCCESS;
1406 fail:
1407 if (cs)
1408 queue->device->ws->cs_destroy(cs);
1409 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
1410 queue->device->ws->buffer_destroy(descriptor_bo);
1411 if (scratch_bo && scratch_bo != queue->scratch_bo)
1412 queue->device->ws->buffer_destroy(scratch_bo);
1413 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
1414 queue->device->ws->buffer_destroy(compute_scratch_bo);
1415 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
1416 queue->device->ws->buffer_destroy(esgs_ring_bo);
1417 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
1418 queue->device->ws->buffer_destroy(gsvs_ring_bo);
1419 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1420 }
1421
1422 VkResult radv_QueueSubmit(
1423 VkQueue _queue,
1424 uint32_t submitCount,
1425 const VkSubmitInfo* pSubmits,
1426 VkFence _fence)
1427 {
1428 RADV_FROM_HANDLE(radv_queue, queue, _queue);
1429 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1430 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
1431 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
1432 int ret;
1433 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
1434 uint32_t scratch_size = 0;
1435 uint32_t compute_scratch_size = 0;
1436 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
1437 struct radeon_winsys_cs *preamble_cs = NULL;
1438 VkResult result;
1439 bool fence_emitted = false;
1440
1441 /* Do this first so failing to allocate scratch buffers can't result in
1442 * partially executed submissions. */
1443 for (uint32_t i = 0; i < submitCount; i++) {
1444 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
1445 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
1446 pSubmits[i].pCommandBuffers[j]);
1447
1448 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
1449 compute_scratch_size = MAX2(compute_scratch_size,
1450 cmd_buffer->compute_scratch_size_needed);
1451 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
1452 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
1453 }
1454 }
1455
1456 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size, esgs_ring_size, gsvs_ring_size, &preamble_cs);
1457 if (result != VK_SUCCESS)
1458 return result;
1459
1460 for (uint32_t i = 0; i < submitCount; i++) {
1461 struct radeon_winsys_cs **cs_array;
1462 bool can_patch = true;
1463 uint32_t advance;
1464
1465 if (!pSubmits[i].commandBufferCount) {
1466 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
1467 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
1468 &queue->device->empty_cs[queue->queue_family_index],
1469 1, NULL,
1470 (struct radeon_winsys_sem **)pSubmits[i].pWaitSemaphores,
1471 pSubmits[i].waitSemaphoreCount,
1472 (struct radeon_winsys_sem **)pSubmits[i].pSignalSemaphores,
1473 pSubmits[i].signalSemaphoreCount,
1474 false, base_fence);
1475 if (ret) {
1476 radv_loge("failed to submit CS %d\n", i);
1477 abort();
1478 }
1479 fence_emitted = true;
1480 }
1481 continue;
1482 }
1483
1484 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
1485 pSubmits[i].commandBufferCount);
1486
1487 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
1488 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
1489 pSubmits[i].pCommandBuffers[j]);
1490 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
1491
1492 cs_array[j] = cmd_buffer->cs;
1493 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
1494 can_patch = false;
1495 }
1496
1497 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
1498 advance = MIN2(max_cs_submission,
1499 pSubmits[i].commandBufferCount - j);
1500 bool b = j == 0;
1501 bool e = j + advance == pSubmits[i].commandBufferCount;
1502
1503 if (queue->device->trace_bo)
1504 *queue->device->trace_id_ptr = 0;
1505
1506 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
1507 advance, preamble_cs,
1508 (struct radeon_winsys_sem **)pSubmits[i].pWaitSemaphores,
1509 b ? pSubmits[i].waitSemaphoreCount : 0,
1510 (struct radeon_winsys_sem **)pSubmits[i].pSignalSemaphores,
1511 e ? pSubmits[i].signalSemaphoreCount : 0,
1512 can_patch, base_fence);
1513
1514 if (ret) {
1515 radv_loge("failed to submit CS %d\n", i);
1516 abort();
1517 }
1518 fence_emitted = true;
1519 if (queue->device->trace_bo) {
1520 bool success = queue->device->ws->ctx_wait_idle(
1521 queue->hw_ctx,
1522 radv_queue_family_to_ring(
1523 queue->queue_family_index),
1524 queue->queue_idx);
1525
1526 if (!success) { /* Hang */
1527 radv_dump_trace(queue->device, cs_array[j]);
1528 abort();
1529 }
1530 }
1531 }
1532 free(cs_array);
1533 }
1534
1535 if (fence) {
1536 if (!fence_emitted)
1537 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
1538 &queue->device->empty_cs[queue->queue_family_index],
1539 1, NULL, NULL, 0, NULL, 0,
1540 false, base_fence);
1541
1542 fence->submitted = true;
1543 }
1544
1545 return VK_SUCCESS;
1546 }
1547
1548 VkResult radv_QueueWaitIdle(
1549 VkQueue _queue)
1550 {
1551 RADV_FROM_HANDLE(radv_queue, queue, _queue);
1552
1553 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
1554 radv_queue_family_to_ring(queue->queue_family_index),
1555 queue->queue_idx);
1556 return VK_SUCCESS;
1557 }
1558
1559 VkResult radv_DeviceWaitIdle(
1560 VkDevice _device)
1561 {
1562 RADV_FROM_HANDLE(radv_device, device, _device);
1563
1564 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1565 for (unsigned q = 0; q < device->queue_count[i]; q++) {
1566 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
1567 }
1568 }
1569 return VK_SUCCESS;
1570 }
1571
1572 PFN_vkVoidFunction radv_GetInstanceProcAddr(
1573 VkInstance instance,
1574 const char* pName)
1575 {
1576 return radv_lookup_entrypoint(pName);
1577 }
1578
1579 /* The loader wants us to expose a second GetInstanceProcAddr function
1580 * to work around certain LD_PRELOAD issues seen in apps.
1581 */
1582 PUBLIC
1583 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
1584 VkInstance instance,
1585 const char* pName);
1586
1587 PUBLIC
1588 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
1589 VkInstance instance,
1590 const char* pName)
1591 {
1592 return radv_GetInstanceProcAddr(instance, pName);
1593 }
1594
1595 PFN_vkVoidFunction radv_GetDeviceProcAddr(
1596 VkDevice device,
1597 const char* pName)
1598 {
1599 return radv_lookup_entrypoint(pName);
1600 }
1601
1602 VkResult radv_AllocateMemory(
1603 VkDevice _device,
1604 const VkMemoryAllocateInfo* pAllocateInfo,
1605 const VkAllocationCallbacks* pAllocator,
1606 VkDeviceMemory* pMem)
1607 {
1608 RADV_FROM_HANDLE(radv_device, device, _device);
1609 struct radv_device_memory *mem;
1610 VkResult result;
1611 enum radeon_bo_domain domain;
1612 uint32_t flags = 0;
1613 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
1614
1615 if (pAllocateInfo->allocationSize == 0) {
1616 /* Apparently, this is allowed */
1617 *pMem = VK_NULL_HANDLE;
1618 return VK_SUCCESS;
1619 }
1620
1621 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
1622 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1623 if (mem == NULL)
1624 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1625
1626 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
1627 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
1628 pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_CACHED)
1629 domain = RADEON_DOMAIN_GTT;
1630 else
1631 domain = RADEON_DOMAIN_VRAM;
1632
1633 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_VRAM)
1634 flags |= RADEON_FLAG_NO_CPU_ACCESS;
1635 else
1636 flags |= RADEON_FLAG_CPU_ACCESS;
1637
1638 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
1639 flags |= RADEON_FLAG_GTT_WC;
1640
1641 mem->bo = device->ws->buffer_create(device->ws, alloc_size, 65536,
1642 domain, flags);
1643
1644 if (!mem->bo) {
1645 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
1646 goto fail;
1647 }
1648 mem->type_index = pAllocateInfo->memoryTypeIndex;
1649
1650 *pMem = radv_device_memory_to_handle(mem);
1651
1652 return VK_SUCCESS;
1653
1654 fail:
1655 vk_free2(&device->alloc, pAllocator, mem);
1656
1657 return result;
1658 }
1659
1660 void radv_FreeMemory(
1661 VkDevice _device,
1662 VkDeviceMemory _mem,
1663 const VkAllocationCallbacks* pAllocator)
1664 {
1665 RADV_FROM_HANDLE(radv_device, device, _device);
1666 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
1667
1668 if (mem == NULL)
1669 return;
1670
1671 device->ws->buffer_destroy(mem->bo);
1672 mem->bo = NULL;
1673
1674 vk_free2(&device->alloc, pAllocator, mem);
1675 }
1676
1677 VkResult radv_MapMemory(
1678 VkDevice _device,
1679 VkDeviceMemory _memory,
1680 VkDeviceSize offset,
1681 VkDeviceSize size,
1682 VkMemoryMapFlags flags,
1683 void** ppData)
1684 {
1685 RADV_FROM_HANDLE(radv_device, device, _device);
1686 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1687
1688 if (mem == NULL) {
1689 *ppData = NULL;
1690 return VK_SUCCESS;
1691 }
1692
1693 *ppData = device->ws->buffer_map(mem->bo);
1694 if (*ppData) {
1695 *ppData += offset;
1696 return VK_SUCCESS;
1697 }
1698
1699 return VK_ERROR_MEMORY_MAP_FAILED;
1700 }
1701
1702 void radv_UnmapMemory(
1703 VkDevice _device,
1704 VkDeviceMemory _memory)
1705 {
1706 RADV_FROM_HANDLE(radv_device, device, _device);
1707 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1708
1709 if (mem == NULL)
1710 return;
1711
1712 device->ws->buffer_unmap(mem->bo);
1713 }
1714
1715 VkResult radv_FlushMappedMemoryRanges(
1716 VkDevice _device,
1717 uint32_t memoryRangeCount,
1718 const VkMappedMemoryRange* pMemoryRanges)
1719 {
1720 return VK_SUCCESS;
1721 }
1722
1723 VkResult radv_InvalidateMappedMemoryRanges(
1724 VkDevice _device,
1725 uint32_t memoryRangeCount,
1726 const VkMappedMemoryRange* pMemoryRanges)
1727 {
1728 return VK_SUCCESS;
1729 }
1730
1731 void radv_GetBufferMemoryRequirements(
1732 VkDevice device,
1733 VkBuffer _buffer,
1734 VkMemoryRequirements* pMemoryRequirements)
1735 {
1736 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1737
1738 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
1739
1740 pMemoryRequirements->size = buffer->size;
1741 pMemoryRequirements->alignment = 16;
1742 }
1743
1744 void radv_GetImageMemoryRequirements(
1745 VkDevice device,
1746 VkImage _image,
1747 VkMemoryRequirements* pMemoryRequirements)
1748 {
1749 RADV_FROM_HANDLE(radv_image, image, _image);
1750
1751 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
1752
1753 pMemoryRequirements->size = image->size;
1754 pMemoryRequirements->alignment = image->alignment;
1755 }
1756
1757 void radv_GetImageSparseMemoryRequirements(
1758 VkDevice device,
1759 VkImage image,
1760 uint32_t* pSparseMemoryRequirementCount,
1761 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
1762 {
1763 stub();
1764 }
1765
1766 void radv_GetDeviceMemoryCommitment(
1767 VkDevice device,
1768 VkDeviceMemory memory,
1769 VkDeviceSize* pCommittedMemoryInBytes)
1770 {
1771 *pCommittedMemoryInBytes = 0;
1772 }
1773
1774 VkResult radv_BindBufferMemory(
1775 VkDevice device,
1776 VkBuffer _buffer,
1777 VkDeviceMemory _memory,
1778 VkDeviceSize memoryOffset)
1779 {
1780 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1781 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1782
1783 if (mem) {
1784 buffer->bo = mem->bo;
1785 buffer->offset = memoryOffset;
1786 } else {
1787 buffer->bo = NULL;
1788 buffer->offset = 0;
1789 }
1790
1791 return VK_SUCCESS;
1792 }
1793
1794 VkResult radv_BindImageMemory(
1795 VkDevice device,
1796 VkImage _image,
1797 VkDeviceMemory _memory,
1798 VkDeviceSize memoryOffset)
1799 {
1800 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1801 RADV_FROM_HANDLE(radv_image, image, _image);
1802
1803 if (mem) {
1804 image->bo = mem->bo;
1805 image->offset = memoryOffset;
1806 } else {
1807 image->bo = NULL;
1808 image->offset = 0;
1809 }
1810
1811 return VK_SUCCESS;
1812 }
1813
1814 VkResult radv_QueueBindSparse(
1815 VkQueue queue,
1816 uint32_t bindInfoCount,
1817 const VkBindSparseInfo* pBindInfo,
1818 VkFence fence)
1819 {
1820 stub_return(VK_ERROR_INCOMPATIBLE_DRIVER);
1821 }
1822
1823 VkResult radv_CreateFence(
1824 VkDevice _device,
1825 const VkFenceCreateInfo* pCreateInfo,
1826 const VkAllocationCallbacks* pAllocator,
1827 VkFence* pFence)
1828 {
1829 RADV_FROM_HANDLE(radv_device, device, _device);
1830 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
1831 sizeof(*fence), 8,
1832 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1833
1834 if (!fence)
1835 return VK_ERROR_OUT_OF_HOST_MEMORY;
1836
1837 memset(fence, 0, sizeof(*fence));
1838 fence->submitted = false;
1839 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
1840 fence->fence = device->ws->create_fence();
1841 if (!fence->fence) {
1842 vk_free2(&device->alloc, pAllocator, fence);
1843 return VK_ERROR_OUT_OF_HOST_MEMORY;
1844 }
1845
1846 *pFence = radv_fence_to_handle(fence);
1847
1848 return VK_SUCCESS;
1849 }
1850
1851 void radv_DestroyFence(
1852 VkDevice _device,
1853 VkFence _fence,
1854 const VkAllocationCallbacks* pAllocator)
1855 {
1856 RADV_FROM_HANDLE(radv_device, device, _device);
1857 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1858
1859 if (!fence)
1860 return;
1861 device->ws->destroy_fence(fence->fence);
1862 vk_free2(&device->alloc, pAllocator, fence);
1863 }
1864
1865 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
1866 {
1867 uint64_t current_time;
1868 struct timespec tv;
1869
1870 clock_gettime(CLOCK_MONOTONIC, &tv);
1871 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
1872
1873 timeout = MIN2(UINT64_MAX - current_time, timeout);
1874
1875 return current_time + timeout;
1876 }
1877
1878 VkResult radv_WaitForFences(
1879 VkDevice _device,
1880 uint32_t fenceCount,
1881 const VkFence* pFences,
1882 VkBool32 waitAll,
1883 uint64_t timeout)
1884 {
1885 RADV_FROM_HANDLE(radv_device, device, _device);
1886 timeout = radv_get_absolute_timeout(timeout);
1887
1888 if (!waitAll && fenceCount > 1) {
1889 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
1890 }
1891
1892 for (uint32_t i = 0; i < fenceCount; ++i) {
1893 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
1894 bool expired = false;
1895
1896 if (fence->signalled)
1897 continue;
1898
1899 if (!fence->submitted)
1900 return VK_TIMEOUT;
1901
1902 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
1903 if (!expired)
1904 return VK_TIMEOUT;
1905
1906 fence->signalled = true;
1907 }
1908
1909 return VK_SUCCESS;
1910 }
1911
1912 VkResult radv_ResetFences(VkDevice device,
1913 uint32_t fenceCount,
1914 const VkFence *pFences)
1915 {
1916 for (unsigned i = 0; i < fenceCount; ++i) {
1917 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
1918 fence->submitted = fence->signalled = false;
1919 }
1920
1921 return VK_SUCCESS;
1922 }
1923
1924 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
1925 {
1926 RADV_FROM_HANDLE(radv_device, device, _device);
1927 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1928
1929 if (fence->signalled)
1930 return VK_SUCCESS;
1931 if (!fence->submitted)
1932 return VK_NOT_READY;
1933
1934 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
1935 return VK_NOT_READY;
1936
1937 return VK_SUCCESS;
1938 }
1939
1940
1941 // Queue semaphore functions
1942
1943 VkResult radv_CreateSemaphore(
1944 VkDevice _device,
1945 const VkSemaphoreCreateInfo* pCreateInfo,
1946 const VkAllocationCallbacks* pAllocator,
1947 VkSemaphore* pSemaphore)
1948 {
1949 RADV_FROM_HANDLE(radv_device, device, _device);
1950 struct radeon_winsys_sem *sem;
1951
1952 sem = device->ws->create_sem(device->ws);
1953 if (!sem)
1954 return VK_ERROR_OUT_OF_HOST_MEMORY;
1955
1956 *pSemaphore = (VkSemaphore)sem;
1957 return VK_SUCCESS;
1958 }
1959
1960 void radv_DestroySemaphore(
1961 VkDevice _device,
1962 VkSemaphore _semaphore,
1963 const VkAllocationCallbacks* pAllocator)
1964 {
1965 RADV_FROM_HANDLE(radv_device, device, _device);
1966 struct radeon_winsys_sem *sem;
1967 if (!_semaphore)
1968 return;
1969
1970 sem = (struct radeon_winsys_sem *)_semaphore;
1971 device->ws->destroy_sem(sem);
1972 }
1973
1974 VkResult radv_CreateEvent(
1975 VkDevice _device,
1976 const VkEventCreateInfo* pCreateInfo,
1977 const VkAllocationCallbacks* pAllocator,
1978 VkEvent* pEvent)
1979 {
1980 RADV_FROM_HANDLE(radv_device, device, _device);
1981 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
1982 sizeof(*event), 8,
1983 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1984
1985 if (!event)
1986 return VK_ERROR_OUT_OF_HOST_MEMORY;
1987
1988 event->bo = device->ws->buffer_create(device->ws, 8, 8,
1989 RADEON_DOMAIN_GTT,
1990 RADEON_FLAG_CPU_ACCESS);
1991 if (!event->bo) {
1992 vk_free2(&device->alloc, pAllocator, event);
1993 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1994 }
1995
1996 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
1997
1998 *pEvent = radv_event_to_handle(event);
1999
2000 return VK_SUCCESS;
2001 }
2002
2003 void radv_DestroyEvent(
2004 VkDevice _device,
2005 VkEvent _event,
2006 const VkAllocationCallbacks* pAllocator)
2007 {
2008 RADV_FROM_HANDLE(radv_device, device, _device);
2009 RADV_FROM_HANDLE(radv_event, event, _event);
2010
2011 if (!event)
2012 return;
2013 device->ws->buffer_destroy(event->bo);
2014 vk_free2(&device->alloc, pAllocator, event);
2015 }
2016
2017 VkResult radv_GetEventStatus(
2018 VkDevice _device,
2019 VkEvent _event)
2020 {
2021 RADV_FROM_HANDLE(radv_event, event, _event);
2022
2023 if (*event->map == 1)
2024 return VK_EVENT_SET;
2025 return VK_EVENT_RESET;
2026 }
2027
2028 VkResult radv_SetEvent(
2029 VkDevice _device,
2030 VkEvent _event)
2031 {
2032 RADV_FROM_HANDLE(radv_event, event, _event);
2033 *event->map = 1;
2034
2035 return VK_SUCCESS;
2036 }
2037
2038 VkResult radv_ResetEvent(
2039 VkDevice _device,
2040 VkEvent _event)
2041 {
2042 RADV_FROM_HANDLE(radv_event, event, _event);
2043 *event->map = 0;
2044
2045 return VK_SUCCESS;
2046 }
2047
2048 VkResult radv_CreateBuffer(
2049 VkDevice _device,
2050 const VkBufferCreateInfo* pCreateInfo,
2051 const VkAllocationCallbacks* pAllocator,
2052 VkBuffer* pBuffer)
2053 {
2054 RADV_FROM_HANDLE(radv_device, device, _device);
2055 struct radv_buffer *buffer;
2056
2057 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
2058
2059 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
2060 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2061 if (buffer == NULL)
2062 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2063
2064 buffer->size = pCreateInfo->size;
2065 buffer->usage = pCreateInfo->usage;
2066 buffer->bo = NULL;
2067 buffer->offset = 0;
2068
2069 *pBuffer = radv_buffer_to_handle(buffer);
2070
2071 return VK_SUCCESS;
2072 }
2073
2074 void radv_DestroyBuffer(
2075 VkDevice _device,
2076 VkBuffer _buffer,
2077 const VkAllocationCallbacks* pAllocator)
2078 {
2079 RADV_FROM_HANDLE(radv_device, device, _device);
2080 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2081
2082 if (!buffer)
2083 return;
2084
2085 vk_free2(&device->alloc, pAllocator, buffer);
2086 }
2087
2088 static inline unsigned
2089 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
2090 {
2091 if (stencil)
2092 return image->surface.stencil_tiling_index[level];
2093 else
2094 return image->surface.tiling_index[level];
2095 }
2096
2097 static uint32_t radv_surface_layer_count(struct radv_image_view *iview)
2098 {
2099 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : iview->layer_count;
2100 }
2101
2102 static void
2103 radv_initialise_color_surface(struct radv_device *device,
2104 struct radv_color_buffer_info *cb,
2105 struct radv_image_view *iview)
2106 {
2107 const struct vk_format_description *desc;
2108 unsigned ntype, format, swap, endian;
2109 unsigned blend_clamp = 0, blend_bypass = 0;
2110 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2111 uint64_t va;
2112 const struct radeon_surf *surf = &iview->image->surface;
2113 const struct radeon_surf_level *level_info = &surf->level[iview->base_mip];
2114
2115 desc = vk_format_description(iview->vk_format);
2116
2117 memset(cb, 0, sizeof(*cb));
2118
2119 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2120 va += level_info->offset;
2121 cb->cb_color_base = va >> 8;
2122
2123 /* CMASK variables */
2124 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2125 va += iview->image->cmask.offset;
2126 cb->cb_color_cmask = va >> 8;
2127 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
2128
2129 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2130 va += iview->image->dcc_offset;
2131 cb->cb_dcc_base = va >> 8;
2132
2133 uint32_t max_slice = radv_surface_layer_count(iview);
2134 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
2135 S_028C6C_SLICE_MAX(iview->base_layer + max_slice - 1);
2136
2137 cb->micro_tile_mode = iview->image->surface.micro_tile_mode;
2138 pitch_tile_max = level_info->nblk_x / 8 - 1;
2139 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
2140 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
2141
2142 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2143 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2144
2145 /* Intensity is implemented as Red, so treat it that way. */
2146 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1) |
2147 S_028C74_TILE_MODE_INDEX(tile_mode_index);
2148
2149 if (iview->image->samples > 1) {
2150 unsigned log_samples = util_logbase2(iview->image->samples);
2151
2152 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2153 S_028C74_NUM_FRAGMENTS(log_samples);
2154 }
2155
2156 if (iview->image->fmask.size) {
2157 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
2158 if (device->physical_device->rad_info.chip_class >= CIK)
2159 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
2160 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
2161 cb->cb_color_fmask = va >> 8;
2162 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
2163 } else {
2164 /* This must be set for fast clear to work without FMASK. */
2165 if (device->physical_device->rad_info.chip_class >= CIK)
2166 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2167 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2168 cb->cb_color_fmask = cb->cb_color_base;
2169 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2170 }
2171
2172 ntype = radv_translate_color_numformat(iview->vk_format,
2173 desc,
2174 vk_format_get_first_non_void_channel(iview->vk_format));
2175 format = radv_translate_colorformat(iview->vk_format);
2176 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
2177 radv_finishme("Illegal color\n");
2178 swap = radv_translate_colorswap(iview->vk_format, FALSE);
2179 endian = radv_colorformat_endian_swap(format);
2180
2181 /* blend clamp should be set for all NORM/SRGB types */
2182 if (ntype == V_028C70_NUMBER_UNORM ||
2183 ntype == V_028C70_NUMBER_SNORM ||
2184 ntype == V_028C70_NUMBER_SRGB)
2185 blend_clamp = 1;
2186
2187 /* set blend bypass according to docs if SINT/UINT or
2188 8/24 COLOR variants */
2189 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2190 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2191 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2192 blend_clamp = 0;
2193 blend_bypass = 1;
2194 }
2195 #if 0
2196 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
2197 (format == V_028C70_COLOR_8 ||
2198 format == V_028C70_COLOR_8_8 ||
2199 format == V_028C70_COLOR_8_8_8_8))
2200 ->color_is_int8 = true;
2201 #endif
2202 cb->cb_color_info = S_028C70_FORMAT(format) |
2203 S_028C70_COMP_SWAP(swap) |
2204 S_028C70_BLEND_CLAMP(blend_clamp) |
2205 S_028C70_BLEND_BYPASS(blend_bypass) |
2206 S_028C70_SIMPLE_FLOAT(1) |
2207 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2208 ntype != V_028C70_NUMBER_SNORM &&
2209 ntype != V_028C70_NUMBER_SRGB &&
2210 format != V_028C70_COLOR_8_24 &&
2211 format != V_028C70_COLOR_24_8) |
2212 S_028C70_NUMBER_TYPE(ntype) |
2213 S_028C70_ENDIAN(endian);
2214 if (iview->image->samples > 1)
2215 if (iview->image->fmask.size)
2216 cb->cb_color_info |= S_028C70_COMPRESSION(1);
2217
2218 if (iview->image->cmask.size &&
2219 !(device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
2220 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
2221
2222 if (iview->image->surface.dcc_size && level_info->dcc_enabled)
2223 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
2224
2225 if (device->physical_device->rad_info.chip_class >= VI) {
2226 unsigned max_uncompressed_block_size = 2;
2227 if (iview->image->samples > 1) {
2228 if (iview->image->surface.bpe == 1)
2229 max_uncompressed_block_size = 0;
2230 else if (iview->image->surface.bpe == 2)
2231 max_uncompressed_block_size = 1;
2232 }
2233
2234 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2235 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2236 }
2237
2238 /* This must be set for fast clear to work without FMASK. */
2239 if (!iview->image->fmask.size &&
2240 device->physical_device->rad_info.chip_class == SI) {
2241 unsigned bankh = util_logbase2(iview->image->surface.bankh);
2242 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2243 }
2244 }
2245
2246 static void
2247 radv_initialise_ds_surface(struct radv_device *device,
2248 struct radv_ds_buffer_info *ds,
2249 struct radv_image_view *iview)
2250 {
2251 unsigned level = iview->base_mip;
2252 unsigned format;
2253 uint64_t va, s_offs, z_offs;
2254 const struct radeon_surf_level *level_info = &iview->image->surface.level[level];
2255 memset(ds, 0, sizeof(*ds));
2256 switch (iview->vk_format) {
2257 case VK_FORMAT_D24_UNORM_S8_UINT:
2258 case VK_FORMAT_X8_D24_UNORM_PACK32:
2259 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
2260 ds->offset_scale = 2.0f;
2261 break;
2262 case VK_FORMAT_D16_UNORM:
2263 case VK_FORMAT_D16_UNORM_S8_UINT:
2264 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
2265 ds->offset_scale = 4.0f;
2266 break;
2267 case VK_FORMAT_D32_SFLOAT:
2268 case VK_FORMAT_D32_SFLOAT_S8_UINT:
2269 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
2270 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2271 ds->offset_scale = 1.0f;
2272 break;
2273 default:
2274 break;
2275 }
2276
2277 format = radv_translate_dbformat(iview->vk_format);
2278 if (format == V_028040_Z_INVALID) {
2279 fprintf(stderr, "Invalid DB format: %d, disabling DB.\n", iview->vk_format);
2280 }
2281
2282 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2283 s_offs = z_offs = va;
2284 z_offs += iview->image->surface.level[level].offset;
2285 s_offs += iview->image->surface.stencil_level[level].offset;
2286
2287 uint32_t max_slice = radv_surface_layer_count(iview);
2288 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
2289 S_028008_SLICE_MAX(iview->base_layer + max_slice - 1);
2290 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
2291 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
2292
2293 if (iview->image->samples > 1)
2294 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->samples));
2295
2296 if (iview->image->surface.flags & RADEON_SURF_SBUFFER)
2297 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8);
2298 else
2299 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2300
2301 if (device->physical_device->rad_info.chip_class >= CIK) {
2302 struct radeon_info *info = &device->physical_device->rad_info;
2303 unsigned tiling_index = iview->image->surface.tiling_index[level];
2304 unsigned stencil_index = iview->image->surface.stencil_tiling_index[level];
2305 unsigned macro_index = iview->image->surface.macro_tile_index;
2306 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
2307 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2308 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2309
2310 ds->db_depth_info |=
2311 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2312 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2313 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2314 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2315 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2316 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2317 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2318 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2319 } else {
2320 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
2321 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2322 tile_mode_index = si_tile_mode_index(iview->image, level, true);
2323 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2324 }
2325
2326 if (iview->image->htile.size && !level) {
2327 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2328 S_028040_ALLOW_EXPCLEAR(1);
2329
2330 if (iview->image->surface.flags & RADEON_SURF_SBUFFER) {
2331 /* Workaround: For a not yet understood reason, the
2332 * combination of MSAA, fast stencil clear and stencil
2333 * decompress messes with subsequent stencil buffer
2334 * uses. Problem was reproduced on Verde, Bonaire,
2335 * Tonga, and Carrizo.
2336 *
2337 * Disabling EXPCLEAR works around the problem.
2338 *
2339 * Check piglit's arb_texture_multisample-stencil-clear
2340 * test if you want to try changing this.
2341 */
2342 if (iview->image->samples <= 1)
2343 ds->db_stencil_info |= S_028044_ALLOW_EXPCLEAR(1);
2344 } else
2345 /* Use all of the htile_buffer for depth if there's no stencil. */
2346 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
2347
2348 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
2349 iview->image->htile.offset;
2350 ds->db_htile_data_base = va >> 8;
2351 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
2352 } else {
2353 ds->db_htile_data_base = 0;
2354 ds->db_htile_surface = 0;
2355 }
2356
2357 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
2358 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
2359
2360 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
2361 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
2362 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
2363 }
2364
2365 VkResult radv_CreateFramebuffer(
2366 VkDevice _device,
2367 const VkFramebufferCreateInfo* pCreateInfo,
2368 const VkAllocationCallbacks* pAllocator,
2369 VkFramebuffer* pFramebuffer)
2370 {
2371 RADV_FROM_HANDLE(radv_device, device, _device);
2372 struct radv_framebuffer *framebuffer;
2373
2374 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
2375
2376 size_t size = sizeof(*framebuffer) +
2377 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
2378 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
2379 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2380 if (framebuffer == NULL)
2381 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2382
2383 framebuffer->attachment_count = pCreateInfo->attachmentCount;
2384 framebuffer->width = pCreateInfo->width;
2385 framebuffer->height = pCreateInfo->height;
2386 framebuffer->layers = pCreateInfo->layers;
2387 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
2388 VkImageView _iview = pCreateInfo->pAttachments[i];
2389 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
2390 framebuffer->attachments[i].attachment = iview;
2391 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
2392 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
2393 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
2394 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
2395 }
2396 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
2397 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
2398 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_layer_count(iview));
2399 }
2400
2401 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
2402 return VK_SUCCESS;
2403 }
2404
2405 void radv_DestroyFramebuffer(
2406 VkDevice _device,
2407 VkFramebuffer _fb,
2408 const VkAllocationCallbacks* pAllocator)
2409 {
2410 RADV_FROM_HANDLE(radv_device, device, _device);
2411 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
2412
2413 if (!fb)
2414 return;
2415 vk_free2(&device->alloc, pAllocator, fb);
2416 }
2417
2418 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
2419 {
2420 switch (address_mode) {
2421 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
2422 return V_008F30_SQ_TEX_WRAP;
2423 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
2424 return V_008F30_SQ_TEX_MIRROR;
2425 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
2426 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
2427 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
2428 return V_008F30_SQ_TEX_CLAMP_BORDER;
2429 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
2430 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
2431 default:
2432 unreachable("illegal tex wrap mode");
2433 break;
2434 }
2435 }
2436
2437 static unsigned
2438 radv_tex_compare(VkCompareOp op)
2439 {
2440 switch (op) {
2441 case VK_COMPARE_OP_NEVER:
2442 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
2443 case VK_COMPARE_OP_LESS:
2444 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
2445 case VK_COMPARE_OP_EQUAL:
2446 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
2447 case VK_COMPARE_OP_LESS_OR_EQUAL:
2448 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
2449 case VK_COMPARE_OP_GREATER:
2450 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
2451 case VK_COMPARE_OP_NOT_EQUAL:
2452 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
2453 case VK_COMPARE_OP_GREATER_OR_EQUAL:
2454 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
2455 case VK_COMPARE_OP_ALWAYS:
2456 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
2457 default:
2458 unreachable("illegal compare mode");
2459 break;
2460 }
2461 }
2462
2463 static unsigned
2464 radv_tex_filter(VkFilter filter, unsigned max_ansio)
2465 {
2466 switch (filter) {
2467 case VK_FILTER_NEAREST:
2468 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
2469 V_008F38_SQ_TEX_XY_FILTER_POINT);
2470 case VK_FILTER_LINEAR:
2471 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
2472 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
2473 case VK_FILTER_CUBIC_IMG:
2474 default:
2475 fprintf(stderr, "illegal texture filter");
2476 return 0;
2477 }
2478 }
2479
2480 static unsigned
2481 radv_tex_mipfilter(VkSamplerMipmapMode mode)
2482 {
2483 switch (mode) {
2484 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
2485 return V_008F38_SQ_TEX_Z_FILTER_POINT;
2486 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
2487 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
2488 default:
2489 return V_008F38_SQ_TEX_Z_FILTER_NONE;
2490 }
2491 }
2492
2493 static unsigned
2494 radv_tex_bordercolor(VkBorderColor bcolor)
2495 {
2496 switch (bcolor) {
2497 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
2498 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
2499 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2500 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
2501 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
2502 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
2503 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
2504 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
2505 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
2506 default:
2507 break;
2508 }
2509 return 0;
2510 }
2511
2512 static unsigned
2513 radv_tex_aniso_filter(unsigned filter)
2514 {
2515 if (filter < 2)
2516 return 0;
2517 if (filter < 4)
2518 return 1;
2519 if (filter < 8)
2520 return 2;
2521 if (filter < 16)
2522 return 3;
2523 return 4;
2524 }
2525
2526 static void
2527 radv_init_sampler(struct radv_device *device,
2528 struct radv_sampler *sampler,
2529 const VkSamplerCreateInfo *pCreateInfo)
2530 {
2531 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
2532 (uint32_t) pCreateInfo->maxAnisotropy : 0;
2533 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
2534 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
2535
2536 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
2537 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
2538 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
2539 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
2540 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
2541 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
2542 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
2543 S_008F30_ANISO_BIAS(max_aniso_ratio) |
2544 S_008F30_DISABLE_CUBE_WRAP(0) |
2545 S_008F30_COMPAT_MODE(is_vi));
2546 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
2547 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
2548 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
2549 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
2550 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
2551 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
2552 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
2553 S_008F38_MIP_POINT_PRECLAMP(1) |
2554 S_008F38_DISABLE_LSB_CEIL(1) |
2555 S_008F38_FILTER_PREC_FIX(1) |
2556 S_008F38_ANISO_OVERRIDE(is_vi));
2557 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
2558 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
2559 }
2560
2561 VkResult radv_CreateSampler(
2562 VkDevice _device,
2563 const VkSamplerCreateInfo* pCreateInfo,
2564 const VkAllocationCallbacks* pAllocator,
2565 VkSampler* pSampler)
2566 {
2567 RADV_FROM_HANDLE(radv_device, device, _device);
2568 struct radv_sampler *sampler;
2569
2570 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
2571
2572 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
2573 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2574 if (!sampler)
2575 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2576
2577 radv_init_sampler(device, sampler, pCreateInfo);
2578 *pSampler = radv_sampler_to_handle(sampler);
2579
2580 return VK_SUCCESS;
2581 }
2582
2583 void radv_DestroySampler(
2584 VkDevice _device,
2585 VkSampler _sampler,
2586 const VkAllocationCallbacks* pAllocator)
2587 {
2588 RADV_FROM_HANDLE(radv_device, device, _device);
2589 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
2590
2591 if (!sampler)
2592 return;
2593 vk_free2(&device->alloc, pAllocator, sampler);
2594 }
2595
2596
2597 /* vk_icd.h does not declare this function, so we declare it here to
2598 * suppress Wmissing-prototypes.
2599 */
2600 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
2601 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
2602
2603 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
2604 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
2605 {
2606 /* For the full details on loader interface versioning, see
2607 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
2608 * What follows is a condensed summary, to help you navigate the large and
2609 * confusing official doc.
2610 *
2611 * - Loader interface v0 is incompatible with later versions. We don't
2612 * support it.
2613 *
2614 * - In loader interface v1:
2615 * - The first ICD entrypoint called by the loader is
2616 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
2617 * entrypoint.
2618 * - The ICD must statically expose no other Vulkan symbol unless it is
2619 * linked with -Bsymbolic.
2620 * - Each dispatchable Vulkan handle created by the ICD must be
2621 * a pointer to a struct whose first member is VK_LOADER_DATA. The
2622 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
2623 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
2624 * vkDestroySurfaceKHR(). The ICD must be capable of working with
2625 * such loader-managed surfaces.
2626 *
2627 * - Loader interface v2 differs from v1 in:
2628 * - The first ICD entrypoint called by the loader is
2629 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
2630 * statically expose this entrypoint.
2631 *
2632 * - Loader interface v3 differs from v2 in:
2633 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
2634 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
2635 * because the loader no longer does so.
2636 */
2637 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
2638 return VK_SUCCESS;
2639 }