7a6af56379787e75ee9c2bfbd98692290124b9ae
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include <llvm/Config/llvm-config.h>
33 #include "radv_debug.h"
34 #include "radv_private.h"
35 #include "radv_shader.h"
36 #include "radv_cs.h"
37 #include "util/disk_cache.h"
38 #include "util/strtod.h"
39 #include "vk_util.h"
40 #include <xf86drm.h>
41 #include <amdgpu.h>
42 #include <amdgpu_drm.h>
43 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
44 #include "ac_llvm_util.h"
45 #include "vk_format.h"
46 #include "sid.h"
47 #include "git_sha1.h"
48 #include "util/build_id.h"
49 #include "util/debug.h"
50 #include "util/mesa-sha1.h"
51 #include "compiler/glsl_types.h"
52 #include "util/xmlpool.h"
53
54 static int
55 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
56 {
57 struct mesa_sha1 ctx;
58 unsigned char sha1[20];
59 unsigned ptr_size = sizeof(void*);
60
61 memset(uuid, 0, VK_UUID_SIZE);
62 _mesa_sha1_init(&ctx);
63
64 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
65 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
66 return -1;
67
68 _mesa_sha1_update(&ctx, &family, sizeof(family));
69 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
70 _mesa_sha1_final(&ctx, sha1);
71
72 memcpy(uuid, sha1, VK_UUID_SIZE);
73 return 0;
74 }
75
76 static void
77 radv_get_driver_uuid(void *uuid)
78 {
79 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
80 }
81
82 static void
83 radv_get_device_uuid(struct radeon_info *info, void *uuid)
84 {
85 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
86 }
87
88 static void
89 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
90 {
91 const char *chip_string;
92
93 switch (family) {
94 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
95 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
96 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
97 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
98 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
99 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
100 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
101 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
102 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
103 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
104 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
105 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
106 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
107 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
108 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
109 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
110 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
111 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
112 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
113 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
114 case CHIP_VEGA20: chip_string = "AMD RADV VEGA20"; break;
115 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
116 case CHIP_RAVEN2: chip_string = "AMD RADV RAVEN2"; break;
117 case CHIP_NAVI10: chip_string = "AMD RADV NAVI10"; break;
118 case CHIP_NAVI12: chip_string = "AMD RADV NAVI12"; break;
119 case CHIP_NAVI14: chip_string = "AMD RADV NAVI14"; break;
120 default: chip_string = "AMD RADV unknown"; break;
121 }
122
123 snprintf(name, name_len, "%s (LLVM " MESA_LLVM_VERSION_STRING ")", chip_string);
124 }
125
126 static uint64_t
127 radv_get_visible_vram_size(struct radv_physical_device *device)
128 {
129 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
130 }
131
132 static uint64_t
133 radv_get_vram_size(struct radv_physical_device *device)
134 {
135 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
136 }
137
138 static void
139 radv_physical_device_init_mem_types(struct radv_physical_device *device)
140 {
141 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
142 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
143 uint64_t vram_size = radv_get_vram_size(device);
144 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
145 device->memory_properties.memoryHeapCount = 0;
146 if (vram_size > 0) {
147 vram_index = device->memory_properties.memoryHeapCount++;
148 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
149 .size = vram_size,
150 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
151 };
152 }
153 if (visible_vram_size) {
154 visible_vram_index = device->memory_properties.memoryHeapCount++;
155 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
156 .size = visible_vram_size,
157 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
158 };
159 }
160 if (device->rad_info.gart_size > 0) {
161 gart_index = device->memory_properties.memoryHeapCount++;
162 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
163 .size = device->rad_info.gart_size,
164 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
165 };
166 }
167
168 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
169 unsigned type_count = 0;
170 if (vram_index >= 0) {
171 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
172 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
173 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
174 .heapIndex = vram_index,
175 };
176 }
177 if (gart_index >= 0 && device->rad_info.has_dedicated_vram) {
178 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
179 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
180 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
181 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
182 .heapIndex = gart_index,
183 };
184 }
185 if (visible_vram_index >= 0) {
186 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
187 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
188 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
189 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
190 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
191 .heapIndex = visible_vram_index,
192 };
193 }
194 if (gart_index >= 0 && !device->rad_info.has_dedicated_vram) {
195 /* Put GTT after visible VRAM for GPUs without dedicated VRAM
196 * as they have identical property flags, and according to the
197 * spec, for types with identical flags, the one with greater
198 * performance must be given a lower index. */
199 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
200 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
201 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
202 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
203 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
204 .heapIndex = gart_index,
205 };
206 }
207 if (gart_index >= 0) {
208 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
209 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
210 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
211 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
212 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
213 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
214 .heapIndex = gart_index,
215 };
216 }
217 device->memory_properties.memoryTypeCount = type_count;
218 }
219
220 static void
221 radv_handle_env_var_force_family(struct radv_physical_device *device)
222 {
223 const char *family = getenv("RADV_FORCE_FAMILY");
224 unsigned i;
225
226 if (!family)
227 return;
228
229 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
230 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
231 /* Override family and chip_class. */
232 device->rad_info.family = i;
233
234 if (i >= CHIP_NAVI10)
235 device->rad_info.chip_class = GFX10;
236 else if (i >= CHIP_VEGA10)
237 device->rad_info.chip_class = GFX9;
238 else if (i >= CHIP_TONGA)
239 device->rad_info.chip_class = GFX8;
240 else if (i >= CHIP_BONAIRE)
241 device->rad_info.chip_class = GFX7;
242 else
243 device->rad_info.chip_class = GFX6;
244
245 return;
246 }
247 }
248
249 fprintf(stderr, "radv: Unknown family: %s\n", family);
250 exit(1);
251 }
252
253 static VkResult
254 radv_physical_device_init(struct radv_physical_device *device,
255 struct radv_instance *instance,
256 drmDevicePtr drm_device)
257 {
258 const char *path = drm_device->nodes[DRM_NODE_RENDER];
259 VkResult result;
260 drmVersionPtr version;
261 int fd;
262 int master_fd = -1;
263
264 fd = open(path, O_RDWR | O_CLOEXEC);
265 if (fd < 0) {
266 if (instance->debug_flags & RADV_DEBUG_STARTUP)
267 radv_logi("Could not open device '%s'", path);
268
269 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
270 }
271
272 version = drmGetVersion(fd);
273 if (!version) {
274 close(fd);
275
276 if (instance->debug_flags & RADV_DEBUG_STARTUP)
277 radv_logi("Could not get the kernel driver version for device '%s'", path);
278
279 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
280 "failed to get version %s: %m", path);
281 }
282
283 if (strcmp(version->name, "amdgpu")) {
284 drmFreeVersion(version);
285 close(fd);
286
287 if (instance->debug_flags & RADV_DEBUG_STARTUP)
288 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
289
290 return VK_ERROR_INCOMPATIBLE_DRIVER;
291 }
292 drmFreeVersion(version);
293
294 if (instance->debug_flags & RADV_DEBUG_STARTUP)
295 radv_logi("Found compatible device '%s'.", path);
296
297 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
298 device->instance = instance;
299
300 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
301 instance->perftest_flags);
302 if (!device->ws) {
303 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
304 goto fail;
305 }
306
307 if (instance->enabled_extensions.KHR_display) {
308 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
309 if (master_fd >= 0) {
310 uint32_t accel_working = 0;
311 struct drm_amdgpu_info request = {
312 .return_pointer = (uintptr_t)&accel_working,
313 .return_size = sizeof(accel_working),
314 .query = AMDGPU_INFO_ACCEL_WORKING
315 };
316
317 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
318 close(master_fd);
319 master_fd = -1;
320 }
321 }
322 }
323
324 device->master_fd = master_fd;
325 device->local_fd = fd;
326 device->ws->query_info(device->ws, &device->rad_info);
327
328 radv_handle_env_var_force_family(device);
329
330 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
331
332 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
333 device->ws->destroy(device->ws);
334 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
335 "cannot generate UUID");
336 goto fail;
337 }
338
339 /* These flags affect shader compilation. */
340 uint64_t shader_env_flags =
341 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
342 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
343
344 /* The gpu id is already embedded in the uuid so we just pass "radv"
345 * when creating the cache.
346 */
347 char buf[VK_UUID_SIZE * 2 + 1];
348 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
349 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
350
351 if (device->rad_info.chip_class < GFX8 ||
352 device->rad_info.chip_class > GFX9)
353 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
354
355 radv_get_driver_uuid(&device->driver_uuid);
356 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
357
358 device->out_of_order_rast_allowed = device->rad_info.has_out_of_order_rast &&
359 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
360
361 device->dcc_msaa_allowed =
362 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
363
364 device->use_shader_ballot = device->rad_info.chip_class >= GFX8 &&
365 device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT;
366
367 /* Determine the number of threads per wave for all stages. */
368 device->cs_wave_size = 64;
369 device->ps_wave_size = 64;
370 device->ge_wave_size = 64;
371
372 if (device->rad_info.chip_class >= GFX10) {
373 if (device->instance->perftest_flags & RADV_PERFTEST_CS_WAVE_32)
374 device->cs_wave_size = 32;
375
376 /* For pixel shaders, wave64 is recommanded. */
377 if (device->instance->perftest_flags & RADV_PERFTEST_PS_WAVE_32)
378 device->ps_wave_size = 32;
379
380 if (device->instance->perftest_flags & RADV_PERFTEST_GE_WAVE_32)
381 device->ge_wave_size = 32;
382 }
383
384 radv_physical_device_init_mem_types(device);
385 radv_fill_device_extension_table(device, &device->supported_extensions);
386
387 device->bus_info = *drm_device->businfo.pci;
388
389 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
390 ac_print_gpu_info(&device->rad_info);
391
392 /* The WSI is structured as a layer on top of the driver, so this has
393 * to be the last part of initialization (at least until we get other
394 * semi-layers).
395 */
396 result = radv_init_wsi(device);
397 if (result != VK_SUCCESS) {
398 device->ws->destroy(device->ws);
399 vk_error(instance, result);
400 goto fail;
401 }
402
403 return VK_SUCCESS;
404
405 fail:
406 close(fd);
407 if (master_fd != -1)
408 close(master_fd);
409 return result;
410 }
411
412 static void
413 radv_physical_device_finish(struct radv_physical_device *device)
414 {
415 radv_finish_wsi(device);
416 device->ws->destroy(device->ws);
417 disk_cache_destroy(device->disk_cache);
418 close(device->local_fd);
419 if (device->master_fd != -1)
420 close(device->master_fd);
421 }
422
423 static void *
424 default_alloc_func(void *pUserData, size_t size, size_t align,
425 VkSystemAllocationScope allocationScope)
426 {
427 return malloc(size);
428 }
429
430 static void *
431 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
432 size_t align, VkSystemAllocationScope allocationScope)
433 {
434 return realloc(pOriginal, size);
435 }
436
437 static void
438 default_free_func(void *pUserData, void *pMemory)
439 {
440 free(pMemory);
441 }
442
443 static const VkAllocationCallbacks default_alloc = {
444 .pUserData = NULL,
445 .pfnAllocation = default_alloc_func,
446 .pfnReallocation = default_realloc_func,
447 .pfnFree = default_free_func,
448 };
449
450 static const struct debug_control radv_debug_options[] = {
451 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
452 {"nodcc", RADV_DEBUG_NO_DCC},
453 {"shaders", RADV_DEBUG_DUMP_SHADERS},
454 {"nocache", RADV_DEBUG_NO_CACHE},
455 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
456 {"nohiz", RADV_DEBUG_NO_HIZ},
457 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
458 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
459 {"allbos", RADV_DEBUG_ALL_BOS},
460 {"noibs", RADV_DEBUG_NO_IBS},
461 {"spirv", RADV_DEBUG_DUMP_SPIRV},
462 {"vmfaults", RADV_DEBUG_VM_FAULTS},
463 {"zerovram", RADV_DEBUG_ZERO_VRAM},
464 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
465 {"nosisched", RADV_DEBUG_NO_SISCHED},
466 {"preoptir", RADV_DEBUG_PREOPTIR},
467 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
468 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
469 {"info", RADV_DEBUG_INFO},
470 {"errors", RADV_DEBUG_ERRORS},
471 {"startup", RADV_DEBUG_STARTUP},
472 {"checkir", RADV_DEBUG_CHECKIR},
473 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
474 {"nobinning", RADV_DEBUG_NOBINNING},
475 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT},
476 {"nongg", RADV_DEBUG_NO_NGG},
477 {"noshaderballot", RADV_DEBUG_NO_SHADER_BALLOT},
478 {"allentrypoints", RADV_DEBUG_ALL_ENTRYPOINTS},
479 {NULL, 0}
480 };
481
482 const char *
483 radv_get_debug_option_name(int id)
484 {
485 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
486 return radv_debug_options[id].string;
487 }
488
489 static const struct debug_control radv_perftest_options[] = {
490 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
491 {"sisched", RADV_PERFTEST_SISCHED},
492 {"localbos", RADV_PERFTEST_LOCAL_BOS},
493 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
494 {"bolist", RADV_PERFTEST_BO_LIST},
495 {"shader_ballot", RADV_PERFTEST_SHADER_BALLOT},
496 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
497 {"cswave32", RADV_PERFTEST_CS_WAVE_32},
498 {"pswave32", RADV_PERFTEST_PS_WAVE_32},
499 {"gewave32", RADV_PERFTEST_GE_WAVE_32},
500 {NULL, 0}
501 };
502
503 const char *
504 radv_get_perftest_option_name(int id)
505 {
506 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
507 return radv_perftest_options[id].string;
508 }
509
510 static void
511 radv_handle_per_app_options(struct radv_instance *instance,
512 const VkApplicationInfo *info)
513 {
514 const char *name = info ? info->pApplicationName : NULL;
515
516 if (!name)
517 return;
518
519 if (!strcmp(name, "Talos - Linux - 32bit") ||
520 !strcmp(name, "Talos - Linux - 64bit")) {
521 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
522 /* Force enable LLVM sisched for Talos because it looks
523 * safe and it gives few more FPS.
524 */
525 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
526 }
527 } else if (!strcmp(name, "DOOM_VFR")) {
528 /* Work around a Doom VFR game bug */
529 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
530 } else if (!strcmp(name, "MonsterHunterWorld.exe")) {
531 /* Workaround for a WaW hazard when LLVM moves/merges
532 * load/store memory operations.
533 * See https://reviews.llvm.org/D61313
534 */
535 if (LLVM_VERSION_MAJOR < 9)
536 instance->debug_flags |= RADV_DEBUG_NO_LOAD_STORE_OPT;
537 } else if (!strcmp(name, "Wolfenstein: Youngblood")) {
538 if (!(instance->debug_flags & RADV_DEBUG_NO_SHADER_BALLOT)) {
539 /* Force enable VK_AMD_shader_ballot because it looks
540 * safe and it gives a nice boost (+20% on Vega 56 at
541 * this time).
542 */
543 instance->perftest_flags |= RADV_PERFTEST_SHADER_BALLOT;
544 }
545 }
546 }
547
548 static int radv_get_instance_extension_index(const char *name)
549 {
550 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
551 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
552 return i;
553 }
554 return -1;
555 }
556
557 static const char radv_dri_options_xml[] =
558 DRI_CONF_BEGIN
559 DRI_CONF_SECTION_PERFORMANCE
560 DRI_CONF_ADAPTIVE_SYNC("true")
561 DRI_CONF_VK_X11_OVERRIDE_MIN_IMAGE_COUNT(0)
562 DRI_CONF_SECTION_END
563 DRI_CONF_END;
564
565 static void radv_init_dri_options(struct radv_instance *instance)
566 {
567 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
568 driParseConfigFiles(&instance->dri_options,
569 &instance->available_dri_options,
570 0, "radv", NULL,
571 instance->engineName,
572 instance->engineVersion);
573 }
574
575 VkResult radv_CreateInstance(
576 const VkInstanceCreateInfo* pCreateInfo,
577 const VkAllocationCallbacks* pAllocator,
578 VkInstance* pInstance)
579 {
580 struct radv_instance *instance;
581 VkResult result;
582
583 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
584
585 uint32_t client_version;
586 if (pCreateInfo->pApplicationInfo &&
587 pCreateInfo->pApplicationInfo->apiVersion != 0) {
588 client_version = pCreateInfo->pApplicationInfo->apiVersion;
589 } else {
590 client_version = VK_API_VERSION_1_0;
591 }
592
593 const char *engine_name = NULL;
594 uint32_t engine_version = 0;
595 if (pCreateInfo->pApplicationInfo) {
596 engine_name = pCreateInfo->pApplicationInfo->pEngineName;
597 engine_version = pCreateInfo->pApplicationInfo->engineVersion;
598 }
599
600 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
601 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
602 if (!instance)
603 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
604
605 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
606
607 if (pAllocator)
608 instance->alloc = *pAllocator;
609 else
610 instance->alloc = default_alloc;
611
612 instance->apiVersion = client_version;
613 instance->physicalDeviceCount = -1;
614
615 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
616 radv_debug_options);
617
618 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
619 radv_perftest_options);
620
621
622 if (instance->debug_flags & RADV_DEBUG_STARTUP)
623 radv_logi("Created an instance");
624
625 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
626 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
627 int index = radv_get_instance_extension_index(ext_name);
628
629 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
630 vk_free2(&default_alloc, pAllocator, instance);
631 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
632 }
633
634 instance->enabled_extensions.extensions[index] = true;
635 }
636
637 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
638 if (result != VK_SUCCESS) {
639 vk_free2(&default_alloc, pAllocator, instance);
640 return vk_error(instance, result);
641 }
642
643 instance->engineName = vk_strdup(&instance->alloc, engine_name,
644 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
645 instance->engineVersion = engine_version;
646
647 _mesa_locale_init();
648 glsl_type_singleton_init_or_ref();
649
650 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
651
652 radv_init_dri_options(instance);
653 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
654
655 *pInstance = radv_instance_to_handle(instance);
656
657 return VK_SUCCESS;
658 }
659
660 void radv_DestroyInstance(
661 VkInstance _instance,
662 const VkAllocationCallbacks* pAllocator)
663 {
664 RADV_FROM_HANDLE(radv_instance, instance, _instance);
665
666 if (!instance)
667 return;
668
669 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
670 radv_physical_device_finish(instance->physicalDevices + i);
671 }
672
673 vk_free(&instance->alloc, instance->engineName);
674
675 VG(VALGRIND_DESTROY_MEMPOOL(instance));
676
677 glsl_type_singleton_decref();
678 _mesa_locale_fini();
679
680 driDestroyOptionCache(&instance->dri_options);
681 driDestroyOptionInfo(&instance->available_dri_options);
682
683 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
684
685 vk_free(&instance->alloc, instance);
686 }
687
688 static VkResult
689 radv_enumerate_devices(struct radv_instance *instance)
690 {
691 /* TODO: Check for more devices ? */
692 drmDevicePtr devices[8];
693 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
694 int max_devices;
695
696 instance->physicalDeviceCount = 0;
697
698 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
699
700 if (instance->debug_flags & RADV_DEBUG_STARTUP)
701 radv_logi("Found %d drm nodes", max_devices);
702
703 if (max_devices < 1)
704 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
705
706 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
707 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
708 devices[i]->bustype == DRM_BUS_PCI &&
709 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
710
711 result = radv_physical_device_init(instance->physicalDevices +
712 instance->physicalDeviceCount,
713 instance,
714 devices[i]);
715 if (result == VK_SUCCESS)
716 ++instance->physicalDeviceCount;
717 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
718 break;
719 }
720 }
721 drmFreeDevices(devices, max_devices);
722
723 return result;
724 }
725
726 VkResult radv_EnumeratePhysicalDevices(
727 VkInstance _instance,
728 uint32_t* pPhysicalDeviceCount,
729 VkPhysicalDevice* pPhysicalDevices)
730 {
731 RADV_FROM_HANDLE(radv_instance, instance, _instance);
732 VkResult result;
733
734 if (instance->physicalDeviceCount < 0) {
735 result = radv_enumerate_devices(instance);
736 if (result != VK_SUCCESS &&
737 result != VK_ERROR_INCOMPATIBLE_DRIVER)
738 return result;
739 }
740
741 if (!pPhysicalDevices) {
742 *pPhysicalDeviceCount = instance->physicalDeviceCount;
743 } else {
744 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
745 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
746 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
747 }
748
749 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
750 : VK_SUCCESS;
751 }
752
753 VkResult radv_EnumeratePhysicalDeviceGroups(
754 VkInstance _instance,
755 uint32_t* pPhysicalDeviceGroupCount,
756 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
757 {
758 RADV_FROM_HANDLE(radv_instance, instance, _instance);
759 VkResult result;
760
761 if (instance->physicalDeviceCount < 0) {
762 result = radv_enumerate_devices(instance);
763 if (result != VK_SUCCESS &&
764 result != VK_ERROR_INCOMPATIBLE_DRIVER)
765 return result;
766 }
767
768 if (!pPhysicalDeviceGroupProperties) {
769 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
770 } else {
771 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
772 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
773 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
774 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
775 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
776 }
777 }
778 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
779 : VK_SUCCESS;
780 }
781
782 void radv_GetPhysicalDeviceFeatures(
783 VkPhysicalDevice physicalDevice,
784 VkPhysicalDeviceFeatures* pFeatures)
785 {
786 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
787 memset(pFeatures, 0, sizeof(*pFeatures));
788
789 *pFeatures = (VkPhysicalDeviceFeatures) {
790 .robustBufferAccess = true,
791 .fullDrawIndexUint32 = true,
792 .imageCubeArray = true,
793 .independentBlend = true,
794 .geometryShader = true,
795 .tessellationShader = true,
796 .sampleRateShading = true,
797 .dualSrcBlend = true,
798 .logicOp = true,
799 .multiDrawIndirect = true,
800 .drawIndirectFirstInstance = true,
801 .depthClamp = true,
802 .depthBiasClamp = true,
803 .fillModeNonSolid = true,
804 .depthBounds = true,
805 .wideLines = true,
806 .largePoints = true,
807 .alphaToOne = true,
808 .multiViewport = true,
809 .samplerAnisotropy = true,
810 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
811 .textureCompressionASTC_LDR = false,
812 .textureCompressionBC = true,
813 .occlusionQueryPrecise = true,
814 .pipelineStatisticsQuery = true,
815 .vertexPipelineStoresAndAtomics = true,
816 .fragmentStoresAndAtomics = true,
817 .shaderTessellationAndGeometryPointSize = true,
818 .shaderImageGatherExtended = true,
819 .shaderStorageImageExtendedFormats = true,
820 .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= GFX8,
821 .shaderUniformBufferArrayDynamicIndexing = true,
822 .shaderSampledImageArrayDynamicIndexing = true,
823 .shaderStorageBufferArrayDynamicIndexing = true,
824 .shaderStorageImageArrayDynamicIndexing = true,
825 .shaderStorageImageReadWithoutFormat = true,
826 .shaderStorageImageWriteWithoutFormat = true,
827 .shaderClipDistance = true,
828 .shaderCullDistance = true,
829 .shaderFloat64 = true,
830 .shaderInt64 = true,
831 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9,
832 .sparseBinding = true,
833 .variableMultisampleRate = true,
834 .inheritedQueries = true,
835 };
836 }
837
838 void radv_GetPhysicalDeviceFeatures2(
839 VkPhysicalDevice physicalDevice,
840 VkPhysicalDeviceFeatures2 *pFeatures)
841 {
842 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
843 vk_foreach_struct(ext, pFeatures->pNext) {
844 switch (ext->sType) {
845 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
846 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
847 features->variablePointersStorageBuffer = true;
848 features->variablePointers = true;
849 break;
850 }
851 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
852 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
853 features->multiview = true;
854 features->multiviewGeometryShader = true;
855 features->multiviewTessellationShader = true;
856 break;
857 }
858 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
859 VkPhysicalDeviceShaderDrawParametersFeatures *features =
860 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
861 features->shaderDrawParameters = true;
862 break;
863 }
864 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
865 VkPhysicalDeviceProtectedMemoryFeatures *features =
866 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
867 features->protectedMemory = false;
868 break;
869 }
870 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
871 VkPhysicalDevice16BitStorageFeatures *features =
872 (VkPhysicalDevice16BitStorageFeatures*)ext;
873 bool enabled = pdevice->rad_info.chip_class >= GFX8;
874 features->storageBuffer16BitAccess = enabled;
875 features->uniformAndStorageBuffer16BitAccess = enabled;
876 features->storagePushConstant16 = enabled;
877 features->storageInputOutput16 = enabled && LLVM_VERSION_MAJOR >= 9;
878 break;
879 }
880 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
881 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
882 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
883 features->samplerYcbcrConversion = true;
884 break;
885 }
886 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
887 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
888 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
889 features->shaderInputAttachmentArrayDynamicIndexing = true;
890 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
891 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
892 features->shaderUniformBufferArrayNonUniformIndexing = true;
893 features->shaderSampledImageArrayNonUniformIndexing = true;
894 features->shaderStorageBufferArrayNonUniformIndexing = true;
895 features->shaderStorageImageArrayNonUniformIndexing = true;
896 features->shaderInputAttachmentArrayNonUniformIndexing = true;
897 features->shaderUniformTexelBufferArrayNonUniformIndexing = true;
898 features->shaderStorageTexelBufferArrayNonUniformIndexing = true;
899 features->descriptorBindingUniformBufferUpdateAfterBind = true;
900 features->descriptorBindingSampledImageUpdateAfterBind = true;
901 features->descriptorBindingStorageImageUpdateAfterBind = true;
902 features->descriptorBindingStorageBufferUpdateAfterBind = true;
903 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
904 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
905 features->descriptorBindingUpdateUnusedWhilePending = true;
906 features->descriptorBindingPartiallyBound = true;
907 features->descriptorBindingVariableDescriptorCount = true;
908 features->runtimeDescriptorArray = true;
909 break;
910 }
911 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
912 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
913 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
914 features->conditionalRendering = true;
915 features->inheritedConditionalRendering = false;
916 break;
917 }
918 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
919 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
920 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
921 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
922 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
923 break;
924 }
925 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
926 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
927 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
928 features->transformFeedback = true;
929 features->geometryStreams = true;
930 break;
931 }
932 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT: {
933 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *features =
934 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *)ext;
935 features->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
936 break;
937 }
938 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
939 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
940 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
941 features->memoryPriority = VK_TRUE;
942 break;
943 }
944 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
945 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
946 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
947 features->bufferDeviceAddress = true;
948 features->bufferDeviceAddressCaptureReplay = false;
949 features->bufferDeviceAddressMultiDevice = false;
950 break;
951 }
952 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
953 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
954 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
955 features->depthClipEnable = true;
956 break;
957 }
958 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT: {
959 VkPhysicalDeviceHostQueryResetFeaturesEXT *features =
960 (VkPhysicalDeviceHostQueryResetFeaturesEXT *)ext;
961 features->hostQueryReset = true;
962 break;
963 }
964 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR: {
965 VkPhysicalDevice8BitStorageFeaturesKHR *features =
966 (VkPhysicalDevice8BitStorageFeaturesKHR*)ext;
967 bool enabled = pdevice->rad_info.chip_class >= GFX8;
968 features->storageBuffer8BitAccess = enabled;
969 features->uniformAndStorageBuffer8BitAccess = enabled;
970 features->storagePushConstant8 = enabled;
971 break;
972 }
973 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT16_INT8_FEATURES_KHR: {
974 VkPhysicalDeviceFloat16Int8FeaturesKHR *features =
975 (VkPhysicalDeviceFloat16Int8FeaturesKHR*)ext;
976 features->shaderFloat16 = pdevice->rad_info.chip_class >= GFX8;
977 features->shaderInt8 = true;
978 break;
979 }
980 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR: {
981 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *features =
982 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *)ext;
983 features->shaderBufferInt64Atomics = LLVM_VERSION_MAJOR >= 9;
984 features->shaderSharedInt64Atomics = LLVM_VERSION_MAJOR >= 9;
985 break;
986 }
987 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
988 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
989 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
990
991 features->inlineUniformBlock = true;
992 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
993 break;
994 }
995 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
996 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
997 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
998 features->computeDerivativeGroupQuads = false;
999 features->computeDerivativeGroupLinear = true;
1000 break;
1001 }
1002 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
1003 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
1004 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
1005 features->ycbcrImageArrays = true;
1006 break;
1007 }
1008 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES_KHR: {
1009 VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *features =
1010 (VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *)ext;
1011 features->uniformBufferStandardLayout = true;
1012 break;
1013 }
1014 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT: {
1015 VkPhysicalDeviceIndexTypeUint8FeaturesEXT *features =
1016 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT *)ext;
1017 features->indexTypeUint8 = pdevice->rad_info.chip_class >= GFX8;
1018 break;
1019 }
1020 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGELESS_FRAMEBUFFER_FEATURES_KHR: {
1021 VkPhysicalDeviceImagelessFramebufferFeaturesKHR *features =
1022 (VkPhysicalDeviceImagelessFramebufferFeaturesKHR *)ext;
1023 features->imagelessFramebuffer = true;
1024 break;
1025 }
1026 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR: {
1027 VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *features =
1028 (VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *)ext;
1029 features->pipelineExecutableInfo = true;
1030 break;
1031 }
1032 default:
1033 break;
1034 }
1035 }
1036 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
1037 }
1038
1039 void radv_GetPhysicalDeviceProperties(
1040 VkPhysicalDevice physicalDevice,
1041 VkPhysicalDeviceProperties* pProperties)
1042 {
1043 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1044 VkSampleCountFlags sample_counts = 0xf;
1045
1046 /* make sure that the entire descriptor set is addressable with a signed
1047 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1048 * be at most 2 GiB. the combined image & samples object count as one of
1049 * both. This limit is for the pipeline layout, not for the set layout, but
1050 * there is no set limit, so we just set a pipeline limit. I don't think
1051 * any app is going to hit this soon. */
1052 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1053 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1054 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1055 32 /* sampler, largest when combined with image */ +
1056 64 /* sampled image */ +
1057 64 /* storage image */);
1058
1059 VkPhysicalDeviceLimits limits = {
1060 .maxImageDimension1D = (1 << 14),
1061 .maxImageDimension2D = (1 << 14),
1062 .maxImageDimension3D = (1 << 11),
1063 .maxImageDimensionCube = (1 << 14),
1064 .maxImageArrayLayers = (1 << 11),
1065 .maxTexelBufferElements = 128 * 1024 * 1024,
1066 .maxUniformBufferRange = UINT32_MAX,
1067 .maxStorageBufferRange = UINT32_MAX,
1068 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1069 .maxMemoryAllocationCount = UINT32_MAX,
1070 .maxSamplerAllocationCount = 64 * 1024,
1071 .bufferImageGranularity = 64, /* A cache line */
1072 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
1073 .maxBoundDescriptorSets = MAX_SETS,
1074 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1075 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1076 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1077 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1078 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1079 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1080 .maxPerStageResources = max_descriptor_set_size,
1081 .maxDescriptorSetSamplers = max_descriptor_set_size,
1082 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1083 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1084 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1085 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1086 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1087 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1088 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1089 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1090 .maxVertexInputBindings = MAX_VBS,
1091 .maxVertexInputAttributeOffset = 2047,
1092 .maxVertexInputBindingStride = 2048,
1093 .maxVertexOutputComponents = 128,
1094 .maxTessellationGenerationLevel = 64,
1095 .maxTessellationPatchSize = 32,
1096 .maxTessellationControlPerVertexInputComponents = 128,
1097 .maxTessellationControlPerVertexOutputComponents = 128,
1098 .maxTessellationControlPerPatchOutputComponents = 120,
1099 .maxTessellationControlTotalOutputComponents = 4096,
1100 .maxTessellationEvaluationInputComponents = 128,
1101 .maxTessellationEvaluationOutputComponents = 128,
1102 .maxGeometryShaderInvocations = 127,
1103 .maxGeometryInputComponents = 64,
1104 .maxGeometryOutputComponents = 128,
1105 .maxGeometryOutputVertices = 256,
1106 .maxGeometryTotalOutputComponents = 1024,
1107 .maxFragmentInputComponents = 128,
1108 .maxFragmentOutputAttachments = 8,
1109 .maxFragmentDualSrcAttachments = 1,
1110 .maxFragmentCombinedOutputResources = 8,
1111 .maxComputeSharedMemorySize = 32768,
1112 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1113 .maxComputeWorkGroupInvocations = 2048,
1114 .maxComputeWorkGroupSize = {
1115 2048,
1116 2048,
1117 2048
1118 },
1119 .subPixelPrecisionBits = 8,
1120 .subTexelPrecisionBits = 8,
1121 .mipmapPrecisionBits = 8,
1122 .maxDrawIndexedIndexValue = UINT32_MAX,
1123 .maxDrawIndirectCount = UINT32_MAX,
1124 .maxSamplerLodBias = 16,
1125 .maxSamplerAnisotropy = 16,
1126 .maxViewports = MAX_VIEWPORTS,
1127 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1128 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1129 .viewportSubPixelBits = 8,
1130 .minMemoryMapAlignment = 4096, /* A page */
1131 .minTexelBufferOffsetAlignment = 1,
1132 .minUniformBufferOffsetAlignment = 4,
1133 .minStorageBufferOffsetAlignment = 4,
1134 .minTexelOffset = -32,
1135 .maxTexelOffset = 31,
1136 .minTexelGatherOffset = -32,
1137 .maxTexelGatherOffset = 31,
1138 .minInterpolationOffset = -2,
1139 .maxInterpolationOffset = 2,
1140 .subPixelInterpolationOffsetBits = 8,
1141 .maxFramebufferWidth = (1 << 14),
1142 .maxFramebufferHeight = (1 << 14),
1143 .maxFramebufferLayers = (1 << 10),
1144 .framebufferColorSampleCounts = sample_counts,
1145 .framebufferDepthSampleCounts = sample_counts,
1146 .framebufferStencilSampleCounts = sample_counts,
1147 .framebufferNoAttachmentsSampleCounts = sample_counts,
1148 .maxColorAttachments = MAX_RTS,
1149 .sampledImageColorSampleCounts = sample_counts,
1150 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
1151 .sampledImageDepthSampleCounts = sample_counts,
1152 .sampledImageStencilSampleCounts = sample_counts,
1153 .storageImageSampleCounts = pdevice->rad_info.chip_class >= GFX8 ? sample_counts : VK_SAMPLE_COUNT_1_BIT,
1154 .maxSampleMaskWords = 1,
1155 .timestampComputeAndGraphics = true,
1156 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1157 .maxClipDistances = 8,
1158 .maxCullDistances = 8,
1159 .maxCombinedClipAndCullDistances = 8,
1160 .discreteQueuePriorities = 2,
1161 .pointSizeRange = { 0.0, 8192.0 },
1162 .lineWidthRange = { 0.0, 7.9921875 },
1163 .pointSizeGranularity = (1.0 / 8.0),
1164 .lineWidthGranularity = (1.0 / 128.0),
1165 .strictLines = false, /* FINISHME */
1166 .standardSampleLocations = true,
1167 .optimalBufferCopyOffsetAlignment = 128,
1168 .optimalBufferCopyRowPitchAlignment = 128,
1169 .nonCoherentAtomSize = 64,
1170 };
1171
1172 *pProperties = (VkPhysicalDeviceProperties) {
1173 .apiVersion = radv_physical_device_api_version(pdevice),
1174 .driverVersion = vk_get_driver_version(),
1175 .vendorID = ATI_VENDOR_ID,
1176 .deviceID = pdevice->rad_info.pci_id,
1177 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1178 .limits = limits,
1179 .sparseProperties = {0},
1180 };
1181
1182 strcpy(pProperties->deviceName, pdevice->name);
1183 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1184 }
1185
1186 void radv_GetPhysicalDeviceProperties2(
1187 VkPhysicalDevice physicalDevice,
1188 VkPhysicalDeviceProperties2 *pProperties)
1189 {
1190 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1191 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1192
1193 vk_foreach_struct(ext, pProperties->pNext) {
1194 switch (ext->sType) {
1195 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1196 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1197 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1198 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1199 break;
1200 }
1201 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1202 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1203 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1204 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1205 properties->deviceLUIDValid = false;
1206 break;
1207 }
1208 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1209 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1210 properties->maxMultiviewViewCount = MAX_VIEWS;
1211 properties->maxMultiviewInstanceIndex = INT_MAX;
1212 break;
1213 }
1214 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1215 VkPhysicalDevicePointClippingProperties *properties =
1216 (VkPhysicalDevicePointClippingProperties*)ext;
1217 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1218 break;
1219 }
1220 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1221 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1222 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1223 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1224 break;
1225 }
1226 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1227 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1228 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1229 properties->minImportedHostPointerAlignment = 4096;
1230 break;
1231 }
1232 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1233 VkPhysicalDeviceSubgroupProperties *properties =
1234 (VkPhysicalDeviceSubgroupProperties*)ext;
1235 properties->subgroupSize = 64;
1236 properties->supportedStages = VK_SHADER_STAGE_ALL;
1237 properties->supportedOperations =
1238 VK_SUBGROUP_FEATURE_BASIC_BIT |
1239 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1240 VK_SUBGROUP_FEATURE_QUAD_BIT |
1241 VK_SUBGROUP_FEATURE_VOTE_BIT;
1242 if (pdevice->rad_info.chip_class >= GFX8) {
1243 properties->supportedOperations |=
1244 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1245 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1246 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1247 }
1248 properties->quadOperationsInAllStages = true;
1249 break;
1250 }
1251 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1252 VkPhysicalDeviceMaintenance3Properties *properties =
1253 (VkPhysicalDeviceMaintenance3Properties*)ext;
1254 /* Make sure everything is addressable by a signed 32-bit int, and
1255 * our largest descriptors are 96 bytes. */
1256 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1257 /* Our buffer size fields allow only this much */
1258 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1259 break;
1260 }
1261 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1262 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1263 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1264 /* GFX6-8 only support single channel min/max filter. */
1265 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1266 properties->filterMinmaxSingleComponentFormats = true;
1267 break;
1268 }
1269 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1270 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1271 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1272
1273 /* Shader engines. */
1274 properties->shaderEngineCount =
1275 pdevice->rad_info.max_se;
1276 properties->shaderArraysPerEngineCount =
1277 pdevice->rad_info.max_sh_per_se;
1278 properties->computeUnitsPerShaderArray =
1279 pdevice->rad_info.num_good_cu_per_sh;
1280 properties->simdPerComputeUnit = 4;
1281 properties->wavefrontsPerSimd =
1282 pdevice->rad_info.family == CHIP_TONGA ||
1283 pdevice->rad_info.family == CHIP_ICELAND ||
1284 pdevice->rad_info.family == CHIP_POLARIS10 ||
1285 pdevice->rad_info.family == CHIP_POLARIS11 ||
1286 pdevice->rad_info.family == CHIP_POLARIS12 ||
1287 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1288 properties->wavefrontSize = 64;
1289
1290 /* SGPR. */
1291 properties->sgprsPerSimd =
1292 ac_get_num_physical_sgprs(&pdevice->rad_info);
1293 properties->minSgprAllocation =
1294 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1295 properties->maxSgprAllocation =
1296 pdevice->rad_info.family == CHIP_TONGA ||
1297 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1298 properties->sgprAllocationGranularity =
1299 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1300
1301 /* VGPR. */
1302 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1303 properties->minVgprAllocation = 4;
1304 properties->maxVgprAllocation = 256;
1305 properties->vgprAllocationGranularity = 4;
1306 break;
1307 }
1308 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_2_AMD: {
1309 VkPhysicalDeviceShaderCoreProperties2AMD *properties =
1310 (VkPhysicalDeviceShaderCoreProperties2AMD *)ext;
1311
1312 properties->shaderCoreFeatures = 0;
1313 properties->activeComputeUnitCount =
1314 pdevice->rad_info.num_good_compute_units;
1315 break;
1316 }
1317 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1318 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1319 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1320 properties->maxVertexAttribDivisor = UINT32_MAX;
1321 break;
1322 }
1323 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1324 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1325 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1326 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1327 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1328 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1329 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1330 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1331 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1332 properties->robustBufferAccessUpdateAfterBind = false;
1333 properties->quadDivergentImplicitLod = false;
1334
1335 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1336 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1337 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1338 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1339 32 /* sampler, largest when combined with image */ +
1340 64 /* sampled image */ +
1341 64 /* storage image */);
1342 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1343 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1344 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1345 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1346 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1347 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1348 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1349 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1350 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1351 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1352 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1353 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1354 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1355 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1356 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1357 break;
1358 }
1359 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1360 VkPhysicalDeviceProtectedMemoryProperties *properties =
1361 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1362 properties->protectedNoFault = false;
1363 break;
1364 }
1365 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1366 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1367 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1368 properties->primitiveOverestimationSize = 0;
1369 properties->maxExtraPrimitiveOverestimationSize = 0;
1370 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1371 properties->primitiveUnderestimation = VK_FALSE;
1372 properties->conservativePointAndLineRasterization = VK_FALSE;
1373 properties->degenerateTrianglesRasterized = VK_FALSE;
1374 properties->degenerateLinesRasterized = VK_FALSE;
1375 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1376 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1377 break;
1378 }
1379 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1380 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1381 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1382 properties->pciDomain = pdevice->bus_info.domain;
1383 properties->pciBus = pdevice->bus_info.bus;
1384 properties->pciDevice = pdevice->bus_info.dev;
1385 properties->pciFunction = pdevice->bus_info.func;
1386 break;
1387 }
1388 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
1389 VkPhysicalDeviceDriverPropertiesKHR *driver_props =
1390 (VkPhysicalDeviceDriverPropertiesKHR *) ext;
1391
1392 driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
1393 snprintf(driver_props->driverName, VK_MAX_DRIVER_NAME_SIZE_KHR, "radv");
1394 snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
1395 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1396 " (LLVM " MESA_LLVM_VERSION_STRING ")");
1397
1398 driver_props->conformanceVersion = (VkConformanceVersionKHR) {
1399 .major = 1,
1400 .minor = 1,
1401 .subminor = 2,
1402 .patch = 0,
1403 };
1404 break;
1405 }
1406 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1407 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1408 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1409 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1410 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1411 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1412 properties->maxTransformFeedbackStreamDataSize = 512;
1413 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1414 properties->maxTransformFeedbackBufferDataStride = 512;
1415 properties->transformFeedbackQueries = true;
1416 properties->transformFeedbackStreamsLinesTriangles = true;
1417 properties->transformFeedbackRasterizationStreamSelect = false;
1418 properties->transformFeedbackDraw = true;
1419 break;
1420 }
1421 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1422 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1423 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1424
1425 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1426 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1427 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1428 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1429 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1430 break;
1431 }
1432 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT: {
1433 VkPhysicalDeviceSampleLocationsPropertiesEXT *properties =
1434 (VkPhysicalDeviceSampleLocationsPropertiesEXT *)ext;
1435 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_2_BIT |
1436 VK_SAMPLE_COUNT_4_BIT |
1437 VK_SAMPLE_COUNT_8_BIT;
1438 properties->maxSampleLocationGridSize = (VkExtent2D){ 2 , 2 };
1439 properties->sampleLocationCoordinateRange[0] = 0.0f;
1440 properties->sampleLocationCoordinateRange[1] = 0.9375f;
1441 properties->sampleLocationSubPixelBits = 4;
1442 properties->variableSampleLocations = VK_FALSE;
1443 break;
1444 }
1445 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES_KHR: {
1446 VkPhysicalDeviceDepthStencilResolvePropertiesKHR *properties =
1447 (VkPhysicalDeviceDepthStencilResolvePropertiesKHR *)ext;
1448
1449 /* We support all of the depth resolve modes */
1450 properties->supportedDepthResolveModes =
1451 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1452 VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
1453 VK_RESOLVE_MODE_MIN_BIT_KHR |
1454 VK_RESOLVE_MODE_MAX_BIT_KHR;
1455
1456 /* Average doesn't make sense for stencil so we don't support that */
1457 properties->supportedStencilResolveModes =
1458 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1459 VK_RESOLVE_MODE_MIN_BIT_KHR |
1460 VK_RESOLVE_MODE_MAX_BIT_KHR;
1461
1462 properties->independentResolveNone = VK_TRUE;
1463 properties->independentResolve = VK_TRUE;
1464 break;
1465 }
1466 default:
1467 break;
1468 }
1469 }
1470 }
1471
1472 static void radv_get_physical_device_queue_family_properties(
1473 struct radv_physical_device* pdevice,
1474 uint32_t* pCount,
1475 VkQueueFamilyProperties** pQueueFamilyProperties)
1476 {
1477 int num_queue_families = 1;
1478 int idx;
1479 if (pdevice->rad_info.num_compute_rings > 0 &&
1480 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1481 num_queue_families++;
1482
1483 if (pQueueFamilyProperties == NULL) {
1484 *pCount = num_queue_families;
1485 return;
1486 }
1487
1488 if (!*pCount)
1489 return;
1490
1491 idx = 0;
1492 if (*pCount >= 1) {
1493 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1494 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1495 VK_QUEUE_COMPUTE_BIT |
1496 VK_QUEUE_TRANSFER_BIT |
1497 VK_QUEUE_SPARSE_BINDING_BIT,
1498 .queueCount = 1,
1499 .timestampValidBits = 64,
1500 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1501 };
1502 idx++;
1503 }
1504
1505 if (pdevice->rad_info.num_compute_rings > 0 &&
1506 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1507 if (*pCount > idx) {
1508 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1509 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1510 VK_QUEUE_TRANSFER_BIT |
1511 VK_QUEUE_SPARSE_BINDING_BIT,
1512 .queueCount = pdevice->rad_info.num_compute_rings,
1513 .timestampValidBits = 64,
1514 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1515 };
1516 idx++;
1517 }
1518 }
1519 *pCount = idx;
1520 }
1521
1522 void radv_GetPhysicalDeviceQueueFamilyProperties(
1523 VkPhysicalDevice physicalDevice,
1524 uint32_t* pCount,
1525 VkQueueFamilyProperties* pQueueFamilyProperties)
1526 {
1527 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1528 if (!pQueueFamilyProperties) {
1529 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1530 return;
1531 }
1532 VkQueueFamilyProperties *properties[] = {
1533 pQueueFamilyProperties + 0,
1534 pQueueFamilyProperties + 1,
1535 pQueueFamilyProperties + 2,
1536 };
1537 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1538 assert(*pCount <= 3);
1539 }
1540
1541 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1542 VkPhysicalDevice physicalDevice,
1543 uint32_t* pCount,
1544 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1545 {
1546 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1547 if (!pQueueFamilyProperties) {
1548 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1549 return;
1550 }
1551 VkQueueFamilyProperties *properties[] = {
1552 &pQueueFamilyProperties[0].queueFamilyProperties,
1553 &pQueueFamilyProperties[1].queueFamilyProperties,
1554 &pQueueFamilyProperties[2].queueFamilyProperties,
1555 };
1556 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1557 assert(*pCount <= 3);
1558 }
1559
1560 void radv_GetPhysicalDeviceMemoryProperties(
1561 VkPhysicalDevice physicalDevice,
1562 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1563 {
1564 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1565
1566 *pMemoryProperties = physical_device->memory_properties;
1567 }
1568
1569 static void
1570 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1571 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1572 {
1573 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1574 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
1575 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
1576 uint64_t vram_size = radv_get_vram_size(device);
1577 uint64_t gtt_size = device->rad_info.gart_size;
1578 uint64_t heap_budget, heap_usage;
1579
1580 /* For all memory heaps, the computation of budget is as follow:
1581 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1582 *
1583 * The Vulkan spec 1.1.97 says that the budget should include any
1584 * currently allocated device memory.
1585 *
1586 * Note that the application heap usages are not really accurate (eg.
1587 * in presence of shared buffers).
1588 */
1589 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
1590 uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;
1591
1592 switch (device->mem_type_indices[i]) {
1593 case RADV_MEM_TYPE_VRAM:
1594 heap_usage = device->ws->query_value(device->ws,
1595 RADEON_ALLOCATED_VRAM);
1596
1597 heap_budget = vram_size -
1598 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
1599 heap_usage;
1600
1601 memoryBudget->heapBudget[heap_index] = heap_budget;
1602 memoryBudget->heapUsage[heap_index] = heap_usage;
1603 break;
1604 case RADV_MEM_TYPE_VRAM_CPU_ACCESS:
1605 heap_usage = device->ws->query_value(device->ws,
1606 RADEON_ALLOCATED_VRAM_VIS);
1607
1608 heap_budget = visible_vram_size -
1609 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
1610 heap_usage;
1611
1612 memoryBudget->heapBudget[heap_index] = heap_budget;
1613 memoryBudget->heapUsage[heap_index] = heap_usage;
1614 break;
1615 case RADV_MEM_TYPE_GTT_WRITE_COMBINE:
1616 heap_usage = device->ws->query_value(device->ws,
1617 RADEON_ALLOCATED_GTT);
1618
1619 heap_budget = gtt_size -
1620 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
1621 heap_usage;
1622
1623 memoryBudget->heapBudget[heap_index] = heap_budget;
1624 memoryBudget->heapUsage[heap_index] = heap_usage;
1625 break;
1626 default:
1627 break;
1628 }
1629 }
1630
1631 /* The heapBudget and heapUsage values must be zero for array elements
1632 * greater than or equal to
1633 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1634 */
1635 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
1636 memoryBudget->heapBudget[i] = 0;
1637 memoryBudget->heapUsage[i] = 0;
1638 }
1639 }
1640
1641 void radv_GetPhysicalDeviceMemoryProperties2(
1642 VkPhysicalDevice physicalDevice,
1643 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
1644 {
1645 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1646 &pMemoryProperties->memoryProperties);
1647
1648 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
1649 vk_find_struct(pMemoryProperties->pNext,
1650 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
1651 if (memory_budget)
1652 radv_get_memory_budget_properties(physicalDevice, memory_budget);
1653 }
1654
1655 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1656 VkDevice _device,
1657 VkExternalMemoryHandleTypeFlagBits handleType,
1658 const void *pHostPointer,
1659 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1660 {
1661 RADV_FROM_HANDLE(radv_device, device, _device);
1662
1663 switch (handleType)
1664 {
1665 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1666 const struct radv_physical_device *physical_device = device->physical_device;
1667 uint32_t memoryTypeBits = 0;
1668 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1669 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1670 memoryTypeBits = (1 << i);
1671 break;
1672 }
1673 }
1674 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1675 return VK_SUCCESS;
1676 }
1677 default:
1678 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
1679 }
1680 }
1681
1682 static enum radeon_ctx_priority
1683 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1684 {
1685 /* Default to MEDIUM when a specific global priority isn't requested */
1686 if (!pObj)
1687 return RADEON_CTX_PRIORITY_MEDIUM;
1688
1689 switch(pObj->globalPriority) {
1690 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1691 return RADEON_CTX_PRIORITY_REALTIME;
1692 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1693 return RADEON_CTX_PRIORITY_HIGH;
1694 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1695 return RADEON_CTX_PRIORITY_MEDIUM;
1696 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1697 return RADEON_CTX_PRIORITY_LOW;
1698 default:
1699 unreachable("Illegal global priority value");
1700 return RADEON_CTX_PRIORITY_INVALID;
1701 }
1702 }
1703
1704 static int
1705 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1706 uint32_t queue_family_index, int idx,
1707 VkDeviceQueueCreateFlags flags,
1708 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1709 {
1710 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1711 queue->device = device;
1712 queue->queue_family_index = queue_family_index;
1713 queue->queue_idx = idx;
1714 queue->priority = radv_get_queue_global_priority(global_priority);
1715 queue->flags = flags;
1716
1717 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1718 if (!queue->hw_ctx)
1719 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1720
1721 return VK_SUCCESS;
1722 }
1723
1724 static void
1725 radv_queue_finish(struct radv_queue *queue)
1726 {
1727 if (queue->hw_ctx)
1728 queue->device->ws->ctx_destroy(queue->hw_ctx);
1729
1730 if (queue->initial_full_flush_preamble_cs)
1731 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1732 if (queue->initial_preamble_cs)
1733 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1734 if (queue->continue_preamble_cs)
1735 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1736 if (queue->descriptor_bo)
1737 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1738 if (queue->scratch_bo)
1739 queue->device->ws->buffer_destroy(queue->scratch_bo);
1740 if (queue->esgs_ring_bo)
1741 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1742 if (queue->gsvs_ring_bo)
1743 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1744 if (queue->tess_rings_bo)
1745 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1746 if (queue->compute_scratch_bo)
1747 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1748 }
1749
1750 static void
1751 radv_bo_list_init(struct radv_bo_list *bo_list)
1752 {
1753 pthread_mutex_init(&bo_list->mutex, NULL);
1754 bo_list->list.count = bo_list->capacity = 0;
1755 bo_list->list.bos = NULL;
1756 }
1757
1758 static void
1759 radv_bo_list_finish(struct radv_bo_list *bo_list)
1760 {
1761 free(bo_list->list.bos);
1762 pthread_mutex_destroy(&bo_list->mutex);
1763 }
1764
1765 static VkResult radv_bo_list_add(struct radv_device *device,
1766 struct radeon_winsys_bo *bo)
1767 {
1768 struct radv_bo_list *bo_list = &device->bo_list;
1769
1770 if (bo->is_local)
1771 return VK_SUCCESS;
1772
1773 if (unlikely(!device->use_global_bo_list))
1774 return VK_SUCCESS;
1775
1776 pthread_mutex_lock(&bo_list->mutex);
1777 if (bo_list->list.count == bo_list->capacity) {
1778 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1779 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1780
1781 if (!data) {
1782 pthread_mutex_unlock(&bo_list->mutex);
1783 return VK_ERROR_OUT_OF_HOST_MEMORY;
1784 }
1785
1786 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1787 bo_list->capacity = capacity;
1788 }
1789
1790 bo_list->list.bos[bo_list->list.count++] = bo;
1791 pthread_mutex_unlock(&bo_list->mutex);
1792 return VK_SUCCESS;
1793 }
1794
1795 static void radv_bo_list_remove(struct radv_device *device,
1796 struct radeon_winsys_bo *bo)
1797 {
1798 struct radv_bo_list *bo_list = &device->bo_list;
1799
1800 if (bo->is_local)
1801 return;
1802
1803 if (unlikely(!device->use_global_bo_list))
1804 return;
1805
1806 pthread_mutex_lock(&bo_list->mutex);
1807 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1808 if (bo_list->list.bos[i] == bo) {
1809 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1810 --bo_list->list.count;
1811 break;
1812 }
1813 }
1814 pthread_mutex_unlock(&bo_list->mutex);
1815 }
1816
1817 static void
1818 radv_device_init_gs_info(struct radv_device *device)
1819 {
1820 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1821 device->physical_device->rad_info.family);
1822 }
1823
1824 static int radv_get_device_extension_index(const char *name)
1825 {
1826 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1827 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1828 return i;
1829 }
1830 return -1;
1831 }
1832
1833 static int
1834 radv_get_int_debug_option(const char *name, int default_value)
1835 {
1836 const char *str;
1837 int result;
1838
1839 str = getenv(name);
1840 if (!str) {
1841 result = default_value;
1842 } else {
1843 char *endptr;
1844
1845 result = strtol(str, &endptr, 0);
1846 if (str == endptr) {
1847 /* No digits founs. */
1848 result = default_value;
1849 }
1850 }
1851
1852 return result;
1853 }
1854
1855 VkResult radv_CreateDevice(
1856 VkPhysicalDevice physicalDevice,
1857 const VkDeviceCreateInfo* pCreateInfo,
1858 const VkAllocationCallbacks* pAllocator,
1859 VkDevice* pDevice)
1860 {
1861 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1862 VkResult result;
1863 struct radv_device *device;
1864
1865 bool keep_shader_info = false;
1866
1867 /* Check enabled features */
1868 if (pCreateInfo->pEnabledFeatures) {
1869 VkPhysicalDeviceFeatures supported_features;
1870 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1871 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1872 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1873 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1874 for (uint32_t i = 0; i < num_features; i++) {
1875 if (enabled_feature[i] && !supported_feature[i])
1876 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1877 }
1878 }
1879
1880 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1881 sizeof(*device), 8,
1882 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1883 if (!device)
1884 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1885
1886 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1887 device->instance = physical_device->instance;
1888 device->physical_device = physical_device;
1889
1890 device->ws = physical_device->ws;
1891 if (pAllocator)
1892 device->alloc = *pAllocator;
1893 else
1894 device->alloc = physical_device->instance->alloc;
1895
1896 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1897 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1898 int index = radv_get_device_extension_index(ext_name);
1899 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1900 vk_free(&device->alloc, device);
1901 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1902 }
1903
1904 device->enabled_extensions.extensions[index] = true;
1905 }
1906
1907 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1908
1909 /* With update after bind we can't attach bo's to the command buffer
1910 * from the descriptor set anymore, so we have to use a global BO list.
1911 */
1912 device->use_global_bo_list =
1913 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
1914 device->enabled_extensions.EXT_descriptor_indexing ||
1915 device->enabled_extensions.EXT_buffer_device_address;
1916
1917 device->robust_buffer_access = pCreateInfo->pEnabledFeatures &&
1918 pCreateInfo->pEnabledFeatures->robustBufferAccess;
1919
1920 mtx_init(&device->shader_slab_mutex, mtx_plain);
1921 list_inithead(&device->shader_slabs);
1922
1923 radv_bo_list_init(&device->bo_list);
1924
1925 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1926 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1927 uint32_t qfi = queue_create->queueFamilyIndex;
1928 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1929 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1930
1931 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1932
1933 device->queues[qfi] = vk_alloc(&device->alloc,
1934 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1935 if (!device->queues[qfi]) {
1936 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1937 goto fail;
1938 }
1939
1940 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1941
1942 device->queue_count[qfi] = queue_create->queueCount;
1943
1944 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1945 result = radv_queue_init(device, &device->queues[qfi][q],
1946 qfi, q, queue_create->flags,
1947 global_priority);
1948 if (result != VK_SUCCESS)
1949 goto fail;
1950 }
1951 }
1952
1953 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1954 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
1955
1956 device->dfsm_allowed = device->pbb_allowed &&
1957 (device->physical_device->rad_info.family == CHIP_RAVEN ||
1958 device->physical_device->rad_info.family == CHIP_RAVEN2 ||
1959 device->physical_device->rad_info.family == CHIP_RENOIR);
1960
1961 #ifdef ANDROID
1962 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1963 #endif
1964
1965 /* The maximum number of scratch waves. Scratch space isn't divided
1966 * evenly between CUs. The number is only a function of the number of CUs.
1967 * We can decrease the constant to decrease the scratch buffer size.
1968 *
1969 * sctx->scratch_waves must be >= the maximum possible size of
1970 * 1 threadgroup, so that the hw doesn't hang from being unable
1971 * to start any.
1972 *
1973 * The recommended value is 4 per CU at most. Higher numbers don't
1974 * bring much benefit, but they still occupy chip resources (think
1975 * async compute). I've seen ~2% performance difference between 4 and 32.
1976 */
1977 uint32_t max_threads_per_block = 2048;
1978 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1979 max_threads_per_block / 64);
1980
1981 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) |
1982 S_00B800_CS_W32_EN(device->physical_device->cs_wave_size == 32);
1983
1984 if (device->physical_device->rad_info.chip_class >= GFX7) {
1985 /* If the KMD allows it (there is a KMD hw register for it),
1986 * allow launching waves out-of-order.
1987 */
1988 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1989 }
1990
1991 radv_device_init_gs_info(device);
1992
1993 device->tess_offchip_block_dw_size =
1994 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1995
1996 if (getenv("RADV_TRACE_FILE")) {
1997 const char *filename = getenv("RADV_TRACE_FILE");
1998
1999 keep_shader_info = true;
2000
2001 if (!radv_init_trace(device))
2002 goto fail;
2003
2004 fprintf(stderr, "*****************************************************************************\n");
2005 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
2006 fprintf(stderr, "*****************************************************************************\n");
2007
2008 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
2009 radv_dump_enabled_options(device, stderr);
2010 }
2011
2012 device->keep_shader_info = keep_shader_info;
2013
2014 result = radv_device_init_meta(device);
2015 if (result != VK_SUCCESS)
2016 goto fail;
2017
2018 radv_device_init_msaa(device);
2019
2020 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
2021 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
2022 switch (family) {
2023 case RADV_QUEUE_GENERAL:
2024 /* Since amdgpu version 3.6.0, CONTEXT_CONTROL is emitted by the kernel */
2025 if (device->physical_device->rad_info.drm_minor < 6) {
2026 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2027 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
2028 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
2029 }
2030 break;
2031 case RADV_QUEUE_COMPUTE:
2032 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
2033 radeon_emit(device->empty_cs[family], 0);
2034 break;
2035 }
2036 device->ws->cs_finalize(device->empty_cs[family]);
2037 }
2038
2039 if (device->physical_device->rad_info.chip_class >= GFX7)
2040 cik_create_gfx_config(device);
2041
2042 VkPipelineCacheCreateInfo ci;
2043 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
2044 ci.pNext = NULL;
2045 ci.flags = 0;
2046 ci.pInitialData = NULL;
2047 ci.initialDataSize = 0;
2048 VkPipelineCache pc;
2049 result = radv_CreatePipelineCache(radv_device_to_handle(device),
2050 &ci, NULL, &pc);
2051 if (result != VK_SUCCESS)
2052 goto fail_meta;
2053
2054 device->mem_cache = radv_pipeline_cache_from_handle(pc);
2055
2056 device->force_aniso =
2057 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
2058 if (device->force_aniso >= 0) {
2059 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
2060 1 << util_logbase2(device->force_aniso));
2061 }
2062
2063 *pDevice = radv_device_to_handle(device);
2064 return VK_SUCCESS;
2065
2066 fail_meta:
2067 radv_device_finish_meta(device);
2068 fail:
2069 radv_bo_list_finish(&device->bo_list);
2070
2071 if (device->trace_bo)
2072 device->ws->buffer_destroy(device->trace_bo);
2073
2074 if (device->gfx_init)
2075 device->ws->buffer_destroy(device->gfx_init);
2076
2077 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2078 for (unsigned q = 0; q < device->queue_count[i]; q++)
2079 radv_queue_finish(&device->queues[i][q]);
2080 if (device->queue_count[i])
2081 vk_free(&device->alloc, device->queues[i]);
2082 }
2083
2084 vk_free(&device->alloc, device);
2085 return result;
2086 }
2087
2088 void radv_DestroyDevice(
2089 VkDevice _device,
2090 const VkAllocationCallbacks* pAllocator)
2091 {
2092 RADV_FROM_HANDLE(radv_device, device, _device);
2093
2094 if (!device)
2095 return;
2096
2097 if (device->trace_bo)
2098 device->ws->buffer_destroy(device->trace_bo);
2099
2100 if (device->gfx_init)
2101 device->ws->buffer_destroy(device->gfx_init);
2102
2103 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2104 for (unsigned q = 0; q < device->queue_count[i]; q++)
2105 radv_queue_finish(&device->queues[i][q]);
2106 if (device->queue_count[i])
2107 vk_free(&device->alloc, device->queues[i]);
2108 if (device->empty_cs[i])
2109 device->ws->cs_destroy(device->empty_cs[i]);
2110 }
2111 radv_device_finish_meta(device);
2112
2113 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
2114 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2115
2116 radv_destroy_shader_slabs(device);
2117
2118 radv_bo_list_finish(&device->bo_list);
2119 vk_free(&device->alloc, device);
2120 }
2121
2122 VkResult radv_EnumerateInstanceLayerProperties(
2123 uint32_t* pPropertyCount,
2124 VkLayerProperties* pProperties)
2125 {
2126 if (pProperties == NULL) {
2127 *pPropertyCount = 0;
2128 return VK_SUCCESS;
2129 }
2130
2131 /* None supported at this time */
2132 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2133 }
2134
2135 VkResult radv_EnumerateDeviceLayerProperties(
2136 VkPhysicalDevice physicalDevice,
2137 uint32_t* pPropertyCount,
2138 VkLayerProperties* pProperties)
2139 {
2140 if (pProperties == NULL) {
2141 *pPropertyCount = 0;
2142 return VK_SUCCESS;
2143 }
2144
2145 /* None supported at this time */
2146 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2147 }
2148
2149 void radv_GetDeviceQueue2(
2150 VkDevice _device,
2151 const VkDeviceQueueInfo2* pQueueInfo,
2152 VkQueue* pQueue)
2153 {
2154 RADV_FROM_HANDLE(radv_device, device, _device);
2155 struct radv_queue *queue;
2156
2157 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
2158 if (pQueueInfo->flags != queue->flags) {
2159 /* From the Vulkan 1.1.70 spec:
2160 *
2161 * "The queue returned by vkGetDeviceQueue2 must have the same
2162 * flags value from this structure as that used at device
2163 * creation time in a VkDeviceQueueCreateInfo instance. If no
2164 * matching flags were specified at device creation time then
2165 * pQueue will return VK_NULL_HANDLE."
2166 */
2167 *pQueue = VK_NULL_HANDLE;
2168 return;
2169 }
2170
2171 *pQueue = radv_queue_to_handle(queue);
2172 }
2173
2174 void radv_GetDeviceQueue(
2175 VkDevice _device,
2176 uint32_t queueFamilyIndex,
2177 uint32_t queueIndex,
2178 VkQueue* pQueue)
2179 {
2180 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
2181 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
2182 .queueFamilyIndex = queueFamilyIndex,
2183 .queueIndex = queueIndex
2184 };
2185
2186 radv_GetDeviceQueue2(_device, &info, pQueue);
2187 }
2188
2189 static void
2190 fill_geom_tess_rings(struct radv_queue *queue,
2191 uint32_t *map,
2192 bool add_sample_positions,
2193 uint32_t esgs_ring_size,
2194 struct radeon_winsys_bo *esgs_ring_bo,
2195 uint32_t gsvs_ring_size,
2196 struct radeon_winsys_bo *gsvs_ring_bo,
2197 uint32_t tess_factor_ring_size,
2198 uint32_t tess_offchip_ring_offset,
2199 uint32_t tess_offchip_ring_size,
2200 struct radeon_winsys_bo *tess_rings_bo)
2201 {
2202 uint32_t *desc = &map[4];
2203
2204 if (esgs_ring_bo) {
2205 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
2206
2207 /* stride 0, num records - size, add tid, swizzle, elsize4,
2208 index stride 64 */
2209 desc[0] = esgs_va;
2210 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
2211 S_008F04_SWIZZLE_ENABLE(true);
2212 desc[2] = esgs_ring_size;
2213 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2214 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2215 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2216 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2217 S_008F0C_INDEX_STRIDE(3) |
2218 S_008F0C_ADD_TID_ENABLE(1);
2219
2220 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2221 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2222 S_008F0C_OOB_SELECT(2) |
2223 S_008F0C_RESOURCE_LEVEL(1);
2224 } else {
2225 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2226 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2227 S_008F0C_ELEMENT_SIZE(1);
2228 }
2229
2230 /* GS entry for ES->GS ring */
2231 /* stride 0, num records - size, elsize0,
2232 index stride 0 */
2233 desc[4] = esgs_va;
2234 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32);
2235 desc[6] = esgs_ring_size;
2236 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2237 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2238 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2239 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2240
2241 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2242 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2243 S_008F0C_OOB_SELECT(2) |
2244 S_008F0C_RESOURCE_LEVEL(1);
2245 } else {
2246 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2247 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2248 }
2249 }
2250
2251 desc += 8;
2252
2253 if (gsvs_ring_bo) {
2254 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
2255
2256 /* VS entry for GS->VS ring */
2257 /* stride 0, num records - size, elsize0,
2258 index stride 0 */
2259 desc[0] = gsvs_va;
2260 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32);
2261 desc[2] = gsvs_ring_size;
2262 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2263 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2264 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2265 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2266
2267 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2268 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2269 S_008F0C_OOB_SELECT(2) |
2270 S_008F0C_RESOURCE_LEVEL(1);
2271 } else {
2272 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2273 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2274 }
2275
2276 /* stride gsvs_itemsize, num records 64
2277 elsize 4, index stride 16 */
2278 /* shader will patch stride and desc[2] */
2279 desc[4] = gsvs_va;
2280 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32) |
2281 S_008F04_SWIZZLE_ENABLE(1);
2282 desc[6] = 0;
2283 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2284 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2285 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2286 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2287 S_008F0C_INDEX_STRIDE(1) |
2288 S_008F0C_ADD_TID_ENABLE(true);
2289
2290 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2291 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2292 S_008F0C_OOB_SELECT(2) |
2293 S_008F0C_RESOURCE_LEVEL(1);
2294 } else {
2295 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2296 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2297 S_008F0C_ELEMENT_SIZE(1);
2298 }
2299
2300 }
2301
2302 desc += 8;
2303
2304 if (tess_rings_bo) {
2305 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
2306 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
2307
2308 desc[0] = tess_va;
2309 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32);
2310 desc[2] = tess_factor_ring_size;
2311 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2312 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2313 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2314 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2315
2316 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2317 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2318 S_008F0C_OOB_SELECT(3) |
2319 S_008F0C_RESOURCE_LEVEL(1);
2320 } else {
2321 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2322 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2323 }
2324
2325 desc[4] = tess_offchip_va;
2326 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32);
2327 desc[6] = tess_offchip_ring_size;
2328 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2329 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2330 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2331 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2332
2333 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2334 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2335 S_008F0C_OOB_SELECT(3) |
2336 S_008F0C_RESOURCE_LEVEL(1);
2337 } else {
2338 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2339 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2340 }
2341 }
2342
2343 desc += 8;
2344
2345 if (add_sample_positions) {
2346 /* add sample positions after all rings */
2347 memcpy(desc, queue->device->sample_locations_1x, 8);
2348 desc += 2;
2349 memcpy(desc, queue->device->sample_locations_2x, 16);
2350 desc += 4;
2351 memcpy(desc, queue->device->sample_locations_4x, 32);
2352 desc += 8;
2353 memcpy(desc, queue->device->sample_locations_8x, 64);
2354 }
2355 }
2356
2357 static unsigned
2358 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
2359 {
2360 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 &&
2361 device->physical_device->rad_info.family != CHIP_CARRIZO &&
2362 device->physical_device->rad_info.family != CHIP_STONEY;
2363 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2364 unsigned max_offchip_buffers;
2365 unsigned offchip_granularity;
2366 unsigned hs_offchip_param;
2367
2368 /*
2369 * Per RadeonSI:
2370 * This must be one less than the maximum number due to a hw limitation.
2371 * Various hardware bugs need thGFX7
2372 *
2373 * Per AMDVLK:
2374 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2375 * Gfx7 should limit max_offchip_buffers to 508
2376 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2377 *
2378 * Follow AMDVLK here.
2379 */
2380 if (device->physical_device->rad_info.chip_class >= GFX10) {
2381 max_offchip_buffers_per_se = 256;
2382 } else if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
2383 device->physical_device->rad_info.chip_class == GFX7 ||
2384 device->physical_device->rad_info.chip_class == GFX6)
2385 --max_offchip_buffers_per_se;
2386
2387 max_offchip_buffers = max_offchip_buffers_per_se *
2388 device->physical_device->rad_info.max_se;
2389
2390 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2391 * around by setting 4K granularity.
2392 */
2393 if (device->tess_offchip_block_dw_size == 4096) {
2394 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
2395 offchip_granularity = V_03093C_X_4K_DWORDS;
2396 } else {
2397 assert(device->tess_offchip_block_dw_size == 8192);
2398 offchip_granularity = V_03093C_X_8K_DWORDS;
2399 }
2400
2401 switch (device->physical_device->rad_info.chip_class) {
2402 case GFX6:
2403 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2404 break;
2405 case GFX7:
2406 case GFX8:
2407 case GFX9:
2408 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2409 break;
2410 case GFX10:
2411 break;
2412 default:
2413 break;
2414 }
2415
2416 *max_offchip_buffers_p = max_offchip_buffers;
2417 if (device->physical_device->rad_info.chip_class >= GFX7) {
2418 if (device->physical_device->rad_info.chip_class >= GFX8)
2419 --max_offchip_buffers;
2420 hs_offchip_param =
2421 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2422 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2423 } else {
2424 hs_offchip_param =
2425 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2426 }
2427 return hs_offchip_param;
2428 }
2429
2430 static void
2431 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2432 struct radeon_winsys_bo *esgs_ring_bo,
2433 uint32_t esgs_ring_size,
2434 struct radeon_winsys_bo *gsvs_ring_bo,
2435 uint32_t gsvs_ring_size)
2436 {
2437 if (!esgs_ring_bo && !gsvs_ring_bo)
2438 return;
2439
2440 if (esgs_ring_bo)
2441 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2442
2443 if (gsvs_ring_bo)
2444 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2445
2446 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2447 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2448 radeon_emit(cs, esgs_ring_size >> 8);
2449 radeon_emit(cs, gsvs_ring_size >> 8);
2450 } else {
2451 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2452 radeon_emit(cs, esgs_ring_size >> 8);
2453 radeon_emit(cs, gsvs_ring_size >> 8);
2454 }
2455 }
2456
2457 static void
2458 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2459 unsigned hs_offchip_param, unsigned tf_ring_size,
2460 struct radeon_winsys_bo *tess_rings_bo)
2461 {
2462 uint64_t tf_va;
2463
2464 if (!tess_rings_bo)
2465 return;
2466
2467 tf_va = radv_buffer_get_va(tess_rings_bo);
2468
2469 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2470
2471 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2472 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2473 S_030938_SIZE(tf_ring_size / 4));
2474 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2475 tf_va >> 8);
2476
2477 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2478 radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
2479 S_030984_BASE_HI(tf_va >> 40));
2480 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
2481 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2482 S_030944_BASE_HI(tf_va >> 40));
2483 }
2484 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2485 hs_offchip_param);
2486 } else {
2487 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2488 S_008988_SIZE(tf_ring_size / 4));
2489 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2490 tf_va >> 8);
2491 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2492 hs_offchip_param);
2493 }
2494 }
2495
2496 static void
2497 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2498 struct radeon_winsys_bo *compute_scratch_bo)
2499 {
2500 uint64_t scratch_va;
2501
2502 if (!compute_scratch_bo)
2503 return;
2504
2505 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2506
2507 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2508
2509 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2510 radeon_emit(cs, scratch_va);
2511 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2512 S_008F04_SWIZZLE_ENABLE(1));
2513 }
2514
2515 static void
2516 radv_emit_global_shader_pointers(struct radv_queue *queue,
2517 struct radeon_cmdbuf *cs,
2518 struct radeon_winsys_bo *descriptor_bo)
2519 {
2520 uint64_t va;
2521
2522 if (!descriptor_bo)
2523 return;
2524
2525 va = radv_buffer_get_va(descriptor_bo);
2526
2527 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2528
2529 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2530 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2531 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2532 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2533 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2534
2535 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2536 radv_emit_shader_pointer(queue->device, cs, regs[i],
2537 va, true);
2538 }
2539 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
2540 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2541 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2542 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2543 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2544
2545 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2546 radv_emit_shader_pointer(queue->device, cs, regs[i],
2547 va, true);
2548 }
2549 } else {
2550 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2551 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2552 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2553 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2554 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2555 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2556
2557 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2558 radv_emit_shader_pointer(queue->device, cs, regs[i],
2559 va, true);
2560 }
2561 }
2562 }
2563
2564 static void
2565 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2566 {
2567 struct radv_device *device = queue->device;
2568
2569 if (device->gfx_init) {
2570 uint64_t va = radv_buffer_get_va(device->gfx_init);
2571
2572 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2573 radeon_emit(cs, va);
2574 radeon_emit(cs, va >> 32);
2575 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2576
2577 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2578 } else {
2579 struct radv_physical_device *physical_device = device->physical_device;
2580 si_emit_graphics(physical_device, cs);
2581 }
2582 }
2583
2584 static void
2585 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2586 {
2587 struct radv_physical_device *physical_device = queue->device->physical_device;
2588 si_emit_compute(physical_device, cs);
2589 }
2590
2591 static VkResult
2592 radv_get_preamble_cs(struct radv_queue *queue,
2593 uint32_t scratch_size,
2594 uint32_t compute_scratch_size,
2595 uint32_t esgs_ring_size,
2596 uint32_t gsvs_ring_size,
2597 bool needs_tess_rings,
2598 bool needs_sample_positions,
2599 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2600 struct radeon_cmdbuf **initial_preamble_cs,
2601 struct radeon_cmdbuf **continue_preamble_cs)
2602 {
2603 struct radeon_winsys_bo *scratch_bo = NULL;
2604 struct radeon_winsys_bo *descriptor_bo = NULL;
2605 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2606 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2607 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2608 struct radeon_winsys_bo *tess_rings_bo = NULL;
2609 struct radeon_cmdbuf *dest_cs[3] = {0};
2610 bool add_tess_rings = false, add_sample_positions = false;
2611 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2612 unsigned max_offchip_buffers;
2613 unsigned hs_offchip_param = 0;
2614 unsigned tess_offchip_ring_offset;
2615 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2616 if (!queue->has_tess_rings) {
2617 if (needs_tess_rings)
2618 add_tess_rings = true;
2619 }
2620 if (!queue->has_sample_positions) {
2621 if (needs_sample_positions)
2622 add_sample_positions = true;
2623 }
2624 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2625 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2626 &max_offchip_buffers);
2627 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2628 tess_offchip_ring_size = max_offchip_buffers *
2629 queue->device->tess_offchip_block_dw_size * 4;
2630
2631 if (scratch_size <= queue->scratch_size &&
2632 compute_scratch_size <= queue->compute_scratch_size &&
2633 esgs_ring_size <= queue->esgs_ring_size &&
2634 gsvs_ring_size <= queue->gsvs_ring_size &&
2635 !add_tess_rings && !add_sample_positions &&
2636 queue->initial_preamble_cs) {
2637 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2638 *initial_preamble_cs = queue->initial_preamble_cs;
2639 *continue_preamble_cs = queue->continue_preamble_cs;
2640 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2641 *continue_preamble_cs = NULL;
2642 return VK_SUCCESS;
2643 }
2644
2645 if (scratch_size > queue->scratch_size) {
2646 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2647 scratch_size,
2648 4096,
2649 RADEON_DOMAIN_VRAM,
2650 ring_bo_flags,
2651 RADV_BO_PRIORITY_SCRATCH);
2652 if (!scratch_bo)
2653 goto fail;
2654 } else
2655 scratch_bo = queue->scratch_bo;
2656
2657 if (compute_scratch_size > queue->compute_scratch_size) {
2658 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2659 compute_scratch_size,
2660 4096,
2661 RADEON_DOMAIN_VRAM,
2662 ring_bo_flags,
2663 RADV_BO_PRIORITY_SCRATCH);
2664 if (!compute_scratch_bo)
2665 goto fail;
2666
2667 } else
2668 compute_scratch_bo = queue->compute_scratch_bo;
2669
2670 if (esgs_ring_size > queue->esgs_ring_size) {
2671 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2672 esgs_ring_size,
2673 4096,
2674 RADEON_DOMAIN_VRAM,
2675 ring_bo_flags,
2676 RADV_BO_PRIORITY_SCRATCH);
2677 if (!esgs_ring_bo)
2678 goto fail;
2679 } else {
2680 esgs_ring_bo = queue->esgs_ring_bo;
2681 esgs_ring_size = queue->esgs_ring_size;
2682 }
2683
2684 if (gsvs_ring_size > queue->gsvs_ring_size) {
2685 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2686 gsvs_ring_size,
2687 4096,
2688 RADEON_DOMAIN_VRAM,
2689 ring_bo_flags,
2690 RADV_BO_PRIORITY_SCRATCH);
2691 if (!gsvs_ring_bo)
2692 goto fail;
2693 } else {
2694 gsvs_ring_bo = queue->gsvs_ring_bo;
2695 gsvs_ring_size = queue->gsvs_ring_size;
2696 }
2697
2698 if (add_tess_rings) {
2699 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2700 tess_offchip_ring_offset + tess_offchip_ring_size,
2701 256,
2702 RADEON_DOMAIN_VRAM,
2703 ring_bo_flags,
2704 RADV_BO_PRIORITY_SCRATCH);
2705 if (!tess_rings_bo)
2706 goto fail;
2707 } else {
2708 tess_rings_bo = queue->tess_rings_bo;
2709 }
2710
2711 if (scratch_bo != queue->scratch_bo ||
2712 esgs_ring_bo != queue->esgs_ring_bo ||
2713 gsvs_ring_bo != queue->gsvs_ring_bo ||
2714 tess_rings_bo != queue->tess_rings_bo ||
2715 add_sample_positions) {
2716 uint32_t size = 0;
2717 if (gsvs_ring_bo || esgs_ring_bo ||
2718 tess_rings_bo || add_sample_positions) {
2719 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2720 if (add_sample_positions)
2721 size += 128; /* 64+32+16+8 = 120 bytes */
2722 }
2723 else if (scratch_bo)
2724 size = 8; /* 2 dword */
2725
2726 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2727 size,
2728 4096,
2729 RADEON_DOMAIN_VRAM,
2730 RADEON_FLAG_CPU_ACCESS |
2731 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2732 RADEON_FLAG_READ_ONLY,
2733 RADV_BO_PRIORITY_DESCRIPTOR);
2734 if (!descriptor_bo)
2735 goto fail;
2736 } else
2737 descriptor_bo = queue->descriptor_bo;
2738
2739 if (descriptor_bo != queue->descriptor_bo) {
2740 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2741
2742 if (scratch_bo) {
2743 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2744 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2745 S_008F04_SWIZZLE_ENABLE(1);
2746 map[0] = scratch_va;
2747 map[1] = rsrc1;
2748 }
2749
2750 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
2751 fill_geom_tess_rings(queue, map, add_sample_positions,
2752 esgs_ring_size, esgs_ring_bo,
2753 gsvs_ring_size, gsvs_ring_bo,
2754 tess_factor_ring_size,
2755 tess_offchip_ring_offset,
2756 tess_offchip_ring_size,
2757 tess_rings_bo);
2758
2759 queue->device->ws->buffer_unmap(descriptor_bo);
2760 }
2761
2762 for(int i = 0; i < 3; ++i) {
2763 struct radeon_cmdbuf *cs = NULL;
2764 cs = queue->device->ws->cs_create(queue->device->ws,
2765 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2766 if (!cs)
2767 goto fail;
2768
2769 dest_cs[i] = cs;
2770
2771 if (scratch_bo)
2772 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2773
2774 /* Emit initial configuration. */
2775 switch (queue->queue_family_index) {
2776 case RADV_QUEUE_GENERAL:
2777 radv_init_graphics_state(cs, queue);
2778 break;
2779 case RADV_QUEUE_COMPUTE:
2780 radv_init_compute_state(cs, queue);
2781 break;
2782 case RADV_QUEUE_TRANSFER:
2783 break;
2784 }
2785
2786 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2787 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2788 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2789
2790 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2791 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2792 }
2793
2794 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2795 gsvs_ring_bo, gsvs_ring_size);
2796 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2797 tess_factor_ring_size, tess_rings_bo);
2798 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2799 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2800
2801 if (i == 0) {
2802 si_cs_emit_cache_flush(cs,
2803 queue->device->physical_device->rad_info.chip_class,
2804 NULL, 0,
2805 queue->queue_family_index == RING_COMPUTE &&
2806 queue->device->physical_device->rad_info.chip_class >= GFX7,
2807 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2808 RADV_CMD_FLAG_INV_ICACHE |
2809 RADV_CMD_FLAG_INV_SCACHE |
2810 RADV_CMD_FLAG_INV_VCACHE |
2811 RADV_CMD_FLAG_INV_L2 |
2812 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2813 } else if (i == 1) {
2814 si_cs_emit_cache_flush(cs,
2815 queue->device->physical_device->rad_info.chip_class,
2816 NULL, 0,
2817 queue->queue_family_index == RING_COMPUTE &&
2818 queue->device->physical_device->rad_info.chip_class >= GFX7,
2819 RADV_CMD_FLAG_INV_ICACHE |
2820 RADV_CMD_FLAG_INV_SCACHE |
2821 RADV_CMD_FLAG_INV_VCACHE |
2822 RADV_CMD_FLAG_INV_L2 |
2823 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2824 }
2825
2826 if (!queue->device->ws->cs_finalize(cs))
2827 goto fail;
2828 }
2829
2830 if (queue->initial_full_flush_preamble_cs)
2831 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2832
2833 if (queue->initial_preamble_cs)
2834 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2835
2836 if (queue->continue_preamble_cs)
2837 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2838
2839 queue->initial_full_flush_preamble_cs = dest_cs[0];
2840 queue->initial_preamble_cs = dest_cs[1];
2841 queue->continue_preamble_cs = dest_cs[2];
2842
2843 if (scratch_bo != queue->scratch_bo) {
2844 if (queue->scratch_bo)
2845 queue->device->ws->buffer_destroy(queue->scratch_bo);
2846 queue->scratch_bo = scratch_bo;
2847 queue->scratch_size = scratch_size;
2848 }
2849
2850 if (compute_scratch_bo != queue->compute_scratch_bo) {
2851 if (queue->compute_scratch_bo)
2852 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2853 queue->compute_scratch_bo = compute_scratch_bo;
2854 queue->compute_scratch_size = compute_scratch_size;
2855 }
2856
2857 if (esgs_ring_bo != queue->esgs_ring_bo) {
2858 if (queue->esgs_ring_bo)
2859 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2860 queue->esgs_ring_bo = esgs_ring_bo;
2861 queue->esgs_ring_size = esgs_ring_size;
2862 }
2863
2864 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2865 if (queue->gsvs_ring_bo)
2866 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2867 queue->gsvs_ring_bo = gsvs_ring_bo;
2868 queue->gsvs_ring_size = gsvs_ring_size;
2869 }
2870
2871 if (tess_rings_bo != queue->tess_rings_bo) {
2872 queue->tess_rings_bo = tess_rings_bo;
2873 queue->has_tess_rings = true;
2874 }
2875
2876 if (descriptor_bo != queue->descriptor_bo) {
2877 if (queue->descriptor_bo)
2878 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2879
2880 queue->descriptor_bo = descriptor_bo;
2881 }
2882
2883 if (add_sample_positions)
2884 queue->has_sample_positions = true;
2885
2886 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2887 *initial_preamble_cs = queue->initial_preamble_cs;
2888 *continue_preamble_cs = queue->continue_preamble_cs;
2889 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2890 *continue_preamble_cs = NULL;
2891 return VK_SUCCESS;
2892 fail:
2893 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2894 if (dest_cs[i])
2895 queue->device->ws->cs_destroy(dest_cs[i]);
2896 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2897 queue->device->ws->buffer_destroy(descriptor_bo);
2898 if (scratch_bo && scratch_bo != queue->scratch_bo)
2899 queue->device->ws->buffer_destroy(scratch_bo);
2900 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2901 queue->device->ws->buffer_destroy(compute_scratch_bo);
2902 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2903 queue->device->ws->buffer_destroy(esgs_ring_bo);
2904 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2905 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2906 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2907 queue->device->ws->buffer_destroy(tess_rings_bo);
2908 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2909 }
2910
2911 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2912 struct radv_winsys_sem_counts *counts,
2913 int num_sems,
2914 const VkSemaphore *sems,
2915 VkFence _fence,
2916 bool reset_temp)
2917 {
2918 int syncobj_idx = 0, sem_idx = 0;
2919
2920 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2921 return VK_SUCCESS;
2922
2923 for (uint32_t i = 0; i < num_sems; i++) {
2924 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2925
2926 if (sem->temp_syncobj || sem->syncobj)
2927 counts->syncobj_count++;
2928 else
2929 counts->sem_count++;
2930 }
2931
2932 if (_fence != VK_NULL_HANDLE) {
2933 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2934 if (fence->temp_syncobj || fence->syncobj)
2935 counts->syncobj_count++;
2936 }
2937
2938 if (counts->syncobj_count) {
2939 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2940 if (!counts->syncobj)
2941 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2942 }
2943
2944 if (counts->sem_count) {
2945 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2946 if (!counts->sem) {
2947 free(counts->syncobj);
2948 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2949 }
2950 }
2951
2952 for (uint32_t i = 0; i < num_sems; i++) {
2953 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2954
2955 if (sem->temp_syncobj) {
2956 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2957 }
2958 else if (sem->syncobj)
2959 counts->syncobj[syncobj_idx++] = sem->syncobj;
2960 else {
2961 assert(sem->sem);
2962 counts->sem[sem_idx++] = sem->sem;
2963 }
2964 }
2965
2966 if (_fence != VK_NULL_HANDLE) {
2967 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2968 if (fence->temp_syncobj)
2969 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2970 else if (fence->syncobj)
2971 counts->syncobj[syncobj_idx++] = fence->syncobj;
2972 }
2973
2974 return VK_SUCCESS;
2975 }
2976
2977 static void
2978 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2979 {
2980 free(sem_info->wait.syncobj);
2981 free(sem_info->wait.sem);
2982 free(sem_info->signal.syncobj);
2983 free(sem_info->signal.sem);
2984 }
2985
2986
2987 static void radv_free_temp_syncobjs(struct radv_device *device,
2988 int num_sems,
2989 const VkSemaphore *sems)
2990 {
2991 for (uint32_t i = 0; i < num_sems; i++) {
2992 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2993
2994 if (sem->temp_syncobj) {
2995 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2996 sem->temp_syncobj = 0;
2997 }
2998 }
2999 }
3000
3001 static VkResult
3002 radv_alloc_sem_info(struct radv_instance *instance,
3003 struct radv_winsys_sem_info *sem_info,
3004 int num_wait_sems,
3005 const VkSemaphore *wait_sems,
3006 int num_signal_sems,
3007 const VkSemaphore *signal_sems,
3008 VkFence fence)
3009 {
3010 VkResult ret;
3011 memset(sem_info, 0, sizeof(*sem_info));
3012
3013 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
3014 if (ret)
3015 return ret;
3016 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
3017 if (ret)
3018 radv_free_sem_info(sem_info);
3019
3020 /* caller can override these */
3021 sem_info->cs_emit_wait = true;
3022 sem_info->cs_emit_signal = true;
3023 return ret;
3024 }
3025
3026 /* Signals fence as soon as all the work currently put on queue is done. */
3027 static VkResult radv_signal_fence(struct radv_queue *queue,
3028 struct radv_fence *fence