2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
32 #include <llvm/Config/llvm-config.h>
33 #include "radv_debug.h"
34 #include "radv_private.h"
35 #include "radv_shader.h"
37 #include "util/disk_cache.h"
38 #include "util/strtod.h"
42 #include <amdgpu_drm.h>
43 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
44 #include "ac_llvm_util.h"
45 #include "vk_format.h"
48 #include "util/build_id.h"
49 #include "util/debug.h"
50 #include "util/mesa-sha1.h"
51 #include "compiler/glsl_types.h"
52 #include "util/xmlpool.h"
55 radv_device_get_cache_uuid(enum radeon_family family
, void *uuid
)
58 unsigned char sha1
[20];
59 unsigned ptr_size
= sizeof(void*);
61 memset(uuid
, 0, VK_UUID_SIZE
);
62 _mesa_sha1_init(&ctx
);
64 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid
, &ctx
) ||
65 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo
, &ctx
))
68 _mesa_sha1_update(&ctx
, &family
, sizeof(family
));
69 _mesa_sha1_update(&ctx
, &ptr_size
, sizeof(ptr_size
));
70 _mesa_sha1_final(&ctx
, sha1
);
72 memcpy(uuid
, sha1
, VK_UUID_SIZE
);
77 radv_get_driver_uuid(void *uuid
)
79 ac_compute_driver_uuid(uuid
, VK_UUID_SIZE
);
83 radv_get_device_uuid(struct radeon_info
*info
, void *uuid
)
85 ac_compute_device_uuid(info
, uuid
, VK_UUID_SIZE
);
89 radv_get_device_name(enum radeon_family family
, char *name
, size_t name_len
)
91 const char *chip_string
;
94 case CHIP_TAHITI
: chip_string
= "AMD RADV TAHITI"; break;
95 case CHIP_PITCAIRN
: chip_string
= "AMD RADV PITCAIRN"; break;
96 case CHIP_VERDE
: chip_string
= "AMD RADV CAPE VERDE"; break;
97 case CHIP_OLAND
: chip_string
= "AMD RADV OLAND"; break;
98 case CHIP_HAINAN
: chip_string
= "AMD RADV HAINAN"; break;
99 case CHIP_BONAIRE
: chip_string
= "AMD RADV BONAIRE"; break;
100 case CHIP_KAVERI
: chip_string
= "AMD RADV KAVERI"; break;
101 case CHIP_KABINI
: chip_string
= "AMD RADV KABINI"; break;
102 case CHIP_HAWAII
: chip_string
= "AMD RADV HAWAII"; break;
103 case CHIP_TONGA
: chip_string
= "AMD RADV TONGA"; break;
104 case CHIP_ICELAND
: chip_string
= "AMD RADV ICELAND"; break;
105 case CHIP_CARRIZO
: chip_string
= "AMD RADV CARRIZO"; break;
106 case CHIP_FIJI
: chip_string
= "AMD RADV FIJI"; break;
107 case CHIP_POLARIS10
: chip_string
= "AMD RADV POLARIS10"; break;
108 case CHIP_POLARIS11
: chip_string
= "AMD RADV POLARIS11"; break;
109 case CHIP_POLARIS12
: chip_string
= "AMD RADV POLARIS12"; break;
110 case CHIP_STONEY
: chip_string
= "AMD RADV STONEY"; break;
111 case CHIP_VEGAM
: chip_string
= "AMD RADV VEGA M"; break;
112 case CHIP_VEGA10
: chip_string
= "AMD RADV VEGA10"; break;
113 case CHIP_VEGA12
: chip_string
= "AMD RADV VEGA12"; break;
114 case CHIP_VEGA20
: chip_string
= "AMD RADV VEGA20"; break;
115 case CHIP_RAVEN
: chip_string
= "AMD RADV RAVEN"; break;
116 case CHIP_RAVEN2
: chip_string
= "AMD RADV RAVEN2"; break;
117 case CHIP_NAVI10
: chip_string
= "AMD RADV NAVI10"; break;
118 case CHIP_NAVI12
: chip_string
= "AMD RADV NAVI12"; break;
119 case CHIP_NAVI14
: chip_string
= "AMD RADV NAVI14"; break;
120 default: chip_string
= "AMD RADV unknown"; break;
123 snprintf(name
, name_len
, "%s (LLVM " MESA_LLVM_VERSION_STRING
")", chip_string
);
127 radv_get_visible_vram_size(struct radv_physical_device
*device
)
129 return MIN2(device
->rad_info
.vram_size
, device
->rad_info
.vram_vis_size
);
133 radv_get_vram_size(struct radv_physical_device
*device
)
135 return device
->rad_info
.vram_size
- radv_get_visible_vram_size(device
);
139 radv_physical_device_init_mem_types(struct radv_physical_device
*device
)
141 STATIC_ASSERT(RADV_MEM_HEAP_COUNT
<= VK_MAX_MEMORY_HEAPS
);
142 uint64_t visible_vram_size
= radv_get_visible_vram_size(device
);
143 uint64_t vram_size
= radv_get_vram_size(device
);
144 int vram_index
= -1, visible_vram_index
= -1, gart_index
= -1;
145 device
->memory_properties
.memoryHeapCount
= 0;
147 vram_index
= device
->memory_properties
.memoryHeapCount
++;
148 device
->memory_properties
.memoryHeaps
[vram_index
] = (VkMemoryHeap
) {
150 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
153 if (visible_vram_size
) {
154 visible_vram_index
= device
->memory_properties
.memoryHeapCount
++;
155 device
->memory_properties
.memoryHeaps
[visible_vram_index
] = (VkMemoryHeap
) {
156 .size
= visible_vram_size
,
157 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
160 if (device
->rad_info
.gart_size
> 0) {
161 gart_index
= device
->memory_properties
.memoryHeapCount
++;
162 device
->memory_properties
.memoryHeaps
[gart_index
] = (VkMemoryHeap
) {
163 .size
= device
->rad_info
.gart_size
,
164 .flags
= device
->rad_info
.has_dedicated_vram
? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
168 STATIC_ASSERT(RADV_MEM_TYPE_COUNT
<= VK_MAX_MEMORY_TYPES
);
169 unsigned type_count
= 0;
170 if (vram_index
>= 0) {
171 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_VRAM
;
172 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
173 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
,
174 .heapIndex
= vram_index
,
177 if (gart_index
>= 0 && device
->rad_info
.has_dedicated_vram
) {
178 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_WRITE_COMBINE
;
179 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
180 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
181 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
182 .heapIndex
= gart_index
,
185 if (visible_vram_index
>= 0) {
186 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_VRAM_CPU_ACCESS
;
187 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
188 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
|
189 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
190 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
191 .heapIndex
= visible_vram_index
,
194 if (gart_index
>= 0 && !device
->rad_info
.has_dedicated_vram
) {
195 /* Put GTT after visible VRAM for GPUs without dedicated VRAM
196 * as they have identical property flags, and according to the
197 * spec, for types with identical flags, the one with greater
198 * performance must be given a lower index. */
199 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_WRITE_COMBINE
;
200 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
201 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
|
202 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
203 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
204 .heapIndex
= gart_index
,
207 if (gart_index
>= 0) {
208 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_CACHED
;
209 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
210 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
211 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
212 VK_MEMORY_PROPERTY_HOST_CACHED_BIT
|
213 (device
->rad_info
.has_dedicated_vram
? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
),
214 .heapIndex
= gart_index
,
217 device
->memory_properties
.memoryTypeCount
= type_count
;
221 radv_handle_env_var_force_family(struct radv_physical_device
*device
)
223 const char *family
= getenv("RADV_FORCE_FAMILY");
229 for (i
= CHIP_TAHITI
; i
< CHIP_LAST
; i
++) {
230 if (!strcmp(family
, ac_get_llvm_processor_name(i
))) {
231 /* Override family and chip_class. */
232 device
->rad_info
.family
= i
;
234 if (i
>= CHIP_NAVI10
)
235 device
->rad_info
.chip_class
= GFX10
;
236 else if (i
>= CHIP_VEGA10
)
237 device
->rad_info
.chip_class
= GFX9
;
238 else if (i
>= CHIP_TONGA
)
239 device
->rad_info
.chip_class
= GFX8
;
240 else if (i
>= CHIP_BONAIRE
)
241 device
->rad_info
.chip_class
= GFX7
;
243 device
->rad_info
.chip_class
= GFX6
;
249 fprintf(stderr
, "radv: Unknown family: %s\n", family
);
254 radv_physical_device_init(struct radv_physical_device
*device
,
255 struct radv_instance
*instance
,
256 drmDevicePtr drm_device
)
258 const char *path
= drm_device
->nodes
[DRM_NODE_RENDER
];
260 drmVersionPtr version
;
264 fd
= open(path
, O_RDWR
| O_CLOEXEC
);
266 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
267 radv_logi("Could not open device '%s'", path
);
269 return vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
272 version
= drmGetVersion(fd
);
276 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
277 radv_logi("Could not get the kernel driver version for device '%s'", path
);
279 return vk_errorf(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
,
280 "failed to get version %s: %m", path
);
283 if (strcmp(version
->name
, "amdgpu")) {
284 drmFreeVersion(version
);
287 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
288 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path
);
290 return VK_ERROR_INCOMPATIBLE_DRIVER
;
292 drmFreeVersion(version
);
294 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
295 radv_logi("Found compatible device '%s'.", path
);
297 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
298 device
->instance
= instance
;
300 device
->ws
= radv_amdgpu_winsys_create(fd
, instance
->debug_flags
,
301 instance
->perftest_flags
);
303 result
= vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
307 if (instance
->enabled_extensions
.KHR_display
) {
308 master_fd
= open(drm_device
->nodes
[DRM_NODE_PRIMARY
], O_RDWR
| O_CLOEXEC
);
309 if (master_fd
>= 0) {
310 uint32_t accel_working
= 0;
311 struct drm_amdgpu_info request
= {
312 .return_pointer
= (uintptr_t)&accel_working
,
313 .return_size
= sizeof(accel_working
),
314 .query
= AMDGPU_INFO_ACCEL_WORKING
317 if (drmCommandWrite(master_fd
, DRM_AMDGPU_INFO
, &request
, sizeof (struct drm_amdgpu_info
)) < 0 || !accel_working
) {
324 device
->master_fd
= master_fd
;
325 device
->local_fd
= fd
;
326 device
->ws
->query_info(device
->ws
, &device
->rad_info
);
328 radv_handle_env_var_force_family(device
);
330 radv_get_device_name(device
->rad_info
.family
, device
->name
, sizeof(device
->name
));
332 if (radv_device_get_cache_uuid(device
->rad_info
.family
, device
->cache_uuid
)) {
333 device
->ws
->destroy(device
->ws
);
334 result
= vk_errorf(instance
, VK_ERROR_INITIALIZATION_FAILED
,
335 "cannot generate UUID");
339 /* These flags affect shader compilation. */
340 uint64_t shader_env_flags
=
341 (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
? 0x1 : 0) |
342 (device
->instance
->debug_flags
& RADV_DEBUG_UNSAFE_MATH
? 0x2 : 0);
344 /* The gpu id is already embedded in the uuid so we just pass "radv"
345 * when creating the cache.
347 char buf
[VK_UUID_SIZE
* 2 + 1];
348 disk_cache_format_hex_id(buf
, device
->cache_uuid
, VK_UUID_SIZE
* 2);
349 device
->disk_cache
= disk_cache_create(device
->name
, buf
, shader_env_flags
);
351 if (device
->rad_info
.chip_class
< GFX8
||
352 device
->rad_info
.chip_class
> GFX9
)
353 fprintf(stderr
, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
355 radv_get_driver_uuid(&device
->driver_uuid
);
356 radv_get_device_uuid(&device
->rad_info
, &device
->device_uuid
);
358 device
->out_of_order_rast_allowed
= device
->rad_info
.has_out_of_order_rast
&&
359 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_OUT_OF_ORDER
);
361 device
->dcc_msaa_allowed
=
362 (device
->instance
->perftest_flags
& RADV_PERFTEST_DCC_MSAA
);
364 device
->use_shader_ballot
= device
->rad_info
.chip_class
>= GFX8
&&
365 device
->instance
->perftest_flags
& RADV_PERFTEST_SHADER_BALLOT
;
367 /* Determine the number of threads per wave for all stages. */
368 device
->cs_wave_size
= 64;
369 device
->ps_wave_size
= 64;
370 device
->ge_wave_size
= 64;
372 if (device
->rad_info
.chip_class
>= GFX10
) {
373 if (device
->instance
->perftest_flags
& RADV_PERFTEST_CS_WAVE_32
)
374 device
->cs_wave_size
= 32;
376 /* For pixel shaders, wave64 is recommanded. */
377 if (device
->instance
->perftest_flags
& RADV_PERFTEST_PS_WAVE_32
)
378 device
->ps_wave_size
= 32;
380 if (device
->instance
->perftest_flags
& RADV_PERFTEST_GE_WAVE_32
)
381 device
->ge_wave_size
= 32;
384 radv_physical_device_init_mem_types(device
);
385 radv_fill_device_extension_table(device
, &device
->supported_extensions
);
387 device
->bus_info
= *drm_device
->businfo
.pci
;
389 if ((device
->instance
->debug_flags
& RADV_DEBUG_INFO
))
390 ac_print_gpu_info(&device
->rad_info
);
392 /* The WSI is structured as a layer on top of the driver, so this has
393 * to be the last part of initialization (at least until we get other
396 result
= radv_init_wsi(device
);
397 if (result
!= VK_SUCCESS
) {
398 device
->ws
->destroy(device
->ws
);
399 vk_error(instance
, result
);
413 radv_physical_device_finish(struct radv_physical_device
*device
)
415 radv_finish_wsi(device
);
416 device
->ws
->destroy(device
->ws
);
417 disk_cache_destroy(device
->disk_cache
);
418 close(device
->local_fd
);
419 if (device
->master_fd
!= -1)
420 close(device
->master_fd
);
424 default_alloc_func(void *pUserData
, size_t size
, size_t align
,
425 VkSystemAllocationScope allocationScope
)
431 default_realloc_func(void *pUserData
, void *pOriginal
, size_t size
,
432 size_t align
, VkSystemAllocationScope allocationScope
)
434 return realloc(pOriginal
, size
);
438 default_free_func(void *pUserData
, void *pMemory
)
443 static const VkAllocationCallbacks default_alloc
= {
445 .pfnAllocation
= default_alloc_func
,
446 .pfnReallocation
= default_realloc_func
,
447 .pfnFree
= default_free_func
,
450 static const struct debug_control radv_debug_options
[] = {
451 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS
},
452 {"nodcc", RADV_DEBUG_NO_DCC
},
453 {"shaders", RADV_DEBUG_DUMP_SHADERS
},
454 {"nocache", RADV_DEBUG_NO_CACHE
},
455 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS
},
456 {"nohiz", RADV_DEBUG_NO_HIZ
},
457 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE
},
458 {"unsafemath", RADV_DEBUG_UNSAFE_MATH
},
459 {"allbos", RADV_DEBUG_ALL_BOS
},
460 {"noibs", RADV_DEBUG_NO_IBS
},
461 {"spirv", RADV_DEBUG_DUMP_SPIRV
},
462 {"vmfaults", RADV_DEBUG_VM_FAULTS
},
463 {"zerovram", RADV_DEBUG_ZERO_VRAM
},
464 {"syncshaders", RADV_DEBUG_SYNC_SHADERS
},
465 {"nosisched", RADV_DEBUG_NO_SISCHED
},
466 {"preoptir", RADV_DEBUG_PREOPTIR
},
467 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS
},
468 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER
},
469 {"info", RADV_DEBUG_INFO
},
470 {"errors", RADV_DEBUG_ERRORS
},
471 {"startup", RADV_DEBUG_STARTUP
},
472 {"checkir", RADV_DEBUG_CHECKIR
},
473 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM
},
474 {"nobinning", RADV_DEBUG_NOBINNING
},
475 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT
},
476 {"nongg", RADV_DEBUG_NO_NGG
},
477 {"noshaderballot", RADV_DEBUG_NO_SHADER_BALLOT
},
478 {"allentrypoints", RADV_DEBUG_ALL_ENTRYPOINTS
},
483 radv_get_debug_option_name(int id
)
485 assert(id
< ARRAY_SIZE(radv_debug_options
) - 1);
486 return radv_debug_options
[id
].string
;
489 static const struct debug_control radv_perftest_options
[] = {
490 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN
},
491 {"sisched", RADV_PERFTEST_SISCHED
},
492 {"localbos", RADV_PERFTEST_LOCAL_BOS
},
493 {"dccmsaa", RADV_PERFTEST_DCC_MSAA
},
494 {"bolist", RADV_PERFTEST_BO_LIST
},
495 {"shader_ballot", RADV_PERFTEST_SHADER_BALLOT
},
496 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK
},
497 {"cswave32", RADV_PERFTEST_CS_WAVE_32
},
498 {"pswave32", RADV_PERFTEST_PS_WAVE_32
},
499 {"gewave32", RADV_PERFTEST_GE_WAVE_32
},
504 radv_get_perftest_option_name(int id
)
506 assert(id
< ARRAY_SIZE(radv_perftest_options
) - 1);
507 return radv_perftest_options
[id
].string
;
511 radv_handle_per_app_options(struct radv_instance
*instance
,
512 const VkApplicationInfo
*info
)
514 const char *name
= info
? info
->pApplicationName
: NULL
;
519 if (!strcmp(name
, "Talos - Linux - 32bit") ||
520 !strcmp(name
, "Talos - Linux - 64bit")) {
521 if (!(instance
->debug_flags
& RADV_DEBUG_NO_SISCHED
)) {
522 /* Force enable LLVM sisched for Talos because it looks
523 * safe and it gives few more FPS.
525 instance
->perftest_flags
|= RADV_PERFTEST_SISCHED
;
527 } else if (!strcmp(name
, "DOOM_VFR")) {
528 /* Work around a Doom VFR game bug */
529 instance
->debug_flags
|= RADV_DEBUG_NO_DYNAMIC_BOUNDS
;
530 } else if (!strcmp(name
, "MonsterHunterWorld.exe")) {
531 /* Workaround for a WaW hazard when LLVM moves/merges
532 * load/store memory operations.
533 * See https://reviews.llvm.org/D61313
535 if (LLVM_VERSION_MAJOR
< 9)
536 instance
->debug_flags
|= RADV_DEBUG_NO_LOAD_STORE_OPT
;
537 } else if (!strcmp(name
, "Wolfenstein: Youngblood")) {
538 if (!(instance
->debug_flags
& RADV_DEBUG_NO_SHADER_BALLOT
)) {
539 /* Force enable VK_AMD_shader_ballot because it looks
540 * safe and it gives a nice boost (+20% on Vega 56 at
543 instance
->perftest_flags
|= RADV_PERFTEST_SHADER_BALLOT
;
548 static int radv_get_instance_extension_index(const char *name
)
550 for (unsigned i
= 0; i
< RADV_INSTANCE_EXTENSION_COUNT
; ++i
) {
551 if (strcmp(name
, radv_instance_extensions
[i
].extensionName
) == 0)
557 static const char radv_dri_options_xml
[] =
559 DRI_CONF_SECTION_PERFORMANCE
560 DRI_CONF_ADAPTIVE_SYNC("true")
561 DRI_CONF_VK_X11_OVERRIDE_MIN_IMAGE_COUNT(0)
565 static void radv_init_dri_options(struct radv_instance
*instance
)
567 driParseOptionInfo(&instance
->available_dri_options
, radv_dri_options_xml
);
568 driParseConfigFiles(&instance
->dri_options
,
569 &instance
->available_dri_options
,
571 instance
->engineName
,
572 instance
->engineVersion
);
575 VkResult
radv_CreateInstance(
576 const VkInstanceCreateInfo
* pCreateInfo
,
577 const VkAllocationCallbacks
* pAllocator
,
578 VkInstance
* pInstance
)
580 struct radv_instance
*instance
;
583 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO
);
585 uint32_t client_version
;
586 if (pCreateInfo
->pApplicationInfo
&&
587 pCreateInfo
->pApplicationInfo
->apiVersion
!= 0) {
588 client_version
= pCreateInfo
->pApplicationInfo
->apiVersion
;
590 client_version
= VK_API_VERSION_1_0
;
593 const char *engine_name
= NULL
;
594 uint32_t engine_version
= 0;
595 if (pCreateInfo
->pApplicationInfo
) {
596 engine_name
= pCreateInfo
->pApplicationInfo
->pEngineName
;
597 engine_version
= pCreateInfo
->pApplicationInfo
->engineVersion
;
600 instance
= vk_zalloc2(&default_alloc
, pAllocator
, sizeof(*instance
), 8,
601 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
603 return vk_error(NULL
, VK_ERROR_OUT_OF_HOST_MEMORY
);
605 instance
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
608 instance
->alloc
= *pAllocator
;
610 instance
->alloc
= default_alloc
;
612 instance
->apiVersion
= client_version
;
613 instance
->physicalDeviceCount
= -1;
615 instance
->debug_flags
= parse_debug_string(getenv("RADV_DEBUG"),
618 instance
->perftest_flags
= parse_debug_string(getenv("RADV_PERFTEST"),
619 radv_perftest_options
);
622 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
623 radv_logi("Created an instance");
625 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
626 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
627 int index
= radv_get_instance_extension_index(ext_name
);
629 if (index
< 0 || !radv_supported_instance_extensions
.extensions
[index
]) {
630 vk_free2(&default_alloc
, pAllocator
, instance
);
631 return vk_error(instance
, VK_ERROR_EXTENSION_NOT_PRESENT
);
634 instance
->enabled_extensions
.extensions
[index
] = true;
637 result
= vk_debug_report_instance_init(&instance
->debug_report_callbacks
);
638 if (result
!= VK_SUCCESS
) {
639 vk_free2(&default_alloc
, pAllocator
, instance
);
640 return vk_error(instance
, result
);
643 instance
->engineName
= vk_strdup(&instance
->alloc
, engine_name
,
644 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
645 instance
->engineVersion
= engine_version
;
648 glsl_type_singleton_init_or_ref();
650 VG(VALGRIND_CREATE_MEMPOOL(instance
, 0, false));
652 radv_init_dri_options(instance
);
653 radv_handle_per_app_options(instance
, pCreateInfo
->pApplicationInfo
);
655 *pInstance
= radv_instance_to_handle(instance
);
660 void radv_DestroyInstance(
661 VkInstance _instance
,
662 const VkAllocationCallbacks
* pAllocator
)
664 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
669 for (int i
= 0; i
< instance
->physicalDeviceCount
; ++i
) {
670 radv_physical_device_finish(instance
->physicalDevices
+ i
);
673 vk_free(&instance
->alloc
, instance
->engineName
);
675 VG(VALGRIND_DESTROY_MEMPOOL(instance
));
677 glsl_type_singleton_decref();
680 driDestroyOptionCache(&instance
->dri_options
);
681 driDestroyOptionInfo(&instance
->available_dri_options
);
683 vk_debug_report_instance_destroy(&instance
->debug_report_callbacks
);
685 vk_free(&instance
->alloc
, instance
);
689 radv_enumerate_devices(struct radv_instance
*instance
)
691 /* TODO: Check for more devices ? */
692 drmDevicePtr devices
[8];
693 VkResult result
= VK_ERROR_INCOMPATIBLE_DRIVER
;
696 instance
->physicalDeviceCount
= 0;
698 max_devices
= drmGetDevices2(0, devices
, ARRAY_SIZE(devices
));
700 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
701 radv_logi("Found %d drm nodes", max_devices
);
704 return vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
706 for (unsigned i
= 0; i
< (unsigned)max_devices
; i
++) {
707 if (devices
[i
]->available_nodes
& 1 << DRM_NODE_RENDER
&&
708 devices
[i
]->bustype
== DRM_BUS_PCI
&&
709 devices
[i
]->deviceinfo
.pci
->vendor_id
== ATI_VENDOR_ID
) {
711 result
= radv_physical_device_init(instance
->physicalDevices
+
712 instance
->physicalDeviceCount
,
715 if (result
== VK_SUCCESS
)
716 ++instance
->physicalDeviceCount
;
717 else if (result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
721 drmFreeDevices(devices
, max_devices
);
726 VkResult
radv_EnumeratePhysicalDevices(
727 VkInstance _instance
,
728 uint32_t* pPhysicalDeviceCount
,
729 VkPhysicalDevice
* pPhysicalDevices
)
731 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
734 if (instance
->physicalDeviceCount
< 0) {
735 result
= radv_enumerate_devices(instance
);
736 if (result
!= VK_SUCCESS
&&
737 result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
741 if (!pPhysicalDevices
) {
742 *pPhysicalDeviceCount
= instance
->physicalDeviceCount
;
744 *pPhysicalDeviceCount
= MIN2(*pPhysicalDeviceCount
, instance
->physicalDeviceCount
);
745 for (unsigned i
= 0; i
< *pPhysicalDeviceCount
; ++i
)
746 pPhysicalDevices
[i
] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
749 return *pPhysicalDeviceCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
753 VkResult
radv_EnumeratePhysicalDeviceGroups(
754 VkInstance _instance
,
755 uint32_t* pPhysicalDeviceGroupCount
,
756 VkPhysicalDeviceGroupProperties
* pPhysicalDeviceGroupProperties
)
758 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
761 if (instance
->physicalDeviceCount
< 0) {
762 result
= radv_enumerate_devices(instance
);
763 if (result
!= VK_SUCCESS
&&
764 result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
768 if (!pPhysicalDeviceGroupProperties
) {
769 *pPhysicalDeviceGroupCount
= instance
->physicalDeviceCount
;
771 *pPhysicalDeviceGroupCount
= MIN2(*pPhysicalDeviceGroupCount
, instance
->physicalDeviceCount
);
772 for (unsigned i
= 0; i
< *pPhysicalDeviceGroupCount
; ++i
) {
773 pPhysicalDeviceGroupProperties
[i
].physicalDeviceCount
= 1;
774 pPhysicalDeviceGroupProperties
[i
].physicalDevices
[0] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
775 pPhysicalDeviceGroupProperties
[i
].subsetAllocation
= false;
778 return *pPhysicalDeviceGroupCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
782 void radv_GetPhysicalDeviceFeatures(
783 VkPhysicalDevice physicalDevice
,
784 VkPhysicalDeviceFeatures
* pFeatures
)
786 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
787 memset(pFeatures
, 0, sizeof(*pFeatures
));
789 *pFeatures
= (VkPhysicalDeviceFeatures
) {
790 .robustBufferAccess
= true,
791 .fullDrawIndexUint32
= true,
792 .imageCubeArray
= true,
793 .independentBlend
= true,
794 .geometryShader
= true,
795 .tessellationShader
= true,
796 .sampleRateShading
= true,
797 .dualSrcBlend
= true,
799 .multiDrawIndirect
= true,
800 .drawIndirectFirstInstance
= true,
802 .depthBiasClamp
= true,
803 .fillModeNonSolid
= true,
808 .multiViewport
= true,
809 .samplerAnisotropy
= true,
810 .textureCompressionETC2
= radv_device_supports_etc(pdevice
),
811 .textureCompressionASTC_LDR
= false,
812 .textureCompressionBC
= true,
813 .occlusionQueryPrecise
= true,
814 .pipelineStatisticsQuery
= true,
815 .vertexPipelineStoresAndAtomics
= true,
816 .fragmentStoresAndAtomics
= true,
817 .shaderTessellationAndGeometryPointSize
= true,
818 .shaderImageGatherExtended
= true,
819 .shaderStorageImageExtendedFormats
= true,
820 .shaderStorageImageMultisample
= pdevice
->rad_info
.chip_class
>= GFX8
,
821 .shaderUniformBufferArrayDynamicIndexing
= true,
822 .shaderSampledImageArrayDynamicIndexing
= true,
823 .shaderStorageBufferArrayDynamicIndexing
= true,
824 .shaderStorageImageArrayDynamicIndexing
= true,
825 .shaderStorageImageReadWithoutFormat
= true,
826 .shaderStorageImageWriteWithoutFormat
= true,
827 .shaderClipDistance
= true,
828 .shaderCullDistance
= true,
829 .shaderFloat64
= true,
831 .shaderInt16
= pdevice
->rad_info
.chip_class
>= GFX9
,
832 .sparseBinding
= true,
833 .variableMultisampleRate
= true,
834 .inheritedQueries
= true,
838 void radv_GetPhysicalDeviceFeatures2(
839 VkPhysicalDevice physicalDevice
,
840 VkPhysicalDeviceFeatures2
*pFeatures
)
842 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
843 vk_foreach_struct(ext
, pFeatures
->pNext
) {
844 switch (ext
->sType
) {
845 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES
: {
846 VkPhysicalDeviceVariablePointersFeatures
*features
= (void *)ext
;
847 features
->variablePointersStorageBuffer
= true;
848 features
->variablePointers
= true;
851 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES
: {
852 VkPhysicalDeviceMultiviewFeatures
*features
= (VkPhysicalDeviceMultiviewFeatures
*)ext
;
853 features
->multiview
= true;
854 features
->multiviewGeometryShader
= true;
855 features
->multiviewTessellationShader
= true;
858 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES
: {
859 VkPhysicalDeviceShaderDrawParametersFeatures
*features
=
860 (VkPhysicalDeviceShaderDrawParametersFeatures
*)ext
;
861 features
->shaderDrawParameters
= true;
864 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES
: {
865 VkPhysicalDeviceProtectedMemoryFeatures
*features
=
866 (VkPhysicalDeviceProtectedMemoryFeatures
*)ext
;
867 features
->protectedMemory
= false;
870 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES
: {
871 VkPhysicalDevice16BitStorageFeatures
*features
=
872 (VkPhysicalDevice16BitStorageFeatures
*)ext
;
873 bool enabled
= pdevice
->rad_info
.chip_class
>= GFX8
;
874 features
->storageBuffer16BitAccess
= enabled
;
875 features
->uniformAndStorageBuffer16BitAccess
= enabled
;
876 features
->storagePushConstant16
= enabled
;
877 features
->storageInputOutput16
= enabled
&& LLVM_VERSION_MAJOR
>= 9;
880 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES
: {
881 VkPhysicalDeviceSamplerYcbcrConversionFeatures
*features
=
882 (VkPhysicalDeviceSamplerYcbcrConversionFeatures
*)ext
;
883 features
->samplerYcbcrConversion
= true;
886 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT
: {
887 VkPhysicalDeviceDescriptorIndexingFeaturesEXT
*features
=
888 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT
*)ext
;
889 features
->shaderInputAttachmentArrayDynamicIndexing
= true;
890 features
->shaderUniformTexelBufferArrayDynamicIndexing
= true;
891 features
->shaderStorageTexelBufferArrayDynamicIndexing
= true;
892 features
->shaderUniformBufferArrayNonUniformIndexing
= true;
893 features
->shaderSampledImageArrayNonUniformIndexing
= true;
894 features
->shaderStorageBufferArrayNonUniformIndexing
= true;
895 features
->shaderStorageImageArrayNonUniformIndexing
= true;
896 features
->shaderInputAttachmentArrayNonUniformIndexing
= true;
897 features
->shaderUniformTexelBufferArrayNonUniformIndexing
= true;
898 features
->shaderStorageTexelBufferArrayNonUniformIndexing
= true;
899 features
->descriptorBindingUniformBufferUpdateAfterBind
= true;
900 features
->descriptorBindingSampledImageUpdateAfterBind
= true;
901 features
->descriptorBindingStorageImageUpdateAfterBind
= true;
902 features
->descriptorBindingStorageBufferUpdateAfterBind
= true;
903 features
->descriptorBindingUniformTexelBufferUpdateAfterBind
= true;
904 features
->descriptorBindingStorageTexelBufferUpdateAfterBind
= true;
905 features
->descriptorBindingUpdateUnusedWhilePending
= true;
906 features
->descriptorBindingPartiallyBound
= true;
907 features
->descriptorBindingVariableDescriptorCount
= true;
908 features
->runtimeDescriptorArray
= true;
911 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT
: {
912 VkPhysicalDeviceConditionalRenderingFeaturesEXT
*features
=
913 (VkPhysicalDeviceConditionalRenderingFeaturesEXT
*)ext
;
914 features
->conditionalRendering
= true;
915 features
->inheritedConditionalRendering
= false;
918 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT
: {
919 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT
*features
=
920 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT
*)ext
;
921 features
->vertexAttributeInstanceRateDivisor
= VK_TRUE
;
922 features
->vertexAttributeInstanceRateZeroDivisor
= VK_TRUE
;
925 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT
: {
926 VkPhysicalDeviceTransformFeedbackFeaturesEXT
*features
=
927 (VkPhysicalDeviceTransformFeedbackFeaturesEXT
*)ext
;
928 features
->transformFeedback
= true;
929 features
->geometryStreams
= true;
932 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT
: {
933 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT
*features
=
934 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT
*)ext
;
935 features
->scalarBlockLayout
= pdevice
->rad_info
.chip_class
>= GFX7
;
938 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT
: {
939 VkPhysicalDeviceMemoryPriorityFeaturesEXT
*features
=
940 (VkPhysicalDeviceMemoryPriorityFeaturesEXT
*)ext
;
941 features
->memoryPriority
= VK_TRUE
;
944 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT
: {
945 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT
*features
=
946 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT
*)ext
;
947 features
->bufferDeviceAddress
= true;
948 features
->bufferDeviceAddressCaptureReplay
= false;
949 features
->bufferDeviceAddressMultiDevice
= false;
952 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT
: {
953 VkPhysicalDeviceDepthClipEnableFeaturesEXT
*features
=
954 (VkPhysicalDeviceDepthClipEnableFeaturesEXT
*)ext
;
955 features
->depthClipEnable
= true;
958 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT
: {
959 VkPhysicalDeviceHostQueryResetFeaturesEXT
*features
=
960 (VkPhysicalDeviceHostQueryResetFeaturesEXT
*)ext
;
961 features
->hostQueryReset
= true;
964 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR
: {
965 VkPhysicalDevice8BitStorageFeaturesKHR
*features
=
966 (VkPhysicalDevice8BitStorageFeaturesKHR
*)ext
;
967 bool enabled
= pdevice
->rad_info
.chip_class
>= GFX8
;
968 features
->storageBuffer8BitAccess
= enabled
;
969 features
->uniformAndStorageBuffer8BitAccess
= enabled
;
970 features
->storagePushConstant8
= enabled
;
973 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT16_INT8_FEATURES_KHR
: {
974 VkPhysicalDeviceFloat16Int8FeaturesKHR
*features
=
975 (VkPhysicalDeviceFloat16Int8FeaturesKHR
*)ext
;
976 features
->shaderFloat16
= pdevice
->rad_info
.chip_class
>= GFX8
;
977 features
->shaderInt8
= true;
980 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR
: {
981 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR
*features
=
982 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR
*)ext
;
983 features
->shaderBufferInt64Atomics
= LLVM_VERSION_MAJOR
>= 9;
984 features
->shaderSharedInt64Atomics
= LLVM_VERSION_MAJOR
>= 9;
987 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT
: {
988 VkPhysicalDeviceInlineUniformBlockFeaturesEXT
*features
=
989 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT
*)ext
;
991 features
->inlineUniformBlock
= true;
992 features
->descriptorBindingInlineUniformBlockUpdateAfterBind
= true;
995 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV
: {
996 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV
*features
=
997 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV
*)ext
;
998 features
->computeDerivativeGroupQuads
= false;
999 features
->computeDerivativeGroupLinear
= true;
1002 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT
: {
1003 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT
*features
=
1004 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT
*)ext
;
1005 features
->ycbcrImageArrays
= true;
1008 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES_KHR
: {
1009 VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR
*features
=
1010 (VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR
*)ext
;
1011 features
->uniformBufferStandardLayout
= true;
1014 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT
: {
1015 VkPhysicalDeviceIndexTypeUint8FeaturesEXT
*features
=
1016 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT
*)ext
;
1017 features
->indexTypeUint8
= pdevice
->rad_info
.chip_class
>= GFX8
;
1020 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGELESS_FRAMEBUFFER_FEATURES_KHR
: {
1021 VkPhysicalDeviceImagelessFramebufferFeaturesKHR
*features
=
1022 (VkPhysicalDeviceImagelessFramebufferFeaturesKHR
*)ext
;
1023 features
->imagelessFramebuffer
= true;
1026 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR
: {
1027 VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR
*features
=
1028 (VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR
*)ext
;
1029 features
->pipelineExecutableInfo
= true;
1036 return radv_GetPhysicalDeviceFeatures(physicalDevice
, &pFeatures
->features
);
1039 void radv_GetPhysicalDeviceProperties(
1040 VkPhysicalDevice physicalDevice
,
1041 VkPhysicalDeviceProperties
* pProperties
)
1043 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1044 VkSampleCountFlags sample_counts
= 0xf;
1046 /* make sure that the entire descriptor set is addressable with a signed
1047 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1048 * be at most 2 GiB. the combined image & samples object count as one of
1049 * both. This limit is for the pipeline layout, not for the set layout, but
1050 * there is no set limit, so we just set a pipeline limit. I don't think
1051 * any app is going to hit this soon. */
1052 size_t max_descriptor_set_size
= ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
) /
1053 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1054 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1055 32 /* sampler, largest when combined with image */ +
1056 64 /* sampled image */ +
1057 64 /* storage image */);
1059 VkPhysicalDeviceLimits limits
= {
1060 .maxImageDimension1D
= (1 << 14),
1061 .maxImageDimension2D
= (1 << 14),
1062 .maxImageDimension3D
= (1 << 11),
1063 .maxImageDimensionCube
= (1 << 14),
1064 .maxImageArrayLayers
= (1 << 11),
1065 .maxTexelBufferElements
= 128 * 1024 * 1024,
1066 .maxUniformBufferRange
= UINT32_MAX
,
1067 .maxStorageBufferRange
= UINT32_MAX
,
1068 .maxPushConstantsSize
= MAX_PUSH_CONSTANTS_SIZE
,
1069 .maxMemoryAllocationCount
= UINT32_MAX
,
1070 .maxSamplerAllocationCount
= 64 * 1024,
1071 .bufferImageGranularity
= 64, /* A cache line */
1072 .sparseAddressSpaceSize
= 0xffffffffu
, /* buffer max size */
1073 .maxBoundDescriptorSets
= MAX_SETS
,
1074 .maxPerStageDescriptorSamplers
= max_descriptor_set_size
,
1075 .maxPerStageDescriptorUniformBuffers
= max_descriptor_set_size
,
1076 .maxPerStageDescriptorStorageBuffers
= max_descriptor_set_size
,
1077 .maxPerStageDescriptorSampledImages
= max_descriptor_set_size
,
1078 .maxPerStageDescriptorStorageImages
= max_descriptor_set_size
,
1079 .maxPerStageDescriptorInputAttachments
= max_descriptor_set_size
,
1080 .maxPerStageResources
= max_descriptor_set_size
,
1081 .maxDescriptorSetSamplers
= max_descriptor_set_size
,
1082 .maxDescriptorSetUniformBuffers
= max_descriptor_set_size
,
1083 .maxDescriptorSetUniformBuffersDynamic
= MAX_DYNAMIC_UNIFORM_BUFFERS
,
1084 .maxDescriptorSetStorageBuffers
= max_descriptor_set_size
,
1085 .maxDescriptorSetStorageBuffersDynamic
= MAX_DYNAMIC_STORAGE_BUFFERS
,
1086 .maxDescriptorSetSampledImages
= max_descriptor_set_size
,
1087 .maxDescriptorSetStorageImages
= max_descriptor_set_size
,
1088 .maxDescriptorSetInputAttachments
= max_descriptor_set_size
,
1089 .maxVertexInputAttributes
= MAX_VERTEX_ATTRIBS
,
1090 .maxVertexInputBindings
= MAX_VBS
,
1091 .maxVertexInputAttributeOffset
= 2047,
1092 .maxVertexInputBindingStride
= 2048,
1093 .maxVertexOutputComponents
= 128,
1094 .maxTessellationGenerationLevel
= 64,
1095 .maxTessellationPatchSize
= 32,
1096 .maxTessellationControlPerVertexInputComponents
= 128,
1097 .maxTessellationControlPerVertexOutputComponents
= 128,
1098 .maxTessellationControlPerPatchOutputComponents
= 120,
1099 .maxTessellationControlTotalOutputComponents
= 4096,
1100 .maxTessellationEvaluationInputComponents
= 128,
1101 .maxTessellationEvaluationOutputComponents
= 128,
1102 .maxGeometryShaderInvocations
= 127,
1103 .maxGeometryInputComponents
= 64,
1104 .maxGeometryOutputComponents
= 128,
1105 .maxGeometryOutputVertices
= 256,
1106 .maxGeometryTotalOutputComponents
= 1024,
1107 .maxFragmentInputComponents
= 128,
1108 .maxFragmentOutputAttachments
= 8,
1109 .maxFragmentDualSrcAttachments
= 1,
1110 .maxFragmentCombinedOutputResources
= 8,
1111 .maxComputeSharedMemorySize
= 32768,
1112 .maxComputeWorkGroupCount
= { 65535, 65535, 65535 },
1113 .maxComputeWorkGroupInvocations
= 2048,
1114 .maxComputeWorkGroupSize
= {
1119 .subPixelPrecisionBits
= 8,
1120 .subTexelPrecisionBits
= 8,
1121 .mipmapPrecisionBits
= 8,
1122 .maxDrawIndexedIndexValue
= UINT32_MAX
,
1123 .maxDrawIndirectCount
= UINT32_MAX
,
1124 .maxSamplerLodBias
= 16,
1125 .maxSamplerAnisotropy
= 16,
1126 .maxViewports
= MAX_VIEWPORTS
,
1127 .maxViewportDimensions
= { (1 << 14), (1 << 14) },
1128 .viewportBoundsRange
= { INT16_MIN
, INT16_MAX
},
1129 .viewportSubPixelBits
= 8,
1130 .minMemoryMapAlignment
= 4096, /* A page */
1131 .minTexelBufferOffsetAlignment
= 1,
1132 .minUniformBufferOffsetAlignment
= 4,
1133 .minStorageBufferOffsetAlignment
= 4,
1134 .minTexelOffset
= -32,
1135 .maxTexelOffset
= 31,
1136 .minTexelGatherOffset
= -32,
1137 .maxTexelGatherOffset
= 31,
1138 .minInterpolationOffset
= -2,
1139 .maxInterpolationOffset
= 2,
1140 .subPixelInterpolationOffsetBits
= 8,
1141 .maxFramebufferWidth
= (1 << 14),
1142 .maxFramebufferHeight
= (1 << 14),
1143 .maxFramebufferLayers
= (1 << 10),
1144 .framebufferColorSampleCounts
= sample_counts
,
1145 .framebufferDepthSampleCounts
= sample_counts
,
1146 .framebufferStencilSampleCounts
= sample_counts
,
1147 .framebufferNoAttachmentsSampleCounts
= sample_counts
,
1148 .maxColorAttachments
= MAX_RTS
,
1149 .sampledImageColorSampleCounts
= sample_counts
,
1150 .sampledImageIntegerSampleCounts
= VK_SAMPLE_COUNT_1_BIT
,
1151 .sampledImageDepthSampleCounts
= sample_counts
,
1152 .sampledImageStencilSampleCounts
= sample_counts
,
1153 .storageImageSampleCounts
= pdevice
->rad_info
.chip_class
>= GFX8
? sample_counts
: VK_SAMPLE_COUNT_1_BIT
,
1154 .maxSampleMaskWords
= 1,
1155 .timestampComputeAndGraphics
= true,
1156 .timestampPeriod
= 1000000.0 / pdevice
->rad_info
.clock_crystal_freq
,
1157 .maxClipDistances
= 8,
1158 .maxCullDistances
= 8,
1159 .maxCombinedClipAndCullDistances
= 8,
1160 .discreteQueuePriorities
= 2,
1161 .pointSizeRange
= { 0.0, 8192.0 },
1162 .lineWidthRange
= { 0.0, 7.9921875 },
1163 .pointSizeGranularity
= (1.0 / 8.0),
1164 .lineWidthGranularity
= (1.0 / 128.0),
1165 .strictLines
= false, /* FINISHME */
1166 .standardSampleLocations
= true,
1167 .optimalBufferCopyOffsetAlignment
= 128,
1168 .optimalBufferCopyRowPitchAlignment
= 128,
1169 .nonCoherentAtomSize
= 64,
1172 *pProperties
= (VkPhysicalDeviceProperties
) {
1173 .apiVersion
= radv_physical_device_api_version(pdevice
),
1174 .driverVersion
= vk_get_driver_version(),
1175 .vendorID
= ATI_VENDOR_ID
,
1176 .deviceID
= pdevice
->rad_info
.pci_id
,
1177 .deviceType
= pdevice
->rad_info
.has_dedicated_vram
? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU
: VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU
,
1179 .sparseProperties
= {0},
1182 strcpy(pProperties
->deviceName
, pdevice
->name
);
1183 memcpy(pProperties
->pipelineCacheUUID
, pdevice
->cache_uuid
, VK_UUID_SIZE
);
1186 void radv_GetPhysicalDeviceProperties2(
1187 VkPhysicalDevice physicalDevice
,
1188 VkPhysicalDeviceProperties2
*pProperties
)
1190 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1191 radv_GetPhysicalDeviceProperties(physicalDevice
, &pProperties
->properties
);
1193 vk_foreach_struct(ext
, pProperties
->pNext
) {
1194 switch (ext
->sType
) {
1195 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR
: {
1196 VkPhysicalDevicePushDescriptorPropertiesKHR
*properties
=
1197 (VkPhysicalDevicePushDescriptorPropertiesKHR
*) ext
;
1198 properties
->maxPushDescriptors
= MAX_PUSH_DESCRIPTORS
;
1201 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES
: {
1202 VkPhysicalDeviceIDProperties
*properties
= (VkPhysicalDeviceIDProperties
*)ext
;
1203 memcpy(properties
->driverUUID
, pdevice
->driver_uuid
, VK_UUID_SIZE
);
1204 memcpy(properties
->deviceUUID
, pdevice
->device_uuid
, VK_UUID_SIZE
);
1205 properties
->deviceLUIDValid
= false;
1208 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES
: {
1209 VkPhysicalDeviceMultiviewProperties
*properties
= (VkPhysicalDeviceMultiviewProperties
*)ext
;
1210 properties
->maxMultiviewViewCount
= MAX_VIEWS
;
1211 properties
->maxMultiviewInstanceIndex
= INT_MAX
;
1214 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES
: {
1215 VkPhysicalDevicePointClippingProperties
*properties
=
1216 (VkPhysicalDevicePointClippingProperties
*)ext
;
1217 properties
->pointClippingBehavior
= VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES
;
1220 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT
: {
1221 VkPhysicalDeviceDiscardRectanglePropertiesEXT
*properties
=
1222 (VkPhysicalDeviceDiscardRectanglePropertiesEXT
*)ext
;
1223 properties
->maxDiscardRectangles
= MAX_DISCARD_RECTANGLES
;
1226 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT
: {
1227 VkPhysicalDeviceExternalMemoryHostPropertiesEXT
*properties
=
1228 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT
*) ext
;
1229 properties
->minImportedHostPointerAlignment
= 4096;
1232 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES
: {
1233 VkPhysicalDeviceSubgroupProperties
*properties
=
1234 (VkPhysicalDeviceSubgroupProperties
*)ext
;
1235 properties
->subgroupSize
= 64;
1236 properties
->supportedStages
= VK_SHADER_STAGE_ALL
;
1237 properties
->supportedOperations
=
1238 VK_SUBGROUP_FEATURE_BASIC_BIT
|
1239 VK_SUBGROUP_FEATURE_BALLOT_BIT
|
1240 VK_SUBGROUP_FEATURE_QUAD_BIT
|
1241 VK_SUBGROUP_FEATURE_VOTE_BIT
;
1242 if (pdevice
->rad_info
.chip_class
>= GFX8
) {
1243 properties
->supportedOperations
|=
1244 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT
|
1245 VK_SUBGROUP_FEATURE_SHUFFLE_BIT
|
1246 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT
;
1248 properties
->quadOperationsInAllStages
= true;
1251 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES
: {
1252 VkPhysicalDeviceMaintenance3Properties
*properties
=
1253 (VkPhysicalDeviceMaintenance3Properties
*)ext
;
1254 /* Make sure everything is addressable by a signed 32-bit int, and
1255 * our largest descriptors are 96 bytes. */
1256 properties
->maxPerSetDescriptors
= (1ull << 31) / 96;
1257 /* Our buffer size fields allow only this much */
1258 properties
->maxMemoryAllocationSize
= 0xFFFFFFFFull
;
1261 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT
: {
1262 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT
*properties
=
1263 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT
*)ext
;
1264 /* GFX6-8 only support single channel min/max filter. */
1265 properties
->filterMinmaxImageComponentMapping
= pdevice
->rad_info
.chip_class
>= GFX9
;
1266 properties
->filterMinmaxSingleComponentFormats
= true;
1269 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD
: {
1270 VkPhysicalDeviceShaderCorePropertiesAMD
*properties
=
1271 (VkPhysicalDeviceShaderCorePropertiesAMD
*)ext
;
1273 /* Shader engines. */
1274 properties
->shaderEngineCount
=
1275 pdevice
->rad_info
.max_se
;
1276 properties
->shaderArraysPerEngineCount
=
1277 pdevice
->rad_info
.max_sh_per_se
;
1278 properties
->computeUnitsPerShaderArray
=
1279 pdevice
->rad_info
.num_good_cu_per_sh
;
1280 properties
->simdPerComputeUnit
= 4;
1281 properties
->wavefrontsPerSimd
=
1282 pdevice
->rad_info
.family
== CHIP_TONGA
||
1283 pdevice
->rad_info
.family
== CHIP_ICELAND
||
1284 pdevice
->rad_info
.family
== CHIP_POLARIS10
||
1285 pdevice
->rad_info
.family
== CHIP_POLARIS11
||
1286 pdevice
->rad_info
.family
== CHIP_POLARIS12
||
1287 pdevice
->rad_info
.family
== CHIP_VEGAM
? 8 : 10;
1288 properties
->wavefrontSize
= 64;
1291 properties
->sgprsPerSimd
=
1292 ac_get_num_physical_sgprs(&pdevice
->rad_info
);
1293 properties
->minSgprAllocation
=
1294 pdevice
->rad_info
.chip_class
>= GFX8
? 16 : 8;
1295 properties
->maxSgprAllocation
=
1296 pdevice
->rad_info
.family
== CHIP_TONGA
||
1297 pdevice
->rad_info
.family
== CHIP_ICELAND
? 96 : 104;
1298 properties
->sgprAllocationGranularity
=
1299 pdevice
->rad_info
.chip_class
>= GFX8
? 16 : 8;
1302 properties
->vgprsPerSimd
= RADV_NUM_PHYSICAL_VGPRS
;
1303 properties
->minVgprAllocation
= 4;
1304 properties
->maxVgprAllocation
= 256;
1305 properties
->vgprAllocationGranularity
= 4;
1308 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_2_AMD
: {
1309 VkPhysicalDeviceShaderCoreProperties2AMD
*properties
=
1310 (VkPhysicalDeviceShaderCoreProperties2AMD
*)ext
;
1312 properties
->shaderCoreFeatures
= 0;
1313 properties
->activeComputeUnitCount
=
1314 pdevice
->rad_info
.num_good_compute_units
;
1317 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT
: {
1318 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT
*properties
=
1319 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT
*)ext
;
1320 properties
->maxVertexAttribDivisor
= UINT32_MAX
;
1323 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT
: {
1324 VkPhysicalDeviceDescriptorIndexingPropertiesEXT
*properties
=
1325 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT
*)ext
;
1326 properties
->maxUpdateAfterBindDescriptorsInAllPools
= UINT32_MAX
/ 64;
1327 properties
->shaderUniformBufferArrayNonUniformIndexingNative
= false;
1328 properties
->shaderSampledImageArrayNonUniformIndexingNative
= false;
1329 properties
->shaderStorageBufferArrayNonUniformIndexingNative
= false;
1330 properties
->shaderStorageImageArrayNonUniformIndexingNative
= false;
1331 properties
->shaderInputAttachmentArrayNonUniformIndexingNative
= false;
1332 properties
->robustBufferAccessUpdateAfterBind
= false;
1333 properties
->quadDivergentImplicitLod
= false;
1335 size_t max_descriptor_set_size
= ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
-
1336 MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_INLINE_UNIFORM_BLOCK_COUNT
) /
1337 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1338 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1339 32 /* sampler, largest when combined with image */ +
1340 64 /* sampled image */ +
1341 64 /* storage image */);
1342 properties
->maxPerStageDescriptorUpdateAfterBindSamplers
= max_descriptor_set_size
;
1343 properties
->maxPerStageDescriptorUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1344 properties
->maxPerStageDescriptorUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1345 properties
->maxPerStageDescriptorUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1346 properties
->maxPerStageDescriptorUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1347 properties
->maxPerStageDescriptorUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1348 properties
->maxPerStageUpdateAfterBindResources
= max_descriptor_set_size
;
1349 properties
->maxDescriptorSetUpdateAfterBindSamplers
= max_descriptor_set_size
;
1350 properties
->maxDescriptorSetUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1351 properties
->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic
= MAX_DYNAMIC_UNIFORM_BUFFERS
;
1352 properties
->maxDescriptorSetUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1353 properties
->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic
= MAX_DYNAMIC_STORAGE_BUFFERS
;
1354 properties
->maxDescriptorSetUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1355 properties
->maxDescriptorSetUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1356 properties
->maxDescriptorSetUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1359 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES
: {
1360 VkPhysicalDeviceProtectedMemoryProperties
*properties
=
1361 (VkPhysicalDeviceProtectedMemoryProperties
*)ext
;
1362 properties
->protectedNoFault
= false;
1365 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT
: {
1366 VkPhysicalDeviceConservativeRasterizationPropertiesEXT
*properties
=
1367 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT
*)ext
;
1368 properties
->primitiveOverestimationSize
= 0;
1369 properties
->maxExtraPrimitiveOverestimationSize
= 0;
1370 properties
->extraPrimitiveOverestimationSizeGranularity
= 0;
1371 properties
->primitiveUnderestimation
= VK_FALSE
;
1372 properties
->conservativePointAndLineRasterization
= VK_FALSE
;
1373 properties
->degenerateTrianglesRasterized
= VK_FALSE
;
1374 properties
->degenerateLinesRasterized
= VK_FALSE
;
1375 properties
->fullyCoveredFragmentShaderInputVariable
= VK_FALSE
;
1376 properties
->conservativeRasterizationPostDepthCoverage
= VK_FALSE
;
1379 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT
: {
1380 VkPhysicalDevicePCIBusInfoPropertiesEXT
*properties
=
1381 (VkPhysicalDevicePCIBusInfoPropertiesEXT
*)ext
;
1382 properties
->pciDomain
= pdevice
->bus_info
.domain
;
1383 properties
->pciBus
= pdevice
->bus_info
.bus
;
1384 properties
->pciDevice
= pdevice
->bus_info
.dev
;
1385 properties
->pciFunction
= pdevice
->bus_info
.func
;
1388 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR
: {
1389 VkPhysicalDeviceDriverPropertiesKHR
*driver_props
=
1390 (VkPhysicalDeviceDriverPropertiesKHR
*) ext
;
1392 driver_props
->driverID
= VK_DRIVER_ID_MESA_RADV_KHR
;
1393 snprintf(driver_props
->driverName
, VK_MAX_DRIVER_NAME_SIZE_KHR
, "radv");
1394 snprintf(driver_props
->driverInfo
, VK_MAX_DRIVER_INFO_SIZE_KHR
,
1395 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1396 " (LLVM " MESA_LLVM_VERSION_STRING
")");
1398 driver_props
->conformanceVersion
= (VkConformanceVersionKHR
) {
1406 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT
: {
1407 VkPhysicalDeviceTransformFeedbackPropertiesEXT
*properties
=
1408 (VkPhysicalDeviceTransformFeedbackPropertiesEXT
*)ext
;
1409 properties
->maxTransformFeedbackStreams
= MAX_SO_STREAMS
;
1410 properties
->maxTransformFeedbackBuffers
= MAX_SO_BUFFERS
;
1411 properties
->maxTransformFeedbackBufferSize
= UINT32_MAX
;
1412 properties
->maxTransformFeedbackStreamDataSize
= 512;
1413 properties
->maxTransformFeedbackBufferDataSize
= UINT32_MAX
;
1414 properties
->maxTransformFeedbackBufferDataStride
= 512;
1415 properties
->transformFeedbackQueries
= true;
1416 properties
->transformFeedbackStreamsLinesTriangles
= true;
1417 properties
->transformFeedbackRasterizationStreamSelect
= false;
1418 properties
->transformFeedbackDraw
= true;
1421 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT
: {
1422 VkPhysicalDeviceInlineUniformBlockPropertiesEXT
*props
=
1423 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT
*)ext
;
1425 props
->maxInlineUniformBlockSize
= MAX_INLINE_UNIFORM_BLOCK_SIZE
;
1426 props
->maxPerStageDescriptorInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_SETS
;
1427 props
->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_SETS
;
1428 props
->maxDescriptorSetInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_COUNT
;
1429 props
->maxDescriptorSetUpdateAfterBindInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_COUNT
;
1432 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT
: {
1433 VkPhysicalDeviceSampleLocationsPropertiesEXT
*properties
=
1434 (VkPhysicalDeviceSampleLocationsPropertiesEXT
*)ext
;
1435 properties
->sampleLocationSampleCounts
= VK_SAMPLE_COUNT_2_BIT
|
1436 VK_SAMPLE_COUNT_4_BIT
|
1437 VK_SAMPLE_COUNT_8_BIT
;
1438 properties
->maxSampleLocationGridSize
= (VkExtent2D
){ 2 , 2 };
1439 properties
->sampleLocationCoordinateRange
[0] = 0.0f
;
1440 properties
->sampleLocationCoordinateRange
[1] = 0.9375f
;
1441 properties
->sampleLocationSubPixelBits
= 4;
1442 properties
->variableSampleLocations
= VK_FALSE
;
1445 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES_KHR
: {
1446 VkPhysicalDeviceDepthStencilResolvePropertiesKHR
*properties
=
1447 (VkPhysicalDeviceDepthStencilResolvePropertiesKHR
*)ext
;
1449 /* We support all of the depth resolve modes */
1450 properties
->supportedDepthResolveModes
=
1451 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
|
1452 VK_RESOLVE_MODE_AVERAGE_BIT_KHR
|
1453 VK_RESOLVE_MODE_MIN_BIT_KHR
|
1454 VK_RESOLVE_MODE_MAX_BIT_KHR
;
1456 /* Average doesn't make sense for stencil so we don't support that */
1457 properties
->supportedStencilResolveModes
=
1458 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
|
1459 VK_RESOLVE_MODE_MIN_BIT_KHR
|
1460 VK_RESOLVE_MODE_MAX_BIT_KHR
;
1462 properties
->independentResolveNone
= VK_TRUE
;
1463 properties
->independentResolve
= VK_TRUE
;
1472 static void radv_get_physical_device_queue_family_properties(
1473 struct radv_physical_device
* pdevice
,
1475 VkQueueFamilyProperties
** pQueueFamilyProperties
)
1477 int num_queue_families
= 1;
1479 if (pdevice
->rad_info
.num_compute_rings
> 0 &&
1480 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
))
1481 num_queue_families
++;
1483 if (pQueueFamilyProperties
== NULL
) {
1484 *pCount
= num_queue_families
;
1493 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
1494 .queueFlags
= VK_QUEUE_GRAPHICS_BIT
|
1495 VK_QUEUE_COMPUTE_BIT
|
1496 VK_QUEUE_TRANSFER_BIT
|
1497 VK_QUEUE_SPARSE_BINDING_BIT
,
1499 .timestampValidBits
= 64,
1500 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
1505 if (pdevice
->rad_info
.num_compute_rings
> 0 &&
1506 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
)) {
1507 if (*pCount
> idx
) {
1508 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
1509 .queueFlags
= VK_QUEUE_COMPUTE_BIT
|
1510 VK_QUEUE_TRANSFER_BIT
|
1511 VK_QUEUE_SPARSE_BINDING_BIT
,
1512 .queueCount
= pdevice
->rad_info
.num_compute_rings
,
1513 .timestampValidBits
= 64,
1514 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
1522 void radv_GetPhysicalDeviceQueueFamilyProperties(
1523 VkPhysicalDevice physicalDevice
,
1525 VkQueueFamilyProperties
* pQueueFamilyProperties
)
1527 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1528 if (!pQueueFamilyProperties
) {
1529 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
1532 VkQueueFamilyProperties
*properties
[] = {
1533 pQueueFamilyProperties
+ 0,
1534 pQueueFamilyProperties
+ 1,
1535 pQueueFamilyProperties
+ 2,
1537 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
1538 assert(*pCount
<= 3);
1541 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1542 VkPhysicalDevice physicalDevice
,
1544 VkQueueFamilyProperties2
*pQueueFamilyProperties
)
1546 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1547 if (!pQueueFamilyProperties
) {
1548 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
1551 VkQueueFamilyProperties
*properties
[] = {
1552 &pQueueFamilyProperties
[0].queueFamilyProperties
,
1553 &pQueueFamilyProperties
[1].queueFamilyProperties
,
1554 &pQueueFamilyProperties
[2].queueFamilyProperties
,
1556 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
1557 assert(*pCount
<= 3);
1560 void radv_GetPhysicalDeviceMemoryProperties(
1561 VkPhysicalDevice physicalDevice
,
1562 VkPhysicalDeviceMemoryProperties
*pMemoryProperties
)
1564 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
1566 *pMemoryProperties
= physical_device
->memory_properties
;
1570 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice
,
1571 VkPhysicalDeviceMemoryBudgetPropertiesEXT
*memoryBudget
)
1573 RADV_FROM_HANDLE(radv_physical_device
, device
, physicalDevice
);
1574 VkPhysicalDeviceMemoryProperties
*memory_properties
= &device
->memory_properties
;
1575 uint64_t visible_vram_size
= radv_get_visible_vram_size(device
);
1576 uint64_t vram_size
= radv_get_vram_size(device
);
1577 uint64_t gtt_size
= device
->rad_info
.gart_size
;
1578 uint64_t heap_budget
, heap_usage
;
1580 /* For all memory heaps, the computation of budget is as follow:
1581 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1583 * The Vulkan spec 1.1.97 says that the budget should include any
1584 * currently allocated device memory.
1586 * Note that the application heap usages are not really accurate (eg.
1587 * in presence of shared buffers).
1589 for (int i
= 0; i
< device
->memory_properties
.memoryTypeCount
; i
++) {
1590 uint32_t heap_index
= device
->memory_properties
.memoryTypes
[i
].heapIndex
;
1592 switch (device
->mem_type_indices
[i
]) {
1593 case RADV_MEM_TYPE_VRAM
:
1594 heap_usage
= device
->ws
->query_value(device
->ws
,
1595 RADEON_ALLOCATED_VRAM
);
1597 heap_budget
= vram_size
-
1598 device
->ws
->query_value(device
->ws
, RADEON_VRAM_USAGE
) +
1601 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
1602 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
1604 case RADV_MEM_TYPE_VRAM_CPU_ACCESS
:
1605 heap_usage
= device
->ws
->query_value(device
->ws
,
1606 RADEON_ALLOCATED_VRAM_VIS
);
1608 heap_budget
= visible_vram_size
-
1609 device
->ws
->query_value(device
->ws
, RADEON_VRAM_VIS_USAGE
) +
1612 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
1613 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
1615 case RADV_MEM_TYPE_GTT_WRITE_COMBINE
:
1616 heap_usage
= device
->ws
->query_value(device
->ws
,
1617 RADEON_ALLOCATED_GTT
);
1619 heap_budget
= gtt_size
-
1620 device
->ws
->query_value(device
->ws
, RADEON_GTT_USAGE
) +
1623 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
1624 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
1631 /* The heapBudget and heapUsage values must be zero for array elements
1632 * greater than or equal to
1633 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1635 for (uint32_t i
= memory_properties
->memoryHeapCount
; i
< VK_MAX_MEMORY_HEAPS
; i
++) {
1636 memoryBudget
->heapBudget
[i
] = 0;
1637 memoryBudget
->heapUsage
[i
] = 0;
1641 void radv_GetPhysicalDeviceMemoryProperties2(
1642 VkPhysicalDevice physicalDevice
,
1643 VkPhysicalDeviceMemoryProperties2
*pMemoryProperties
)
1645 radv_GetPhysicalDeviceMemoryProperties(physicalDevice
,
1646 &pMemoryProperties
->memoryProperties
);
1648 VkPhysicalDeviceMemoryBudgetPropertiesEXT
*memory_budget
=
1649 vk_find_struct(pMemoryProperties
->pNext
,
1650 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT
);
1652 radv_get_memory_budget_properties(physicalDevice
, memory_budget
);
1655 VkResult
radv_GetMemoryHostPointerPropertiesEXT(
1657 VkExternalMemoryHandleTypeFlagBits handleType
,
1658 const void *pHostPointer
,
1659 VkMemoryHostPointerPropertiesEXT
*pMemoryHostPointerProperties
)
1661 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1665 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT
: {
1666 const struct radv_physical_device
*physical_device
= device
->physical_device
;
1667 uint32_t memoryTypeBits
= 0;
1668 for (int i
= 0; i
< physical_device
->memory_properties
.memoryTypeCount
; i
++) {
1669 if (physical_device
->mem_type_indices
[i
] == RADV_MEM_TYPE_GTT_CACHED
) {
1670 memoryTypeBits
= (1 << i
);
1674 pMemoryHostPointerProperties
->memoryTypeBits
= memoryTypeBits
;
1678 return VK_ERROR_INVALID_EXTERNAL_HANDLE
;
1682 static enum radeon_ctx_priority
1683 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT
*pObj
)
1685 /* Default to MEDIUM when a specific global priority isn't requested */
1687 return RADEON_CTX_PRIORITY_MEDIUM
;
1689 switch(pObj
->globalPriority
) {
1690 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT
:
1691 return RADEON_CTX_PRIORITY_REALTIME
;
1692 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT
:
1693 return RADEON_CTX_PRIORITY_HIGH
;
1694 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT
:
1695 return RADEON_CTX_PRIORITY_MEDIUM
;
1696 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT
:
1697 return RADEON_CTX_PRIORITY_LOW
;
1699 unreachable("Illegal global priority value");
1700 return RADEON_CTX_PRIORITY_INVALID
;
1705 radv_queue_init(struct radv_device
*device
, struct radv_queue
*queue
,
1706 uint32_t queue_family_index
, int idx
,
1707 VkDeviceQueueCreateFlags flags
,
1708 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
)
1710 queue
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1711 queue
->device
= device
;
1712 queue
->queue_family_index
= queue_family_index
;
1713 queue
->queue_idx
= idx
;
1714 queue
->priority
= radv_get_queue_global_priority(global_priority
);
1715 queue
->flags
= flags
;
1717 queue
->hw_ctx
= device
->ws
->ctx_create(device
->ws
, queue
->priority
);
1719 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1725 radv_queue_finish(struct radv_queue
*queue
)
1728 queue
->device
->ws
->ctx_destroy(queue
->hw_ctx
);
1730 if (queue
->initial_full_flush_preamble_cs
)
1731 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
1732 if (queue
->initial_preamble_cs
)
1733 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
1734 if (queue
->continue_preamble_cs
)
1735 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
1736 if (queue
->descriptor_bo
)
1737 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
1738 if (queue
->scratch_bo
)
1739 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
1740 if (queue
->esgs_ring_bo
)
1741 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
1742 if (queue
->gsvs_ring_bo
)
1743 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
1744 if (queue
->tess_rings_bo
)
1745 queue
->device
->ws
->buffer_destroy(queue
->tess_rings_bo
);
1746 if (queue
->compute_scratch_bo
)
1747 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
1751 radv_bo_list_init(struct radv_bo_list
*bo_list
)
1753 pthread_mutex_init(&bo_list
->mutex
, NULL
);
1754 bo_list
->list
.count
= bo_list
->capacity
= 0;
1755 bo_list
->list
.bos
= NULL
;
1759 radv_bo_list_finish(struct radv_bo_list
*bo_list
)
1761 free(bo_list
->list
.bos
);
1762 pthread_mutex_destroy(&bo_list
->mutex
);
1765 static VkResult
radv_bo_list_add(struct radv_device
*device
,
1766 struct radeon_winsys_bo
*bo
)
1768 struct radv_bo_list
*bo_list
= &device
->bo_list
;
1773 if (unlikely(!device
->use_global_bo_list
))
1776 pthread_mutex_lock(&bo_list
->mutex
);
1777 if (bo_list
->list
.count
== bo_list
->capacity
) {
1778 unsigned capacity
= MAX2(4, bo_list
->capacity
* 2);
1779 void *data
= realloc(bo_list
->list
.bos
, capacity
* sizeof(struct radeon_winsys_bo
*));
1782 pthread_mutex_unlock(&bo_list
->mutex
);
1783 return VK_ERROR_OUT_OF_HOST_MEMORY
;
1786 bo_list
->list
.bos
= (struct radeon_winsys_bo
**)data
;
1787 bo_list
->capacity
= capacity
;
1790 bo_list
->list
.bos
[bo_list
->list
.count
++] = bo
;
1791 pthread_mutex_unlock(&bo_list
->mutex
);
1795 static void radv_bo_list_remove(struct radv_device
*device
,
1796 struct radeon_winsys_bo
*bo
)
1798 struct radv_bo_list
*bo_list
= &device
->bo_list
;
1803 if (unlikely(!device
->use_global_bo_list
))
1806 pthread_mutex_lock(&bo_list
->mutex
);
1807 for(unsigned i
= 0; i
< bo_list
->list
.count
; ++i
) {
1808 if (bo_list
->list
.bos
[i
] == bo
) {
1809 bo_list
->list
.bos
[i
] = bo_list
->list
.bos
[bo_list
->list
.count
- 1];
1810 --bo_list
->list
.count
;
1814 pthread_mutex_unlock(&bo_list
->mutex
);
1818 radv_device_init_gs_info(struct radv_device
*device
)
1820 device
->gs_table_depth
= ac_get_gs_table_depth(device
->physical_device
->rad_info
.chip_class
,
1821 device
->physical_device
->rad_info
.family
);
1824 static int radv_get_device_extension_index(const char *name
)
1826 for (unsigned i
= 0; i
< RADV_DEVICE_EXTENSION_COUNT
; ++i
) {
1827 if (strcmp(name
, radv_device_extensions
[i
].extensionName
) == 0)
1834 radv_get_int_debug_option(const char *name
, int default_value
)
1841 result
= default_value
;
1845 result
= strtol(str
, &endptr
, 0);
1846 if (str
== endptr
) {
1847 /* No digits founs. */
1848 result
= default_value
;
1855 VkResult
radv_CreateDevice(
1856 VkPhysicalDevice physicalDevice
,
1857 const VkDeviceCreateInfo
* pCreateInfo
,
1858 const VkAllocationCallbacks
* pAllocator
,
1861 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
1863 struct radv_device
*device
;
1865 bool keep_shader_info
= false;
1867 /* Check enabled features */
1868 if (pCreateInfo
->pEnabledFeatures
) {
1869 VkPhysicalDeviceFeatures supported_features
;
1870 radv_GetPhysicalDeviceFeatures(physicalDevice
, &supported_features
);
1871 VkBool32
*supported_feature
= (VkBool32
*)&supported_features
;
1872 VkBool32
*enabled_feature
= (VkBool32
*)pCreateInfo
->pEnabledFeatures
;
1873 unsigned num_features
= sizeof(VkPhysicalDeviceFeatures
) / sizeof(VkBool32
);
1874 for (uint32_t i
= 0; i
< num_features
; i
++) {
1875 if (enabled_feature
[i
] && !supported_feature
[i
])
1876 return vk_error(physical_device
->instance
, VK_ERROR_FEATURE_NOT_PRESENT
);
1880 device
= vk_zalloc2(&physical_device
->instance
->alloc
, pAllocator
,
1882 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
1884 return vk_error(physical_device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1886 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1887 device
->instance
= physical_device
->instance
;
1888 device
->physical_device
= physical_device
;
1890 device
->ws
= physical_device
->ws
;
1892 device
->alloc
= *pAllocator
;
1894 device
->alloc
= physical_device
->instance
->alloc
;
1896 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
1897 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
1898 int index
= radv_get_device_extension_index(ext_name
);
1899 if (index
< 0 || !physical_device
->supported_extensions
.extensions
[index
]) {
1900 vk_free(&device
->alloc
, device
);
1901 return vk_error(physical_device
->instance
, VK_ERROR_EXTENSION_NOT_PRESENT
);
1904 device
->enabled_extensions
.extensions
[index
] = true;
1907 keep_shader_info
= device
->enabled_extensions
.AMD_shader_info
;
1909 /* With update after bind we can't attach bo's to the command buffer
1910 * from the descriptor set anymore, so we have to use a global BO list.
1912 device
->use_global_bo_list
=
1913 (device
->instance
->perftest_flags
& RADV_PERFTEST_BO_LIST
) ||
1914 device
->enabled_extensions
.EXT_descriptor_indexing
||
1915 device
->enabled_extensions
.EXT_buffer_device_address
;
1917 device
->robust_buffer_access
= pCreateInfo
->pEnabledFeatures
&&
1918 pCreateInfo
->pEnabledFeatures
->robustBufferAccess
;
1920 mtx_init(&device
->shader_slab_mutex
, mtx_plain
);
1921 list_inithead(&device
->shader_slabs
);
1923 radv_bo_list_init(&device
->bo_list
);
1925 for (unsigned i
= 0; i
< pCreateInfo
->queueCreateInfoCount
; i
++) {
1926 const VkDeviceQueueCreateInfo
*queue_create
= &pCreateInfo
->pQueueCreateInfos
[i
];
1927 uint32_t qfi
= queue_create
->queueFamilyIndex
;
1928 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
=
1929 vk_find_struct_const(queue_create
->pNext
, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT
);
1931 assert(!global_priority
|| device
->physical_device
->rad_info
.has_ctx_priority
);
1933 device
->queues
[qfi
] = vk_alloc(&device
->alloc
,
1934 queue_create
->queueCount
* sizeof(struct radv_queue
), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
1935 if (!device
->queues
[qfi
]) {
1936 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
1940 memset(device
->queues
[qfi
], 0, queue_create
->queueCount
* sizeof(struct radv_queue
));
1942 device
->queue_count
[qfi
] = queue_create
->queueCount
;
1944 for (unsigned q
= 0; q
< queue_create
->queueCount
; q
++) {
1945 result
= radv_queue_init(device
, &device
->queues
[qfi
][q
],
1946 qfi
, q
, queue_create
->flags
,
1948 if (result
!= VK_SUCCESS
)
1953 device
->pbb_allowed
= device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
1954 !(device
->instance
->debug_flags
& RADV_DEBUG_NOBINNING
);
1956 device
->dfsm_allowed
= device
->pbb_allowed
&&
1957 (device
->physical_device
->rad_info
.family
== CHIP_RAVEN
||
1958 device
->physical_device
->rad_info
.family
== CHIP_RAVEN2
||
1959 device
->physical_device
->rad_info
.family
== CHIP_RENOIR
);
1962 device
->always_use_syncobj
= device
->physical_device
->rad_info
.has_syncobj_wait_for_submit
;
1965 /* The maximum number of scratch waves. Scratch space isn't divided
1966 * evenly between CUs. The number is only a function of the number of CUs.
1967 * We can decrease the constant to decrease the scratch buffer size.
1969 * sctx->scratch_waves must be >= the maximum possible size of
1970 * 1 threadgroup, so that the hw doesn't hang from being unable
1973 * The recommended value is 4 per CU at most. Higher numbers don't
1974 * bring much benefit, but they still occupy chip resources (think
1975 * async compute). I've seen ~2% performance difference between 4 and 32.
1977 uint32_t max_threads_per_block
= 2048;
1978 device
->scratch_waves
= MAX2(32 * physical_device
->rad_info
.num_good_compute_units
,
1979 max_threads_per_block
/ 64);
1981 device
->dispatch_initiator
= S_00B800_COMPUTE_SHADER_EN(1) |
1982 S_00B800_CS_W32_EN(device
->physical_device
->cs_wave_size
== 32);
1984 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
1985 /* If the KMD allows it (there is a KMD hw register for it),
1986 * allow launching waves out-of-order.
1988 device
->dispatch_initiator
|= S_00B800_ORDER_MODE(1);
1991 radv_device_init_gs_info(device
);
1993 device
->tess_offchip_block_dw_size
=
1994 device
->physical_device
->rad_info
.family
== CHIP_HAWAII
? 4096 : 8192;
1996 if (getenv("RADV_TRACE_FILE")) {
1997 const char *filename
= getenv("RADV_TRACE_FILE");
1999 keep_shader_info
= true;
2001 if (!radv_init_trace(device
))
2004 fprintf(stderr
, "*****************************************************************************\n");
2005 fprintf(stderr
, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
2006 fprintf(stderr
, "*****************************************************************************\n");
2008 fprintf(stderr
, "Trace file will be dumped to %s\n", filename
);
2009 radv_dump_enabled_options(device
, stderr
);
2012 device
->keep_shader_info
= keep_shader_info
;
2014 result
= radv_device_init_meta(device
);
2015 if (result
!= VK_SUCCESS
)
2018 radv_device_init_msaa(device
);
2020 for (int family
= 0; family
< RADV_MAX_QUEUE_FAMILIES
; ++family
) {
2021 device
->empty_cs
[family
] = device
->ws
->cs_create(device
->ws
, family
);
2023 case RADV_QUEUE_GENERAL
:
2024 /* Since amdgpu version 3.6.0, CONTEXT_CONTROL is emitted by the kernel */
2025 if (device
->physical_device
->rad_info
.drm_minor
< 6) {
2026 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
2027 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_LOAD_ENABLE(1));
2028 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_SHADOW_ENABLE(1));
2031 case RADV_QUEUE_COMPUTE
:
2032 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_NOP
, 0, 0));
2033 radeon_emit(device
->empty_cs
[family
], 0);
2036 device
->ws
->cs_finalize(device
->empty_cs
[family
]);
2039 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
2040 cik_create_gfx_config(device
);
2042 VkPipelineCacheCreateInfo ci
;
2043 ci
.sType
= VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO
;
2046 ci
.pInitialData
= NULL
;
2047 ci
.initialDataSize
= 0;
2049 result
= radv_CreatePipelineCache(radv_device_to_handle(device
),
2051 if (result
!= VK_SUCCESS
)
2054 device
->mem_cache
= radv_pipeline_cache_from_handle(pc
);
2056 device
->force_aniso
=
2057 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
2058 if (device
->force_aniso
>= 0) {
2059 fprintf(stderr
, "radv: Forcing anisotropy filter to %ix\n",
2060 1 << util_logbase2(device
->force_aniso
));
2063 *pDevice
= radv_device_to_handle(device
);
2067 radv_device_finish_meta(device
);
2069 radv_bo_list_finish(&device
->bo_list
);
2071 if (device
->trace_bo
)
2072 device
->ws
->buffer_destroy(device
->trace_bo
);
2074 if (device
->gfx_init
)
2075 device
->ws
->buffer_destroy(device
->gfx_init
);
2077 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
2078 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
2079 radv_queue_finish(&device
->queues
[i
][q
]);
2080 if (device
->queue_count
[i
])
2081 vk_free(&device
->alloc
, device
->queues
[i
]);
2084 vk_free(&device
->alloc
, device
);
2088 void radv_DestroyDevice(
2090 const VkAllocationCallbacks
* pAllocator
)
2092 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2097 if (device
->trace_bo
)
2098 device
->ws
->buffer_destroy(device
->trace_bo
);
2100 if (device
->gfx_init
)
2101 device
->ws
->buffer_destroy(device
->gfx_init
);
2103 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
2104 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
2105 radv_queue_finish(&device
->queues
[i
][q
]);
2106 if (device
->queue_count
[i
])
2107 vk_free(&device
->alloc
, device
->queues
[i
]);
2108 if (device
->empty_cs
[i
])
2109 device
->ws
->cs_destroy(device
->empty_cs
[i
]);
2111 radv_device_finish_meta(device
);
2113 VkPipelineCache pc
= radv_pipeline_cache_to_handle(device
->mem_cache
);
2114 radv_DestroyPipelineCache(radv_device_to_handle(device
), pc
, NULL
);
2116 radv_destroy_shader_slabs(device
);
2118 radv_bo_list_finish(&device
->bo_list
);
2119 vk_free(&device
->alloc
, device
);
2122 VkResult
radv_EnumerateInstanceLayerProperties(
2123 uint32_t* pPropertyCount
,
2124 VkLayerProperties
* pProperties
)
2126 if (pProperties
== NULL
) {
2127 *pPropertyCount
= 0;
2131 /* None supported at this time */
2132 return vk_error(NULL
, VK_ERROR_LAYER_NOT_PRESENT
);
2135 VkResult
radv_EnumerateDeviceLayerProperties(
2136 VkPhysicalDevice physicalDevice
,
2137 uint32_t* pPropertyCount
,
2138 VkLayerProperties
* pProperties
)
2140 if (pProperties
== NULL
) {
2141 *pPropertyCount
= 0;
2145 /* None supported at this time */
2146 return vk_error(NULL
, VK_ERROR_LAYER_NOT_PRESENT
);
2149 void radv_GetDeviceQueue2(
2151 const VkDeviceQueueInfo2
* pQueueInfo
,
2154 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2155 struct radv_queue
*queue
;
2157 queue
= &device
->queues
[pQueueInfo
->queueFamilyIndex
][pQueueInfo
->queueIndex
];
2158 if (pQueueInfo
->flags
!= queue
->flags
) {
2159 /* From the Vulkan 1.1.70 spec:
2161 * "The queue returned by vkGetDeviceQueue2 must have the same
2162 * flags value from this structure as that used at device
2163 * creation time in a VkDeviceQueueCreateInfo instance. If no
2164 * matching flags were specified at device creation time then
2165 * pQueue will return VK_NULL_HANDLE."
2167 *pQueue
= VK_NULL_HANDLE
;
2171 *pQueue
= radv_queue_to_handle(queue
);
2174 void radv_GetDeviceQueue(
2176 uint32_t queueFamilyIndex
,
2177 uint32_t queueIndex
,
2180 const VkDeviceQueueInfo2 info
= (VkDeviceQueueInfo2
) {
2181 .sType
= VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2
,
2182 .queueFamilyIndex
= queueFamilyIndex
,
2183 .queueIndex
= queueIndex
2186 radv_GetDeviceQueue2(_device
, &info
, pQueue
);
2190 fill_geom_tess_rings(struct radv_queue
*queue
,
2192 bool add_sample_positions
,
2193 uint32_t esgs_ring_size
,
2194 struct radeon_winsys_bo
*esgs_ring_bo
,
2195 uint32_t gsvs_ring_size
,
2196 struct radeon_winsys_bo
*gsvs_ring_bo
,
2197 uint32_t tess_factor_ring_size
,
2198 uint32_t tess_offchip_ring_offset
,
2199 uint32_t tess_offchip_ring_size
,
2200 struct radeon_winsys_bo
*tess_rings_bo
)
2202 uint32_t *desc
= &map
[4];
2205 uint64_t esgs_va
= radv_buffer_get_va(esgs_ring_bo
);
2207 /* stride 0, num records - size, add tid, swizzle, elsize4,
2210 desc
[1] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32) |
2211 S_008F04_SWIZZLE_ENABLE(true);
2212 desc
[2] = esgs_ring_size
;
2213 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2214 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2215 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2216 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2217 S_008F0C_INDEX_STRIDE(3) |
2218 S_008F0C_ADD_TID_ENABLE(1);
2220 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2221 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2222 S_008F0C_OOB_SELECT(2) |
2223 S_008F0C_RESOURCE_LEVEL(1);
2225 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2226 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
2227 S_008F0C_ELEMENT_SIZE(1);
2230 /* GS entry for ES->GS ring */
2231 /* stride 0, num records - size, elsize0,
2234 desc
[5] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32);
2235 desc
[6] = esgs_ring_size
;
2236 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2237 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2238 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2239 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
2241 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2242 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2243 S_008F0C_OOB_SELECT(2) |
2244 S_008F0C_RESOURCE_LEVEL(1);
2246 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2247 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2254 uint64_t gsvs_va
= radv_buffer_get_va(gsvs_ring_bo
);
2256 /* VS entry for GS->VS ring */
2257 /* stride 0, num records - size, elsize0,
2260 desc
[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32);
2261 desc
[2] = gsvs_ring_size
;
2262 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2263 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2264 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2265 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
2267 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2268 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2269 S_008F0C_OOB_SELECT(2) |
2270 S_008F0C_RESOURCE_LEVEL(1);
2272 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2273 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2276 /* stride gsvs_itemsize, num records 64
2277 elsize 4, index stride 16 */
2278 /* shader will patch stride and desc[2] */
2280 desc
[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32) |
2281 S_008F04_SWIZZLE_ENABLE(1);
2283 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2284 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2285 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2286 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2287 S_008F0C_INDEX_STRIDE(1) |
2288 S_008F0C_ADD_TID_ENABLE(true);
2290 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2291 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2292 S_008F0C_OOB_SELECT(2) |
2293 S_008F0C_RESOURCE_LEVEL(1);
2295 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2296 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
2297 S_008F0C_ELEMENT_SIZE(1);
2304 if (tess_rings_bo
) {
2305 uint64_t tess_va
= radv_buffer_get_va(tess_rings_bo
);
2306 uint64_t tess_offchip_va
= tess_va
+ tess_offchip_ring_offset
;
2309 desc
[1] = S_008F04_BASE_ADDRESS_HI(tess_va
>> 32);
2310 desc
[2] = tess_factor_ring_size
;
2311 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2312 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2313 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2314 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
2316 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2317 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2318 S_008F0C_OOB_SELECT(3) |
2319 S_008F0C_RESOURCE_LEVEL(1);
2321 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2322 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2325 desc
[4] = tess_offchip_va
;
2326 desc
[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va
>> 32);
2327 desc
[6] = tess_offchip_ring_size
;
2328 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2329 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2330 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2331 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
2333 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2334 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2335 S_008F0C_OOB_SELECT(3) |
2336 S_008F0C_RESOURCE_LEVEL(1);
2338 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2339 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2345 if (add_sample_positions
) {
2346 /* add sample positions after all rings */
2347 memcpy(desc
, queue
->device
->sample_locations_1x
, 8);
2349 memcpy(desc
, queue
->device
->sample_locations_2x
, 16);
2351 memcpy(desc
, queue
->device
->sample_locations_4x
, 32);
2353 memcpy(desc
, queue
->device
->sample_locations_8x
, 64);
2358 radv_get_hs_offchip_param(struct radv_device
*device
, uint32_t *max_offchip_buffers_p
)
2360 bool double_offchip_buffers
= device
->physical_device
->rad_info
.chip_class
>= GFX7
&&
2361 device
->physical_device
->rad_info
.family
!= CHIP_CARRIZO
&&
2362 device
->physical_device
->rad_info
.family
!= CHIP_STONEY
;
2363 unsigned max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
2364 unsigned max_offchip_buffers
;
2365 unsigned offchip_granularity
;
2366 unsigned hs_offchip_param
;
2370 * This must be one less than the maximum number due to a hw limitation.
2371 * Various hardware bugs need thGFX7
2374 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2375 * Gfx7 should limit max_offchip_buffers to 508
2376 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2378 * Follow AMDVLK here.
2380 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2381 max_offchip_buffers_per_se
= 256;
2382 } else if (device
->physical_device
->rad_info
.family
== CHIP_VEGA10
||
2383 device
->physical_device
->rad_info
.chip_class
== GFX7
||
2384 device
->physical_device
->rad_info
.chip_class
== GFX6
)
2385 --max_offchip_buffers_per_se
;
2387 max_offchip_buffers
= max_offchip_buffers_per_se
*
2388 device
->physical_device
->rad_info
.max_se
;
2390 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2391 * around by setting 4K granularity.
2393 if (device
->tess_offchip_block_dw_size
== 4096) {
2394 assert(device
->physical_device
->rad_info
.family
== CHIP_HAWAII
);
2395 offchip_granularity
= V_03093C_X_4K_DWORDS
;
2397 assert(device
->tess_offchip_block_dw_size
== 8192);
2398 offchip_granularity
= V_03093C_X_8K_DWORDS
;
2401 switch (device
->physical_device
->rad_info
.chip_class
) {
2403 max_offchip_buffers
= MIN2(max_offchip_buffers
, 126);
2408 max_offchip_buffers
= MIN2(max_offchip_buffers
, 508);
2416 *max_offchip_buffers_p
= max_offchip_buffers
;
2417 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2418 if (device
->physical_device
->rad_info
.chip_class
>= GFX8
)
2419 --max_offchip_buffers
;
2421 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
2422 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
);
2425 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
);
2427 return hs_offchip_param
;
2431 radv_emit_gs_ring_sizes(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
2432 struct radeon_winsys_bo
*esgs_ring_bo
,
2433 uint32_t esgs_ring_size
,
2434 struct radeon_winsys_bo
*gsvs_ring_bo
,
2435 uint32_t gsvs_ring_size
)
2437 if (!esgs_ring_bo
&& !gsvs_ring_bo
)
2441 radv_cs_add_buffer(queue
->device
->ws
, cs
, esgs_ring_bo
);
2444 radv_cs_add_buffer(queue
->device
->ws
, cs
, gsvs_ring_bo
);
2446 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2447 radeon_set_uconfig_reg_seq(cs
, R_030900_VGT_ESGS_RING_SIZE
, 2);
2448 radeon_emit(cs
, esgs_ring_size
>> 8);
2449 radeon_emit(cs
, gsvs_ring_size
>> 8);
2451 radeon_set_config_reg_seq(cs
, R_0088C8_VGT_ESGS_RING_SIZE
, 2);
2452 radeon_emit(cs
, esgs_ring_size
>> 8);
2453 radeon_emit(cs
, gsvs_ring_size
>> 8);
2458 radv_emit_tess_factor_ring(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
2459 unsigned hs_offchip_param
, unsigned tf_ring_size
,
2460 struct radeon_winsys_bo
*tess_rings_bo
)
2467 tf_va
= radv_buffer_get_va(tess_rings_bo
);
2469 radv_cs_add_buffer(queue
->device
->ws
, cs
, tess_rings_bo
);
2471 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2472 radeon_set_uconfig_reg(cs
, R_030938_VGT_TF_RING_SIZE
,
2473 S_030938_SIZE(tf_ring_size
/ 4));
2474 radeon_set_uconfig_reg(cs
, R_030940_VGT_TF_MEMORY_BASE
,
2477 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2478 radeon_set_uconfig_reg(cs
, R_030984_VGT_TF_MEMORY_BASE_HI_UMD
,
2479 S_030984_BASE_HI(tf_va
>> 40));
2480 } else if (queue
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
2481 radeon_set_uconfig_reg(cs
, R_030944_VGT_TF_MEMORY_BASE_HI
,
2482 S_030944_BASE_HI(tf_va
>> 40));
2484 radeon_set_uconfig_reg(cs
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
2487 radeon_set_config_reg(cs
, R_008988_VGT_TF_RING_SIZE
,
2488 S_008988_SIZE(tf_ring_size
/ 4));
2489 radeon_set_config_reg(cs
, R_0089B8_VGT_TF_MEMORY_BASE
,
2491 radeon_set_config_reg(cs
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
2497 radv_emit_compute_scratch(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
2498 struct radeon_winsys_bo
*compute_scratch_bo
)
2500 uint64_t scratch_va
;
2502 if (!compute_scratch_bo
)
2505 scratch_va
= radv_buffer_get_va(compute_scratch_bo
);
2507 radv_cs_add_buffer(queue
->device
->ws
, cs
, compute_scratch_bo
);
2509 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
, 2);
2510 radeon_emit(cs
, scratch_va
);
2511 radeon_emit(cs
, S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
2512 S_008F04_SWIZZLE_ENABLE(1));
2516 radv_emit_global_shader_pointers(struct radv_queue
*queue
,
2517 struct radeon_cmdbuf
*cs
,
2518 struct radeon_winsys_bo
*descriptor_bo
)
2525 va
= radv_buffer_get_va(descriptor_bo
);
2527 radv_cs_add_buffer(queue
->device
->ws
, cs
, descriptor_bo
);
2529 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2530 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
2531 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
2532 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
,
2533 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
};
2535 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
2536 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
2539 } else if (queue
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
2540 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
2541 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
2542 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
,
2543 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
};
2545 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
2546 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
2550 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
2551 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
2552 R_00B230_SPI_SHADER_USER_DATA_GS_0
,
2553 R_00B330_SPI_SHADER_USER_DATA_ES_0
,
2554 R_00B430_SPI_SHADER_USER_DATA_HS_0
,
2555 R_00B530_SPI_SHADER_USER_DATA_LS_0
};
2557 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
2558 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
2565 radv_init_graphics_state(struct radeon_cmdbuf
*cs
, struct radv_queue
*queue
)
2567 struct radv_device
*device
= queue
->device
;
2569 if (device
->gfx_init
) {
2570 uint64_t va
= radv_buffer_get_va(device
->gfx_init
);
2572 radeon_emit(cs
, PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0));
2573 radeon_emit(cs
, va
);
2574 radeon_emit(cs
, va
>> 32);
2575 radeon_emit(cs
, device
->gfx_init_size_dw
& 0xffff);
2577 radv_cs_add_buffer(device
->ws
, cs
, device
->gfx_init
);
2579 struct radv_physical_device
*physical_device
= device
->physical_device
;
2580 si_emit_graphics(physical_device
, cs
);
2585 radv_init_compute_state(struct radeon_cmdbuf
*cs
, struct radv_queue
*queue
)
2587 struct radv_physical_device
*physical_device
= queue
->device
->physical_device
;
2588 si_emit_compute(physical_device
, cs
);
2592 radv_get_preamble_cs(struct radv_queue
*queue
,
2593 uint32_t scratch_size
,
2594 uint32_t compute_scratch_size
,
2595 uint32_t esgs_ring_size
,
2596 uint32_t gsvs_ring_size
,
2597 bool needs_tess_rings
,
2598 bool needs_sample_positions
,
2599 struct radeon_cmdbuf
**initial_full_flush_preamble_cs
,
2600 struct radeon_cmdbuf
**initial_preamble_cs
,
2601 struct radeon_cmdbuf
**continue_preamble_cs
)
2603 struct radeon_winsys_bo
*scratch_bo
= NULL
;
2604 struct radeon_winsys_bo
*descriptor_bo
= NULL
;
2605 struct radeon_winsys_bo
*compute_scratch_bo
= NULL
;
2606 struct radeon_winsys_bo
*esgs_ring_bo
= NULL
;
2607 struct radeon_winsys_bo
*gsvs_ring_bo
= NULL
;
2608 struct radeon_winsys_bo
*tess_rings_bo
= NULL
;
2609 struct radeon_cmdbuf
*dest_cs
[3] = {0};
2610 bool add_tess_rings
= false, add_sample_positions
= false;
2611 unsigned tess_factor_ring_size
= 0, tess_offchip_ring_size
= 0;
2612 unsigned max_offchip_buffers
;
2613 unsigned hs_offchip_param
= 0;
2614 unsigned tess_offchip_ring_offset
;
2615 uint32_t ring_bo_flags
= RADEON_FLAG_NO_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
;
2616 if (!queue
->has_tess_rings
) {
2617 if (needs_tess_rings
)
2618 add_tess_rings
= true;
2620 if (!queue
->has_sample_positions
) {
2621 if (needs_sample_positions
)
2622 add_sample_positions
= true;
2624 tess_factor_ring_size
= 32768 * queue
->device
->physical_device
->rad_info
.max_se
;
2625 hs_offchip_param
= radv_get_hs_offchip_param(queue
->device
,
2626 &max_offchip_buffers
);
2627 tess_offchip_ring_offset
= align(tess_factor_ring_size
, 64 * 1024);
2628 tess_offchip_ring_size
= max_offchip_buffers
*
2629 queue
->device
->tess_offchip_block_dw_size
* 4;
2631 if (scratch_size
<= queue
->scratch_size
&&
2632 compute_scratch_size
<= queue
->compute_scratch_size
&&
2633 esgs_ring_size
<= queue
->esgs_ring_size
&&
2634 gsvs_ring_size
<= queue
->gsvs_ring_size
&&
2635 !add_tess_rings
&& !add_sample_positions
&&
2636 queue
->initial_preamble_cs
) {
2637 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
2638 *initial_preamble_cs
= queue
->initial_preamble_cs
;
2639 *continue_preamble_cs
= queue
->continue_preamble_cs
;
2640 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
2641 *continue_preamble_cs
= NULL
;
2645 if (scratch_size
> queue
->scratch_size
) {
2646 scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2651 RADV_BO_PRIORITY_SCRATCH
);
2655 scratch_bo
= queue
->scratch_bo
;
2657 if (compute_scratch_size
> queue
->compute_scratch_size
) {
2658 compute_scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2659 compute_scratch_size
,
2663 RADV_BO_PRIORITY_SCRATCH
);
2664 if (!compute_scratch_bo
)
2668 compute_scratch_bo
= queue
->compute_scratch_bo
;
2670 if (esgs_ring_size
> queue
->esgs_ring_size
) {
2671 esgs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2676 RADV_BO_PRIORITY_SCRATCH
);
2680 esgs_ring_bo
= queue
->esgs_ring_bo
;
2681 esgs_ring_size
= queue
->esgs_ring_size
;
2684 if (gsvs_ring_size
> queue
->gsvs_ring_size
) {
2685 gsvs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2690 RADV_BO_PRIORITY_SCRATCH
);
2694 gsvs_ring_bo
= queue
->gsvs_ring_bo
;
2695 gsvs_ring_size
= queue
->gsvs_ring_size
;
2698 if (add_tess_rings
) {
2699 tess_rings_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2700 tess_offchip_ring_offset
+ tess_offchip_ring_size
,
2704 RADV_BO_PRIORITY_SCRATCH
);
2708 tess_rings_bo
= queue
->tess_rings_bo
;
2711 if (scratch_bo
!= queue
->scratch_bo
||
2712 esgs_ring_bo
!= queue
->esgs_ring_bo
||
2713 gsvs_ring_bo
!= queue
->gsvs_ring_bo
||
2714 tess_rings_bo
!= queue
->tess_rings_bo
||
2715 add_sample_positions
) {
2717 if (gsvs_ring_bo
|| esgs_ring_bo
||
2718 tess_rings_bo
|| add_sample_positions
) {
2719 size
= 112; /* 2 dword + 2 padding + 4 dword * 6 */
2720 if (add_sample_positions
)
2721 size
+= 128; /* 64+32+16+8 = 120 bytes */
2723 else if (scratch_bo
)
2724 size
= 8; /* 2 dword */
2726 descriptor_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2730 RADEON_FLAG_CPU_ACCESS
|
2731 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
2732 RADEON_FLAG_READ_ONLY
,
2733 RADV_BO_PRIORITY_DESCRIPTOR
);
2737 descriptor_bo
= queue
->descriptor_bo
;
2739 if (descriptor_bo
!= queue
->descriptor_bo
) {
2740 uint32_t *map
= (uint32_t*)queue
->device
->ws
->buffer_map(descriptor_bo
);
2743 uint64_t scratch_va
= radv_buffer_get_va(scratch_bo
);
2744 uint32_t rsrc1
= S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
2745 S_008F04_SWIZZLE_ENABLE(1);
2746 map
[0] = scratch_va
;
2750 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_rings_bo
|| add_sample_positions
)
2751 fill_geom_tess_rings(queue
, map
, add_sample_positions
,
2752 esgs_ring_size
, esgs_ring_bo
,
2753 gsvs_ring_size
, gsvs_ring_bo
,
2754 tess_factor_ring_size
,
2755 tess_offchip_ring_offset
,
2756 tess_offchip_ring_size
,
2759 queue
->device
->ws
->buffer_unmap(descriptor_bo
);
2762 for(int i
= 0; i
< 3; ++i
) {
2763 struct radeon_cmdbuf
*cs
= NULL
;
2764 cs
= queue
->device
->ws
->cs_create(queue
->device
->ws
,
2765 queue
->queue_family_index
? RING_COMPUTE
: RING_GFX
);
2772 radv_cs_add_buffer(queue
->device
->ws
, cs
, scratch_bo
);
2774 /* Emit initial configuration. */
2775 switch (queue
->queue_family_index
) {
2776 case RADV_QUEUE_GENERAL
:
2777 radv_init_graphics_state(cs
, queue
);
2779 case RADV_QUEUE_COMPUTE
:
2780 radv_init_compute_state(cs
, queue
);
2782 case RADV_QUEUE_TRANSFER
:
2786 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_rings_bo
) {
2787 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2788 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2790 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2791 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
2794 radv_emit_gs_ring_sizes(queue
, cs
, esgs_ring_bo
, esgs_ring_size
,
2795 gsvs_ring_bo
, gsvs_ring_size
);
2796 radv_emit_tess_factor_ring(queue
, cs
, hs_offchip_param
,
2797 tess_factor_ring_size
, tess_rings_bo
);
2798 radv_emit_global_shader_pointers(queue
, cs
, descriptor_bo
);
2799 radv_emit_compute_scratch(queue
, cs
, compute_scratch_bo
);
2802 si_cs_emit_cache_flush(cs
,
2803 queue
->device
->physical_device
->rad_info
.chip_class
,
2805 queue
->queue_family_index
== RING_COMPUTE
&&
2806 queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
,
2807 (queue
->queue_family_index
== RADV_QUEUE_COMPUTE
? RADV_CMD_FLAG_CS_PARTIAL_FLUSH
: (RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
)) |
2808 RADV_CMD_FLAG_INV_ICACHE
|
2809 RADV_CMD_FLAG_INV_SCACHE
|
2810 RADV_CMD_FLAG_INV_VCACHE
|
2811 RADV_CMD_FLAG_INV_L2
|
2812 RADV_CMD_FLAG_START_PIPELINE_STATS
, 0);
2813 } else if (i
== 1) {
2814 si_cs_emit_cache_flush(cs
,
2815 queue
->device
->physical_device
->rad_info
.chip_class
,
2817 queue
->queue_family_index
== RING_COMPUTE
&&
2818 queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
,
2819 RADV_CMD_FLAG_INV_ICACHE
|
2820 RADV_CMD_FLAG_INV_SCACHE
|
2821 RADV_CMD_FLAG_INV_VCACHE
|
2822 RADV_CMD_FLAG_INV_L2
|
2823 RADV_CMD_FLAG_START_PIPELINE_STATS
, 0);
2826 if (!queue
->device
->ws
->cs_finalize(cs
))
2830 if (queue
->initial_full_flush_preamble_cs
)
2831 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
2833 if (queue
->initial_preamble_cs
)
2834 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
2836 if (queue
->continue_preamble_cs
)
2837 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
2839 queue
->initial_full_flush_preamble_cs
= dest_cs
[0];
2840 queue
->initial_preamble_cs
= dest_cs
[1];
2841 queue
->continue_preamble_cs
= dest_cs
[2];
2843 if (scratch_bo
!= queue
->scratch_bo
) {
2844 if (queue
->scratch_bo
)
2845 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
2846 queue
->scratch_bo
= scratch_bo
;
2847 queue
->scratch_size
= scratch_size
;
2850 if (compute_scratch_bo
!= queue
->compute_scratch_bo
) {
2851 if (queue
->compute_scratch_bo
)
2852 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
2853 queue
->compute_scratch_bo
= compute_scratch_bo
;
2854 queue
->compute_scratch_size
= compute_scratch_size
;
2857 if (esgs_ring_bo
!= queue
->esgs_ring_bo
) {
2858 if (queue
->esgs_ring_bo
)
2859 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
2860 queue
->esgs_ring_bo
= esgs_ring_bo
;
2861 queue
->esgs_ring_size
= esgs_ring_size
;
2864 if (gsvs_ring_bo
!= queue
->gsvs_ring_bo
) {
2865 if (queue
->gsvs_ring_bo
)
2866 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
2867 queue
->gsvs_ring_bo
= gsvs_ring_bo
;
2868 queue
->gsvs_ring_size
= gsvs_ring_size
;
2871 if (tess_rings_bo
!= queue
->tess_rings_bo
) {
2872 queue
->tess_rings_bo
= tess_rings_bo
;
2873 queue
->has_tess_rings
= true;
2876 if (descriptor_bo
!= queue
->descriptor_bo
) {
2877 if (queue
->descriptor_bo
)
2878 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
2880 queue
->descriptor_bo
= descriptor_bo
;
2883 if (add_sample_positions
)
2884 queue
->has_sample_positions
= true;
2886 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
2887 *initial_preamble_cs
= queue
->initial_preamble_cs
;
2888 *continue_preamble_cs
= queue
->continue_preamble_cs
;
2889 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
2890 *continue_preamble_cs
= NULL
;
2893 for (int i
= 0; i
< ARRAY_SIZE(dest_cs
); ++i
)
2895 queue
->device
->ws
->cs_destroy(dest_cs
[i
]);
2896 if (descriptor_bo
&& descriptor_bo
!= queue
->descriptor_bo
)
2897 queue
->device
->ws
->buffer_destroy(descriptor_bo
);
2898 if (scratch_bo
&& scratch_bo
!= queue
->scratch_bo
)
2899 queue
->device
->ws
->buffer_destroy(scratch_bo
);
2900 if (compute_scratch_bo
&& compute_scratch_bo
!= queue
->compute_scratch_bo
)
2901 queue
->device
->ws
->buffer_destroy(compute_scratch_bo
);
2902 if (esgs_ring_bo
&& esgs_ring_bo
!= queue
->esgs_ring_bo
)
2903 queue
->device
->ws
->buffer_destroy(esgs_ring_bo
);
2904 if (gsvs_ring_bo
&& gsvs_ring_bo
!= queue
->gsvs_ring_bo
)
2905 queue
->device
->ws
->buffer_destroy(gsvs_ring_bo
);
2906 if (tess_rings_bo
&& tess_rings_bo
!= queue
->tess_rings_bo
)
2907 queue
->device
->ws
->buffer_destroy(tess_rings_bo
);
2908 return vk_error(queue
->device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2911 static VkResult
radv_alloc_sem_counts(struct radv_instance
*instance
,
2912 struct radv_winsys_sem_counts
*counts
,
2914 const VkSemaphore
*sems
,
2918 int syncobj_idx
= 0, sem_idx
= 0;
2920 if (num_sems
== 0 && _fence
== VK_NULL_HANDLE
)
2923 for (uint32_t i
= 0; i
< num_sems
; i
++) {
2924 RADV_FROM_HANDLE(radv_semaphore
, sem
, sems
[i
]);
2926 if (sem
->temp_syncobj
|| sem
->syncobj
)
2927 counts
->syncobj_count
++;
2929 counts
->sem_count
++;
2932 if (_fence
!= VK_NULL_HANDLE
) {
2933 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2934 if (fence
->temp_syncobj
|| fence
->syncobj
)
2935 counts
->syncobj_count
++;
2938 if (counts
->syncobj_count
) {
2939 counts
->syncobj
= (uint32_t *)malloc(sizeof(uint32_t) * counts
->syncobj_count
);
2940 if (!counts
->syncobj
)
2941 return vk_error(instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2944 if (counts
->sem_count
) {
2945 counts
->sem
= (struct radeon_winsys_sem
**)malloc(sizeof(struct radeon_winsys_sem
*) * counts
->sem_count
);
2947 free(counts
->syncobj
);
2948 return vk_error(instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2952 for (uint32_t i
= 0; i
< num_sems
; i
++) {
2953 RADV_FROM_HANDLE(radv_semaphore
, sem
, sems
[i
]);
2955 if (sem
->temp_syncobj
) {
2956 counts
->syncobj
[syncobj_idx
++] = sem
->temp_syncobj
;
2958 else if (sem
->syncobj
)
2959 counts
->syncobj
[syncobj_idx
++] = sem
->syncobj
;
2962 counts
->sem
[sem_idx
++] = sem
->sem
;
2966 if (_fence
!= VK_NULL_HANDLE
) {
2967 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2968 if (fence
->temp_syncobj
)
2969 counts
->syncobj
[syncobj_idx
++] = fence
->temp_syncobj
;
2970 else if (fence
->syncobj
)
2971 counts
->syncobj
[syncobj_idx
++] = fence
->syncobj
;
2978 radv_free_sem_info(struct radv_winsys_sem_info
*sem_info
)
2980 free(sem_info
->wait
.syncobj
);
2981 free(sem_info
->wait
.sem
);
2982 free(sem_info
->signal
.syncobj
);
2983 free(sem_info
->signal
.sem
);
2987 static void radv_free_temp_syncobjs(struct radv_device
*device
,
2989 const VkSemaphore
*sems
)
2991 for (uint32_t i
= 0; i
< num_sems
; i
++) {
2992 RADV_FROM_HANDLE(radv_semaphore
, sem
, sems
[i
]);
2994 if (sem
->temp_syncobj
) {
2995 device
->ws
->destroy_syncobj(device
->ws
, sem
->temp_syncobj
);
2996 sem
->temp_syncobj
= 0;
3002 radv_alloc_sem_info(struct radv_instance
*instance
,
3003 struct radv_winsys_sem_info
*sem_info
,
3005 const VkSemaphore
*wait_sems
,
3006 int num_signal_sems
,
3007 const VkSemaphore
*signal_sems
,
3011 memset(sem_info
, 0, sizeof(*sem_info
));
3013 ret
= radv_alloc_sem_counts(instance
, &sem_info
->wait
, num_wait_sems
, wait_sems
, VK_NULL_HANDLE
, true);
3016 ret
= radv_alloc_sem_counts(instance
, &sem_info
->signal
, num_signal_sems
, signal_sems
, fence
, false);
3018 radv_free_sem_info(sem_info
);
3020 /* caller can override these */
3021 sem_info
->cs_emit_wait
= true;
3022 sem_info
->cs_emit_signal
= true;
3026 /* Signals fence as soon as all the work currently put on queue is done. */
3027 static VkResult
radv_signal_fence(struct radv_queue
*queue
,
3028 struct radv_fence
*fence
)
3032 struct radv_winsys_sem_info sem_info
;
3034 result
= radv_alloc_sem_info(queue
->device
->instance
, &sem_info
, 0, NULL
, 0, NULL
,
3035 radv_fence_to_handle(fence
));
3036 if (result
!= VK_SUCCESS
)
3039 ret
= queue
->device
->ws
->cs_submit(queue
->hw_ctx
, queue
->queue_idx
,
3040 &queue
->device
->empty_cs
[queue
->queue_family_index
],
3041 1, NULL
, NULL
, &sem_info
, NULL
,
3042 false, fence
->fence
);
3043 radv_free_sem_info(&sem_info
);
3046 return vk_error(queue
->device
->instance
, VK_ERROR_DEVICE_LOST
);
3051 VkResult
radv_QueueSubmit(
3053 uint32_t submitCount
,
3054 const VkSubmitInfo
* pSubmits
,
3057 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
3058 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
3059 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
3060 struct radeon_winsys_ctx
*ctx
= queue
->hw_ctx
;
3062 uint32_t max_cs_submission
= queue
->device
->trace_bo
? 1 : RADV_MAX_IBS_PER_SUBMIT
;
3063 uint32_t scratch_size
= 0;
3064 uint32_t compute_scratch_size
= 0;
3065 uint32_t esgs_ring_size
= 0, gsvs_ring_size
= 0;
3066 struct radeon_cmdbuf
*initial_preamble_cs
= NULL
, *initial_flush_preamble_cs
= NULL
, *continue_preamble_cs
= NULL
;
3068 bool fence_emitted
= false;
3069 bool tess_rings_needed
= false;
3070 bool sample_positions_needed
= false;
3072 /* Do this first so failing to allocate scratch buffers can't result in
3073 * partially executed submissions. */
3074 for (uint32_t i
= 0; i
< submitCount
; i
++) {
3075 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
++) {
3076 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
3077 pSubmits
[i
].pCommandBuffers
[j
]);
3079 scratch_size
= MAX2(scratch_size
, cmd_buffer
->scratch_size_needed
);
3080 compute_scratch_size
= MAX2(compute_scratch_size
,
3081 cmd_buffer
->compute_scratch_size_needed
);
3082 esgs_ring_size
= MAX2(esgs_ring_size
, cmd_buffer
->esgs_ring_size_needed
);
3083 gsvs_ring_size
= MAX2(gsvs_ring_size
, cmd_buffer
->gsvs_ring_size_needed
);
3084 tess_rings_needed
|= cmd_buffer
->tess_rings_needed
;
3085 sample_positions_needed
|= cmd_buffer
->sample_positions_needed
;
3089 result
= radv_get_preamble_cs(queue
, scratch_size
, compute_scratch_size
,
3090 esgs_ring_size
, gsvs_ring_size
, tess_rings_needed
,
3091 sample_positions_needed
, &initial_flush_preamble_cs
,
3092 &initial_preamble_cs
, &continue_preamble_cs
);
3093 if (result
!= VK_SUCCESS
)
3096 for (uint32_t i
= 0; i
< submitCount
; i
++) {
3097 struct radeon_cmdbuf
**cs_array
;
3098 bool do_flush
= !i
|| pSubmits
[i
].pWaitDstStageMask
;
3099 bool can_patch
= true;
3101 struct radv_winsys_sem_info sem_info
;
3103 result
= radv_alloc_sem_info(queue
->device
->instance
,
3105 pSubmits
[i
].waitSemaphoreCount
,
3106 pSubmits
[i
].pWaitSemaphores
,
3107 pSubmits
[i
].signalSemaphoreCount
,
3108 pSubmits
[i
].pSignalSemaphores
,
3110 if (result
!= VK_SUCCESS
)
3113 if (!pSubmits
[i
].commandBufferCount
) {
3114 if (pSubmits
[i
].waitSemaphoreCount
|| pSubmits
[i
].signalSemaphoreCount
) {
3115 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
,
3116 &queue
->device
->empty_cs
[queue
->queue_family_index
],
3121 radv_loge("failed to submit CS %d\n", i
);
3124 fence_emitted
= true;
3126 radv_free_sem_info(&sem_info
);
3130 cs_array
= malloc(sizeof(struct radeon_cmdbuf
*) *
3131 (pSubmits
[i
].commandBufferCount
));
3133 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
++) {
3134 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
3135 pSubmits
[i
].pCommandBuffers
[j
]);
3136 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
3138 cs_array
[j
] = cmd_buffer
->cs
;
3139 if ((cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT
))
3142 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_PENDING
;
3145 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
+= advance
) {
3146 struct radeon_cmdbuf
*initial_preamble
= (do_flush
&& !j
) ? initial_flush_preamble_cs
: initial_preamble_cs
;
3147 const struct radv_winsys_bo_list
*bo_list
= NULL
;
3149 advance
= MIN2(max_cs_submission
,
3150 pSubmits
[i
].commandBufferCount
- j
);
3152 if (queue
->device
->trace_bo
)
3153 *queue
->device
->trace_id_ptr
= 0;
3155 sem_info
.cs_emit_wait
= j
== 0;
3156 sem_info
.cs_emit_signal
= j
+ advance
== pSubmits
[i
].commandBufferCount
;
3158 if (unlikely(queue
->device
->use_global_bo_list
)) {
3159 pthread_mutex_lock(&queue
->device
->bo_list
.mutex
);
3160 bo_list
= &queue
->device
->bo_list
.list
;
3163 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
, cs_array
+ j
,
3164 advance
, initial_preamble
, continue_preamble_cs
,
3166 can_patch
, base_fence
);
3168 if (unlikely(queue
->device
->use_global_bo_list
))
3169 pthread_mutex_unlock(&queue
->device
->bo_list
.mutex
);
3172 radv_loge("failed to submit CS %d\n", i
);
3175 fence_emitted
= true;
3176 if (queue
->device
->trace_bo
) {
3177 radv_check_gpu_hangs(queue
, cs_array
[j
]);
3181 radv_free_temp_syncobjs(queue
->device
,
3182 pSubmits
[i
].waitSemaphoreCount
,
3183 pSubmits
[i
].pWaitSemaphores
);
3184 radv_free_sem_info(&sem_info
);
3189 if (!fence_emitted
) {
3190 result
= radv_signal_fence(queue
, fence
);
3191 if (result
!= VK_SUCCESS
)
3199 VkResult
radv_QueueWaitIdle(
3202 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
3204 queue
->device
->ws
->ctx_wait_idle(queue
->hw_ctx
,
3205 radv_queue_family_to_ring(queue
->queue_family_index
),
3210 VkResult
radv_DeviceWaitIdle(
3213 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3215 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
3216 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++) {
3217 radv_QueueWaitIdle(radv_queue_to_handle(&device
->queues
[i
][q
]));
3223 VkResult
radv_EnumerateInstanceExtensionProperties(
3224 const char* pLayerName
,
3225 uint32_t* pPropertyCount
,
3226 VkExtensionProperties
* pProperties
)
3228 VK_OUTARRAY_MAKE(out
, pProperties
, pPropertyCount
);
3230 for (int i
= 0; i
< RADV_INSTANCE_EXTENSION_COUNT
; i
++) {
3231 if (radv_supported_instance_extensions
.extensions
[i
]) {
3232 vk_outarray_append(&out
, prop
) {
3233 *prop
= radv_instance_extensions
[i
];
3238 return vk_outarray_status(&out
);
3241 VkResult
radv_EnumerateDeviceExtensionProperties(
3242 VkPhysicalDevice physicalDevice
,
3243 const char* pLayerName
,
3244 uint32_t* pPropertyCount
,
3245 VkExtensionProperties
* pProperties
)
3247 RADV_FROM_HANDLE(radv_physical_device
, device
, physicalDevice
);
3248 VK_OUTARRAY_MAKE(out
, pProperties
, pPropertyCount
);
3250 for (int i
= 0; i
< RADV_DEVICE_EXTENSION_COUNT
; i
++) {
3251 if (device
->supported_extensions
.extensions
[i
]) {
3252 vk_outarray_append(&out
, prop
) {
3253 *prop
= radv_device_extensions
[i
];
3258 return vk_outarray_status(&out
);
3261 PFN_vkVoidFunction
radv_GetInstanceProcAddr(
3262 VkInstance _instance
,
3265 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
3266 bool unchecked
= instance
? instance
->debug_flags
& RADV_DEBUG_ALL_ENTRYPOINTS
: false;
3269 return radv_lookup_entrypoint_unchecked(pName
);
3271 return radv_lookup_entrypoint_checked(pName
,
3272 instance
? instance
->apiVersion
: 0,
3273 instance
? &instance
->enabled_extensions
: NULL
,
3278 /* The loader wants us to expose a second GetInstanceProcAddr function
3279 * to work around certain LD_PRELOAD issues seen in apps.
3282 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
3283 VkInstance instance
,
3287 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
3288 VkInstance instance
,
3291 return radv_GetInstanceProcAddr(instance
, pName
);
3295 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetPhysicalDeviceProcAddr(
3296 VkInstance _instance
,
3300 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetPhysicalDeviceProcAddr(
3301 VkInstance _instance
,
3304 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
3306 return radv_lookup_physical_device_entrypoint_checked(pName
,
3307 instance
? instance
->apiVersion
: 0,
3308 instance
? &instance
->enabled_extensions
: NULL
);
3311 PFN_vkVoidFunction
radv_GetDeviceProcAddr(
3315 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3316 bool unchecked
= device
? device
->instance
->debug_flags
& RADV_DEBUG_ALL_ENTRYPOINTS
: false;
3319 return radv_lookup_entrypoint_unchecked(pName
);
3321 return radv_lookup_entrypoint_checked(pName
,
3322 device
->instance
->apiVersion
,
3323 &device
->instance
->enabled_extensions
,
3324 &device
->enabled_extensions
);
3328 bool radv_get_memory_fd(struct radv_device
*device
,
3329 struct radv_device_memory
*memory
,
3332 struct radeon_bo_metadata metadata
;
3334 if (memory
->image
) {
3335 radv_init_metadata(device
, memory
->image
, &metadata
);
3336 device
->ws
->buffer_set_metadata(memory
->bo
, &metadata
);
3339 return device
->ws
->buffer_get_fd(device
->ws
, memory
->bo
,
3343 static VkResult
radv_alloc_memory(struct radv_device
*device
,
3344 const VkMemoryAllocateInfo
* pAllocateInfo
,
3345 const VkAllocationCallbacks
* pAllocator
,
3346 VkDeviceMemory
* pMem
)
3348 struct radv_device_memory
*mem
;
3350 enum radeon_bo_domain domain
;
3352 enum radv_mem_type mem_type_index
= device
->physical_device
->mem_type_indices
[pAllocateInfo
->memoryTypeIndex
];
3354 assert(pAllocateInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO
);
3356 if (pAllocateInfo
->allocationSize
== 0) {
3357 /* Apparently, this is allowed */
3358 *pMem
= VK_NULL_HANDLE
;
3362 const VkImportMemoryFdInfoKHR
*import_info
=
3363 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_FD_INFO_KHR
);
3364 const VkMemoryDedicatedAllocateInfo
*dedicate_info
=
3365 vk_find_struct_const(pAllocateInfo
->pNext
, MEMORY_DEDICATED_ALLOCATE_INFO
);
3366 const VkExportMemoryAllocateInfo
*export_info
=
3367 vk_find_struct_const(pAllocateInfo
->pNext
, EXPORT_MEMORY_ALLOCATE_INFO
);
3368 const VkImportMemoryHostPointerInfoEXT
*host_ptr_info
=
3369 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_HOST_POINTER_INFO_EXT
);
3371 const struct wsi_memory_allocate_info
*wsi_info
=
3372 vk_find_struct_const(pAllocateInfo
->pNext
, WSI_MEMORY_ALLOCATE_INFO_MESA
);
3374 mem
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*mem
), 8,
3375 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3377 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3379 if (wsi_info
&& wsi_info
->implicit_sync
)
3380 flags
|= RADEON_FLAG_IMPLICIT_SYNC
;
3382 if (dedicate_info
) {
3383 mem
->image
= radv_image_from_handle(dedicate_info
->image
);
3384 mem
->buffer
= radv_buffer_from_handle(dedicate_info
->buffer
);
3390 float priority_float
= 0.5;
3391 const struct VkMemoryPriorityAllocateInfoEXT
*priority_ext
=
3392 vk_find_struct_const(pAllocateInfo
->pNext
,
3393 MEMORY_PRIORITY_ALLOCATE_INFO_EXT
);
3395 priority_float
= priority_ext
->priority
;
3397 unsigned priority
= MIN2(RADV_BO_PRIORITY_APPLICATION_MAX
- 1,
3398 (int)(priority_float
* RADV_BO_PRIORITY_APPLICATION_MAX
));
3400 mem
->user_ptr
= NULL
;
3403 assert(import_info
->handleType
==
3404 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT
||
3405 import_info
->handleType
==
3406 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
3407 mem
->bo
= device
->ws
->buffer_from_fd(device
->ws
, import_info
->fd
,
3408 priority
, NULL
, NULL
);
3410 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE
;
3413 close(import_info
->fd
);
3415 } else if (host_ptr_info
) {
3416 assert(host_ptr_info
->handleType
== VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT
);
3417 assert(mem_type_index
== RADV_MEM_TYPE_GTT_CACHED
);
3418 mem
->bo
= device
->ws
->buffer_from_ptr(device
->ws
, host_ptr_info
->pHostPointer
,
3419 pAllocateInfo
->allocationSize
,
3422 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE
;
3425 mem
->user_ptr
= host_ptr_info
->pHostPointer
;
3428 uint64_t alloc_size
= align_u64(pAllocateInfo
->allocationSize
, 4096);
3429 if (mem_type_index
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
||
3430 mem_type_index
== RADV_MEM_TYPE_GTT_CACHED
)
3431 domain
= RADEON_DOMAIN_GTT
;
3433 domain
= RADEON_DOMAIN_VRAM
;
3435 if (mem_type_index
== RADV_MEM_TYPE_VRAM
)
3436 flags
|= RADEON_FLAG_NO_CPU_ACCESS
;
3438 flags
|= RADEON_FLAG_CPU_ACCESS
;
3440 if (mem_type_index
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
)
3441 flags
|= RADEON_FLAG_GTT_WC
;
3443 if (!dedicate_info
&& !import_info
&& (!export_info
|| !export_info
->handleTypes
)) {
3444 flags
|= RADEON_FLAG_NO_INTERPROCESS_SHARING
;
3445 if (device
->use_global_bo_list
) {
3446 flags
|= RADEON_FLAG_PREFER_LOCAL_BO
;
3450 mem
->bo
= device
->ws
->buffer_create(device
->ws
, alloc_size
, device
->physical_device
->rad_info
.max_alignment
,
3451 domain
, flags
, priority
);
3454 result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
3457 mem
->type_index
= mem_type_index
;
3460 result
= radv_bo_list_add(device
, mem
->bo
);
3461 if (result
!= VK_SUCCESS
)
3464 *pMem
= radv_device_memory_to_handle(mem
);
3469 device
->ws
->buffer_destroy(mem
->bo
);
3471 vk_free2(&device
->alloc
, pAllocator
, mem
);
3476 VkResult
radv_AllocateMemory(
3478 const VkMemoryAllocateInfo
* pAllocateInfo
,
3479 const VkAllocationCallbacks
* pAllocator
,
3480 VkDeviceMemory
* pMem
)
3482 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3483 return radv_alloc_memory(device
, pAllocateInfo
, pAllocator
, pMem
);
3486 void radv_FreeMemory(
3488 VkDeviceMemory _mem
,
3489 const VkAllocationCallbacks
* pAllocator
)
3491 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3492 RADV_FROM_HANDLE(radv_device_memory
, mem
, _mem
);
3497 radv_bo_list_remove(device
, mem
->bo
);
3498 device
->ws
->buffer_destroy(mem
->bo
);
3501 vk_free2(&device
->alloc
, pAllocator
, mem
);
3504 VkResult
radv_MapMemory(
3506 VkDeviceMemory _memory
,
3507 VkDeviceSize offset
,
3509 VkMemoryMapFlags flags
,
3512 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3513 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
3521 *ppData
= mem
->user_ptr
;
3523 *ppData
= device
->ws
->buffer_map(mem
->bo
);
3530 return vk_error(device
->instance
, VK_ERROR_MEMORY_MAP_FAILED
);
3533 void radv_UnmapMemory(
3535 VkDeviceMemory _memory
)
3537 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3538 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
3543 if (mem
->user_ptr
== NULL
)
3544 device
->ws
->buffer_unmap(mem
->bo
);
3547 VkResult
radv_FlushMappedMemoryRanges(
3549 uint32_t memoryRangeCount
,
3550 const VkMappedMemoryRange
* pMemoryRanges
)
3555 VkResult
radv_InvalidateMappedMemoryRanges(
3557 uint32_t memoryRangeCount
,
3558 const VkMappedMemoryRange
* pMemoryRanges
)
3563 void radv_GetBufferMemoryRequirements(
3566 VkMemoryRequirements
* pMemoryRequirements
)
3568 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3569 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3571 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
3573 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
3574 pMemoryRequirements
->alignment
= 4096;
3576 pMemoryRequirements
->alignment
= 16;
3578 pMemoryRequirements
->size
= align64(buffer
->size
, pMemoryRequirements
->alignment
);
3581 void radv_GetBufferMemoryRequirements2(
3583 const VkBufferMemoryRequirementsInfo2
*pInfo
,
3584 VkMemoryRequirements2
*pMemoryRequirements
)
3586 radv_GetBufferMemoryRequirements(device
, pInfo
->buffer
,
3587 &pMemoryRequirements
->memoryRequirements
);
3588 RADV_FROM_HANDLE(radv_buffer
, buffer
, pInfo
->buffer
);
3589 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
3590 switch (ext
->sType
) {
3591 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS
: {
3592 VkMemoryDedicatedRequirements
*req
=
3593 (VkMemoryDedicatedRequirements
*) ext
;
3594 req
->requiresDedicatedAllocation
= buffer
->shareable
;
3595 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
3604 void radv_GetImageMemoryRequirements(
3607 VkMemoryRequirements
* pMemoryRequirements
)
3609 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3610 RADV_FROM_HANDLE(radv_image
, image
, _image
);
3612 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
3614 pMemoryRequirements
->size
= image
->size
;
3615 pMemoryRequirements
->alignment
= image
->alignment
;
3618 void radv_GetImageMemoryRequirements2(
3620 const VkImageMemoryRequirementsInfo2
*pInfo
,
3621 VkMemoryRequirements2
*pMemoryRequirements
)
3623 radv_GetImageMemoryRequirements(device
, pInfo
->image
,
3624 &pMemoryRequirements
->memoryRequirements
);
3626 RADV_FROM_HANDLE(radv_image
, image
, pInfo
->image
);
3628 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
3629 switch (ext
->sType
) {
3630 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS
: {
3631 VkMemoryDedicatedRequirements
*req
=
3632 (VkMemoryDedicatedRequirements
*) ext
;
3633 req
->requiresDedicatedAllocation
= image
->shareable
;
3634 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
3643 void radv_GetImageSparseMemoryRequirements(
3646 uint32_t* pSparseMemoryRequirementCount
,
3647 VkSparseImageMemoryRequirements
* pSparseMemoryRequirements
)
3652 void radv_GetImageSparseMemoryRequirements2(
3654 const VkImageSparseMemoryRequirementsInfo2
*pInfo
,
3655 uint32_t* pSparseMemoryRequirementCount
,
3656 VkSparseImageMemoryRequirements2
*pSparseMemoryRequirements
)
3661 void radv_GetDeviceMemoryCommitment(
3663 VkDeviceMemory memory
,
3664 VkDeviceSize
* pCommittedMemoryInBytes
)
3666 *pCommittedMemoryInBytes
= 0;
3669 VkResult
radv_BindBufferMemory2(VkDevice device
,
3670 uint32_t bindInfoCount
,
3671 const VkBindBufferMemoryInfo
*pBindInfos
)
3673 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
3674 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
3675 RADV_FROM_HANDLE(radv_buffer
, buffer
, pBindInfos
[i
].buffer
);
3678 buffer
->bo
= mem
->bo
;
3679 buffer
->offset
= pBindInfos
[i
].memoryOffset
;
3687 VkResult
radv_BindBufferMemory(
3690 VkDeviceMemory memory
,
3691 VkDeviceSize memoryOffset
)
3693 const VkBindBufferMemoryInfo info
= {
3694 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO
,
3697 .memoryOffset
= memoryOffset
3700 return radv_BindBufferMemory2(device
, 1, &info
);
3703 VkResult
radv_BindImageMemory2(VkDevice device
,
3704 uint32_t bindInfoCount
,
3705 const VkBindImageMemoryInfo
*pBindInfos
)
3707 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
3708 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
3709 RADV_FROM_HANDLE(radv_image
, image
, pBindInfos
[i
].image
);
3712 image
->bo
= mem
->bo
;
3713 image
->offset
= pBindInfos
[i
].memoryOffset
;
3723 VkResult
radv_BindImageMemory(
3726 VkDeviceMemory memory
,
3727 VkDeviceSize memoryOffset
)
3729 const VkBindImageMemoryInfo info
= {
3730 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO
,
3733 .memoryOffset
= memoryOffset
3736 return radv_BindImageMemory2(device
, 1, &info
);
3741 radv_sparse_buffer_bind_memory(struct radv_device
*device
,
3742 const VkSparseBufferMemoryBindInfo
*bind
)
3744 RADV_FROM_HANDLE(radv_buffer
, buffer
, bind
->buffer
);
3746 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
3747 struct radv_device_memory
*mem
= NULL
;
3749 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
3750 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
3752 device
->ws
->buffer_virtual_bind(buffer
->bo
,
3753 bind
->pBinds
[i
].resourceOffset
,
3754 bind
->pBinds
[i
].size
,
3755 mem
? mem
->bo
: NULL
,
3756 bind
->pBinds
[i
].memoryOffset
);
3761 radv_sparse_image_opaque_bind_memory(struct radv_device
*device
,
3762 const VkSparseImageOpaqueMemoryBindInfo
*bind
)
3764 RADV_FROM_HANDLE(radv_image
, image
, bind
->image
);
3766 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
3767 struct radv_device_memory
*mem
= NULL
;
3769 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
3770 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
3772 device
->ws
->buffer_virtual_bind(image
->bo
,
3773 bind
->pBinds
[i
].resourceOffset
,
3774 bind
->pBinds
[i
].size
,
3775 mem
? mem
->bo
: NULL
,
3776 bind
->pBinds
[i
].memoryOffset
);
3780 VkResult
radv_QueueBindSparse(
3782 uint32_t bindInfoCount
,
3783 const VkBindSparseInfo
* pBindInfo
,
3786 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
3787 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
3788 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
3789 bool fence_emitted
= false;
3793 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
3794 struct radv_winsys_sem_info sem_info
;
3795 for (uint32_t j
= 0; j
< pBindInfo
[i
].bufferBindCount
; ++j
) {
3796 radv_sparse_buffer_bind_memory(queue
->device
,
3797 pBindInfo
[i
].pBufferBinds
+ j
);
3800 for (uint32_t j
= 0; j
< pBindInfo
[i
].imageOpaqueBindCount
; ++j
) {
3801 radv_sparse_image_opaque_bind_memory(queue
->device
,
3802 pBindInfo
[i
].pImageOpaqueBinds
+ j
);
3806 result
= radv_alloc_sem_info(queue
->device
->instance
,
3808 pBindInfo
[i
].waitSemaphoreCount
,
3809 pBindInfo
[i
].pWaitSemaphores
,
3810 pBindInfo
[i
].signalSemaphoreCount
,
3811 pBindInfo
[i
].pSignalSemaphores
,
3813 if (result
!= VK_SUCCESS
)
3816 if (pBindInfo
[i
].waitSemaphoreCount
|| pBindInfo
[i
].signalSemaphoreCount
) {
3817 ret
= queue
->device
->ws
->cs_submit(queue
->hw_ctx
, queue
->queue_idx
,
3818 &queue
->device
->empty_cs
[queue
->queue_family_index
],
3823 radv_loge("failed to submit CS %d\n", i
);
3827 fence_emitted
= true;
3830 radv_free_sem_info(&sem_info
);
3835 if (!fence_emitted
) {
3836 result
= radv_signal_fence(queue
, fence
);
3837 if (result
!= VK_SUCCESS
)
3845 VkResult
radv_CreateFence(
3847 const VkFenceCreateInfo
* pCreateInfo
,
3848 const VkAllocationCallbacks
* pAllocator
,
3851 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3852 const VkExportFenceCreateInfo
*export
=
3853 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_FENCE_CREATE_INFO
);
3854 VkExternalFenceHandleTypeFlags handleTypes
=
3855 export
? export
->handleTypes
: 0;
3857 struct radv_fence
*fence
= vk_alloc2(&device
->alloc
, pAllocator
,
3859 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3862 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3864 fence
->fence_wsi
= NULL
;
3865 fence
->temp_syncobj
= 0;
3866 if (device
->always_use_syncobj
|| handleTypes
) {
3867 int ret
= device
->ws
->create_syncobj(device
->ws
, &fence
->syncobj
);
3869 vk_free2(&device
->alloc
, pAllocator
, fence
);
3870 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3872 if (pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
) {
3873 device
->ws
->signal_syncobj(device
->ws
, fence
->syncobj
);
3875 fence
->fence
= NULL
;
3877 fence
->fence
= device
->ws
->create_fence();
3878 if (!fence
->fence
) {
3879 vk_free2(&device
->alloc
, pAllocator
, fence
);
3880 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3883 if (pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
)
3884 device
->ws
->signal_fence(fence
->fence
);
3887 *pFence
= radv_fence_to_handle(fence
);
3892 void radv_DestroyFence(
3895 const VkAllocationCallbacks
* pAllocator
)
3897 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3898 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
3903 if (fence
->temp_syncobj
)
3904 device
->ws
->destroy_syncobj(device
->ws
, fence
->temp_syncobj
);
3906 device
->ws
->destroy_syncobj(device
->ws
, fence
->syncobj
);
3908 device
->ws
->destroy_fence(fence
->fence
);
3909 if (fence
->fence_wsi
)
3910 fence
->fence_wsi
->destroy(fence
->fence_wsi
);
3911 vk_free2(&device
->alloc
, pAllocator
, fence
);
3915 uint64_t radv_get_current_time(void)
3918 clock_gettime(CLOCK_MONOTONIC
, &tv
);
3919 return tv
.tv_nsec
+ tv
.tv_sec
*1000000000ull;
3922 static uint64_t radv_get_absolute_timeout(uint64_t timeout
)
3924 uint64_t current_time
= radv_get_current_time();
3926 timeout
= MIN2(UINT64_MAX
- current_time
, timeout
);
3928 return current_time
+ timeout
;
3932 static bool radv_all_fences_plain_and_submitted(struct radv_device
*device
,
3933 uint32_t fenceCount
, const VkFence
*pFences
)
3935 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3936 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3937 if (fence
->fence
== NULL
|| fence
->syncobj
||
3938 fence
->temp_syncobj
|| fence
->fence_wsi
||
3939 (!device
->ws
->is_fence_waitable(fence
->fence
)))
3945 static bool radv_all_fences_syncobj(uint32_t fenceCount
, const VkFence
*pFences
)
3947 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3948 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3949 if (fence
->syncobj
== 0 && fence
->temp_syncobj
== 0)
3955 VkResult
radv_WaitForFences(
3957 uint32_t fenceCount
,
3958 const VkFence
* pFences
,
3962 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3963 timeout
= radv_get_absolute_timeout(timeout
);
3965 if (device
->always_use_syncobj
&&
3966 radv_all_fences_syncobj(fenceCount
, pFences
))
3968 uint32_t *handles
= malloc(sizeof(uint32_t) * fenceCount
);
3970 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3972 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3973 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3974 handles
[i
] = fence
->temp_syncobj
? fence
->temp_syncobj
: fence
->syncobj
;
3977 bool success
= device
->ws
->wait_syncobj(device
->ws
, handles
, fenceCount
, waitAll
, timeout
);
3980 return success
? VK_SUCCESS
: VK_TIMEOUT
;
3983 if (!waitAll
&& fenceCount
> 1) {
3984 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3985 if (device
->physical_device
->rad_info
.drm_minor
>= 10 && radv_all_fences_plain_and_submitted(device
, fenceCount
, pFences
)) {
3986 uint32_t wait_count
= 0;
3987 struct radeon_winsys_fence
**fences
= malloc(sizeof(struct radeon_winsys_fence
*) * fenceCount
);
3989 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3991 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3992 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3994 if (device
->ws
->fence_wait(device
->ws
, fence
->fence
, false, 0)) {
3999 fences
[wait_count
++] = fence
->fence
;
4002 bool success
= device
->ws
->fences_wait(device
->ws
, fences
, wait_count
,
4003 waitAll
, timeout
- radv_get_current_time());
4006 return success
? VK_SUCCESS
: VK_TIMEOUT
;
4009 while(radv_get_current_time() <= timeout
) {
4010 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
4011 if (radv_GetFenceStatus(_device
, pFences
[i
]) == VK_SUCCESS
)
4018 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
4019 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
4020 bool expired
= false;
4022 if (fence
->temp_syncobj
) {
4023 if (!device
->ws
->wait_syncobj(device
->ws
, &fence
->temp_syncobj
, 1, true, timeout
))
4028 if (fence
->syncobj
) {
4029 if (!device
->ws
->wait_syncobj(device
->ws
, &fence
->syncobj
, 1, true, timeout
))
4035 if (!device
->ws
->is_fence_waitable(fence
->fence
)) {
4036 while(!device
->ws
->is_fence_waitable(fence
->fence
) &&
4037 radv_get_current_time() <= timeout
)
4041 expired
= device
->ws
->fence_wait(device
->ws
,
4048 if (fence
->fence_wsi
) {
4049 VkResult result
= fence
->fence_wsi
->wait(fence
->fence_wsi
, timeout
);
4050 if (result
!= VK_SUCCESS
)
4058 VkResult
radv_ResetFences(VkDevice _device
,
4059 uint32_t fenceCount
,
4060 const VkFence
*pFences
)
4062 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4064 for (unsigned i
= 0; i
< fenceCount
; ++i
) {
4065 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
4067 device
->ws
->reset_fence(fence
->fence
);
4069 /* Per spec, we first restore the permanent payload, and then reset, so
4070 * having a temp syncobj should not skip resetting the permanent syncobj. */
4071 if (fence
->temp_syncobj
) {
4072 device
->ws
->destroy_syncobj(device
->ws
, fence
->temp_syncobj
);
4073 fence
->temp_syncobj
= 0;
4076 if (fence
->syncobj
) {
4077 device
->ws
->reset_syncobj(device
->ws
, fence
->syncobj
);
4084 VkResult
radv_GetFenceStatus(VkDevice _device
, VkFence _fence
)
4086 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4087 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
4089 if (fence
->temp_syncobj
) {
4090 bool success
= device
->ws
->wait_syncobj(device
->ws
, &fence
->temp_syncobj
, 1, true, 0);
4091 return success
? VK_SUCCESS
: VK_NOT_READY
;
4094 if (fence
->syncobj
) {
4095 bool success
= device
->ws
->wait_syncobj(device
->ws
, &fence
->syncobj
, 1, true, 0);
4096 return success
? VK_SUCCESS
: VK_NOT_READY
;
4100 if (!device
->ws
->fence_wait(device
->ws
, fence
->fence
, false, 0))
4101 return VK_NOT_READY
;
4103 if (fence
->fence_wsi
) {
4104 VkResult result
= fence
->fence_wsi
->wait(fence
->fence_wsi
, 0);
4106 if (result
!= VK_SUCCESS
) {
4107 if (result
== VK_TIMEOUT
)
4108 return VK_NOT_READY
;
4116 // Queue semaphore functions
4118 VkResult
radv_CreateSemaphore(
4120 const VkSemaphoreCreateInfo
* pCreateInfo
,
4121 const VkAllocationCallbacks
* pAllocator
,
4122 VkSemaphore
* pSemaphore
)
4124 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4125 const VkExportSemaphoreCreateInfo
*export
=
4126 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_SEMAPHORE_CREATE_INFO
);
4127 VkExternalSemaphoreHandleTypeFlags handleTypes
=
4128 export
? export
->handleTypes
: 0;
4130 struct radv_semaphore
*sem
= vk_alloc2(&device
->alloc
, pAllocator
,
4132 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4134 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4136 sem
->temp_syncobj
= 0;
4137 /* create a syncobject if we are going to export this semaphore */
4138 if (device
->always_use_syncobj
|| handleTypes
) {
4139 assert (device
->physical_device
->rad_info
.has_syncobj
);
4140 int ret
= device
->ws
->create_syncobj(device
->ws
, &sem
->syncobj
);
4142 vk_free2(&device
->alloc
, pAllocator
, sem
);
4143 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4147 sem
->sem
= device
->ws
->create_sem(device
->ws
);
4149 vk_free2(&device
->alloc
, pAllocator
, sem
);
4150 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4155 *pSemaphore
= radv_semaphore_to_handle(sem
);
4159 void radv_DestroySemaphore(
4161 VkSemaphore _semaphore
,
4162 const VkAllocationCallbacks
* pAllocator
)
4164 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4165 RADV_FROM_HANDLE(radv_semaphore
, sem
, _semaphore
);
4170 device
->ws
->destroy_syncobj(device
->ws
, sem
->syncobj
);
4172 device
->ws
->destroy_sem(sem
->sem
);
4173 vk_free2(&device
->alloc
, pAllocator
, sem
);
4176 VkResult
radv_CreateEvent(
4178 const VkEventCreateInfo
* pCreateInfo
,
4179 const VkAllocationCallbacks
* pAllocator
,
4182 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4183 struct radv_event
*event
= vk_alloc2(&device
->alloc
, pAllocator
,
4185 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4188 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4190 event
->bo
= device
->ws
->buffer_create(device
->ws
, 8, 8,
4192 RADEON_FLAG_VA_UNCACHED
| RADEON_FLAG_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
,
4193 RADV_BO_PRIORITY_FENCE
);
4195 vk_free2(&device
->alloc
, pAllocator
, event
);
4196 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
4199 event
->map
= (uint64_t*)device
->ws
->buffer_map(event
->bo
);
4201 *pEvent
= radv_event_to_handle(event
);
4206 void radv_DestroyEvent(
4209 const VkAllocationCallbacks
* pAllocator
)
4211 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4212 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4216 device
->ws
->buffer_destroy(event
->bo
);
4217 vk_free2(&device
->alloc
, pAllocator
, event
);
4220 VkResult
radv_GetEventStatus(
4224 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4226 if (*event
->map
== 1)
4227 return VK_EVENT_SET
;
4228 return VK_EVENT_RESET
;
4231 VkResult
radv_SetEvent(
4235 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4241 VkResult
radv_ResetEvent(
4245 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4251 VkResult
radv_CreateBuffer(
4253 const VkBufferCreateInfo
* pCreateInfo
,
4254 const VkAllocationCallbacks
* pAllocator
,
4257 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4258 struct radv_buffer
*buffer
;
4260 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO
);
4262 buffer
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*buffer
), 8,
4263 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4265 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4267 buffer
->size
= pCreateInfo
->size
;
4268 buffer
->usage
= pCreateInfo
->usage
;
4271 buffer
->flags
= pCreateInfo
->flags
;
4273 buffer
->shareable
= vk_find_struct_const(pCreateInfo
->pNext
,
4274 EXTERNAL_MEMORY_BUFFER_CREATE_INFO
) != NULL
;
4276 if (pCreateInfo
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
) {
4277 buffer
->bo
= device
->ws
->buffer_create(device
->ws
,
4278 align64(buffer
->size
, 4096),
4279 4096, 0, RADEON_FLAG_VIRTUAL
,
4280 RADV_BO_PRIORITY_VIRTUAL
);
4282 vk_free2(&device
->alloc
, pAllocator
, buffer
);
4283 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
4287 *pBuffer
= radv_buffer_to_handle(buffer
);
4292 void radv_DestroyBuffer(
4295 const VkAllocationCallbacks
* pAllocator
)
4297 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4298 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4303 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
4304 device
->ws
->buffer_destroy(buffer
->bo
);
4306 vk_free2(&device
->alloc
, pAllocator
, buffer
);
4309 VkDeviceAddress
radv_GetBufferDeviceAddressEXT(
4311 const VkBufferDeviceAddressInfoEXT
* pInfo
)
4313 RADV_FROM_HANDLE(radv_buffer
, buffer
, pInfo
->buffer
);
4314 return radv_buffer_get_va(buffer
->bo
) + buffer
->offset
;
4318 static inline unsigned
4319 si_tile_mode_index(const struct radv_image_plane
*plane
, unsigned level
, bool stencil
)
4322 return plane
->surface
.u
.legacy
.stencil_tiling_index
[level
];
4324 return plane
->surface
.u
.legacy
.tiling_index
[level
];
4327 static uint32_t radv_surface_max_layer_count(struct radv_image_view
*iview
)
4329 return iview
->type
== VK_IMAGE_VIEW_TYPE_3D
? iview
->extent
.depth
: (iview
->base_layer
+ iview
->layer_count
);
4333 radv_init_dcc_control_reg(struct radv_device
*device
,
4334 struct radv_image_view
*iview
)
4336 unsigned max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_256B
;
4337 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
4338 unsigned max_compressed_block_size
;
4339 unsigned independent_128b_blocks
;
4340 unsigned independent_64b_blocks
;
4342 if (!radv_dcc_enabled(iview
->image
, iview
->base_mip
))
4345 if (!device
->physical_device
->rad_info
.has_dedicated_vram
) {
4346 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4347 * dGPU and 64 for APU because all of our APUs to date use
4348 * DIMMs which have a request granularity size of 64B while all
4349 * other chips have a 32B request size.
4351 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
4354 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4355 max_compressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
4356 independent_64b_blocks
= 0;
4357 independent_128b_blocks
= 1;
4359 independent_128b_blocks
= 0;
4361 if (iview
->image
->info
.samples
> 1) {
4362 if (iview
->image
->planes
[0].surface
.bpe
== 1)
4363 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
4364 else if (iview
->image
->planes
[0].surface
.bpe
== 2)
4365 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
4368 if (iview
->image
->usage
& (VK_IMAGE_USAGE_SAMPLED_BIT
|
4369 VK_IMAGE_USAGE_TRANSFER_SRC_BIT
|
4370 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
)) {
4371 /* If this DCC image is potentially going to be used in texture
4372 * fetches, we need some special settings.
4374 independent_64b_blocks
= 1;
4375 max_compressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
4377 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4378 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4379 * big as possible for better compression state.
4381 independent_64b_blocks
= 0;
4382 max_compressed_block_size
= max_uncompressed_block_size
;
4386 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
4387 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size
) |
4388 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
4389 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks
) |
4390 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks
);
4394 radv_initialise_color_surface(struct radv_device
*device
,
4395 struct radv_color_buffer_info
*cb
,
4396 struct radv_image_view
*iview
)
4398 const struct vk_format_description
*desc
;
4399 unsigned ntype
, format
, swap
, endian
;
4400 unsigned blend_clamp
= 0, blend_bypass
= 0;
4402 const struct radv_image_plane
*plane
= &iview
->image
->planes
[iview
->plane_id
];
4403 const struct radeon_surf
*surf
= &plane
->surface
;
4405 desc
= vk_format_description(iview
->vk_format
);
4407 memset(cb
, 0, sizeof(*cb
));
4409 /* Intensity is implemented as Red, so treat it that way. */
4410 cb
->cb_color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == VK_SWIZZLE_1
);
4412 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+ plane
->offset
;
4414 cb
->cb_color_base
= va
>> 8;
4416 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4417 struct gfx9_surf_meta_flags meta
;
4418 if (iview
->image
->dcc_offset
)
4419 meta
= surf
->u
.gfx9
.dcc
;
4421 meta
= surf
->u
.gfx9
.cmask
;
4423 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4424 cb
->cb_color_attrib3
|= S_028EE0_COLOR_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
4425 S_028EE0_FMASK_SW_MODE(surf
->u
.gfx9
.fmask
.swizzle_mode
) |
4426 S_028EE0_CMASK_PIPE_ALIGNED(surf
->u
.gfx9
.cmask
.pipe_aligned
) |
4427 S_028EE0_DCC_PIPE_ALIGNED(surf
->u
.gfx9
.dcc
.pipe_aligned
);
4429 cb
->cb_color_attrib
|= S_028C74_COLOR_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
4430 S_028C74_FMASK_SW_MODE(surf
->u
.gfx9
.fmask
.swizzle_mode
) |
4431 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
4432 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
4433 cb
->cb_mrt_epitch
= S_0287A0_EPITCH(surf
->u
.gfx9
.surf
.epitch
);
4436 cb
->cb_color_base
+= surf
->u
.gfx9
.surf_offset
>> 8;
4437 cb
->cb_color_base
|= surf
->tile_swizzle
;
4439 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[iview
->base_mip
];
4440 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
4442 cb
->cb_color_base
+= level_info
->offset
>> 8;
4443 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
4444 cb
->cb_color_base
|= surf
->tile_swizzle
;
4446 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
4447 slice_tile_max
= (level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1;
4448 tile_mode_index
= si_tile_mode_index(plane
, iview
->base_mip
, false);
4450 cb
->cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
4451 cb
->cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
4452 cb
->cb_color_cmask_slice
= surf
->u
.legacy
.cmask_slice_tile_max
;
4454 cb
->cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
4456 if (radv_image_has_fmask(iview
->image
)) {
4457 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
4458 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(surf
->u
.legacy
.fmask
.pitch_in_pixels
/ 8 - 1);
4459 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(surf
->u
.legacy
.fmask
.tiling_index
);
4460 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(surf
->u
.legacy
.fmask
.slice_tile_max
);
4462 /* This must be set for fast clear to work without FMASK. */
4463 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
4464 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
4465 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
4466 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
4470 /* CMASK variables */
4471 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
4472 va
+= iview
->image
->cmask_offset
;
4473 cb
->cb_color_cmask
= va
>> 8;
4475 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
4476 va
+= iview
->image
->dcc_offset
;
4478 if (radv_dcc_enabled(iview
->image
, iview
->base_mip
) &&
4479 device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4480 va
+= plane
->surface
.u
.legacy
.level
[iview
->base_mip
].dcc_offset
;
4482 unsigned dcc_tile_swizzle
= surf
->tile_swizzle
;
4483 dcc_tile_swizzle
&= (surf
->dcc_alignment
- 1) >> 8;
4485 cb
->cb_dcc_base
= va
>> 8;
4486 cb
->cb_dcc_base
|= dcc_tile_swizzle
;
4488 /* GFX10 field has the same base shift as the GFX6 field. */
4489 uint32_t max_slice
= radv_surface_max_layer_count(iview
) - 1;
4490 cb
->cb_color_view
= S_028C6C_SLICE_START(iview
->base_layer
) |
4491 S_028C6C_SLICE_MAX_GFX10(max_slice
);
4493 if (iview
->image
->info
.samples
> 1) {
4494 unsigned log_samples
= util_logbase2(iview
->image
->info
.samples
);
4496 cb
->cb_color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
4497 S_028C74_NUM_FRAGMENTS(log_samples
);
4500 if (radv_image_has_fmask(iview
->image
)) {
4501 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+ iview
->image
->fmask_offset
;
4502 cb
->cb_color_fmask
= va
>> 8;
4503 cb
->cb_color_fmask
|= surf
->fmask_tile_swizzle
;
4505 cb
->cb_color_fmask
= cb
->cb_color_base
;
4508 ntype
= radv_translate_color_numformat(iview
->vk_format
,
4510 vk_format_get_first_non_void_channel(iview
->vk_format
));
4511 format
= radv_translate_colorformat(iview
->vk_format
);
4512 if (format
== V_028C70_COLOR_INVALID
|| ntype
== ~0u)
4513 radv_finishme("Illegal color\n");
4514 swap
= radv_translate_colorswap(iview
->vk_format
, false);
4515 endian
= radv_colorformat_endian_swap(format
);
4517 /* blend clamp should be set for all NORM/SRGB types */
4518 if (ntype
== V_028C70_NUMBER_UNORM
||
4519 ntype
== V_028C70_NUMBER_SNORM
||
4520 ntype
== V_028C70_NUMBER_SRGB
)
4523 /* set blend bypass according to docs if SINT/UINT or
4524 8/24 COLOR variants */
4525 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
4526 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
4527 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
4532 if ((ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) &&
4533 (format
== V_028C70_COLOR_8
||
4534 format
== V_028C70_COLOR_8_8
||
4535 format
== V_028C70_COLOR_8_8_8_8
))
4536 ->color_is_int8
= true;
4538 cb
->cb_color_info
= S_028C70_FORMAT(format
) |
4539 S_028C70_COMP_SWAP(swap
) |
4540 S_028C70_BLEND_CLAMP(blend_clamp
) |
4541 S_028C70_BLEND_BYPASS(blend_bypass
) |
4542 S_028C70_SIMPLE_FLOAT(1) |
4543 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
4544 ntype
!= V_028C70_NUMBER_SNORM
&&
4545 ntype
!= V_028C70_NUMBER_SRGB
&&
4546 format
!= V_028C70_COLOR_8_24
&&
4547 format
!= V_028C70_COLOR_24_8
) |
4548 S_028C70_NUMBER_TYPE(ntype
) |
4549 S_028C70_ENDIAN(endian
);
4550 if (radv_image_has_fmask(iview
->image
)) {
4551 cb
->cb_color_info
|= S_028C70_COMPRESSION(1);
4552 if (device
->physical_device
->rad_info
.chip_class
== GFX6
) {
4553 unsigned fmask_bankh
= util_logbase2(surf
->u
.legacy
.fmask
.bankh
);
4554 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
4557 if (radv_image_is_tc_compat_cmask(iview
->image
)) {
4558 /* Allow the texture block to read FMASK directly
4559 * without decompressing it. This bit must be cleared
4560 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
4561 * otherwise the operation doesn't happen.
4563 cb
->cb_color_info
|= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
4565 /* Set CMASK into a tiling format that allows the
4566 * texture block to read it.
4568 cb
->cb_color_info
|= S_028C70_CMASK_ADDR_TYPE(2);
4572 if (radv_image_has_cmask(iview
->image
) &&
4573 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_FAST_CLEARS
))
4574 cb
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
4576 if (radv_dcc_enabled(iview
->image
, iview
->base_mip
))
4577 cb
->cb_color_info
|= S_028C70_DCC_ENABLE(1);
4579 cb
->cb_dcc_control
= radv_init_dcc_control_reg(device
, iview
);
4581 /* This must be set for fast clear to work without FMASK. */
4582 if (!radv_image_has_fmask(iview
->image
) &&
4583 device
->physical_device
->rad_info
.chip_class
== GFX6
) {
4584 unsigned bankh
= util_logbase2(surf
->u
.legacy
.bankh
);
4585 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
4588 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4589 const struct vk_format_description
*format_desc
= vk_format_description(iview
->image
->vk_format
);
4591 unsigned mip0_depth
= iview
->image
->type
== VK_IMAGE_TYPE_3D
?
4592 (iview
->extent
.depth
- 1) : (iview
->image
->info
.array_size
- 1);
4593 unsigned width
= iview
->extent
.width
/ (iview
->plane_id
? format_desc
->width_divisor
: 1);
4594 unsigned height
= iview
->extent
.height
/ (iview
->plane_id
? format_desc
->height_divisor
: 1);
4596 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4597 cb
->cb_color_view
|= S_028C6C_MIP_LEVEL_GFX10(iview
->base_mip
);
4599 cb
->cb_color_attrib3
|= S_028EE0_MIP0_DEPTH(mip0_depth
) |
4600 S_028EE0_RESOURCE_TYPE(surf
->u
.gfx9
.resource_type
) |
4601 S_028EE0_RESOURCE_LEVEL(1);
4603 cb
->cb_color_view
|= S_028C6C_MIP_LEVEL_GFX9(iview
->base_mip
);
4604 cb
->cb_color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
4605 S_028C74_RESOURCE_TYPE(surf
->u
.gfx9
.resource_type
);
4608 cb
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(width
- 1) |
4609 S_028C68_MIP0_HEIGHT(height
- 1) |
4610 S_028C68_MAX_MIP(iview
->image
->info
.levels
- 1);
4615 radv_calc_decompress_on_z_planes(struct radv_device
*device
,
4616 struct radv_image_view
*iview
)
4618 unsigned max_zplanes
= 0;
4620 assert(radv_image_is_tc_compat_htile(iview
->image
));
4622 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4623 /* Default value for 32-bit depth surfaces. */
4626 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
&&
4627 iview
->image
->info
.samples
> 1)
4630 max_zplanes
= max_zplanes
+ 1;
4632 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
) {
4633 /* Do not enable Z plane compression for 16-bit depth
4634 * surfaces because isn't supported on GFX8. Only
4635 * 32-bit depth surfaces are supported by the hardware.
4636 * This allows to maintain shader compatibility and to
4637 * reduce the number of depth decompressions.
4641 if (iview
->image
->info
.samples
<= 1)
4643 else if (iview
->image
->info
.samples
<= 4)
4654 radv_initialise_ds_surface(struct radv_device
*device
,
4655 struct radv_ds_buffer_info
*ds
,
4656 struct radv_image_view
*iview
)
4658 unsigned level
= iview
->base_mip
;
4659 unsigned format
, stencil_format
;
4660 uint64_t va
, s_offs
, z_offs
;
4661 bool stencil_only
= false;
4662 const struct radv_image_plane
*plane
= &iview
->image
->planes
[0];
4663 const struct radeon_surf
*surf
= &plane
->surface
;
4665 assert(vk_format_get_plane_count(iview
->image
->vk_format
) == 1);
4667 memset(ds
, 0, sizeof(*ds
));
4668 switch (iview
->image
->vk_format
) {
4669 case VK_FORMAT_D24_UNORM_S8_UINT
:
4670 case VK_FORMAT_X8_D24_UNORM_PACK32
:
4671 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4672 ds
->offset_scale
= 2.0f
;
4674 case VK_FORMAT_D16_UNORM
:
4675 case VK_FORMAT_D16_UNORM_S8_UINT
:
4676 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4677 ds
->offset_scale
= 4.0f
;
4679 case VK_FORMAT_D32_SFLOAT
:
4680 case VK_FORMAT_D32_SFLOAT_S8_UINT
:
4681 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4682 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4683 ds
->offset_scale
= 1.0f
;
4685 case VK_FORMAT_S8_UINT
:
4686 stencil_only
= true;
4692 format
= radv_translate_dbformat(iview
->image
->vk_format
);
4693 stencil_format
= surf
->has_stencil
?
4694 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
4696 uint32_t max_slice
= radv_surface_max_layer_count(iview
) - 1;
4697 ds
->db_depth_view
= S_028008_SLICE_START(iview
->base_layer
) |
4698 S_028008_SLICE_MAX(max_slice
);
4699 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4700 ds
->db_depth_view
|= S_028008_SLICE_START_HI(iview
->base_layer
>> 11) |
4701 S_028008_SLICE_MAX_HI(max_slice
>> 11);
4704 ds
->db_htile_data_base
= 0;
4705 ds
->db_htile_surface
= 0;
4707 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
4708 s_offs
= z_offs
= va
;
4710 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4711 assert(surf
->u
.gfx9
.surf_offset
== 0);
4712 s_offs
+= surf
->u
.gfx9
.stencil_offset
;
4714 ds
->db_z_info
= S_028038_FORMAT(format
) |
4715 S_028038_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
)) |
4716 S_028038_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
4717 S_028038_MAXMIP(iview
->image
->info
.levels
- 1) |
4718 S_028038_ZRANGE_PRECISION(1);
4719 ds
->db_stencil_info
= S_02803C_FORMAT(stencil_format
) |
4720 S_02803C_SW_MODE(surf
->u
.gfx9
.stencil
.swizzle_mode
);
4722 if (device
->physical_device
->rad_info
.chip_class
== GFX9
) {
4723 ds
->db_z_info2
= S_028068_EPITCH(surf
->u
.gfx9
.surf
.epitch
);
4724 ds
->db_stencil_info2
= S_02806C_EPITCH(surf
->u
.gfx9
.stencil
.epitch
);
4727 ds
->db_depth_view
|= S_028008_MIPID(level
);
4728 ds
->db_depth_size
= S_02801C_X_MAX(iview
->image
->info
.width
- 1) |
4729 S_02801C_Y_MAX(iview
->image
->info
.height
- 1);
4731 if (radv_htile_enabled(iview
->image
, level
)) {
4732 ds
->db_z_info
|= S_028038_TILE_SURFACE_ENABLE(1);
4734 if (radv_image_is_tc_compat_htile(iview
->image
)) {
4735 unsigned max_zplanes
=
4736 radv_calc_decompress_on_z_planes(device
, iview
);
4738 ds
->db_z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
);
4740 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4741 ds
->db_z_info
|= S_028040_ITERATE_FLUSH(1);
4742 ds
->db_stencil_info
|= S_028044_ITERATE_FLUSH(1);
4744 ds
->db_z_info
|= S_028038_ITERATE_FLUSH(1);
4745 ds
->db_stencil_info
|= S_02803C_ITERATE_FLUSH(1);
4749 if (!surf
->has_stencil
)
4750 /* Use all of the htile_buffer for depth if there's no stencil. */
4751 ds
->db_stencil_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
4752 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
4753 iview
->image
->htile_offset
;
4754 ds
->db_htile_data_base
= va
>> 8;
4755 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1) |
4756 S_028ABC_PIPE_ALIGNED(surf
->u
.gfx9
.htile
.pipe_aligned
);
4758 if (device
->physical_device
->rad_info
.chip_class
== GFX9
) {
4759 ds
->db_htile_surface
|= S_028ABC_RB_ALIGNED(surf
->u
.gfx9
.htile
.rb_aligned
);
4763 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[level
];
4766 level_info
= &surf
->u
.legacy
.stencil_level
[level
];
4768 z_offs
+= surf
->u
.legacy
.level
[level
].offset
;
4769 s_offs
+= surf
->u
.legacy
.stencil_level
[level
].offset
;
4771 ds
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview
->image
));
4772 ds
->db_z_info
= S_028040_FORMAT(format
) | S_028040_ZRANGE_PRECISION(1);
4773 ds
->db_stencil_info
= S_028044_FORMAT(stencil_format
);
4775 if (iview
->image
->info
.samples
> 1)
4776 ds
->db_z_info
|= S_028040_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
));
4778 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4779 struct radeon_info
*info
= &device
->physical_device
->rad_info
;
4780 unsigned tiling_index
= surf
->u
.legacy
.tiling_index
[level
];
4781 unsigned stencil_index
= surf
->u
.legacy
.stencil_tiling_index
[level
];
4782 unsigned macro_index
= surf
->u
.legacy
.macro_tile_index
;
4783 unsigned tile_mode
= info
->si_tile_mode_array
[tiling_index
];
4784 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
4785 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
4788 tile_mode
= stencil_tile_mode
;
4790 ds
->db_depth_info
|=
4791 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
4792 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
4793 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
4794 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
4795 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
4796 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
4797 ds
->db_z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
4798 ds
->db_stencil_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
4800 unsigned tile_mode_index
= si_tile_mode_index(&iview
->image
->planes
[0], level
, false);
4801 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
4802 tile_mode_index
= si_tile_mode_index(&iview
->image
->planes
[0], level
, true);
4803 ds
->db_stencil_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
4805 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
4808 ds
->db_depth_size
= S_028058_PITCH_TILE_MAX((level_info
->nblk_x
/ 8) - 1) |
4809 S_028058_HEIGHT_TILE_MAX((level_info
->nblk_y
/ 8) - 1);
4810 ds
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1);
4812 if (radv_htile_enabled(iview
->image
, level
)) {
4813 ds
->db_z_info
|= S_028040_TILE_SURFACE_ENABLE(1);
4815 if (!surf
->has_stencil
&&
4816 !radv_image_is_tc_compat_htile(iview
->image
))
4817 /* Use all of the htile_buffer for depth if there's no stencil. */
4818 ds
->db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
4820 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
4821 iview
->image
->htile_offset
;
4822 ds
->db_htile_data_base
= va
>> 8;
4823 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
4825 if (radv_image_is_tc_compat_htile(iview
->image
)) {
4826 unsigned max_zplanes
=
4827 radv_calc_decompress_on_z_planes(device
, iview
);
4829 ds
->db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
4830 ds
->db_z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes
);
4835 ds
->db_z_read_base
= ds
->db_z_write_base
= z_offs
>> 8;
4836 ds
->db_stencil_read_base
= ds
->db_stencil_write_base
= s_offs
>> 8;
4839 VkResult
radv_CreateFramebuffer(
4841 const VkFramebufferCreateInfo
* pCreateInfo
,
4842 const VkAllocationCallbacks
* pAllocator
,
4843 VkFramebuffer
* pFramebuffer
)
4845 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4846 struct radv_framebuffer
*framebuffer
;
4847 const VkFramebufferAttachmentsCreateInfoKHR
*imageless_create_info
=
4848 vk_find_struct_const(pCreateInfo
->pNext
,
4849 FRAMEBUFFER_ATTACHMENTS_CREATE_INFO_KHR
);
4851 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
);
4853 size_t size
= sizeof(*framebuffer
);
4854 if (!imageless_create_info
)
4855 size
+= sizeof(struct radv_image_view
*) * pCreateInfo
->attachmentCount
;
4856 framebuffer
= vk_alloc2(&device
->alloc
, pAllocator
, size
, 8,
4857 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4858 if (framebuffer
== NULL
)
4859 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4861 framebuffer
->attachment_count
= pCreateInfo
->attachmentCount
;
4862 framebuffer
->width
= pCreateInfo
->width
;
4863 framebuffer
->height
= pCreateInfo
->height
;
4864 framebuffer
->layers
= pCreateInfo
->layers
;
4865 if (imageless_create_info
) {
4866 for (unsigned i
= 0; i
< imageless_create_info
->attachmentImageInfoCount
; ++i
) {
4867 const VkFramebufferAttachmentImageInfoKHR
*attachment
=
4868 imageless_create_info
->pAttachmentImageInfos
+ i
;
4869 framebuffer
->width
= MIN2(framebuffer
->width
, attachment
->width
);
4870 framebuffer
->height
= MIN2(framebuffer
->height
, attachment
->height
);
4871 framebuffer
->layers
= MIN2(framebuffer
->layers
, attachment
->layerCount
);
4874 for (uint32_t i
= 0; i
< pCreateInfo
->attachmentCount
; i
++) {
4875 VkImageView _iview
= pCreateInfo
->pAttachments
[i
];
4876 struct radv_image_view
*iview
= radv_image_view_from_handle(_iview
);
4877 framebuffer
->attachments
[i
] = iview
;
4878 framebuffer
->width
= MIN2(framebuffer
->width
, iview
->extent
.width
);
4879 framebuffer
->height
= MIN2(framebuffer
->height
, iview
->extent
.height
);
4880 framebuffer
->layers
= MIN2(framebuffer
->layers
, radv_surface_max_layer_count(iview
));
4884 *pFramebuffer
= radv_framebuffer_to_handle(framebuffer
);
4888 void radv_DestroyFramebuffer(
4891 const VkAllocationCallbacks
* pAllocator
)
4893 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4894 RADV_FROM_HANDLE(radv_framebuffer
, fb
, _fb
);
4898 vk_free2(&device
->alloc
, pAllocator
, fb
);
4901 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode
)
4903 switch (address_mode
) {
4904 case VK_SAMPLER_ADDRESS_MODE_REPEAT
:
4905 return V_008F30_SQ_TEX_WRAP
;
4906 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT
:
4907 return V_008F30_SQ_TEX_MIRROR
;
4908 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE
:
4909 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
4910 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER
:
4911 return V_008F30_SQ_TEX_CLAMP_BORDER
;
4912 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE
:
4913 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
4915 unreachable("illegal tex wrap mode");
4921 radv_tex_compare(VkCompareOp op
)
4924 case VK_COMPARE_OP_NEVER
:
4925 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
4926 case VK_COMPARE_OP_LESS
:
4927 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
4928 case VK_COMPARE_OP_EQUAL
:
4929 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
4930 case VK_COMPARE_OP_LESS_OR_EQUAL
:
4931 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
4932 case VK_COMPARE_OP_GREATER
:
4933 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
4934 case VK_COMPARE_OP_NOT_EQUAL
:
4935 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
4936 case VK_COMPARE_OP_GREATER_OR_EQUAL
:
4937 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
4938 case VK_COMPARE_OP_ALWAYS
:
4939 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
4941 unreachable("illegal compare mode");
4947 radv_tex_filter(VkFilter filter
, unsigned max_ansio
)
4950 case VK_FILTER_NEAREST
:
4951 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
:
4952 V_008F38_SQ_TEX_XY_FILTER_POINT
);
4953 case VK_FILTER_LINEAR
:
4954 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
:
4955 V_008F38_SQ_TEX_XY_FILTER_BILINEAR
);
4956 case VK_FILTER_CUBIC_IMG
:
4958 fprintf(stderr
, "illegal texture filter");
4964 radv_tex_mipfilter(VkSamplerMipmapMode mode
)
4967 case VK_SAMPLER_MIPMAP_MODE_NEAREST
:
4968 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
4969 case VK_SAMPLER_MIPMAP_MODE_LINEAR
:
4970 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
4972 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
4977 radv_tex_bordercolor(VkBorderColor bcolor
)
4980 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK
:
4981 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK
:
4982 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
4983 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK
:
4984 case VK_BORDER_COLOR_INT_OPAQUE_BLACK
:
4985 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK
;
4986 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE
:
4987 case VK_BORDER_COLOR_INT_OPAQUE_WHITE
:
4988 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE
;
4996 radv_tex_aniso_filter(unsigned filter
)
5010 radv_tex_filter_mode(VkSamplerReductionModeEXT mode
)
5013 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT
:
5014 return V_008F30_SQ_IMG_FILTER_MODE_BLEND
;
5015 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT
:
5016 return V_008F30_SQ_IMG_FILTER_MODE_MIN
;
5017 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT
:
5018 return V_008F30_SQ_IMG_FILTER_MODE_MAX
;
5026 radv_get_max_anisotropy(struct radv_device
*device
,
5027 const VkSamplerCreateInfo
*pCreateInfo
)
5029 if (device
->force_aniso
>= 0)
5030 return device
->force_aniso
;
5032 if (pCreateInfo
->anisotropyEnable
&&
5033 pCreateInfo
->maxAnisotropy
> 1.0f
)
5034 return (uint32_t)pCreateInfo
->maxAnisotropy
;
5040 radv_init_sampler(struct radv_device
*device
,
5041 struct radv_sampler
*sampler
,
5042 const VkSamplerCreateInfo
*pCreateInfo
)
5044 uint32_t max_aniso
= radv_get_max_anisotropy(device
, pCreateInfo
);
5045 uint32_t max_aniso_ratio
= radv_tex_aniso_filter(max_aniso
);
5046 bool compat_mode
= device
->physical_device
->rad_info
.chip_class
== GFX8
||
5047 device
->physical_device
->rad_info
.chip_class
== GFX9
;
5048 unsigned filter_mode
= V_008F30_SQ_IMG_FILTER_MODE_BLEND
;
5050 const struct VkSamplerReductionModeCreateInfoEXT
*sampler_reduction
=
5051 vk_find_struct_const(pCreateInfo
->pNext
,
5052 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT
);
5053 if (sampler_reduction
)
5054 filter_mode
= radv_tex_filter_mode(sampler_reduction
->reductionMode
);
5056 sampler
->state
[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo
->addressModeU
)) |
5057 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo
->addressModeV
)) |
5058 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo
->addressModeW
)) |
5059 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
5060 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo
->compareOp
)) |
5061 S_008F30_FORCE_UNNORMALIZED(pCreateInfo
->unnormalizedCoordinates
? 1 : 0) |
5062 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
5063 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
5064 S_008F30_DISABLE_CUBE_WRAP(0) |
5065 S_008F30_COMPAT_MODE(compat_mode
) |
5066 S_008F30_FILTER_MODE(filter_mode
));
5067 sampler
->state
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo
->minLod
, 0, 15), 8)) |
5068 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo
->maxLod
, 0, 15), 8)) |
5069 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
5070 sampler
->state
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo
->mipLodBias
, -16, 16), 8)) |
5071 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo
->magFilter
, max_aniso
)) |
5072 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo
->minFilter
, max_aniso
)) |
5073 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo
->mipmapMode
)) |
5074 S_008F38_MIP_POINT_PRECLAMP(0));
5075 sampler
->state
[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
5076 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo
->borderColor
)));
5078 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
5079 sampler
->state
[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
5081 sampler
->state
[2] |=
5082 S_008F38_DISABLE_LSB_CEIL(device
->physical_device
->rad_info
.chip_class
<= GFX8
) |
5083 S_008F38_FILTER_PREC_FIX(1) |
5084 S_008F38_ANISO_OVERRIDE_GFX6(device
->physical_device
->rad_info
.chip_class
>= GFX8
);
5088 VkResult
radv_CreateSampler(
5090 const VkSamplerCreateInfo
* pCreateInfo
,
5091 const VkAllocationCallbacks
* pAllocator
,
5092 VkSampler
* pSampler
)
5094 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5095 struct radv_sampler
*sampler
;
5097 const struct VkSamplerYcbcrConversionInfo
*ycbcr_conversion
=
5098 vk_find_struct_const(pCreateInfo
->pNext
,
5099 SAMPLER_YCBCR_CONVERSION_INFO
);
5101 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO
);
5103 sampler
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*sampler
), 8,
5104 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5106 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5108 radv_init_sampler(device
, sampler
, pCreateInfo
);
5110 sampler
->ycbcr_sampler
= ycbcr_conversion
? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion
->conversion
): NULL
;
5111 *pSampler
= radv_sampler_to_handle(sampler
);
5116 void radv_DestroySampler(
5119 const VkAllocationCallbacks
* pAllocator
)
5121 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5122 RADV_FROM_HANDLE(radv_sampler
, sampler
, _sampler
);
5126 vk_free2(&device
->alloc
, pAllocator
, sampler
);
5129 /* vk_icd.h does not declare this function, so we declare it here to
5130 * suppress Wmissing-prototypes.
5132 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5133 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
);
5135 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5136 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
)
5138 /* For the full details on loader interface versioning, see
5139 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
5140 * What follows is a condensed summary, to help you navigate the large and
5141 * confusing official doc.
5143 * - Loader interface v0 is incompatible with later versions. We don't
5146 * - In loader interface v1:
5147 * - The first ICD entrypoint called by the loader is
5148 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
5150 * - The ICD must statically expose no other Vulkan symbol unless it is
5151 * linked with -Bsymbolic.
5152 * - Each dispatchable Vulkan handle created by the ICD must be
5153 * a pointer to a struct whose first member is VK_LOADER_DATA. The
5154 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
5155 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
5156 * vkDestroySurfaceKHR(). The ICD must be capable of working with
5157 * such loader-managed surfaces.
5159 * - Loader interface v2 differs from v1 in:
5160 * - The first ICD entrypoint called by the loader is
5161 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
5162 * statically expose this entrypoint.
5164 * - Loader interface v3 differs from v2 in:
5165 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
5166 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
5167 * because the loader no longer does so.
5169 *pSupportedVersion
= MIN2(*pSupportedVersion
, 4u);
5173 VkResult
radv_GetMemoryFdKHR(VkDevice _device
,
5174 const VkMemoryGetFdInfoKHR
*pGetFdInfo
,
5177 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5178 RADV_FROM_HANDLE(radv_device_memory
, memory
, pGetFdInfo
->memory
);
5180 assert(pGetFdInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR
);
5182 /* At the moment, we support only the below handle types. */
5183 assert(pGetFdInfo
->handleType
==
5184 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT
||
5185 pGetFdInfo
->handleType
==
5186 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
5188 bool ret
= radv_get_memory_fd(device
, memory
, pFD
);
5190 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
5194 VkResult
radv_GetMemoryFdPropertiesKHR(VkDevice _device
,
5195 VkExternalMemoryHandleTypeFlagBits handleType
,
5197 VkMemoryFdPropertiesKHR
*pMemoryFdProperties
)
5199 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5201 switch (handleType
) {
5202 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
:
5203 pMemoryFdProperties
->memoryTypeBits
= (1 << RADV_MEM_TYPE_COUNT
) - 1;
5207 /* The valid usage section for this function says:
5209 * "handleType must not be one of the handle types defined as
5212 * So opaque handle types fall into the default "unsupported" case.
5214 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5218 static VkResult
radv_import_opaque_fd(struct radv_device
*device
,
5222 uint32_t syncobj_handle
= 0;
5223 int ret
= device
->ws
->import_syncobj(device
->ws
, fd
, &syncobj_handle
);
5225 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5228 device
->ws
->destroy_syncobj(device
->ws
, *syncobj
);
5230 *syncobj
= syncobj_handle
;
5236 static VkResult
radv_import_sync_fd(struct radv_device
*device
,
5240 /* If we create a syncobj we do it locally so that if we have an error, we don't
5241 * leave a syncobj in an undetermined state in the fence. */
5242 uint32_t syncobj_handle
= *syncobj
;
5243 if (!syncobj_handle
) {
5244 int ret
= device
->ws
->create_syncobj(device
->ws
, &syncobj_handle
);
5246 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5251 device
->ws
->signal_syncobj(device
->ws
, syncobj_handle
);
5253 int ret
= device
->ws
->import_syncobj_from_sync_file(device
->ws
, syncobj_handle
, fd
);
5255 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5258 *syncobj
= syncobj_handle
;
5265 VkResult
radv_ImportSemaphoreFdKHR(VkDevice _device
,
5266 const VkImportSemaphoreFdInfoKHR
*pImportSemaphoreFdInfo
)
5268 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5269 RADV_FROM_HANDLE(radv_semaphore
, sem
, pImportSemaphoreFdInfo
->semaphore
);
5270 uint32_t *syncobj_dst
= NULL
;
5272 if (pImportSemaphoreFdInfo
->flags
& VK_SEMAPHORE_IMPORT_TEMPORARY_BIT
) {
5273 syncobj_dst
= &sem
->temp_syncobj
;
5275 syncobj_dst
= &sem
->syncobj
;
5278 switch(pImportSemaphoreFdInfo
->handleType
) {
5279 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
:
5280 return radv_import_opaque_fd(device
, pImportSemaphoreFdInfo
->fd
, syncobj_dst
);
5281 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
:
5282 return radv_import_sync_fd(device
, pImportSemaphoreFdInfo
->fd
, syncobj_dst
);
5284 unreachable("Unhandled semaphore handle type");
5288 VkResult
radv_GetSemaphoreFdKHR(VkDevice _device
,
5289 const VkSemaphoreGetFdInfoKHR
*pGetFdInfo
,
5292 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5293 RADV_FROM_HANDLE(radv_semaphore
, sem
, pGetFdInfo
->semaphore
);
5295 uint32_t syncobj_handle
;
5297 if (sem
->temp_syncobj
)
5298 syncobj_handle
= sem
->temp_syncobj
;
5300 syncobj_handle
= sem
->syncobj
;
5302 switch(pGetFdInfo
->handleType
) {
5303 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
:
5304 ret
= device
->ws
->export_syncobj(device
->ws
, syncobj_handle
, pFd
);
5306 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
:
5307 ret
= device
->ws
->export_syncobj_to_sync_file(device
->ws
, syncobj_handle
, pFd
);
5309 if (sem
->temp_syncobj
) {
5310 close (sem
->temp_syncobj
);
5311 sem
->temp_syncobj
= 0;
5313 device
->ws
->reset_syncobj(device
->ws
, syncobj_handle
);
5318 unreachable("Unhandled semaphore handle type");
5322 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5326 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
5327 VkPhysicalDevice physicalDevice
,
5328 const VkPhysicalDeviceExternalSemaphoreInfo
*pExternalSemaphoreInfo
,
5329 VkExternalSemaphoreProperties
*pExternalSemaphoreProperties
)
5331 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
5333 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
5334 if (pdevice
->rad_info
.has_syncobj_wait_for_submit
&&
5335 (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
||
5336 pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
)) {
5337 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
;
5338 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
;
5339 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT
|
5340 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
5341 } else if (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
) {
5342 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
5343 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
5344 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT
|
5345 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
5347 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= 0;
5348 pExternalSemaphoreProperties
->compatibleHandleTypes
= 0;
5349 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= 0;
5353 VkResult
radv_ImportFenceFdKHR(VkDevice _device
,
5354 const VkImportFenceFdInfoKHR
*pImportFenceFdInfo
)
5356 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5357 RADV_FROM_HANDLE(radv_fence
, fence
, pImportFenceFdInfo
->fence
);
5358 uint32_t *syncobj_dst
= NULL
;
5361 if (pImportFenceFdInfo
->flags
& VK_FENCE_IMPORT_TEMPORARY_BIT
) {
5362 syncobj_dst
= &fence
->temp_syncobj
;
5364 syncobj_dst
= &fence
->syncobj
;
5367 switch(pImportFenceFdInfo
->handleType
) {
5368 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
:
5369 return radv_import_opaque_fd(device
, pImportFenceFdInfo
->fd
, syncobj_dst
);
5370 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
:
5371 return radv_import_sync_fd(device
, pImportFenceFdInfo
->fd
, syncobj_dst
);
5373 unreachable("Unhandled fence handle type");
5377 VkResult
radv_GetFenceFdKHR(VkDevice _device
,
5378 const VkFenceGetFdInfoKHR
*pGetFdInfo
,
5381 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5382 RADV_FROM_HANDLE(radv_fence
, fence
, pGetFdInfo
->fence
);
5384 uint32_t syncobj_handle
;
5386 if (fence
->temp_syncobj
)
5387 syncobj_handle
= fence
->temp_syncobj
;
5389 syncobj_handle
= fence
->syncobj
;
5391 switch(pGetFdInfo
->handleType
) {
5392 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
:
5393 ret
= device
->ws
->export_syncobj(device
->ws
, syncobj_handle
, pFd
);
5395 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
:
5396 ret
= device
->ws
->export_syncobj_to_sync_file(device
->ws
, syncobj_handle
, pFd
);
5398 if (fence
->temp_syncobj
) {
5399 close (fence
->temp_syncobj
);
5400 fence
->temp_syncobj
= 0;
5402 device
->ws
->reset_syncobj(device
->ws
, syncobj_handle
);
5407 unreachable("Unhandled fence handle type");
5411 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5415 void radv_GetPhysicalDeviceExternalFenceProperties(
5416 VkPhysicalDevice physicalDevice
,
5417 const VkPhysicalDeviceExternalFenceInfo
*pExternalFenceInfo
,
5418 VkExternalFenceProperties
*pExternalFenceProperties
)
5420 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
5422 if (pdevice
->rad_info
.has_syncobj_wait_for_submit
&&
5423 (pExternalFenceInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
||
5424 pExternalFenceInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
)) {
5425 pExternalFenceProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
;
5426 pExternalFenceProperties
->compatibleHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
;
5427 pExternalFenceProperties
->externalFenceFeatures
= VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT
|
5428 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
5430 pExternalFenceProperties
->exportFromImportedHandleTypes
= 0;
5431 pExternalFenceProperties
->compatibleHandleTypes
= 0;
5432 pExternalFenceProperties
->externalFenceFeatures
= 0;
5437 radv_CreateDebugReportCallbackEXT(VkInstance _instance
,
5438 const VkDebugReportCallbackCreateInfoEXT
* pCreateInfo
,
5439 const VkAllocationCallbacks
* pAllocator
,
5440 VkDebugReportCallbackEXT
* pCallback
)
5442 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
5443 return vk_create_debug_report_callback(&instance
->debug_report_callbacks
,
5444 pCreateInfo
, pAllocator
, &instance
->alloc
,
5449 radv_DestroyDebugReportCallbackEXT(VkInstance _instance
,
5450 VkDebugReportCallbackEXT _callback
,
5451 const VkAllocationCallbacks
* pAllocator
)
5453 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
5454 vk_destroy_debug_report_callback(&instance
->debug_report_callbacks
,
5455 _callback
, pAllocator
, &instance
->alloc
);
5459 radv_DebugReportMessageEXT(VkInstance _instance
,
5460 VkDebugReportFlagsEXT flags
,
5461 VkDebugReportObjectTypeEXT objectType
,
5464 int32_t messageCode
,
5465 const char* pLayerPrefix
,
5466 const char* pMessage
)
5468 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
5469 vk_debug_report(&instance
->debug_report_callbacks
, flags
, objectType
,
5470 object
, location
, messageCode
, pLayerPrefix
, pMessage
);
5474 radv_GetDeviceGroupPeerMemoryFeatures(
5477 uint32_t localDeviceIndex
,
5478 uint32_t remoteDeviceIndex
,
5479 VkPeerMemoryFeatureFlags
* pPeerMemoryFeatures
)
5481 assert(localDeviceIndex
== remoteDeviceIndex
);
5483 *pPeerMemoryFeatures
= VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT
|
5484 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT
|
5485 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT
|
5486 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT
;
5489 static const VkTimeDomainEXT radv_time_domains
[] = {
5490 VK_TIME_DOMAIN_DEVICE_EXT
,
5491 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT
,
5492 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT
,
5495 VkResult
radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5496 VkPhysicalDevice physicalDevice
,
5497 uint32_t *pTimeDomainCount
,
5498 VkTimeDomainEXT
*pTimeDomains
)
5501 VK_OUTARRAY_MAKE(out
, pTimeDomains
, pTimeDomainCount
);
5503 for (d
= 0; d
< ARRAY_SIZE(radv_time_domains
); d
++) {
5504 vk_outarray_append(&out
, i
) {
5505 *i
= radv_time_domains
[d
];
5509 return vk_outarray_status(&out
);
5513 radv_clock_gettime(clockid_t clock_id
)
5515 struct timespec current
;
5518 ret
= clock_gettime(clock_id
, ¤t
);
5519 if (ret
< 0 && clock_id
== CLOCK_MONOTONIC_RAW
)
5520 ret
= clock_gettime(CLOCK_MONOTONIC
, ¤t
);
5524 return (uint64_t) current
.tv_sec
* 1000000000ULL + current
.tv_nsec
;
5527 VkResult
radv_GetCalibratedTimestampsEXT(
5529 uint32_t timestampCount
,
5530 const VkCalibratedTimestampInfoEXT
*pTimestampInfos
,
5531 uint64_t *pTimestamps
,
5532 uint64_t *pMaxDeviation
)
5534 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5535 uint32_t clock_crystal_freq
= device
->physical_device
->rad_info
.clock_crystal_freq
;
5537 uint64_t begin
, end
;
5538 uint64_t max_clock_period
= 0;
5540 begin
= radv_clock_gettime(CLOCK_MONOTONIC_RAW
);
5542 for (d
= 0; d
< timestampCount
; d
++) {
5543 switch (pTimestampInfos
[d
].timeDomain
) {
5544 case VK_TIME_DOMAIN_DEVICE_EXT
:
5545 pTimestamps
[d
] = device
->ws
->query_value(device
->ws
,
5547 uint64_t device_period
= DIV_ROUND_UP(1000000, clock_crystal_freq
);
5548 max_clock_period
= MAX2(max_clock_period
, device_period
);
5550 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT
:
5551 pTimestamps
[d
] = radv_clock_gettime(CLOCK_MONOTONIC
);
5552 max_clock_period
= MAX2(max_clock_period
, 1);
5555 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT
:
5556 pTimestamps
[d
] = begin
;
5564 end
= radv_clock_gettime(CLOCK_MONOTONIC_RAW
);
5567 * The maximum deviation is the sum of the interval over which we
5568 * perform the sampling and the maximum period of any sampled
5569 * clock. That's because the maximum skew between any two sampled
5570 * clock edges is when the sampled clock with the largest period is
5571 * sampled at the end of that period but right at the beginning of the
5572 * sampling interval and some other clock is sampled right at the
5573 * begining of its sampling period and right at the end of the
5574 * sampling interval. Let's assume the GPU has the longest clock
5575 * period and that the application is sampling GPU and monotonic:
5578 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5579 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5583 * GPU -----_____-----_____-----_____-----_____
5586 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5587 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5589 * Interval <----------------->
5590 * Deviation <-------------------------->
5594 * m = read(monotonic) 2
5597 * We round the sample interval up by one tick to cover sampling error
5598 * in the interval clock
5601 uint64_t sample_interval
= end
- begin
+ 1;
5603 *pMaxDeviation
= sample_interval
+ max_clock_period
;
5608 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
5609 VkPhysicalDevice physicalDevice
,
5610 VkSampleCountFlagBits samples
,
5611 VkMultisamplePropertiesEXT
* pMultisampleProperties
)
5613 if (samples
& (VK_SAMPLE_COUNT_2_BIT
|
5614 VK_SAMPLE_COUNT_4_BIT
|
5615 VK_SAMPLE_COUNT_8_BIT
)) {
5616 pMultisampleProperties
->maxSampleLocationGridSize
= (VkExtent2D
){ 2, 2 };
5618 pMultisampleProperties
->maxSampleLocationGridSize
= (VkExtent2D
){ 0, 0 };