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radv: Allow triggering thread traces by file.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "dirent.h"
29 #include <errno.h>
30 #include <fcntl.h>
31 #include <linux/audit.h>
32 #include <linux/bpf.h>
33 #include <linux/filter.h>
34 #include <linux/seccomp.h>
35 #include <linux/unistd.h>
36 #include <stdatomic.h>
37 #include <stdbool.h>
38 #include <stddef.h>
39 #include <stdio.h>
40 #include <string.h>
41 #include <sys/prctl.h>
42 #include <sys/wait.h>
43 #include <unistd.h>
44 #include <fcntl.h>
45
46 #include "radv_debug.h"
47 #include "radv_private.h"
48 #include "radv_shader.h"
49 #include "radv_cs.h"
50 #include "util/disk_cache.h"
51 #include "vk_util.h"
52 #include <xf86drm.h>
53 #include <amdgpu.h>
54 #include "drm-uapi/amdgpu_drm.h"
55 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
56 #include "winsys/null/radv_null_winsys_public.h"
57 #include "ac_llvm_util.h"
58 #include "vk_format.h"
59 #include "sid.h"
60 #include "git_sha1.h"
61 #include "util/build_id.h"
62 #include "util/debug.h"
63 #include "util/mesa-sha1.h"
64 #include "util/timespec.h"
65 #include "util/u_atomic.h"
66 #include "compiler/glsl_types.h"
67 #include "util/driconf.h"
68
69 static struct radv_timeline_point *
70 radv_timeline_find_point_at_least_locked(struct radv_device *device,
71 struct radv_timeline *timeline,
72 uint64_t p);
73
74 static struct radv_timeline_point *
75 radv_timeline_add_point_locked(struct radv_device *device,
76 struct radv_timeline *timeline,
77 uint64_t p);
78
79 static void
80 radv_timeline_trigger_waiters_locked(struct radv_timeline *timeline,
81 struct list_head *processing_list);
82
83 static
84 void radv_destroy_semaphore_part(struct radv_device *device,
85 struct radv_semaphore_part *part);
86
87 static VkResult
88 radv_create_pthread_cond(pthread_cond_t *cond);
89
90 uint64_t radv_get_current_time(void)
91 {
92 struct timespec tv;
93 clock_gettime(CLOCK_MONOTONIC, &tv);
94 return tv.tv_nsec + tv.tv_sec*1000000000ull;
95 }
96
97 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
98 {
99 uint64_t current_time = radv_get_current_time();
100
101 timeout = MIN2(UINT64_MAX - current_time, timeout);
102
103 return current_time + timeout;
104 }
105
106 static int
107 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
108 {
109 struct mesa_sha1 ctx;
110 unsigned char sha1[20];
111 unsigned ptr_size = sizeof(void*);
112
113 memset(uuid, 0, VK_UUID_SIZE);
114 _mesa_sha1_init(&ctx);
115
116 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
117 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
118 return -1;
119
120 _mesa_sha1_update(&ctx, &family, sizeof(family));
121 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
122 _mesa_sha1_final(&ctx, sha1);
123
124 memcpy(uuid, sha1, VK_UUID_SIZE);
125 return 0;
126 }
127
128 static void
129 radv_get_driver_uuid(void *uuid)
130 {
131 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
132 }
133
134 static void
135 radv_get_device_uuid(struct radeon_info *info, void *uuid)
136 {
137 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
138 }
139
140 static uint64_t
141 radv_get_visible_vram_size(struct radv_physical_device *device)
142 {
143 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
144 }
145
146 static uint64_t
147 radv_get_vram_size(struct radv_physical_device *device)
148 {
149 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
150 }
151
152 static void
153 radv_physical_device_init_mem_types(struct radv_physical_device *device)
154 {
155 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
156 uint64_t vram_size = radv_get_vram_size(device);
157 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
158 device->memory_properties.memoryHeapCount = 0;
159 if (vram_size > 0) {
160 vram_index = device->memory_properties.memoryHeapCount++;
161 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
162 .size = vram_size,
163 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
164 };
165 }
166
167 if (device->rad_info.gart_size > 0) {
168 gart_index = device->memory_properties.memoryHeapCount++;
169 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
170 .size = device->rad_info.gart_size,
171 .flags = 0,
172 };
173 }
174
175 if (visible_vram_size) {
176 visible_vram_index = device->memory_properties.memoryHeapCount++;
177 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
178 .size = visible_vram_size,
179 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
180 };
181 }
182
183 unsigned type_count = 0;
184
185 if (vram_index >= 0 || visible_vram_index >= 0) {
186 device->memory_domains[type_count] = RADEON_DOMAIN_VRAM;
187 device->memory_flags[type_count] = RADEON_FLAG_NO_CPU_ACCESS;
188 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
189 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
190 .heapIndex = vram_index >= 0 ? vram_index : visible_vram_index,
191 };
192 }
193
194 if (gart_index >= 0) {
195 device->memory_domains[type_count] = RADEON_DOMAIN_GTT;
196 device->memory_flags[type_count] = RADEON_FLAG_GTT_WC | RADEON_FLAG_CPU_ACCESS;
197 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
198 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
199 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
200 .heapIndex = gart_index,
201 };
202 }
203 if (visible_vram_index >= 0) {
204 device->memory_domains[type_count] = RADEON_DOMAIN_VRAM;
205 device->memory_flags[type_count] = RADEON_FLAG_CPU_ACCESS;
206 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
207 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
208 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
209 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
210 .heapIndex = visible_vram_index,
211 };
212 }
213
214 if (gart_index >= 0) {
215 device->memory_domains[type_count] = RADEON_DOMAIN_GTT;
216 device->memory_flags[type_count] = RADEON_FLAG_CPU_ACCESS;
217 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
218 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
219 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
220 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
221 .heapIndex = gart_index,
222 };
223 }
224 device->memory_properties.memoryTypeCount = type_count;
225
226 if (device->rad_info.has_l2_uncached) {
227 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
228 VkMemoryType mem_type = device->memory_properties.memoryTypes[i];
229
230 if ((mem_type.propertyFlags & (VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
231 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT)) ||
232 mem_type.propertyFlags == VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT) {
233
234 VkMemoryPropertyFlags property_flags = mem_type.propertyFlags |
235 VK_MEMORY_PROPERTY_DEVICE_COHERENT_BIT_AMD |
236 VK_MEMORY_PROPERTY_DEVICE_UNCACHED_BIT_AMD;
237
238 device->memory_domains[type_count] = device->memory_domains[i];
239 device->memory_flags[type_count] = device->memory_flags[i] | RADEON_FLAG_VA_UNCACHED;
240 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
241 .propertyFlags = property_flags,
242 .heapIndex = mem_type.heapIndex,
243 };
244 }
245 }
246 device->memory_properties.memoryTypeCount = type_count;
247 }
248 }
249
250 static const char *
251 radv_get_compiler_string(struct radv_physical_device *pdevice)
252 {
253 if (!pdevice->use_llvm) {
254 /* Some games like SotTR apply shader workarounds if the LLVM
255 * version is too old or if the LLVM version string is
256 * missing. This gives 2-5% performance with SotTR and ACO.
257 */
258 if (driQueryOptionb(&pdevice->instance->dri_options,
259 "radv_report_llvm9_version_string")) {
260 return "ACO/LLVM 9.0.1";
261 }
262
263 return "ACO";
264 }
265
266 return "LLVM " MESA_LLVM_VERSION_STRING;
267 }
268
269 static VkResult
270 radv_physical_device_try_create(struct radv_instance *instance,
271 drmDevicePtr drm_device,
272 struct radv_physical_device **device_out)
273 {
274 VkResult result;
275 int fd = -1;
276 int master_fd = -1;
277
278 if (drm_device) {
279 const char *path = drm_device->nodes[DRM_NODE_RENDER];
280 drmVersionPtr version;
281
282 fd = open(path, O_RDWR | O_CLOEXEC);
283 if (fd < 0) {
284 if (instance->debug_flags & RADV_DEBUG_STARTUP)
285 radv_logi("Could not open device '%s'", path);
286
287 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
288 }
289
290 version = drmGetVersion(fd);
291 if (!version) {
292 close(fd);
293
294 if (instance->debug_flags & RADV_DEBUG_STARTUP)
295 radv_logi("Could not get the kernel driver version for device '%s'", path);
296
297 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
298 "failed to get version %s: %m", path);
299 }
300
301 if (strcmp(version->name, "amdgpu")) {
302 drmFreeVersion(version);
303 close(fd);
304
305 if (instance->debug_flags & RADV_DEBUG_STARTUP)
306 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
307
308 return VK_ERROR_INCOMPATIBLE_DRIVER;
309 }
310 drmFreeVersion(version);
311
312 if (instance->debug_flags & RADV_DEBUG_STARTUP)
313 radv_logi("Found compatible device '%s'.", path);
314 }
315
316 struct radv_physical_device *device =
317 vk_zalloc2(&instance->alloc, NULL, sizeof(*device), 8,
318 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
319 if (!device) {
320 result = vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
321 goto fail_fd;
322 }
323
324 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
325 device->instance = instance;
326
327 if (drm_device) {
328 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
329 instance->perftest_flags);
330 } else {
331 device->ws = radv_null_winsys_create();
332 }
333
334 if (!device->ws) {
335 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
336 "failed to initialize winsys");
337 goto fail_alloc;
338 }
339
340 if (drm_device && instance->enabled_extensions.KHR_display) {
341 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
342 if (master_fd >= 0) {
343 uint32_t accel_working = 0;
344 struct drm_amdgpu_info request = {
345 .return_pointer = (uintptr_t)&accel_working,
346 .return_size = sizeof(accel_working),
347 .query = AMDGPU_INFO_ACCEL_WORKING
348 };
349
350 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
351 close(master_fd);
352 master_fd = -1;
353 }
354 }
355 }
356
357 device->master_fd = master_fd;
358 device->local_fd = fd;
359 device->ws->query_info(device->ws, &device->rad_info);
360
361 device->use_llvm = instance->debug_flags & RADV_DEBUG_LLVM;
362
363 snprintf(device->name, sizeof(device->name),
364 "AMD RADV %s (%s)",
365 device->rad_info.name, radv_get_compiler_string(device));
366
367 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
368 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
369 "cannot generate UUID");
370 goto fail_wsi;
371 }
372
373 /* These flags affect shader compilation. */
374 uint64_t shader_env_flags = (device->use_llvm ? 0 : 0x2);
375
376 /* The gpu id is already embedded in the uuid so we just pass "radv"
377 * when creating the cache.
378 */
379 char buf[VK_UUID_SIZE * 2 + 1];
380 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
381 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
382
383 if (device->rad_info.chip_class < GFX8)
384 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
385
386 radv_get_driver_uuid(&device->driver_uuid);
387 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
388
389 device->out_of_order_rast_allowed = device->rad_info.has_out_of_order_rast &&
390 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
391
392 device->dcc_msaa_allowed =
393 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
394
395 device->use_ngg = device->rad_info.chip_class >= GFX10 &&
396 device->rad_info.family != CHIP_NAVI14 &&
397 !(device->instance->debug_flags & RADV_DEBUG_NO_NGG);
398
399 /* TODO: Implement NGG GS with ACO. */
400 device->use_ngg_gs = device->use_ngg && device->use_llvm;
401 device->use_ngg_streamout = false;
402
403 /* Determine the number of threads per wave for all stages. */
404 device->cs_wave_size = 64;
405 device->ps_wave_size = 64;
406 device->ge_wave_size = 64;
407
408 if (device->rad_info.chip_class >= GFX10) {
409 if (device->instance->perftest_flags & RADV_PERFTEST_CS_WAVE_32)
410 device->cs_wave_size = 32;
411
412 /* For pixel shaders, wave64 is recommanded. */
413 if (device->instance->perftest_flags & RADV_PERFTEST_PS_WAVE_32)
414 device->ps_wave_size = 32;
415
416 if (device->instance->perftest_flags & RADV_PERFTEST_GE_WAVE_32)
417 device->ge_wave_size = 32;
418 }
419
420 radv_physical_device_init_mem_types(device);
421
422 radv_physical_device_get_supported_extensions(device,
423 &device->supported_extensions);
424
425 if (drm_device)
426 device->bus_info = *drm_device->businfo.pci;
427
428 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
429 ac_print_gpu_info(&device->rad_info);
430
431 /* The WSI is structured as a layer on top of the driver, so this has
432 * to be the last part of initialization (at least until we get other
433 * semi-layers).
434 */
435 result = radv_init_wsi(device);
436 if (result != VK_SUCCESS) {
437 vk_error(instance, result);
438 goto fail_disk_cache;
439 }
440
441 *device_out = device;
442
443 return VK_SUCCESS;
444
445 fail_disk_cache:
446 disk_cache_destroy(device->disk_cache);
447 fail_wsi:
448 device->ws->destroy(device->ws);
449 fail_alloc:
450 vk_free(&instance->alloc, device);
451 fail_fd:
452 if (fd != -1)
453 close(fd);
454 if (master_fd != -1)
455 close(master_fd);
456 return result;
457 }
458
459 static void
460 radv_physical_device_destroy(struct radv_physical_device *device)
461 {
462 radv_finish_wsi(device);
463 device->ws->destroy(device->ws);
464 disk_cache_destroy(device->disk_cache);
465 close(device->local_fd);
466 if (device->master_fd != -1)
467 close(device->master_fd);
468 vk_free(&device->instance->alloc, device);
469 }
470
471 static void *
472 default_alloc_func(void *pUserData, size_t size, size_t align,
473 VkSystemAllocationScope allocationScope)
474 {
475 return malloc(size);
476 }
477
478 static void *
479 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
480 size_t align, VkSystemAllocationScope allocationScope)
481 {
482 return realloc(pOriginal, size);
483 }
484
485 static void
486 default_free_func(void *pUserData, void *pMemory)
487 {
488 free(pMemory);
489 }
490
491 static const VkAllocationCallbacks default_alloc = {
492 .pUserData = NULL,
493 .pfnAllocation = default_alloc_func,
494 .pfnReallocation = default_realloc_func,
495 .pfnFree = default_free_func,
496 };
497
498 static const struct debug_control radv_debug_options[] = {
499 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
500 {"nodcc", RADV_DEBUG_NO_DCC},
501 {"shaders", RADV_DEBUG_DUMP_SHADERS},
502 {"nocache", RADV_DEBUG_NO_CACHE},
503 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
504 {"nohiz", RADV_DEBUG_NO_HIZ},
505 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
506 {"allbos", RADV_DEBUG_ALL_BOS},
507 {"noibs", RADV_DEBUG_NO_IBS},
508 {"spirv", RADV_DEBUG_DUMP_SPIRV},
509 {"vmfaults", RADV_DEBUG_VM_FAULTS},
510 {"zerovram", RADV_DEBUG_ZERO_VRAM},
511 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
512 {"preoptir", RADV_DEBUG_PREOPTIR},
513 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
514 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
515 {"info", RADV_DEBUG_INFO},
516 {"errors", RADV_DEBUG_ERRORS},
517 {"startup", RADV_DEBUG_STARTUP},
518 {"checkir", RADV_DEBUG_CHECKIR},
519 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
520 {"nobinning", RADV_DEBUG_NOBINNING},
521 {"nongg", RADV_DEBUG_NO_NGG},
522 {"allentrypoints", RADV_DEBUG_ALL_ENTRYPOINTS},
523 {"metashaders", RADV_DEBUG_DUMP_META_SHADERS},
524 {"nomemorycache", RADV_DEBUG_NO_MEMORY_CACHE},
525 {"llvm", RADV_DEBUG_LLVM},
526 {"forcecompress", RADV_DEBUG_FORCE_COMPRESS},
527 {NULL, 0}
528 };
529
530 const char *
531 radv_get_debug_option_name(int id)
532 {
533 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
534 return radv_debug_options[id].string;
535 }
536
537 static const struct debug_control radv_perftest_options[] = {
538 {"localbos", RADV_PERFTEST_LOCAL_BOS},
539 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
540 {"bolist", RADV_PERFTEST_BO_LIST},
541 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
542 {"cswave32", RADV_PERFTEST_CS_WAVE_32},
543 {"pswave32", RADV_PERFTEST_PS_WAVE_32},
544 {"gewave32", RADV_PERFTEST_GE_WAVE_32},
545 {"dfsm", RADV_PERFTEST_DFSM},
546 {NULL, 0}
547 };
548
549 const char *
550 radv_get_perftest_option_name(int id)
551 {
552 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
553 return radv_perftest_options[id].string;
554 }
555
556 static void
557 radv_handle_per_app_options(struct radv_instance *instance,
558 const VkApplicationInfo *info)
559 {
560 const char *name = info ? info->pApplicationName : NULL;
561 const char *engine_name = info ? info->pEngineName : NULL;
562
563 if (name) {
564 if (!strcmp(name, "DOOM_VFR")) {
565 /* Work around a Doom VFR game bug */
566 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
567 } else if (!strcmp(name, "Fledge")) {
568 /*
569 * Zero VRAM for "The Surge 2"
570 *
571 * This avoid a hang when when rendering any level. Likely
572 * uninitialized data in an indirect draw.
573 */
574 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
575 } else if (!strcmp(name, "No Man's Sky")) {
576 /* Work around a NMS game bug */
577 instance->debug_flags |= RADV_DEBUG_DISCARD_TO_DEMOTE;
578 } else if (!strcmp(name, "DOOMEternal")) {
579 /* Zero VRAM for Doom Eternal to fix rendering issues. */
580 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
581 } else if (!strcmp(name, "Red Dead Redemption 2")) {
582 /* Work around a RDR2 game bug */
583 instance->debug_flags |= RADV_DEBUG_DISCARD_TO_DEMOTE;
584 }
585 }
586
587 if (engine_name) {
588 if (!strcmp(engine_name, "vkd3d")) {
589 /* Zero VRAM for all VKD3D (DX12->VK) games to fix
590 * rendering issues.
591 */
592 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
593 } else if (!strcmp(engine_name, "Quantic Dream Engine")) {
594 /* Fix various artifacts in Detroit: Become Human */
595 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM |
596 RADV_DEBUG_DISCARD_TO_DEMOTE;
597 }
598 }
599
600 instance->enable_mrt_output_nan_fixup =
601 driQueryOptionb(&instance->dri_options,
602 "radv_enable_mrt_output_nan_fixup");
603
604 if (driQueryOptionb(&instance->dri_options, "radv_no_dynamic_bounds"))
605 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
606 }
607
608 static const char radv_dri_options_xml[] =
609 DRI_CONF_BEGIN
610 DRI_CONF_SECTION_PERFORMANCE
611 DRI_CONF_ADAPTIVE_SYNC("true")
612 DRI_CONF_VK_X11_OVERRIDE_MIN_IMAGE_COUNT(0)
613 DRI_CONF_VK_X11_STRICT_IMAGE_COUNT("false")
614 DRI_CONF_VK_X11_ENSURE_MIN_IMAGE_COUNT("false")
615 DRI_CONF_RADV_REPORT_LLVM9_VERSION_STRING("false")
616 DRI_CONF_RADV_ENABLE_MRT_OUTPUT_NAN_FIXUP("false")
617 DRI_CONF_RADV_NO_DYNAMIC_BOUNDS("false")
618 DRI_CONF_RADV_OVERRIDE_UNIFORM_OFFSET_ALIGNMENT(0)
619 DRI_CONF_SECTION_END
620
621 DRI_CONF_SECTION_DEBUG
622 DRI_CONF_VK_WSI_FORCE_BGRA8_UNORM_FIRST("false")
623 DRI_CONF_SECTION_END
624 DRI_CONF_END;
625
626 static void radv_init_dri_options(struct radv_instance *instance)
627 {
628 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
629 driParseConfigFiles(&instance->dri_options,
630 &instance->available_dri_options,
631 0, "radv", NULL,
632 instance->applicationName,
633 instance->applicationVersion,
634 instance->engineName,
635 instance->engineVersion);
636 }
637
638 VkResult radv_CreateInstance(
639 const VkInstanceCreateInfo* pCreateInfo,
640 const VkAllocationCallbacks* pAllocator,
641 VkInstance* pInstance)
642 {
643 struct radv_instance *instance;
644 VkResult result;
645
646 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
647 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
648 if (!instance)
649 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
650
651 vk_object_base_init(NULL, &instance->base, VK_OBJECT_TYPE_INSTANCE);
652
653 if (pAllocator)
654 instance->alloc = *pAllocator;
655 else
656 instance->alloc = default_alloc;
657
658 if (pCreateInfo->pApplicationInfo) {
659 const VkApplicationInfo *app = pCreateInfo->pApplicationInfo;
660
661 instance->applicationName =
662 vk_strdup(&instance->alloc, app->pApplicationName,
663 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
664 instance->applicationVersion = app->applicationVersion;
665
666 instance->engineName =
667 vk_strdup(&instance->alloc, app->pEngineName,
668 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
669 instance->engineVersion = app->engineVersion;
670 instance->apiVersion = app->apiVersion;
671 }
672
673 if (instance->apiVersion == 0)
674 instance->apiVersion = VK_API_VERSION_1_0;
675
676 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
677 radv_debug_options);
678
679 const char *radv_perftest_str = getenv("RADV_PERFTEST");
680 instance->perftest_flags = parse_debug_string(radv_perftest_str,
681 radv_perftest_options);
682
683 if (radv_perftest_str) {
684 /* Output warnings for famous RADV_PERFTEST options that no
685 * longer exist or are deprecated.
686 */
687 if (strstr(radv_perftest_str, "aco")) {
688 fprintf(stderr, "*******************************************************************************\n");
689 fprintf(stderr, "* WARNING: Unknown option RADV_PERFTEST='aco'. ACO is enabled by default now. *\n");
690 fprintf(stderr, "*******************************************************************************\n");
691 }
692 if (strstr(radv_perftest_str, "llvm")) {
693 fprintf(stderr, "*********************************************************************************\n");
694 fprintf(stderr, "* WARNING: Unknown option 'RADV_PERFTEST=llvm'. Did you mean 'RADV_DEBUG=llvm'? *\n");
695 fprintf(stderr, "*********************************************************************************\n");
696 abort();
697 }
698 }
699
700 if (instance->debug_flags & RADV_DEBUG_STARTUP)
701 radv_logi("Created an instance");
702
703 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
704 int idx;
705 for (idx = 0; idx < RADV_INSTANCE_EXTENSION_COUNT; idx++) {
706 if (!strcmp(pCreateInfo->ppEnabledExtensionNames[i],
707 radv_instance_extensions[idx].extensionName))
708 break;
709 }
710
711 if (idx >= RADV_INSTANCE_EXTENSION_COUNT ||
712 !radv_instance_extensions_supported.extensions[idx]) {
713 vk_object_base_finish(&instance->base);
714 vk_free2(&default_alloc, pAllocator, instance);
715 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
716 }
717
718 instance->enabled_extensions.extensions[idx] = true;
719 }
720
721 bool unchecked = instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS;
722
723 for (unsigned i = 0; i < ARRAY_SIZE(instance->dispatch.entrypoints); i++) {
724 /* Vulkan requires that entrypoints for extensions which have
725 * not been enabled must not be advertised.
726 */
727 if (!unchecked &&
728 !radv_instance_entrypoint_is_enabled(i, instance->apiVersion,
729 &instance->enabled_extensions)) {
730 instance->dispatch.entrypoints[i] = NULL;
731 } else {
732 instance->dispatch.entrypoints[i] =
733 radv_instance_dispatch_table.entrypoints[i];
734 }
735 }
736
737 for (unsigned i = 0; i < ARRAY_SIZE(instance->physical_device_dispatch.entrypoints); i++) {
738 /* Vulkan requires that entrypoints for extensions which have
739 * not been enabled must not be advertised.
740 */
741 if (!unchecked &&
742 !radv_physical_device_entrypoint_is_enabled(i, instance->apiVersion,
743 &instance->enabled_extensions)) {
744 instance->physical_device_dispatch.entrypoints[i] = NULL;
745 } else {
746 instance->physical_device_dispatch.entrypoints[i] =
747 radv_physical_device_dispatch_table.entrypoints[i];
748 }
749 }
750
751 for (unsigned i = 0; i < ARRAY_SIZE(instance->device_dispatch.entrypoints); i++) {
752 /* Vulkan requires that entrypoints for extensions which have
753 * not been enabled must not be advertised.
754 */
755 if (!unchecked &&
756 !radv_device_entrypoint_is_enabled(i, instance->apiVersion,
757 &instance->enabled_extensions, NULL)) {
758 instance->device_dispatch.entrypoints[i] = NULL;
759 } else {
760 instance->device_dispatch.entrypoints[i] =
761 radv_device_dispatch_table.entrypoints[i];
762 }
763 }
764
765 instance->physical_devices_enumerated = false;
766 list_inithead(&instance->physical_devices);
767
768 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
769 if (result != VK_SUCCESS) {
770 vk_object_base_finish(&instance->base);
771 vk_free2(&default_alloc, pAllocator, instance);
772 return vk_error(instance, result);
773 }
774
775 glsl_type_singleton_init_or_ref();
776
777 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
778
779 radv_init_dri_options(instance);
780 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
781
782 *pInstance = radv_instance_to_handle(instance);
783
784 return VK_SUCCESS;
785 }
786
787 void radv_DestroyInstance(
788 VkInstance _instance,
789 const VkAllocationCallbacks* pAllocator)
790 {
791 RADV_FROM_HANDLE(radv_instance, instance, _instance);
792
793 if (!instance)
794 return;
795
796 list_for_each_entry_safe(struct radv_physical_device, pdevice,
797 &instance->physical_devices, link) {
798 radv_physical_device_destroy(pdevice);
799 }
800
801 vk_free(&instance->alloc, instance->engineName);
802 vk_free(&instance->alloc, instance->applicationName);
803
804 VG(VALGRIND_DESTROY_MEMPOOL(instance));
805
806 glsl_type_singleton_decref();
807
808 driDestroyOptionCache(&instance->dri_options);
809 driDestroyOptionInfo(&instance->available_dri_options);
810
811 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
812
813 vk_object_base_finish(&instance->base);
814 vk_free(&instance->alloc, instance);
815 }
816
817 static VkResult
818 radv_enumerate_physical_devices(struct radv_instance *instance)
819 {
820 if (instance->physical_devices_enumerated)
821 return VK_SUCCESS;
822
823 instance->physical_devices_enumerated = true;
824
825 /* TODO: Check for more devices ? */
826 drmDevicePtr devices[8];
827 VkResult result = VK_SUCCESS;
828 int max_devices;
829
830 if (getenv("RADV_FORCE_FAMILY")) {
831 /* When RADV_FORCE_FAMILY is set, the driver creates a nul
832 * device that allows to test the compiler without having an
833 * AMDGPU instance.
834 */
835 struct radv_physical_device *pdevice;
836
837 result = radv_physical_device_try_create(instance, NULL, &pdevice);
838 if (result != VK_SUCCESS)
839 return result;
840
841 list_addtail(&pdevice->link, &instance->physical_devices);
842 return VK_SUCCESS;
843 }
844
845 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
846
847 if (instance->debug_flags & RADV_DEBUG_STARTUP)
848 radv_logi("Found %d drm nodes", max_devices);
849
850 if (max_devices < 1)
851 return vk_error(instance, VK_SUCCESS);
852
853 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
854 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
855 devices[i]->bustype == DRM_BUS_PCI &&
856 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
857
858 struct radv_physical_device *pdevice;
859 result = radv_physical_device_try_create(instance, devices[i],
860 &pdevice);
861 /* Incompatible DRM device, skip. */
862 if (result == VK_ERROR_INCOMPATIBLE_DRIVER) {
863 result = VK_SUCCESS;
864 continue;
865 }
866
867 /* Error creating the physical device, report the error. */
868 if (result != VK_SUCCESS)
869 break;
870
871 list_addtail(&pdevice->link, &instance->physical_devices);
872 }
873 }
874 drmFreeDevices(devices, max_devices);
875
876 /* If we successfully enumerated any devices, call it success */
877 return result;
878 }
879
880 VkResult radv_EnumeratePhysicalDevices(
881 VkInstance _instance,
882 uint32_t* pPhysicalDeviceCount,
883 VkPhysicalDevice* pPhysicalDevices)
884 {
885 RADV_FROM_HANDLE(radv_instance, instance, _instance);
886 VK_OUTARRAY_MAKE(out, pPhysicalDevices, pPhysicalDeviceCount);
887
888 VkResult result = radv_enumerate_physical_devices(instance);
889 if (result != VK_SUCCESS)
890 return result;
891
892 list_for_each_entry(struct radv_physical_device, pdevice,
893 &instance->physical_devices, link) {
894 vk_outarray_append(&out, i) {
895 *i = radv_physical_device_to_handle(pdevice);
896 }
897 }
898
899 return vk_outarray_status(&out);
900 }
901
902 VkResult radv_EnumeratePhysicalDeviceGroups(
903 VkInstance _instance,
904 uint32_t* pPhysicalDeviceGroupCount,
905 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
906 {
907 RADV_FROM_HANDLE(radv_instance, instance, _instance);
908 VK_OUTARRAY_MAKE(out, pPhysicalDeviceGroupProperties,
909 pPhysicalDeviceGroupCount);
910
911 VkResult result = radv_enumerate_physical_devices(instance);
912 if (result != VK_SUCCESS)
913 return result;
914
915 list_for_each_entry(struct radv_physical_device, pdevice,
916 &instance->physical_devices, link) {
917 vk_outarray_append(&out, p) {
918 p->physicalDeviceCount = 1;
919 memset(p->physicalDevices, 0, sizeof(p->physicalDevices));
920 p->physicalDevices[0] = radv_physical_device_to_handle(pdevice);
921 p->subsetAllocation = false;
922 }
923 }
924
925 return vk_outarray_status(&out);
926 }
927
928 void radv_GetPhysicalDeviceFeatures(
929 VkPhysicalDevice physicalDevice,
930 VkPhysicalDeviceFeatures* pFeatures)
931 {
932 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
933 memset(pFeatures, 0, sizeof(*pFeatures));
934
935 *pFeatures = (VkPhysicalDeviceFeatures) {
936 .robustBufferAccess = true,
937 .fullDrawIndexUint32 = true,
938 .imageCubeArray = true,
939 .independentBlend = true,
940 .geometryShader = true,
941 .tessellationShader = true,
942 .sampleRateShading = true,
943 .dualSrcBlend = true,
944 .logicOp = true,
945 .multiDrawIndirect = true,
946 .drawIndirectFirstInstance = true,
947 .depthClamp = true,
948 .depthBiasClamp = true,
949 .fillModeNonSolid = true,
950 .depthBounds = true,
951 .wideLines = true,
952 .largePoints = true,
953 .alphaToOne = true,
954 .multiViewport = true,
955 .samplerAnisotropy = true,
956 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
957 .textureCompressionASTC_LDR = false,
958 .textureCompressionBC = true,
959 .occlusionQueryPrecise = true,
960 .pipelineStatisticsQuery = true,
961 .vertexPipelineStoresAndAtomics = true,
962 .fragmentStoresAndAtomics = true,
963 .shaderTessellationAndGeometryPointSize = true,
964 .shaderImageGatherExtended = true,
965 .shaderStorageImageExtendedFormats = true,
966 .shaderStorageImageMultisample = true,
967 .shaderUniformBufferArrayDynamicIndexing = true,
968 .shaderSampledImageArrayDynamicIndexing = true,
969 .shaderStorageBufferArrayDynamicIndexing = true,
970 .shaderStorageImageArrayDynamicIndexing = true,
971 .shaderStorageImageReadWithoutFormat = true,
972 .shaderStorageImageWriteWithoutFormat = true,
973 .shaderClipDistance = true,
974 .shaderCullDistance = true,
975 .shaderFloat64 = true,
976 .shaderInt64 = true,
977 .shaderInt16 = true,
978 .sparseBinding = true,
979 .variableMultisampleRate = true,
980 .shaderResourceMinLod = true,
981 .inheritedQueries = true,
982 };
983 }
984
985 static void
986 radv_get_physical_device_features_1_1(struct radv_physical_device *pdevice,
987 VkPhysicalDeviceVulkan11Features *f)
988 {
989 assert(f->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES);
990
991 f->storageBuffer16BitAccess = true;
992 f->uniformAndStorageBuffer16BitAccess = true;
993 f->storagePushConstant16 = true;
994 f->storageInputOutput16 = pdevice->rad_info.has_packed_math_16bit && (LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm);
995 f->multiview = true;
996 f->multiviewGeometryShader = true;
997 f->multiviewTessellationShader = true;
998 f->variablePointersStorageBuffer = true;
999 f->variablePointers = true;
1000 f->protectedMemory = false;
1001 f->samplerYcbcrConversion = true;
1002 f->shaderDrawParameters = true;
1003 }
1004
1005 static void
1006 radv_get_physical_device_features_1_2(struct radv_physical_device *pdevice,
1007 VkPhysicalDeviceVulkan12Features *f)
1008 {
1009 assert(f->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES);
1010
1011 f->samplerMirrorClampToEdge = true;
1012 f->drawIndirectCount = true;
1013 f->storageBuffer8BitAccess = true;
1014 f->uniformAndStorageBuffer8BitAccess = true;
1015 f->storagePushConstant8 = true;
1016 f->shaderBufferInt64Atomics = LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm;
1017 f->shaderSharedInt64Atomics = LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm;
1018 f->shaderFloat16 = pdevice->rad_info.has_packed_math_16bit;
1019 f->shaderInt8 = true;
1020
1021 f->descriptorIndexing = true;
1022 f->shaderInputAttachmentArrayDynamicIndexing = true;
1023 f->shaderUniformTexelBufferArrayDynamicIndexing = true;
1024 f->shaderStorageTexelBufferArrayDynamicIndexing = true;
1025 f->shaderUniformBufferArrayNonUniformIndexing = true;
1026 f->shaderSampledImageArrayNonUniformIndexing = true;
1027 f->shaderStorageBufferArrayNonUniformIndexing = true;
1028 f->shaderStorageImageArrayNonUniformIndexing = true;
1029 f->shaderInputAttachmentArrayNonUniformIndexing = true;
1030 f->shaderUniformTexelBufferArrayNonUniformIndexing = true;
1031 f->shaderStorageTexelBufferArrayNonUniformIndexing = true;
1032 f->descriptorBindingUniformBufferUpdateAfterBind = true;
1033 f->descriptorBindingSampledImageUpdateAfterBind = true;
1034 f->descriptorBindingStorageImageUpdateAfterBind = true;
1035 f->descriptorBindingStorageBufferUpdateAfterBind = true;
1036 f->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
1037 f->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
1038 f->descriptorBindingUpdateUnusedWhilePending = true;
1039 f->descriptorBindingPartiallyBound = true;
1040 f->descriptorBindingVariableDescriptorCount = true;
1041 f->runtimeDescriptorArray = true;
1042
1043 f->samplerFilterMinmax = true;
1044 f->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
1045 f->imagelessFramebuffer = true;
1046 f->uniformBufferStandardLayout = true;
1047 f->shaderSubgroupExtendedTypes = true;
1048 f->separateDepthStencilLayouts = true;
1049 f->hostQueryReset = true;
1050 f->timelineSemaphore = pdevice->rad_info.has_syncobj_wait_for_submit;
1051 f->bufferDeviceAddress = true;
1052 f->bufferDeviceAddressCaptureReplay = false;
1053 f->bufferDeviceAddressMultiDevice = false;
1054 f->vulkanMemoryModel = true;
1055 f->vulkanMemoryModelDeviceScope = true;
1056 f->vulkanMemoryModelAvailabilityVisibilityChains = false;
1057 f->shaderOutputViewportIndex = true;
1058 f->shaderOutputLayer = true;
1059 f->subgroupBroadcastDynamicId = true;
1060 }
1061
1062 void radv_GetPhysicalDeviceFeatures2(
1063 VkPhysicalDevice physicalDevice,
1064 VkPhysicalDeviceFeatures2 *pFeatures)
1065 {
1066 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1067 radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
1068
1069 VkPhysicalDeviceVulkan11Features core_1_1 = {
1070 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES,
1071 };
1072 radv_get_physical_device_features_1_1(pdevice, &core_1_1);
1073
1074 VkPhysicalDeviceVulkan12Features core_1_2 = {
1075 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES,
1076 };
1077 radv_get_physical_device_features_1_2(pdevice, &core_1_2);
1078
1079 #define CORE_FEATURE(major, minor, feature) \
1080 features->feature = core_##major##_##minor.feature
1081
1082 vk_foreach_struct(ext, pFeatures->pNext) {
1083 switch (ext->sType) {
1084 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
1085 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
1086 CORE_FEATURE(1, 1, variablePointersStorageBuffer);
1087 CORE_FEATURE(1, 1, variablePointers);
1088 break;
1089 }
1090 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
1091 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
1092 CORE_FEATURE(1, 1, multiview);
1093 CORE_FEATURE(1, 1, multiviewGeometryShader);
1094 CORE_FEATURE(1, 1, multiviewTessellationShader);
1095 break;
1096 }
1097 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
1098 VkPhysicalDeviceShaderDrawParametersFeatures *features =
1099 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
1100 CORE_FEATURE(1, 1, shaderDrawParameters);
1101 break;
1102 }
1103 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
1104 VkPhysicalDeviceProtectedMemoryFeatures *features =
1105 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
1106 CORE_FEATURE(1, 1, protectedMemory);
1107 break;
1108 }
1109 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
1110 VkPhysicalDevice16BitStorageFeatures *features =
1111 (VkPhysicalDevice16BitStorageFeatures*)ext;
1112 CORE_FEATURE(1, 1, storageBuffer16BitAccess);
1113 CORE_FEATURE(1, 1, uniformAndStorageBuffer16BitAccess);
1114 CORE_FEATURE(1, 1, storagePushConstant16);
1115 CORE_FEATURE(1, 1, storageInputOutput16);
1116 break;
1117 }
1118 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
1119 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
1120 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
1121 CORE_FEATURE(1, 1, samplerYcbcrConversion);
1122 break;
1123 }
1124 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES: {
1125 VkPhysicalDeviceDescriptorIndexingFeatures *features =
1126 (VkPhysicalDeviceDescriptorIndexingFeatures*)ext;
1127 CORE_FEATURE(1, 2, shaderInputAttachmentArrayDynamicIndexing);
1128 CORE_FEATURE(1, 2, shaderUniformTexelBufferArrayDynamicIndexing);
1129 CORE_FEATURE(1, 2, shaderStorageTexelBufferArrayDynamicIndexing);
1130 CORE_FEATURE(1, 2, shaderUniformBufferArrayNonUniformIndexing);
1131 CORE_FEATURE(1, 2, shaderSampledImageArrayNonUniformIndexing);
1132 CORE_FEATURE(1, 2, shaderStorageBufferArrayNonUniformIndexing);
1133 CORE_FEATURE(1, 2, shaderStorageImageArrayNonUniformIndexing);
1134 CORE_FEATURE(1, 2, shaderInputAttachmentArrayNonUniformIndexing);
1135 CORE_FEATURE(1, 2, shaderUniformTexelBufferArrayNonUniformIndexing);
1136 CORE_FEATURE(1, 2, shaderStorageTexelBufferArrayNonUniformIndexing);
1137 CORE_FEATURE(1, 2, descriptorBindingUniformBufferUpdateAfterBind);
1138 CORE_FEATURE(1, 2, descriptorBindingSampledImageUpdateAfterBind);
1139 CORE_FEATURE(1, 2, descriptorBindingStorageImageUpdateAfterBind);
1140 CORE_FEATURE(1, 2, descriptorBindingStorageBufferUpdateAfterBind);
1141 CORE_FEATURE(1, 2, descriptorBindingUniformTexelBufferUpdateAfterBind);
1142 CORE_FEATURE(1, 2, descriptorBindingStorageTexelBufferUpdateAfterBind);
1143 CORE_FEATURE(1, 2, descriptorBindingUpdateUnusedWhilePending);
1144 CORE_FEATURE(1, 2, descriptorBindingPartiallyBound);
1145 CORE_FEATURE(1, 2, descriptorBindingVariableDescriptorCount);
1146 CORE_FEATURE(1, 2, runtimeDescriptorArray);
1147 break;
1148 }
1149 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
1150 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
1151 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
1152 features->conditionalRendering = true;
1153 features->inheritedConditionalRendering = false;
1154 break;
1155 }
1156 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
1157 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
1158 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
1159 features->vertexAttributeInstanceRateDivisor = true;
1160 features->vertexAttributeInstanceRateZeroDivisor = true;
1161 break;
1162 }
1163 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
1164 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
1165 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
1166 features->transformFeedback = true;
1167 features->geometryStreams = !pdevice->use_ngg_streamout;
1168 break;
1169 }
1170 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES: {
1171 VkPhysicalDeviceScalarBlockLayoutFeatures *features =
1172 (VkPhysicalDeviceScalarBlockLayoutFeatures *)ext;
1173 CORE_FEATURE(1, 2, scalarBlockLayout);
1174 break;
1175 }
1176 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
1177 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
1178 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
1179 features->memoryPriority = true;
1180 break;
1181 }
1182 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
1183 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
1184 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
1185 features->bufferDeviceAddress = true;
1186 features->bufferDeviceAddressCaptureReplay = false;
1187 features->bufferDeviceAddressMultiDevice = false;
1188 break;
1189 }
1190 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES: {
1191 VkPhysicalDeviceBufferDeviceAddressFeatures *features =
1192 (VkPhysicalDeviceBufferDeviceAddressFeatures *)ext;
1193 CORE_FEATURE(1, 2, bufferDeviceAddress);
1194 CORE_FEATURE(1, 2, bufferDeviceAddressCaptureReplay);
1195 CORE_FEATURE(1, 2, bufferDeviceAddressMultiDevice);
1196 break;
1197 }
1198 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
1199 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
1200 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
1201 features->depthClipEnable = true;
1202 break;
1203 }
1204 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES: {
1205 VkPhysicalDeviceHostQueryResetFeatures *features =
1206 (VkPhysicalDeviceHostQueryResetFeatures *)ext;
1207 CORE_FEATURE(1, 2, hostQueryReset);
1208 break;
1209 }
1210 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES: {
1211 VkPhysicalDevice8BitStorageFeatures *features =
1212 (VkPhysicalDevice8BitStorageFeatures *)ext;
1213 CORE_FEATURE(1, 2, storageBuffer8BitAccess);
1214 CORE_FEATURE(1, 2, uniformAndStorageBuffer8BitAccess);
1215 CORE_FEATURE(1, 2, storagePushConstant8);
1216 break;
1217 }
1218 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_FLOAT16_INT8_FEATURES: {
1219 VkPhysicalDeviceShaderFloat16Int8Features *features =
1220 (VkPhysicalDeviceShaderFloat16Int8Features*)ext;
1221 CORE_FEATURE(1, 2, shaderFloat16);
1222 CORE_FEATURE(1, 2, shaderInt8);
1223 break;
1224 }
1225 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES: {
1226 VkPhysicalDeviceShaderAtomicInt64Features *features =
1227 (VkPhysicalDeviceShaderAtomicInt64Features *)ext;
1228 CORE_FEATURE(1, 2, shaderBufferInt64Atomics);
1229 CORE_FEATURE(1, 2, shaderSharedInt64Atomics);
1230 break;
1231 }
1232 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DEMOTE_TO_HELPER_INVOCATION_FEATURES_EXT: {
1233 VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT *features =
1234 (VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT *)ext;
1235 features->shaderDemoteToHelperInvocation = LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm;
1236 break;
1237 }
1238 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
1239 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
1240 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
1241
1242 features->inlineUniformBlock = true;
1243 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
1244 break;
1245 }
1246 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
1247 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
1248 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
1249 features->computeDerivativeGroupQuads = false;
1250 features->computeDerivativeGroupLinear = true;
1251 break;
1252 }
1253 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
1254 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
1255 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
1256 features->ycbcrImageArrays = true;
1257 break;
1258 }
1259 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES: {
1260 VkPhysicalDeviceUniformBufferStandardLayoutFeatures *features =
1261 (VkPhysicalDeviceUniformBufferStandardLayoutFeatures *)ext;
1262 CORE_FEATURE(1, 2, uniformBufferStandardLayout);
1263 break;
1264 }
1265 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT: {
1266 VkPhysicalDeviceIndexTypeUint8FeaturesEXT *features =
1267 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT *)ext;
1268 features->indexTypeUint8 = pdevice->rad_info.chip_class >= GFX8;
1269 break;
1270 }
1271 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGELESS_FRAMEBUFFER_FEATURES: {
1272 VkPhysicalDeviceImagelessFramebufferFeatures *features =
1273 (VkPhysicalDeviceImagelessFramebufferFeatures *)ext;
1274 CORE_FEATURE(1, 2, imagelessFramebuffer);
1275 break;
1276 }
1277 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR: {
1278 VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *features =
1279 (VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *)ext;
1280 features->pipelineExecutableInfo = true;
1281 break;
1282 }
1283 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CLOCK_FEATURES_KHR: {
1284 VkPhysicalDeviceShaderClockFeaturesKHR *features =
1285 (VkPhysicalDeviceShaderClockFeaturesKHR *)ext;
1286 features->shaderSubgroupClock = true;
1287 features->shaderDeviceClock = pdevice->rad_info.chip_class >= GFX8;
1288 break;
1289 }
1290 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_FEATURES_EXT: {
1291 VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT *features =
1292 (VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT *)ext;
1293 features->texelBufferAlignment = true;
1294 break;
1295 }
1296 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_FEATURES: {
1297 VkPhysicalDeviceTimelineSemaphoreFeatures *features =
1298 (VkPhysicalDeviceTimelineSemaphoreFeatures *) ext;
1299 CORE_FEATURE(1, 2, timelineSemaphore);
1300 break;
1301 }
1302 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_FEATURES_EXT: {
1303 VkPhysicalDeviceSubgroupSizeControlFeaturesEXT *features =
1304 (VkPhysicalDeviceSubgroupSizeControlFeaturesEXT *)ext;
1305 features->subgroupSizeControl = true;
1306 features->computeFullSubgroups = true;
1307 break;
1308 }
1309 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COHERENT_MEMORY_FEATURES_AMD: {
1310 VkPhysicalDeviceCoherentMemoryFeaturesAMD *features =
1311 (VkPhysicalDeviceCoherentMemoryFeaturesAMD *)ext;
1312 features->deviceCoherentMemory = pdevice->rad_info.has_l2_uncached;
1313 break;
1314 }
1315 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_SUBGROUP_EXTENDED_TYPES_FEATURES: {
1316 VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures *features =
1317 (VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures *)ext;
1318 CORE_FEATURE(1, 2, shaderSubgroupExtendedTypes);
1319 break;
1320 }
1321 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SEPARATE_DEPTH_STENCIL_LAYOUTS_FEATURES_KHR: {
1322 VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR *features =
1323 (VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR *)ext;
1324 CORE_FEATURE(1, 2, separateDepthStencilLayouts);
1325 break;
1326 }
1327 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES: {
1328 radv_get_physical_device_features_1_1(pdevice, (void *)ext);
1329 break;
1330 }
1331 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES: {
1332 radv_get_physical_device_features_1_2(pdevice, (void *)ext);
1333 break;
1334 }
1335 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_FEATURES_EXT: {
1336 VkPhysicalDeviceLineRasterizationFeaturesEXT *features =
1337 (VkPhysicalDeviceLineRasterizationFeaturesEXT *)ext;
1338 features->rectangularLines = false;
1339 features->bresenhamLines = true;
1340 features->smoothLines = false;
1341 features->stippledRectangularLines = false;
1342 features->stippledBresenhamLines = true;
1343 features->stippledSmoothLines = false;
1344 break;
1345 }
1346 case VK_STRUCTURE_TYPE_DEVICE_MEMORY_OVERALLOCATION_CREATE_INFO_AMD: {
1347 VkDeviceMemoryOverallocationCreateInfoAMD *features =
1348 (VkDeviceMemoryOverallocationCreateInfoAMD *)ext;
1349 features->overallocationBehavior = true;
1350 break;
1351 }
1352 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ROBUSTNESS_2_FEATURES_EXT: {
1353 VkPhysicalDeviceRobustness2FeaturesEXT *features =
1354 (VkPhysicalDeviceRobustness2FeaturesEXT *)ext;
1355 features->robustBufferAccess2 = true;
1356 features->robustImageAccess2 = true;
1357 features->nullDescriptor = true;
1358 break;
1359 }
1360 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_FEATURES_EXT: {
1361 VkPhysicalDeviceCustomBorderColorFeaturesEXT *features =
1362 (VkPhysicalDeviceCustomBorderColorFeaturesEXT *)ext;
1363 features->customBorderColors = true;
1364 features->customBorderColorWithoutFormat = true;
1365 break;
1366 }
1367 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PRIVATE_DATA_FEATURES_EXT: {
1368 VkPhysicalDevicePrivateDataFeaturesEXT *features =
1369 (VkPhysicalDevicePrivateDataFeaturesEXT *)ext;
1370 features->privateData = true;
1371 break;
1372 }
1373 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_CREATION_CACHE_CONTROL_FEATURES_EXT: {
1374 VkPhysicalDevicePipelineCreationCacheControlFeaturesEXT *features =
1375 (VkPhysicalDevicePipelineCreationCacheControlFeaturesEXT *)ext;
1376 features-> pipelineCreationCacheControl = true;
1377 break;
1378 }
1379 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_MEMORY_MODEL_FEATURES_KHR: {
1380 VkPhysicalDeviceVulkanMemoryModelFeaturesKHR *features =
1381 (VkPhysicalDeviceVulkanMemoryModelFeaturesKHR *)ext;
1382 CORE_FEATURE(1, 2, vulkanMemoryModel);
1383 CORE_FEATURE(1, 2, vulkanMemoryModelDeviceScope);
1384 CORE_FEATURE(1, 2, vulkanMemoryModelAvailabilityVisibilityChains);
1385 break;
1386 }
1387 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTENDED_DYNAMIC_STATE_FEATURES_EXT: {
1388 VkPhysicalDeviceExtendedDynamicStateFeaturesEXT *features =
1389 (VkPhysicalDeviceExtendedDynamicStateFeaturesEXT *) ext;
1390 features->extendedDynamicState = true;
1391 break;
1392 }
1393 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGE_ROBUSTNESS_FEATURES_EXT: {
1394 VkPhysicalDeviceImageRobustnessFeaturesEXT *features =
1395 (VkPhysicalDeviceImageRobustnessFeaturesEXT *)ext;
1396 features->robustImageAccess = true;
1397 break;
1398 }
1399 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_FLOAT_FEATURES_EXT: {
1400 VkPhysicalDeviceShaderAtomicFloatFeaturesEXT *features =
1401 (VkPhysicalDeviceShaderAtomicFloatFeaturesEXT *)ext;
1402 features->shaderBufferFloat32Atomics = true;
1403 features->shaderBufferFloat32AtomicAdd = false;
1404 features->shaderBufferFloat64Atomics = true;
1405 features->shaderBufferFloat64AtomicAdd = false;
1406 features->shaderSharedFloat32Atomics = true;
1407 features->shaderSharedFloat32AtomicAdd = pdevice->rad_info.chip_class >= GFX8 &&
1408 (!pdevice->use_llvm || LLVM_VERSION_MAJOR >= 10);
1409 features->shaderSharedFloat64Atomics = true;
1410 features->shaderSharedFloat64AtomicAdd = false;
1411 features->shaderImageFloat32Atomics = true;
1412 features->shaderImageFloat32AtomicAdd = false;
1413 features->sparseImageFloat32Atomics = false;
1414 features->sparseImageFloat32AtomicAdd = false;
1415 break;
1416 }
1417 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_4444_FORMATS_FEATURES_EXT: {
1418 VkPhysicalDevice4444FormatsFeaturesEXT *features =
1419 (VkPhysicalDevice4444FormatsFeaturesEXT *)ext;
1420 features->formatA4R4G4B4 = true;
1421 features->formatA4B4G4R4 = true;
1422 break;
1423 }
1424 default:
1425 break;
1426 }
1427 }
1428 #undef CORE_FEATURE
1429 }
1430
1431 static size_t
1432 radv_max_descriptor_set_size()
1433 {
1434 /* make sure that the entire descriptor set is addressable with a signed
1435 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1436 * be at most 2 GiB. the combined image & samples object count as one of
1437 * both. This limit is for the pipeline layout, not for the set layout, but
1438 * there is no set limit, so we just set a pipeline limit. I don't think
1439 * any app is going to hit this soon. */
1440 return ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
1441 - MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1442 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1443 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1444 32 /* sampler, largest when combined with image */ +
1445 64 /* sampled image */ +
1446 64 /* storage image */);
1447 }
1448
1449 static uint32_t
1450 radv_uniform_buffer_offset_alignment(const struct radv_physical_device *pdevice)
1451 {
1452 uint32_t uniform_offset_alignment = driQueryOptioni(&pdevice->instance->dri_options,
1453 "radv_override_uniform_offset_alignment");
1454 if (!util_is_power_of_two_or_zero(uniform_offset_alignment)) {
1455 fprintf(stderr, "ERROR: invalid radv_override_uniform_offset_alignment setting %d:"
1456 "not a power of two\n", uniform_offset_alignment);
1457 uniform_offset_alignment = 0;
1458 }
1459
1460 /* Take at least the hardware limit. */
1461 return MAX2(uniform_offset_alignment, 4);
1462 }
1463
1464 void radv_GetPhysicalDeviceProperties(
1465 VkPhysicalDevice physicalDevice,
1466 VkPhysicalDeviceProperties* pProperties)
1467 {
1468 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1469 VkSampleCountFlags sample_counts = 0xf;
1470
1471 size_t max_descriptor_set_size = radv_max_descriptor_set_size();
1472
1473 VkPhysicalDeviceLimits limits = {
1474 .maxImageDimension1D = (1 << 14),
1475 .maxImageDimension2D = (1 << 14),
1476 .maxImageDimension3D = (1 << 11),
1477 .maxImageDimensionCube = (1 << 14),
1478 .maxImageArrayLayers = (1 << 11),
1479 .maxTexelBufferElements = UINT32_MAX,
1480 .maxUniformBufferRange = UINT32_MAX,
1481 .maxStorageBufferRange = UINT32_MAX,
1482 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1483 .maxMemoryAllocationCount = UINT32_MAX,
1484 .maxSamplerAllocationCount = 64 * 1024,
1485 .bufferImageGranularity = 64, /* A cache line */
1486 .sparseAddressSpaceSize = RADV_MAX_MEMORY_ALLOCATION_SIZE, /* buffer max size */
1487 .maxBoundDescriptorSets = MAX_SETS,
1488 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1489 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1490 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1491 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1492 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1493 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1494 .maxPerStageResources = max_descriptor_set_size,
1495 .maxDescriptorSetSamplers = max_descriptor_set_size,
1496 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1497 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1498 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1499 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1500 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1501 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1502 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1503 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1504 .maxVertexInputBindings = MAX_VBS,
1505 .maxVertexInputAttributeOffset = 2047,
1506 .maxVertexInputBindingStride = 2048,
1507 .maxVertexOutputComponents = 128,
1508 .maxTessellationGenerationLevel = 64,
1509 .maxTessellationPatchSize = 32,
1510 .maxTessellationControlPerVertexInputComponents = 128,
1511 .maxTessellationControlPerVertexOutputComponents = 128,
1512 .maxTessellationControlPerPatchOutputComponents = 120,
1513 .maxTessellationControlTotalOutputComponents = 4096,
1514 .maxTessellationEvaluationInputComponents = 128,
1515 .maxTessellationEvaluationOutputComponents = 128,
1516 .maxGeometryShaderInvocations = 127,
1517 .maxGeometryInputComponents = 64,
1518 .maxGeometryOutputComponents = 128,
1519 .maxGeometryOutputVertices = 256,
1520 .maxGeometryTotalOutputComponents = 1024,
1521 .maxFragmentInputComponents = 128,
1522 .maxFragmentOutputAttachments = 8,
1523 .maxFragmentDualSrcAttachments = 1,
1524 .maxFragmentCombinedOutputResources = 8,
1525 .maxComputeSharedMemorySize = 32768,
1526 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1527 .maxComputeWorkGroupInvocations = 1024,
1528 .maxComputeWorkGroupSize = {
1529 1024,
1530 1024,
1531 1024
1532 },
1533 .subPixelPrecisionBits = 8,
1534 .subTexelPrecisionBits = 8,
1535 .mipmapPrecisionBits = 8,
1536 .maxDrawIndexedIndexValue = UINT32_MAX,
1537 .maxDrawIndirectCount = UINT32_MAX,
1538 .maxSamplerLodBias = 16,
1539 .maxSamplerAnisotropy = 16,
1540 .maxViewports = MAX_VIEWPORTS,
1541 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1542 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1543 .viewportSubPixelBits = 8,
1544 .minMemoryMapAlignment = 4096, /* A page */
1545 .minTexelBufferOffsetAlignment = 4,
1546 .minUniformBufferOffsetAlignment = radv_uniform_buffer_offset_alignment(pdevice),
1547 .minStorageBufferOffsetAlignment = 4,
1548 .minTexelOffset = -32,
1549 .maxTexelOffset = 31,
1550 .minTexelGatherOffset = -32,
1551 .maxTexelGatherOffset = 31,
1552 .minInterpolationOffset = -2,
1553 .maxInterpolationOffset = 2,
1554 .subPixelInterpolationOffsetBits = 8,
1555 .maxFramebufferWidth = (1 << 14),
1556 .maxFramebufferHeight = (1 << 14),
1557 .maxFramebufferLayers = (1 << 10),
1558 .framebufferColorSampleCounts = sample_counts,
1559 .framebufferDepthSampleCounts = sample_counts,
1560 .framebufferStencilSampleCounts = sample_counts,
1561 .framebufferNoAttachmentsSampleCounts = sample_counts,
1562 .maxColorAttachments = MAX_RTS,
1563 .sampledImageColorSampleCounts = sample_counts,
1564 .sampledImageIntegerSampleCounts = sample_counts,
1565 .sampledImageDepthSampleCounts = sample_counts,
1566 .sampledImageStencilSampleCounts = sample_counts,
1567 .storageImageSampleCounts = sample_counts,
1568 .maxSampleMaskWords = 1,
1569 .timestampComputeAndGraphics = true,
1570 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1571 .maxClipDistances = 8,
1572 .maxCullDistances = 8,
1573 .maxCombinedClipAndCullDistances = 8,
1574 .discreteQueuePriorities = 2,
1575 .pointSizeRange = { 0.0, 8191.875 },
1576 .lineWidthRange = { 0.0, 8191.875 },
1577 .pointSizeGranularity = (1.0 / 8.0),
1578 .lineWidthGranularity = (1.0 / 8.0),
1579 .strictLines = false, /* FINISHME */
1580 .standardSampleLocations = true,
1581 .optimalBufferCopyOffsetAlignment = 128,
1582 .optimalBufferCopyRowPitchAlignment = 128,
1583 .nonCoherentAtomSize = 64,
1584 };
1585
1586 *pProperties = (VkPhysicalDeviceProperties) {
1587 .apiVersion = radv_physical_device_api_version(pdevice),
1588 .driverVersion = vk_get_driver_version(),
1589 .vendorID = ATI_VENDOR_ID,
1590 .deviceID = pdevice->rad_info.pci_id,
1591 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1592 .limits = limits,
1593 .sparseProperties = {0},
1594 };
1595
1596 strcpy(pProperties->deviceName, pdevice->name);
1597 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1598 }
1599
1600 static void
1601 radv_get_physical_device_properties_1_1(struct radv_physical_device *pdevice,
1602 VkPhysicalDeviceVulkan11Properties *p)
1603 {
1604 assert(p->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES);
1605
1606 memcpy(p->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1607 memcpy(p->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1608 memset(p->deviceLUID, 0, VK_LUID_SIZE);
1609 /* The LUID is for Windows. */
1610 p->deviceLUIDValid = false;
1611 p->deviceNodeMask = 0;
1612
1613 p->subgroupSize = RADV_SUBGROUP_SIZE;
1614 p->subgroupSupportedStages = VK_SHADER_STAGE_ALL_GRAPHICS |
1615 VK_SHADER_STAGE_COMPUTE_BIT;
1616 p->subgroupSupportedOperations = VK_SUBGROUP_FEATURE_BASIC_BIT |
1617 VK_SUBGROUP_FEATURE_VOTE_BIT |
1618 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1619 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1620 VK_SUBGROUP_FEATURE_CLUSTERED_BIT |
1621 VK_SUBGROUP_FEATURE_QUAD_BIT |
1622 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1623 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1624 p->subgroupQuadOperationsInAllStages = true;
1625
1626 p->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1627 p->maxMultiviewViewCount = MAX_VIEWS;
1628 p->maxMultiviewInstanceIndex = INT_MAX;
1629 p->protectedNoFault = false;
1630 p->maxPerSetDescriptors = RADV_MAX_PER_SET_DESCRIPTORS;
1631 p->maxMemoryAllocationSize = RADV_MAX_MEMORY_ALLOCATION_SIZE;
1632 }
1633
1634 static void
1635 radv_get_physical_device_properties_1_2(struct radv_physical_device *pdevice,
1636 VkPhysicalDeviceVulkan12Properties *p)
1637 {
1638 assert(p->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES);
1639
1640 p->driverID = VK_DRIVER_ID_MESA_RADV;
1641 snprintf(p->driverName, VK_MAX_DRIVER_NAME_SIZE, "radv");
1642 snprintf(p->driverInfo, VK_MAX_DRIVER_INFO_SIZE,
1643 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1 " (%s)",
1644 radv_get_compiler_string(pdevice));
1645 p->conformanceVersion = (VkConformanceVersion) {
1646 .major = 1,
1647 .minor = 2,
1648 .subminor = 3,
1649 .patch = 0,
1650 };
1651
1652 /* On AMD hardware, denormals and rounding modes for fp16/fp64 are
1653 * controlled by the same config register.
1654 */
1655 if (pdevice->rad_info.has_packed_math_16bit) {
1656 p->denormBehaviorIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
1657 p->roundingModeIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
1658 } else {
1659 p->denormBehaviorIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL_KHR;
1660 p->roundingModeIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL_KHR;
1661 }
1662
1663 /* With LLVM, do not allow both preserving and flushing denorms because
1664 * different shaders in the same pipeline can have different settings and
1665 * this won't work for merged shaders. To make it work, this requires LLVM
1666 * support for changing the register. The same logic applies for the
1667 * rounding modes because they are configured with the same config
1668 * register.
1669 */
1670 p->shaderDenormFlushToZeroFloat32 = true;
1671 p->shaderDenormPreserveFloat32 = !pdevice->use_llvm;
1672 p->shaderRoundingModeRTEFloat32 = true;
1673 p->shaderRoundingModeRTZFloat32 = !pdevice->use_llvm;
1674 p->shaderSignedZeroInfNanPreserveFloat32 = true;
1675
1676 p->shaderDenormFlushToZeroFloat16 = pdevice->rad_info.has_packed_math_16bit && !pdevice->use_llvm;
1677 p->shaderDenormPreserveFloat16 = pdevice->rad_info.has_packed_math_16bit;
1678 p->shaderRoundingModeRTEFloat16 = pdevice->rad_info.has_packed_math_16bit;
1679 p->shaderRoundingModeRTZFloat16 = pdevice->rad_info.has_packed_math_16bit && !pdevice->use_llvm;
1680 p->shaderSignedZeroInfNanPreserveFloat16 = pdevice->rad_info.has_packed_math_16bit;
1681
1682 p->shaderDenormFlushToZeroFloat64 = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_llvm;
1683 p->shaderDenormPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8;
1684 p->shaderRoundingModeRTEFloat64 = pdevice->rad_info.chip_class >= GFX8;
1685 p->shaderRoundingModeRTZFloat64 = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_llvm;
1686 p->shaderSignedZeroInfNanPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8;
1687
1688 p->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1689 p->shaderUniformBufferArrayNonUniformIndexingNative = false;
1690 p->shaderSampledImageArrayNonUniformIndexingNative = false;
1691 p->shaderStorageBufferArrayNonUniformIndexingNative = false;
1692 p->shaderStorageImageArrayNonUniformIndexingNative = false;
1693 p->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1694 p->robustBufferAccessUpdateAfterBind = false;
1695 p->quadDivergentImplicitLod = false;
1696
1697 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1698 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1699 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1700 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1701 32 /* sampler, largest when combined with image */ +
1702 64 /* sampled image */ +
1703 64 /* storage image */);
1704 p->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1705 p->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1706 p->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1707 p->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1708 p->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1709 p->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1710 p->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1711 p->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1712 p->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1713 p->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1714 p->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1715 p->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1716 p->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1717 p->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1718 p->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1719
1720 /* We support all of the depth resolve modes */
1721 p->supportedDepthResolveModes = VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1722 VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
1723 VK_RESOLVE_MODE_MIN_BIT_KHR |
1724 VK_RESOLVE_MODE_MAX_BIT_KHR;
1725
1726 /* Average doesn't make sense for stencil so we don't support that */
1727 p->supportedStencilResolveModes = VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1728 VK_RESOLVE_MODE_MIN_BIT_KHR |
1729 VK_RESOLVE_MODE_MAX_BIT_KHR;
1730
1731 p->independentResolveNone = true;
1732 p->independentResolve = true;
1733
1734 /* GFX6-8 only support single channel min/max filter. */
1735 p->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1736 p->filterMinmaxSingleComponentFormats = true;
1737
1738 p->maxTimelineSemaphoreValueDifference = UINT64_MAX;
1739
1740 p->framebufferIntegerColorSampleCounts = VK_SAMPLE_COUNT_1_BIT;
1741 }
1742
1743 void radv_GetPhysicalDeviceProperties2(
1744 VkPhysicalDevice physicalDevice,
1745 VkPhysicalDeviceProperties2 *pProperties)
1746 {
1747 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1748 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1749
1750 VkPhysicalDeviceVulkan11Properties core_1_1 = {
1751 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES,
1752 };
1753 radv_get_physical_device_properties_1_1(pdevice, &core_1_1);
1754
1755 VkPhysicalDeviceVulkan12Properties core_1_2 = {
1756 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES,
1757 };
1758 radv_get_physical_device_properties_1_2(pdevice, &core_1_2);
1759
1760 #define CORE_RENAMED_PROPERTY(major, minor, ext_property, core_property) \
1761 memcpy(&properties->ext_property, &core_##major##_##minor.core_property, \
1762 sizeof(core_##major##_##minor.core_property))
1763
1764 #define CORE_PROPERTY(major, minor, property) \
1765 CORE_RENAMED_PROPERTY(major, minor, property, property)
1766
1767 vk_foreach_struct(ext, pProperties->pNext) {
1768 switch (ext->sType) {
1769 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1770 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1771 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1772 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1773 break;
1774 }
1775 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1776 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1777 CORE_PROPERTY(1, 1, deviceUUID);
1778 CORE_PROPERTY(1, 1, driverUUID);
1779 CORE_PROPERTY(1, 1, deviceLUID);
1780 CORE_PROPERTY(1, 1, deviceLUIDValid);
1781 break;
1782 }
1783 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1784 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1785 CORE_PROPERTY(1, 1, maxMultiviewViewCount);
1786 CORE_PROPERTY(1, 1, maxMultiviewInstanceIndex);
1787 break;
1788 }
1789 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1790 VkPhysicalDevicePointClippingProperties *properties =
1791 (VkPhysicalDevicePointClippingProperties*)ext;
1792 CORE_PROPERTY(1, 1, pointClippingBehavior);
1793 break;
1794 }
1795 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1796 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1797 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1798 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1799 break;
1800 }
1801 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1802 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1803 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1804 properties->minImportedHostPointerAlignment = 4096;
1805 break;
1806 }
1807 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1808 VkPhysicalDeviceSubgroupProperties *properties =
1809 (VkPhysicalDeviceSubgroupProperties*)ext;
1810 CORE_PROPERTY(1, 1, subgroupSize);
1811 CORE_RENAMED_PROPERTY(1, 1, supportedStages,
1812 subgroupSupportedStages);
1813 CORE_RENAMED_PROPERTY(1, 1, supportedOperations,
1814 subgroupSupportedOperations);
1815 CORE_RENAMED_PROPERTY(1, 1, quadOperationsInAllStages,
1816 subgroupQuadOperationsInAllStages);
1817 break;
1818 }
1819 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1820 VkPhysicalDeviceMaintenance3Properties *properties =
1821 (VkPhysicalDeviceMaintenance3Properties*)ext;
1822 CORE_PROPERTY(1, 1, maxPerSetDescriptors);
1823 CORE_PROPERTY(1, 1, maxMemoryAllocationSize);
1824 break;
1825 }
1826 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES: {
1827 VkPhysicalDeviceSamplerFilterMinmaxProperties *properties =
1828 (VkPhysicalDeviceSamplerFilterMinmaxProperties *)ext;
1829 CORE_PROPERTY(1, 2, filterMinmaxImageComponentMapping);
1830 CORE_PROPERTY(1, 2, filterMinmaxSingleComponentFormats);
1831 break;
1832 }
1833 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1834 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1835 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1836
1837 /* Shader engines. */
1838 properties->shaderEngineCount =
1839 pdevice->rad_info.max_se;
1840 properties->shaderArraysPerEngineCount =
1841 pdevice->rad_info.max_sh_per_se;
1842 properties->computeUnitsPerShaderArray =
1843 pdevice->rad_info.min_good_cu_per_sa;
1844 properties->simdPerComputeUnit =
1845 pdevice->rad_info.num_simd_per_compute_unit;
1846 properties->wavefrontsPerSimd =
1847 pdevice->rad_info.max_wave64_per_simd;
1848 properties->wavefrontSize = 64;
1849
1850 /* SGPR. */
1851 properties->sgprsPerSimd =
1852 pdevice->rad_info.num_physical_sgprs_per_simd;
1853 properties->minSgprAllocation =
1854 pdevice->rad_info.min_sgpr_alloc;
1855 properties->maxSgprAllocation =
1856 pdevice->rad_info.max_sgpr_alloc;
1857 properties->sgprAllocationGranularity =
1858 pdevice->rad_info.sgpr_alloc_granularity;
1859
1860 /* VGPR. */
1861 properties->vgprsPerSimd =
1862 pdevice->rad_info.num_physical_wave64_vgprs_per_simd;
1863 properties->minVgprAllocation =
1864 pdevice->rad_info.min_wave64_vgpr_alloc;
1865 properties->maxVgprAllocation =
1866 pdevice->rad_info.max_vgpr_alloc;
1867 properties->vgprAllocationGranularity =
1868 pdevice->rad_info.wave64_vgpr_alloc_granularity;
1869 break;
1870 }
1871 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_2_AMD: {
1872 VkPhysicalDeviceShaderCoreProperties2AMD *properties =
1873 (VkPhysicalDeviceShaderCoreProperties2AMD *)ext;
1874
1875 properties->shaderCoreFeatures = 0;
1876 properties->activeComputeUnitCount =
1877 pdevice->rad_info.num_good_compute_units;
1878 break;
1879 }
1880 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1881 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1882 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1883 properties->maxVertexAttribDivisor = UINT32_MAX;
1884 break;
1885 }
1886 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES: {
1887 VkPhysicalDeviceDescriptorIndexingProperties *properties =
1888 (VkPhysicalDeviceDescriptorIndexingProperties*)ext;
1889 CORE_PROPERTY(1, 2, maxUpdateAfterBindDescriptorsInAllPools);
1890 CORE_PROPERTY(1, 2, shaderUniformBufferArrayNonUniformIndexingNative);
1891 CORE_PROPERTY(1, 2, shaderSampledImageArrayNonUniformIndexingNative);
1892 CORE_PROPERTY(1, 2, shaderStorageBufferArrayNonUniformIndexingNative);
1893 CORE_PROPERTY(1, 2, shaderStorageImageArrayNonUniformIndexingNative);
1894 CORE_PROPERTY(1, 2, shaderInputAttachmentArrayNonUniformIndexingNative);
1895 CORE_PROPERTY(1, 2, robustBufferAccessUpdateAfterBind);
1896 CORE_PROPERTY(1, 2, quadDivergentImplicitLod);
1897 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSamplers);
1898 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindUniformBuffers);
1899 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageBuffers);
1900 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSampledImages);
1901 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageImages);
1902 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindInputAttachments);
1903 CORE_PROPERTY(1, 2, maxPerStageUpdateAfterBindResources);
1904 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSamplers);
1905 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffers);
1906 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffersDynamic);
1907 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffers);
1908 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffersDynamic);
1909 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSampledImages);
1910 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageImages);
1911 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindInputAttachments);
1912 break;
1913 }
1914 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1915 VkPhysicalDeviceProtectedMemoryProperties *properties =
1916 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1917 CORE_PROPERTY(1, 1, protectedNoFault);
1918 break;
1919 }
1920 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1921 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1922 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1923 properties->primitiveOverestimationSize = 0;
1924 properties->maxExtraPrimitiveOverestimationSize = 0;
1925 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1926 properties->primitiveUnderestimation = false;
1927 properties->conservativePointAndLineRasterization = false;
1928 properties->degenerateTrianglesRasterized = false;
1929 properties->degenerateLinesRasterized = false;
1930 properties->fullyCoveredFragmentShaderInputVariable = false;
1931 properties->conservativeRasterizationPostDepthCoverage = false;
1932 break;
1933 }
1934 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1935 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1936 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1937 properties->pciDomain = pdevice->bus_info.domain;
1938 properties->pciBus = pdevice->bus_info.bus;
1939 properties->pciDevice = pdevice->bus_info.dev;
1940 properties->pciFunction = pdevice->bus_info.func;
1941 break;
1942 }
1943 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES: {
1944 VkPhysicalDeviceDriverProperties *properties =
1945 (VkPhysicalDeviceDriverProperties *) ext;
1946 CORE_PROPERTY(1, 2, driverID);
1947 CORE_PROPERTY(1, 2, driverName);
1948 CORE_PROPERTY(1, 2, driverInfo);
1949 CORE_PROPERTY(1, 2, conformanceVersion);
1950 break;
1951 }
1952 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1953 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1954 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1955 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1956 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1957 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1958 properties->maxTransformFeedbackStreamDataSize = 512;
1959 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1960 properties->maxTransformFeedbackBufferDataStride = 512;
1961 properties->transformFeedbackQueries = !pdevice->use_ngg_streamout;
1962 properties->transformFeedbackStreamsLinesTriangles = !pdevice->use_ngg_streamout;
1963 properties->transformFeedbackRasterizationStreamSelect = false;
1964 properties->transformFeedbackDraw = true;
1965 break;
1966 }
1967 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1968 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1969 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1970
1971 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1972 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1973 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1974 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1975 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1976 break;
1977 }
1978 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT: {
1979 VkPhysicalDeviceSampleLocationsPropertiesEXT *properties =
1980 (VkPhysicalDeviceSampleLocationsPropertiesEXT *)ext;
1981 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_2_BIT |
1982 VK_SAMPLE_COUNT_4_BIT |
1983 VK_SAMPLE_COUNT_8_BIT;
1984 properties->maxSampleLocationGridSize = (VkExtent2D){ 2 , 2 };
1985 properties->sampleLocationCoordinateRange[0] = 0.0f;
1986 properties->sampleLocationCoordinateRange[1] = 0.9375f;
1987 properties->sampleLocationSubPixelBits = 4;
1988 properties->variableSampleLocations = false;
1989 break;
1990 }
1991 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES: {
1992 VkPhysicalDeviceDepthStencilResolveProperties *properties =
1993 (VkPhysicalDeviceDepthStencilResolveProperties *)ext;
1994 CORE_PROPERTY(1, 2, supportedDepthResolveModes);
1995 CORE_PROPERTY(1, 2, supportedStencilResolveModes);
1996 CORE_PROPERTY(1, 2, independentResolveNone);
1997 CORE_PROPERTY(1, 2, independentResolve);
1998 break;
1999 }
2000 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_PROPERTIES_EXT: {
2001 VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT *properties =
2002 (VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT *)ext;
2003 properties->storageTexelBufferOffsetAlignmentBytes = 4;
2004 properties->storageTexelBufferOffsetSingleTexelAlignment = true;
2005 properties->uniformTexelBufferOffsetAlignmentBytes = 4;
2006 properties->uniformTexelBufferOffsetSingleTexelAlignment = true;
2007 break;
2008 }
2009 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT_CONTROLS_PROPERTIES : {
2010 VkPhysicalDeviceFloatControlsProperties *properties =
2011 (VkPhysicalDeviceFloatControlsProperties *)ext;
2012 CORE_PROPERTY(1, 2, denormBehaviorIndependence);
2013 CORE_PROPERTY(1, 2, roundingModeIndependence);
2014 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat16);
2015 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat16);
2016 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat16);
2017 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat16);
2018 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat16);
2019 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat32);
2020 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat32);
2021 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat32);
2022 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat32);
2023 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat32);
2024 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat64);
2025 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat64);
2026 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat64);
2027 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat64);
2028 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat64);
2029 break;
2030 }
2031 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_PROPERTIES: {
2032 VkPhysicalDeviceTimelineSemaphoreProperties *properties =
2033 (VkPhysicalDeviceTimelineSemaphoreProperties *) ext;
2034 CORE_PROPERTY(1, 2, maxTimelineSemaphoreValueDifference);
2035 break;
2036 }
2037 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_PROPERTIES_EXT: {
2038 VkPhysicalDeviceSubgroupSizeControlPropertiesEXT *props =
2039 (VkPhysicalDeviceSubgroupSizeControlPropertiesEXT *)ext;
2040 props->minSubgroupSize = 64;
2041 props->maxSubgroupSize = 64;
2042 props->maxComputeWorkgroupSubgroups = UINT32_MAX;
2043 props->requiredSubgroupSizeStages = 0;
2044
2045 if (pdevice->rad_info.chip_class >= GFX10) {
2046 /* Only GFX10+ supports wave32. */
2047 props->minSubgroupSize = 32;
2048 props->requiredSubgroupSizeStages = VK_SHADER_STAGE_COMPUTE_BIT;
2049 }
2050 break;
2051 }
2052 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES:
2053 radv_get_physical_device_properties_1_1(pdevice, (void *)ext);
2054 break;
2055 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES:
2056 radv_get_physical_device_properties_1_2(pdevice, (void *)ext);
2057 break;
2058 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_PROPERTIES_EXT: {
2059 VkPhysicalDeviceLineRasterizationPropertiesEXT *props =
2060 (VkPhysicalDeviceLineRasterizationPropertiesEXT *)ext;
2061 props->lineSubPixelPrecisionBits = 4;
2062 break;
2063 }
2064 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ROBUSTNESS_2_PROPERTIES_EXT: {
2065 VkPhysicalDeviceRobustness2PropertiesEXT *properties =
2066 (VkPhysicalDeviceRobustness2PropertiesEXT *)ext;
2067 properties->robustStorageBufferAccessSizeAlignment = 4;
2068 properties->robustUniformBufferAccessSizeAlignment = 4;
2069 break;
2070 }
2071 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_PROPERTIES_EXT: {
2072 VkPhysicalDeviceCustomBorderColorPropertiesEXT *props =
2073 (VkPhysicalDeviceCustomBorderColorPropertiesEXT *)ext;
2074 props->maxCustomBorderColorSamplers = RADV_BORDER_COLOR_COUNT;
2075 break;
2076 }
2077 default:
2078 break;
2079 }
2080 }
2081 }
2082
2083 static void radv_get_physical_device_queue_family_properties(
2084 struct radv_physical_device* pdevice,
2085 uint32_t* pCount,
2086 VkQueueFamilyProperties** pQueueFamilyProperties)
2087 {
2088 int num_queue_families = 1;
2089 int idx;
2090 if (pdevice->rad_info.num_rings[RING_COMPUTE] > 0 &&
2091 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
2092 num_queue_families++;
2093
2094 if (pQueueFamilyProperties == NULL) {
2095 *pCount = num_queue_families;
2096 return;
2097 }
2098
2099 if (!*pCount)
2100 return;
2101
2102 idx = 0;
2103 if (*pCount >= 1) {
2104 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
2105 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
2106 VK_QUEUE_COMPUTE_BIT |
2107 VK_QUEUE_TRANSFER_BIT |
2108 VK_QUEUE_SPARSE_BINDING_BIT,
2109 .queueCount = 1,
2110 .timestampValidBits = 64,
2111 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
2112 };
2113 idx++;
2114 }
2115
2116 if (pdevice->rad_info.num_rings[RING_COMPUTE] > 0 &&
2117 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
2118 if (*pCount > idx) {
2119 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
2120 .queueFlags = VK_QUEUE_COMPUTE_BIT |
2121 VK_QUEUE_TRANSFER_BIT |
2122 VK_QUEUE_SPARSE_BINDING_BIT,
2123 .queueCount = pdevice->rad_info.num_rings[RING_COMPUTE],
2124 .timestampValidBits = 64,
2125 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
2126 };
2127 idx++;
2128 }
2129 }
2130 *pCount = idx;
2131 }
2132
2133 void radv_GetPhysicalDeviceQueueFamilyProperties(
2134 VkPhysicalDevice physicalDevice,
2135 uint32_t* pCount,
2136 VkQueueFamilyProperties* pQueueFamilyProperties)
2137 {
2138 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
2139 if (!pQueueFamilyProperties) {
2140 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
2141 return;
2142 }
2143 VkQueueFamilyProperties *properties[] = {
2144 pQueueFamilyProperties + 0,
2145 pQueueFamilyProperties + 1,
2146 pQueueFamilyProperties + 2,
2147 };
2148 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
2149 assert(*pCount <= 3);
2150 }
2151
2152 void radv_GetPhysicalDeviceQueueFamilyProperties2(
2153 VkPhysicalDevice physicalDevice,
2154 uint32_t* pCount,
2155 VkQueueFamilyProperties2 *pQueueFamilyProperties)
2156 {
2157 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
2158 if (!pQueueFamilyProperties) {
2159 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
2160 return;
2161 }
2162 VkQueueFamilyProperties *properties[] = {
2163 &pQueueFamilyProperties[0].queueFamilyProperties,
2164 &pQueueFamilyProperties[1].queueFamilyProperties,
2165 &pQueueFamilyProperties[2].queueFamilyProperties,
2166 };
2167 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
2168 assert(*pCount <= 3);
2169 }
2170
2171 void radv_GetPhysicalDeviceMemoryProperties(
2172 VkPhysicalDevice physicalDevice,
2173 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
2174 {
2175 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2176
2177 *pMemoryProperties = physical_device->memory_properties;
2178 }
2179
2180 static void
2181 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
2182 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
2183 {
2184 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2185 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
2186 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
2187 uint64_t vram_size = radv_get_vram_size(device);
2188 uint64_t gtt_size = device->rad_info.gart_size;
2189 uint64_t heap_budget, heap_usage;
2190
2191 /* For all memory heaps, the computation of budget is as follow:
2192 * heap_budget = heap_size - global_heap_usage + app_heap_usage
2193 *
2194 * The Vulkan spec 1.1.97 says that the budget should include any
2195 * currently allocated device memory.
2196 *
2197 * Note that the application heap usages are not really accurate (eg.
2198 * in presence of shared buffers).
2199 */
2200 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
2201 uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;
2202
2203 if ((device->memory_domains[i] & RADEON_DOMAIN_VRAM) && (device->memory_flags[i] & RADEON_FLAG_NO_CPU_ACCESS)) {
2204 heap_usage = device->ws->query_value(device->ws,
2205 RADEON_ALLOCATED_VRAM);
2206
2207 heap_budget = vram_size -
2208 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
2209 heap_usage;
2210
2211 memoryBudget->heapBudget[heap_index] = heap_budget;
2212 memoryBudget->heapUsage[heap_index] = heap_usage;
2213 } else if (device->memory_domains[i] & RADEON_DOMAIN_VRAM) {
2214 heap_usage = device->ws->query_value(device->ws,
2215 RADEON_ALLOCATED_VRAM_VIS);
2216
2217 heap_budget = visible_vram_size -
2218 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
2219 heap_usage;
2220
2221 memoryBudget->heapBudget[heap_index] = heap_budget;
2222 memoryBudget->heapUsage[heap_index] = heap_usage;
2223 } else {
2224 assert(device->memory_domains[i] & RADEON_DOMAIN_GTT);
2225
2226 heap_usage = device->ws->query_value(device->ws,
2227 RADEON_ALLOCATED_GTT);
2228
2229 heap_budget = gtt_size -
2230 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
2231 heap_usage;
2232
2233 memoryBudget->heapBudget[heap_index] = heap_budget;
2234 memoryBudget->heapUsage[heap_index] = heap_usage;
2235 }
2236 }
2237
2238 /* The heapBudget and heapUsage values must be zero for array elements
2239 * greater than or equal to
2240 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
2241 */
2242 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
2243 memoryBudget->heapBudget[i] = 0;
2244 memoryBudget->heapUsage[i] = 0;
2245 }
2246 }
2247
2248 void radv_GetPhysicalDeviceMemoryProperties2(
2249 VkPhysicalDevice physicalDevice,
2250 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
2251 {
2252 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
2253 &pMemoryProperties->memoryProperties);
2254
2255 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
2256 vk_find_struct(pMemoryProperties->pNext,
2257 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
2258 if (memory_budget)
2259 radv_get_memory_budget_properties(physicalDevice, memory_budget);
2260 }
2261
2262 VkResult radv_GetMemoryHostPointerPropertiesEXT(
2263 VkDevice _device,
2264 VkExternalMemoryHandleTypeFlagBits handleType,
2265 const void *pHostPointer,
2266 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
2267 {
2268 RADV_FROM_HANDLE(radv_device, device, _device);
2269
2270 switch (handleType)
2271 {
2272 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
2273 const struct radv_physical_device *physical_device = device->physical_device;
2274 uint32_t memoryTypeBits = 0;
2275 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
2276 if (physical_device->memory_domains[i] == RADEON_DOMAIN_GTT &&
2277 !(physical_device->memory_flags[i] & RADEON_FLAG_GTT_WC)) {
2278 memoryTypeBits = (1 << i);
2279 break;
2280 }
2281 }
2282 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
2283 return VK_SUCCESS;
2284 }
2285 default:
2286 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
2287 }
2288 }
2289
2290 static enum radeon_ctx_priority
2291 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
2292 {
2293 /* Default to MEDIUM when a specific global priority isn't requested */
2294 if (!pObj)
2295 return RADEON_CTX_PRIORITY_MEDIUM;
2296
2297 switch(pObj->globalPriority) {
2298 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
2299 return RADEON_CTX_PRIORITY_REALTIME;
2300 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
2301 return RADEON_CTX_PRIORITY_HIGH;
2302 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
2303 return RADEON_CTX_PRIORITY_MEDIUM;
2304 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
2305 return RADEON_CTX_PRIORITY_LOW;
2306 default:
2307 unreachable("Illegal global priority value");
2308 return RADEON_CTX_PRIORITY_INVALID;
2309 }
2310 }
2311
2312 static int
2313 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
2314 uint32_t queue_family_index, int idx,
2315 VkDeviceQueueCreateFlags flags,
2316 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
2317 {
2318 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2319 queue->device = device;
2320 queue->queue_family_index = queue_family_index;
2321 queue->queue_idx = idx;
2322 queue->priority = radv_get_queue_global_priority(global_priority);
2323 queue->flags = flags;
2324 queue->hw_ctx = NULL;
2325
2326 VkResult result = device->ws->ctx_create(device->ws, queue->priority, &queue->hw_ctx);
2327 if (result != VK_SUCCESS)
2328 return vk_error(device->instance, result);
2329
2330 list_inithead(&queue->pending_submissions);
2331 pthread_mutex_init(&queue->pending_mutex, NULL);
2332
2333 pthread_mutex_init(&queue->thread_mutex, NULL);
2334 queue->thread_submission = NULL;
2335 queue->thread_running = queue->thread_exit = false;
2336 result = radv_create_pthread_cond(&queue->thread_cond);
2337 if (result != VK_SUCCESS)
2338 return vk_error(device->instance, result);
2339
2340 return VK_SUCCESS;
2341 }
2342
2343 static void
2344 radv_queue_finish(struct radv_queue *queue)
2345 {
2346 if (queue->thread_running) {
2347 p_atomic_set(&queue->thread_exit, true);
2348 pthread_cond_broadcast(&queue->thread_cond);
2349 pthread_join(queue->submission_thread, NULL);
2350 }
2351 pthread_cond_destroy(&queue->thread_cond);
2352 pthread_mutex_destroy(&queue->pending_mutex);
2353 pthread_mutex_destroy(&queue->thread_mutex);
2354
2355 if (queue->hw_ctx)
2356 queue->device->ws->ctx_destroy(queue->hw_ctx);
2357
2358 if (queue->initial_full_flush_preamble_cs)
2359 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2360 if (queue->initial_preamble_cs)
2361 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2362 if (queue->continue_preamble_cs)
2363 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2364 if (queue->descriptor_bo)
2365 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2366 if (queue->scratch_bo)
2367 queue->device->ws->buffer_destroy(queue->scratch_bo);
2368 if (queue->esgs_ring_bo)
2369 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2370 if (queue->gsvs_ring_bo)
2371 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2372 if (queue->tess_rings_bo)
2373 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
2374 if (queue->gds_bo)
2375 queue->device->ws->buffer_destroy(queue->gds_bo);
2376 if (queue->gds_oa_bo)
2377 queue->device->ws->buffer_destroy(queue->gds_oa_bo);
2378 if (queue->compute_scratch_bo)
2379 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2380 }
2381
2382 static void
2383 radv_bo_list_init(struct radv_bo_list *bo_list)
2384 {
2385 pthread_mutex_init(&bo_list->mutex, NULL);
2386 bo_list->list.count = bo_list->capacity = 0;
2387 bo_list->list.bos = NULL;
2388 }
2389
2390 static void
2391 radv_bo_list_finish(struct radv_bo_list *bo_list)
2392 {
2393 free(bo_list->list.bos);
2394 pthread_mutex_destroy(&bo_list->mutex);
2395 }
2396
2397 VkResult radv_bo_list_add(struct radv_device *device,
2398 struct radeon_winsys_bo *bo)
2399 {
2400 struct radv_bo_list *bo_list = &device->bo_list;
2401
2402 if (bo->is_local)
2403 return VK_SUCCESS;
2404
2405 if (unlikely(!device->use_global_bo_list))
2406 return VK_SUCCESS;
2407
2408 pthread_mutex_lock(&bo_list->mutex);
2409 if (bo_list->list.count == bo_list->capacity) {
2410 unsigned capacity = MAX2(4, bo_list->capacity * 2);
2411 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
2412
2413 if (!data) {
2414 pthread_mutex_unlock(&bo_list->mutex);
2415 return VK_ERROR_OUT_OF_HOST_MEMORY;
2416 }
2417
2418 bo_list->list.bos = (struct radeon_winsys_bo**)data;
2419 bo_list->capacity = capacity;
2420 }
2421
2422 bo_list->list.bos[bo_list->list.count++] = bo;
2423 pthread_mutex_unlock(&bo_list->mutex);
2424 return VK_SUCCESS;
2425 }
2426
2427 void radv_bo_list_remove(struct radv_device *device,
2428 struct radeon_winsys_bo *bo)
2429 {
2430 struct radv_bo_list *bo_list = &device->bo_list;
2431
2432 if (bo->is_local)
2433 return;
2434
2435 if (unlikely(!device->use_global_bo_list))
2436 return;
2437
2438 pthread_mutex_lock(&bo_list->mutex);
2439 /* Loop the list backwards so we find the most recently added
2440 * memory first. */
2441 for(unsigned i = bo_list->list.count; i-- > 0;) {
2442 if (bo_list->list.bos[i] == bo) {
2443 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
2444 --bo_list->list.count;
2445 break;
2446 }
2447 }
2448 pthread_mutex_unlock(&bo_list->mutex);
2449 }
2450
2451 static void
2452 radv_device_init_gs_info(struct radv_device *device)
2453 {
2454 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
2455 device->physical_device->rad_info.family);
2456 }
2457
2458 static int radv_get_device_extension_index(const char *name)
2459 {
2460 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
2461 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
2462 return i;
2463 }
2464 return -1;
2465 }
2466
2467 static int
2468 radv_get_int_debug_option(const char *name, int default_value)
2469 {
2470 const char *str;
2471 int result;
2472
2473 str = getenv(name);
2474 if (!str) {
2475 result = default_value;
2476 } else {
2477 char *endptr;
2478
2479 result = strtol(str, &endptr, 0);
2480 if (str == endptr) {
2481 /* No digits founs. */
2482 result = default_value;
2483 }
2484 }
2485
2486 return result;
2487 }
2488
2489 static bool radv_thread_trace_enabled()
2490 {
2491 return radv_get_int_debug_option("RADV_THREAD_TRACE", -1) >= 0 ||
2492 getenv("RADV_THREAD_TRACE_TRIGGER");
2493 }
2494
2495 static void
2496 radv_device_init_dispatch(struct radv_device *device)
2497 {
2498 const struct radv_instance *instance = device->physical_device->instance;
2499 const struct radv_device_dispatch_table *dispatch_table_layer = NULL;
2500 bool unchecked = instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS;
2501
2502 if (radv_thread_trace_enabled()) {
2503 /* Use device entrypoints from the SQTT layer if enabled. */
2504 dispatch_table_layer = &sqtt_device_dispatch_table;
2505 }
2506
2507 for (unsigned i = 0; i < ARRAY_SIZE(device->dispatch.entrypoints); i++) {
2508 /* Vulkan requires that entrypoints for extensions which have not been
2509 * enabled must not be advertised.
2510 */
2511 if (!unchecked &&
2512 !radv_device_entrypoint_is_enabled(i, instance->apiVersion,
2513 &instance->enabled_extensions,
2514 &device->enabled_extensions)) {
2515 device->dispatch.entrypoints[i] = NULL;
2516 } else if (dispatch_table_layer &&
2517 dispatch_table_layer->entrypoints[i]) {
2518 device->dispatch.entrypoints[i] =
2519 dispatch_table_layer->entrypoints[i];
2520 } else {
2521 device->dispatch.entrypoints[i] =
2522 radv_device_dispatch_table.entrypoints[i];
2523 }
2524 }
2525 }
2526
2527 static VkResult
2528 radv_create_pthread_cond(pthread_cond_t *cond)
2529 {
2530 pthread_condattr_t condattr;
2531 if (pthread_condattr_init(&condattr)) {
2532 return VK_ERROR_INITIALIZATION_FAILED;
2533 }
2534
2535 if (pthread_condattr_setclock(&condattr, CLOCK_MONOTONIC)) {
2536 pthread_condattr_destroy(&condattr);
2537 return VK_ERROR_INITIALIZATION_FAILED;
2538 }
2539 if (pthread_cond_init(cond, &condattr)) {
2540 pthread_condattr_destroy(&condattr);
2541 return VK_ERROR_INITIALIZATION_FAILED;
2542 }
2543 pthread_condattr_destroy(&condattr);
2544 return VK_SUCCESS;
2545 }
2546
2547 static VkResult
2548 check_physical_device_features(VkPhysicalDevice physicalDevice,
2549 const VkPhysicalDeviceFeatures *features)
2550 {
2551 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2552 VkPhysicalDeviceFeatures supported_features;
2553 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
2554 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
2555 VkBool32 *enabled_feature = (VkBool32 *)features;
2556 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
2557 for (uint32_t i = 0; i < num_features; i++) {
2558 if (enabled_feature[i] && !supported_feature[i])
2559 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
2560 }
2561
2562 return VK_SUCCESS;
2563 }
2564
2565 static VkResult radv_device_init_border_color(struct radv_device *device)
2566 {
2567 device->border_color_data.bo =
2568 device->ws->buffer_create(device->ws,
2569 RADV_BORDER_COLOR_BUFFER_SIZE,
2570 4096,
2571 RADEON_DOMAIN_VRAM,
2572 RADEON_FLAG_CPU_ACCESS |
2573 RADEON_FLAG_READ_ONLY |
2574 RADEON_FLAG_NO_INTERPROCESS_SHARING,
2575 RADV_BO_PRIORITY_SHADER);
2576
2577 if (device->border_color_data.bo == NULL)
2578 return vk_error(device->physical_device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2579
2580 device->border_color_data.colors_gpu_ptr =
2581 device->ws->buffer_map(device->border_color_data.bo);
2582 if (!device->border_color_data.colors_gpu_ptr)
2583 return vk_error(device->physical_device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2584 pthread_mutex_init(&device->border_color_data.mutex, NULL);
2585
2586 return VK_SUCCESS;
2587 }
2588
2589 static void radv_device_finish_border_color(struct radv_device *device)
2590 {
2591 if (device->border_color_data.bo) {
2592 device->ws->buffer_destroy(device->border_color_data.bo);
2593
2594 pthread_mutex_destroy(&device->border_color_data.mutex);
2595 }
2596 }
2597
2598 VkResult
2599 _radv_device_set_lost(struct radv_device *device,
2600 const char *file, int line,
2601 const char *msg, ...)
2602 {
2603 VkResult err;
2604 va_list ap;
2605
2606 p_atomic_inc(&device->lost);
2607
2608 va_start(ap, msg);
2609 err = __vk_errorv(device->physical_device->instance, device,
2610 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT,
2611 VK_ERROR_DEVICE_LOST, file, line, msg, ap);
2612 va_end(ap);
2613
2614 return err;
2615 }
2616
2617 VkResult radv_CreateDevice(
2618 VkPhysicalDevice physicalDevice,
2619 const VkDeviceCreateInfo* pCreateInfo,
2620 const VkAllocationCallbacks* pAllocator,
2621 VkDevice* pDevice)
2622 {
2623 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2624 VkResult result;
2625 struct radv_device *device;
2626
2627 bool keep_shader_info = false;
2628 bool robust_buffer_access = false;
2629 bool overallocation_disallowed = false;
2630 bool custom_border_colors = false;
2631
2632 /* Check enabled features */
2633 if (pCreateInfo->pEnabledFeatures) {
2634 result = check_physical_device_features(physicalDevice,
2635 pCreateInfo->pEnabledFeatures);
2636 if (result != VK_SUCCESS)
2637 return result;
2638
2639 if (pCreateInfo->pEnabledFeatures->robustBufferAccess)
2640 robust_buffer_access = true;
2641 }
2642
2643 vk_foreach_struct_const(ext, pCreateInfo->pNext) {
2644 switch (ext->sType) {
2645 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FEATURES_2: {
2646 const VkPhysicalDeviceFeatures2 *features = (const void *)ext;
2647 result = check_physical_device_features(physicalDevice,
2648 &features->features);
2649 if (result != VK_SUCCESS)
2650 return result;
2651
2652 if (features->features.robustBufferAccess)
2653 robust_buffer_access = true;
2654 break;
2655 }
2656 case VK_STRUCTURE_TYPE_DEVICE_MEMORY_OVERALLOCATION_CREATE_INFO_AMD: {
2657 const VkDeviceMemoryOverallocationCreateInfoAMD *overallocation = (const void *)ext;
2658 if (overallocation->overallocationBehavior == VK_MEMORY_OVERALLOCATION_BEHAVIOR_DISALLOWED_AMD)
2659 overallocation_disallowed = true;
2660 break;
2661 }
2662 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_FEATURES_EXT: {
2663 const VkPhysicalDeviceCustomBorderColorFeaturesEXT *border_color_features = (const void *)ext;
2664 custom_border_colors = border_color_features->customBorderColors;
2665 break;
2666 }
2667 default:
2668 break;
2669 }
2670 }
2671
2672 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
2673 sizeof(*device), 8,
2674 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2675 if (!device)
2676 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2677
2678 vk_device_init(&device->vk, pCreateInfo,
2679 &physical_device->instance->alloc, pAllocator);
2680
2681 device->instance = physical_device->instance;
2682 device->physical_device = physical_device;
2683
2684 device->ws = physical_device->ws;
2685
2686 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
2687 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
2688 int index = radv_get_device_extension_index(ext_name);
2689 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
2690 vk_free(&device->vk.alloc, device);
2691 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
2692 }
2693
2694 device->enabled_extensions.extensions[index] = true;
2695 }
2696
2697 radv_device_init_dispatch(device);
2698
2699 keep_shader_info = device->enabled_extensions.AMD_shader_info;
2700
2701 /* With update after bind we can't attach bo's to the command buffer
2702 * from the descriptor set anymore, so we have to use a global BO list.
2703 */
2704 device->use_global_bo_list =
2705 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
2706 device->enabled_extensions.EXT_descriptor_indexing ||
2707 device->enabled_extensions.EXT_buffer_device_address ||
2708 device->enabled_extensions.KHR_buffer_device_address;
2709
2710 device->robust_buffer_access = robust_buffer_access;
2711
2712 mtx_init(&device->shader_slab_mutex, mtx_plain);
2713 list_inithead(&device->shader_slabs);
2714
2715 device->overallocation_disallowed = overallocation_disallowed;
2716 mtx_init(&device->overallocation_mutex, mtx_plain);
2717
2718 radv_bo_list_init(&device->bo_list);
2719
2720 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
2721 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
2722 uint32_t qfi = queue_create->queueFamilyIndex;
2723 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
2724 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
2725
2726 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
2727
2728 device->queues[qfi] = vk_alloc(&device->vk.alloc,
2729 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2730 if (!device->queues[qfi]) {
2731 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2732 goto fail;
2733 }
2734
2735 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
2736
2737 device->queue_count[qfi] = queue_create->queueCount;
2738
2739 for (unsigned q = 0; q < queue_create->queueCount; q++) {
2740 result = radv_queue_init(device, &device->queues[qfi][q],
2741 qfi, q, queue_create->flags,
2742 global_priority);
2743 if (result != VK_SUCCESS)
2744 goto fail;
2745 }
2746 }
2747
2748 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
2749 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
2750
2751 /* Disable DFSM by default. As of 2019-09-15 Talos on Low is still 3% slower on Raven. */
2752 device->dfsm_allowed = device->pbb_allowed &&
2753 (device->instance->perftest_flags & RADV_PERFTEST_DFSM);
2754
2755 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
2756
2757 /* The maximum number of scratch waves. Scratch space isn't divided
2758 * evenly between CUs. The number is only a function of the number of CUs.
2759 * We can decrease the constant to decrease the scratch buffer size.
2760 *
2761 * sctx->scratch_waves must be >= the maximum possible size of
2762 * 1 threadgroup, so that the hw doesn't hang from being unable
2763 * to start any.
2764 *
2765 * The recommended value is 4 per CU at most. Higher numbers don't
2766 * bring much benefit, but they still occupy chip resources (think
2767 * async compute). I've seen ~2% performance difference between 4 and 32.
2768 */
2769 uint32_t max_threads_per_block = 2048;
2770 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
2771 max_threads_per_block / 64);
2772
2773 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
2774
2775 if (device->physical_device->rad_info.chip_class >= GFX7) {
2776 /* If the KMD allows it (there is a KMD hw register for it),
2777 * allow launching waves out-of-order.
2778 */
2779 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
2780 }
2781
2782 radv_device_init_gs_info(device);
2783
2784 device->tess_offchip_block_dw_size =
2785 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
2786
2787 if (getenv("RADV_TRACE_FILE")) {
2788 const char *filename = getenv("RADV_TRACE_FILE");
2789
2790 keep_shader_info = true;
2791
2792 if (!radv_init_trace(device))
2793 goto fail;
2794
2795 fprintf(stderr, "*****************************************************************************\n");
2796 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
2797 fprintf(stderr, "*****************************************************************************\n");
2798
2799 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
2800
2801 /* Wait for idle after every draw/dispatch to identify the
2802 * first bad call.
2803 */
2804 device->instance->debug_flags |= RADV_DEBUG_SYNC_SHADERS;
2805
2806 radv_dump_enabled_options(device, stderr);
2807 }
2808
2809 if (radv_thread_trace_enabled()) {
2810 fprintf(stderr, "*************************************************\n");
2811 fprintf(stderr, "* WARNING: Thread trace support is experimental *\n");
2812 fprintf(stderr, "*************************************************\n");
2813
2814 if (device->physical_device->rad_info.chip_class < GFX8) {
2815 fprintf(stderr, "GPU hardware not supported: refer to "
2816 "the RGP documentation for the list of "
2817 "supported GPUs!\n");
2818 abort();
2819 }
2820
2821 /* Default buffer size set to 1MB per SE. */
2822 device->thread_trace_buffer_size =
2823 radv_get_int_debug_option("RADV_THREAD_TRACE_BUFFER_SIZE", 1024 * 1024);
2824 device->thread_trace_start_frame = radv_get_int_debug_option("RADV_THREAD_TRACE", -1);
2825
2826 const char *trigger_file = getenv("RADV_THREAD_TRACE_TRIGGER");
2827 if (trigger_file)
2828 device->thread_trace_trigger_file = strdup(trigger_file);
2829
2830 if (!radv_thread_trace_init(device))
2831 goto fail;
2832 }
2833
2834 if (getenv("RADV_TRAP_HANDLER")) {
2835 /* TODO: Add support for more hardware. */
2836 assert(device->physical_device->rad_info.chip_class == GFX8);
2837
2838 fprintf(stderr, "**********************************************************************\n");
2839 fprintf(stderr, "* WARNING: RADV_TRAP_HANDLER is experimental and only for debugging! *\n");
2840 fprintf(stderr, "**********************************************************************\n");
2841
2842 /* To get the disassembly of the faulty shaders, we have to
2843 * keep some shader info around.
2844 */
2845 keep_shader_info = true;
2846
2847 if (!radv_trap_handler_init(device))
2848 goto fail;
2849 }
2850
2851 device->keep_shader_info = keep_shader_info;
2852 result = radv_device_init_meta(device);
2853 if (result != VK_SUCCESS)
2854 goto fail;
2855
2856 radv_device_init_msaa(device);
2857
2858 /* If the border color extension is enabled, let's create the buffer we need. */
2859 if (custom_border_colors) {
2860 result = radv_device_init_border_color(device);
2861 if (result != VK_SUCCESS)
2862 goto fail;
2863 }
2864
2865 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
2866 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
2867 if (!device->empty_cs[family])
2868 goto fail;
2869
2870 switch (family) {
2871 case RADV_QUEUE_GENERAL:
2872 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2873 radeon_emit(device->empty_cs[family], CC0_UPDATE_LOAD_ENABLES(1));
2874 radeon_emit(device->empty_cs[family], CC1_UPDATE_SHADOW_ENABLES(1));
2875 break;
2876 case RADV_QUEUE_COMPUTE:
2877 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
2878 radeon_emit(device->empty_cs[family], 0);
2879 break;
2880 }
2881
2882 result = device->ws->cs_finalize(device->empty_cs[family]);
2883 if (result != VK_SUCCESS)
2884 goto fail;
2885 }
2886
2887 if (device->physical_device->rad_info.chip_class >= GFX7)
2888 cik_create_gfx_config(device);
2889
2890 VkPipelineCacheCreateInfo ci;
2891 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
2892 ci.pNext = NULL;
2893 ci.flags = 0;
2894 ci.pInitialData = NULL;
2895 ci.initialDataSize = 0;
2896 VkPipelineCache pc;
2897 result = radv_CreatePipelineCache(radv_device_to_handle(device),
2898 &ci, NULL, &pc);
2899 if (result != VK_SUCCESS)
2900 goto fail_meta;
2901
2902 device->mem_cache = radv_pipeline_cache_from_handle(pc);
2903
2904 result = radv_create_pthread_cond(&device->timeline_cond);
2905 if (result != VK_SUCCESS)
2906 goto fail_mem_cache;
2907
2908 device->force_aniso =
2909 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
2910 if (device->force_aniso >= 0) {
2911 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
2912 1 << util_logbase2(device->force_aniso));
2913 }
2914
2915 *pDevice = radv_device_to_handle(device);
2916 return VK_SUCCESS;
2917
2918 fail_mem_cache:
2919 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2920 fail_meta:
2921 radv_device_finish_meta(device);
2922 fail:
2923 radv_bo_list_finish(&device->bo_list);
2924
2925 radv_thread_trace_finish(device);
2926 free(device->thread_trace_trigger_file);
2927
2928 radv_trap_handler_finish(device);
2929
2930 if (device->trace_bo)
2931 device->ws->buffer_destroy(device->trace_bo);
2932
2933 if (device->gfx_init)
2934 device->ws->buffer_destroy(device->gfx_init);
2935
2936 radv_device_finish_border_color(device);
2937
2938 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2939 for (unsigned q = 0; q < device->queue_count[i]; q++)
2940 radv_queue_finish(&device->queues[i][q]);
2941 if (device->queue_count[i])
2942 vk_free(&device->vk.alloc, device->queues[i]);
2943 }
2944
2945 vk_free(&device->vk.alloc, device);
2946 return result;
2947 }
2948
2949 void radv_DestroyDevice(
2950 VkDevice _device,
2951 const VkAllocationCallbacks* pAllocator)
2952 {
2953 RADV_FROM_HANDLE(radv_device, device, _device);
2954
2955 if (!device)
2956 return;
2957
2958 if (device->trace_bo)
2959 device->ws->buffer_destroy(device->trace_bo);
2960
2961 if (device->gfx_init)
2962 device->ws->buffer_destroy(device->gfx_init);
2963
2964 radv_device_finish_border_color(device);
2965
2966 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2967 for (unsigned q = 0; q < device->queue_count[i]; q++)
2968 radv_queue_finish(&device->queues[i][q]);
2969 if (device->queue_count[i])
2970 vk_free(&device->vk.alloc, device->queues[i]);
2971 if (device->empty_cs[i])
2972 device->ws->cs_destroy(device->empty_cs[i]);
2973 }
2974 radv_device_finish_meta(device);
2975
2976 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
2977 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2978
2979 radv_trap_handler_finish(device);
2980
2981 radv_destroy_shader_slabs(device);
2982
2983 pthread_cond_destroy(&device->timeline_cond);
2984 radv_bo_list_finish(&device->bo_list);
2985
2986 free(device->thread_trace_trigger_file);
2987 radv_thread_trace_finish(device);
2988
2989 vk_free(&device->vk.alloc, device);
2990 }
2991
2992 VkResult radv_EnumerateInstanceLayerProperties(
2993 uint32_t* pPropertyCount,
2994 VkLayerProperties* pProperties)
2995 {
2996 if (pProperties == NULL) {
2997 *pPropertyCount = 0;
2998 return VK_SUCCESS;
2999 }
3000
3001 /* None supported at this time */
3002 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
3003 }
3004
3005 VkResult radv_EnumerateDeviceLayerProperties(
3006 VkPhysicalDevice physicalDevice,
3007 uint32_t* pPropertyCount,
3008 VkLayerProperties* pProperties)
3009 {
3010 if (pProperties == NULL) {
3011 *pPropertyCount = 0;
3012 return VK_SUCCESS;
3013 }
3014
3015 /* None supported at this time */
3016 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
3017 }
3018
3019 void radv_GetDeviceQueue2(
3020 VkDevice _device,
3021 const VkDeviceQueueInfo2* pQueueInfo,
3022 VkQueue* pQueue)
3023 {
3024 RADV_FROM_HANDLE(radv_device, device, _device);
3025 struct radv_queue *queue;
3026
3027 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
3028 if (pQueueInfo->flags != queue->flags) {
3029 /* From the Vulkan 1.1.70 spec:
3030 *
3031 * "The queue returned by vkGetDeviceQueue2 must have the same
3032 * flags value from this structure as that used at device
3033 * creation time in a VkDeviceQueueCreateInfo instance. If no
3034 * matching flags were specified at device creation time then
3035 * pQueue will return VK_NULL_HANDLE."
3036 */
3037 *pQueue = VK_NULL_HANDLE;
3038 return;
3039 }
3040
3041 *pQueue = radv_queue_to_handle(queue);
3042 }
3043
3044 void radv_GetDeviceQueue(
3045 VkDevice _device,
3046 uint32_t queueFamilyIndex,
3047 uint32_t queueIndex,
3048 VkQueue* pQueue)
3049 {
3050 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
3051 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
3052 .queueFamilyIndex = queueFamilyIndex,
3053 .queueIndex = queueIndex
3054 };
3055
3056 radv_GetDeviceQueue2(_device, &info, pQueue);
3057 }
3058
3059 static void
3060 fill_geom_tess_rings(struct radv_queue *queue,
3061 uint32_t *map,
3062 bool add_sample_positions,
3063 uint32_t esgs_ring_size,
3064 struct radeon_winsys_bo *esgs_ring_bo,
3065 uint32_t gsvs_ring_size,
3066 struct radeon_winsys_bo *gsvs_ring_bo,
3067 uint32_t tess_factor_ring_size,
3068 uint32_t tess_offchip_ring_offset,
3069 uint32_t tess_offchip_ring_size,
3070 struct radeon_winsys_bo *tess_rings_bo)
3071 {
3072 uint32_t *desc = &map[4];
3073
3074 if (esgs_ring_bo) {
3075 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
3076
3077 /* stride 0, num records - size, add tid, swizzle, elsize4,
3078 index stride 64 */
3079 desc[0] = esgs_va;
3080 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
3081 S_008F04_SWIZZLE_ENABLE(true);
3082 desc[2] = esgs_ring_size;
3083 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3084 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3085 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3086 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
3087 S_008F0C_INDEX_STRIDE(3) |
3088 S_008F0C_ADD_TID_ENABLE(1);
3089
3090 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3091 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3092 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3093 S_008F0C_RESOURCE_LEVEL(1);
3094 } else {
3095 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3096 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
3097 S_008F0C_ELEMENT_SIZE(1);
3098 }
3099
3100 /* GS entry for ES->GS ring */
3101 /* stride 0, num records - size, elsize0,
3102 index stride 0 */
3103 desc[4] = esgs_va;
3104 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32);
3105 desc[6] = esgs_ring_size;
3106 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3107 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3108 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3109 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3110
3111 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3112 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3113 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3114 S_008F0C_RESOURCE_LEVEL(1);
3115 } else {
3116 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3117 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3118 }
3119 }
3120
3121 desc += 8;
3122
3123 if (gsvs_ring_bo) {
3124 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
3125
3126 /* VS entry for GS->VS ring */
3127 /* stride 0, num records - size, elsize0,
3128 index stride 0 */
3129 desc[0] = gsvs_va;
3130 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32);
3131 desc[2] = gsvs_ring_size;
3132 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3133 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3134 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3135 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3136
3137 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3138 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3139 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3140 S_008F0C_RESOURCE_LEVEL(1);
3141 } else {
3142 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3143 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3144 }
3145
3146 /* stride gsvs_itemsize, num records 64
3147 elsize 4, index stride 16 */
3148 /* shader will patch stride and desc[2] */
3149 desc[4] = gsvs_va;
3150 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32) |
3151 S_008F04_SWIZZLE_ENABLE(1);
3152 desc[6] = 0;
3153 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3154 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3155 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3156 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
3157 S_008F0C_INDEX_STRIDE(1) |
3158 S_008F0C_ADD_TID_ENABLE(true);
3159
3160 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3161 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3162 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3163 S_008F0C_RESOURCE_LEVEL(1);
3164 } else {
3165 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3166 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
3167 S_008F0C_ELEMENT_SIZE(1);
3168 }
3169
3170 }
3171
3172 desc += 8;
3173
3174 if (tess_rings_bo) {
3175 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
3176 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
3177
3178 desc[0] = tess_va;
3179 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32);
3180 desc[2] = tess_factor_ring_size;
3181 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3182 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3183 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3184 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3185
3186 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3187 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3188 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3189 S_008F0C_RESOURCE_LEVEL(1);
3190 } else {
3191 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3192 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3193 }
3194
3195 desc[4] = tess_offchip_va;
3196 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32);
3197 desc[6] = tess_offchip_ring_size;
3198 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3199 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3200 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3201 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3202
3203 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3204 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3205 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3206 S_008F0C_RESOURCE_LEVEL(1);
3207 } else {
3208 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3209 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3210 }
3211 }
3212
3213 desc += 8;
3214
3215 if (add_sample_positions) {
3216 /* add sample positions after all rings */
3217 memcpy(desc, queue->device->sample_locations_1x, 8);
3218 desc += 2;
3219 memcpy(desc, queue->device->sample_locations_2x, 16);
3220 desc += 4;
3221 memcpy(desc, queue->device->sample_locations_4x, 32);
3222 desc += 8;
3223 memcpy(desc, queue->device->sample_locations_8x, 64);
3224 }
3225 }
3226
3227 static unsigned
3228 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
3229 {
3230 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 &&
3231 device->physical_device->rad_info.family != CHIP_CARRIZO &&
3232 device->physical_device->rad_info.family != CHIP_STONEY;
3233 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
3234 unsigned max_offchip_buffers;
3235 unsigned offchip_granularity;
3236 unsigned hs_offchip_param;
3237
3238 /*
3239 * Per RadeonSI:
3240 * This must be one less than the maximum number due to a hw limitation.
3241 * Various hardware bugs need thGFX7
3242 *
3243 * Per AMDVLK:
3244 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
3245 * Gfx7 should limit max_offchip_buffers to 508
3246 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
3247 *
3248 * Follow AMDVLK here.
3249 */
3250 if (device->physical_device->rad_info.chip_class >= GFX10) {
3251 max_offchip_buffers_per_se = 256;
3252 } else if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
3253 device->physical_device->rad_info.chip_class == GFX7 ||
3254 device->physical_device->rad_info.chip_class == GFX6)
3255 --max_offchip_buffers_per_se;
3256
3257 max_offchip_buffers = max_offchip_buffers_per_se *
3258 device->physical_device->rad_info.max_se;
3259
3260 /* Hawaii has a bug with offchip buffers > 256 that can be worked
3261 * around by setting 4K granularity.
3262 */
3263 if (device->tess_offchip_block_dw_size == 4096) {
3264 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
3265 offchip_granularity = V_03093C_X_4K_DWORDS;
3266 } else {
3267 assert(device->tess_offchip_block_dw_size == 8192);
3268 offchip_granularity = V_03093C_X_8K_DWORDS;
3269 }
3270
3271 switch (device->physical_device->rad_info.chip_class) {
3272 case GFX6:
3273 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
3274 break;
3275 case GFX7:
3276 case GFX8:
3277 case GFX9:
3278 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
3279 break;
3280 case GFX10:
3281 break;
3282 default:
3283 break;
3284 }
3285
3286 *max_offchip_buffers_p = max_offchip_buffers;
3287 if (device->physical_device->rad_info.chip_class >= GFX10_3) {
3288 hs_offchip_param = S_03093C_OFFCHIP_BUFFERING_GFX103(max_offchip_buffers - 1) |
3289 S_03093C_OFFCHIP_GRANULARITY_GFX103(offchip_granularity);
3290 } else if (device->physical_device->rad_info.chip_class >= GFX7) {
3291 if (device->physical_device->rad_info.chip_class >= GFX8)
3292 --max_offchip_buffers;
3293 hs_offchip_param =
3294 S_03093C_OFFCHIP_BUFFERING_GFX7(max_offchip_buffers) |
3295 S_03093C_OFFCHIP_GRANULARITY_GFX7(offchip_granularity);
3296 } else {
3297 hs_offchip_param =
3298 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
3299 }
3300 return hs_offchip_param;
3301 }
3302
3303 static void
3304 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3305 struct radeon_winsys_bo *esgs_ring_bo,
3306 uint32_t esgs_ring_size,
3307 struct radeon_winsys_bo *gsvs_ring_bo,
3308 uint32_t gsvs_ring_size)
3309 {
3310 if (!esgs_ring_bo && !gsvs_ring_bo)
3311 return;
3312
3313 if (esgs_ring_bo)
3314 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
3315
3316 if (gsvs_ring_bo)
3317 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
3318
3319 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
3320 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
3321 radeon_emit(cs, esgs_ring_size >> 8);
3322 radeon_emit(cs, gsvs_ring_size >> 8);
3323 } else {
3324 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
3325 radeon_emit(cs, esgs_ring_size >> 8);
3326 radeon_emit(cs, gsvs_ring_size >> 8);
3327 }
3328 }
3329
3330 static void
3331 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3332 unsigned hs_offchip_param, unsigned tf_ring_size,
3333 struct radeon_winsys_bo *tess_rings_bo)
3334 {
3335 uint64_t tf_va;
3336
3337 if (!tess_rings_bo)
3338 return;
3339
3340 tf_va = radv_buffer_get_va(tess_rings_bo);
3341
3342 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
3343
3344 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
3345 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
3346 S_030938_SIZE(tf_ring_size / 4));
3347 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
3348 tf_va >> 8);
3349
3350 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3351 radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3352 S_030984_BASE_HI(tf_va >> 40));
3353 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
3354 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
3355 S_030944_BASE_HI(tf_va >> 40));
3356 }
3357 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
3358 hs_offchip_param);
3359 } else {
3360 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
3361 S_008988_SIZE(tf_ring_size / 4));
3362 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
3363 tf_va >> 8);
3364 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3365 hs_offchip_param);
3366 }
3367 }
3368
3369 static void
3370 radv_emit_graphics_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3371 uint32_t size_per_wave, uint32_t waves,
3372 struct radeon_winsys_bo *scratch_bo)
3373 {
3374 if (queue->queue_family_index != RADV_QUEUE_GENERAL)
3375 return;
3376
3377 if (!scratch_bo)
3378 return;
3379
3380 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
3381
3382 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
3383 S_0286E8_WAVES(waves) |
3384 S_0286E8_WAVESIZE(round_up_u32(size_per_wave, 1024)));
3385 }
3386
3387 static void
3388 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3389 uint32_t size_per_wave, uint32_t waves,
3390 struct radeon_winsys_bo *compute_scratch_bo)
3391 {
3392 uint64_t scratch_va;
3393
3394 if (!compute_scratch_bo)
3395 return;
3396
3397 scratch_va = radv_buffer_get_va(compute_scratch_bo);
3398
3399 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
3400
3401 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
3402 radeon_emit(cs, scratch_va);
3403 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
3404 S_008F04_SWIZZLE_ENABLE(1));
3405
3406 radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
3407 S_00B860_WAVES(waves) |
3408 S_00B860_WAVESIZE(round_up_u32(size_per_wave, 1024)));
3409 }
3410
3411 static void
3412 radv_emit_global_shader_pointers(struct radv_queue *queue,
3413 struct radeon_cmdbuf *cs,
3414 struct radeon_winsys_bo *descriptor_bo)
3415 {
3416 uint64_t va;
3417
3418 if (!descriptor_bo)
3419 return;
3420
3421 va = radv_buffer_get_va(descriptor_bo);
3422
3423 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
3424
3425 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3426 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3427 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3428 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
3429 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
3430
3431 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3432 radv_emit_shader_pointer(queue->device, cs, regs[i],
3433 va, true);
3434 }
3435 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
3436 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3437 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3438 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
3439 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
3440
3441 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3442 radv_emit_shader_pointer(queue->device, cs, regs[i],
3443 va, true);
3444 }
3445 } else {
3446 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3447 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3448 R_00B230_SPI_SHADER_USER_DATA_GS_0,
3449 R_00B330_SPI_SHADER_USER_DATA_ES_0,
3450 R_00B430_SPI_SHADER_USER_DATA_HS_0,
3451 R_00B530_SPI_SHADER_USER_DATA_LS_0};
3452
3453 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3454 radv_emit_shader_pointer(queue->device, cs, regs[i],
3455 va, true);
3456 }
3457 }
3458 }
3459
3460 static void
3461 radv_emit_trap_handler(struct radv_queue *queue,
3462 struct radeon_cmdbuf *cs,
3463 struct radeon_winsys_bo *tma_bo)
3464 {
3465 struct radv_device *device = queue->device;
3466 struct radeon_winsys_bo *tba_bo;
3467 uint64_t tba_va, tma_va;
3468
3469 if (!device->trap_handler_shader || !tma_bo)
3470 return;
3471
3472 tba_bo = device->trap_handler_shader->bo;
3473
3474 tba_va = radv_buffer_get_va(tba_bo) + device->trap_handler_shader->bo_offset;
3475 tma_va = radv_buffer_get_va(tma_bo);
3476
3477 radv_cs_add_buffer(queue->device->ws, cs, tba_bo);
3478 radv_cs_add_buffer(queue->device->ws, cs, tma_bo);
3479
3480 if (queue->queue_family_index == RADV_QUEUE_GENERAL) {
3481 uint32_t regs[] = {R_00B000_SPI_SHADER_TBA_LO_PS,
3482 R_00B100_SPI_SHADER_TBA_LO_VS,
3483 R_00B200_SPI_SHADER_TBA_LO_GS,
3484 R_00B300_SPI_SHADER_TBA_LO_ES,
3485 R_00B400_SPI_SHADER_TBA_LO_HS,
3486 R_00B500_SPI_SHADER_TBA_LO_LS};
3487
3488 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3489 radeon_set_sh_reg_seq(cs, regs[i], 4);
3490 radeon_emit(cs, tba_va >> 8);
3491 radeon_emit(cs, tba_va >> 40);
3492 radeon_emit(cs, tma_va >> 8);
3493 radeon_emit(cs, tma_va >> 40);
3494 }
3495 } else {
3496 radeon_set_sh_reg_seq(cs, R_00B838_COMPUTE_TBA_LO, 4);
3497 radeon_emit(cs, tba_va >> 8);
3498 radeon_emit(cs, tba_va >> 40);
3499 radeon_emit(cs, tma_va >> 8);
3500 radeon_emit(cs, tma_va >> 40);
3501 }
3502 }
3503
3504 static void
3505 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
3506 {
3507 struct radv_device *device = queue->device;
3508
3509 if (device->gfx_init) {
3510 uint64_t va = radv_buffer_get_va(device->gfx_init);
3511
3512 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
3513 radeon_emit(cs, va);
3514 radeon_emit(cs, va >> 32);
3515 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
3516
3517 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
3518 } else {
3519 si_emit_graphics(device, cs);
3520 }
3521 }
3522
3523 static void
3524 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
3525 {
3526 si_emit_compute(queue->device, cs);
3527 }
3528
3529 static VkResult
3530 radv_get_preamble_cs(struct radv_queue *queue,
3531 uint32_t scratch_size_per_wave,
3532 uint32_t scratch_waves,
3533 uint32_t compute_scratch_size_per_wave,
3534 uint32_t compute_scratch_waves,
3535 uint32_t esgs_ring_size,
3536 uint32_t gsvs_ring_size,
3537 bool needs_tess_rings,
3538 bool needs_gds,
3539 bool needs_gds_oa,
3540 bool needs_sample_positions,
3541 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
3542 struct radeon_cmdbuf **initial_preamble_cs,
3543 struct radeon_cmdbuf **continue_preamble_cs)
3544 {
3545 struct radeon_winsys_bo *scratch_bo = NULL;
3546 struct radeon_winsys_bo *descriptor_bo = NULL;
3547 struct radeon_winsys_bo *compute_scratch_bo = NULL;
3548 struct radeon_winsys_bo *esgs_ring_bo = NULL;
3549 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
3550 struct radeon_winsys_bo *tess_rings_bo = NULL;
3551 struct radeon_winsys_bo *gds_bo = NULL;
3552 struct radeon_winsys_bo *gds_oa_bo = NULL;
3553 struct radeon_cmdbuf *dest_cs[3] = {0};
3554 bool add_tess_rings = false, add_gds = false, add_gds_oa = false, add_sample_positions = false;
3555 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
3556 unsigned max_offchip_buffers;
3557 unsigned hs_offchip_param = 0;
3558 unsigned tess_offchip_ring_offset;
3559 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
3560 if (!queue->has_tess_rings) {
3561 if (needs_tess_rings)
3562 add_tess_rings = true;
3563 }
3564 if (!queue->has_gds) {
3565 if (needs_gds)
3566 add_gds = true;
3567 }
3568 if (!queue->has_gds_oa) {
3569 if (needs_gds_oa)
3570 add_gds_oa = true;
3571 }
3572 if (!queue->has_sample_positions) {
3573 if (needs_sample_positions)
3574 add_sample_positions = true;
3575 }
3576 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
3577 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
3578 &max_offchip_buffers);
3579 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
3580 tess_offchip_ring_size = max_offchip_buffers *
3581 queue->device->tess_offchip_block_dw_size * 4;
3582
3583 scratch_size_per_wave = MAX2(scratch_size_per_wave, queue->scratch_size_per_wave);
3584 if (scratch_size_per_wave)
3585 scratch_waves = MIN2(scratch_waves, UINT32_MAX / scratch_size_per_wave);
3586 else
3587 scratch_waves = 0;
3588
3589 compute_scratch_size_per_wave = MAX2(compute_scratch_size_per_wave, queue->compute_scratch_size_per_wave);
3590 if (compute_scratch_size_per_wave)
3591 compute_scratch_waves = MIN2(compute_scratch_waves, UINT32_MAX / compute_scratch_size_per_wave);
3592 else
3593 compute_scratch_waves = 0;
3594
3595 if (scratch_size_per_wave <= queue->scratch_size_per_wave &&
3596 scratch_waves <= queue->scratch_waves &&
3597 compute_scratch_size_per_wave <= queue->compute_scratch_size_per_wave &&
3598 compute_scratch_waves <= queue->compute_scratch_waves &&
3599 esgs_ring_size <= queue->esgs_ring_size &&
3600 gsvs_ring_size <= queue->gsvs_ring_size &&
3601 !add_tess_rings && !add_gds && !add_gds_oa && !add_sample_positions &&
3602 queue->initial_preamble_cs) {
3603 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
3604 *initial_preamble_cs = queue->initial_preamble_cs;
3605 *continue_preamble_cs = queue->continue_preamble_cs;
3606 if (!scratch_size_per_wave && !compute_scratch_size_per_wave &&
3607 !esgs_ring_size && !gsvs_ring_size && !needs_tess_rings &&
3608 !needs_gds && !needs_gds_oa && !needs_sample_positions)
3609 *continue_preamble_cs = NULL;
3610 return VK_SUCCESS;
3611 }
3612
3613 uint32_t scratch_size = scratch_size_per_wave * scratch_waves;
3614 uint32_t queue_scratch_size = queue->scratch_size_per_wave * queue->scratch_waves;
3615 if (scratch_size > queue_scratch_size) {
3616 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
3617 scratch_size,
3618 4096,
3619 RADEON_DOMAIN_VRAM,
3620 ring_bo_flags,
3621 RADV_BO_PRIORITY_SCRATCH);
3622 if (!scratch_bo)
3623 goto fail;
3624 } else
3625 scratch_bo = queue->scratch_bo;
3626
3627 uint32_t compute_scratch_size = compute_scratch_size_per_wave * compute_scratch_waves;
3628 uint32_t compute_queue_scratch_size = queue->compute_scratch_size_per_wave * queue->compute_scratch_waves;
3629 if (compute_scratch_size > compute_queue_scratch_size) {
3630 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
3631 compute_scratch_size,
3632 4096,
3633 RADEON_DOMAIN_VRAM,
3634 ring_bo_flags,
3635 RADV_BO_PRIORITY_SCRATCH);
3636 if (!compute_scratch_bo)
3637 goto fail;
3638
3639 } else
3640 compute_scratch_bo = queue->compute_scratch_bo;
3641
3642 if (esgs_ring_size > queue->esgs_ring_size) {
3643 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
3644 esgs_ring_size,
3645 4096,
3646 RADEON_DOMAIN_VRAM,
3647 ring_bo_flags,
3648 RADV_BO_PRIORITY_SCRATCH);
3649 if (!esgs_ring_bo)
3650 goto fail;
3651 } else {
3652 esgs_ring_bo = queue->esgs_ring_bo;
3653 esgs_ring_size = queue->esgs_ring_size;
3654 }
3655
3656 if (gsvs_ring_size > queue->gsvs_ring_size) {
3657 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
3658 gsvs_ring_size,
3659 4096,
3660 RADEON_DOMAIN_VRAM,
3661 ring_bo_flags,
3662 RADV_BO_PRIORITY_SCRATCH);
3663 if (!gsvs_ring_bo)
3664 goto fail;
3665 } else {
3666 gsvs_ring_bo = queue->gsvs_ring_bo;
3667 gsvs_ring_size = queue->gsvs_ring_size;
3668 }
3669
3670 if (add_tess_rings) {
3671 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
3672 tess_offchip_ring_offset + tess_offchip_ring_size,
3673 256,
3674 RADEON_DOMAIN_VRAM,
3675 ring_bo_flags,
3676 RADV_BO_PRIORITY_SCRATCH);
3677 if (!tess_rings_bo)
3678 goto fail;
3679 } else {
3680 tess_rings_bo = queue->tess_rings_bo;
3681 }
3682
3683 if (add_gds) {
3684 assert(queue->device->physical_device->rad_info.chip_class >= GFX10);
3685
3686 /* 4 streamout GDS counters.
3687 * We need 256B (64 dw) of GDS, otherwise streamout hangs.
3688 */
3689 gds_bo = queue->device->ws->buffer_create(queue->device->ws,
3690 256, 4,
3691 RADEON_DOMAIN_GDS,
3692 ring_bo_flags,
3693 RADV_BO_PRIORITY_SCRATCH);
3694 if (!gds_bo)
3695 goto fail;
3696 } else {
3697 gds_bo = queue->gds_bo;
3698 }
3699
3700 if (add_gds_oa) {
3701 assert(queue->device->physical_device->rad_info.chip_class >= GFX10);
3702
3703 gds_oa_bo = queue->device->ws->buffer_create(queue->device->ws,
3704 4, 1,
3705 RADEON_DOMAIN_OA,
3706 ring_bo_flags,
3707 RADV_BO_PRIORITY_SCRATCH);
3708 if (!gds_oa_bo)
3709 goto fail;
3710 } else {
3711 gds_oa_bo = queue->gds_oa_bo;
3712 }
3713
3714 if (scratch_bo != queue->scratch_bo ||
3715 esgs_ring_bo != queue->esgs_ring_bo ||
3716 gsvs_ring_bo != queue->gsvs_ring_bo ||
3717 tess_rings_bo != queue->tess_rings_bo ||
3718 add_sample_positions) {
3719 uint32_t size = 0;
3720 if (gsvs_ring_bo || esgs_ring_bo ||
3721 tess_rings_bo || add_sample_positions) {
3722 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
3723 if (add_sample_positions)
3724 size += 128; /* 64+32+16+8 = 120 bytes */
3725 }
3726 else if (scratch_bo)
3727 size = 8; /* 2 dword */
3728
3729 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
3730 size,
3731 4096,
3732 RADEON_DOMAIN_VRAM,
3733 RADEON_FLAG_CPU_ACCESS |
3734 RADEON_FLAG_NO_INTERPROCESS_SHARING |
3735 RADEON_FLAG_READ_ONLY,
3736 RADV_BO_PRIORITY_DESCRIPTOR);
3737 if (!descriptor_bo)
3738 goto fail;
3739 } else
3740 descriptor_bo = queue->descriptor_bo;
3741
3742 if (descriptor_bo != queue->descriptor_bo) {
3743 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
3744 if (!map)
3745 goto fail;
3746
3747 if (scratch_bo) {
3748 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
3749 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
3750 S_008F04_SWIZZLE_ENABLE(1);
3751 map[0] = scratch_va;
3752 map[1] = rsrc1;
3753 }
3754
3755 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
3756 fill_geom_tess_rings(queue, map, add_sample_positions,
3757 esgs_ring_size, esgs_ring_bo,
3758 gsvs_ring_size, gsvs_ring_bo,
3759 tess_factor_ring_size,
3760 tess_offchip_ring_offset,
3761 tess_offchip_ring_size,
3762 tess_rings_bo);
3763
3764 queue->device->ws->buffer_unmap(descriptor_bo);
3765 }
3766
3767 for(int i = 0; i < 3; ++i) {
3768 struct radeon_cmdbuf *cs = NULL;
3769 cs = queue->device->ws->cs_create(queue->device->ws,
3770 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
3771 if (!cs)
3772 goto fail;
3773
3774 dest_cs[i] = cs;
3775
3776 if (scratch_bo)
3777 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
3778
3779 /* Emit initial configuration. */
3780 switch (queue->queue_family_index) {
3781 case RADV_QUEUE_GENERAL:
3782 radv_init_graphics_state(cs, queue);
3783 break;
3784 case RADV_QUEUE_COMPUTE:
3785 radv_init_compute_state(cs, queue);
3786 break;
3787 case RADV_QUEUE_TRANSFER:
3788 break;
3789 }
3790
3791 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
3792 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3793 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3794
3795 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3796 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
3797 }
3798
3799 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
3800 gsvs_ring_bo, gsvs_ring_size);
3801 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
3802 tess_factor_ring_size, tess_rings_bo);
3803 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
3804 radv_emit_compute_scratch(queue, cs, compute_scratch_size_per_wave,
3805 compute_scratch_waves, compute_scratch_bo);
3806 radv_emit_graphics_scratch(queue, cs, scratch_size_per_wave,
3807 scratch_waves, scratch_bo);
3808 radv_emit_trap_handler(queue, cs, queue->device->tma_bo);
3809
3810 if (gds_bo)
3811 radv_cs_add_buffer(queue->device->ws, cs, gds_bo);
3812 if (gds_oa_bo)
3813 radv_cs_add_buffer(queue->device->ws, cs, gds_oa_bo);
3814
3815 if (queue->device->trace_bo)
3816 radv_cs_add_buffer(queue->device->ws, cs, queue->device->trace_bo);
3817
3818 if (queue->device->border_color_data.bo)
3819 radv_cs_add_buffer(queue->device->ws, cs,
3820 queue->device->border_color_data.bo);
3821
3822 if (i == 0) {
3823 si_cs_emit_cache_flush(cs,
3824 queue->device->physical_device->rad_info.chip_class,
3825 NULL, 0,
3826 queue->queue_family_index == RING_COMPUTE &&
3827 queue->device->physical_device->rad_info.chip_class >= GFX7,
3828 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
3829 RADV_CMD_FLAG_INV_ICACHE |
3830 RADV_CMD_FLAG_INV_SCACHE |
3831 RADV_CMD_FLAG_INV_VCACHE |
3832 RADV_CMD_FLAG_INV_L2 |
3833 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
3834 } else if (i == 1) {
3835 si_cs_emit_cache_flush(cs,
3836 queue->device->physical_device->rad_info.chip_class,
3837 NULL, 0,
3838 queue->queue_family_index == RING_COMPUTE &&
3839 queue->device->physical_device->rad_info.chip_class >= GFX7,
3840 RADV_CMD_FLAG_INV_ICACHE |
3841 RADV_CMD_FLAG_INV_SCACHE |
3842 RADV_CMD_FLAG_INV_VCACHE |
3843 RADV_CMD_FLAG_INV_L2 |
3844 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
3845 }
3846
3847 if (queue->device->ws->cs_finalize(cs) != VK_SUCCESS)
3848 goto fail;
3849 }
3850
3851 if (queue->initial_full_flush_preamble_cs)
3852 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
3853
3854 if (queue->initial_preamble_cs)
3855 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
3856
3857 if (queue->continue_preamble_cs)
3858 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
3859
3860 queue->initial_full_flush_preamble_cs = dest_cs[0];
3861 queue->initial_preamble_cs = dest_cs[1];
3862 queue->continue_preamble_cs = dest_cs[2];
3863
3864 if (scratch_bo != queue->scratch_bo) {
3865 if (queue->scratch_bo)
3866 queue->device->ws->buffer_destroy(queue->scratch_bo);
3867 queue->scratch_bo = scratch_bo;
3868 }
3869 queue->scratch_size_per_wave = scratch_size_per_wave;
3870 queue->scratch_waves = scratch_waves;
3871
3872 if (compute_scratch_bo != queue->compute_scratch_bo) {
3873 if (queue->compute_scratch_bo)
3874 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
3875 queue->compute_scratch_bo = compute_scratch_bo;
3876 }
3877 queue->compute_scratch_size_per_wave = compute_scratch_size_per_wave;
3878 queue->compute_scratch_waves = compute_scratch_waves;
3879
3880 if (esgs_ring_bo != queue->esgs_ring_bo) {
3881 if (queue->esgs_ring_bo)
3882 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
3883 queue->esgs_ring_bo = esgs_ring_bo;
3884 queue->esgs_ring_size = esgs_ring_size;
3885 }
3886
3887 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
3888 if (queue->gsvs_ring_bo)
3889 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
3890 queue->gsvs_ring_bo = gsvs_ring_bo;
3891 queue->gsvs_ring_size = gsvs_ring_size;
3892 }
3893
3894 if (tess_rings_bo != queue->tess_rings_bo) {
3895 queue->tess_rings_bo = tess_rings_bo;
3896 queue->has_tess_rings = true;
3897 }
3898
3899 if (gds_bo != queue->gds_bo) {
3900 queue->gds_bo = gds_bo;
3901 queue->has_gds = true;
3902 }
3903
3904 if (gds_oa_bo != queue->gds_oa_bo) {
3905 queue->gds_oa_bo = gds_oa_bo;
3906 queue->has_gds_oa = true;
3907 }
3908
3909 if (descriptor_bo != queue->descriptor_bo) {
3910 if (queue->descriptor_bo)
3911 queue->device->ws->buffer_destroy(queue->descriptor_bo);
3912
3913 queue->descriptor_bo = descriptor_bo;
3914 }
3915
3916 if (add_sample_positions)
3917 queue->has_sample_positions = true;
3918
3919 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
3920 *initial_preamble_cs = queue->initial_preamble_cs;
3921 *continue_preamble_cs = queue->continue_preamble_cs;
3922 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
3923 *continue_preamble_cs = NULL;
3924 return VK_SUCCESS;
3925 fail:
3926 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
3927 if (dest_cs[i])
3928 queue->device->ws->cs_destroy(dest_cs[i]);
3929 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
3930 queue->device->ws->buffer_destroy(descriptor_bo);
3931 if (scratch_bo && scratch_bo != queue->scratch_bo)
3932 queue->device->ws->buffer_destroy(scratch_bo);
3933 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
3934 queue->device->ws->buffer_destroy(compute_scratch_bo);
3935 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
3936 queue->device->ws->buffer_destroy(esgs_ring_bo);
3937 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
3938 queue->device->ws->buffer_destroy(gsvs_ring_bo);
3939 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
3940 queue->device->ws->buffer_destroy(tess_rings_bo);
3941 if (gds_bo && gds_bo != queue->gds_bo)
3942 queue->device->ws->buffer_destroy(gds_bo);
3943 if (gds_oa_bo && gds_oa_bo != queue->gds_oa_bo)
3944 queue->device->ws->buffer_destroy(gds_oa_bo);
3945
3946 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3947 }
3948
3949 static VkResult radv_alloc_sem_counts(struct radv_device *device,
3950 struct radv_winsys_sem_counts *counts,
3951 int num_sems,
3952 struct radv_semaphore_part **sems,
3953 const uint64_t *timeline_values,
3954 VkFence _fence,
3955 bool is_signal)
3956 {
3957 int syncobj_idx = 0, non_reset_idx = 0, sem_idx = 0, timeline_idx = 0;
3958
3959 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
3960 return VK_SUCCESS;
3961
3962 for (uint32_t i = 0; i < num_sems; i++) {
3963 switch(sems[i]->kind) {
3964 case RADV_SEMAPHORE_SYNCOBJ:
3965 counts->syncobj_count++;
3966 counts->syncobj_reset_count++;
3967 break;
3968 case RADV_SEMAPHORE_WINSYS:
3969 counts->sem_count++;
3970 break;
3971 case RADV_SEMAPHORE_NONE:
3972 break;
3973 case RADV_SEMAPHORE_TIMELINE:
3974 counts->syncobj_count++;
3975 break;
3976 case RADV_SEMAPHORE_TIMELINE_SYNCOBJ:
3977 counts->timeline_syncobj_count++;
3978 break;
3979 }
3980 }
3981
3982 if (_fence != VK_NULL_HANDLE) {
3983 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3984
3985 struct radv_fence_part *part =
3986 fence->temporary.kind != RADV_FENCE_NONE ?
3987 &fence->temporary : &fence->permanent;
3988 if (part->kind == RADV_FENCE_SYNCOBJ)
3989 counts->syncobj_count++;
3990 }
3991
3992 if (counts->syncobj_count || counts->timeline_syncobj_count) {
3993 counts->points = (uint64_t *)malloc(
3994 sizeof(*counts->syncobj) * counts->syncobj_count +
3995 (sizeof(*counts->syncobj) + sizeof(*counts->points)) * counts->timeline_syncobj_count);
3996 if (!counts->points)
3997 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3998 counts->syncobj = (uint32_t*)(counts->points + counts->timeline_syncobj_count);
3999 }
4000
4001 if (counts->sem_count) {
4002 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
4003 if (!counts->sem) {
4004 free(counts->syncobj);
4005 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4006 }
4007 }
4008
4009 non_reset_idx = counts->syncobj_reset_count;
4010
4011 for (uint32_t i = 0; i < num_sems; i++) {
4012 switch(sems[i]->kind) {
4013 case RADV_SEMAPHORE_NONE:
4014 unreachable("Empty semaphore");
4015 break;
4016 case RADV_SEMAPHORE_SYNCOBJ:
4017 counts->syncobj[syncobj_idx++] = sems[i]->syncobj;
4018 break;
4019 case RADV_SEMAPHORE_WINSYS:
4020 counts->sem[sem_idx++] = sems[i]->ws_sem;
4021 break;
4022 case RADV_SEMAPHORE_TIMELINE: {
4023 pthread_mutex_lock(&sems[i]->timeline.mutex);
4024 struct radv_timeline_point *point = NULL;
4025 if (is_signal) {
4026 point = radv_timeline_add_point_locked(device, &sems[i]->timeline, timeline_values[i]);
4027 } else {
4028 point = radv_timeline_find_point_at_least_locked(device, &sems[i]->timeline, timeline_values[i]);
4029 }
4030
4031 pthread_mutex_unlock(&sems[i]->timeline.mutex);
4032
4033 if (point) {
4034 counts->syncobj[non_reset_idx++] = point->syncobj;
4035 } else {
4036 /* Explicitly remove the semaphore so we might not find
4037 * a point later post-submit. */
4038 sems[i] = NULL;
4039 }
4040 break;
4041 }
4042 case RADV_SEMAPHORE_TIMELINE_SYNCOBJ:
4043 counts->syncobj[counts->syncobj_count + timeline_idx] = sems[i]->syncobj;
4044 counts->points[timeline_idx] = timeline_values[i];
4045 ++timeline_idx;
4046 break;
4047 }
4048 }
4049
4050 if (_fence != VK_NULL_HANDLE) {
4051 RADV_FROM_HANDLE(radv_fence, fence, _fence);
4052
4053 struct radv_fence_part *part =
4054 fence->temporary.kind != RADV_FENCE_NONE ?
4055 &fence->temporary : &fence->permanent;
4056 if (part->kind == RADV_FENCE_SYNCOBJ)
4057 counts->syncobj[non_reset_idx++] = part->syncobj;
4058 }
4059
4060 assert(MAX2(syncobj_idx, non_reset_idx) <= counts->syncobj_count);
4061 counts->syncobj_count = MAX2(syncobj_idx, non_reset_idx);
4062
4063 return VK_SUCCESS;
4064 }
4065
4066 static void
4067 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
4068 {
4069 free(sem_info->wait.points);
4070 free(sem_info->wait.sem);
4071 free(sem_info->signal.points);
4072 free(sem_info->signal.sem);
4073 }
4074
4075
4076 static void radv_free_temp_syncobjs(struct radv_device *device,
4077 int num_sems,
4078 struct radv_semaphore_part *sems)
4079 {
4080 for (uint32_t i = 0; i < num_sems; i++) {
4081 radv_destroy_semaphore_part(device, sems + i);
4082 }
4083 }
4084
4085 static VkResult
4086 radv_alloc_sem_info(struct radv_device *device,
4087 struct radv_winsys_sem_info *sem_info,
4088 int num_wait_sems,
4089 struct radv_semaphore_part **wait_sems,
4090 const uint64_t *wait_values,
4091 int num_signal_sems,
4092 struct radv_semaphore_part **signal_sems,
4093 const uint64_t *signal_values,
4094 VkFence fence)
4095 {
4096 VkResult ret;
4097 memset(sem_info, 0, sizeof(*sem_info));
4098
4099 ret = radv_alloc_sem_counts(device, &sem_info->wait, num_wait_sems, wait_sems, wait_values, VK_NULL_HANDLE, false);
4100 if (ret)
4101 return ret;
4102 ret = radv_alloc_sem_counts(device, &sem_info->signal, num_signal_sems, signal_sems, signal_values, fence, true);
4103 if (ret)
4104 radv_free_sem_info(sem_info);
4105
4106 /* caller can override these */
4107 sem_info->cs_emit_wait = true;
4108 sem_info->cs_emit_signal = true;
4109 return ret;
4110 }
4111
4112 static void
4113 radv_finalize_timelines(struct radv_device *device,
4114 uint32_t num_wait_sems,
4115 struct radv_semaphore_part **wait_sems,
4116 const uint64_t *wait_values,
4117 uint32_t num_signal_sems,
4118 struct radv_semaphore_part **signal_sems,
4119 const uint64_t *signal_values,
4120 struct list_head *processing_list)
4121 {
4122 for (uint32_t i = 0; i < num_wait_sems; ++i) {
4123 if (wait_sems[i] && wait_sems[i]->kind == RADV_SEMAPHORE_TIMELINE) {
4124 pthread_mutex_lock(&wait_sems[i]->timeline.mutex);
4125 struct radv_timeline_point *point =
4126 radv_timeline_find_point_at_least_locked(device, &wait_sems[i]->timeline, wait_values[i]);
4127 point->wait_count -= 2;
4128 pthread_mutex_unlock(&wait_sems[i]->timeline.mutex);
4129 }
4130 }
4131 for (uint32_t i = 0; i < num_signal_sems; ++i) {
4132 if (signal_sems[i] && signal_sems[i]->kind == RADV_SEMAPHORE_TIMELINE) {
4133 pthread_mutex_lock(&signal_sems[i]->timeline.mutex);
4134 struct radv_timeline_point *point =
4135 radv_timeline_find_point_at_least_locked(device, &signal_sems[i]->timeline, signal_values[i]);
4136 signal_sems[i]->timeline.highest_submitted =
4137 MAX2(signal_sems[i]->timeline.highest_submitted, point->value);
4138 point->wait_count -= 2;
4139 radv_timeline_trigger_waiters_locked(&signal_sems[i]->timeline, processing_list);
4140 pthread_mutex_unlock(&signal_sems[i]->timeline.mutex);
4141 } else if (signal_sems[i] && signal_sems[i]->kind == RADV_SEMAPHORE_TIMELINE_SYNCOBJ) {
4142 signal_sems[i]->timeline_syncobj.max_point =
4143 MAX2(signal_sems[i]->timeline_syncobj.max_point, signal_values[i]);
4144 }
4145 }
4146 }
4147
4148 static VkResult
4149 radv_sparse_buffer_bind_memory(struct radv_device *device,
4150 const VkSparseBufferMemoryBindInfo *bind)
4151 {
4152 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
4153 VkResult result;
4154
4155 for (uint32_t i = 0; i < bind->bindCount; ++i) {
4156 struct radv_device_memory *mem = NULL;
4157
4158 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
4159 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
4160
4161 result = device->ws->buffer_virtual_bind(buffer->bo,
4162 bind->pBinds[i].resourceOffset,
4163 bind->pBinds[i].size,
4164 mem ? mem->bo : NULL,
4165 bind->pBinds[i].memoryOffset);
4166 if (result != VK_SUCCESS)
4167 return result;
4168 }
4169
4170 return VK_SUCCESS;
4171 }
4172
4173 static VkResult
4174 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
4175 const VkSparseImageOpaqueMemoryBindInfo *bind)
4176 {
4177 RADV_FROM_HANDLE(radv_image, image, bind->image);
4178 VkResult result;
4179
4180 for (uint32_t i = 0; i < bind->bindCount; ++i) {
4181 struct radv_device_memory *mem = NULL;
4182
4183 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
4184 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
4185
4186 result = device->ws->buffer_virtual_bind(image->bo,
4187 bind->pBinds[i].resourceOffset,
4188 bind->pBinds[i].size,
4189 mem ? mem->bo : NULL,
4190 bind->pBinds[i].memoryOffset);
4191 if (result != VK_SUCCESS)
4192 return result;
4193 }
4194
4195 return VK_SUCCESS;
4196 }
4197
4198 static VkResult
4199 radv_get_preambles(struct radv_queue *queue,
4200 const VkCommandBuffer *cmd_buffers,
4201 uint32_t cmd_buffer_count,
4202 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
4203 struct radeon_cmdbuf **initial_preamble_cs,
4204 struct radeon_cmdbuf **continue_preamble_cs)
4205 {
4206 uint32_t scratch_size_per_wave = 0, waves_wanted = 0;
4207 uint32_t compute_scratch_size_per_wave = 0, compute_waves_wanted = 0;
4208 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
4209 bool tess_rings_needed = false;
4210 bool gds_needed = false;
4211 bool gds_oa_needed = false;
4212 bool sample_positions_needed = false;
4213
4214 for (uint32_t j = 0; j < cmd_buffer_count; j++) {
4215 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
4216 cmd_buffers[j]);
4217
4218 scratch_size_per_wave = MAX2(scratch_size_per_wave, cmd_buffer->scratch_size_per_wave_needed);
4219 waves_wanted = MAX2(waves_wanted, cmd_buffer->scratch_waves_wanted);
4220 compute_scratch_size_per_wave = MAX2(compute_scratch_size_per_wave,
4221 cmd_buffer->compute_scratch_size_per_wave_needed);
4222 compute_waves_wanted = MAX2(compute_waves_wanted,
4223 cmd_buffer->compute_scratch_waves_wanted);
4224 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
4225 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
4226 tess_rings_needed |= cmd_buffer->tess_rings_needed;
4227 gds_needed |= cmd_buffer->gds_needed;
4228 gds_oa_needed |= cmd_buffer->gds_oa_needed;
4229 sample_positions_needed |= cmd_buffer->sample_positions_needed;
4230 }
4231
4232 return radv_get_preamble_cs(queue, scratch_size_per_wave, waves_wanted,
4233 compute_scratch_size_per_wave, compute_waves_wanted,
4234 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
4235 gds_needed, gds_oa_needed, sample_positions_needed,
4236 initial_full_flush_preamble_cs,
4237 initial_preamble_cs, continue_preamble_cs);
4238 }
4239
4240 struct radv_deferred_queue_submission {
4241 struct radv_queue *queue;
4242 VkCommandBuffer *cmd_buffers;
4243 uint32_t cmd_buffer_count;
4244
4245 /* Sparse bindings that happen on a queue. */
4246 VkSparseBufferMemoryBindInfo *buffer_binds;
4247 uint32_t buffer_bind_count;
4248 VkSparseImageOpaqueMemoryBindInfo *image_opaque_binds;
4249 uint32_t image_opaque_bind_count;
4250
4251 bool flush_caches;
4252 VkShaderStageFlags wait_dst_stage_mask;
4253 struct radv_semaphore_part **wait_semaphores;
4254 uint32_t wait_semaphore_count;
4255 struct radv_semaphore_part **signal_semaphores;
4256 uint32_t signal_semaphore_count;
4257 VkFence fence;
4258
4259 uint64_t *wait_values;
4260 uint64_t *signal_values;
4261
4262 struct radv_semaphore_part *temporary_semaphore_parts;
4263 uint32_t temporary_semaphore_part_count;
4264
4265 struct list_head queue_pending_list;
4266 uint32_t submission_wait_count;
4267 struct radv_timeline_waiter *wait_nodes;
4268
4269 struct list_head processing_list;
4270 };
4271
4272 struct radv_queue_submission {
4273 const VkCommandBuffer *cmd_buffers;
4274 uint32_t cmd_buffer_count;
4275
4276 /* Sparse bindings that happen on a queue. */
4277 const VkSparseBufferMemoryBindInfo *buffer_binds;
4278 uint32_t buffer_bind_count;
4279 const VkSparseImageOpaqueMemoryBindInfo *image_opaque_binds;
4280 uint32_t image_opaque_bind_count;
4281
4282 bool flush_caches;
4283 VkPipelineStageFlags wait_dst_stage_mask;
4284 const VkSemaphore *wait_semaphores;
4285 uint32_t wait_semaphore_count;
4286 const VkSemaphore *signal_semaphores;
4287 uint32_t signal_semaphore_count;
4288 VkFence fence;
4289
4290 const uint64_t *wait_values;
4291 uint32_t wait_value_count;
4292 const uint64_t *signal_values;
4293 uint32_t signal_value_count;
4294 };
4295
4296 static VkResult
4297 radv_queue_trigger_submission(struct radv_deferred_queue_submission *submission,
4298 uint32_t decrement,
4299 struct list_head *processing_list);
4300
4301 static VkResult
4302 radv_create_deferred_submission(struct radv_queue *queue,
4303 const struct radv_queue_submission *submission,
4304 struct radv_deferred_queue_submission **out)
4305 {
4306 struct radv_deferred_queue_submission *deferred = NULL;
4307 size_t size = sizeof(struct radv_deferred_queue_submission);
4308
4309 uint32_t temporary_count = 0;
4310 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4311 RADV_FROM_HANDLE(radv_semaphore, semaphore, submission->wait_semaphores[i]);
4312 if (semaphore->temporary.kind != RADV_SEMAPHORE_NONE)
4313 ++temporary_count;
4314 }
4315
4316 size += submission->cmd_buffer_count * sizeof(VkCommandBuffer);
4317 size += submission->buffer_bind_count * sizeof(VkSparseBufferMemoryBindInfo);
4318 size += submission->image_opaque_bind_count * sizeof(VkSparseImageOpaqueMemoryBindInfo);
4319 size += submission->wait_semaphore_count * sizeof(struct radv_semaphore_part *);
4320 size += temporary_count * sizeof(struct radv_semaphore_part);
4321 size += submission->signal_semaphore_count * sizeof(struct radv_semaphore_part *);
4322 size += submission->wait_value_count * sizeof(uint64_t);
4323 size += submission->signal_value_count * sizeof(uint64_t);
4324 size += submission->wait_semaphore_count * sizeof(struct radv_timeline_waiter);
4325
4326 deferred = calloc(1, size);
4327 if (!deferred)
4328 return VK_ERROR_OUT_OF_HOST_MEMORY;
4329
4330 deferred->queue = queue;
4331
4332 deferred->cmd_buffers = (void*)(deferred + 1);
4333 deferred->cmd_buffer_count = submission->cmd_buffer_count;
4334 memcpy(deferred->cmd_buffers, submission->cmd_buffers,
4335 submission->cmd_buffer_count * sizeof(*deferred->cmd_buffers));
4336
4337 deferred->buffer_binds = (void*)(deferred->cmd_buffers + submission->cmd_buffer_count);
4338 deferred->buffer_bind_count = submission->buffer_bind_count;
4339 memcpy(deferred->buffer_binds, submission->buffer_binds,
4340 submission->buffer_bind_count * sizeof(*deferred->buffer_binds));
4341
4342 deferred->image_opaque_binds = (void*)(deferred->buffer_binds + submission->buffer_bind_count);
4343 deferred->image_opaque_bind_count = submission->image_opaque_bind_count;
4344 memcpy(deferred->image_opaque_binds, submission->image_opaque_binds,
4345 submission->image_opaque_bind_count * sizeof(*deferred->image_opaque_binds));
4346
4347 deferred->flush_caches = submission->flush_caches;
4348 deferred->wait_dst_stage_mask = submission->wait_dst_stage_mask;
4349
4350 deferred->wait_semaphores = (void*)(deferred->image_opaque_binds + deferred->image_opaque_bind_count);
4351 deferred->wait_semaphore_count = submission->wait_semaphore_count;
4352
4353 deferred->signal_semaphores = (void*)(deferred->wait_semaphores + deferred->wait_semaphore_count);
4354 deferred->signal_semaphore_count = submission->signal_semaphore_count;
4355
4356 deferred->fence = submission->fence;
4357
4358 deferred->temporary_semaphore_parts = (void*)(deferred->signal_semaphores + deferred->signal_semaphore_count);
4359 deferred->temporary_semaphore_part_count = temporary_count;
4360
4361 uint32_t temporary_idx = 0;
4362 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4363 RADV_FROM_HANDLE(radv_semaphore, semaphore, submission->wait_semaphores[i]);
4364 if (semaphore->temporary.kind != RADV_SEMAPHORE_NONE) {
4365 deferred->wait_semaphores[i] = &deferred->temporary_semaphore_parts[temporary_idx];
4366 deferred->temporary_semaphore_parts[temporary_idx] = semaphore->temporary;
4367 semaphore->temporary.kind = RADV_SEMAPHORE_NONE;
4368 ++temporary_idx;
4369 } else
4370 deferred->wait_semaphores[i] = &semaphore->permanent;
4371 }
4372
4373 for (uint32_t i = 0; i < submission->signal_semaphore_count; ++i) {
4374 RADV_FROM_HANDLE(radv_semaphore, semaphore, submission->signal_semaphores[i]);
4375 if (semaphore->temporary.kind != RADV_SEMAPHORE_NONE) {
4376 deferred->signal_semaphores[i] = &semaphore->temporary;
4377 } else {
4378 deferred->signal_semaphores[i] = &semaphore->permanent;
4379 }
4380 }
4381
4382 deferred->wait_values = (void*)(deferred->temporary_semaphore_parts + temporary_count);
4383 memcpy(deferred->wait_values, submission->wait_values, submission->wait_value_count * sizeof(uint64_t));
4384 deferred->signal_values = deferred->wait_values + submission->wait_value_count;
4385 memcpy(deferred->signal_values, submission->signal_values, submission->signal_value_count * sizeof(uint64_t));
4386
4387 deferred->wait_nodes = (void*)(deferred->signal_values + submission->signal_value_count);
4388 /* This is worst-case. radv_queue_enqueue_submission will fill in further, but this
4389 * ensure the submission is not accidentally triggered early when adding wait timelines. */
4390 deferred->submission_wait_count = 1 + submission->wait_semaphore_count;
4391
4392 *out = deferred;
4393 return VK_SUCCESS;
4394 }
4395
4396 static VkResult
4397 radv_queue_enqueue_submission(struct radv_deferred_queue_submission *submission,
4398 struct list_head *processing_list)
4399 {
4400 uint32_t wait_cnt = 0;
4401 struct radv_timeline_waiter *waiter = submission->wait_nodes;
4402 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4403 if (submission->wait_semaphores[i]->kind == RADV_SEMAPHORE_TIMELINE) {
4404 pthread_mutex_lock(&submission->wait_semaphores[i]->timeline.mutex);
4405 if (submission->wait_semaphores[i]->timeline.highest_submitted < submission->wait_values[i]) {
4406 ++wait_cnt;
4407 waiter->value = submission->wait_values[i];
4408 waiter->submission = submission;
4409 list_addtail(&waiter->list, &submission->wait_semaphores[i]->timeline.waiters);
4410 ++waiter;
4411 }
4412 pthread_mutex_unlock(&submission->wait_semaphores[i]->timeline.mutex);
4413 }
4414 }
4415
4416 pthread_mutex_lock(&submission->queue->pending_mutex);
4417
4418 bool is_first = list_is_empty(&submission->queue->pending_submissions);
4419 list_addtail(&submission->queue_pending_list, &submission->queue->pending_submissions);
4420
4421 pthread_mutex_unlock(&submission->queue->pending_mutex);
4422
4423 /* If there is already a submission in the queue, that will decrement the counter by 1 when
4424 * submitted, but if the queue was empty, we decrement ourselves as there is no previous
4425 * submission. */
4426 uint32_t decrement = submission->wait_semaphore_count - wait_cnt + (is_first ? 1 : 0);
4427 return radv_queue_trigger_submission(submission, decrement, processing_list);
4428 }
4429
4430 static void
4431 radv_queue_submission_update_queue(struct radv_deferred_queue_submission *submission,
4432 struct list_head *processing_list)
4433 {
4434 pthread_mutex_lock(&submission->queue->pending_mutex);
4435 list_del(&submission->queue_pending_list);
4436
4437 /* trigger the next submission in the queue. */
4438 if (!list_is_empty(&submission->queue->pending_submissions)) {
4439 struct radv_deferred_queue_submission *next_submission =
4440 list_first_entry(&submission->queue->pending_submissions,
4441 struct radv_deferred_queue_submission,
4442 queue_pending_list);
4443 radv_queue_trigger_submission(next_submission, 1, processing_list);
4444 }
4445 pthread_mutex_unlock(&submission->queue->pending_mutex);
4446
4447 pthread_cond_broadcast(&submission->queue->device->timeline_cond);
4448 }
4449
4450 static VkResult
4451 radv_queue_submit_deferred(struct radv_deferred_queue_submission *submission,
4452 struct list_head *processing_list)
4453 {
4454 RADV_FROM_HANDLE(radv_fence, fence, submission->fence);
4455 struct radv_queue *queue = submission->queue;
4456 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
4457 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
4458 struct radeon_winsys_fence *base_fence = NULL;
4459 bool do_flush = submission->flush_caches || submission->wait_dst_stage_mask;
4460 bool can_patch = true;
4461 uint32_t advance;
4462 struct radv_winsys_sem_info sem_info;
4463 VkResult result;
4464 struct radeon_cmdbuf *initial_preamble_cs = NULL;
4465 struct radeon_cmdbuf *initial_flush_preamble_cs = NULL;
4466 struct radeon_cmdbuf *continue_preamble_cs = NULL;
4467
4468 if (fence) {
4469 /* Under most circumstances, out fences won't be temporary.
4470 * However, the spec does allow it for opaque_fd.
4471 *
4472 * From the Vulkan 1.0.53 spec:
4473 *
4474 * "If the import is temporary, the implementation must
4475 * restore the semaphore to its prior permanent state after
4476 * submitting the next semaphore wait operation."
4477 */
4478 struct radv_fence_part *part =
4479 fence->temporary.kind != RADV_FENCE_NONE ?
4480 &fence->temporary : &fence->permanent;
4481 if (part->kind == RADV_FENCE_WINSYS)
4482 base_fence = part->fence;
4483 }
4484
4485 result = radv_get_preambles(queue, submission->cmd_buffers,
4486 submission->cmd_buffer_count,
4487 &initial_preamble_cs,
4488 &initial_flush_preamble_cs,
4489 &continue_preamble_cs);
4490 if (result != VK_SUCCESS)
4491 goto fail;
4492
4493 result = radv_alloc_sem_info(queue->device,
4494 &sem_info,
4495 submission->wait_semaphore_count,
4496 submission->wait_semaphores,
4497 submission->wait_values,
4498 submission->signal_semaphore_count,
4499 submission->signal_semaphores,
4500 submission->signal_values,
4501 submission->fence);
4502 if (result != VK_SUCCESS)
4503 goto fail;
4504
4505 for (uint32_t i = 0; i < submission->buffer_bind_count; ++i) {
4506 result = radv_sparse_buffer_bind_memory(queue->device,
4507 submission->buffer_binds + i);
4508 if (result != VK_SUCCESS)
4509 goto fail;
4510 }
4511
4512 for (uint32_t i = 0; i < submission->image_opaque_bind_count; ++i) {
4513 result = radv_sparse_image_opaque_bind_memory(queue->device,
4514 submission->image_opaque_binds + i);
4515 if (result != VK_SUCCESS)
4516 goto fail;
4517 }
4518
4519 if (!submission->cmd_buffer_count) {
4520 result = queue->device->ws->cs_submit(ctx, queue->queue_idx,
4521 &queue->device->empty_cs[queue->queue_family_index],
4522 1, NULL, NULL,
4523 &sem_info, NULL,
4524 false, base_fence);
4525 if (result != VK_SUCCESS)
4526 goto fail;
4527 } else {
4528 struct radeon_cmdbuf **cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
4529 (submission->cmd_buffer_count));
4530
4531 for (uint32_t j = 0; j < submission->cmd_buffer_count; j++) {
4532 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, submission->cmd_buffers[j]);
4533 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
4534
4535 cs_array[j] = cmd_buffer->cs;
4536 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
4537 can_patch = false;
4538
4539 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
4540 }
4541
4542 for (uint32_t j = 0; j < submission->cmd_buffer_count; j += advance) {
4543 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
4544 const struct radv_winsys_bo_list *bo_list = NULL;
4545
4546 advance = MIN2(max_cs_submission,
4547 submission->cmd_buffer_count - j);
4548
4549 if (queue->device->trace_bo)
4550 *queue->device->trace_id_ptr = 0;
4551
4552 sem_info.cs_emit_wait = j == 0;
4553 sem_info.cs_emit_signal = j + advance == submission->cmd_buffer_count;
4554
4555 if (unlikely(queue->device->use_global_bo_list)) {
4556 pthread_mutex_lock(&queue->device->bo_list.mutex);
4557 bo_list = &queue->device->bo_list.list;
4558 }
4559
4560 result = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
4561 advance, initial_preamble, continue_preamble_cs,
4562 &sem_info, bo_list,
4563 can_patch, base_fence);
4564
4565 if (unlikely(queue->device->use_global_bo_list))
4566 pthread_mutex_unlock(&queue->device->bo_list.mutex);
4567
4568 if (result != VK_SUCCESS)
4569 goto fail;
4570
4571 if (queue->device->trace_bo) {
4572 radv_check_gpu_hangs(queue, cs_array[j]);
4573 }
4574
4575 if (queue->device->tma_bo) {
4576 radv_check_trap_handler(queue);
4577 }
4578 }
4579
4580 free(cs_array);
4581 }
4582
4583 radv_free_temp_syncobjs(queue->device,
4584 submission->temporary_semaphore_part_count,
4585 submission->temporary_semaphore_parts);
4586 radv_finalize_timelines(queue->device,
4587 submission->wait_semaphore_count,
4588 submission->wait_semaphores,
4589 submission->wait_values,
4590 submission->signal_semaphore_count,
4591 submission->signal_semaphores,
4592 submission->signal_values,
4593 processing_list);
4594 /* Has to happen after timeline finalization to make sure the
4595 * condition variable is only triggered when timelines and queue have
4596 * been updated. */
4597 radv_queue_submission_update_queue(submission, processing_list);
4598 radv_free_sem_info(&sem_info);
4599 free(submission);
4600 return VK_SUCCESS;
4601
4602 fail:
4603 if (result != VK_SUCCESS && result != VK_ERROR_DEVICE_LOST) {
4604 /* When something bad happened during the submission, such as
4605 * an out of memory issue, it might be hard to recover from
4606 * this inconsistent state. To avoid this sort of problem, we
4607 * assume that we are in a really bad situation and return
4608 * VK_ERROR_DEVICE_LOST to ensure the clients do not attempt
4609 * to submit the same job again to this device.
4610 */
4611 result = radv_device_set_lost(queue->device, "vkQueueSubmit() failed");
4612 }
4613
4614 radv_free_temp_syncobjs(queue->device,
4615 submission->temporary_semaphore_part_count,
4616 submission->temporary_semaphore_parts);
4617 free(submission);
4618 return result;
4619 }
4620
4621 static VkResult
4622 radv_process_submissions(struct list_head *processing_list)
4623 {
4624 while(!list_is_empty(processing_list)) {
4625 struct radv_deferred_queue_submission *submission =
4626 list_first_entry(processing_list, struct radv_deferred_queue_submission, processing_list);
4627 list_del(&submission->processing_list);
4628
4629 VkResult result = radv_queue_submit_deferred(submission, processing_list);
4630 if (result != VK_SUCCESS)
4631 return result;
4632 }
4633 return VK_SUCCESS;
4634 }
4635
4636 static VkResult
4637 wait_for_submission_timelines_available(struct radv_deferred_queue_submission *submission,
4638 uint64_t timeout)
4639 {
4640 struct radv_device *device = submission->queue->device;
4641 uint32_t syncobj_count = 0;
4642 uint32_t syncobj_idx = 0;
4643
4644 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4645 if (submission->wait_semaphores[i]->kind != RADV_SEMAPHORE_TIMELINE_SYNCOBJ)
4646 continue;
4647
4648 if (submission->wait_semaphores[i]->timeline_syncobj.max_point >= submission->wait_values[i])
4649 continue;
4650 ++syncobj_count;
4651 }
4652
4653 if (!syncobj_count)
4654 return VK_SUCCESS;
4655
4656 uint64_t *points = malloc((sizeof(uint64_t) + sizeof(uint32_t)) * syncobj_count);
4657 if (!points)
4658 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4659
4660 uint32_t *syncobj = (uint32_t*)(points + syncobj_count);
4661
4662 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4663 if (submission->wait_semaphores[i]->kind != RADV_SEMAPHORE_TIMELINE_SYNCOBJ)
4664 continue;
4665
4666 if (submission->wait_semaphores[i]->timeline_syncobj.max_point >= submission->wait_values[i])
4667 continue;
4668
4669 syncobj[syncobj_idx] = submission->wait_semaphores[i]->syncobj;
4670 points[syncobj_idx] = submission->wait_values[i];
4671 ++syncobj_idx;
4672 }
4673 bool success = device->ws->wait_timeline_syncobj(device->ws, syncobj, points, syncobj_idx, true, true, timeout);
4674
4675 free(points);
4676 return success ? VK_SUCCESS : VK_TIMEOUT;
4677 }
4678
4679 static void* radv_queue_submission_thread_run(void *q)
4680 {
4681 struct radv_queue *queue = q;
4682
4683 pthread_mutex_lock(&queue->thread_mutex);
4684 while (!p_atomic_read(&queue->thread_exit)) {
4685 struct radv_deferred_queue_submission *submission = queue->thread_submission;
4686 struct list_head processing_list;
4687 VkResult result = VK_SUCCESS;
4688 if (!submission) {
4689 pthread_cond_wait(&queue->thread_cond, &queue->thread_mutex);
4690 continue;
4691 }
4692 pthread_mutex_unlock(&queue->thread_mutex);
4693
4694 /* Wait at most 5 seconds so we have a chance to notice shutdown when
4695 * a semaphore never gets signaled. If it takes longer we just retry
4696 * the wait next iteration. */
4697 result = wait_for_submission_timelines_available(submission,
4698 radv_get_absolute_timeout(5000000000));
4699 if (result != VK_SUCCESS) {
4700 pthread_mutex_lock(&queue->thread_mutex);
4701 continue;
4702 }
4703
4704 /* The lock isn't held but nobody will add one until we finish
4705 * the current submission. */
4706 p_atomic_set(&queue->thread_submission, NULL);
4707
4708 list_inithead(&processing_list);
4709 list_addtail(&submission->processing_list, &processing_list);
4710 result = radv_process_submissions(&processing_list);
4711
4712 pthread_mutex_lock(&queue->thread_mutex);
4713 }
4714 pthread_mutex_unlock(&queue->thread_mutex);
4715 return NULL;
4716 }
4717
4718 static VkResult
4719 radv_queue_trigger_submission(struct radv_deferred_queue_submission *submission,
4720 uint32_t decrement,
4721 struct list_head *processing_list)
4722 {
4723 struct radv_queue *queue = submission->queue;
4724 int ret;
4725 if (p_atomic_add_return(&submission->submission_wait_count, -decrement))
4726 return VK_SUCCESS;
4727
4728 if (wait_for_submission_timelines_available(submission, radv_get_absolute_timeout(0)) == VK_SUCCESS) {
4729 list_addtail(&submission->processing_list, processing_list);
4730 return VK_SUCCESS;
4731 }
4732
4733 pthread_mutex_lock(&queue->thread_mutex);
4734
4735 /* A submission can only be ready for the thread if it doesn't have
4736 * any predecessors in the same queue, so there can only be one such
4737 * submission at a time. */
4738 assert(queue->thread_submission == NULL);
4739
4740 /* Only start the thread on demand to save resources for the many games
4741 * which only use binary semaphores. */
4742 if (!queue->thread_running) {
4743 ret = pthread_create(&queue->submission_thread, NULL,
4744 radv_queue_submission_thread_run, queue);
4745 if (ret) {
4746 pthread_mutex_unlock(&queue->thread_mutex);
4747 return vk_errorf(queue->device->instance,
4748 VK_ERROR_DEVICE_LOST,
4749 "Failed to start submission thread");
4750 }
4751 queue->thread_running = true;
4752 }
4753
4754 queue->thread_submission = submission;
4755 pthread_mutex_unlock(&queue->thread_mutex);
4756
4757 pthread_cond_signal(&queue->thread_cond);
4758 return VK_SUCCESS;
4759 }
4760
4761 static VkResult radv_queue_submit(struct radv_queue *queue,
4762 const struct radv_queue_submission *submission)
4763 {
4764 struct radv_deferred_queue_submission *deferred = NULL;
4765
4766 VkResult result = radv_create_deferred_submission(queue, submission, &deferred);
4767 if (result != VK_SUCCESS)
4768 return result;
4769
4770 struct list_head processing_list;
4771 list_inithead(&processing_list);
4772
4773 result = radv_queue_enqueue_submission(deferred, &processing_list);
4774 if (result != VK_SUCCESS) {
4775 /* If anything is in the list we leak. */
4776 assert(list_is_empty(&processing_list));
4777 return result;
4778 }
4779 return radv_process_submissions(&processing_list);
4780 }
4781
4782 bool
4783 radv_queue_internal_submit(struct radv_queue *queue, struct radeon_cmdbuf *cs)
4784 {
4785 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
4786 struct radv_winsys_sem_info sem_info;
4787 VkResult result;
4788
4789 result = radv_alloc_sem_info(queue->device, &sem_info, 0, NULL, 0, 0,
4790 0, NULL, VK_NULL_HANDLE);
4791 if (result != VK_SUCCESS)
4792 return false;
4793
4794 result = queue->device->ws->cs_submit(ctx, queue->queue_idx, &cs, 1,
4795 NULL, NULL, &sem_info, NULL,
4796 false, NULL);
4797 radv_free_sem_info(&sem_info);
4798 if (result != VK_SUCCESS)
4799 return false;
4800
4801 return true;
4802
4803 }
4804
4805 /* Signals fence as soon as all the work currently put on queue is done. */
4806 static VkResult radv_signal_fence(struct radv_queue *queue,
4807 VkFence fence)
4808 {
4809 return radv_queue_submit(queue, &(struct radv_queue_submission) {
4810 .fence = fence
4811 });
4812 }
4813
4814 static bool radv_submit_has_effects(const VkSubmitInfo *info)
4815 {
4816 return info->commandBufferCount ||
4817 info->waitSemaphoreCount ||
4818 info->signalSemaphoreCount;
4819 }
4820
4821 VkResult radv_QueueSubmit(
4822 VkQueue _queue,
4823 uint32_t submitCount,
4824 const VkSubmitInfo* pSubmits,
4825 VkFence fence)
4826 {
4827 RADV_FROM_HANDLE(radv_queue, queue, _queue);
4828 VkResult result;
4829 uint32_t fence_idx = 0;
4830 bool flushed_caches = false;
4831
4832 if (radv_device_is_lost(queue->device))
4833 return VK_ERROR_DEVICE_LOST;
4834
4835 if (fence != VK_NULL_HANDLE) {
4836 for (uint32_t i = 0; i < submitCount; ++i)
4837 if (radv_submit_has_effects(pSubmits + i))
4838 fence_idx = i;
4839 } else
4840 fence_idx = UINT32_MAX;
4841
4842 for (uint32_t i = 0; i < submitCount; i++) {
4843 if (!radv_submit_has_effects(pSubmits + i) && fence_idx != i)
4844 continue;
4845
4846 VkPipelineStageFlags wait_dst_stage_mask = 0;
4847 for (unsigned j = 0; j < pSubmits[i].waitSemaphoreCount; ++j) {
4848 wait_dst_stage_mask |= pSubmits[i].pWaitDstStageMask[j];
4849 }
4850
4851 const VkTimelineSemaphoreSubmitInfo *timeline_info =
4852 vk_find_struct_const(pSubmits[i].pNext, TIMELINE_SEMAPHORE_SUBMIT_INFO);
4853
4854 result = radv_queue_submit(queue, &(struct radv_queue_submission) {
4855 .cmd_buffers = pSubmits[i].pCommandBuffers,
4856 .cmd_buffer_count = pSubmits[i].commandBufferCount,
4857 .wait_dst_stage_mask = wait_dst_stage_mask,
4858 .flush_caches = !flushed_caches,
4859 .wait_semaphores = pSubmits[i].pWaitSemaphores,
4860 .wait_semaphore_count = pSubmits[i].waitSemaphoreCount,
4861 .signal_semaphores = pSubmits[i].pSignalSemaphores,
4862 .signal_semaphore_count = pSubmits[i].signalSemaphoreCount,
4863 .fence = i == fence_idx ? fence : VK_NULL_HANDLE,
4864 .wait_values = timeline_info ? timeline_info->pWaitSemaphoreValues : NULL,
4865 .wait_value_count = timeline_info && timeline_info->pWaitSemaphoreValues ? timeline_info->waitSemaphoreValueCount : 0,
4866 .signal_values = timeline_info ? timeline_info->pSignalSemaphoreValues : NULL,
4867 .signal_value_count = timeline_info && timeline_info->pSignalSemaphoreValues ? timeline_info->signalSemaphoreValueCount : 0,
4868 });
4869 if (result != VK_SUCCESS)
4870 return result;
4871
4872 flushed_caches = true;
4873 }
4874
4875 if (fence != VK_NULL_HANDLE && !submitCount) {
4876 result = radv_signal_fence(queue, fence);
4877 if (result != VK_SUCCESS)
4878 return result;
4879 }
4880
4881 return VK_SUCCESS;
4882 }
4883
4884 static const char *
4885 radv_get_queue_family_name(struct radv_queue *queue)
4886 {
4887 switch (queue->queue_family_index) {
4888 case RADV_QUEUE_GENERAL:
4889 return "graphics";
4890 case RADV_QUEUE_COMPUTE:
4891 return "compute";
4892 case RADV_QUEUE_TRANSFER:
4893 return "transfer";
4894 default:
4895 unreachable("Unknown queue family");
4896 }
4897 }
4898
4899 VkResult radv_QueueWaitIdle(
4900 VkQueue _queue)
4901 {
4902 RADV_FROM_HANDLE(radv_queue, queue, _queue);
4903
4904 if (radv_device_is_lost(queue->device))
4905 return VK_ERROR_DEVICE_LOST;
4906
4907 pthread_mutex_lock(&queue->pending_mutex);
4908 while (!list_is_empty(&queue->pending_submissions)) {
4909 pthread_cond_wait(&queue->device->timeline_cond, &queue->pending_mutex);
4910 }
4911 pthread_mutex_unlock(&queue->pending_mutex);
4912
4913 if (!queue->device->ws->ctx_wait_idle(queue->hw_ctx,
4914 radv_queue_family_to_ring(queue->queue_family_index),
4915 queue->queue_idx)) {
4916 return radv_device_set_lost(queue->device,
4917 "Failed to wait for a '%s' queue "
4918 "to be idle. GPU hang ?",
4919 radv_get_queue_family_name(queue));
4920 }
4921
4922 return VK_SUCCESS;
4923 }
4924
4925 VkResult radv_DeviceWaitIdle(
4926 VkDevice _device)
4927 {
4928 RADV_FROM_HANDLE(radv_device, device, _device);
4929
4930 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
4931 for (unsigned q = 0; q < device->queue_count[i]; q++) {
4932 VkResult result =
4933 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
4934
4935 if (result != VK_SUCCESS)
4936 return result;
4937 }
4938 }
4939 return VK_SUCCESS;
4940 }
4941
4942 VkResult radv_EnumerateInstanceExtensionProperties(
4943 const char* pLayerName,
4944 uint32_t* pPropertyCount,
4945 VkExtensionProperties* pProperties)
4946 {
4947 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
4948
4949 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
4950 if (radv_instance_extensions_supported.extensions[i]) {
4951 vk_outarray_append(&out, prop) {
4952 *prop = radv_instance_extensions[i];
4953 }
4954 }
4955 }
4956
4957 return vk_outarray_status(&out);
4958 }
4959
4960 VkResult radv_EnumerateDeviceExtensionProperties(
4961 VkPhysicalDevice physicalDevice,
4962 const char* pLayerName,
4963 uint32_t* pPropertyCount,
4964 VkExtensionProperties* pProperties)
4965 {
4966 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
4967 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
4968
4969 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
4970 if (device->supported_extensions.extensions[i]) {
4971 vk_outarray_append(&out, prop) {
4972 *prop = radv_device_extensions[i];
4973 }
4974 }
4975 }
4976
4977 return vk_outarray_status(&out);
4978 }
4979
4980 PFN_vkVoidFunction radv_GetInstanceProcAddr(
4981 VkInstance _instance,
4982 const char* pName)
4983 {
4984 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4985
4986 /* The Vulkan 1.0 spec for vkGetInstanceProcAddr has a table of exactly
4987 * when we have to return valid function pointers, NULL, or it's left
4988 * undefined. See the table for exact details.
4989 */
4990 if (pName == NULL)
4991 return NULL;
4992
4993 #define LOOKUP_RADV_ENTRYPOINT(entrypoint) \
4994 if (strcmp(pName, "vk" #entrypoint) == 0) \
4995 return (PFN_vkVoidFunction)radv_##entrypoint
4996
4997 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceExtensionProperties);
4998 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceLayerProperties);
4999 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceVersion);
5000 LOOKUP_RADV_ENTRYPOINT(CreateInstance);
5001
5002 /* GetInstanceProcAddr() can also be called with a NULL instance.
5003 * See https://gitlab.khronos.org/vulkan/vulkan/issues/2057
5004 */
5005 LOOKUP_RADV_ENTRYPOINT(GetInstanceProcAddr);
5006
5007 #undef LOOKUP_RADV_ENTRYPOINT
5008
5009 if (instance == NULL)
5010 return NULL;
5011
5012 int idx = radv_get_instance_entrypoint_index(pName);
5013 if (idx >= 0)
5014 return instance->dispatch.entrypoints[idx];
5015
5016 idx = radv_get_physical_device_entrypoint_index(pName);
5017 if (idx >= 0)
5018 return instance->physical_device_dispatch.entrypoints[idx];
5019
5020 idx = radv_get_device_entrypoint_index(pName);
5021 if (idx >= 0)
5022 return instance->device_dispatch.entrypoints[idx];
5023
5024 return NULL;
5025 }
5026
5027 /* The loader wants us to expose a second GetInstanceProcAddr function
5028 * to work around certain LD_PRELOAD issues seen in apps.
5029 */
5030 PUBLIC
5031 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
5032 VkInstance instance,
5033 const char* pName);
5034
5035 PUBLIC
5036 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
5037 VkInstance instance,
5038 const char* pName)
5039 {
5040 return radv_GetInstanceProcAddr(instance, pName);
5041 }
5042
5043 PUBLIC
5044 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
5045 VkInstance _instance,
5046 const char* pName);
5047
5048 PUBLIC
5049 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
5050 VkInstance _instance,
5051 const char* pName)
5052 {
5053 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5054
5055 if (!pName || !instance)
5056 return NULL;
5057
5058 int idx = radv_get_physical_device_entrypoint_index(pName);
5059 if (idx < 0)
5060 return NULL;
5061
5062 return instance->physical_device_dispatch.entrypoints[idx];
5063 }
5064
5065 PFN_vkVoidFunction radv_GetDeviceProcAddr(
5066 VkDevice _device,
5067 const char* pName)
5068 {
5069 RADV_FROM_HANDLE(radv_device, device, _device);
5070
5071 if (!device || !pName)
5072 return NULL;
5073
5074 int idx = radv_get_device_entrypoint_index(pName);
5075 if (idx < 0)
5076 return NULL;
5077
5078 return device->dispatch.entrypoints[idx];
5079 }
5080
5081 bool radv_get_memory_fd(struct radv_device *device,
5082 struct radv_device_memory *memory,
5083 int *pFD)
5084 {
5085 struct radeon_bo_metadata metadata;
5086
5087 if (memory->image) {
5088 if (memory->image->tiling != VK_IMAGE_TILING_LINEAR)
5089 radv_init_metadata(device, memory->image, &metadata);
5090 device->ws->buffer_set_metadata(memory->bo, &metadata);
5091 }
5092
5093 return device->ws->buffer_get_fd(device->ws, memory->bo,
5094 pFD);
5095 }
5096
5097
5098 void
5099 radv_free_memory(struct radv_device *device,
5100 const VkAllocationCallbacks* pAllocator,
5101 struct radv_device_memory *mem)
5102 {
5103 if (mem == NULL)
5104 return;
5105
5106 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
5107 if (mem->android_hardware_buffer)
5108 AHardwareBuffer_release(mem->android_hardware_buffer);
5109 #endif
5110
5111 if (mem->bo) {
5112 if (device->overallocation_disallowed) {
5113 mtx_lock(&device->overallocation_mutex);
5114 device->allocated_memory_size[mem->heap_index] -= mem->alloc_size;
5115 mtx_unlock(&device->overallocation_mutex);
5116 }
5117
5118 radv_bo_list_remove(device, mem->bo);
5119 device->ws->buffer_destroy(mem->bo);
5120 mem->bo = NULL;
5121 }
5122
5123 vk_object_base_finish(&mem->base);
5124 vk_free2(&device->vk.alloc, pAllocator, mem);
5125 }
5126
5127 static VkResult radv_alloc_memory(struct radv_device *device,
5128 const VkMemoryAllocateInfo* pAllocateInfo,
5129 const VkAllocationCallbacks* pAllocator,
5130 VkDeviceMemory* pMem)
5131 {
5132 struct radv_device_memory *mem;
5133 VkResult result;
5134 enum radeon_bo_domain domain;
5135 uint32_t flags = 0;
5136
5137 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
5138
5139 const VkImportMemoryFdInfoKHR *import_info =
5140 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
5141 const VkMemoryDedicatedAllocateInfo *dedicate_info =
5142 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
5143 const VkExportMemoryAllocateInfo *export_info =
5144 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
5145 const struct VkImportAndroidHardwareBufferInfoANDROID *ahb_import_info =
5146 vk_find_struct_const(pAllocateInfo->pNext,
5147 IMPORT_ANDROID_HARDWARE_BUFFER_INFO_ANDROID);
5148 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
5149 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
5150
5151 const struct wsi_memory_allocate_info *wsi_info =
5152 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
5153
5154 if (pAllocateInfo->allocationSize == 0 && !ahb_import_info &&
5155 !(export_info && (export_info->handleTypes & VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID))) {
5156 /* Apparently, this is allowed */
5157 *pMem = VK_NULL_HANDLE;
5158 return VK_SUCCESS;
5159 }
5160
5161 mem = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*mem), 8,
5162 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5163 if (mem == NULL)
5164 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5165
5166 vk_object_base_init(&device->vk, &mem->base,
5167 VK_OBJECT_TYPE_DEVICE_MEMORY);
5168
5169 if (wsi_info && wsi_info->implicit_sync)
5170 flags |= RADEON_FLAG_IMPLICIT_SYNC;
5171
5172 if (dedicate_info) {
5173 mem->image = radv_image_from_handle(dedicate_info->image);
5174 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
5175 } else {
5176 mem->image = NULL;
5177 mem->buffer = NULL;
5178 }
5179
5180 float priority_float = 0.5;
5181 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
5182 vk_find_struct_const(pAllocateInfo->pNext,
5183 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
5184 if (priority_ext)
5185 priority_float = priority_ext->priority;
5186
5187 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
5188 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
5189
5190 mem->user_ptr = NULL;
5191 mem->bo = NULL;
5192
5193 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
5194 mem->android_hardware_buffer = NULL;
5195 #endif
5196
5197 if (ahb_import_info) {
5198 result = radv_import_ahb_memory(device, mem, priority, ahb_import_info);
5199 if (result != VK_SUCCESS)
5200 goto fail;
5201 } else if(export_info && (export_info->handleTypes & VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID)) {
5202 result = radv_create_ahb_memory(device, mem, priority, pAllocateInfo);
5203 if (result != VK_SUCCESS)
5204 goto fail;
5205 } else if (import_info) {
5206 assert(import_info->handleType ==
5207 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
5208 import_info->handleType ==
5209 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
5210 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
5211 priority, NULL);
5212 if (!mem->bo) {
5213 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
5214 goto fail;
5215 } else {
5216 close(import_info->fd);
5217 }
5218
5219 if (mem->image && mem->image->plane_count == 1 &&
5220 !vk_format_is_depth_or_stencil(mem->image->vk_format)) {
5221 struct radeon_bo_metadata metadata;
5222 device->ws->buffer_get_metadata(mem->bo, &metadata);
5223
5224 struct radv_image_create_info create_info = {
5225 .no_metadata_planes = true,
5226 .bo_metadata = &metadata
5227 };
5228
5229 /* This gives a basic ability to import radeonsi images
5230 * that don't have DCC. This is not guaranteed by any
5231 * spec and can be removed after we support modifiers. */
5232 result = radv_image_create_layout(device, create_info, mem->image);
5233 if (result != VK_SUCCESS) {
5234 device->ws->buffer_destroy(mem->bo);
5235 goto fail;
5236 }
5237 }
5238 } else if (host_ptr_info) {
5239 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
5240 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
5241 pAllocateInfo->allocationSize,
5242 priority);
5243 if (!mem->bo) {
5244 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
5245 goto fail;
5246 } else {
5247 mem->user_ptr = host_ptr_info->pHostPointer;
5248 }
5249 } else {
5250 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
5251 uint32_t heap_index;
5252
5253 heap_index = device->physical_device->memory_properties.memoryTypes[pAllocateInfo->memoryTypeIndex].heapIndex;
5254 domain = device->physical_device->memory_domains[pAllocateInfo->memoryTypeIndex];
5255 flags |= device->physical_device->memory_flags[pAllocateInfo->memoryTypeIndex];
5256
5257 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes)) {
5258 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
5259 if (device->use_global_bo_list) {
5260 flags |= RADEON_FLAG_PREFER_LOCAL_BO;
5261 }
5262 }
5263
5264 if (device->overallocation_disallowed) {
5265 uint64_t total_size =
5266 device->physical_device->memory_properties.memoryHeaps[heap_index].size;
5267
5268 mtx_lock(&device->overallocation_mutex);
5269 if (device->allocated_memory_size[heap_index] + alloc_size > total_size) {
5270 mtx_unlock(&device->overallocation_mutex);
5271 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
5272 goto fail;
5273 }
5274 device->allocated_memory_size[heap_index] += alloc_size;
5275 mtx_unlock(&device->overallocation_mutex);
5276 }
5277
5278 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
5279 domain, flags, priority);
5280
5281 if (!mem->bo) {
5282 if (device->overallocation_disallowed) {
5283 mtx_lock(&device->overallocation_mutex);
5284 device->allocated_memory_size[heap_index] -= alloc_size;
5285 mtx_unlock(&device->overallocation_mutex);
5286 }
5287 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
5288 goto fail;
5289 }
5290
5291 mem->heap_index = heap_index;
5292 mem->alloc_size = alloc_size;
5293 }
5294
5295 if (!wsi_info) {
5296 result = radv_bo_list_add(device, mem->bo);
5297 if (result != VK_SUCCESS)
5298 goto fail;
5299 }
5300
5301 *pMem = radv_device_memory_to_handle(mem);
5302
5303 return VK_SUCCESS;
5304
5305 fail:
5306 radv_free_memory(device, pAllocator,mem);
5307
5308 return result;
5309 }
5310
5311 VkResult radv_AllocateMemory(
5312 VkDevice _device,
5313 const VkMemoryAllocateInfo* pAllocateInfo,
5314 const VkAllocationCallbacks* pAllocator,
5315 VkDeviceMemory* pMem)
5316 {
5317 RADV_FROM_HANDLE(radv_device, device, _device);
5318 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
5319 }
5320
5321 void radv_FreeMemory(
5322 VkDevice _device,
5323 VkDeviceMemory _mem,
5324 const VkAllocationCallbacks* pAllocator)
5325 {
5326 RADV_FROM_HANDLE(radv_device, device, _device);
5327 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
5328
5329 radv_free_memory(device, pAllocator, mem);
5330 }
5331
5332 VkResult radv_MapMemory(
5333 VkDevice _device,
5334 VkDeviceMemory _memory,
5335 VkDeviceSize offset,
5336 VkDeviceSize size,
5337 VkMemoryMapFlags flags,
5338 void** ppData)
5339 {
5340 RADV_FROM_HANDLE(radv_device, device, _device);
5341 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
5342
5343 if (mem == NULL) {
5344 *ppData = NULL;
5345 return VK_SUCCESS;
5346 }
5347
5348 if (mem->user_ptr)
5349 *ppData = mem->user_ptr;
5350 else
5351 *ppData = device->ws->buffer_map(mem->bo);
5352
5353 if (*ppData) {
5354 *ppData += offset;
5355 return VK_SUCCESS;
5356 }
5357
5358 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
5359 }
5360
5361 void radv_UnmapMemory(
5362 VkDevice _device,
5363 VkDeviceMemory _memory)
5364 {
5365 RADV_FROM_HANDLE(radv_device, device, _device);
5366 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
5367
5368 if (mem == NULL)
5369 return;
5370
5371 if (mem->user_ptr == NULL)
5372 device->ws->buffer_unmap(mem->bo);
5373 }
5374
5375 VkResult radv_FlushMappedMemoryRanges(
5376 VkDevice _device,
5377 uint32_t memoryRangeCount,
5378 const VkMappedMemoryRange* pMemoryRanges)
5379 {
5380 return VK_SUCCESS;
5381 }
5382
5383 VkResult radv_InvalidateMappedMemoryRanges(
5384 VkDevice _device,
5385 uint32_t memoryRangeCount,
5386 const VkMappedMemoryRange* pMemoryRanges)
5387 {
5388 return VK_SUCCESS;
5389 }
5390
5391 void radv_GetBufferMemoryRequirements(
5392 VkDevice _device,
5393 VkBuffer _buffer,
5394 VkMemoryRequirements* pMemoryRequirements)
5395 {
5396 RADV_FROM_HANDLE(radv_device, device, _device);
5397 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5398
5399 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
5400
5401 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
5402 pMemoryRequirements->alignment = 4096;
5403 else
5404 pMemoryRequirements->alignment = 16;
5405
5406 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
5407 }
5408
5409 void radv_GetBufferMemoryRequirements2(
5410 VkDevice device,
5411 const VkBufferMemoryRequirementsInfo2 *pInfo,
5412 VkMemoryRequirements2 *pMemoryRequirements)
5413 {
5414 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
5415 &pMemoryRequirements->memoryRequirements);
5416 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
5417 switch (ext->sType) {
5418 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
5419 VkMemoryDedicatedRequirements *req =
5420 (VkMemoryDedicatedRequirements *) ext;
5421 req->requiresDedicatedAllocation = false;
5422 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
5423 break;
5424 }
5425 default:
5426 break;
5427 }
5428 }
5429 }
5430
5431 void radv_GetImageMemoryRequirements(
5432 VkDevice _device,
5433 VkImage _image,
5434 VkMemoryRequirements* pMemoryRequirements)
5435 {
5436 RADV_FROM_HANDLE(radv_device, device, _device);
5437 RADV_FROM_HANDLE(radv_image, image, _image);
5438
5439 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
5440
5441 pMemoryRequirements->size = image->size;
5442 pMemoryRequirements->alignment = image->alignment;
5443 }
5444
5445 void radv_GetImageMemoryRequirements2(
5446 VkDevice device,
5447 const VkImageMemoryRequirementsInfo2 *pInfo,
5448 VkMemoryRequirements2 *pMemoryRequirements)
5449 {
5450 radv_GetImageMemoryRequirements(device, pInfo->image,
5451 &pMemoryRequirements->memoryRequirements);
5452
5453 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
5454
5455 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
5456 switch (ext->sType) {
5457 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
5458 VkMemoryDedicatedRequirements *req =
5459 (VkMemoryDedicatedRequirements *) ext;
5460 req->requiresDedicatedAllocation = image->shareable &&
5461 image->tiling != VK_IMAGE_TILING_LINEAR;
5462 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
5463 break;
5464 }
5465 default:
5466 break;
5467 }
5468 }
5469 }
5470
5471 void radv_GetImageSparseMemoryRequirements(
5472 VkDevice device,
5473 VkImage image,
5474 uint32_t* pSparseMemoryRequirementCount,
5475 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
5476 {
5477 stub();
5478 }
5479
5480 void radv_GetImageSparseMemoryRequirements2(
5481 VkDevice device,
5482 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
5483 uint32_t* pSparseMemoryRequirementCount,
5484 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
5485 {
5486 stub();
5487 }
5488
5489 void radv_GetDeviceMemoryCommitment(
5490 VkDevice device,
5491 VkDeviceMemory memory,
5492 VkDeviceSize* pCommittedMemoryInBytes)
5493 {
5494 *pCommittedMemoryInBytes = 0;
5495 }
5496
5497 VkResult radv_BindBufferMemory2(VkDevice device,
5498 uint32_t bindInfoCount,
5499 const VkBindBufferMemoryInfo *pBindInfos)
5500 {
5501 for (uint32_t i = 0; i < bindInfoCount; ++i) {
5502 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
5503 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
5504
5505 if (mem) {
5506 buffer->bo = mem->bo;
5507 buffer->offset = pBindInfos[i].memoryOffset;
5508 } else {
5509 buffer->bo = NULL;
5510 }
5511 }
5512 return VK_SUCCESS;
5513 }
5514
5515 VkResult radv_BindBufferMemory(
5516 VkDevice device,
5517 VkBuffer buffer,
5518 VkDeviceMemory memory,
5519 VkDeviceSize memoryOffset)
5520 {
5521 const VkBindBufferMemoryInfo info = {
5522 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
5523 .buffer = buffer,
5524 .memory = memory,
5525 .memoryOffset = memoryOffset
5526 };
5527
5528 return radv_BindBufferMemory2(device, 1, &info);
5529 }
5530
5531 VkResult radv_BindImageMemory2(VkDevice device,
5532 uint32_t bindInfoCount,
5533 const VkBindImageMemoryInfo *pBindInfos)
5534 {
5535 for (uint32_t i = 0; i < bindInfoCount; ++i) {
5536 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
5537 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
5538
5539 if (mem) {
5540 image->bo = mem->bo;
5541 image->offset = pBindInfos[i].memoryOffset;
5542 } else {
5543 image->bo = NULL;
5544 image->offset = 0;
5545 }
5546 }
5547 return VK_SUCCESS;
5548 }
5549
5550
5551 VkResult radv_BindImageMemory(
5552 VkDevice device,
5553 VkImage image,
5554 VkDeviceMemory memory,
5555 VkDeviceSize memoryOffset)
5556 {
5557 const VkBindImageMemoryInfo info = {
5558 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
5559 .image = image,
5560 .memory = memory,
5561 .memoryOffset = memoryOffset
5562 };
5563
5564 return radv_BindImageMemory2(device, 1, &info);
5565 }
5566
5567 static bool radv_sparse_bind_has_effects(const VkBindSparseInfo *info)
5568 {
5569 return info->bufferBindCount ||
5570 info->imageOpaqueBindCount ||
5571 info->imageBindCount ||
5572 info->waitSemaphoreCount ||
5573 info->signalSemaphoreCount;
5574 }
5575
5576 VkResult radv_QueueBindSparse(
5577 VkQueue _queue,
5578 uint32_t bindInfoCount,
5579 const VkBindSparseInfo* pBindInfo,
5580 VkFence fence)
5581 {
5582 RADV_FROM_HANDLE(radv_queue, queue, _queue);
5583 VkResult result;
5584 uint32_t fence_idx = 0;
5585
5586 if (radv_device_is_lost(queue->device))
5587 return VK_ERROR_DEVICE_LOST;
5588
5589 if (fence != VK_NULL_HANDLE) {
5590 for (uint32_t i = 0; i < bindInfoCount; ++i)
5591 if (radv_sparse_bind_has_effects(pBindInfo + i))
5592 fence_idx = i;
5593 } else
5594 fence_idx = UINT32_MAX;
5595
5596 for (uint32_t i = 0; i < bindInfoCount; ++i) {
5597 if (i != fence_idx && !radv_sparse_bind_has_effects(pBindInfo + i))
5598 continue;
5599
5600 const VkTimelineSemaphoreSubmitInfo *timeline_info =
5601 vk_find_struct_const(pBindInfo[i].pNext, TIMELINE_SEMAPHORE_SUBMIT_INFO);
5602
5603 VkResult result = radv_queue_submit(queue, &(struct radv_queue_submission) {
5604 .buffer_binds = pBindInfo[i].pBufferBinds,
5605 .buffer_bind_count = pBindInfo[i].bufferBindCount,
5606 .image_opaque_binds = pBindInfo[i].pImageOpaqueBinds,
5607 .image_opaque_bind_count = pBindInfo[i].imageOpaqueBindCount,
5608 .wait_semaphores = pBindInfo[i].pWaitSemaphores,
5609 .wait_semaphore_count = pBindInfo[i].waitSemaphoreCount,
5610 .signal_semaphores = pBindInfo[i].pSignalSemaphores,
5611 .signal_semaphore_count = pBindInfo[i].signalSemaphoreCount,
5612 .fence = i == fence_idx ? fence : VK_NULL_HANDLE,
5613 .wait_values = timeline_info ? timeline_info->pWaitSemaphoreValues : NULL,
5614 .wait_value_count = timeline_info && timeline_info->pWaitSemaphoreValues ? timeline_info->waitSemaphoreValueCount : 0,
5615 .signal_values = timeline_info ? timeline_info->pSignalSemaphoreValues : NULL,
5616 .signal_value_count = timeline_info && timeline_info->pSignalSemaphoreValues ? timeline_info->signalSemaphoreValueCount : 0,
5617 });
5618
5619 if (result != VK_SUCCESS)
5620 return result;
5621 }
5622
5623 if (fence != VK_NULL_HANDLE && !bindInfoCount) {
5624 result = radv_signal_fence(queue, fence);
5625 if (result != VK_SUCCESS)
5626 return result;
5627 }
5628
5629 return VK_SUCCESS;
5630 }
5631
5632 static void
5633 radv_destroy_fence_part(struct radv_device *device,
5634 struct radv_fence_part *part)
5635 {
5636 switch (part->kind) {
5637 case RADV_FENCE_NONE:
5638 break;
5639 case RADV_FENCE_WINSYS:
5640 device->ws->destroy_fence(part->fence);
5641 break;
5642 case RADV_FENCE_SYNCOBJ:
5643 device->ws->destroy_syncobj(device->ws, part->syncobj);
5644 break;
5645 case RADV_FENCE_WSI:
5646 part->fence_wsi->destroy(part->fence_wsi);
5647 break;
5648 default:
5649 unreachable("Invalid fence type");
5650 }
5651
5652 part->kind = RADV_FENCE_NONE;
5653 }
5654
5655 static void
5656 radv_destroy_fence(struct radv_device *device,
5657 const VkAllocationCallbacks *pAllocator,
5658 struct radv_fence *fence)
5659 {
5660 radv_destroy_fence_part(device, &fence->temporary);
5661 radv_destroy_fence_part(device, &fence->permanent);
5662
5663 vk_object_base_finish(&fence->base);
5664 vk_free2(&device->vk.alloc, pAllocator, fence);
5665 }
5666
5667 VkResult radv_CreateFence(
5668 VkDevice _device,
5669 const VkFenceCreateInfo* pCreateInfo,
5670 const VkAllocationCallbacks* pAllocator,
5671 VkFence* pFence)
5672 {
5673 RADV_FROM_HANDLE(radv_device, device, _device);
5674 const VkExportFenceCreateInfo *export =
5675 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
5676 VkExternalFenceHandleTypeFlags handleTypes =
5677 export ? export->handleTypes : 0;
5678 struct radv_fence *fence;
5679
5680 fence = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*fence), 8,
5681 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5682 if (!fence)
5683 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5684
5685 vk_object_base_init(&device->vk, &fence->base, VK_OBJECT_TYPE_FENCE);
5686
5687 if (device->always_use_syncobj || handleTypes) {
5688 fence->permanent.kind = RADV_FENCE_SYNCOBJ;
5689
5690 bool create_signaled = false;
5691 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
5692 create_signaled = true;
5693
5694 int ret = device->ws->create_syncobj(device->ws, create_signaled,
5695 &fence->permanent.syncobj);
5696 if (ret) {
5697 radv_destroy_fence(device, pAllocator, fence);
5698 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5699 }
5700 } else {
5701 fence->permanent.kind = RADV_FENCE_WINSYS;
5702
5703 fence->permanent.fence = device->ws->create_fence();
5704 if (!fence->permanent.fence) {
5705 vk_free2(&device->vk.alloc, pAllocator, fence);
5706 radv_destroy_fence(device, pAllocator, fence);
5707 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5708 }
5709 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
5710 device->ws->signal_fence(fence->permanent.fence);
5711 }
5712
5713 *pFence = radv_fence_to_handle(fence);
5714
5715 return VK_SUCCESS;
5716 }
5717
5718
5719 void radv_DestroyFence(
5720 VkDevice _device,
5721 VkFence _fence,
5722 const VkAllocationCallbacks* pAllocator)
5723 {
5724 RADV_FROM_HANDLE(radv_device, device, _device);
5725 RADV_FROM_HANDLE(radv_fence, fence, _fence);
5726
5727 if (!fence)
5728 return;
5729
5730 radv_destroy_fence(device, pAllocator, fence);
5731 }
5732
5733 static bool radv_all_fences_plain_and_submitted(struct radv_device *device,
5734 uint32_t fenceCount, const VkFence *pFences)
5735 {
5736 for (uint32_t i = 0; i < fenceCount; ++i) {
5737 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5738
5739 struct radv_fence_part *part =
5740 fence->temporary.kind != RADV_FENCE_NONE ?
5741 &fence->temporary : &fence->permanent;
5742 if (part->kind != RADV_FENCE_WINSYS ||
5743 !device->ws->is_fence_waitable(part->fence))
5744 return false;
5745 }
5746 return true;
5747 }
5748
5749 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
5750 {
5751 for (uint32_t i = 0; i < fenceCount; ++i) {
5752 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5753
5754 struct radv_fence_part *part =
5755 fence->temporary.kind != RADV_FENCE_NONE ?
5756 &fence->temporary : &fence->permanent;
5757 if (part->kind != RADV_FENCE_SYNCOBJ)
5758 return false;
5759 }
5760 return true;
5761 }
5762
5763 VkResult radv_WaitForFences(
5764 VkDevice _device,
5765 uint32_t fenceCount,
5766 const VkFence* pFences,
5767 VkBool32 waitAll,
5768 uint64_t timeout)
5769 {
5770 RADV_FROM_HANDLE(radv_device, device, _device);
5771
5772 if (radv_device_is_lost(device))
5773 return VK_ERROR_DEVICE_LOST;
5774
5775 timeout = radv_get_absolute_timeout(timeout);
5776
5777 if (device->always_use_syncobj &&
5778 radv_all_fences_syncobj(fenceCount, pFences))
5779 {
5780 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
5781 if (!handles)
5782 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5783
5784 for (uint32_t i = 0; i < fenceCount; ++i) {
5785 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5786
5787 struct radv_fence_part *part =
5788 fence->temporary.kind != RADV_FENCE_NONE ?
5789 &fence->temporary : &fence->permanent;
5790
5791 assert(part->kind == RADV_FENCE_SYNCOBJ);
5792 handles[i] = part->syncobj;
5793 }
5794
5795 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
5796
5797 free(handles);
5798 return success ? VK_SUCCESS : VK_TIMEOUT;
5799 }
5800
5801 if (!waitAll && fenceCount > 1) {
5802 /* Not doing this by default for waitAll, due to needing to allocate twice. */
5803 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(device, fenceCount, pFences)) {
5804 uint32_t wait_count = 0;
5805 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
5806 if (!fences)
5807 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5808
5809 for (uint32_t i = 0; i < fenceCount; ++i) {
5810 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5811
5812 struct radv_fence_part *part =
5813 fence->temporary.kind != RADV_FENCE_NONE ?
5814 &fence->temporary : &fence->permanent;
5815 assert(part->kind == RADV_FENCE_WINSYS);
5816
5817 if (device->ws->fence_wait(device->ws, part->fence, false, 0)) {
5818 free(fences);
5819 return VK_SUCCESS;
5820 }
5821
5822 fences[wait_count++] = part->fence;
5823 }
5824
5825 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
5826 waitAll, timeout - radv_get_current_time());
5827
5828 free(fences);
5829 return success ? VK_SUCCESS : VK_TIMEOUT;
5830 }
5831
5832 while(radv_get_current_time() <= timeout) {
5833 for (uint32_t i = 0; i < fenceCount; ++i) {
5834 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
5835 return VK_SUCCESS;
5836 }
5837 }
5838 return VK_TIMEOUT;
5839 }
5840
5841 for (uint32_t i = 0; i < fenceCount; ++i) {
5842 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5843 bool expired = false;
5844
5845 struct radv_fence_part *part =
5846 fence->temporary.kind != RADV_FENCE_NONE ?
5847 &fence->temporary : &fence->permanent;
5848
5849 switch (part->kind) {
5850 case RADV_FENCE_NONE:
5851 break;
5852 case RADV_FENCE_WINSYS:
5853 if (!device->ws->is_fence_waitable(part->fence)) {
5854 while (!device->ws->is_fence_waitable(part->fence) &&
5855 radv_get_current_time() <= timeout)
5856 /* Do nothing */;
5857 }
5858
5859 expired = device->ws->fence_wait(device->ws,
5860 part->fence,
5861 true, timeout);
5862 if (!expired)
5863 return VK_TIMEOUT;
5864 break;
5865 case RADV_FENCE_SYNCOBJ:
5866 if (!device->ws->wait_syncobj(device->ws,
5867 &part->syncobj, 1, true,
5868 timeout))
5869 return VK_TIMEOUT;
5870 break;
5871 case RADV_FENCE_WSI: {
5872 VkResult result = part->fence_wsi->wait(part->fence_wsi, timeout);
5873 if (result != VK_SUCCESS)
5874 return result;
5875 break;
5876 }
5877 default:
5878 unreachable("Invalid fence type");
5879 }
5880 }
5881
5882 return VK_SUCCESS;
5883 }
5884
5885 VkResult radv_ResetFences(VkDevice _device,
5886 uint32_t fenceCount,
5887 const VkFence *pFences)
5888 {
5889 RADV_FROM_HANDLE(radv_device, device, _device);
5890
5891 for (unsigned i = 0; i < fenceCount; ++i) {
5892 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5893
5894 /* From the Vulkan 1.0.53 spec:
5895 *
5896 * "If any member of pFences currently has its payload
5897 * imported with temporary permanence, that fence’s prior
5898 * permanent payload is irst restored. The remaining
5899 * operations described therefore operate on the restored
5900 * payload."
5901 */
5902 if (fence->temporary.kind != RADV_FENCE_NONE)
5903 radv_destroy_fence_part(device, &fence->temporary);
5904
5905 struct radv_fence_part *part = &fence->permanent;
5906
5907 switch (part->kind) {
5908 case RADV_FENCE_WSI:
5909 device->ws->reset_fence(part->fence);
5910 break;
5911 case RADV_FENCE_SYNCOBJ:
5912 device->ws->reset_syncobj(device->ws, part->syncobj);
5913 break;
5914 default:
5915 unreachable("Invalid fence type");
5916 }
5917 }
5918
5919 return VK_SUCCESS;
5920 }
5921
5922 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
5923 {
5924 RADV_FROM_HANDLE(radv_device, device, _device);
5925 RADV_FROM_HANDLE(radv_fence, fence, _fence);
5926
5927 struct radv_fence_part *part =
5928 fence->temporary.kind != RADV_FENCE_NONE ?
5929 &fence->temporary : &fence->permanent;
5930
5931 if (radv_device_is_lost(device))
5932 return VK_ERROR_DEVICE_LOST;
5933
5934 switch (part->kind) {
5935 case RADV_FENCE_NONE:
5936 break;
5937 case RADV_FENCE_WINSYS:
5938 if (!device->ws->fence_wait(device->ws, part->fence, false, 0))
5939 return VK_NOT_READY;
5940 break;
5941 case RADV_FENCE_SYNCOBJ: {
5942 bool success = device->ws->wait_syncobj(device->ws,
5943 &part->syncobj, 1, true, 0);
5944 if (!success)
5945 return VK_NOT_READY;
5946 break;
5947 }
5948 case RADV_FENCE_WSI: {
5949 VkResult result = part->fence_wsi->wait(part->fence_wsi, 0);
5950 if (result != VK_SUCCESS) {
5951 if (result == VK_TIMEOUT)
5952 return VK_NOT_READY;
5953 return result;
5954 }
5955 break;
5956 }
5957 default:
5958 unreachable("Invalid fence type");
5959 }
5960
5961 return VK_SUCCESS;
5962 }
5963
5964
5965 // Queue semaphore functions
5966
5967 static void
5968 radv_create_timeline(struct radv_timeline *timeline, uint64_t value)
5969 {
5970 timeline->highest_signaled = value;
5971 timeline->highest_submitted = value;
5972 list_inithead(&timeline->points);
5973 list_inithead(&timeline->free_points);
5974 list_inithead(&timeline->waiters);
5975 pthread_mutex_init(&timeline->mutex, NULL);
5976 }
5977
5978 static void
5979 radv_destroy_timeline(struct radv_device *device,
5980 struct radv_timeline *timeline)
5981 {
5982 list_for_each_entry_safe(struct radv_timeline_point, point,
5983 &timeline->free_points, list) {
5984 list_del(&point->list);
5985 device->ws->destroy_syncobj(device->ws, point->syncobj);
5986 free(point);
5987 }
5988 list_for_each_entry_safe(struct radv_timeline_point, point,
5989 &timeline->points, list) {
5990 list_del(&point->list);
5991 device->ws->destroy_syncobj(device->ws, point->syncobj);
5992 free(point);
5993 }
5994 pthread_mutex_destroy(&timeline->mutex);
5995 }
5996
5997 static void
5998 radv_timeline_gc_locked(struct radv_device *device,
5999 struct radv_timeline *timeline)
6000 {
6001 list_for_each_entry_safe(struct radv_timeline_point, point,
6002 &timeline->points, list) {
6003 if (point->wait_count || point->value > timeline->highest_submitted)
6004 return;
6005
6006 if (device->ws->wait_syncobj(device->ws, &point->syncobj, 1, true, 0)) {
6007 timeline->highest_signaled = point->value;
6008 list_del(&point->list);
6009 list_add(&point->list, &timeline->free_points);
6010 }
6011 }
6012 }
6013
6014 static struct radv_timeline_point *
6015 radv_timeline_find_point_at_least_locked(struct radv_device *device,
6016 struct radv_timeline *timeline,
6017 uint64_t p)
6018 {
6019 radv_timeline_gc_locked(device, timeline);
6020
6021 if (p <= timeline->highest_signaled)
6022 return NULL;
6023
6024 list_for_each_entry(struct radv_timeline_point, point,
6025 &timeline->points, list) {
6026 if (point->value >= p) {
6027 ++point->wait_count;
6028 return point;
6029 }
6030 }
6031 return NULL;
6032 }
6033
6034 static struct radv_timeline_point *
6035 radv_timeline_add_point_locked(struct radv_device *device,
6036 struct radv_timeline *timeline,
6037 uint64_t p)
6038 {
6039 radv_timeline_gc_locked(device, timeline);
6040
6041 struct radv_timeline_point *ret = NULL;
6042 struct radv_timeline_point *prev = NULL;
6043 int r;
6044
6045 if (p <= timeline->highest_signaled)
6046 return NULL;
6047
6048 list_for_each_entry(struct radv_timeline_point, point,
6049 &timeline->points, list) {
6050 if (point->value == p) {
6051 return NULL;
6052 }
6053
6054 if (point->value < p)
6055 prev = point;
6056 }
6057
6058 if (list_is_empty(&timeline->free_points)) {
6059 ret = malloc(sizeof(struct radv_timeline_point));
6060 r = device->ws->create_syncobj(device->ws, false, &ret->syncobj);
6061 if (r) {
6062 free(ret);
6063 return NULL;
6064 }
6065 } else {
6066 ret = list_first_entry(&timeline->free_points, struct radv_timeline_point, list);
6067 list_del(&ret->list);
6068
6069 device->ws->reset_syncobj(device->ws, ret->syncobj);
6070 }
6071
6072 ret->value = p;
6073 ret->wait_count = 1;
6074
6075 if (prev) {
6076 list_add(&ret->list, &prev->list);
6077 } else {
6078 list_addtail(&ret->list, &timeline->points);
6079 }
6080 return ret;
6081 }
6082
6083
6084 static VkResult
6085 radv_timeline_wait(struct radv_device *device,
6086 struct radv_timeline *timeline,
6087 uint64_t value,
6088 uint64_t abs_timeout)
6089 {
6090 pthread_mutex_lock(&timeline->mutex);
6091
6092 while(timeline->highest_submitted < value) {
6093 struct timespec abstime;
6094 timespec_from_nsec(&abstime, abs_timeout);
6095
6096 pthread_cond_timedwait(&device->timeline_cond, &timeline->mutex, &abstime);
6097
6098 if (radv_get_current_time() >= abs_timeout && timeline->highest_submitted < value) {
6099 pthread_mutex_unlock(&timeline->mutex);
6100 return VK_TIMEOUT;
6101 }
6102 }
6103
6104 struct radv_timeline_point *point = radv_timeline_find_point_at_least_locked(device, timeline, value);
6105 pthread_mutex_unlock(&timeline->mutex);
6106 if (!point)
6107 return VK_SUCCESS;
6108
6109 bool success = device->ws->wait_syncobj(device->ws, &point->syncobj, 1, true, abs_timeout);
6110
6111 pthread_mutex_lock(&timeline->mutex);
6112 point->wait_count--;
6113 pthread_mutex_unlock(&timeline->mutex);
6114 return success ? VK_SUCCESS : VK_TIMEOUT;
6115 }
6116
6117 static void
6118 radv_timeline_trigger_waiters_locked(struct radv_timeline *timeline,
6119 struct list_head *processing_list)
6120 {
6121 list_for_each_entry_safe(struct radv_timeline_waiter, waiter,
6122 &timeline->waiters, list) {
6123 if (waiter->value > timeline->highest_submitted)
6124 continue;
6125
6126 radv_queue_trigger_submission(waiter->submission, 1, processing_list);
6127 list_del(&waiter->list);
6128 }
6129 }
6130
6131 static
6132 void radv_destroy_semaphore_part(struct radv_device *device,
6133 struct radv_semaphore_part *part)
6134 {
6135 switch(part->kind) {
6136 case RADV_SEMAPHORE_NONE:
6137 break;
6138 case RADV_SEMAPHORE_WINSYS:
6139 device->ws->destroy_sem(part->ws_sem);
6140 break;
6141 case RADV_SEMAPHORE_TIMELINE:
6142 radv_destroy_timeline(device, &part->timeline);
6143 break;
6144 case RADV_SEMAPHORE_SYNCOBJ:
6145 case RADV_SEMAPHORE_TIMELINE_SYNCOBJ:
6146 device->ws->destroy_syncobj(device->ws, part->syncobj);
6147 break;
6148 }
6149 part->kind = RADV_SEMAPHORE_NONE;
6150 }
6151
6152 static VkSemaphoreTypeKHR
6153 radv_get_semaphore_type(const void *pNext, uint64_t *initial_value)
6154 {
6155 const VkSemaphoreTypeCreateInfo *type_info =
6156 vk_find_struct_const(pNext, SEMAPHORE_TYPE_CREATE_INFO);
6157
6158 if (!type_info)
6159 return VK_SEMAPHORE_TYPE_BINARY;
6160
6161 if (initial_value)
6162 *initial_value = type_info->initialValue;
6163 return type_info->semaphoreType;
6164 }
6165
6166 static void
6167 radv_destroy_semaphore(struct radv_device *device,
6168 const VkAllocationCallbacks *pAllocator,
6169 struct radv_semaphore *sem)
6170 {
6171 radv_destroy_semaphore_part(device, &sem->temporary);
6172 radv_destroy_semaphore_part(device, &sem->permanent);
6173 vk_object_base_finish(&sem->base);
6174 vk_free2(&device->vk.alloc, pAllocator, sem);
6175 }
6176
6177 VkResult radv_CreateSemaphore(
6178 VkDevice _device,
6179 const VkSemaphoreCreateInfo* pCreateInfo,
6180 const VkAllocationCallbacks* pAllocator,
6181 VkSemaphore* pSemaphore)
6182 {
6183 RADV_FROM_HANDLE(radv_device, device, _device);
6184 const VkExportSemaphoreCreateInfo *export =
6185 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
6186 VkExternalSemaphoreHandleTypeFlags handleTypes =
6187 export ? export->handleTypes : 0;
6188 uint64_t initial_value = 0;
6189 VkSemaphoreTypeKHR type = radv_get_semaphore_type(pCreateInfo->pNext, &initial_value);
6190
6191 struct radv_semaphore *sem = vk_alloc2(&device->vk.alloc, pAllocator,
6192 sizeof(*sem), 8,
6193 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
6194 if (!sem)
6195 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6196
6197 vk_object_base_init(&device->vk, &sem->base,
6198 VK_OBJECT_TYPE_SEMAPHORE);
6199
6200 sem->temporary.kind = RADV_SEMAPHORE_NONE;
6201 sem->permanent.kind = RADV_SEMAPHORE_NONE;
6202
6203 if (type == VK_SEMAPHORE_TYPE_TIMELINE &&
6204 device->physical_device->rad_info.has_timeline_syncobj) {
6205 int ret = device->ws->create_syncobj(device->ws, false, &sem->permanent.syncobj);
6206 if (ret) {
6207 radv_destroy_semaphore(device, pAllocator, sem);
6208 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6209 }
6210 device->ws->signal_syncobj(device->ws, sem->permanent.syncobj, initial_value);
6211 sem->permanent.timeline_syncobj.max_point = initial_value;
6212 sem->permanent.kind = RADV_SEMAPHORE_TIMELINE_SYNCOBJ;
6213 } else if (type == VK_SEMAPHORE_TYPE_TIMELINE) {
6214 radv_create_timeline(&sem->permanent.timeline, initial_value);
6215 sem->permanent.kind = RADV_SEMAPHORE_TIMELINE;
6216 } else if (device->always_use_syncobj || handleTypes) {
6217 assert (device->physical_device->rad_info.has_syncobj);
6218 int ret = device->ws->create_syncobj(device->ws, false,
6219 &sem->permanent.syncobj);
6220 if (ret) {
6221 radv_destroy_semaphore(device, pAllocator, sem);
6222 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6223 }
6224 sem->permanent.kind = RADV_SEMAPHORE_SYNCOBJ;
6225 } else {
6226 sem->permanent.ws_sem = device->ws->create_sem(device->ws);
6227 if (!sem->permanent.ws_sem) {
6228 radv_destroy_semaphore(device, pAllocator, sem);
6229 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6230 }
6231 sem->permanent.kind = RADV_SEMAPHORE_WINSYS;
6232 }
6233
6234 *pSemaphore = radv_semaphore_to_handle(sem);
6235 return VK_SUCCESS;
6236 }
6237
6238 void radv_DestroySemaphore(
6239 VkDevice _device,
6240 VkSemaphore _semaphore,
6241 const VkAllocationCallbacks* pAllocator)
6242 {
6243 RADV_FROM_HANDLE(radv_device, device, _device);
6244 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
6245 if (!_semaphore)
6246 return;
6247
6248 radv_destroy_semaphore(device, pAllocator, sem);
6249 }
6250
6251 VkResult
6252 radv_GetSemaphoreCounterValue(VkDevice _device,
6253 VkSemaphore _semaphore,
6254 uint64_t* pValue)
6255 {
6256 RADV_FROM_HANDLE(radv_device, device, _device);
6257 RADV_FROM_HANDLE(radv_semaphore, semaphore, _semaphore);
6258
6259 if (radv_device_is_lost(device))
6260 return VK_ERROR_DEVICE_LOST;
6261
6262 struct radv_semaphore_part *part =
6263 semaphore->temporary.kind != RADV_SEMAPHORE_NONE ? &semaphore->temporary : &semaphore->permanent;
6264
6265 switch (part->kind) {
6266 case RADV_SEMAPHORE_TIMELINE: {
6267 pthread_mutex_lock(&part->timeline.mutex);
6268 radv_timeline_gc_locked(device, &part->timeline);
6269 *pValue = part->timeline.highest_signaled;
6270 pthread_mutex_unlock(&part->timeline.mutex);
6271 return VK_SUCCESS;
6272 }
6273 case RADV_SEMAPHORE_TIMELINE_SYNCOBJ: {
6274 return device->ws->query_syncobj(device->ws, part->syncobj, pValue);
6275 }
6276 case RADV_SEMAPHORE_NONE:
6277 case RADV_SEMAPHORE_SYNCOBJ:
6278 case RADV_SEMAPHORE_WINSYS:
6279 unreachable("Invalid semaphore type");
6280 }
6281 unreachable("Unhandled semaphore type");
6282 }
6283
6284
6285 static VkResult
6286 radv_wait_timelines(struct radv_device *device,
6287 const VkSemaphoreWaitInfo* pWaitInfo,
6288 uint64_t abs_timeout)
6289 {
6290 if ((pWaitInfo->flags & VK_SEMAPHORE_WAIT_ANY_BIT_KHR) && pWaitInfo->semaphoreCount > 1) {
6291 for (;;) {
6292 for(uint32_t i = 0; i < pWaitInfo->semaphoreCount; ++i) {
6293 RADV_FROM_HANDLE(radv_semaphore, semaphore, pWaitInfo->pSemaphores[i]);
6294 VkResult result = radv_timeline_wait(device, &semaphore->permanent.timeline, pWaitInfo->pValues[i], 0);
6295
6296 if (result == VK_SUCCESS)
6297 return VK_SUCCESS;
6298 }
6299 if (radv_get_current_time() > abs_timeout)
6300 return VK_TIMEOUT;
6301 }
6302 }
6303
6304 for(uint32_t i = 0; i < pWaitInfo->semaphoreCount; ++i) {
6305 RADV_FROM_HANDLE(radv_semaphore, semaphore, pWaitInfo->pSemaphores[i]);
6306 VkResult result = radv_timeline_wait(device, &semaphore->permanent.timeline, pWaitInfo->pValues[i], abs_timeout);
6307
6308 if (result != VK_SUCCESS)
6309 return result;
6310 }
6311 return VK_SUCCESS;
6312 }
6313 VkResult
6314 radv_WaitSemaphores(VkDevice _device,
6315 const VkSemaphoreWaitInfo* pWaitInfo,
6316 uint64_t timeout)
6317 {
6318 RADV_FROM_HANDLE(radv_device, device, _device);
6319
6320 if (radv_device_is_lost(device))
6321 return VK_ERROR_DEVICE_LOST;
6322
6323 uint64_t abs_timeout = radv_get_absolute_timeout(timeout);
6324
6325 if (radv_semaphore_from_handle(pWaitInfo->pSemaphores[0])->permanent.kind == RADV_SEMAPHORE_TIMELINE)
6326 return radv_wait_timelines(device, pWaitInfo, abs_timeout);
6327
6328 if (pWaitInfo->semaphoreCount > UINT32_MAX / sizeof(uint32_t))
6329 return vk_errorf(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY, "semaphoreCount integer overflow");
6330
6331 bool wait_all = !(pWaitInfo->flags & VK_SEMAPHORE_WAIT_ANY_BIT_KHR);
6332 uint32_t *handles = malloc(sizeof(*handles) * pWaitInfo->semaphoreCount);
6333 if (!handles)
6334 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6335
6336 for (uint32_t i = 0; i < pWaitInfo->semaphoreCount; ++i) {
6337 RADV_FROM_HANDLE(radv_semaphore, semaphore, pWaitInfo->pSemaphores[i]);
6338 handles[i] = semaphore->permanent.syncobj;
6339 }
6340
6341 bool success = device->ws->wait_timeline_syncobj(device->ws, handles, pWaitInfo->pValues,
6342 pWaitInfo->semaphoreCount, wait_all, false,
6343 abs_timeout);
6344 free(handles);
6345 return success ? VK_SUCCESS : VK_TIMEOUT;
6346 }
6347
6348 VkResult
6349 radv_SignalSemaphore(VkDevice _device,
6350 const VkSemaphoreSignalInfo* pSignalInfo)
6351 {
6352 RADV_FROM_HANDLE(radv_device, device, _device);
6353 RADV_FROM_HANDLE(radv_semaphore, semaphore, pSignalInfo->semaphore);
6354
6355 struct radv_semaphore_part *part =
6356 semaphore->temporary.kind != RADV_SEMAPHORE_NONE ? &semaphore->temporary : &semaphore->permanent;
6357
6358 switch(part->kind) {
6359 case RADV_SEMAPHORE_TIMELINE: {
6360 pthread_mutex_lock(&part->timeline.mutex);
6361 radv_timeline_gc_locked(device, &part->timeline);
6362 part->timeline.highest_submitted = MAX2(part->timeline.highest_submitted, pSignalInfo->value);
6363 part->timeline.highest_signaled = MAX2(part->timeline.highest_signaled, pSignalInfo->value);
6364
6365 struct list_head processing_list;
6366 list_inithead(&processing_list);
6367 radv_timeline_trigger_waiters_locked(&part->timeline, &processing_list);
6368 pthread_mutex_unlock(&part->timeline.mutex);
6369
6370 VkResult result = radv_process_submissions(&processing_list);
6371
6372 /* This needs to happen after radv_process_submissions, so
6373 * that any submitted submissions that are now unblocked get
6374 * processed before we wake the application. This way we
6375 * ensure that any binary semaphores that are now unblocked
6376 * are usable by the application. */
6377 pthread_cond_broadcast(&device->timeline_cond);
6378
6379 return result;
6380 }
6381 case RADV_SEMAPHORE_TIMELINE_SYNCOBJ: {
6382 part->timeline_syncobj.max_point = MAX2(part->timeline_syncobj.max_point, pSignalInfo->value);
6383 device->ws->signal_syncobj(device->ws, part->syncobj, pSignalInfo->value);
6384 break;
6385 }
6386 case RADV_SEMAPHORE_NONE:
6387 case RADV_SEMAPHORE_SYNCOBJ:
6388 case RADV_SEMAPHORE_WINSYS:
6389 unreachable("Invalid semaphore type");
6390 }
6391 return VK_SUCCESS;
6392 }
6393
6394 static void radv_destroy_event(struct radv_device *device,
6395 const VkAllocationCallbacks* pAllocator,
6396 struct radv_event *event)
6397 {
6398 if (event->bo)
6399 device->ws->buffer_destroy(event->bo);
6400
6401 vk_object_base_finish(&event->base);
6402 vk_free2(&device->vk.alloc, pAllocator, event);
6403 }
6404
6405 VkResult radv_CreateEvent(
6406 VkDevice _device,
6407 const VkEventCreateInfo* pCreateInfo,
6408 const VkAllocationCallbacks* pAllocator,
6409 VkEvent* pEvent)
6410 {
6411 RADV_FROM_HANDLE(radv_device, device, _device);
6412 struct radv_event *event = vk_alloc2(&device->vk.alloc, pAllocator,
6413 sizeof(*event), 8,
6414 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
6415
6416 if (!event)
6417 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6418
6419 vk_object_base_init(&device->vk, &event->base, VK_OBJECT_TYPE_EVENT);
6420
6421 event->bo = device->ws->buffer_create(device->ws, 8, 8,
6422 RADEON_DOMAIN_GTT,
6423 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
6424 RADV_BO_PRIORITY_FENCE);
6425 if (!event->bo) {
6426 radv_destroy_event(device, pAllocator, event);
6427 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
6428 }
6429
6430 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
6431 if (!event->map) {
6432 radv_destroy_event(device, pAllocator, event);
6433 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
6434 }
6435
6436 *pEvent = radv_event_to_handle(event);
6437
6438 return VK_SUCCESS;
6439 }
6440
6441 void radv_DestroyEvent(
6442 VkDevice _device,
6443 VkEvent _event,
6444 const VkAllocationCallbacks* pAllocator)
6445 {
6446 RADV_FROM_HANDLE(radv_device, device, _device);
6447 RADV_FROM_HANDLE(radv_event, event, _event);
6448
6449 if (!event)
6450 return;
6451
6452 radv_destroy_event(device, pAllocator, event);
6453 }
6454
6455 VkResult radv_GetEventStatus(
6456 VkDevice _device,
6457 VkEvent _event)
6458 {
6459 RADV_FROM_HANDLE(radv_device, device, _device);
6460 RADV_FROM_HANDLE(radv_event, event, _event);
6461
6462 if (radv_device_is_lost(device))
6463 return VK_ERROR_DEVICE_LOST;
6464
6465 if (*event->map == 1)
6466 return VK_EVENT_SET;
6467 return VK_EVENT_RESET;
6468 }
6469
6470 VkResult radv_SetEvent(
6471 VkDevice _device,
6472 VkEvent _event)
6473 {
6474 RADV_FROM_HANDLE(radv_event, event, _event);
6475 *event->map = 1;
6476
6477 return VK_SUCCESS;
6478 }
6479
6480 VkResult radv_ResetEvent(
6481 VkDevice _device,
6482 VkEvent _event)
6483 {
6484 RADV_FROM_HANDLE(radv_event, event, _event);
6485 *event->map = 0;
6486
6487 return VK_SUCCESS;
6488 }
6489
6490 static void
6491 radv_destroy_buffer(struct radv_device *device,
6492 const VkAllocationCallbacks *pAllocator,
6493 struct radv_buffer *buffer)
6494 {
6495 if ((buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) && buffer->bo)
6496 device->ws->buffer_destroy(buffer->bo);
6497
6498 vk_object_base_finish(&buffer->base);
6499 vk_free2(&device->vk.alloc, pAllocator, buffer);
6500 }
6501
6502 VkResult radv_CreateBuffer(
6503 VkDevice _device,
6504 const VkBufferCreateInfo* pCreateInfo,
6505 const VkAllocationCallbacks* pAllocator,
6506 VkBuffer* pBuffer)
6507 {
6508 RADV_FROM_HANDLE(radv_device, device, _device);
6509 struct radv_buffer *buffer;
6510
6511 if (pCreateInfo->size > RADV_MAX_MEMORY_ALLOCATION_SIZE)
6512 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
6513
6514 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
6515
6516 buffer = vk_alloc2(&device->vk.alloc, pAllocator, sizeof(*buffer), 8,
6517 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
6518 if (buffer == NULL)
6519 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6520
6521 vk_object_base_init(&device->vk, &buffer->base, VK_OBJECT_TYPE_BUFFER);
6522
6523 buffer->size = pCreateInfo->size;
6524 buffer->usage = pCreateInfo->usage;
6525 buffer->bo = NULL;
6526 buffer->offset = 0;
6527 buffer->flags = pCreateInfo->flags;
6528
6529 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
6530 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
6531
6532 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
6533 buffer->bo = device->ws->buffer_create(device->ws,
6534 align64(buffer->size, 4096),
6535 4096, 0, RADEON_FLAG_VIRTUAL,
6536 RADV_BO_PRIORITY_VIRTUAL);
6537 if (!buffer->bo) {
6538 radv_destroy_buffer(device, pAllocator, buffer);
6539 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
6540 }
6541 }
6542
6543 *pBuffer = radv_buffer_to_handle(buffer);
6544
6545 return VK_SUCCESS;
6546 }
6547
6548 void radv_DestroyBuffer(
6549 VkDevice _device,
6550 VkBuffer _buffer,
6551 const VkAllocationCallbacks* pAllocator)
6552 {
6553 RADV_FROM_HANDLE(radv_device, device, _device);
6554 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
6555
6556 if (!buffer)
6557 return;
6558
6559 radv_destroy_buffer(device, pAllocator, buffer);
6560 }
6561
6562 VkDeviceAddress radv_GetBufferDeviceAddress(
6563 VkDevice device,
6564 const VkBufferDeviceAddressInfo* pInfo)
6565 {
6566 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
6567 return radv_buffer_get_va(buffer->bo) + buffer->offset;
6568 }
6569
6570
6571 uint64_t radv_GetBufferOpaqueCaptureAddress(VkDevice device,
6572 const VkBufferDeviceAddressInfo* pInfo)
6573 {
6574 return 0;
6575 }
6576
6577 uint64_t radv_GetDeviceMemoryOpaqueCaptureAddress(VkDevice device,
6578 const VkDeviceMemoryOpaqueCaptureAddressInfo* pInfo)
6579 {
6580 return 0;
6581 }
6582
6583 static inline unsigned
6584 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
6585 {
6586 if (stencil)
6587 return plane->surface.u.legacy.stencil_tiling_index[level];
6588 else
6589 return plane->surface.u.legacy.tiling_index[level];
6590 }
6591
6592 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
6593 {
6594 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
6595 }
6596
6597 static uint32_t
6598 radv_init_dcc_control_reg(struct radv_device *device,
6599 struct radv_image_view *iview)
6600 {
6601 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
6602 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
6603 unsigned max_compressed_block_size;
6604 unsigned independent_128b_blocks;
6605 unsigned independent_64b_blocks;
6606
6607 if (!radv_dcc_enabled(iview->image, iview->base_mip))
6608 return 0;
6609
6610 if (!device->physical_device->rad_info.has_dedicated_vram) {
6611 /* amdvlk: [min-compressed-block-size] should be set to 32 for
6612 * dGPU and 64 for APU because all of our APUs to date use
6613 * DIMMs which have a request granularity size of 64B while all
6614 * other chips have a 32B request size.
6615 */
6616 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
6617 }
6618
6619 if (device->physical_device->rad_info.chip_class >= GFX10) {
6620 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
6621 independent_64b_blocks = 0;
6622 independent_128b_blocks = 1;
6623 } else {
6624 independent_128b_blocks = 0;
6625
6626 if (iview->image->info.samples > 1) {
6627 if (iview->image->planes[0].surface.bpe == 1)
6628 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
6629 else if (iview->image->planes[0].surface.bpe == 2)
6630 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
6631 }
6632
6633 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
6634 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
6635 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
6636 /* If this DCC image is potentially going to be used in texture
6637 * fetches, we need some special settings.
6638 */
6639 independent_64b_blocks = 1;
6640 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
6641 } else {
6642 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
6643 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
6644 * big as possible for better compression state.
6645 */
6646 independent_64b_blocks = 0;
6647 max_compressed_block_size = max_uncompressed_block_size;
6648 }
6649 }
6650
6651 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
6652 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
6653 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
6654 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks) |
6655 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks);
6656 }
6657
6658 void
6659 radv_initialise_color_surface(struct radv_device *device,
6660 struct radv_color_buffer_info *cb,
6661 struct radv_image_view *iview)
6662 {
6663 const struct vk_format_description *desc;
6664 unsigned ntype, format, swap, endian;
6665 unsigned blend_clamp = 0, blend_bypass = 0;
6666 uint64_t va;
6667 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
6668 const struct radeon_surf *surf = &plane->surface;
6669
6670 desc = vk_format_description(iview->vk_format);
6671
6672 memset(cb, 0, sizeof(*cb));
6673
6674 /* Intensity is implemented as Red, so treat it that way. */
6675 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
6676
6677 va = radv_buffer_get_va(iview->bo) + iview->image->offset + plane->offset;
6678
6679 cb->cb_color_base = va >> 8;
6680
6681 if (device->physical_device->rad_info.chip_class >= GFX9) {
6682 if (device->physical_device->rad_info.chip_class >= GFX10) {
6683 cb->cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
6684 S_028EE0_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
6685 S_028EE0_CMASK_PIPE_ALIGNED(1) |
6686 S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.dcc.pipe_aligned);
6687 } else {
6688 struct gfx9_surf_meta_flags meta = {
6689 .rb_aligned = 1,
6690 .pipe_aligned = 1,
6691 };
6692
6693 if (surf->dcc_offset)
6694 meta = surf->u.gfx9.dcc;
6695
6696 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
6697 S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
6698 S_028C74_RB_ALIGNED(meta.rb_aligned) |
6699 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
6700 cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch);
6701 }
6702
6703 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
6704 cb->cb_color_base |= surf->tile_swizzle;
6705 } else {
6706 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
6707 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
6708
6709 cb->cb_color_base += level_info->offset >> 8;
6710 if (level_info->mode == RADEON_SURF_MODE_2D)
6711 cb->cb_color_base |= surf->tile_swizzle;
6712
6713 pitch_tile_max = level_info->nblk_x / 8 - 1;
6714 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
6715 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false);
6716
6717 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
6718 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
6719 cb->cb_color_cmask_slice = surf->u.legacy.cmask_slice_tile_max;
6720
6721 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
6722
6723 if (radv_image_has_fmask(iview->image)) {
6724 if (device->physical_device->rad_info.chip_class >= GFX7)
6725 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(surf->u.legacy.fmask.pitch_in_pixels / 8 - 1);
6726 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(surf->u.legacy.fmask.tiling_index);
6727 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(surf->u.legacy.fmask.slice_tile_max);
6728 } else {
6729 /* This must be set for fast clear to work without FMASK. */
6730 if (device->physical_device->rad_info.chip_class >= GFX7)
6731 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
6732 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
6733 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
6734 }
6735 }
6736
6737 /* CMASK variables */
6738 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
6739 va += surf->cmask_offset;
6740 cb->cb_color_cmask = va >> 8;
6741
6742 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
6743 va += surf->dcc_offset;
6744
6745 if (radv_dcc_enabled(iview->image, iview->base_mip) &&
6746 device->physical_device->rad_info.chip_class <= GFX8)
6747 va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
6748
6749 unsigned dcc_tile_swizzle = surf->tile_swizzle;
6750 dcc_tile_swizzle &= (surf->dcc_alignment - 1) >> 8;
6751
6752 cb->cb_dcc_base = va >> 8;
6753 cb->cb_dcc_base |= dcc_tile_swizzle;
6754
6755 /* GFX10 field has the same base shift as the GFX6 field. */
6756 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
6757 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
6758 S_028C6C_SLICE_MAX_GFX10(max_slice);
6759
6760 if (iview->image->info.samples > 1) {
6761 unsigned log_samples = util_logbase2(iview->image->info.samples);
6762
6763 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
6764 S_028C74_NUM_FRAGMENTS(log_samples);
6765 }
6766
6767 if (radv_image_has_fmask(iview->image)) {
6768 va = radv_buffer_get_va(iview->bo) + iview->image->offset + surf->fmask_offset;
6769 cb->cb_color_fmask = va >> 8;
6770 cb->cb_color_fmask |= surf->fmask_tile_swizzle;
6771 } else {
6772 cb->cb_color_fmask = cb->cb_color_base;
6773 }
6774
6775 ntype = radv_translate_color_numformat(iview->vk_format,
6776 desc,
6777 vk_format_get_first_non_void_channel(iview->vk_format));
6778 format = radv_translate_colorformat(iview->vk_format);
6779 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
6780 radv_finishme("Illegal color\n");
6781 swap = radv_translate_colorswap(iview->vk_format, false);
6782 endian = radv_colorformat_endian_swap(format);
6783
6784 /* blend clamp should be set for all NORM/SRGB types */
6785 if (ntype == V_028C70_NUMBER_UNORM ||
6786 ntype == V_028C70_NUMBER_SNORM ||
6787 ntype == V_028C70_NUMBER_SRGB)
6788 blend_clamp = 1;
6789
6790 /* set blend bypass according to docs if SINT/UINT or
6791 8/24 COLOR variants */
6792 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
6793 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
6794 format == V_028C70_COLOR_X24_8_32_FLOAT) {
6795 blend_clamp = 0;
6796 blend_bypass = 1;
6797 }
6798 #if 0
6799 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
6800 (format == V_028C70_COLOR_8 ||
6801 format == V_028C70_COLOR_8_8 ||
6802 format == V_028C70_COLOR_8_8_8_8))
6803 ->color_is_int8 = true;
6804 #endif
6805 cb->cb_color_info = S_028C70_FORMAT(format) |
6806 S_028C70_COMP_SWAP(swap) |
6807 S_028C70_BLEND_CLAMP(blend_clamp) |
6808 S_028C70_BLEND_BYPASS(blend_bypass) |
6809 S_028C70_SIMPLE_FLOAT(1) |
6810 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
6811 ntype != V_028C70_NUMBER_SNORM &&
6812 ntype != V_028C70_NUMBER_SRGB &&
6813 format != V_028C70_COLOR_8_24 &&
6814 format != V_028C70_COLOR_24_8) |
6815 S_028C70_NUMBER_TYPE(ntype) |
6816 S_028C70_ENDIAN(endian);
6817 if (radv_image_has_fmask(iview->image)) {
6818 cb->cb_color_info |= S_028C70_COMPRESSION(1);
6819 if (device->physical_device->rad_info.chip_class == GFX6) {
6820 unsigned fmask_bankh = util_logbase2(surf->u.legacy.fmask.bankh);
6821 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
6822 }
6823
6824 if (radv_image_is_tc_compat_cmask(iview->image)) {
6825 /* Allow the texture block to read FMASK directly
6826 * without decompressing it. This bit must be cleared
6827 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
6828 * otherwise the operation doesn't happen.
6829 */
6830 cb->cb_color_info |= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
6831
6832 /* Set CMASK into a tiling format that allows the
6833 * texture block to read it.
6834 */
6835 cb->cb_color_info |= S_028C70_CMASK_ADDR_TYPE(2);
6836 }
6837 }
6838
6839 if (radv_image_has_cmask(iview->image) &&
6840 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
6841 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
6842
6843 if (radv_dcc_enabled(iview->image, iview->base_mip))
6844 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
6845
6846 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
6847
6848 /* This must be set for fast clear to work without FMASK. */
6849 if (!radv_image_has_fmask(iview->image) &&
6850 device->physical_device->rad_info.chip_class == GFX6) {
6851 unsigned bankh = util_logbase2(surf->u.legacy.bankh);
6852 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
6853 }
6854
6855 if (device->physical_device->rad_info.chip_class >= GFX9) {
6856 const struct vk_format_description *format_desc = vk_format_description(iview->image->vk_format);
6857
6858 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
6859 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
6860 unsigned width = iview->extent.width / (iview->plane_id ? format_desc->width_divisor : 1);
6861 unsigned height = iview->extent.height / (iview->plane_id ? format_desc->height_divisor : 1);
6862
6863 if (device->physical_device->rad_info.chip_class >= GFX10) {
6864 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX10(iview->base_mip);
6865
6866 cb->cb_color_attrib3 |= S_028EE0_MIP0_DEPTH(mip0_depth) |
6867 S_028EE0_RESOURCE_TYPE(surf->u.gfx9.resource_type) |
6868 S_028EE0_RESOURCE_LEVEL(1);
6869 } else {
6870 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX9(iview->base_mip);
6871 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
6872 S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
6873 }
6874
6875 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(width - 1) |
6876 S_028C68_MIP0_HEIGHT(height - 1) |
6877 S_028C68_MAX_MIP(iview->image->info.levels - 1);
6878 }
6879 }
6880
6881 static unsigned
6882 radv_calc_decompress_on_z_planes(struct radv_device *device,
6883 struct radv_image_view *iview)
6884 {
6885 unsigned max_zplanes = 0;
6886
6887 assert(radv_image_is_tc_compat_htile(iview->image));
6888
6889 if (device->physical_device->rad_info.chip_class >= GFX9) {
6890 /* Default value for 32-bit depth surfaces. */
6891 max_zplanes = 4;
6892
6893 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
6894 iview->image->info.samples > 1)
6895 max_zplanes = 2;
6896
6897 max_zplanes = max_zplanes + 1;
6898 } else {
6899 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
6900 /* Do not enable Z plane compression for 16-bit depth
6901 * surfaces because isn't supported on GFX8. Only
6902 * 32-bit depth surfaces are supported by the hardware.
6903 * This allows to maintain shader compatibility and to
6904 * reduce the number of depth decompressions.
6905 */
6906 max_zplanes = 1;
6907 } else {
6908 if (iview->image->info.samples <= 1)
6909 max_zplanes = 5;
6910 else if (iview->image->info.samples <= 4)
6911 max_zplanes = 3;
6912 else
6913 max_zplanes = 2;
6914 }
6915 }
6916
6917 return max_zplanes;
6918 }
6919
6920 void
6921 radv_initialise_ds_surface(struct radv_device *device,
6922 struct radv_ds_buffer_info *ds,
6923 struct radv_image_view *iview)
6924 {
6925 unsigned level = iview->base_mip;
6926 unsigned format, stencil_format;
6927 uint64_t va, s_offs, z_offs;
6928 bool stencil_only = false;
6929 const struct radv_image_plane *plane = &iview->image->planes[0];
6930 const struct radeon_surf *surf = &plane->surface;
6931
6932 assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
6933
6934 memset(ds, 0, sizeof(*ds));
6935 switch (iview->image->vk_format) {
6936 case VK_FORMAT_D24_UNORM_S8_UINT:
6937 case VK_FORMAT_X8_D24_UNORM_PACK32:
6938 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
6939 ds->offset_scale = 2.0f;
6940 break;
6941 case VK_FORMAT_D16_UNORM:
6942 case VK_FORMAT_D16_UNORM_S8_UINT:
6943 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
6944 ds->offset_scale = 4.0f;
6945 break;
6946 case VK_FORMAT_D32_SFLOAT:
6947 case VK_FORMAT_D32_SFLOAT_S8_UINT:
6948 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
6949 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
6950 ds->offset_scale = 1.0f;
6951 break;
6952 case VK_FORMAT_S8_UINT:
6953 stencil_only = true;
6954 break;
6955 default:
6956 break;
6957 }
6958
6959 format = radv_translate_dbformat(iview->image->vk_format);
6960 stencil_format = surf->has_stencil ?
6961 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
6962
6963 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
6964 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
6965 S_028008_SLICE_MAX(max_slice);
6966 if (device->physical_device->rad_info.chip_class >= GFX10) {
6967 ds->db_depth_view |= S_028008_SLICE_START_HI(iview->base_layer >> 11) |
6968 S_028008_SLICE_MAX_HI(max_slice >> 11);
6969 }
6970
6971 ds->db_htile_data_base = 0;
6972 ds->db_htile_surface = 0;
6973
6974 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
6975 s_offs = z_offs = va;
6976
6977 if (device->physical_device->rad_info.chip_class >= GFX9) {
6978 assert(surf->u.gfx9.surf_offset == 0);
6979 s_offs += surf->u.gfx9.stencil_offset;
6980
6981 ds->db_z_info = S_028038_FORMAT(format) |
6982 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
6983 S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
6984 S_028038_MAXMIP(iview->image->info.levels - 1) |
6985 S_028038_ZRANGE_PRECISION(1);
6986 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
6987 S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode);
6988
6989 if (device->physical_device->rad_info.chip_class == GFX9) {
6990 ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch);
6991 ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch);
6992 }
6993
6994 ds->db_depth_view |= S_028008_MIPID(level);
6995 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
6996 S_02801C_Y_MAX(iview->image->info.height - 1);
6997
6998 if (radv_htile_enabled(iview->image, level)) {
6999 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
7000
7001 if (radv_image_is_tc_compat_htile(iview->image)) {
7002 unsigned max_zplanes =
7003 radv_calc_decompress_on_z_planes(device, iview);
7004
7005 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
7006
7007 if (device->physical_device->rad_info.chip_class >= GFX10) {
7008 ds->db_z_info |= S_028040_ITERATE_FLUSH(1);
7009 ds->db_stencil_info |= S_028044_ITERATE_FLUSH(1);
7010 } else {
7011 ds->db_z_info |= S_028038_ITERATE_FLUSH(1);
7012 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
7013 }
7014 }
7015
7016 if (!surf->has_stencil)
7017 /* Use all of the htile_buffer for depth if there's no stencil. */
7018 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
7019 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
7020 surf->htile_offset;
7021 ds->db_htile_data_base = va >> 8;
7022 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
7023 S_028ABC_PIPE_ALIGNED(1);
7024
7025 if (device->physical_device->rad_info.chip_class == GFX9) {
7026 ds->db_htile_surface |= S_028ABC_RB_ALIGNED(1);
7027 }
7028 }
7029 } else {
7030 const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];
7031
7032 if (stencil_only)
7033 level_info = &surf->u.legacy.stencil_level[level];
7034
7035 z_offs += surf->u.legacy.level[level].offset;
7036 s_offs += surf->u.legacy.stencil_level[level].offset;
7037
7038 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
7039 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
7040 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
7041
7042 if (iview->image->info.samples > 1)
7043 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
7044
7045 if (device->physical_device->rad_info.chip_class >= GFX7) {
7046 struct radeon_info *info = &device->physical_device->rad_info;
7047 unsigned tiling_index = surf->u.legacy.tiling_index[level];
7048 unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level];
7049 unsigned macro_index = surf->u.legacy.macro_tile_index;
7050 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
7051 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
7052 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
7053
7054 if (stencil_only)
7055 tile_mode = stencil_tile_mode;
7056
7057 ds->db_depth_info |=
7058 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
7059 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
7060 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
7061 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
7062 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
7063 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
7064 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
7065 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
7066 } else {
7067 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false);
7068 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
7069 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true);
7070 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
7071 if (stencil_only)
7072 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
7073 }
7074
7075 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
7076 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
7077 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
7078
7079 if (radv_htile_enabled(iview->image, level)) {
7080 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
7081
7082 if (!surf->has_stencil &&
7083 !radv_image_is_tc_compat_htile(iview->image))
7084 /* Use all of the htile_buffer for depth if there's no stencil. */
7085 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
7086
7087 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
7088 surf->htile_offset;
7089 ds->db_htile_data_base = va >> 8;
7090 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
7091
7092 if (radv_image_is_tc_compat_htile(iview->image)) {
7093 unsigned max_zplanes =
7094 radv_calc_decompress_on_z_planes(device, iview);
7095
7096 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
7097 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
7098 }
7099 }
7100 }
7101
7102 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
7103 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
7104 }
7105
7106 VkResult radv_CreateFramebuffer(
7107 VkDevice _device,
7108 const VkFramebufferCreateInfo* pCreateInfo,
7109 const VkAllocationCallbacks* pAllocator,
7110 VkFramebuffer* pFramebuffer)
7111 {
7112 RADV_FROM_HANDLE(radv_device, device, _device);
7113 struct radv_framebuffer *framebuffer;
7114 const VkFramebufferAttachmentsCreateInfo *imageless_create_info =
7115 vk_find_struct_const(pCreateInfo->pNext,
7116 FRAMEBUFFER_ATTACHMENTS_CREATE_INFO);
7117
7118 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
7119
7120 size_t size = sizeof(*framebuffer);
7121 if (!imageless_create_info)
7122 size += sizeof(struct radv_image_view*) * pCreateInfo->attachmentCount;
7123 framebuffer = vk_alloc2(&device->vk.alloc, pAllocator, size, 8,
7124 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
7125 if (framebuffer == NULL)
7126 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
7127
7128 vk_object_base_init(&device->vk, &framebuffer->base,
7129 VK_OBJECT_TYPE_FRAMEBUFFER);
7130
7131 framebuffer->attachment_count = pCreateInfo->attachmentCount;
7132 framebuffer->width = pCreateInfo->width;
7133 framebuffer->height = pCreateInfo->height;
7134 framebuffer->layers = pCreateInfo->layers;
7135 if (imageless_create_info) {
7136 for (unsigned i = 0; i < imageless_create_info->attachmentImageInfoCount; ++i) {
7137 const VkFramebufferAttachmentImageInfo *attachment =
7138 imageless_create_info->pAttachmentImageInfos + i;
7139 framebuffer->width = MIN2(framebuffer->width, attachment->width);
7140 framebuffer->height = MIN2(framebuffer->height, attachment->height);
7141 framebuffer->layers = MIN2(framebuffer->layers, attachment->layerCount);
7142 }
7143 } else {
7144 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
7145 VkImageView _iview = pCreateInfo->pAttachments[i];
7146 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
7147 framebuffer->attachments[i] = iview;
7148 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
7149 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
7150 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
7151 }
7152 }
7153
7154 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
7155 return VK_SUCCESS;
7156 }
7157
7158 void radv_DestroyFramebuffer(
7159 VkDevice _device,
7160 VkFramebuffer _fb,
7161 const VkAllocationCallbacks* pAllocator)
7162 {
7163 RADV_FROM_HANDLE(radv_device, device, _device);
7164 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
7165
7166 if (!fb)
7167 return;
7168 vk_object_base_finish(&fb->base);
7169 vk_free2(&device->vk.alloc, pAllocator, fb);
7170 }
7171
7172 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
7173 {
7174 switch (address_mode) {
7175 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
7176 return V_008F30_SQ_TEX_WRAP;
7177 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
7178 return V_008F30_SQ_TEX_MIRROR;
7179 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
7180 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
7181 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
7182 return V_008F30_SQ_TEX_CLAMP_BORDER;
7183 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
7184 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
7185 default:
7186 unreachable("illegal tex wrap mode");
7187 break;
7188 }
7189 }
7190
7191 static unsigned
7192 radv_tex_compare(VkCompareOp op)
7193 {
7194 switch (op) {
7195 case VK_COMPARE_OP_NEVER:
7196 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
7197 case VK_COMPARE_OP_LESS:
7198 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
7199 case VK_COMPARE_OP_EQUAL:
7200 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
7201 case VK_COMPARE_OP_LESS_OR_EQUAL:
7202 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
7203 case VK_COMPARE_OP_GREATER:
7204 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
7205 case VK_COMPARE_OP_NOT_EQUAL:
7206 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
7207 case VK_COMPARE_OP_GREATER_OR_EQUAL:
7208 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
7209 case VK_COMPARE_OP_ALWAYS:
7210 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
7211 default:
7212 unreachable("illegal compare mode");
7213 break;
7214 }
7215 }
7216
7217 static unsigned
7218 radv_tex_filter(VkFilter filter, unsigned max_ansio)
7219 {
7220 switch (filter) {
7221 case VK_FILTER_NEAREST:
7222 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
7223 V_008F38_SQ_TEX_XY_FILTER_POINT);
7224 case VK_FILTER_LINEAR:
7225 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
7226 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
7227 case VK_FILTER_CUBIC_IMG:
7228 default:
7229 fprintf(stderr, "illegal texture filter");
7230 return 0;
7231 }
7232 }
7233
7234 static unsigned
7235 radv_tex_mipfilter(VkSamplerMipmapMode mode)
7236 {
7237 switch (mode) {
7238 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
7239 return V_008F38_SQ_TEX_Z_FILTER_POINT;
7240 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
7241 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
7242 default:
7243 return V_008F38_SQ_TEX_Z_FILTER_NONE;
7244 }
7245 }
7246
7247 static unsigned
7248 radv_tex_bordercolor(VkBorderColor bcolor)
7249 {
7250 switch (bcolor) {
7251 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
7252 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
7253 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
7254 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
7255 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
7256 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
7257 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
7258 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
7259 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
7260 case VK_BORDER_COLOR_FLOAT_CUSTOM_EXT:
7261 case VK_BORDER_COLOR_INT_CUSTOM_EXT:
7262 return V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
7263 default:
7264 break;
7265 }
7266 return 0;
7267 }
7268
7269 static unsigned
7270 radv_tex_aniso_filter(unsigned filter)
7271 {
7272 if (filter < 2)
7273 return 0;
7274 if (filter < 4)
7275 return 1;
7276 if (filter < 8)
7277 return 2;
7278 if (filter < 16)
7279 return 3;
7280 return 4;
7281 }
7282
7283 static unsigned
7284 radv_tex_filter_mode(VkSamplerReductionMode mode)
7285 {
7286 switch (mode) {
7287 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
7288 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
7289 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
7290 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
7291 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
7292 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
7293 default:
7294 break;
7295 }
7296 return 0;
7297 }
7298
7299 static uint32_t
7300 radv_get_max_anisotropy(struct radv_device *device,
7301 const VkSamplerCreateInfo *pCreateInfo)
7302 {
7303 if (device->force_aniso >= 0)
7304 return device->force_aniso;
7305
7306 if (pCreateInfo->anisotropyEnable &&
7307 pCreateInfo->maxAnisotropy > 1.0f)
7308 return (uint32_t)pCreateInfo->maxAnisotropy;
7309
7310 return 0;
7311 }
7312
7313 static inline int S_FIXED(float value, unsigned frac_bits)
7314 {
7315 return value * (1 << frac_bits);
7316 }
7317
7318 static uint32_t radv_register_border_color(struct radv_device *device,
7319 VkClearColorValue value)
7320 {
7321 uint32_t slot;
7322
7323 pthread_mutex_lock(&device->border_color_data.mutex);
7324
7325 for (slot = 0; slot < RADV_BORDER_COLOR_COUNT; slot++) {
7326 if (!device->border_color_data.used[slot]) {
7327 /* Copy to the GPU wrt endian-ness. */
7328 util_memcpy_cpu_to_le32(&device->border_color_data.colors_gpu_ptr[slot],
7329 &value,
7330 sizeof(VkClearColorValue));
7331
7332 device->border_color_data.used[slot] = true;
7333 break;
7334 }
7335 }
7336
7337 pthread_mutex_unlock(&device->border_color_data.mutex);
7338
7339 return slot;
7340 }
7341
7342 static void radv_unregister_border_color(struct radv_device *device,
7343 uint32_t slot)
7344 {
7345 pthread_mutex_lock(&device->border_color_data.mutex);
7346
7347 device->border_color_data.used[slot] = false;
7348
7349 pthread_mutex_unlock(&device->border_color_data.mutex);
7350 }
7351
7352 static void
7353 radv_init_sampler(struct radv_device *device,
7354 struct radv_sampler *sampler,
7355 const VkSamplerCreateInfo *pCreateInfo)
7356 {
7357 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
7358 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
7359 bool compat_mode = device->physical_device->rad_info.chip_class == GFX8 ||
7360 device->physical_device->rad_info.chip_class == GFX9;
7361 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
7362 unsigned depth_compare_func = V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
7363 bool trunc_coord = pCreateInfo->minFilter == VK_FILTER_NEAREST && pCreateInfo->magFilter == VK_FILTER_NEAREST;
7364 bool uses_border_color = pCreateInfo->addressModeU == VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER ||
7365 pCreateInfo->addressModeV == VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER ||
7366 pCreateInfo->addressModeW == VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER;
7367 VkBorderColor border_color = uses_border_color ? pCreateInfo->borderColor : VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK;
7368 uint32_t border_color_ptr;
7369
7370 const struct VkSamplerReductionModeCreateInfo *sampler_reduction =
7371 vk_find_struct_const(pCreateInfo->pNext,
7372 SAMPLER_REDUCTION_MODE_CREATE_INFO);
7373 if (sampler_reduction)
7374 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
7375
7376 if (pCreateInfo->compareEnable)
7377 depth_compare_func = radv_tex_compare(pCreateInfo->compareOp);
7378
7379 sampler->border_color_slot = RADV_BORDER_COLOR_COUNT;
7380
7381 if (border_color == VK_BORDER_COLOR_FLOAT_CUSTOM_EXT || border_color == VK_BORDER_COLOR_INT_CUSTOM_EXT) {
7382 const VkSamplerCustomBorderColorCreateInfoEXT *custom_border_color =
7383 vk_find_struct_const(pCreateInfo->pNext,
7384 SAMPLER_CUSTOM_BORDER_COLOR_CREATE_INFO_EXT);
7385
7386 assert(custom_border_color);
7387
7388 sampler->border_color_slot =
7389 radv_register_border_color(device, custom_border_color->customBorderColor);
7390
7391 /* Did we fail to find a slot? */
7392 if (sampler->border_color_slot == RADV_BORDER_COLOR_COUNT) {
7393 fprintf(stderr, "WARNING: no free border color slots, defaulting to TRANS_BLACK.\n");
7394 border_color = VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK;
7395 }
7396 }
7397
7398 /* If we don't have a custom color, set the ptr to 0 */
7399 border_color_ptr = sampler->border_color_slot != RADV_BORDER_COLOR_COUNT
7400 ? sampler->border_color_slot
7401 : 0;
7402
7403 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
7404 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
7405 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
7406 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
7407 S_008F30_DEPTH_COMPARE_FUNC(depth_compare_func) |
7408 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
7409 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
7410 S_008F30_ANISO_BIAS(max_aniso_ratio) |
7411 S_008F30_DISABLE_CUBE_WRAP(0) |
7412 S_008F30_COMPAT_MODE(compat_mode) |
7413 S_008F30_FILTER_MODE(filter_mode) |
7414 S_008F30_TRUNC_COORD(trunc_coord));
7415 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
7416 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
7417 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
7418 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
7419 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
7420 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
7421 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
7422 S_008F38_MIP_POINT_PRECLAMP(0));
7423 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(border_color_ptr) |
7424 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(border_color)));
7425
7426 if (device->physical_device->rad_info.chip_class >= GFX10) {
7427 sampler->state[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
7428 } else {
7429 sampler->state[2] |=
7430 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) |
7431 S_008F38_FILTER_PREC_FIX(1) |
7432 S_008F38_ANISO_OVERRIDE_GFX8(device->physical_device->rad_info.chip_class >= GFX8);
7433 }
7434 }
7435
7436 VkResult radv_CreateSampler(
7437 VkDevice _device,
7438 const VkSamplerCreateInfo* pCreateInfo,
7439 const VkAllocationCallbacks* pAllocator,
7440 VkSampler* pSampler)
7441 {
7442 RADV_FROM_HANDLE(radv_device, device, _device);
7443 struct radv_sampler *sampler;
7444
7445 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
7446 vk_find_struct_const(pCreateInfo->pNext,
7447 SAMPLER_YCBCR_CONVERSION_INFO);
7448
7449 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
7450
7451 sampler = vk_alloc2(&device->vk.alloc, pAllocator, sizeof(*sampler), 8,
7452 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
7453 if (!sampler)
7454 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
7455
7456 vk_object_base_init(&device->vk, &sampler->base,
7457 VK_OBJECT_TYPE_SAMPLER);
7458
7459 radv_init_sampler(device, sampler, pCreateInfo);
7460
7461 sampler->ycbcr_sampler = ycbcr_conversion ? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion): NULL;
7462 *pSampler = radv_sampler_to_handle(sampler);
7463
7464 return VK_SUCCESS;
7465 }
7466
7467 void radv_DestroySampler(
7468 VkDevice _device,
7469 VkSampler _sampler,
7470 const VkAllocationCallbacks* pAllocator)
7471 {
7472 RADV_FROM_HANDLE(radv_device, device, _device);
7473 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
7474
7475 if (!sampler)
7476 return;
7477
7478 if (sampler->border_color_slot != RADV_BORDER_COLOR_COUNT)
7479 radv_unregister_border_color(device, sampler->border_color_slot);
7480
7481 vk_object_base_finish(&sampler->base);
7482 vk_free2(&device->vk.alloc, pAllocator, sampler);
7483 }
7484
7485 /* vk_icd.h does not declare this function, so we declare it here to
7486 * suppress Wmissing-prototypes.
7487 */
7488 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
7489 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
7490
7491 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
7492 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
7493 {
7494 /* For the full details on loader interface versioning, see
7495 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
7496 * What follows is a condensed summary, to help you navigate the large and
7497 * confusing official doc.
7498 *
7499 * - Loader interface v0 is incompatible with later versions. We don't
7500 * support it.
7501 *
7502 * - In loader interface v1:
7503 * - The first ICD entrypoint called by the loader is
7504 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
7505 * entrypoint.
7506 * - The ICD must statically expose no other Vulkan symbol unless it is
7507 * linked with -Bsymbolic.
7508 * - Each dispatchable Vulkan handle created by the ICD must be
7509 * a pointer to a struct whose first member is VK_LOADER_DATA. The
7510 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
7511 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
7512 * vkDestroySurfaceKHR(). The ICD must be capable of working with
7513 * such loader-managed surfaces.
7514 *
7515 * - Loader interface v2 differs from v1 in:
7516 * - The first ICD entrypoint called by the loader is
7517 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
7518 * statically expose this entrypoint.
7519 *
7520 * - Loader interface v3 differs from v2 in:
7521 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
7522 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
7523 * because the loader no longer does so.
7524 */
7525 *pSupportedVersion = MIN2(*pSupportedVersion, 4u);
7526 return VK_SUCCESS;
7527 }
7528
7529 VkResult radv_GetMemoryFdKHR(VkDevice _device,
7530 const VkMemoryGetFdInfoKHR *pGetFdInfo,
7531 int *pFD)
7532 {
7533 RADV_FROM_HANDLE(radv_device, device, _device);
7534 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
7535
7536 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
7537
7538 /* At the moment, we support only the below handle types. */
7539 assert(pGetFdInfo->handleType ==
7540 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
7541 pGetFdInfo->handleType ==
7542 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
7543
7544 bool ret = radv_get_memory_fd(device, memory, pFD);
7545 if (ret == false)
7546 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
7547 return VK_SUCCESS;
7548 }
7549
7550 static uint32_t radv_compute_valid_memory_types_attempt(struct radv_physical_device *dev,
7551 enum radeon_bo_domain domains,
7552 enum radeon_bo_flag flags,
7553 enum radeon_bo_flag ignore_flags)
7554 {
7555 /* Don't count GTT/CPU as relevant:
7556 *
7557 * - We're not fully consistent between the two.
7558 * - Sometimes VRAM gets VRAM|GTT.
7559 */
7560 const enum radeon_bo_domain relevant_domains = RADEON_DOMAIN_VRAM |
7561 RADEON_DOMAIN_GDS |
7562 RADEON_DOMAIN_OA;
7563 uint32_t bits = 0;
7564 for (unsigned i = 0; i < dev->memory_properties.memoryTypeCount; ++i) {
7565 if ((domains & relevant_domains) != (dev->memory_domains[i] & relevant_domains))
7566 continue;
7567
7568 if ((flags & ~ignore_flags) != (dev->memory_flags[i] & ~ignore_flags))
7569 continue;
7570
7571 bits |= 1u << i;
7572 }
7573
7574 return bits;
7575 }
7576
7577 static uint32_t radv_compute_valid_memory_types(struct radv_physical_device *dev,
7578 enum radeon_bo_domain domains,
7579 enum radeon_bo_flag flags)
7580 {
7581 enum radeon_bo_flag ignore_flags = ~(RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_GTT_WC);
7582 uint32_t bits = radv_compute_valid_memory_types_attempt(dev, domains, flags, ignore_flags);
7583
7584 if (!bits) {
7585 ignore_flags |= RADEON_FLAG_NO_CPU_ACCESS;
7586 bits = radv_compute_valid_memory_types_attempt(dev, domains, flags, ignore_flags);
7587 }
7588
7589 return bits;
7590 }
7591 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
7592 VkExternalMemoryHandleTypeFlagBits handleType,
7593 int fd,
7594 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
7595 {
7596 RADV_FROM_HANDLE(radv_device, device, _device);
7597
7598 switch (handleType) {
7599 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT: {
7600 enum radeon_bo_domain domains;
7601 enum radeon_bo_flag flags;
7602 if (!device->ws->buffer_get_flags_from_fd(device->ws, fd, &domains, &flags))
7603 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7604
7605 pMemoryFdProperties->memoryTypeBits = radv_compute_valid_memory_types(device->physical_device, domains, flags);
7606 return VK_SUCCESS;
7607 }
7608 default:
7609 /* The valid usage section for this function says:
7610 *
7611 * "handleType must not be one of the handle types defined as
7612 * opaque."
7613 *
7614 * So opaque handle types fall into the default "unsupported" case.
7615 */
7616 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7617 }
7618 }
7619
7620 static VkResult radv_import_opaque_fd(struct radv_device *device,
7621 int fd,
7622 uint32_t *syncobj)
7623 {
7624 uint32_t syncobj_handle = 0;
7625 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
7626 if (ret != 0)
7627 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7628
7629 if (*syncobj)
7630 device->ws->destroy_syncobj(device->ws, *syncobj);
7631
7632 *syncobj = syncobj_handle;
7633 close(fd);
7634
7635 return VK_SUCCESS;
7636 }
7637
7638 static VkResult radv_import_sync_fd(struct radv_device *device,
7639 int fd,
7640 uint32_t *syncobj)
7641 {
7642 /* If we create a syncobj we do it locally so that if we have an error, we don't
7643 * leave a syncobj in an undetermined state in the fence. */
7644 uint32_t syncobj_handle = *syncobj;
7645 if (!syncobj_handle) {
7646 bool create_signaled = fd == -1 ? true : false;
7647
7648 int ret = device->ws->create_syncobj(device->ws, create_signaled,
7649 &syncobj_handle);
7650 if (ret) {
7651 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
7652 }
7653 } else {
7654 if (fd == -1)
7655 device->ws->signal_syncobj(device->ws, syncobj_handle, 0);
7656 }
7657
7658 if (fd != -1) {
7659 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
7660 if (ret)
7661 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7662 close(fd);
7663 }
7664
7665 *syncobj = syncobj_handle;
7666
7667 return VK_SUCCESS;
7668 }
7669
7670 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
7671 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
7672 {
7673 RADV_FROM_HANDLE(radv_device, device, _device);
7674 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
7675 VkResult result;
7676 struct radv_semaphore_part *dst = NULL;
7677 bool timeline = sem->permanent.kind == RADV_SEMAPHORE_TIMELINE_SYNCOBJ;
7678
7679 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
7680 assert(!timeline);
7681 dst = &sem->temporary;
7682 } else {
7683 dst = &sem->permanent;
7684 }
7685
7686 uint32_t syncobj = (dst->kind == RADV_SEMAPHORE_SYNCOBJ ||
7687 dst->kind == RADV_SEMAPHORE_TIMELINE_SYNCOBJ) ? dst->syncobj : 0;
7688
7689 switch(pImportSemaphoreFdInfo->handleType) {
7690 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
7691 result = radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, &syncobj);
7692 break;
7693 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
7694 assert(!timeline);
7695 result = radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, &syncobj);
7696 break;
7697 default:
7698 unreachable("Unhandled semaphore handle type");
7699 }
7700
7701 if (result == VK_SUCCESS) {
7702 dst->syncobj = syncobj;
7703 dst->kind = RADV_SEMAPHORE_SYNCOBJ;
7704 if (timeline) {
7705 dst->kind = RADV_SEMAPHORE_TIMELINE_SYNCOBJ;
7706 dst->timeline_syncobj.max_point = 0;
7707 }
7708 }
7709
7710 return result;
7711 }
7712
7713 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
7714 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
7715 int *pFd)
7716 {
7717 RADV_FROM_HANDLE(radv_device, device, _device);
7718 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
7719 int ret;
7720 uint32_t syncobj_handle;
7721
7722 if (sem->temporary.kind != RADV_SEMAPHORE_NONE) {
7723 assert(sem->temporary.kind == RADV_SEMAPHORE_SYNCOBJ ||
7724 sem->temporary.kind == RADV_SEMAPHORE_TIMELINE_SYNCOBJ);
7725 syncobj_handle = sem->temporary.syncobj;
7726 } else {
7727 assert(sem->permanent.kind == RADV_SEMAPHORE_SYNCOBJ ||
7728 sem->permanent.kind == RADV_SEMAPHORE_TIMELINE_SYNCOBJ);
7729 syncobj_handle = sem->permanent.syncobj;
7730 }
7731
7732 switch(pGetFdInfo->handleType) {
7733 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
7734 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
7735 if (ret)
7736 return vk_error(device->instance, VK_ERROR_TOO_MANY_OBJECTS);
7737 break;
7738 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
7739 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
7740 if (ret)
7741 return vk_error(device->instance, VK_ERROR_TOO_MANY_OBJECTS);
7742
7743 if (sem->temporary.kind != RADV_SEMAPHORE_NONE) {
7744 radv_destroy_semaphore_part(device, &sem->temporary);
7745 } else {
7746 device->ws->reset_syncobj(device->ws, syncobj_handle);
7747 }
7748 break;
7749 default:
7750 unreachable("Unhandled semaphore handle type");
7751 }
7752
7753 return VK_SUCCESS;
7754 }
7755
7756 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
7757 VkPhysicalDevice physicalDevice,
7758 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
7759 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
7760 {
7761 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
7762 VkSemaphoreTypeKHR type = radv_get_semaphore_type(pExternalSemaphoreInfo->pNext, NULL);
7763
7764 if (type == VK_SEMAPHORE_TYPE_TIMELINE && pdevice->rad_info.has_timeline_syncobj &&
7765 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
7766 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
7767 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
7768 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
7769 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
7770 } else if (type == VK_SEMAPHORE_TYPE_TIMELINE) {
7771 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
7772 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
7773 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
7774
7775 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
7776 } else if (pdevice->rad_info.has_syncobj_wait_for_submit &&
7777 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
7778 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
7779 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
7780 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
7781 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
7782 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
7783 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
7784 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
7785 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
7786 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
7787 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
7788 } else {
7789 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
7790 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
7791 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
7792 }
7793 }
7794
7795 VkResult radv_ImportFenceFdKHR(VkDevice _device,
7796 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
7797 {
7798 RADV_FROM_HANDLE(radv_device, device, _device);
7799 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
7800 struct radv_fence_part *dst = NULL;
7801 VkResult result;
7802
7803 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
7804 dst = &fence->temporary;
7805 } else {
7806 dst = &fence->permanent;
7807 }
7808
7809 uint32_t syncobj = dst->kind == RADV_FENCE_SYNCOBJ ? dst->syncobj : 0;
7810
7811 switch(pImportFenceFdInfo->handleType) {
7812 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
7813 result = radv_import_opaque_fd(device, pImportFenceFdInfo->fd, &syncobj);
7814 break;
7815 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
7816 result = radv_import_sync_fd(device, pImportFenceFdInfo->fd, &syncobj);
7817 break;
7818 default:
7819 unreachable("Unhandled fence handle type");
7820 }
7821
7822 if (result == VK_SUCCESS) {
7823 dst->syncobj = syncobj;
7824 dst->kind = RADV_FENCE_SYNCOBJ;
7825 }
7826
7827 return result;
7828 }
7829
7830 VkResult radv_GetFenceFdKHR(VkDevice _device,
7831 const VkFenceGetFdInfoKHR *pGetFdInfo,
7832 int *pFd)
7833 {
7834 RADV_FROM_HANDLE(radv_device, device, _device);
7835 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
7836 int ret;
7837
7838 struct radv_fence_part *part =
7839 fence->temporary.kind != RADV_FENCE_NONE ?
7840 &fence->temporary : &fence->permanent;
7841
7842 switch(pGetFdInfo->handleType) {
7843 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
7844 ret = device->ws->export_syncobj(device->ws, part->syncobj, pFd);
7845 if (ret)
7846 return vk_error(device->instance, VK_ERROR_TOO_MANY_OBJECTS);
7847 break;
7848 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
7849 ret = device->ws->export_syncobj_to_sync_file(device->ws,
7850 part->syncobj, pFd);
7851 if (ret)
7852 return vk_error(device->instance, VK_ERROR_TOO_MANY_OBJECTS);
7853
7854 if (part == &fence->temporary) {
7855 radv_destroy_fence_part(device, part);
7856 } else {
7857 device->ws->reset_syncobj(device->ws, part->syncobj);
7858 }
7859 break;
7860 default:
7861 unreachable("Unhandled fence handle type");
7862 }
7863
7864 return VK_SUCCESS;
7865 }
7866
7867 void radv_GetPhysicalDeviceExternalFenceProperties(
7868 VkPhysicalDevice physicalDevice,
7869 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
7870 VkExternalFenceProperties *pExternalFenceProperties)
7871 {
7872 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
7873
7874 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
7875 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
7876 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
7877 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
7878 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
7879 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
7880 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
7881 } else {
7882 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
7883 pExternalFenceProperties->compatibleHandleTypes = 0;
7884 pExternalFenceProperties->externalFenceFeatures = 0;
7885 }
7886 }
7887
7888 VkResult
7889 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
7890 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
7891 const VkAllocationCallbacks* pAllocator,
7892 VkDebugReportCallbackEXT* pCallback)
7893 {
7894 RADV_FROM_HANDLE(radv_instance, instance, _instance);
7895 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
7896 pCreateInfo, pAllocator, &instance->alloc,
7897 pCallback);
7898 }
7899
7900 void
7901 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
7902 VkDebugReportCallbackEXT _callback,
7903 const VkAllocationCallbacks* pAllocator)
7904 {
7905 RADV_FROM_HANDLE(radv_instance, instance, _instance);
7906 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
7907 _callback, pAllocator, &instance->alloc);
7908 }
7909
7910 void
7911 radv_DebugReportMessageEXT(VkInstance _instance,
7912 VkDebugReportFlagsEXT flags,
7913 VkDebugReportObjectTypeEXT objectType,
7914 uint64_t object,
7915 size_t location,
7916 int32_t messageCode,
7917 const char* pLayerPrefix,
7918 const char* pMessage)
7919 {
7920 RADV_FROM_HANDLE(radv_instance, instance, _instance);
7921 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
7922 object, location, messageCode, pLayerPrefix, pMessage);
7923 }
7924
7925 void
7926 radv_GetDeviceGroupPeerMemoryFeatures(
7927 VkDevice device,
7928 uint32_t heapIndex,
7929 uint32_t localDeviceIndex,
7930 uint32_t remoteDeviceIndex,
7931 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
7932 {
7933 assert(localDeviceIndex == remoteDeviceIndex);
7934
7935 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
7936 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
7937 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
7938 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
7939 }
7940
7941 static const VkTimeDomainEXT radv_time_domains[] = {
7942 VK_TIME_DOMAIN_DEVICE_EXT,
7943 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
7944 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
7945 };
7946
7947 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
7948 VkPhysicalDevice physicalDevice,
7949 uint32_t *pTimeDomainCount,
7950 VkTimeDomainEXT *pTimeDomains)
7951 {
7952 int d;
7953 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
7954
7955 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
7956 vk_outarray_append(&out, i) {
7957 *i = radv_time_domains[d];
7958 }
7959 }
7960
7961 return vk_outarray_status(&out);
7962 }
7963
7964 static uint64_t
7965 radv_clock_gettime(clockid_t clock_id)
7966 {
7967 struct timespec current;
7968 int ret;
7969
7970 ret = clock_gettime(clock_id, &current);
7971 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
7972 ret = clock_gettime(CLOCK_MONOTONIC, &current);
7973 if (ret < 0)
7974 return 0;
7975
7976 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
7977 }
7978
7979 VkResult radv_GetCalibratedTimestampsEXT(
7980 VkDevice _device,
7981 uint32_t timestampCount,
7982 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
7983 uint64_t *pTimestamps,
7984 uint64_t *pMaxDeviation)
7985 {
7986 RADV_FROM_HANDLE(radv_device, device, _device);
7987 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
7988 int d;
7989 uint64_t begin, end;
7990 uint64_t max_clock_period = 0;
7991
7992 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
7993
7994 for (d = 0; d < timestampCount; d++) {
7995 switch (pTimestampInfos[d].timeDomain) {
7996 case VK_TIME_DOMAIN_DEVICE_EXT:
7997 pTimestamps[d] = device->ws->query_value(device->ws,
7998 RADEON_TIMESTAMP);
7999 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
8000 max_clock_period = MAX2(max_clock_period, device_period);
8001 break;
8002 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
8003 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
8004 max_clock_period = MAX2(max_clock_period, 1);
8005 break;
8006
8007 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
8008 pTimestamps[d] = begin;
8009 break;
8010 default:
8011 pTimestamps[d] = 0;
8012 break;
8013 }
8014 }
8015
8016 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
8017
8018 /*
8019 * The maximum deviation is the sum of the interval over which we
8020 * perform the sampling and the maximum period of any sampled
8021 * clock. That's because the maximum skew between any two sampled
8022 * clock edges is when the sampled clock with the largest period is
8023 * sampled at the end of that period but right at the beginning of the
8024 * sampling interval and some other clock is sampled right at the
8025 * begining of its sampling period and right at the end of the
8026 * sampling interval. Let's assume the GPU has the longest clock
8027 * period and that the application is sampling GPU and monotonic:
8028 *
8029 * s e
8030 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
8031 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
8032 *
8033 * g
8034 * 0 1 2 3
8035 * GPU -----_____-----_____-----_____-----_____
8036 *
8037 * m
8038 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
8039 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
8040 *
8041 * Interval <----------------->
8042 * Deviation <-------------------------->
8043 *
8044 * s = read(raw) 2
8045 * g = read(GPU) 1
8046 * m = read(monotonic) 2
8047 * e = read(raw) b
8048 *
8049 * We round the sample interval up by one tick to cover sampling error
8050 * in the interval clock
8051 */
8052
8053 uint64_t sample_interval = end - begin + 1;
8054
8055 *pMaxDeviation = sample_interval + max_clock_period;
8056
8057 return VK_SUCCESS;
8058 }
8059
8060 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
8061 VkPhysicalDevice physicalDevice,
8062 VkSampleCountFlagBits samples,
8063 VkMultisamplePropertiesEXT* pMultisampleProperties)
8064 {
8065 if (samples & (VK_SAMPLE_COUNT_2_BIT |
8066 VK_SAMPLE_COUNT_4_BIT |
8067 VK_SAMPLE_COUNT_8_BIT)) {
8068 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 2, 2 };
8069 } else {
8070 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 0, 0 };
8071 }
8072 }
8073
8074 VkResult radv_CreatePrivateDataSlotEXT(
8075 VkDevice _device,
8076 const VkPrivateDataSlotCreateInfoEXT* pCreateInfo,
8077 const VkAllocationCallbacks* pAllocator,
8078 VkPrivateDataSlotEXT* pPrivateDataSlot)
8079 {
8080 RADV_FROM_HANDLE(radv_device, device, _device);
8081 return vk_private_data_slot_create(&device->vk, pCreateInfo, pAllocator,
8082 pPrivateDataSlot);
8083 }
8084
8085 void radv_DestroyPrivateDataSlotEXT(
8086 VkDevice _device,
8087 VkPrivateDataSlotEXT privateDataSlot,
8088 const VkAllocationCallbacks* pAllocator)
8089 {
8090 RADV_FROM_HANDLE(radv_device, device, _device);
8091 vk_private_data_slot_destroy(&device->vk, privateDataSlot, pAllocator);
8092 }
8093
8094 VkResult radv_SetPrivateDataEXT(
8095 VkDevice _device,
8096 VkObjectType objectType,
8097 uint64_t objectHandle,
8098 VkPrivateDataSlotEXT privateDataSlot,
8099 uint64_t data)
8100 {
8101 RADV_FROM_HANDLE(radv_device, device, _device);
8102 return vk_object_base_set_private_data(&device->vk, objectType,
8103 objectHandle, privateDataSlot,
8104 data);
8105 }
8106
8107 void radv_GetPrivateDataEXT(
8108 VkDevice _device,
8109 VkObjectType objectType,
8110 uint64_t objectHandle,
8111 VkPrivateDataSlotEXT privateDataSlot,
8112 uint64_t* pData)
8113 {
8114 RADV_FROM_HANDLE(radv_device, device, _device);
8115 vk_object_base_get_private_data(&device->vk, objectType, objectHandle,
8116 privateDataSlot, pData);
8117 }