b0eba6abe8677f9cfcb2afc53c816bf0228f9dcb
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "dirent.h"
29
30 #include <stdatomic.h>
31 #include <stdbool.h>
32 #include <string.h>
33 #include <unistd.h>
34 #include <fcntl.h>
35
36 #include "radv_debug.h"
37 #include "radv_private.h"
38 #include "radv_shader.h"
39 #include "radv_cs.h"
40 #include "util/disk_cache.h"
41 #include "vk_util.h"
42 #include <xf86drm.h>
43 #include <amdgpu.h>
44 #include "drm-uapi/amdgpu_drm.h"
45 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
46 #include "winsys/null/radv_null_winsys_public.h"
47 #include "ac_llvm_util.h"
48 #include "vk_format.h"
49 #include "sid.h"
50 #include "git_sha1.h"
51 #include "util/build_id.h"
52 #include "util/debug.h"
53 #include "util/mesa-sha1.h"
54 #include "util/timespec.h"
55 #include "util/u_atomic.h"
56 #include "compiler/glsl_types.h"
57 #include "util/driconf.h"
58
59 static struct radv_timeline_point *
60 radv_timeline_find_point_at_least_locked(struct radv_device *device,
61 struct radv_timeline *timeline,
62 uint64_t p);
63
64 static struct radv_timeline_point *
65 radv_timeline_add_point_locked(struct radv_device *device,
66 struct radv_timeline *timeline,
67 uint64_t p);
68
69 static void
70 radv_timeline_trigger_waiters_locked(struct radv_timeline *timeline,
71 struct list_head *processing_list);
72
73 static
74 void radv_destroy_semaphore_part(struct radv_device *device,
75 struct radv_semaphore_part *part);
76
77 static VkResult
78 radv_create_pthread_cond(pthread_cond_t *cond);
79
80 uint64_t radv_get_current_time(void)
81 {
82 struct timespec tv;
83 clock_gettime(CLOCK_MONOTONIC, &tv);
84 return tv.tv_nsec + tv.tv_sec*1000000000ull;
85 }
86
87 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
88 {
89 uint64_t current_time = radv_get_current_time();
90
91 timeout = MIN2(UINT64_MAX - current_time, timeout);
92
93 return current_time + timeout;
94 }
95
96 static int
97 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
98 {
99 struct mesa_sha1 ctx;
100 unsigned char sha1[20];
101 unsigned ptr_size = sizeof(void*);
102
103 memset(uuid, 0, VK_UUID_SIZE);
104 _mesa_sha1_init(&ctx);
105
106 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
107 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
108 return -1;
109
110 _mesa_sha1_update(&ctx, &family, sizeof(family));
111 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
112 _mesa_sha1_final(&ctx, sha1);
113
114 memcpy(uuid, sha1, VK_UUID_SIZE);
115 return 0;
116 }
117
118 static void
119 radv_get_driver_uuid(void *uuid)
120 {
121 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
122 }
123
124 static void
125 radv_get_device_uuid(struct radeon_info *info, void *uuid)
126 {
127 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
128 }
129
130 static uint64_t
131 radv_get_visible_vram_size(struct radv_physical_device *device)
132 {
133 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
134 }
135
136 static uint64_t
137 radv_get_vram_size(struct radv_physical_device *device)
138 {
139 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
140 }
141
142 static void
143 radv_physical_device_init_mem_types(struct radv_physical_device *device)
144 {
145 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
146 uint64_t vram_size = radv_get_vram_size(device);
147 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
148 device->memory_properties.memoryHeapCount = 0;
149 if (vram_size > 0) {
150 vram_index = device->memory_properties.memoryHeapCount++;
151 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
152 .size = vram_size,
153 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
154 };
155 }
156
157 if (device->rad_info.gart_size > 0) {
158 gart_index = device->memory_properties.memoryHeapCount++;
159 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
160 .size = device->rad_info.gart_size,
161 .flags = 0,
162 };
163 }
164
165 if (visible_vram_size) {
166 visible_vram_index = device->memory_properties.memoryHeapCount++;
167 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
168 .size = visible_vram_size,
169 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
170 };
171 }
172
173 unsigned type_count = 0;
174
175 if (vram_index >= 0 || visible_vram_index >= 0) {
176 device->memory_domains[type_count] = RADEON_DOMAIN_VRAM;
177 device->memory_flags[type_count] = RADEON_FLAG_NO_CPU_ACCESS;
178 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
179 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
180 .heapIndex = vram_index >= 0 ? vram_index : visible_vram_index,
181 };
182 }
183
184 if (gart_index >= 0) {
185 device->memory_domains[type_count] = RADEON_DOMAIN_GTT;
186 device->memory_flags[type_count] = RADEON_FLAG_GTT_WC | RADEON_FLAG_CPU_ACCESS;
187 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
188 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
189 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
190 .heapIndex = gart_index,
191 };
192 }
193 if (visible_vram_index >= 0) {
194 device->memory_domains[type_count] = RADEON_DOMAIN_VRAM;
195 device->memory_flags[type_count] = RADEON_FLAG_CPU_ACCESS;
196 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
197 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
198 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
199 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
200 .heapIndex = visible_vram_index,
201 };
202 }
203
204 if (gart_index >= 0) {
205 device->memory_domains[type_count] = RADEON_DOMAIN_GTT;
206 device->memory_flags[type_count] = RADEON_FLAG_CPU_ACCESS;
207 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
208 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
209 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
210 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
211 .heapIndex = gart_index,
212 };
213 }
214 device->memory_properties.memoryTypeCount = type_count;
215
216 if (device->rad_info.has_l2_uncached) {
217 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
218 VkMemoryType mem_type = device->memory_properties.memoryTypes[i];
219
220 if ((mem_type.propertyFlags & (VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
221 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT)) ||
222 mem_type.propertyFlags == VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT) {
223
224 VkMemoryPropertyFlags property_flags = mem_type.propertyFlags |
225 VK_MEMORY_PROPERTY_DEVICE_COHERENT_BIT_AMD |
226 VK_MEMORY_PROPERTY_DEVICE_UNCACHED_BIT_AMD;
227
228 device->memory_domains[type_count] = device->memory_domains[i];
229 device->memory_flags[type_count] = device->memory_flags[i] | RADEON_FLAG_VA_UNCACHED;
230 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
231 .propertyFlags = property_flags,
232 .heapIndex = mem_type.heapIndex,
233 };
234 }
235 }
236 device->memory_properties.memoryTypeCount = type_count;
237 }
238 }
239
240 static const char *
241 radv_get_compiler_string(struct radv_physical_device *pdevice)
242 {
243 if (!pdevice->use_llvm) {
244 /* Some games like SotTR apply shader workarounds if the LLVM
245 * version is too old or if the LLVM version string is
246 * missing. This gives 2-5% performance with SotTR and ACO.
247 */
248 if (driQueryOptionb(&pdevice->instance->dri_options,
249 "radv_report_llvm9_version_string")) {
250 return "ACO/LLVM 9.0.1";
251 }
252
253 return "ACO";
254 }
255
256 return "LLVM " MESA_LLVM_VERSION_STRING;
257 }
258
259 static VkResult
260 radv_physical_device_try_create(struct radv_instance *instance,
261 drmDevicePtr drm_device,
262 struct radv_physical_device **device_out)
263 {
264 VkResult result;
265 int fd = -1;
266 int master_fd = -1;
267
268 if (drm_device) {
269 const char *path = drm_device->nodes[DRM_NODE_RENDER];
270 drmVersionPtr version;
271
272 fd = open(path, O_RDWR | O_CLOEXEC);
273 if (fd < 0) {
274 if (instance->debug_flags & RADV_DEBUG_STARTUP)
275 radv_logi("Could not open device '%s'", path);
276
277 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
278 }
279
280 version = drmGetVersion(fd);
281 if (!version) {
282 close(fd);
283
284 if (instance->debug_flags & RADV_DEBUG_STARTUP)
285 radv_logi("Could not get the kernel driver version for device '%s'", path);
286
287 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
288 "failed to get version %s: %m", path);
289 }
290
291 if (strcmp(version->name, "amdgpu")) {
292 drmFreeVersion(version);
293 close(fd);
294
295 if (instance->debug_flags & RADV_DEBUG_STARTUP)
296 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
297
298 return VK_ERROR_INCOMPATIBLE_DRIVER;
299 }
300 drmFreeVersion(version);
301
302 if (instance->debug_flags & RADV_DEBUG_STARTUP)
303 radv_logi("Found compatible device '%s'.", path);
304 }
305
306 struct radv_physical_device *device =
307 vk_zalloc2(&instance->alloc, NULL, sizeof(*device), 8,
308 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
309 if (!device) {
310 result = vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
311 goto fail_fd;
312 }
313
314 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
315 device->instance = instance;
316
317 if (drm_device) {
318 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
319 instance->perftest_flags);
320 } else {
321 device->ws = radv_null_winsys_create();
322 }
323
324 if (!device->ws) {
325 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
326 "failed to initialize winsys");
327 goto fail_alloc;
328 }
329
330 if (drm_device && instance->enabled_extensions.KHR_display) {
331 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
332 if (master_fd >= 0) {
333 uint32_t accel_working = 0;
334 struct drm_amdgpu_info request = {
335 .return_pointer = (uintptr_t)&accel_working,
336 .return_size = sizeof(accel_working),
337 .query = AMDGPU_INFO_ACCEL_WORKING
338 };
339
340 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
341 close(master_fd);
342 master_fd = -1;
343 }
344 }
345 }
346
347 device->master_fd = master_fd;
348 device->local_fd = fd;
349 device->ws->query_info(device->ws, &device->rad_info);
350
351 device->use_llvm = instance->debug_flags & RADV_DEBUG_LLVM;
352
353 snprintf(device->name, sizeof(device->name),
354 "AMD RADV %s (%s)",
355 device->rad_info.name, radv_get_compiler_string(device));
356
357 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
358 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
359 "cannot generate UUID");
360 goto fail_wsi;
361 }
362
363 /* These flags affect shader compilation. */
364 uint64_t shader_env_flags = (device->use_llvm ? 0 : 0x2);
365
366 /* The gpu id is already embedded in the uuid so we just pass "radv"
367 * when creating the cache.
368 */
369 char buf[VK_UUID_SIZE * 2 + 1];
370 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
371 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
372
373 if (device->rad_info.chip_class < GFX8)
374 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
375
376 radv_get_driver_uuid(&device->driver_uuid);
377 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
378
379 device->out_of_order_rast_allowed = device->rad_info.has_out_of_order_rast &&
380 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
381
382 device->dcc_msaa_allowed =
383 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
384
385 device->use_ngg = device->rad_info.chip_class >= GFX10 &&
386 device->rad_info.family != CHIP_NAVI14 &&
387 !(device->instance->debug_flags & RADV_DEBUG_NO_NGG);
388
389 /* TODO: Implement NGG GS with ACO. */
390 device->use_ngg_gs = device->use_ngg && device->use_llvm;
391 device->use_ngg_streamout = false;
392
393 /* Determine the number of threads per wave for all stages. */
394 device->cs_wave_size = 64;
395 device->ps_wave_size = 64;
396 device->ge_wave_size = 64;
397
398 if (device->rad_info.chip_class >= GFX10) {
399 if (device->instance->perftest_flags & RADV_PERFTEST_CS_WAVE_32)
400 device->cs_wave_size = 32;
401
402 /* For pixel shaders, wave64 is recommanded. */
403 if (device->instance->perftest_flags & RADV_PERFTEST_PS_WAVE_32)
404 device->ps_wave_size = 32;
405
406 if (device->instance->perftest_flags & RADV_PERFTEST_GE_WAVE_32)
407 device->ge_wave_size = 32;
408 }
409
410 radv_physical_device_init_mem_types(device);
411
412 radv_physical_device_get_supported_extensions(device,
413 &device->supported_extensions);
414
415 if (drm_device)
416 device->bus_info = *drm_device->businfo.pci;
417
418 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
419 ac_print_gpu_info(&device->rad_info);
420
421 /* The WSI is structured as a layer on top of the driver, so this has
422 * to be the last part of initialization (at least until we get other
423 * semi-layers).
424 */
425 result = radv_init_wsi(device);
426 if (result != VK_SUCCESS) {
427 vk_error(instance, result);
428 goto fail_disk_cache;
429 }
430
431 *device_out = device;
432
433 return VK_SUCCESS;
434
435 fail_disk_cache:
436 disk_cache_destroy(device->disk_cache);
437 fail_wsi:
438 device->ws->destroy(device->ws);
439 fail_alloc:
440 vk_free(&instance->alloc, device);
441 fail_fd:
442 if (fd != -1)
443 close(fd);
444 if (master_fd != -1)
445 close(master_fd);
446 return result;
447 }
448
449 static void
450 radv_physical_device_destroy(struct radv_physical_device *device)
451 {
452 radv_finish_wsi(device);
453 device->ws->destroy(device->ws);
454 disk_cache_destroy(device->disk_cache);
455 close(device->local_fd);
456 if (device->master_fd != -1)
457 close(device->master_fd);
458 vk_free(&device->instance->alloc, device);
459 }
460
461 static void *
462 default_alloc_func(void *pUserData, size_t size, size_t align,
463 VkSystemAllocationScope allocationScope)
464 {
465 return malloc(size);
466 }
467
468 static void *
469 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
470 size_t align, VkSystemAllocationScope allocationScope)
471 {
472 return realloc(pOriginal, size);
473 }
474
475 static void
476 default_free_func(void *pUserData, void *pMemory)
477 {
478 free(pMemory);
479 }
480
481 static const VkAllocationCallbacks default_alloc = {
482 .pUserData = NULL,
483 .pfnAllocation = default_alloc_func,
484 .pfnReallocation = default_realloc_func,
485 .pfnFree = default_free_func,
486 };
487
488 static const struct debug_control radv_debug_options[] = {
489 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
490 {"nodcc", RADV_DEBUG_NO_DCC},
491 {"shaders", RADV_DEBUG_DUMP_SHADERS},
492 {"nocache", RADV_DEBUG_NO_CACHE},
493 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
494 {"nohiz", RADV_DEBUG_NO_HIZ},
495 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
496 {"allbos", RADV_DEBUG_ALL_BOS},
497 {"noibs", RADV_DEBUG_NO_IBS},
498 {"spirv", RADV_DEBUG_DUMP_SPIRV},
499 {"vmfaults", RADV_DEBUG_VM_FAULTS},
500 {"zerovram", RADV_DEBUG_ZERO_VRAM},
501 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
502 {"preoptir", RADV_DEBUG_PREOPTIR},
503 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
504 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
505 {"info", RADV_DEBUG_INFO},
506 {"errors", RADV_DEBUG_ERRORS},
507 {"startup", RADV_DEBUG_STARTUP},
508 {"checkir", RADV_DEBUG_CHECKIR},
509 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
510 {"nobinning", RADV_DEBUG_NOBINNING},
511 {"nongg", RADV_DEBUG_NO_NGG},
512 {"allentrypoints", RADV_DEBUG_ALL_ENTRYPOINTS},
513 {"metashaders", RADV_DEBUG_DUMP_META_SHADERS},
514 {"nomemorycache", RADV_DEBUG_NO_MEMORY_CACHE},
515 {"llvm", RADV_DEBUG_LLVM},
516 {"forcecompress", RADV_DEBUG_FORCE_COMPRESS},
517 {NULL, 0}
518 };
519
520 const char *
521 radv_get_debug_option_name(int id)
522 {
523 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
524 return radv_debug_options[id].string;
525 }
526
527 static const struct debug_control radv_perftest_options[] = {
528 {"localbos", RADV_PERFTEST_LOCAL_BOS},
529 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
530 {"bolist", RADV_PERFTEST_BO_LIST},
531 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
532 {"cswave32", RADV_PERFTEST_CS_WAVE_32},
533 {"pswave32", RADV_PERFTEST_PS_WAVE_32},
534 {"gewave32", RADV_PERFTEST_GE_WAVE_32},
535 {"dfsm", RADV_PERFTEST_DFSM},
536 {NULL, 0}
537 };
538
539 const char *
540 radv_get_perftest_option_name(int id)
541 {
542 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
543 return radv_perftest_options[id].string;
544 }
545
546 static void
547 radv_handle_per_app_options(struct radv_instance *instance,
548 const VkApplicationInfo *info)
549 {
550 const char *name = info ? info->pApplicationName : NULL;
551 const char *engine_name = info ? info->pEngineName : NULL;
552
553 if (name) {
554 if (!strcmp(name, "DOOM_VFR")) {
555 /* Work around a Doom VFR game bug */
556 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
557 } else if (!strcmp(name, "Fledge")) {
558 /*
559 * Zero VRAM for "The Surge 2"
560 *
561 * This avoid a hang when when rendering any level. Likely
562 * uninitialized data in an indirect draw.
563 */
564 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
565 } else if (!strcmp(name, "No Man's Sky")) {
566 /* Work around a NMS game bug */
567 instance->debug_flags |= RADV_DEBUG_DISCARD_TO_DEMOTE;
568 } else if (!strcmp(name, "DOOMEternal")) {
569 /* Zero VRAM for Doom Eternal to fix rendering issues. */
570 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
571 } else if (!strcmp(name, "Red Dead Redemption 2")) {
572 /* Work around a RDR2 game bug */
573 instance->debug_flags |= RADV_DEBUG_DISCARD_TO_DEMOTE;
574 }
575 }
576
577 if (engine_name) {
578 if (!strcmp(engine_name, "vkd3d")) {
579 /* Zero VRAM for all VKD3D (DX12->VK) games to fix
580 * rendering issues.
581 */
582 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
583 } else if (!strcmp(engine_name, "Quantic Dream Engine")) {
584 /* Fix various artifacts in Detroit: Become Human */
585 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM |
586 RADV_DEBUG_DISCARD_TO_DEMOTE;
587 }
588 }
589
590 instance->enable_mrt_output_nan_fixup =
591 driQueryOptionb(&instance->dri_options,
592 "radv_enable_mrt_output_nan_fixup");
593
594 if (driQueryOptionb(&instance->dri_options, "radv_no_dynamic_bounds"))
595 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
596 }
597
598 static const char radv_dri_options_xml[] =
599 DRI_CONF_BEGIN
600 DRI_CONF_SECTION_PERFORMANCE
601 DRI_CONF_ADAPTIVE_SYNC("true")
602 DRI_CONF_VK_X11_OVERRIDE_MIN_IMAGE_COUNT(0)
603 DRI_CONF_VK_X11_STRICT_IMAGE_COUNT("false")
604 DRI_CONF_VK_X11_ENSURE_MIN_IMAGE_COUNT("false")
605 DRI_CONF_RADV_REPORT_LLVM9_VERSION_STRING("false")
606 DRI_CONF_RADV_ENABLE_MRT_OUTPUT_NAN_FIXUP("false")
607 DRI_CONF_RADV_NO_DYNAMIC_BOUNDS("false")
608 DRI_CONF_RADV_OVERRIDE_UNIFORM_OFFSET_ALIGNMENT(0)
609 DRI_CONF_SECTION_END
610
611 DRI_CONF_SECTION_DEBUG
612 DRI_CONF_VK_WSI_FORCE_BGRA8_UNORM_FIRST("false")
613 DRI_CONF_SECTION_END
614 DRI_CONF_END;
615
616 static void radv_init_dri_options(struct radv_instance *instance)
617 {
618 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
619 driParseConfigFiles(&instance->dri_options,
620 &instance->available_dri_options,
621 0, "radv", NULL,
622 instance->applicationName,
623 instance->applicationVersion,
624 instance->engineName,
625 instance->engineVersion);
626 }
627
628 VkResult radv_CreateInstance(
629 const VkInstanceCreateInfo* pCreateInfo,
630 const VkAllocationCallbacks* pAllocator,
631 VkInstance* pInstance)
632 {
633 struct radv_instance *instance;
634 VkResult result;
635
636 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
637 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
638 if (!instance)
639 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
640
641 vk_object_base_init(NULL, &instance->base, VK_OBJECT_TYPE_INSTANCE);
642
643 if (pAllocator)
644 instance->alloc = *pAllocator;
645 else
646 instance->alloc = default_alloc;
647
648 if (pCreateInfo->pApplicationInfo) {
649 const VkApplicationInfo *app = pCreateInfo->pApplicationInfo;
650
651 instance->applicationName =
652 vk_strdup(&instance->alloc, app->pApplicationName,
653 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
654 instance->applicationVersion = app->applicationVersion;
655
656 instance->engineName =
657 vk_strdup(&instance->alloc, app->pEngineName,
658 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
659 instance->engineVersion = app->engineVersion;
660 instance->apiVersion = app->apiVersion;
661 }
662
663 if (instance->apiVersion == 0)
664 instance->apiVersion = VK_API_VERSION_1_0;
665
666 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
667 radv_debug_options);
668
669 const char *radv_perftest_str = getenv("RADV_PERFTEST");
670 instance->perftest_flags = parse_debug_string(radv_perftest_str,
671 radv_perftest_options);
672
673 if (radv_perftest_str) {
674 /* Output warnings for famous RADV_PERFTEST options that no
675 * longer exist or are deprecated.
676 */
677 if (strstr(radv_perftest_str, "aco")) {
678 fprintf(stderr, "*******************************************************************************\n");
679 fprintf(stderr, "* WARNING: Unknown option RADV_PERFTEST='aco'. ACO is enabled by default now. *\n");
680 fprintf(stderr, "*******************************************************************************\n");
681 }
682 if (strstr(radv_perftest_str, "llvm")) {
683 fprintf(stderr, "*********************************************************************************\n");
684 fprintf(stderr, "* WARNING: Unknown option 'RADV_PERFTEST=llvm'. Did you mean 'RADV_DEBUG=llvm'? *\n");
685 fprintf(stderr, "*********************************************************************************\n");
686 abort();
687 }
688 }
689
690 if (instance->debug_flags & RADV_DEBUG_STARTUP)
691 radv_logi("Created an instance");
692
693 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
694 int idx;
695 for (idx = 0; idx < RADV_INSTANCE_EXTENSION_COUNT; idx++) {
696 if (!strcmp(pCreateInfo->ppEnabledExtensionNames[i],
697 radv_instance_extensions[idx].extensionName))
698 break;
699 }
700
701 if (idx >= RADV_INSTANCE_EXTENSION_COUNT ||
702 !radv_instance_extensions_supported.extensions[idx]) {
703 vk_object_base_finish(&instance->base);
704 vk_free2(&default_alloc, pAllocator, instance);
705 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
706 }
707
708 instance->enabled_extensions.extensions[idx] = true;
709 }
710
711 bool unchecked = instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS;
712
713 for (unsigned i = 0; i < ARRAY_SIZE(instance->dispatch.entrypoints); i++) {
714 /* Vulkan requires that entrypoints for extensions which have
715 * not been enabled must not be advertised.
716 */
717 if (!unchecked &&
718 !radv_instance_entrypoint_is_enabled(i, instance->apiVersion,
719 &instance->enabled_extensions)) {
720 instance->dispatch.entrypoints[i] = NULL;
721 } else {
722 instance->dispatch.entrypoints[i] =
723 radv_instance_dispatch_table.entrypoints[i];
724 }
725 }
726
727 for (unsigned i = 0; i < ARRAY_SIZE(instance->physical_device_dispatch.entrypoints); i++) {
728 /* Vulkan requires that entrypoints for extensions which have
729 * not been enabled must not be advertised.
730 */
731 if (!unchecked &&
732 !radv_physical_device_entrypoint_is_enabled(i, instance->apiVersion,
733 &instance->enabled_extensions)) {
734 instance->physical_device_dispatch.entrypoints[i] = NULL;
735 } else {
736 instance->physical_device_dispatch.entrypoints[i] =
737 radv_physical_device_dispatch_table.entrypoints[i];
738 }
739 }
740
741 for (unsigned i = 0; i < ARRAY_SIZE(instance->device_dispatch.entrypoints); i++) {
742 /* Vulkan requires that entrypoints for extensions which have
743 * not been enabled must not be advertised.
744 */
745 if (!unchecked &&
746 !radv_device_entrypoint_is_enabled(i, instance->apiVersion,
747 &instance->enabled_extensions, NULL)) {
748 instance->device_dispatch.entrypoints[i] = NULL;
749 } else {
750 instance->device_dispatch.entrypoints[i] =
751 radv_device_dispatch_table.entrypoints[i];
752 }
753 }
754
755 instance->physical_devices_enumerated = false;
756 list_inithead(&instance->physical_devices);
757
758 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
759 if (result != VK_SUCCESS) {
760 vk_object_base_finish(&instance->base);
761 vk_free2(&default_alloc, pAllocator, instance);
762 return vk_error(instance, result);
763 }
764
765 glsl_type_singleton_init_or_ref();
766
767 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
768
769 radv_init_dri_options(instance);
770 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
771
772 *pInstance = radv_instance_to_handle(instance);
773
774 return VK_SUCCESS;
775 }
776
777 void radv_DestroyInstance(
778 VkInstance _instance,
779 const VkAllocationCallbacks* pAllocator)
780 {
781 RADV_FROM_HANDLE(radv_instance, instance, _instance);
782
783 if (!instance)
784 return;
785
786 list_for_each_entry_safe(struct radv_physical_device, pdevice,
787 &instance->physical_devices, link) {
788 radv_physical_device_destroy(pdevice);
789 }
790
791 vk_free(&instance->alloc, instance->engineName);
792 vk_free(&instance->alloc, instance->applicationName);
793
794 VG(VALGRIND_DESTROY_MEMPOOL(instance));
795
796 glsl_type_singleton_decref();
797
798 driDestroyOptionCache(&instance->dri_options);
799 driDestroyOptionInfo(&instance->available_dri_options);
800
801 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
802
803 vk_object_base_finish(&instance->base);
804 vk_free(&instance->alloc, instance);
805 }
806
807 static VkResult
808 radv_enumerate_physical_devices(struct radv_instance *instance)
809 {
810 if (instance->physical_devices_enumerated)
811 return VK_SUCCESS;
812
813 instance->physical_devices_enumerated = true;
814
815 /* TODO: Check for more devices ? */
816 drmDevicePtr devices[8];
817 VkResult result = VK_SUCCESS;
818 int max_devices;
819
820 if (getenv("RADV_FORCE_FAMILY")) {
821 /* When RADV_FORCE_FAMILY is set, the driver creates a nul
822 * device that allows to test the compiler without having an
823 * AMDGPU instance.
824 */
825 struct radv_physical_device *pdevice;
826
827 result = radv_physical_device_try_create(instance, NULL, &pdevice);
828 if (result != VK_SUCCESS)
829 return result;
830
831 list_addtail(&pdevice->link, &instance->physical_devices);
832 return VK_SUCCESS;
833 }
834
835 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
836
837 if (instance->debug_flags & RADV_DEBUG_STARTUP)
838 radv_logi("Found %d drm nodes", max_devices);
839
840 if (max_devices < 1)
841 return vk_error(instance, VK_SUCCESS);
842
843 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
844 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
845 devices[i]->bustype == DRM_BUS_PCI &&
846 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
847
848 struct radv_physical_device *pdevice;
849 result = radv_physical_device_try_create(instance, devices[i],
850 &pdevice);
851 /* Incompatible DRM device, skip. */
852 if (result == VK_ERROR_INCOMPATIBLE_DRIVER) {
853 result = VK_SUCCESS;
854 continue;
855 }
856
857 /* Error creating the physical device, report the error. */
858 if (result != VK_SUCCESS)
859 break;
860
861 list_addtail(&pdevice->link, &instance->physical_devices);
862 }
863 }
864 drmFreeDevices(devices, max_devices);
865
866 /* If we successfully enumerated any devices, call it success */
867 return result;
868 }
869
870 VkResult radv_EnumeratePhysicalDevices(
871 VkInstance _instance,
872 uint32_t* pPhysicalDeviceCount,
873 VkPhysicalDevice* pPhysicalDevices)
874 {
875 RADV_FROM_HANDLE(radv_instance, instance, _instance);
876 VK_OUTARRAY_MAKE(out, pPhysicalDevices, pPhysicalDeviceCount);
877
878 VkResult result = radv_enumerate_physical_devices(instance);
879 if (result != VK_SUCCESS)
880 return result;
881
882 list_for_each_entry(struct radv_physical_device, pdevice,
883 &instance->physical_devices, link) {
884 vk_outarray_append(&out, i) {
885 *i = radv_physical_device_to_handle(pdevice);
886 }
887 }
888
889 return vk_outarray_status(&out);
890 }
891
892 VkResult radv_EnumeratePhysicalDeviceGroups(
893 VkInstance _instance,
894 uint32_t* pPhysicalDeviceGroupCount,
895 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
896 {
897 RADV_FROM_HANDLE(radv_instance, instance, _instance);
898 VK_OUTARRAY_MAKE(out, pPhysicalDeviceGroupProperties,
899 pPhysicalDeviceGroupCount);
900
901 VkResult result = radv_enumerate_physical_devices(instance);
902 if (result != VK_SUCCESS)
903 return result;
904
905 list_for_each_entry(struct radv_physical_device, pdevice,
906 &instance->physical_devices, link) {
907 vk_outarray_append(&out, p) {
908 p->physicalDeviceCount = 1;
909 memset(p->physicalDevices, 0, sizeof(p->physicalDevices));
910 p->physicalDevices[0] = radv_physical_device_to_handle(pdevice);
911 p->subsetAllocation = false;
912 }
913 }
914
915 return vk_outarray_status(&out);
916 }
917
918 void radv_GetPhysicalDeviceFeatures(
919 VkPhysicalDevice physicalDevice,
920 VkPhysicalDeviceFeatures* pFeatures)
921 {
922 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
923 memset(pFeatures, 0, sizeof(*pFeatures));
924
925 *pFeatures = (VkPhysicalDeviceFeatures) {
926 .robustBufferAccess = true,
927 .fullDrawIndexUint32 = true,
928 .imageCubeArray = true,
929 .independentBlend = true,
930 .geometryShader = true,
931 .tessellationShader = true,
932 .sampleRateShading = true,
933 .dualSrcBlend = true,
934 .logicOp = true,
935 .multiDrawIndirect = true,
936 .drawIndirectFirstInstance = true,
937 .depthClamp = true,
938 .depthBiasClamp = true,
939 .fillModeNonSolid = true,
940 .depthBounds = true,
941 .wideLines = true,
942 .largePoints = true,
943 .alphaToOne = true,
944 .multiViewport = true,
945 .samplerAnisotropy = true,
946 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
947 .textureCompressionASTC_LDR = false,
948 .textureCompressionBC = true,
949 .occlusionQueryPrecise = true,
950 .pipelineStatisticsQuery = true,
951 .vertexPipelineStoresAndAtomics = true,
952 .fragmentStoresAndAtomics = true,
953 .shaderTessellationAndGeometryPointSize = true,
954 .shaderImageGatherExtended = true,
955 .shaderStorageImageExtendedFormats = true,
956 .shaderStorageImageMultisample = true,
957 .shaderUniformBufferArrayDynamicIndexing = true,
958 .shaderSampledImageArrayDynamicIndexing = true,
959 .shaderStorageBufferArrayDynamicIndexing = true,
960 .shaderStorageImageArrayDynamicIndexing = true,
961 .shaderStorageImageReadWithoutFormat = true,
962 .shaderStorageImageWriteWithoutFormat = true,
963 .shaderClipDistance = true,
964 .shaderCullDistance = true,
965 .shaderFloat64 = true,
966 .shaderInt64 = true,
967 .shaderInt16 = true,
968 .sparseBinding = true,
969 .variableMultisampleRate = true,
970 .shaderResourceMinLod = true,
971 .inheritedQueries = true,
972 };
973 }
974
975 static void
976 radv_get_physical_device_features_1_1(struct radv_physical_device *pdevice,
977 VkPhysicalDeviceVulkan11Features *f)
978 {
979 assert(f->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES);
980
981 f->storageBuffer16BitAccess = true;
982 f->uniformAndStorageBuffer16BitAccess = true;
983 f->storagePushConstant16 = true;
984 f->storageInputOutput16 = pdevice->rad_info.has_packed_math_16bit && (LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm);
985 f->multiview = true;
986 f->multiviewGeometryShader = true;
987 f->multiviewTessellationShader = true;
988 f->variablePointersStorageBuffer = true;
989 f->variablePointers = true;
990 f->protectedMemory = false;
991 f->samplerYcbcrConversion = true;
992 f->shaderDrawParameters = true;
993 }
994
995 static void
996 radv_get_physical_device_features_1_2(struct radv_physical_device *pdevice,
997 VkPhysicalDeviceVulkan12Features *f)
998 {
999 assert(f->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES);
1000
1001 f->samplerMirrorClampToEdge = true;
1002 f->drawIndirectCount = true;
1003 f->storageBuffer8BitAccess = true;
1004 f->uniformAndStorageBuffer8BitAccess = true;
1005 f->storagePushConstant8 = true;
1006 f->shaderBufferInt64Atomics = LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm;
1007 f->shaderSharedInt64Atomics = LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm;
1008 f->shaderFloat16 = pdevice->rad_info.has_packed_math_16bit;
1009 f->shaderInt8 = true;
1010
1011 f->descriptorIndexing = true;
1012 f->shaderInputAttachmentArrayDynamicIndexing = true;
1013 f->shaderUniformTexelBufferArrayDynamicIndexing = true;
1014 f->shaderStorageTexelBufferArrayDynamicIndexing = true;
1015 f->shaderUniformBufferArrayNonUniformIndexing = true;
1016 f->shaderSampledImageArrayNonUniformIndexing = true;
1017 f->shaderStorageBufferArrayNonUniformIndexing = true;
1018 f->shaderStorageImageArrayNonUniformIndexing = true;
1019 f->shaderInputAttachmentArrayNonUniformIndexing = true;
1020 f->shaderUniformTexelBufferArrayNonUniformIndexing = true;
1021 f->shaderStorageTexelBufferArrayNonUniformIndexing = true;
1022 f->descriptorBindingUniformBufferUpdateAfterBind = true;
1023 f->descriptorBindingSampledImageUpdateAfterBind = true;
1024 f->descriptorBindingStorageImageUpdateAfterBind = true;
1025 f->descriptorBindingStorageBufferUpdateAfterBind = true;
1026 f->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
1027 f->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
1028 f->descriptorBindingUpdateUnusedWhilePending = true;
1029 f->descriptorBindingPartiallyBound = true;
1030 f->descriptorBindingVariableDescriptorCount = true;
1031 f->runtimeDescriptorArray = true;
1032
1033 f->samplerFilterMinmax = true;
1034 f->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
1035 f->imagelessFramebuffer = true;
1036 f->uniformBufferStandardLayout = true;
1037 f->shaderSubgroupExtendedTypes = true;
1038 f->separateDepthStencilLayouts = true;
1039 f->hostQueryReset = true;
1040 f->timelineSemaphore = pdevice->rad_info.has_syncobj_wait_for_submit;
1041 f->bufferDeviceAddress = true;
1042 f->bufferDeviceAddressCaptureReplay = false;
1043 f->bufferDeviceAddressMultiDevice = false;
1044 f->vulkanMemoryModel = true;
1045 f->vulkanMemoryModelDeviceScope = true;
1046 f->vulkanMemoryModelAvailabilityVisibilityChains = false;
1047 f->shaderOutputViewportIndex = true;
1048 f->shaderOutputLayer = true;
1049 f->subgroupBroadcastDynamicId = true;
1050 }
1051
1052 void radv_GetPhysicalDeviceFeatures2(
1053 VkPhysicalDevice physicalDevice,
1054 VkPhysicalDeviceFeatures2 *pFeatures)
1055 {
1056 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1057 radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
1058
1059 VkPhysicalDeviceVulkan11Features core_1_1 = {
1060 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES,
1061 };
1062 radv_get_physical_device_features_1_1(pdevice, &core_1_1);
1063
1064 VkPhysicalDeviceVulkan12Features core_1_2 = {
1065 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES,
1066 };
1067 radv_get_physical_device_features_1_2(pdevice, &core_1_2);
1068
1069 #define CORE_FEATURE(major, minor, feature) \
1070 features->feature = core_##major##_##minor.feature
1071
1072 vk_foreach_struct(ext, pFeatures->pNext) {
1073 switch (ext->sType) {
1074 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
1075 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
1076 CORE_FEATURE(1, 1, variablePointersStorageBuffer);
1077 CORE_FEATURE(1, 1, variablePointers);
1078 break;
1079 }
1080 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
1081 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
1082 CORE_FEATURE(1, 1, multiview);
1083 CORE_FEATURE(1, 1, multiviewGeometryShader);
1084 CORE_FEATURE(1, 1, multiviewTessellationShader);
1085 break;
1086 }
1087 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
1088 VkPhysicalDeviceShaderDrawParametersFeatures *features =
1089 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
1090 CORE_FEATURE(1, 1, shaderDrawParameters);
1091 break;
1092 }
1093 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
1094 VkPhysicalDeviceProtectedMemoryFeatures *features =
1095 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
1096 CORE_FEATURE(1, 1, protectedMemory);
1097 break;
1098 }
1099 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
1100 VkPhysicalDevice16BitStorageFeatures *features =
1101 (VkPhysicalDevice16BitStorageFeatures*)ext;
1102 CORE_FEATURE(1, 1, storageBuffer16BitAccess);
1103 CORE_FEATURE(1, 1, uniformAndStorageBuffer16BitAccess);
1104 CORE_FEATURE(1, 1, storagePushConstant16);
1105 CORE_FEATURE(1, 1, storageInputOutput16);
1106 break;
1107 }
1108 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
1109 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
1110 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
1111 CORE_FEATURE(1, 1, samplerYcbcrConversion);
1112 break;
1113 }
1114 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES: {
1115 VkPhysicalDeviceDescriptorIndexingFeatures *features =
1116 (VkPhysicalDeviceDescriptorIndexingFeatures*)ext;
1117 CORE_FEATURE(1, 2, shaderInputAttachmentArrayDynamicIndexing);
1118 CORE_FEATURE(1, 2, shaderUniformTexelBufferArrayDynamicIndexing);
1119 CORE_FEATURE(1, 2, shaderStorageTexelBufferArrayDynamicIndexing);
1120 CORE_FEATURE(1, 2, shaderUniformBufferArrayNonUniformIndexing);
1121 CORE_FEATURE(1, 2, shaderSampledImageArrayNonUniformIndexing);
1122 CORE_FEATURE(1, 2, shaderStorageBufferArrayNonUniformIndexing);
1123 CORE_FEATURE(1, 2, shaderStorageImageArrayNonUniformIndexing);
1124 CORE_FEATURE(1, 2, shaderInputAttachmentArrayNonUniformIndexing);
1125 CORE_FEATURE(1, 2, shaderUniformTexelBufferArrayNonUniformIndexing);
1126 CORE_FEATURE(1, 2, shaderStorageTexelBufferArrayNonUniformIndexing);
1127 CORE_FEATURE(1, 2, descriptorBindingUniformBufferUpdateAfterBind);
1128 CORE_FEATURE(1, 2, descriptorBindingSampledImageUpdateAfterBind);
1129 CORE_FEATURE(1, 2, descriptorBindingStorageImageUpdateAfterBind);
1130 CORE_FEATURE(1, 2, descriptorBindingStorageBufferUpdateAfterBind);
1131 CORE_FEATURE(1, 2, descriptorBindingUniformTexelBufferUpdateAfterBind);
1132 CORE_FEATURE(1, 2, descriptorBindingStorageTexelBufferUpdateAfterBind);
1133 CORE_FEATURE(1, 2, descriptorBindingUpdateUnusedWhilePending);
1134 CORE_FEATURE(1, 2, descriptorBindingPartiallyBound);
1135 CORE_FEATURE(1, 2, descriptorBindingVariableDescriptorCount);
1136 CORE_FEATURE(1, 2, runtimeDescriptorArray);
1137 break;
1138 }
1139 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
1140 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
1141 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
1142 features->conditionalRendering = true;
1143 features->inheritedConditionalRendering = false;
1144 break;
1145 }
1146 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
1147 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
1148 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
1149 features->vertexAttributeInstanceRateDivisor = true;
1150 features->vertexAttributeInstanceRateZeroDivisor = true;
1151 break;
1152 }
1153 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
1154 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
1155 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
1156 features->transformFeedback = true;
1157 features->geometryStreams = !pdevice->use_ngg_streamout;
1158 break;
1159 }
1160 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES: {
1161 VkPhysicalDeviceScalarBlockLayoutFeatures *features =
1162 (VkPhysicalDeviceScalarBlockLayoutFeatures *)ext;
1163 CORE_FEATURE(1, 2, scalarBlockLayout);
1164 break;
1165 }
1166 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
1167 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
1168 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
1169 features->memoryPriority = true;
1170 break;
1171 }
1172 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
1173 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
1174 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
1175 features->bufferDeviceAddress = true;
1176 features->bufferDeviceAddressCaptureReplay = false;
1177 features->bufferDeviceAddressMultiDevice = false;
1178 break;
1179 }
1180 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES: {
1181 VkPhysicalDeviceBufferDeviceAddressFeatures *features =
1182 (VkPhysicalDeviceBufferDeviceAddressFeatures *)ext;
1183 CORE_FEATURE(1, 2, bufferDeviceAddress);
1184 CORE_FEATURE(1, 2, bufferDeviceAddressCaptureReplay);
1185 CORE_FEATURE(1, 2, bufferDeviceAddressMultiDevice);
1186 break;
1187 }
1188 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
1189 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
1190 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
1191 features->depthClipEnable = true;
1192 break;
1193 }
1194 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES: {
1195 VkPhysicalDeviceHostQueryResetFeatures *features =
1196 (VkPhysicalDeviceHostQueryResetFeatures *)ext;
1197 CORE_FEATURE(1, 2, hostQueryReset);
1198 break;
1199 }
1200 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES: {
1201 VkPhysicalDevice8BitStorageFeatures *features =
1202 (VkPhysicalDevice8BitStorageFeatures *)ext;
1203 CORE_FEATURE(1, 2, storageBuffer8BitAccess);
1204 CORE_FEATURE(1, 2, uniformAndStorageBuffer8BitAccess);
1205 CORE_FEATURE(1, 2, storagePushConstant8);
1206 break;
1207 }
1208 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_FLOAT16_INT8_FEATURES: {
1209 VkPhysicalDeviceShaderFloat16Int8Features *features =
1210 (VkPhysicalDeviceShaderFloat16Int8Features*)ext;
1211 CORE_FEATURE(1, 2, shaderFloat16);
1212 CORE_FEATURE(1, 2, shaderInt8);
1213 break;
1214 }
1215 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES: {
1216 VkPhysicalDeviceShaderAtomicInt64Features *features =
1217 (VkPhysicalDeviceShaderAtomicInt64Features *)ext;
1218 CORE_FEATURE(1, 2, shaderBufferInt64Atomics);
1219 CORE_FEATURE(1, 2, shaderSharedInt64Atomics);
1220 break;
1221 }
1222 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DEMOTE_TO_HELPER_INVOCATION_FEATURES_EXT: {
1223 VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT *features =
1224 (VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT *)ext;
1225 features->shaderDemoteToHelperInvocation = LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm;
1226 break;
1227 }
1228 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
1229 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
1230 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
1231
1232 features->inlineUniformBlock = true;
1233 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
1234 break;
1235 }
1236 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
1237 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
1238 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
1239 features->computeDerivativeGroupQuads = false;
1240 features->computeDerivativeGroupLinear = true;
1241 break;
1242 }
1243 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
1244 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
1245 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
1246 features->ycbcrImageArrays = true;
1247 break;
1248 }
1249 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES: {
1250 VkPhysicalDeviceUniformBufferStandardLayoutFeatures *features =
1251 (VkPhysicalDeviceUniformBufferStandardLayoutFeatures *)ext;
1252 CORE_FEATURE(1, 2, uniformBufferStandardLayout);
1253 break;
1254 }
1255 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT: {
1256 VkPhysicalDeviceIndexTypeUint8FeaturesEXT *features =
1257 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT *)ext;
1258 features->indexTypeUint8 = pdevice->rad_info.chip_class >= GFX8;
1259 break;
1260 }
1261 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGELESS_FRAMEBUFFER_FEATURES: {
1262 VkPhysicalDeviceImagelessFramebufferFeatures *features =
1263 (VkPhysicalDeviceImagelessFramebufferFeatures *)ext;
1264 CORE_FEATURE(1, 2, imagelessFramebuffer);
1265 break;
1266 }
1267 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR: {
1268 VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *features =
1269 (VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *)ext;
1270 features->pipelineExecutableInfo = true;
1271 break;
1272 }
1273 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CLOCK_FEATURES_KHR: {
1274 VkPhysicalDeviceShaderClockFeaturesKHR *features =
1275 (VkPhysicalDeviceShaderClockFeaturesKHR *)ext;
1276 features->shaderSubgroupClock = true;
1277 features->shaderDeviceClock = pdevice->rad_info.chip_class >= GFX8;
1278 break;
1279 }
1280 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_FEATURES_EXT: {
1281 VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT *features =
1282 (VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT *)ext;
1283 features->texelBufferAlignment = true;
1284 break;
1285 }
1286 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_FEATURES: {
1287 VkPhysicalDeviceTimelineSemaphoreFeatures *features =
1288 (VkPhysicalDeviceTimelineSemaphoreFeatures *) ext;
1289 CORE_FEATURE(1, 2, timelineSemaphore);
1290 break;
1291 }
1292 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_FEATURES_EXT: {
1293 VkPhysicalDeviceSubgroupSizeControlFeaturesEXT *features =
1294 (VkPhysicalDeviceSubgroupSizeControlFeaturesEXT *)ext;
1295 features->subgroupSizeControl = true;
1296 features->computeFullSubgroups = true;
1297 break;
1298 }
1299 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COHERENT_MEMORY_FEATURES_AMD: {
1300 VkPhysicalDeviceCoherentMemoryFeaturesAMD *features =
1301 (VkPhysicalDeviceCoherentMemoryFeaturesAMD *)ext;
1302 features->deviceCoherentMemory = pdevice->rad_info.has_l2_uncached;
1303 break;
1304 }
1305 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_SUBGROUP_EXTENDED_TYPES_FEATURES: {
1306 VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures *features =
1307 (VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures *)ext;
1308 CORE_FEATURE(1, 2, shaderSubgroupExtendedTypes);
1309 break;
1310 }
1311 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SEPARATE_DEPTH_STENCIL_LAYOUTS_FEATURES_KHR: {
1312 VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR *features =
1313 (VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR *)ext;
1314 CORE_FEATURE(1, 2, separateDepthStencilLayouts);
1315 break;
1316 }
1317 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES: {
1318 radv_get_physical_device_features_1_1(pdevice, (void *)ext);
1319 break;
1320 }
1321 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES: {
1322 radv_get_physical_device_features_1_2(pdevice, (void *)ext);
1323 break;
1324 }
1325 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_FEATURES_EXT: {
1326 VkPhysicalDeviceLineRasterizationFeaturesEXT *features =
1327 (VkPhysicalDeviceLineRasterizationFeaturesEXT *)ext;
1328 features->rectangularLines = false;
1329 features->bresenhamLines = true;
1330 features->smoothLines = false;
1331 features->stippledRectangularLines = false;
1332 features->stippledBresenhamLines = true;
1333 features->stippledSmoothLines = false;
1334 break;
1335 }
1336 case VK_STRUCTURE_TYPE_DEVICE_MEMORY_OVERALLOCATION_CREATE_INFO_AMD: {
1337 VkDeviceMemoryOverallocationCreateInfoAMD *features =
1338 (VkDeviceMemoryOverallocationCreateInfoAMD *)ext;
1339 features->overallocationBehavior = true;
1340 break;
1341 }
1342 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ROBUSTNESS_2_FEATURES_EXT: {
1343 VkPhysicalDeviceRobustness2FeaturesEXT *features =
1344 (VkPhysicalDeviceRobustness2FeaturesEXT *)ext;
1345 features->robustBufferAccess2 = true;
1346 features->robustImageAccess2 = true;
1347 features->nullDescriptor = true;
1348 break;
1349 }
1350 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_FEATURES_EXT: {
1351 VkPhysicalDeviceCustomBorderColorFeaturesEXT *features =
1352 (VkPhysicalDeviceCustomBorderColorFeaturesEXT *)ext;
1353 features->customBorderColors = true;
1354 features->customBorderColorWithoutFormat = true;
1355 break;
1356 }
1357 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PRIVATE_DATA_FEATURES_EXT: {
1358 VkPhysicalDevicePrivateDataFeaturesEXT *features =
1359 (VkPhysicalDevicePrivateDataFeaturesEXT *)ext;
1360 features->privateData = true;
1361 break;
1362 }
1363 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_CREATION_CACHE_CONTROL_FEATURES_EXT: {
1364 VkPhysicalDevicePipelineCreationCacheControlFeaturesEXT *features =
1365 (VkPhysicalDevicePipelineCreationCacheControlFeaturesEXT *)ext;
1366 features-> pipelineCreationCacheControl = true;
1367 break;
1368 }
1369 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_MEMORY_MODEL_FEATURES_KHR: {
1370 VkPhysicalDeviceVulkanMemoryModelFeaturesKHR *features =
1371 (VkPhysicalDeviceVulkanMemoryModelFeaturesKHR *)ext;
1372 CORE_FEATURE(1, 2, vulkanMemoryModel);
1373 CORE_FEATURE(1, 2, vulkanMemoryModelDeviceScope);
1374 CORE_FEATURE(1, 2, vulkanMemoryModelAvailabilityVisibilityChains);
1375 break;
1376 }
1377 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTENDED_DYNAMIC_STATE_FEATURES_EXT: {
1378 VkPhysicalDeviceExtendedDynamicStateFeaturesEXT *features =
1379 (VkPhysicalDeviceExtendedDynamicStateFeaturesEXT *) ext;
1380 features->extendedDynamicState = true;
1381 break;
1382 }
1383 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGE_ROBUSTNESS_FEATURES_EXT: {
1384 VkPhysicalDeviceImageRobustnessFeaturesEXT *features =
1385 (VkPhysicalDeviceImageRobustnessFeaturesEXT *)ext;
1386 features->robustImageAccess = true;
1387 break;
1388 }
1389 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_FLOAT_FEATURES_EXT: {
1390 VkPhysicalDeviceShaderAtomicFloatFeaturesEXT *features =
1391 (VkPhysicalDeviceShaderAtomicFloatFeaturesEXT *)ext;
1392 features->shaderBufferFloat32Atomics = true;
1393 features->shaderBufferFloat32AtomicAdd = false;
1394 features->shaderBufferFloat64Atomics = true;
1395 features->shaderBufferFloat64AtomicAdd = false;
1396 features->shaderSharedFloat32Atomics = true;
1397 features->shaderSharedFloat32AtomicAdd = pdevice->rad_info.chip_class >= GFX8 &&
1398 (!pdevice->use_llvm || LLVM_VERSION_MAJOR >= 10);
1399 features->shaderSharedFloat64Atomics = true;
1400 features->shaderSharedFloat64AtomicAdd = false;
1401 features->shaderImageFloat32Atomics = true;
1402 features->shaderImageFloat32AtomicAdd = false;
1403 features->sparseImageFloat32Atomics = false;
1404 features->sparseImageFloat32AtomicAdd = false;
1405 break;
1406 }
1407 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_4444_FORMATS_FEATURES_EXT: {
1408 VkPhysicalDevice4444FormatsFeaturesEXT *features =
1409 (VkPhysicalDevice4444FormatsFeaturesEXT *)ext;
1410 features->formatA4R4G4B4 = true;
1411 features->formatA4B4G4R4 = true;
1412 break;
1413 }
1414 default:
1415 break;
1416 }
1417 }
1418 #undef CORE_FEATURE
1419 }
1420
1421 static size_t
1422 radv_max_descriptor_set_size()
1423 {
1424 /* make sure that the entire descriptor set is addressable with a signed
1425 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1426 * be at most 2 GiB. the combined image & samples object count as one of
1427 * both. This limit is for the pipeline layout, not for the set layout, but
1428 * there is no set limit, so we just set a pipeline limit. I don't think
1429 * any app is going to hit this soon. */
1430 return ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
1431 - MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1432 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1433 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1434 32 /* sampler, largest when combined with image */ +
1435 64 /* sampled image */ +
1436 64 /* storage image */);
1437 }
1438
1439 static uint32_t
1440 radv_uniform_buffer_offset_alignment(const struct radv_physical_device *pdevice)
1441 {
1442 uint32_t uniform_offset_alignment = driQueryOptioni(&pdevice->instance->dri_options,
1443 "radv_override_uniform_offset_alignment");
1444 if (!util_is_power_of_two_or_zero(uniform_offset_alignment)) {
1445 fprintf(stderr, "ERROR: invalid radv_override_uniform_offset_alignment setting %d:"
1446 "not a power of two\n", uniform_offset_alignment);
1447 uniform_offset_alignment = 0;
1448 }
1449
1450 /* Take at least the hardware limit. */
1451 return MAX2(uniform_offset_alignment, 4);
1452 }
1453
1454 void radv_GetPhysicalDeviceProperties(
1455 VkPhysicalDevice physicalDevice,
1456 VkPhysicalDeviceProperties* pProperties)
1457 {
1458 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1459 VkSampleCountFlags sample_counts = 0xf;
1460
1461 size_t max_descriptor_set_size = radv_max_descriptor_set_size();
1462
1463 VkPhysicalDeviceLimits limits = {
1464 .maxImageDimension1D = (1 << 14),
1465 .maxImageDimension2D = (1 << 14),
1466 .maxImageDimension3D = (1 << 11),
1467 .maxImageDimensionCube = (1 << 14),
1468 .maxImageArrayLayers = (1 << 11),
1469 .maxTexelBufferElements = UINT32_MAX,
1470 .maxUniformBufferRange = UINT32_MAX,
1471 .maxStorageBufferRange = UINT32_MAX,
1472 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1473 .maxMemoryAllocationCount = UINT32_MAX,
1474 .maxSamplerAllocationCount = 64 * 1024,
1475 .bufferImageGranularity = 64, /* A cache line */
1476 .sparseAddressSpaceSize = RADV_MAX_MEMORY_ALLOCATION_SIZE, /* buffer max size */
1477 .maxBoundDescriptorSets = MAX_SETS,
1478 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1479 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1480 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1481 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1482 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1483 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1484 .maxPerStageResources = max_descriptor_set_size,
1485 .maxDescriptorSetSamplers = max_descriptor_set_size,
1486 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1487 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1488 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1489 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1490 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1491 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1492 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1493 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1494 .maxVertexInputBindings = MAX_VBS,
1495 .maxVertexInputAttributeOffset = 2047,
1496 .maxVertexInputBindingStride = 2048,
1497 .maxVertexOutputComponents = 128,
1498 .maxTessellationGenerationLevel = 64,
1499 .maxTessellationPatchSize = 32,
1500 .maxTessellationControlPerVertexInputComponents = 128,
1501 .maxTessellationControlPerVertexOutputComponents = 128,
1502 .maxTessellationControlPerPatchOutputComponents = 120,
1503 .maxTessellationControlTotalOutputComponents = 4096,
1504 .maxTessellationEvaluationInputComponents = 128,
1505 .maxTessellationEvaluationOutputComponents = 128,
1506 .maxGeometryShaderInvocations = 127,
1507 .maxGeometryInputComponents = 64,
1508 .maxGeometryOutputComponents = 128,
1509 .maxGeometryOutputVertices = 256,
1510 .maxGeometryTotalOutputComponents = 1024,
1511 .maxFragmentInputComponents = 128,
1512 .maxFragmentOutputAttachments = 8,
1513 .maxFragmentDualSrcAttachments = 1,
1514 .maxFragmentCombinedOutputResources = 8,
1515 .maxComputeSharedMemorySize = 32768,
1516 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1517 .maxComputeWorkGroupInvocations = 1024,
1518 .maxComputeWorkGroupSize = {
1519 1024,
1520 1024,
1521 1024
1522 },
1523 .subPixelPrecisionBits = 8,
1524 .subTexelPrecisionBits = 8,
1525 .mipmapPrecisionBits = 8,
1526 .maxDrawIndexedIndexValue = UINT32_MAX,
1527 .maxDrawIndirectCount = UINT32_MAX,
1528 .maxSamplerLodBias = 16,
1529 .maxSamplerAnisotropy = 16,
1530 .maxViewports = MAX_VIEWPORTS,
1531 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1532 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1533 .viewportSubPixelBits = 8,
1534 .minMemoryMapAlignment = 4096, /* A page */
1535 .minTexelBufferOffsetAlignment = 4,
1536 .minUniformBufferOffsetAlignment = radv_uniform_buffer_offset_alignment(pdevice),
1537 .minStorageBufferOffsetAlignment = 4,
1538 .minTexelOffset = -32,
1539 .maxTexelOffset = 31,
1540 .minTexelGatherOffset = -32,
1541 .maxTexelGatherOffset = 31,
1542 .minInterpolationOffset = -2,
1543 .maxInterpolationOffset = 2,
1544 .subPixelInterpolationOffsetBits = 8,
1545 .maxFramebufferWidth = (1 << 14),
1546 .maxFramebufferHeight = (1 << 14),
1547 .maxFramebufferLayers = (1 << 10),
1548 .framebufferColorSampleCounts = sample_counts,
1549 .framebufferDepthSampleCounts = sample_counts,
1550 .framebufferStencilSampleCounts = sample_counts,
1551 .framebufferNoAttachmentsSampleCounts = sample_counts,
1552 .maxColorAttachments = MAX_RTS,
1553 .sampledImageColorSampleCounts = sample_counts,
1554 .sampledImageIntegerSampleCounts = sample_counts,
1555 .sampledImageDepthSampleCounts = sample_counts,
1556 .sampledImageStencilSampleCounts = sample_counts,
1557 .storageImageSampleCounts = sample_counts,
1558 .maxSampleMaskWords = 1,
1559 .timestampComputeAndGraphics = true,
1560 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1561 .maxClipDistances = 8,
1562 .maxCullDistances = 8,
1563 .maxCombinedClipAndCullDistances = 8,
1564 .discreteQueuePriorities = 2,
1565 .pointSizeRange = { 0.0, 8191.875 },
1566 .lineWidthRange = { 0.0, 8191.875 },
1567 .pointSizeGranularity = (1.0 / 8.0),
1568 .lineWidthGranularity = (1.0 / 8.0),
1569 .strictLines = false, /* FINISHME */
1570 .standardSampleLocations = true,
1571 .optimalBufferCopyOffsetAlignment = 128,
1572 .optimalBufferCopyRowPitchAlignment = 128,
1573 .nonCoherentAtomSize = 64,
1574 };
1575
1576 *pProperties = (VkPhysicalDeviceProperties) {
1577 .apiVersion = radv_physical_device_api_version(pdevice),
1578 .driverVersion = vk_get_driver_version(),
1579 .vendorID = ATI_VENDOR_ID,
1580 .deviceID = pdevice->rad_info.pci_id,
1581 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1582 .limits = limits,
1583 .sparseProperties = {0},
1584 };
1585
1586 strcpy(pProperties->deviceName, pdevice->name);
1587 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1588 }
1589
1590 static void
1591 radv_get_physical_device_properties_1_1(struct radv_physical_device *pdevice,
1592 VkPhysicalDeviceVulkan11Properties *p)
1593 {
1594 assert(p->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES);
1595
1596 memcpy(p->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1597 memcpy(p->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1598 memset(p->deviceLUID, 0, VK_LUID_SIZE);
1599 /* The LUID is for Windows. */
1600 p->deviceLUIDValid = false;
1601 p->deviceNodeMask = 0;
1602
1603 p->subgroupSize = RADV_SUBGROUP_SIZE;
1604 p->subgroupSupportedStages = VK_SHADER_STAGE_ALL_GRAPHICS |
1605 VK_SHADER_STAGE_COMPUTE_BIT;
1606 p->subgroupSupportedOperations = VK_SUBGROUP_FEATURE_BASIC_BIT |
1607 VK_SUBGROUP_FEATURE_VOTE_BIT |
1608 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1609 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1610 VK_SUBGROUP_FEATURE_CLUSTERED_BIT |
1611 VK_SUBGROUP_FEATURE_QUAD_BIT |
1612 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1613 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1614 p->subgroupQuadOperationsInAllStages = true;
1615
1616 p->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1617 p->maxMultiviewViewCount = MAX_VIEWS;
1618 p->maxMultiviewInstanceIndex = INT_MAX;
1619 p->protectedNoFault = false;
1620 p->maxPerSetDescriptors = RADV_MAX_PER_SET_DESCRIPTORS;
1621 p->maxMemoryAllocationSize = RADV_MAX_MEMORY_ALLOCATION_SIZE;
1622 }
1623
1624 static void
1625 radv_get_physical_device_properties_1_2(struct radv_physical_device *pdevice,
1626 VkPhysicalDeviceVulkan12Properties *p)
1627 {
1628 assert(p->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES);
1629
1630 p->driverID = VK_DRIVER_ID_MESA_RADV;
1631 snprintf(p->driverName, VK_MAX_DRIVER_NAME_SIZE, "radv");
1632 snprintf(p->driverInfo, VK_MAX_DRIVER_INFO_SIZE,
1633 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1 " (%s)",
1634 radv_get_compiler_string(pdevice));
1635 p->conformanceVersion = (VkConformanceVersion) {
1636 .major = 1,
1637 .minor = 2,
1638 .subminor = 3,
1639 .patch = 0,
1640 };
1641
1642 /* On AMD hardware, denormals and rounding modes for fp16/fp64 are
1643 * controlled by the same config register.
1644 */
1645 if (pdevice->rad_info.has_packed_math_16bit) {
1646 p->denormBehaviorIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
1647 p->roundingModeIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
1648 } else {
1649 p->denormBehaviorIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL_KHR;
1650 p->roundingModeIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL_KHR;
1651 }
1652
1653 /* With LLVM, do not allow both preserving and flushing denorms because
1654 * different shaders in the same pipeline can have different settings and
1655 * this won't work for merged shaders. To make it work, this requires LLVM
1656 * support for changing the register. The same logic applies for the
1657 * rounding modes because they are configured with the same config
1658 * register.
1659 */
1660 p->shaderDenormFlushToZeroFloat32 = true;
1661 p->shaderDenormPreserveFloat32 = !pdevice->use_llvm;
1662 p->shaderRoundingModeRTEFloat32 = true;
1663 p->shaderRoundingModeRTZFloat32 = !pdevice->use_llvm;
1664 p->shaderSignedZeroInfNanPreserveFloat32 = true;
1665
1666 p->shaderDenormFlushToZeroFloat16 = pdevice->rad_info.has_packed_math_16bit && !pdevice->use_llvm;
1667 p->shaderDenormPreserveFloat16 = pdevice->rad_info.has_packed_math_16bit;
1668 p->shaderRoundingModeRTEFloat16 = pdevice->rad_info.has_packed_math_16bit;
1669 p->shaderRoundingModeRTZFloat16 = pdevice->rad_info.has_packed_math_16bit && !pdevice->use_llvm;
1670 p->shaderSignedZeroInfNanPreserveFloat16 = pdevice->rad_info.has_packed_math_16bit;
1671
1672 p->shaderDenormFlushToZeroFloat64 = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_llvm;
1673 p->shaderDenormPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8;
1674 p->shaderRoundingModeRTEFloat64 = pdevice->rad_info.chip_class >= GFX8;
1675 p->shaderRoundingModeRTZFloat64 = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_llvm;
1676 p->shaderSignedZeroInfNanPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8;
1677
1678 p->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1679 p->shaderUniformBufferArrayNonUniformIndexingNative = false;
1680 p->shaderSampledImageArrayNonUniformIndexingNative = false;
1681 p->shaderStorageBufferArrayNonUniformIndexingNative = false;
1682 p->shaderStorageImageArrayNonUniformIndexingNative = false;
1683 p->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1684 p->robustBufferAccessUpdateAfterBind = false;
1685 p->quadDivergentImplicitLod = false;
1686
1687 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1688 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1689 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1690 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1691 32 /* sampler, largest when combined with image */ +
1692 64 /* sampled image */ +
1693 64 /* storage image */);
1694 p->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1695 p->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1696 p->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1697 p->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1698 p->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1699 p->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1700 p->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1701 p->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1702 p->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1703 p->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1704 p->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1705 p->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1706 p->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1707 p->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1708 p->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1709
1710 /* We support all of the depth resolve modes */
1711 p->supportedDepthResolveModes = VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1712 VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
1713 VK_RESOLVE_MODE_MIN_BIT_KHR |
1714 VK_RESOLVE_MODE_MAX_BIT_KHR;
1715
1716 /* Average doesn't make sense for stencil so we don't support that */
1717 p->supportedStencilResolveModes = VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1718 VK_RESOLVE_MODE_MIN_BIT_KHR |
1719 VK_RESOLVE_MODE_MAX_BIT_KHR;
1720
1721 p->independentResolveNone = true;
1722 p->independentResolve = true;
1723
1724 /* GFX6-8 only support single channel min/max filter. */
1725 p->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1726 p->filterMinmaxSingleComponentFormats = true;
1727
1728 p->maxTimelineSemaphoreValueDifference = UINT64_MAX;
1729
1730 p->framebufferIntegerColorSampleCounts = VK_SAMPLE_COUNT_1_BIT;
1731 }
1732
1733 void radv_GetPhysicalDeviceProperties2(
1734 VkPhysicalDevice physicalDevice,
1735 VkPhysicalDeviceProperties2 *pProperties)
1736 {
1737 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1738 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1739
1740 VkPhysicalDeviceVulkan11Properties core_1_1 = {
1741 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES,
1742 };
1743 radv_get_physical_device_properties_1_1(pdevice, &core_1_1);
1744
1745 VkPhysicalDeviceVulkan12Properties core_1_2 = {
1746 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES,
1747 };
1748 radv_get_physical_device_properties_1_2(pdevice, &core_1_2);
1749
1750 #define CORE_RENAMED_PROPERTY(major, minor, ext_property, core_property) \
1751 memcpy(&properties->ext_property, &core_##major##_##minor.core_property, \
1752 sizeof(core_##major##_##minor.core_property))
1753
1754 #define CORE_PROPERTY(major, minor, property) \
1755 CORE_RENAMED_PROPERTY(major, minor, property, property)
1756
1757 vk_foreach_struct(ext, pProperties->pNext) {
1758 switch (ext->sType) {
1759 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1760 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1761 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1762 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1763 break;
1764 }
1765 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1766 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1767 CORE_PROPERTY(1, 1, deviceUUID);
1768 CORE_PROPERTY(1, 1, driverUUID);
1769 CORE_PROPERTY(1, 1, deviceLUID);
1770 CORE_PROPERTY(1, 1, deviceLUIDValid);
1771 break;
1772 }
1773 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1774 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1775 CORE_PROPERTY(1, 1, maxMultiviewViewCount);
1776 CORE_PROPERTY(1, 1, maxMultiviewInstanceIndex);
1777 break;
1778 }
1779 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1780 VkPhysicalDevicePointClippingProperties *properties =
1781 (VkPhysicalDevicePointClippingProperties*)ext;
1782 CORE_PROPERTY(1, 1, pointClippingBehavior);
1783 break;
1784 }
1785 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1786 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1787 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1788 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1789 break;
1790 }
1791 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1792 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1793 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1794 properties->minImportedHostPointerAlignment = 4096;
1795 break;
1796 }
1797 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1798 VkPhysicalDeviceSubgroupProperties *properties =
1799 (VkPhysicalDeviceSubgroupProperties*)ext;
1800 CORE_PROPERTY(1, 1, subgroupSize);
1801 CORE_RENAMED_PROPERTY(1, 1, supportedStages,
1802 subgroupSupportedStages);
1803 CORE_RENAMED_PROPERTY(1, 1, supportedOperations,
1804 subgroupSupportedOperations);
1805 CORE_RENAMED_PROPERTY(1, 1, quadOperationsInAllStages,
1806 subgroupQuadOperationsInAllStages);
1807 break;
1808 }
1809 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1810 VkPhysicalDeviceMaintenance3Properties *properties =
1811 (VkPhysicalDeviceMaintenance3Properties*)ext;
1812 CORE_PROPERTY(1, 1, maxPerSetDescriptors);
1813 CORE_PROPERTY(1, 1, maxMemoryAllocationSize);
1814 break;
1815 }
1816 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES: {
1817 VkPhysicalDeviceSamplerFilterMinmaxProperties *properties =
1818 (VkPhysicalDeviceSamplerFilterMinmaxProperties *)ext;
1819 CORE_PROPERTY(1, 2, filterMinmaxImageComponentMapping);
1820 CORE_PROPERTY(1, 2, filterMinmaxSingleComponentFormats);
1821 break;
1822 }
1823 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1824 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1825 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1826
1827 /* Shader engines. */
1828 properties->shaderEngineCount =
1829 pdevice->rad_info.max_se;
1830 properties->shaderArraysPerEngineCount =
1831 pdevice->rad_info.max_sh_per_se;
1832 properties->computeUnitsPerShaderArray =
1833 pdevice->rad_info.min_good_cu_per_sa;
1834 properties->simdPerComputeUnit =
1835 pdevice->rad_info.num_simd_per_compute_unit;
1836 properties->wavefrontsPerSimd =
1837 pdevice->rad_info.max_wave64_per_simd;
1838 properties->wavefrontSize = 64;
1839
1840 /* SGPR. */
1841 properties->sgprsPerSimd =
1842 pdevice->rad_info.num_physical_sgprs_per_simd;
1843 properties->minSgprAllocation =
1844 pdevice->rad_info.min_sgpr_alloc;
1845 properties->maxSgprAllocation =
1846 pdevice->rad_info.max_sgpr_alloc;
1847 properties->sgprAllocationGranularity =
1848 pdevice->rad_info.sgpr_alloc_granularity;
1849
1850 /* VGPR. */
1851 properties->vgprsPerSimd =
1852 pdevice->rad_info.num_physical_wave64_vgprs_per_simd;
1853 properties->minVgprAllocation =
1854 pdevice->rad_info.min_wave64_vgpr_alloc;
1855 properties->maxVgprAllocation =
1856 pdevice->rad_info.max_vgpr_alloc;
1857 properties->vgprAllocationGranularity =
1858 pdevice->rad_info.wave64_vgpr_alloc_granularity;
1859 break;
1860 }
1861 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_2_AMD: {
1862 VkPhysicalDeviceShaderCoreProperties2AMD *properties =
1863 (VkPhysicalDeviceShaderCoreProperties2AMD *)ext;
1864
1865 properties->shaderCoreFeatures = 0;
1866 properties->activeComputeUnitCount =
1867 pdevice->rad_info.num_good_compute_units;
1868 break;
1869 }
1870 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1871 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1872 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1873 properties->maxVertexAttribDivisor = UINT32_MAX;
1874 break;
1875 }
1876 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES: {
1877 VkPhysicalDeviceDescriptorIndexingProperties *properties =
1878 (VkPhysicalDeviceDescriptorIndexingProperties*)ext;
1879 CORE_PROPERTY(1, 2, maxUpdateAfterBindDescriptorsInAllPools);
1880 CORE_PROPERTY(1, 2, shaderUniformBufferArrayNonUniformIndexingNative);
1881 CORE_PROPERTY(1, 2, shaderSampledImageArrayNonUniformIndexingNative);
1882 CORE_PROPERTY(1, 2, shaderStorageBufferArrayNonUniformIndexingNative);
1883 CORE_PROPERTY(1, 2, shaderStorageImageArrayNonUniformIndexingNative);
1884 CORE_PROPERTY(1, 2, shaderInputAttachmentArrayNonUniformIndexingNative);
1885 CORE_PROPERTY(1, 2, robustBufferAccessUpdateAfterBind);
1886 CORE_PROPERTY(1, 2, quadDivergentImplicitLod);
1887 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSamplers);
1888 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindUniformBuffers);
1889 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageBuffers);
1890 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSampledImages);
1891 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageImages);
1892 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindInputAttachments);
1893 CORE_PROPERTY(1, 2, maxPerStageUpdateAfterBindResources);
1894 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSamplers);
1895 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffers);
1896 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffersDynamic);
1897 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffers);
1898 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffersDynamic);
1899 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSampledImages);
1900 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageImages);
1901 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindInputAttachments);
1902 break;
1903 }
1904 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1905 VkPhysicalDeviceProtectedMemoryProperties *properties =
1906 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1907 CORE_PROPERTY(1, 1, protectedNoFault);
1908 break;
1909 }
1910 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1911 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1912 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1913 properties->primitiveOverestimationSize = 0;
1914 properties->maxExtraPrimitiveOverestimationSize = 0;
1915 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1916 properties->primitiveUnderestimation = false;
1917 properties->conservativePointAndLineRasterization = false;
1918 properties->degenerateTrianglesRasterized = false;
1919 properties->degenerateLinesRasterized = false;
1920 properties->fullyCoveredFragmentShaderInputVariable = false;
1921 properties->conservativeRasterizationPostDepthCoverage = false;
1922 break;
1923 }
1924 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1925 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1926 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1927 properties->pciDomain = pdevice->bus_info.domain;
1928 properties->pciBus = pdevice->bus_info.bus;
1929 properties->pciDevice = pdevice->bus_info.dev;
1930 properties->pciFunction = pdevice->bus_info.func;
1931 break;
1932 }
1933 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES: {
1934 VkPhysicalDeviceDriverProperties *properties =
1935 (VkPhysicalDeviceDriverProperties *) ext;
1936 CORE_PROPERTY(1, 2, driverID);
1937 CORE_PROPERTY(1, 2, driverName);
1938 CORE_PROPERTY(1, 2, driverInfo);
1939 CORE_PROPERTY(1, 2, conformanceVersion);
1940 break;
1941 }
1942 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1943 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1944 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1945 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1946 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1947 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1948 properties->maxTransformFeedbackStreamDataSize = 512;
1949 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1950 properties->maxTransformFeedbackBufferDataStride = 512;
1951 properties->transformFeedbackQueries = !pdevice->use_ngg_streamout;
1952 properties->transformFeedbackStreamsLinesTriangles = !pdevice->use_ngg_streamout;
1953 properties->transformFeedbackRasterizationStreamSelect = false;
1954 properties->transformFeedbackDraw = true;
1955 break;
1956 }
1957 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1958 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1959 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1960
1961 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1962 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1963 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1964 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1965 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1966 break;
1967 }
1968 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT: {
1969 VkPhysicalDeviceSampleLocationsPropertiesEXT *properties =
1970 (VkPhysicalDeviceSampleLocationsPropertiesEXT *)ext;
1971 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_2_BIT |
1972 VK_SAMPLE_COUNT_4_BIT |
1973 VK_SAMPLE_COUNT_8_BIT;
1974 properties->maxSampleLocationGridSize = (VkExtent2D){ 2 , 2 };
1975 properties->sampleLocationCoordinateRange[0] = 0.0f;
1976 properties->sampleLocationCoordinateRange[1] = 0.9375f;
1977 properties->sampleLocationSubPixelBits = 4;
1978 properties->variableSampleLocations = false;
1979 break;
1980 }
1981 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES: {
1982 VkPhysicalDeviceDepthStencilResolveProperties *properties =
1983 (VkPhysicalDeviceDepthStencilResolveProperties *)ext;
1984 CORE_PROPERTY(1, 2, supportedDepthResolveModes);
1985 CORE_PROPERTY(1, 2, supportedStencilResolveModes);
1986 CORE_PROPERTY(1, 2, independentResolveNone);
1987 CORE_PROPERTY(1, 2, independentResolve);
1988 break;
1989 }
1990 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_PROPERTIES_EXT: {
1991 VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT *properties =
1992 (VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT *)ext;
1993 properties->storageTexelBufferOffsetAlignmentBytes = 4;
1994 properties->storageTexelBufferOffsetSingleTexelAlignment = true;
1995 properties->uniformTexelBufferOffsetAlignmentBytes = 4;
1996 properties->uniformTexelBufferOffsetSingleTexelAlignment = true;
1997 break;
1998 }
1999 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT_CONTROLS_PROPERTIES : {
2000 VkPhysicalDeviceFloatControlsProperties *properties =
2001 (VkPhysicalDeviceFloatControlsProperties *)ext;
2002 CORE_PROPERTY(1, 2, denormBehaviorIndependence);
2003 CORE_PROPERTY(1, 2, roundingModeIndependence);
2004 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat16);
2005 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat16);
2006 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat16);
2007 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat16);
2008 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat16);
2009 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat32);
2010 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat32);
2011 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat32);
2012 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat32);
2013 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat32);
2014 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat64);
2015 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat64);
2016 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat64);
2017 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat64);
2018 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat64);
2019 break;
2020 }
2021 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_PROPERTIES: {
2022 VkPhysicalDeviceTimelineSemaphoreProperties *properties =
2023 (VkPhysicalDeviceTimelineSemaphoreProperties *) ext;
2024 CORE_PROPERTY(1, 2, maxTimelineSemaphoreValueDifference);
2025 break;
2026 }
2027 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_PROPERTIES_EXT: {
2028 VkPhysicalDeviceSubgroupSizeControlPropertiesEXT *props =
2029 (VkPhysicalDeviceSubgroupSizeControlPropertiesEXT *)ext;
2030 props->minSubgroupSize = 64;
2031 props->maxSubgroupSize = 64;
2032 props->maxComputeWorkgroupSubgroups = UINT32_MAX;
2033 props->requiredSubgroupSizeStages = 0;
2034
2035 if (pdevice->rad_info.chip_class >= GFX10) {
2036 /* Only GFX10+ supports wave32. */
2037 props->minSubgroupSize = 32;
2038 props->requiredSubgroupSizeStages = VK_SHADER_STAGE_COMPUTE_BIT;
2039 }
2040 break;
2041 }
2042 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES:
2043 radv_get_physical_device_properties_1_1(pdevice, (void *)ext);
2044 break;
2045 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES:
2046 radv_get_physical_device_properties_1_2(pdevice, (void *)ext);
2047 break;
2048 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_PROPERTIES_EXT: {
2049 VkPhysicalDeviceLineRasterizationPropertiesEXT *props =
2050 (VkPhysicalDeviceLineRasterizationPropertiesEXT *)ext;
2051 props->lineSubPixelPrecisionBits = 4;
2052 break;
2053 }
2054 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ROBUSTNESS_2_PROPERTIES_EXT: {
2055 VkPhysicalDeviceRobustness2PropertiesEXT *properties =
2056 (VkPhysicalDeviceRobustness2PropertiesEXT *)ext;
2057 properties->robustStorageBufferAccessSizeAlignment = 4;
2058 properties->robustUniformBufferAccessSizeAlignment = 4;
2059 break;
2060 }
2061 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_PROPERTIES_EXT: {
2062 VkPhysicalDeviceCustomBorderColorPropertiesEXT *props =
2063 (VkPhysicalDeviceCustomBorderColorPropertiesEXT *)ext;
2064 props->maxCustomBorderColorSamplers = RADV_BORDER_COLOR_COUNT;
2065 break;
2066 }
2067 default:
2068 break;
2069 }
2070 }
2071 }
2072
2073 static void radv_get_physical_device_queue_family_properties(
2074 struct radv_physical_device* pdevice,
2075 uint32_t* pCount,
2076 VkQueueFamilyProperties** pQueueFamilyProperties)
2077 {
2078 int num_queue_families = 1;
2079 int idx;
2080 if (pdevice->rad_info.num_rings[RING_COMPUTE] > 0 &&
2081 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
2082 num_queue_families++;
2083
2084 if (pQueueFamilyProperties == NULL) {
2085 *pCount = num_queue_families;
2086 return;
2087 }
2088
2089 if (!*pCount)
2090 return;
2091
2092 idx = 0;
2093 if (*pCount >= 1) {
2094 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
2095 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
2096 VK_QUEUE_COMPUTE_BIT |
2097 VK_QUEUE_TRANSFER_BIT |
2098 VK_QUEUE_SPARSE_BINDING_BIT,
2099 .queueCount = 1,
2100 .timestampValidBits = 64,
2101 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
2102 };
2103 idx++;
2104 }
2105
2106 if (pdevice->rad_info.num_rings[RING_COMPUTE] > 0 &&
2107 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
2108 if (*pCount > idx) {
2109 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
2110 .queueFlags = VK_QUEUE_COMPUTE_BIT |
2111 VK_QUEUE_TRANSFER_BIT |
2112 VK_QUEUE_SPARSE_BINDING_BIT,
2113 .queueCount = pdevice->rad_info.num_rings[RING_COMPUTE],
2114 .timestampValidBits = 64,
2115 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
2116 };
2117 idx++;
2118 }
2119 }
2120 *pCount = idx;
2121 }
2122
2123 void radv_GetPhysicalDeviceQueueFamilyProperties(
2124 VkPhysicalDevice physicalDevice,
2125 uint32_t* pCount,
2126 VkQueueFamilyProperties* pQueueFamilyProperties)
2127 {
2128 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
2129 if (!pQueueFamilyProperties) {
2130 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
2131 return;
2132 }
2133 VkQueueFamilyProperties *properties[] = {
2134 pQueueFamilyProperties + 0,
2135 pQueueFamilyProperties + 1,
2136 pQueueFamilyProperties + 2,
2137 };
2138 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
2139 assert(*pCount <= 3);
2140 }
2141
2142 void radv_GetPhysicalDeviceQueueFamilyProperties2(
2143 VkPhysicalDevice physicalDevice,
2144 uint32_t* pCount,
2145 VkQueueFamilyProperties2 *pQueueFamilyProperties)
2146 {
2147 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
2148 if (!pQueueFamilyProperties) {
2149 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
2150 return;
2151 }
2152 VkQueueFamilyProperties *properties[] = {
2153 &pQueueFamilyProperties[0].queueFamilyProperties,
2154 &pQueueFamilyProperties[1].queueFamilyProperties,
2155 &pQueueFamilyProperties[2].queueFamilyProperties,
2156 };
2157 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
2158 assert(*pCount <= 3);
2159 }
2160
2161 void radv_GetPhysicalDeviceMemoryProperties(
2162 VkPhysicalDevice physicalDevice,
2163 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
2164 {
2165 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2166
2167 *pMemoryProperties = physical_device->memory_properties;
2168 }
2169
2170 static void
2171 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
2172 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
2173 {
2174 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2175 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
2176 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
2177 uint64_t vram_size = radv_get_vram_size(device);
2178 uint64_t gtt_size = device->rad_info.gart_size;
2179 uint64_t heap_budget, heap_usage;
2180
2181 /* For all memory heaps, the computation of budget is as follow:
2182 * heap_budget = heap_size - global_heap_usage + app_heap_usage
2183 *
2184 * The Vulkan spec 1.1.97 says that the budget should include any
2185 * currently allocated device memory.
2186 *
2187 * Note that the application heap usages are not really accurate (eg.
2188 * in presence of shared buffers).
2189 */
2190 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
2191 uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;
2192
2193 if ((device->memory_domains[i] & RADEON_DOMAIN_VRAM) && (device->memory_flags[i] & RADEON_FLAG_NO_CPU_ACCESS)) {
2194 heap_usage = device->ws->query_value(device->ws,
2195 RADEON_ALLOCATED_VRAM);
2196
2197 heap_budget = vram_size -
2198 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
2199 heap_usage;
2200
2201 memoryBudget->heapBudget[heap_index] = heap_budget;
2202 memoryBudget->heapUsage[heap_index] = heap_usage;
2203 } else if (device->memory_domains[i] & RADEON_DOMAIN_VRAM) {
2204 heap_usage = device->ws->query_value(device->ws,
2205 RADEON_ALLOCATED_VRAM_VIS);
2206
2207 heap_budget = visible_vram_size -
2208 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
2209 heap_usage;
2210
2211 memoryBudget->heapBudget[heap_index] = heap_budget;
2212 memoryBudget->heapUsage[heap_index] = heap_usage;
2213 } else {
2214 assert(device->memory_domains[i] & RADEON_DOMAIN_GTT);
2215
2216 heap_usage = device->ws->query_value(device->ws,
2217 RADEON_ALLOCATED_GTT);
2218
2219 heap_budget = gtt_size -
2220 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
2221 heap_usage;
2222
2223 memoryBudget->heapBudget[heap_index] = heap_budget;
2224 memoryBudget->heapUsage[heap_index] = heap_usage;
2225 }
2226 }
2227
2228 /* The heapBudget and heapUsage values must be zero for array elements
2229 * greater than or equal to
2230 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
2231 */
2232 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
2233 memoryBudget->heapBudget[i] = 0;
2234 memoryBudget->heapUsage[i] = 0;
2235 }
2236 }
2237
2238 void radv_GetPhysicalDeviceMemoryProperties2(
2239 VkPhysicalDevice physicalDevice,
2240 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
2241 {
2242 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
2243 &pMemoryProperties->memoryProperties);
2244
2245 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
2246 vk_find_struct(pMemoryProperties->pNext,
2247 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
2248 if (memory_budget)
2249 radv_get_memory_budget_properties(physicalDevice, memory_budget);
2250 }
2251
2252 VkResult radv_GetMemoryHostPointerPropertiesEXT(
2253 VkDevice _device,
2254 VkExternalMemoryHandleTypeFlagBits handleType,
2255 const void *pHostPointer,
2256 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
2257 {
2258 RADV_FROM_HANDLE(radv_device, device, _device);
2259
2260 switch (handleType)
2261 {
2262 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
2263 const struct radv_physical_device *physical_device = device->physical_device;
2264 uint32_t memoryTypeBits = 0;
2265 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
2266 if (physical_device->memory_domains[i] == RADEON_DOMAIN_GTT &&
2267 !(physical_device->memory_flags[i] & RADEON_FLAG_GTT_WC)) {
2268 memoryTypeBits = (1 << i);
2269 break;
2270 }
2271 }
2272 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
2273 return VK_SUCCESS;
2274 }
2275 default:
2276 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
2277 }
2278 }
2279
2280 static enum radeon_ctx_priority
2281 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
2282 {
2283 /* Default to MEDIUM when a specific global priority isn't requested */
2284 if (!pObj)
2285 return RADEON_CTX_PRIORITY_MEDIUM;
2286
2287 switch(pObj->globalPriority) {
2288 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
2289 return RADEON_CTX_PRIORITY_REALTIME;
2290 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
2291 return RADEON_CTX_PRIORITY_HIGH;
2292 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
2293 return RADEON_CTX_PRIORITY_MEDIUM;
2294 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
2295 return RADEON_CTX_PRIORITY_LOW;
2296 default:
2297 unreachable("Illegal global priority value");
2298 return RADEON_CTX_PRIORITY_INVALID;
2299 }
2300 }
2301
2302 static int
2303 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
2304 uint32_t queue_family_index, int idx,
2305 VkDeviceQueueCreateFlags flags,
2306 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
2307 {
2308 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2309 queue->device = device;
2310 queue->queue_family_index = queue_family_index;
2311 queue->queue_idx = idx;
2312 queue->priority = radv_get_queue_global_priority(global_priority);
2313 queue->flags = flags;
2314 queue->hw_ctx = NULL;
2315
2316 VkResult result = device->ws->ctx_create(device->ws, queue->priority, &queue->hw_ctx);
2317 if (result != VK_SUCCESS)
2318 return vk_error(device->instance, result);
2319
2320 list_inithead(&queue->pending_submissions);
2321 pthread_mutex_init(&queue->pending_mutex, NULL);
2322
2323 pthread_mutex_init(&queue->thread_mutex, NULL);
2324 queue->thread_submission = NULL;
2325 queue->thread_running = queue->thread_exit = false;
2326 result = radv_create_pthread_cond(&queue->thread_cond);
2327 if (result != VK_SUCCESS)
2328 return vk_error(device->instance, result);
2329
2330 return VK_SUCCESS;
2331 }
2332
2333 static void
2334 radv_queue_finish(struct radv_queue *queue)
2335 {
2336 if (queue->thread_running) {
2337 p_atomic_set(&queue->thread_exit, true);
2338 pthread_cond_broadcast(&queue->thread_cond);
2339 pthread_join(queue->submission_thread, NULL);
2340 }
2341 pthread_cond_destroy(&queue->thread_cond);
2342 pthread_mutex_destroy(&queue->pending_mutex);
2343 pthread_mutex_destroy(&queue->thread_mutex);
2344
2345 if (queue->hw_ctx)
2346 queue->device->ws->ctx_destroy(queue->hw_ctx);
2347
2348 if (queue->initial_full_flush_preamble_cs)
2349 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2350 if (queue->initial_preamble_cs)
2351 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2352 if (queue->continue_preamble_cs)
2353 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2354 if (queue->descriptor_bo)
2355 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2356 if (queue->scratch_bo)
2357 queue->device->ws->buffer_destroy(queue->scratch_bo);
2358 if (queue->esgs_ring_bo)
2359 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2360 if (queue->gsvs_ring_bo)
2361 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2362 if (queue->tess_rings_bo)
2363 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
2364 if (queue->gds_bo)
2365 queue->device->ws->buffer_destroy(queue->gds_bo);
2366 if (queue->gds_oa_bo)
2367 queue->device->ws->buffer_destroy(queue->gds_oa_bo);
2368 if (queue->compute_scratch_bo)
2369 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2370 }
2371
2372 static void
2373 radv_bo_list_init(struct radv_bo_list *bo_list)
2374 {
2375 pthread_mutex_init(&bo_list->mutex, NULL);
2376 bo_list->list.count = bo_list->capacity = 0;
2377 bo_list->list.bos = NULL;
2378 }
2379
2380 static void
2381 radv_bo_list_finish(struct radv_bo_list *bo_list)
2382 {
2383 free(bo_list->list.bos);
2384 pthread_mutex_destroy(&bo_list->mutex);
2385 }
2386
2387 VkResult radv_bo_list_add(struct radv_device *device,
2388 struct radeon_winsys_bo *bo)
2389 {
2390 struct radv_bo_list *bo_list = &device->bo_list;
2391
2392 if (bo->is_local)
2393 return VK_SUCCESS;
2394
2395 if (unlikely(!device->use_global_bo_list))
2396 return VK_SUCCESS;
2397
2398 pthread_mutex_lock(&bo_list->mutex);
2399 if (bo_list->list.count == bo_list->capacity) {
2400 unsigned capacity = MAX2(4, bo_list->capacity * 2);
2401 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
2402
2403 if (!data) {
2404 pthread_mutex_unlock(&bo_list->mutex);
2405 return VK_ERROR_OUT_OF_HOST_MEMORY;
2406 }
2407
2408 bo_list->list.bos = (struct radeon_winsys_bo**)data;
2409 bo_list->capacity = capacity;
2410 }
2411
2412 bo_list->list.bos[bo_list->list.count++] = bo;
2413 pthread_mutex_unlock(&bo_list->mutex);
2414 return VK_SUCCESS;
2415 }
2416
2417 void radv_bo_list_remove(struct radv_device *device,
2418 struct radeon_winsys_bo *bo)
2419 {
2420 struct radv_bo_list *bo_list = &device->bo_list;
2421
2422 if (bo->is_local)
2423 return;
2424
2425 if (unlikely(!device->use_global_bo_list))
2426 return;
2427
2428 pthread_mutex_lock(&bo_list->mutex);
2429 /* Loop the list backwards so we find the most recently added
2430 * memory first. */
2431 for(unsigned i = bo_list->list.count; i-- > 0;) {
2432 if (bo_list->list.bos[i] == bo) {
2433 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
2434 --bo_list->list.count;
2435 break;
2436 }
2437 }
2438 pthread_mutex_unlock(&bo_list->mutex);
2439 }
2440
2441 static void
2442 radv_device_init_gs_info(struct radv_device *device)
2443 {
2444 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
2445 device->physical_device->rad_info.family);
2446 }
2447
2448 static int radv_get_device_extension_index(const char *name)
2449 {
2450 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
2451 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
2452 return i;
2453 }
2454 return -1;
2455 }
2456
2457 static int
2458 radv_get_int_debug_option(const char *name, int default_value)
2459 {
2460 const char *str;
2461 int result;
2462
2463 str = getenv(name);
2464 if (!str) {
2465 result = default_value;
2466 } else {
2467 char *endptr;
2468
2469 result = strtol(str, &endptr, 0);
2470 if (str == endptr) {
2471 /* No digits founs. */
2472 result = default_value;
2473 }
2474 }
2475
2476 return result;
2477 }
2478
2479 static bool radv_thread_trace_enabled()
2480 {
2481 return radv_get_int_debug_option("RADV_THREAD_TRACE", -1) >= 0 ||
2482 getenv("RADV_THREAD_TRACE_TRIGGER");
2483 }
2484
2485 static void
2486 radv_device_init_dispatch(struct radv_device *device)
2487 {
2488 const struct radv_instance *instance = device->physical_device->instance;
2489 const struct radv_device_dispatch_table *dispatch_table_layer = NULL;
2490 bool unchecked = instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS;
2491
2492 if (radv_thread_trace_enabled()) {
2493 /* Use device entrypoints from the SQTT layer if enabled. */
2494 dispatch_table_layer = &sqtt_device_dispatch_table;
2495 }
2496
2497 for (unsigned i = 0; i < ARRAY_SIZE(device->dispatch.entrypoints); i++) {
2498 /* Vulkan requires that entrypoints for extensions which have not been
2499 * enabled must not be advertised.
2500 */
2501 if (!unchecked &&
2502 !radv_device_entrypoint_is_enabled(i, instance->apiVersion,
2503 &instance->enabled_extensions,
2504 &device->enabled_extensions)) {
2505 device->dispatch.entrypoints[i] = NULL;
2506 } else if (dispatch_table_layer &&
2507 dispatch_table_layer->entrypoints[i]) {
2508 device->dispatch.entrypoints[i] =
2509 dispatch_table_layer->entrypoints[i];
2510 } else {
2511 device->dispatch.entrypoints[i] =
2512 radv_device_dispatch_table.entrypoints[i];
2513 }
2514 }
2515 }
2516
2517 static VkResult
2518 radv_create_pthread_cond(pthread_cond_t *cond)
2519 {
2520 pthread_condattr_t condattr;
2521 if (pthread_condattr_init(&condattr)) {
2522 return VK_ERROR_INITIALIZATION_FAILED;
2523 }
2524
2525 if (pthread_condattr_setclock(&condattr, CLOCK_MONOTONIC)) {
2526 pthread_condattr_destroy(&condattr);
2527 return VK_ERROR_INITIALIZATION_FAILED;
2528 }
2529 if (pthread_cond_init(cond, &condattr)) {
2530 pthread_condattr_destroy(&condattr);
2531 return VK_ERROR_INITIALIZATION_FAILED;
2532 }
2533 pthread_condattr_destroy(&condattr);
2534 return VK_SUCCESS;
2535 }
2536
2537 static VkResult
2538 check_physical_device_features(VkPhysicalDevice physicalDevice,
2539 const VkPhysicalDeviceFeatures *features)
2540 {
2541 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2542 VkPhysicalDeviceFeatures supported_features;
2543 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
2544 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
2545 VkBool32 *enabled_feature = (VkBool32 *)features;
2546 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
2547 for (uint32_t i = 0; i < num_features; i++) {
2548 if (enabled_feature[i] && !supported_feature[i])
2549 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
2550 }
2551
2552 return VK_SUCCESS;
2553 }
2554
2555 static VkResult radv_device_init_border_color(struct radv_device *device)
2556 {
2557 device->border_color_data.bo =
2558 device->ws->buffer_create(device->ws,
2559 RADV_BORDER_COLOR_BUFFER_SIZE,
2560 4096,
2561 RADEON_DOMAIN_VRAM,
2562 RADEON_FLAG_CPU_ACCESS |
2563 RADEON_FLAG_READ_ONLY |
2564 RADEON_FLAG_NO_INTERPROCESS_SHARING,
2565 RADV_BO_PRIORITY_SHADER);
2566
2567 if (device->border_color_data.bo == NULL)
2568 return vk_error(device->physical_device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2569
2570 device->border_color_data.colors_gpu_ptr =
2571 device->ws->buffer_map(device->border_color_data.bo);
2572 if (!device->border_color_data.colors_gpu_ptr)
2573 return vk_error(device->physical_device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2574 pthread_mutex_init(&device->border_color_data.mutex, NULL);
2575
2576 return VK_SUCCESS;
2577 }
2578
2579 static void radv_device_finish_border_color(struct radv_device *device)
2580 {
2581 if (device->border_color_data.bo) {
2582 device->ws->buffer_destroy(device->border_color_data.bo);
2583
2584 pthread_mutex_destroy(&device->border_color_data.mutex);
2585 }
2586 }
2587
2588 VkResult
2589 _radv_device_set_lost(struct radv_device *device,
2590 const char *file, int line,
2591 const char *msg, ...)
2592 {
2593 VkResult err;
2594 va_list ap;
2595
2596 p_atomic_inc(&device->lost);
2597
2598 va_start(ap, msg);
2599 err = __vk_errorv(device->physical_device->instance, device,
2600 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT,
2601 VK_ERROR_DEVICE_LOST, file, line, msg, ap);
2602 va_end(ap);
2603
2604 return err;
2605 }
2606
2607 VkResult radv_CreateDevice(
2608 VkPhysicalDevice physicalDevice,
2609 const VkDeviceCreateInfo* pCreateInfo,
2610 const VkAllocationCallbacks* pAllocator,
2611 VkDevice* pDevice)
2612 {
2613 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2614 VkResult result;
2615 struct radv_device *device;
2616
2617 bool keep_shader_info = false;
2618 bool robust_buffer_access = false;
2619 bool overallocation_disallowed = false;
2620 bool custom_border_colors = false;
2621
2622 /* Check enabled features */
2623 if (pCreateInfo->pEnabledFeatures) {
2624 result = check_physical_device_features(physicalDevice,
2625 pCreateInfo->pEnabledFeatures);
2626 if (result != VK_SUCCESS)
2627 return result;
2628
2629 if (pCreateInfo->pEnabledFeatures->robustBufferAccess)
2630 robust_buffer_access = true;
2631 }
2632
2633 vk_foreach_struct_const(ext, pCreateInfo->pNext) {
2634 switch (ext->sType) {
2635 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FEATURES_2: {
2636 const VkPhysicalDeviceFeatures2 *features = (const void *)ext;
2637 result = check_physical_device_features(physicalDevice,
2638 &features->features);
2639 if (result != VK_SUCCESS)
2640 return result;
2641
2642 if (features->features.robustBufferAccess)
2643 robust_buffer_access = true;
2644 break;
2645 }
2646 case VK_STRUCTURE_TYPE_DEVICE_MEMORY_OVERALLOCATION_CREATE_INFO_AMD: {
2647 const VkDeviceMemoryOverallocationCreateInfoAMD *overallocation = (const void *)ext;
2648 if (overallocation->overallocationBehavior == VK_MEMORY_OVERALLOCATION_BEHAVIOR_DISALLOWED_AMD)
2649 overallocation_disallowed = true;
2650 break;
2651 }
2652 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_FEATURES_EXT: {
2653 const VkPhysicalDeviceCustomBorderColorFeaturesEXT *border_color_features = (const void *)ext;
2654 custom_border_colors = border_color_features->customBorderColors;
2655 break;
2656 }
2657 default:
2658 break;
2659 }
2660 }
2661
2662 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
2663 sizeof(*device), 8,
2664 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2665 if (!device)
2666 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2667
2668 vk_device_init(&device->vk, pCreateInfo,
2669 &physical_device->instance->alloc, pAllocator);
2670
2671 device->instance = physical_device->instance;
2672 device->physical_device = physical_device;
2673
2674 device->ws = physical_device->ws;
2675
2676 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
2677 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
2678 int index = radv_get_device_extension_index(ext_name);
2679 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
2680 vk_free(&device->vk.alloc, device);
2681 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
2682 }
2683
2684 device->enabled_extensions.extensions[index] = true;
2685 }
2686
2687 radv_device_init_dispatch(device);
2688
2689 keep_shader_info = device->enabled_extensions.AMD_shader_info;
2690
2691 /* With update after bind we can't attach bo's to the command buffer
2692 * from the descriptor set anymore, so we have to use a global BO list.
2693 */
2694 device->use_global_bo_list =
2695 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
2696 device->enabled_extensions.EXT_descriptor_indexing ||
2697 device->enabled_extensions.EXT_buffer_device_address ||
2698 device->enabled_extensions.KHR_buffer_device_address;
2699
2700 device->robust_buffer_access = robust_buffer_access;
2701
2702 mtx_init(&device->shader_slab_mutex, mtx_plain);
2703 list_inithead(&device->shader_slabs);
2704
2705 device->overallocation_disallowed = overallocation_disallowed;
2706 mtx_init(&device->overallocation_mutex, mtx_plain);
2707
2708 radv_bo_list_init(&device->bo_list);
2709
2710 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
2711 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
2712 uint32_t qfi = queue_create->queueFamilyIndex;
2713 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
2714 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
2715
2716 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
2717
2718 device->queues[qfi] = vk_alloc(&device->vk.alloc,
2719 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2720 if (!device->queues[qfi]) {
2721 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2722 goto fail;
2723 }
2724
2725 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
2726
2727 device->queue_count[qfi] = queue_create->queueCount;
2728
2729 for (unsigned q = 0; q < queue_create->queueCount; q++) {
2730 result = radv_queue_init(device, &device->queues[qfi][q],
2731 qfi, q, queue_create->flags,
2732 global_priority);
2733 if (result != VK_SUCCESS)
2734 goto fail;
2735 }
2736 }
2737
2738 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
2739 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
2740
2741 /* Disable DFSM by default. As of 2019-09-15 Talos on Low is still 3% slower on Raven. */
2742 device->dfsm_allowed = device->pbb_allowed &&
2743 (device->instance->perftest_flags & RADV_PERFTEST_DFSM);
2744
2745 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
2746
2747 /* The maximum number of scratch waves. Scratch space isn't divided
2748 * evenly between CUs. The number is only a function of the number of CUs.
2749 * We can decrease the constant to decrease the scratch buffer size.
2750 *
2751 * sctx->scratch_waves must be >= the maximum possible size of
2752 * 1 threadgroup, so that the hw doesn't hang from being unable
2753 * to start any.
2754 *
2755 * The recommended value is 4 per CU at most. Higher numbers don't
2756 * bring much benefit, but they still occupy chip resources (think
2757 * async compute). I've seen ~2% performance difference between 4 and 32.
2758 */
2759 uint32_t max_threads_per_block = 2048;
2760 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
2761 max_threads_per_block / 64);
2762
2763 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
2764
2765 if (device->physical_device->rad_info.chip_class >= GFX7) {
2766 /* If the KMD allows it (there is a KMD hw register for it),
2767 * allow launching waves out-of-order.
2768 */
2769 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
2770 }
2771
2772 radv_device_init_gs_info(device);
2773
2774 device->tess_offchip_block_dw_size =
2775 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
2776
2777 if (getenv("RADV_TRACE_FILE")) {
2778 const char *filename = getenv("RADV_TRACE_FILE");
2779
2780 keep_shader_info = true;
2781
2782 if (!radv_init_trace(device))
2783 goto fail;
2784
2785 fprintf(stderr, "*****************************************************************************\n");
2786 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
2787 fprintf(stderr, "*****************************************************************************\n");
2788
2789 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
2790
2791 /* Wait for idle after every draw/dispatch to identify the
2792 * first bad call.
2793 */
2794 device->instance->debug_flags |= RADV_DEBUG_SYNC_SHADERS;
2795
2796 radv_dump_enabled_options(device, stderr);
2797 }
2798
2799 if (radv_thread_trace_enabled()) {
2800 fprintf(stderr, "*************************************************\n");
2801 fprintf(stderr, "* WARNING: Thread trace support is experimental *\n");
2802 fprintf(stderr, "*************************************************\n");
2803
2804 if (device->physical_device->rad_info.chip_class < GFX8) {
2805 fprintf(stderr, "GPU hardware not supported: refer to "
2806 "the RGP documentation for the list of "
2807 "supported GPUs!\n");
2808 abort();
2809 }
2810
2811 /* Default buffer size set to 1MB per SE. */
2812 device->thread_trace_buffer_size =
2813 radv_get_int_debug_option("RADV_THREAD_TRACE_BUFFER_SIZE", 1024 * 1024);
2814 device->thread_trace_start_frame = radv_get_int_debug_option("RADV_THREAD_TRACE", -1);
2815
2816 const char *trigger_file = getenv("RADV_THREAD_TRACE_TRIGGER");
2817 if (trigger_file)
2818 device->thread_trace_trigger_file = strdup(trigger_file);
2819
2820 if (!radv_thread_trace_init(device))
2821 goto fail;
2822 }
2823
2824 if (getenv("RADV_TRAP_HANDLER")) {
2825 /* TODO: Add support for more hardware. */
2826 assert(device->physical_device->rad_info.chip_class == GFX8);
2827
2828 fprintf(stderr, "**********************************************************************\n");
2829 fprintf(stderr, "* WARNING: RADV_TRAP_HANDLER is experimental and only for debugging! *\n");
2830 fprintf(stderr, "**********************************************************************\n");
2831
2832 /* To get the disassembly of the faulty shaders, we have to
2833 * keep some shader info around.
2834 */
2835 keep_shader_info = true;
2836
2837 if (!radv_trap_handler_init(device))
2838 goto fail;
2839 }
2840
2841 device->keep_shader_info = keep_shader_info;
2842 result = radv_device_init_meta(device);
2843 if (result != VK_SUCCESS)
2844 goto fail;
2845
2846 radv_device_init_msaa(device);
2847
2848 /* If the border color extension is enabled, let's create the buffer we need. */
2849 if (custom_border_colors) {
2850 result = radv_device_init_border_color(device);
2851 if (result != VK_SUCCESS)
2852 goto fail;
2853 }
2854
2855 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
2856 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
2857 if (!device->empty_cs[family])
2858 goto fail;
2859
2860 switch (family) {
2861 case RADV_QUEUE_GENERAL:
2862 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2863 radeon_emit(device->empty_cs[family], CC0_UPDATE_LOAD_ENABLES(1));
2864 radeon_emit(device->empty_cs[family], CC1_UPDATE_SHADOW_ENABLES(1));
2865 break;
2866 case RADV_QUEUE_COMPUTE:
2867 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
2868 radeon_emit(device->empty_cs[family], 0);
2869 break;
2870 }
2871
2872 result = device->ws->cs_finalize(device->empty_cs[family]);
2873 if (result != VK_SUCCESS)
2874 goto fail;
2875 }
2876
2877 if (device->physical_device->rad_info.chip_class >= GFX7)
2878 cik_create_gfx_config(device);
2879
2880 VkPipelineCacheCreateInfo ci;
2881 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
2882 ci.pNext = NULL;
2883 ci.flags = 0;
2884 ci.pInitialData = NULL;
2885 ci.initialDataSize = 0;
2886 VkPipelineCache pc;
2887 result = radv_CreatePipelineCache(radv_device_to_handle(device),
2888 &ci, NULL, &pc);
2889 if (result != VK_SUCCESS)
2890 goto fail_meta;
2891
2892 device->mem_cache = radv_pipeline_cache_from_handle(pc);
2893
2894 result = radv_create_pthread_cond(&device->timeline_cond);
2895 if (result != VK_SUCCESS)
2896 goto fail_mem_cache;
2897
2898 device->force_aniso =
2899 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
2900 if (device->force_aniso >= 0) {
2901 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
2902 1 << util_logbase2(device->force_aniso));
2903 }
2904
2905 *pDevice = radv_device_to_handle(device);
2906 return VK_SUCCESS;
2907
2908 fail_mem_cache:
2909 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2910 fail_meta:
2911 radv_device_finish_meta(device);
2912 fail:
2913 radv_bo_list_finish(&device->bo_list);
2914
2915 radv_thread_trace_finish(device);
2916 free(device->thread_trace_trigger_file);
2917
2918 radv_trap_handler_finish(device);
2919
2920 if (device->trace_bo)
2921 device->ws->buffer_destroy(device->trace_bo);
2922
2923 if (device->gfx_init)
2924 device->ws->buffer_destroy(device->gfx_init);
2925
2926 radv_device_finish_border_color(device);
2927
2928 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2929 for (unsigned q = 0; q < device->queue_count[i]; q++)
2930 radv_queue_finish(&device->queues[i][q]);
2931 if (device->queue_count[i])
2932 vk_free(&device->vk.alloc, device->queues[i]);
2933 }
2934
2935 vk_free(&device->vk.alloc, device);
2936 return result;
2937 }
2938
2939 void radv_DestroyDevice(
2940 VkDevice _device,
2941 const VkAllocationCallbacks* pAllocator)
2942 {
2943 RADV_FROM_HANDLE(radv_device, device, _device);
2944
2945 if (!device)
2946 return;
2947
2948 if (device->trace_bo)
2949 device->ws->buffer_destroy(device->trace_bo);
2950
2951 if (device->gfx_init)
2952 device->ws->buffer_destroy(device->gfx_init);
2953
2954 radv_device_finish_border_color(device);
2955
2956 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2957 for (unsigned q = 0; q < device->queue_count[i]; q++)
2958 radv_queue_finish(&device->queues[i][q]);
2959 if (device->queue_count[i])
2960 vk_free(&device->vk.alloc, device->queues[i]);
2961 if (device->empty_cs[i])
2962 device->ws->cs_destroy(device->empty_cs[i]);
2963 }
2964 radv_device_finish_meta(device);
2965
2966 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
2967 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2968
2969 radv_trap_handler_finish(device);
2970
2971 radv_destroy_shader_slabs(device);
2972
2973 pthread_cond_destroy(&device->timeline_cond);
2974 radv_bo_list_finish(&device->bo_list);
2975
2976 free(device->thread_trace_trigger_file);
2977 radv_thread_trace_finish(device);
2978
2979 vk_free(&device->vk.alloc, device);
2980 }
2981
2982 VkResult radv_EnumerateInstanceLayerProperties(
2983 uint32_t* pPropertyCount,
2984 VkLayerProperties* pProperties)
2985 {
2986 if (pProperties == NULL) {
2987 *pPropertyCount = 0;
2988 return VK_SUCCESS;
2989 }
2990
2991 /* None supported at this time */
2992 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2993 }
2994
2995 VkResult radv_EnumerateDeviceLayerProperties(
2996 VkPhysicalDevice physicalDevice,
2997 uint32_t* pPropertyCount,
2998 VkLayerProperties* pProperties)
2999 {
3000 if (pProperties == NULL) {
3001 *pPropertyCount = 0;
3002 return VK_SUCCESS;
3003 }
3004
3005 /* None supported at this time */
3006 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
3007 }
3008
3009 void radv_GetDeviceQueue2(
3010 VkDevice _device,
3011 const VkDeviceQueueInfo2* pQueueInfo,
3012 VkQueue* pQueue)
3013 {
3014 RADV_FROM_HANDLE(radv_device, device, _device);
3015 struct radv_queue *queue;
3016
3017 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
3018 if (pQueueInfo->flags != queue->flags) {
3019 /* From the Vulkan 1.1.70 spec:
3020 *
3021 * "The queue returned by vkGetDeviceQueue2 must have the same
3022 * flags value from this structure as that used at device
3023 * creation time in a VkDeviceQueueCreateInfo instance. If no
3024 * matching flags were specified at device creation time then
3025 * pQueue will return VK_NULL_HANDLE."
3026 */
3027 *pQueue = VK_NULL_HANDLE;
3028 return;
3029 }
3030
3031 *pQueue = radv_queue_to_handle(queue);
3032 }
3033
3034 void radv_GetDeviceQueue(
3035 VkDevice _device,
3036 uint32_t queueFamilyIndex,
3037 uint32_t queueIndex,
3038 VkQueue* pQueue)
3039 {
3040 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
3041 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
3042 .queueFamilyIndex = queueFamilyIndex,
3043 .queueIndex = queueIndex
3044 };
3045
3046 radv_GetDeviceQueue2(_device, &info, pQueue);
3047 }
3048
3049 static void
3050 fill_geom_tess_rings(struct radv_queue *queue,
3051 uint32_t *map,
3052 bool add_sample_positions,
3053 uint32_t esgs_ring_size,
3054 struct radeon_winsys_bo *esgs_ring_bo,
3055 uint32_t gsvs_ring_size,
3056 struct radeon_winsys_bo *gsvs_ring_bo,
3057 uint32_t tess_factor_ring_size,
3058 uint32_t tess_offchip_ring_offset,
3059 uint32_t tess_offchip_ring_size,
3060 struct radeon_winsys_bo *tess_rings_bo)
3061 {
3062 uint32_t *desc = &map[4];
3063
3064 if (esgs_ring_bo) {
3065 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
3066
3067 /* stride 0, num records - size, add tid, swizzle, elsize4,
3068 index stride 64 */
3069 desc[0] = esgs_va;
3070 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
3071 S_008F04_SWIZZLE_ENABLE(true);
3072 desc[2] = esgs_ring_size;
3073 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3074 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3075 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3076 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
3077 S_008F0C_INDEX_STRIDE(3) |
3078 S_008F0C_ADD_TID_ENABLE(1);
3079
3080 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3081 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3082 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3083 S_008F0C_RESOURCE_LEVEL(1);
3084 } else {
3085 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3086 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
3087 S_008F0C_ELEMENT_SIZE(1);
3088 }
3089
3090 /* GS entry for ES->GS ring */
3091 /* stride 0, num records - size, elsize0,
3092 index stride 0 */
3093 desc[4] = esgs_va;
3094 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32);
3095 desc[6] = esgs_ring_size;
3096 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3097 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3098 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3099 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3100
3101 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3102 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3103 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3104 S_008F0C_RESOURCE_LEVEL(1);
3105 } else {
3106 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3107 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3108 }
3109 }
3110
3111 desc += 8;
3112
3113 if (gsvs_ring_bo) {
3114 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
3115
3116 /* VS entry for GS->VS ring */
3117 /* stride 0, num records - size, elsize0,
3118 index stride 0 */
3119 desc[0] = gsvs_va;
3120 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32);
3121 desc[2] = gsvs_ring_size;
3122 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3123 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3124 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3125 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3126
3127 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3128 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3129 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3130 S_008F0C_RESOURCE_LEVEL(1);
3131 } else {
3132 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3133 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3134 }
3135
3136 /* stride gsvs_itemsize, num records 64
3137 elsize 4, index stride 16 */
3138 /* shader will patch stride and desc[2] */
3139 desc[4] = gsvs_va;
3140 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32) |
3141 S_008F04_SWIZZLE_ENABLE(1);
3142 desc[6] = 0;
3143 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3144 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3145 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3146 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
3147 S_008F0C_INDEX_STRIDE(1) |
3148 S_008F0C_ADD_TID_ENABLE(true);
3149
3150 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3151 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3152 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3153 S_008F0C_RESOURCE_LEVEL(1);
3154 } else {
3155 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3156 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
3157 S_008F0C_ELEMENT_SIZE(1);
3158 }
3159
3160 }
3161
3162 desc += 8;
3163
3164 if (tess_rings_bo) {
3165 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
3166 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
3167
3168 desc[0] = tess_va;
3169 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32);
3170 desc[2] = tess_factor_ring_size;
3171 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3172 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3173 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3174 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3175
3176 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3177 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3178 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3179 S_008F0C_RESOURCE_LEVEL(1);
3180 } else {
3181 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3182 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3183 }
3184
3185 desc[4] = tess_offchip_va;
3186 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32);
3187 desc[6] = tess_offchip_ring_size;
3188 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3189 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3190 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3191 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3192
3193 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3194 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3195 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3196 S_008F0C_RESOURCE_LEVEL(1);
3197 } else {
3198 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3199 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3200 }
3201 }
3202
3203 desc += 8;
3204
3205 if (add_sample_positions) {
3206 /* add sample positions after all rings */
3207 memcpy(desc, queue->device->sample_locations_1x, 8);
3208 desc += 2;
3209 memcpy(desc, queue->device->sample_locations_2x, 16);
3210 desc += 4;
3211 memcpy(desc, queue->device->sample_locations_4x, 32);
3212 desc += 8;
3213 memcpy(desc, queue->device->sample_locations_8x, 64);
3214 }
3215 }
3216
3217 static unsigned
3218 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
3219 {
3220 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 &&
3221 device->physical_device->rad_info.family != CHIP_CARRIZO &&
3222 device->physical_device->rad_info.family != CHIP_STONEY;
3223 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
3224 unsigned max_offchip_buffers;
3225 unsigned offchip_granularity;
3226 unsigned hs_offchip_param;
3227
3228 /*
3229 * Per RadeonSI:
3230 * This must be one less than the maximum number due to a hw limitation.
3231 * Various hardware bugs need thGFX7
3232 *
3233 * Per AMDVLK:
3234 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
3235 * Gfx7 should limit max_offchip_buffers to 508
3236 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
3237 *
3238 * Follow AMDVLK here.
3239 */
3240 if (device->physical_device->rad_info.chip_class >= GFX10) {
3241 max_offchip_buffers_per_se = 256;
3242 } else if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
3243 device->physical_device->rad_info.chip_class == GFX7 ||
3244 device->physical_device->rad_info.chip_class == GFX6)
3245 --max_offchip_buffers_per_se;
3246
3247 max_offchip_buffers = max_offchip_buffers_per_se *
3248 device->physical_device->rad_info.max_se;
3249
3250 /* Hawaii has a bug with offchip buffers > 256 that can be worked
3251 * around by setting 4K granularity.
3252 */
3253 if (device->tess_offchip_block_dw_size == 4096) {
3254 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
3255 offchip_granularity = V_03093C_X_4K_DWORDS;
3256 } else {
3257 assert(device->tess_offchip_block_dw_size == 8192);
3258 offchip_granularity = V_03093C_X_8K_DWORDS;
3259 }
3260
3261 switch (device->physical_device->rad_info.chip_class) {
3262 case GFX6:
3263 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
3264 break;
3265 case GFX7:
3266 case GFX8:
3267 case GFX9:
3268 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
3269 break;
3270 case GFX10:
3271 break;
3272 default:
3273 break;
3274 }
3275
3276 *max_offchip_buffers_p = max_offchip_buffers;
3277 if (device->physical_device->rad_info.chip_class >= GFX10_3) {
3278 hs_offchip_param = S_03093C_OFFCHIP_BUFFERING_GFX103(max_offchip_buffers - 1) |
3279 S_03093C_OFFCHIP_GRANULARITY_GFX103(offchip_granularity);
3280 } else if (device->physical_device->rad_info.chip_class >= GFX7) {
3281 if (device->physical_device->rad_info.chip_class >= GFX8)
3282 --max_offchip_buffers;
3283 hs_offchip_param =
3284 S_03093C_OFFCHIP_BUFFERING_GFX7(max_offchip_buffers) |
3285 S_03093C_OFFCHIP_GRANULARITY_GFX7(offchip_granularity);
3286 } else {
3287 hs_offchip_param =
3288 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
3289 }
3290 return hs_offchip_param;
3291 }
3292
3293 static void
3294 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3295 struct radeon_winsys_bo *esgs_ring_bo,
3296 uint32_t esgs_ring_size,
3297 struct radeon_winsys_bo *gsvs_ring_bo,
3298 uint32_t gsvs_ring_size)
3299 {
3300 if (!esgs_ring_bo && !gsvs_ring_bo)
3301 return;
3302
3303 if (esgs_ring_bo)
3304 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
3305
3306 if (gsvs_ring_bo)
3307 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
3308
3309 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
3310 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
3311 radeon_emit(cs, esgs_ring_size >> 8);
3312 radeon_emit(cs, gsvs_ring_size >> 8);
3313 } else {
3314 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
3315 radeon_emit(cs, esgs_ring_size >> 8);
3316 radeon_emit(cs, gsvs_ring_size >> 8);
3317 }
3318 }
3319
3320 static void
3321 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3322 unsigned hs_offchip_param, unsigned tf_ring_size,
3323 struct radeon_winsys_bo *tess_rings_bo)
3324 {
3325 uint64_t tf_va;
3326
3327 if (!tess_rings_bo)
3328 return;
3329
3330 tf_va = radv_buffer_get_va(tess_rings_bo);
3331
3332 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
3333
3334 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
3335 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
3336 S_030938_SIZE(tf_ring_size / 4));
3337 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
3338 tf_va >> 8);
3339
3340 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3341 radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3342 S_030984_BASE_HI(tf_va >> 40));
3343 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
3344 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
3345 S_030944_BASE_HI(tf_va >> 40));
3346 }
3347 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
3348 hs_offchip_param);
3349 } else {
3350 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
3351 S_008988_SIZE(tf_ring_size / 4));
3352 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
3353 tf_va >> 8);
3354 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3355 hs_offchip_param);
3356 }
3357 }
3358
3359 static void
3360 radv_emit_graphics_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3361 uint32_t size_per_wave, uint32_t waves,
3362 struct radeon_winsys_bo *scratch_bo)
3363 {
3364 if (queue->queue_family_index != RADV_QUEUE_GENERAL)
3365 return;
3366
3367 if (!scratch_bo)
3368 return;
3369
3370 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
3371
3372 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
3373 S_0286E8_WAVES(waves) |
3374 S_0286E8_WAVESIZE(round_up_u32(size_per_wave, 1024)));
3375 }
3376
3377 static void
3378 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3379 uint32_t size_per_wave, uint32_t waves,
3380 struct radeon_winsys_bo *compute_scratch_bo)
3381 {
3382 uint64_t scratch_va;
3383
3384 if (!compute_scratch_bo)
3385 return;
3386
3387 scratch_va = radv_buffer_get_va(compute_scratch_bo);
3388
3389 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
3390
3391 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
3392 radeon_emit(cs, scratch_va);
3393 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
3394 S_008F04_SWIZZLE_ENABLE(1));
3395
3396 radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
3397 S_00B860_WAVES(waves) |
3398 S_00B860_WAVESIZE(round_up_u32(size_per_wave, 1024)));
3399 }
3400
3401 static void
3402 radv_emit_global_shader_pointers(struct radv_queue *queue,
3403 struct radeon_cmdbuf *cs,
3404 struct radeon_winsys_bo *descriptor_bo)
3405 {
3406 uint64_t va;
3407
3408 if (!descriptor_bo)
3409 return;
3410
3411 va = radv_buffer_get_va(descriptor_bo);
3412
3413 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
3414
3415 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3416 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3417 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3418 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
3419 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
3420
3421 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3422 radv_emit_shader_pointer(queue->device, cs, regs[i],
3423 va, true);
3424 }
3425 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
3426 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3427 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3428 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
3429 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
3430
3431 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3432 radv_emit_shader_pointer(queue->device, cs, regs[i],
3433 va, true);
3434 }
3435 } else {
3436 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3437 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3438 R_00B230_SPI_SHADER_USER_DATA_GS_0,
3439 R_00B330_SPI_SHADER_USER_DATA_ES_0,
3440 R_00B430_SPI_SHADER_USER_DATA_HS_0,
3441 R_00B530_SPI_SHADER_USER_DATA_LS_0};
3442
3443 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3444 radv_emit_shader_pointer(queue->device, cs, regs[i],
3445 va, true);
3446 }
3447 }
3448 }
3449
3450 static void
3451 radv_emit_trap_handler(struct radv_queue *queue,
3452 struct radeon_cmdbuf *cs,
3453 struct radeon_winsys_bo *tma_bo)
3454 {
3455 struct radv_device *device = queue->device;
3456 struct radeon_winsys_bo *tba_bo;
3457 uint64_t tba_va, tma_va;
3458
3459 if (!device->trap_handler_shader || !tma_bo)
3460 return;
3461
3462 tba_bo = device->trap_handler_shader->bo;
3463
3464 tba_va = radv_buffer_get_va(tba_bo) + device->trap_handler_shader->bo_offset;
3465 tma_va = radv_buffer_get_va(tma_bo);
3466
3467 radv_cs_add_buffer(queue->device->ws, cs, tba_bo);
3468 radv_cs_add_buffer(queue->device->ws, cs, tma_bo);
3469
3470 if (queue->queue_family_index == RADV_QUEUE_GENERAL) {
3471 uint32_t regs[] = {R_00B000_SPI_SHADER_TBA_LO_PS,
3472 R_00B100_SPI_SHADER_TBA_LO_VS,
3473 R_00B200_SPI_SHADER_TBA_LO_GS,