radv/winsys: Add binary syncobj ABI changes for timeline semaphores.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "dirent.h"
29 #include <errno.h>
30 #include <fcntl.h>
31 #include <linux/audit.h>
32 #include <linux/bpf.h>
33 #include <linux/filter.h>
34 #include <linux/seccomp.h>
35 #include <linux/unistd.h>
36 #include <stdbool.h>
37 #include <stddef.h>
38 #include <stdio.h>
39 #include <string.h>
40 #include <sys/prctl.h>
41 #include <sys/wait.h>
42 #include <unistd.h>
43 #include <fcntl.h>
44
45 #include "radv_debug.h"
46 #include "radv_private.h"
47 #include "radv_shader.h"
48 #include "radv_cs.h"
49 #include "util/disk_cache.h"
50 #include "vk_util.h"
51 #include <xf86drm.h>
52 #include <amdgpu.h>
53 #include "drm-uapi/amdgpu_drm.h"
54 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
55 #include "winsys/null/radv_null_winsys_public.h"
56 #include "ac_llvm_util.h"
57 #include "vk_format.h"
58 #include "sid.h"
59 #include "git_sha1.h"
60 #include "util/build_id.h"
61 #include "util/debug.h"
62 #include "util/mesa-sha1.h"
63 #include "util/timespec.h"
64 #include "util/u_atomic.h"
65 #include "compiler/glsl_types.h"
66 #include "util/driconf.h"
67
68 static struct radv_timeline_point *
69 radv_timeline_find_point_at_least_locked(struct radv_device *device,
70 struct radv_timeline *timeline,
71 uint64_t p);
72
73 static struct radv_timeline_point *
74 radv_timeline_add_point_locked(struct radv_device *device,
75 struct radv_timeline *timeline,
76 uint64_t p);
77
78 static void
79 radv_timeline_trigger_waiters_locked(struct radv_timeline *timeline,
80 struct list_head *processing_list);
81
82 static
83 void radv_destroy_semaphore_part(struct radv_device *device,
84 struct radv_semaphore_part *part);
85
86 static int
87 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
88 {
89 struct mesa_sha1 ctx;
90 unsigned char sha1[20];
91 unsigned ptr_size = sizeof(void*);
92
93 memset(uuid, 0, VK_UUID_SIZE);
94 _mesa_sha1_init(&ctx);
95
96 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
97 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
98 return -1;
99
100 _mesa_sha1_update(&ctx, &family, sizeof(family));
101 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
102 _mesa_sha1_final(&ctx, sha1);
103
104 memcpy(uuid, sha1, VK_UUID_SIZE);
105 return 0;
106 }
107
108 static void
109 radv_get_driver_uuid(void *uuid)
110 {
111 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
112 }
113
114 static void
115 radv_get_device_uuid(struct radeon_info *info, void *uuid)
116 {
117 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
118 }
119
120 static uint64_t
121 radv_get_visible_vram_size(struct radv_physical_device *device)
122 {
123 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
124 }
125
126 static uint64_t
127 radv_get_vram_size(struct radv_physical_device *device)
128 {
129 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
130 }
131
132 static void
133 radv_physical_device_init_mem_types(struct radv_physical_device *device)
134 {
135 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
136 uint64_t vram_size = radv_get_vram_size(device);
137 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
138 device->memory_properties.memoryHeapCount = 0;
139 if (vram_size > 0) {
140 vram_index = device->memory_properties.memoryHeapCount++;
141 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
142 .size = vram_size,
143 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
144 };
145 }
146
147 if (device->rad_info.gart_size > 0) {
148 gart_index = device->memory_properties.memoryHeapCount++;
149 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
150 .size = device->rad_info.gart_size,
151 .flags = 0,
152 };
153 }
154
155 if (visible_vram_size) {
156 visible_vram_index = device->memory_properties.memoryHeapCount++;
157 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
158 .size = visible_vram_size,
159 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
160 };
161 }
162
163 unsigned type_count = 0;
164
165 if (vram_index >= 0 || visible_vram_index >= 0) {
166 device->memory_domains[type_count] = RADEON_DOMAIN_VRAM;
167 device->memory_flags[type_count] = RADEON_FLAG_NO_CPU_ACCESS;
168 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
169 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
170 .heapIndex = vram_index >= 0 ? vram_index : visible_vram_index,
171 };
172 }
173
174 if (gart_index >= 0) {
175 device->memory_domains[type_count] = RADEON_DOMAIN_GTT;
176 device->memory_flags[type_count] = RADEON_FLAG_GTT_WC | RADEON_FLAG_CPU_ACCESS;
177 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
178 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
179 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
180 .heapIndex = gart_index,
181 };
182 }
183 if (visible_vram_index >= 0) {
184 device->memory_domains[type_count] = RADEON_DOMAIN_VRAM;
185 device->memory_flags[type_count] = RADEON_FLAG_CPU_ACCESS;
186 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
187 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
188 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
189 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
190 .heapIndex = visible_vram_index,
191 };
192 }
193
194 if (gart_index >= 0) {
195 device->memory_domains[type_count] = RADEON_DOMAIN_GTT;
196 device->memory_flags[type_count] = RADEON_FLAG_CPU_ACCESS;
197 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
198 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
199 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
200 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
201 .heapIndex = gart_index,
202 };
203 }
204 device->memory_properties.memoryTypeCount = type_count;
205
206 if (device->rad_info.has_l2_uncached) {
207 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
208 VkMemoryType mem_type = device->memory_properties.memoryTypes[i];
209
210 if ((mem_type.propertyFlags & (VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
211 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT)) ||
212 mem_type.propertyFlags == VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT) {
213
214 VkMemoryPropertyFlags property_flags = mem_type.propertyFlags |
215 VK_MEMORY_PROPERTY_DEVICE_COHERENT_BIT_AMD |
216 VK_MEMORY_PROPERTY_DEVICE_UNCACHED_BIT_AMD;
217
218 device->memory_domains[type_count] = device->memory_domains[i];
219 device->memory_flags[type_count] = device->memory_flags[i] | RADEON_FLAG_VA_UNCACHED;
220 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
221 .propertyFlags = property_flags,
222 .heapIndex = mem_type.heapIndex,
223 };
224 }
225 }
226 device->memory_properties.memoryTypeCount = type_count;
227 }
228 }
229
230 static const char *
231 radv_get_compiler_string(struct radv_physical_device *pdevice)
232 {
233 if (!pdevice->use_llvm) {
234 /* Some games like SotTR apply shader workarounds if the LLVM
235 * version is too old or if the LLVM version string is
236 * missing. This gives 2-5% performance with SotTR and ACO.
237 */
238 if (driQueryOptionb(&pdevice->instance->dri_options,
239 "radv_report_llvm9_version_string")) {
240 return "ACO/LLVM 9.0.1";
241 }
242
243 return "ACO";
244 }
245
246 return "LLVM " MESA_LLVM_VERSION_STRING;
247 }
248
249 static VkResult
250 radv_physical_device_try_create(struct radv_instance *instance,
251 drmDevicePtr drm_device,
252 struct radv_physical_device **device_out)
253 {
254 VkResult result;
255 int fd = -1;
256 int master_fd = -1;
257
258 if (drm_device) {
259 const char *path = drm_device->nodes[DRM_NODE_RENDER];
260 drmVersionPtr version;
261
262 fd = open(path, O_RDWR | O_CLOEXEC);
263 if (fd < 0) {
264 if (instance->debug_flags & RADV_DEBUG_STARTUP)
265 radv_logi("Could not open device '%s'", path);
266
267 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
268 }
269
270 version = drmGetVersion(fd);
271 if (!version) {
272 close(fd);
273
274 if (instance->debug_flags & RADV_DEBUG_STARTUP)
275 radv_logi("Could not get the kernel driver version for device '%s'", path);
276
277 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
278 "failed to get version %s: %m", path);
279 }
280
281 if (strcmp(version->name, "amdgpu")) {
282 drmFreeVersion(version);
283 close(fd);
284
285 if (instance->debug_flags & RADV_DEBUG_STARTUP)
286 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
287
288 return VK_ERROR_INCOMPATIBLE_DRIVER;
289 }
290 drmFreeVersion(version);
291
292 if (instance->debug_flags & RADV_DEBUG_STARTUP)
293 radv_logi("Found compatible device '%s'.", path);
294 }
295
296 struct radv_physical_device *device =
297 vk_zalloc2(&instance->alloc, NULL, sizeof(*device), 8,
298 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
299 if (!device) {
300 result = vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
301 goto fail_fd;
302 }
303
304 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
305 device->instance = instance;
306
307 if (drm_device) {
308 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
309 instance->perftest_flags);
310 } else {
311 device->ws = radv_null_winsys_create();
312 }
313
314 if (!device->ws) {
315 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
316 "failed to initialize winsys");
317 goto fail_alloc;
318 }
319
320 if (drm_device && instance->enabled_extensions.KHR_display) {
321 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
322 if (master_fd >= 0) {
323 uint32_t accel_working = 0;
324 struct drm_amdgpu_info request = {
325 .return_pointer = (uintptr_t)&accel_working,
326 .return_size = sizeof(accel_working),
327 .query = AMDGPU_INFO_ACCEL_WORKING
328 };
329
330 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
331 close(master_fd);
332 master_fd = -1;
333 }
334 }
335 }
336
337 device->master_fd = master_fd;
338 device->local_fd = fd;
339 device->ws->query_info(device->ws, &device->rad_info);
340
341 device->use_llvm = instance->debug_flags & RADV_DEBUG_LLVM;
342
343 snprintf(device->name, sizeof(device->name),
344 "AMD RADV %s (%s)",
345 device->rad_info.name, radv_get_compiler_string(device));
346
347 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
348 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
349 "cannot generate UUID");
350 goto fail_wsi;
351 }
352
353 /* These flags affect shader compilation. */
354 uint64_t shader_env_flags = (device->use_llvm ? 0 : 0x2);
355
356 /* The gpu id is already embedded in the uuid so we just pass "radv"
357 * when creating the cache.
358 */
359 char buf[VK_UUID_SIZE * 2 + 1];
360 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
361 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
362
363 if (device->rad_info.chip_class < GFX8 || !device->use_llvm)
364 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
365
366 radv_get_driver_uuid(&device->driver_uuid);
367 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
368
369 device->out_of_order_rast_allowed = device->rad_info.has_out_of_order_rast &&
370 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
371
372 device->dcc_msaa_allowed =
373 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
374
375 device->use_ngg = device->rad_info.chip_class >= GFX10 &&
376 device->rad_info.family != CHIP_NAVI14 &&
377 !(device->instance->debug_flags & RADV_DEBUG_NO_NGG);
378
379 /* TODO: Implement NGG GS with ACO. */
380 device->use_ngg_gs = device->use_ngg && device->use_llvm;
381 device->use_ngg_streamout = false;
382
383 /* Determine the number of threads per wave for all stages. */
384 device->cs_wave_size = 64;
385 device->ps_wave_size = 64;
386 device->ge_wave_size = 64;
387
388 if (device->rad_info.chip_class >= GFX10) {
389 if (device->instance->perftest_flags & RADV_PERFTEST_CS_WAVE_32)
390 device->cs_wave_size = 32;
391
392 /* For pixel shaders, wave64 is recommanded. */
393 if (device->instance->perftest_flags & RADV_PERFTEST_PS_WAVE_32)
394 device->ps_wave_size = 32;
395
396 if (device->instance->perftest_flags & RADV_PERFTEST_GE_WAVE_32)
397 device->ge_wave_size = 32;
398 }
399
400 radv_physical_device_init_mem_types(device);
401
402 radv_physical_device_get_supported_extensions(device,
403 &device->supported_extensions);
404
405 if (drm_device)
406 device->bus_info = *drm_device->businfo.pci;
407
408 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
409 ac_print_gpu_info(&device->rad_info);
410
411 /* The WSI is structured as a layer on top of the driver, so this has
412 * to be the last part of initialization (at least until we get other
413 * semi-layers).
414 */
415 result = radv_init_wsi(device);
416 if (result != VK_SUCCESS) {
417 vk_error(instance, result);
418 goto fail_disk_cache;
419 }
420
421 *device_out = device;
422
423 return VK_SUCCESS;
424
425 fail_disk_cache:
426 disk_cache_destroy(device->disk_cache);
427 fail_wsi:
428 device->ws->destroy(device->ws);
429 fail_alloc:
430 vk_free(&instance->alloc, device);
431 fail_fd:
432 if (fd != -1)
433 close(fd);
434 if (master_fd != -1)
435 close(master_fd);
436 return result;
437 }
438
439 static void
440 radv_physical_device_destroy(struct radv_physical_device *device)
441 {
442 radv_finish_wsi(device);
443 device->ws->destroy(device->ws);
444 disk_cache_destroy(device->disk_cache);
445 close(device->local_fd);
446 if (device->master_fd != -1)
447 close(device->master_fd);
448 vk_free(&device->instance->alloc, device);
449 }
450
451 static void *
452 default_alloc_func(void *pUserData, size_t size, size_t align,
453 VkSystemAllocationScope allocationScope)
454 {
455 return malloc(size);
456 }
457
458 static void *
459 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
460 size_t align, VkSystemAllocationScope allocationScope)
461 {
462 return realloc(pOriginal, size);
463 }
464
465 static void
466 default_free_func(void *pUserData, void *pMemory)
467 {
468 free(pMemory);
469 }
470
471 static const VkAllocationCallbacks default_alloc = {
472 .pUserData = NULL,
473 .pfnAllocation = default_alloc_func,
474 .pfnReallocation = default_realloc_func,
475 .pfnFree = default_free_func,
476 };
477
478 static const struct debug_control radv_debug_options[] = {
479 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
480 {"nodcc", RADV_DEBUG_NO_DCC},
481 {"shaders", RADV_DEBUG_DUMP_SHADERS},
482 {"nocache", RADV_DEBUG_NO_CACHE},
483 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
484 {"nohiz", RADV_DEBUG_NO_HIZ},
485 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
486 {"allbos", RADV_DEBUG_ALL_BOS},
487 {"noibs", RADV_DEBUG_NO_IBS},
488 {"spirv", RADV_DEBUG_DUMP_SPIRV},
489 {"vmfaults", RADV_DEBUG_VM_FAULTS},
490 {"zerovram", RADV_DEBUG_ZERO_VRAM},
491 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
492 {"preoptir", RADV_DEBUG_PREOPTIR},
493 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
494 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
495 {"info", RADV_DEBUG_INFO},
496 {"errors", RADV_DEBUG_ERRORS},
497 {"startup", RADV_DEBUG_STARTUP},
498 {"checkir", RADV_DEBUG_CHECKIR},
499 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
500 {"nobinning", RADV_DEBUG_NOBINNING},
501 {"nongg", RADV_DEBUG_NO_NGG},
502 {"allentrypoints", RADV_DEBUG_ALL_ENTRYPOINTS},
503 {"metashaders", RADV_DEBUG_DUMP_META_SHADERS},
504 {"nomemorycache", RADV_DEBUG_NO_MEMORY_CACHE},
505 {"llvm", RADV_DEBUG_LLVM},
506 {NULL, 0}
507 };
508
509 const char *
510 radv_get_debug_option_name(int id)
511 {
512 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
513 return radv_debug_options[id].string;
514 }
515
516 static const struct debug_control radv_perftest_options[] = {
517 {"localbos", RADV_PERFTEST_LOCAL_BOS},
518 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
519 {"bolist", RADV_PERFTEST_BO_LIST},
520 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
521 {"cswave32", RADV_PERFTEST_CS_WAVE_32},
522 {"pswave32", RADV_PERFTEST_PS_WAVE_32},
523 {"gewave32", RADV_PERFTEST_GE_WAVE_32},
524 {"dfsm", RADV_PERFTEST_DFSM},
525 {NULL, 0}
526 };
527
528 const char *
529 radv_get_perftest_option_name(int id)
530 {
531 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
532 return radv_perftest_options[id].string;
533 }
534
535 static void
536 radv_handle_per_app_options(struct radv_instance *instance,
537 const VkApplicationInfo *info)
538 {
539 const char *name = info ? info->pApplicationName : NULL;
540 const char *engine_name = info ? info->pEngineName : NULL;
541
542 if (name) {
543 if (!strcmp(name, "DOOM_VFR")) {
544 /* Work around a Doom VFR game bug */
545 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
546 } else if (!strcmp(name, "Fledge")) {
547 /*
548 * Zero VRAM for "The Surge 2"
549 *
550 * This avoid a hang when when rendering any level. Likely
551 * uninitialized data in an indirect draw.
552 */
553 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
554 } else if (!strcmp(name, "No Man's Sky")) {
555 /* Work around a NMS game bug */
556 instance->debug_flags |= RADV_DEBUG_DISCARD_TO_DEMOTE;
557 } else if (!strcmp(name, "DOOMEternal")) {
558 /* Zero VRAM for Doom Eternal to fix rendering issues. */
559 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
560 } else if (!strcmp(name, "Red Dead Redemption 2")) {
561 /* Work around a RDR2 game bug */
562 instance->debug_flags |= RADV_DEBUG_DISCARD_TO_DEMOTE;
563 }
564 }
565
566 if (engine_name) {
567 if (!strcmp(engine_name, "vkd3d")) {
568 /* Zero VRAM for all VKD3D (DX12->VK) games to fix
569 * rendering issues.
570 */
571 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
572 } else if (!strcmp(engine_name, "Quantic Dream Engine")) {
573 /* Fix various artifacts in Detroit: Become Human */
574 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM |
575 RADV_DEBUG_DISCARD_TO_DEMOTE;
576 }
577 }
578
579 instance->enable_mrt_output_nan_fixup =
580 driQueryOptionb(&instance->dri_options,
581 "radv_enable_mrt_output_nan_fixup");
582
583 if (driQueryOptionb(&instance->dri_options, "radv_no_dynamic_bounds"))
584 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
585 }
586
587 static const char radv_dri_options_xml[] =
588 DRI_CONF_BEGIN
589 DRI_CONF_SECTION_PERFORMANCE
590 DRI_CONF_ADAPTIVE_SYNC("true")
591 DRI_CONF_VK_X11_OVERRIDE_MIN_IMAGE_COUNT(0)
592 DRI_CONF_VK_X11_STRICT_IMAGE_COUNT("false")
593 DRI_CONF_VK_X11_ENSURE_MIN_IMAGE_COUNT("false")
594 DRI_CONF_RADV_REPORT_LLVM9_VERSION_STRING("false")
595 DRI_CONF_RADV_ENABLE_MRT_OUTPUT_NAN_FIXUP("false")
596 DRI_CONF_RADV_NO_DYNAMIC_BOUNDS("false")
597 DRI_CONF_SECTION_END
598
599 DRI_CONF_SECTION_DEBUG
600 DRI_CONF_VK_WSI_FORCE_BGRA8_UNORM_FIRST("false")
601 DRI_CONF_SECTION_END
602 DRI_CONF_END;
603
604 static void radv_init_dri_options(struct radv_instance *instance)
605 {
606 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
607 driParseConfigFiles(&instance->dri_options,
608 &instance->available_dri_options,
609 0, "radv", NULL,
610 instance->engineName,
611 instance->engineVersion);
612 }
613
614 VkResult radv_CreateInstance(
615 const VkInstanceCreateInfo* pCreateInfo,
616 const VkAllocationCallbacks* pAllocator,
617 VkInstance* pInstance)
618 {
619 struct radv_instance *instance;
620 VkResult result;
621
622 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
623 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
624 if (!instance)
625 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
626
627 vk_object_base_init(NULL, &instance->base, VK_OBJECT_TYPE_INSTANCE);
628
629 if (pAllocator)
630 instance->alloc = *pAllocator;
631 else
632 instance->alloc = default_alloc;
633
634 if (pCreateInfo->pApplicationInfo) {
635 const VkApplicationInfo *app = pCreateInfo->pApplicationInfo;
636
637 instance->engineName =
638 vk_strdup(&instance->alloc, app->pEngineName,
639 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
640 instance->engineVersion = app->engineVersion;
641 instance->apiVersion = app->apiVersion;
642 }
643
644 if (instance->apiVersion == 0)
645 instance->apiVersion = VK_API_VERSION_1_0;
646
647 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
648 radv_debug_options);
649
650 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
651 radv_perftest_options);
652
653 if (instance->debug_flags & RADV_DEBUG_STARTUP)
654 radv_logi("Created an instance");
655
656 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
657 int idx;
658 for (idx = 0; idx < RADV_INSTANCE_EXTENSION_COUNT; idx++) {
659 if (!strcmp(pCreateInfo->ppEnabledExtensionNames[i],
660 radv_instance_extensions[idx].extensionName))
661 break;
662 }
663
664 if (idx >= RADV_INSTANCE_EXTENSION_COUNT ||
665 !radv_instance_extensions_supported.extensions[idx]) {
666 vk_object_base_finish(&instance->base);
667 vk_free2(&default_alloc, pAllocator, instance);
668 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
669 }
670
671 instance->enabled_extensions.extensions[idx] = true;
672 }
673
674 bool unchecked = instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS;
675
676 for (unsigned i = 0; i < ARRAY_SIZE(instance->dispatch.entrypoints); i++) {
677 /* Vulkan requires that entrypoints for extensions which have
678 * not been enabled must not be advertised.
679 */
680 if (!unchecked &&
681 !radv_instance_entrypoint_is_enabled(i, instance->apiVersion,
682 &instance->enabled_extensions)) {
683 instance->dispatch.entrypoints[i] = NULL;
684 } else {
685 instance->dispatch.entrypoints[i] =
686 radv_instance_dispatch_table.entrypoints[i];
687 }
688 }
689
690 for (unsigned i = 0; i < ARRAY_SIZE(instance->physical_device_dispatch.entrypoints); i++) {
691 /* Vulkan requires that entrypoints for extensions which have
692 * not been enabled must not be advertised.
693 */
694 if (!unchecked &&
695 !radv_physical_device_entrypoint_is_enabled(i, instance->apiVersion,
696 &instance->enabled_extensions)) {
697 instance->physical_device_dispatch.entrypoints[i] = NULL;
698 } else {
699 instance->physical_device_dispatch.entrypoints[i] =
700 radv_physical_device_dispatch_table.entrypoints[i];
701 }
702 }
703
704 for (unsigned i = 0; i < ARRAY_SIZE(instance->device_dispatch.entrypoints); i++) {
705 /* Vulkan requires that entrypoints for extensions which have
706 * not been enabled must not be advertised.
707 */
708 if (!unchecked &&
709 !radv_device_entrypoint_is_enabled(i, instance->apiVersion,
710 &instance->enabled_extensions, NULL)) {
711 instance->device_dispatch.entrypoints[i] = NULL;
712 } else {
713 instance->device_dispatch.entrypoints[i] =
714 radv_device_dispatch_table.entrypoints[i];
715 }
716 }
717
718 instance->physical_devices_enumerated = false;
719 list_inithead(&instance->physical_devices);
720
721 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
722 if (result != VK_SUCCESS) {
723 vk_object_base_finish(&instance->base);
724 vk_free2(&default_alloc, pAllocator, instance);
725 return vk_error(instance, result);
726 }
727
728 glsl_type_singleton_init_or_ref();
729
730 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
731
732 radv_init_dri_options(instance);
733 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
734
735 *pInstance = radv_instance_to_handle(instance);
736
737 return VK_SUCCESS;
738 }
739
740 void radv_DestroyInstance(
741 VkInstance _instance,
742 const VkAllocationCallbacks* pAllocator)
743 {
744 RADV_FROM_HANDLE(radv_instance, instance, _instance);
745
746 if (!instance)
747 return;
748
749 list_for_each_entry_safe(struct radv_physical_device, pdevice,
750 &instance->physical_devices, link) {
751 radv_physical_device_destroy(pdevice);
752 }
753
754 vk_free(&instance->alloc, instance->engineName);
755
756 VG(VALGRIND_DESTROY_MEMPOOL(instance));
757
758 glsl_type_singleton_decref();
759
760 driDestroyOptionCache(&instance->dri_options);
761 driDestroyOptionInfo(&instance->available_dri_options);
762
763 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
764
765 vk_object_base_finish(&instance->base);
766 vk_free(&instance->alloc, instance);
767 }
768
769 static VkResult
770 radv_enumerate_physical_devices(struct radv_instance *instance)
771 {
772 if (instance->physical_devices_enumerated)
773 return VK_SUCCESS;
774
775 instance->physical_devices_enumerated = true;
776
777 /* TODO: Check for more devices ? */
778 drmDevicePtr devices[8];
779 VkResult result = VK_SUCCESS;
780 int max_devices;
781
782 if (getenv("RADV_FORCE_FAMILY")) {
783 /* When RADV_FORCE_FAMILY is set, the driver creates a nul
784 * device that allows to test the compiler without having an
785 * AMDGPU instance.
786 */
787 struct radv_physical_device *pdevice;
788
789 result = radv_physical_device_try_create(instance, NULL, &pdevice);
790 if (result != VK_SUCCESS)
791 return result;
792
793 list_addtail(&pdevice->link, &instance->physical_devices);
794 return VK_SUCCESS;
795 }
796
797 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
798
799 if (instance->debug_flags & RADV_DEBUG_STARTUP)
800 radv_logi("Found %d drm nodes", max_devices);
801
802 if (max_devices < 1)
803 return vk_error(instance, VK_SUCCESS);
804
805 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
806 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
807 devices[i]->bustype == DRM_BUS_PCI &&
808 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
809
810 struct radv_physical_device *pdevice;
811 result = radv_physical_device_try_create(instance, devices[i],
812 &pdevice);
813 /* Incompatible DRM device, skip. */
814 if (result == VK_ERROR_INCOMPATIBLE_DRIVER) {
815 result = VK_SUCCESS;
816 continue;
817 }
818
819 /* Error creating the physical device, report the error. */
820 if (result != VK_SUCCESS)
821 break;
822
823 list_addtail(&pdevice->link, &instance->physical_devices);
824 }
825 }
826 drmFreeDevices(devices, max_devices);
827
828 /* If we successfully enumerated any devices, call it success */
829 return result;
830 }
831
832 VkResult radv_EnumeratePhysicalDevices(
833 VkInstance _instance,
834 uint32_t* pPhysicalDeviceCount,
835 VkPhysicalDevice* pPhysicalDevices)
836 {
837 RADV_FROM_HANDLE(radv_instance, instance, _instance);
838 VK_OUTARRAY_MAKE(out, pPhysicalDevices, pPhysicalDeviceCount);
839
840 VkResult result = radv_enumerate_physical_devices(instance);
841 if (result != VK_SUCCESS)
842 return result;
843
844 list_for_each_entry(struct radv_physical_device, pdevice,
845 &instance->physical_devices, link) {
846 vk_outarray_append(&out, i) {
847 *i = radv_physical_device_to_handle(pdevice);
848 }
849 }
850
851 return vk_outarray_status(&out);
852 }
853
854 VkResult radv_EnumeratePhysicalDeviceGroups(
855 VkInstance _instance,
856 uint32_t* pPhysicalDeviceGroupCount,
857 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
858 {
859 RADV_FROM_HANDLE(radv_instance, instance, _instance);
860 VK_OUTARRAY_MAKE(out, pPhysicalDeviceGroupProperties,
861 pPhysicalDeviceGroupCount);
862
863 VkResult result = radv_enumerate_physical_devices(instance);
864 if (result != VK_SUCCESS)
865 return result;
866
867 list_for_each_entry(struct radv_physical_device, pdevice,
868 &instance->physical_devices, link) {
869 vk_outarray_append(&out, p) {
870 p->physicalDeviceCount = 1;
871 memset(p->physicalDevices, 0, sizeof(p->physicalDevices));
872 p->physicalDevices[0] = radv_physical_device_to_handle(pdevice);
873 p->subsetAllocation = false;
874 }
875 }
876
877 return vk_outarray_status(&out);
878 }
879
880 void radv_GetPhysicalDeviceFeatures(
881 VkPhysicalDevice physicalDevice,
882 VkPhysicalDeviceFeatures* pFeatures)
883 {
884 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
885 memset(pFeatures, 0, sizeof(*pFeatures));
886
887 *pFeatures = (VkPhysicalDeviceFeatures) {
888 .robustBufferAccess = true,
889 .fullDrawIndexUint32 = true,
890 .imageCubeArray = true,
891 .independentBlend = true,
892 .geometryShader = true,
893 .tessellationShader = true,
894 .sampleRateShading = true,
895 .dualSrcBlend = true,
896 .logicOp = true,
897 .multiDrawIndirect = true,
898 .drawIndirectFirstInstance = true,
899 .depthClamp = true,
900 .depthBiasClamp = true,
901 .fillModeNonSolid = true,
902 .depthBounds = true,
903 .wideLines = true,
904 .largePoints = true,
905 .alphaToOne = true,
906 .multiViewport = true,
907 .samplerAnisotropy = true,
908 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
909 .textureCompressionASTC_LDR = false,
910 .textureCompressionBC = true,
911 .occlusionQueryPrecise = true,
912 .pipelineStatisticsQuery = true,
913 .vertexPipelineStoresAndAtomics = true,
914 .fragmentStoresAndAtomics = true,
915 .shaderTessellationAndGeometryPointSize = true,
916 .shaderImageGatherExtended = true,
917 .shaderStorageImageExtendedFormats = true,
918 .shaderStorageImageMultisample = true,
919 .shaderUniformBufferArrayDynamicIndexing = true,
920 .shaderSampledImageArrayDynamicIndexing = true,
921 .shaderStorageBufferArrayDynamicIndexing = true,
922 .shaderStorageImageArrayDynamicIndexing = true,
923 .shaderStorageImageReadWithoutFormat = true,
924 .shaderStorageImageWriteWithoutFormat = true,
925 .shaderClipDistance = true,
926 .shaderCullDistance = true,
927 .shaderFloat64 = true,
928 .shaderInt64 = true,
929 .shaderInt16 = true,
930 .sparseBinding = true,
931 .variableMultisampleRate = true,
932 .shaderResourceMinLod = true,
933 .inheritedQueries = true,
934 };
935 }
936
937 static void
938 radv_get_physical_device_features_1_1(struct radv_physical_device *pdevice,
939 VkPhysicalDeviceVulkan11Features *f)
940 {
941 assert(f->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES);
942
943 f->storageBuffer16BitAccess = true;
944 f->uniformAndStorageBuffer16BitAccess = true;
945 f->storagePushConstant16 = true;
946 f->storageInputOutput16 = pdevice->rad_info.has_packed_math_16bit && (LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm);
947 f->multiview = true;
948 f->multiviewGeometryShader = true;
949 f->multiviewTessellationShader = true;
950 f->variablePointersStorageBuffer = true;
951 f->variablePointers = true;
952 f->protectedMemory = false;
953 f->samplerYcbcrConversion = true;
954 f->shaderDrawParameters = true;
955 }
956
957 static void
958 radv_get_physical_device_features_1_2(struct radv_physical_device *pdevice,
959 VkPhysicalDeviceVulkan12Features *f)
960 {
961 assert(f->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES);
962
963 f->samplerMirrorClampToEdge = true;
964 f->drawIndirectCount = true;
965 f->storageBuffer8BitAccess = true;
966 f->uniformAndStorageBuffer8BitAccess = true;
967 f->storagePushConstant8 = true;
968 f->shaderBufferInt64Atomics = LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm;
969 f->shaderSharedInt64Atomics = LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm;
970 f->shaderFloat16 = pdevice->rad_info.has_packed_math_16bit;
971 f->shaderInt8 = true;
972
973 f->descriptorIndexing = true;
974 f->shaderInputAttachmentArrayDynamicIndexing = true;
975 f->shaderUniformTexelBufferArrayDynamicIndexing = true;
976 f->shaderStorageTexelBufferArrayDynamicIndexing = true;
977 f->shaderUniformBufferArrayNonUniformIndexing = true;
978 f->shaderSampledImageArrayNonUniformIndexing = true;
979 f->shaderStorageBufferArrayNonUniformIndexing = true;
980 f->shaderStorageImageArrayNonUniformIndexing = true;
981 f->shaderInputAttachmentArrayNonUniformIndexing = true;
982 f->shaderUniformTexelBufferArrayNonUniformIndexing = true;
983 f->shaderStorageTexelBufferArrayNonUniformIndexing = true;
984 f->descriptorBindingUniformBufferUpdateAfterBind = true;
985 f->descriptorBindingSampledImageUpdateAfterBind = true;
986 f->descriptorBindingStorageImageUpdateAfterBind = true;
987 f->descriptorBindingStorageBufferUpdateAfterBind = true;
988 f->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
989 f->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
990 f->descriptorBindingUpdateUnusedWhilePending = true;
991 f->descriptorBindingPartiallyBound = true;
992 f->descriptorBindingVariableDescriptorCount = true;
993 f->runtimeDescriptorArray = true;
994
995 f->samplerFilterMinmax = true;
996 f->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
997 f->imagelessFramebuffer = true;
998 f->uniformBufferStandardLayout = true;
999 f->shaderSubgroupExtendedTypes = true;
1000 f->separateDepthStencilLayouts = true;
1001 f->hostQueryReset = true;
1002 f->timelineSemaphore = pdevice->rad_info.has_syncobj_wait_for_submit;
1003 f->bufferDeviceAddress = true;
1004 f->bufferDeviceAddressCaptureReplay = false;
1005 f->bufferDeviceAddressMultiDevice = false;
1006 f->vulkanMemoryModel = false;
1007 f->vulkanMemoryModelDeviceScope = false;
1008 f->vulkanMemoryModelAvailabilityVisibilityChains = false;
1009 f->shaderOutputViewportIndex = true;
1010 f->shaderOutputLayer = true;
1011 f->subgroupBroadcastDynamicId = true;
1012 }
1013
1014 void radv_GetPhysicalDeviceFeatures2(
1015 VkPhysicalDevice physicalDevice,
1016 VkPhysicalDeviceFeatures2 *pFeatures)
1017 {
1018 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1019 radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
1020
1021 VkPhysicalDeviceVulkan11Features core_1_1 = {
1022 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES,
1023 };
1024 radv_get_physical_device_features_1_1(pdevice, &core_1_1);
1025
1026 VkPhysicalDeviceVulkan12Features core_1_2 = {
1027 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES,
1028 };
1029 radv_get_physical_device_features_1_2(pdevice, &core_1_2);
1030
1031 #define CORE_FEATURE(major, minor, feature) \
1032 features->feature = core_##major##_##minor.feature
1033
1034 vk_foreach_struct(ext, pFeatures->pNext) {
1035 switch (ext->sType) {
1036 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
1037 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
1038 CORE_FEATURE(1, 1, variablePointersStorageBuffer);
1039 CORE_FEATURE(1, 1, variablePointers);
1040 break;
1041 }
1042 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
1043 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
1044 CORE_FEATURE(1, 1, multiview);
1045 CORE_FEATURE(1, 1, multiviewGeometryShader);
1046 CORE_FEATURE(1, 1, multiviewTessellationShader);
1047 break;
1048 }
1049 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
1050 VkPhysicalDeviceShaderDrawParametersFeatures *features =
1051 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
1052 CORE_FEATURE(1, 1, shaderDrawParameters);
1053 break;
1054 }
1055 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
1056 VkPhysicalDeviceProtectedMemoryFeatures *features =
1057 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
1058 CORE_FEATURE(1, 1, protectedMemory);
1059 break;
1060 }
1061 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
1062 VkPhysicalDevice16BitStorageFeatures *features =
1063 (VkPhysicalDevice16BitStorageFeatures*)ext;
1064 CORE_FEATURE(1, 1, storageBuffer16BitAccess);
1065 CORE_FEATURE(1, 1, uniformAndStorageBuffer16BitAccess);
1066 CORE_FEATURE(1, 1, storagePushConstant16);
1067 CORE_FEATURE(1, 1, storageInputOutput16);
1068 break;
1069 }
1070 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
1071 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
1072 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
1073 CORE_FEATURE(1, 1, samplerYcbcrConversion);
1074 break;
1075 }
1076 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES: {
1077 VkPhysicalDeviceDescriptorIndexingFeatures *features =
1078 (VkPhysicalDeviceDescriptorIndexingFeatures*)ext;
1079 CORE_FEATURE(1, 2, shaderInputAttachmentArrayDynamicIndexing);
1080 CORE_FEATURE(1, 2, shaderUniformTexelBufferArrayDynamicIndexing);
1081 CORE_FEATURE(1, 2, shaderStorageTexelBufferArrayDynamicIndexing);
1082 CORE_FEATURE(1, 2, shaderUniformBufferArrayNonUniformIndexing);
1083 CORE_FEATURE(1, 2, shaderSampledImageArrayNonUniformIndexing);
1084 CORE_FEATURE(1, 2, shaderStorageBufferArrayNonUniformIndexing);
1085 CORE_FEATURE(1, 2, shaderStorageImageArrayNonUniformIndexing);
1086 CORE_FEATURE(1, 2, shaderInputAttachmentArrayNonUniformIndexing);
1087 CORE_FEATURE(1, 2, shaderUniformTexelBufferArrayNonUniformIndexing);
1088 CORE_FEATURE(1, 2, shaderStorageTexelBufferArrayNonUniformIndexing);
1089 CORE_FEATURE(1, 2, descriptorBindingUniformBufferUpdateAfterBind);
1090 CORE_FEATURE(1, 2, descriptorBindingSampledImageUpdateAfterBind);
1091 CORE_FEATURE(1, 2, descriptorBindingStorageImageUpdateAfterBind);
1092 CORE_FEATURE(1, 2, descriptorBindingStorageBufferUpdateAfterBind);
1093 CORE_FEATURE(1, 2, descriptorBindingUniformTexelBufferUpdateAfterBind);
1094 CORE_FEATURE(1, 2, descriptorBindingStorageTexelBufferUpdateAfterBind);
1095 CORE_FEATURE(1, 2, descriptorBindingUpdateUnusedWhilePending);
1096 CORE_FEATURE(1, 2, descriptorBindingPartiallyBound);
1097 CORE_FEATURE(1, 2, descriptorBindingVariableDescriptorCount);
1098 CORE_FEATURE(1, 2, runtimeDescriptorArray);
1099 break;
1100 }
1101 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
1102 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
1103 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
1104 features->conditionalRendering = true;
1105 features->inheritedConditionalRendering = false;
1106 break;
1107 }
1108 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
1109 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
1110 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
1111 features->vertexAttributeInstanceRateDivisor = true;
1112 features->vertexAttributeInstanceRateZeroDivisor = true;
1113 break;
1114 }
1115 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
1116 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
1117 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
1118 features->transformFeedback = true;
1119 features->geometryStreams = !pdevice->use_ngg_streamout;
1120 break;
1121 }
1122 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES: {
1123 VkPhysicalDeviceScalarBlockLayoutFeatures *features =
1124 (VkPhysicalDeviceScalarBlockLayoutFeatures *)ext;
1125 CORE_FEATURE(1, 2, scalarBlockLayout);
1126 break;
1127 }
1128 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
1129 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
1130 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
1131 features->memoryPriority = true;
1132 break;
1133 }
1134 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
1135 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
1136 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
1137 features->bufferDeviceAddress = true;
1138 features->bufferDeviceAddressCaptureReplay = false;
1139 features->bufferDeviceAddressMultiDevice = false;
1140 break;
1141 }
1142 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES: {
1143 VkPhysicalDeviceBufferDeviceAddressFeatures *features =
1144 (VkPhysicalDeviceBufferDeviceAddressFeatures *)ext;
1145 CORE_FEATURE(1, 2, bufferDeviceAddress);
1146 CORE_FEATURE(1, 2, bufferDeviceAddressCaptureReplay);
1147 CORE_FEATURE(1, 2, bufferDeviceAddressMultiDevice);
1148 break;
1149 }
1150 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
1151 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
1152 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
1153 features->depthClipEnable = true;
1154 break;
1155 }
1156 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES: {
1157 VkPhysicalDeviceHostQueryResetFeatures *features =
1158 (VkPhysicalDeviceHostQueryResetFeatures *)ext;
1159 CORE_FEATURE(1, 2, hostQueryReset);
1160 break;
1161 }
1162 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES: {
1163 VkPhysicalDevice8BitStorageFeatures *features =
1164 (VkPhysicalDevice8BitStorageFeatures *)ext;
1165 CORE_FEATURE(1, 2, storageBuffer8BitAccess);
1166 CORE_FEATURE(1, 2, uniformAndStorageBuffer8BitAccess);
1167 CORE_FEATURE(1, 2, storagePushConstant8);
1168 break;
1169 }
1170 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_FLOAT16_INT8_FEATURES: {
1171 VkPhysicalDeviceShaderFloat16Int8Features *features =
1172 (VkPhysicalDeviceShaderFloat16Int8Features*)ext;
1173 CORE_FEATURE(1, 2, shaderFloat16);
1174 CORE_FEATURE(1, 2, shaderInt8);
1175 break;
1176 }
1177 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES: {
1178 VkPhysicalDeviceShaderAtomicInt64Features *features =
1179 (VkPhysicalDeviceShaderAtomicInt64Features *)ext;
1180 CORE_FEATURE(1, 2, shaderBufferInt64Atomics);
1181 CORE_FEATURE(1, 2, shaderSharedInt64Atomics);
1182 break;
1183 }
1184 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DEMOTE_TO_HELPER_INVOCATION_FEATURES_EXT: {
1185 VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT *features =
1186 (VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT *)ext;
1187 features->shaderDemoteToHelperInvocation = LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm;
1188 break;
1189 }
1190 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
1191 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
1192 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
1193
1194 features->inlineUniformBlock = true;
1195 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
1196 break;
1197 }
1198 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
1199 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
1200 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
1201 features->computeDerivativeGroupQuads = false;
1202 features->computeDerivativeGroupLinear = true;
1203 break;
1204 }
1205 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
1206 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
1207 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
1208 features->ycbcrImageArrays = true;
1209 break;
1210 }
1211 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES: {
1212 VkPhysicalDeviceUniformBufferStandardLayoutFeatures *features =
1213 (VkPhysicalDeviceUniformBufferStandardLayoutFeatures *)ext;
1214 CORE_FEATURE(1, 2, uniformBufferStandardLayout);
1215 break;
1216 }
1217 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT: {
1218 VkPhysicalDeviceIndexTypeUint8FeaturesEXT *features =
1219 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT *)ext;
1220 features->indexTypeUint8 = pdevice->rad_info.chip_class >= GFX8;
1221 break;
1222 }
1223 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGELESS_FRAMEBUFFER_FEATURES: {
1224 VkPhysicalDeviceImagelessFramebufferFeatures *features =
1225 (VkPhysicalDeviceImagelessFramebufferFeatures *)ext;
1226 CORE_FEATURE(1, 2, imagelessFramebuffer);
1227 break;
1228 }
1229 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR: {
1230 VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *features =
1231 (VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *)ext;
1232 features->pipelineExecutableInfo = true;
1233 break;
1234 }
1235 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CLOCK_FEATURES_KHR: {
1236 VkPhysicalDeviceShaderClockFeaturesKHR *features =
1237 (VkPhysicalDeviceShaderClockFeaturesKHR *)ext;
1238 features->shaderSubgroupClock = true;
1239 features->shaderDeviceClock = pdevice->rad_info.chip_class >= GFX8;
1240 break;
1241 }
1242 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_FEATURES_EXT: {
1243 VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT *features =
1244 (VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT *)ext;
1245 features->texelBufferAlignment = true;
1246 break;
1247 }
1248 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_FEATURES: {
1249 VkPhysicalDeviceTimelineSemaphoreFeatures *features =
1250 (VkPhysicalDeviceTimelineSemaphoreFeatures *) ext;
1251 CORE_FEATURE(1, 2, timelineSemaphore);
1252 break;
1253 }
1254 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_FEATURES_EXT: {
1255 VkPhysicalDeviceSubgroupSizeControlFeaturesEXT *features =
1256 (VkPhysicalDeviceSubgroupSizeControlFeaturesEXT *)ext;
1257 features->subgroupSizeControl = true;
1258 features->computeFullSubgroups = true;
1259 break;
1260 }
1261 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COHERENT_MEMORY_FEATURES_AMD: {
1262 VkPhysicalDeviceCoherentMemoryFeaturesAMD *features =
1263 (VkPhysicalDeviceCoherentMemoryFeaturesAMD *)ext;
1264 features->deviceCoherentMemory = pdevice->rad_info.has_l2_uncached;
1265 break;
1266 }
1267 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_SUBGROUP_EXTENDED_TYPES_FEATURES: {
1268 VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures *features =
1269 (VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures *)ext;
1270 CORE_FEATURE(1, 2, shaderSubgroupExtendedTypes);
1271 break;
1272 }
1273 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SEPARATE_DEPTH_STENCIL_LAYOUTS_FEATURES_KHR: {
1274 VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR *features =
1275 (VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR *)ext;
1276 CORE_FEATURE(1, 2, separateDepthStencilLayouts);
1277 break;
1278 }
1279 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES: {
1280 radv_get_physical_device_features_1_1(pdevice, (void *)ext);
1281 break;
1282 }
1283 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES: {
1284 radv_get_physical_device_features_1_2(pdevice, (void *)ext);
1285 break;
1286 }
1287 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_FEATURES_EXT: {
1288 VkPhysicalDeviceLineRasterizationFeaturesEXT *features =
1289 (VkPhysicalDeviceLineRasterizationFeaturesEXT *)ext;
1290 features->rectangularLines = false;
1291 features->bresenhamLines = true;
1292 features->smoothLines = false;
1293 features->stippledRectangularLines = false;
1294 features->stippledBresenhamLines = true;
1295 features->stippledSmoothLines = false;
1296 break;
1297 }
1298 case VK_STRUCTURE_TYPE_DEVICE_MEMORY_OVERALLOCATION_CREATE_INFO_AMD: {
1299 VkDeviceMemoryOverallocationCreateInfoAMD *features =
1300 (VkDeviceMemoryOverallocationCreateInfoAMD *)ext;
1301 features->overallocationBehavior = true;
1302 break;
1303 }
1304 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ROBUSTNESS_2_FEATURES_EXT: {
1305 VkPhysicalDeviceRobustness2FeaturesEXT *features =
1306 (VkPhysicalDeviceRobustness2FeaturesEXT *)ext;
1307 features->robustBufferAccess2 = true;
1308 features->robustImageAccess2 = true;
1309 features->nullDescriptor = true;
1310 break;
1311 }
1312 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_FEATURES_EXT: {
1313 VkPhysicalDeviceCustomBorderColorFeaturesEXT *features =
1314 (VkPhysicalDeviceCustomBorderColorFeaturesEXT *)ext;
1315 features->customBorderColors = true;
1316 features->customBorderColorWithoutFormat = true;
1317 break;
1318 }
1319 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PRIVATE_DATA_FEATURES_EXT: {
1320 VkPhysicalDevicePrivateDataFeaturesEXT *features =
1321 (VkPhysicalDevicePrivateDataFeaturesEXT *)ext;
1322 features->privateData = true;
1323 break;
1324 }
1325 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_CREATION_CACHE_CONTROL_FEATURES_EXT: {
1326 VkPhysicalDevicePipelineCreationCacheControlFeaturesEXT *features =
1327 (VkPhysicalDevicePipelineCreationCacheControlFeaturesEXT *)ext;
1328 features-> pipelineCreationCacheControl = true;
1329 break;
1330 }
1331 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTENDED_DYNAMIC_STATE_FEATURES_EXT: {
1332 VkPhysicalDeviceExtendedDynamicStateFeaturesEXT *features =
1333 (VkPhysicalDeviceExtendedDynamicStateFeaturesEXT *) ext;
1334 features->extendedDynamicState = true;
1335 break;
1336 }
1337 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGE_ROBUSTNESS_FEATURES_EXT: {
1338 VkPhysicalDeviceImageRobustnessFeaturesEXT *features =
1339 (VkPhysicalDeviceImageRobustnessFeaturesEXT *)ext;
1340 features->robustImageAccess = true;
1341 break;
1342 }
1343 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_FLOAT_FEATURES_EXT: {
1344 VkPhysicalDeviceShaderAtomicFloatFeaturesEXT *features =
1345 (VkPhysicalDeviceShaderAtomicFloatFeaturesEXT *)ext;
1346 features->shaderBufferFloat32Atomics = true;
1347 features->shaderBufferFloat32AtomicAdd = false;
1348 features->shaderBufferFloat64Atomics = true;
1349 features->shaderBufferFloat64AtomicAdd = false;
1350 features->shaderSharedFloat32Atomics = true;
1351 features->shaderSharedFloat32AtomicAdd = pdevice->rad_info.chip_class >= GFX8 &&
1352 (!pdevice->use_llvm || LLVM_VERSION_MAJOR >= 10);
1353 features->shaderSharedFloat64Atomics = true;
1354 features->shaderSharedFloat64AtomicAdd = false;
1355 features->shaderImageFloat32Atomics = true;
1356 features->shaderImageFloat32AtomicAdd = false;
1357 features->sparseImageFloat32Atomics = false;
1358 features->sparseImageFloat32AtomicAdd = false;
1359 break;
1360 }
1361 default:
1362 break;
1363 }
1364 }
1365 #undef CORE_FEATURE
1366 }
1367
1368 static size_t
1369 radv_max_descriptor_set_size()
1370 {
1371 /* make sure that the entire descriptor set is addressable with a signed
1372 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1373 * be at most 2 GiB. the combined image & samples object count as one of
1374 * both. This limit is for the pipeline layout, not for the set layout, but
1375 * there is no set limit, so we just set a pipeline limit. I don't think
1376 * any app is going to hit this soon. */
1377 return ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
1378 - MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1379 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1380 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1381 32 /* sampler, largest when combined with image */ +
1382 64 /* sampled image */ +
1383 64 /* storage image */);
1384 }
1385
1386 void radv_GetPhysicalDeviceProperties(
1387 VkPhysicalDevice physicalDevice,
1388 VkPhysicalDeviceProperties* pProperties)
1389 {
1390 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1391 VkSampleCountFlags sample_counts = 0xf;
1392
1393 size_t max_descriptor_set_size = radv_max_descriptor_set_size();
1394
1395 VkPhysicalDeviceLimits limits = {
1396 .maxImageDimension1D = (1 << 14),
1397 .maxImageDimension2D = (1 << 14),
1398 .maxImageDimension3D = (1 << 11),
1399 .maxImageDimensionCube = (1 << 14),
1400 .maxImageArrayLayers = (1 << 11),
1401 .maxTexelBufferElements = UINT32_MAX,
1402 .maxUniformBufferRange = UINT32_MAX,
1403 .maxStorageBufferRange = UINT32_MAX,
1404 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1405 .maxMemoryAllocationCount = UINT32_MAX,
1406 .maxSamplerAllocationCount = 64 * 1024,
1407 .bufferImageGranularity = 64, /* A cache line */
1408 .sparseAddressSpaceSize = RADV_MAX_MEMORY_ALLOCATION_SIZE, /* buffer max size */
1409 .maxBoundDescriptorSets = MAX_SETS,
1410 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1411 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1412 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1413 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1414 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1415 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1416 .maxPerStageResources = max_descriptor_set_size,
1417 .maxDescriptorSetSamplers = max_descriptor_set_size,
1418 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1419 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1420 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1421 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1422 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1423 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1424 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1425 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1426 .maxVertexInputBindings = MAX_VBS,
1427 .maxVertexInputAttributeOffset = 2047,
1428 .maxVertexInputBindingStride = 2048,
1429 .maxVertexOutputComponents = 128,
1430 .maxTessellationGenerationLevel = 64,
1431 .maxTessellationPatchSize = 32,
1432 .maxTessellationControlPerVertexInputComponents = 128,
1433 .maxTessellationControlPerVertexOutputComponents = 128,
1434 .maxTessellationControlPerPatchOutputComponents = 120,
1435 .maxTessellationControlTotalOutputComponents = 4096,
1436 .maxTessellationEvaluationInputComponents = 128,
1437 .maxTessellationEvaluationOutputComponents = 128,
1438 .maxGeometryShaderInvocations = 127,
1439 .maxGeometryInputComponents = 64,
1440 .maxGeometryOutputComponents = 128,
1441 .maxGeometryOutputVertices = 256,
1442 .maxGeometryTotalOutputComponents = 1024,
1443 .maxFragmentInputComponents = 128,
1444 .maxFragmentOutputAttachments = 8,
1445 .maxFragmentDualSrcAttachments = 1,
1446 .maxFragmentCombinedOutputResources = 8,
1447 .maxComputeSharedMemorySize = 32768,
1448 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1449 .maxComputeWorkGroupInvocations = 1024,
1450 .maxComputeWorkGroupSize = {
1451 1024,
1452 1024,
1453 1024
1454 },
1455 .subPixelPrecisionBits = 8,
1456 .subTexelPrecisionBits = 8,
1457 .mipmapPrecisionBits = 8,
1458 .maxDrawIndexedIndexValue = UINT32_MAX,
1459 .maxDrawIndirectCount = UINT32_MAX,
1460 .maxSamplerLodBias = 16,
1461 .maxSamplerAnisotropy = 16,
1462 .maxViewports = MAX_VIEWPORTS,
1463 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1464 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1465 .viewportSubPixelBits = 8,
1466 .minMemoryMapAlignment = 4096, /* A page */
1467 .minTexelBufferOffsetAlignment = 4,
1468 .minUniformBufferOffsetAlignment = 4,
1469 .minStorageBufferOffsetAlignment = 4,
1470 .minTexelOffset = -32,
1471 .maxTexelOffset = 31,
1472 .minTexelGatherOffset = -32,
1473 .maxTexelGatherOffset = 31,
1474 .minInterpolationOffset = -2,
1475 .maxInterpolationOffset = 2,
1476 .subPixelInterpolationOffsetBits = 8,
1477 .maxFramebufferWidth = (1 << 14),
1478 .maxFramebufferHeight = (1 << 14),
1479 .maxFramebufferLayers = (1 << 10),
1480 .framebufferColorSampleCounts = sample_counts,
1481 .framebufferDepthSampleCounts = sample_counts,
1482 .framebufferStencilSampleCounts = sample_counts,
1483 .framebufferNoAttachmentsSampleCounts = sample_counts,
1484 .maxColorAttachments = MAX_RTS,
1485 .sampledImageColorSampleCounts = sample_counts,
1486 .sampledImageIntegerSampleCounts = sample_counts,
1487 .sampledImageDepthSampleCounts = sample_counts,
1488 .sampledImageStencilSampleCounts = sample_counts,
1489 .storageImageSampleCounts = sample_counts,
1490 .maxSampleMaskWords = 1,
1491 .timestampComputeAndGraphics = true,
1492 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1493 .maxClipDistances = 8,
1494 .maxCullDistances = 8,
1495 .maxCombinedClipAndCullDistances = 8,
1496 .discreteQueuePriorities = 2,
1497 .pointSizeRange = { 0.0, 8191.875 },
1498 .lineWidthRange = { 0.0, 8191.875 },
1499 .pointSizeGranularity = (1.0 / 8.0),
1500 .lineWidthGranularity = (1.0 / 8.0),
1501 .strictLines = false, /* FINISHME */
1502 .standardSampleLocations = true,
1503 .optimalBufferCopyOffsetAlignment = 128,
1504 .optimalBufferCopyRowPitchAlignment = 128,
1505 .nonCoherentAtomSize = 64,
1506 };
1507
1508 *pProperties = (VkPhysicalDeviceProperties) {
1509 .apiVersion = radv_physical_device_api_version(pdevice),
1510 .driverVersion = vk_get_driver_version(),
1511 .vendorID = ATI_VENDOR_ID,
1512 .deviceID = pdevice->rad_info.pci_id,
1513 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1514 .limits = limits,
1515 .sparseProperties = {0},
1516 };
1517
1518 strcpy(pProperties->deviceName, pdevice->name);
1519 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1520 }
1521
1522 static void
1523 radv_get_physical_device_properties_1_1(struct radv_physical_device *pdevice,
1524 VkPhysicalDeviceVulkan11Properties *p)
1525 {
1526 assert(p->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES);
1527
1528 memcpy(p->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1529 memcpy(p->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1530 memset(p->deviceLUID, 0, VK_LUID_SIZE);
1531 /* The LUID is for Windows. */
1532 p->deviceLUIDValid = false;
1533 p->deviceNodeMask = 0;
1534
1535 p->subgroupSize = RADV_SUBGROUP_SIZE;
1536 p->subgroupSupportedStages = VK_SHADER_STAGE_ALL_GRAPHICS |
1537 VK_SHADER_STAGE_COMPUTE_BIT;
1538 p->subgroupSupportedOperations = VK_SUBGROUP_FEATURE_BASIC_BIT |
1539 VK_SUBGROUP_FEATURE_VOTE_BIT |
1540 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1541 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1542 VK_SUBGROUP_FEATURE_CLUSTERED_BIT |
1543 VK_SUBGROUP_FEATURE_QUAD_BIT |
1544 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1545 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1546 p->subgroupQuadOperationsInAllStages = true;
1547
1548 p->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1549 p->maxMultiviewViewCount = MAX_VIEWS;
1550 p->maxMultiviewInstanceIndex = INT_MAX;
1551 p->protectedNoFault = false;
1552 p->maxPerSetDescriptors = RADV_MAX_PER_SET_DESCRIPTORS;
1553 p->maxMemoryAllocationSize = RADV_MAX_MEMORY_ALLOCATION_SIZE;
1554 }
1555
1556 static void
1557 radv_get_physical_device_properties_1_2(struct radv_physical_device *pdevice,
1558 VkPhysicalDeviceVulkan12Properties *p)
1559 {
1560 assert(p->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES);
1561
1562 p->driverID = VK_DRIVER_ID_MESA_RADV;
1563 snprintf(p->driverName, VK_MAX_DRIVER_NAME_SIZE, "radv");
1564 snprintf(p->driverInfo, VK_MAX_DRIVER_INFO_SIZE,
1565 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1 " (%s)",
1566 radv_get_compiler_string(pdevice));
1567 p->conformanceVersion = (VkConformanceVersion) {
1568 .major = 1,
1569 .minor = 2,
1570 .subminor = 0,
1571 .patch = 0,
1572 };
1573
1574 /* On AMD hardware, denormals and rounding modes for fp16/fp64 are
1575 * controlled by the same config register.
1576 */
1577 if (pdevice->rad_info.has_packed_math_16bit) {
1578 p->denormBehaviorIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
1579 p->roundingModeIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
1580 } else {
1581 p->denormBehaviorIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL_KHR;
1582 p->roundingModeIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL_KHR;
1583 }
1584
1585 /* With LLVM, do not allow both preserving and flushing denorms because
1586 * different shaders in the same pipeline can have different settings and
1587 * this won't work for merged shaders. To make it work, this requires LLVM
1588 * support for changing the register. The same logic applies for the
1589 * rounding modes because they are configured with the same config
1590 * register.
1591 */
1592 p->shaderDenormFlushToZeroFloat32 = true;
1593 p->shaderDenormPreserveFloat32 = !pdevice->use_llvm;
1594 p->shaderRoundingModeRTEFloat32 = true;
1595 p->shaderRoundingModeRTZFloat32 = !pdevice->use_llvm;
1596 p->shaderSignedZeroInfNanPreserveFloat32 = true;
1597
1598 p->shaderDenormFlushToZeroFloat16 = pdevice->rad_info.has_packed_math_16bit && !pdevice->use_llvm;
1599 p->shaderDenormPreserveFloat16 = pdevice->rad_info.has_packed_math_16bit;
1600 p->shaderRoundingModeRTEFloat16 = pdevice->rad_info.has_packed_math_16bit;
1601 p->shaderRoundingModeRTZFloat16 = pdevice->rad_info.has_packed_math_16bit && !pdevice->use_llvm;
1602 p->shaderSignedZeroInfNanPreserveFloat16 = pdevice->rad_info.has_packed_math_16bit;
1603
1604 p->shaderDenormFlushToZeroFloat64 = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_llvm;
1605 p->shaderDenormPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8;
1606 p->shaderRoundingModeRTEFloat64 = pdevice->rad_info.chip_class >= GFX8;
1607 p->shaderRoundingModeRTZFloat64 = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_llvm;
1608 p->shaderSignedZeroInfNanPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8;
1609
1610 p->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1611 p->shaderUniformBufferArrayNonUniformIndexingNative = false;
1612 p->shaderSampledImageArrayNonUniformIndexingNative = false;
1613 p->shaderStorageBufferArrayNonUniformIndexingNative = false;
1614 p->shaderStorageImageArrayNonUniformIndexingNative = false;
1615 p->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1616 p->robustBufferAccessUpdateAfterBind = false;
1617 p->quadDivergentImplicitLod = false;
1618
1619 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1620 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1621 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1622 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1623 32 /* sampler, largest when combined with image */ +
1624 64 /* sampled image */ +
1625 64 /* storage image */);
1626 p->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1627 p->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1628 p->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1629 p->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1630 p->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1631 p->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1632 p->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1633 p->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1634 p->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1635 p->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1636 p->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1637 p->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1638 p->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1639 p->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1640 p->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1641
1642 /* We support all of the depth resolve modes */
1643 p->supportedDepthResolveModes = VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1644 VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
1645 VK_RESOLVE_MODE_MIN_BIT_KHR |
1646 VK_RESOLVE_MODE_MAX_BIT_KHR;
1647
1648 /* Average doesn't make sense for stencil so we don't support that */
1649 p->supportedStencilResolveModes = VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1650 VK_RESOLVE_MODE_MIN_BIT_KHR |
1651 VK_RESOLVE_MODE_MAX_BIT_KHR;
1652
1653 p->independentResolveNone = true;
1654 p->independentResolve = true;
1655
1656 /* GFX6-8 only support single channel min/max filter. */
1657 p->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1658 p->filterMinmaxSingleComponentFormats = true;
1659
1660 p->maxTimelineSemaphoreValueDifference = UINT64_MAX;
1661
1662 p->framebufferIntegerColorSampleCounts = VK_SAMPLE_COUNT_1_BIT;
1663 }
1664
1665 void radv_GetPhysicalDeviceProperties2(
1666 VkPhysicalDevice physicalDevice,
1667 VkPhysicalDeviceProperties2 *pProperties)
1668 {
1669 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1670 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1671
1672 VkPhysicalDeviceVulkan11Properties core_1_1 = {
1673 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES,
1674 };
1675 radv_get_physical_device_properties_1_1(pdevice, &core_1_1);
1676
1677 VkPhysicalDeviceVulkan12Properties core_1_2 = {
1678 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES,
1679 };
1680 radv_get_physical_device_properties_1_2(pdevice, &core_1_2);
1681
1682 #define CORE_RENAMED_PROPERTY(major, minor, ext_property, core_property) \
1683 memcpy(&properties->ext_property, &core_##major##_##minor.core_property, \
1684 sizeof(core_##major##_##minor.core_property))
1685
1686 #define CORE_PROPERTY(major, minor, property) \
1687 CORE_RENAMED_PROPERTY(major, minor, property, property)
1688
1689 vk_foreach_struct(ext, pProperties->pNext) {
1690 switch (ext->sType) {
1691 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1692 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1693 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1694 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1695 break;
1696 }
1697 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1698 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1699 CORE_PROPERTY(1, 1, deviceUUID);
1700 CORE_PROPERTY(1, 1, driverUUID);
1701 CORE_PROPERTY(1, 1, deviceLUID);
1702 CORE_PROPERTY(1, 1, deviceLUIDValid);
1703 break;
1704 }
1705 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1706 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1707 CORE_PROPERTY(1, 1, maxMultiviewViewCount);
1708 CORE_PROPERTY(1, 1, maxMultiviewInstanceIndex);
1709 break;
1710 }
1711 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1712 VkPhysicalDevicePointClippingProperties *properties =
1713 (VkPhysicalDevicePointClippingProperties*)ext;
1714 CORE_PROPERTY(1, 1, pointClippingBehavior);
1715 break;
1716 }
1717 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1718 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1719 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1720 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1721 break;
1722 }
1723 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1724 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1725 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1726 properties->minImportedHostPointerAlignment = 4096;
1727 break;
1728 }
1729 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1730 VkPhysicalDeviceSubgroupProperties *properties =
1731 (VkPhysicalDeviceSubgroupProperties*)ext;
1732 CORE_PROPERTY(1, 1, subgroupSize);
1733 CORE_RENAMED_PROPERTY(1, 1, supportedStages,
1734 subgroupSupportedStages);
1735 CORE_RENAMED_PROPERTY(1, 1, supportedOperations,
1736 subgroupSupportedOperations);
1737 CORE_RENAMED_PROPERTY(1, 1, quadOperationsInAllStages,
1738 subgroupQuadOperationsInAllStages);
1739 break;
1740 }
1741 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1742 VkPhysicalDeviceMaintenance3Properties *properties =
1743 (VkPhysicalDeviceMaintenance3Properties*)ext;
1744 CORE_PROPERTY(1, 1, maxPerSetDescriptors);
1745 CORE_PROPERTY(1, 1, maxMemoryAllocationSize);
1746 break;
1747 }
1748 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES: {
1749 VkPhysicalDeviceSamplerFilterMinmaxProperties *properties =
1750 (VkPhysicalDeviceSamplerFilterMinmaxProperties *)ext;
1751 CORE_PROPERTY(1, 2, filterMinmaxImageComponentMapping);
1752 CORE_PROPERTY(1, 2, filterMinmaxSingleComponentFormats);
1753 break;
1754 }
1755 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1756 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1757 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1758
1759 /* Shader engines. */
1760 properties->shaderEngineCount =
1761 pdevice->rad_info.max_se;
1762 properties->shaderArraysPerEngineCount =
1763 pdevice->rad_info.max_sh_per_se;
1764 properties->computeUnitsPerShaderArray =
1765 pdevice->rad_info.min_good_cu_per_sa;
1766 properties->simdPerComputeUnit =
1767 pdevice->rad_info.num_simd_per_compute_unit;
1768 properties->wavefrontsPerSimd =
1769 pdevice->rad_info.max_wave64_per_simd;
1770 properties->wavefrontSize = 64;
1771
1772 /* SGPR. */
1773 properties->sgprsPerSimd =
1774 pdevice->rad_info.num_physical_sgprs_per_simd;
1775 properties->minSgprAllocation =
1776 pdevice->rad_info.min_sgpr_alloc;
1777 properties->maxSgprAllocation =
1778 pdevice->rad_info.max_sgpr_alloc;
1779 properties->sgprAllocationGranularity =
1780 pdevice->rad_info.sgpr_alloc_granularity;
1781
1782 /* VGPR. */
1783 properties->vgprsPerSimd =
1784 pdevice->rad_info.num_physical_wave64_vgprs_per_simd;
1785 properties->minVgprAllocation =
1786 pdevice->rad_info.min_wave64_vgpr_alloc;
1787 properties->maxVgprAllocation =
1788 pdevice->rad_info.max_vgpr_alloc;
1789 properties->vgprAllocationGranularity =
1790 pdevice->rad_info.wave64_vgpr_alloc_granularity;
1791 break;
1792 }
1793 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_2_AMD: {
1794 VkPhysicalDeviceShaderCoreProperties2AMD *properties =
1795 (VkPhysicalDeviceShaderCoreProperties2AMD *)ext;
1796
1797 properties->shaderCoreFeatures = 0;
1798 properties->activeComputeUnitCount =
1799 pdevice->rad_info.num_good_compute_units;
1800 break;
1801 }
1802 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1803 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1804 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1805 properties->maxVertexAttribDivisor = UINT32_MAX;
1806 break;
1807 }
1808 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES: {
1809 VkPhysicalDeviceDescriptorIndexingProperties *properties =
1810 (VkPhysicalDeviceDescriptorIndexingProperties*)ext;
1811 CORE_PROPERTY(1, 2, maxUpdateAfterBindDescriptorsInAllPools);
1812 CORE_PROPERTY(1, 2, shaderUniformBufferArrayNonUniformIndexingNative);
1813 CORE_PROPERTY(1, 2, shaderSampledImageArrayNonUniformIndexingNative);
1814 CORE_PROPERTY(1, 2, shaderStorageBufferArrayNonUniformIndexingNative);
1815 CORE_PROPERTY(1, 2, shaderStorageImageArrayNonUniformIndexingNative);
1816 CORE_PROPERTY(1, 2, shaderInputAttachmentArrayNonUniformIndexingNative);
1817 CORE_PROPERTY(1, 2, robustBufferAccessUpdateAfterBind);
1818 CORE_PROPERTY(1, 2, quadDivergentImplicitLod);
1819 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSamplers);
1820 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindUniformBuffers);
1821 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageBuffers);
1822 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSampledImages);
1823 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageImages);
1824 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindInputAttachments);
1825 CORE_PROPERTY(1, 2, maxPerStageUpdateAfterBindResources);
1826 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSamplers);
1827 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffers);
1828 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffersDynamic);
1829 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffers);
1830 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffersDynamic);
1831 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSampledImages);
1832 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageImages);
1833 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindInputAttachments);
1834 break;
1835 }
1836 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1837 VkPhysicalDeviceProtectedMemoryProperties *properties =
1838 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1839 CORE_PROPERTY(1, 1, protectedNoFault);
1840 break;
1841 }
1842 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1843 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1844 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1845 properties->primitiveOverestimationSize = 0;
1846 properties->maxExtraPrimitiveOverestimationSize = 0;
1847 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1848 properties->primitiveUnderestimation = false;
1849 properties->conservativePointAndLineRasterization = false;
1850 properties->degenerateTrianglesRasterized = false;
1851 properties->degenerateLinesRasterized = false;
1852 properties->fullyCoveredFragmentShaderInputVariable = false;
1853 properties->conservativeRasterizationPostDepthCoverage = false;
1854 break;
1855 }
1856 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1857 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1858 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1859 properties->pciDomain = pdevice->bus_info.domain;
1860 properties->pciBus = pdevice->bus_info.bus;
1861 properties->pciDevice = pdevice->bus_info.dev;
1862 properties->pciFunction = pdevice->bus_info.func;
1863 break;
1864 }
1865 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES: {
1866 VkPhysicalDeviceDriverProperties *properties =
1867 (VkPhysicalDeviceDriverProperties *) ext;
1868 CORE_PROPERTY(1, 2, driverID);
1869 CORE_PROPERTY(1, 2, driverName);
1870 CORE_PROPERTY(1, 2, driverInfo);
1871 CORE_PROPERTY(1, 2, conformanceVersion);
1872 break;
1873 }
1874 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1875 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1876 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1877 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1878 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1879 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1880 properties->maxTransformFeedbackStreamDataSize = 512;
1881 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1882 properties->maxTransformFeedbackBufferDataStride = 512;
1883 properties->transformFeedbackQueries = !pdevice->use_ngg_streamout;
1884 properties->transformFeedbackStreamsLinesTriangles = !pdevice->use_ngg_streamout;
1885 properties->transformFeedbackRasterizationStreamSelect = false;
1886 properties->transformFeedbackDraw = true;
1887 break;
1888 }
1889 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1890 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1891 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1892
1893 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1894 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1895 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1896 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1897 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1898 break;
1899 }
1900 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT: {
1901 VkPhysicalDeviceSampleLocationsPropertiesEXT *properties =
1902 (VkPhysicalDeviceSampleLocationsPropertiesEXT *)ext;
1903 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_2_BIT |
1904 VK_SAMPLE_COUNT_4_BIT |
1905 VK_SAMPLE_COUNT_8_BIT;
1906 properties->maxSampleLocationGridSize = (VkExtent2D){ 2 , 2 };
1907 properties->sampleLocationCoordinateRange[0] = 0.0f;
1908 properties->sampleLocationCoordinateRange[1] = 0.9375f;
1909 properties->sampleLocationSubPixelBits = 4;
1910 properties->variableSampleLocations = false;
1911 break;
1912 }
1913 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES: {
1914 VkPhysicalDeviceDepthStencilResolveProperties *properties =
1915 (VkPhysicalDeviceDepthStencilResolveProperties *)ext;
1916 CORE_PROPERTY(1, 2, supportedDepthResolveModes);
1917 CORE_PROPERTY(1, 2, supportedStencilResolveModes);
1918 CORE_PROPERTY(1, 2, independentResolveNone);
1919 CORE_PROPERTY(1, 2, independentResolve);
1920 break;
1921 }
1922 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_PROPERTIES_EXT: {
1923 VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT *properties =
1924 (VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT *)ext;
1925 properties->storageTexelBufferOffsetAlignmentBytes = 4;
1926 properties->storageTexelBufferOffsetSingleTexelAlignment = true;
1927 properties->uniformTexelBufferOffsetAlignmentBytes = 4;
1928 properties->uniformTexelBufferOffsetSingleTexelAlignment = true;
1929 break;
1930 }
1931 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT_CONTROLS_PROPERTIES : {
1932 VkPhysicalDeviceFloatControlsProperties *properties =
1933 (VkPhysicalDeviceFloatControlsProperties *)ext;
1934 CORE_PROPERTY(1, 2, denormBehaviorIndependence);
1935 CORE_PROPERTY(1, 2, roundingModeIndependence);
1936 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat16);
1937 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat16);
1938 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat16);
1939 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat16);
1940 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat16);
1941 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat32);
1942 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat32);
1943 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat32);
1944 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat32);
1945 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat32);
1946 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat64);
1947 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat64);
1948 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat64);
1949 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat64);
1950 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat64);
1951 break;
1952 }
1953 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_PROPERTIES: {
1954 VkPhysicalDeviceTimelineSemaphoreProperties *properties =
1955 (VkPhysicalDeviceTimelineSemaphoreProperties *) ext;
1956 CORE_PROPERTY(1, 2, maxTimelineSemaphoreValueDifference);
1957 break;
1958 }
1959 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_PROPERTIES_EXT: {
1960 VkPhysicalDeviceSubgroupSizeControlPropertiesEXT *props =
1961 (VkPhysicalDeviceSubgroupSizeControlPropertiesEXT *)ext;
1962 props->minSubgroupSize = 64;
1963 props->maxSubgroupSize = 64;
1964 props->maxComputeWorkgroupSubgroups = UINT32_MAX;
1965 props->requiredSubgroupSizeStages = 0;
1966
1967 if (pdevice->rad_info.chip_class >= GFX10) {
1968 /* Only GFX10+ supports wave32. */
1969 props->minSubgroupSize = 32;
1970 props->requiredSubgroupSizeStages = VK_SHADER_STAGE_COMPUTE_BIT;
1971 }
1972 break;
1973 }
1974 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES:
1975 radv_get_physical_device_properties_1_1(pdevice, (void *)ext);
1976 break;
1977 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES:
1978 radv_get_physical_device_properties_1_2(pdevice, (void *)ext);
1979 break;
1980 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_PROPERTIES_EXT: {
1981 VkPhysicalDeviceLineRasterizationPropertiesEXT *props =
1982 (VkPhysicalDeviceLineRasterizationPropertiesEXT *)ext;
1983 props->lineSubPixelPrecisionBits = 4;
1984 break;
1985 }
1986 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ROBUSTNESS_2_PROPERTIES_EXT: {
1987 VkPhysicalDeviceRobustness2PropertiesEXT *properties =
1988 (VkPhysicalDeviceRobustness2PropertiesEXT *)ext;
1989 properties->robustStorageBufferAccessSizeAlignment = 4;
1990 properties->robustUniformBufferAccessSizeAlignment = 4;
1991 break;
1992 }
1993 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_PROPERTIES_EXT: {
1994 VkPhysicalDeviceCustomBorderColorPropertiesEXT *props =
1995 (VkPhysicalDeviceCustomBorderColorPropertiesEXT *)ext;
1996 props->maxCustomBorderColorSamplers = RADV_BORDER_COLOR_COUNT;
1997 break;
1998 }
1999 default:
2000 break;
2001 }
2002 }
2003 }
2004
2005 static void radv_get_physical_device_queue_family_properties(
2006 struct radv_physical_device* pdevice,
2007 uint32_t* pCount,
2008 VkQueueFamilyProperties** pQueueFamilyProperties)
2009 {
2010 int num_queue_families = 1;
2011 int idx;
2012 if (pdevice->rad_info.num_rings[RING_COMPUTE] > 0 &&
2013 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
2014 num_queue_families++;
2015
2016 if (pQueueFamilyProperties == NULL) {
2017 *pCount = num_queue_families;
2018 return;
2019 }
2020
2021 if (!*pCount)
2022 return;
2023
2024 idx = 0;
2025 if (*pCount >= 1) {
2026 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
2027 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
2028 VK_QUEUE_COMPUTE_BIT |
2029 VK_QUEUE_TRANSFER_BIT |
2030 VK_QUEUE_SPARSE_BINDING_BIT,
2031 .queueCount = 1,
2032 .timestampValidBits = 64,
2033 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
2034 };
2035 idx++;
2036 }
2037
2038 if (pdevice->rad_info.num_rings[RING_COMPUTE] > 0 &&
2039 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
2040 if (*pCount > idx) {
2041 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
2042 .queueFlags = VK_QUEUE_COMPUTE_BIT |
2043 VK_QUEUE_TRANSFER_BIT |
2044 VK_QUEUE_SPARSE_BINDING_BIT,
2045 .queueCount = pdevice->rad_info.num_rings[RING_COMPUTE],
2046 .timestampValidBits = 64,
2047 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
2048 };
2049 idx++;
2050 }
2051 }
2052 *pCount = idx;
2053 }
2054
2055 void radv_GetPhysicalDeviceQueueFamilyProperties(
2056 VkPhysicalDevice physicalDevice,
2057 uint32_t* pCount,
2058 VkQueueFamilyProperties* pQueueFamilyProperties)
2059 {
2060 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
2061 if (!pQueueFamilyProperties) {
2062 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
2063 return;
2064 }
2065 VkQueueFamilyProperties *properties[] = {
2066 pQueueFamilyProperties + 0,
2067 pQueueFamilyProperties + 1,
2068 pQueueFamilyProperties + 2,
2069 };
2070 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
2071 assert(*pCount <= 3);
2072 }
2073
2074 void radv_GetPhysicalDeviceQueueFamilyProperties2(
2075 VkPhysicalDevice physicalDevice,
2076 uint32_t* pCount,
2077 VkQueueFamilyProperties2 *pQueueFamilyProperties)
2078 {
2079 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
2080 if (!pQueueFamilyProperties) {
2081 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
2082 return;
2083 }
2084 VkQueueFamilyProperties *properties[] = {
2085 &pQueueFamilyProperties[0].queueFamilyProperties,
2086 &pQueueFamilyProperties[1].queueFamilyProperties,
2087 &pQueueFamilyProperties[2].queueFamilyProperties,
2088 };
2089 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
2090 assert(*pCount <= 3);
2091 }
2092
2093 void radv_GetPhysicalDeviceMemoryProperties(
2094 VkPhysicalDevice physicalDevice,
2095 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
2096 {
2097 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2098
2099 *pMemoryProperties = physical_device->memory_properties;
2100 }
2101
2102 static void
2103 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
2104 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
2105 {
2106 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2107 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
2108 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
2109 uint64_t vram_size = radv_get_vram_size(device);
2110 uint64_t gtt_size = device->rad_info.gart_size;
2111 uint64_t heap_budget, heap_usage;
2112
2113 /* For all memory heaps, the computation of budget is as follow:
2114 * heap_budget = heap_size - global_heap_usage + app_heap_usage
2115 *
2116 * The Vulkan spec 1.1.97 says that the budget should include any
2117 * currently allocated device memory.
2118 *
2119 * Note that the application heap usages are not really accurate (eg.
2120 * in presence of shared buffers).
2121 */
2122 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
2123 uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;
2124
2125 if ((device->memory_domains[i] & RADEON_DOMAIN_VRAM) && (device->memory_flags[i] & RADEON_FLAG_NO_CPU_ACCESS)) {
2126 heap_usage = device->ws->query_value(device->ws,
2127 RADEON_ALLOCATED_VRAM);
2128
2129 heap_budget = vram_size -
2130 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
2131 heap_usage;
2132
2133 memoryBudget->heapBudget[heap_index] = heap_budget;
2134 memoryBudget->heapUsage[heap_index] = heap_usage;
2135 } else if (device->memory_domains[i] & RADEON_DOMAIN_VRAM) {
2136 heap_usage = device->ws->query_value(device->ws,
2137 RADEON_ALLOCATED_VRAM_VIS);
2138
2139 heap_budget = visible_vram_size -
2140 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
2141 heap_usage;
2142
2143 memoryBudget->heapBudget[heap_index] = heap_budget;
2144 memoryBudget->heapUsage[heap_index] = heap_usage;
2145 } else {
2146 assert(device->memory_domains[i] & RADEON_DOMAIN_GTT);
2147
2148 heap_usage = device->ws->query_value(device->ws,
2149 RADEON_ALLOCATED_GTT);
2150
2151 heap_budget = gtt_size -
2152 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
2153 heap_usage;
2154
2155 memoryBudget->heapBudget[heap_index] = heap_budget;
2156 memoryBudget->heapUsage[heap_index] = heap_usage;
2157 }
2158 }
2159
2160 /* The heapBudget and heapUsage values must be zero for array elements
2161 * greater than or equal to
2162 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
2163 */
2164 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
2165 memoryBudget->heapBudget[i] = 0;
2166 memoryBudget->heapUsage[i] = 0;
2167 }
2168 }
2169
2170 void radv_GetPhysicalDeviceMemoryProperties2(
2171 VkPhysicalDevice physicalDevice,
2172 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
2173 {
2174 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
2175 &pMemoryProperties->memoryProperties);
2176
2177 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
2178 vk_find_struct(pMemoryProperties->pNext,
2179 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
2180 if (memory_budget)
2181 radv_get_memory_budget_properties(physicalDevice, memory_budget);
2182 }
2183
2184 VkResult radv_GetMemoryHostPointerPropertiesEXT(
2185 VkDevice _device,
2186 VkExternalMemoryHandleTypeFlagBits handleType,
2187 const void *pHostPointer,
2188 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
2189 {
2190 RADV_FROM_HANDLE(radv_device, device, _device);
2191
2192 switch (handleType)
2193 {
2194 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
2195 const struct radv_physical_device *physical_device = device->physical_device;
2196 uint32_t memoryTypeBits = 0;
2197 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
2198 if (physical_device->memory_domains[i] == RADEON_DOMAIN_GTT &&
2199 !(physical_device->memory_flags[i] & RADEON_FLAG_GTT_WC)) {
2200 memoryTypeBits = (1 << i);
2201 break;
2202 }
2203 }
2204 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
2205 return VK_SUCCESS;
2206 }
2207 default:
2208 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
2209 }
2210 }
2211
2212 static enum radeon_ctx_priority
2213 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
2214 {
2215 /* Default to MEDIUM when a specific global priority isn't requested */
2216 if (!pObj)
2217 return RADEON_CTX_PRIORITY_MEDIUM;
2218
2219 switch(pObj->globalPriority) {
2220 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
2221 return RADEON_CTX_PRIORITY_REALTIME;
2222 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
2223 return RADEON_CTX_PRIORITY_HIGH;
2224 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
2225 return RADEON_CTX_PRIORITY_MEDIUM;
2226 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
2227 return RADEON_CTX_PRIORITY_LOW;
2228 default:
2229 unreachable("Illegal global priority value");
2230 return RADEON_CTX_PRIORITY_INVALID;
2231 }
2232 }
2233
2234 static int
2235 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
2236 uint32_t queue_family_index, int idx,
2237 VkDeviceQueueCreateFlags flags,
2238 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
2239 {
2240 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2241 queue->device = device;
2242 queue->queue_family_index = queue_family_index;
2243 queue->queue_idx = idx;
2244 queue->priority = radv_get_queue_global_priority(global_priority);
2245 queue->flags = flags;
2246 queue->hw_ctx = NULL;
2247
2248 VkResult result = device->ws->ctx_create(device->ws, queue->priority, &queue->hw_ctx);
2249 if (result != VK_SUCCESS)
2250 return vk_error(device->instance, result);
2251
2252 list_inithead(&queue->pending_submissions);
2253 pthread_mutex_init(&queue->pending_mutex, NULL);
2254
2255 return VK_SUCCESS;
2256 }
2257
2258 static void
2259 radv_queue_finish(struct radv_queue *queue)
2260 {
2261 pthread_mutex_destroy(&queue->pending_mutex);
2262
2263 if (queue->hw_ctx)
2264 queue->device->ws->ctx_destroy(queue->hw_ctx);
2265
2266 if (queue->initial_full_flush_preamble_cs)
2267 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2268 if (queue->initial_preamble_cs)
2269 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2270 if (queue->continue_preamble_cs)
2271 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2272 if (queue->descriptor_bo)
2273 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2274 if (queue->scratch_bo)
2275 queue->device->ws->buffer_destroy(queue->scratch_bo);
2276 if (queue->esgs_ring_bo)
2277 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2278 if (queue->gsvs_ring_bo)
2279 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2280 if (queue->tess_rings_bo)
2281 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
2282 if (queue->gds_bo)
2283 queue->device->ws->buffer_destroy(queue->gds_bo);
2284 if (queue->gds_oa_bo)
2285 queue->device->ws->buffer_destroy(queue->gds_oa_bo);
2286 if (queue->compute_scratch_bo)
2287 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2288 }
2289
2290 static void
2291 radv_bo_list_init(struct radv_bo_list *bo_list)
2292 {
2293 pthread_mutex_init(&bo_list->mutex, NULL);
2294 bo_list->list.count = bo_list->capacity = 0;
2295 bo_list->list.bos = NULL;
2296 }
2297
2298 static void
2299 radv_bo_list_finish(struct radv_bo_list *bo_list)
2300 {
2301 free(bo_list->list.bos);
2302 pthread_mutex_destroy(&bo_list->mutex);
2303 }
2304
2305 VkResult radv_bo_list_add(struct radv_device *device,
2306 struct radeon_winsys_bo *bo)
2307 {
2308 struct radv_bo_list *bo_list = &device->bo_list;
2309
2310 if (bo->is_local)
2311 return VK_SUCCESS;
2312
2313 if (unlikely(!device->use_global_bo_list))
2314 return VK_SUCCESS;
2315
2316 pthread_mutex_lock(&bo_list->mutex);
2317 if (bo_list->list.count == bo_list->capacity) {
2318 unsigned capacity = MAX2(4, bo_list->capacity * 2);
2319 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
2320
2321 if (!data) {
2322 pthread_mutex_unlock(&bo_list->mutex);
2323 return VK_ERROR_OUT_OF_HOST_MEMORY;
2324 }
2325
2326 bo_list->list.bos = (struct radeon_winsys_bo**)data;
2327 bo_list->capacity = capacity;
2328 }
2329
2330 bo_list->list.bos[bo_list->list.count++] = bo;
2331 pthread_mutex_unlock(&bo_list->mutex);
2332 return VK_SUCCESS;
2333 }
2334
2335 void radv_bo_list_remove(struct radv_device *device,
2336 struct radeon_winsys_bo *bo)
2337 {
2338 struct radv_bo_list *bo_list = &device->bo_list;
2339
2340 if (bo->is_local)
2341 return;
2342
2343 if (unlikely(!device->use_global_bo_list))
2344 return;
2345
2346 pthread_mutex_lock(&bo_list->mutex);
2347 /* Loop the list backwards so we find the most recently added
2348 * memory first. */
2349 for(unsigned i = bo_list->list.count; i-- > 0;) {
2350 if (bo_list->list.bos[i] == bo) {
2351 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
2352 --bo_list->list.count;
2353 break;
2354 }
2355 }
2356 pthread_mutex_unlock(&bo_list->mutex);
2357 }
2358
2359 static void
2360 radv_device_init_gs_info(struct radv_device *device)
2361 {
2362 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
2363 device->physical_device->rad_info.family);
2364 }
2365
2366 static int radv_get_device_extension_index(const char *name)
2367 {
2368 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
2369 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
2370 return i;
2371 }
2372 return -1;
2373 }
2374
2375 static int
2376 radv_get_int_debug_option(const char *name, int default_value)
2377 {
2378 const char *str;
2379 int result;
2380
2381 str = getenv(name);
2382 if (!str) {
2383 result = default_value;
2384 } else {
2385 char *endptr;
2386
2387 result = strtol(str, &endptr, 0);
2388 if (str == endptr) {
2389 /* No digits founs. */
2390 result = default_value;
2391 }
2392 }
2393
2394 return result;
2395 }
2396
2397 static void
2398 radv_device_init_dispatch(struct radv_device *device)
2399 {
2400 const struct radv_instance *instance = device->physical_device->instance;
2401 const struct radv_device_dispatch_table *dispatch_table_layer = NULL;
2402 bool unchecked = instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS;
2403 int radv_thread_trace = radv_get_int_debug_option("RADV_THREAD_TRACE", -1);
2404
2405 if (radv_thread_trace >= 0) {
2406 /* Use device entrypoints from the SQTT layer if enabled. */
2407 dispatch_table_layer = &sqtt_device_dispatch_table;
2408 }
2409
2410 for (unsigned i = 0; i < ARRAY_SIZE(device->dispatch.entrypoints); i++) {
2411 /* Vulkan requires that entrypoints for extensions which have not been
2412 * enabled must not be advertised.
2413 */
2414 if (!unchecked &&
2415 !radv_device_entrypoint_is_enabled(i, instance->apiVersion,
2416 &instance->enabled_extensions,
2417 &device->enabled_extensions)) {
2418 device->dispatch.entrypoints[i] = NULL;
2419 } else if (dispatch_table_layer &&
2420 dispatch_table_layer->entrypoints[i]) {
2421 device->dispatch.entrypoints[i] =
2422 dispatch_table_layer->entrypoints[i];
2423 } else {
2424 device->dispatch.entrypoints[i] =
2425 radv_device_dispatch_table.entrypoints[i];
2426 }
2427 }
2428 }
2429
2430 static VkResult
2431 radv_create_pthread_cond(pthread_cond_t *cond)
2432 {
2433 pthread_condattr_t condattr;
2434 if (pthread_condattr_init(&condattr)) {
2435 return VK_ERROR_INITIALIZATION_FAILED;
2436 }
2437
2438 if (pthread_condattr_setclock(&condattr, CLOCK_MONOTONIC)) {
2439 pthread_condattr_destroy(&condattr);
2440 return VK_ERROR_INITIALIZATION_FAILED;
2441 }
2442 if (pthread_cond_init(cond, &condattr)) {
2443 pthread_condattr_destroy(&condattr);
2444 return VK_ERROR_INITIALIZATION_FAILED;
2445 }
2446 pthread_condattr_destroy(&condattr);
2447 return VK_SUCCESS;
2448 }
2449
2450 static VkResult
2451 check_physical_device_features(VkPhysicalDevice physicalDevice,
2452 const VkPhysicalDeviceFeatures *features)
2453 {
2454 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2455 VkPhysicalDeviceFeatures supported_features;
2456 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
2457 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
2458 VkBool32 *enabled_feature = (VkBool32 *)features;
2459 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
2460 for (uint32_t i = 0; i < num_features; i++) {
2461 if (enabled_feature[i] && !supported_feature[i])
2462 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
2463 }
2464
2465 return VK_SUCCESS;
2466 }
2467
2468 static VkResult radv_device_init_border_color(struct radv_device *device)
2469 {
2470 device->border_color_data.bo =
2471 device->ws->buffer_create(device->ws,
2472 RADV_BORDER_COLOR_BUFFER_SIZE,
2473 4096,
2474 RADEON_DOMAIN_VRAM,
2475 RADEON_FLAG_CPU_ACCESS |
2476 RADEON_FLAG_READ_ONLY |
2477 RADEON_FLAG_NO_INTERPROCESS_SHARING,
2478 RADV_BO_PRIORITY_SHADER);
2479
2480 if (device->border_color_data.bo == NULL)
2481 return vk_error(device->physical_device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2482
2483 device->border_color_data.colors_gpu_ptr =
2484 device->ws->buffer_map(device->border_color_data.bo);
2485 if (!device->border_color_data.colors_gpu_ptr)
2486 return vk_error(device->physical_device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2487 pthread_mutex_init(&device->border_color_data.mutex, NULL);
2488
2489 return VK_SUCCESS;
2490 }
2491
2492 static void radv_device_finish_border_color(struct radv_device *device)
2493 {
2494 if (device->border_color_data.bo) {
2495 device->ws->buffer_destroy(device->border_color_data.bo);
2496
2497 pthread_mutex_destroy(&device->border_color_data.mutex);
2498 }
2499 }
2500
2501 VkResult radv_CreateDevice(
2502 VkPhysicalDevice physicalDevice,
2503 const VkDeviceCreateInfo* pCreateInfo,
2504 const VkAllocationCallbacks* pAllocator,
2505 VkDevice* pDevice)
2506 {
2507 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2508 VkResult result;
2509 struct radv_device *device;
2510
2511 bool keep_shader_info = false;
2512 bool robust_buffer_access = false;
2513 bool overallocation_disallowed = false;
2514 bool custom_border_colors = false;
2515
2516 /* Check enabled features */
2517 if (pCreateInfo->pEnabledFeatures) {
2518 result = check_physical_device_features(physicalDevice,
2519 pCreateInfo->pEnabledFeatures);
2520 if (result != VK_SUCCESS)
2521 return result;
2522
2523 if (pCreateInfo->pEnabledFeatures->robustBufferAccess)
2524 robust_buffer_access = true;
2525 }
2526
2527 vk_foreach_struct_const(ext, pCreateInfo->pNext) {
2528 switch (ext->sType) {
2529 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FEATURES_2: {
2530 const VkPhysicalDeviceFeatures2 *features = (const void *)ext;
2531 result = check_physical_device_features(physicalDevice,
2532 &features->features);
2533 if (result != VK_SUCCESS)
2534 return result;
2535
2536 if (features->features.robustBufferAccess)
2537 robust_buffer_access = true;
2538 break;
2539 }
2540 case VK_STRUCTURE_TYPE_DEVICE_MEMORY_OVERALLOCATION_CREATE_INFO_AMD: {
2541 const VkDeviceMemoryOverallocationCreateInfoAMD *overallocation = (const void *)ext;
2542 if (overallocation->overallocationBehavior == VK_MEMORY_OVERALLOCATION_BEHAVIOR_DISALLOWED_AMD)
2543 overallocation_disallowed = true;
2544 break;
2545 }
2546 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_FEATURES_EXT: {
2547 const VkPhysicalDeviceCustomBorderColorFeaturesEXT *border_color_features = (const void *)ext;
2548 custom_border_colors = border_color_features->customBorderColors;
2549 break;
2550 }
2551 default:
2552 break;
2553 }
2554 }
2555
2556 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
2557 sizeof(*device), 8,
2558 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2559 if (!device)
2560 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2561
2562 vk_device_init(&device->vk, pCreateInfo,
2563 &physical_device->instance->alloc, pAllocator);
2564
2565 device->instance = physical_device->instance;
2566 device->physical_device = physical_device;
2567
2568 device->ws = physical_device->ws;
2569
2570 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
2571 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
2572 int index = radv_get_device_extension_index(ext_name);
2573 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
2574 vk_free(&device->vk.alloc, device);
2575 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
2576 }
2577
2578 device->enabled_extensions.extensions[index] = true;
2579 }
2580
2581 radv_device_init_dispatch(device);
2582
2583 keep_shader_info = device->enabled_extensions.AMD_shader_info;
2584
2585 /* With update after bind we can't attach bo's to the command buffer
2586 * from the descriptor set anymore, so we have to use a global BO list.
2587 */
2588 device->use_global_bo_list =
2589 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
2590 device->enabled_extensions.EXT_descriptor_indexing ||
2591 device->enabled_extensions.EXT_buffer_device_address ||
2592 device->enabled_extensions.KHR_buffer_device_address;
2593
2594 device->robust_buffer_access = robust_buffer_access;
2595
2596 mtx_init(&device->shader_slab_mutex, mtx_plain);
2597 list_inithead(&device->shader_slabs);
2598
2599 device->overallocation_disallowed = overallocation_disallowed;
2600 mtx_init(&device->overallocation_mutex, mtx_plain);
2601
2602 radv_bo_list_init(&device->bo_list);
2603
2604 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
2605 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
2606 uint32_t qfi = queue_create->queueFamilyIndex;
2607 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
2608 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
2609
2610 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
2611
2612 device->queues[qfi] = vk_alloc(&device->vk.alloc,
2613 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2614 if (!device->queues[qfi]) {
2615 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2616 goto fail;
2617 }
2618
2619 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
2620
2621 device->queue_count[qfi] = queue_create->queueCount;
2622
2623 for (unsigned q = 0; q < queue_create->queueCount; q++) {
2624 result = radv_queue_init(device, &device->queues[qfi][q],
2625 qfi, q, queue_create->flags,
2626 global_priority);
2627 if (result != VK_SUCCESS)
2628 goto fail;
2629 }
2630 }
2631
2632 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
2633 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
2634
2635 /* Disable DFSM by default. As of 2019-09-15 Talos on Low is still 3% slower on Raven. */
2636 device->dfsm_allowed = device->pbb_allowed &&
2637 (device->instance->perftest_flags & RADV_PERFTEST_DFSM);
2638
2639 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
2640
2641 /* The maximum number of scratch waves. Scratch space isn't divided
2642 * evenly between CUs. The number is only a function of the number of CUs.
2643 * We can decrease the constant to decrease the scratch buffer size.
2644 *
2645 * sctx->scratch_waves must be >= the maximum possible size of
2646 * 1 threadgroup, so that the hw doesn't hang from being unable
2647 * to start any.
2648 *
2649 * The recommended value is 4 per CU at most. Higher numbers don't
2650 * bring much benefit, but they still occupy chip resources (think
2651 * async compute). I've seen ~2% performance difference between 4 and 32.
2652 */
2653 uint32_t max_threads_per_block = 2048;
2654 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
2655 max_threads_per_block / 64);
2656
2657 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
2658
2659 if (device->physical_device->rad_info.chip_class >= GFX7) {
2660 /* If the KMD allows it (there is a KMD hw register for it),
2661 * allow launching waves out-of-order.
2662 */
2663 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
2664 }
2665
2666 radv_device_init_gs_info(device);
2667
2668 device->tess_offchip_block_dw_size =
2669 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
2670
2671 if (getenv("RADV_TRACE_FILE")) {
2672 const char *filename = getenv("RADV_TRACE_FILE");
2673
2674 keep_shader_info = true;
2675
2676 if (!radv_init_trace(device))
2677 goto fail;
2678
2679 fprintf(stderr, "*****************************************************************************\n");
2680 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
2681 fprintf(stderr, "*****************************************************************************\n");
2682
2683 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
2684 radv_dump_enabled_options(device, stderr);
2685 }
2686
2687 int radv_thread_trace = radv_get_int_debug_option("RADV_THREAD_TRACE", -1);
2688 if (radv_thread_trace >= 0) {
2689 fprintf(stderr, "*************************************************\n");
2690 fprintf(stderr, "* WARNING: Thread trace support is experimental *\n");
2691 fprintf(stderr, "*************************************************\n");
2692
2693 if (device->physical_device->rad_info.chip_class < GFX8) {
2694 fprintf(stderr, "GPU hardware not supported: refer to "
2695 "the RGP documentation for the list of "
2696 "supported GPUs!\n");
2697 abort();
2698 }
2699
2700 /* Default buffer size set to 1MB per SE. */
2701 device->thread_trace_buffer_size =
2702 radv_get_int_debug_option("RADV_THREAD_TRACE_BUFFER_SIZE", 1024 * 1024);
2703 device->thread_trace_start_frame = radv_thread_trace;
2704
2705 if (!radv_thread_trace_init(device))
2706 goto fail;
2707 }
2708
2709 device->keep_shader_info = keep_shader_info;
2710 result = radv_device_init_meta(device);
2711 if (result != VK_SUCCESS)
2712 goto fail;
2713
2714 radv_device_init_msaa(device);
2715
2716 /* If the border color extension is enabled, let's create the buffer we need. */
2717 if (custom_border_colors) {
2718 result = radv_device_init_border_color(device);
2719 if (result != VK_SUCCESS)
2720 goto fail;
2721 }
2722
2723 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
2724 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
2725 if (!device->empty_cs[family])
2726 goto fail;
2727
2728 switch (family) {
2729 case RADV_QUEUE_GENERAL:
2730 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2731 radeon_emit(device->empty_cs[family], CC0_UPDATE_LOAD_ENABLES(1));
2732 radeon_emit(device->empty_cs[family], CC1_UPDATE_SHADOW_ENABLES(1));
2733 break;
2734 case RADV_QUEUE_COMPUTE:
2735 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
2736 radeon_emit(device->empty_cs[family], 0);
2737 break;
2738 }
2739
2740 result = device->ws->cs_finalize(device->empty_cs[family]);
2741 if (result != VK_SUCCESS)
2742 goto fail;
2743 }
2744
2745 if (device->physical_device->rad_info.chip_class >= GFX7)
2746 cik_create_gfx_config(device);
2747
2748 VkPipelineCacheCreateInfo ci;
2749 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
2750 ci.pNext = NULL;
2751 ci.flags = 0;
2752 ci.pInitialData = NULL;
2753 ci.initialDataSize = 0;
2754 VkPipelineCache pc;
2755 result = radv_CreatePipelineCache(radv_device_to_handle(device),
2756 &ci, NULL, &pc);
2757 if (result != VK_SUCCESS)
2758 goto fail_meta;
2759
2760 device->mem_cache = radv_pipeline_cache_from_handle(pc);
2761
2762 result = radv_create_pthread_cond(&device->timeline_cond);
2763 if (result != VK_SUCCESS)
2764 goto fail_mem_cache;
2765
2766 device->force_aniso =
2767 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
2768 if (device->force_aniso >= 0) {
2769 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
2770 1 << util_logbase2(device->force_aniso));
2771 }
2772
2773 *pDevice = radv_device_to_handle(device);
2774 return VK_SUCCESS;
2775
2776 fail_mem_cache:
2777 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2778 fail_meta:
2779 radv_device_finish_meta(device);
2780 fail:
2781 radv_bo_list_finish(&device->bo_list);
2782
2783 radv_thread_trace_finish(device);
2784
2785 if (device->trace_bo)
2786 device->ws->buffer_destroy(device->trace_bo);
2787
2788 if (device->gfx_init)
2789 device->ws->buffer_destroy(device->gfx_init);
2790
2791 radv_device_finish_border_color(device);
2792
2793 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2794 for (unsigned q = 0; q < device->queue_count[i]; q++)
2795 radv_queue_finish(&device->queues[i][q]);
2796 if (device->queue_count[i])
2797 vk_free(&device->vk.alloc, device->queues[i]);
2798 }
2799
2800 vk_free(&device->vk.alloc, device);
2801 return result;
2802 }
2803
2804 void radv_DestroyDevice(
2805 VkDevice _device,
2806 const VkAllocationCallbacks* pAllocator)
2807 {
2808 RADV_FROM_HANDLE(radv_device, device, _device);
2809
2810 if (!device)
2811 return;
2812
2813 if (device->trace_bo)
2814 device->ws->buffer_destroy(device->trace_bo);
2815
2816 if (device->gfx_init)
2817 device->ws->buffer_destroy(device->gfx_init);
2818
2819 radv_device_finish_border_color(device);
2820
2821 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2822 for (unsigned q = 0; q < device->queue_count[i]; q++)
2823 radv_queue_finish(&device->queues[i][q]);
2824 if (device->queue_count[i])
2825 vk_free(&device->vk.alloc, device->queues[i]);
2826 if (device->empty_cs[i])
2827 device->ws->cs_destroy(device->empty_cs[i]);
2828 }
2829 radv_device_finish_meta(device);
2830
2831 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
2832 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2833
2834 radv_destroy_shader_slabs(device);
2835
2836 pthread_cond_destroy(&device->timeline_cond);
2837 radv_bo_list_finish(&device->bo_list);
2838
2839 radv_thread_trace_finish(device);
2840
2841 vk_free(&device->vk.alloc, device);
2842 }
2843
2844 VkResult radv_EnumerateInstanceLayerProperties(
2845 uint32_t* pPropertyCount,
2846 VkLayerProperties* pProperties)
2847 {
2848 if (pProperties == NULL) {
2849 *pPropertyCount = 0;
2850 return VK_SUCCESS;
2851 }
2852
2853 /* None supported at this time */
2854 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2855 }
2856
2857 VkResult radv_EnumerateDeviceLayerProperties(
2858 VkPhysicalDevice physicalDevice,
2859 uint32_t* pPropertyCount,
2860 VkLayerProperties* pProperties)
2861 {
2862 if (pProperties == NULL) {
2863 *pPropertyCount = 0;
2864 return VK_SUCCESS;
2865 }
2866
2867 /* None supported at this time */
2868 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2869 }
2870
2871 void radv_GetDeviceQueue2(
2872 VkDevice _device,
2873 const VkDeviceQueueInfo2* pQueueInfo,
2874 VkQueue* pQueue)
2875 {
2876 RADV_FROM_HANDLE(radv_device, device, _device);
2877 struct radv_queue *queue;
2878
2879 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
2880 if (pQueueInfo->flags != queue->flags) {
2881 /* From the Vulkan 1.1.70 spec:
2882 *
2883 * "The queue returned by vkGetDeviceQueue2 must have the same
2884 * flags value from this structure as that used at device
2885 * creation time in a VkDeviceQueueCreateInfo instance. If no
2886 * matching flags were specified at device creation time then
2887 * pQueue will return VK_NULL_HANDLE."
2888 */
2889 *pQueue = VK_NULL_HANDLE;
2890 return;
2891 }
2892
2893 *pQueue = radv_queue_to_handle(queue);
2894 }
2895
2896 void radv_GetDeviceQueue(
2897 VkDevice _device,
2898 uint32_t queueFamilyIndex,
2899 uint32_t queueIndex,
2900 VkQueue* pQueue)
2901 {
2902 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
2903 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
2904 .queueFamilyIndex = queueFamilyIndex,
2905 .queueIndex = queueIndex
2906 };
2907
2908 radv_GetDeviceQueue2(_device, &info, pQueue);
2909 }
2910
2911 static void
2912 fill_geom_tess_rings(struct radv_queue *queue,
2913 uint32_t *map,
2914 bool add_sample_positions,
2915 uint32_t esgs_ring_size,
2916 struct radeon_winsys_bo *esgs_ring_bo,
2917 uint32_t gsvs_ring_size,
2918 struct radeon_winsys_bo *gsvs_ring_bo,
2919 uint32_t tess_factor_ring_size,
2920 uint32_t tess_offchip_ring_offset,
2921 uint32_t tess_offchip_ring_size,
2922 struct radeon_winsys_bo *tess_rings_bo)
2923 {
2924 uint32_t *desc = &map[4];
2925
2926 if (esgs_ring_bo) {
2927 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
2928
2929 /* stride 0, num records - size, add tid, swizzle, elsize4,
2930 index stride 64 */
2931 desc[0] = esgs_va;
2932 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
2933 S_008F04_SWIZZLE_ENABLE(true);
2934 desc[2] = esgs_ring_size;
2935 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2936 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2937 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2938 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2939 S_008F0C_INDEX_STRIDE(3) |
2940 S_008F0C_ADD_TID_ENABLE(1);
2941
2942 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2943 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2944 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
2945 S_008F0C_RESOURCE_LEVEL(1);
2946 } else {
2947 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2948 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2949 S_008F0C_ELEMENT_SIZE(1);
2950 }
2951
2952 /* GS entry for ES->GS ring */
2953 /* stride 0, num records - size, elsize0,
2954 index stride 0 */
2955 desc[4] = esgs_va;
2956 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32);
2957 desc[6] = esgs_ring_size;
2958 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2959 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2960 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2961 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2962
2963 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2964 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2965 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
2966 S_008F0C_RESOURCE_LEVEL(1);
2967 } else {
2968 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2969 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2970 }
2971 }
2972
2973 desc += 8;
2974
2975 if (gsvs_ring_bo) {
2976 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
2977
2978 /* VS entry for GS->VS ring */
2979 /* stride 0, num records - size, elsize0,
2980 index stride 0 */
2981 desc[0] = gsvs_va;
2982 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32);
2983 desc[2] = gsvs_ring_size;
2984 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2985 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2986 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2987 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2988
2989 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2990 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2991 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
2992 S_008F0C_RESOURCE_LEVEL(1);
2993 } else {
2994 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2995 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2996 }
2997
2998 /* stride gsvs_itemsize, num records 64
2999 elsize 4, index stride 16 */
3000 /* shader will patch stride and desc[2] */
3001 desc[4] = gsvs_va;
3002 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32) |
3003 S_008F04_SWIZZLE_ENABLE(1);
3004 desc[6] = 0;
3005 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3006 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3007 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3008 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
3009 S_008F0C_INDEX_STRIDE(1) |
3010 S_008F0C_ADD_TID_ENABLE(true);
3011
3012 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3013 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3014 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3015 S_008F0C_RESOURCE_LEVEL(1);
3016 } else {
3017 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3018 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
3019 S_008F0C_ELEMENT_SIZE(1);
3020 }
3021
3022 }
3023
3024 desc += 8;