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[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "gfx9d.h"
47 #include "addrlib/gfx9/chip/gfx9_enum.h"
48 #include "util/debug.h"
49
50 static int
51 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
52 {
53 uint32_t mesa_timestamp, llvm_timestamp;
54 uint16_t f = family;
55 memset(uuid, 0, VK_UUID_SIZE);
56 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
57 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
58 return -1;
59
60 memcpy(uuid, &mesa_timestamp, 4);
61 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
62 memcpy((char*)uuid + 8, &f, 2);
63 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
64 return 0;
65 }
66
67 static void
68 radv_get_driver_uuid(void *uuid)
69 {
70 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
71 }
72
73 static void
74 radv_get_device_uuid(struct radeon_info *info, void *uuid)
75 {
76 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
77 }
78
79 static void
80 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
81 {
82 const char *chip_string;
83 char llvm_string[32] = {};
84
85 switch (family) {
86 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
87 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
88 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
89 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
90 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
91 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
92 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
93 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
94 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
95 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
96 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
97 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
98 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
99 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
100 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
101 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
102 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
103 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
104 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
105 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
106 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
107 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
108 default: chip_string = "AMD RADV unknown"; break;
109 }
110
111 snprintf(llvm_string, sizeof(llvm_string),
112 " (LLVM %i.%i.%i)", (HAVE_LLVM >> 8) & 0xff,
113 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
114 snprintf(name, name_len, "%s%s", chip_string, llvm_string);
115 }
116
117 static void
118 radv_physical_device_init_mem_types(struct radv_physical_device *device)
119 {
120 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
121 uint64_t visible_vram_size = MIN2(device->rad_info.vram_size,
122 device->rad_info.vram_vis_size);
123
124 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
125 device->memory_properties.memoryHeapCount = 0;
126 if (device->rad_info.vram_size - visible_vram_size > 0) {
127 vram_index = device->memory_properties.memoryHeapCount++;
128 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
129 .size = device->rad_info.vram_size - visible_vram_size,
130 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
131 };
132 }
133 if (visible_vram_size) {
134 visible_vram_index = device->memory_properties.memoryHeapCount++;
135 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
136 .size = visible_vram_size,
137 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
138 };
139 }
140 if (device->rad_info.gart_size > 0) {
141 gart_index = device->memory_properties.memoryHeapCount++;
142 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
143 .size = device->rad_info.gart_size,
144 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
145 };
146 }
147
148 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
149 unsigned type_count = 0;
150 if (vram_index >= 0) {
151 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
152 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
153 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
154 .heapIndex = vram_index,
155 };
156 }
157 if (gart_index >= 0) {
158 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
159 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
160 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
161 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
162 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
163 .heapIndex = gart_index,
164 };
165 }
166 if (visible_vram_index >= 0) {
167 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
168 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
169 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
170 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
171 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
172 .heapIndex = visible_vram_index,
173 };
174 }
175 if (gart_index >= 0) {
176 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
177 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
178 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
179 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
180 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
181 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
182 .heapIndex = gart_index,
183 };
184 }
185 device->memory_properties.memoryTypeCount = type_count;
186 }
187
188 static void
189 radv_handle_env_var_force_family(struct radv_physical_device *device)
190 {
191 const char *family = getenv("RADV_FORCE_FAMILY");
192 unsigned i;
193
194 if (!family)
195 return;
196
197 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
198 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
199 /* Override family and chip_class. */
200 device->rad_info.family = i;
201
202 if (i >= CHIP_VEGA10)
203 device->rad_info.chip_class = GFX9;
204 else if (i >= CHIP_TONGA)
205 device->rad_info.chip_class = VI;
206 else if (i >= CHIP_BONAIRE)
207 device->rad_info.chip_class = CIK;
208 else
209 device->rad_info.chip_class = SI;
210
211 return;
212 }
213 }
214
215 fprintf(stderr, "radv: Unknown family: %s\n", family);
216 exit(1);
217 }
218
219 static VkResult
220 radv_physical_device_init(struct radv_physical_device *device,
221 struct radv_instance *instance,
222 drmDevicePtr drm_device)
223 {
224 const char *path = drm_device->nodes[DRM_NODE_RENDER];
225 VkResult result;
226 drmVersionPtr version;
227 int fd;
228
229 fd = open(path, O_RDWR | O_CLOEXEC);
230 if (fd < 0) {
231 if (instance->debug_flags & RADV_DEBUG_STARTUP)
232 radv_logi("Could not open device '%s'", path);
233
234 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
235 }
236
237 version = drmGetVersion(fd);
238 if (!version) {
239 close(fd);
240
241 if (instance->debug_flags & RADV_DEBUG_STARTUP)
242 radv_logi("Could not get the kernel driver version for device '%s'", path);
243
244 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
245 "failed to get version %s: %m", path);
246 }
247
248 if (strcmp(version->name, "amdgpu")) {
249 drmFreeVersion(version);
250 close(fd);
251
252 if (instance->debug_flags & RADV_DEBUG_STARTUP)
253 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
254
255 return VK_ERROR_INCOMPATIBLE_DRIVER;
256 }
257 drmFreeVersion(version);
258
259 if (instance->debug_flags & RADV_DEBUG_STARTUP)
260 radv_logi("Found compatible device '%s'.", path);
261
262 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
263 device->instance = instance;
264 assert(strlen(path) < ARRAY_SIZE(device->path));
265 strncpy(device->path, path, ARRAY_SIZE(device->path));
266
267 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
268 instance->perftest_flags);
269 if (!device->ws) {
270 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
271 goto fail;
272 }
273
274 device->local_fd = fd;
275 device->ws->query_info(device->ws, &device->rad_info);
276
277 radv_handle_env_var_force_family(device);
278
279 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
280
281 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
282 device->ws->destroy(device->ws);
283 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
284 "cannot generate UUID");
285 goto fail;
286 }
287
288 /* These flags affect shader compilation. */
289 uint64_t shader_env_flags =
290 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
291 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
292
293 /* The gpu id is already embedded in the uuid so we just pass "radv"
294 * when creating the cache.
295 */
296 char buf[VK_UUID_SIZE * 2 + 1];
297 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
298 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
299
300 if (device->rad_info.chip_class < VI ||
301 device->rad_info.chip_class > GFX9)
302 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
303
304 radv_get_driver_uuid(&device->device_uuid);
305 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
306
307 if (device->rad_info.family == CHIP_STONEY ||
308 device->rad_info.chip_class >= GFX9) {
309 device->has_rbplus = true;
310 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
311 device->rad_info.family == CHIP_VEGA12 ||
312 device->rad_info.family == CHIP_RAVEN;
313 }
314
315 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
316 * on SI.
317 */
318 device->has_clear_state = device->rad_info.chip_class >= CIK;
319
320 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
321
322 /* Vega10/Raven need a special workaround for a hardware bug. */
323 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
324 device->rad_info.family == CHIP_RAVEN;
325
326 /* Out-of-order primitive rasterization. */
327 device->has_out_of_order_rast = device->rad_info.chip_class >= VI &&
328 device->rad_info.max_se >= 2;
329 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
330 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
331
332 device->dcc_msaa_allowed =
333 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
334
335 radv_physical_device_init_mem_types(device);
336 radv_fill_device_extension_table(device, &device->supported_extensions);
337
338 result = radv_init_wsi(device);
339 if (result != VK_SUCCESS) {
340 device->ws->destroy(device->ws);
341 vk_error(instance, result);
342 goto fail;
343 }
344
345 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
346 ac_print_gpu_info(&device->rad_info);
347
348 return VK_SUCCESS;
349
350 fail:
351 close(fd);
352 return result;
353 }
354
355 static void
356 radv_physical_device_finish(struct radv_physical_device *device)
357 {
358 radv_finish_wsi(device);
359 device->ws->destroy(device->ws);
360 disk_cache_destroy(device->disk_cache);
361 close(device->local_fd);
362 }
363
364 static void *
365 default_alloc_func(void *pUserData, size_t size, size_t align,
366 VkSystemAllocationScope allocationScope)
367 {
368 return malloc(size);
369 }
370
371 static void *
372 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
373 size_t align, VkSystemAllocationScope allocationScope)
374 {
375 return realloc(pOriginal, size);
376 }
377
378 static void
379 default_free_func(void *pUserData, void *pMemory)
380 {
381 free(pMemory);
382 }
383
384 static const VkAllocationCallbacks default_alloc = {
385 .pUserData = NULL,
386 .pfnAllocation = default_alloc_func,
387 .pfnReallocation = default_realloc_func,
388 .pfnFree = default_free_func,
389 };
390
391 static const struct debug_control radv_debug_options[] = {
392 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
393 {"nodcc", RADV_DEBUG_NO_DCC},
394 {"shaders", RADV_DEBUG_DUMP_SHADERS},
395 {"nocache", RADV_DEBUG_NO_CACHE},
396 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
397 {"nohiz", RADV_DEBUG_NO_HIZ},
398 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
399 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
400 {"allbos", RADV_DEBUG_ALL_BOS},
401 {"noibs", RADV_DEBUG_NO_IBS},
402 {"spirv", RADV_DEBUG_DUMP_SPIRV},
403 {"vmfaults", RADV_DEBUG_VM_FAULTS},
404 {"zerovram", RADV_DEBUG_ZERO_VRAM},
405 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
406 {"nosisched", RADV_DEBUG_NO_SISCHED},
407 {"preoptir", RADV_DEBUG_PREOPTIR},
408 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
409 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
410 {"info", RADV_DEBUG_INFO},
411 {"errors", RADV_DEBUG_ERRORS},
412 {"startup", RADV_DEBUG_STARTUP},
413 {"checkir", RADV_DEBUG_CHECKIR},
414 {NULL, 0}
415 };
416
417 const char *
418 radv_get_debug_option_name(int id)
419 {
420 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
421 return radv_debug_options[id].string;
422 }
423
424 static const struct debug_control radv_perftest_options[] = {
425 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
426 {"sisched", RADV_PERFTEST_SISCHED},
427 {"localbos", RADV_PERFTEST_LOCAL_BOS},
428 {"binning", RADV_PERFTEST_BINNING},
429 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
430 {NULL, 0}
431 };
432
433 const char *
434 radv_get_perftest_option_name(int id)
435 {
436 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
437 return radv_perftest_options[id].string;
438 }
439
440 static void
441 radv_handle_per_app_options(struct radv_instance *instance,
442 const VkApplicationInfo *info)
443 {
444 const char *name = info ? info->pApplicationName : NULL;
445
446 if (!name)
447 return;
448
449 if (!strcmp(name, "Talos - Linux - 32bit") ||
450 !strcmp(name, "Talos - Linux - 64bit")) {
451 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
452 /* Force enable LLVM sisched for Talos because it looks
453 * safe and it gives few more FPS.
454 */
455 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
456 }
457 }
458 }
459
460 static int radv_get_instance_extension_index(const char *name)
461 {
462 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
463 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
464 return i;
465 }
466 return -1;
467 }
468
469
470 VkResult radv_CreateInstance(
471 const VkInstanceCreateInfo* pCreateInfo,
472 const VkAllocationCallbacks* pAllocator,
473 VkInstance* pInstance)
474 {
475 struct radv_instance *instance;
476 VkResult result;
477
478 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
479
480 uint32_t client_version;
481 if (pCreateInfo->pApplicationInfo &&
482 pCreateInfo->pApplicationInfo->apiVersion != 0) {
483 client_version = pCreateInfo->pApplicationInfo->apiVersion;
484 } else {
485 radv_EnumerateInstanceVersion(&client_version);
486 }
487
488 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
489 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
490 if (!instance)
491 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
492
493 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
494
495 if (pAllocator)
496 instance->alloc = *pAllocator;
497 else
498 instance->alloc = default_alloc;
499
500 instance->apiVersion = client_version;
501 instance->physicalDeviceCount = -1;
502
503 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
504 radv_debug_options);
505
506 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
507 radv_perftest_options);
508
509
510 if (instance->debug_flags & RADV_DEBUG_STARTUP)
511 radv_logi("Created an instance");
512
513 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
514 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
515 int index = radv_get_instance_extension_index(ext_name);
516
517 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
518 vk_free2(&default_alloc, pAllocator, instance);
519 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
520 }
521
522 instance->enabled_extensions.extensions[index] = true;
523 }
524
525 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
526 if (result != VK_SUCCESS) {
527 vk_free2(&default_alloc, pAllocator, instance);
528 return vk_error(instance, result);
529 }
530
531 _mesa_locale_init();
532
533 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
534
535 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
536
537 *pInstance = radv_instance_to_handle(instance);
538
539 return VK_SUCCESS;
540 }
541
542 void radv_DestroyInstance(
543 VkInstance _instance,
544 const VkAllocationCallbacks* pAllocator)
545 {
546 RADV_FROM_HANDLE(radv_instance, instance, _instance);
547
548 if (!instance)
549 return;
550
551 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
552 radv_physical_device_finish(instance->physicalDevices + i);
553 }
554
555 VG(VALGRIND_DESTROY_MEMPOOL(instance));
556
557 _mesa_locale_fini();
558
559 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
560
561 vk_free(&instance->alloc, instance);
562 }
563
564 static VkResult
565 radv_enumerate_devices(struct radv_instance *instance)
566 {
567 /* TODO: Check for more devices ? */
568 drmDevicePtr devices[8];
569 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
570 int max_devices;
571
572 instance->physicalDeviceCount = 0;
573
574 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
575
576 if (instance->debug_flags & RADV_DEBUG_STARTUP)
577 radv_logi("Found %d drm nodes", max_devices);
578
579 if (max_devices < 1)
580 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
581
582 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
583 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
584 devices[i]->bustype == DRM_BUS_PCI &&
585 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
586
587 result = radv_physical_device_init(instance->physicalDevices +
588 instance->physicalDeviceCount,
589 instance,
590 devices[i]);
591 if (result == VK_SUCCESS)
592 ++instance->physicalDeviceCount;
593 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
594 break;
595 }
596 }
597 drmFreeDevices(devices, max_devices);
598
599 return result;
600 }
601
602 VkResult radv_EnumeratePhysicalDevices(
603 VkInstance _instance,
604 uint32_t* pPhysicalDeviceCount,
605 VkPhysicalDevice* pPhysicalDevices)
606 {
607 RADV_FROM_HANDLE(radv_instance, instance, _instance);
608 VkResult result;
609
610 if (instance->physicalDeviceCount < 0) {
611 result = radv_enumerate_devices(instance);
612 if (result != VK_SUCCESS &&
613 result != VK_ERROR_INCOMPATIBLE_DRIVER)
614 return result;
615 }
616
617 if (!pPhysicalDevices) {
618 *pPhysicalDeviceCount = instance->physicalDeviceCount;
619 } else {
620 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
621 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
622 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
623 }
624
625 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
626 : VK_SUCCESS;
627 }
628
629 VkResult radv_EnumeratePhysicalDeviceGroups(
630 VkInstance _instance,
631 uint32_t* pPhysicalDeviceGroupCount,
632 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
633 {
634 RADV_FROM_HANDLE(radv_instance, instance, _instance);
635 VkResult result;
636
637 if (instance->physicalDeviceCount < 0) {
638 result = radv_enumerate_devices(instance);
639 if (result != VK_SUCCESS &&
640 result != VK_ERROR_INCOMPATIBLE_DRIVER)
641 return result;
642 }
643
644 if (!pPhysicalDeviceGroupProperties) {
645 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
646 } else {
647 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
648 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
649 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
650 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
651 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
652 }
653 }
654 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
655 : VK_SUCCESS;
656 }
657
658 void radv_GetPhysicalDeviceFeatures(
659 VkPhysicalDevice physicalDevice,
660 VkPhysicalDeviceFeatures* pFeatures)
661 {
662 memset(pFeatures, 0, sizeof(*pFeatures));
663
664 *pFeatures = (VkPhysicalDeviceFeatures) {
665 .robustBufferAccess = true,
666 .fullDrawIndexUint32 = true,
667 .imageCubeArray = true,
668 .independentBlend = true,
669 .geometryShader = true,
670 .tessellationShader = true,
671 .sampleRateShading = true,
672 .dualSrcBlend = true,
673 .logicOp = true,
674 .multiDrawIndirect = true,
675 .drawIndirectFirstInstance = true,
676 .depthClamp = true,
677 .depthBiasClamp = true,
678 .fillModeNonSolid = true,
679 .depthBounds = true,
680 .wideLines = true,
681 .largePoints = true,
682 .alphaToOne = true,
683 .multiViewport = true,
684 .samplerAnisotropy = true,
685 .textureCompressionETC2 = false,
686 .textureCompressionASTC_LDR = false,
687 .textureCompressionBC = true,
688 .occlusionQueryPrecise = true,
689 .pipelineStatisticsQuery = true,
690 .vertexPipelineStoresAndAtomics = true,
691 .fragmentStoresAndAtomics = true,
692 .shaderTessellationAndGeometryPointSize = true,
693 .shaderImageGatherExtended = true,
694 .shaderStorageImageExtendedFormats = true,
695 .shaderStorageImageMultisample = false,
696 .shaderUniformBufferArrayDynamicIndexing = true,
697 .shaderSampledImageArrayDynamicIndexing = true,
698 .shaderStorageBufferArrayDynamicIndexing = true,
699 .shaderStorageImageArrayDynamicIndexing = true,
700 .shaderStorageImageReadWithoutFormat = true,
701 .shaderStorageImageWriteWithoutFormat = true,
702 .shaderClipDistance = true,
703 .shaderCullDistance = true,
704 .shaderFloat64 = true,
705 .shaderInt64 = true,
706 .shaderInt16 = false,
707 .sparseBinding = true,
708 .variableMultisampleRate = true,
709 .inheritedQueries = true,
710 };
711 }
712
713 void radv_GetPhysicalDeviceFeatures2(
714 VkPhysicalDevice physicalDevice,
715 VkPhysicalDeviceFeatures2KHR *pFeatures)
716 {
717 vk_foreach_struct(ext, pFeatures->pNext) {
718 switch (ext->sType) {
719 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
720 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
721 features->variablePointersStorageBuffer = true;
722 features->variablePointers = false;
723 break;
724 }
725 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHR: {
726 VkPhysicalDeviceMultiviewFeaturesKHR *features = (VkPhysicalDeviceMultiviewFeaturesKHR*)ext;
727 features->multiview = true;
728 features->multiviewGeometryShader = true;
729 features->multiviewTessellationShader = true;
730 break;
731 }
732 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETER_FEATURES: {
733 VkPhysicalDeviceShaderDrawParameterFeatures *features =
734 (VkPhysicalDeviceShaderDrawParameterFeatures*)ext;
735 features->shaderDrawParameters = true;
736 break;
737 }
738 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
739 VkPhysicalDeviceProtectedMemoryFeatures *features =
740 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
741 features->protectedMemory = false;
742 break;
743 }
744 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
745 VkPhysicalDevice16BitStorageFeatures *features =
746 (VkPhysicalDevice16BitStorageFeatures*)ext;
747 features->storageBuffer16BitAccess = false;
748 features->uniformAndStorageBuffer16BitAccess = false;
749 features->storagePushConstant16 = false;
750 features->storageInputOutput16 = false;
751 break;
752 }
753 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
754 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
755 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
756 features->samplerYcbcrConversion = false;
757 break;
758 }
759 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
760 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
761 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
762 features->shaderInputAttachmentArrayDynamicIndexing = true;
763 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
764 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
765 features->shaderUniformBufferArrayNonUniformIndexing = false;
766 features->shaderSampledImageArrayNonUniformIndexing = false;
767 features->shaderStorageBufferArrayNonUniformIndexing = false;
768 features->shaderStorageImageArrayNonUniformIndexing = false;
769 features->shaderInputAttachmentArrayNonUniformIndexing = false;
770 features->shaderUniformTexelBufferArrayNonUniformIndexing = false;
771 features->shaderStorageTexelBufferArrayNonUniformIndexing = false;
772 features->descriptorBindingUniformBufferUpdateAfterBind = true;
773 features->descriptorBindingSampledImageUpdateAfterBind = true;
774 features->descriptorBindingStorageImageUpdateAfterBind = true;
775 features->descriptorBindingStorageBufferUpdateAfterBind = true;
776 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
777 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
778 features->descriptorBindingUpdateUnusedWhilePending = true;
779 features->descriptorBindingPartiallyBound = true;
780 features->descriptorBindingVariableDescriptorCount = true;
781 features->runtimeDescriptorArray = true;
782 break;
783 }
784 default:
785 break;
786 }
787 }
788 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
789 }
790
791 void radv_GetPhysicalDeviceProperties(
792 VkPhysicalDevice physicalDevice,
793 VkPhysicalDeviceProperties* pProperties)
794 {
795 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
796 VkSampleCountFlags sample_counts = 0xf;
797
798 /* make sure that the entire descriptor set is addressable with a signed
799 * 32-bit int. So the sum of all limits scaled by descriptor size has to
800 * be at most 2 GiB. the combined image & samples object count as one of
801 * both. This limit is for the pipeline layout, not for the set layout, but
802 * there is no set limit, so we just set a pipeline limit. I don't think
803 * any app is going to hit this soon. */
804 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
805 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
806 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
807 32 /* sampler, largest when combined with image */ +
808 64 /* sampled image */ +
809 64 /* storage image */);
810
811 VkPhysicalDeviceLimits limits = {
812 .maxImageDimension1D = (1 << 14),
813 .maxImageDimension2D = (1 << 14),
814 .maxImageDimension3D = (1 << 11),
815 .maxImageDimensionCube = (1 << 14),
816 .maxImageArrayLayers = (1 << 11),
817 .maxTexelBufferElements = 128 * 1024 * 1024,
818 .maxUniformBufferRange = UINT32_MAX,
819 .maxStorageBufferRange = UINT32_MAX,
820 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
821 .maxMemoryAllocationCount = UINT32_MAX,
822 .maxSamplerAllocationCount = 64 * 1024,
823 .bufferImageGranularity = 64, /* A cache line */
824 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
825 .maxBoundDescriptorSets = MAX_SETS,
826 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
827 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
828 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
829 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
830 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
831 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
832 .maxPerStageResources = max_descriptor_set_size,
833 .maxDescriptorSetSamplers = max_descriptor_set_size,
834 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
835 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
836 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
837 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
838 .maxDescriptorSetSampledImages = max_descriptor_set_size,
839 .maxDescriptorSetStorageImages = max_descriptor_set_size,
840 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
841 .maxVertexInputAttributes = 32,
842 .maxVertexInputBindings = 32,
843 .maxVertexInputAttributeOffset = 2047,
844 .maxVertexInputBindingStride = 2048,
845 .maxVertexOutputComponents = 128,
846 .maxTessellationGenerationLevel = 64,
847 .maxTessellationPatchSize = 32,
848 .maxTessellationControlPerVertexInputComponents = 128,
849 .maxTessellationControlPerVertexOutputComponents = 128,
850 .maxTessellationControlPerPatchOutputComponents = 120,
851 .maxTessellationControlTotalOutputComponents = 4096,
852 .maxTessellationEvaluationInputComponents = 128,
853 .maxTessellationEvaluationOutputComponents = 128,
854 .maxGeometryShaderInvocations = 127,
855 .maxGeometryInputComponents = 64,
856 .maxGeometryOutputComponents = 128,
857 .maxGeometryOutputVertices = 256,
858 .maxGeometryTotalOutputComponents = 1024,
859 .maxFragmentInputComponents = 128,
860 .maxFragmentOutputAttachments = 8,
861 .maxFragmentDualSrcAttachments = 1,
862 .maxFragmentCombinedOutputResources = 8,
863 .maxComputeSharedMemorySize = 32768,
864 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
865 .maxComputeWorkGroupInvocations = 2048,
866 .maxComputeWorkGroupSize = {
867 2048,
868 2048,
869 2048
870 },
871 .subPixelPrecisionBits = 4 /* FIXME */,
872 .subTexelPrecisionBits = 4 /* FIXME */,
873 .mipmapPrecisionBits = 4 /* FIXME */,
874 .maxDrawIndexedIndexValue = UINT32_MAX,
875 .maxDrawIndirectCount = UINT32_MAX,
876 .maxSamplerLodBias = 16,
877 .maxSamplerAnisotropy = 16,
878 .maxViewports = MAX_VIEWPORTS,
879 .maxViewportDimensions = { (1 << 14), (1 << 14) },
880 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
881 .viewportSubPixelBits = 8,
882 .minMemoryMapAlignment = 4096, /* A page */
883 .minTexelBufferOffsetAlignment = 1,
884 .minUniformBufferOffsetAlignment = 4,
885 .minStorageBufferOffsetAlignment = 4,
886 .minTexelOffset = -32,
887 .maxTexelOffset = 31,
888 .minTexelGatherOffset = -32,
889 .maxTexelGatherOffset = 31,
890 .minInterpolationOffset = -2,
891 .maxInterpolationOffset = 2,
892 .subPixelInterpolationOffsetBits = 8,
893 .maxFramebufferWidth = (1 << 14),
894 .maxFramebufferHeight = (1 << 14),
895 .maxFramebufferLayers = (1 << 10),
896 .framebufferColorSampleCounts = sample_counts,
897 .framebufferDepthSampleCounts = sample_counts,
898 .framebufferStencilSampleCounts = sample_counts,
899 .framebufferNoAttachmentsSampleCounts = sample_counts,
900 .maxColorAttachments = MAX_RTS,
901 .sampledImageColorSampleCounts = sample_counts,
902 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
903 .sampledImageDepthSampleCounts = sample_counts,
904 .sampledImageStencilSampleCounts = sample_counts,
905 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
906 .maxSampleMaskWords = 1,
907 .timestampComputeAndGraphics = true,
908 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
909 .maxClipDistances = 8,
910 .maxCullDistances = 8,
911 .maxCombinedClipAndCullDistances = 8,
912 .discreteQueuePriorities = 1,
913 .pointSizeRange = { 0.125, 255.875 },
914 .lineWidthRange = { 0.0, 7.9921875 },
915 .pointSizeGranularity = (1.0 / 8.0),
916 .lineWidthGranularity = (1.0 / 128.0),
917 .strictLines = false, /* FINISHME */
918 .standardSampleLocations = true,
919 .optimalBufferCopyOffsetAlignment = 128,
920 .optimalBufferCopyRowPitchAlignment = 128,
921 .nonCoherentAtomSize = 64,
922 };
923
924 *pProperties = (VkPhysicalDeviceProperties) {
925 .apiVersion = radv_physical_device_api_version(pdevice),
926 .driverVersion = vk_get_driver_version(),
927 .vendorID = ATI_VENDOR_ID,
928 .deviceID = pdevice->rad_info.pci_id,
929 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
930 .limits = limits,
931 .sparseProperties = {0},
932 };
933
934 strcpy(pProperties->deviceName, pdevice->name);
935 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
936 }
937
938 void radv_GetPhysicalDeviceProperties2(
939 VkPhysicalDevice physicalDevice,
940 VkPhysicalDeviceProperties2KHR *pProperties)
941 {
942 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
943 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
944
945 vk_foreach_struct(ext, pProperties->pNext) {
946 switch (ext->sType) {
947 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
948 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
949 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
950 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
951 break;
952 }
953 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
954 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
955 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
956 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
957 properties->deviceLUIDValid = false;
958 break;
959 }
960 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHR: {
961 VkPhysicalDeviceMultiviewPropertiesKHR *properties = (VkPhysicalDeviceMultiviewPropertiesKHR*)ext;
962 properties->maxMultiviewViewCount = MAX_VIEWS;
963 properties->maxMultiviewInstanceIndex = INT_MAX;
964 break;
965 }
966 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR: {
967 VkPhysicalDevicePointClippingPropertiesKHR *properties =
968 (VkPhysicalDevicePointClippingPropertiesKHR*)ext;
969 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR;
970 break;
971 }
972 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
973 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
974 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
975 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
976 break;
977 }
978 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
979 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
980 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
981 properties->minImportedHostPointerAlignment = 4096;
982 break;
983 }
984 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
985 VkPhysicalDeviceSubgroupProperties *properties =
986 (VkPhysicalDeviceSubgroupProperties*)ext;
987 properties->subgroupSize = 64;
988 properties->supportedStages = VK_SHADER_STAGE_ALL;
989 properties->supportedOperations =
990 VK_SUBGROUP_FEATURE_BASIC_BIT |
991 VK_SUBGROUP_FEATURE_BALLOT_BIT |
992 VK_SUBGROUP_FEATURE_QUAD_BIT |
993 VK_SUBGROUP_FEATURE_VOTE_BIT;
994 if (pdevice->rad_info.chip_class >= VI) {
995 properties->supportedOperations |=
996 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
997 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
998 }
999 properties->quadOperationsInAllStages = true;
1000 break;
1001 }
1002 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1003 VkPhysicalDeviceMaintenance3Properties *properties =
1004 (VkPhysicalDeviceMaintenance3Properties*)ext;
1005 /* Make sure everything is addressable by a signed 32-bit int, and
1006 * our largest descriptors are 96 bytes. */
1007 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1008 /* Our buffer size fields allow only this much */
1009 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1010 break;
1011 }
1012 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1013 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1014 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1015 /* GFX6-8 only support single channel min/max filter. */
1016 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1017 properties->filterMinmaxSingleComponentFormats = true;
1018 break;
1019 }
1020 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1021 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1022 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1023
1024 /* Shader engines. */
1025 properties->shaderEngineCount =
1026 pdevice->rad_info.max_se;
1027 properties->shaderArraysPerEngineCount =
1028 pdevice->rad_info.max_sh_per_se;
1029 properties->computeUnitsPerShaderArray =
1030 pdevice->rad_info.num_good_compute_units /
1031 (pdevice->rad_info.max_se *
1032 pdevice->rad_info.max_sh_per_se);
1033 properties->simdPerComputeUnit = 4;
1034 properties->wavefrontsPerSimd =
1035 pdevice->rad_info.family == CHIP_TONGA ||
1036 pdevice->rad_info.family == CHIP_ICELAND ||
1037 pdevice->rad_info.family == CHIP_POLARIS10 ||
1038 pdevice->rad_info.family == CHIP_POLARIS11 ||
1039 pdevice->rad_info.family == CHIP_POLARIS12 ||
1040 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1041 properties->wavefrontSize = 64;
1042
1043 /* SGPR. */
1044 properties->sgprsPerSimd =
1045 radv_get_num_physical_sgprs(pdevice);
1046 properties->minSgprAllocation =
1047 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1048 properties->maxSgprAllocation =
1049 pdevice->rad_info.family == CHIP_TONGA ||
1050 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1051 properties->sgprAllocationGranularity =
1052 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1053
1054 /* VGPR. */
1055 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1056 properties->minVgprAllocation = 4;
1057 properties->maxVgprAllocation = 256;
1058 properties->vgprAllocationGranularity = 4;
1059 break;
1060 }
1061 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1062 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1063 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1064 properties->maxVertexAttribDivisor = UINT32_MAX;
1065 break;
1066 }
1067 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1068 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1069 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1070 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1071 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1072 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1073 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1074 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1075 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1076 properties->robustBufferAccessUpdateAfterBind = false;
1077 properties->quadDivergentImplicitLod = false;
1078
1079 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1080 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1081 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1082 32 /* sampler, largest when combined with image */ +
1083 64 /* sampled image */ +
1084 64 /* storage image */);
1085 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1086 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1087 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1088 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1089 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1090 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1091 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1092 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1093 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1094 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1095 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1096 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1097 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1098 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1099 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1100 break;
1101 }
1102 default:
1103 break;
1104 }
1105 }
1106 }
1107
1108 static void radv_get_physical_device_queue_family_properties(
1109 struct radv_physical_device* pdevice,
1110 uint32_t* pCount,
1111 VkQueueFamilyProperties** pQueueFamilyProperties)
1112 {
1113 int num_queue_families = 1;
1114 int idx;
1115 if (pdevice->rad_info.num_compute_rings > 0 &&
1116 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1117 num_queue_families++;
1118
1119 if (pQueueFamilyProperties == NULL) {
1120 *pCount = num_queue_families;
1121 return;
1122 }
1123
1124 if (!*pCount)
1125 return;
1126
1127 idx = 0;
1128 if (*pCount >= 1) {
1129 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1130 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1131 VK_QUEUE_COMPUTE_BIT |
1132 VK_QUEUE_TRANSFER_BIT |
1133 VK_QUEUE_SPARSE_BINDING_BIT,
1134 .queueCount = 1,
1135 .timestampValidBits = 64,
1136 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1137 };
1138 idx++;
1139 }
1140
1141 if (pdevice->rad_info.num_compute_rings > 0 &&
1142 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1143 if (*pCount > idx) {
1144 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1145 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1146 VK_QUEUE_TRANSFER_BIT |
1147 VK_QUEUE_SPARSE_BINDING_BIT,
1148 .queueCount = pdevice->rad_info.num_compute_rings,
1149 .timestampValidBits = 64,
1150 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1151 };
1152 idx++;
1153 }
1154 }
1155 *pCount = idx;
1156 }
1157
1158 void radv_GetPhysicalDeviceQueueFamilyProperties(
1159 VkPhysicalDevice physicalDevice,
1160 uint32_t* pCount,
1161 VkQueueFamilyProperties* pQueueFamilyProperties)
1162 {
1163 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1164 if (!pQueueFamilyProperties) {
1165 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1166 return;
1167 }
1168 VkQueueFamilyProperties *properties[] = {
1169 pQueueFamilyProperties + 0,
1170 pQueueFamilyProperties + 1,
1171 pQueueFamilyProperties + 2,
1172 };
1173 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1174 assert(*pCount <= 3);
1175 }
1176
1177 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1178 VkPhysicalDevice physicalDevice,
1179 uint32_t* pCount,
1180 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
1181 {
1182 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1183 if (!pQueueFamilyProperties) {
1184 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1185 return;
1186 }
1187 VkQueueFamilyProperties *properties[] = {
1188 &pQueueFamilyProperties[0].queueFamilyProperties,
1189 &pQueueFamilyProperties[1].queueFamilyProperties,
1190 &pQueueFamilyProperties[2].queueFamilyProperties,
1191 };
1192 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1193 assert(*pCount <= 3);
1194 }
1195
1196 void radv_GetPhysicalDeviceMemoryProperties(
1197 VkPhysicalDevice physicalDevice,
1198 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1199 {
1200 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1201
1202 *pMemoryProperties = physical_device->memory_properties;
1203 }
1204
1205 void radv_GetPhysicalDeviceMemoryProperties2(
1206 VkPhysicalDevice physicalDevice,
1207 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
1208 {
1209 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1210 &pMemoryProperties->memoryProperties);
1211 }
1212
1213 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1214 VkDevice _device,
1215 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
1216 const void *pHostPointer,
1217 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1218 {
1219 RADV_FROM_HANDLE(radv_device, device, _device);
1220
1221 switch (handleType)
1222 {
1223 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1224 const struct radv_physical_device *physical_device = device->physical_device;
1225 uint32_t memoryTypeBits = 0;
1226 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1227 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1228 memoryTypeBits = (1 << i);
1229 break;
1230 }
1231 }
1232 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1233 return VK_SUCCESS;
1234 }
1235 default:
1236 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
1237 }
1238 }
1239
1240 static enum radeon_ctx_priority
1241 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1242 {
1243 /* Default to MEDIUM when a specific global priority isn't requested */
1244 if (!pObj)
1245 return RADEON_CTX_PRIORITY_MEDIUM;
1246
1247 switch(pObj->globalPriority) {
1248 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1249 return RADEON_CTX_PRIORITY_REALTIME;
1250 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1251 return RADEON_CTX_PRIORITY_HIGH;
1252 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1253 return RADEON_CTX_PRIORITY_MEDIUM;
1254 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1255 return RADEON_CTX_PRIORITY_LOW;
1256 default:
1257 unreachable("Illegal global priority value");
1258 return RADEON_CTX_PRIORITY_INVALID;
1259 }
1260 }
1261
1262 static int
1263 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1264 uint32_t queue_family_index, int idx,
1265 VkDeviceQueueCreateFlags flags,
1266 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1267 {
1268 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1269 queue->device = device;
1270 queue->queue_family_index = queue_family_index;
1271 queue->queue_idx = idx;
1272 queue->priority = radv_get_queue_global_priority(global_priority);
1273 queue->flags = flags;
1274
1275 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1276 if (!queue->hw_ctx)
1277 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1278
1279 return VK_SUCCESS;
1280 }
1281
1282 static void
1283 radv_queue_finish(struct radv_queue *queue)
1284 {
1285 if (queue->hw_ctx)
1286 queue->device->ws->ctx_destroy(queue->hw_ctx);
1287
1288 if (queue->initial_full_flush_preamble_cs)
1289 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1290 if (queue->initial_preamble_cs)
1291 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1292 if (queue->continue_preamble_cs)
1293 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1294 if (queue->descriptor_bo)
1295 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1296 if (queue->scratch_bo)
1297 queue->device->ws->buffer_destroy(queue->scratch_bo);
1298 if (queue->esgs_ring_bo)
1299 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1300 if (queue->gsvs_ring_bo)
1301 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1302 if (queue->tess_rings_bo)
1303 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1304 if (queue->compute_scratch_bo)
1305 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1306 }
1307
1308 static void
1309 radv_bo_list_init(struct radv_bo_list *bo_list)
1310 {
1311 pthread_mutex_init(&bo_list->mutex, NULL);
1312 bo_list->list.count = bo_list->capacity = 0;
1313 bo_list->list.bos = NULL;
1314 }
1315
1316 static void
1317 radv_bo_list_finish(struct radv_bo_list *bo_list)
1318 {
1319 free(bo_list->list.bos);
1320 pthread_mutex_destroy(&bo_list->mutex);
1321 }
1322
1323 static VkResult radv_bo_list_add(struct radv_device *device,
1324 struct radeon_winsys_bo *bo)
1325 {
1326 struct radv_bo_list *bo_list = &device->bo_list;
1327
1328 if (unlikely(!device->use_global_bo_list))
1329 return VK_SUCCESS;
1330
1331 pthread_mutex_lock(&bo_list->mutex);
1332 if (bo_list->list.count == bo_list->capacity) {
1333 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1334 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1335
1336 if (!data) {
1337 pthread_mutex_unlock(&bo_list->mutex);
1338 return VK_ERROR_OUT_OF_HOST_MEMORY;
1339 }
1340
1341 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1342 bo_list->capacity = capacity;
1343 }
1344
1345 bo_list->list.bos[bo_list->list.count++] = bo;
1346 pthread_mutex_unlock(&bo_list->mutex);
1347 return VK_SUCCESS;
1348 }
1349
1350 static void radv_bo_list_remove(struct radv_device *device,
1351 struct radeon_winsys_bo *bo)
1352 {
1353 struct radv_bo_list *bo_list = &device->bo_list;
1354
1355 if (unlikely(!device->use_global_bo_list))
1356 return;
1357
1358 pthread_mutex_lock(&bo_list->mutex);
1359 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1360 if (bo_list->list.bos[i] == bo) {
1361 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1362 --bo_list->list.count;
1363 break;
1364 }
1365 }
1366 pthread_mutex_unlock(&bo_list->mutex);
1367 }
1368
1369 static void
1370 radv_device_init_gs_info(struct radv_device *device)
1371 {
1372 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1373 device->physical_device->rad_info.family);
1374 }
1375
1376 static int radv_get_device_extension_index(const char *name)
1377 {
1378 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1379 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1380 return i;
1381 }
1382 return -1;
1383 }
1384
1385 VkResult radv_CreateDevice(
1386 VkPhysicalDevice physicalDevice,
1387 const VkDeviceCreateInfo* pCreateInfo,
1388 const VkAllocationCallbacks* pAllocator,
1389 VkDevice* pDevice)
1390 {
1391 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1392 VkResult result;
1393 struct radv_device *device;
1394
1395 bool keep_shader_info = false;
1396
1397 /* Check enabled features */
1398 if (pCreateInfo->pEnabledFeatures) {
1399 VkPhysicalDeviceFeatures supported_features;
1400 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1401 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1402 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1403 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1404 for (uint32_t i = 0; i < num_features; i++) {
1405 if (enabled_feature[i] && !supported_feature[i])
1406 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1407 }
1408 }
1409
1410 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1411 sizeof(*device), 8,
1412 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1413 if (!device)
1414 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1415
1416 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1417 device->instance = physical_device->instance;
1418 device->physical_device = physical_device;
1419
1420 device->ws = physical_device->ws;
1421 if (pAllocator)
1422 device->alloc = *pAllocator;
1423 else
1424 device->alloc = physical_device->instance->alloc;
1425
1426 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1427 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1428 int index = radv_get_device_extension_index(ext_name);
1429 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1430 vk_free(&device->alloc, device);
1431 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1432 }
1433
1434 device->enabled_extensions.extensions[index] = true;
1435 }
1436
1437 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1438
1439 /* With update after bind we can't attach bo's to the command buffer
1440 * from the descriptor set anymore, so we have to use a global BO list.
1441 */
1442 device->use_global_bo_list =
1443 device->enabled_extensions.EXT_descriptor_indexing;
1444
1445 mtx_init(&device->shader_slab_mutex, mtx_plain);
1446 list_inithead(&device->shader_slabs);
1447
1448 radv_bo_list_init(&device->bo_list);
1449
1450 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1451 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1452 uint32_t qfi = queue_create->queueFamilyIndex;
1453 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1454 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1455
1456 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1457
1458 device->queues[qfi] = vk_alloc(&device->alloc,
1459 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1460 if (!device->queues[qfi]) {
1461 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1462 goto fail;
1463 }
1464
1465 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1466
1467 device->queue_count[qfi] = queue_create->queueCount;
1468
1469 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1470 result = radv_queue_init(device, &device->queues[qfi][q],
1471 qfi, q, queue_create->flags,
1472 global_priority);
1473 if (result != VK_SUCCESS)
1474 goto fail;
1475 }
1476 }
1477
1478 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1479 (device->instance->perftest_flags & RADV_PERFTEST_BINNING);
1480
1481 /* Disabled and not implemented for now. */
1482 device->dfsm_allowed = device->pbb_allowed && false;
1483
1484 #ifdef ANDROID
1485 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1486 #endif
1487
1488 /* The maximum number of scratch waves. Scratch space isn't divided
1489 * evenly between CUs. The number is only a function of the number of CUs.
1490 * We can decrease the constant to decrease the scratch buffer size.
1491 *
1492 * sctx->scratch_waves must be >= the maximum possible size of
1493 * 1 threadgroup, so that the hw doesn't hang from being unable
1494 * to start any.
1495 *
1496 * The recommended value is 4 per CU at most. Higher numbers don't
1497 * bring much benefit, but they still occupy chip resources (think
1498 * async compute). I've seen ~2% performance difference between 4 and 32.
1499 */
1500 uint32_t max_threads_per_block = 2048;
1501 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1502 max_threads_per_block / 64);
1503
1504 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1505
1506 if (device->physical_device->rad_info.chip_class >= CIK) {
1507 /* If the KMD allows it (there is a KMD hw register for it),
1508 * allow launching waves out-of-order.
1509 */
1510 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1511 }
1512
1513 radv_device_init_gs_info(device);
1514
1515 device->tess_offchip_block_dw_size =
1516 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1517 device->has_distributed_tess =
1518 device->physical_device->rad_info.chip_class >= VI &&
1519 device->physical_device->rad_info.max_se >= 2;
1520
1521 if (getenv("RADV_TRACE_FILE")) {
1522 const char *filename = getenv("RADV_TRACE_FILE");
1523
1524 keep_shader_info = true;
1525
1526 if (!radv_init_trace(device))
1527 goto fail;
1528
1529 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1530 radv_dump_enabled_options(device, stderr);
1531 }
1532
1533 device->keep_shader_info = keep_shader_info;
1534
1535 result = radv_device_init_meta(device);
1536 if (result != VK_SUCCESS)
1537 goto fail;
1538
1539 radv_device_init_msaa(device);
1540
1541 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1542 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1543 switch (family) {
1544 case RADV_QUEUE_GENERAL:
1545 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1546 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1547 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1548 break;
1549 case RADV_QUEUE_COMPUTE:
1550 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1551 radeon_emit(device->empty_cs[family], 0);
1552 break;
1553 }
1554 device->ws->cs_finalize(device->empty_cs[family]);
1555 }
1556
1557 if (device->physical_device->rad_info.chip_class >= CIK)
1558 cik_create_gfx_config(device);
1559
1560 VkPipelineCacheCreateInfo ci;
1561 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1562 ci.pNext = NULL;
1563 ci.flags = 0;
1564 ci.pInitialData = NULL;
1565 ci.initialDataSize = 0;
1566 VkPipelineCache pc;
1567 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1568 &ci, NULL, &pc);
1569 if (result != VK_SUCCESS)
1570 goto fail_meta;
1571
1572 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1573
1574 *pDevice = radv_device_to_handle(device);
1575 return VK_SUCCESS;
1576
1577 fail_meta:
1578 radv_device_finish_meta(device);
1579 fail:
1580 radv_bo_list_finish(&device->bo_list);
1581
1582 if (device->trace_bo)
1583 device->ws->buffer_destroy(device->trace_bo);
1584
1585 if (device->gfx_init)
1586 device->ws->buffer_destroy(device->gfx_init);
1587
1588 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1589 for (unsigned q = 0; q < device->queue_count[i]; q++)
1590 radv_queue_finish(&device->queues[i][q]);
1591 if (device->queue_count[i])
1592 vk_free(&device->alloc, device->queues[i]);
1593 }
1594
1595 vk_free(&device->alloc, device);
1596 return result;
1597 }
1598
1599 void radv_DestroyDevice(
1600 VkDevice _device,
1601 const VkAllocationCallbacks* pAllocator)
1602 {
1603 RADV_FROM_HANDLE(radv_device, device, _device);
1604
1605 if (!device)
1606 return;
1607
1608 if (device->trace_bo)
1609 device->ws->buffer_destroy(device->trace_bo);
1610
1611 if (device->gfx_init)
1612 device->ws->buffer_destroy(device->gfx_init);
1613
1614 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1615 for (unsigned q = 0; q < device->queue_count[i]; q++)
1616 radv_queue_finish(&device->queues[i][q]);
1617 if (device->queue_count[i])
1618 vk_free(&device->alloc, device->queues[i]);
1619 if (device->empty_cs[i])
1620 device->ws->cs_destroy(device->empty_cs[i]);
1621 }
1622 radv_device_finish_meta(device);
1623
1624 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1625 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1626
1627 radv_destroy_shader_slabs(device);
1628
1629 radv_bo_list_finish(&device->bo_list);
1630 vk_free(&device->alloc, device);
1631 }
1632
1633 VkResult radv_EnumerateInstanceLayerProperties(
1634 uint32_t* pPropertyCount,
1635 VkLayerProperties* pProperties)
1636 {
1637 if (pProperties == NULL) {
1638 *pPropertyCount = 0;
1639 return VK_SUCCESS;
1640 }
1641
1642 /* None supported at this time */
1643 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1644 }
1645
1646 VkResult radv_EnumerateDeviceLayerProperties(
1647 VkPhysicalDevice physicalDevice,
1648 uint32_t* pPropertyCount,
1649 VkLayerProperties* pProperties)
1650 {
1651 if (pProperties == NULL) {
1652 *pPropertyCount = 0;
1653 return VK_SUCCESS;
1654 }
1655
1656 /* None supported at this time */
1657 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1658 }
1659
1660 void radv_GetDeviceQueue2(
1661 VkDevice _device,
1662 const VkDeviceQueueInfo2* pQueueInfo,
1663 VkQueue* pQueue)
1664 {
1665 RADV_FROM_HANDLE(radv_device, device, _device);
1666 struct radv_queue *queue;
1667
1668 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
1669 if (pQueueInfo->flags != queue->flags) {
1670 /* From the Vulkan 1.1.70 spec:
1671 *
1672 * "The queue returned by vkGetDeviceQueue2 must have the same
1673 * flags value from this structure as that used at device
1674 * creation time in a VkDeviceQueueCreateInfo instance. If no
1675 * matching flags were specified at device creation time then
1676 * pQueue will return VK_NULL_HANDLE."
1677 */
1678 *pQueue = VK_NULL_HANDLE;
1679 return;
1680 }
1681
1682 *pQueue = radv_queue_to_handle(queue);
1683 }
1684
1685 void radv_GetDeviceQueue(
1686 VkDevice _device,
1687 uint32_t queueFamilyIndex,
1688 uint32_t queueIndex,
1689 VkQueue* pQueue)
1690 {
1691 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
1692 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
1693 .queueFamilyIndex = queueFamilyIndex,
1694 .queueIndex = queueIndex
1695 };
1696
1697 radv_GetDeviceQueue2(_device, &info, pQueue);
1698 }
1699
1700 static void
1701 fill_geom_tess_rings(struct radv_queue *queue,
1702 uint32_t *map,
1703 bool add_sample_positions,
1704 uint32_t esgs_ring_size,
1705 struct radeon_winsys_bo *esgs_ring_bo,
1706 uint32_t gsvs_ring_size,
1707 struct radeon_winsys_bo *gsvs_ring_bo,
1708 uint32_t tess_factor_ring_size,
1709 uint32_t tess_offchip_ring_offset,
1710 uint32_t tess_offchip_ring_size,
1711 struct radeon_winsys_bo *tess_rings_bo)
1712 {
1713 uint64_t esgs_va = 0, gsvs_va = 0;
1714 uint64_t tess_va = 0, tess_offchip_va = 0;
1715 uint32_t *desc = &map[4];
1716
1717 if (esgs_ring_bo)
1718 esgs_va = radv_buffer_get_va(esgs_ring_bo);
1719 if (gsvs_ring_bo)
1720 gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
1721 if (tess_rings_bo) {
1722 tess_va = radv_buffer_get_va(tess_rings_bo);
1723 tess_offchip_va = tess_va + tess_offchip_ring_offset;
1724 }
1725
1726 /* stride 0, num records - size, add tid, swizzle, elsize4,
1727 index stride 64 */
1728 desc[0] = esgs_va;
1729 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1730 S_008F04_STRIDE(0) |
1731 S_008F04_SWIZZLE_ENABLE(true);
1732 desc[2] = esgs_ring_size;
1733 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1734 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1735 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1736 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1737 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1738 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1739 S_008F0C_ELEMENT_SIZE(1) |
1740 S_008F0C_INDEX_STRIDE(3) |
1741 S_008F0C_ADD_TID_ENABLE(true);
1742
1743 desc += 4;
1744 /* GS entry for ES->GS ring */
1745 /* stride 0, num records - size, elsize0,
1746 index stride 0 */
1747 desc[0] = esgs_va;
1748 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1749 S_008F04_STRIDE(0) |
1750 S_008F04_SWIZZLE_ENABLE(false);
1751 desc[2] = esgs_ring_size;
1752 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1753 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1754 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1755 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1756 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1757 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1758 S_008F0C_ELEMENT_SIZE(0) |
1759 S_008F0C_INDEX_STRIDE(0) |
1760 S_008F0C_ADD_TID_ENABLE(false);
1761
1762 desc += 4;
1763 /* VS entry for GS->VS ring */
1764 /* stride 0, num records - size, elsize0,
1765 index stride 0 */
1766 desc[0] = gsvs_va;
1767 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1768 S_008F04_STRIDE(0) |
1769 S_008F04_SWIZZLE_ENABLE(false);
1770 desc[2] = gsvs_ring_size;
1771 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1772 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1773 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1774 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1775 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1776 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1777 S_008F0C_ELEMENT_SIZE(0) |
1778 S_008F0C_INDEX_STRIDE(0) |
1779 S_008F0C_ADD_TID_ENABLE(false);
1780 desc += 4;
1781
1782 /* stride gsvs_itemsize, num records 64
1783 elsize 4, index stride 16 */
1784 /* shader will patch stride and desc[2] */
1785 desc[0] = gsvs_va;
1786 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1787 S_008F04_STRIDE(0) |
1788 S_008F04_SWIZZLE_ENABLE(true);
1789 desc[2] = 0;
1790 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1791 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1792 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1793 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1794 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1795 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1796 S_008F0C_ELEMENT_SIZE(1) |
1797 S_008F0C_INDEX_STRIDE(1) |
1798 S_008F0C_ADD_TID_ENABLE(true);
1799 desc += 4;
1800
1801 desc[0] = tess_va;
1802 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
1803 S_008F04_STRIDE(0) |
1804 S_008F04_SWIZZLE_ENABLE(false);
1805 desc[2] = tess_factor_ring_size;
1806 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1807 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1808 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1809 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1810 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1811 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1812 S_008F0C_ELEMENT_SIZE(0) |
1813 S_008F0C_INDEX_STRIDE(0) |
1814 S_008F0C_ADD_TID_ENABLE(false);
1815 desc += 4;
1816
1817 desc[0] = tess_offchip_va;
1818 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1819 S_008F04_STRIDE(0) |
1820 S_008F04_SWIZZLE_ENABLE(false);
1821 desc[2] = tess_offchip_ring_size;
1822 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1823 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1824 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1825 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1826 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1827 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1828 S_008F0C_ELEMENT_SIZE(0) |
1829 S_008F0C_INDEX_STRIDE(0) |
1830 S_008F0C_ADD_TID_ENABLE(false);
1831 desc += 4;
1832
1833 /* add sample positions after all rings */
1834 memcpy(desc, queue->device->sample_locations_1x, 8);
1835 desc += 2;
1836 memcpy(desc, queue->device->sample_locations_2x, 16);
1837 desc += 4;
1838 memcpy(desc, queue->device->sample_locations_4x, 32);
1839 desc += 8;
1840 memcpy(desc, queue->device->sample_locations_8x, 64);
1841 desc += 16;
1842 memcpy(desc, queue->device->sample_locations_16x, 128);
1843 }
1844
1845 static unsigned
1846 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1847 {
1848 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1849 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1850 device->physical_device->rad_info.family != CHIP_STONEY;
1851 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1852 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1853 device->physical_device->rad_info.max_se;
1854 unsigned offchip_granularity;
1855 unsigned hs_offchip_param;
1856 switch (device->tess_offchip_block_dw_size) {
1857 default:
1858 assert(0);
1859 /* fall through */
1860 case 8192:
1861 offchip_granularity = V_03093C_X_8K_DWORDS;
1862 break;
1863 case 4096:
1864 offchip_granularity = V_03093C_X_4K_DWORDS;
1865 break;
1866 }
1867
1868 switch (device->physical_device->rad_info.chip_class) {
1869 case SI:
1870 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1871 break;
1872 case CIK:
1873 case VI:
1874 case GFX9:
1875 default:
1876 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1877 break;
1878 }
1879
1880 *max_offchip_buffers_p = max_offchip_buffers;
1881 if (device->physical_device->rad_info.chip_class >= CIK) {
1882 if (device->physical_device->rad_info.chip_class >= VI)
1883 --max_offchip_buffers;
1884 hs_offchip_param =
1885 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1886 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1887 } else {
1888 hs_offchip_param =
1889 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1890 }
1891 return hs_offchip_param;
1892 }
1893
1894 static void
1895 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
1896 struct radeon_winsys_bo *esgs_ring_bo,
1897 uint32_t esgs_ring_size,
1898 struct radeon_winsys_bo *gsvs_ring_bo,
1899 uint32_t gsvs_ring_size)
1900 {
1901 if (!esgs_ring_bo && !gsvs_ring_bo)
1902 return;
1903
1904 if (esgs_ring_bo)
1905 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo, 8);
1906
1907 if (gsvs_ring_bo)
1908 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo, 8);
1909
1910 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1911 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1912 radeon_emit(cs, esgs_ring_size >> 8);
1913 radeon_emit(cs, gsvs_ring_size >> 8);
1914 } else {
1915 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1916 radeon_emit(cs, esgs_ring_size >> 8);
1917 radeon_emit(cs, gsvs_ring_size >> 8);
1918 }
1919 }
1920
1921 static void
1922 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
1923 unsigned hs_offchip_param, unsigned tf_ring_size,
1924 struct radeon_winsys_bo *tess_rings_bo)
1925 {
1926 uint64_t tf_va;
1927
1928 if (!tess_rings_bo)
1929 return;
1930
1931 tf_va = radv_buffer_get_va(tess_rings_bo);
1932
1933 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo, 8);
1934
1935 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1936 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1937 S_030938_SIZE(tf_ring_size / 4));
1938 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1939 tf_va >> 8);
1940 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1941 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
1942 S_030944_BASE_HI(tf_va >> 40));
1943 }
1944 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
1945 hs_offchip_param);
1946 } else {
1947 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
1948 S_008988_SIZE(tf_ring_size / 4));
1949 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
1950 tf_va >> 8);
1951 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1952 hs_offchip_param);
1953 }
1954 }
1955
1956 static void
1957 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
1958 struct radeon_winsys_bo *compute_scratch_bo)
1959 {
1960 uint64_t scratch_va;
1961
1962 if (!compute_scratch_bo)
1963 return;
1964
1965 scratch_va = radv_buffer_get_va(compute_scratch_bo);
1966
1967 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo, 8);
1968
1969 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
1970 radeon_emit(cs, scratch_va);
1971 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1972 S_008F04_SWIZZLE_ENABLE(1));
1973 }
1974
1975 static void
1976 radv_emit_global_shader_pointers(struct radv_queue *queue,
1977 struct radeon_cmdbuf *cs,
1978 struct radeon_winsys_bo *descriptor_bo)
1979 {
1980 uint64_t va;
1981
1982 if (!descriptor_bo)
1983 return;
1984
1985 va = radv_buffer_get_va(descriptor_bo);
1986
1987 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo, 8);
1988
1989 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1990 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1991 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1992 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
1993 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
1994
1995 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1996 radv_emit_shader_pointer(queue->device, cs, regs[i],
1997 va, true);
1998 }
1999 } else {
2000 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2001 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2002 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2003 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2004 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2005 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2006
2007 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2008 radv_emit_shader_pointer(queue->device, cs, regs[i],
2009 va, true);
2010 }
2011 }
2012 }
2013
2014 static VkResult
2015 radv_get_preamble_cs(struct radv_queue *queue,
2016 uint32_t scratch_size,
2017 uint32_t compute_scratch_size,
2018 uint32_t esgs_ring_size,
2019 uint32_t gsvs_ring_size,
2020 bool needs_tess_rings,
2021 bool needs_sample_positions,
2022 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2023 struct radeon_cmdbuf **initial_preamble_cs,
2024 struct radeon_cmdbuf **continue_preamble_cs)
2025 {
2026 struct radeon_winsys_bo *scratch_bo = NULL;
2027 struct radeon_winsys_bo *descriptor_bo = NULL;
2028 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2029 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2030 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2031 struct radeon_winsys_bo *tess_rings_bo = NULL;
2032 struct radeon_cmdbuf *dest_cs[3] = {0};
2033 bool add_tess_rings = false, add_sample_positions = false;
2034 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2035 unsigned max_offchip_buffers;
2036 unsigned hs_offchip_param = 0;
2037 unsigned tess_offchip_ring_offset;
2038 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2039 if (!queue->has_tess_rings) {
2040 if (needs_tess_rings)
2041 add_tess_rings = true;
2042 }
2043 if (!queue->has_sample_positions) {
2044 if (needs_sample_positions)
2045 add_sample_positions = true;
2046 }
2047 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2048 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2049 &max_offchip_buffers);
2050 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2051 tess_offchip_ring_size = max_offchip_buffers *
2052 queue->device->tess_offchip_block_dw_size * 4;
2053
2054 if (scratch_size <= queue->scratch_size &&
2055 compute_scratch_size <= queue->compute_scratch_size &&
2056 esgs_ring_size <= queue->esgs_ring_size &&
2057 gsvs_ring_size <= queue->gsvs_ring_size &&
2058 !add_tess_rings && !add_sample_positions &&
2059 queue->initial_preamble_cs) {
2060 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2061 *initial_preamble_cs = queue->initial_preamble_cs;
2062 *continue_preamble_cs = queue->continue_preamble_cs;
2063 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2064 *continue_preamble_cs = NULL;
2065 return VK_SUCCESS;
2066 }
2067
2068 if (scratch_size > queue->scratch_size) {
2069 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2070 scratch_size,
2071 4096,
2072 RADEON_DOMAIN_VRAM,
2073 ring_bo_flags);
2074 if (!scratch_bo)
2075 goto fail;
2076 } else
2077 scratch_bo = queue->scratch_bo;
2078
2079 if (compute_scratch_size > queue->compute_scratch_size) {
2080 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2081 compute_scratch_size,
2082 4096,
2083 RADEON_DOMAIN_VRAM,
2084 ring_bo_flags);
2085 if (!compute_scratch_bo)
2086 goto fail;
2087
2088 } else
2089 compute_scratch_bo = queue->compute_scratch_bo;
2090
2091 if (esgs_ring_size > queue->esgs_ring_size) {
2092 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2093 esgs_ring_size,
2094 4096,
2095 RADEON_DOMAIN_VRAM,
2096 ring_bo_flags);
2097 if (!esgs_ring_bo)
2098 goto fail;
2099 } else {
2100 esgs_ring_bo = queue->esgs_ring_bo;
2101 esgs_ring_size = queue->esgs_ring_size;
2102 }
2103
2104 if (gsvs_ring_size > queue->gsvs_ring_size) {
2105 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2106 gsvs_ring_size,
2107 4096,
2108 RADEON_DOMAIN_VRAM,
2109 ring_bo_flags);
2110 if (!gsvs_ring_bo)
2111 goto fail;
2112 } else {
2113 gsvs_ring_bo = queue->gsvs_ring_bo;
2114 gsvs_ring_size = queue->gsvs_ring_size;
2115 }
2116
2117 if (add_tess_rings) {
2118 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2119 tess_offchip_ring_offset + tess_offchip_ring_size,
2120 256,
2121 RADEON_DOMAIN_VRAM,
2122 ring_bo_flags);
2123 if (!tess_rings_bo)
2124 goto fail;
2125 } else {
2126 tess_rings_bo = queue->tess_rings_bo;
2127 }
2128
2129 if (scratch_bo != queue->scratch_bo ||
2130 esgs_ring_bo != queue->esgs_ring_bo ||
2131 gsvs_ring_bo != queue->gsvs_ring_bo ||
2132 tess_rings_bo != queue->tess_rings_bo ||
2133 add_sample_positions) {
2134 uint32_t size = 0;
2135 if (gsvs_ring_bo || esgs_ring_bo ||
2136 tess_rings_bo || add_sample_positions) {
2137 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2138 if (add_sample_positions)
2139 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
2140 }
2141 else if (scratch_bo)
2142 size = 8; /* 2 dword */
2143
2144 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2145 size,
2146 4096,
2147 RADEON_DOMAIN_VRAM,
2148 RADEON_FLAG_CPU_ACCESS |
2149 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2150 RADEON_FLAG_READ_ONLY);
2151 if (!descriptor_bo)
2152 goto fail;
2153 } else
2154 descriptor_bo = queue->descriptor_bo;
2155
2156 for(int i = 0; i < 3; ++i) {
2157 struct radeon_cmdbuf *cs = NULL;
2158 cs = queue->device->ws->cs_create(queue->device->ws,
2159 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2160 if (!cs)
2161 goto fail;
2162
2163 dest_cs[i] = cs;
2164
2165 if (scratch_bo)
2166 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo, 8);
2167
2168 if (descriptor_bo != queue->descriptor_bo) {
2169 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2170
2171 if (scratch_bo) {
2172 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2173 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2174 S_008F04_SWIZZLE_ENABLE(1);
2175 map[0] = scratch_va;
2176 map[1] = rsrc1;
2177 }
2178
2179 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo ||
2180 add_sample_positions)
2181 fill_geom_tess_rings(queue, map, add_sample_positions,
2182 esgs_ring_size, esgs_ring_bo,
2183 gsvs_ring_size, gsvs_ring_bo,
2184 tess_factor_ring_size,
2185 tess_offchip_ring_offset,
2186 tess_offchip_ring_size,
2187 tess_rings_bo);
2188
2189 queue->device->ws->buffer_unmap(descriptor_bo);
2190 }
2191
2192 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2193 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2194 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2195 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2196 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2197 }
2198
2199 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2200 gsvs_ring_bo, gsvs_ring_size);
2201 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2202 tess_factor_ring_size, tess_rings_bo);
2203 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2204 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2205
2206 if (i == 0) {
2207 si_cs_emit_cache_flush(cs,
2208 queue->device->physical_device->rad_info.chip_class,
2209 NULL, 0,
2210 queue->queue_family_index == RING_COMPUTE &&
2211 queue->device->physical_device->rad_info.chip_class >= CIK,
2212 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2213 RADV_CMD_FLAG_INV_ICACHE |
2214 RADV_CMD_FLAG_INV_SMEM_L1 |
2215 RADV_CMD_FLAG_INV_VMEM_L1 |
2216 RADV_CMD_FLAG_INV_GLOBAL_L2);
2217 } else if (i == 1) {
2218 si_cs_emit_cache_flush(cs,
2219 queue->device->physical_device->rad_info.chip_class,
2220 NULL, 0,
2221 queue->queue_family_index == RING_COMPUTE &&
2222 queue->device->physical_device->rad_info.chip_class >= CIK,
2223 RADV_CMD_FLAG_INV_ICACHE |
2224 RADV_CMD_FLAG_INV_SMEM_L1 |
2225 RADV_CMD_FLAG_INV_VMEM_L1 |
2226 RADV_CMD_FLAG_INV_GLOBAL_L2);
2227 }
2228
2229 if (!queue->device->ws->cs_finalize(cs))
2230 goto fail;
2231 }
2232
2233 if (queue->initial_full_flush_preamble_cs)
2234 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2235
2236 if (queue->initial_preamble_cs)
2237 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2238
2239 if (queue->continue_preamble_cs)
2240 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2241
2242 queue->initial_full_flush_preamble_cs = dest_cs[0];
2243 queue->initial_preamble_cs = dest_cs[1];
2244 queue->continue_preamble_cs = dest_cs[2];
2245
2246 if (scratch_bo != queue->scratch_bo) {
2247 if (queue->scratch_bo)
2248 queue->device->ws->buffer_destroy(queue->scratch_bo);
2249 queue->scratch_bo = scratch_bo;
2250 queue->scratch_size = scratch_size;
2251 }
2252
2253 if (compute_scratch_bo != queue->compute_scratch_bo) {
2254 if (queue->compute_scratch_bo)
2255 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2256 queue->compute_scratch_bo = compute_scratch_bo;
2257 queue->compute_scratch_size = compute_scratch_size;
2258 }
2259
2260 if (esgs_ring_bo != queue->esgs_ring_bo) {
2261 if (queue->esgs_ring_bo)
2262 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2263 queue->esgs_ring_bo = esgs_ring_bo;
2264 queue->esgs_ring_size = esgs_ring_size;
2265 }
2266
2267 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2268 if (queue->gsvs_ring_bo)
2269 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2270 queue->gsvs_ring_bo = gsvs_ring_bo;
2271 queue->gsvs_ring_size = gsvs_ring_size;
2272 }
2273
2274 if (tess_rings_bo != queue->tess_rings_bo) {
2275 queue->tess_rings_bo = tess_rings_bo;
2276 queue->has_tess_rings = true;
2277 }
2278
2279 if (descriptor_bo != queue->descriptor_bo) {
2280 if (queue->descriptor_bo)
2281 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2282
2283 queue->descriptor_bo = descriptor_bo;
2284 }
2285
2286 if (add_sample_positions)
2287 queue->has_sample_positions = true;
2288
2289 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2290 *initial_preamble_cs = queue->initial_preamble_cs;
2291 *continue_preamble_cs = queue->continue_preamble_cs;
2292 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2293 *continue_preamble_cs = NULL;
2294 return VK_SUCCESS;
2295 fail:
2296 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2297 if (dest_cs[i])
2298 queue->device->ws->cs_destroy(dest_cs[i]);
2299 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2300 queue->device->ws->buffer_destroy(descriptor_bo);
2301 if (scratch_bo && scratch_bo != queue->scratch_bo)
2302 queue->device->ws->buffer_destroy(scratch_bo);
2303 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2304 queue->device->ws->buffer_destroy(compute_scratch_bo);
2305 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2306 queue->device->ws->buffer_destroy(esgs_ring_bo);
2307 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2308 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2309 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2310 queue->device->ws->buffer_destroy(tess_rings_bo);
2311 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2312 }
2313
2314 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2315 struct radv_winsys_sem_counts *counts,
2316 int num_sems,
2317 const VkSemaphore *sems,
2318 VkFence _fence,
2319 bool reset_temp)
2320 {
2321 int syncobj_idx = 0, sem_idx = 0;
2322
2323 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2324 return VK_SUCCESS;
2325
2326 for (uint32_t i = 0; i < num_sems; i++) {
2327 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2328
2329 if (sem->temp_syncobj || sem->syncobj)
2330 counts->syncobj_count++;
2331 else
2332 counts->sem_count++;
2333 }
2334
2335 if (_fence != VK_NULL_HANDLE) {
2336 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2337 if (fence->temp_syncobj || fence->syncobj)
2338 counts->syncobj_count++;
2339 }
2340
2341 if (counts->syncobj_count) {
2342 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2343 if (!counts->syncobj)
2344 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2345 }
2346
2347 if (counts->sem_count) {
2348 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2349 if (!counts->sem) {
2350 free(counts->syncobj);
2351 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2352 }
2353 }
2354
2355 for (uint32_t i = 0; i < num_sems; i++) {
2356 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2357
2358 if (sem->temp_syncobj) {
2359 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2360 }
2361 else if (sem->syncobj)
2362 counts->syncobj[syncobj_idx++] = sem->syncobj;
2363 else {
2364 assert(sem->sem);
2365 counts->sem[sem_idx++] = sem->sem;
2366 }
2367 }
2368
2369 if (_fence != VK_NULL_HANDLE) {
2370 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2371 if (fence->temp_syncobj)
2372 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2373 else if (fence->syncobj)
2374 counts->syncobj[syncobj_idx++] = fence->syncobj;
2375 }
2376
2377 return VK_SUCCESS;
2378 }
2379
2380 static void
2381 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2382 {
2383 free(sem_info->wait.syncobj);
2384 free(sem_info->wait.sem);
2385 free(sem_info->signal.syncobj);
2386 free(sem_info->signal.sem);
2387 }
2388
2389
2390 static void radv_free_temp_syncobjs(struct radv_device *device,
2391 int num_sems,
2392 const VkSemaphore *sems)
2393 {
2394 for (uint32_t i = 0; i < num_sems; i++) {
2395 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2396
2397 if (sem->temp_syncobj) {
2398 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2399 sem->temp_syncobj = 0;
2400 }
2401 }
2402 }
2403
2404 static VkResult
2405 radv_alloc_sem_info(struct radv_instance *instance,
2406 struct radv_winsys_sem_info *sem_info,
2407 int num_wait_sems,
2408 const VkSemaphore *wait_sems,
2409 int num_signal_sems,
2410 const VkSemaphore *signal_sems,
2411 VkFence fence)
2412 {
2413 VkResult ret;
2414 memset(sem_info, 0, sizeof(*sem_info));
2415
2416 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2417 if (ret)
2418 return ret;
2419 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2420 if (ret)
2421 radv_free_sem_info(sem_info);
2422
2423 /* caller can override these */
2424 sem_info->cs_emit_wait = true;
2425 sem_info->cs_emit_signal = true;
2426 return ret;
2427 }
2428
2429 /* Signals fence as soon as all the work currently put on queue is done. */
2430 static VkResult radv_signal_fence(struct radv_queue *queue,
2431 struct radv_fence *fence)
2432 {
2433 int ret;
2434 VkResult result;
2435 struct radv_winsys_sem_info sem_info;
2436
2437 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2438 radv_fence_to_handle(fence));
2439 if (result != VK_SUCCESS)
2440 return result;
2441
2442 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2443 &queue->device->empty_cs[queue->queue_family_index],
2444 1, NULL, NULL, &sem_info, NULL,
2445 false, fence->fence);
2446 radv_free_sem_info(&sem_info);
2447
2448 /* TODO: find a better error */
2449 if (ret)
2450 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2451
2452 return VK_SUCCESS;
2453 }
2454
2455 VkResult radv_QueueSubmit(
2456 VkQueue _queue,
2457 uint32_t submitCount,
2458 const VkSubmitInfo* pSubmits,
2459 VkFence _fence)
2460 {
2461 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2462 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2463 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2464 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2465 int ret;
2466 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2467 uint32_t scratch_size = 0;
2468 uint32_t compute_scratch_size = 0;
2469 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2470 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2471 VkResult result;
2472 bool fence_emitted = false;
2473 bool tess_rings_needed = false;
2474 bool sample_positions_needed = false;
2475
2476 /* Do this first so failing to allocate scratch buffers can't result in
2477 * partially executed submissions. */
2478 for (uint32_t i = 0; i < submitCount; i++) {
2479 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2480 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2481 pSubmits[i].pCommandBuffers[j]);
2482
2483 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2484 compute_scratch_size = MAX2(compute_scratch_size,
2485 cmd_buffer->compute_scratch_size_needed);
2486 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2487 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2488 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2489 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2490 }
2491 }
2492
2493 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2494 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2495 sample_positions_needed, &initial_flush_preamble_cs,
2496 &initial_preamble_cs, &continue_preamble_cs);
2497 if (result != VK_SUCCESS)
2498 return result;
2499
2500 for (uint32_t i = 0; i < submitCount; i++) {
2501 struct radeon_cmdbuf **cs_array;
2502 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2503 bool can_patch = true;
2504 uint32_t advance;
2505 struct radv_winsys_sem_info sem_info;
2506
2507 result = radv_alloc_sem_info(queue->device->instance,
2508 &sem_info,
2509 pSubmits[i].waitSemaphoreCount,
2510 pSubmits[i].pWaitSemaphores,
2511 pSubmits[i].signalSemaphoreCount,
2512 pSubmits[i].pSignalSemaphores,
2513 _fence);
2514 if (result != VK_SUCCESS)
2515 return result;
2516
2517 if (!pSubmits[i].commandBufferCount) {
2518 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2519 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2520 &queue->device->empty_cs[queue->queue_family_index],
2521 1, NULL, NULL,
2522 &sem_info, NULL,
2523 false, base_fence);
2524 if (ret) {
2525 radv_loge("failed to submit CS %d\n", i);
2526 abort();
2527 }
2528 fence_emitted = true;
2529 }
2530 radv_free_sem_info(&sem_info);
2531 continue;
2532 }
2533
2534 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
2535 (pSubmits[i].commandBufferCount));
2536
2537 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2538 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2539 pSubmits[i].pCommandBuffers[j]);
2540 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2541
2542 cs_array[j] = cmd_buffer->cs;
2543 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2544 can_patch = false;
2545
2546 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2547 }
2548
2549 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2550 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2551 const struct radv_winsys_bo_list *bo_list = NULL;
2552
2553 advance = MIN2(max_cs_submission,
2554 pSubmits[i].commandBufferCount - j);
2555
2556 if (queue->device->trace_bo)
2557 *queue->device->trace_id_ptr = 0;
2558
2559 sem_info.cs_emit_wait = j == 0;
2560 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2561
2562 if (unlikely(queue->device->use_global_bo_list)) {
2563 pthread_mutex_lock(&queue->device->bo_list.mutex);
2564 bo_list = &queue->device->bo_list.list;
2565 }
2566
2567 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2568 advance, initial_preamble, continue_preamble_cs,
2569 &sem_info, bo_list,
2570 can_patch, base_fence);
2571
2572 if (unlikely(queue->device->use_global_bo_list))
2573 pthread_mutex_unlock(&queue->device->bo_list.mutex);
2574
2575 if (ret) {
2576 radv_loge("failed to submit CS %d\n", i);
2577 abort();
2578 }
2579 fence_emitted = true;
2580 if (queue->device->trace_bo) {
2581 radv_check_gpu_hangs(queue, cs_array[j]);
2582 }
2583 }
2584
2585 radv_free_temp_syncobjs(queue->device,
2586 pSubmits[i].waitSemaphoreCount,
2587 pSubmits[i].pWaitSemaphores);
2588 radv_free_sem_info(&sem_info);
2589 free(cs_array);
2590 }
2591
2592 if (fence) {
2593 if (!fence_emitted) {
2594 radv_signal_fence(queue, fence);
2595 }
2596 fence->submitted = true;
2597 }
2598
2599 return VK_SUCCESS;
2600 }
2601
2602 VkResult radv_QueueWaitIdle(
2603 VkQueue _queue)
2604 {
2605 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2606
2607 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2608 radv_queue_family_to_ring(queue->queue_family_index),
2609 queue->queue_idx);
2610 return VK_SUCCESS;
2611 }
2612
2613 VkResult radv_DeviceWaitIdle(
2614 VkDevice _device)
2615 {
2616 RADV_FROM_HANDLE(radv_device, device, _device);
2617
2618 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2619 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2620 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2621 }
2622 }
2623 return VK_SUCCESS;
2624 }
2625
2626 VkResult radv_EnumerateInstanceExtensionProperties(
2627 const char* pLayerName,
2628 uint32_t* pPropertyCount,
2629 VkExtensionProperties* pProperties)
2630 {
2631 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2632
2633 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
2634 if (radv_supported_instance_extensions.extensions[i]) {
2635 vk_outarray_append(&out, prop) {
2636 *prop = radv_instance_extensions[i];
2637 }
2638 }
2639 }
2640
2641 return vk_outarray_status(&out);
2642 }
2643
2644 VkResult radv_EnumerateDeviceExtensionProperties(
2645 VkPhysicalDevice physicalDevice,
2646 const char* pLayerName,
2647 uint32_t* pPropertyCount,
2648 VkExtensionProperties* pProperties)
2649 {
2650 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2651 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2652
2653 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
2654 if (device->supported_extensions.extensions[i]) {
2655 vk_outarray_append(&out, prop) {
2656 *prop = radv_device_extensions[i];
2657 }
2658 }
2659 }
2660
2661 return vk_outarray_status(&out);
2662 }
2663
2664 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2665 VkInstance _instance,
2666 const char* pName)
2667 {
2668 RADV_FROM_HANDLE(radv_instance, instance, _instance);
2669
2670 return radv_lookup_entrypoint_checked(pName,
2671 instance ? instance->apiVersion : 0,
2672 instance ? &instance->enabled_extensions : NULL,
2673 NULL);
2674 }
2675
2676 /* The loader wants us to expose a second GetInstanceProcAddr function
2677 * to work around certain LD_PRELOAD issues seen in apps.
2678 */
2679 PUBLIC
2680 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2681 VkInstance instance,
2682 const char* pName);
2683
2684 PUBLIC
2685 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2686 VkInstance instance,
2687 const char* pName)
2688 {
2689 return radv_GetInstanceProcAddr(instance, pName);
2690 }
2691
2692 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2693 VkDevice _device,
2694 const char* pName)
2695 {
2696 RADV_FROM_HANDLE(radv_device, device, _device);
2697
2698 return radv_lookup_entrypoint_checked(pName,
2699 device->instance->apiVersion,
2700 &device->instance->enabled_extensions,
2701 &device->enabled_extensions);
2702 }
2703
2704 bool radv_get_memory_fd(struct radv_device *device,
2705 struct radv_device_memory *memory,
2706 int *pFD)
2707 {
2708 struct radeon_bo_metadata metadata;
2709
2710 if (memory->image) {
2711 radv_init_metadata(device, memory->image, &metadata);
2712 device->ws->buffer_set_metadata(memory->bo, &metadata);
2713 }
2714
2715 return device->ws->buffer_get_fd(device->ws, memory->bo,
2716 pFD);
2717 }
2718
2719 static VkResult radv_alloc_memory(struct radv_device *device,
2720 const VkMemoryAllocateInfo* pAllocateInfo,
2721 const VkAllocationCallbacks* pAllocator,
2722 VkDeviceMemory* pMem)
2723 {
2724 struct radv_device_memory *mem;
2725 VkResult result;
2726 enum radeon_bo_domain domain;
2727 uint32_t flags = 0;
2728 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
2729
2730 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2731
2732 if (pAllocateInfo->allocationSize == 0) {
2733 /* Apparently, this is allowed */
2734 *pMem = VK_NULL_HANDLE;
2735 return VK_SUCCESS;
2736 }
2737
2738 const VkImportMemoryFdInfoKHR *import_info =
2739 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2740 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2741 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2742 const VkExportMemoryAllocateInfoKHR *export_info =
2743 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO_KHR);
2744 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
2745 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
2746
2747 const struct wsi_memory_allocate_info *wsi_info =
2748 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
2749
2750 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2751 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2752 if (mem == NULL)
2753 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2754
2755 if (wsi_info && wsi_info->implicit_sync)
2756 flags |= RADEON_FLAG_IMPLICIT_SYNC;
2757
2758 if (dedicate_info) {
2759 mem->image = radv_image_from_handle(dedicate_info->image);
2760 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2761 } else {
2762 mem->image = NULL;
2763 mem->buffer = NULL;
2764 }
2765
2766 mem->user_ptr = NULL;
2767
2768 if (import_info) {
2769 assert(import_info->handleType ==
2770 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
2771 import_info->handleType ==
2772 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
2773 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2774 NULL, NULL);
2775 if (!mem->bo) {
2776 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2777 goto fail;
2778 } else {
2779 close(import_info->fd);
2780 }
2781 } else if (host_ptr_info) {
2782 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
2783 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
2784 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
2785 pAllocateInfo->allocationSize);
2786 if (!mem->bo) {
2787 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2788 goto fail;
2789 } else {
2790 mem->user_ptr = host_ptr_info->pHostPointer;
2791 }
2792 } else {
2793 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2794 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2795 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
2796 domain = RADEON_DOMAIN_GTT;
2797 else
2798 domain = RADEON_DOMAIN_VRAM;
2799
2800 if (mem_type_index == RADV_MEM_TYPE_VRAM)
2801 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2802 else
2803 flags |= RADEON_FLAG_CPU_ACCESS;
2804
2805 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2806 flags |= RADEON_FLAG_GTT_WC;
2807
2808 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes))
2809 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
2810
2811 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2812 domain, flags);
2813
2814 if (!mem->bo) {
2815 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2816 goto fail;
2817 }
2818 mem->type_index = mem_type_index;
2819 }
2820
2821 result = radv_bo_list_add(device, mem->bo);
2822 if (result != VK_SUCCESS)
2823 goto fail_bo;
2824
2825 *pMem = radv_device_memory_to_handle(mem);
2826
2827 return VK_SUCCESS;
2828
2829 fail_bo:
2830 device->ws->buffer_destroy(mem->bo);
2831 fail:
2832 vk_free2(&device->alloc, pAllocator, mem);
2833
2834 return result;
2835 }
2836
2837 VkResult radv_AllocateMemory(
2838 VkDevice _device,
2839 const VkMemoryAllocateInfo* pAllocateInfo,
2840 const VkAllocationCallbacks* pAllocator,
2841 VkDeviceMemory* pMem)
2842 {
2843 RADV_FROM_HANDLE(radv_device, device, _device);
2844 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
2845 }
2846
2847 void radv_FreeMemory(
2848 VkDevice _device,
2849 VkDeviceMemory _mem,
2850 const VkAllocationCallbacks* pAllocator)
2851 {
2852 RADV_FROM_HANDLE(radv_device, device, _device);
2853 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2854
2855 if (mem == NULL)
2856 return;
2857
2858 radv_bo_list_remove(device, mem->bo);
2859 device->ws->buffer_destroy(mem->bo);
2860 mem->bo = NULL;
2861
2862 vk_free2(&device->alloc, pAllocator, mem);
2863 }
2864
2865 VkResult radv_MapMemory(
2866 VkDevice _device,
2867 VkDeviceMemory _memory,
2868 VkDeviceSize offset,
2869 VkDeviceSize size,
2870 VkMemoryMapFlags flags,
2871 void** ppData)
2872 {
2873 RADV_FROM_HANDLE(radv_device, device, _device);
2874 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2875
2876 if (mem == NULL) {
2877 *ppData = NULL;
2878 return VK_SUCCESS;
2879 }
2880
2881 if (mem->user_ptr)
2882 *ppData = mem->user_ptr;
2883 else
2884 *ppData = device->ws->buffer_map(mem->bo);
2885
2886 if (*ppData) {
2887 *ppData += offset;
2888 return VK_SUCCESS;
2889 }
2890
2891 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
2892 }
2893
2894 void radv_UnmapMemory(
2895 VkDevice _device,
2896 VkDeviceMemory _memory)
2897 {
2898 RADV_FROM_HANDLE(radv_device, device, _device);
2899 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2900
2901 if (mem == NULL)
2902 return;
2903
2904 if (mem->user_ptr == NULL)
2905 device->ws->buffer_unmap(mem->bo);
2906 }
2907
2908 VkResult radv_FlushMappedMemoryRanges(
2909 VkDevice _device,
2910 uint32_t memoryRangeCount,
2911 const VkMappedMemoryRange* pMemoryRanges)
2912 {
2913 return VK_SUCCESS;
2914 }
2915
2916 VkResult radv_InvalidateMappedMemoryRanges(
2917 VkDevice _device,
2918 uint32_t memoryRangeCount,
2919 const VkMappedMemoryRange* pMemoryRanges)
2920 {
2921 return VK_SUCCESS;
2922 }
2923
2924 void radv_GetBufferMemoryRequirements(
2925 VkDevice _device,
2926 VkBuffer _buffer,
2927 VkMemoryRequirements* pMemoryRequirements)
2928 {
2929 RADV_FROM_HANDLE(radv_device, device, _device);
2930 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2931
2932 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2933
2934 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2935 pMemoryRequirements->alignment = 4096;
2936 else
2937 pMemoryRequirements->alignment = 16;
2938
2939 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2940 }
2941
2942 void radv_GetBufferMemoryRequirements2(
2943 VkDevice device,
2944 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
2945 VkMemoryRequirements2KHR* pMemoryRequirements)
2946 {
2947 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
2948 &pMemoryRequirements->memoryRequirements);
2949 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
2950 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2951 switch (ext->sType) {
2952 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2953 VkMemoryDedicatedRequirementsKHR *req =
2954 (VkMemoryDedicatedRequirementsKHR *) ext;
2955 req->requiresDedicatedAllocation = buffer->shareable;
2956 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2957 break;
2958 }
2959 default:
2960 break;
2961 }
2962 }
2963 }
2964
2965 void radv_GetImageMemoryRequirements(
2966 VkDevice _device,
2967 VkImage _image,
2968 VkMemoryRequirements* pMemoryRequirements)
2969 {
2970 RADV_FROM_HANDLE(radv_device, device, _device);
2971 RADV_FROM_HANDLE(radv_image, image, _image);
2972
2973 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2974
2975 pMemoryRequirements->size = image->size;
2976 pMemoryRequirements->alignment = image->alignment;
2977 }
2978
2979 void radv_GetImageMemoryRequirements2(
2980 VkDevice device,
2981 const VkImageMemoryRequirementsInfo2KHR* pInfo,
2982 VkMemoryRequirements2KHR* pMemoryRequirements)
2983 {
2984 radv_GetImageMemoryRequirements(device, pInfo->image,
2985 &pMemoryRequirements->memoryRequirements);
2986
2987 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
2988
2989 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2990 switch (ext->sType) {
2991 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2992 VkMemoryDedicatedRequirementsKHR *req =
2993 (VkMemoryDedicatedRequirementsKHR *) ext;
2994 req->requiresDedicatedAllocation = image->shareable;
2995 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2996 break;
2997 }
2998 default:
2999 break;
3000 }
3001 }
3002 }
3003
3004 void radv_GetImageSparseMemoryRequirements(
3005 VkDevice device,
3006 VkImage image,
3007 uint32_t* pSparseMemoryRequirementCount,
3008 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3009 {
3010 stub();
3011 }
3012
3013 void radv_GetImageSparseMemoryRequirements2(
3014 VkDevice device,
3015 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
3016 uint32_t* pSparseMemoryRequirementCount,
3017 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
3018 {
3019 stub();
3020 }
3021
3022 void radv_GetDeviceMemoryCommitment(
3023 VkDevice device,
3024 VkDeviceMemory memory,
3025 VkDeviceSize* pCommittedMemoryInBytes)
3026 {
3027 *pCommittedMemoryInBytes = 0;
3028 }
3029
3030 VkResult radv_BindBufferMemory2(VkDevice device,
3031 uint32_t bindInfoCount,
3032 const VkBindBufferMemoryInfoKHR *pBindInfos)
3033 {
3034 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3035 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3036 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3037
3038 if (mem) {
3039 buffer->bo = mem->bo;
3040 buffer->offset = pBindInfos[i].memoryOffset;
3041 } else {
3042 buffer->bo = NULL;
3043 }
3044 }
3045 return VK_SUCCESS;
3046 }
3047
3048 VkResult radv_BindBufferMemory(
3049 VkDevice device,
3050 VkBuffer buffer,
3051 VkDeviceMemory memory,
3052 VkDeviceSize memoryOffset)
3053 {
3054 const VkBindBufferMemoryInfoKHR info = {
3055 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
3056 .buffer = buffer,
3057 .memory = memory,
3058 .memoryOffset = memoryOffset
3059 };
3060
3061 return radv_BindBufferMemory2(device, 1, &info);
3062 }
3063
3064 VkResult radv_BindImageMemory2(VkDevice device,
3065 uint32_t bindInfoCount,
3066 const VkBindImageMemoryInfoKHR *pBindInfos)
3067 {
3068 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3069 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3070 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3071
3072 if (mem) {
3073 image->bo = mem->bo;
3074 image->offset = pBindInfos[i].memoryOffset;
3075 } else {
3076 image->bo = NULL;
3077 image->offset = 0;
3078 }
3079 }
3080 return VK_SUCCESS;
3081 }
3082
3083
3084 VkResult radv_BindImageMemory(
3085 VkDevice device,
3086 VkImage image,
3087 VkDeviceMemory memory,
3088 VkDeviceSize memoryOffset)
3089 {
3090 const VkBindImageMemoryInfoKHR info = {
3091 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
3092 .image = image,
3093 .memory = memory,
3094 .memoryOffset = memoryOffset
3095 };
3096
3097 return radv_BindImageMemory2(device, 1, &info);
3098 }
3099
3100
3101 static void
3102 radv_sparse_buffer_bind_memory(struct radv_device *device,
3103 const VkSparseBufferMemoryBindInfo *bind)
3104 {
3105 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3106
3107 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3108 struct radv_device_memory *mem = NULL;
3109
3110 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3111 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3112
3113 device->ws->buffer_virtual_bind(buffer->bo,
3114 bind->pBinds[i].resourceOffset,
3115 bind->pBinds[i].size,
3116 mem ? mem->bo : NULL,
3117 bind->pBinds[i].memoryOffset);
3118 }
3119 }
3120
3121 static void
3122 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3123 const VkSparseImageOpaqueMemoryBindInfo *bind)
3124 {
3125 RADV_FROM_HANDLE(radv_image, image, bind->image);
3126
3127 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3128 struct radv_device_memory *mem = NULL;
3129
3130 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3131 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3132
3133 device->ws->buffer_virtual_bind(image->bo,
3134 bind->pBinds[i].resourceOffset,
3135 bind->pBinds[i].size,
3136 mem ? mem->bo : NULL,
3137 bind->pBinds[i].memoryOffset);
3138 }
3139 }
3140
3141 VkResult radv_QueueBindSparse(
3142 VkQueue _queue,
3143 uint32_t bindInfoCount,
3144 const VkBindSparseInfo* pBindInfo,
3145 VkFence _fence)
3146 {
3147 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3148 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3149 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3150 bool fence_emitted = false;
3151
3152 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3153 struct radv_winsys_sem_info sem_info;
3154 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3155 radv_sparse_buffer_bind_memory(queue->device,
3156 pBindInfo[i].pBufferBinds + j);
3157 }
3158
3159 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3160 radv_sparse_image_opaque_bind_memory(queue->device,
3161 pBindInfo[i].pImageOpaqueBinds + j);
3162 }
3163
3164 VkResult result;
3165 result = radv_alloc_sem_info(queue->device->instance,
3166 &sem_info,
3167 pBindInfo[i].waitSemaphoreCount,
3168 pBindInfo[i].pWaitSemaphores,
3169 pBindInfo[i].signalSemaphoreCount,
3170 pBindInfo[i].pSignalSemaphores,
3171 _fence);
3172 if (result != VK_SUCCESS)
3173 return result;
3174
3175 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3176 queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3177 &queue->device->empty_cs[queue->queue_family_index],
3178 1, NULL, NULL,
3179 &sem_info, NULL,
3180 false, base_fence);
3181 fence_emitted = true;
3182 if (fence)
3183 fence->submitted = true;
3184 }
3185
3186 radv_free_sem_info(&sem_info);
3187
3188 }
3189
3190 if (fence) {
3191 if (!fence_emitted) {
3192 radv_signal_fence(queue, fence);
3193 }
3194 fence->submitted = true;
3195 }
3196
3197 return VK_SUCCESS;
3198 }
3199
3200 VkResult radv_CreateFence(
3201 VkDevice _device,
3202 const VkFenceCreateInfo* pCreateInfo,
3203 const VkAllocationCallbacks* pAllocator,
3204 VkFence* pFence)
3205 {
3206 RADV_FROM_HANDLE(radv_device, device, _device);
3207 const VkExportFenceCreateInfoKHR *export =
3208 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO_KHR);
3209 VkExternalFenceHandleTypeFlagsKHR handleTypes =
3210 export ? export->handleTypes : 0;
3211
3212 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3213 sizeof(*fence), 8,
3214 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3215
3216 if (!fence)
3217 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3218
3219 fence->submitted = false;
3220 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
3221 fence->temp_syncobj = 0;
3222 if (device->always_use_syncobj || handleTypes) {
3223 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3224 if (ret) {
3225 vk_free2(&device->alloc, pAllocator, fence);
3226 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3227 }
3228 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3229 device->ws->signal_syncobj(device->ws, fence->syncobj);
3230 }
3231 fence->fence = NULL;
3232 } else {
3233 fence->fence = device->ws->create_fence();
3234 if (!fence->fence) {
3235 vk_free2(&device->alloc, pAllocator, fence);
3236 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3237 }
3238 fence->syncobj = 0;
3239 }
3240
3241 *pFence = radv_fence_to_handle(fence);
3242
3243 return VK_SUCCESS;
3244 }
3245
3246 void radv_DestroyFence(
3247 VkDevice _device,
3248 VkFence _fence,
3249 const VkAllocationCallbacks* pAllocator)
3250 {
3251 RADV_FROM_HANDLE(radv_device, device, _device);
3252 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3253
3254 if (!fence)
3255 return;
3256
3257 if (fence->temp_syncobj)
3258 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3259 if (fence->syncobj)
3260 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3261 if (fence->fence)
3262 device->ws->destroy_fence(fence->fence);
3263 vk_free2(&device->alloc, pAllocator, fence);
3264 }
3265
3266
3267 static uint64_t radv_get_current_time()
3268 {
3269 struct timespec tv;
3270 clock_gettime(CLOCK_MONOTONIC, &tv);
3271 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3272 }
3273
3274 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3275 {
3276 uint64_t current_time = radv_get_current_time();
3277
3278 timeout = MIN2(UINT64_MAX - current_time, timeout);
3279
3280 return current_time + timeout;
3281 }
3282
3283
3284 static bool radv_all_fences_plain_and_submitted(uint32_t fenceCount, const VkFence *pFences)
3285 {
3286 for (uint32_t i = 0; i < fenceCount; ++i) {
3287 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3288 if (fence->syncobj || fence->temp_syncobj || (!fence->signalled && !fence->submitted))
3289 return false;
3290 }
3291 return true;
3292 }
3293
3294 VkResult radv_WaitForFences(
3295 VkDevice _device,
3296 uint32_t fenceCount,
3297 const VkFence* pFences,
3298 VkBool32 waitAll,
3299 uint64_t timeout)
3300 {
3301 RADV_FROM_HANDLE(radv_device, device, _device);
3302 timeout = radv_get_absolute_timeout(timeout);
3303
3304 if (device->always_use_syncobj) {
3305 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3306 if (!handles)
3307 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3308
3309 for (uint32_t i = 0; i < fenceCount; ++i) {
3310 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3311 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3312 }
3313
3314 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3315
3316 free(handles);
3317 return success ? VK_SUCCESS : VK_TIMEOUT;
3318 }
3319
3320 if (!waitAll && fenceCount > 1) {
3321 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3322 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(fenceCount, pFences)) {
3323 uint32_t wait_count = 0;
3324 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3325 if (!fences)
3326 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3327
3328 for (uint32_t i = 0; i < fenceCount; ++i) {
3329 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3330
3331 if (fence->signalled) {
3332 free(fences);
3333 return VK_SUCCESS;
3334 }
3335
3336 fences[wait_count++] = fence->fence;
3337 }
3338
3339 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3340 waitAll, timeout - radv_get_current_time());
3341
3342 free(fences);
3343 return success ? VK_SUCCESS : VK_TIMEOUT;
3344 }
3345
3346 while(radv_get_current_time() <= timeout) {
3347 for (uint32_t i = 0; i < fenceCount; ++i) {
3348 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3349 return VK_SUCCESS;
3350 }
3351 }
3352 return VK_TIMEOUT;
3353 }
3354
3355 for (uint32_t i = 0; i < fenceCount; ++i) {
3356 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3357 bool expired = false;
3358
3359 if (fence->temp_syncobj) {
3360 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3361 return VK_TIMEOUT;
3362 continue;
3363 }
3364
3365 if (fence->syncobj) {
3366 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3367 return VK_TIMEOUT;
3368 continue;
3369 }
3370
3371 if (fence->signalled)
3372 continue;
3373
3374 if (!fence->submitted) {
3375 while(radv_get_current_time() <= timeout && !fence->submitted)
3376 /* Do nothing */;
3377
3378 if (!fence->submitted)
3379 return VK_TIMEOUT;
3380
3381 /* Recheck as it may have been set by submitting operations. */
3382 if (fence->signalled)
3383 continue;
3384 }
3385
3386 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
3387 if (!expired)
3388 return VK_TIMEOUT;
3389
3390 fence->signalled = true;
3391 }
3392
3393 return VK_SUCCESS;
3394 }
3395
3396 VkResult radv_ResetFences(VkDevice _device,
3397 uint32_t fenceCount,
3398 const VkFence *pFences)
3399 {
3400 RADV_FROM_HANDLE(radv_device, device, _device);
3401
3402 for (unsigned i = 0; i < fenceCount; ++i) {
3403 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3404 fence->submitted = fence->signalled = false;
3405
3406 /* Per spec, we first restore the permanent payload, and then reset, so
3407 * having a temp syncobj should not skip resetting the permanent syncobj. */
3408 if (fence->temp_syncobj) {
3409 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3410 fence->temp_syncobj = 0;
3411 }
3412
3413 if (fence->syncobj) {
3414 device->ws->reset_syncobj(device->ws, fence->syncobj);
3415 }
3416 }
3417
3418 return VK_SUCCESS;
3419 }
3420
3421 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3422 {
3423 RADV_FROM_HANDLE(radv_device, device, _device);
3424 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3425
3426 if (fence->temp_syncobj) {
3427 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3428 return success ? VK_SUCCESS : VK_NOT_READY;
3429 }
3430
3431 if (fence->syncobj) {
3432 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3433 return success ? VK_SUCCESS : VK_NOT_READY;
3434 }
3435
3436 if (fence->signalled)
3437 return VK_SUCCESS;
3438 if (!fence->submitted)
3439 return VK_NOT_READY;
3440 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3441 return VK_NOT_READY;
3442
3443 return VK_SUCCESS;
3444 }
3445
3446
3447 // Queue semaphore functions
3448
3449 VkResult radv_CreateSemaphore(
3450 VkDevice _device,
3451 const VkSemaphoreCreateInfo* pCreateInfo,
3452 const VkAllocationCallbacks* pAllocator,
3453 VkSemaphore* pSemaphore)
3454 {
3455 RADV_FROM_HANDLE(radv_device, device, _device);
3456 const VkExportSemaphoreCreateInfoKHR *export =
3457 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
3458 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
3459 export ? export->handleTypes : 0;
3460
3461 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3462 sizeof(*sem), 8,
3463 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3464 if (!sem)
3465 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3466
3467 sem->temp_syncobj = 0;
3468 /* create a syncobject if we are going to export this semaphore */
3469 if (device->always_use_syncobj || handleTypes) {
3470 assert (device->physical_device->rad_info.has_syncobj);
3471 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
3472 if (ret) {
3473 vk_free2(&device->alloc, pAllocator, sem);
3474 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3475 }
3476 sem->sem = NULL;
3477 } else {
3478 sem->sem = device->ws->create_sem(device->ws);
3479 if (!sem->sem) {
3480 vk_free2(&device->alloc, pAllocator, sem);
3481 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3482 }
3483 sem->syncobj = 0;
3484 }
3485
3486 *pSemaphore = radv_semaphore_to_handle(sem);
3487 return VK_SUCCESS;
3488 }
3489
3490 void radv_DestroySemaphore(
3491 VkDevice _device,
3492 VkSemaphore _semaphore,
3493 const VkAllocationCallbacks* pAllocator)
3494 {
3495 RADV_FROM_HANDLE(radv_device, device, _device);
3496 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
3497 if (!_semaphore)
3498 return;
3499
3500 if (sem->syncobj)
3501 device->ws->destroy_syncobj(device->ws, sem->syncobj);
3502 else
3503 device->ws->destroy_sem(sem->sem);
3504 vk_free2(&device->alloc, pAllocator, sem);
3505 }
3506
3507 VkResult radv_CreateEvent(
3508 VkDevice _device,
3509 const VkEventCreateInfo* pCreateInfo,
3510 const VkAllocationCallbacks* pAllocator,
3511 VkEvent* pEvent)
3512 {
3513 RADV_FROM_HANDLE(radv_device, device, _device);
3514 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
3515 sizeof(*event), 8,
3516 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3517
3518 if (!event)
3519 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3520
3521 event->bo = device->ws->buffer_create(device->ws, 8, 8,
3522 RADEON_DOMAIN_GTT,
3523 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING);
3524 if (!event->bo) {
3525 vk_free2(&device->alloc, pAllocator, event);
3526 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3527 }
3528
3529 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
3530
3531 *pEvent = radv_event_to_handle(event);
3532
3533 return VK_SUCCESS;
3534 }
3535
3536 void radv_DestroyEvent(
3537 VkDevice _device,
3538 VkEvent _event,
3539 const VkAllocationCallbacks* pAllocator)
3540 {
3541 RADV_FROM_HANDLE(radv_device, device, _device);
3542 RADV_FROM_HANDLE(radv_event, event, _event);
3543
3544 if (!event)
3545 return;
3546 device->ws->buffer_destroy(event->bo);
3547 vk_free2(&device->alloc, pAllocator, event);
3548 }
3549
3550 VkResult radv_GetEventStatus(
3551 VkDevice _device,
3552 VkEvent _event)
3553 {
3554 RADV_FROM_HANDLE(radv_event, event, _event);
3555
3556 if (*event->map == 1)
3557 return VK_EVENT_SET;
3558 return VK_EVENT_RESET;
3559 }
3560
3561 VkResult radv_SetEvent(
3562 VkDevice _device,
3563 VkEvent _event)
3564 {
3565 RADV_FROM_HANDLE(radv_event, event, _event);
3566 *event->map = 1;
3567
3568 return VK_SUCCESS;
3569 }
3570
3571 VkResult radv_ResetEvent(
3572 VkDevice _device,
3573 VkEvent _event)
3574 {
3575 RADV_FROM_HANDLE(radv_event, event, _event);
3576 *event->map = 0;
3577
3578 return VK_SUCCESS;
3579 }
3580
3581 VkResult radv_CreateBuffer(
3582 VkDevice _device,
3583 const VkBufferCreateInfo* pCreateInfo,
3584 const VkAllocationCallbacks* pAllocator,
3585 VkBuffer* pBuffer)
3586 {
3587 RADV_FROM_HANDLE(radv_device, device, _device);
3588 struct radv_buffer *buffer;
3589
3590 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
3591
3592 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
3593 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3594 if (buffer == NULL)
3595 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3596
3597 buffer->size = pCreateInfo->size;
3598 buffer->usage = pCreateInfo->usage;
3599 buffer->bo = NULL;
3600 buffer->offset = 0;
3601 buffer->flags = pCreateInfo->flags;
3602
3603 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
3604 EXTERNAL_MEMORY_BUFFER_CREATE_INFO_KHR) != NULL;
3605
3606 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
3607 buffer->bo = device->ws->buffer_create(device->ws,
3608 align64(buffer->size, 4096),
3609 4096, 0, RADEON_FLAG_VIRTUAL);
3610 if (!buffer->bo) {
3611 vk_free2(&device->alloc, pAllocator, buffer);
3612 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3613 }
3614 }
3615
3616 *pBuffer = radv_buffer_to_handle(buffer);
3617
3618 return VK_SUCCESS;
3619 }
3620
3621 void radv_DestroyBuffer(
3622 VkDevice _device,
3623 VkBuffer _buffer,
3624 const VkAllocationCallbacks* pAllocator)
3625 {
3626 RADV_FROM_HANDLE(radv_device, device, _device);
3627 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3628
3629 if (!buffer)
3630 return;
3631
3632 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3633 device->ws->buffer_destroy(buffer->bo);
3634
3635 vk_free2(&device->alloc, pAllocator, buffer);
3636 }
3637
3638 static inline unsigned
3639 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
3640 {
3641 if (stencil)
3642 return image->surface.u.legacy.stencil_tiling_index[level];
3643 else
3644 return image->surface.u.legacy.tiling_index[level];
3645 }
3646
3647 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
3648 {
3649 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
3650 }
3651
3652 static uint32_t
3653 radv_init_dcc_control_reg(struct radv_device *device,
3654 struct radv_image_view *iview)
3655 {
3656 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
3657 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
3658 unsigned max_compressed_block_size;
3659 unsigned independent_64b_blocks;
3660
3661 if (device->physical_device->rad_info.chip_class < VI)
3662 return 0;
3663
3664 if (iview->image->info.samples > 1) {
3665 if (iview->image->surface.bpe == 1)
3666 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3667 else if (iview->image->surface.bpe == 2)
3668 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
3669 }
3670
3671 if (!device->physical_device->rad_info.has_dedicated_vram) {
3672 /* amdvlk: [min-compressed-block-size] should be set to 32 for
3673 * dGPU and 64 for APU because all of our APUs to date use
3674 * DIMMs which have a request granularity size of 64B while all
3675 * other chips have a 32B request size.
3676 */
3677 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
3678 }
3679
3680 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
3681 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
3682 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
3683 /* If this DCC image is potentially going to be used in texture
3684 * fetches, we need some special settings.
3685 */
3686 independent_64b_blocks = 1;
3687 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3688 } else {
3689 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
3690 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
3691 * big as possible for better compression state.
3692 */
3693 independent_64b_blocks = 0;
3694 max_compressed_block_size = max_uncompressed_block_size;
3695 }
3696
3697 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3698 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
3699 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
3700 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
3701 }
3702
3703 static void
3704 radv_initialise_color_surface(struct radv_device *device,
3705 struct radv_color_buffer_info *cb,
3706 struct radv_image_view *iview)
3707 {
3708 const struct vk_format_description *desc;
3709 unsigned ntype, format, swap, endian;
3710 unsigned blend_clamp = 0, blend_bypass = 0;
3711 uint64_t va;
3712 const struct radeon_surf *surf = &iview->image->surface;
3713
3714 desc = vk_format_description(iview->vk_format);
3715
3716 memset(cb, 0, sizeof(*cb));
3717
3718 /* Intensity is implemented as Red, so treat it that way. */
3719 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
3720
3721 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3722
3723 cb->cb_color_base = va >> 8;
3724
3725 if (device->physical_device->rad_info.chip_class >= GFX9) {
3726 struct gfx9_surf_meta_flags meta;
3727 if (iview->image->dcc_offset)
3728 meta = iview->image->surface.u.gfx9.dcc;
3729 else
3730 meta = iview->image->surface.u.gfx9.cmask;
3731
3732 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3733 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
3734 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3735 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3736
3737 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
3738 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3739 } else {
3740 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
3741 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3742
3743 cb->cb_color_base += level_info->offset >> 8;
3744 if (level_info->mode == RADEON_SURF_MODE_2D)
3745 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3746
3747 pitch_tile_max = level_info->nblk_x / 8 - 1;
3748 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
3749 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
3750
3751 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3752 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3753 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
3754
3755 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3756
3757 if (radv_image_has_fmask(iview->image)) {
3758 if (device->physical_device->rad_info.chip_class >= CIK)
3759 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
3760 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
3761 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
3762 } else {
3763 /* This must be set for fast clear to work without FMASK. */
3764 if (device->physical_device->rad_info.chip_class >= CIK)
3765 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3766 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3767 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3768 }
3769 }
3770
3771 /* CMASK variables */
3772 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3773 va += iview->image->cmask.offset;
3774 cb->cb_color_cmask = va >> 8;
3775
3776 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3777 va += iview->image->dcc_offset;
3778 cb->cb_dcc_base = va >> 8;
3779 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
3780
3781 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3782 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
3783 S_028C6C_SLICE_MAX(max_slice);
3784
3785 if (iview->image->info.samples > 1) {
3786 unsigned log_samples = util_logbase2(iview->image->info.samples);
3787
3788 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
3789 S_028C74_NUM_FRAGMENTS(log_samples);
3790 }
3791
3792 if (radv_image_has_fmask(iview->image)) {
3793 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
3794 cb->cb_color_fmask = va >> 8;
3795 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
3796 } else {
3797 cb->cb_color_fmask = cb->cb_color_base;
3798 }
3799
3800 ntype = radv_translate_color_numformat(iview->vk_format,
3801 desc,
3802 vk_format_get_first_non_void_channel(iview->vk_format));
3803 format = radv_translate_colorformat(iview->vk_format);
3804 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
3805 radv_finishme("Illegal color\n");
3806 swap = radv_translate_colorswap(iview->vk_format, FALSE);
3807 endian = radv_colorformat_endian_swap(format);
3808
3809 /* blend clamp should be set for all NORM/SRGB types */
3810 if (ntype == V_028C70_NUMBER_UNORM ||
3811 ntype == V_028C70_NUMBER_SNORM ||
3812 ntype == V_028C70_NUMBER_SRGB)
3813 blend_clamp = 1;
3814
3815 /* set blend bypass according to docs if SINT/UINT or
3816 8/24 COLOR variants */
3817 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
3818 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
3819 format == V_028C70_COLOR_X24_8_32_FLOAT) {
3820 blend_clamp = 0;
3821 blend_bypass = 1;
3822 }
3823 #if 0
3824 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
3825 (format == V_028C70_COLOR_8 ||
3826 format == V_028C70_COLOR_8_8 ||
3827 format == V_028C70_COLOR_8_8_8_8))
3828 ->color_is_int8 = true;
3829 #endif
3830 cb->cb_color_info = S_028C70_FORMAT(format) |
3831 S_028C70_COMP_SWAP(swap) |
3832 S_028C70_BLEND_CLAMP(blend_clamp) |
3833 S_028C70_BLEND_BYPASS(blend_bypass) |
3834 S_028C70_SIMPLE_FLOAT(1) |
3835 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
3836 ntype != V_028C70_NUMBER_SNORM &&
3837 ntype != V_028C70_NUMBER_SRGB &&
3838 format != V_028C70_COLOR_8_24 &&
3839 format != V_028C70_COLOR_24_8) |
3840 S_028C70_NUMBER_TYPE(ntype) |
3841 S_028C70_ENDIAN(endian);
3842 if (radv_image_has_fmask(iview->image)) {
3843 cb->cb_color_info |= S_028C70_COMPRESSION(1);
3844 if (device->physical_device->rad_info.chip_class == SI) {
3845 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
3846 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
3847 }
3848 }
3849
3850 if (radv_image_has_cmask(iview->image) &&
3851 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
3852 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
3853
3854 if (radv_dcc_enabled(iview->image, iview->base_mip))
3855 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
3856
3857 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
3858
3859 /* This must be set for fast clear to work without FMASK. */
3860 if (!radv_image_has_fmask(iview->image) &&
3861 device->physical_device->rad_info.chip_class == SI) {
3862 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
3863 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
3864 }
3865
3866 if (device->physical_device->rad_info.chip_class >= GFX9) {
3867 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
3868 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
3869
3870 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
3871 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
3872 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
3873 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
3874 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
3875 S_028C68_MAX_MIP(iview->image->info.levels - 1);
3876 }
3877 }
3878
3879 static unsigned
3880 radv_calc_decompress_on_z_planes(struct radv_device *device,
3881 struct radv_image_view *iview)
3882 {
3883 unsigned max_zplanes = 0;
3884
3885 assert(radv_image_is_tc_compat_htile(iview->image));
3886
3887 if (device->physical_device->rad_info.chip_class >= GFX9) {
3888 /* Default value for 32-bit depth surfaces. */
3889 max_zplanes = 4;
3890
3891 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
3892 iview->image->info.samples > 1)
3893 max_zplanes = 2;
3894
3895 max_zplanes = max_zplanes + 1;
3896 } else {
3897 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
3898 /* Do not enable Z plane compression for 16-bit depth
3899 * surfaces because isn't supported on GFX8. Only
3900 * 32-bit depth surfaces are supported by the hardware.
3901 * This allows to maintain shader compatibility and to
3902 * reduce the number of depth decompressions.
3903 */
3904 max_zplanes = 1;
3905 } else {
3906 if (iview->image->info.samples <= 1)
3907 max_zplanes = 5;
3908 else if (iview->image->info.samples <= 4)
3909 max_zplanes = 3;
3910 else
3911 max_zplanes = 2;
3912 }
3913 }
3914
3915 return max_zplanes;
3916 }
3917
3918 static void
3919 radv_initialise_ds_surface(struct radv_device *device,
3920 struct radv_ds_buffer_info *ds,
3921 struct radv_image_view *iview)
3922 {
3923 unsigned level = iview->base_mip;
3924 unsigned format, stencil_format;
3925 uint64_t va, s_offs, z_offs;
3926 bool stencil_only = false;
3927 memset(ds, 0, sizeof(*ds));
3928 switch (iview->image->vk_format) {
3929 case VK_FORMAT_D24_UNORM_S8_UINT:
3930 case VK_FORMAT_X8_D24_UNORM_PACK32:
3931 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
3932 ds->offset_scale = 2.0f;
3933 break;
3934 case VK_FORMAT_D16_UNORM:
3935 case VK_FORMAT_D16_UNORM_S8_UINT:
3936 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
3937 ds->offset_scale = 4.0f;
3938 break;
3939 case VK_FORMAT_D32_SFLOAT:
3940 case VK_FORMAT_D32_SFLOAT_S8_UINT:
3941 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
3942 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
3943 ds->offset_scale = 1.0f;
3944 break;
3945 case VK_FORMAT_S8_UINT:
3946 stencil_only = true;
3947 break;
3948 default:
3949 break;
3950 }
3951
3952 format = radv_translate_dbformat(iview->image->vk_format);
3953 stencil_format = iview->image->surface.has_stencil ?
3954 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
3955
3956 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3957 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
3958 S_028008_SLICE_MAX(max_slice);
3959
3960 ds->db_htile_data_base = 0;
3961 ds->db_htile_surface = 0;
3962
3963 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3964 s_offs = z_offs = va;
3965
3966 if (device->physical_device->rad_info.chip_class >= GFX9) {
3967 assert(iview->image->surface.u.gfx9.surf_offset == 0);
3968 s_offs += iview->image->surface.u.gfx9.stencil_offset;
3969
3970 ds->db_z_info = S_028038_FORMAT(format) |
3971 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
3972 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3973 S_028038_MAXMIP(iview->image->info.levels - 1) |
3974 S_028038_ZRANGE_PRECISION(1);
3975 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
3976 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
3977
3978 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3979 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
3980 ds->db_depth_view |= S_028008_MIPID(level);
3981
3982 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
3983 S_02801C_Y_MAX(iview->image->info.height - 1);
3984
3985 if (radv_htile_enabled(iview->image, level)) {
3986 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
3987
3988 if (radv_image_is_tc_compat_htile(iview->image)) {
3989 unsigned max_zplanes =
3990 radv_calc_decompress_on_z_planes(device, iview);
3991
3992 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes) |
3993 S_028038_ITERATE_FLUSH(1);
3994 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
3995 }
3996
3997 if (!iview->image->surface.has_stencil)
3998 /* Use all of the htile_buffer for depth if there's no stencil. */
3999 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4000 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4001 iview->image->htile_offset;
4002 ds->db_htile_data_base = va >> 8;
4003 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4004 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
4005 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
4006 }
4007 } else {
4008 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
4009
4010 if (stencil_only)
4011 level_info = &iview->image->surface.u.legacy.stencil_level[level];
4012
4013 z_offs += iview->image->surface.u.legacy.level[level].offset;
4014 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
4015
4016 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4017 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4018 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4019
4020 if (iview->image->info.samples > 1)
4021 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4022
4023 if (device->physical_device->rad_info.chip_class >= CIK) {
4024 struct radeon_info *info = &device->physical_device->rad_info;
4025 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
4026 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
4027 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
4028 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4029 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4030 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4031
4032 if (stencil_only)
4033 tile_mode = stencil_tile_mode;
4034
4035 ds->db_depth_info |=
4036 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4037 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4038 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4039 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4040 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4041 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4042 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4043 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4044 } else {
4045 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
4046 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4047 tile_mode_index = si_tile_mode_index(iview->image, level, true);
4048 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4049 if (stencil_only)
4050 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4051 }
4052
4053 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4054 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4055 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4056
4057 if (radv_htile_enabled(iview->image, level)) {
4058 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4059
4060 if (!iview->image->surface.has_stencil &&
4061 !radv_image_is_tc_compat_htile(iview->image))
4062 /* Use all of the htile_buffer for depth if there's no stencil. */
4063 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4064
4065 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4066 iview->image->htile_offset;
4067 ds->db_htile_data_base = va >> 8;
4068 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4069
4070 if (radv_image_is_tc_compat_htile(iview->image)) {
4071 unsigned max_zplanes =
4072 radv_calc_decompress_on_z_planes(device, iview);
4073
4074 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4075 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4076 }
4077 }
4078 }
4079
4080 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4081 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4082 }
4083
4084 VkResult radv_CreateFramebuffer(
4085 VkDevice _device,
4086 const VkFramebufferCreateInfo* pCreateInfo,
4087 const VkAllocationCallbacks* pAllocator,
4088 VkFramebuffer* pFramebuffer)
4089 {
4090 RADV_FROM_HANDLE(radv_device, device, _device);
4091 struct radv_framebuffer *framebuffer;
4092
4093 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4094
4095 size_t size = sizeof(*framebuffer) +
4096 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4097 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4098 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4099 if (framebuffer == NULL)
4100 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4101
4102 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4103 framebuffer->width = pCreateInfo->width;
4104 framebuffer->height = pCreateInfo->height;
4105 framebuffer->layers = pCreateInfo->layers;
4106 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4107 VkImageView _iview = pCreateInfo->pAttachments[i];
4108 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4109 framebuffer->attachments[i].attachment = iview;
4110 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
4111 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4112 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4113 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4114 }
4115 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4116 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4117 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4118 }
4119
4120 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4121 return VK_SUCCESS;
4122 }
4123
4124 void radv_DestroyFramebuffer(
4125 VkDevice _device,
4126 VkFramebuffer _fb,
4127 const VkAllocationCallbacks* pAllocator)
4128 {
4129 RADV_FROM_HANDLE(radv_device, device, _device);
4130 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4131
4132 if (!fb)
4133 return;
4134 vk_free2(&device->alloc, pAllocator, fb);
4135 }
4136
4137 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4138 {
4139 switch (address_mode) {
4140 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4141 return V_008F30_SQ_TEX_WRAP;
4142 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4143 return V_008F30_SQ_TEX_MIRROR;
4144 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4145 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4146 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4147 return V_008F30_SQ_TEX_CLAMP_BORDER;
4148 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4149 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4150 default:
4151 unreachable("illegal tex wrap mode");
4152 break;
4153 }
4154 }
4155
4156 static unsigned
4157 radv_tex_compare(VkCompareOp op)
4158 {
4159 switch (op) {
4160 case VK_COMPARE_OP_NEVER:
4161 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4162 case VK_COMPARE_OP_LESS:
4163 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4164 case VK_COMPARE_OP_EQUAL:
4165 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4166 case VK_COMPARE_OP_LESS_OR_EQUAL:
4167 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4168 case VK_COMPARE_OP_GREATER:
4169 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4170 case VK_COMPARE_OP_NOT_EQUAL:
4171 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4172 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4173 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4174 case VK_COMPARE_OP_ALWAYS:
4175 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4176 default:
4177 unreachable("illegal compare mode");
4178 break;
4179 }
4180 }
4181
4182 static unsigned
4183 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4184 {
4185 switch (filter) {
4186 case VK_FILTER_NEAREST:
4187 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4188 V_008F38_SQ_TEX_XY_FILTER_POINT);
4189 case VK_FILTER_LINEAR:
4190 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4191 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4192 case VK_FILTER_CUBIC_IMG:
4193 default:
4194 fprintf(stderr, "illegal texture filter");
4195 return 0;
4196 }
4197 }
4198
4199 static unsigned
4200 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4201 {
4202 switch (mode) {
4203 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4204 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4205 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4206 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4207 default:
4208 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4209 }
4210 }
4211
4212 static unsigned
4213 radv_tex_bordercolor(VkBorderColor bcolor)
4214 {
4215 switch (bcolor) {
4216 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4217 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4218 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4219 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4220 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4221 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4222 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4223 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4224 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4225 default:
4226 break;
4227 }
4228 return 0;
4229 }
4230
4231 static unsigned
4232 radv_tex_aniso_filter(unsigned filter)
4233 {
4234 if (filter < 2)
4235 return 0;
4236 if (filter < 4)
4237 return 1;
4238 if (filter < 8)
4239 return 2;
4240 if (filter < 16)
4241 return 3;
4242 return 4;
4243 }
4244
4245 static unsigned
4246 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4247 {
4248 switch (mode) {
4249 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4250 return SQ_IMG_FILTER_MODE_BLEND;
4251 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4252 return SQ_IMG_FILTER_MODE_MIN;
4253 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4254 return SQ_IMG_FILTER_MODE_MAX;
4255 default:
4256 break;
4257 }
4258 return 0;
4259 }
4260
4261 static void
4262 radv_init_sampler(struct radv_device *device,
4263 struct radv_sampler *sampler,
4264 const VkSamplerCreateInfo *pCreateInfo)
4265 {
4266 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
4267 (uint32_t) pCreateInfo->maxAnisotropy : 0;
4268 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4269 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
4270 unsigned filter_mode = SQ_IMG_FILTER_MODE_BLEND;
4271
4272 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4273 vk_find_struct_const(pCreateInfo->pNext,
4274 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4275 if (sampler_reduction)
4276 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4277
4278 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4279 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4280 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4281 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4282 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4283 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4284 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4285 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4286 S_008F30_DISABLE_CUBE_WRAP(0) |
4287 S_008F30_COMPAT_MODE(is_vi) |
4288 S_008F30_FILTER_MODE(filter_mode));
4289 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4290 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4291 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4292 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4293 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4294 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4295 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4296 S_008F38_MIP_POINT_PRECLAMP(0) |
4297 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
4298 S_008F38_FILTER_PREC_FIX(1) |
4299 S_008F38_ANISO_OVERRIDE(is_vi));
4300 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4301 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4302 }
4303
4304 VkResult radv_CreateSampler(
4305 VkDevice _device,
4306 const VkSamplerCreateInfo* pCreateInfo,
4307 const VkAllocationCallbacks* pAllocator,
4308 VkSampler* pSampler)
4309 {
4310 RADV_FROM_HANDLE(radv_device, device, _device);
4311 struct radv_sampler *sampler;
4312
4313 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4314
4315 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4316 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4317 if (!sampler)
4318 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4319
4320 radv_init_sampler(device, sampler, pCreateInfo);
4321 *pSampler = radv_sampler_to_handle(sampler);
4322
4323 return VK_SUCCESS;
4324 }
4325
4326 void radv_DestroySampler(
4327 VkDevice _device,
4328 VkSampler _sampler,
4329 const VkAllocationCallbacks* pAllocator)
4330 {
4331 RADV_FROM_HANDLE(radv_device, device, _device);
4332 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4333
4334 if (!sampler)
4335 return;
4336 vk_free2(&device->alloc, pAllocator, sampler);
4337 }
4338
4339 /* vk_icd.h does not declare this function, so we declare it here to
4340 * suppress Wmissing-prototypes.
4341 */
4342 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4343 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
4344
4345 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4346 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
4347 {
4348 /* For the full details on loader interface versioning, see
4349 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4350 * What follows is a condensed summary, to help you navigate the large and
4351 * confusing official doc.
4352 *
4353 * - Loader interface v0 is incompatible with later versions. We don't
4354 * support it.
4355 *
4356 * - In loader interface v1:
4357 * - The first ICD entrypoint called by the loader is
4358 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4359 * entrypoint.
4360 * - The ICD must statically expose no other Vulkan symbol unless it is
4361 * linked with -Bsymbolic.
4362 * - Each dispatchable Vulkan handle created by the ICD must be
4363 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4364 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4365 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4366 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4367 * such loader-managed surfaces.
4368 *
4369 * - Loader interface v2 differs from v1 in:
4370 * - The first ICD entrypoint called by the loader is
4371 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4372 * statically expose this entrypoint.
4373 *
4374 * - Loader interface v3 differs from v2 in:
4375 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4376 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4377 * because the loader no longer does so.
4378 */
4379 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
4380 return VK_SUCCESS;
4381 }
4382
4383 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4384 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4385 int *pFD)
4386 {
4387 RADV_FROM_HANDLE(radv_device, device, _device);
4388 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4389
4390 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4391
4392 /* At the moment, we support only the below handle types. */
4393 assert(pGetFdInfo->handleType ==
4394 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4395 pGetFdInfo->handleType ==
4396 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4397
4398 bool ret = radv_get_memory_fd(device, memory, pFD);
4399 if (ret == false)
4400 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4401 return VK_SUCCESS;
4402 }
4403
4404 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
4405 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
4406 int fd,
4407 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
4408 {
4409 RADV_FROM_HANDLE(radv_device, device, _device);
4410
4411 switch (handleType) {
4412 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
4413 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
4414 return VK_SUCCESS;
4415
4416 default:
4417 /* The valid usage section for this function says:
4418 *
4419 * "handleType must not be one of the handle types defined as
4420 * opaque."
4421 *
4422 * So opaque handle types fall into the default "unsupported" case.
4423 */
4424 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4425 }
4426 }
4427
4428 static VkResult radv_import_opaque_fd(struct radv_device *device,
4429 int fd,
4430 uint32_t *syncobj)
4431 {
4432 uint32_t syncobj_handle = 0;
4433 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
4434 if (ret != 0)
4435 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4436
4437 if (*syncobj)
4438 device->ws->destroy_syncobj(device->ws, *syncobj);
4439
4440 *syncobj = syncobj_handle;
4441 close(fd);
4442
4443 return VK_SUCCESS;
4444 }
4445
4446 static VkResult radv_import_sync_fd(struct radv_device *device,
4447 int fd,
4448 uint32_t *syncobj)
4449 {
4450 /* If we create a syncobj we do it locally so that if we have an error, we don't
4451 * leave a syncobj in an undetermined state in the fence. */
4452 uint32_t syncobj_handle = *syncobj;
4453 if (!syncobj_handle) {
4454 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
4455 if (ret) {
4456 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4457 }
4458 }
4459
4460 if (fd == -1) {
4461 device->ws->signal_syncobj(device->ws, syncobj_handle);
4462 } else {
4463 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
4464 if (ret != 0)
4465 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4466 }
4467
4468 *syncobj = syncobj_handle;
4469 if (fd != -1)
4470 close(fd);
4471
4472 return VK_SUCCESS;
4473 }
4474
4475 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
4476 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
4477 {
4478 RADV_FROM_HANDLE(radv_device, device, _device);
4479 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
4480 uint32_t *syncobj_dst = NULL;
4481
4482 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
4483 syncobj_dst = &sem->temp_syncobj;
4484 } else {
4485 syncobj_dst = &sem->syncobj;
4486 }
4487
4488 switch(pImportSemaphoreFdInfo->handleType) {
4489 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4490 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4491 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4492 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4493 default:
4494 unreachable("Unhandled semaphore handle type");
4495 }
4496 }
4497
4498 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
4499 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
4500 int *pFd)
4501 {
4502 RADV_FROM_HANDLE(radv_device, device, _device);
4503 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
4504 int ret;
4505 uint32_t syncobj_handle;
4506
4507 if (sem->temp_syncobj)
4508 syncobj_handle = sem->temp_syncobj;
4509 else
4510 syncobj_handle = sem->syncobj;
4511
4512 switch(pGetFdInfo->handleType) {
4513 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4514 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4515 break;
4516 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4517 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4518 if (!ret) {
4519 if (sem->temp_syncobj) {
4520 close (sem->temp_syncobj);
4521 sem->temp_syncobj = 0;
4522 } else {
4523 device->ws->reset_syncobj(device->ws, syncobj_handle);
4524 }
4525 }
4526 break;
4527 default:
4528 unreachable("Unhandled semaphore handle type");
4529 }
4530
4531 if (ret)
4532 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4533 return VK_SUCCESS;
4534 }
4535
4536 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
4537 VkPhysicalDevice physicalDevice,
4538 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
4539 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
4540 {
4541 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4542
4543 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
4544 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4545 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4546 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4547 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4548 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4549 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4550 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4551 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
4552 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4553 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4554 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4555 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4556 } else {
4557 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
4558 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
4559 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
4560 }
4561 }
4562
4563 VkResult radv_ImportFenceFdKHR(VkDevice _device,
4564 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
4565 {
4566 RADV_FROM_HANDLE(radv_device, device, _device);
4567 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
4568 uint32_t *syncobj_dst = NULL;
4569
4570
4571 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT_KHR) {
4572 syncobj_dst = &fence->temp_syncobj;
4573 } else {
4574 syncobj_dst = &fence->syncobj;
4575 }
4576
4577 switch(pImportFenceFdInfo->handleType) {
4578 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4579 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4580 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4581 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4582 default:
4583 unreachable("Unhandled fence handle type");
4584 }
4585 }
4586
4587 VkResult radv_GetFenceFdKHR(VkDevice _device,
4588 const VkFenceGetFdInfoKHR *pGetFdInfo,
4589 int *pFd)
4590 {
4591 RADV_FROM_HANDLE(radv_device, device, _device);
4592 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
4593 int ret;
4594 uint32_t syncobj_handle;
4595
4596 if (fence->temp_syncobj)
4597 syncobj_handle = fence->temp_syncobj;
4598 else
4599 syncobj_handle = fence->syncobj;
4600
4601 switch(pGetFdInfo->handleType) {
4602 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4603 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4604 break;
4605 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4606 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4607 if (!ret) {
4608 if (fence->temp_syncobj) {
4609 close (fence->temp_syncobj);
4610 fence->temp_syncobj = 0;
4611 } else {
4612 device->ws->reset_syncobj(device->ws, syncobj_handle);
4613 }
4614 }
4615 break;
4616 default:
4617 unreachable("Unhandled fence handle type");
4618 }
4619
4620 if (ret)
4621 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4622 return VK_SUCCESS;
4623 }
4624
4625 void radv_GetPhysicalDeviceExternalFenceProperties(
4626 VkPhysicalDevice physicalDevice,
4627 const VkPhysicalDeviceExternalFenceInfoKHR* pExternalFenceInfo,
4628 VkExternalFencePropertiesKHR* pExternalFenceProperties)
4629 {
4630 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4631
4632 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4633 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4634 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4635 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4636 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4637 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT_KHR |
4638 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4639 } else {
4640 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
4641 pExternalFenceProperties->compatibleHandleTypes = 0;
4642 pExternalFenceProperties->externalFenceFeatures = 0;
4643 }
4644 }
4645
4646 VkResult
4647 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
4648 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
4649 const VkAllocationCallbacks* pAllocator,
4650 VkDebugReportCallbackEXT* pCallback)
4651 {
4652 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4653 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
4654 pCreateInfo, pAllocator, &instance->alloc,
4655 pCallback);
4656 }
4657
4658 void
4659 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
4660 VkDebugReportCallbackEXT _callback,
4661 const VkAllocationCallbacks* pAllocator)
4662 {
4663 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4664 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
4665 _callback, pAllocator, &instance->alloc);
4666 }
4667
4668 void
4669 radv_DebugReportMessageEXT(VkInstance _instance,
4670 VkDebugReportFlagsEXT flags,
4671 VkDebugReportObjectTypeEXT objectType,
4672 uint64_t object,
4673 size_t location,
4674 int32_t messageCode,
4675 const char* pLayerPrefix,
4676 const char* pMessage)
4677 {
4678 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4679 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
4680 object, location, messageCode, pLayerPrefix, pMessage);
4681 }
4682
4683 void
4684 radv_GetDeviceGroupPeerMemoryFeatures(
4685 VkDevice device,
4686 uint32_t heapIndex,
4687 uint32_t localDeviceIndex,
4688 uint32_t remoteDeviceIndex,
4689 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
4690 {
4691 assert(localDeviceIndex == remoteDeviceIndex);
4692
4693 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
4694 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
4695 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
4696 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
4697 }