2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include <linux/audit.h>
32 #include <linux/bpf.h>
33 #include <linux/filter.h>
34 #include <linux/seccomp.h>
35 #include <linux/unistd.h>
40 #include <sys/prctl.h>
45 #include "radv_debug.h"
46 #include "radv_private.h"
47 #include "radv_shader.h"
49 #include "util/disk_cache.h"
53 #include "drm-uapi/amdgpu_drm.h"
54 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
55 #include "winsys/null/radv_null_winsys_public.h"
56 #include "ac_llvm_util.h"
57 #include "vk_format.h"
60 #include "util/build_id.h"
61 #include "util/debug.h"
62 #include "util/mesa-sha1.h"
63 #include "util/timespec.h"
64 #include "util/u_atomic.h"
65 #include "compiler/glsl_types.h"
66 #include "util/driconf.h"
68 static struct radv_timeline_point
*
69 radv_timeline_find_point_at_least_locked(struct radv_device
*device
,
70 struct radv_timeline
*timeline
,
73 static struct radv_timeline_point
*
74 radv_timeline_add_point_locked(struct radv_device
*device
,
75 struct radv_timeline
*timeline
,
79 radv_timeline_trigger_waiters_locked(struct radv_timeline
*timeline
,
80 struct list_head
*processing_list
);
83 void radv_destroy_semaphore_part(struct radv_device
*device
,
84 struct radv_semaphore_part
*part
);
87 radv_device_get_cache_uuid(enum radeon_family family
, void *uuid
)
90 unsigned char sha1
[20];
91 unsigned ptr_size
= sizeof(void*);
93 memset(uuid
, 0, VK_UUID_SIZE
);
94 _mesa_sha1_init(&ctx
);
96 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid
, &ctx
) ||
97 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo
, &ctx
))
100 _mesa_sha1_update(&ctx
, &family
, sizeof(family
));
101 _mesa_sha1_update(&ctx
, &ptr_size
, sizeof(ptr_size
));
102 _mesa_sha1_final(&ctx
, sha1
);
104 memcpy(uuid
, sha1
, VK_UUID_SIZE
);
109 radv_get_driver_uuid(void *uuid
)
111 ac_compute_driver_uuid(uuid
, VK_UUID_SIZE
);
115 radv_get_device_uuid(struct radeon_info
*info
, void *uuid
)
117 ac_compute_device_uuid(info
, uuid
, VK_UUID_SIZE
);
121 radv_get_visible_vram_size(struct radv_physical_device
*device
)
123 return MIN2(device
->rad_info
.vram_size
, device
->rad_info
.vram_vis_size
);
127 radv_get_vram_size(struct radv_physical_device
*device
)
129 return device
->rad_info
.vram_size
- radv_get_visible_vram_size(device
);
133 radv_physical_device_init_mem_types(struct radv_physical_device
*device
)
135 uint64_t visible_vram_size
= radv_get_visible_vram_size(device
);
136 uint64_t vram_size
= radv_get_vram_size(device
);
137 int vram_index
= -1, visible_vram_index
= -1, gart_index
= -1;
138 device
->memory_properties
.memoryHeapCount
= 0;
140 vram_index
= device
->memory_properties
.memoryHeapCount
++;
141 device
->memory_properties
.memoryHeaps
[vram_index
] = (VkMemoryHeap
) {
143 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
147 if (device
->rad_info
.gart_size
> 0) {
148 gart_index
= device
->memory_properties
.memoryHeapCount
++;
149 device
->memory_properties
.memoryHeaps
[gart_index
] = (VkMemoryHeap
) {
150 .size
= device
->rad_info
.gart_size
,
155 if (visible_vram_size
) {
156 visible_vram_index
= device
->memory_properties
.memoryHeapCount
++;
157 device
->memory_properties
.memoryHeaps
[visible_vram_index
] = (VkMemoryHeap
) {
158 .size
= visible_vram_size
,
159 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
163 unsigned type_count
= 0;
165 if (vram_index
>= 0 || visible_vram_index
>= 0) {
166 device
->memory_domains
[type_count
] = RADEON_DOMAIN_VRAM
;
167 device
->memory_flags
[type_count
] = RADEON_FLAG_NO_CPU_ACCESS
;
168 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
169 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
,
170 .heapIndex
= vram_index
>= 0 ? vram_index
: visible_vram_index
,
174 if (gart_index
>= 0) {
175 device
->memory_domains
[type_count
] = RADEON_DOMAIN_GTT
;
176 device
->memory_flags
[type_count
] = RADEON_FLAG_GTT_WC
| RADEON_FLAG_CPU_ACCESS
;
177 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
178 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
179 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
180 .heapIndex
= gart_index
,
183 if (visible_vram_index
>= 0) {
184 device
->memory_domains
[type_count
] = RADEON_DOMAIN_VRAM
;
185 device
->memory_flags
[type_count
] = RADEON_FLAG_CPU_ACCESS
;
186 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
187 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
|
188 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
189 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
190 .heapIndex
= visible_vram_index
,
194 if (gart_index
>= 0) {
195 device
->memory_domains
[type_count
] = RADEON_DOMAIN_GTT
;
196 device
->memory_flags
[type_count
] = RADEON_FLAG_CPU_ACCESS
;
197 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
198 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
199 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
200 VK_MEMORY_PROPERTY_HOST_CACHED_BIT
,
201 .heapIndex
= gart_index
,
204 device
->memory_properties
.memoryTypeCount
= type_count
;
206 if (device
->rad_info
.has_l2_uncached
) {
207 for (int i
= 0; i
< device
->memory_properties
.memoryTypeCount
; i
++) {
208 VkMemoryType mem_type
= device
->memory_properties
.memoryTypes
[i
];
210 if ((mem_type
.propertyFlags
& (VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
211 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
)) ||
212 mem_type
.propertyFlags
== VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
) {
214 VkMemoryPropertyFlags property_flags
= mem_type
.propertyFlags
|
215 VK_MEMORY_PROPERTY_DEVICE_COHERENT_BIT_AMD
|
216 VK_MEMORY_PROPERTY_DEVICE_UNCACHED_BIT_AMD
;
218 device
->memory_domains
[type_count
] = device
->memory_domains
[i
];
219 device
->memory_flags
[type_count
] = device
->memory_flags
[i
] | RADEON_FLAG_VA_UNCACHED
;
220 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
221 .propertyFlags
= property_flags
,
222 .heapIndex
= mem_type
.heapIndex
,
226 device
->memory_properties
.memoryTypeCount
= type_count
;
231 radv_get_compiler_string(struct radv_physical_device
*pdevice
)
233 if (!pdevice
->use_llvm
) {
234 /* Some games like SotTR apply shader workarounds if the LLVM
235 * version is too old or if the LLVM version string is
236 * missing. This gives 2-5% performance with SotTR and ACO.
238 if (driQueryOptionb(&pdevice
->instance
->dri_options
,
239 "radv_report_llvm9_version_string")) {
240 return "ACO/LLVM 9.0.1";
246 return "LLVM " MESA_LLVM_VERSION_STRING
;
250 radv_physical_device_try_create(struct radv_instance
*instance
,
251 drmDevicePtr drm_device
,
252 struct radv_physical_device
**device_out
)
259 const char *path
= drm_device
->nodes
[DRM_NODE_RENDER
];
260 drmVersionPtr version
;
262 fd
= open(path
, O_RDWR
| O_CLOEXEC
);
264 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
265 radv_logi("Could not open device '%s'", path
);
267 return vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
270 version
= drmGetVersion(fd
);
274 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
275 radv_logi("Could not get the kernel driver version for device '%s'", path
);
277 return vk_errorf(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
,
278 "failed to get version %s: %m", path
);
281 if (strcmp(version
->name
, "amdgpu")) {
282 drmFreeVersion(version
);
285 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
286 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path
);
288 return VK_ERROR_INCOMPATIBLE_DRIVER
;
290 drmFreeVersion(version
);
292 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
293 radv_logi("Found compatible device '%s'.", path
);
296 struct radv_physical_device
*device
=
297 vk_zalloc2(&instance
->alloc
, NULL
, sizeof(*device
), 8,
298 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
300 result
= vk_error(instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
304 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
305 device
->instance
= instance
;
308 device
->ws
= radv_amdgpu_winsys_create(fd
, instance
->debug_flags
,
309 instance
->perftest_flags
);
311 device
->ws
= radv_null_winsys_create();
315 result
= vk_errorf(instance
, VK_ERROR_INITIALIZATION_FAILED
,
316 "failed to initialize winsys");
320 if (drm_device
&& instance
->enabled_extensions
.KHR_display
) {
321 master_fd
= open(drm_device
->nodes
[DRM_NODE_PRIMARY
], O_RDWR
| O_CLOEXEC
);
322 if (master_fd
>= 0) {
323 uint32_t accel_working
= 0;
324 struct drm_amdgpu_info request
= {
325 .return_pointer
= (uintptr_t)&accel_working
,
326 .return_size
= sizeof(accel_working
),
327 .query
= AMDGPU_INFO_ACCEL_WORKING
330 if (drmCommandWrite(master_fd
, DRM_AMDGPU_INFO
, &request
, sizeof (struct drm_amdgpu_info
)) < 0 || !accel_working
) {
337 device
->master_fd
= master_fd
;
338 device
->local_fd
= fd
;
339 device
->ws
->query_info(device
->ws
, &device
->rad_info
);
341 device
->use_llvm
= instance
->debug_flags
& RADV_DEBUG_LLVM
;
343 snprintf(device
->name
, sizeof(device
->name
),
345 device
->rad_info
.name
, radv_get_compiler_string(device
));
347 if (radv_device_get_cache_uuid(device
->rad_info
.family
, device
->cache_uuid
)) {
348 result
= vk_errorf(instance
, VK_ERROR_INITIALIZATION_FAILED
,
349 "cannot generate UUID");
353 /* These flags affect shader compilation. */
354 uint64_t shader_env_flags
= (device
->use_llvm
? 0 : 0x2);
356 /* The gpu id is already embedded in the uuid so we just pass "radv"
357 * when creating the cache.
359 char buf
[VK_UUID_SIZE
* 2 + 1];
360 disk_cache_format_hex_id(buf
, device
->cache_uuid
, VK_UUID_SIZE
* 2);
361 device
->disk_cache
= disk_cache_create(device
->name
, buf
, shader_env_flags
);
363 if (device
->rad_info
.chip_class
< GFX8
|| !device
->use_llvm
)
364 fprintf(stderr
, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
366 radv_get_driver_uuid(&device
->driver_uuid
);
367 radv_get_device_uuid(&device
->rad_info
, &device
->device_uuid
);
369 device
->out_of_order_rast_allowed
= device
->rad_info
.has_out_of_order_rast
&&
370 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_OUT_OF_ORDER
);
372 device
->dcc_msaa_allowed
=
373 (device
->instance
->perftest_flags
& RADV_PERFTEST_DCC_MSAA
);
375 device
->use_ngg
= device
->rad_info
.chip_class
>= GFX10
&&
376 device
->rad_info
.family
!= CHIP_NAVI14
&&
377 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_NGG
);
379 /* TODO: Implement NGG GS with ACO. */
380 device
->use_ngg_gs
= device
->use_ngg
&& device
->use_llvm
;
381 device
->use_ngg_streamout
= false;
383 /* Determine the number of threads per wave for all stages. */
384 device
->cs_wave_size
= 64;
385 device
->ps_wave_size
= 64;
386 device
->ge_wave_size
= 64;
388 if (device
->rad_info
.chip_class
>= GFX10
) {
389 if (device
->instance
->perftest_flags
& RADV_PERFTEST_CS_WAVE_32
)
390 device
->cs_wave_size
= 32;
392 /* For pixel shaders, wave64 is recommanded. */
393 if (device
->instance
->perftest_flags
& RADV_PERFTEST_PS_WAVE_32
)
394 device
->ps_wave_size
= 32;
396 if (device
->instance
->perftest_flags
& RADV_PERFTEST_GE_WAVE_32
)
397 device
->ge_wave_size
= 32;
400 radv_physical_device_init_mem_types(device
);
402 radv_physical_device_get_supported_extensions(device
,
403 &device
->supported_extensions
);
406 device
->bus_info
= *drm_device
->businfo
.pci
;
408 if ((device
->instance
->debug_flags
& RADV_DEBUG_INFO
))
409 ac_print_gpu_info(&device
->rad_info
);
411 /* The WSI is structured as a layer on top of the driver, so this has
412 * to be the last part of initialization (at least until we get other
415 result
= radv_init_wsi(device
);
416 if (result
!= VK_SUCCESS
) {
417 vk_error(instance
, result
);
418 goto fail_disk_cache
;
421 *device_out
= device
;
426 disk_cache_destroy(device
->disk_cache
);
428 device
->ws
->destroy(device
->ws
);
430 vk_free(&instance
->alloc
, device
);
440 radv_physical_device_destroy(struct radv_physical_device
*device
)
442 radv_finish_wsi(device
);
443 device
->ws
->destroy(device
->ws
);
444 disk_cache_destroy(device
->disk_cache
);
445 close(device
->local_fd
);
446 if (device
->master_fd
!= -1)
447 close(device
->master_fd
);
448 vk_free(&device
->instance
->alloc
, device
);
452 default_alloc_func(void *pUserData
, size_t size
, size_t align
,
453 VkSystemAllocationScope allocationScope
)
459 default_realloc_func(void *pUserData
, void *pOriginal
, size_t size
,
460 size_t align
, VkSystemAllocationScope allocationScope
)
462 return realloc(pOriginal
, size
);
466 default_free_func(void *pUserData
, void *pMemory
)
471 static const VkAllocationCallbacks default_alloc
= {
473 .pfnAllocation
= default_alloc_func
,
474 .pfnReallocation
= default_realloc_func
,
475 .pfnFree
= default_free_func
,
478 static const struct debug_control radv_debug_options
[] = {
479 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS
},
480 {"nodcc", RADV_DEBUG_NO_DCC
},
481 {"shaders", RADV_DEBUG_DUMP_SHADERS
},
482 {"nocache", RADV_DEBUG_NO_CACHE
},
483 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS
},
484 {"nohiz", RADV_DEBUG_NO_HIZ
},
485 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE
},
486 {"allbos", RADV_DEBUG_ALL_BOS
},
487 {"noibs", RADV_DEBUG_NO_IBS
},
488 {"spirv", RADV_DEBUG_DUMP_SPIRV
},
489 {"vmfaults", RADV_DEBUG_VM_FAULTS
},
490 {"zerovram", RADV_DEBUG_ZERO_VRAM
},
491 {"syncshaders", RADV_DEBUG_SYNC_SHADERS
},
492 {"preoptir", RADV_DEBUG_PREOPTIR
},
493 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS
},
494 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER
},
495 {"info", RADV_DEBUG_INFO
},
496 {"errors", RADV_DEBUG_ERRORS
},
497 {"startup", RADV_DEBUG_STARTUP
},
498 {"checkir", RADV_DEBUG_CHECKIR
},
499 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM
},
500 {"nobinning", RADV_DEBUG_NOBINNING
},
501 {"nongg", RADV_DEBUG_NO_NGG
},
502 {"allentrypoints", RADV_DEBUG_ALL_ENTRYPOINTS
},
503 {"metashaders", RADV_DEBUG_DUMP_META_SHADERS
},
504 {"nomemorycache", RADV_DEBUG_NO_MEMORY_CACHE
},
505 {"llvm", RADV_DEBUG_LLVM
},
510 radv_get_debug_option_name(int id
)
512 assert(id
< ARRAY_SIZE(radv_debug_options
) - 1);
513 return radv_debug_options
[id
].string
;
516 static const struct debug_control radv_perftest_options
[] = {
517 {"localbos", RADV_PERFTEST_LOCAL_BOS
},
518 {"dccmsaa", RADV_PERFTEST_DCC_MSAA
},
519 {"bolist", RADV_PERFTEST_BO_LIST
},
520 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK
},
521 {"cswave32", RADV_PERFTEST_CS_WAVE_32
},
522 {"pswave32", RADV_PERFTEST_PS_WAVE_32
},
523 {"gewave32", RADV_PERFTEST_GE_WAVE_32
},
524 {"dfsm", RADV_PERFTEST_DFSM
},
529 radv_get_perftest_option_name(int id
)
531 assert(id
< ARRAY_SIZE(radv_perftest_options
) - 1);
532 return radv_perftest_options
[id
].string
;
536 radv_handle_per_app_options(struct radv_instance
*instance
,
537 const VkApplicationInfo
*info
)
539 const char *name
= info
? info
->pApplicationName
: NULL
;
540 const char *engine_name
= info
? info
->pEngineName
: NULL
;
543 if (!strcmp(name
, "DOOM_VFR")) {
544 /* Work around a Doom VFR game bug */
545 instance
->debug_flags
|= RADV_DEBUG_NO_DYNAMIC_BOUNDS
;
546 } else if (!strcmp(name
, "Fledge")) {
548 * Zero VRAM for "The Surge 2"
550 * This avoid a hang when when rendering any level. Likely
551 * uninitialized data in an indirect draw.
553 instance
->debug_flags
|= RADV_DEBUG_ZERO_VRAM
;
554 } else if (!strcmp(name
, "No Man's Sky")) {
555 /* Work around a NMS game bug */
556 instance
->debug_flags
|= RADV_DEBUG_DISCARD_TO_DEMOTE
;
557 } else if (!strcmp(name
, "DOOMEternal")) {
558 /* Zero VRAM for Doom Eternal to fix rendering issues. */
559 instance
->debug_flags
|= RADV_DEBUG_ZERO_VRAM
;
560 } else if (!strcmp(name
, "Red Dead Redemption 2")) {
561 /* Work around a RDR2 game bug */
562 instance
->debug_flags
|= RADV_DEBUG_DISCARD_TO_DEMOTE
;
567 if (!strcmp(engine_name
, "vkd3d")) {
568 /* Zero VRAM for all VKD3D (DX12->VK) games to fix
571 instance
->debug_flags
|= RADV_DEBUG_ZERO_VRAM
;
572 } else if (!strcmp(engine_name
, "Quantic Dream Engine")) {
573 /* Fix various artifacts in Detroit: Become Human */
574 instance
->debug_flags
|= RADV_DEBUG_ZERO_VRAM
|
575 RADV_DEBUG_DISCARD_TO_DEMOTE
;
579 instance
->enable_mrt_output_nan_fixup
=
580 driQueryOptionb(&instance
->dri_options
,
581 "radv_enable_mrt_output_nan_fixup");
583 if (driQueryOptionb(&instance
->dri_options
, "radv_no_dynamic_bounds"))
584 instance
->debug_flags
|= RADV_DEBUG_NO_DYNAMIC_BOUNDS
;
587 static const char radv_dri_options_xml
[] =
589 DRI_CONF_SECTION_PERFORMANCE
590 DRI_CONF_ADAPTIVE_SYNC("true")
591 DRI_CONF_VK_X11_OVERRIDE_MIN_IMAGE_COUNT(0)
592 DRI_CONF_VK_X11_STRICT_IMAGE_COUNT("false")
593 DRI_CONF_VK_X11_ENSURE_MIN_IMAGE_COUNT("false")
594 DRI_CONF_RADV_REPORT_LLVM9_VERSION_STRING("false")
595 DRI_CONF_RADV_ENABLE_MRT_OUTPUT_NAN_FIXUP("false")
596 DRI_CONF_RADV_NO_DYNAMIC_BOUNDS("false")
599 DRI_CONF_SECTION_DEBUG
600 DRI_CONF_VK_WSI_FORCE_BGRA8_UNORM_FIRST("false")
604 static void radv_init_dri_options(struct radv_instance
*instance
)
606 driParseOptionInfo(&instance
->available_dri_options
, radv_dri_options_xml
);
607 driParseConfigFiles(&instance
->dri_options
,
608 &instance
->available_dri_options
,
610 instance
->engineName
,
611 instance
->engineVersion
);
614 VkResult
radv_CreateInstance(
615 const VkInstanceCreateInfo
* pCreateInfo
,
616 const VkAllocationCallbacks
* pAllocator
,
617 VkInstance
* pInstance
)
619 struct radv_instance
*instance
;
622 instance
= vk_zalloc2(&default_alloc
, pAllocator
, sizeof(*instance
), 8,
623 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
625 return vk_error(NULL
, VK_ERROR_OUT_OF_HOST_MEMORY
);
627 vk_object_base_init(NULL
, &instance
->base
, VK_OBJECT_TYPE_INSTANCE
);
630 instance
->alloc
= *pAllocator
;
632 instance
->alloc
= default_alloc
;
634 if (pCreateInfo
->pApplicationInfo
) {
635 const VkApplicationInfo
*app
= pCreateInfo
->pApplicationInfo
;
637 instance
->engineName
=
638 vk_strdup(&instance
->alloc
, app
->pEngineName
,
639 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
640 instance
->engineVersion
= app
->engineVersion
;
641 instance
->apiVersion
= app
->apiVersion
;
644 if (instance
->apiVersion
== 0)
645 instance
->apiVersion
= VK_API_VERSION_1_0
;
647 instance
->debug_flags
= parse_debug_string(getenv("RADV_DEBUG"),
650 instance
->perftest_flags
= parse_debug_string(getenv("RADV_PERFTEST"),
651 radv_perftest_options
);
653 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
654 radv_logi("Created an instance");
656 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
658 for (idx
= 0; idx
< RADV_INSTANCE_EXTENSION_COUNT
; idx
++) {
659 if (!strcmp(pCreateInfo
->ppEnabledExtensionNames
[i
],
660 radv_instance_extensions
[idx
].extensionName
))
664 if (idx
>= RADV_INSTANCE_EXTENSION_COUNT
||
665 !radv_instance_extensions_supported
.extensions
[idx
]) {
666 vk_object_base_finish(&instance
->base
);
667 vk_free2(&default_alloc
, pAllocator
, instance
);
668 return vk_error(instance
, VK_ERROR_EXTENSION_NOT_PRESENT
);
671 instance
->enabled_extensions
.extensions
[idx
] = true;
674 bool unchecked
= instance
->debug_flags
& RADV_DEBUG_ALL_ENTRYPOINTS
;
676 for (unsigned i
= 0; i
< ARRAY_SIZE(instance
->dispatch
.entrypoints
); i
++) {
677 /* Vulkan requires that entrypoints for extensions which have
678 * not been enabled must not be advertised.
681 !radv_instance_entrypoint_is_enabled(i
, instance
->apiVersion
,
682 &instance
->enabled_extensions
)) {
683 instance
->dispatch
.entrypoints
[i
] = NULL
;
685 instance
->dispatch
.entrypoints
[i
] =
686 radv_instance_dispatch_table
.entrypoints
[i
];
690 for (unsigned i
= 0; i
< ARRAY_SIZE(instance
->physical_device_dispatch
.entrypoints
); i
++) {
691 /* Vulkan requires that entrypoints for extensions which have
692 * not been enabled must not be advertised.
695 !radv_physical_device_entrypoint_is_enabled(i
, instance
->apiVersion
,
696 &instance
->enabled_extensions
)) {
697 instance
->physical_device_dispatch
.entrypoints
[i
] = NULL
;
699 instance
->physical_device_dispatch
.entrypoints
[i
] =
700 radv_physical_device_dispatch_table
.entrypoints
[i
];
704 for (unsigned i
= 0; i
< ARRAY_SIZE(instance
->device_dispatch
.entrypoints
); i
++) {
705 /* Vulkan requires that entrypoints for extensions which have
706 * not been enabled must not be advertised.
709 !radv_device_entrypoint_is_enabled(i
, instance
->apiVersion
,
710 &instance
->enabled_extensions
, NULL
)) {
711 instance
->device_dispatch
.entrypoints
[i
] = NULL
;
713 instance
->device_dispatch
.entrypoints
[i
] =
714 radv_device_dispatch_table
.entrypoints
[i
];
718 instance
->physical_devices_enumerated
= false;
719 list_inithead(&instance
->physical_devices
);
721 result
= vk_debug_report_instance_init(&instance
->debug_report_callbacks
);
722 if (result
!= VK_SUCCESS
) {
723 vk_object_base_finish(&instance
->base
);
724 vk_free2(&default_alloc
, pAllocator
, instance
);
725 return vk_error(instance
, result
);
728 glsl_type_singleton_init_or_ref();
730 VG(VALGRIND_CREATE_MEMPOOL(instance
, 0, false));
732 radv_init_dri_options(instance
);
733 radv_handle_per_app_options(instance
, pCreateInfo
->pApplicationInfo
);
735 *pInstance
= radv_instance_to_handle(instance
);
740 void radv_DestroyInstance(
741 VkInstance _instance
,
742 const VkAllocationCallbacks
* pAllocator
)
744 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
749 list_for_each_entry_safe(struct radv_physical_device
, pdevice
,
750 &instance
->physical_devices
, link
) {
751 radv_physical_device_destroy(pdevice
);
754 vk_free(&instance
->alloc
, instance
->engineName
);
756 VG(VALGRIND_DESTROY_MEMPOOL(instance
));
758 glsl_type_singleton_decref();
760 driDestroyOptionCache(&instance
->dri_options
);
761 driDestroyOptionInfo(&instance
->available_dri_options
);
763 vk_debug_report_instance_destroy(&instance
->debug_report_callbacks
);
765 vk_object_base_finish(&instance
->base
);
766 vk_free(&instance
->alloc
, instance
);
770 radv_enumerate_physical_devices(struct radv_instance
*instance
)
772 if (instance
->physical_devices_enumerated
)
775 instance
->physical_devices_enumerated
= true;
777 /* TODO: Check for more devices ? */
778 drmDevicePtr devices
[8];
779 VkResult result
= VK_SUCCESS
;
782 if (getenv("RADV_FORCE_FAMILY")) {
783 /* When RADV_FORCE_FAMILY is set, the driver creates a nul
784 * device that allows to test the compiler without having an
787 struct radv_physical_device
*pdevice
;
789 result
= radv_physical_device_try_create(instance
, NULL
, &pdevice
);
790 if (result
!= VK_SUCCESS
)
793 list_addtail(&pdevice
->link
, &instance
->physical_devices
);
797 max_devices
= drmGetDevices2(0, devices
, ARRAY_SIZE(devices
));
799 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
800 radv_logi("Found %d drm nodes", max_devices
);
803 return vk_error(instance
, VK_SUCCESS
);
805 for (unsigned i
= 0; i
< (unsigned)max_devices
; i
++) {
806 if (devices
[i
]->available_nodes
& 1 << DRM_NODE_RENDER
&&
807 devices
[i
]->bustype
== DRM_BUS_PCI
&&
808 devices
[i
]->deviceinfo
.pci
->vendor_id
== ATI_VENDOR_ID
) {
810 struct radv_physical_device
*pdevice
;
811 result
= radv_physical_device_try_create(instance
, devices
[i
],
813 /* Incompatible DRM device, skip. */
814 if (result
== VK_ERROR_INCOMPATIBLE_DRIVER
) {
819 /* Error creating the physical device, report the error. */
820 if (result
!= VK_SUCCESS
)
823 list_addtail(&pdevice
->link
, &instance
->physical_devices
);
826 drmFreeDevices(devices
, max_devices
);
828 /* If we successfully enumerated any devices, call it success */
832 VkResult
radv_EnumeratePhysicalDevices(
833 VkInstance _instance
,
834 uint32_t* pPhysicalDeviceCount
,
835 VkPhysicalDevice
* pPhysicalDevices
)
837 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
838 VK_OUTARRAY_MAKE(out
, pPhysicalDevices
, pPhysicalDeviceCount
);
840 VkResult result
= radv_enumerate_physical_devices(instance
);
841 if (result
!= VK_SUCCESS
)
844 list_for_each_entry(struct radv_physical_device
, pdevice
,
845 &instance
->physical_devices
, link
) {
846 vk_outarray_append(&out
, i
) {
847 *i
= radv_physical_device_to_handle(pdevice
);
851 return vk_outarray_status(&out
);
854 VkResult
radv_EnumeratePhysicalDeviceGroups(
855 VkInstance _instance
,
856 uint32_t* pPhysicalDeviceGroupCount
,
857 VkPhysicalDeviceGroupProperties
* pPhysicalDeviceGroupProperties
)
859 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
860 VK_OUTARRAY_MAKE(out
, pPhysicalDeviceGroupProperties
,
861 pPhysicalDeviceGroupCount
);
863 VkResult result
= radv_enumerate_physical_devices(instance
);
864 if (result
!= VK_SUCCESS
)
867 list_for_each_entry(struct radv_physical_device
, pdevice
,
868 &instance
->physical_devices
, link
) {
869 vk_outarray_append(&out
, p
) {
870 p
->physicalDeviceCount
= 1;
871 memset(p
->physicalDevices
, 0, sizeof(p
->physicalDevices
));
872 p
->physicalDevices
[0] = radv_physical_device_to_handle(pdevice
);
873 p
->subsetAllocation
= false;
877 return vk_outarray_status(&out
);
880 void radv_GetPhysicalDeviceFeatures(
881 VkPhysicalDevice physicalDevice
,
882 VkPhysicalDeviceFeatures
* pFeatures
)
884 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
885 memset(pFeatures
, 0, sizeof(*pFeatures
));
887 *pFeatures
= (VkPhysicalDeviceFeatures
) {
888 .robustBufferAccess
= true,
889 .fullDrawIndexUint32
= true,
890 .imageCubeArray
= true,
891 .independentBlend
= true,
892 .geometryShader
= true,
893 .tessellationShader
= true,
894 .sampleRateShading
= true,
895 .dualSrcBlend
= true,
897 .multiDrawIndirect
= true,
898 .drawIndirectFirstInstance
= true,
900 .depthBiasClamp
= true,
901 .fillModeNonSolid
= true,
906 .multiViewport
= true,
907 .samplerAnisotropy
= true,
908 .textureCompressionETC2
= radv_device_supports_etc(pdevice
),
909 .textureCompressionASTC_LDR
= false,
910 .textureCompressionBC
= true,
911 .occlusionQueryPrecise
= true,
912 .pipelineStatisticsQuery
= true,
913 .vertexPipelineStoresAndAtomics
= true,
914 .fragmentStoresAndAtomics
= true,
915 .shaderTessellationAndGeometryPointSize
= true,
916 .shaderImageGatherExtended
= true,
917 .shaderStorageImageExtendedFormats
= true,
918 .shaderStorageImageMultisample
= true,
919 .shaderUniformBufferArrayDynamicIndexing
= true,
920 .shaderSampledImageArrayDynamicIndexing
= true,
921 .shaderStorageBufferArrayDynamicIndexing
= true,
922 .shaderStorageImageArrayDynamicIndexing
= true,
923 .shaderStorageImageReadWithoutFormat
= true,
924 .shaderStorageImageWriteWithoutFormat
= true,
925 .shaderClipDistance
= true,
926 .shaderCullDistance
= true,
927 .shaderFloat64
= true,
930 .sparseBinding
= true,
931 .variableMultisampleRate
= true,
932 .shaderResourceMinLod
= true,
933 .inheritedQueries
= true,
938 radv_get_physical_device_features_1_1(struct radv_physical_device
*pdevice
,
939 VkPhysicalDeviceVulkan11Features
*f
)
941 assert(f
->sType
== VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES
);
943 f
->storageBuffer16BitAccess
= true;
944 f
->uniformAndStorageBuffer16BitAccess
= true;
945 f
->storagePushConstant16
= true;
946 f
->storageInputOutput16
= pdevice
->rad_info
.has_packed_math_16bit
&& (LLVM_VERSION_MAJOR
>= 9 || !pdevice
->use_llvm
);
948 f
->multiviewGeometryShader
= true;
949 f
->multiviewTessellationShader
= true;
950 f
->variablePointersStorageBuffer
= true;
951 f
->variablePointers
= true;
952 f
->protectedMemory
= false;
953 f
->samplerYcbcrConversion
= true;
954 f
->shaderDrawParameters
= true;
958 radv_get_physical_device_features_1_2(struct radv_physical_device
*pdevice
,
959 VkPhysicalDeviceVulkan12Features
*f
)
961 assert(f
->sType
== VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES
);
963 f
->samplerMirrorClampToEdge
= true;
964 f
->drawIndirectCount
= true;
965 f
->storageBuffer8BitAccess
= true;
966 f
->uniformAndStorageBuffer8BitAccess
= true;
967 f
->storagePushConstant8
= true;
968 f
->shaderBufferInt64Atomics
= LLVM_VERSION_MAJOR
>= 9 || !pdevice
->use_llvm
;
969 f
->shaderSharedInt64Atomics
= LLVM_VERSION_MAJOR
>= 9 || !pdevice
->use_llvm
;
970 f
->shaderFloat16
= pdevice
->rad_info
.has_packed_math_16bit
;
971 f
->shaderInt8
= true;
973 f
->descriptorIndexing
= true;
974 f
->shaderInputAttachmentArrayDynamicIndexing
= true;
975 f
->shaderUniformTexelBufferArrayDynamicIndexing
= true;
976 f
->shaderStorageTexelBufferArrayDynamicIndexing
= true;
977 f
->shaderUniformBufferArrayNonUniformIndexing
= true;
978 f
->shaderSampledImageArrayNonUniformIndexing
= true;
979 f
->shaderStorageBufferArrayNonUniformIndexing
= true;
980 f
->shaderStorageImageArrayNonUniformIndexing
= true;
981 f
->shaderInputAttachmentArrayNonUniformIndexing
= true;
982 f
->shaderUniformTexelBufferArrayNonUniformIndexing
= true;
983 f
->shaderStorageTexelBufferArrayNonUniformIndexing
= true;
984 f
->descriptorBindingUniformBufferUpdateAfterBind
= true;
985 f
->descriptorBindingSampledImageUpdateAfterBind
= true;
986 f
->descriptorBindingStorageImageUpdateAfterBind
= true;
987 f
->descriptorBindingStorageBufferUpdateAfterBind
= true;
988 f
->descriptorBindingUniformTexelBufferUpdateAfterBind
= true;
989 f
->descriptorBindingStorageTexelBufferUpdateAfterBind
= true;
990 f
->descriptorBindingUpdateUnusedWhilePending
= true;
991 f
->descriptorBindingPartiallyBound
= true;
992 f
->descriptorBindingVariableDescriptorCount
= true;
993 f
->runtimeDescriptorArray
= true;
995 f
->samplerFilterMinmax
= true;
996 f
->scalarBlockLayout
= pdevice
->rad_info
.chip_class
>= GFX7
;
997 f
->imagelessFramebuffer
= true;
998 f
->uniformBufferStandardLayout
= true;
999 f
->shaderSubgroupExtendedTypes
= true;
1000 f
->separateDepthStencilLayouts
= true;
1001 f
->hostQueryReset
= true;
1002 f
->timelineSemaphore
= pdevice
->rad_info
.has_syncobj_wait_for_submit
;
1003 f
->bufferDeviceAddress
= true;
1004 f
->bufferDeviceAddressCaptureReplay
= false;
1005 f
->bufferDeviceAddressMultiDevice
= false;
1006 f
->vulkanMemoryModel
= false;
1007 f
->vulkanMemoryModelDeviceScope
= false;
1008 f
->vulkanMemoryModelAvailabilityVisibilityChains
= false;
1009 f
->shaderOutputViewportIndex
= true;
1010 f
->shaderOutputLayer
= true;
1011 f
->subgroupBroadcastDynamicId
= true;
1014 void radv_GetPhysicalDeviceFeatures2(
1015 VkPhysicalDevice physicalDevice
,
1016 VkPhysicalDeviceFeatures2
*pFeatures
)
1018 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1019 radv_GetPhysicalDeviceFeatures(physicalDevice
, &pFeatures
->features
);
1021 VkPhysicalDeviceVulkan11Features core_1_1
= {
1022 .sType
= VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES
,
1024 radv_get_physical_device_features_1_1(pdevice
, &core_1_1
);
1026 VkPhysicalDeviceVulkan12Features core_1_2
= {
1027 .sType
= VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES
,
1029 radv_get_physical_device_features_1_2(pdevice
, &core_1_2
);
1031 #define CORE_FEATURE(major, minor, feature) \
1032 features->feature = core_##major##_##minor.feature
1034 vk_foreach_struct(ext
, pFeatures
->pNext
) {
1035 switch (ext
->sType
) {
1036 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES
: {
1037 VkPhysicalDeviceVariablePointersFeatures
*features
= (void *)ext
;
1038 CORE_FEATURE(1, 1, variablePointersStorageBuffer
);
1039 CORE_FEATURE(1, 1, variablePointers
);
1042 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES
: {
1043 VkPhysicalDeviceMultiviewFeatures
*features
= (VkPhysicalDeviceMultiviewFeatures
*)ext
;
1044 CORE_FEATURE(1, 1, multiview
);
1045 CORE_FEATURE(1, 1, multiviewGeometryShader
);
1046 CORE_FEATURE(1, 1, multiviewTessellationShader
);
1049 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES
: {
1050 VkPhysicalDeviceShaderDrawParametersFeatures
*features
=
1051 (VkPhysicalDeviceShaderDrawParametersFeatures
*)ext
;
1052 CORE_FEATURE(1, 1, shaderDrawParameters
);
1055 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES
: {
1056 VkPhysicalDeviceProtectedMemoryFeatures
*features
=
1057 (VkPhysicalDeviceProtectedMemoryFeatures
*)ext
;
1058 CORE_FEATURE(1, 1, protectedMemory
);
1061 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES
: {
1062 VkPhysicalDevice16BitStorageFeatures
*features
=
1063 (VkPhysicalDevice16BitStorageFeatures
*)ext
;
1064 CORE_FEATURE(1, 1, storageBuffer16BitAccess
);
1065 CORE_FEATURE(1, 1, uniformAndStorageBuffer16BitAccess
);
1066 CORE_FEATURE(1, 1, storagePushConstant16
);
1067 CORE_FEATURE(1, 1, storageInputOutput16
);
1070 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES
: {
1071 VkPhysicalDeviceSamplerYcbcrConversionFeatures
*features
=
1072 (VkPhysicalDeviceSamplerYcbcrConversionFeatures
*)ext
;
1073 CORE_FEATURE(1, 1, samplerYcbcrConversion
);
1076 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES
: {
1077 VkPhysicalDeviceDescriptorIndexingFeatures
*features
=
1078 (VkPhysicalDeviceDescriptorIndexingFeatures
*)ext
;
1079 CORE_FEATURE(1, 2, shaderInputAttachmentArrayDynamicIndexing
);
1080 CORE_FEATURE(1, 2, shaderUniformTexelBufferArrayDynamicIndexing
);
1081 CORE_FEATURE(1, 2, shaderStorageTexelBufferArrayDynamicIndexing
);
1082 CORE_FEATURE(1, 2, shaderUniformBufferArrayNonUniformIndexing
);
1083 CORE_FEATURE(1, 2, shaderSampledImageArrayNonUniformIndexing
);
1084 CORE_FEATURE(1, 2, shaderStorageBufferArrayNonUniformIndexing
);
1085 CORE_FEATURE(1, 2, shaderStorageImageArrayNonUniformIndexing
);
1086 CORE_FEATURE(1, 2, shaderInputAttachmentArrayNonUniformIndexing
);
1087 CORE_FEATURE(1, 2, shaderUniformTexelBufferArrayNonUniformIndexing
);
1088 CORE_FEATURE(1, 2, shaderStorageTexelBufferArrayNonUniformIndexing
);
1089 CORE_FEATURE(1, 2, descriptorBindingUniformBufferUpdateAfterBind
);
1090 CORE_FEATURE(1, 2, descriptorBindingSampledImageUpdateAfterBind
);
1091 CORE_FEATURE(1, 2, descriptorBindingStorageImageUpdateAfterBind
);
1092 CORE_FEATURE(1, 2, descriptorBindingStorageBufferUpdateAfterBind
);
1093 CORE_FEATURE(1, 2, descriptorBindingUniformTexelBufferUpdateAfterBind
);
1094 CORE_FEATURE(1, 2, descriptorBindingStorageTexelBufferUpdateAfterBind
);
1095 CORE_FEATURE(1, 2, descriptorBindingUpdateUnusedWhilePending
);
1096 CORE_FEATURE(1, 2, descriptorBindingPartiallyBound
);
1097 CORE_FEATURE(1, 2, descriptorBindingVariableDescriptorCount
);
1098 CORE_FEATURE(1, 2, runtimeDescriptorArray
);
1101 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT
: {
1102 VkPhysicalDeviceConditionalRenderingFeaturesEXT
*features
=
1103 (VkPhysicalDeviceConditionalRenderingFeaturesEXT
*)ext
;
1104 features
->conditionalRendering
= true;
1105 features
->inheritedConditionalRendering
= false;
1108 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT
: {
1109 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT
*features
=
1110 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT
*)ext
;
1111 features
->vertexAttributeInstanceRateDivisor
= true;
1112 features
->vertexAttributeInstanceRateZeroDivisor
= true;
1115 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT
: {
1116 VkPhysicalDeviceTransformFeedbackFeaturesEXT
*features
=
1117 (VkPhysicalDeviceTransformFeedbackFeaturesEXT
*)ext
;
1118 features
->transformFeedback
= true;
1119 features
->geometryStreams
= !pdevice
->use_ngg_streamout
;
1122 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES
: {
1123 VkPhysicalDeviceScalarBlockLayoutFeatures
*features
=
1124 (VkPhysicalDeviceScalarBlockLayoutFeatures
*)ext
;
1125 CORE_FEATURE(1, 2, scalarBlockLayout
);
1128 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT
: {
1129 VkPhysicalDeviceMemoryPriorityFeaturesEXT
*features
=
1130 (VkPhysicalDeviceMemoryPriorityFeaturesEXT
*)ext
;
1131 features
->memoryPriority
= true;
1134 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT
: {
1135 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT
*features
=
1136 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT
*)ext
;
1137 features
->bufferDeviceAddress
= true;
1138 features
->bufferDeviceAddressCaptureReplay
= false;
1139 features
->bufferDeviceAddressMultiDevice
= false;
1142 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES
: {
1143 VkPhysicalDeviceBufferDeviceAddressFeatures
*features
=
1144 (VkPhysicalDeviceBufferDeviceAddressFeatures
*)ext
;
1145 CORE_FEATURE(1, 2, bufferDeviceAddress
);
1146 CORE_FEATURE(1, 2, bufferDeviceAddressCaptureReplay
);
1147 CORE_FEATURE(1, 2, bufferDeviceAddressMultiDevice
);
1150 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT
: {
1151 VkPhysicalDeviceDepthClipEnableFeaturesEXT
*features
=
1152 (VkPhysicalDeviceDepthClipEnableFeaturesEXT
*)ext
;
1153 features
->depthClipEnable
= true;
1156 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES
: {
1157 VkPhysicalDeviceHostQueryResetFeatures
*features
=
1158 (VkPhysicalDeviceHostQueryResetFeatures
*)ext
;
1159 CORE_FEATURE(1, 2, hostQueryReset
);
1162 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES
: {
1163 VkPhysicalDevice8BitStorageFeatures
*features
=
1164 (VkPhysicalDevice8BitStorageFeatures
*)ext
;
1165 CORE_FEATURE(1, 2, storageBuffer8BitAccess
);
1166 CORE_FEATURE(1, 2, uniformAndStorageBuffer8BitAccess
);
1167 CORE_FEATURE(1, 2, storagePushConstant8
);
1170 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_FLOAT16_INT8_FEATURES
: {
1171 VkPhysicalDeviceShaderFloat16Int8Features
*features
=
1172 (VkPhysicalDeviceShaderFloat16Int8Features
*)ext
;
1173 CORE_FEATURE(1, 2, shaderFloat16
);
1174 CORE_FEATURE(1, 2, shaderInt8
);
1177 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES
: {
1178 VkPhysicalDeviceShaderAtomicInt64Features
*features
=
1179 (VkPhysicalDeviceShaderAtomicInt64Features
*)ext
;
1180 CORE_FEATURE(1, 2, shaderBufferInt64Atomics
);
1181 CORE_FEATURE(1, 2, shaderSharedInt64Atomics
);
1184 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DEMOTE_TO_HELPER_INVOCATION_FEATURES_EXT
: {
1185 VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT
*features
=
1186 (VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT
*)ext
;
1187 features
->shaderDemoteToHelperInvocation
= LLVM_VERSION_MAJOR
>= 9 || !pdevice
->use_llvm
;
1190 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT
: {
1191 VkPhysicalDeviceInlineUniformBlockFeaturesEXT
*features
=
1192 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT
*)ext
;
1194 features
->inlineUniformBlock
= true;
1195 features
->descriptorBindingInlineUniformBlockUpdateAfterBind
= true;
1198 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV
: {
1199 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV
*features
=
1200 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV
*)ext
;
1201 features
->computeDerivativeGroupQuads
= false;
1202 features
->computeDerivativeGroupLinear
= true;
1205 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT
: {
1206 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT
*features
=
1207 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT
*)ext
;
1208 features
->ycbcrImageArrays
= true;
1211 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES
: {
1212 VkPhysicalDeviceUniformBufferStandardLayoutFeatures
*features
=
1213 (VkPhysicalDeviceUniformBufferStandardLayoutFeatures
*)ext
;
1214 CORE_FEATURE(1, 2, uniformBufferStandardLayout
);
1217 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT
: {
1218 VkPhysicalDeviceIndexTypeUint8FeaturesEXT
*features
=
1219 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT
*)ext
;
1220 features
->indexTypeUint8
= pdevice
->rad_info
.chip_class
>= GFX8
;
1223 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGELESS_FRAMEBUFFER_FEATURES
: {
1224 VkPhysicalDeviceImagelessFramebufferFeatures
*features
=
1225 (VkPhysicalDeviceImagelessFramebufferFeatures
*)ext
;
1226 CORE_FEATURE(1, 2, imagelessFramebuffer
);
1229 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR
: {
1230 VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR
*features
=
1231 (VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR
*)ext
;
1232 features
->pipelineExecutableInfo
= true;
1235 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CLOCK_FEATURES_KHR
: {
1236 VkPhysicalDeviceShaderClockFeaturesKHR
*features
=
1237 (VkPhysicalDeviceShaderClockFeaturesKHR
*)ext
;
1238 features
->shaderSubgroupClock
= true;
1239 features
->shaderDeviceClock
= pdevice
->rad_info
.chip_class
>= GFX8
;
1242 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_FEATURES_EXT
: {
1243 VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT
*features
=
1244 (VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT
*)ext
;
1245 features
->texelBufferAlignment
= true;
1248 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_FEATURES
: {
1249 VkPhysicalDeviceTimelineSemaphoreFeatures
*features
=
1250 (VkPhysicalDeviceTimelineSemaphoreFeatures
*) ext
;
1251 CORE_FEATURE(1, 2, timelineSemaphore
);
1254 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_FEATURES_EXT
: {
1255 VkPhysicalDeviceSubgroupSizeControlFeaturesEXT
*features
=
1256 (VkPhysicalDeviceSubgroupSizeControlFeaturesEXT
*)ext
;
1257 features
->subgroupSizeControl
= true;
1258 features
->computeFullSubgroups
= true;
1261 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COHERENT_MEMORY_FEATURES_AMD
: {
1262 VkPhysicalDeviceCoherentMemoryFeaturesAMD
*features
=
1263 (VkPhysicalDeviceCoherentMemoryFeaturesAMD
*)ext
;
1264 features
->deviceCoherentMemory
= pdevice
->rad_info
.has_l2_uncached
;
1267 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_SUBGROUP_EXTENDED_TYPES_FEATURES
: {
1268 VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures
*features
=
1269 (VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures
*)ext
;
1270 CORE_FEATURE(1, 2, shaderSubgroupExtendedTypes
);
1273 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SEPARATE_DEPTH_STENCIL_LAYOUTS_FEATURES_KHR
: {
1274 VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR
*features
=
1275 (VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR
*)ext
;
1276 CORE_FEATURE(1, 2, separateDepthStencilLayouts
);
1279 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES
: {
1280 radv_get_physical_device_features_1_1(pdevice
, (void *)ext
);
1283 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES
: {
1284 radv_get_physical_device_features_1_2(pdevice
, (void *)ext
);
1287 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_FEATURES_EXT
: {
1288 VkPhysicalDeviceLineRasterizationFeaturesEXT
*features
=
1289 (VkPhysicalDeviceLineRasterizationFeaturesEXT
*)ext
;
1290 features
->rectangularLines
= false;
1291 features
->bresenhamLines
= true;
1292 features
->smoothLines
= false;
1293 features
->stippledRectangularLines
= false;
1294 features
->stippledBresenhamLines
= true;
1295 features
->stippledSmoothLines
= false;
1298 case VK_STRUCTURE_TYPE_DEVICE_MEMORY_OVERALLOCATION_CREATE_INFO_AMD
: {
1299 VkDeviceMemoryOverallocationCreateInfoAMD
*features
=
1300 (VkDeviceMemoryOverallocationCreateInfoAMD
*)ext
;
1301 features
->overallocationBehavior
= true;
1304 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ROBUSTNESS_2_FEATURES_EXT
: {
1305 VkPhysicalDeviceRobustness2FeaturesEXT
*features
=
1306 (VkPhysicalDeviceRobustness2FeaturesEXT
*)ext
;
1307 features
->robustBufferAccess2
= true;
1308 features
->robustImageAccess2
= true;
1309 features
->nullDescriptor
= true;
1312 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_FEATURES_EXT
: {
1313 VkPhysicalDeviceCustomBorderColorFeaturesEXT
*features
=
1314 (VkPhysicalDeviceCustomBorderColorFeaturesEXT
*)ext
;
1315 features
->customBorderColors
= true;
1316 features
->customBorderColorWithoutFormat
= true;
1319 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PRIVATE_DATA_FEATURES_EXT
: {
1320 VkPhysicalDevicePrivateDataFeaturesEXT
*features
=
1321 (VkPhysicalDevicePrivateDataFeaturesEXT
*)ext
;
1322 features
->privateData
= true;
1325 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_CREATION_CACHE_CONTROL_FEATURES_EXT
: {
1326 VkPhysicalDevicePipelineCreationCacheControlFeaturesEXT
*features
=
1327 (VkPhysicalDevicePipelineCreationCacheControlFeaturesEXT
*)ext
;
1328 features
-> pipelineCreationCacheControl
= true;
1331 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTENDED_DYNAMIC_STATE_FEATURES_EXT
: {
1332 VkPhysicalDeviceExtendedDynamicStateFeaturesEXT
*features
=
1333 (VkPhysicalDeviceExtendedDynamicStateFeaturesEXT
*) ext
;
1334 features
->extendedDynamicState
= true;
1337 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGE_ROBUSTNESS_FEATURES_EXT
: {
1338 VkPhysicalDeviceImageRobustnessFeaturesEXT
*features
=
1339 (VkPhysicalDeviceImageRobustnessFeaturesEXT
*)ext
;
1340 features
->robustImageAccess
= true;
1343 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_FLOAT_FEATURES_EXT
: {
1344 VkPhysicalDeviceShaderAtomicFloatFeaturesEXT
*features
=
1345 (VkPhysicalDeviceShaderAtomicFloatFeaturesEXT
*)ext
;
1346 features
->shaderBufferFloat32Atomics
= true;
1347 features
->shaderBufferFloat32AtomicAdd
= false;
1348 features
->shaderBufferFloat64Atomics
= true;
1349 features
->shaderBufferFloat64AtomicAdd
= false;
1350 features
->shaderSharedFloat32Atomics
= true;
1351 features
->shaderSharedFloat32AtomicAdd
= pdevice
->rad_info
.chip_class
>= GFX8
&&
1352 (!pdevice
->use_llvm
|| LLVM_VERSION_MAJOR
>= 10);
1353 features
->shaderSharedFloat64Atomics
= true;
1354 features
->shaderSharedFloat64AtomicAdd
= false;
1355 features
->shaderImageFloat32Atomics
= true;
1356 features
->shaderImageFloat32AtomicAdd
= false;
1357 features
->sparseImageFloat32Atomics
= false;
1358 features
->sparseImageFloat32AtomicAdd
= false;
1369 radv_max_descriptor_set_size()
1371 /* make sure that the entire descriptor set is addressable with a signed
1372 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1373 * be at most 2 GiB. the combined image & samples object count as one of
1374 * both. This limit is for the pipeline layout, not for the set layout, but
1375 * there is no set limit, so we just set a pipeline limit. I don't think
1376 * any app is going to hit this soon. */
1377 return ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
1378 - MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_INLINE_UNIFORM_BLOCK_COUNT
) /
1379 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1380 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1381 32 /* sampler, largest when combined with image */ +
1382 64 /* sampled image */ +
1383 64 /* storage image */);
1386 void radv_GetPhysicalDeviceProperties(
1387 VkPhysicalDevice physicalDevice
,
1388 VkPhysicalDeviceProperties
* pProperties
)
1390 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1391 VkSampleCountFlags sample_counts
= 0xf;
1393 size_t max_descriptor_set_size
= radv_max_descriptor_set_size();
1395 VkPhysicalDeviceLimits limits
= {
1396 .maxImageDimension1D
= (1 << 14),
1397 .maxImageDimension2D
= (1 << 14),
1398 .maxImageDimension3D
= (1 << 11),
1399 .maxImageDimensionCube
= (1 << 14),
1400 .maxImageArrayLayers
= (1 << 11),
1401 .maxTexelBufferElements
= UINT32_MAX
,
1402 .maxUniformBufferRange
= UINT32_MAX
,
1403 .maxStorageBufferRange
= UINT32_MAX
,
1404 .maxPushConstantsSize
= MAX_PUSH_CONSTANTS_SIZE
,
1405 .maxMemoryAllocationCount
= UINT32_MAX
,
1406 .maxSamplerAllocationCount
= 64 * 1024,
1407 .bufferImageGranularity
= 64, /* A cache line */
1408 .sparseAddressSpaceSize
= RADV_MAX_MEMORY_ALLOCATION_SIZE
, /* buffer max size */
1409 .maxBoundDescriptorSets
= MAX_SETS
,
1410 .maxPerStageDescriptorSamplers
= max_descriptor_set_size
,
1411 .maxPerStageDescriptorUniformBuffers
= max_descriptor_set_size
,
1412 .maxPerStageDescriptorStorageBuffers
= max_descriptor_set_size
,
1413 .maxPerStageDescriptorSampledImages
= max_descriptor_set_size
,
1414 .maxPerStageDescriptorStorageImages
= max_descriptor_set_size
,
1415 .maxPerStageDescriptorInputAttachments
= max_descriptor_set_size
,
1416 .maxPerStageResources
= max_descriptor_set_size
,
1417 .maxDescriptorSetSamplers
= max_descriptor_set_size
,
1418 .maxDescriptorSetUniformBuffers
= max_descriptor_set_size
,
1419 .maxDescriptorSetUniformBuffersDynamic
= MAX_DYNAMIC_UNIFORM_BUFFERS
,
1420 .maxDescriptorSetStorageBuffers
= max_descriptor_set_size
,
1421 .maxDescriptorSetStorageBuffersDynamic
= MAX_DYNAMIC_STORAGE_BUFFERS
,
1422 .maxDescriptorSetSampledImages
= max_descriptor_set_size
,
1423 .maxDescriptorSetStorageImages
= max_descriptor_set_size
,
1424 .maxDescriptorSetInputAttachments
= max_descriptor_set_size
,
1425 .maxVertexInputAttributes
= MAX_VERTEX_ATTRIBS
,
1426 .maxVertexInputBindings
= MAX_VBS
,
1427 .maxVertexInputAttributeOffset
= 2047,
1428 .maxVertexInputBindingStride
= 2048,
1429 .maxVertexOutputComponents
= 128,
1430 .maxTessellationGenerationLevel
= 64,
1431 .maxTessellationPatchSize
= 32,
1432 .maxTessellationControlPerVertexInputComponents
= 128,
1433 .maxTessellationControlPerVertexOutputComponents
= 128,
1434 .maxTessellationControlPerPatchOutputComponents
= 120,
1435 .maxTessellationControlTotalOutputComponents
= 4096,
1436 .maxTessellationEvaluationInputComponents
= 128,
1437 .maxTessellationEvaluationOutputComponents
= 128,
1438 .maxGeometryShaderInvocations
= 127,
1439 .maxGeometryInputComponents
= 64,
1440 .maxGeometryOutputComponents
= 128,
1441 .maxGeometryOutputVertices
= 256,
1442 .maxGeometryTotalOutputComponents
= 1024,
1443 .maxFragmentInputComponents
= 128,
1444 .maxFragmentOutputAttachments
= 8,
1445 .maxFragmentDualSrcAttachments
= 1,
1446 .maxFragmentCombinedOutputResources
= 8,
1447 .maxComputeSharedMemorySize
= 32768,
1448 .maxComputeWorkGroupCount
= { 65535, 65535, 65535 },
1449 .maxComputeWorkGroupInvocations
= 1024,
1450 .maxComputeWorkGroupSize
= {
1455 .subPixelPrecisionBits
= 8,
1456 .subTexelPrecisionBits
= 8,
1457 .mipmapPrecisionBits
= 8,
1458 .maxDrawIndexedIndexValue
= UINT32_MAX
,
1459 .maxDrawIndirectCount
= UINT32_MAX
,
1460 .maxSamplerLodBias
= 16,
1461 .maxSamplerAnisotropy
= 16,
1462 .maxViewports
= MAX_VIEWPORTS
,
1463 .maxViewportDimensions
= { (1 << 14), (1 << 14) },
1464 .viewportBoundsRange
= { INT16_MIN
, INT16_MAX
},
1465 .viewportSubPixelBits
= 8,
1466 .minMemoryMapAlignment
= 4096, /* A page */
1467 .minTexelBufferOffsetAlignment
= 4,
1468 .minUniformBufferOffsetAlignment
= 4,
1469 .minStorageBufferOffsetAlignment
= 4,
1470 .minTexelOffset
= -32,
1471 .maxTexelOffset
= 31,
1472 .minTexelGatherOffset
= -32,
1473 .maxTexelGatherOffset
= 31,
1474 .minInterpolationOffset
= -2,
1475 .maxInterpolationOffset
= 2,
1476 .subPixelInterpolationOffsetBits
= 8,
1477 .maxFramebufferWidth
= (1 << 14),
1478 .maxFramebufferHeight
= (1 << 14),
1479 .maxFramebufferLayers
= (1 << 10),
1480 .framebufferColorSampleCounts
= sample_counts
,
1481 .framebufferDepthSampleCounts
= sample_counts
,
1482 .framebufferStencilSampleCounts
= sample_counts
,
1483 .framebufferNoAttachmentsSampleCounts
= sample_counts
,
1484 .maxColorAttachments
= MAX_RTS
,
1485 .sampledImageColorSampleCounts
= sample_counts
,
1486 .sampledImageIntegerSampleCounts
= sample_counts
,
1487 .sampledImageDepthSampleCounts
= sample_counts
,
1488 .sampledImageStencilSampleCounts
= sample_counts
,
1489 .storageImageSampleCounts
= sample_counts
,
1490 .maxSampleMaskWords
= 1,
1491 .timestampComputeAndGraphics
= true,
1492 .timestampPeriod
= 1000000.0 / pdevice
->rad_info
.clock_crystal_freq
,
1493 .maxClipDistances
= 8,
1494 .maxCullDistances
= 8,
1495 .maxCombinedClipAndCullDistances
= 8,
1496 .discreteQueuePriorities
= 2,
1497 .pointSizeRange
= { 0.0, 8191.875 },
1498 .lineWidthRange
= { 0.0, 8191.875 },
1499 .pointSizeGranularity
= (1.0 / 8.0),
1500 .lineWidthGranularity
= (1.0 / 8.0),
1501 .strictLines
= false, /* FINISHME */
1502 .standardSampleLocations
= true,
1503 .optimalBufferCopyOffsetAlignment
= 128,
1504 .optimalBufferCopyRowPitchAlignment
= 128,
1505 .nonCoherentAtomSize
= 64,
1508 *pProperties
= (VkPhysicalDeviceProperties
) {
1509 .apiVersion
= radv_physical_device_api_version(pdevice
),
1510 .driverVersion
= vk_get_driver_version(),
1511 .vendorID
= ATI_VENDOR_ID
,
1512 .deviceID
= pdevice
->rad_info
.pci_id
,
1513 .deviceType
= pdevice
->rad_info
.has_dedicated_vram
? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU
: VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU
,
1515 .sparseProperties
= {0},
1518 strcpy(pProperties
->deviceName
, pdevice
->name
);
1519 memcpy(pProperties
->pipelineCacheUUID
, pdevice
->cache_uuid
, VK_UUID_SIZE
);
1523 radv_get_physical_device_properties_1_1(struct radv_physical_device
*pdevice
,
1524 VkPhysicalDeviceVulkan11Properties
*p
)
1526 assert(p
->sType
== VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES
);
1528 memcpy(p
->deviceUUID
, pdevice
->device_uuid
, VK_UUID_SIZE
);
1529 memcpy(p
->driverUUID
, pdevice
->driver_uuid
, VK_UUID_SIZE
);
1530 memset(p
->deviceLUID
, 0, VK_LUID_SIZE
);
1531 /* The LUID is for Windows. */
1532 p
->deviceLUIDValid
= false;
1533 p
->deviceNodeMask
= 0;
1535 p
->subgroupSize
= RADV_SUBGROUP_SIZE
;
1536 p
->subgroupSupportedStages
= VK_SHADER_STAGE_ALL_GRAPHICS
|
1537 VK_SHADER_STAGE_COMPUTE_BIT
;
1538 p
->subgroupSupportedOperations
= VK_SUBGROUP_FEATURE_BASIC_BIT
|
1539 VK_SUBGROUP_FEATURE_VOTE_BIT
|
1540 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT
|
1541 VK_SUBGROUP_FEATURE_BALLOT_BIT
|
1542 VK_SUBGROUP_FEATURE_CLUSTERED_BIT
|
1543 VK_SUBGROUP_FEATURE_QUAD_BIT
|
1544 VK_SUBGROUP_FEATURE_SHUFFLE_BIT
|
1545 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT
;
1546 p
->subgroupQuadOperationsInAllStages
= true;
1548 p
->pointClippingBehavior
= VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES
;
1549 p
->maxMultiviewViewCount
= MAX_VIEWS
;
1550 p
->maxMultiviewInstanceIndex
= INT_MAX
;
1551 p
->protectedNoFault
= false;
1552 p
->maxPerSetDescriptors
= RADV_MAX_PER_SET_DESCRIPTORS
;
1553 p
->maxMemoryAllocationSize
= RADV_MAX_MEMORY_ALLOCATION_SIZE
;
1557 radv_get_physical_device_properties_1_2(struct radv_physical_device
*pdevice
,
1558 VkPhysicalDeviceVulkan12Properties
*p
)
1560 assert(p
->sType
== VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES
);
1562 p
->driverID
= VK_DRIVER_ID_MESA_RADV
;
1563 snprintf(p
->driverName
, VK_MAX_DRIVER_NAME_SIZE
, "radv");
1564 snprintf(p
->driverInfo
, VK_MAX_DRIVER_INFO_SIZE
,
1565 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
" (%s)",
1566 radv_get_compiler_string(pdevice
));
1567 p
->conformanceVersion
= (VkConformanceVersion
) {
1574 /* On AMD hardware, denormals and rounding modes for fp16/fp64 are
1575 * controlled by the same config register.
1577 if (pdevice
->rad_info
.has_packed_math_16bit
) {
1578 p
->denormBehaviorIndependence
= VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR
;
1579 p
->roundingModeIndependence
= VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR
;
1581 p
->denormBehaviorIndependence
= VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL_KHR
;
1582 p
->roundingModeIndependence
= VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL_KHR
;
1585 /* With LLVM, do not allow both preserving and flushing denorms because
1586 * different shaders in the same pipeline can have different settings and
1587 * this won't work for merged shaders. To make it work, this requires LLVM
1588 * support for changing the register. The same logic applies for the
1589 * rounding modes because they are configured with the same config
1592 p
->shaderDenormFlushToZeroFloat32
= true;
1593 p
->shaderDenormPreserveFloat32
= !pdevice
->use_llvm
;
1594 p
->shaderRoundingModeRTEFloat32
= true;
1595 p
->shaderRoundingModeRTZFloat32
= !pdevice
->use_llvm
;
1596 p
->shaderSignedZeroInfNanPreserveFloat32
= true;
1598 p
->shaderDenormFlushToZeroFloat16
= pdevice
->rad_info
.has_packed_math_16bit
&& !pdevice
->use_llvm
;
1599 p
->shaderDenormPreserveFloat16
= pdevice
->rad_info
.has_packed_math_16bit
;
1600 p
->shaderRoundingModeRTEFloat16
= pdevice
->rad_info
.has_packed_math_16bit
;
1601 p
->shaderRoundingModeRTZFloat16
= pdevice
->rad_info
.has_packed_math_16bit
&& !pdevice
->use_llvm
;
1602 p
->shaderSignedZeroInfNanPreserveFloat16
= pdevice
->rad_info
.has_packed_math_16bit
;
1604 p
->shaderDenormFlushToZeroFloat64
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_llvm
;
1605 p
->shaderDenormPreserveFloat64
= pdevice
->rad_info
.chip_class
>= GFX8
;
1606 p
->shaderRoundingModeRTEFloat64
= pdevice
->rad_info
.chip_class
>= GFX8
;
1607 p
->shaderRoundingModeRTZFloat64
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_llvm
;
1608 p
->shaderSignedZeroInfNanPreserveFloat64
= pdevice
->rad_info
.chip_class
>= GFX8
;
1610 p
->maxUpdateAfterBindDescriptorsInAllPools
= UINT32_MAX
/ 64;
1611 p
->shaderUniformBufferArrayNonUniformIndexingNative
= false;
1612 p
->shaderSampledImageArrayNonUniformIndexingNative
= false;
1613 p
->shaderStorageBufferArrayNonUniformIndexingNative
= false;
1614 p
->shaderStorageImageArrayNonUniformIndexingNative
= false;
1615 p
->shaderInputAttachmentArrayNonUniformIndexingNative
= false;
1616 p
->robustBufferAccessUpdateAfterBind
= false;
1617 p
->quadDivergentImplicitLod
= false;
1619 size_t max_descriptor_set_size
= ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
-
1620 MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_INLINE_UNIFORM_BLOCK_COUNT
) /
1621 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1622 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1623 32 /* sampler, largest when combined with image */ +
1624 64 /* sampled image */ +
1625 64 /* storage image */);
1626 p
->maxPerStageDescriptorUpdateAfterBindSamplers
= max_descriptor_set_size
;
1627 p
->maxPerStageDescriptorUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1628 p
->maxPerStageDescriptorUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1629 p
->maxPerStageDescriptorUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1630 p
->maxPerStageDescriptorUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1631 p
->maxPerStageDescriptorUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1632 p
->maxPerStageUpdateAfterBindResources
= max_descriptor_set_size
;
1633 p
->maxDescriptorSetUpdateAfterBindSamplers
= max_descriptor_set_size
;
1634 p
->maxDescriptorSetUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1635 p
->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic
= MAX_DYNAMIC_UNIFORM_BUFFERS
;
1636 p
->maxDescriptorSetUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1637 p
->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic
= MAX_DYNAMIC_STORAGE_BUFFERS
;
1638 p
->maxDescriptorSetUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1639 p
->maxDescriptorSetUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1640 p
->maxDescriptorSetUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1642 /* We support all of the depth resolve modes */
1643 p
->supportedDepthResolveModes
= VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
|
1644 VK_RESOLVE_MODE_AVERAGE_BIT_KHR
|
1645 VK_RESOLVE_MODE_MIN_BIT_KHR
|
1646 VK_RESOLVE_MODE_MAX_BIT_KHR
;
1648 /* Average doesn't make sense for stencil so we don't support that */
1649 p
->supportedStencilResolveModes
= VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
|
1650 VK_RESOLVE_MODE_MIN_BIT_KHR
|
1651 VK_RESOLVE_MODE_MAX_BIT_KHR
;
1653 p
->independentResolveNone
= true;
1654 p
->independentResolve
= true;
1656 /* GFX6-8 only support single channel min/max filter. */
1657 p
->filterMinmaxImageComponentMapping
= pdevice
->rad_info
.chip_class
>= GFX9
;
1658 p
->filterMinmaxSingleComponentFormats
= true;
1660 p
->maxTimelineSemaphoreValueDifference
= UINT64_MAX
;
1662 p
->framebufferIntegerColorSampleCounts
= VK_SAMPLE_COUNT_1_BIT
;
1665 void radv_GetPhysicalDeviceProperties2(
1666 VkPhysicalDevice physicalDevice
,
1667 VkPhysicalDeviceProperties2
*pProperties
)
1669 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1670 radv_GetPhysicalDeviceProperties(physicalDevice
, &pProperties
->properties
);
1672 VkPhysicalDeviceVulkan11Properties core_1_1
= {
1673 .sType
= VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES
,
1675 radv_get_physical_device_properties_1_1(pdevice
, &core_1_1
);
1677 VkPhysicalDeviceVulkan12Properties core_1_2
= {
1678 .sType
= VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES
,
1680 radv_get_physical_device_properties_1_2(pdevice
, &core_1_2
);
1682 #define CORE_RENAMED_PROPERTY(major, minor, ext_property, core_property) \
1683 memcpy(&properties->ext_property, &core_##major##_##minor.core_property, \
1684 sizeof(core_##major##_##minor.core_property))
1686 #define CORE_PROPERTY(major, minor, property) \
1687 CORE_RENAMED_PROPERTY(major, minor, property, property)
1689 vk_foreach_struct(ext
, pProperties
->pNext
) {
1690 switch (ext
->sType
) {
1691 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR
: {
1692 VkPhysicalDevicePushDescriptorPropertiesKHR
*properties
=
1693 (VkPhysicalDevicePushDescriptorPropertiesKHR
*) ext
;
1694 properties
->maxPushDescriptors
= MAX_PUSH_DESCRIPTORS
;
1697 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES
: {
1698 VkPhysicalDeviceIDProperties
*properties
= (VkPhysicalDeviceIDProperties
*)ext
;
1699 CORE_PROPERTY(1, 1, deviceUUID
);
1700 CORE_PROPERTY(1, 1, driverUUID
);
1701 CORE_PROPERTY(1, 1, deviceLUID
);
1702 CORE_PROPERTY(1, 1, deviceLUIDValid
);
1705 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES
: {
1706 VkPhysicalDeviceMultiviewProperties
*properties
= (VkPhysicalDeviceMultiviewProperties
*)ext
;
1707 CORE_PROPERTY(1, 1, maxMultiviewViewCount
);
1708 CORE_PROPERTY(1, 1, maxMultiviewInstanceIndex
);
1711 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES
: {
1712 VkPhysicalDevicePointClippingProperties
*properties
=
1713 (VkPhysicalDevicePointClippingProperties
*)ext
;
1714 CORE_PROPERTY(1, 1, pointClippingBehavior
);
1717 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT
: {
1718 VkPhysicalDeviceDiscardRectanglePropertiesEXT
*properties
=
1719 (VkPhysicalDeviceDiscardRectanglePropertiesEXT
*)ext
;
1720 properties
->maxDiscardRectangles
= MAX_DISCARD_RECTANGLES
;
1723 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT
: {
1724 VkPhysicalDeviceExternalMemoryHostPropertiesEXT
*properties
=
1725 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT
*) ext
;
1726 properties
->minImportedHostPointerAlignment
= 4096;
1729 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES
: {
1730 VkPhysicalDeviceSubgroupProperties
*properties
=
1731 (VkPhysicalDeviceSubgroupProperties
*)ext
;
1732 CORE_PROPERTY(1, 1, subgroupSize
);
1733 CORE_RENAMED_PROPERTY(1, 1, supportedStages
,
1734 subgroupSupportedStages
);
1735 CORE_RENAMED_PROPERTY(1, 1, supportedOperations
,
1736 subgroupSupportedOperations
);
1737 CORE_RENAMED_PROPERTY(1, 1, quadOperationsInAllStages
,
1738 subgroupQuadOperationsInAllStages
);
1741 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES
: {
1742 VkPhysicalDeviceMaintenance3Properties
*properties
=
1743 (VkPhysicalDeviceMaintenance3Properties
*)ext
;
1744 CORE_PROPERTY(1, 1, maxPerSetDescriptors
);
1745 CORE_PROPERTY(1, 1, maxMemoryAllocationSize
);
1748 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES
: {
1749 VkPhysicalDeviceSamplerFilterMinmaxProperties
*properties
=
1750 (VkPhysicalDeviceSamplerFilterMinmaxProperties
*)ext
;
1751 CORE_PROPERTY(1, 2, filterMinmaxImageComponentMapping
);
1752 CORE_PROPERTY(1, 2, filterMinmaxSingleComponentFormats
);
1755 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD
: {
1756 VkPhysicalDeviceShaderCorePropertiesAMD
*properties
=
1757 (VkPhysicalDeviceShaderCorePropertiesAMD
*)ext
;
1759 /* Shader engines. */
1760 properties
->shaderEngineCount
=
1761 pdevice
->rad_info
.max_se
;
1762 properties
->shaderArraysPerEngineCount
=
1763 pdevice
->rad_info
.max_sh_per_se
;
1764 properties
->computeUnitsPerShaderArray
=
1765 pdevice
->rad_info
.min_good_cu_per_sa
;
1766 properties
->simdPerComputeUnit
=
1767 pdevice
->rad_info
.num_simd_per_compute_unit
;
1768 properties
->wavefrontsPerSimd
=
1769 pdevice
->rad_info
.max_wave64_per_simd
;
1770 properties
->wavefrontSize
= 64;
1773 properties
->sgprsPerSimd
=
1774 pdevice
->rad_info
.num_physical_sgprs_per_simd
;
1775 properties
->minSgprAllocation
=
1776 pdevice
->rad_info
.min_sgpr_alloc
;
1777 properties
->maxSgprAllocation
=
1778 pdevice
->rad_info
.max_sgpr_alloc
;
1779 properties
->sgprAllocationGranularity
=
1780 pdevice
->rad_info
.sgpr_alloc_granularity
;
1783 properties
->vgprsPerSimd
=
1784 pdevice
->rad_info
.num_physical_wave64_vgprs_per_simd
;
1785 properties
->minVgprAllocation
=
1786 pdevice
->rad_info
.min_wave64_vgpr_alloc
;
1787 properties
->maxVgprAllocation
=
1788 pdevice
->rad_info
.max_vgpr_alloc
;
1789 properties
->vgprAllocationGranularity
=
1790 pdevice
->rad_info
.wave64_vgpr_alloc_granularity
;
1793 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_2_AMD
: {
1794 VkPhysicalDeviceShaderCoreProperties2AMD
*properties
=
1795 (VkPhysicalDeviceShaderCoreProperties2AMD
*)ext
;
1797 properties
->shaderCoreFeatures
= 0;
1798 properties
->activeComputeUnitCount
=
1799 pdevice
->rad_info
.num_good_compute_units
;
1802 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT
: {
1803 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT
*properties
=
1804 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT
*)ext
;
1805 properties
->maxVertexAttribDivisor
= UINT32_MAX
;
1808 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES
: {
1809 VkPhysicalDeviceDescriptorIndexingProperties
*properties
=
1810 (VkPhysicalDeviceDescriptorIndexingProperties
*)ext
;
1811 CORE_PROPERTY(1, 2, maxUpdateAfterBindDescriptorsInAllPools
);
1812 CORE_PROPERTY(1, 2, shaderUniformBufferArrayNonUniformIndexingNative
);
1813 CORE_PROPERTY(1, 2, shaderSampledImageArrayNonUniformIndexingNative
);
1814 CORE_PROPERTY(1, 2, shaderStorageBufferArrayNonUniformIndexingNative
);
1815 CORE_PROPERTY(1, 2, shaderStorageImageArrayNonUniformIndexingNative
);
1816 CORE_PROPERTY(1, 2, shaderInputAttachmentArrayNonUniformIndexingNative
);
1817 CORE_PROPERTY(1, 2, robustBufferAccessUpdateAfterBind
);
1818 CORE_PROPERTY(1, 2, quadDivergentImplicitLod
);
1819 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSamplers
);
1820 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindUniformBuffers
);
1821 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageBuffers
);
1822 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSampledImages
);
1823 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageImages
);
1824 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindInputAttachments
);
1825 CORE_PROPERTY(1, 2, maxPerStageUpdateAfterBindResources
);
1826 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSamplers
);
1827 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffers
);
1828 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffersDynamic
);
1829 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffers
);
1830 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffersDynamic
);
1831 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSampledImages
);
1832 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageImages
);
1833 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindInputAttachments
);
1836 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES
: {
1837 VkPhysicalDeviceProtectedMemoryProperties
*properties
=
1838 (VkPhysicalDeviceProtectedMemoryProperties
*)ext
;
1839 CORE_PROPERTY(1, 1, protectedNoFault
);
1842 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT
: {
1843 VkPhysicalDeviceConservativeRasterizationPropertiesEXT
*properties
=
1844 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT
*)ext
;
1845 properties
->primitiveOverestimationSize
= 0;
1846 properties
->maxExtraPrimitiveOverestimationSize
= 0;
1847 properties
->extraPrimitiveOverestimationSizeGranularity
= 0;
1848 properties
->primitiveUnderestimation
= false;
1849 properties
->conservativePointAndLineRasterization
= false;
1850 properties
->degenerateTrianglesRasterized
= false;
1851 properties
->degenerateLinesRasterized
= false;
1852 properties
->fullyCoveredFragmentShaderInputVariable
= false;
1853 properties
->conservativeRasterizationPostDepthCoverage
= false;
1856 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT
: {
1857 VkPhysicalDevicePCIBusInfoPropertiesEXT
*properties
=
1858 (VkPhysicalDevicePCIBusInfoPropertiesEXT
*)ext
;
1859 properties
->pciDomain
= pdevice
->bus_info
.domain
;
1860 properties
->pciBus
= pdevice
->bus_info
.bus
;
1861 properties
->pciDevice
= pdevice
->bus_info
.dev
;
1862 properties
->pciFunction
= pdevice
->bus_info
.func
;
1865 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES
: {
1866 VkPhysicalDeviceDriverProperties
*properties
=
1867 (VkPhysicalDeviceDriverProperties
*) ext
;
1868 CORE_PROPERTY(1, 2, driverID
);
1869 CORE_PROPERTY(1, 2, driverName
);
1870 CORE_PROPERTY(1, 2, driverInfo
);
1871 CORE_PROPERTY(1, 2, conformanceVersion
);
1874 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT
: {
1875 VkPhysicalDeviceTransformFeedbackPropertiesEXT
*properties
=
1876 (VkPhysicalDeviceTransformFeedbackPropertiesEXT
*)ext
;
1877 properties
->maxTransformFeedbackStreams
= MAX_SO_STREAMS
;
1878 properties
->maxTransformFeedbackBuffers
= MAX_SO_BUFFERS
;
1879 properties
->maxTransformFeedbackBufferSize
= UINT32_MAX
;
1880 properties
->maxTransformFeedbackStreamDataSize
= 512;
1881 properties
->maxTransformFeedbackBufferDataSize
= UINT32_MAX
;
1882 properties
->maxTransformFeedbackBufferDataStride
= 512;
1883 properties
->transformFeedbackQueries
= !pdevice
->use_ngg_streamout
;
1884 properties
->transformFeedbackStreamsLinesTriangles
= !pdevice
->use_ngg_streamout
;
1885 properties
->transformFeedbackRasterizationStreamSelect
= false;
1886 properties
->transformFeedbackDraw
= true;
1889 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT
: {
1890 VkPhysicalDeviceInlineUniformBlockPropertiesEXT
*props
=
1891 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT
*)ext
;
1893 props
->maxInlineUniformBlockSize
= MAX_INLINE_UNIFORM_BLOCK_SIZE
;
1894 props
->maxPerStageDescriptorInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_SETS
;
1895 props
->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_SETS
;
1896 props
->maxDescriptorSetInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_COUNT
;
1897 props
->maxDescriptorSetUpdateAfterBindInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_COUNT
;
1900 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT
: {
1901 VkPhysicalDeviceSampleLocationsPropertiesEXT
*properties
=
1902 (VkPhysicalDeviceSampleLocationsPropertiesEXT
*)ext
;
1903 properties
->sampleLocationSampleCounts
= VK_SAMPLE_COUNT_2_BIT
|
1904 VK_SAMPLE_COUNT_4_BIT
|
1905 VK_SAMPLE_COUNT_8_BIT
;
1906 properties
->maxSampleLocationGridSize
= (VkExtent2D
){ 2 , 2 };
1907 properties
->sampleLocationCoordinateRange
[0] = 0.0f
;
1908 properties
->sampleLocationCoordinateRange
[1] = 0.9375f
;
1909 properties
->sampleLocationSubPixelBits
= 4;
1910 properties
->variableSampleLocations
= false;
1913 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES
: {
1914 VkPhysicalDeviceDepthStencilResolveProperties
*properties
=
1915 (VkPhysicalDeviceDepthStencilResolveProperties
*)ext
;
1916 CORE_PROPERTY(1, 2, supportedDepthResolveModes
);
1917 CORE_PROPERTY(1, 2, supportedStencilResolveModes
);
1918 CORE_PROPERTY(1, 2, independentResolveNone
);
1919 CORE_PROPERTY(1, 2, independentResolve
);
1922 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_PROPERTIES_EXT
: {
1923 VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT
*properties
=
1924 (VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT
*)ext
;
1925 properties
->storageTexelBufferOffsetAlignmentBytes
= 4;
1926 properties
->storageTexelBufferOffsetSingleTexelAlignment
= true;
1927 properties
->uniformTexelBufferOffsetAlignmentBytes
= 4;
1928 properties
->uniformTexelBufferOffsetSingleTexelAlignment
= true;
1931 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT_CONTROLS_PROPERTIES
: {
1932 VkPhysicalDeviceFloatControlsProperties
*properties
=
1933 (VkPhysicalDeviceFloatControlsProperties
*)ext
;
1934 CORE_PROPERTY(1, 2, denormBehaviorIndependence
);
1935 CORE_PROPERTY(1, 2, roundingModeIndependence
);
1936 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat16
);
1937 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat16
);
1938 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat16
);
1939 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat16
);
1940 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat16
);
1941 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat32
);
1942 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat32
);
1943 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat32
);
1944 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat32
);
1945 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat32
);
1946 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat64
);
1947 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat64
);
1948 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat64
);
1949 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat64
);
1950 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat64
);
1953 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_PROPERTIES
: {
1954 VkPhysicalDeviceTimelineSemaphoreProperties
*properties
=
1955 (VkPhysicalDeviceTimelineSemaphoreProperties
*) ext
;
1956 CORE_PROPERTY(1, 2, maxTimelineSemaphoreValueDifference
);
1959 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_PROPERTIES_EXT
: {
1960 VkPhysicalDeviceSubgroupSizeControlPropertiesEXT
*props
=
1961 (VkPhysicalDeviceSubgroupSizeControlPropertiesEXT
*)ext
;
1962 props
->minSubgroupSize
= 64;
1963 props
->maxSubgroupSize
= 64;
1964 props
->maxComputeWorkgroupSubgroups
= UINT32_MAX
;
1965 props
->requiredSubgroupSizeStages
= 0;
1967 if (pdevice
->rad_info
.chip_class
>= GFX10
) {
1968 /* Only GFX10+ supports wave32. */
1969 props
->minSubgroupSize
= 32;
1970 props
->requiredSubgroupSizeStages
= VK_SHADER_STAGE_COMPUTE_BIT
;
1974 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES
:
1975 radv_get_physical_device_properties_1_1(pdevice
, (void *)ext
);
1977 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES
:
1978 radv_get_physical_device_properties_1_2(pdevice
, (void *)ext
);
1980 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_PROPERTIES_EXT
: {
1981 VkPhysicalDeviceLineRasterizationPropertiesEXT
*props
=
1982 (VkPhysicalDeviceLineRasterizationPropertiesEXT
*)ext
;
1983 props
->lineSubPixelPrecisionBits
= 4;
1986 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ROBUSTNESS_2_PROPERTIES_EXT
: {
1987 VkPhysicalDeviceRobustness2PropertiesEXT
*properties
=
1988 (VkPhysicalDeviceRobustness2PropertiesEXT
*)ext
;
1989 properties
->robustStorageBufferAccessSizeAlignment
= 4;
1990 properties
->robustUniformBufferAccessSizeAlignment
= 4;
1993 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_PROPERTIES_EXT
: {
1994 VkPhysicalDeviceCustomBorderColorPropertiesEXT
*props
=
1995 (VkPhysicalDeviceCustomBorderColorPropertiesEXT
*)ext
;
1996 props
->maxCustomBorderColorSamplers
= RADV_BORDER_COLOR_COUNT
;
2005 static void radv_get_physical_device_queue_family_properties(
2006 struct radv_physical_device
* pdevice
,
2008 VkQueueFamilyProperties
** pQueueFamilyProperties
)
2010 int num_queue_families
= 1;
2012 if (pdevice
->rad_info
.num_rings
[RING_COMPUTE
] > 0 &&
2013 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
))
2014 num_queue_families
++;
2016 if (pQueueFamilyProperties
== NULL
) {
2017 *pCount
= num_queue_families
;
2026 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
2027 .queueFlags
= VK_QUEUE_GRAPHICS_BIT
|
2028 VK_QUEUE_COMPUTE_BIT
|
2029 VK_QUEUE_TRANSFER_BIT
|
2030 VK_QUEUE_SPARSE_BINDING_BIT
,
2032 .timestampValidBits
= 64,
2033 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
2038 if (pdevice
->rad_info
.num_rings
[RING_COMPUTE
] > 0 &&
2039 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
)) {
2040 if (*pCount
> idx
) {
2041 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
2042 .queueFlags
= VK_QUEUE_COMPUTE_BIT
|
2043 VK_QUEUE_TRANSFER_BIT
|
2044 VK_QUEUE_SPARSE_BINDING_BIT
,
2045 .queueCount
= pdevice
->rad_info
.num_rings
[RING_COMPUTE
],
2046 .timestampValidBits
= 64,
2047 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
2055 void radv_GetPhysicalDeviceQueueFamilyProperties(
2056 VkPhysicalDevice physicalDevice
,
2058 VkQueueFamilyProperties
* pQueueFamilyProperties
)
2060 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
2061 if (!pQueueFamilyProperties
) {
2062 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
2065 VkQueueFamilyProperties
*properties
[] = {
2066 pQueueFamilyProperties
+ 0,
2067 pQueueFamilyProperties
+ 1,
2068 pQueueFamilyProperties
+ 2,
2070 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
2071 assert(*pCount
<= 3);
2074 void radv_GetPhysicalDeviceQueueFamilyProperties2(
2075 VkPhysicalDevice physicalDevice
,
2077 VkQueueFamilyProperties2
*pQueueFamilyProperties
)
2079 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
2080 if (!pQueueFamilyProperties
) {
2081 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
2084 VkQueueFamilyProperties
*properties
[] = {
2085 &pQueueFamilyProperties
[0].queueFamilyProperties
,
2086 &pQueueFamilyProperties
[1].queueFamilyProperties
,
2087 &pQueueFamilyProperties
[2].queueFamilyProperties
,
2089 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
2090 assert(*pCount
<= 3);
2093 void radv_GetPhysicalDeviceMemoryProperties(
2094 VkPhysicalDevice physicalDevice
,
2095 VkPhysicalDeviceMemoryProperties
*pMemoryProperties
)
2097 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
2099 *pMemoryProperties
= physical_device
->memory_properties
;
2103 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice
,
2104 VkPhysicalDeviceMemoryBudgetPropertiesEXT
*memoryBudget
)
2106 RADV_FROM_HANDLE(radv_physical_device
, device
, physicalDevice
);
2107 VkPhysicalDeviceMemoryProperties
*memory_properties
= &device
->memory_properties
;
2108 uint64_t visible_vram_size
= radv_get_visible_vram_size(device
);
2109 uint64_t vram_size
= radv_get_vram_size(device
);
2110 uint64_t gtt_size
= device
->rad_info
.gart_size
;
2111 uint64_t heap_budget
, heap_usage
;
2113 /* For all memory heaps, the computation of budget is as follow:
2114 * heap_budget = heap_size - global_heap_usage + app_heap_usage
2116 * The Vulkan spec 1.1.97 says that the budget should include any
2117 * currently allocated device memory.
2119 * Note that the application heap usages are not really accurate (eg.
2120 * in presence of shared buffers).
2122 for (int i
= 0; i
< device
->memory_properties
.memoryTypeCount
; i
++) {
2123 uint32_t heap_index
= device
->memory_properties
.memoryTypes
[i
].heapIndex
;
2125 if ((device
->memory_domains
[i
] & RADEON_DOMAIN_VRAM
) && (device
->memory_flags
[i
] & RADEON_FLAG_NO_CPU_ACCESS
)) {
2126 heap_usage
= device
->ws
->query_value(device
->ws
,
2127 RADEON_ALLOCATED_VRAM
);
2129 heap_budget
= vram_size
-
2130 device
->ws
->query_value(device
->ws
, RADEON_VRAM_USAGE
) +
2133 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
2134 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
2135 } else if (device
->memory_domains
[i
] & RADEON_DOMAIN_VRAM
) {
2136 heap_usage
= device
->ws
->query_value(device
->ws
,
2137 RADEON_ALLOCATED_VRAM_VIS
);
2139 heap_budget
= visible_vram_size
-
2140 device
->ws
->query_value(device
->ws
, RADEON_VRAM_VIS_USAGE
) +
2143 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
2144 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
2146 assert(device
->memory_domains
[i
] & RADEON_DOMAIN_GTT
);
2148 heap_usage
= device
->ws
->query_value(device
->ws
,
2149 RADEON_ALLOCATED_GTT
);
2151 heap_budget
= gtt_size
-
2152 device
->ws
->query_value(device
->ws
, RADEON_GTT_USAGE
) +
2155 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
2156 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
2160 /* The heapBudget and heapUsage values must be zero for array elements
2161 * greater than or equal to
2162 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
2164 for (uint32_t i
= memory_properties
->memoryHeapCount
; i
< VK_MAX_MEMORY_HEAPS
; i
++) {
2165 memoryBudget
->heapBudget
[i
] = 0;
2166 memoryBudget
->heapUsage
[i
] = 0;
2170 void radv_GetPhysicalDeviceMemoryProperties2(
2171 VkPhysicalDevice physicalDevice
,
2172 VkPhysicalDeviceMemoryProperties2
*pMemoryProperties
)
2174 radv_GetPhysicalDeviceMemoryProperties(physicalDevice
,
2175 &pMemoryProperties
->memoryProperties
);
2177 VkPhysicalDeviceMemoryBudgetPropertiesEXT
*memory_budget
=
2178 vk_find_struct(pMemoryProperties
->pNext
,
2179 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT
);
2181 radv_get_memory_budget_properties(physicalDevice
, memory_budget
);
2184 VkResult
radv_GetMemoryHostPointerPropertiesEXT(
2186 VkExternalMemoryHandleTypeFlagBits handleType
,
2187 const void *pHostPointer
,
2188 VkMemoryHostPointerPropertiesEXT
*pMemoryHostPointerProperties
)
2190 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2194 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT
: {
2195 const struct radv_physical_device
*physical_device
= device
->physical_device
;
2196 uint32_t memoryTypeBits
= 0;
2197 for (int i
= 0; i
< physical_device
->memory_properties
.memoryTypeCount
; i
++) {
2198 if (physical_device
->memory_domains
[i
] == RADEON_DOMAIN_GTT
&&
2199 !(physical_device
->memory_flags
[i
] & RADEON_FLAG_GTT_WC
)) {
2200 memoryTypeBits
= (1 << i
);
2204 pMemoryHostPointerProperties
->memoryTypeBits
= memoryTypeBits
;
2208 return VK_ERROR_INVALID_EXTERNAL_HANDLE
;
2212 static enum radeon_ctx_priority
2213 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT
*pObj
)
2215 /* Default to MEDIUM when a specific global priority isn't requested */
2217 return RADEON_CTX_PRIORITY_MEDIUM
;
2219 switch(pObj
->globalPriority
) {
2220 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT
:
2221 return RADEON_CTX_PRIORITY_REALTIME
;
2222 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT
:
2223 return RADEON_CTX_PRIORITY_HIGH
;
2224 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT
:
2225 return RADEON_CTX_PRIORITY_MEDIUM
;
2226 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT
:
2227 return RADEON_CTX_PRIORITY_LOW
;
2229 unreachable("Illegal global priority value");
2230 return RADEON_CTX_PRIORITY_INVALID
;
2235 radv_queue_init(struct radv_device
*device
, struct radv_queue
*queue
,
2236 uint32_t queue_family_index
, int idx
,
2237 VkDeviceQueueCreateFlags flags
,
2238 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
)
2240 queue
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
2241 queue
->device
= device
;
2242 queue
->queue_family_index
= queue_family_index
;
2243 queue
->queue_idx
= idx
;
2244 queue
->priority
= radv_get_queue_global_priority(global_priority
);
2245 queue
->flags
= flags
;
2246 queue
->hw_ctx
= NULL
;
2248 VkResult result
= device
->ws
->ctx_create(device
->ws
, queue
->priority
, &queue
->hw_ctx
);
2249 if (result
!= VK_SUCCESS
)
2250 return vk_error(device
->instance
, result
);
2252 list_inithead(&queue
->pending_submissions
);
2253 pthread_mutex_init(&queue
->pending_mutex
, NULL
);
2259 radv_queue_finish(struct radv_queue
*queue
)
2261 pthread_mutex_destroy(&queue
->pending_mutex
);
2264 queue
->device
->ws
->ctx_destroy(queue
->hw_ctx
);
2266 if (queue
->initial_full_flush_preamble_cs
)
2267 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
2268 if (queue
->initial_preamble_cs
)
2269 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
2270 if (queue
->continue_preamble_cs
)
2271 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
2272 if (queue
->descriptor_bo
)
2273 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
2274 if (queue
->scratch_bo
)
2275 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
2276 if (queue
->esgs_ring_bo
)
2277 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
2278 if (queue
->gsvs_ring_bo
)
2279 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
2280 if (queue
->tess_rings_bo
)
2281 queue
->device
->ws
->buffer_destroy(queue
->tess_rings_bo
);
2283 queue
->device
->ws
->buffer_destroy(queue
->gds_bo
);
2284 if (queue
->gds_oa_bo
)
2285 queue
->device
->ws
->buffer_destroy(queue
->gds_oa_bo
);
2286 if (queue
->compute_scratch_bo
)
2287 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
2291 radv_bo_list_init(struct radv_bo_list
*bo_list
)
2293 pthread_mutex_init(&bo_list
->mutex
, NULL
);
2294 bo_list
->list
.count
= bo_list
->capacity
= 0;
2295 bo_list
->list
.bos
= NULL
;
2299 radv_bo_list_finish(struct radv_bo_list
*bo_list
)
2301 free(bo_list
->list
.bos
);
2302 pthread_mutex_destroy(&bo_list
->mutex
);
2305 VkResult
radv_bo_list_add(struct radv_device
*device
,
2306 struct radeon_winsys_bo
*bo
)
2308 struct radv_bo_list
*bo_list
= &device
->bo_list
;
2313 if (unlikely(!device
->use_global_bo_list
))
2316 pthread_mutex_lock(&bo_list
->mutex
);
2317 if (bo_list
->list
.count
== bo_list
->capacity
) {
2318 unsigned capacity
= MAX2(4, bo_list
->capacity
* 2);
2319 void *data
= realloc(bo_list
->list
.bos
, capacity
* sizeof(struct radeon_winsys_bo
*));
2322 pthread_mutex_unlock(&bo_list
->mutex
);
2323 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2326 bo_list
->list
.bos
= (struct radeon_winsys_bo
**)data
;
2327 bo_list
->capacity
= capacity
;
2330 bo_list
->list
.bos
[bo_list
->list
.count
++] = bo
;
2331 pthread_mutex_unlock(&bo_list
->mutex
);
2335 void radv_bo_list_remove(struct radv_device
*device
,
2336 struct radeon_winsys_bo
*bo
)
2338 struct radv_bo_list
*bo_list
= &device
->bo_list
;
2343 if (unlikely(!device
->use_global_bo_list
))
2346 pthread_mutex_lock(&bo_list
->mutex
);
2347 /* Loop the list backwards so we find the most recently added
2349 for(unsigned i
= bo_list
->list
.count
; i
-- > 0;) {
2350 if (bo_list
->list
.bos
[i
] == bo
) {
2351 bo_list
->list
.bos
[i
] = bo_list
->list
.bos
[bo_list
->list
.count
- 1];
2352 --bo_list
->list
.count
;
2356 pthread_mutex_unlock(&bo_list
->mutex
);
2360 radv_device_init_gs_info(struct radv_device
*device
)
2362 device
->gs_table_depth
= ac_get_gs_table_depth(device
->physical_device
->rad_info
.chip_class
,
2363 device
->physical_device
->rad_info
.family
);
2366 static int radv_get_device_extension_index(const char *name
)
2368 for (unsigned i
= 0; i
< RADV_DEVICE_EXTENSION_COUNT
; ++i
) {
2369 if (strcmp(name
, radv_device_extensions
[i
].extensionName
) == 0)
2376 radv_get_int_debug_option(const char *name
, int default_value
)
2383 result
= default_value
;
2387 result
= strtol(str
, &endptr
, 0);
2388 if (str
== endptr
) {
2389 /* No digits founs. */
2390 result
= default_value
;
2398 radv_device_init_dispatch(struct radv_device
*device
)
2400 const struct radv_instance
*instance
= device
->physical_device
->instance
;
2401 const struct radv_device_dispatch_table
*dispatch_table_layer
= NULL
;
2402 bool unchecked
= instance
->debug_flags
& RADV_DEBUG_ALL_ENTRYPOINTS
;
2403 int radv_thread_trace
= radv_get_int_debug_option("RADV_THREAD_TRACE", -1);
2405 if (radv_thread_trace
>= 0) {
2406 /* Use device entrypoints from the SQTT layer if enabled. */
2407 dispatch_table_layer
= &sqtt_device_dispatch_table
;
2410 for (unsigned i
= 0; i
< ARRAY_SIZE(device
->dispatch
.entrypoints
); i
++) {
2411 /* Vulkan requires that entrypoints for extensions which have not been
2412 * enabled must not be advertised.
2415 !radv_device_entrypoint_is_enabled(i
, instance
->apiVersion
,
2416 &instance
->enabled_extensions
,
2417 &device
->enabled_extensions
)) {
2418 device
->dispatch
.entrypoints
[i
] = NULL
;
2419 } else if (dispatch_table_layer
&&
2420 dispatch_table_layer
->entrypoints
[i
]) {
2421 device
->dispatch
.entrypoints
[i
] =
2422 dispatch_table_layer
->entrypoints
[i
];
2424 device
->dispatch
.entrypoints
[i
] =
2425 radv_device_dispatch_table
.entrypoints
[i
];
2431 radv_create_pthread_cond(pthread_cond_t
*cond
)
2433 pthread_condattr_t condattr
;
2434 if (pthread_condattr_init(&condattr
)) {
2435 return VK_ERROR_INITIALIZATION_FAILED
;
2438 if (pthread_condattr_setclock(&condattr
, CLOCK_MONOTONIC
)) {
2439 pthread_condattr_destroy(&condattr
);
2440 return VK_ERROR_INITIALIZATION_FAILED
;
2442 if (pthread_cond_init(cond
, &condattr
)) {
2443 pthread_condattr_destroy(&condattr
);
2444 return VK_ERROR_INITIALIZATION_FAILED
;
2446 pthread_condattr_destroy(&condattr
);
2451 check_physical_device_features(VkPhysicalDevice physicalDevice
,
2452 const VkPhysicalDeviceFeatures
*features
)
2454 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
2455 VkPhysicalDeviceFeatures supported_features
;
2456 radv_GetPhysicalDeviceFeatures(physicalDevice
, &supported_features
);
2457 VkBool32
*supported_feature
= (VkBool32
*)&supported_features
;
2458 VkBool32
*enabled_feature
= (VkBool32
*)features
;
2459 unsigned num_features
= sizeof(VkPhysicalDeviceFeatures
) / sizeof(VkBool32
);
2460 for (uint32_t i
= 0; i
< num_features
; i
++) {
2461 if (enabled_feature
[i
] && !supported_feature
[i
])
2462 return vk_error(physical_device
->instance
, VK_ERROR_FEATURE_NOT_PRESENT
);
2468 static VkResult
radv_device_init_border_color(struct radv_device
*device
)
2470 device
->border_color_data
.bo
=
2471 device
->ws
->buffer_create(device
->ws
,
2472 RADV_BORDER_COLOR_BUFFER_SIZE
,
2475 RADEON_FLAG_CPU_ACCESS
|
2476 RADEON_FLAG_READ_ONLY
|
2477 RADEON_FLAG_NO_INTERPROCESS_SHARING
,
2478 RADV_BO_PRIORITY_SHADER
);
2480 if (device
->border_color_data
.bo
== NULL
)
2481 return vk_error(device
->physical_device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2483 device
->border_color_data
.colors_gpu_ptr
=
2484 device
->ws
->buffer_map(device
->border_color_data
.bo
);
2485 if (!device
->border_color_data
.colors_gpu_ptr
)
2486 return vk_error(device
->physical_device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2487 pthread_mutex_init(&device
->border_color_data
.mutex
, NULL
);
2492 static void radv_device_finish_border_color(struct radv_device
*device
)
2494 if (device
->border_color_data
.bo
) {
2495 device
->ws
->buffer_destroy(device
->border_color_data
.bo
);
2497 pthread_mutex_destroy(&device
->border_color_data
.mutex
);
2501 VkResult
radv_CreateDevice(
2502 VkPhysicalDevice physicalDevice
,
2503 const VkDeviceCreateInfo
* pCreateInfo
,
2504 const VkAllocationCallbacks
* pAllocator
,
2507 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
2509 struct radv_device
*device
;
2511 bool keep_shader_info
= false;
2512 bool robust_buffer_access
= false;
2513 bool overallocation_disallowed
= false;
2514 bool custom_border_colors
= false;
2516 /* Check enabled features */
2517 if (pCreateInfo
->pEnabledFeatures
) {
2518 result
= check_physical_device_features(physicalDevice
,
2519 pCreateInfo
->pEnabledFeatures
);
2520 if (result
!= VK_SUCCESS
)
2523 if (pCreateInfo
->pEnabledFeatures
->robustBufferAccess
)
2524 robust_buffer_access
= true;
2527 vk_foreach_struct_const(ext
, pCreateInfo
->pNext
) {
2528 switch (ext
->sType
) {
2529 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FEATURES_2
: {
2530 const VkPhysicalDeviceFeatures2
*features
= (const void *)ext
;
2531 result
= check_physical_device_features(physicalDevice
,
2532 &features
->features
);
2533 if (result
!= VK_SUCCESS
)
2536 if (features
->features
.robustBufferAccess
)
2537 robust_buffer_access
= true;
2540 case VK_STRUCTURE_TYPE_DEVICE_MEMORY_OVERALLOCATION_CREATE_INFO_AMD
: {
2541 const VkDeviceMemoryOverallocationCreateInfoAMD
*overallocation
= (const void *)ext
;
2542 if (overallocation
->overallocationBehavior
== VK_MEMORY_OVERALLOCATION_BEHAVIOR_DISALLOWED_AMD
)
2543 overallocation_disallowed
= true;
2546 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_FEATURES_EXT
: {
2547 const VkPhysicalDeviceCustomBorderColorFeaturesEXT
*border_color_features
= (const void *)ext
;
2548 custom_border_colors
= border_color_features
->customBorderColors
;
2556 device
= vk_zalloc2(&physical_device
->instance
->alloc
, pAllocator
,
2558 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
2560 return vk_error(physical_device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2562 vk_device_init(&device
->vk
, pCreateInfo
,
2563 &physical_device
->instance
->alloc
, pAllocator
);
2565 device
->instance
= physical_device
->instance
;
2566 device
->physical_device
= physical_device
;
2568 device
->ws
= physical_device
->ws
;
2570 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
2571 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
2572 int index
= radv_get_device_extension_index(ext_name
);
2573 if (index
< 0 || !physical_device
->supported_extensions
.extensions
[index
]) {
2574 vk_free(&device
->vk
.alloc
, device
);
2575 return vk_error(physical_device
->instance
, VK_ERROR_EXTENSION_NOT_PRESENT
);
2578 device
->enabled_extensions
.extensions
[index
] = true;
2581 radv_device_init_dispatch(device
);
2583 keep_shader_info
= device
->enabled_extensions
.AMD_shader_info
;
2585 /* With update after bind we can't attach bo's to the command buffer
2586 * from the descriptor set anymore, so we have to use a global BO list.
2588 device
->use_global_bo_list
=
2589 (device
->instance
->perftest_flags
& RADV_PERFTEST_BO_LIST
) ||
2590 device
->enabled_extensions
.EXT_descriptor_indexing
||
2591 device
->enabled_extensions
.EXT_buffer_device_address
||
2592 device
->enabled_extensions
.KHR_buffer_device_address
;
2594 device
->robust_buffer_access
= robust_buffer_access
;
2596 mtx_init(&device
->shader_slab_mutex
, mtx_plain
);
2597 list_inithead(&device
->shader_slabs
);
2599 device
->overallocation_disallowed
= overallocation_disallowed
;
2600 mtx_init(&device
->overallocation_mutex
, mtx_plain
);
2602 radv_bo_list_init(&device
->bo_list
);
2604 for (unsigned i
= 0; i
< pCreateInfo
->queueCreateInfoCount
; i
++) {
2605 const VkDeviceQueueCreateInfo
*queue_create
= &pCreateInfo
->pQueueCreateInfos
[i
];
2606 uint32_t qfi
= queue_create
->queueFamilyIndex
;
2607 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
=
2608 vk_find_struct_const(queue_create
->pNext
, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT
);
2610 assert(!global_priority
|| device
->physical_device
->rad_info
.has_ctx_priority
);
2612 device
->queues
[qfi
] = vk_alloc(&device
->vk
.alloc
,
2613 queue_create
->queueCount
* sizeof(struct radv_queue
), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
2614 if (!device
->queues
[qfi
]) {
2615 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2619 memset(device
->queues
[qfi
], 0, queue_create
->queueCount
* sizeof(struct radv_queue
));
2621 device
->queue_count
[qfi
] = queue_create
->queueCount
;
2623 for (unsigned q
= 0; q
< queue_create
->queueCount
; q
++) {
2624 result
= radv_queue_init(device
, &device
->queues
[qfi
][q
],
2625 qfi
, q
, queue_create
->flags
,
2627 if (result
!= VK_SUCCESS
)
2632 device
->pbb_allowed
= device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2633 !(device
->instance
->debug_flags
& RADV_DEBUG_NOBINNING
);
2635 /* Disable DFSM by default. As of 2019-09-15 Talos on Low is still 3% slower on Raven. */
2636 device
->dfsm_allowed
= device
->pbb_allowed
&&
2637 (device
->instance
->perftest_flags
& RADV_PERFTEST_DFSM
);
2639 device
->always_use_syncobj
= device
->physical_device
->rad_info
.has_syncobj_wait_for_submit
;
2641 /* The maximum number of scratch waves. Scratch space isn't divided
2642 * evenly between CUs. The number is only a function of the number of CUs.
2643 * We can decrease the constant to decrease the scratch buffer size.
2645 * sctx->scratch_waves must be >= the maximum possible size of
2646 * 1 threadgroup, so that the hw doesn't hang from being unable
2649 * The recommended value is 4 per CU at most. Higher numbers don't
2650 * bring much benefit, but they still occupy chip resources (think
2651 * async compute). I've seen ~2% performance difference between 4 and 32.
2653 uint32_t max_threads_per_block
= 2048;
2654 device
->scratch_waves
= MAX2(32 * physical_device
->rad_info
.num_good_compute_units
,
2655 max_threads_per_block
/ 64);
2657 device
->dispatch_initiator
= S_00B800_COMPUTE_SHADER_EN(1);
2659 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2660 /* If the KMD allows it (there is a KMD hw register for it),
2661 * allow launching waves out-of-order.
2663 device
->dispatch_initiator
|= S_00B800_ORDER_MODE(1);
2666 radv_device_init_gs_info(device
);
2668 device
->tess_offchip_block_dw_size
=
2669 device
->physical_device
->rad_info
.family
== CHIP_HAWAII
? 4096 : 8192;
2671 if (getenv("RADV_TRACE_FILE")) {
2672 const char *filename
= getenv("RADV_TRACE_FILE");
2674 keep_shader_info
= true;
2676 if (!radv_init_trace(device
))
2679 fprintf(stderr
, "*****************************************************************************\n");
2680 fprintf(stderr
, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
2681 fprintf(stderr
, "*****************************************************************************\n");
2683 fprintf(stderr
, "Trace file will be dumped to %s\n", filename
);
2684 radv_dump_enabled_options(device
, stderr
);
2687 int radv_thread_trace
= radv_get_int_debug_option("RADV_THREAD_TRACE", -1);
2688 if (radv_thread_trace
>= 0) {
2689 fprintf(stderr
, "*************************************************\n");
2690 fprintf(stderr
, "* WARNING: Thread trace support is experimental *\n");
2691 fprintf(stderr
, "*************************************************\n");
2693 if (device
->physical_device
->rad_info
.chip_class
< GFX8
) {
2694 fprintf(stderr
, "GPU hardware not supported: refer to "
2695 "the RGP documentation for the list of "
2696 "supported GPUs!\n");
2700 /* Default buffer size set to 1MB per SE. */
2701 device
->thread_trace_buffer_size
=
2702 radv_get_int_debug_option("RADV_THREAD_TRACE_BUFFER_SIZE", 1024 * 1024);
2703 device
->thread_trace_start_frame
= radv_thread_trace
;
2705 if (!radv_thread_trace_init(device
))
2709 device
->keep_shader_info
= keep_shader_info
;
2710 result
= radv_device_init_meta(device
);
2711 if (result
!= VK_SUCCESS
)
2714 radv_device_init_msaa(device
);
2716 /* If the border color extension is enabled, let's create the buffer we need. */
2717 if (custom_border_colors
) {
2718 result
= radv_device_init_border_color(device
);
2719 if (result
!= VK_SUCCESS
)
2723 for (int family
= 0; family
< RADV_MAX_QUEUE_FAMILIES
; ++family
) {
2724 device
->empty_cs
[family
] = device
->ws
->cs_create(device
->ws
, family
);
2725 if (!device
->empty_cs
[family
])
2729 case RADV_QUEUE_GENERAL
:
2730 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
2731 radeon_emit(device
->empty_cs
[family
], CC0_UPDATE_LOAD_ENABLES(1));
2732 radeon_emit(device
->empty_cs
[family
], CC1_UPDATE_SHADOW_ENABLES(1));
2734 case RADV_QUEUE_COMPUTE
:
2735 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_NOP
, 0, 0));
2736 radeon_emit(device
->empty_cs
[family
], 0);
2740 result
= device
->ws
->cs_finalize(device
->empty_cs
[family
]);
2741 if (result
!= VK_SUCCESS
)
2745 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
2746 cik_create_gfx_config(device
);
2748 VkPipelineCacheCreateInfo ci
;
2749 ci
.sType
= VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO
;
2752 ci
.pInitialData
= NULL
;
2753 ci
.initialDataSize
= 0;
2755 result
= radv_CreatePipelineCache(radv_device_to_handle(device
),
2757 if (result
!= VK_SUCCESS
)
2760 device
->mem_cache
= radv_pipeline_cache_from_handle(pc
);
2762 result
= radv_create_pthread_cond(&device
->timeline_cond
);
2763 if (result
!= VK_SUCCESS
)
2764 goto fail_mem_cache
;
2766 device
->force_aniso
=
2767 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
2768 if (device
->force_aniso
>= 0) {
2769 fprintf(stderr
, "radv: Forcing anisotropy filter to %ix\n",
2770 1 << util_logbase2(device
->force_aniso
));
2773 *pDevice
= radv_device_to_handle(device
);
2777 radv_DestroyPipelineCache(radv_device_to_handle(device
), pc
, NULL
);
2779 radv_device_finish_meta(device
);
2781 radv_bo_list_finish(&device
->bo_list
);
2783 radv_thread_trace_finish(device
);
2785 if (device
->trace_bo
)
2786 device
->ws
->buffer_destroy(device
->trace_bo
);
2788 if (device
->gfx_init
)
2789 device
->ws
->buffer_destroy(device
->gfx_init
);
2791 radv_device_finish_border_color(device
);
2793 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
2794 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
2795 radv_queue_finish(&device
->queues
[i
][q
]);
2796 if (device
->queue_count
[i
])
2797 vk_free(&device
->vk
.alloc
, device
->queues
[i
]);
2800 vk_free(&device
->vk
.alloc
, device
);
2804 void radv_DestroyDevice(
2806 const VkAllocationCallbacks
* pAllocator
)
2808 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2813 if (device
->trace_bo
)
2814 device
->ws
->buffer_destroy(device
->trace_bo
);
2816 if (device
->gfx_init
)
2817 device
->ws
->buffer_destroy(device
->gfx_init
);
2819 radv_device_finish_border_color(device
);
2821 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
2822 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
2823 radv_queue_finish(&device
->queues
[i
][q
]);
2824 if (device
->queue_count
[i
])
2825 vk_free(&device
->vk
.alloc
, device
->queues
[i
]);
2826 if (device
->empty_cs
[i
])
2827 device
->ws
->cs_destroy(device
->empty_cs
[i
]);
2829 radv_device_finish_meta(device
);
2831 VkPipelineCache pc
= radv_pipeline_cache_to_handle(device
->mem_cache
);
2832 radv_DestroyPipelineCache(radv_device_to_handle(device
), pc
, NULL
);
2834 radv_destroy_shader_slabs(device
);
2836 pthread_cond_destroy(&device
->timeline_cond
);
2837 radv_bo_list_finish(&device
->bo_list
);
2839 radv_thread_trace_finish(device
);
2841 vk_free(&device
->vk
.alloc
, device
);
2844 VkResult
radv_EnumerateInstanceLayerProperties(
2845 uint32_t* pPropertyCount
,
2846 VkLayerProperties
* pProperties
)
2848 if (pProperties
== NULL
) {
2849 *pPropertyCount
= 0;
2853 /* None supported at this time */
2854 return vk_error(NULL
, VK_ERROR_LAYER_NOT_PRESENT
);
2857 VkResult
radv_EnumerateDeviceLayerProperties(
2858 VkPhysicalDevice physicalDevice
,
2859 uint32_t* pPropertyCount
,
2860 VkLayerProperties
* pProperties
)
2862 if (pProperties
== NULL
) {
2863 *pPropertyCount
= 0;
2867 /* None supported at this time */
2868 return vk_error(NULL
, VK_ERROR_LAYER_NOT_PRESENT
);
2871 void radv_GetDeviceQueue2(
2873 const VkDeviceQueueInfo2
* pQueueInfo
,
2876 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2877 struct radv_queue
*queue
;
2879 queue
= &device
->queues
[pQueueInfo
->queueFamilyIndex
][pQueueInfo
->queueIndex
];
2880 if (pQueueInfo
->flags
!= queue
->flags
) {
2881 /* From the Vulkan 1.1.70 spec:
2883 * "The queue returned by vkGetDeviceQueue2 must have the same
2884 * flags value from this structure as that used at device
2885 * creation time in a VkDeviceQueueCreateInfo instance. If no
2886 * matching flags were specified at device creation time then
2887 * pQueue will return VK_NULL_HANDLE."
2889 *pQueue
= VK_NULL_HANDLE
;
2893 *pQueue
= radv_queue_to_handle(queue
);
2896 void radv_GetDeviceQueue(
2898 uint32_t queueFamilyIndex
,
2899 uint32_t queueIndex
,
2902 const VkDeviceQueueInfo2 info
= (VkDeviceQueueInfo2
) {
2903 .sType
= VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2
,
2904 .queueFamilyIndex
= queueFamilyIndex
,
2905 .queueIndex
= queueIndex
2908 radv_GetDeviceQueue2(_device
, &info
, pQueue
);
2912 fill_geom_tess_rings(struct radv_queue
*queue
,
2914 bool add_sample_positions
,
2915 uint32_t esgs_ring_size
,
2916 struct radeon_winsys_bo
*esgs_ring_bo
,
2917 uint32_t gsvs_ring_size
,
2918 struct radeon_winsys_bo
*gsvs_ring_bo
,
2919 uint32_t tess_factor_ring_size
,
2920 uint32_t tess_offchip_ring_offset
,
2921 uint32_t tess_offchip_ring_size
,
2922 struct radeon_winsys_bo
*tess_rings_bo
)
2924 uint32_t *desc
= &map
[4];
2927 uint64_t esgs_va
= radv_buffer_get_va(esgs_ring_bo
);
2929 /* stride 0, num records - size, add tid, swizzle, elsize4,
2932 desc
[1] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32) |
2933 S_008F04_SWIZZLE_ENABLE(true);
2934 desc
[2] = esgs_ring_size
;
2935 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2936 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2937 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2938 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2939 S_008F0C_INDEX_STRIDE(3) |
2940 S_008F0C_ADD_TID_ENABLE(1);
2942 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2943 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2944 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) |
2945 S_008F0C_RESOURCE_LEVEL(1);
2947 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2948 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
2949 S_008F0C_ELEMENT_SIZE(1);
2952 /* GS entry for ES->GS ring */
2953 /* stride 0, num records - size, elsize0,
2956 desc
[5] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32);
2957 desc
[6] = esgs_ring_size
;
2958 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2959 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2960 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2961 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
2963 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2964 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2965 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) |
2966 S_008F0C_RESOURCE_LEVEL(1);
2968 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2969 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2976 uint64_t gsvs_va
= radv_buffer_get_va(gsvs_ring_bo
);
2978 /* VS entry for GS->VS ring */
2979 /* stride 0, num records - size, elsize0,
2982 desc
[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32);
2983 desc
[2] = gsvs_ring_size
;
2984 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2985 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2986 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2987 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
2989 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2990 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2991 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) |
2992 S_008F0C_RESOURCE_LEVEL(1);
2994 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2995 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2998 /* stride gsvs_itemsize, num records 64
2999 elsize 4, index stride 16 */
3000 /* shader will patch stride and desc[2] */
3002 desc
[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32) |
3003 S_008F04_SWIZZLE_ENABLE(1);
3005 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3006 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3007 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3008 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
3009 S_008F0C_INDEX_STRIDE(1) |
3010 S_008F0C_ADD_TID_ENABLE(true);
3012 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3013 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3014 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) |
3015 S_008F0C_RESOURCE_LEVEL(1);
3017 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3018 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
3019 S_008F0C_ELEMENT_SIZE(1);
3026 if (tess_rings_bo
) {
3027 uint64_t tess_va
= radv_buffer_get_va(tess_rings_bo
);
3028 uint64_t tess_offchip_va
= tess_va
+ tess_offchip_ring_offset
;
3031 desc
[1] = S_008F04_BASE_ADDRESS_HI(tess_va
>> 32);
3032 desc
[2] = tess_factor_ring_size
;
3033 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3034 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3035 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3036 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3038 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3039 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3040 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
3041 S_008F0C_RESOURCE_LEVEL(1);
3043 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3044 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3047 desc
[4] = tess_offchip_va
;
3048 desc
[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va
>> 32);
3049 desc
[6] = tess_offchip_ring_size
;
3050 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3051 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3052 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3053 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3055 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3056 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3057 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
3058 S_008F0C_RESOURCE_LEVEL(1);
3060 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3061 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3067 if (add_sample_positions
) {
3068 /* add sample positions after all rings */
3069 memcpy(desc
, queue
->device
->sample_locations_1x
, 8);
3071 memcpy(desc
, queue
->device
->sample_locations_2x
, 16);
3073 memcpy(desc
, queue
->device
->sample_locations_4x
, 32);
3075 memcpy(desc
, queue
->device
->sample_locations_8x
, 64);
3080 radv_get_hs_offchip_param(struct radv_device
*device
, uint32_t *max_offchip_buffers_p
)
3082 bool double_offchip_buffers
= device
->physical_device
->rad_info
.chip_class
>= GFX7
&&
3083 device
->physical_device
->rad_info
.family
!= CHIP_CARRIZO
&&
3084 device
->physical_device
->rad_info
.family
!= CHIP_STONEY
;
3085 unsigned max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
3086 unsigned max_offchip_buffers
;
3087 unsigned offchip_granularity
;
3088 unsigned hs_offchip_param
;
3092 * This must be one less than the maximum number due to a hw limitation.
3093 * Various hardware bugs need thGFX7
3096 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
3097 * Gfx7 should limit max_offchip_buffers to 508
3098 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
3100 * Follow AMDVLK here.
3102 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3103 max_offchip_buffers_per_se
= 256;
3104 } else if (device
->physical_device
->rad_info
.family
== CHIP_VEGA10
||
3105 device
->physical_device
->rad_info
.chip_class
== GFX7
||
3106 device
->physical_device
->rad_info
.chip_class
== GFX6
)
3107 --max_offchip_buffers_per_se
;
3109 max_offchip_buffers
= max_offchip_buffers_per_se
*
3110 device
->physical_device
->rad_info
.max_se
;
3112 /* Hawaii has a bug with offchip buffers > 256 that can be worked
3113 * around by setting 4K granularity.
3115 if (device
->tess_offchip_block_dw_size
== 4096) {
3116 assert(device
->physical_device
->rad_info
.family
== CHIP_HAWAII
);
3117 offchip_granularity
= V_03093C_X_4K_DWORDS
;
3119 assert(device
->tess_offchip_block_dw_size
== 8192);
3120 offchip_granularity
= V_03093C_X_8K_DWORDS
;
3123 switch (device
->physical_device
->rad_info
.chip_class
) {
3125 max_offchip_buffers
= MIN2(max_offchip_buffers
, 126);
3130 max_offchip_buffers
= MIN2(max_offchip_buffers
, 508);
3138 *max_offchip_buffers_p
= max_offchip_buffers
;
3139 if (device
->physical_device
->rad_info
.chip_class
>= GFX10_3
) {
3140 hs_offchip_param
= S_03093C_OFFCHIP_BUFFERING_GFX103(max_offchip_buffers
- 1) |
3141 S_03093C_OFFCHIP_GRANULARITY_GFX103(offchip_granularity
);
3142 } else if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
3143 if (device
->physical_device
->rad_info
.chip_class
>= GFX8
)
3144 --max_offchip_buffers
;
3146 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
3147 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
);
3150 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
);
3152 return hs_offchip_param
;
3156 radv_emit_gs_ring_sizes(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
3157 struct radeon_winsys_bo
*esgs_ring_bo
,
3158 uint32_t esgs_ring_size
,
3159 struct radeon_winsys_bo
*gsvs_ring_bo
,
3160 uint32_t gsvs_ring_size
)
3162 if (!esgs_ring_bo
&& !gsvs_ring_bo
)
3166 radv_cs_add_buffer(queue
->device
->ws
, cs
, esgs_ring_bo
);
3169 radv_cs_add_buffer(queue
->device
->ws
, cs
, gsvs_ring_bo
);
3171 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
3172 radeon_set_uconfig_reg_seq(cs
, R_030900_VGT_ESGS_RING_SIZE
, 2);
3173 radeon_emit(cs
, esgs_ring_size
>> 8);
3174 radeon_emit(cs
, gsvs_ring_size
>> 8);
3176 radeon_set_config_reg_seq(cs
, R_0088C8_VGT_ESGS_RING_SIZE
, 2);
3177 radeon_emit(cs
, esgs_ring_size
>> 8);
3178 radeon_emit(cs
, gsvs_ring_size
>> 8);
3183 radv_emit_tess_factor_ring(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
3184 unsigned hs_offchip_param
, unsigned tf_ring_size
,
3185 struct radeon_winsys_bo
*tess_rings_bo
)
3192 tf_va
= radv_buffer_get_va(tess_rings_bo
);
3194 radv_cs_add_buffer(queue
->device
->ws
, cs
, tess_rings_bo
);
3196 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
3197 radeon_set_uconfig_reg(cs
, R_030938_VGT_TF_RING_SIZE
,
3198 S_030938_SIZE(tf_ring_size
/ 4));
3199 radeon_set_uconfig_reg(cs
, R_030940_VGT_TF_MEMORY_BASE
,
3202 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3203 radeon_set_uconfig_reg(cs
, R_030984_VGT_TF_MEMORY_BASE_HI_UMD
,
3204 S_030984_BASE_HI(tf_va
>> 40));
3205 } else if (queue
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
3206 radeon_set_uconfig_reg(cs
, R_030944_VGT_TF_MEMORY_BASE_HI
,
3207 S_030944_BASE_HI(tf_va
>> 40));
3209 radeon_set_uconfig_reg(cs
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
3212 radeon_set_config_reg(cs
, R_008988_VGT_TF_RING_SIZE
,
3213 S_008988_SIZE(tf_ring_size
/ 4));
3214 radeon_set_config_reg(cs
, R_0089B8_VGT_TF_MEMORY_BASE
,
3216 radeon_set_config_reg(cs
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
3222 radv_emit_graphics_scratch(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
3223 uint32_t size_per_wave
, uint32_t waves
,
3224 struct radeon_winsys_bo
*scratch_bo
)
3226 if (queue
->queue_family_index
!= RADV_QUEUE_GENERAL
)
3232 radv_cs_add_buffer(queue
->device
->ws
, cs
, scratch_bo
);
3234 radeon_set_context_reg(cs
, R_0286E8_SPI_TMPRING_SIZE
,
3235 S_0286E8_WAVES(waves
) |
3236 S_0286E8_WAVESIZE(round_up_u32(size_per_wave
, 1024)));
3240 radv_emit_compute_scratch(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
3241 uint32_t size_per_wave
, uint32_t waves
,
3242 struct radeon_winsys_bo
*compute_scratch_bo
)
3244 uint64_t scratch_va
;
3246 if (!compute_scratch_bo
)
3249 scratch_va
= radv_buffer_get_va(compute_scratch_bo
);
3251 radv_cs_add_buffer(queue
->device
->ws
, cs
, compute_scratch_bo
);
3253 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
, 2);
3254 radeon_emit(cs
, scratch_va
);
3255 radeon_emit(cs
, S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
3256 S_008F04_SWIZZLE_ENABLE(1));
3258 radeon_set_sh_reg(cs
, R_00B860_COMPUTE_TMPRING_SIZE
,
3259 S_00B860_WAVES(waves
) |
3260 S_00B860_WAVESIZE(round_up_u32(size_per_wave
, 1024)));
3264 radv_emit_global_shader_pointers(struct radv_queue
*queue
,
3265 struct radeon_cmdbuf
*cs
,
3266 struct radeon_winsys_bo
*descriptor_bo
)
3273 va
= radv_buffer_get_va(descriptor_bo
);
3275 radv_cs_add_buffer(queue
->device
->ws
, cs
, descriptor_bo
);
3277 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3278 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
3279 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
3280 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
,
3281 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
};
3283 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
3284 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
3287 } else if (queue
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
3288 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
3289 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
3290 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
,
3291 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
};
3293 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
3294 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
3298 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
3299 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
3300 R_00B230_SPI_SHADER_USER_DATA_GS_0
,
3301 R_00B330_SPI_SHADER_USER_DATA_ES_0
,
3302 R_00B430_SPI_SHADER_USER_DATA_HS_0
,
3303 R_00B530_SPI_SHADER_USER_DATA_LS_0
};
3305 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
3306 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
3313 radv_init_graphics_state(struct radeon_cmdbuf
*cs
, struct radv_queue
*queue
)
3315 struct radv_device
*device
= queue
->device
;
3317 if (device
->gfx_init
) {
3318 uint64_t va
= radv_buffer_get_va(device
->gfx_init
);
3320 radeon_emit(cs
, PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0));
3321 radeon_emit(cs
, va
);
3322 radeon_emit(cs
, va
>> 32);
3323 radeon_emit(cs
, device
->gfx_init_size_dw
& 0xffff);
3325 radv_cs_add_buffer(device
->ws
, cs
, device
->gfx_init
);
3327 si_emit_graphics(device
, cs
);
3332 radv_init_compute_state(struct radeon_cmdbuf
*cs
, struct radv_queue
*queue
)
3334 struct radv_physical_device
*physical_device
= queue
->device
->physical_device
;
3335 si_emit_compute(physical_device
, cs
);
3339 radv_get_preamble_cs(struct radv_queue
*queue
,
3340 uint32_t scratch_size_per_wave
,
3341 uint32_t scratch_waves
,
3342 uint32_t compute_scratch_size_per_wave
,
3343 uint32_t compute_scratch_waves
,
3344 uint32_t esgs_ring_size
,
3345 uint32_t gsvs_ring_size
,
3346 bool needs_tess_rings
,
3349 bool needs_sample_positions
,
3350 struct radeon_cmdbuf
**initial_full_flush_preamble_cs
,
3351 struct radeon_cmdbuf
**initial_preamble_cs
,
3352 struct radeon_cmdbuf
**continue_preamble_cs
)
3354 struct radeon_winsys_bo
*scratch_bo
= NULL
;
3355 struct radeon_winsys_bo
*descriptor_bo
= NULL
;
3356 struct radeon_winsys_bo
*compute_scratch_bo
= NULL
;
3357 struct radeon_winsys_bo
*esgs_ring_bo
= NULL
;
3358 struct radeon_winsys_bo
*gsvs_ring_bo
= NULL
;
3359 struct radeon_winsys_bo
*tess_rings_bo
= NULL
;
3360 struct radeon_winsys_bo
*gds_bo
= NULL
;
3361 struct radeon_winsys_bo
*gds_oa_bo
= NULL
;
3362 struct radeon_cmdbuf
*dest_cs
[3] = {0};
3363 bool add_tess_rings
= false, add_gds
= false, add_gds_oa
= false, add_sample_positions
= false;
3364 unsigned tess_factor_ring_size
= 0, tess_offchip_ring_size
= 0;
3365 unsigned max_offchip_buffers
;
3366 unsigned hs_offchip_param
= 0;
3367 unsigned tess_offchip_ring_offset
;
3368 uint32_t ring_bo_flags
= RADEON_FLAG_NO_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
;
3369 if (!queue
->has_tess_rings
) {
3370 if (needs_tess_rings
)
3371 add_tess_rings
= true;
3373 if (!queue
->has_gds
) {
3377 if (!queue
->has_gds_oa
) {
3381 if (!queue
->has_sample_positions
) {
3382 if (needs_sample_positions
)
3383 add_sample_positions
= true;
3385 tess_factor_ring_size
= 32768 * queue
->device
->physical_device
->rad_info
.max_se
;
3386 hs_offchip_param
= radv_get_hs_offchip_param(queue
->device
,
3387 &max_offchip_buffers
);
3388 tess_offchip_ring_offset
= align(tess_factor_ring_size
, 64 * 1024);
3389 tess_offchip_ring_size
= max_offchip_buffers
*
3390 queue
->device
->tess_offchip_block_dw_size
* 4;
3392 scratch_size_per_wave
= MAX2(scratch_size_per_wave
, queue
->scratch_size_per_wave
);
3393 if (scratch_size_per_wave
)
3394 scratch_waves
= MIN2(scratch_waves
, UINT32_MAX
/ scratch_size_per_wave
);
3398 compute_scratch_size_per_wave
= MAX2(compute_scratch_size_per_wave
, queue
->compute_scratch_size_per_wave
);
3399 if (compute_scratch_size_per_wave
)
3400 compute_scratch_waves
= MIN2(compute_scratch_waves
, UINT32_MAX
/ compute_scratch_size_per_wave
);
3402 compute_scratch_waves
= 0;
3404 if (scratch_size_per_wave
<= queue
->scratch_size_per_wave
&&
3405 scratch_waves
<= queue
->scratch_waves
&&
3406 compute_scratch_size_per_wave
<= queue
->compute_scratch_size_per_wave
&&
3407 compute_scratch_waves
<= queue
->compute_scratch_waves
&&
3408 esgs_ring_size
<= queue
->esgs_ring_size
&&
3409 gsvs_ring_size
<= queue
->gsvs_ring_size
&&
3410 !add_tess_rings
&& !add_gds
&& !add_gds_oa
&& !add_sample_positions
&&
3411 queue
->initial_preamble_cs
) {
3412 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
3413 *initial_preamble_cs
= queue
->initial_preamble_cs
;
3414 *continue_preamble_cs
= queue
->continue_preamble_cs
;
3415 if (!scratch_size_per_wave
&& !compute_scratch_size_per_wave
&&
3416 !esgs_ring_size
&& !gsvs_ring_size
&& !needs_tess_rings
&&
3417 !needs_gds
&& !needs_gds_oa
&& !needs_sample_positions
)
3418 *continue_preamble_cs
= NULL
;
3422 uint32_t scratch_size
= scratch_size_per_wave
* scratch_waves
;
3423 uint32_t queue_scratch_size
= queue
->scratch_size_per_wave
* queue
->scratch_waves
;
3424 if (scratch_size
> queue_scratch_size
) {
3425 scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3430 RADV_BO_PRIORITY_SCRATCH
);
3434 scratch_bo
= queue
->scratch_bo
;
3436 uint32_t compute_scratch_size
= compute_scratch_size_per_wave
* compute_scratch_waves
;
3437 uint32_t compute_queue_scratch_size
= queue
->compute_scratch_size_per_wave
* queue
->compute_scratch_waves
;
3438 if (compute_scratch_size
> compute_queue_scratch_size
) {
3439 compute_scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3440 compute_scratch_size
,
3444 RADV_BO_PRIORITY_SCRATCH
);
3445 if (!compute_scratch_bo
)
3449 compute_scratch_bo
= queue
->compute_scratch_bo
;
3451 if (esgs_ring_size
> queue
->esgs_ring_size
) {
3452 esgs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3457 RADV_BO_PRIORITY_SCRATCH
);
3461 esgs_ring_bo
= queue
->esgs_ring_bo
;
3462 esgs_ring_size
= queue
->esgs_ring_size
;
3465 if (gsvs_ring_size
> queue
->gsvs_ring_size
) {
3466 gsvs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3471 RADV_BO_PRIORITY_SCRATCH
);
3475 gsvs_ring_bo
= queue
->gsvs_ring_bo
;
3476 gsvs_ring_size
= queue
->gsvs_ring_size
;
3479 if (add_tess_rings
) {
3480 tess_rings_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3481 tess_offchip_ring_offset
+ tess_offchip_ring_size
,
3485 RADV_BO_PRIORITY_SCRATCH
);
3489 tess_rings_bo
= queue
->tess_rings_bo
;
3493 assert(queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
);
3495 /* 4 streamout GDS counters.
3496 * We need 256B (64 dw) of GDS, otherwise streamout hangs.
3498 gds_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3502 RADV_BO_PRIORITY_SCRATCH
);
3506 gds_bo
= queue
->gds_bo
;
3510 assert(queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
);
3512 gds_oa_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3516 RADV_BO_PRIORITY_SCRATCH
);
3520 gds_oa_bo
= queue
->gds_oa_bo
;
3523 if (scratch_bo
!= queue
->scratch_bo
||
3524 esgs_ring_bo
!= queue
->esgs_ring_bo
||
3525 gsvs_ring_bo
!= queue
->gsvs_ring_bo
||
3526 tess_rings_bo
!= queue
->tess_rings_bo
||
3527 add_sample_positions
) {
3529 if (gsvs_ring_bo
|| esgs_ring_bo
||
3530 tess_rings_bo
|| add_sample_positions
) {
3531 size
= 112; /* 2 dword + 2 padding + 4 dword * 6 */
3532 if (add_sample_positions
)
3533 size
+= 128; /* 64+32+16+8 = 120 bytes */
3535 else if (scratch_bo
)
3536 size
= 8; /* 2 dword */
3538 descriptor_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3542 RADEON_FLAG_CPU_ACCESS
|
3543 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
3544 RADEON_FLAG_READ_ONLY
,
3545 RADV_BO_PRIORITY_DESCRIPTOR
);
3549 descriptor_bo
= queue
->descriptor_bo
;
3551 if (descriptor_bo
!= queue
->descriptor_bo
) {
3552 uint32_t *map
= (uint32_t*)queue
->device
->ws
->buffer_map(descriptor_bo
);
3557 uint64_t scratch_va
= radv_buffer_get_va(scratch_bo
);
3558 uint32_t rsrc1
= S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
3559 S_008F04_SWIZZLE_ENABLE(1);
3560 map
[0] = scratch_va
;
3564 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_rings_bo
|| add_sample_positions
)
3565 fill_geom_tess_rings(queue
, map
, add_sample_positions
,
3566 esgs_ring_size
, esgs_ring_bo
,
3567 gsvs_ring_size
, gsvs_ring_bo
,
3568 tess_factor_ring_size
,
3569 tess_offchip_ring_offset
,
3570 tess_offchip_ring_size
,
3573 queue
->device
->ws
->buffer_unmap(descriptor_bo
);
3576 for(int i
= 0; i
< 3; ++i
) {
3577 struct radeon_cmdbuf
*cs
= NULL
;
3578 cs
= queue
->device
->ws
->cs_create(queue
->device
->ws
,
3579 queue
->queue_family_index
? RING_COMPUTE
: RING_GFX
);
3586 radv_cs_add_buffer(queue
->device
->ws
, cs
, scratch_bo
);
3588 /* Emit initial configuration. */
3589 switch (queue
->queue_family_index
) {
3590 case RADV_QUEUE_GENERAL
:
3591 radv_init_graphics_state(cs
, queue
);
3593 case RADV_QUEUE_COMPUTE
:
3594 radv_init_compute_state(cs
, queue
);
3596 case RADV_QUEUE_TRANSFER
:
3600 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_rings_bo
) {
3601 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3602 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
3604 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3605 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
3608 radv_emit_gs_ring_sizes(queue
, cs
, esgs_ring_bo
, esgs_ring_size
,
3609 gsvs_ring_bo
, gsvs_ring_size
);
3610 radv_emit_tess_factor_ring(queue
, cs
, hs_offchip_param
,
3611 tess_factor_ring_size
, tess_rings_bo
);
3612 radv_emit_global_shader_pointers(queue
, cs
, descriptor_bo
);
3613 radv_emit_compute_scratch(queue
, cs
, compute_scratch_size_per_wave
,
3614 compute_scratch_waves
, compute_scratch_bo
);
3615 radv_emit_graphics_scratch(queue
, cs
, scratch_size_per_wave
,
3616 scratch_waves
, scratch_bo
);
3619 radv_cs_add_buffer(queue
->device
->ws
, cs
, gds_bo
);
3621 radv_cs_add_buffer(queue
->device
->ws
, cs
, gds_oa_bo
);
3623 if (queue
->device
->trace_bo
)
3624 radv_cs_add_buffer(queue
->device
->ws
, cs
, queue
->device
->trace_bo
);
3626 if (queue
->device
->border_color_data
.bo
)
3627 radv_cs_add_buffer(queue
->device
->ws
, cs
,
3628 queue
->device
->border_color_data
.bo
);
3631 si_cs_emit_cache_flush(cs
,
3632 queue
->device
->physical_device
->rad_info
.chip_class
,
3634 queue
->queue_family_index
== RING_COMPUTE
&&
3635 queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
,
3636 (queue
->queue_family_index
== RADV_QUEUE_COMPUTE
? RADV_CMD_FLAG_CS_PARTIAL_FLUSH
: (RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
)) |
3637 RADV_CMD_FLAG_INV_ICACHE
|
3638 RADV_CMD_FLAG_INV_SCACHE
|
3639 RADV_CMD_FLAG_INV_VCACHE
|
3640 RADV_CMD_FLAG_INV_L2
|
3641 RADV_CMD_FLAG_START_PIPELINE_STATS
, 0);
3642 } else if (i
== 1) {
3643 si_cs_emit_cache_flush(cs
,
3644 queue
->device
->physical_device
->rad_info
.chip_class
,
3646 queue
->queue_family_index
== RING_COMPUTE
&&
3647 queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
,
3648 RADV_CMD_FLAG_INV_ICACHE
|
3649 RADV_CMD_FLAG_INV_SCACHE
|
3650 RADV_CMD_FLAG_INV_VCACHE
|
3651 RADV_CMD_FLAG_INV_L2
|
3652 RADV_CMD_FLAG_START_PIPELINE_STATS
, 0);
3655 if (queue
->device
->ws
->cs_finalize(cs
) != VK_SUCCESS
)
3659 if (queue
->initial_full_flush_preamble_cs
)
3660 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
3662 if (queue
->initial_preamble_cs
)
3663 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
3665 if (queue
->continue_preamble_cs
)
3666 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
3668 queue
->initial_full_flush_preamble_cs
= dest_cs
[0];
3669 queue
->initial_preamble_cs
= dest_cs
[1];
3670 queue
->continue_preamble_cs
= dest_cs
[2];
3672 if (scratch_bo
!= queue
->scratch_bo
) {
3673 if (queue
->scratch_bo
)
3674 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
3675 queue
->scratch_bo
= scratch_bo
;
3677 queue
->scratch_size_per_wave
= scratch_size_per_wave
;
3678 queue
->scratch_waves
= scratch_waves
;
3680 if (compute_scratch_bo
!= queue
->compute_scratch_bo
) {
3681 if (queue
->compute_scratch_bo
)
3682 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
3683 queue
->compute_scratch_bo
= compute_scratch_bo
;
3685 queue
->compute_scratch_size_per_wave
= compute_scratch_size_per_wave
;
3686 queue
->compute_scratch_waves
= compute_scratch_waves
;
3688 if (esgs_ring_bo
!= queue
->esgs_ring_bo
) {
3689 if (queue
->esgs_ring_bo
)
3690 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
3691 queue
->esgs_ring_bo
= esgs_ring_bo
;
3692 queue
->esgs_ring_size
= esgs_ring_size
;
3695 if (gsvs_ring_bo
!= queue
->gsvs_ring_bo
) {
3696 if (queue
->gsvs_ring_bo
)
3697 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
3698 queue
->gsvs_ring_bo
= gsvs_ring_bo
;
3699 queue
->gsvs_ring_size
= gsvs_ring_size
;
3702 if (tess_rings_bo
!= queue
->tess_rings_bo
) {
3703 queue
->tess_rings_bo
= tess_rings_bo
;
3704 queue
->has_tess_rings
= true;
3707 if (gds_bo
!= queue
->gds_bo
) {
3708 queue
->gds_bo
= gds_bo
;
3709 queue
->has_gds
= true;
3712 if (gds_oa_bo
!= queue
->gds_oa_bo
) {
3713 queue
->gds_oa_bo
= gds_oa_bo
;
3714 queue
->has_gds_oa
= true;
3717 if (descriptor_bo
!= queue
->descriptor_bo
) {
3718 if (queue
->descriptor_bo
)
3719 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
3721 queue
->descriptor_bo
= descriptor_bo
;
3724 if (add_sample_positions
)
3725 queue
->has_sample_positions
= true;
3727 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
3728 *initial_preamble_cs
= queue
->initial_preamble_cs
;
3729 *continue_preamble_cs
= queue
->continue_preamble_cs
;
3730 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
3731 *continue_preamble_cs
= NULL
;
3734 for (int i
= 0; i
< ARRAY_SIZE(dest_cs
); ++i
)
3736 queue
->device
->ws
->cs_destroy(dest_cs
[i
]);
3737 if (descriptor_bo
&& descriptor_bo
!= queue
->descriptor_bo
)
3738 queue
->device
->ws
->buffer_destroy(descriptor_bo
);
3739 if (scratch_bo
&& scratch_bo
!= queue
->scratch_bo
)
3740 queue
->device
->ws
->buffer_destroy(scratch_bo
);
3741 if (compute_scratch_bo
&& compute_scratch_bo
!= queue
->compute_scratch_bo
)
3742 queue
->device
->ws
->buffer_destroy(compute_scratch_bo
);
3743 if (esgs_ring_bo
&& esgs_ring_bo
!= queue
->esgs_ring_bo
)
3744 queue
->device
->ws
->buffer_destroy(esgs_ring_bo
);
3745 if (gsvs_ring_bo
&& gsvs_ring_bo
!= queue
->gsvs_ring_bo
)
3746 queue
->device
->ws
->buffer_destroy(gsvs_ring_bo
);
3747 if (tess_rings_bo
&& tess_rings_bo
!= queue
->tess_rings_bo
)
3748 queue
->device
->ws
->buffer_destroy(tess_rings_bo
);
3749 if (gds_bo
&& gds_bo
!= queue
->gds_bo
)
3750 queue
->device
->ws
->buffer_destroy(gds_bo
);
3751 if (gds_oa_bo
&& gds_oa_bo
!= queue
->gds_oa_bo
)
3752 queue
->device
->ws
->buffer_destroy(gds_oa_bo
);
3754 return vk_error(queue
->device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
3757 static VkResult
radv_alloc_sem_counts(struct radv_device
*device
,
3758 struct radv_winsys_sem_counts
*counts
,
3760 struct radv_semaphore_part
**sems
,
3761 const uint64_t *timeline_values
,
3765 int syncobj_idx
= 0, sem_idx
= 0;
3767 if (num_sems
== 0 && _fence
== VK_NULL_HANDLE
)
3770 for (uint32_t i
= 0; i
< num_sems
; i
++) {
3771 switch(sems
[i
]->kind
) {
3772 case RADV_SEMAPHORE_SYNCOBJ
:
3773 counts
->syncobj_count
++;
3775 case RADV_SEMAPHORE_WINSYS
:
3776 counts
->sem_count
++;
3778 case RADV_SEMAPHORE_NONE
:
3780 case RADV_SEMAPHORE_TIMELINE
:
3781 counts
->syncobj_count
++;
3786 if (_fence
!= VK_NULL_HANDLE
) {
3787 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
3789 struct radv_fence_part
*part
=
3790 fence
->temporary
.kind
!= RADV_FENCE_NONE
?
3791 &fence
->temporary
: &fence
->permanent
;
3792 if (part
->kind
== RADV_FENCE_SYNCOBJ
)
3793 counts
->syncobj_count
++;
3796 if (counts
->syncobj_count
) {
3797 counts
->syncobj
= (uint32_t *)malloc(sizeof(uint32_t) * counts
->syncobj_count
);
3798 if (!counts
->syncobj
)
3799 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3802 if (counts
->sem_count
) {
3803 counts
->sem
= (struct radeon_winsys_sem
**)malloc(sizeof(struct radeon_winsys_sem
*) * counts
->sem_count
);
3805 free(counts
->syncobj
);
3806 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3810 for (uint32_t i
= 0; i
< num_sems
; i
++) {
3811 switch(sems
[i
]->kind
) {
3812 case RADV_SEMAPHORE_NONE
:
3813 unreachable("Empty semaphore");
3815 case RADV_SEMAPHORE_SYNCOBJ
:
3816 counts
->syncobj
[syncobj_idx
++] = sems
[i
]->syncobj
;
3818 case RADV_SEMAPHORE_WINSYS
:
3819 counts
->sem
[sem_idx
++] = sems
[i
]->ws_sem
;
3821 case RADV_SEMAPHORE_TIMELINE
: {
3822 pthread_mutex_lock(&sems
[i
]->timeline
.mutex
);
3823 struct radv_timeline_point
*point
= NULL
;
3825 point
= radv_timeline_add_point_locked(device
, &sems
[i
]->timeline
, timeline_values
[i
]);
3827 point
= radv_timeline_find_point_at_least_locked(device
, &sems
[i
]->timeline
, timeline_values
[i
]);
3830 pthread_mutex_unlock(&sems
[i
]->timeline
.mutex
);
3833 counts
->syncobj
[syncobj_idx
++] = point
->syncobj
;
3835 /* Explicitly remove the semaphore so we might not find
3836 * a point later post-submit. */
3844 if (_fence
!= VK_NULL_HANDLE
) {
3845 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
3847 struct radv_fence_part
*part
=
3848 fence
->temporary
.kind
!= RADV_FENCE_NONE
?
3849 &fence
->temporary
: &fence
->permanent
;
3850 if (part
->kind
== RADV_FENCE_SYNCOBJ
)
3851 counts
->syncobj
[syncobj_idx
++] = part
->syncobj
;
3854 assert(syncobj_idx
<= counts
->syncobj_count
);
3855 counts
->syncobj_count
= syncobj_idx
;
3861 radv_free_sem_info(struct radv_winsys_sem_info
*sem_info
)
3863 free(sem_info
->wait
.syncobj
);
3864 free(sem_info
->wait
.sem
);
3865 free(sem_info
->signal
.syncobj
);
3866 free(sem_info
->signal
.sem
);
3870 static void radv_free_temp_syncobjs(struct radv_device
*device
,
3872 struct radv_semaphore_part
*sems
)
3874 for (uint32_t i
= 0; i
< num_sems
; i
++) {
3875 radv_destroy_semaphore_part(device
, sems
+ i
);
3880 radv_alloc_sem_info(struct radv_device
*device
,
3881 struct radv_winsys_sem_info
*sem_info
,
3883 struct radv_semaphore_part
**wait_sems
,
3884 const uint64_t *wait_values
,
3885 int num_signal_sems
,
3886 struct radv_semaphore_part
**signal_sems
,
3887 const uint64_t *signal_values
,
3891 memset(sem_info
, 0, sizeof(*sem_info
));
3893 ret
= radv_alloc_sem_counts(device
, &sem_info
->wait
, num_wait_sems
, wait_sems
, wait_values
, VK_NULL_HANDLE
, false);
3896 ret
= radv_alloc_sem_counts(device
, &sem_info
->signal
, num_signal_sems
, signal_sems
, signal_values
, fence
, true);
3898 radv_free_sem_info(sem_info
);
3900 /* caller can override these */
3901 sem_info
->cs_emit_wait
= true;
3902 sem_info
->cs_emit_signal
= true;
3907 radv_finalize_timelines(struct radv_device
*device
,
3908 uint32_t num_wait_sems
,
3909 struct radv_semaphore_part
**wait_sems
,
3910 const uint64_t *wait_values
,
3911 uint32_t num_signal_sems
,
3912 struct radv_semaphore_part
**signal_sems
,
3913 const uint64_t *signal_values
,
3914 struct list_head
*processing_list
)
3916 for (uint32_t i
= 0; i
< num_wait_sems
; ++i
) {
3917 if (wait_sems
[i
] && wait_sems
[i
]->kind
== RADV_SEMAPHORE_TIMELINE
) {
3918 pthread_mutex_lock(&wait_sems
[i
]->timeline
.mutex
);
3919 struct radv_timeline_point
*point
=
3920 radv_timeline_find_point_at_least_locked(device
, &wait_sems
[i
]->timeline
, wait_values
[i
]);
3921 point
->wait_count
-= 2;
3922 pthread_mutex_unlock(&wait_sems
[i
]->timeline
.mutex
);
3925 for (uint32_t i
= 0; i
< num_signal_sems
; ++i
) {
3926 if (signal_sems
[i
] && signal_sems
[i
]->kind
== RADV_SEMAPHORE_TIMELINE
) {
3927 pthread_mutex_lock(&signal_sems
[i
]->timeline
.mutex
);
3928 struct radv_timeline_point
*point
=
3929 radv_timeline_find_point_at_least_locked(device
, &signal_sems
[i
]->timeline
, signal_values
[i
]);
3930 signal_sems
[i
]->timeline
.highest_submitted
=
3931 MAX2(signal_sems
[i
]->timeline
.highest_submitted
, point
->value
);
3932 point
->wait_count
-= 2;
3933 radv_timeline_trigger_waiters_locked(&signal_sems
[i
]->timeline
, processing_list
);
3934 pthread_mutex_unlock(&signal_sems
[i
]->timeline
.mutex
);
3940 radv_sparse_buffer_bind_memory(struct radv_device
*device
,
3941 const VkSparseBufferMemoryBindInfo
*bind
)
3943 RADV_FROM_HANDLE(radv_buffer
, buffer
, bind
->buffer
);
3946 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
3947 struct radv_device_memory
*mem
= NULL
;
3949 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
3950 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
3952 result
= device
->ws
->buffer_virtual_bind(buffer
->bo
,
3953 bind
->pBinds
[i
].resourceOffset
,
3954 bind
->pBinds
[i
].size
,
3955 mem
? mem
->bo
: NULL
,
3956 bind
->pBinds
[i
].memoryOffset
);
3957 if (result
!= VK_SUCCESS
)
3965 radv_sparse_image_opaque_bind_memory(struct radv_device
*device
,
3966 const VkSparseImageOpaqueMemoryBindInfo
*bind
)
3968 RADV_FROM_HANDLE(radv_image
, image
, bind
->image
);
3971 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
3972 struct radv_device_memory
*mem
= NULL
;
3974 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
3975 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
3977 result
= device
->ws
->buffer_virtual_bind(image
->bo
,
3978 bind
->pBinds
[i
].resourceOffset
,
3979 bind
->pBinds
[i
].size
,
3980 mem
? mem
->bo
: NULL
,
3981 bind
->pBinds
[i
].memoryOffset
);
3982 if (result
!= VK_SUCCESS
)
3990 radv_get_preambles(struct radv_queue
*queue
,
3991 const VkCommandBuffer
*cmd_buffers
,
3992 uint32_t cmd_buffer_count
,
3993 struct radeon_cmdbuf
**initial_full_flush_preamble_cs
,
3994 struct radeon_cmdbuf
**initial_preamble_cs
,
3995 struct radeon_cmdbuf
**continue_preamble_cs
)
3997 uint32_t scratch_size_per_wave
= 0, waves_wanted
= 0;
3998 uint32_t compute_scratch_size_per_wave
= 0, compute_waves_wanted
= 0;
3999 uint32_t esgs_ring_size
= 0, gsvs_ring_size
= 0;
4000 bool tess_rings_needed
= false;
4001 bool gds_needed
= false;
4002 bool gds_oa_needed
= false;
4003 bool sample_positions_needed
= false;
4005 for (uint32_t j
= 0; j
< cmd_buffer_count
; j
++) {
4006 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
4009 scratch_size_per_wave
= MAX2(scratch_size_per_wave
, cmd_buffer
->scratch_size_per_wave_needed
);
4010 waves_wanted
= MAX2(waves_wanted
, cmd_buffer
->scratch_waves_wanted
);
4011 compute_scratch_size_per_wave
= MAX2(compute_scratch_size_per_wave
,
4012 cmd_buffer
->compute_scratch_size_per_wave_needed
);
4013 compute_waves_wanted
= MAX2(compute_waves_wanted
,
4014 cmd_buffer
->compute_scratch_waves_wanted
);
4015 esgs_ring_size
= MAX2(esgs_ring_size
, cmd_buffer
->esgs_ring_size_needed
);
4016 gsvs_ring_size
= MAX2(gsvs_ring_size
, cmd_buffer
->gsvs_ring_size_needed
);
4017 tess_rings_needed
|= cmd_buffer
->tess_rings_needed
;
4018 gds_needed
|= cmd_buffer
->gds_needed
;
4019 gds_oa_needed
|= cmd_buffer
->gds_oa_needed
;
4020 sample_positions_needed
|= cmd_buffer
->sample_positions_needed
;
4023 return radv_get_preamble_cs(queue
, scratch_size_per_wave
, waves_wanted
,
4024 compute_scratch_size_per_wave
, compute_waves_wanted
,
4025 esgs_ring_size
, gsvs_ring_size
, tess_rings_needed
,
4026 gds_needed
, gds_oa_needed
, sample_positions_needed
,
4027 initial_full_flush_preamble_cs
,
4028 initial_preamble_cs
, continue_preamble_cs
);
4031 struct radv_deferred_queue_submission
{
4032 struct radv_queue
*queue
;
4033 VkCommandBuffer
*cmd_buffers
;
4034 uint32_t cmd_buffer_count
;
4036 /* Sparse bindings that happen on a queue. */
4037 VkSparseBufferMemoryBindInfo
*buffer_binds
;
4038 uint32_t buffer_bind_count
;
4039 VkSparseImageOpaqueMemoryBindInfo
*image_opaque_binds
;
4040 uint32_t image_opaque_bind_count
;
4043 VkShaderStageFlags wait_dst_stage_mask
;
4044 struct radv_semaphore_part
**wait_semaphores
;
4045 uint32_t wait_semaphore_count
;
4046 struct radv_semaphore_part
**signal_semaphores
;
4047 uint32_t signal_semaphore_count
;
4050 uint64_t *wait_values
;
4051 uint64_t *signal_values
;
4053 struct radv_semaphore_part
*temporary_semaphore_parts
;
4054 uint32_t temporary_semaphore_part_count
;
4056 struct list_head queue_pending_list
;
4057 uint32_t submission_wait_count
;
4058 struct radv_timeline_waiter
*wait_nodes
;
4060 struct list_head processing_list
;
4063 struct radv_queue_submission
{
4064 const VkCommandBuffer
*cmd_buffers
;
4065 uint32_t cmd_buffer_count
;
4067 /* Sparse bindings that happen on a queue. */
4068 const VkSparseBufferMemoryBindInfo
*buffer_binds
;
4069 uint32_t buffer_bind_count
;
4070 const VkSparseImageOpaqueMemoryBindInfo
*image_opaque_binds
;
4071 uint32_t image_opaque_bind_count
;
4074 VkPipelineStageFlags wait_dst_stage_mask
;
4075 const VkSemaphore
*wait_semaphores
;
4076 uint32_t wait_semaphore_count
;
4077 const VkSemaphore
*signal_semaphores
;
4078 uint32_t signal_semaphore_count
;
4081 const uint64_t *wait_values
;
4082 uint32_t wait_value_count
;
4083 const uint64_t *signal_values
;
4084 uint32_t signal_value_count
;
4088 radv_create_deferred_submission(struct radv_queue
*queue
,
4089 const struct radv_queue_submission
*submission
,
4090 struct radv_deferred_queue_submission
**out
)
4092 struct radv_deferred_queue_submission
*deferred
= NULL
;
4093 size_t size
= sizeof(struct radv_deferred_queue_submission
);
4095 uint32_t temporary_count
= 0;
4096 for (uint32_t i
= 0; i
< submission
->wait_semaphore_count
; ++i
) {
4097 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, submission
->wait_semaphores
[i
]);
4098 if (semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
)
4102 size
+= submission
->cmd_buffer_count
* sizeof(VkCommandBuffer
);
4103 size
+= submission
->buffer_bind_count
* sizeof(VkSparseBufferMemoryBindInfo
);
4104 size
+= submission
->image_opaque_bind_count
* sizeof(VkSparseImageOpaqueMemoryBindInfo
);
4105 size
+= submission
->wait_semaphore_count
* sizeof(struct radv_semaphore_part
*);
4106 size
+= temporary_count
* sizeof(struct radv_semaphore_part
);
4107 size
+= submission
->signal_semaphore_count
* sizeof(struct radv_semaphore_part
*);
4108 size
+= submission
->wait_value_count
* sizeof(uint64_t);
4109 size
+= submission
->signal_value_count
* sizeof(uint64_t);
4110 size
+= submission
->wait_semaphore_count
* sizeof(struct radv_timeline_waiter
);
4112 deferred
= calloc(1, size
);
4114 return VK_ERROR_OUT_OF_HOST_MEMORY
;
4116 deferred
->queue
= queue
;
4118 deferred
->cmd_buffers
= (void*)(deferred
+ 1);
4119 deferred
->cmd_buffer_count
= submission
->cmd_buffer_count
;
4120 memcpy(deferred
->cmd_buffers
, submission
->cmd_buffers
,
4121 submission
->cmd_buffer_count
* sizeof(*deferred
->cmd_buffers
));
4123 deferred
->buffer_binds
= (void*)(deferred
->cmd_buffers
+ submission
->cmd_buffer_count
);
4124 deferred
->buffer_bind_count
= submission
->buffer_bind_count
;
4125 memcpy(deferred
->buffer_binds
, submission
->buffer_binds
,
4126 submission
->buffer_bind_count
* sizeof(*deferred
->buffer_binds
));
4128 deferred
->image_opaque_binds
= (void*)(deferred
->buffer_binds
+ submission
->buffer_bind_count
);
4129 deferred
->image_opaque_bind_count
= submission
->image_opaque_bind_count
;
4130 memcpy(deferred
->image_opaque_binds
, submission
->image_opaque_binds
,
4131 submission
->image_opaque_bind_count
* sizeof(*deferred
->image_opaque_binds
));
4133 deferred
->flush_caches
= submission
->flush_caches
;
4134 deferred
->wait_dst_stage_mask
= submission
->wait_dst_stage_mask
;
4136 deferred
->wait_semaphores
= (void*)(deferred
->image_opaque_binds
+ deferred
->image_opaque_bind_count
);
4137 deferred
->wait_semaphore_count
= submission
->wait_semaphore_count
;
4139 deferred
->signal_semaphores
= (void*)(deferred
->wait_semaphores
+ deferred
->wait_semaphore_count
);
4140 deferred
->signal_semaphore_count
= submission
->signal_semaphore_count
;
4142 deferred
->fence
= submission
->fence
;
4144 deferred
->temporary_semaphore_parts
= (void*)(deferred
->signal_semaphores
+ deferred
->signal_semaphore_count
);
4145 deferred
->temporary_semaphore_part_count
= temporary_count
;
4147 uint32_t temporary_idx
= 0;
4148 for (uint32_t i
= 0; i
< submission
->wait_semaphore_count
; ++i
) {
4149 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, submission
->wait_semaphores
[i
]);
4150 if (semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
) {
4151 deferred
->wait_semaphores
[i
] = &deferred
->temporary_semaphore_parts
[temporary_idx
];
4152 deferred
->temporary_semaphore_parts
[temporary_idx
] = semaphore
->temporary
;
4153 semaphore
->temporary
.kind
= RADV_SEMAPHORE_NONE
;
4156 deferred
->wait_semaphores
[i
] = &semaphore
->permanent
;
4159 for (uint32_t i
= 0; i
< submission
->signal_semaphore_count
; ++i
) {
4160 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, submission
->signal_semaphores
[i
]);
4161 if (semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
) {
4162 deferred
->signal_semaphores
[i
] = &semaphore
->temporary
;
4164 deferred
->signal_semaphores
[i
] = &semaphore
->permanent
;
4168 deferred
->wait_values
= (void*)(deferred
->temporary_semaphore_parts
+ temporary_count
);
4169 memcpy(deferred
->wait_values
, submission
->wait_values
, submission
->wait_value_count
* sizeof(uint64_t));
4170 deferred
->signal_values
= deferred
->wait_values
+ submission
->wait_value_count
;
4171 memcpy(deferred
->signal_values
, submission
->signal_values
, submission
->signal_value_count
* sizeof(uint64_t));
4173 deferred
->wait_nodes
= (void*)(deferred
->signal_values
+ submission
->signal_value_count
);
4174 /* This is worst-case. radv_queue_enqueue_submission will fill in further, but this
4175 * ensure the submission is not accidentally triggered early when adding wait timelines. */
4176 deferred
->submission_wait_count
= 1 + submission
->wait_semaphore_count
;
4183 radv_queue_enqueue_submission(struct radv_deferred_queue_submission
*submission
,
4184 struct list_head
*processing_list
)
4186 uint32_t wait_cnt
= 0;
4187 struct radv_timeline_waiter
*waiter
= submission
->wait_nodes
;
4188 for (uint32_t i
= 0; i
< submission
->wait_semaphore_count
; ++i
) {
4189 if (submission
->wait_semaphores
[i
]->kind
== RADV_SEMAPHORE_TIMELINE
) {
4190 pthread_mutex_lock(&submission
->wait_semaphores
[i
]->timeline
.mutex
);
4191 if (submission
->wait_semaphores
[i
]->timeline
.highest_submitted
< submission
->wait_values
[i
]) {
4193 waiter
->value
= submission
->wait_values
[i
];
4194 waiter
->submission
= submission
;
4195 list_addtail(&waiter
->list
, &submission
->wait_semaphores
[i
]->timeline
.waiters
);
4198 pthread_mutex_unlock(&submission
->wait_semaphores
[i
]->timeline
.mutex
);
4202 pthread_mutex_lock(&submission
->queue
->pending_mutex
);
4204 bool is_first
= list_is_empty(&submission
->queue
->pending_submissions
);
4205 list_addtail(&submission
->queue_pending_list
, &submission
->queue
->pending_submissions
);
4207 pthread_mutex_unlock(&submission
->queue
->pending_mutex
);
4209 /* If there is already a submission in the queue, that will decrement the counter by 1 when
4210 * submitted, but if the queue was empty, we decrement ourselves as there is no previous
4212 uint32_t decrement
= submission
->wait_semaphore_count
- wait_cnt
+ (is_first
? 1 : 0);
4213 if (__atomic_sub_fetch(&submission
->submission_wait_count
, decrement
, __ATOMIC_ACQ_REL
) == 0) {
4214 list_addtail(&submission
->processing_list
, processing_list
);
4219 radv_queue_submission_update_queue(struct radv_deferred_queue_submission
*submission
,
4220 struct list_head
*processing_list
)
4222 pthread_mutex_lock(&submission
->queue
->pending_mutex
);
4223 list_del(&submission
->queue_pending_list
);
4225 /* trigger the next submission in the queue. */
4226 if (!list_is_empty(&submission
->queue
->pending_submissions
)) {
4227 struct radv_deferred_queue_submission
*next_submission
=
4228 list_first_entry(&submission
->queue
->pending_submissions
,
4229 struct radv_deferred_queue_submission
,
4230 queue_pending_list
);
4231 if (p_atomic_dec_zero(&next_submission
->submission_wait_count
)) {
4232 list_addtail(&next_submission
->processing_list
, processing_list
);
4235 pthread_mutex_unlock(&submission
->queue
->pending_mutex
);
4237 pthread_cond_broadcast(&submission
->queue
->device
->timeline_cond
);
4241 radv_queue_submit_deferred(struct radv_deferred_queue_submission
*submission
,
4242 struct list_head
*processing_list
)
4244 RADV_FROM_HANDLE(radv_fence
, fence
, submission
->fence
);
4245 struct radv_queue
*queue
= submission
->queue
;
4246 struct radeon_winsys_ctx
*ctx
= queue
->hw_ctx
;
4247 uint32_t max_cs_submission
= queue
->device
->trace_bo
? 1 : RADV_MAX_IBS_PER_SUBMIT
;
4248 struct radeon_winsys_fence
*base_fence
= NULL
;
4249 bool do_flush
= submission
->flush_caches
|| submission
->wait_dst_stage_mask
;
4250 bool can_patch
= true;
4252 struct radv_winsys_sem_info sem_info
;
4254 struct radeon_cmdbuf
*initial_preamble_cs
= NULL
;
4255 struct radeon_cmdbuf
*initial_flush_preamble_cs
= NULL
;
4256 struct radeon_cmdbuf
*continue_preamble_cs
= NULL
;
4259 /* Under most circumstances, out fences won't be temporary.
4260 * However, the spec does allow it for opaque_fd.
4262 * From the Vulkan 1.0.53 spec:
4264 * "If the import is temporary, the implementation must
4265 * restore the semaphore to its prior permanent state after
4266 * submitting the next semaphore wait operation."
4268 struct radv_fence_part
*part
=
4269 fence
->temporary
.kind
!= RADV_FENCE_NONE
?
4270 &fence
->temporary
: &fence
->permanent
;
4271 if (part
->kind
== RADV_FENCE_WINSYS
)
4272 base_fence
= part
->fence
;
4275 result
= radv_get_preambles(queue
, submission
->cmd_buffers
,
4276 submission
->cmd_buffer_count
,
4277 &initial_preamble_cs
,
4278 &initial_flush_preamble_cs
,
4279 &continue_preamble_cs
);
4280 if (result
!= VK_SUCCESS
)
4283 result
= radv_alloc_sem_info(queue
->device
,
4285 submission
->wait_semaphore_count
,
4286 submission
->wait_semaphores
,
4287 submission
->wait_values
,
4288 submission
->signal_semaphore_count
,
4289 submission
->signal_semaphores
,
4290 submission
->signal_values
,
4292 if (result
!= VK_SUCCESS
)
4295 for (uint32_t i
= 0; i
< submission
->buffer_bind_count
; ++i
) {
4296 result
= radv_sparse_buffer_bind_memory(queue
->device
,
4297 submission
->buffer_binds
+ i
);
4298 if (result
!= VK_SUCCESS
)
4302 for (uint32_t i
= 0; i
< submission
->image_opaque_bind_count
; ++i
) {
4303 result
= radv_sparse_image_opaque_bind_memory(queue
->device
,
4304 submission
->image_opaque_binds
+ i
);
4305 if (result
!= VK_SUCCESS
)
4309 if (!submission
->cmd_buffer_count
) {
4310 result
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
,
4311 &queue
->device
->empty_cs
[queue
->queue_family_index
],
4315 if (result
!= VK_SUCCESS
)
4318 struct radeon_cmdbuf
**cs_array
= malloc(sizeof(struct radeon_cmdbuf
*) *
4319 (submission
->cmd_buffer_count
));
4321 for (uint32_t j
= 0; j
< submission
->cmd_buffer_count
; j
++) {
4322 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, submission
->cmd_buffers
[j
]);
4323 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
4325 cs_array
[j
] = cmd_buffer
->cs
;
4326 if ((cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT
))
4329 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_PENDING
;
4332 for (uint32_t j
= 0; j
< submission
->cmd_buffer_count
; j
+= advance
) {
4333 struct radeon_cmdbuf
*initial_preamble
= (do_flush
&& !j
) ? initial_flush_preamble_cs
: initial_preamble_cs
;
4334 const struct radv_winsys_bo_list
*bo_list
= NULL
;
4336 advance
= MIN2(max_cs_submission
,
4337 submission
->cmd_buffer_count
- j
);
4339 if (queue
->device
->trace_bo
)
4340 *queue
->device
->trace_id_ptr
= 0;
4342 sem_info
.cs_emit_wait
= j
== 0;
4343 sem_info
.cs_emit_signal
= j
+ advance
== submission
->cmd_buffer_count
;
4345 if (unlikely(queue
->device
->use_global_bo_list
)) {
4346 pthread_mutex_lock(&queue
->device
->bo_list
.mutex
);
4347 bo_list
= &queue
->device
->bo_list
.list
;
4350 result
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
, cs_array
+ j
,
4351 advance
, initial_preamble
, continue_preamble_cs
,
4353 can_patch
, base_fence
);
4355 if (unlikely(queue
->device
->use_global_bo_list
))
4356 pthread_mutex_unlock(&queue
->device
->bo_list
.mutex
);
4358 if (result
!= VK_SUCCESS
)
4361 if (queue
->device
->trace_bo
) {
4362 radv_check_gpu_hangs(queue
, cs_array
[j
]);
4369 radv_free_temp_syncobjs(queue
->device
,
4370 submission
->temporary_semaphore_part_count
,
4371 submission
->temporary_semaphore_parts
);
4372 radv_finalize_timelines(queue
->device
,
4373 submission
->wait_semaphore_count
,
4374 submission
->wait_semaphores
,
4375 submission
->wait_values
,
4376 submission
->signal_semaphore_count
,
4377 submission
->signal_semaphores
,
4378 submission
->signal_values
,
4380 /* Has to happen after timeline finalization to make sure the
4381 * condition variable is only triggered when timelines and queue have
4383 radv_queue_submission_update_queue(submission
, processing_list
);
4384 radv_free_sem_info(&sem_info
);
4389 if (result
!= VK_SUCCESS
&& result
!= VK_ERROR_DEVICE_LOST
) {
4390 /* When something bad happened during the submission, such as
4391 * an out of memory issue, it might be hard to recover from
4392 * this inconsistent state. To avoid this sort of problem, we
4393 * assume that we are in a really bad situation and return
4394 * VK_ERROR_DEVICE_LOST to ensure the clients do not attempt
4395 * to submit the same job again to this device.
4397 result
= VK_ERROR_DEVICE_LOST
;
4400 radv_free_temp_syncobjs(queue
->device
,
4401 submission
->temporary_semaphore_part_count
,
4402 submission
->temporary_semaphore_parts
);
4408 radv_process_submissions(struct list_head
*processing_list
)
4410 while(!list_is_empty(processing_list
)) {
4411 struct radv_deferred_queue_submission
*submission
=
4412 list_first_entry(processing_list
, struct radv_deferred_queue_submission
, processing_list
);
4413 list_del(&submission
->processing_list
);
4415 VkResult result
= radv_queue_submit_deferred(submission
, processing_list
);
4416 if (result
!= VK_SUCCESS
)
4422 static VkResult
radv_queue_submit(struct radv_queue
*queue
,
4423 const struct radv_queue_submission
*submission
)
4425 struct radv_deferred_queue_submission
*deferred
= NULL
;
4427 VkResult result
= radv_create_deferred_submission(queue
, submission
, &deferred
);
4428 if (result
!= VK_SUCCESS
)
4431 struct list_head processing_list
;
4432 list_inithead(&processing_list
);
4434 radv_queue_enqueue_submission(deferred
, &processing_list
);
4435 return radv_process_submissions(&processing_list
);
4439 radv_queue_internal_submit(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
)
4441 struct radeon_winsys_ctx
*ctx
= queue
->hw_ctx
;
4442 struct radv_winsys_sem_info sem_info
;
4445 result
= radv_alloc_sem_info(queue
->device
, &sem_info
, 0, NULL
, 0, 0,
4446 0, NULL
, VK_NULL_HANDLE
);
4447 if (result
!= VK_SUCCESS
)
4450 result
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
, &cs
, 1,
4451 NULL
, NULL
, &sem_info
, NULL
,
4453 radv_free_sem_info(&sem_info
);
4454 if (result
!= VK_SUCCESS
)
4461 /* Signals fence as soon as all the work currently put on queue is done. */
4462 static VkResult
radv_signal_fence(struct radv_queue
*queue
,
4465 return radv_queue_submit(queue
, &(struct radv_queue_submission
) {
4470 static bool radv_submit_has_effects(const VkSubmitInfo
*info
)
4472 return info
->commandBufferCount
||
4473 info
->waitSemaphoreCount
||
4474 info
->signalSemaphoreCount
;
4477 VkResult
radv_QueueSubmit(
4479 uint32_t submitCount
,
4480 const VkSubmitInfo
* pSubmits
,
4483 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
4485 uint32_t fence_idx
= 0;
4486 bool flushed_caches
= false;
4488 if (fence
!= VK_NULL_HANDLE
) {
4489 for (uint32_t i
= 0; i
< submitCount
; ++i
)
4490 if (radv_submit_has_effects(pSubmits
+ i
))
4493 fence_idx
= UINT32_MAX
;
4495 for (uint32_t i
= 0; i
< submitCount
; i
++) {
4496 if (!radv_submit_has_effects(pSubmits
+ i
) && fence_idx
!= i
)
4499 VkPipelineStageFlags wait_dst_stage_mask
= 0;
4500 for (unsigned j
= 0; j
< pSubmits
[i
].waitSemaphoreCount
; ++j
) {
4501 wait_dst_stage_mask
|= pSubmits
[i
].pWaitDstStageMask
[j
];
4504 const VkTimelineSemaphoreSubmitInfo
*timeline_info
=
4505 vk_find_struct_const(pSubmits
[i
].pNext
, TIMELINE_SEMAPHORE_SUBMIT_INFO
);
4507 result
= radv_queue_submit(queue
, &(struct radv_queue_submission
) {
4508 .cmd_buffers
= pSubmits
[i
].pCommandBuffers
,
4509 .cmd_buffer_count
= pSubmits
[i
].commandBufferCount
,
4510 .wait_dst_stage_mask
= wait_dst_stage_mask
,
4511 .flush_caches
= !flushed_caches
,
4512 .wait_semaphores
= pSubmits
[i
].pWaitSemaphores
,
4513 .wait_semaphore_count
= pSubmits
[i
].waitSemaphoreCount
,
4514 .signal_semaphores
= pSubmits
[i
].pSignalSemaphores
,
4515 .signal_semaphore_count
= pSubmits
[i
].signalSemaphoreCount
,
4516 .fence
= i
== fence_idx
? fence
: VK_NULL_HANDLE
,
4517 .wait_values
= timeline_info
? timeline_info
->pWaitSemaphoreValues
: NULL
,
4518 .wait_value_count
= timeline_info
&& timeline_info
->pWaitSemaphoreValues
? timeline_info
->waitSemaphoreValueCount
: 0,
4519 .signal_values
= timeline_info
? timeline_info
->pSignalSemaphoreValues
: NULL
,
4520 .signal_value_count
= timeline_info
&& timeline_info
->pSignalSemaphoreValues
? timeline_info
->signalSemaphoreValueCount
: 0,
4522 if (result
!= VK_SUCCESS
)
4525 flushed_caches
= true;
4528 if (fence
!= VK_NULL_HANDLE
&& !submitCount
) {
4529 result
= radv_signal_fence(queue
, fence
);
4530 if (result
!= VK_SUCCESS
)
4537 VkResult
radv_QueueWaitIdle(
4540 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
4542 pthread_mutex_lock(&queue
->pending_mutex
);
4543 while (!list_is_empty(&queue
->pending_submissions
)) {
4544 pthread_cond_wait(&queue
->device
->timeline_cond
, &queue
->pending_mutex
);
4546 pthread_mutex_unlock(&queue
->pending_mutex
);
4548 if (!queue
->device
->ws
->ctx_wait_idle(queue
->hw_ctx
,
4549 radv_queue_family_to_ring(queue
->queue_family_index
),
4551 return VK_ERROR_DEVICE_LOST
;
4556 VkResult
radv_DeviceWaitIdle(
4559 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4561 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
4562 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++) {
4564 radv_QueueWaitIdle(radv_queue_to_handle(&device
->queues
[i
][q
]));
4566 if (result
!= VK_SUCCESS
)
4573 VkResult
radv_EnumerateInstanceExtensionProperties(
4574 const char* pLayerName
,
4575 uint32_t* pPropertyCount
,
4576 VkExtensionProperties
* pProperties
)
4578 VK_OUTARRAY_MAKE(out
, pProperties
, pPropertyCount
);
4580 for (int i
= 0; i
< RADV_INSTANCE_EXTENSION_COUNT
; i
++) {
4581 if (radv_instance_extensions_supported
.extensions
[i
]) {
4582 vk_outarray_append(&out
, prop
) {
4583 *prop
= radv_instance_extensions
[i
];
4588 return vk_outarray_status(&out
);
4591 VkResult
radv_EnumerateDeviceExtensionProperties(
4592 VkPhysicalDevice physicalDevice
,
4593 const char* pLayerName
,
4594 uint32_t* pPropertyCount
,
4595 VkExtensionProperties
* pProperties
)
4597 RADV_FROM_HANDLE(radv_physical_device
, device
, physicalDevice
);
4598 VK_OUTARRAY_MAKE(out
, pProperties
, pPropertyCount
);
4600 for (int i
= 0; i
< RADV_DEVICE_EXTENSION_COUNT
; i
++) {
4601 if (device
->supported_extensions
.extensions
[i
]) {
4602 vk_outarray_append(&out
, prop
) {
4603 *prop
= radv_device_extensions
[i
];
4608 return vk_outarray_status(&out
);
4611 PFN_vkVoidFunction
radv_GetInstanceProcAddr(
4612 VkInstance _instance
,
4615 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
4617 /* The Vulkan 1.0 spec for vkGetInstanceProcAddr has a table of exactly
4618 * when we have to return valid function pointers, NULL, or it's left
4619 * undefined. See the table for exact details.
4624 #define LOOKUP_RADV_ENTRYPOINT(entrypoint) \
4625 if (strcmp(pName, "vk" #entrypoint) == 0) \
4626 return (PFN_vkVoidFunction)radv_##entrypoint
4628 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceExtensionProperties
);
4629 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceLayerProperties
);
4630 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceVersion
);
4631 LOOKUP_RADV_ENTRYPOINT(CreateInstance
);
4633 /* GetInstanceProcAddr() can also be called with a NULL instance.
4634 * See https://gitlab.khronos.org/vulkan/vulkan/issues/2057
4636 LOOKUP_RADV_ENTRYPOINT(GetInstanceProcAddr
);
4638 #undef LOOKUP_RADV_ENTRYPOINT
4640 if (instance
== NULL
)
4643 int idx
= radv_get_instance_entrypoint_index(pName
);
4645 return instance
->dispatch
.entrypoints
[idx
];
4647 idx
= radv_get_physical_device_entrypoint_index(pName
);
4649 return instance
->physical_device_dispatch
.entrypoints
[idx
];
4651 idx
= radv_get_device_entrypoint_index(pName
);
4653 return instance
->device_dispatch
.entrypoints
[idx
];
4658 /* The loader wants us to expose a second GetInstanceProcAddr function
4659 * to work around certain LD_PRELOAD issues seen in apps.
4662 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
4663 VkInstance instance
,
4667 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
4668 VkInstance instance
,
4671 return radv_GetInstanceProcAddr(instance
, pName
);
4675 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetPhysicalDeviceProcAddr(
4676 VkInstance _instance
,
4680 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetPhysicalDeviceProcAddr(
4681 VkInstance _instance
,
4684 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
4686 if (!pName
|| !instance
)
4689 int idx
= radv_get_physical_device_entrypoint_index(pName
);
4693 return instance
->physical_device_dispatch
.entrypoints
[idx
];
4696 PFN_vkVoidFunction
radv_GetDeviceProcAddr(
4700 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4702 if (!device
|| !pName
)
4705 int idx
= radv_get_device_entrypoint_index(pName
);
4709 return device
->dispatch
.entrypoints
[idx
];
4712 bool radv_get_memory_fd(struct radv_device
*device
,
4713 struct radv_device_memory
*memory
,
4716 struct radeon_bo_metadata metadata
;
4718 if (memory
->image
) {
4719 if (memory
->image
->tiling
!= VK_IMAGE_TILING_LINEAR
)
4720 radv_init_metadata(device
, memory
->image
, &metadata
);
4721 device
->ws
->buffer_set_metadata(memory
->bo
, &metadata
);
4724 return device
->ws
->buffer_get_fd(device
->ws
, memory
->bo
,
4730 radv_free_memory(struct radv_device
*device
,
4731 const VkAllocationCallbacks
* pAllocator
,
4732 struct radv_device_memory
*mem
)
4737 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
4738 if (mem
->android_hardware_buffer
)
4739 AHardwareBuffer_release(mem
->android_hardware_buffer
);
4743 if (device
->overallocation_disallowed
) {
4744 mtx_lock(&device
->overallocation_mutex
);
4745 device
->allocated_memory_size
[mem
->heap_index
] -= mem
->alloc_size
;
4746 mtx_unlock(&device
->overallocation_mutex
);
4749 radv_bo_list_remove(device
, mem
->bo
);
4750 device
->ws
->buffer_destroy(mem
->bo
);
4754 vk_object_base_finish(&mem
->base
);
4755 vk_free2(&device
->vk
.alloc
, pAllocator
, mem
);
4758 static VkResult
radv_alloc_memory(struct radv_device
*device
,
4759 const VkMemoryAllocateInfo
* pAllocateInfo
,
4760 const VkAllocationCallbacks
* pAllocator
,
4761 VkDeviceMemory
* pMem
)
4763 struct radv_device_memory
*mem
;
4765 enum radeon_bo_domain domain
;
4768 assert(pAllocateInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO
);
4770 const VkImportMemoryFdInfoKHR
*import_info
=
4771 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_FD_INFO_KHR
);
4772 const VkMemoryDedicatedAllocateInfo
*dedicate_info
=
4773 vk_find_struct_const(pAllocateInfo
->pNext
, MEMORY_DEDICATED_ALLOCATE_INFO
);
4774 const VkExportMemoryAllocateInfo
*export_info
=
4775 vk_find_struct_const(pAllocateInfo
->pNext
, EXPORT_MEMORY_ALLOCATE_INFO
);
4776 const struct VkImportAndroidHardwareBufferInfoANDROID
*ahb_import_info
=
4777 vk_find_struct_const(pAllocateInfo
->pNext
,
4778 IMPORT_ANDROID_HARDWARE_BUFFER_INFO_ANDROID
);
4779 const VkImportMemoryHostPointerInfoEXT
*host_ptr_info
=
4780 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_HOST_POINTER_INFO_EXT
);
4782 const struct wsi_memory_allocate_info
*wsi_info
=
4783 vk_find_struct_const(pAllocateInfo
->pNext
, WSI_MEMORY_ALLOCATE_INFO_MESA
);
4785 if (pAllocateInfo
->allocationSize
== 0 && !ahb_import_info
&&
4786 !(export_info
&& (export_info
->handleTypes
& VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID
))) {
4787 /* Apparently, this is allowed */
4788 *pMem
= VK_NULL_HANDLE
;
4792 mem
= vk_zalloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*mem
), 8,
4793 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4795 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4797 vk_object_base_init(&device
->vk
, &mem
->base
,
4798 VK_OBJECT_TYPE_DEVICE_MEMORY
);
4800 if (wsi_info
&& wsi_info
->implicit_sync
)
4801 flags
|= RADEON_FLAG_IMPLICIT_SYNC
;
4803 if (dedicate_info
) {
4804 mem
->image
= radv_image_from_handle(dedicate_info
->image
);
4805 mem
->buffer
= radv_buffer_from_handle(dedicate_info
->buffer
);
4811 float priority_float
= 0.5;
4812 const struct VkMemoryPriorityAllocateInfoEXT
*priority_ext
=
4813 vk_find_struct_const(pAllocateInfo
->pNext
,
4814 MEMORY_PRIORITY_ALLOCATE_INFO_EXT
);
4816 priority_float
= priority_ext
->priority
;
4818 unsigned priority
= MIN2(RADV_BO_PRIORITY_APPLICATION_MAX
- 1,
4819 (int)(priority_float
* RADV_BO_PRIORITY_APPLICATION_MAX
));
4821 mem
->user_ptr
= NULL
;
4824 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
4825 mem
->android_hardware_buffer
= NULL
;
4828 if (ahb_import_info
) {
4829 result
= radv_import_ahb_memory(device
, mem
, priority
, ahb_import_info
);
4830 if (result
!= VK_SUCCESS
)
4832 } else if(export_info
&& (export_info
->handleTypes
& VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID
)) {
4833 result
= radv_create_ahb_memory(device
, mem
, priority
, pAllocateInfo
);
4834 if (result
!= VK_SUCCESS
)
4836 } else if (import_info
) {
4837 assert(import_info
->handleType
==
4838 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT
||
4839 import_info
->handleType
==
4840 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
4841 mem
->bo
= device
->ws
->buffer_from_fd(device
->ws
, import_info
->fd
,
4844 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE
;
4847 close(import_info
->fd
);
4849 } else if (host_ptr_info
) {
4850 assert(host_ptr_info
->handleType
== VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT
);
4851 mem
->bo
= device
->ws
->buffer_from_ptr(device
->ws
, host_ptr_info
->pHostPointer
,
4852 pAllocateInfo
->allocationSize
,
4855 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE
;
4858 mem
->user_ptr
= host_ptr_info
->pHostPointer
;
4861 uint64_t alloc_size
= align_u64(pAllocateInfo
->allocationSize
, 4096);
4862 uint32_t heap_index
;
4864 heap_index
= device
->physical_device
->memory_properties
.memoryTypes
[pAllocateInfo
->memoryTypeIndex
].heapIndex
;
4865 domain
= device
->physical_device
->memory_domains
[pAllocateInfo
->memoryTypeIndex
];
4866 flags
|= device
->physical_device
->memory_flags
[pAllocateInfo
->memoryTypeIndex
];
4868 if (!dedicate_info
&& !import_info
&& (!export_info
|| !export_info
->handleTypes
)) {
4869 flags
|= RADEON_FLAG_NO_INTERPROCESS_SHARING
;
4870 if (device
->use_global_bo_list
) {
4871 flags
|= RADEON_FLAG_PREFER_LOCAL_BO
;
4875 if (device
->overallocation_disallowed
) {
4876 uint64_t total_size
=
4877 device
->physical_device
->memory_properties
.memoryHeaps
[heap_index
].size
;
4879 mtx_lock(&device
->overallocation_mutex
);
4880 if (device
->allocated_memory_size
[heap_index
] + alloc_size
> total_size
) {
4881 mtx_unlock(&device
->overallocation_mutex
);
4882 result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
4885 device
->allocated_memory_size
[heap_index
] += alloc_size
;
4886 mtx_unlock(&device
->overallocation_mutex
);
4889 mem
->bo
= device
->ws
->buffer_create(device
->ws
, alloc_size
, device
->physical_device
->rad_info
.max_alignment
,
4890 domain
, flags
, priority
);
4893 if (device
->overallocation_disallowed
) {
4894 mtx_lock(&device
->overallocation_mutex
);
4895 device
->allocated_memory_size
[heap_index
] -= alloc_size
;
4896 mtx_unlock(&device
->overallocation_mutex
);
4898 result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
4902 mem
->heap_index
= heap_index
;
4903 mem
->alloc_size
= alloc_size
;
4907 result
= radv_bo_list_add(device
, mem
->bo
);
4908 if (result
!= VK_SUCCESS
)
4912 *pMem
= radv_device_memory_to_handle(mem
);
4917 radv_free_memory(device
, pAllocator
,mem
);
4922 VkResult
radv_AllocateMemory(
4924 const VkMemoryAllocateInfo
* pAllocateInfo
,
4925 const VkAllocationCallbacks
* pAllocator
,
4926 VkDeviceMemory
* pMem
)
4928 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4929 return radv_alloc_memory(device
, pAllocateInfo
, pAllocator
, pMem
);
4932 void radv_FreeMemory(
4934 VkDeviceMemory _mem
,
4935 const VkAllocationCallbacks
* pAllocator
)
4937 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4938 RADV_FROM_HANDLE(radv_device_memory
, mem
, _mem
);
4940 radv_free_memory(device
, pAllocator
, mem
);
4943 VkResult
radv_MapMemory(
4945 VkDeviceMemory _memory
,
4946 VkDeviceSize offset
,
4948 VkMemoryMapFlags flags
,
4951 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4952 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
4960 *ppData
= mem
->user_ptr
;
4962 *ppData
= device
->ws
->buffer_map(mem
->bo
);
4969 return vk_error(device
->instance
, VK_ERROR_MEMORY_MAP_FAILED
);
4972 void radv_UnmapMemory(
4974 VkDeviceMemory _memory
)
4976 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4977 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
4982 if (mem
->user_ptr
== NULL
)
4983 device
->ws
->buffer_unmap(mem
->bo
);
4986 VkResult
radv_FlushMappedMemoryRanges(
4988 uint32_t memoryRangeCount
,
4989 const VkMappedMemoryRange
* pMemoryRanges
)
4994 VkResult
radv_InvalidateMappedMemoryRanges(
4996 uint32_t memoryRangeCount
,
4997 const VkMappedMemoryRange
* pMemoryRanges
)
5002 void radv_GetBufferMemoryRequirements(
5005 VkMemoryRequirements
* pMemoryRequirements
)
5007 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5008 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
5010 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
5012 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
5013 pMemoryRequirements
->alignment
= 4096;
5015 pMemoryRequirements
->alignment
= 16;
5017 pMemoryRequirements
->size
= align64(buffer
->size
, pMemoryRequirements
->alignment
);
5020 void radv_GetBufferMemoryRequirements2(
5022 const VkBufferMemoryRequirementsInfo2
*pInfo
,
5023 VkMemoryRequirements2
*pMemoryRequirements
)
5025 radv_GetBufferMemoryRequirements(device
, pInfo
->buffer
,
5026 &pMemoryRequirements
->memoryRequirements
);
5027 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
5028 switch (ext
->sType
) {
5029 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS
: {
5030 VkMemoryDedicatedRequirements
*req
=
5031 (VkMemoryDedicatedRequirements
*) ext
;
5032 req
->requiresDedicatedAllocation
= false;
5033 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
5042 void radv_GetImageMemoryRequirements(
5045 VkMemoryRequirements
* pMemoryRequirements
)
5047 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5048 RADV_FROM_HANDLE(radv_image
, image
, _image
);
5050 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
5052 pMemoryRequirements
->size
= image
->size
;
5053 pMemoryRequirements
->alignment
= image
->alignment
;
5056 void radv_GetImageMemoryRequirements2(
5058 const VkImageMemoryRequirementsInfo2
*pInfo
,
5059 VkMemoryRequirements2
*pMemoryRequirements
)
5061 radv_GetImageMemoryRequirements(device
, pInfo
->image
,
5062 &pMemoryRequirements
->memoryRequirements
);
5064 RADV_FROM_HANDLE(radv_image
, image
, pInfo
->image
);
5066 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
5067 switch (ext
->sType
) {
5068 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS
: {
5069 VkMemoryDedicatedRequirements
*req
=
5070 (VkMemoryDedicatedRequirements
*) ext
;
5071 req
->requiresDedicatedAllocation
= image
->shareable
&&
5072 image
->tiling
!= VK_IMAGE_TILING_LINEAR
;
5073 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
5082 void radv_GetImageSparseMemoryRequirements(
5085 uint32_t* pSparseMemoryRequirementCount
,
5086 VkSparseImageMemoryRequirements
* pSparseMemoryRequirements
)
5091 void radv_GetImageSparseMemoryRequirements2(
5093 const VkImageSparseMemoryRequirementsInfo2
*pInfo
,
5094 uint32_t* pSparseMemoryRequirementCount
,
5095 VkSparseImageMemoryRequirements2
*pSparseMemoryRequirements
)
5100 void radv_GetDeviceMemoryCommitment(
5102 VkDeviceMemory memory
,
5103 VkDeviceSize
* pCommittedMemoryInBytes
)
5105 *pCommittedMemoryInBytes
= 0;
5108 VkResult
radv_BindBufferMemory2(VkDevice device
,
5109 uint32_t bindInfoCount
,
5110 const VkBindBufferMemoryInfo
*pBindInfos
)
5112 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
5113 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
5114 RADV_FROM_HANDLE(radv_buffer
, buffer
, pBindInfos
[i
].buffer
);
5117 buffer
->bo
= mem
->bo
;
5118 buffer
->offset
= pBindInfos
[i
].memoryOffset
;
5126 VkResult
radv_BindBufferMemory(
5129 VkDeviceMemory memory
,
5130 VkDeviceSize memoryOffset
)
5132 const VkBindBufferMemoryInfo info
= {
5133 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO
,
5136 .memoryOffset
= memoryOffset
5139 return radv_BindBufferMemory2(device
, 1, &info
);
5142 VkResult
radv_BindImageMemory2(VkDevice device
,
5143 uint32_t bindInfoCount
,
5144 const VkBindImageMemoryInfo
*pBindInfos
)
5146 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
5147 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
5148 RADV_FROM_HANDLE(radv_image
, image
, pBindInfos
[i
].image
);
5151 image
->bo
= mem
->bo
;
5152 image
->offset
= pBindInfos
[i
].memoryOffset
;
5162 VkResult
radv_BindImageMemory(
5165 VkDeviceMemory memory
,
5166 VkDeviceSize memoryOffset
)
5168 const VkBindImageMemoryInfo info
= {
5169 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO
,
5172 .memoryOffset
= memoryOffset
5175 return radv_BindImageMemory2(device
, 1, &info
);
5178 static bool radv_sparse_bind_has_effects(const VkBindSparseInfo
*info
)
5180 return info
->bufferBindCount
||
5181 info
->imageOpaqueBindCount
||
5182 info
->imageBindCount
||
5183 info
->waitSemaphoreCount
||
5184 info
->signalSemaphoreCount
;
5187 VkResult
radv_QueueBindSparse(
5189 uint32_t bindInfoCount
,
5190 const VkBindSparseInfo
* pBindInfo
,
5193 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
5195 uint32_t fence_idx
= 0;
5197 if (fence
!= VK_NULL_HANDLE
) {
5198 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
)
5199 if (radv_sparse_bind_has_effects(pBindInfo
+ i
))
5202 fence_idx
= UINT32_MAX
;
5204 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
5205 if (i
!= fence_idx
&& !radv_sparse_bind_has_effects(pBindInfo
+ i
))
5208 const VkTimelineSemaphoreSubmitInfo
*timeline_info
=
5209 vk_find_struct_const(pBindInfo
[i
].pNext
, TIMELINE_SEMAPHORE_SUBMIT_INFO
);
5211 VkResult result
= radv_queue_submit(queue
, &(struct radv_queue_submission
) {
5212 .buffer_binds
= pBindInfo
[i
].pBufferBinds
,
5213 .buffer_bind_count
= pBindInfo
[i
].bufferBindCount
,
5214 .image_opaque_binds
= pBindInfo
[i
].pImageOpaqueBinds
,
5215 .image_opaque_bind_count
= pBindInfo
[i
].imageOpaqueBindCount
,
5216 .wait_semaphores
= pBindInfo
[i
].pWaitSemaphores
,
5217 .wait_semaphore_count
= pBindInfo
[i
].waitSemaphoreCount
,
5218 .signal_semaphores
= pBindInfo
[i
].pSignalSemaphores
,
5219 .signal_semaphore_count
= pBindInfo
[i
].signalSemaphoreCount
,
5220 .fence
= i
== fence_idx
? fence
: VK_NULL_HANDLE
,
5221 .wait_values
= timeline_info
? timeline_info
->pWaitSemaphoreValues
: NULL
,
5222 .wait_value_count
= timeline_info
&& timeline_info
->pWaitSemaphoreValues
? timeline_info
->waitSemaphoreValueCount
: 0,
5223 .signal_values
= timeline_info
? timeline_info
->pSignalSemaphoreValues
: NULL
,
5224 .signal_value_count
= timeline_info
&& timeline_info
->pSignalSemaphoreValues
? timeline_info
->signalSemaphoreValueCount
: 0,
5227 if (result
!= VK_SUCCESS
)
5231 if (fence
!= VK_NULL_HANDLE
&& !bindInfoCount
) {
5232 result
= radv_signal_fence(queue
, fence
);
5233 if (result
!= VK_SUCCESS
)
5241 radv_destroy_fence_part(struct radv_device
*device
,
5242 struct radv_fence_part
*part
)
5244 switch (part
->kind
) {
5245 case RADV_FENCE_NONE
:
5247 case RADV_FENCE_WINSYS
:
5248 device
->ws
->destroy_fence(part
->fence
);
5250 case RADV_FENCE_SYNCOBJ
:
5251 device
->ws
->destroy_syncobj(device
->ws
, part
->syncobj
);
5253 case RADV_FENCE_WSI
:
5254 part
->fence_wsi
->destroy(part
->fence_wsi
);
5257 unreachable("Invalid fence type");
5260 part
->kind
= RADV_FENCE_NONE
;
5264 radv_destroy_fence(struct radv_device
*device
,
5265 const VkAllocationCallbacks
*pAllocator
,
5266 struct radv_fence
*fence
)
5268 radv_destroy_fence_part(device
, &fence
->temporary
);
5269 radv_destroy_fence_part(device
, &fence
->permanent
);
5271 vk_object_base_finish(&fence
->base
);
5272 vk_free2(&device
->vk
.alloc
, pAllocator
, fence
);
5275 VkResult
radv_CreateFence(
5277 const VkFenceCreateInfo
* pCreateInfo
,
5278 const VkAllocationCallbacks
* pAllocator
,
5281 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5282 const VkExportFenceCreateInfo
*export
=
5283 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_FENCE_CREATE_INFO
);
5284 VkExternalFenceHandleTypeFlags handleTypes
=
5285 export
? export
->handleTypes
: 0;
5286 struct radv_fence
*fence
;
5288 fence
= vk_zalloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*fence
), 8,
5289 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5291 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5293 vk_object_base_init(&device
->vk
, &fence
->base
, VK_OBJECT_TYPE_FENCE
);
5295 if (device
->always_use_syncobj
|| handleTypes
) {
5296 fence
->permanent
.kind
= RADV_FENCE_SYNCOBJ
;
5298 bool create_signaled
= false;
5299 if (pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
)
5300 create_signaled
= true;
5302 int ret
= device
->ws
->create_syncobj(device
->ws
, create_signaled
,
5303 &fence
->permanent
.syncobj
);
5305 radv_destroy_fence(device
, pAllocator
, fence
);
5306 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5309 fence
->permanent
.kind
= RADV_FENCE_WINSYS
;
5311 fence
->permanent
.fence
= device
->ws
->create_fence();
5312 if (!fence
->permanent
.fence
) {
5313 vk_free2(&device
->vk
.alloc
, pAllocator
, fence
);
5314 radv_destroy_fence(device
, pAllocator
, fence
);
5315 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5317 if (pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
)
5318 device
->ws
->signal_fence(fence
->permanent
.fence
);
5321 *pFence
= radv_fence_to_handle(fence
);
5327 void radv_DestroyFence(
5330 const VkAllocationCallbacks
* pAllocator
)
5332 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5333 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
5338 radv_destroy_fence(device
, pAllocator
, fence
);
5342 uint64_t radv_get_current_time(void)
5345 clock_gettime(CLOCK_MONOTONIC
, &tv
);
5346 return tv
.tv_nsec
+ tv
.tv_sec
*1000000000ull;
5349 static uint64_t radv_get_absolute_timeout(uint64_t timeout
)
5351 uint64_t current_time
= radv_get_current_time();
5353 timeout
= MIN2(UINT64_MAX
- current_time
, timeout
);
5355 return current_time
+ timeout
;
5359 static bool radv_all_fences_plain_and_submitted(struct radv_device
*device
,
5360 uint32_t fenceCount
, const VkFence
*pFences
)
5362 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5363 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5365 struct radv_fence_part
*part
=
5366 fence
->temporary
.kind
!= RADV_FENCE_NONE
?
5367 &fence
->temporary
: &fence
->permanent
;
5368 if (part
->kind
!= RADV_FENCE_WINSYS
||
5369 !device
->ws
->is_fence_waitable(part
->fence
))
5375 static bool radv_all_fences_syncobj(uint32_t fenceCount
, const VkFence
*pFences
)
5377 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5378 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5380 struct radv_fence_part
*part
=
5381 fence
->temporary
.kind
!= RADV_FENCE_NONE
?
5382 &fence
->temporary
: &fence
->permanent
;
5383 if (part
->kind
!= RADV_FENCE_SYNCOBJ
)
5389 VkResult
radv_WaitForFences(
5391 uint32_t fenceCount
,
5392 const VkFence
* pFences
,
5396 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5397 timeout
= radv_get_absolute_timeout(timeout
);
5399 if (device
->always_use_syncobj
&&
5400 radv_all_fences_syncobj(fenceCount
, pFences
))
5402 uint32_t *handles
= malloc(sizeof(uint32_t) * fenceCount
);
5404 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5406 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5407 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5409 struct radv_fence_part
*part
=
5410 fence
->temporary
.kind
!= RADV_FENCE_NONE
?
5411 &fence
->temporary
: &fence
->permanent
;
5413 assert(part
->kind
== RADV_FENCE_SYNCOBJ
);
5414 handles
[i
] = part
->syncobj
;
5417 bool success
= device
->ws
->wait_syncobj(device
->ws
, handles
, fenceCount
, waitAll
, timeout
);
5420 return success
? VK_SUCCESS
: VK_TIMEOUT
;
5423 if (!waitAll
&& fenceCount
> 1) {
5424 /* Not doing this by default for waitAll, due to needing to allocate twice. */
5425 if (device
->physical_device
->rad_info
.drm_minor
>= 10 && radv_all_fences_plain_and_submitted(device
, fenceCount
, pFences
)) {
5426 uint32_t wait_count
= 0;
5427 struct radeon_winsys_fence
**fences
= malloc(sizeof(struct radeon_winsys_fence
*) * fenceCount
);
5429 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5431 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5432 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5434 struct radv_fence_part
*part
=
5435 fence
->temporary
.kind
!= RADV_FENCE_NONE
?
5436 &fence
->temporary
: &fence
->permanent
;
5437 assert(part
->kind
== RADV_FENCE_WINSYS
);
5439 if (device
->ws
->fence_wait(device
->ws
, part
->fence
, false, 0)) {
5444 fences
[wait_count
++] = part
->fence
;
5447 bool success
= device
->ws
->fences_wait(device
->ws
, fences
, wait_count
,
5448 waitAll
, timeout
- radv_get_current_time());
5451 return success
? VK_SUCCESS
: VK_TIMEOUT
;
5454 while(radv_get_current_time() <= timeout
) {
5455 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5456 if (radv_GetFenceStatus(_device
, pFences
[i
]) == VK_SUCCESS
)
5463 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5464 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5465 bool expired
= false;
5467 struct radv_fence_part
*part
=
5468 fence
->temporary
.kind
!= RADV_FENCE_NONE
?
5469 &fence
->temporary
: &fence
->permanent
;
5471 switch (part
->kind
) {
5472 case RADV_FENCE_NONE
:
5474 case RADV_FENCE_WINSYS
:
5475 if (!device
->ws
->is_fence_waitable(part
->fence
)) {
5476 while (!device
->ws
->is_fence_waitable(part
->fence
) &&
5477 radv_get_current_time() <= timeout
)
5481 expired
= device
->ws
->fence_wait(device
->ws
,
5487 case RADV_FENCE_SYNCOBJ
:
5488 if (!device
->ws
->wait_syncobj(device
->ws
,
5489 &part
->syncobj
, 1, true,
5493 case RADV_FENCE_WSI
: {
5494 VkResult result
= part
->fence_wsi
->wait(part
->fence_wsi
, timeout
);
5495 if (result
!= VK_SUCCESS
)
5500 unreachable("Invalid fence type");
5507 VkResult
radv_ResetFences(VkDevice _device
,
5508 uint32_t fenceCount
,
5509 const VkFence
*pFences
)
5511 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5513 for (unsigned i
= 0; i
< fenceCount
; ++i
) {
5514 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5516 /* From the Vulkan 1.0.53 spec:
5518 * "If any member of pFences currently has its payload
5519 * imported with temporary permanence, that fence’s prior
5520 * permanent payload is irst restored. The remaining
5521 * operations described therefore operate on the restored
5524 if (fence
->temporary
.kind
!= RADV_FENCE_NONE
)
5525 radv_destroy_fence_part(device
, &fence
->temporary
);
5527 struct radv_fence_part
*part
= &fence
->permanent
;
5529 switch (part
->kind
) {
5530 case RADV_FENCE_WSI
:
5531 device
->ws
->reset_fence(part
->fence
);
5533 case RADV_FENCE_SYNCOBJ
:
5534 device
->ws
->reset_syncobj(device
->ws
, part
->syncobj
);
5537 unreachable("Invalid fence type");
5544 VkResult
radv_GetFenceStatus(VkDevice _device
, VkFence _fence
)
5546 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5547 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
5549 struct radv_fence_part
*part
=
5550 fence
->temporary
.kind
!= RADV_FENCE_NONE
?
5551 &fence
->temporary
: &fence
->permanent
;
5553 switch (part
->kind
) {
5554 case RADV_FENCE_NONE
:
5556 case RADV_FENCE_WINSYS
:
5557 if (!device
->ws
->fence_wait(device
->ws
, part
->fence
, false, 0))
5558 return VK_NOT_READY
;
5560 case RADV_FENCE_SYNCOBJ
: {
5561 bool success
= device
->ws
->wait_syncobj(device
->ws
,
5562 &part
->syncobj
, 1, true, 0);
5564 return VK_NOT_READY
;
5567 case RADV_FENCE_WSI
: {
5568 VkResult result
= part
->fence_wsi
->wait(part
->fence_wsi
, 0);
5569 if (result
!= VK_SUCCESS
) {
5570 if (result
== VK_TIMEOUT
)
5571 return VK_NOT_READY
;
5577 unreachable("Invalid fence type");
5584 // Queue semaphore functions
5587 radv_create_timeline(struct radv_timeline
*timeline
, uint64_t value
)
5589 timeline
->highest_signaled
= value
;
5590 timeline
->highest_submitted
= value
;
5591 list_inithead(&timeline
->points
);
5592 list_inithead(&timeline
->free_points
);
5593 list_inithead(&timeline
->waiters
);
5594 pthread_mutex_init(&timeline
->mutex
, NULL
);
5598 radv_destroy_timeline(struct radv_device
*device
,
5599 struct radv_timeline
*timeline
)
5601 list_for_each_entry_safe(struct radv_timeline_point
, point
,
5602 &timeline
->free_points
, list
) {
5603 list_del(&point
->list
);
5604 device
->ws
->destroy_syncobj(device
->ws
, point
->syncobj
);
5607 list_for_each_entry_safe(struct radv_timeline_point
, point
,
5608 &timeline
->points
, list
) {
5609 list_del(&point
->list
);
5610 device
->ws
->destroy_syncobj(device
->ws
, point
->syncobj
);
5613 pthread_mutex_destroy(&timeline
->mutex
);
5617 radv_timeline_gc_locked(struct radv_device
*device
,
5618 struct radv_timeline
*timeline
)
5620 list_for_each_entry_safe(struct radv_timeline_point
, point
,
5621 &timeline
->points
, list
) {
5622 if (point
->wait_count
|| point
->value
> timeline
->highest_submitted
)
5625 if (device
->ws
->wait_syncobj(device
->ws
, &point
->syncobj
, 1, true, 0)) {
5626 timeline
->highest_signaled
= point
->value
;
5627 list_del(&point
->list
);
5628 list_add(&point
->list
, &timeline
->free_points
);
5633 static struct radv_timeline_point
*
5634 radv_timeline_find_point_at_least_locked(struct radv_device
*device
,
5635 struct radv_timeline
*timeline
,
5638 radv_timeline_gc_locked(device
, timeline
);
5640 if (p
<= timeline
->highest_signaled
)
5643 list_for_each_entry(struct radv_timeline_point
, point
,
5644 &timeline
->points
, list
) {
5645 if (point
->value
>= p
) {
5646 ++point
->wait_count
;
5653 static struct radv_timeline_point
*
5654 radv_timeline_add_point_locked(struct radv_device
*device
,
5655 struct radv_timeline
*timeline
,
5658 radv_timeline_gc_locked(device
, timeline
);
5660 struct radv_timeline_point
*ret
= NULL
;
5661 struct radv_timeline_point
*prev
= NULL
;
5664 if (p
<= timeline
->highest_signaled
)
5667 list_for_each_entry(struct radv_timeline_point
, point
,
5668 &timeline
->points
, list
) {
5669 if (point
->value
== p
) {
5673 if (point
->value
< p
)
5677 if (list_is_empty(&timeline
->free_points
)) {
5678 ret
= malloc(sizeof(struct radv_timeline_point
));
5679 r
= device
->ws
->create_syncobj(device
->ws
, false, &ret
->syncobj
);
5685 ret
= list_first_entry(&timeline
->free_points
, struct radv_timeline_point
, list
);
5686 list_del(&ret
->list
);
5688 device
->ws
->reset_syncobj(device
->ws
, ret
->syncobj
);
5692 ret
->wait_count
= 1;
5695 list_add(&ret
->list
, &prev
->list
);
5697 list_addtail(&ret
->list
, &timeline
->points
);
5704 radv_timeline_wait_locked(struct radv_device
*device
,
5705 struct radv_timeline
*timeline
,
5707 uint64_t abs_timeout
)
5709 while(timeline
->highest_submitted
< value
) {
5710 struct timespec abstime
;
5711 timespec_from_nsec(&abstime
, abs_timeout
);
5713 pthread_cond_timedwait(&device
->timeline_cond
, &timeline
->mutex
, &abstime
);
5715 if (radv_get_current_time() >= abs_timeout
&& timeline
->highest_submitted
< value
)
5719 struct radv_timeline_point
*point
= radv_timeline_find_point_at_least_locked(device
, timeline
, value
);
5723 pthread_mutex_unlock(&timeline
->mutex
);
5725 bool success
= device
->ws
->wait_syncobj(device
->ws
, &point
->syncobj
, 1, true, abs_timeout
);
5727 pthread_mutex_lock(&timeline
->mutex
);
5728 point
->wait_count
--;
5729 return success
? VK_SUCCESS
: VK_TIMEOUT
;
5733 radv_timeline_trigger_waiters_locked(struct radv_timeline
*timeline
,
5734 struct list_head
*processing_list
)
5736 list_for_each_entry_safe(struct radv_timeline_waiter
, waiter
,
5737 &timeline
->waiters
, list
) {
5738 if (waiter
->value
> timeline
->highest_submitted
)
5741 if (p_atomic_dec_zero(&waiter
->submission
->submission_wait_count
)) {
5742 list_addtail(&waiter
->submission
->processing_list
, processing_list
);
5744 list_del(&waiter
->list
);
5749 void radv_destroy_semaphore_part(struct radv_device
*device
,
5750 struct radv_semaphore_part
*part
)
5752 switch(part
->kind
) {
5753 case RADV_SEMAPHORE_NONE
:
5755 case RADV_SEMAPHORE_WINSYS
:
5756 device
->ws
->destroy_sem(part
->ws_sem
);
5758 case RADV_SEMAPHORE_TIMELINE
:
5759 radv_destroy_timeline(device
, &part
->timeline
);
5761 case RADV_SEMAPHORE_SYNCOBJ
:
5762 device
->ws
->destroy_syncobj(device
->ws
, part
->syncobj
);
5765 part
->kind
= RADV_SEMAPHORE_NONE
;
5768 static VkSemaphoreTypeKHR
5769 radv_get_semaphore_type(const void *pNext
, uint64_t *initial_value
)
5771 const VkSemaphoreTypeCreateInfo
*type_info
=
5772 vk_find_struct_const(pNext
, SEMAPHORE_TYPE_CREATE_INFO
);
5775 return VK_SEMAPHORE_TYPE_BINARY
;
5778 *initial_value
= type_info
->initialValue
;
5779 return type_info
->semaphoreType
;
5783 radv_destroy_semaphore(struct radv_device
*device
,
5784 const VkAllocationCallbacks
*pAllocator
,
5785 struct radv_semaphore
*sem
)
5787 radv_destroy_semaphore_part(device
, &sem
->temporary
);
5788 radv_destroy_semaphore_part(device
, &sem
->permanent
);
5789 vk_object_base_finish(&sem
->base
);
5790 vk_free2(&device
->vk
.alloc
, pAllocator
, sem
);
5793 VkResult
radv_CreateSemaphore(
5795 const VkSemaphoreCreateInfo
* pCreateInfo
,
5796 const VkAllocationCallbacks
* pAllocator
,
5797 VkSemaphore
* pSemaphore
)
5799 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5800 const VkExportSemaphoreCreateInfo
*export
=
5801 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_SEMAPHORE_CREATE_INFO
);
5802 VkExternalSemaphoreHandleTypeFlags handleTypes
=
5803 export
? export
->handleTypes
: 0;
5804 uint64_t initial_value
= 0;
5805 VkSemaphoreTypeKHR type
= radv_get_semaphore_type(pCreateInfo
->pNext
, &initial_value
);
5807 struct radv_semaphore
*sem
= vk_alloc2(&device
->vk
.alloc
, pAllocator
,
5809 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5811 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5813 vk_object_base_init(&device
->vk
, &sem
->base
,
5814 VK_OBJECT_TYPE_SEMAPHORE
);
5816 sem
->temporary
.kind
= RADV_SEMAPHORE_NONE
;
5817 sem
->permanent
.kind
= RADV_SEMAPHORE_NONE
;
5819 if (type
== VK_SEMAPHORE_TYPE_TIMELINE
) {
5820 radv_create_timeline(&sem
->permanent
.timeline
, initial_value
);
5821 sem
->permanent
.kind
= RADV_SEMAPHORE_TIMELINE
;
5822 } else if (device
->always_use_syncobj
|| handleTypes
) {
5823 assert (device
->physical_device
->rad_info
.has_syncobj
);
5824 int ret
= device
->ws
->create_syncobj(device
->ws
, false,
5825 &sem
->permanent
.syncobj
);
5827 radv_destroy_semaphore(device
, pAllocator
, sem
);
5828 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5830 sem
->permanent
.kind
= RADV_SEMAPHORE_SYNCOBJ
;
5832 sem
->permanent
.ws_sem
= device
->ws
->create_sem(device
->ws
);
5833 if (!sem
->permanent
.ws_sem
) {
5834 radv_destroy_semaphore(device
, pAllocator
, sem
);
5835 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5837 sem
->permanent
.kind
= RADV_SEMAPHORE_WINSYS
;
5840 *pSemaphore
= radv_semaphore_to_handle(sem
);
5844 void radv_DestroySemaphore(
5846 VkSemaphore _semaphore
,
5847 const VkAllocationCallbacks
* pAllocator
)
5849 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5850 RADV_FROM_HANDLE(radv_semaphore
, sem
, _semaphore
);
5854 radv_destroy_semaphore(device
, pAllocator
, sem
);
5858 radv_GetSemaphoreCounterValue(VkDevice _device
,
5859 VkSemaphore _semaphore
,
5862 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5863 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, _semaphore
);
5865 struct radv_semaphore_part
*part
=
5866 semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
? &semaphore
->temporary
: &semaphore
->permanent
;
5868 switch (part
->kind
) {
5869 case RADV_SEMAPHORE_TIMELINE
: {
5870 pthread_mutex_lock(&part
->timeline
.mutex
);
5871 radv_timeline_gc_locked(device
, &part
->timeline
);
5872 *pValue
= part
->timeline
.highest_signaled
;
5873 pthread_mutex_unlock(&part
->timeline
.mutex
);
5876 case RADV_SEMAPHORE_NONE
:
5877 case RADV_SEMAPHORE_SYNCOBJ
:
5878 case RADV_SEMAPHORE_WINSYS
:
5879 unreachable("Invalid semaphore type");
5881 unreachable("Unhandled semaphore type");
5886 radv_wait_timelines(struct radv_device
*device
,
5887 const VkSemaphoreWaitInfo
* pWaitInfo
,
5888 uint64_t abs_timeout
)
5890 if ((pWaitInfo
->flags
& VK_SEMAPHORE_WAIT_ANY_BIT_KHR
) && pWaitInfo
->semaphoreCount
> 1) {
5892 for(uint32_t i
= 0; i
< pWaitInfo
->semaphoreCount
; ++i
) {
5893 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, pWaitInfo
->pSemaphores
[i
]);
5894 pthread_mutex_lock(&semaphore
->permanent
.timeline
.mutex
);
5895 VkResult result
= radv_timeline_wait_locked(device
, &semaphore
->permanent
.timeline
, pWaitInfo
->pValues
[i
], 0);
5896 pthread_mutex_unlock(&semaphore
->permanent
.timeline
.mutex
);
5898 if (result
== VK_SUCCESS
)
5901 if (radv_get_current_time() > abs_timeout
)
5906 for(uint32_t i
= 0; i
< pWaitInfo
->semaphoreCount
; ++i
) {
5907 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, pWaitInfo
->pSemaphores
[i
]);
5908 pthread_mutex_lock(&semaphore
->permanent
.timeline
.mutex
);
5909 VkResult result
= radv_timeline_wait_locked(device
, &semaphore
->permanent
.timeline
, pWaitInfo
->pValues
[i
], abs_timeout
);
5910 pthread_mutex_unlock(&semaphore
->permanent
.timeline
.mutex
);
5912 if (result
!= VK_SUCCESS
)
5918 radv_WaitSemaphores(VkDevice _device
,
5919 const VkSemaphoreWaitInfo
* pWaitInfo
,
5922 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5923 uint64_t abs_timeout
= radv_get_absolute_timeout(timeout
);
5924 return radv_wait_timelines(device
, pWaitInfo
, abs_timeout
);
5928 radv_SignalSemaphore(VkDevice _device
,
5929 const VkSemaphoreSignalInfo
* pSignalInfo
)
5931 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5932 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, pSignalInfo
->semaphore
);
5934 struct radv_semaphore_part
*part
=
5935 semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
? &semaphore
->temporary
: &semaphore
->permanent
;
5937 switch(part
->kind
) {
5938 case RADV_SEMAPHORE_TIMELINE
: {
5939 pthread_mutex_lock(&part
->timeline
.mutex
);
5940 radv_timeline_gc_locked(device
, &part
->timeline
);
5941 part
->timeline
.highest_submitted
= MAX2(part
->timeline
.highest_submitted
, pSignalInfo
->value
);
5942 part
->timeline
.highest_signaled
= MAX2(part
->timeline
.highest_signaled
, pSignalInfo
->value
);
5944 struct list_head processing_list
;
5945 list_inithead(&processing_list
);
5946 radv_timeline_trigger_waiters_locked(&part
->timeline
, &processing_list
);
5947 pthread_mutex_unlock(&part
->timeline
.mutex
);
5949 return radv_process_submissions(&processing_list
);
5951 case RADV_SEMAPHORE_NONE
:
5952 case RADV_SEMAPHORE_SYNCOBJ
:
5953 case RADV_SEMAPHORE_WINSYS
:
5954 unreachable("Invalid semaphore type");
5959 static void radv_destroy_event(struct radv_device
*device
,
5960 const VkAllocationCallbacks
* pAllocator
,
5961 struct radv_event
*event
)
5964 device
->ws
->buffer_destroy(event
->bo
);
5966 vk_object_base_finish(&event
->base
);
5967 vk_free2(&device
->vk
.alloc
, pAllocator
, event
);
5970 VkResult
radv_CreateEvent(
5972 const VkEventCreateInfo
* pCreateInfo
,
5973 const VkAllocationCallbacks
* pAllocator
,
5976 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5977 struct radv_event
*event
= vk_alloc2(&device
->vk
.alloc
, pAllocator
,
5979 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5982 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5984 vk_object_base_init(&device
->vk
, &event
->base
, VK_OBJECT_TYPE_EVENT
);
5986 event
->bo
= device
->ws
->buffer_create(device
->ws
, 8, 8,
5988 RADEON_FLAG_VA_UNCACHED
| RADEON_FLAG_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
,
5989 RADV_BO_PRIORITY_FENCE
);
5991 radv_destroy_event(device
, pAllocator
, event
);
5992 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
5995 event
->map
= (uint64_t*)device
->ws
->buffer_map(event
->bo
);
5997 radv_destroy_event(device
, pAllocator
, event
);
5998 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
6001 *pEvent
= radv_event_to_handle(event
);
6006 void radv_DestroyEvent(
6009 const VkAllocationCallbacks
* pAllocator
)
6011 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6012 RADV_FROM_HANDLE(radv_event
, event
, _event
);
6017 radv_destroy_event(device
, pAllocator
, event
);
6020 VkResult
radv_GetEventStatus(
6024 RADV_FROM_HANDLE(radv_event
, event
, _event
);
6026 if (*event
->map
== 1)
6027 return VK_EVENT_SET
;
6028 return VK_EVENT_RESET
;
6031 VkResult
radv_SetEvent(
6035 RADV_FROM_HANDLE(radv_event
, event
, _event
);
6041 VkResult
radv_ResetEvent(
6045 RADV_FROM_HANDLE(radv_event
, event
, _event
);
6052 radv_destroy_buffer(struct radv_device
*device
,
6053 const VkAllocationCallbacks
*pAllocator
,
6054 struct radv_buffer
*buffer
)
6056 if ((buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
) && buffer
->bo
)
6057 device
->ws
->buffer_destroy(buffer
->bo
);
6059 vk_object_base_finish(&buffer
->base
);
6060 vk_free2(&device
->vk
.alloc
, pAllocator
, buffer
);
6063 VkResult
radv_CreateBuffer(
6065 const VkBufferCreateInfo
* pCreateInfo
,
6066 const VkAllocationCallbacks
* pAllocator
,
6069 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6070 struct radv_buffer
*buffer
;
6072 if (pCreateInfo
->size
> RADV_MAX_MEMORY_ALLOCATION_SIZE
)
6073 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
6075 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO
);
6077 buffer
= vk_alloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*buffer
), 8,
6078 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
6080 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6082 vk_object_base_init(&device
->vk
, &buffer
->base
, VK_OBJECT_TYPE_BUFFER
);
6084 buffer
->size
= pCreateInfo
->size
;
6085 buffer
->usage
= pCreateInfo
->usage
;
6088 buffer
->flags
= pCreateInfo
->flags
;
6090 buffer
->shareable
= vk_find_struct_const(pCreateInfo
->pNext
,
6091 EXTERNAL_MEMORY_BUFFER_CREATE_INFO
) != NULL
;
6093 if (pCreateInfo
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
) {
6094 buffer
->bo
= device
->ws
->buffer_create(device
->ws
,
6095 align64(buffer
->size
, 4096),
6096 4096, 0, RADEON_FLAG_VIRTUAL
,
6097 RADV_BO_PRIORITY_VIRTUAL
);
6099 radv_destroy_buffer(device
, pAllocator
, buffer
);
6100 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
6104 *pBuffer
= radv_buffer_to_handle(buffer
);
6109 void radv_DestroyBuffer(
6112 const VkAllocationCallbacks
* pAllocator
)
6114 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6115 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
6120 radv_destroy_buffer(device
, pAllocator
, buffer
);
6123 VkDeviceAddress
radv_GetBufferDeviceAddress(
6125 const VkBufferDeviceAddressInfo
* pInfo
)
6127 RADV_FROM_HANDLE(radv_buffer
, buffer
, pInfo
->buffer
);
6128 return radv_buffer_get_va(buffer
->bo
) + buffer
->offset
;
6132 uint64_t radv_GetBufferOpaqueCaptureAddress(VkDevice device
,
6133 const VkBufferDeviceAddressInfo
* pInfo
)
6138 uint64_t radv_GetDeviceMemoryOpaqueCaptureAddress(VkDevice device
,
6139 const VkDeviceMemoryOpaqueCaptureAddressInfo
* pInfo
)
6144 static inline unsigned
6145 si_tile_mode_index(const struct radv_image_plane
*plane
, unsigned level
, bool stencil
)
6148 return plane
->surface
.u
.legacy
.stencil_tiling_index
[level
];
6150 return plane
->surface
.u
.legacy
.tiling_index
[level
];
6153 static uint32_t radv_surface_max_layer_count(struct radv_image_view
*iview
)
6155 return iview
->type
== VK_IMAGE_VIEW_TYPE_3D
? iview
->extent
.depth
: (iview
->base_layer
+ iview
->layer_count
);
6159 radv_init_dcc_control_reg(struct radv_device
*device
,
6160 struct radv_image_view
*iview
)
6162 unsigned max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_256B
;
6163 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
6164 unsigned max_compressed_block_size
;
6165 unsigned independent_128b_blocks
;
6166 unsigned independent_64b_blocks
;
6168 if (!radv_dcc_enabled(iview
->image
, iview
->base_mip
))
6171 if (!device
->physical_device
->rad_info
.has_dedicated_vram
) {
6172 /* amdvlk: [min-compressed-block-size] should be set to 32 for
6173 * dGPU and 64 for APU because all of our APUs to date use
6174 * DIMMs which have a request granularity size of 64B while all
6175 * other chips have a 32B request size.
6177 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
6180 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6181 max_compressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
6182 independent_64b_blocks
= 0;
6183 independent_128b_blocks
= 1;
6185 independent_128b_blocks
= 0;
6187 if (iview
->image
->info
.samples
> 1) {
6188 if (iview
->image
->planes
[0].surface
.bpe
== 1)
6189 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
6190 else if (iview
->image
->planes
[0].surface
.bpe
== 2)
6191 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
6194 if (iview
->image
->usage
& (VK_IMAGE_USAGE_SAMPLED_BIT
|
6195 VK_IMAGE_USAGE_TRANSFER_SRC_BIT
|
6196 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
)) {
6197 /* If this DCC image is potentially going to be used in texture
6198 * fetches, we need some special settings.
6200 independent_64b_blocks
= 1;
6201 max_compressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
6203 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
6204 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
6205 * big as possible for better compression state.
6207 independent_64b_blocks
= 0;
6208 max_compressed_block_size
= max_uncompressed_block_size
;
6212 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
6213 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size
) |
6214 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
6215 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks
) |
6216 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks
);
6220 radv_initialise_color_surface(struct radv_device
*device
,
6221 struct radv_color_buffer_info
*cb
,
6222 struct radv_image_view
*iview
)
6224 const struct vk_format_description
*desc
;
6225 unsigned ntype
, format
, swap
, endian
;
6226 unsigned blend_clamp
= 0, blend_bypass
= 0;
6228 const struct radv_image_plane
*plane
= &iview
->image
->planes
[iview
->plane_id
];
6229 const struct radeon_surf
*surf
= &plane
->surface
;
6231 desc
= vk_format_description(iview
->vk_format
);
6233 memset(cb
, 0, sizeof(*cb
));
6235 /* Intensity is implemented as Red, so treat it that way. */
6236 cb
->cb_color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == VK_SWIZZLE_1
);
6238 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+ plane
->offset
;
6240 cb
->cb_color_base
= va
>> 8;
6242 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
6243 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6244 cb
->cb_color_attrib3
|= S_028EE0_COLOR_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
6245 S_028EE0_FMASK_SW_MODE(surf
->u
.gfx9
.fmask
.swizzle_mode
) |
6246 S_028EE0_CMASK_PIPE_ALIGNED(1) |
6247 S_028EE0_DCC_PIPE_ALIGNED(surf
->u
.gfx9
.dcc
.pipe_aligned
);
6249 struct gfx9_surf_meta_flags meta
= {
6254 if (surf
->dcc_offset
)
6255 meta
= surf
->u
.gfx9
.dcc
;
6257 cb
->cb_color_attrib
|= S_028C74_COLOR_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
6258 S_028C74_FMASK_SW_MODE(surf
->u
.gfx9
.fmask
.swizzle_mode
) |
6259 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
6260 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
6261 cb
->cb_mrt_epitch
= S_0287A0_EPITCH(surf
->u
.gfx9
.surf
.epitch
);
6264 cb
->cb_color_base
+= surf
->u
.gfx9
.surf_offset
>> 8;
6265 cb
->cb_color_base
|= surf
->tile_swizzle
;
6267 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[iview
->base_mip
];
6268 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
6270 cb
->cb_color_base
+= level_info
->offset
>> 8;
6271 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
6272 cb
->cb_color_base
|= surf
->tile_swizzle
;
6274 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
6275 slice_tile_max
= (level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1;
6276 tile_mode_index
= si_tile_mode_index(plane
, iview
->base_mip
, false);
6278 cb
->cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
6279 cb
->cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
6280 cb
->cb_color_cmask_slice
= surf
->u
.legacy
.cmask_slice_tile_max
;
6282 cb
->cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
6284 if (radv_image_has_fmask(iview
->image
)) {
6285 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
6286 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(surf
->u
.legacy
.fmask
.pitch_in_pixels
/ 8 - 1);
6287 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(surf
->u
.legacy
.fmask
.tiling_index
);
6288 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(surf
->u
.legacy
.fmask
.slice_tile_max
);
6290 /* This must be set for fast clear to work without FMASK. */
6291 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
6292 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
6293 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
6294 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
6298 /* CMASK variables */
6299 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
6300 va
+= surf
->cmask_offset
;
6301 cb
->cb_color_cmask
= va
>> 8;
6303 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
6304 va
+= surf
->dcc_offset
;
6306 if (radv_dcc_enabled(iview
->image
, iview
->base_mip
) &&
6307 device
->physical_device
->rad_info
.chip_class
<= GFX8
)
6308 va
+= plane
->surface
.u
.legacy
.level
[iview
->base_mip
].dcc_offset
;
6310 unsigned dcc_tile_swizzle
= surf
->tile_swizzle
;
6311 dcc_tile_swizzle
&= (surf
->dcc_alignment
- 1) >> 8;
6313 cb
->cb_dcc_base
= va
>> 8;
6314 cb
->cb_dcc_base
|= dcc_tile_swizzle
;
6316 /* GFX10 field has the same base shift as the GFX6 field. */
6317 uint32_t max_slice
= radv_surface_max_layer_count(iview
) - 1;
6318 cb
->cb_color_view
= S_028C6C_SLICE_START(iview
->base_layer
) |
6319 S_028C6C_SLICE_MAX_GFX10(max_slice
);
6321 if (iview
->image
->info
.samples
> 1) {
6322 unsigned log_samples
= util_logbase2(iview
->image
->info
.samples
);
6324 cb
->cb_color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
6325 S_028C74_NUM_FRAGMENTS(log_samples
);
6328 if (radv_image_has_fmask(iview
->image
)) {
6329 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+ surf
->fmask_offset
;
6330 cb
->cb_color_fmask
= va
>> 8;
6331 cb
->cb_color_fmask
|= surf
->fmask_tile_swizzle
;
6333 cb
->cb_color_fmask
= cb
->cb_color_base
;
6336 ntype
= radv_translate_color_numformat(iview
->vk_format
,
6338 vk_format_get_first_non_void_channel(iview
->vk_format
));
6339 format
= radv_translate_colorformat(iview
->vk_format
);
6340 if (format
== V_028C70_COLOR_INVALID
|| ntype
== ~0u)
6341 radv_finishme("Illegal color\n");
6342 swap
= radv_translate_colorswap(iview
->vk_format
, false);
6343 endian
= radv_colorformat_endian_swap(format
);
6345 /* blend clamp should be set for all NORM/SRGB types */
6346 if (ntype
== V_028C70_NUMBER_UNORM
||
6347 ntype
== V_028C70_NUMBER_SNORM
||
6348 ntype
== V_028C70_NUMBER_SRGB
)
6351 /* set blend bypass according to docs if SINT/UINT or
6352 8/24 COLOR variants */
6353 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
6354 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
6355 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
6360 if ((ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) &&
6361 (format
== V_028C70_COLOR_8
||
6362 format
== V_028C70_COLOR_8_8
||
6363 format
== V_028C70_COLOR_8_8_8_8
))
6364 ->color_is_int8
= true;
6366 cb
->cb_color_info
= S_028C70_FORMAT(format
) |
6367 S_028C70_COMP_SWAP(swap
) |
6368 S_028C70_BLEND_CLAMP(blend_clamp
) |
6369 S_028C70_BLEND_BYPASS(blend_bypass
) |
6370 S_028C70_SIMPLE_FLOAT(1) |
6371 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
6372 ntype
!= V_028C70_NUMBER_SNORM
&&
6373 ntype
!= V_028C70_NUMBER_SRGB
&&
6374 format
!= V_028C70_COLOR_8_24
&&
6375 format
!= V_028C70_COLOR_24_8
) |
6376 S_028C70_NUMBER_TYPE(ntype
) |
6377 S_028C70_ENDIAN(endian
);
6378 if (radv_image_has_fmask(iview
->image
)) {
6379 cb
->cb_color_info
|= S_028C70_COMPRESSION(1);
6380 if (device
->physical_device
->rad_info
.chip_class
== GFX6
) {
6381 unsigned fmask_bankh
= util_logbase2(surf
->u
.legacy
.fmask
.bankh
);
6382 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
6385 if (radv_image_is_tc_compat_cmask(iview
->image
)) {
6386 /* Allow the texture block to read FMASK directly
6387 * without decompressing it. This bit must be cleared
6388 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
6389 * otherwise the operation doesn't happen.
6391 cb
->cb_color_info
|= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
6393 /* Set CMASK into a tiling format that allows the
6394 * texture block to read it.
6396 cb
->cb_color_info
|= S_028C70_CMASK_ADDR_TYPE(2);
6400 if (radv_image_has_cmask(iview
->image
) &&
6401 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_FAST_CLEARS
))
6402 cb
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
6404 if (radv_dcc_enabled(iview
->image
, iview
->base_mip
))
6405 cb
->cb_color_info
|= S_028C70_DCC_ENABLE(1);
6407 cb
->cb_dcc_control
= radv_init_dcc_control_reg(device
, iview
);
6409 /* This must be set for fast clear to work without FMASK. */
6410 if (!radv_image_has_fmask(iview
->image
) &&
6411 device
->physical_device
->rad_info
.chip_class
== GFX6
) {
6412 unsigned bankh
= util_logbase2(surf
->u
.legacy
.bankh
);
6413 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
6416 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
6417 const struct vk_format_description
*format_desc
= vk_format_description(iview
->image
->vk_format
);
6419 unsigned mip0_depth
= iview
->image
->type
== VK_IMAGE_TYPE_3D
?
6420 (iview
->extent
.depth
- 1) : (iview
->image
->info
.array_size
- 1);
6421 unsigned width
= iview
->extent
.width
/ (iview
->plane_id
? format_desc
->width_divisor
: 1);
6422 unsigned height
= iview
->extent
.height
/ (iview
->plane_id
? format_desc
->height_divisor
: 1);
6424 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6425 cb
->cb_color_view
|= S_028C6C_MIP_LEVEL_GFX10(iview
->base_mip
);
6427 cb
->cb_color_attrib3
|= S_028EE0_MIP0_DEPTH(mip0_depth
) |
6428 S_028EE0_RESOURCE_TYPE(surf
->u
.gfx9
.resource_type
) |
6429 S_028EE0_RESOURCE_LEVEL(1);
6431 cb
->cb_color_view
|= S_028C6C_MIP_LEVEL_GFX9(iview
->base_mip
);
6432 cb
->cb_color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
6433 S_028C74_RESOURCE_TYPE(surf
->u
.gfx9
.resource_type
);
6436 cb
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(width
- 1) |
6437 S_028C68_MIP0_HEIGHT(height
- 1) |
6438 S_028C68_MAX_MIP(iview
->image
->info
.levels
- 1);
6443 radv_calc_decompress_on_z_planes(struct radv_device
*device
,
6444 struct radv_image_view
*iview
)
6446 unsigned max_zplanes
= 0;
6448 assert(radv_image_is_tc_compat_htile(iview
->image
));
6450 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
6451 /* Default value for 32-bit depth surfaces. */
6454 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
&&
6455 iview
->image
->info
.samples
> 1)
6458 max_zplanes
= max_zplanes
+ 1;
6460 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
) {
6461 /* Do not enable Z plane compression for 16-bit depth
6462 * surfaces because isn't supported on GFX8. Only
6463 * 32-bit depth surfaces are supported by the hardware.
6464 * This allows to maintain shader compatibility and to
6465 * reduce the number of depth decompressions.
6469 if (iview
->image
->info
.samples
<= 1)
6471 else if (iview
->image
->info
.samples
<= 4)
6482 radv_initialise_ds_surface(struct radv_device
*device
,
6483 struct radv_ds_buffer_info
*ds
,
6484 struct radv_image_view
*iview
)
6486 unsigned level
= iview
->base_mip
;
6487 unsigned format
, stencil_format
;
6488 uint64_t va
, s_offs
, z_offs
;
6489 bool stencil_only
= false;
6490 const struct radv_image_plane
*plane
= &iview
->image
->planes
[0];
6491 const struct radeon_surf
*surf
= &plane
->surface
;
6493 assert(vk_format_get_plane_count(iview
->image
->vk_format
) == 1);
6495 memset(ds
, 0, sizeof(*ds
));
6496 switch (iview
->image
->vk_format
) {
6497 case VK_FORMAT_D24_UNORM_S8_UINT
:
6498 case VK_FORMAT_X8_D24_UNORM_PACK32
:
6499 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
6500 ds
->offset_scale
= 2.0f
;
6502 case VK_FORMAT_D16_UNORM
:
6503 case VK_FORMAT_D16_UNORM_S8_UINT
:
6504 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
6505 ds
->offset_scale
= 4.0f
;
6507 case VK_FORMAT_D32_SFLOAT
:
6508 case VK_FORMAT_D32_SFLOAT_S8_UINT
:
6509 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
6510 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
6511 ds
->offset_scale
= 1.0f
;
6513 case VK_FORMAT_S8_UINT
:
6514 stencil_only
= true;
6520 format
= radv_translate_dbformat(iview
->image
->vk_format
);
6521 stencil_format
= surf
->has_stencil
?
6522 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
6524 uint32_t max_slice
= radv_surface_max_layer_count(iview
) - 1;
6525 ds
->db_depth_view
= S_028008_SLICE_START(iview
->base_layer
) |
6526 S_028008_SLICE_MAX(max_slice
);
6527 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6528 ds
->db_depth_view
|= S_028008_SLICE_START_HI(iview
->base_layer
>> 11) |
6529 S_028008_SLICE_MAX_HI(max_slice
>> 11);
6532 ds
->db_htile_data_base
= 0;
6533 ds
->db_htile_surface
= 0;
6535 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
6536 s_offs
= z_offs
= va
;
6538 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
6539 assert(surf
->u
.gfx9
.surf_offset
== 0);
6540 s_offs
+= surf
->u
.gfx9
.stencil_offset
;
6542 ds
->db_z_info
= S_028038_FORMAT(format
) |
6543 S_028038_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
)) |
6544 S_028038_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
6545 S_028038_MAXMIP(iview
->image
->info
.levels
- 1) |
6546 S_028038_ZRANGE_PRECISION(1);
6547 ds
->db_stencil_info
= S_02803C_FORMAT(stencil_format
) |
6548 S_02803C_SW_MODE(surf
->u
.gfx9
.stencil
.swizzle_mode
);
6550 if (device
->physical_device
->rad_info
.chip_class
== GFX9
) {
6551 ds
->db_z_info2
= S_028068_EPITCH(surf
->u
.gfx9
.surf
.epitch
);
6552 ds
->db_stencil_info2
= S_02806C_EPITCH(surf
->u
.gfx9
.stencil
.epitch
);
6555 ds
->db_depth_view
|= S_028008_MIPID(level
);
6556 ds
->db_depth_size
= S_02801C_X_MAX(iview
->image
->info
.width
- 1) |
6557 S_02801C_Y_MAX(iview
->image
->info
.height
- 1);
6559 if (radv_htile_enabled(iview
->image
, level
)) {
6560 ds
->db_z_info
|= S_028038_TILE_SURFACE_ENABLE(1);
6562 if (radv_image_is_tc_compat_htile(iview
->image
)) {
6563 unsigned max_zplanes
=
6564 radv_calc_decompress_on_z_planes(device
, iview
);
6566 ds
->db_z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
);
6568 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6569 ds
->db_z_info
|= S_028040_ITERATE_FLUSH(1);
6570 ds
->db_stencil_info
|= S_028044_ITERATE_FLUSH(1);
6572 ds
->db_z_info
|= S_028038_ITERATE_FLUSH(1);
6573 ds
->db_stencil_info
|= S_02803C_ITERATE_FLUSH(1);
6577 if (!surf
->has_stencil
)
6578 /* Use all of the htile_buffer for depth if there's no stencil. */
6579 ds
->db_stencil_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
6580 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
6582 ds
->db_htile_data_base
= va
>> 8;
6583 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1) |
6584 S_028ABC_PIPE_ALIGNED(1);
6586 if (device
->physical_device
->rad_info
.chip_class
== GFX9
) {
6587 ds
->db_htile_surface
|= S_028ABC_RB_ALIGNED(1);
6591 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[level
];
6594 level_info
= &surf
->u
.legacy
.stencil_level
[level
];
6596 z_offs
+= surf
->u
.legacy
.level
[level
].offset
;
6597 s_offs
+= surf
->u
.legacy
.stencil_level
[level
].offset
;
6599 ds
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview
->image
));
6600 ds
->db_z_info
= S_028040_FORMAT(format
) | S_028040_ZRANGE_PRECISION(1);
6601 ds
->db_stencil_info
= S_028044_FORMAT(stencil_format
);
6603 if (iview
->image
->info
.samples
> 1)
6604 ds
->db_z_info
|= S_028040_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
));
6606 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
6607 struct radeon_info
*info
= &device
->physical_device
->rad_info
;
6608 unsigned tiling_index
= surf
->u
.legacy
.tiling_index
[level
];
6609 unsigned stencil_index
= surf
->u
.legacy
.stencil_tiling_index
[level
];
6610 unsigned macro_index
= surf
->u
.legacy
.macro_tile_index
;
6611 unsigned tile_mode
= info
->si_tile_mode_array
[tiling_index
];
6612 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
6613 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
6616 tile_mode
= stencil_tile_mode
;
6618 ds
->db_depth_info
|=
6619 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
6620 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
6621 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
6622 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
6623 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
6624 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
6625 ds
->db_z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
6626 ds
->db_stencil_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
6628 unsigned tile_mode_index
= si_tile_mode_index(&iview
->image
->planes
[0], level
, false);
6629 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
6630 tile_mode_index
= si_tile_mode_index(&iview
->image
->planes
[0], level
, true);
6631 ds
->db_stencil_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
6633 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
6636 ds
->db_depth_size
= S_028058_PITCH_TILE_MAX((level_info
->nblk_x
/ 8) - 1) |
6637 S_028058_HEIGHT_TILE_MAX((level_info
->nblk_y
/ 8) - 1);
6638 ds
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1);
6640 if (radv_htile_enabled(iview
->image
, level
)) {
6641 ds
->db_z_info
|= S_028040_TILE_SURFACE_ENABLE(1);
6643 if (!surf
->has_stencil
&&
6644 !radv_image_is_tc_compat_htile(iview
->image
))
6645 /* Use all of the htile_buffer for depth if there's no stencil. */
6646 ds
->db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
6648 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
6650 ds
->db_htile_data_base
= va
>> 8;
6651 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
6653 if (radv_image_is_tc_compat_htile(iview
->image
)) {
6654 unsigned max_zplanes
=
6655 radv_calc_decompress_on_z_planes(device
, iview
);
6657 ds
->db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
6658 ds
->db_z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes
);
6663 ds
->db_z_read_base
= ds
->db_z_write_base
= z_offs
>> 8;
6664 ds
->db_stencil_read_base
= ds
->db_stencil_write_base
= s_offs
>> 8;
6667 VkResult
radv_CreateFramebuffer(
6669 const VkFramebufferCreateInfo
* pCreateInfo
,
6670 const VkAllocationCallbacks
* pAllocator
,
6671 VkFramebuffer
* pFramebuffer
)
6673 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6674 struct radv_framebuffer
*framebuffer
;
6675 const VkFramebufferAttachmentsCreateInfo
*imageless_create_info
=
6676 vk_find_struct_const(pCreateInfo
->pNext
,
6677 FRAMEBUFFER_ATTACHMENTS_CREATE_INFO
);
6679 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
);
6681 size_t size
= sizeof(*framebuffer
);
6682 if (!imageless_create_info
)
6683 size
+= sizeof(struct radv_image_view
*) * pCreateInfo
->attachmentCount
;
6684 framebuffer
= vk_alloc2(&device
->vk
.alloc
, pAllocator
, size
, 8,
6685 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
6686 if (framebuffer
== NULL
)
6687 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6689 vk_object_base_init(&device
->vk
, &framebuffer
->base
,
6690 VK_OBJECT_TYPE_FRAMEBUFFER
);
6692 framebuffer
->attachment_count
= pCreateInfo
->attachmentCount
;
6693 framebuffer
->width
= pCreateInfo
->width
;
6694 framebuffer
->height
= pCreateInfo
->height
;
6695 framebuffer
->layers
= pCreateInfo
->layers
;
6696 if (imageless_create_info
) {
6697 for (unsigned i
= 0; i
< imageless_create_info
->attachmentImageInfoCount
; ++i
) {
6698 const VkFramebufferAttachmentImageInfo
*attachment
=
6699 imageless_create_info
->pAttachmentImageInfos
+ i
;
6700 framebuffer
->width
= MIN2(framebuffer
->width
, attachment
->width
);
6701 framebuffer
->height
= MIN2(framebuffer
->height
, attachment
->height
);
6702 framebuffer
->layers
= MIN2(framebuffer
->layers
, attachment
->layerCount
);
6705 for (uint32_t i
= 0; i
< pCreateInfo
->attachmentCount
; i
++) {
6706 VkImageView _iview
= pCreateInfo
->pAttachments
[i
];
6707 struct radv_image_view
*iview
= radv_image_view_from_handle(_iview
);
6708 framebuffer
->attachments
[i
] = iview
;
6709 framebuffer
->width
= MIN2(framebuffer
->width
, iview
->extent
.width
);
6710 framebuffer
->height
= MIN2(framebuffer
->height
, iview
->extent
.height
);
6711 framebuffer
->layers
= MIN2(framebuffer
->layers
, radv_surface_max_layer_count(iview
));
6715 *pFramebuffer
= radv_framebuffer_to_handle(framebuffer
);
6719 void radv_DestroyFramebuffer(
6722 const VkAllocationCallbacks
* pAllocator
)
6724 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6725 RADV_FROM_HANDLE(radv_framebuffer
, fb
, _fb
);
6729 vk_object_base_finish(&fb
->base
);
6730 vk_free2(&device
->vk
.alloc
, pAllocator
, fb
);
6733 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode
)
6735 switch (address_mode
) {
6736 case VK_SAMPLER_ADDRESS_MODE_REPEAT
:
6737 return V_008F30_SQ_TEX_WRAP
;
6738 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT
:
6739 return V_008F30_SQ_TEX_MIRROR
;
6740 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE
:
6741 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
6742 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER
:
6743 return V_008F30_SQ_TEX_CLAMP_BORDER
;
6744 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE
:
6745 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
6747 unreachable("illegal tex wrap mode");
6753 radv_tex_compare(VkCompareOp op
)
6756 case VK_COMPARE_OP_NEVER
:
6757 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
6758 case VK_COMPARE_OP_LESS
:
6759 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
6760 case VK_COMPARE_OP_EQUAL
:
6761 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
6762 case VK_COMPARE_OP_LESS_OR_EQUAL
:
6763 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
6764 case VK_COMPARE_OP_GREATER
:
6765 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
6766 case VK_COMPARE_OP_NOT_EQUAL
:
6767 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
6768 case VK_COMPARE_OP_GREATER_OR_EQUAL
:
6769 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
6770 case VK_COMPARE_OP_ALWAYS
:
6771 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
6773 unreachable("illegal compare mode");
6779 radv_tex_filter(VkFilter filter
, unsigned max_ansio
)
6782 case VK_FILTER_NEAREST
:
6783 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
:
6784 V_008F38_SQ_TEX_XY_FILTER_POINT
);
6785 case VK_FILTER_LINEAR
:
6786 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
:
6787 V_008F38_SQ_TEX_XY_FILTER_BILINEAR
);
6788 case VK_FILTER_CUBIC_IMG
:
6790 fprintf(stderr
, "illegal texture filter");
6796 radv_tex_mipfilter(VkSamplerMipmapMode mode
)
6799 case VK_SAMPLER_MIPMAP_MODE_NEAREST
:
6800 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
6801 case VK_SAMPLER_MIPMAP_MODE_LINEAR
:
6802 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
6804 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
6809 radv_tex_bordercolor(VkBorderColor bcolor
)
6812 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK
:
6813 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK
:
6814 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
6815 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK
:
6816 case VK_BORDER_COLOR_INT_OPAQUE_BLACK
:
6817 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK
;
6818 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE
:
6819 case VK_BORDER_COLOR_INT_OPAQUE_WHITE
:
6820 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE
;
6821 case VK_BORDER_COLOR_FLOAT_CUSTOM_EXT
:
6822 case VK_BORDER_COLOR_INT_CUSTOM_EXT
:
6823 return V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
;
6831 radv_tex_aniso_filter(unsigned filter
)
6845 radv_tex_filter_mode(VkSamplerReductionMode mode
)
6848 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT
:
6849 return V_008F30_SQ_IMG_FILTER_MODE_BLEND
;
6850 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT
:
6851 return V_008F30_SQ_IMG_FILTER_MODE_MIN
;
6852 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT
:
6853 return V_008F30_SQ_IMG_FILTER_MODE_MAX
;
6861 radv_get_max_anisotropy(struct radv_device
*device
,
6862 const VkSamplerCreateInfo
*pCreateInfo
)
6864 if (device
->force_aniso
>= 0)
6865 return device
->force_aniso
;
6867 if (pCreateInfo
->anisotropyEnable
&&
6868 pCreateInfo
->maxAnisotropy
> 1.0f
)
6869 return (uint32_t)pCreateInfo
->maxAnisotropy
;
6874 static inline int S_FIXED(float value
, unsigned frac_bits
)
6876 return value
* (1 << frac_bits
);
6879 static uint32_t radv_register_border_color(struct radv_device
*device
,
6880 VkClearColorValue value
)
6884 pthread_mutex_lock(&device
->border_color_data
.mutex
);
6886 for (slot
= 0; slot
< RADV_BORDER_COLOR_COUNT
; slot
++) {
6887 if (!device
->border_color_data
.used
[slot
]) {
6888 /* Copy to the GPU wrt endian-ness. */
6889 util_memcpy_cpu_to_le32(&device
->border_color_data
.colors_gpu_ptr
[slot
],
6891 sizeof(VkClearColorValue
));
6893 device
->border_color_data
.used
[slot
] = true;
6898 pthread_mutex_unlock(&device
->border_color_data
.mutex
);
6903 static void radv_unregister_border_color(struct radv_device
*device
,
6906 pthread_mutex_lock(&device
->border_color_data
.mutex
);
6908 device
->border_color_data
.used
[slot
] = false;
6910 pthread_mutex_unlock(&device
->border_color_data
.mutex
);
6914 radv_init_sampler(struct radv_device
*device
,
6915 struct radv_sampler
*sampler
,
6916 const VkSamplerCreateInfo
*pCreateInfo
)
6918 uint32_t max_aniso
= radv_get_max_anisotropy(device
, pCreateInfo
);
6919 uint32_t max_aniso_ratio
= radv_tex_aniso_filter(max_aniso
);
6920 bool compat_mode
= device
->physical_device
->rad_info
.chip_class
== GFX8
||
6921 device
->physical_device
->rad_info
.chip_class
== GFX9
;
6922 unsigned filter_mode
= V_008F30_SQ_IMG_FILTER_MODE_BLEND
;
6923 unsigned depth_compare_func
= V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
6924 bool trunc_coord
= pCreateInfo
->minFilter
== VK_FILTER_NEAREST
&& pCreateInfo
->magFilter
== VK_FILTER_NEAREST
;
6925 bool uses_border_color
= pCreateInfo
->addressModeU
== VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER
||
6926 pCreateInfo
->addressModeV
== VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER
||
6927 pCreateInfo
->addressModeW
== VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER
;
6928 VkBorderColor border_color
= uses_border_color
? pCreateInfo
->borderColor
: VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK
;
6929 uint32_t border_color_ptr
;
6931 const struct VkSamplerReductionModeCreateInfo
*sampler_reduction
=
6932 vk_find_struct_const(pCreateInfo
->pNext
,
6933 SAMPLER_REDUCTION_MODE_CREATE_INFO
);
6934 if (sampler_reduction
)
6935 filter_mode
= radv_tex_filter_mode(sampler_reduction
->reductionMode
);
6937 if (pCreateInfo
->compareEnable
)
6938 depth_compare_func
= radv_tex_compare(pCreateInfo
->compareOp
);
6940 sampler
->border_color_slot
= RADV_BORDER_COLOR_COUNT
;
6942 if (border_color
== VK_BORDER_COLOR_FLOAT_CUSTOM_EXT
|| border_color
== VK_BORDER_COLOR_INT_CUSTOM_EXT
) {
6943 const VkSamplerCustomBorderColorCreateInfoEXT
*custom_border_color
=
6944 vk_find_struct_const(pCreateInfo
->pNext
,
6945 SAMPLER_CUSTOM_BORDER_COLOR_CREATE_INFO_EXT
);
6947 assert(custom_border_color
);
6949 sampler
->border_color_slot
=
6950 radv_register_border_color(device
, custom_border_color
->customBorderColor
);
6952 /* Did we fail to find a slot? */
6953 if (sampler
->border_color_slot
== RADV_BORDER_COLOR_COUNT
) {
6954 fprintf(stderr
, "WARNING: no free border color slots, defaulting to TRANS_BLACK.\n");
6955 border_color
= VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK
;
6959 /* If we don't have a custom color, set the ptr to 0 */
6960 border_color_ptr
= sampler
->border_color_slot
!= RADV_BORDER_COLOR_COUNT
6961 ? sampler
->border_color_slot
6964 sampler
->state
[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo
->addressModeU
)) |
6965 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo
->addressModeV
)) |
6966 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo
->addressModeW
)) |
6967 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
6968 S_008F30_DEPTH_COMPARE_FUNC(depth_compare_func
) |
6969 S_008F30_FORCE_UNNORMALIZED(pCreateInfo
->unnormalizedCoordinates
? 1 : 0) |
6970 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
6971 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
6972 S_008F30_DISABLE_CUBE_WRAP(0) |
6973 S_008F30_COMPAT_MODE(compat_mode
) |
6974 S_008F30_FILTER_MODE(filter_mode
) |
6975 S_008F30_TRUNC_COORD(trunc_coord
));
6976 sampler
->state
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo
->minLod
, 0, 15), 8)) |
6977 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo
->maxLod
, 0, 15), 8)) |
6978 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
6979 sampler
->state
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo
->mipLodBias
, -16, 16), 8)) |
6980 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo
->magFilter
, max_aniso
)) |
6981 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo
->minFilter
, max_aniso
)) |
6982 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo
->mipmapMode
)) |
6983 S_008F38_MIP_POINT_PRECLAMP(0));
6984 sampler
->state
[3] = (S_008F3C_BORDER_COLOR_PTR(border_color_ptr
) |
6985 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(border_color
)));
6987 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6988 sampler
->state
[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
6990 sampler
->state
[2] |=
6991 S_008F38_DISABLE_LSB_CEIL(device
->physical_device
->rad_info
.chip_class
<= GFX8
) |
6992 S_008F38_FILTER_PREC_FIX(1) |
6993 S_008F38_ANISO_OVERRIDE_GFX6(device
->physical_device
->rad_info
.chip_class
>= GFX8
);
6997 VkResult
radv_CreateSampler(
6999 const VkSamplerCreateInfo
* pCreateInfo
,
7000 const VkAllocationCallbacks
* pAllocator
,
7001 VkSampler
* pSampler
)
7003 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7004 struct radv_sampler
*sampler
;
7006 const struct VkSamplerYcbcrConversionInfo
*ycbcr_conversion
=
7007 vk_find_struct_const(pCreateInfo
->pNext
,
7008 SAMPLER_YCBCR_CONVERSION_INFO
);
7010 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO
);
7012 sampler
= vk_alloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*sampler
), 8,
7013 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
7015 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
7017 vk_object_base_init(&device
->vk
, &sampler
->base
,
7018 VK_OBJECT_TYPE_SAMPLER
);
7020 radv_init_sampler(device
, sampler
, pCreateInfo
);
7022 sampler
->ycbcr_sampler
= ycbcr_conversion
? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion
->conversion
): NULL
;
7023 *pSampler
= radv_sampler_to_handle(sampler
);
7028 void radv_DestroySampler(
7031 const VkAllocationCallbacks
* pAllocator
)
7033 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7034 RADV_FROM_HANDLE(radv_sampler
, sampler
, _sampler
);
7039 if (sampler
->border_color_slot
!= RADV_BORDER_COLOR_COUNT
)
7040 radv_unregister_border_color(device
, sampler
->border_color_slot
);
7042 vk_object_base_finish(&sampler
->base
);
7043 vk_free2(&device
->vk
.alloc
, pAllocator
, sampler
);
7046 /* vk_icd.h does not declare this function, so we declare it here to
7047 * suppress Wmissing-prototypes.
7049 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
7050 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
);
7052 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
7053 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
)
7055 /* For the full details on loader interface versioning, see
7056 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
7057 * What follows is a condensed summary, to help you navigate the large and
7058 * confusing official doc.
7060 * - Loader interface v0 is incompatible with later versions. We don't
7063 * - In loader interface v1:
7064 * - The first ICD entrypoint called by the loader is
7065 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
7067 * - The ICD must statically expose no other Vulkan symbol unless it is
7068 * linked with -Bsymbolic.
7069 * - Each dispatchable Vulkan handle created by the ICD must be
7070 * a pointer to a struct whose first member is VK_LOADER_DATA. The
7071 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
7072 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
7073 * vkDestroySurfaceKHR(). The ICD must be capable of working with
7074 * such loader-managed surfaces.
7076 * - Loader interface v2 differs from v1 in:
7077 * - The first ICD entrypoint called by the loader is
7078 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
7079 * statically expose this entrypoint.
7081 * - Loader interface v3 differs from v2 in:
7082 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
7083 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
7084 * because the loader no longer does so.
7086 *pSupportedVersion
= MIN2(*pSupportedVersion
, 4u);
7090 VkResult
radv_GetMemoryFdKHR(VkDevice _device
,
7091 const VkMemoryGetFdInfoKHR
*pGetFdInfo
,
7094 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7095 RADV_FROM_HANDLE(radv_device_memory
, memory
, pGetFdInfo
->memory
);
7097 assert(pGetFdInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR
);
7099 /* At the moment, we support only the below handle types. */
7100 assert(pGetFdInfo
->handleType
==
7101 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT
||
7102 pGetFdInfo
->handleType
==
7103 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
7105 bool ret
= radv_get_memory_fd(device
, memory
, pFD
);
7107 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
7111 static uint32_t radv_compute_valid_memory_types_attempt(struct radv_physical_device
*dev
,
7112 enum radeon_bo_domain domains
,
7113 enum radeon_bo_flag flags
,
7114 enum radeon_bo_flag ignore_flags
)
7116 /* Don't count GTT/CPU as relevant:
7118 * - We're not fully consistent between the two.
7119 * - Sometimes VRAM gets VRAM|GTT.
7121 const enum radeon_bo_domain relevant_domains
= RADEON_DOMAIN_VRAM
|
7125 for (unsigned i
= 0; i
< dev
->memory_properties
.memoryTypeCount
; ++i
) {
7126 if ((domains
& relevant_domains
) != (dev
->memory_domains
[i
] & relevant_domains
))
7129 if ((flags
& ~ignore_flags
) != (dev
->memory_flags
[i
] & ~ignore_flags
))
7138 static uint32_t radv_compute_valid_memory_types(struct radv_physical_device
*dev
,
7139 enum radeon_bo_domain domains
,
7140 enum radeon_bo_flag flags
)
7142 enum radeon_bo_flag ignore_flags
= ~(RADEON_FLAG_NO_CPU_ACCESS
| RADEON_FLAG_GTT_WC
);
7143 uint32_t bits
= radv_compute_valid_memory_types_attempt(dev
, domains
, flags
, ignore_flags
);
7146 ignore_flags
|= RADEON_FLAG_NO_CPU_ACCESS
;
7147 bits
= radv_compute_valid_memory_types_attempt(dev
, domains
, flags
, ignore_flags
);
7152 VkResult
radv_GetMemoryFdPropertiesKHR(VkDevice _device
,
7153 VkExternalMemoryHandleTypeFlagBits handleType
,
7155 VkMemoryFdPropertiesKHR
*pMemoryFdProperties
)
7157 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7159 switch (handleType
) {
7160 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
: {
7161 enum radeon_bo_domain domains
;
7162 enum radeon_bo_flag flags
;
7163 if (!device
->ws
->buffer_get_flags_from_fd(device
->ws
, fd
, &domains
, &flags
))
7164 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7166 pMemoryFdProperties
->memoryTypeBits
= radv_compute_valid_memory_types(device
->physical_device
, domains
, flags
);
7170 /* The valid usage section for this function says:
7172 * "handleType must not be one of the handle types defined as
7175 * So opaque handle types fall into the default "unsupported" case.
7177 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7181 static VkResult
radv_import_opaque_fd(struct radv_device
*device
,
7185 uint32_t syncobj_handle
= 0;
7186 int ret
= device
->ws
->import_syncobj(device
->ws
, fd
, &syncobj_handle
);
7188 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7191 device
->ws
->destroy_syncobj(device
->ws
, *syncobj
);
7193 *syncobj
= syncobj_handle
;
7199 static VkResult
radv_import_sync_fd(struct radv_device
*device
,
7203 /* If we create a syncobj we do it locally so that if we have an error, we don't
7204 * leave a syncobj in an undetermined state in the fence. */
7205 uint32_t syncobj_handle
= *syncobj
;
7206 if (!syncobj_handle
) {
7207 bool create_signaled
= fd
== -1 ? true : false;
7209 int ret
= device
->ws
->create_syncobj(device
->ws
, create_signaled
,
7212 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
7216 device
->ws
->signal_syncobj(device
->ws
, syncobj_handle
);
7220 int ret
= device
->ws
->import_syncobj_from_sync_file(device
->ws
, syncobj_handle
, fd
);
7222 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7226 *syncobj
= syncobj_handle
;
7231 VkResult
radv_ImportSemaphoreFdKHR(VkDevice _device
,
7232 const VkImportSemaphoreFdInfoKHR
*pImportSemaphoreFdInfo
)
7234 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7235 RADV_FROM_HANDLE(radv_semaphore
, sem
, pImportSemaphoreFdInfo
->semaphore
);
7237 struct radv_semaphore_part
*dst
= NULL
;
7239 if (pImportSemaphoreFdInfo
->flags
& VK_SEMAPHORE_IMPORT_TEMPORARY_BIT
) {
7240 dst
= &sem
->temporary
;
7242 dst
= &sem
->permanent
;
7245 uint32_t syncobj
= dst
->kind
== RADV_SEMAPHORE_SYNCOBJ
? dst
->syncobj
: 0;
7247 switch(pImportSemaphoreFdInfo
->handleType
) {
7248 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
:
7249 result
= radv_import_opaque_fd(device
, pImportSemaphoreFdInfo
->fd
, &syncobj
);
7251 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
:
7252 result
= radv_import_sync_fd(device
, pImportSemaphoreFdInfo
->fd
, &syncobj
);
7255 unreachable("Unhandled semaphore handle type");
7258 if (result
== VK_SUCCESS
) {
7259 dst
->syncobj
= syncobj
;
7260 dst
->kind
= RADV_SEMAPHORE_SYNCOBJ
;
7266 VkResult
radv_GetSemaphoreFdKHR(VkDevice _device
,
7267 const VkSemaphoreGetFdInfoKHR
*pGetFdInfo
,
7270 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7271 RADV_FROM_HANDLE(radv_semaphore
, sem
, pGetFdInfo
->semaphore
);
7273 uint32_t syncobj_handle
;
7275 if (sem
->temporary
.kind
!= RADV_SEMAPHORE_NONE
) {
7276 assert(sem
->temporary
.kind
== RADV_SEMAPHORE_SYNCOBJ
);
7277 syncobj_handle
= sem
->temporary
.syncobj
;
7279 assert(sem
->permanent
.kind
== RADV_SEMAPHORE_SYNCOBJ
);
7280 syncobj_handle
= sem
->permanent
.syncobj
;
7283 switch(pGetFdInfo
->handleType
) {
7284 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
:
7285 ret
= device
->ws
->export_syncobj(device
->ws
, syncobj_handle
, pFd
);
7287 return vk_error(device
->instance
, VK_ERROR_TOO_MANY_OBJECTS
);
7289 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
:
7290 ret
= device
->ws
->export_syncobj_to_sync_file(device
->ws
, syncobj_handle
, pFd
);
7292 return vk_error(device
->instance
, VK_ERROR_TOO_MANY_OBJECTS
);
7294 if (sem
->temporary
.kind
!= RADV_SEMAPHORE_NONE
) {
7295 radv_destroy_semaphore_part(device
, &sem
->temporary
);
7297 device
->ws
->reset_syncobj(device
->ws
, syncobj_handle
);
7301 unreachable("Unhandled semaphore handle type");
7307 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
7308 VkPhysicalDevice physicalDevice
,
7309 const VkPhysicalDeviceExternalSemaphoreInfo
*pExternalSemaphoreInfo
,
7310 VkExternalSemaphoreProperties
*pExternalSemaphoreProperties
)
7312 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
7313 VkSemaphoreTypeKHR type
= radv_get_semaphore_type(pExternalSemaphoreInfo
->pNext
, NULL
);
7315 if (type
== VK_SEMAPHORE_TYPE_TIMELINE
) {
7316 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= 0;
7317 pExternalSemaphoreProperties
->compatibleHandleTypes
= 0;
7318 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= 0;
7320 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
7321 } else if (pdevice
->rad_info
.has_syncobj_wait_for_submit
&&
7322 (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
||
7323 pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
)) {
7324 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
;
7325 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
;
7326 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT
|
7327 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
7328 } else if (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
) {
7329 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
7330 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
7331 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT
|
7332 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
7334 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= 0;
7335 pExternalSemaphoreProperties
->compatibleHandleTypes
= 0;
7336 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= 0;
7340 VkResult
radv_ImportFenceFdKHR(VkDevice _device
,
7341 const VkImportFenceFdInfoKHR
*pImportFenceFdInfo
)
7343 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7344 RADV_FROM_HANDLE(radv_fence
, fence
, pImportFenceFdInfo
->fence
);
7345 struct radv_fence_part
*dst
= NULL
;
7348 if (pImportFenceFdInfo
->flags
& VK_FENCE_IMPORT_TEMPORARY_BIT
) {
7349 dst
= &fence
->temporary
;
7351 dst
= &fence
->permanent
;
7354 uint32_t syncobj
= dst
->kind
== RADV_FENCE_SYNCOBJ
? dst
->syncobj
: 0;
7356 switch(pImportFenceFdInfo
->handleType
) {
7357 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
:
7358 result
= radv_import_opaque_fd(device
, pImportFenceFdInfo
->fd
, &syncobj
);
7360 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
:
7361 result
= radv_import_sync_fd(device
, pImportFenceFdInfo
->fd
, &syncobj
);
7364 unreachable("Unhandled fence handle type");
7367 if (result
== VK_SUCCESS
) {
7368 dst
->syncobj
= syncobj
;
7369 dst
->kind
= RADV_FENCE_SYNCOBJ
;
7375 VkResult
radv_GetFenceFdKHR(VkDevice _device
,
7376 const VkFenceGetFdInfoKHR
*pGetFdInfo
,
7379 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7380 RADV_FROM_HANDLE(radv_fence
, fence
, pGetFdInfo
->fence
);
7383 struct radv_fence_part
*part
=
7384 fence
->temporary
.kind
!= RADV_FENCE_NONE
?
7385 &fence
->temporary
: &fence
->permanent
;
7387 switch(pGetFdInfo
->handleType
) {
7388 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
:
7389 ret
= device
->ws
->export_syncobj(device
->ws
, part
->syncobj
, pFd
);
7391 return vk_error(device
->instance
, VK_ERROR_TOO_MANY_OBJECTS
);
7393 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
:
7394 ret
= device
->ws
->export_syncobj_to_sync_file(device
->ws
,
7395 part
->syncobj
, pFd
);
7397 return vk_error(device
->instance
, VK_ERROR_TOO_MANY_OBJECTS
);
7399 if (part
== &fence
->temporary
) {
7400 radv_destroy_fence_part(device
, part
);
7402 device
->ws
->reset_syncobj(device
->ws
, part
->syncobj
);
7406 unreachable("Unhandled fence handle type");
7412 void radv_GetPhysicalDeviceExternalFenceProperties(
7413 VkPhysicalDevice physicalDevice
,
7414 const VkPhysicalDeviceExternalFenceInfo
*pExternalFenceInfo
,
7415 VkExternalFenceProperties
*pExternalFenceProperties
)
7417 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
7419 if (pdevice
->rad_info
.has_syncobj_wait_for_submit
&&
7420 (pExternalFenceInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
||
7421 pExternalFenceInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
)) {
7422 pExternalFenceProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
;
7423 pExternalFenceProperties
->compatibleHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
;
7424 pExternalFenceProperties
->externalFenceFeatures
= VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT
|
7425 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
7427 pExternalFenceProperties
->exportFromImportedHandleTypes
= 0;
7428 pExternalFenceProperties
->compatibleHandleTypes
= 0;
7429 pExternalFenceProperties
->externalFenceFeatures
= 0;
7434 radv_CreateDebugReportCallbackEXT(VkInstance _instance
,
7435 const VkDebugReportCallbackCreateInfoEXT
* pCreateInfo
,
7436 const VkAllocationCallbacks
* pAllocator
,
7437 VkDebugReportCallbackEXT
* pCallback
)
7439 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
7440 return vk_create_debug_report_callback(&instance
->debug_report_callbacks
,
7441 pCreateInfo
, pAllocator
, &instance
->alloc
,
7446 radv_DestroyDebugReportCallbackEXT(VkInstance _instance
,
7447 VkDebugReportCallbackEXT _callback
,
7448 const VkAllocationCallbacks
* pAllocator
)
7450 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
7451 vk_destroy_debug_report_callback(&instance
->debug_report_callbacks
,
7452 _callback
, pAllocator
, &instance
->alloc
);
7456 radv_DebugReportMessageEXT(VkInstance _instance
,
7457 VkDebugReportFlagsEXT flags
,
7458 VkDebugReportObjectTypeEXT objectType
,
7461 int32_t messageCode
,
7462 const char* pLayerPrefix
,
7463 const char* pMessage
)
7465 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
7466 vk_debug_report(&instance
->debug_report_callbacks
, flags
, objectType
,
7467 object
, location
, messageCode
, pLayerPrefix
, pMessage
);
7471 radv_GetDeviceGroupPeerMemoryFeatures(
7474 uint32_t localDeviceIndex
,
7475 uint32_t remoteDeviceIndex
,
7476 VkPeerMemoryFeatureFlags
* pPeerMemoryFeatures
)
7478 assert(localDeviceIndex
== remoteDeviceIndex
);
7480 *pPeerMemoryFeatures
= VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT
|
7481 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT
|
7482 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT
|
7483 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT
;
7486 static const VkTimeDomainEXT radv_time_domains
[] = {
7487 VK_TIME_DOMAIN_DEVICE_EXT
,
7488 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT
,
7489 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT
,
7492 VkResult
radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
7493 VkPhysicalDevice physicalDevice
,
7494 uint32_t *pTimeDomainCount
,
7495 VkTimeDomainEXT
*pTimeDomains
)
7498 VK_OUTARRAY_MAKE(out
, pTimeDomains
, pTimeDomainCount
);
7500 for (d
= 0; d
< ARRAY_SIZE(radv_time_domains
); d
++) {
7501 vk_outarray_append(&out
, i
) {
7502 *i
= radv_time_domains
[d
];
7506 return vk_outarray_status(&out
);
7510 radv_clock_gettime(clockid_t clock_id
)
7512 struct timespec current
;
7515 ret
= clock_gettime(clock_id
, ¤t
);
7516 if (ret
< 0 && clock_id
== CLOCK_MONOTONIC_RAW
)
7517 ret
= clock_gettime(CLOCK_MONOTONIC
, ¤t
);
7521 return (uint64_t) current
.tv_sec
* 1000000000ULL + current
.tv_nsec
;
7524 VkResult
radv_GetCalibratedTimestampsEXT(
7526 uint32_t timestampCount
,
7527 const VkCalibratedTimestampInfoEXT
*pTimestampInfos
,
7528 uint64_t *pTimestamps
,
7529 uint64_t *pMaxDeviation
)
7531 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7532 uint32_t clock_crystal_freq
= device
->physical_device
->rad_info
.clock_crystal_freq
;
7534 uint64_t begin
, end
;
7535 uint64_t max_clock_period
= 0;
7537 begin
= radv_clock_gettime(CLOCK_MONOTONIC_RAW
);
7539 for (d
= 0; d
< timestampCount
; d
++) {
7540 switch (pTimestampInfos
[d
].timeDomain
) {
7541 case VK_TIME_DOMAIN_DEVICE_EXT
:
7542 pTimestamps
[d
] = device
->ws
->query_value(device
->ws
,
7544 uint64_t device_period
= DIV_ROUND_UP(1000000, clock_crystal_freq
);
7545 max_clock_period
= MAX2(max_clock_period
, device_period
);
7547 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT
:
7548 pTimestamps
[d
] = radv_clock_gettime(CLOCK_MONOTONIC
);
7549 max_clock_period
= MAX2(max_clock_period
, 1);
7552 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT
:
7553 pTimestamps
[d
] = begin
;
7561 end
= radv_clock_gettime(CLOCK_MONOTONIC_RAW
);
7564 * The maximum deviation is the sum of the interval over which we
7565 * perform the sampling and the maximum period of any sampled
7566 * clock. That's because the maximum skew between any two sampled
7567 * clock edges is when the sampled clock with the largest period is
7568 * sampled at the end of that period but right at the beginning of the
7569 * sampling interval and some other clock is sampled right at the
7570 * begining of its sampling period and right at the end of the
7571 * sampling interval. Let's assume the GPU has the longest clock
7572 * period and that the application is sampling GPU and monotonic:
7575 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
7576 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
7580 * GPU -----_____-----_____-----_____-----_____
7583 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
7584 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
7586 * Interval <----------------->
7587 * Deviation <-------------------------->
7591 * m = read(monotonic) 2
7594 * We round the sample interval up by one tick to cover sampling error
7595 * in the interval clock
7598 uint64_t sample_interval
= end
- begin
+ 1;
7600 *pMaxDeviation
= sample_interval
+ max_clock_period
;
7605 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
7606 VkPhysicalDevice physicalDevice
,
7607 VkSampleCountFlagBits samples
,
7608 VkMultisamplePropertiesEXT
* pMultisampleProperties
)
7610 if (samples
& (VK_SAMPLE_COUNT_2_BIT
|
7611 VK_SAMPLE_COUNT_4_BIT
|
7612 VK_SAMPLE_COUNT_8_BIT
)) {
7613 pMultisampleProperties
->maxSampleLocationGridSize
= (VkExtent2D
){ 2, 2 };
7615 pMultisampleProperties
->maxSampleLocationGridSize
= (VkExtent2D
){ 0, 0 };
7619 VkResult
radv_CreatePrivateDataSlotEXT(
7621 const VkPrivateDataSlotCreateInfoEXT
* pCreateInfo
,
7622 const VkAllocationCallbacks
* pAllocator
,
7623 VkPrivateDataSlotEXT
* pPrivateDataSlot
)
7625 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7626 return vk_private_data_slot_create(&device
->vk
, pCreateInfo
, pAllocator
,
7630 void radv_DestroyPrivateDataSlotEXT(
7632 VkPrivateDataSlotEXT privateDataSlot
,
7633 const VkAllocationCallbacks
* pAllocator
)
7635 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7636 vk_private_data_slot_destroy(&device
->vk
, privateDataSlot
, pAllocator
);
7639 VkResult
radv_SetPrivateDataEXT(
7641 VkObjectType objectType
,
7642 uint64_t objectHandle
,
7643 VkPrivateDataSlotEXT privateDataSlot
,
7646 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7647 return vk_object_base_set_private_data(&device
->vk
, objectType
,
7648 objectHandle
, privateDataSlot
,
7652 void radv_GetPrivateDataEXT(
7654 VkObjectType objectType
,
7655 uint64_t objectHandle
,
7656 VkPrivateDataSlotEXT privateDataSlot
,
7659 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7660 vk_object_base_get_private_data(&device
->vk
, objectType
, objectHandle
,
7661 privateDataSlot
, pData
);