2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include <linux/audit.h>
32 #include <linux/bpf.h>
33 #include <linux/filter.h>
34 #include <linux/seccomp.h>
35 #include <linux/unistd.h>
36 #include <stdatomic.h>
41 #include <sys/prctl.h>
46 #include "radv_debug.h"
47 #include "radv_private.h"
48 #include "radv_shader.h"
50 #include "util/disk_cache.h"
54 #include "drm-uapi/amdgpu_drm.h"
55 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
56 #include "winsys/null/radv_null_winsys_public.h"
57 #include "ac_llvm_util.h"
58 #include "vk_format.h"
61 #include "util/build_id.h"
62 #include "util/debug.h"
63 #include "util/mesa-sha1.h"
64 #include "util/timespec.h"
65 #include "util/u_atomic.h"
66 #include "compiler/glsl_types.h"
67 #include "util/driconf.h"
69 static struct radv_timeline_point
*
70 radv_timeline_find_point_at_least_locked(struct radv_device
*device
,
71 struct radv_timeline
*timeline
,
74 static struct radv_timeline_point
*
75 radv_timeline_add_point_locked(struct radv_device
*device
,
76 struct radv_timeline
*timeline
,
80 radv_timeline_trigger_waiters_locked(struct radv_timeline
*timeline
,
81 struct list_head
*processing_list
);
84 void radv_destroy_semaphore_part(struct radv_device
*device
,
85 struct radv_semaphore_part
*part
);
88 radv_create_pthread_cond(pthread_cond_t
*cond
);
90 uint64_t radv_get_current_time(void)
93 clock_gettime(CLOCK_MONOTONIC
, &tv
);
94 return tv
.tv_nsec
+ tv
.tv_sec
*1000000000ull;
97 static uint64_t radv_get_absolute_timeout(uint64_t timeout
)
99 uint64_t current_time
= radv_get_current_time();
101 timeout
= MIN2(UINT64_MAX
- current_time
, timeout
);
103 return current_time
+ timeout
;
107 radv_device_get_cache_uuid(enum radeon_family family
, void *uuid
)
109 struct mesa_sha1 ctx
;
110 unsigned char sha1
[20];
111 unsigned ptr_size
= sizeof(void*);
113 memset(uuid
, 0, VK_UUID_SIZE
);
114 _mesa_sha1_init(&ctx
);
116 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid
, &ctx
) ||
117 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo
, &ctx
))
120 _mesa_sha1_update(&ctx
, &family
, sizeof(family
));
121 _mesa_sha1_update(&ctx
, &ptr_size
, sizeof(ptr_size
));
122 _mesa_sha1_final(&ctx
, sha1
);
124 memcpy(uuid
, sha1
, VK_UUID_SIZE
);
129 radv_get_driver_uuid(void *uuid
)
131 ac_compute_driver_uuid(uuid
, VK_UUID_SIZE
);
135 radv_get_device_uuid(struct radeon_info
*info
, void *uuid
)
137 ac_compute_device_uuid(info
, uuid
, VK_UUID_SIZE
);
141 radv_get_visible_vram_size(struct radv_physical_device
*device
)
143 return MIN2(device
->rad_info
.vram_size
, device
->rad_info
.vram_vis_size
);
147 radv_get_vram_size(struct radv_physical_device
*device
)
149 return device
->rad_info
.vram_size
- radv_get_visible_vram_size(device
);
153 radv_physical_device_init_mem_types(struct radv_physical_device
*device
)
155 uint64_t visible_vram_size
= radv_get_visible_vram_size(device
);
156 uint64_t vram_size
= radv_get_vram_size(device
);
157 int vram_index
= -1, visible_vram_index
= -1, gart_index
= -1;
158 device
->memory_properties
.memoryHeapCount
= 0;
160 vram_index
= device
->memory_properties
.memoryHeapCount
++;
161 device
->memory_properties
.memoryHeaps
[vram_index
] = (VkMemoryHeap
) {
163 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
167 if (device
->rad_info
.gart_size
> 0) {
168 gart_index
= device
->memory_properties
.memoryHeapCount
++;
169 device
->memory_properties
.memoryHeaps
[gart_index
] = (VkMemoryHeap
) {
170 .size
= device
->rad_info
.gart_size
,
175 if (visible_vram_size
) {
176 visible_vram_index
= device
->memory_properties
.memoryHeapCount
++;
177 device
->memory_properties
.memoryHeaps
[visible_vram_index
] = (VkMemoryHeap
) {
178 .size
= visible_vram_size
,
179 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
183 unsigned type_count
= 0;
185 if (vram_index
>= 0 || visible_vram_index
>= 0) {
186 device
->memory_domains
[type_count
] = RADEON_DOMAIN_VRAM
;
187 device
->memory_flags
[type_count
] = RADEON_FLAG_NO_CPU_ACCESS
;
188 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
189 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
,
190 .heapIndex
= vram_index
>= 0 ? vram_index
: visible_vram_index
,
194 if (gart_index
>= 0) {
195 device
->memory_domains
[type_count
] = RADEON_DOMAIN_GTT
;
196 device
->memory_flags
[type_count
] = RADEON_FLAG_GTT_WC
| RADEON_FLAG_CPU_ACCESS
;
197 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
198 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
199 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
200 .heapIndex
= gart_index
,
203 if (visible_vram_index
>= 0) {
204 device
->memory_domains
[type_count
] = RADEON_DOMAIN_VRAM
;
205 device
->memory_flags
[type_count
] = RADEON_FLAG_CPU_ACCESS
;
206 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
207 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
|
208 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
209 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
210 .heapIndex
= visible_vram_index
,
214 if (gart_index
>= 0) {
215 device
->memory_domains
[type_count
] = RADEON_DOMAIN_GTT
;
216 device
->memory_flags
[type_count
] = RADEON_FLAG_CPU_ACCESS
;
217 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
218 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
219 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
220 VK_MEMORY_PROPERTY_HOST_CACHED_BIT
,
221 .heapIndex
= gart_index
,
224 device
->memory_properties
.memoryTypeCount
= type_count
;
226 if (device
->rad_info
.has_l2_uncached
) {
227 for (int i
= 0; i
< device
->memory_properties
.memoryTypeCount
; i
++) {
228 VkMemoryType mem_type
= device
->memory_properties
.memoryTypes
[i
];
230 if ((mem_type
.propertyFlags
& (VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
231 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
)) ||
232 mem_type
.propertyFlags
== VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
) {
234 VkMemoryPropertyFlags property_flags
= mem_type
.propertyFlags
|
235 VK_MEMORY_PROPERTY_DEVICE_COHERENT_BIT_AMD
|
236 VK_MEMORY_PROPERTY_DEVICE_UNCACHED_BIT_AMD
;
238 device
->memory_domains
[type_count
] = device
->memory_domains
[i
];
239 device
->memory_flags
[type_count
] = device
->memory_flags
[i
] | RADEON_FLAG_VA_UNCACHED
;
240 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
241 .propertyFlags
= property_flags
,
242 .heapIndex
= mem_type
.heapIndex
,
246 device
->memory_properties
.memoryTypeCount
= type_count
;
251 radv_get_compiler_string(struct radv_physical_device
*pdevice
)
253 if (!pdevice
->use_llvm
) {
254 /* Some games like SotTR apply shader workarounds if the LLVM
255 * version is too old or if the LLVM version string is
256 * missing. This gives 2-5% performance with SotTR and ACO.
258 if (driQueryOptionb(&pdevice
->instance
->dri_options
,
259 "radv_report_llvm9_version_string")) {
260 return "ACO/LLVM 9.0.1";
266 return "LLVM " MESA_LLVM_VERSION_STRING
;
270 radv_physical_device_try_create(struct radv_instance
*instance
,
271 drmDevicePtr drm_device
,
272 struct radv_physical_device
**device_out
)
279 const char *path
= drm_device
->nodes
[DRM_NODE_RENDER
];
280 drmVersionPtr version
;
282 fd
= open(path
, O_RDWR
| O_CLOEXEC
);
284 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
285 radv_logi("Could not open device '%s'", path
);
287 return vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
290 version
= drmGetVersion(fd
);
294 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
295 radv_logi("Could not get the kernel driver version for device '%s'", path
);
297 return vk_errorf(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
,
298 "failed to get version %s: %m", path
);
301 if (strcmp(version
->name
, "amdgpu")) {
302 drmFreeVersion(version
);
305 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
306 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path
);
308 return VK_ERROR_INCOMPATIBLE_DRIVER
;
310 drmFreeVersion(version
);
312 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
313 radv_logi("Found compatible device '%s'.", path
);
316 struct radv_physical_device
*device
=
317 vk_zalloc2(&instance
->alloc
, NULL
, sizeof(*device
), 8,
318 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
320 result
= vk_error(instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
324 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
325 device
->instance
= instance
;
328 device
->ws
= radv_amdgpu_winsys_create(fd
, instance
->debug_flags
,
329 instance
->perftest_flags
);
331 device
->ws
= radv_null_winsys_create();
335 result
= vk_errorf(instance
, VK_ERROR_INITIALIZATION_FAILED
,
336 "failed to initialize winsys");
340 if (drm_device
&& instance
->enabled_extensions
.KHR_display
) {
341 master_fd
= open(drm_device
->nodes
[DRM_NODE_PRIMARY
], O_RDWR
| O_CLOEXEC
);
342 if (master_fd
>= 0) {
343 uint32_t accel_working
= 0;
344 struct drm_amdgpu_info request
= {
345 .return_pointer
= (uintptr_t)&accel_working
,
346 .return_size
= sizeof(accel_working
),
347 .query
= AMDGPU_INFO_ACCEL_WORKING
350 if (drmCommandWrite(master_fd
, DRM_AMDGPU_INFO
, &request
, sizeof (struct drm_amdgpu_info
)) < 0 || !accel_working
) {
357 device
->master_fd
= master_fd
;
358 device
->local_fd
= fd
;
359 device
->ws
->query_info(device
->ws
, &device
->rad_info
);
361 device
->use_llvm
= instance
->debug_flags
& RADV_DEBUG_LLVM
;
363 snprintf(device
->name
, sizeof(device
->name
),
365 device
->rad_info
.name
, radv_get_compiler_string(device
));
367 if (radv_device_get_cache_uuid(device
->rad_info
.family
, device
->cache_uuid
)) {
368 result
= vk_errorf(instance
, VK_ERROR_INITIALIZATION_FAILED
,
369 "cannot generate UUID");
373 /* These flags affect shader compilation. */
374 uint64_t shader_env_flags
= (device
->use_llvm
? 0 : 0x2);
376 /* The gpu id is already embedded in the uuid so we just pass "radv"
377 * when creating the cache.
379 char buf
[VK_UUID_SIZE
* 2 + 1];
380 disk_cache_format_hex_id(buf
, device
->cache_uuid
, VK_UUID_SIZE
* 2);
381 device
->disk_cache
= disk_cache_create(device
->name
, buf
, shader_env_flags
);
383 if (device
->rad_info
.chip_class
< GFX8
)
384 fprintf(stderr
, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
386 radv_get_driver_uuid(&device
->driver_uuid
);
387 radv_get_device_uuid(&device
->rad_info
, &device
->device_uuid
);
389 device
->out_of_order_rast_allowed
= device
->rad_info
.has_out_of_order_rast
&&
390 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_OUT_OF_ORDER
);
392 device
->dcc_msaa_allowed
=
393 (device
->instance
->perftest_flags
& RADV_PERFTEST_DCC_MSAA
);
395 device
->use_ngg
= device
->rad_info
.chip_class
>= GFX10
&&
396 device
->rad_info
.family
!= CHIP_NAVI14
&&
397 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_NGG
);
399 /* TODO: Implement NGG GS with ACO. */
400 device
->use_ngg_gs
= device
->use_ngg
&& device
->use_llvm
;
401 device
->use_ngg_streamout
= false;
403 /* Determine the number of threads per wave for all stages. */
404 device
->cs_wave_size
= 64;
405 device
->ps_wave_size
= 64;
406 device
->ge_wave_size
= 64;
408 if (device
->rad_info
.chip_class
>= GFX10
) {
409 if (device
->instance
->perftest_flags
& RADV_PERFTEST_CS_WAVE_32
)
410 device
->cs_wave_size
= 32;
412 /* For pixel shaders, wave64 is recommanded. */
413 if (device
->instance
->perftest_flags
& RADV_PERFTEST_PS_WAVE_32
)
414 device
->ps_wave_size
= 32;
416 if (device
->instance
->perftest_flags
& RADV_PERFTEST_GE_WAVE_32
)
417 device
->ge_wave_size
= 32;
420 radv_physical_device_init_mem_types(device
);
422 radv_physical_device_get_supported_extensions(device
,
423 &device
->supported_extensions
);
426 device
->bus_info
= *drm_device
->businfo
.pci
;
428 if ((device
->instance
->debug_flags
& RADV_DEBUG_INFO
))
429 ac_print_gpu_info(&device
->rad_info
);
431 /* The WSI is structured as a layer on top of the driver, so this has
432 * to be the last part of initialization (at least until we get other
435 result
= radv_init_wsi(device
);
436 if (result
!= VK_SUCCESS
) {
437 vk_error(instance
, result
);
438 goto fail_disk_cache
;
441 *device_out
= device
;
446 disk_cache_destroy(device
->disk_cache
);
448 device
->ws
->destroy(device
->ws
);
450 vk_free(&instance
->alloc
, device
);
460 radv_physical_device_destroy(struct radv_physical_device
*device
)
462 radv_finish_wsi(device
);
463 device
->ws
->destroy(device
->ws
);
464 disk_cache_destroy(device
->disk_cache
);
465 close(device
->local_fd
);
466 if (device
->master_fd
!= -1)
467 close(device
->master_fd
);
468 vk_free(&device
->instance
->alloc
, device
);
472 default_alloc_func(void *pUserData
, size_t size
, size_t align
,
473 VkSystemAllocationScope allocationScope
)
479 default_realloc_func(void *pUserData
, void *pOriginal
, size_t size
,
480 size_t align
, VkSystemAllocationScope allocationScope
)
482 return realloc(pOriginal
, size
);
486 default_free_func(void *pUserData
, void *pMemory
)
491 static const VkAllocationCallbacks default_alloc
= {
493 .pfnAllocation
= default_alloc_func
,
494 .pfnReallocation
= default_realloc_func
,
495 .pfnFree
= default_free_func
,
498 static const struct debug_control radv_debug_options
[] = {
499 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS
},
500 {"nodcc", RADV_DEBUG_NO_DCC
},
501 {"shaders", RADV_DEBUG_DUMP_SHADERS
},
502 {"nocache", RADV_DEBUG_NO_CACHE
},
503 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS
},
504 {"nohiz", RADV_DEBUG_NO_HIZ
},
505 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE
},
506 {"allbos", RADV_DEBUG_ALL_BOS
},
507 {"noibs", RADV_DEBUG_NO_IBS
},
508 {"spirv", RADV_DEBUG_DUMP_SPIRV
},
509 {"vmfaults", RADV_DEBUG_VM_FAULTS
},
510 {"zerovram", RADV_DEBUG_ZERO_VRAM
},
511 {"syncshaders", RADV_DEBUG_SYNC_SHADERS
},
512 {"preoptir", RADV_DEBUG_PREOPTIR
},
513 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS
},
514 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER
},
515 {"info", RADV_DEBUG_INFO
},
516 {"errors", RADV_DEBUG_ERRORS
},
517 {"startup", RADV_DEBUG_STARTUP
},
518 {"checkir", RADV_DEBUG_CHECKIR
},
519 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM
},
520 {"nobinning", RADV_DEBUG_NOBINNING
},
521 {"nongg", RADV_DEBUG_NO_NGG
},
522 {"allentrypoints", RADV_DEBUG_ALL_ENTRYPOINTS
},
523 {"metashaders", RADV_DEBUG_DUMP_META_SHADERS
},
524 {"nomemorycache", RADV_DEBUG_NO_MEMORY_CACHE
},
525 {"llvm", RADV_DEBUG_LLVM
},
526 {"forcecompress", RADV_DEBUG_FORCE_COMPRESS
},
531 radv_get_debug_option_name(int id
)
533 assert(id
< ARRAY_SIZE(radv_debug_options
) - 1);
534 return radv_debug_options
[id
].string
;
537 static const struct debug_control radv_perftest_options
[] = {
538 {"localbos", RADV_PERFTEST_LOCAL_BOS
},
539 {"dccmsaa", RADV_PERFTEST_DCC_MSAA
},
540 {"bolist", RADV_PERFTEST_BO_LIST
},
541 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK
},
542 {"cswave32", RADV_PERFTEST_CS_WAVE_32
},
543 {"pswave32", RADV_PERFTEST_PS_WAVE_32
},
544 {"gewave32", RADV_PERFTEST_GE_WAVE_32
},
545 {"dfsm", RADV_PERFTEST_DFSM
},
550 radv_get_perftest_option_name(int id
)
552 assert(id
< ARRAY_SIZE(radv_perftest_options
) - 1);
553 return radv_perftest_options
[id
].string
;
557 radv_handle_per_app_options(struct radv_instance
*instance
,
558 const VkApplicationInfo
*info
)
560 const char *name
= info
? info
->pApplicationName
: NULL
;
561 const char *engine_name
= info
? info
->pEngineName
: NULL
;
564 if (!strcmp(name
, "DOOM_VFR")) {
565 /* Work around a Doom VFR game bug */
566 instance
->debug_flags
|= RADV_DEBUG_NO_DYNAMIC_BOUNDS
;
567 } else if (!strcmp(name
, "Fledge")) {
569 * Zero VRAM for "The Surge 2"
571 * This avoid a hang when when rendering any level. Likely
572 * uninitialized data in an indirect draw.
574 instance
->debug_flags
|= RADV_DEBUG_ZERO_VRAM
;
575 } else if (!strcmp(name
, "No Man's Sky")) {
576 /* Work around a NMS game bug */
577 instance
->debug_flags
|= RADV_DEBUG_DISCARD_TO_DEMOTE
;
578 } else if (!strcmp(name
, "DOOMEternal")) {
579 /* Zero VRAM for Doom Eternal to fix rendering issues. */
580 instance
->debug_flags
|= RADV_DEBUG_ZERO_VRAM
;
581 } else if (!strcmp(name
, "Red Dead Redemption 2")) {
582 /* Work around a RDR2 game bug */
583 instance
->debug_flags
|= RADV_DEBUG_DISCARD_TO_DEMOTE
;
588 if (!strcmp(engine_name
, "vkd3d")) {
589 /* Zero VRAM for all VKD3D (DX12->VK) games to fix
592 instance
->debug_flags
|= RADV_DEBUG_ZERO_VRAM
;
593 } else if (!strcmp(engine_name
, "Quantic Dream Engine")) {
594 /* Fix various artifacts in Detroit: Become Human */
595 instance
->debug_flags
|= RADV_DEBUG_ZERO_VRAM
|
596 RADV_DEBUG_DISCARD_TO_DEMOTE
;
600 instance
->enable_mrt_output_nan_fixup
=
601 driQueryOptionb(&instance
->dri_options
,
602 "radv_enable_mrt_output_nan_fixup");
604 if (driQueryOptionb(&instance
->dri_options
, "radv_no_dynamic_bounds"))
605 instance
->debug_flags
|= RADV_DEBUG_NO_DYNAMIC_BOUNDS
;
608 static const char radv_dri_options_xml
[] =
610 DRI_CONF_SECTION_PERFORMANCE
611 DRI_CONF_ADAPTIVE_SYNC("true")
612 DRI_CONF_VK_X11_OVERRIDE_MIN_IMAGE_COUNT(0)
613 DRI_CONF_VK_X11_STRICT_IMAGE_COUNT("false")
614 DRI_CONF_VK_X11_ENSURE_MIN_IMAGE_COUNT("false")
615 DRI_CONF_RADV_REPORT_LLVM9_VERSION_STRING("false")
616 DRI_CONF_RADV_ENABLE_MRT_OUTPUT_NAN_FIXUP("false")
617 DRI_CONF_RADV_NO_DYNAMIC_BOUNDS("false")
618 DRI_CONF_RADV_OVERRIDE_UNIFORM_OFFSET_ALIGNMENT(0)
621 DRI_CONF_SECTION_DEBUG
622 DRI_CONF_VK_WSI_FORCE_BGRA8_UNORM_FIRST("false")
626 static void radv_init_dri_options(struct radv_instance
*instance
)
628 driParseOptionInfo(&instance
->available_dri_options
, radv_dri_options_xml
);
629 driParseConfigFiles(&instance
->dri_options
,
630 &instance
->available_dri_options
,
632 instance
->applicationName
,
633 instance
->applicationVersion
,
634 instance
->engineName
,
635 instance
->engineVersion
);
638 VkResult
radv_CreateInstance(
639 const VkInstanceCreateInfo
* pCreateInfo
,
640 const VkAllocationCallbacks
* pAllocator
,
641 VkInstance
* pInstance
)
643 struct radv_instance
*instance
;
646 instance
= vk_zalloc2(&default_alloc
, pAllocator
, sizeof(*instance
), 8,
647 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
649 return vk_error(NULL
, VK_ERROR_OUT_OF_HOST_MEMORY
);
651 vk_object_base_init(NULL
, &instance
->base
, VK_OBJECT_TYPE_INSTANCE
);
654 instance
->alloc
= *pAllocator
;
656 instance
->alloc
= default_alloc
;
658 if (pCreateInfo
->pApplicationInfo
) {
659 const VkApplicationInfo
*app
= pCreateInfo
->pApplicationInfo
;
661 instance
->applicationName
=
662 vk_strdup(&instance
->alloc
, app
->pApplicationName
,
663 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
664 instance
->applicationVersion
= app
->applicationVersion
;
666 instance
->engineName
=
667 vk_strdup(&instance
->alloc
, app
->pEngineName
,
668 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
669 instance
->engineVersion
= app
->engineVersion
;
670 instance
->apiVersion
= app
->apiVersion
;
673 if (instance
->apiVersion
== 0)
674 instance
->apiVersion
= VK_API_VERSION_1_0
;
676 instance
->debug_flags
= parse_debug_string(getenv("RADV_DEBUG"),
679 const char *radv_perftest_str
= getenv("RADV_PERFTEST");
680 instance
->perftest_flags
= parse_debug_string(radv_perftest_str
,
681 radv_perftest_options
);
683 if (radv_perftest_str
) {
684 /* Output warnings for famous RADV_PERFTEST options that no
685 * longer exist or are deprecated.
687 if (strstr(radv_perftest_str
, "aco")) {
688 fprintf(stderr
, "*******************************************************************************\n");
689 fprintf(stderr
, "* WARNING: Unknown option RADV_PERFTEST='aco'. ACO is enabled by default now. *\n");
690 fprintf(stderr
, "*******************************************************************************\n");
692 if (strstr(radv_perftest_str
, "llvm")) {
693 fprintf(stderr
, "*********************************************************************************\n");
694 fprintf(stderr
, "* WARNING: Unknown option 'RADV_PERFTEST=llvm'. Did you mean 'RADV_DEBUG=llvm'? *\n");
695 fprintf(stderr
, "*********************************************************************************\n");
700 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
701 radv_logi("Created an instance");
703 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
705 for (idx
= 0; idx
< RADV_INSTANCE_EXTENSION_COUNT
; idx
++) {
706 if (!strcmp(pCreateInfo
->ppEnabledExtensionNames
[i
],
707 radv_instance_extensions
[idx
].extensionName
))
711 if (idx
>= RADV_INSTANCE_EXTENSION_COUNT
||
712 !radv_instance_extensions_supported
.extensions
[idx
]) {
713 vk_object_base_finish(&instance
->base
);
714 vk_free2(&default_alloc
, pAllocator
, instance
);
715 return vk_error(instance
, VK_ERROR_EXTENSION_NOT_PRESENT
);
718 instance
->enabled_extensions
.extensions
[idx
] = true;
721 bool unchecked
= instance
->debug_flags
& RADV_DEBUG_ALL_ENTRYPOINTS
;
723 for (unsigned i
= 0; i
< ARRAY_SIZE(instance
->dispatch
.entrypoints
); i
++) {
724 /* Vulkan requires that entrypoints for extensions which have
725 * not been enabled must not be advertised.
728 !radv_instance_entrypoint_is_enabled(i
, instance
->apiVersion
,
729 &instance
->enabled_extensions
)) {
730 instance
->dispatch
.entrypoints
[i
] = NULL
;
732 instance
->dispatch
.entrypoints
[i
] =
733 radv_instance_dispatch_table
.entrypoints
[i
];
737 for (unsigned i
= 0; i
< ARRAY_SIZE(instance
->physical_device_dispatch
.entrypoints
); i
++) {
738 /* Vulkan requires that entrypoints for extensions which have
739 * not been enabled must not be advertised.
742 !radv_physical_device_entrypoint_is_enabled(i
, instance
->apiVersion
,
743 &instance
->enabled_extensions
)) {
744 instance
->physical_device_dispatch
.entrypoints
[i
] = NULL
;
746 instance
->physical_device_dispatch
.entrypoints
[i
] =
747 radv_physical_device_dispatch_table
.entrypoints
[i
];
751 for (unsigned i
= 0; i
< ARRAY_SIZE(instance
->device_dispatch
.entrypoints
); i
++) {
752 /* Vulkan requires that entrypoints for extensions which have
753 * not been enabled must not be advertised.
756 !radv_device_entrypoint_is_enabled(i
, instance
->apiVersion
,
757 &instance
->enabled_extensions
, NULL
)) {
758 instance
->device_dispatch
.entrypoints
[i
] = NULL
;
760 instance
->device_dispatch
.entrypoints
[i
] =
761 radv_device_dispatch_table
.entrypoints
[i
];
765 instance
->physical_devices_enumerated
= false;
766 list_inithead(&instance
->physical_devices
);
768 result
= vk_debug_report_instance_init(&instance
->debug_report_callbacks
);
769 if (result
!= VK_SUCCESS
) {
770 vk_object_base_finish(&instance
->base
);
771 vk_free2(&default_alloc
, pAllocator
, instance
);
772 return vk_error(instance
, result
);
775 glsl_type_singleton_init_or_ref();
777 VG(VALGRIND_CREATE_MEMPOOL(instance
, 0, false));
779 radv_init_dri_options(instance
);
780 radv_handle_per_app_options(instance
, pCreateInfo
->pApplicationInfo
);
782 *pInstance
= radv_instance_to_handle(instance
);
787 void radv_DestroyInstance(
788 VkInstance _instance
,
789 const VkAllocationCallbacks
* pAllocator
)
791 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
796 list_for_each_entry_safe(struct radv_physical_device
, pdevice
,
797 &instance
->physical_devices
, link
) {
798 radv_physical_device_destroy(pdevice
);
801 vk_free(&instance
->alloc
, instance
->engineName
);
802 vk_free(&instance
->alloc
, instance
->applicationName
);
804 VG(VALGRIND_DESTROY_MEMPOOL(instance
));
806 glsl_type_singleton_decref();
808 driDestroyOptionCache(&instance
->dri_options
);
809 driDestroyOptionInfo(&instance
->available_dri_options
);
811 vk_debug_report_instance_destroy(&instance
->debug_report_callbacks
);
813 vk_object_base_finish(&instance
->base
);
814 vk_free(&instance
->alloc
, instance
);
818 radv_enumerate_physical_devices(struct radv_instance
*instance
)
820 if (instance
->physical_devices_enumerated
)
823 instance
->physical_devices_enumerated
= true;
825 /* TODO: Check for more devices ? */
826 drmDevicePtr devices
[8];
827 VkResult result
= VK_SUCCESS
;
830 if (getenv("RADV_FORCE_FAMILY")) {
831 /* When RADV_FORCE_FAMILY is set, the driver creates a nul
832 * device that allows to test the compiler without having an
835 struct radv_physical_device
*pdevice
;
837 result
= radv_physical_device_try_create(instance
, NULL
, &pdevice
);
838 if (result
!= VK_SUCCESS
)
841 list_addtail(&pdevice
->link
, &instance
->physical_devices
);
845 max_devices
= drmGetDevices2(0, devices
, ARRAY_SIZE(devices
));
847 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
848 radv_logi("Found %d drm nodes", max_devices
);
851 return vk_error(instance
, VK_SUCCESS
);
853 for (unsigned i
= 0; i
< (unsigned)max_devices
; i
++) {
854 if (devices
[i
]->available_nodes
& 1 << DRM_NODE_RENDER
&&
855 devices
[i
]->bustype
== DRM_BUS_PCI
&&
856 devices
[i
]->deviceinfo
.pci
->vendor_id
== ATI_VENDOR_ID
) {
858 struct radv_physical_device
*pdevice
;
859 result
= radv_physical_device_try_create(instance
, devices
[i
],
861 /* Incompatible DRM device, skip. */
862 if (result
== VK_ERROR_INCOMPATIBLE_DRIVER
) {
867 /* Error creating the physical device, report the error. */
868 if (result
!= VK_SUCCESS
)
871 list_addtail(&pdevice
->link
, &instance
->physical_devices
);
874 drmFreeDevices(devices
, max_devices
);
876 /* If we successfully enumerated any devices, call it success */
880 VkResult
radv_EnumeratePhysicalDevices(
881 VkInstance _instance
,
882 uint32_t* pPhysicalDeviceCount
,
883 VkPhysicalDevice
* pPhysicalDevices
)
885 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
886 VK_OUTARRAY_MAKE(out
, pPhysicalDevices
, pPhysicalDeviceCount
);
888 VkResult result
= radv_enumerate_physical_devices(instance
);
889 if (result
!= VK_SUCCESS
)
892 list_for_each_entry(struct radv_physical_device
, pdevice
,
893 &instance
->physical_devices
, link
) {
894 vk_outarray_append(&out
, i
) {
895 *i
= radv_physical_device_to_handle(pdevice
);
899 return vk_outarray_status(&out
);
902 VkResult
radv_EnumeratePhysicalDeviceGroups(
903 VkInstance _instance
,
904 uint32_t* pPhysicalDeviceGroupCount
,
905 VkPhysicalDeviceGroupProperties
* pPhysicalDeviceGroupProperties
)
907 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
908 VK_OUTARRAY_MAKE(out
, pPhysicalDeviceGroupProperties
,
909 pPhysicalDeviceGroupCount
);
911 VkResult result
= radv_enumerate_physical_devices(instance
);
912 if (result
!= VK_SUCCESS
)
915 list_for_each_entry(struct radv_physical_device
, pdevice
,
916 &instance
->physical_devices
, link
) {
917 vk_outarray_append(&out
, p
) {
918 p
->physicalDeviceCount
= 1;
919 memset(p
->physicalDevices
, 0, sizeof(p
->physicalDevices
));
920 p
->physicalDevices
[0] = radv_physical_device_to_handle(pdevice
);
921 p
->subsetAllocation
= false;
925 return vk_outarray_status(&out
);
928 void radv_GetPhysicalDeviceFeatures(
929 VkPhysicalDevice physicalDevice
,
930 VkPhysicalDeviceFeatures
* pFeatures
)
932 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
933 memset(pFeatures
, 0, sizeof(*pFeatures
));
935 *pFeatures
= (VkPhysicalDeviceFeatures
) {
936 .robustBufferAccess
= true,
937 .fullDrawIndexUint32
= true,
938 .imageCubeArray
= true,
939 .independentBlend
= true,
940 .geometryShader
= true,
941 .tessellationShader
= true,
942 .sampleRateShading
= true,
943 .dualSrcBlend
= true,
945 .multiDrawIndirect
= true,
946 .drawIndirectFirstInstance
= true,
948 .depthBiasClamp
= true,
949 .fillModeNonSolid
= true,
954 .multiViewport
= true,
955 .samplerAnisotropy
= true,
956 .textureCompressionETC2
= radv_device_supports_etc(pdevice
),
957 .textureCompressionASTC_LDR
= false,
958 .textureCompressionBC
= true,
959 .occlusionQueryPrecise
= true,
960 .pipelineStatisticsQuery
= true,
961 .vertexPipelineStoresAndAtomics
= true,
962 .fragmentStoresAndAtomics
= true,
963 .shaderTessellationAndGeometryPointSize
= true,
964 .shaderImageGatherExtended
= true,
965 .shaderStorageImageExtendedFormats
= true,
966 .shaderStorageImageMultisample
= true,
967 .shaderUniformBufferArrayDynamicIndexing
= true,
968 .shaderSampledImageArrayDynamicIndexing
= true,
969 .shaderStorageBufferArrayDynamicIndexing
= true,
970 .shaderStorageImageArrayDynamicIndexing
= true,
971 .shaderStorageImageReadWithoutFormat
= true,
972 .shaderStorageImageWriteWithoutFormat
= true,
973 .shaderClipDistance
= true,
974 .shaderCullDistance
= true,
975 .shaderFloat64
= true,
978 .sparseBinding
= true,
979 .variableMultisampleRate
= true,
980 .shaderResourceMinLod
= true,
981 .inheritedQueries
= true,
986 radv_get_physical_device_features_1_1(struct radv_physical_device
*pdevice
,
987 VkPhysicalDeviceVulkan11Features
*f
)
989 assert(f
->sType
== VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES
);
991 f
->storageBuffer16BitAccess
= true;
992 f
->uniformAndStorageBuffer16BitAccess
= true;
993 f
->storagePushConstant16
= true;
994 f
->storageInputOutput16
= pdevice
->rad_info
.has_packed_math_16bit
&& (LLVM_VERSION_MAJOR
>= 9 || !pdevice
->use_llvm
);
996 f
->multiviewGeometryShader
= true;
997 f
->multiviewTessellationShader
= true;
998 f
->variablePointersStorageBuffer
= true;
999 f
->variablePointers
= true;
1000 f
->protectedMemory
= false;
1001 f
->samplerYcbcrConversion
= true;
1002 f
->shaderDrawParameters
= true;
1006 radv_get_physical_device_features_1_2(struct radv_physical_device
*pdevice
,
1007 VkPhysicalDeviceVulkan12Features
*f
)
1009 assert(f
->sType
== VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES
);
1011 f
->samplerMirrorClampToEdge
= true;
1012 f
->drawIndirectCount
= true;
1013 f
->storageBuffer8BitAccess
= true;
1014 f
->uniformAndStorageBuffer8BitAccess
= true;
1015 f
->storagePushConstant8
= true;
1016 f
->shaderBufferInt64Atomics
= LLVM_VERSION_MAJOR
>= 9 || !pdevice
->use_llvm
;
1017 f
->shaderSharedInt64Atomics
= LLVM_VERSION_MAJOR
>= 9 || !pdevice
->use_llvm
;
1018 f
->shaderFloat16
= pdevice
->rad_info
.has_packed_math_16bit
;
1019 f
->shaderInt8
= true;
1021 f
->descriptorIndexing
= true;
1022 f
->shaderInputAttachmentArrayDynamicIndexing
= true;
1023 f
->shaderUniformTexelBufferArrayDynamicIndexing
= true;
1024 f
->shaderStorageTexelBufferArrayDynamicIndexing
= true;
1025 f
->shaderUniformBufferArrayNonUniformIndexing
= true;
1026 f
->shaderSampledImageArrayNonUniformIndexing
= true;
1027 f
->shaderStorageBufferArrayNonUniformIndexing
= true;
1028 f
->shaderStorageImageArrayNonUniformIndexing
= true;
1029 f
->shaderInputAttachmentArrayNonUniformIndexing
= true;
1030 f
->shaderUniformTexelBufferArrayNonUniformIndexing
= true;
1031 f
->shaderStorageTexelBufferArrayNonUniformIndexing
= true;
1032 f
->descriptorBindingUniformBufferUpdateAfterBind
= true;
1033 f
->descriptorBindingSampledImageUpdateAfterBind
= true;
1034 f
->descriptorBindingStorageImageUpdateAfterBind
= true;
1035 f
->descriptorBindingStorageBufferUpdateAfterBind
= true;
1036 f
->descriptorBindingUniformTexelBufferUpdateAfterBind
= true;
1037 f
->descriptorBindingStorageTexelBufferUpdateAfterBind
= true;
1038 f
->descriptorBindingUpdateUnusedWhilePending
= true;
1039 f
->descriptorBindingPartiallyBound
= true;
1040 f
->descriptorBindingVariableDescriptorCount
= true;
1041 f
->runtimeDescriptorArray
= true;
1043 f
->samplerFilterMinmax
= true;
1044 f
->scalarBlockLayout
= pdevice
->rad_info
.chip_class
>= GFX7
;
1045 f
->imagelessFramebuffer
= true;
1046 f
->uniformBufferStandardLayout
= true;
1047 f
->shaderSubgroupExtendedTypes
= true;
1048 f
->separateDepthStencilLayouts
= true;
1049 f
->hostQueryReset
= true;
1050 f
->timelineSemaphore
= pdevice
->rad_info
.has_syncobj_wait_for_submit
;
1051 f
->bufferDeviceAddress
= true;
1052 f
->bufferDeviceAddressCaptureReplay
= false;
1053 f
->bufferDeviceAddressMultiDevice
= false;
1054 f
->vulkanMemoryModel
= true;
1055 f
->vulkanMemoryModelDeviceScope
= true;
1056 f
->vulkanMemoryModelAvailabilityVisibilityChains
= false;
1057 f
->shaderOutputViewportIndex
= true;
1058 f
->shaderOutputLayer
= true;
1059 f
->subgroupBroadcastDynamicId
= true;
1062 void radv_GetPhysicalDeviceFeatures2(
1063 VkPhysicalDevice physicalDevice
,
1064 VkPhysicalDeviceFeatures2
*pFeatures
)
1066 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1067 radv_GetPhysicalDeviceFeatures(physicalDevice
, &pFeatures
->features
);
1069 VkPhysicalDeviceVulkan11Features core_1_1
= {
1070 .sType
= VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES
,
1072 radv_get_physical_device_features_1_1(pdevice
, &core_1_1
);
1074 VkPhysicalDeviceVulkan12Features core_1_2
= {
1075 .sType
= VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES
,
1077 radv_get_physical_device_features_1_2(pdevice
, &core_1_2
);
1079 #define CORE_FEATURE(major, minor, feature) \
1080 features->feature = core_##major##_##minor.feature
1082 vk_foreach_struct(ext
, pFeatures
->pNext
) {
1083 switch (ext
->sType
) {
1084 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES
: {
1085 VkPhysicalDeviceVariablePointersFeatures
*features
= (void *)ext
;
1086 CORE_FEATURE(1, 1, variablePointersStorageBuffer
);
1087 CORE_FEATURE(1, 1, variablePointers
);
1090 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES
: {
1091 VkPhysicalDeviceMultiviewFeatures
*features
= (VkPhysicalDeviceMultiviewFeatures
*)ext
;
1092 CORE_FEATURE(1, 1, multiview
);
1093 CORE_FEATURE(1, 1, multiviewGeometryShader
);
1094 CORE_FEATURE(1, 1, multiviewTessellationShader
);
1097 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES
: {
1098 VkPhysicalDeviceShaderDrawParametersFeatures
*features
=
1099 (VkPhysicalDeviceShaderDrawParametersFeatures
*)ext
;
1100 CORE_FEATURE(1, 1, shaderDrawParameters
);
1103 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES
: {
1104 VkPhysicalDeviceProtectedMemoryFeatures
*features
=
1105 (VkPhysicalDeviceProtectedMemoryFeatures
*)ext
;
1106 CORE_FEATURE(1, 1, protectedMemory
);
1109 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES
: {
1110 VkPhysicalDevice16BitStorageFeatures
*features
=
1111 (VkPhysicalDevice16BitStorageFeatures
*)ext
;
1112 CORE_FEATURE(1, 1, storageBuffer16BitAccess
);
1113 CORE_FEATURE(1, 1, uniformAndStorageBuffer16BitAccess
);
1114 CORE_FEATURE(1, 1, storagePushConstant16
);
1115 CORE_FEATURE(1, 1, storageInputOutput16
);
1118 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES
: {
1119 VkPhysicalDeviceSamplerYcbcrConversionFeatures
*features
=
1120 (VkPhysicalDeviceSamplerYcbcrConversionFeatures
*)ext
;
1121 CORE_FEATURE(1, 1, samplerYcbcrConversion
);
1124 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES
: {
1125 VkPhysicalDeviceDescriptorIndexingFeatures
*features
=
1126 (VkPhysicalDeviceDescriptorIndexingFeatures
*)ext
;
1127 CORE_FEATURE(1, 2, shaderInputAttachmentArrayDynamicIndexing
);
1128 CORE_FEATURE(1, 2, shaderUniformTexelBufferArrayDynamicIndexing
);
1129 CORE_FEATURE(1, 2, shaderStorageTexelBufferArrayDynamicIndexing
);
1130 CORE_FEATURE(1, 2, shaderUniformBufferArrayNonUniformIndexing
);
1131 CORE_FEATURE(1, 2, shaderSampledImageArrayNonUniformIndexing
);
1132 CORE_FEATURE(1, 2, shaderStorageBufferArrayNonUniformIndexing
);
1133 CORE_FEATURE(1, 2, shaderStorageImageArrayNonUniformIndexing
);
1134 CORE_FEATURE(1, 2, shaderInputAttachmentArrayNonUniformIndexing
);
1135 CORE_FEATURE(1, 2, shaderUniformTexelBufferArrayNonUniformIndexing
);
1136 CORE_FEATURE(1, 2, shaderStorageTexelBufferArrayNonUniformIndexing
);
1137 CORE_FEATURE(1, 2, descriptorBindingUniformBufferUpdateAfterBind
);
1138 CORE_FEATURE(1, 2, descriptorBindingSampledImageUpdateAfterBind
);
1139 CORE_FEATURE(1, 2, descriptorBindingStorageImageUpdateAfterBind
);
1140 CORE_FEATURE(1, 2, descriptorBindingStorageBufferUpdateAfterBind
);
1141 CORE_FEATURE(1, 2, descriptorBindingUniformTexelBufferUpdateAfterBind
);
1142 CORE_FEATURE(1, 2, descriptorBindingStorageTexelBufferUpdateAfterBind
);
1143 CORE_FEATURE(1, 2, descriptorBindingUpdateUnusedWhilePending
);
1144 CORE_FEATURE(1, 2, descriptorBindingPartiallyBound
);
1145 CORE_FEATURE(1, 2, descriptorBindingVariableDescriptorCount
);
1146 CORE_FEATURE(1, 2, runtimeDescriptorArray
);
1149 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT
: {
1150 VkPhysicalDeviceConditionalRenderingFeaturesEXT
*features
=
1151 (VkPhysicalDeviceConditionalRenderingFeaturesEXT
*)ext
;
1152 features
->conditionalRendering
= true;
1153 features
->inheritedConditionalRendering
= false;
1156 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT
: {
1157 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT
*features
=
1158 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT
*)ext
;
1159 features
->vertexAttributeInstanceRateDivisor
= true;
1160 features
->vertexAttributeInstanceRateZeroDivisor
= true;
1163 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT
: {
1164 VkPhysicalDeviceTransformFeedbackFeaturesEXT
*features
=
1165 (VkPhysicalDeviceTransformFeedbackFeaturesEXT
*)ext
;
1166 features
->transformFeedback
= true;
1167 features
->geometryStreams
= !pdevice
->use_ngg_streamout
;
1170 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES
: {
1171 VkPhysicalDeviceScalarBlockLayoutFeatures
*features
=
1172 (VkPhysicalDeviceScalarBlockLayoutFeatures
*)ext
;
1173 CORE_FEATURE(1, 2, scalarBlockLayout
);
1176 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT
: {
1177 VkPhysicalDeviceMemoryPriorityFeaturesEXT
*features
=
1178 (VkPhysicalDeviceMemoryPriorityFeaturesEXT
*)ext
;
1179 features
->memoryPriority
= true;
1182 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT
: {
1183 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT
*features
=
1184 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT
*)ext
;
1185 features
->bufferDeviceAddress
= true;
1186 features
->bufferDeviceAddressCaptureReplay
= false;
1187 features
->bufferDeviceAddressMultiDevice
= false;
1190 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES
: {
1191 VkPhysicalDeviceBufferDeviceAddressFeatures
*features
=
1192 (VkPhysicalDeviceBufferDeviceAddressFeatures
*)ext
;
1193 CORE_FEATURE(1, 2, bufferDeviceAddress
);
1194 CORE_FEATURE(1, 2, bufferDeviceAddressCaptureReplay
);
1195 CORE_FEATURE(1, 2, bufferDeviceAddressMultiDevice
);
1198 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT
: {
1199 VkPhysicalDeviceDepthClipEnableFeaturesEXT
*features
=
1200 (VkPhysicalDeviceDepthClipEnableFeaturesEXT
*)ext
;
1201 features
->depthClipEnable
= true;
1204 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES
: {
1205 VkPhysicalDeviceHostQueryResetFeatures
*features
=
1206 (VkPhysicalDeviceHostQueryResetFeatures
*)ext
;
1207 CORE_FEATURE(1, 2, hostQueryReset
);
1210 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES
: {
1211 VkPhysicalDevice8BitStorageFeatures
*features
=
1212 (VkPhysicalDevice8BitStorageFeatures
*)ext
;
1213 CORE_FEATURE(1, 2, storageBuffer8BitAccess
);
1214 CORE_FEATURE(1, 2, uniformAndStorageBuffer8BitAccess
);
1215 CORE_FEATURE(1, 2, storagePushConstant8
);
1218 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_FLOAT16_INT8_FEATURES
: {
1219 VkPhysicalDeviceShaderFloat16Int8Features
*features
=
1220 (VkPhysicalDeviceShaderFloat16Int8Features
*)ext
;
1221 CORE_FEATURE(1, 2, shaderFloat16
);
1222 CORE_FEATURE(1, 2, shaderInt8
);
1225 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES
: {
1226 VkPhysicalDeviceShaderAtomicInt64Features
*features
=
1227 (VkPhysicalDeviceShaderAtomicInt64Features
*)ext
;
1228 CORE_FEATURE(1, 2, shaderBufferInt64Atomics
);
1229 CORE_FEATURE(1, 2, shaderSharedInt64Atomics
);
1232 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DEMOTE_TO_HELPER_INVOCATION_FEATURES_EXT
: {
1233 VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT
*features
=
1234 (VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT
*)ext
;
1235 features
->shaderDemoteToHelperInvocation
= LLVM_VERSION_MAJOR
>= 9 || !pdevice
->use_llvm
;
1238 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT
: {
1239 VkPhysicalDeviceInlineUniformBlockFeaturesEXT
*features
=
1240 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT
*)ext
;
1242 features
->inlineUniformBlock
= true;
1243 features
->descriptorBindingInlineUniformBlockUpdateAfterBind
= true;
1246 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV
: {
1247 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV
*features
=
1248 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV
*)ext
;
1249 features
->computeDerivativeGroupQuads
= false;
1250 features
->computeDerivativeGroupLinear
= true;
1253 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT
: {
1254 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT
*features
=
1255 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT
*)ext
;
1256 features
->ycbcrImageArrays
= true;
1259 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES
: {
1260 VkPhysicalDeviceUniformBufferStandardLayoutFeatures
*features
=
1261 (VkPhysicalDeviceUniformBufferStandardLayoutFeatures
*)ext
;
1262 CORE_FEATURE(1, 2, uniformBufferStandardLayout
);
1265 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT
: {
1266 VkPhysicalDeviceIndexTypeUint8FeaturesEXT
*features
=
1267 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT
*)ext
;
1268 features
->indexTypeUint8
= pdevice
->rad_info
.chip_class
>= GFX8
;
1271 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGELESS_FRAMEBUFFER_FEATURES
: {
1272 VkPhysicalDeviceImagelessFramebufferFeatures
*features
=
1273 (VkPhysicalDeviceImagelessFramebufferFeatures
*)ext
;
1274 CORE_FEATURE(1, 2, imagelessFramebuffer
);
1277 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR
: {
1278 VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR
*features
=
1279 (VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR
*)ext
;
1280 features
->pipelineExecutableInfo
= true;
1283 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CLOCK_FEATURES_KHR
: {
1284 VkPhysicalDeviceShaderClockFeaturesKHR
*features
=
1285 (VkPhysicalDeviceShaderClockFeaturesKHR
*)ext
;
1286 features
->shaderSubgroupClock
= true;
1287 features
->shaderDeviceClock
= pdevice
->rad_info
.chip_class
>= GFX8
;
1290 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_FEATURES_EXT
: {
1291 VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT
*features
=
1292 (VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT
*)ext
;
1293 features
->texelBufferAlignment
= true;
1296 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_FEATURES
: {
1297 VkPhysicalDeviceTimelineSemaphoreFeatures
*features
=
1298 (VkPhysicalDeviceTimelineSemaphoreFeatures
*) ext
;
1299 CORE_FEATURE(1, 2, timelineSemaphore
);
1302 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_FEATURES_EXT
: {
1303 VkPhysicalDeviceSubgroupSizeControlFeaturesEXT
*features
=
1304 (VkPhysicalDeviceSubgroupSizeControlFeaturesEXT
*)ext
;
1305 features
->subgroupSizeControl
= true;
1306 features
->computeFullSubgroups
= true;
1309 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COHERENT_MEMORY_FEATURES_AMD
: {
1310 VkPhysicalDeviceCoherentMemoryFeaturesAMD
*features
=
1311 (VkPhysicalDeviceCoherentMemoryFeaturesAMD
*)ext
;
1312 features
->deviceCoherentMemory
= pdevice
->rad_info
.has_l2_uncached
;
1315 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_SUBGROUP_EXTENDED_TYPES_FEATURES
: {
1316 VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures
*features
=
1317 (VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures
*)ext
;
1318 CORE_FEATURE(1, 2, shaderSubgroupExtendedTypes
);
1321 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SEPARATE_DEPTH_STENCIL_LAYOUTS_FEATURES_KHR
: {
1322 VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR
*features
=
1323 (VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR
*)ext
;
1324 CORE_FEATURE(1, 2, separateDepthStencilLayouts
);
1327 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES
: {
1328 radv_get_physical_device_features_1_1(pdevice
, (void *)ext
);
1331 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES
: {
1332 radv_get_physical_device_features_1_2(pdevice
, (void *)ext
);
1335 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_FEATURES_EXT
: {
1336 VkPhysicalDeviceLineRasterizationFeaturesEXT
*features
=
1337 (VkPhysicalDeviceLineRasterizationFeaturesEXT
*)ext
;
1338 features
->rectangularLines
= false;
1339 features
->bresenhamLines
= true;
1340 features
->smoothLines
= false;
1341 features
->stippledRectangularLines
= false;
1342 features
->stippledBresenhamLines
= true;
1343 features
->stippledSmoothLines
= false;
1346 case VK_STRUCTURE_TYPE_DEVICE_MEMORY_OVERALLOCATION_CREATE_INFO_AMD
: {
1347 VkDeviceMemoryOverallocationCreateInfoAMD
*features
=
1348 (VkDeviceMemoryOverallocationCreateInfoAMD
*)ext
;
1349 features
->overallocationBehavior
= true;
1352 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ROBUSTNESS_2_FEATURES_EXT
: {
1353 VkPhysicalDeviceRobustness2FeaturesEXT
*features
=
1354 (VkPhysicalDeviceRobustness2FeaturesEXT
*)ext
;
1355 features
->robustBufferAccess2
= true;
1356 features
->robustImageAccess2
= true;
1357 features
->nullDescriptor
= true;
1360 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_FEATURES_EXT
: {
1361 VkPhysicalDeviceCustomBorderColorFeaturesEXT
*features
=
1362 (VkPhysicalDeviceCustomBorderColorFeaturesEXT
*)ext
;
1363 features
->customBorderColors
= true;
1364 features
->customBorderColorWithoutFormat
= true;
1367 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PRIVATE_DATA_FEATURES_EXT
: {
1368 VkPhysicalDevicePrivateDataFeaturesEXT
*features
=
1369 (VkPhysicalDevicePrivateDataFeaturesEXT
*)ext
;
1370 features
->privateData
= true;
1373 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_CREATION_CACHE_CONTROL_FEATURES_EXT
: {
1374 VkPhysicalDevicePipelineCreationCacheControlFeaturesEXT
*features
=
1375 (VkPhysicalDevicePipelineCreationCacheControlFeaturesEXT
*)ext
;
1376 features
-> pipelineCreationCacheControl
= true;
1379 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_MEMORY_MODEL_FEATURES_KHR
: {
1380 VkPhysicalDeviceVulkanMemoryModelFeaturesKHR
*features
=
1381 (VkPhysicalDeviceVulkanMemoryModelFeaturesKHR
*)ext
;
1382 CORE_FEATURE(1, 2, vulkanMemoryModel
);
1383 CORE_FEATURE(1, 2, vulkanMemoryModelDeviceScope
);
1384 CORE_FEATURE(1, 2, vulkanMemoryModelAvailabilityVisibilityChains
);
1387 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTENDED_DYNAMIC_STATE_FEATURES_EXT
: {
1388 VkPhysicalDeviceExtendedDynamicStateFeaturesEXT
*features
=
1389 (VkPhysicalDeviceExtendedDynamicStateFeaturesEXT
*) ext
;
1390 features
->extendedDynamicState
= true;
1393 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGE_ROBUSTNESS_FEATURES_EXT
: {
1394 VkPhysicalDeviceImageRobustnessFeaturesEXT
*features
=
1395 (VkPhysicalDeviceImageRobustnessFeaturesEXT
*)ext
;
1396 features
->robustImageAccess
= true;
1399 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_FLOAT_FEATURES_EXT
: {
1400 VkPhysicalDeviceShaderAtomicFloatFeaturesEXT
*features
=
1401 (VkPhysicalDeviceShaderAtomicFloatFeaturesEXT
*)ext
;
1402 features
->shaderBufferFloat32Atomics
= true;
1403 features
->shaderBufferFloat32AtomicAdd
= false;
1404 features
->shaderBufferFloat64Atomics
= true;
1405 features
->shaderBufferFloat64AtomicAdd
= false;
1406 features
->shaderSharedFloat32Atomics
= true;
1407 features
->shaderSharedFloat32AtomicAdd
= pdevice
->rad_info
.chip_class
>= GFX8
&&
1408 (!pdevice
->use_llvm
|| LLVM_VERSION_MAJOR
>= 10);
1409 features
->shaderSharedFloat64Atomics
= true;
1410 features
->shaderSharedFloat64AtomicAdd
= false;
1411 features
->shaderImageFloat32Atomics
= true;
1412 features
->shaderImageFloat32AtomicAdd
= false;
1413 features
->sparseImageFloat32Atomics
= false;
1414 features
->sparseImageFloat32AtomicAdd
= false;
1417 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_4444_FORMATS_FEATURES_EXT
: {
1418 VkPhysicalDevice4444FormatsFeaturesEXT
*features
=
1419 (VkPhysicalDevice4444FormatsFeaturesEXT
*)ext
;
1420 features
->formatA4R4G4B4
= true;
1421 features
->formatA4B4G4R4
= true;
1432 radv_max_descriptor_set_size()
1434 /* make sure that the entire descriptor set is addressable with a signed
1435 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1436 * be at most 2 GiB. the combined image & samples object count as one of
1437 * both. This limit is for the pipeline layout, not for the set layout, but
1438 * there is no set limit, so we just set a pipeline limit. I don't think
1439 * any app is going to hit this soon. */
1440 return ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
1441 - MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_INLINE_UNIFORM_BLOCK_COUNT
) /
1442 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1443 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1444 32 /* sampler, largest when combined with image */ +
1445 64 /* sampled image */ +
1446 64 /* storage image */);
1450 radv_uniform_buffer_offset_alignment(const struct radv_physical_device
*pdevice
)
1452 uint32_t uniform_offset_alignment
= driQueryOptioni(&pdevice
->instance
->dri_options
,
1453 "radv_override_uniform_offset_alignment");
1454 if (!util_is_power_of_two_or_zero(uniform_offset_alignment
)) {
1455 fprintf(stderr
, "ERROR: invalid radv_override_uniform_offset_alignment setting %d:"
1456 "not a power of two\n", uniform_offset_alignment
);
1457 uniform_offset_alignment
= 0;
1460 /* Take at least the hardware limit. */
1461 return MAX2(uniform_offset_alignment
, 4);
1464 void radv_GetPhysicalDeviceProperties(
1465 VkPhysicalDevice physicalDevice
,
1466 VkPhysicalDeviceProperties
* pProperties
)
1468 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1469 VkSampleCountFlags sample_counts
= 0xf;
1471 size_t max_descriptor_set_size
= radv_max_descriptor_set_size();
1473 VkPhysicalDeviceLimits limits
= {
1474 .maxImageDimension1D
= (1 << 14),
1475 .maxImageDimension2D
= (1 << 14),
1476 .maxImageDimension3D
= (1 << 11),
1477 .maxImageDimensionCube
= (1 << 14),
1478 .maxImageArrayLayers
= (1 << 11),
1479 .maxTexelBufferElements
= UINT32_MAX
,
1480 .maxUniformBufferRange
= UINT32_MAX
,
1481 .maxStorageBufferRange
= UINT32_MAX
,
1482 .maxPushConstantsSize
= MAX_PUSH_CONSTANTS_SIZE
,
1483 .maxMemoryAllocationCount
= UINT32_MAX
,
1484 .maxSamplerAllocationCount
= 64 * 1024,
1485 .bufferImageGranularity
= 64, /* A cache line */
1486 .sparseAddressSpaceSize
= RADV_MAX_MEMORY_ALLOCATION_SIZE
, /* buffer max size */
1487 .maxBoundDescriptorSets
= MAX_SETS
,
1488 .maxPerStageDescriptorSamplers
= max_descriptor_set_size
,
1489 .maxPerStageDescriptorUniformBuffers
= max_descriptor_set_size
,
1490 .maxPerStageDescriptorStorageBuffers
= max_descriptor_set_size
,
1491 .maxPerStageDescriptorSampledImages
= max_descriptor_set_size
,
1492 .maxPerStageDescriptorStorageImages
= max_descriptor_set_size
,
1493 .maxPerStageDescriptorInputAttachments
= max_descriptor_set_size
,
1494 .maxPerStageResources
= max_descriptor_set_size
,
1495 .maxDescriptorSetSamplers
= max_descriptor_set_size
,
1496 .maxDescriptorSetUniformBuffers
= max_descriptor_set_size
,
1497 .maxDescriptorSetUniformBuffersDynamic
= MAX_DYNAMIC_UNIFORM_BUFFERS
,
1498 .maxDescriptorSetStorageBuffers
= max_descriptor_set_size
,
1499 .maxDescriptorSetStorageBuffersDynamic
= MAX_DYNAMIC_STORAGE_BUFFERS
,
1500 .maxDescriptorSetSampledImages
= max_descriptor_set_size
,
1501 .maxDescriptorSetStorageImages
= max_descriptor_set_size
,
1502 .maxDescriptorSetInputAttachments
= max_descriptor_set_size
,
1503 .maxVertexInputAttributes
= MAX_VERTEX_ATTRIBS
,
1504 .maxVertexInputBindings
= MAX_VBS
,
1505 .maxVertexInputAttributeOffset
= 2047,
1506 .maxVertexInputBindingStride
= 2048,
1507 .maxVertexOutputComponents
= 128,
1508 .maxTessellationGenerationLevel
= 64,
1509 .maxTessellationPatchSize
= 32,
1510 .maxTessellationControlPerVertexInputComponents
= 128,
1511 .maxTessellationControlPerVertexOutputComponents
= 128,
1512 .maxTessellationControlPerPatchOutputComponents
= 120,
1513 .maxTessellationControlTotalOutputComponents
= 4096,
1514 .maxTessellationEvaluationInputComponents
= 128,
1515 .maxTessellationEvaluationOutputComponents
= 128,
1516 .maxGeometryShaderInvocations
= 127,
1517 .maxGeometryInputComponents
= 64,
1518 .maxGeometryOutputComponents
= 128,
1519 .maxGeometryOutputVertices
= 256,
1520 .maxGeometryTotalOutputComponents
= 1024,
1521 .maxFragmentInputComponents
= 128,
1522 .maxFragmentOutputAttachments
= 8,
1523 .maxFragmentDualSrcAttachments
= 1,
1524 .maxFragmentCombinedOutputResources
= 8,
1525 .maxComputeSharedMemorySize
= 32768,
1526 .maxComputeWorkGroupCount
= { 65535, 65535, 65535 },
1527 .maxComputeWorkGroupInvocations
= 1024,
1528 .maxComputeWorkGroupSize
= {
1533 .subPixelPrecisionBits
= 8,
1534 .subTexelPrecisionBits
= 8,
1535 .mipmapPrecisionBits
= 8,
1536 .maxDrawIndexedIndexValue
= UINT32_MAX
,
1537 .maxDrawIndirectCount
= UINT32_MAX
,
1538 .maxSamplerLodBias
= 16,
1539 .maxSamplerAnisotropy
= 16,
1540 .maxViewports
= MAX_VIEWPORTS
,
1541 .maxViewportDimensions
= { (1 << 14), (1 << 14) },
1542 .viewportBoundsRange
= { INT16_MIN
, INT16_MAX
},
1543 .viewportSubPixelBits
= 8,
1544 .minMemoryMapAlignment
= 4096, /* A page */
1545 .minTexelBufferOffsetAlignment
= 4,
1546 .minUniformBufferOffsetAlignment
= radv_uniform_buffer_offset_alignment(pdevice
),
1547 .minStorageBufferOffsetAlignment
= 4,
1548 .minTexelOffset
= -32,
1549 .maxTexelOffset
= 31,
1550 .minTexelGatherOffset
= -32,
1551 .maxTexelGatherOffset
= 31,
1552 .minInterpolationOffset
= -2,
1553 .maxInterpolationOffset
= 2,
1554 .subPixelInterpolationOffsetBits
= 8,
1555 .maxFramebufferWidth
= (1 << 14),
1556 .maxFramebufferHeight
= (1 << 14),
1557 .maxFramebufferLayers
= (1 << 10),
1558 .framebufferColorSampleCounts
= sample_counts
,
1559 .framebufferDepthSampleCounts
= sample_counts
,
1560 .framebufferStencilSampleCounts
= sample_counts
,
1561 .framebufferNoAttachmentsSampleCounts
= sample_counts
,
1562 .maxColorAttachments
= MAX_RTS
,
1563 .sampledImageColorSampleCounts
= sample_counts
,
1564 .sampledImageIntegerSampleCounts
= sample_counts
,
1565 .sampledImageDepthSampleCounts
= sample_counts
,
1566 .sampledImageStencilSampleCounts
= sample_counts
,
1567 .storageImageSampleCounts
= sample_counts
,
1568 .maxSampleMaskWords
= 1,
1569 .timestampComputeAndGraphics
= true,
1570 .timestampPeriod
= 1000000.0 / pdevice
->rad_info
.clock_crystal_freq
,
1571 .maxClipDistances
= 8,
1572 .maxCullDistances
= 8,
1573 .maxCombinedClipAndCullDistances
= 8,
1574 .discreteQueuePriorities
= 2,
1575 .pointSizeRange
= { 0.0, 8191.875 },
1576 .lineWidthRange
= { 0.0, 8191.875 },
1577 .pointSizeGranularity
= (1.0 / 8.0),
1578 .lineWidthGranularity
= (1.0 / 8.0),
1579 .strictLines
= false, /* FINISHME */
1580 .standardSampleLocations
= true,
1581 .optimalBufferCopyOffsetAlignment
= 128,
1582 .optimalBufferCopyRowPitchAlignment
= 128,
1583 .nonCoherentAtomSize
= 64,
1586 *pProperties
= (VkPhysicalDeviceProperties
) {
1587 .apiVersion
= radv_physical_device_api_version(pdevice
),
1588 .driverVersion
= vk_get_driver_version(),
1589 .vendorID
= ATI_VENDOR_ID
,
1590 .deviceID
= pdevice
->rad_info
.pci_id
,
1591 .deviceType
= pdevice
->rad_info
.has_dedicated_vram
? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU
: VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU
,
1593 .sparseProperties
= {0},
1596 strcpy(pProperties
->deviceName
, pdevice
->name
);
1597 memcpy(pProperties
->pipelineCacheUUID
, pdevice
->cache_uuid
, VK_UUID_SIZE
);
1601 radv_get_physical_device_properties_1_1(struct radv_physical_device
*pdevice
,
1602 VkPhysicalDeviceVulkan11Properties
*p
)
1604 assert(p
->sType
== VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES
);
1606 memcpy(p
->deviceUUID
, pdevice
->device_uuid
, VK_UUID_SIZE
);
1607 memcpy(p
->driverUUID
, pdevice
->driver_uuid
, VK_UUID_SIZE
);
1608 memset(p
->deviceLUID
, 0, VK_LUID_SIZE
);
1609 /* The LUID is for Windows. */
1610 p
->deviceLUIDValid
= false;
1611 p
->deviceNodeMask
= 0;
1613 p
->subgroupSize
= RADV_SUBGROUP_SIZE
;
1614 p
->subgroupSupportedStages
= VK_SHADER_STAGE_ALL_GRAPHICS
|
1615 VK_SHADER_STAGE_COMPUTE_BIT
;
1616 p
->subgroupSupportedOperations
= VK_SUBGROUP_FEATURE_BASIC_BIT
|
1617 VK_SUBGROUP_FEATURE_VOTE_BIT
|
1618 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT
|
1619 VK_SUBGROUP_FEATURE_BALLOT_BIT
|
1620 VK_SUBGROUP_FEATURE_CLUSTERED_BIT
|
1621 VK_SUBGROUP_FEATURE_QUAD_BIT
|
1622 VK_SUBGROUP_FEATURE_SHUFFLE_BIT
|
1623 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT
;
1624 p
->subgroupQuadOperationsInAllStages
= true;
1626 p
->pointClippingBehavior
= VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES
;
1627 p
->maxMultiviewViewCount
= MAX_VIEWS
;
1628 p
->maxMultiviewInstanceIndex
= INT_MAX
;
1629 p
->protectedNoFault
= false;
1630 p
->maxPerSetDescriptors
= RADV_MAX_PER_SET_DESCRIPTORS
;
1631 p
->maxMemoryAllocationSize
= RADV_MAX_MEMORY_ALLOCATION_SIZE
;
1635 radv_get_physical_device_properties_1_2(struct radv_physical_device
*pdevice
,
1636 VkPhysicalDeviceVulkan12Properties
*p
)
1638 assert(p
->sType
== VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES
);
1640 p
->driverID
= VK_DRIVER_ID_MESA_RADV
;
1641 snprintf(p
->driverName
, VK_MAX_DRIVER_NAME_SIZE
, "radv");
1642 snprintf(p
->driverInfo
, VK_MAX_DRIVER_INFO_SIZE
,
1643 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
" (%s)",
1644 radv_get_compiler_string(pdevice
));
1645 p
->conformanceVersion
= (VkConformanceVersion
) {
1652 /* On AMD hardware, denormals and rounding modes for fp16/fp64 are
1653 * controlled by the same config register.
1655 if (pdevice
->rad_info
.has_packed_math_16bit
) {
1656 p
->denormBehaviorIndependence
= VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR
;
1657 p
->roundingModeIndependence
= VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR
;
1659 p
->denormBehaviorIndependence
= VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL_KHR
;
1660 p
->roundingModeIndependence
= VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL_KHR
;
1663 /* With LLVM, do not allow both preserving and flushing denorms because
1664 * different shaders in the same pipeline can have different settings and
1665 * this won't work for merged shaders. To make it work, this requires LLVM
1666 * support for changing the register. The same logic applies for the
1667 * rounding modes because they are configured with the same config
1670 p
->shaderDenormFlushToZeroFloat32
= true;
1671 p
->shaderDenormPreserveFloat32
= !pdevice
->use_llvm
;
1672 p
->shaderRoundingModeRTEFloat32
= true;
1673 p
->shaderRoundingModeRTZFloat32
= !pdevice
->use_llvm
;
1674 p
->shaderSignedZeroInfNanPreserveFloat32
= true;
1676 p
->shaderDenormFlushToZeroFloat16
= pdevice
->rad_info
.has_packed_math_16bit
&& !pdevice
->use_llvm
;
1677 p
->shaderDenormPreserveFloat16
= pdevice
->rad_info
.has_packed_math_16bit
;
1678 p
->shaderRoundingModeRTEFloat16
= pdevice
->rad_info
.has_packed_math_16bit
;
1679 p
->shaderRoundingModeRTZFloat16
= pdevice
->rad_info
.has_packed_math_16bit
&& !pdevice
->use_llvm
;
1680 p
->shaderSignedZeroInfNanPreserveFloat16
= pdevice
->rad_info
.has_packed_math_16bit
;
1682 p
->shaderDenormFlushToZeroFloat64
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_llvm
;
1683 p
->shaderDenormPreserveFloat64
= pdevice
->rad_info
.chip_class
>= GFX8
;
1684 p
->shaderRoundingModeRTEFloat64
= pdevice
->rad_info
.chip_class
>= GFX8
;
1685 p
->shaderRoundingModeRTZFloat64
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_llvm
;
1686 p
->shaderSignedZeroInfNanPreserveFloat64
= pdevice
->rad_info
.chip_class
>= GFX8
;
1688 p
->maxUpdateAfterBindDescriptorsInAllPools
= UINT32_MAX
/ 64;
1689 p
->shaderUniformBufferArrayNonUniformIndexingNative
= false;
1690 p
->shaderSampledImageArrayNonUniformIndexingNative
= false;
1691 p
->shaderStorageBufferArrayNonUniformIndexingNative
= false;
1692 p
->shaderStorageImageArrayNonUniformIndexingNative
= false;
1693 p
->shaderInputAttachmentArrayNonUniformIndexingNative
= false;
1694 p
->robustBufferAccessUpdateAfterBind
= false;
1695 p
->quadDivergentImplicitLod
= false;
1697 size_t max_descriptor_set_size
= ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
-
1698 MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_INLINE_UNIFORM_BLOCK_COUNT
) /
1699 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1700 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1701 32 /* sampler, largest when combined with image */ +
1702 64 /* sampled image */ +
1703 64 /* storage image */);
1704 p
->maxPerStageDescriptorUpdateAfterBindSamplers
= max_descriptor_set_size
;
1705 p
->maxPerStageDescriptorUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1706 p
->maxPerStageDescriptorUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1707 p
->maxPerStageDescriptorUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1708 p
->maxPerStageDescriptorUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1709 p
->maxPerStageDescriptorUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1710 p
->maxPerStageUpdateAfterBindResources
= max_descriptor_set_size
;
1711 p
->maxDescriptorSetUpdateAfterBindSamplers
= max_descriptor_set_size
;
1712 p
->maxDescriptorSetUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1713 p
->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic
= MAX_DYNAMIC_UNIFORM_BUFFERS
;
1714 p
->maxDescriptorSetUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1715 p
->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic
= MAX_DYNAMIC_STORAGE_BUFFERS
;
1716 p
->maxDescriptorSetUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1717 p
->maxDescriptorSetUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1718 p
->maxDescriptorSetUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1720 /* We support all of the depth resolve modes */
1721 p
->supportedDepthResolveModes
= VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
|
1722 VK_RESOLVE_MODE_AVERAGE_BIT_KHR
|
1723 VK_RESOLVE_MODE_MIN_BIT_KHR
|
1724 VK_RESOLVE_MODE_MAX_BIT_KHR
;
1726 /* Average doesn't make sense for stencil so we don't support that */
1727 p
->supportedStencilResolveModes
= VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
|
1728 VK_RESOLVE_MODE_MIN_BIT_KHR
|
1729 VK_RESOLVE_MODE_MAX_BIT_KHR
;
1731 p
->independentResolveNone
= true;
1732 p
->independentResolve
= true;
1734 /* GFX6-8 only support single channel min/max filter. */
1735 p
->filterMinmaxImageComponentMapping
= pdevice
->rad_info
.chip_class
>= GFX9
;
1736 p
->filterMinmaxSingleComponentFormats
= true;
1738 p
->maxTimelineSemaphoreValueDifference
= UINT64_MAX
;
1740 p
->framebufferIntegerColorSampleCounts
= VK_SAMPLE_COUNT_1_BIT
;
1743 void radv_GetPhysicalDeviceProperties2(
1744 VkPhysicalDevice physicalDevice
,
1745 VkPhysicalDeviceProperties2
*pProperties
)
1747 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1748 radv_GetPhysicalDeviceProperties(physicalDevice
, &pProperties
->properties
);
1750 VkPhysicalDeviceVulkan11Properties core_1_1
= {
1751 .sType
= VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES
,
1753 radv_get_physical_device_properties_1_1(pdevice
, &core_1_1
);
1755 VkPhysicalDeviceVulkan12Properties core_1_2
= {
1756 .sType
= VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES
,
1758 radv_get_physical_device_properties_1_2(pdevice
, &core_1_2
);
1760 #define CORE_RENAMED_PROPERTY(major, minor, ext_property, core_property) \
1761 memcpy(&properties->ext_property, &core_##major##_##minor.core_property, \
1762 sizeof(core_##major##_##minor.core_property))
1764 #define CORE_PROPERTY(major, minor, property) \
1765 CORE_RENAMED_PROPERTY(major, minor, property, property)
1767 vk_foreach_struct(ext
, pProperties
->pNext
) {
1768 switch (ext
->sType
) {
1769 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR
: {
1770 VkPhysicalDevicePushDescriptorPropertiesKHR
*properties
=
1771 (VkPhysicalDevicePushDescriptorPropertiesKHR
*) ext
;
1772 properties
->maxPushDescriptors
= MAX_PUSH_DESCRIPTORS
;
1775 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES
: {
1776 VkPhysicalDeviceIDProperties
*properties
= (VkPhysicalDeviceIDProperties
*)ext
;
1777 CORE_PROPERTY(1, 1, deviceUUID
);
1778 CORE_PROPERTY(1, 1, driverUUID
);
1779 CORE_PROPERTY(1, 1, deviceLUID
);
1780 CORE_PROPERTY(1, 1, deviceLUIDValid
);
1783 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES
: {
1784 VkPhysicalDeviceMultiviewProperties
*properties
= (VkPhysicalDeviceMultiviewProperties
*)ext
;
1785 CORE_PROPERTY(1, 1, maxMultiviewViewCount
);
1786 CORE_PROPERTY(1, 1, maxMultiviewInstanceIndex
);
1789 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES
: {
1790 VkPhysicalDevicePointClippingProperties
*properties
=
1791 (VkPhysicalDevicePointClippingProperties
*)ext
;
1792 CORE_PROPERTY(1, 1, pointClippingBehavior
);
1795 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT
: {
1796 VkPhysicalDeviceDiscardRectanglePropertiesEXT
*properties
=
1797 (VkPhysicalDeviceDiscardRectanglePropertiesEXT
*)ext
;
1798 properties
->maxDiscardRectangles
= MAX_DISCARD_RECTANGLES
;
1801 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT
: {
1802 VkPhysicalDeviceExternalMemoryHostPropertiesEXT
*properties
=
1803 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT
*) ext
;
1804 properties
->minImportedHostPointerAlignment
= 4096;
1807 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES
: {
1808 VkPhysicalDeviceSubgroupProperties
*properties
=
1809 (VkPhysicalDeviceSubgroupProperties
*)ext
;
1810 CORE_PROPERTY(1, 1, subgroupSize
);
1811 CORE_RENAMED_PROPERTY(1, 1, supportedStages
,
1812 subgroupSupportedStages
);
1813 CORE_RENAMED_PROPERTY(1, 1, supportedOperations
,
1814 subgroupSupportedOperations
);
1815 CORE_RENAMED_PROPERTY(1, 1, quadOperationsInAllStages
,
1816 subgroupQuadOperationsInAllStages
);
1819 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES
: {
1820 VkPhysicalDeviceMaintenance3Properties
*properties
=
1821 (VkPhysicalDeviceMaintenance3Properties
*)ext
;
1822 CORE_PROPERTY(1, 1, maxPerSetDescriptors
);
1823 CORE_PROPERTY(1, 1, maxMemoryAllocationSize
);
1826 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES
: {
1827 VkPhysicalDeviceSamplerFilterMinmaxProperties
*properties
=
1828 (VkPhysicalDeviceSamplerFilterMinmaxProperties
*)ext
;
1829 CORE_PROPERTY(1, 2, filterMinmaxImageComponentMapping
);
1830 CORE_PROPERTY(1, 2, filterMinmaxSingleComponentFormats
);
1833 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD
: {
1834 VkPhysicalDeviceShaderCorePropertiesAMD
*properties
=
1835 (VkPhysicalDeviceShaderCorePropertiesAMD
*)ext
;
1837 /* Shader engines. */
1838 properties
->shaderEngineCount
=
1839 pdevice
->rad_info
.max_se
;
1840 properties
->shaderArraysPerEngineCount
=
1841 pdevice
->rad_info
.max_sh_per_se
;
1842 properties
->computeUnitsPerShaderArray
=
1843 pdevice
->rad_info
.min_good_cu_per_sa
;
1844 properties
->simdPerComputeUnit
=
1845 pdevice
->rad_info
.num_simd_per_compute_unit
;
1846 properties
->wavefrontsPerSimd
=
1847 pdevice
->rad_info
.max_wave64_per_simd
;
1848 properties
->wavefrontSize
= 64;
1851 properties
->sgprsPerSimd
=
1852 pdevice
->rad_info
.num_physical_sgprs_per_simd
;
1853 properties
->minSgprAllocation
=
1854 pdevice
->rad_info
.min_sgpr_alloc
;
1855 properties
->maxSgprAllocation
=
1856 pdevice
->rad_info
.max_sgpr_alloc
;
1857 properties
->sgprAllocationGranularity
=
1858 pdevice
->rad_info
.sgpr_alloc_granularity
;
1861 properties
->vgprsPerSimd
=
1862 pdevice
->rad_info
.num_physical_wave64_vgprs_per_simd
;
1863 properties
->minVgprAllocation
=
1864 pdevice
->rad_info
.min_wave64_vgpr_alloc
;
1865 properties
->maxVgprAllocation
=
1866 pdevice
->rad_info
.max_vgpr_alloc
;
1867 properties
->vgprAllocationGranularity
=
1868 pdevice
->rad_info
.wave64_vgpr_alloc_granularity
;
1871 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_2_AMD
: {
1872 VkPhysicalDeviceShaderCoreProperties2AMD
*properties
=
1873 (VkPhysicalDeviceShaderCoreProperties2AMD
*)ext
;
1875 properties
->shaderCoreFeatures
= 0;
1876 properties
->activeComputeUnitCount
=
1877 pdevice
->rad_info
.num_good_compute_units
;
1880 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT
: {
1881 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT
*properties
=
1882 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT
*)ext
;
1883 properties
->maxVertexAttribDivisor
= UINT32_MAX
;
1886 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES
: {
1887 VkPhysicalDeviceDescriptorIndexingProperties
*properties
=
1888 (VkPhysicalDeviceDescriptorIndexingProperties
*)ext
;
1889 CORE_PROPERTY(1, 2, maxUpdateAfterBindDescriptorsInAllPools
);
1890 CORE_PROPERTY(1, 2, shaderUniformBufferArrayNonUniformIndexingNative
);
1891 CORE_PROPERTY(1, 2, shaderSampledImageArrayNonUniformIndexingNative
);
1892 CORE_PROPERTY(1, 2, shaderStorageBufferArrayNonUniformIndexingNative
);
1893 CORE_PROPERTY(1, 2, shaderStorageImageArrayNonUniformIndexingNative
);
1894 CORE_PROPERTY(1, 2, shaderInputAttachmentArrayNonUniformIndexingNative
);
1895 CORE_PROPERTY(1, 2, robustBufferAccessUpdateAfterBind
);
1896 CORE_PROPERTY(1, 2, quadDivergentImplicitLod
);
1897 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSamplers
);
1898 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindUniformBuffers
);
1899 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageBuffers
);
1900 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSampledImages
);
1901 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageImages
);
1902 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindInputAttachments
);
1903 CORE_PROPERTY(1, 2, maxPerStageUpdateAfterBindResources
);
1904 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSamplers
);
1905 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffers
);
1906 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffersDynamic
);
1907 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffers
);
1908 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffersDynamic
);
1909 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSampledImages
);
1910 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageImages
);
1911 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindInputAttachments
);
1914 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES
: {
1915 VkPhysicalDeviceProtectedMemoryProperties
*properties
=
1916 (VkPhysicalDeviceProtectedMemoryProperties
*)ext
;
1917 CORE_PROPERTY(1, 1, protectedNoFault
);
1920 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT
: {
1921 VkPhysicalDeviceConservativeRasterizationPropertiesEXT
*properties
=
1922 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT
*)ext
;
1923 properties
->primitiveOverestimationSize
= 0;
1924 properties
->maxExtraPrimitiveOverestimationSize
= 0;
1925 properties
->extraPrimitiveOverestimationSizeGranularity
= 0;
1926 properties
->primitiveUnderestimation
= false;
1927 properties
->conservativePointAndLineRasterization
= false;
1928 properties
->degenerateTrianglesRasterized
= false;
1929 properties
->degenerateLinesRasterized
= false;
1930 properties
->fullyCoveredFragmentShaderInputVariable
= false;
1931 properties
->conservativeRasterizationPostDepthCoverage
= false;
1934 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT
: {
1935 VkPhysicalDevicePCIBusInfoPropertiesEXT
*properties
=
1936 (VkPhysicalDevicePCIBusInfoPropertiesEXT
*)ext
;
1937 properties
->pciDomain
= pdevice
->bus_info
.domain
;
1938 properties
->pciBus
= pdevice
->bus_info
.bus
;
1939 properties
->pciDevice
= pdevice
->bus_info
.dev
;
1940 properties
->pciFunction
= pdevice
->bus_info
.func
;
1943 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES
: {
1944 VkPhysicalDeviceDriverProperties
*properties
=
1945 (VkPhysicalDeviceDriverProperties
*) ext
;
1946 CORE_PROPERTY(1, 2, driverID
);
1947 CORE_PROPERTY(1, 2, driverName
);
1948 CORE_PROPERTY(1, 2, driverInfo
);
1949 CORE_PROPERTY(1, 2, conformanceVersion
);
1952 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT
: {
1953 VkPhysicalDeviceTransformFeedbackPropertiesEXT
*properties
=
1954 (VkPhysicalDeviceTransformFeedbackPropertiesEXT
*)ext
;
1955 properties
->maxTransformFeedbackStreams
= MAX_SO_STREAMS
;
1956 properties
->maxTransformFeedbackBuffers
= MAX_SO_BUFFERS
;
1957 properties
->maxTransformFeedbackBufferSize
= UINT32_MAX
;
1958 properties
->maxTransformFeedbackStreamDataSize
= 512;
1959 properties
->maxTransformFeedbackBufferDataSize
= UINT32_MAX
;
1960 properties
->maxTransformFeedbackBufferDataStride
= 512;
1961 properties
->transformFeedbackQueries
= !pdevice
->use_ngg_streamout
;
1962 properties
->transformFeedbackStreamsLinesTriangles
= !pdevice
->use_ngg_streamout
;
1963 properties
->transformFeedbackRasterizationStreamSelect
= false;
1964 properties
->transformFeedbackDraw
= true;
1967 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT
: {
1968 VkPhysicalDeviceInlineUniformBlockPropertiesEXT
*props
=
1969 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT
*)ext
;
1971 props
->maxInlineUniformBlockSize
= MAX_INLINE_UNIFORM_BLOCK_SIZE
;
1972 props
->maxPerStageDescriptorInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_SETS
;
1973 props
->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_SETS
;
1974 props
->maxDescriptorSetInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_COUNT
;
1975 props
->maxDescriptorSetUpdateAfterBindInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_COUNT
;
1978 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT
: {
1979 VkPhysicalDeviceSampleLocationsPropertiesEXT
*properties
=
1980 (VkPhysicalDeviceSampleLocationsPropertiesEXT
*)ext
;
1981 properties
->sampleLocationSampleCounts
= VK_SAMPLE_COUNT_2_BIT
|
1982 VK_SAMPLE_COUNT_4_BIT
|
1983 VK_SAMPLE_COUNT_8_BIT
;
1984 properties
->maxSampleLocationGridSize
= (VkExtent2D
){ 2 , 2 };
1985 properties
->sampleLocationCoordinateRange
[0] = 0.0f
;
1986 properties
->sampleLocationCoordinateRange
[1] = 0.9375f
;
1987 properties
->sampleLocationSubPixelBits
= 4;
1988 properties
->variableSampleLocations
= false;
1991 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES
: {
1992 VkPhysicalDeviceDepthStencilResolveProperties
*properties
=
1993 (VkPhysicalDeviceDepthStencilResolveProperties
*)ext
;
1994 CORE_PROPERTY(1, 2, supportedDepthResolveModes
);
1995 CORE_PROPERTY(1, 2, supportedStencilResolveModes
);
1996 CORE_PROPERTY(1, 2, independentResolveNone
);
1997 CORE_PROPERTY(1, 2, independentResolve
);
2000 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_PROPERTIES_EXT
: {
2001 VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT
*properties
=
2002 (VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT
*)ext
;
2003 properties
->storageTexelBufferOffsetAlignmentBytes
= 4;
2004 properties
->storageTexelBufferOffsetSingleTexelAlignment
= true;
2005 properties
->uniformTexelBufferOffsetAlignmentBytes
= 4;
2006 properties
->uniformTexelBufferOffsetSingleTexelAlignment
= true;
2009 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT_CONTROLS_PROPERTIES
: {
2010 VkPhysicalDeviceFloatControlsProperties
*properties
=
2011 (VkPhysicalDeviceFloatControlsProperties
*)ext
;
2012 CORE_PROPERTY(1, 2, denormBehaviorIndependence
);
2013 CORE_PROPERTY(1, 2, roundingModeIndependence
);
2014 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat16
);
2015 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat16
);
2016 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat16
);
2017 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat16
);
2018 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat16
);
2019 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat32
);
2020 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat32
);
2021 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat32
);
2022 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat32
);
2023 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat32
);
2024 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat64
);
2025 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat64
);
2026 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat64
);
2027 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat64
);
2028 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat64
);
2031 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_PROPERTIES
: {
2032 VkPhysicalDeviceTimelineSemaphoreProperties
*properties
=
2033 (VkPhysicalDeviceTimelineSemaphoreProperties
*) ext
;
2034 CORE_PROPERTY(1, 2, maxTimelineSemaphoreValueDifference
);
2037 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_PROPERTIES_EXT
: {
2038 VkPhysicalDeviceSubgroupSizeControlPropertiesEXT
*props
=
2039 (VkPhysicalDeviceSubgroupSizeControlPropertiesEXT
*)ext
;
2040 props
->minSubgroupSize
= 64;
2041 props
->maxSubgroupSize
= 64;
2042 props
->maxComputeWorkgroupSubgroups
= UINT32_MAX
;
2043 props
->requiredSubgroupSizeStages
= 0;
2045 if (pdevice
->rad_info
.chip_class
>= GFX10
) {
2046 /* Only GFX10+ supports wave32. */
2047 props
->minSubgroupSize
= 32;
2048 props
->requiredSubgroupSizeStages
= VK_SHADER_STAGE_COMPUTE_BIT
;
2052 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES
:
2053 radv_get_physical_device_properties_1_1(pdevice
, (void *)ext
);
2055 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES
:
2056 radv_get_physical_device_properties_1_2(pdevice
, (void *)ext
);
2058 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_PROPERTIES_EXT
: {
2059 VkPhysicalDeviceLineRasterizationPropertiesEXT
*props
=
2060 (VkPhysicalDeviceLineRasterizationPropertiesEXT
*)ext
;
2061 props
->lineSubPixelPrecisionBits
= 4;
2064 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ROBUSTNESS_2_PROPERTIES_EXT
: {
2065 VkPhysicalDeviceRobustness2PropertiesEXT
*properties
=
2066 (VkPhysicalDeviceRobustness2PropertiesEXT
*)ext
;
2067 properties
->robustStorageBufferAccessSizeAlignment
= 4;
2068 properties
->robustUniformBufferAccessSizeAlignment
= 4;
2071 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_PROPERTIES_EXT
: {
2072 VkPhysicalDeviceCustomBorderColorPropertiesEXT
*props
=
2073 (VkPhysicalDeviceCustomBorderColorPropertiesEXT
*)ext
;
2074 props
->maxCustomBorderColorSamplers
= RADV_BORDER_COLOR_COUNT
;
2083 static void radv_get_physical_device_queue_family_properties(
2084 struct radv_physical_device
* pdevice
,
2086 VkQueueFamilyProperties
** pQueueFamilyProperties
)
2088 int num_queue_families
= 1;
2090 if (pdevice
->rad_info
.num_rings
[RING_COMPUTE
] > 0 &&
2091 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
))
2092 num_queue_families
++;
2094 if (pQueueFamilyProperties
== NULL
) {
2095 *pCount
= num_queue_families
;
2104 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
2105 .queueFlags
= VK_QUEUE_GRAPHICS_BIT
|
2106 VK_QUEUE_COMPUTE_BIT
|
2107 VK_QUEUE_TRANSFER_BIT
|
2108 VK_QUEUE_SPARSE_BINDING_BIT
,
2110 .timestampValidBits
= 64,
2111 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
2116 if (pdevice
->rad_info
.num_rings
[RING_COMPUTE
] > 0 &&
2117 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
)) {
2118 if (*pCount
> idx
) {
2119 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
2120 .queueFlags
= VK_QUEUE_COMPUTE_BIT
|
2121 VK_QUEUE_TRANSFER_BIT
|
2122 VK_QUEUE_SPARSE_BINDING_BIT
,
2123 .queueCount
= pdevice
->rad_info
.num_rings
[RING_COMPUTE
],
2124 .timestampValidBits
= 64,
2125 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
2133 void radv_GetPhysicalDeviceQueueFamilyProperties(
2134 VkPhysicalDevice physicalDevice
,
2136 VkQueueFamilyProperties
* pQueueFamilyProperties
)
2138 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
2139 if (!pQueueFamilyProperties
) {
2140 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
2143 VkQueueFamilyProperties
*properties
[] = {
2144 pQueueFamilyProperties
+ 0,
2145 pQueueFamilyProperties
+ 1,
2146 pQueueFamilyProperties
+ 2,
2148 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
2149 assert(*pCount
<= 3);
2152 void radv_GetPhysicalDeviceQueueFamilyProperties2(
2153 VkPhysicalDevice physicalDevice
,
2155 VkQueueFamilyProperties2
*pQueueFamilyProperties
)
2157 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
2158 if (!pQueueFamilyProperties
) {
2159 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
2162 VkQueueFamilyProperties
*properties
[] = {
2163 &pQueueFamilyProperties
[0].queueFamilyProperties
,
2164 &pQueueFamilyProperties
[1].queueFamilyProperties
,
2165 &pQueueFamilyProperties
[2].queueFamilyProperties
,
2167 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
2168 assert(*pCount
<= 3);
2171 void radv_GetPhysicalDeviceMemoryProperties(
2172 VkPhysicalDevice physicalDevice
,
2173 VkPhysicalDeviceMemoryProperties
*pMemoryProperties
)
2175 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
2177 *pMemoryProperties
= physical_device
->memory_properties
;
2181 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice
,
2182 VkPhysicalDeviceMemoryBudgetPropertiesEXT
*memoryBudget
)
2184 RADV_FROM_HANDLE(radv_physical_device
, device
, physicalDevice
);
2185 VkPhysicalDeviceMemoryProperties
*memory_properties
= &device
->memory_properties
;
2186 uint64_t visible_vram_size
= radv_get_visible_vram_size(device
);
2187 uint64_t vram_size
= radv_get_vram_size(device
);
2188 uint64_t gtt_size
= device
->rad_info
.gart_size
;
2189 uint64_t heap_budget
, heap_usage
;
2191 /* For all memory heaps, the computation of budget is as follow:
2192 * heap_budget = heap_size - global_heap_usage + app_heap_usage
2194 * The Vulkan spec 1.1.97 says that the budget should include any
2195 * currently allocated device memory.
2197 * Note that the application heap usages are not really accurate (eg.
2198 * in presence of shared buffers).
2200 for (int i
= 0; i
< device
->memory_properties
.memoryTypeCount
; i
++) {
2201 uint32_t heap_index
= device
->memory_properties
.memoryTypes
[i
].heapIndex
;
2203 if ((device
->memory_domains
[i
] & RADEON_DOMAIN_VRAM
) && (device
->memory_flags
[i
] & RADEON_FLAG_NO_CPU_ACCESS
)) {
2204 heap_usage
= device
->ws
->query_value(device
->ws
,
2205 RADEON_ALLOCATED_VRAM
);
2207 heap_budget
= vram_size
-
2208 device
->ws
->query_value(device
->ws
, RADEON_VRAM_USAGE
) +
2211 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
2212 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
2213 } else if (device
->memory_domains
[i
] & RADEON_DOMAIN_VRAM
) {
2214 heap_usage
= device
->ws
->query_value(device
->ws
,
2215 RADEON_ALLOCATED_VRAM_VIS
);
2217 heap_budget
= visible_vram_size
-
2218 device
->ws
->query_value(device
->ws
, RADEON_VRAM_VIS_USAGE
) +
2221 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
2222 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
2224 assert(device
->memory_domains
[i
] & RADEON_DOMAIN_GTT
);
2226 heap_usage
= device
->ws
->query_value(device
->ws
,
2227 RADEON_ALLOCATED_GTT
);
2229 heap_budget
= gtt_size
-
2230 device
->ws
->query_value(device
->ws
, RADEON_GTT_USAGE
) +
2233 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
2234 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
2238 /* The heapBudget and heapUsage values must be zero for array elements
2239 * greater than or equal to
2240 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
2242 for (uint32_t i
= memory_properties
->memoryHeapCount
; i
< VK_MAX_MEMORY_HEAPS
; i
++) {
2243 memoryBudget
->heapBudget
[i
] = 0;
2244 memoryBudget
->heapUsage
[i
] = 0;
2248 void radv_GetPhysicalDeviceMemoryProperties2(
2249 VkPhysicalDevice physicalDevice
,
2250 VkPhysicalDeviceMemoryProperties2
*pMemoryProperties
)
2252 radv_GetPhysicalDeviceMemoryProperties(physicalDevice
,
2253 &pMemoryProperties
->memoryProperties
);
2255 VkPhysicalDeviceMemoryBudgetPropertiesEXT
*memory_budget
=
2256 vk_find_struct(pMemoryProperties
->pNext
,
2257 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT
);
2259 radv_get_memory_budget_properties(physicalDevice
, memory_budget
);
2262 VkResult
radv_GetMemoryHostPointerPropertiesEXT(
2264 VkExternalMemoryHandleTypeFlagBits handleType
,
2265 const void *pHostPointer
,
2266 VkMemoryHostPointerPropertiesEXT
*pMemoryHostPointerProperties
)
2268 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2272 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT
: {
2273 const struct radv_physical_device
*physical_device
= device
->physical_device
;
2274 uint32_t memoryTypeBits
= 0;
2275 for (int i
= 0; i
< physical_device
->memory_properties
.memoryTypeCount
; i
++) {
2276 if (physical_device
->memory_domains
[i
] == RADEON_DOMAIN_GTT
&&
2277 !(physical_device
->memory_flags
[i
] & RADEON_FLAG_GTT_WC
)) {
2278 memoryTypeBits
= (1 << i
);
2282 pMemoryHostPointerProperties
->memoryTypeBits
= memoryTypeBits
;
2286 return VK_ERROR_INVALID_EXTERNAL_HANDLE
;
2290 static enum radeon_ctx_priority
2291 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT
*pObj
)
2293 /* Default to MEDIUM when a specific global priority isn't requested */
2295 return RADEON_CTX_PRIORITY_MEDIUM
;
2297 switch(pObj
->globalPriority
) {
2298 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT
:
2299 return RADEON_CTX_PRIORITY_REALTIME
;
2300 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT
:
2301 return RADEON_CTX_PRIORITY_HIGH
;
2302 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT
:
2303 return RADEON_CTX_PRIORITY_MEDIUM
;
2304 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT
:
2305 return RADEON_CTX_PRIORITY_LOW
;
2307 unreachable("Illegal global priority value");
2308 return RADEON_CTX_PRIORITY_INVALID
;
2313 radv_queue_init(struct radv_device
*device
, struct radv_queue
*queue
,
2314 uint32_t queue_family_index
, int idx
,
2315 VkDeviceQueueCreateFlags flags
,
2316 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
)
2318 queue
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
2319 queue
->device
= device
;
2320 queue
->queue_family_index
= queue_family_index
;
2321 queue
->queue_idx
= idx
;
2322 queue
->priority
= radv_get_queue_global_priority(global_priority
);
2323 queue
->flags
= flags
;
2324 queue
->hw_ctx
= NULL
;
2326 VkResult result
= device
->ws
->ctx_create(device
->ws
, queue
->priority
, &queue
->hw_ctx
);
2327 if (result
!= VK_SUCCESS
)
2328 return vk_error(device
->instance
, result
);
2330 list_inithead(&queue
->pending_submissions
);
2331 pthread_mutex_init(&queue
->pending_mutex
, NULL
);
2333 pthread_mutex_init(&queue
->thread_mutex
, NULL
);
2334 queue
->thread_submission
= NULL
;
2335 queue
->thread_running
= queue
->thread_exit
= false;
2336 result
= radv_create_pthread_cond(&queue
->thread_cond
);
2337 if (result
!= VK_SUCCESS
)
2338 return vk_error(device
->instance
, result
);
2344 radv_queue_finish(struct radv_queue
*queue
)
2346 if (queue
->thread_running
) {
2347 p_atomic_set(&queue
->thread_exit
, true);
2348 pthread_cond_broadcast(&queue
->thread_cond
);
2349 pthread_join(queue
->submission_thread
, NULL
);
2351 pthread_cond_destroy(&queue
->thread_cond
);
2352 pthread_mutex_destroy(&queue
->pending_mutex
);
2353 pthread_mutex_destroy(&queue
->thread_mutex
);
2356 queue
->device
->ws
->ctx_destroy(queue
->hw_ctx
);
2358 if (queue
->initial_full_flush_preamble_cs
)
2359 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
2360 if (queue
->initial_preamble_cs
)
2361 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
2362 if (queue
->continue_preamble_cs
)
2363 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
2364 if (queue
->descriptor_bo
)
2365 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
2366 if (queue
->scratch_bo
)
2367 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
2368 if (queue
->esgs_ring_bo
)
2369 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
2370 if (queue
->gsvs_ring_bo
)
2371 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
2372 if (queue
->tess_rings_bo
)
2373 queue
->device
->ws
->buffer_destroy(queue
->tess_rings_bo
);
2375 queue
->device
->ws
->buffer_destroy(queue
->gds_bo
);
2376 if (queue
->gds_oa_bo
)
2377 queue
->device
->ws
->buffer_destroy(queue
->gds_oa_bo
);
2378 if (queue
->compute_scratch_bo
)
2379 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
2383 radv_bo_list_init(struct radv_bo_list
*bo_list
)
2385 pthread_mutex_init(&bo_list
->mutex
, NULL
);
2386 bo_list
->list
.count
= bo_list
->capacity
= 0;
2387 bo_list
->list
.bos
= NULL
;
2391 radv_bo_list_finish(struct radv_bo_list
*bo_list
)
2393 free(bo_list
->list
.bos
);
2394 pthread_mutex_destroy(&bo_list
->mutex
);
2397 VkResult
radv_bo_list_add(struct radv_device
*device
,
2398 struct radeon_winsys_bo
*bo
)
2400 struct radv_bo_list
*bo_list
= &device
->bo_list
;
2405 if (unlikely(!device
->use_global_bo_list
))
2408 pthread_mutex_lock(&bo_list
->mutex
);
2409 if (bo_list
->list
.count
== bo_list
->capacity
) {
2410 unsigned capacity
= MAX2(4, bo_list
->capacity
* 2);
2411 void *data
= realloc(bo_list
->list
.bos
, capacity
* sizeof(struct radeon_winsys_bo
*));
2414 pthread_mutex_unlock(&bo_list
->mutex
);
2415 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2418 bo_list
->list
.bos
= (struct radeon_winsys_bo
**)data
;
2419 bo_list
->capacity
= capacity
;
2422 bo_list
->list
.bos
[bo_list
->list
.count
++] = bo
;
2423 pthread_mutex_unlock(&bo_list
->mutex
);
2427 void radv_bo_list_remove(struct radv_device
*device
,
2428 struct radeon_winsys_bo
*bo
)
2430 struct radv_bo_list
*bo_list
= &device
->bo_list
;
2435 if (unlikely(!device
->use_global_bo_list
))
2438 pthread_mutex_lock(&bo_list
->mutex
);
2439 /* Loop the list backwards so we find the most recently added
2441 for(unsigned i
= bo_list
->list
.count
; i
-- > 0;) {
2442 if (bo_list
->list
.bos
[i
] == bo
) {
2443 bo_list
->list
.bos
[i
] = bo_list
->list
.bos
[bo_list
->list
.count
- 1];
2444 --bo_list
->list
.count
;
2448 pthread_mutex_unlock(&bo_list
->mutex
);
2452 radv_device_init_gs_info(struct radv_device
*device
)
2454 device
->gs_table_depth
= ac_get_gs_table_depth(device
->physical_device
->rad_info
.chip_class
,
2455 device
->physical_device
->rad_info
.family
);
2458 static int radv_get_device_extension_index(const char *name
)
2460 for (unsigned i
= 0; i
< RADV_DEVICE_EXTENSION_COUNT
; ++i
) {
2461 if (strcmp(name
, radv_device_extensions
[i
].extensionName
) == 0)
2468 radv_get_int_debug_option(const char *name
, int default_value
)
2475 result
= default_value
;
2479 result
= strtol(str
, &endptr
, 0);
2480 if (str
== endptr
) {
2481 /* No digits founs. */
2482 result
= default_value
;
2490 radv_device_init_dispatch(struct radv_device
*device
)
2492 const struct radv_instance
*instance
= device
->physical_device
->instance
;
2493 const struct radv_device_dispatch_table
*dispatch_table_layer
= NULL
;
2494 bool unchecked
= instance
->debug_flags
& RADV_DEBUG_ALL_ENTRYPOINTS
;
2495 int radv_thread_trace
= radv_get_int_debug_option("RADV_THREAD_TRACE", -1);
2497 if (radv_thread_trace
>= 0) {
2498 /* Use device entrypoints from the SQTT layer if enabled. */
2499 dispatch_table_layer
= &sqtt_device_dispatch_table
;
2502 for (unsigned i
= 0; i
< ARRAY_SIZE(device
->dispatch
.entrypoints
); i
++) {
2503 /* Vulkan requires that entrypoints for extensions which have not been
2504 * enabled must not be advertised.
2507 !radv_device_entrypoint_is_enabled(i
, instance
->apiVersion
,
2508 &instance
->enabled_extensions
,
2509 &device
->enabled_extensions
)) {
2510 device
->dispatch
.entrypoints
[i
] = NULL
;
2511 } else if (dispatch_table_layer
&&
2512 dispatch_table_layer
->entrypoints
[i
]) {
2513 device
->dispatch
.entrypoints
[i
] =
2514 dispatch_table_layer
->entrypoints
[i
];
2516 device
->dispatch
.entrypoints
[i
] =
2517 radv_device_dispatch_table
.entrypoints
[i
];
2523 radv_create_pthread_cond(pthread_cond_t
*cond
)
2525 pthread_condattr_t condattr
;
2526 if (pthread_condattr_init(&condattr
)) {
2527 return VK_ERROR_INITIALIZATION_FAILED
;
2530 if (pthread_condattr_setclock(&condattr
, CLOCK_MONOTONIC
)) {
2531 pthread_condattr_destroy(&condattr
);
2532 return VK_ERROR_INITIALIZATION_FAILED
;
2534 if (pthread_cond_init(cond
, &condattr
)) {
2535 pthread_condattr_destroy(&condattr
);
2536 return VK_ERROR_INITIALIZATION_FAILED
;
2538 pthread_condattr_destroy(&condattr
);
2543 check_physical_device_features(VkPhysicalDevice physicalDevice
,
2544 const VkPhysicalDeviceFeatures
*features
)
2546 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
2547 VkPhysicalDeviceFeatures supported_features
;
2548 radv_GetPhysicalDeviceFeatures(physicalDevice
, &supported_features
);
2549 VkBool32
*supported_feature
= (VkBool32
*)&supported_features
;
2550 VkBool32
*enabled_feature
= (VkBool32
*)features
;
2551 unsigned num_features
= sizeof(VkPhysicalDeviceFeatures
) / sizeof(VkBool32
);
2552 for (uint32_t i
= 0; i
< num_features
; i
++) {
2553 if (enabled_feature
[i
] && !supported_feature
[i
])
2554 return vk_error(physical_device
->instance
, VK_ERROR_FEATURE_NOT_PRESENT
);
2560 static VkResult
radv_device_init_border_color(struct radv_device
*device
)
2562 device
->border_color_data
.bo
=
2563 device
->ws
->buffer_create(device
->ws
,
2564 RADV_BORDER_COLOR_BUFFER_SIZE
,
2567 RADEON_FLAG_CPU_ACCESS
|
2568 RADEON_FLAG_READ_ONLY
|
2569 RADEON_FLAG_NO_INTERPROCESS_SHARING
,
2570 RADV_BO_PRIORITY_SHADER
);
2572 if (device
->border_color_data
.bo
== NULL
)
2573 return vk_error(device
->physical_device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2575 device
->border_color_data
.colors_gpu_ptr
=
2576 device
->ws
->buffer_map(device
->border_color_data
.bo
);
2577 if (!device
->border_color_data
.colors_gpu_ptr
)
2578 return vk_error(device
->physical_device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2579 pthread_mutex_init(&device
->border_color_data
.mutex
, NULL
);
2584 static void radv_device_finish_border_color(struct radv_device
*device
)
2586 if (device
->border_color_data
.bo
) {
2587 device
->ws
->buffer_destroy(device
->border_color_data
.bo
);
2589 pthread_mutex_destroy(&device
->border_color_data
.mutex
);
2594 _radv_device_set_lost(struct radv_device
*device
,
2595 const char *file
, int line
,
2596 const char *msg
, ...)
2601 p_atomic_inc(&device
->lost
);
2604 err
= __vk_errorv(device
->physical_device
->instance
, device
,
2605 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT
,
2606 VK_ERROR_DEVICE_LOST
, file
, line
, msg
, ap
);
2612 VkResult
radv_CreateDevice(
2613 VkPhysicalDevice physicalDevice
,
2614 const VkDeviceCreateInfo
* pCreateInfo
,
2615 const VkAllocationCallbacks
* pAllocator
,
2618 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
2620 struct radv_device
*device
;
2622 bool keep_shader_info
= false;
2623 bool robust_buffer_access
= false;
2624 bool overallocation_disallowed
= false;
2625 bool custom_border_colors
= false;
2627 /* Check enabled features */
2628 if (pCreateInfo
->pEnabledFeatures
) {
2629 result
= check_physical_device_features(physicalDevice
,
2630 pCreateInfo
->pEnabledFeatures
);
2631 if (result
!= VK_SUCCESS
)
2634 if (pCreateInfo
->pEnabledFeatures
->robustBufferAccess
)
2635 robust_buffer_access
= true;
2638 vk_foreach_struct_const(ext
, pCreateInfo
->pNext
) {
2639 switch (ext
->sType
) {
2640 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FEATURES_2
: {
2641 const VkPhysicalDeviceFeatures2
*features
= (const void *)ext
;
2642 result
= check_physical_device_features(physicalDevice
,
2643 &features
->features
);
2644 if (result
!= VK_SUCCESS
)
2647 if (features
->features
.robustBufferAccess
)
2648 robust_buffer_access
= true;
2651 case VK_STRUCTURE_TYPE_DEVICE_MEMORY_OVERALLOCATION_CREATE_INFO_AMD
: {
2652 const VkDeviceMemoryOverallocationCreateInfoAMD
*overallocation
= (const void *)ext
;
2653 if (overallocation
->overallocationBehavior
== VK_MEMORY_OVERALLOCATION_BEHAVIOR_DISALLOWED_AMD
)
2654 overallocation_disallowed
= true;
2657 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_FEATURES_EXT
: {
2658 const VkPhysicalDeviceCustomBorderColorFeaturesEXT
*border_color_features
= (const void *)ext
;
2659 custom_border_colors
= border_color_features
->customBorderColors
;
2667 device
= vk_zalloc2(&physical_device
->instance
->alloc
, pAllocator
,
2669 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
2671 return vk_error(physical_device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2673 vk_device_init(&device
->vk
, pCreateInfo
,
2674 &physical_device
->instance
->alloc
, pAllocator
);
2676 device
->instance
= physical_device
->instance
;
2677 device
->physical_device
= physical_device
;
2679 device
->ws
= physical_device
->ws
;
2681 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
2682 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
2683 int index
= radv_get_device_extension_index(ext_name
);
2684 if (index
< 0 || !physical_device
->supported_extensions
.extensions
[index
]) {
2685 vk_free(&device
->vk
.alloc
, device
);
2686 return vk_error(physical_device
->instance
, VK_ERROR_EXTENSION_NOT_PRESENT
);
2689 device
->enabled_extensions
.extensions
[index
] = true;
2692 radv_device_init_dispatch(device
);
2694 keep_shader_info
= device
->enabled_extensions
.AMD_shader_info
;
2696 /* With update after bind we can't attach bo's to the command buffer
2697 * from the descriptor set anymore, so we have to use a global BO list.
2699 device
->use_global_bo_list
=
2700 (device
->instance
->perftest_flags
& RADV_PERFTEST_BO_LIST
) ||
2701 device
->enabled_extensions
.EXT_descriptor_indexing
||
2702 device
->enabled_extensions
.EXT_buffer_device_address
||
2703 device
->enabled_extensions
.KHR_buffer_device_address
;
2705 device
->robust_buffer_access
= robust_buffer_access
;
2707 mtx_init(&device
->shader_slab_mutex
, mtx_plain
);
2708 list_inithead(&device
->shader_slabs
);
2710 device
->overallocation_disallowed
= overallocation_disallowed
;
2711 mtx_init(&device
->overallocation_mutex
, mtx_plain
);
2713 radv_bo_list_init(&device
->bo_list
);
2715 for (unsigned i
= 0; i
< pCreateInfo
->queueCreateInfoCount
; i
++) {
2716 const VkDeviceQueueCreateInfo
*queue_create
= &pCreateInfo
->pQueueCreateInfos
[i
];
2717 uint32_t qfi
= queue_create
->queueFamilyIndex
;
2718 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
=
2719 vk_find_struct_const(queue_create
->pNext
, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT
);
2721 assert(!global_priority
|| device
->physical_device
->rad_info
.has_ctx_priority
);
2723 device
->queues
[qfi
] = vk_alloc(&device
->vk
.alloc
,
2724 queue_create
->queueCount
* sizeof(struct radv_queue
), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
2725 if (!device
->queues
[qfi
]) {
2726 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2730 memset(device
->queues
[qfi
], 0, queue_create
->queueCount
* sizeof(struct radv_queue
));
2732 device
->queue_count
[qfi
] = queue_create
->queueCount
;
2734 for (unsigned q
= 0; q
< queue_create
->queueCount
; q
++) {
2735 result
= radv_queue_init(device
, &device
->queues
[qfi
][q
],
2736 qfi
, q
, queue_create
->flags
,
2738 if (result
!= VK_SUCCESS
)
2743 device
->pbb_allowed
= device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2744 !(device
->instance
->debug_flags
& RADV_DEBUG_NOBINNING
);
2746 /* Disable DFSM by default. As of 2019-09-15 Talos on Low is still 3% slower on Raven. */
2747 device
->dfsm_allowed
= device
->pbb_allowed
&&
2748 (device
->instance
->perftest_flags
& RADV_PERFTEST_DFSM
);
2750 device
->always_use_syncobj
= device
->physical_device
->rad_info
.has_syncobj_wait_for_submit
;
2752 /* The maximum number of scratch waves. Scratch space isn't divided
2753 * evenly between CUs. The number is only a function of the number of CUs.
2754 * We can decrease the constant to decrease the scratch buffer size.
2756 * sctx->scratch_waves must be >= the maximum possible size of
2757 * 1 threadgroup, so that the hw doesn't hang from being unable
2760 * The recommended value is 4 per CU at most. Higher numbers don't
2761 * bring much benefit, but they still occupy chip resources (think
2762 * async compute). I've seen ~2% performance difference between 4 and 32.
2764 uint32_t max_threads_per_block
= 2048;
2765 device
->scratch_waves
= MAX2(32 * physical_device
->rad_info
.num_good_compute_units
,
2766 max_threads_per_block
/ 64);
2768 device
->dispatch_initiator
= S_00B800_COMPUTE_SHADER_EN(1);
2770 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2771 /* If the KMD allows it (there is a KMD hw register for it),
2772 * allow launching waves out-of-order.
2774 device
->dispatch_initiator
|= S_00B800_ORDER_MODE(1);
2777 radv_device_init_gs_info(device
);
2779 device
->tess_offchip_block_dw_size
=
2780 device
->physical_device
->rad_info
.family
== CHIP_HAWAII
? 4096 : 8192;
2782 if (getenv("RADV_TRACE_FILE")) {
2783 const char *filename
= getenv("RADV_TRACE_FILE");
2785 keep_shader_info
= true;
2787 if (!radv_init_trace(device
))
2790 fprintf(stderr
, "*****************************************************************************\n");
2791 fprintf(stderr
, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
2792 fprintf(stderr
, "*****************************************************************************\n");
2794 fprintf(stderr
, "Trace file will be dumped to %s\n", filename
);
2796 /* Wait for idle after every draw/dispatch to identify the
2799 device
->instance
->debug_flags
|= RADV_DEBUG_SYNC_SHADERS
;
2801 radv_dump_enabled_options(device
, stderr
);
2804 int radv_thread_trace
= radv_get_int_debug_option("RADV_THREAD_TRACE", -1);
2805 if (radv_thread_trace
>= 0) {
2806 fprintf(stderr
, "*************************************************\n");
2807 fprintf(stderr
, "* WARNING: Thread trace support is experimental *\n");
2808 fprintf(stderr
, "*************************************************\n");
2810 if (device
->physical_device
->rad_info
.chip_class
< GFX8
) {
2811 fprintf(stderr
, "GPU hardware not supported: refer to "
2812 "the RGP documentation for the list of "
2813 "supported GPUs!\n");
2817 /* Default buffer size set to 1MB per SE. */
2818 device
->thread_trace_buffer_size
=
2819 radv_get_int_debug_option("RADV_THREAD_TRACE_BUFFER_SIZE", 1024 * 1024);
2820 device
->thread_trace_start_frame
= radv_thread_trace
;
2822 if (!radv_thread_trace_init(device
))
2826 if (getenv("RADV_TRAP_HANDLER")) {
2827 /* TODO: Add support for more hardware. */
2828 assert(device
->physical_device
->rad_info
.chip_class
== GFX8
);
2830 fprintf(stderr
, "**********************************************************************\n");
2831 fprintf(stderr
, "* WARNING: RADV_TRAP_HANDLER is experimental and only for debugging! *\n");
2832 fprintf(stderr
, "**********************************************************************\n");
2834 /* To get the disassembly of the faulty shaders, we have to
2835 * keep some shader info around.
2837 keep_shader_info
= true;
2839 if (!radv_trap_handler_init(device
))
2843 device
->keep_shader_info
= keep_shader_info
;
2844 result
= radv_device_init_meta(device
);
2845 if (result
!= VK_SUCCESS
)
2848 radv_device_init_msaa(device
);
2850 /* If the border color extension is enabled, let's create the buffer we need. */
2851 if (custom_border_colors
) {
2852 result
= radv_device_init_border_color(device
);
2853 if (result
!= VK_SUCCESS
)
2857 for (int family
= 0; family
< RADV_MAX_QUEUE_FAMILIES
; ++family
) {
2858 device
->empty_cs
[family
] = device
->ws
->cs_create(device
->ws
, family
);
2859 if (!device
->empty_cs
[family
])
2863 case RADV_QUEUE_GENERAL
:
2864 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
2865 radeon_emit(device
->empty_cs
[family
], CC0_UPDATE_LOAD_ENABLES(1));
2866 radeon_emit(device
->empty_cs
[family
], CC1_UPDATE_SHADOW_ENABLES(1));
2868 case RADV_QUEUE_COMPUTE
:
2869 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_NOP
, 0, 0));
2870 radeon_emit(device
->empty_cs
[family
], 0);
2874 result
= device
->ws
->cs_finalize(device
->empty_cs
[family
]);
2875 if (result
!= VK_SUCCESS
)
2879 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
2880 cik_create_gfx_config(device
);
2882 VkPipelineCacheCreateInfo ci
;
2883 ci
.sType
= VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO
;
2886 ci
.pInitialData
= NULL
;
2887 ci
.initialDataSize
= 0;
2889 result
= radv_CreatePipelineCache(radv_device_to_handle(device
),
2891 if (result
!= VK_SUCCESS
)
2894 device
->mem_cache
= radv_pipeline_cache_from_handle(pc
);
2896 result
= radv_create_pthread_cond(&device
->timeline_cond
);
2897 if (result
!= VK_SUCCESS
)
2898 goto fail_mem_cache
;
2900 device
->force_aniso
=
2901 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
2902 if (device
->force_aniso
>= 0) {
2903 fprintf(stderr
, "radv: Forcing anisotropy filter to %ix\n",
2904 1 << util_logbase2(device
->force_aniso
));
2907 *pDevice
= radv_device_to_handle(device
);
2911 radv_DestroyPipelineCache(radv_device_to_handle(device
), pc
, NULL
);
2913 radv_device_finish_meta(device
);
2915 radv_bo_list_finish(&device
->bo_list
);
2917 radv_thread_trace_finish(device
);
2919 radv_trap_handler_finish(device
);
2921 if (device
->trace_bo
)
2922 device
->ws
->buffer_destroy(device
->trace_bo
);
2924 if (device
->gfx_init
)
2925 device
->ws
->buffer_destroy(device
->gfx_init
);
2927 radv_device_finish_border_color(device
);
2929 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
2930 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
2931 radv_queue_finish(&device
->queues
[i
][q
]);
2932 if (device
->queue_count
[i
])
2933 vk_free(&device
->vk
.alloc
, device
->queues
[i
]);
2936 vk_free(&device
->vk
.alloc
, device
);
2940 void radv_DestroyDevice(
2942 const VkAllocationCallbacks
* pAllocator
)
2944 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2949 if (device
->trace_bo
)
2950 device
->ws
->buffer_destroy(device
->trace_bo
);
2952 if (device
->gfx_init
)
2953 device
->ws
->buffer_destroy(device
->gfx_init
);
2955 radv_device_finish_border_color(device
);
2957 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
2958 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
2959 radv_queue_finish(&device
->queues
[i
][q
]);
2960 if (device
->queue_count
[i
])
2961 vk_free(&device
->vk
.alloc
, device
->queues
[i
]);
2962 if (device
->empty_cs
[i
])
2963 device
->ws
->cs_destroy(device
->empty_cs
[i
]);
2965 radv_device_finish_meta(device
);
2967 VkPipelineCache pc
= radv_pipeline_cache_to_handle(device
->mem_cache
);
2968 radv_DestroyPipelineCache(radv_device_to_handle(device
), pc
, NULL
);
2970 radv_trap_handler_finish(device
);
2972 radv_destroy_shader_slabs(device
);
2974 pthread_cond_destroy(&device
->timeline_cond
);
2975 radv_bo_list_finish(&device
->bo_list
);
2977 radv_thread_trace_finish(device
);
2979 vk_free(&device
->vk
.alloc
, device
);
2982 VkResult
radv_EnumerateInstanceLayerProperties(
2983 uint32_t* pPropertyCount
,
2984 VkLayerProperties
* pProperties
)
2986 if (pProperties
== NULL
) {
2987 *pPropertyCount
= 0;
2991 /* None supported at this time */
2992 return vk_error(NULL
, VK_ERROR_LAYER_NOT_PRESENT
);
2995 VkResult
radv_EnumerateDeviceLayerProperties(
2996 VkPhysicalDevice physicalDevice
,
2997 uint32_t* pPropertyCount
,
2998 VkLayerProperties
* pProperties
)
3000 if (pProperties
== NULL
) {
3001 *pPropertyCount
= 0;
3005 /* None supported at this time */
3006 return vk_error(NULL
, VK_ERROR_LAYER_NOT_PRESENT
);
3009 void radv_GetDeviceQueue2(
3011 const VkDeviceQueueInfo2
* pQueueInfo
,
3014 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3015 struct radv_queue
*queue
;
3017 queue
= &device
->queues
[pQueueInfo
->queueFamilyIndex
][pQueueInfo
->queueIndex
];
3018 if (pQueueInfo
->flags
!= queue
->flags
) {
3019 /* From the Vulkan 1.1.70 spec:
3021 * "The queue returned by vkGetDeviceQueue2 must have the same
3022 * flags value from this structure as that used at device
3023 * creation time in a VkDeviceQueueCreateInfo instance. If no
3024 * matching flags were specified at device creation time then
3025 * pQueue will return VK_NULL_HANDLE."
3027 *pQueue
= VK_NULL_HANDLE
;
3031 *pQueue
= radv_queue_to_handle(queue
);
3034 void radv_GetDeviceQueue(
3036 uint32_t queueFamilyIndex
,
3037 uint32_t queueIndex
,
3040 const VkDeviceQueueInfo2 info
= (VkDeviceQueueInfo2
) {
3041 .sType
= VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2
,
3042 .queueFamilyIndex
= queueFamilyIndex
,
3043 .queueIndex
= queueIndex
3046 radv_GetDeviceQueue2(_device
, &info
, pQueue
);
3050 fill_geom_tess_rings(struct radv_queue
*queue
,
3052 bool add_sample_positions
,
3053 uint32_t esgs_ring_size
,
3054 struct radeon_winsys_bo
*esgs_ring_bo
,
3055 uint32_t gsvs_ring_size
,
3056 struct radeon_winsys_bo
*gsvs_ring_bo
,
3057 uint32_t tess_factor_ring_size
,
3058 uint32_t tess_offchip_ring_offset
,
3059 uint32_t tess_offchip_ring_size
,
3060 struct radeon_winsys_bo
*tess_rings_bo
)
3062 uint32_t *desc
= &map
[4];
3065 uint64_t esgs_va
= radv_buffer_get_va(esgs_ring_bo
);
3067 /* stride 0, num records - size, add tid, swizzle, elsize4,
3070 desc
[1] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32) |
3071 S_008F04_SWIZZLE_ENABLE(true);
3072 desc
[2] = esgs_ring_size
;
3073 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3074 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3075 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3076 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
3077 S_008F0C_INDEX_STRIDE(3) |
3078 S_008F0C_ADD_TID_ENABLE(1);
3080 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3081 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3082 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) |
3083 S_008F0C_RESOURCE_LEVEL(1);
3085 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3086 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
3087 S_008F0C_ELEMENT_SIZE(1);
3090 /* GS entry for ES->GS ring */
3091 /* stride 0, num records - size, elsize0,
3094 desc
[5] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32);
3095 desc
[6] = esgs_ring_size
;
3096 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3097 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3098 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3099 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3101 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3102 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3103 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) |
3104 S_008F0C_RESOURCE_LEVEL(1);
3106 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3107 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3114 uint64_t gsvs_va
= radv_buffer_get_va(gsvs_ring_bo
);
3116 /* VS entry for GS->VS ring */
3117 /* stride 0, num records - size, elsize0,
3120 desc
[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32);
3121 desc
[2] = gsvs_ring_size
;
3122 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3123 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3124 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3125 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3127 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3128 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3129 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) |
3130 S_008F0C_RESOURCE_LEVEL(1);
3132 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3133 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3136 /* stride gsvs_itemsize, num records 64
3137 elsize 4, index stride 16 */
3138 /* shader will patch stride and desc[2] */
3140 desc
[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32) |
3141 S_008F04_SWIZZLE_ENABLE(1);
3143 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3144 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3145 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3146 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
3147 S_008F0C_INDEX_STRIDE(1) |
3148 S_008F0C_ADD_TID_ENABLE(true);
3150 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3151 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3152 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) |
3153 S_008F0C_RESOURCE_LEVEL(1);
3155 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3156 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
3157 S_008F0C_ELEMENT_SIZE(1);
3164 if (tess_rings_bo
) {
3165 uint64_t tess_va
= radv_buffer_get_va(tess_rings_bo
);
3166 uint64_t tess_offchip_va
= tess_va
+ tess_offchip_ring_offset
;
3169 desc
[1] = S_008F04_BASE_ADDRESS_HI(tess_va
>> 32);
3170 desc
[2] = tess_factor_ring_size
;
3171 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3172 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3173 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3174 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3176 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3177 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3178 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
3179 S_008F0C_RESOURCE_LEVEL(1);
3181 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3182 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3185 desc
[4] = tess_offchip_va
;
3186 desc
[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va
>> 32);
3187 desc
[6] = tess_offchip_ring_size
;
3188 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3189 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3190 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3191 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3193 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3194 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3195 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
3196 S_008F0C_RESOURCE_LEVEL(1);
3198 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3199 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3205 if (add_sample_positions
) {
3206 /* add sample positions after all rings */
3207 memcpy(desc
, queue
->device
->sample_locations_1x
, 8);
3209 memcpy(desc
, queue
->device
->sample_locations_2x
, 16);
3211 memcpy(desc
, queue
->device
->sample_locations_4x
, 32);
3213 memcpy(desc
, queue
->device
->sample_locations_8x
, 64);
3218 radv_get_hs_offchip_param(struct radv_device
*device
, uint32_t *max_offchip_buffers_p
)
3220 bool double_offchip_buffers
= device
->physical_device
->rad_info
.chip_class
>= GFX7
&&
3221 device
->physical_device
->rad_info
.family
!= CHIP_CARRIZO
&&
3222 device
->physical_device
->rad_info
.family
!= CHIP_STONEY
;
3223 unsigned max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
3224 unsigned max_offchip_buffers
;
3225 unsigned offchip_granularity
;
3226 unsigned hs_offchip_param
;
3230 * This must be one less than the maximum number due to a hw limitation.
3231 * Various hardware bugs need thGFX7
3234 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
3235 * Gfx7 should limit max_offchip_buffers to 508
3236 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
3238 * Follow AMDVLK here.
3240 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3241 max_offchip_buffers_per_se
= 256;
3242 } else if (device
->physical_device
->rad_info
.family
== CHIP_VEGA10
||
3243 device
->physical_device
->rad_info
.chip_class
== GFX7
||
3244 device
->physical_device
->rad_info
.chip_class
== GFX6
)
3245 --max_offchip_buffers_per_se
;
3247 max_offchip_buffers
= max_offchip_buffers_per_se
*
3248 device
->physical_device
->rad_info
.max_se
;
3250 /* Hawaii has a bug with offchip buffers > 256 that can be worked
3251 * around by setting 4K granularity.
3253 if (device
->tess_offchip_block_dw_size
== 4096) {
3254 assert(device
->physical_device
->rad_info
.family
== CHIP_HAWAII
);
3255 offchip_granularity
= V_03093C_X_4K_DWORDS
;
3257 assert(device
->tess_offchip_block_dw_size
== 8192);
3258 offchip_granularity
= V_03093C_X_8K_DWORDS
;
3261 switch (device
->physical_device
->rad_info
.chip_class
) {
3263 max_offchip_buffers
= MIN2(max_offchip_buffers
, 126);
3268 max_offchip_buffers
= MIN2(max_offchip_buffers
, 508);
3276 *max_offchip_buffers_p
= max_offchip_buffers
;
3277 if (device
->physical_device
->rad_info
.chip_class
>= GFX10_3
) {
3278 hs_offchip_param
= S_03093C_OFFCHIP_BUFFERING_GFX103(max_offchip_buffers
- 1) |
3279 S_03093C_OFFCHIP_GRANULARITY_GFX103(offchip_granularity
);
3280 } else if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
3281 if (device
->physical_device
->rad_info
.chip_class
>= GFX8
)
3282 --max_offchip_buffers
;
3284 S_03093C_OFFCHIP_BUFFERING_GFX7(max_offchip_buffers
) |
3285 S_03093C_OFFCHIP_GRANULARITY_GFX7(offchip_granularity
);
3288 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
);
3290 return hs_offchip_param
;
3294 radv_emit_gs_ring_sizes(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
3295 struct radeon_winsys_bo
*esgs_ring_bo
,
3296 uint32_t esgs_ring_size
,
3297 struct radeon_winsys_bo
*gsvs_ring_bo
,
3298 uint32_t gsvs_ring_size
)
3300 if (!esgs_ring_bo
&& !gsvs_ring_bo
)
3304 radv_cs_add_buffer(queue
->device
->ws
, cs
, esgs_ring_bo
);
3307 radv_cs_add_buffer(queue
->device
->ws
, cs
, gsvs_ring_bo
);
3309 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
3310 radeon_set_uconfig_reg_seq(cs
, R_030900_VGT_ESGS_RING_SIZE
, 2);
3311 radeon_emit(cs
, esgs_ring_size
>> 8);
3312 radeon_emit(cs
, gsvs_ring_size
>> 8);
3314 radeon_set_config_reg_seq(cs
, R_0088C8_VGT_ESGS_RING_SIZE
, 2);
3315 radeon_emit(cs
, esgs_ring_size
>> 8);
3316 radeon_emit(cs
, gsvs_ring_size
>> 8);
3321 radv_emit_tess_factor_ring(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
3322 unsigned hs_offchip_param
, unsigned tf_ring_size
,
3323 struct radeon_winsys_bo
*tess_rings_bo
)
3330 tf_va
= radv_buffer_get_va(tess_rings_bo
);
3332 radv_cs_add_buffer(queue
->device
->ws
, cs
, tess_rings_bo
);
3334 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
3335 radeon_set_uconfig_reg(cs
, R_030938_VGT_TF_RING_SIZE
,
3336 S_030938_SIZE(tf_ring_size
/ 4));
3337 radeon_set_uconfig_reg(cs
, R_030940_VGT_TF_MEMORY_BASE
,
3340 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3341 radeon_set_uconfig_reg(cs
, R_030984_VGT_TF_MEMORY_BASE_HI_UMD
,
3342 S_030984_BASE_HI(tf_va
>> 40));
3343 } else if (queue
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
3344 radeon_set_uconfig_reg(cs
, R_030944_VGT_TF_MEMORY_BASE_HI
,
3345 S_030944_BASE_HI(tf_va
>> 40));
3347 radeon_set_uconfig_reg(cs
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
3350 radeon_set_config_reg(cs
, R_008988_VGT_TF_RING_SIZE
,
3351 S_008988_SIZE(tf_ring_size
/ 4));
3352 radeon_set_config_reg(cs
, R_0089B8_VGT_TF_MEMORY_BASE
,
3354 radeon_set_config_reg(cs
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
3360 radv_emit_graphics_scratch(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
3361 uint32_t size_per_wave
, uint32_t waves
,
3362 struct radeon_winsys_bo
*scratch_bo
)
3364 if (queue
->queue_family_index
!= RADV_QUEUE_GENERAL
)
3370 radv_cs_add_buffer(queue
->device
->ws
, cs
, scratch_bo
);
3372 radeon_set_context_reg(cs
, R_0286E8_SPI_TMPRING_SIZE
,
3373 S_0286E8_WAVES(waves
) |
3374 S_0286E8_WAVESIZE(round_up_u32(size_per_wave
, 1024)));
3378 radv_emit_compute_scratch(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
3379 uint32_t size_per_wave
, uint32_t waves
,
3380 struct radeon_winsys_bo
*compute_scratch_bo
)
3382 uint64_t scratch_va
;
3384 if (!compute_scratch_bo
)
3387 scratch_va
= radv_buffer_get_va(compute_scratch_bo
);
3389 radv_cs_add_buffer(queue
->device
->ws
, cs
, compute_scratch_bo
);
3391 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
, 2);
3392 radeon_emit(cs
, scratch_va
);
3393 radeon_emit(cs
, S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
3394 S_008F04_SWIZZLE_ENABLE(1));
3396 radeon_set_sh_reg(cs
, R_00B860_COMPUTE_TMPRING_SIZE
,
3397 S_00B860_WAVES(waves
) |
3398 S_00B860_WAVESIZE(round_up_u32(size_per_wave
, 1024)));
3402 radv_emit_global_shader_pointers(struct radv_queue
*queue
,
3403 struct radeon_cmdbuf
*cs
,
3404 struct radeon_winsys_bo
*descriptor_bo
)
3411 va
= radv_buffer_get_va(descriptor_bo
);
3413 radv_cs_add_buffer(queue
->device
->ws
, cs
, descriptor_bo
);
3415 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3416 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
3417 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
3418 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
,
3419 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
};
3421 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
3422 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
3425 } else if (queue
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
3426 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
3427 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
3428 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
,
3429 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
};
3431 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
3432 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
3436 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
3437 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
3438 R_00B230_SPI_SHADER_USER_DATA_GS_0
,
3439 R_00B330_SPI_SHADER_USER_DATA_ES_0
,
3440 R_00B430_SPI_SHADER_USER_DATA_HS_0
,
3441 R_00B530_SPI_SHADER_USER_DATA_LS_0
};
3443 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
3444 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
3451 radv_emit_trap_handler(struct radv_queue
*queue
,
3452 struct radeon_cmdbuf
*cs
,
3453 struct radeon_winsys_bo
*tma_bo
)
3455 struct radv_device
*device
= queue
->device
;
3456 struct radeon_winsys_bo
*tba_bo
;
3457 uint64_t tba_va
, tma_va
;
3459 if (!device
->trap_handler_shader
|| !tma_bo
)
3462 tba_bo
= device
->trap_handler_shader
->bo
;
3464 tba_va
= radv_buffer_get_va(tba_bo
) + device
->trap_handler_shader
->bo_offset
;
3465 tma_va
= radv_buffer_get_va(tma_bo
);
3467 radv_cs_add_buffer(queue
->device
->ws
, cs
, tba_bo
);
3468 radv_cs_add_buffer(queue
->device
->ws
, cs
, tma_bo
);
3470 if (queue
->queue_family_index
== RADV_QUEUE_GENERAL
) {
3471 uint32_t regs
[] = {R_00B000_SPI_SHADER_TBA_LO_PS
,
3472 R_00B100_SPI_SHADER_TBA_LO_VS
,
3473 R_00B200_SPI_SHADER_TBA_LO_GS
,
3474 R_00B300_SPI_SHADER_TBA_LO_ES
,
3475 R_00B400_SPI_SHADER_TBA_LO_HS
,
3476 R_00B500_SPI_SHADER_TBA_LO_LS
};
3478 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
3479 radeon_set_sh_reg_seq(cs
, regs
[i
], 4);
3480 radeon_emit(cs
, tba_va
>> 8);
3481 radeon_emit(cs
, tba_va
>> 40);
3482 radeon_emit(cs
, tma_va
>> 8);
3483 radeon_emit(cs
, tma_va
>> 40);
3486 radeon_set_sh_reg_seq(cs
, R_00B838_COMPUTE_TBA_LO
, 4);
3487 radeon_emit(cs
, tba_va
>> 8);
3488 radeon_emit(cs
, tba_va
>> 40);
3489 radeon_emit(cs
, tma_va
>> 8);
3490 radeon_emit(cs
, tma_va
>> 40);
3495 radv_init_graphics_state(struct radeon_cmdbuf
*cs
, struct radv_queue
*queue
)
3497 struct radv_device
*device
= queue
->device
;
3499 if (device
->gfx_init
) {
3500 uint64_t va
= radv_buffer_get_va(device
->gfx_init
);
3502 radeon_emit(cs
, PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0));
3503 radeon_emit(cs
, va
);
3504 radeon_emit(cs
, va
>> 32);
3505 radeon_emit(cs
, device
->gfx_init_size_dw
& 0xffff);
3507 radv_cs_add_buffer(device
->ws
, cs
, device
->gfx_init
);
3509 si_emit_graphics(device
, cs
);
3514 radv_init_compute_state(struct radeon_cmdbuf
*cs
, struct radv_queue
*queue
)
3516 si_emit_compute(queue
->device
, cs
);
3520 radv_get_preamble_cs(struct radv_queue
*queue
,
3521 uint32_t scratch_size_per_wave
,
3522 uint32_t scratch_waves
,
3523 uint32_t compute_scratch_size_per_wave
,
3524 uint32_t compute_scratch_waves
,
3525 uint32_t esgs_ring_size
,
3526 uint32_t gsvs_ring_size
,
3527 bool needs_tess_rings
,
3530 bool needs_sample_positions
,
3531 struct radeon_cmdbuf
**initial_full_flush_preamble_cs
,
3532 struct radeon_cmdbuf
**initial_preamble_cs
,
3533 struct radeon_cmdbuf
**continue_preamble_cs
)
3535 struct radeon_winsys_bo
*scratch_bo
= NULL
;
3536 struct radeon_winsys_bo
*descriptor_bo
= NULL
;
3537 struct radeon_winsys_bo
*compute_scratch_bo
= NULL
;
3538 struct radeon_winsys_bo
*esgs_ring_bo
= NULL
;
3539 struct radeon_winsys_bo
*gsvs_ring_bo
= NULL
;
3540 struct radeon_winsys_bo
*tess_rings_bo
= NULL
;
3541 struct radeon_winsys_bo
*gds_bo
= NULL
;
3542 struct radeon_winsys_bo
*gds_oa_bo
= NULL
;
3543 struct radeon_cmdbuf
*dest_cs
[3] = {0};
3544 bool add_tess_rings
= false, add_gds
= false, add_gds_oa
= false, add_sample_positions
= false;
3545 unsigned tess_factor_ring_size
= 0, tess_offchip_ring_size
= 0;
3546 unsigned max_offchip_buffers
;
3547 unsigned hs_offchip_param
= 0;
3548 unsigned tess_offchip_ring_offset
;
3549 uint32_t ring_bo_flags
= RADEON_FLAG_NO_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
;
3550 if (!queue
->has_tess_rings
) {
3551 if (needs_tess_rings
)
3552 add_tess_rings
= true;
3554 if (!queue
->has_gds
) {
3558 if (!queue
->has_gds_oa
) {
3562 if (!queue
->has_sample_positions
) {
3563 if (needs_sample_positions
)
3564 add_sample_positions
= true;
3566 tess_factor_ring_size
= 32768 * queue
->device
->physical_device
->rad_info
.max_se
;
3567 hs_offchip_param
= radv_get_hs_offchip_param(queue
->device
,
3568 &max_offchip_buffers
);
3569 tess_offchip_ring_offset
= align(tess_factor_ring_size
, 64 * 1024);
3570 tess_offchip_ring_size
= max_offchip_buffers
*
3571 queue
->device
->tess_offchip_block_dw_size
* 4;
3573 scratch_size_per_wave
= MAX2(scratch_size_per_wave
, queue
->scratch_size_per_wave
);
3574 if (scratch_size_per_wave
)
3575 scratch_waves
= MIN2(scratch_waves
, UINT32_MAX
/ scratch_size_per_wave
);
3579 compute_scratch_size_per_wave
= MAX2(compute_scratch_size_per_wave
, queue
->compute_scratch_size_per_wave
);
3580 if (compute_scratch_size_per_wave
)
3581 compute_scratch_waves
= MIN2(compute_scratch_waves
, UINT32_MAX
/ compute_scratch_size_per_wave
);
3583 compute_scratch_waves
= 0;
3585 if (scratch_size_per_wave
<= queue
->scratch_size_per_wave
&&
3586 scratch_waves
<= queue
->scratch_waves
&&
3587 compute_scratch_size_per_wave
<= queue
->compute_scratch_size_per_wave
&&
3588 compute_scratch_waves
<= queue
->compute_scratch_waves
&&
3589 esgs_ring_size
<= queue
->esgs_ring_size
&&
3590 gsvs_ring_size
<= queue
->gsvs_ring_size
&&
3591 !add_tess_rings
&& !add_gds
&& !add_gds_oa
&& !add_sample_positions
&&
3592 queue
->initial_preamble_cs
) {
3593 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
3594 *initial_preamble_cs
= queue
->initial_preamble_cs
;
3595 *continue_preamble_cs
= queue
->continue_preamble_cs
;
3596 if (!scratch_size_per_wave
&& !compute_scratch_size_per_wave
&&
3597 !esgs_ring_size
&& !gsvs_ring_size
&& !needs_tess_rings
&&
3598 !needs_gds
&& !needs_gds_oa
&& !needs_sample_positions
)
3599 *continue_preamble_cs
= NULL
;
3603 uint32_t scratch_size
= scratch_size_per_wave
* scratch_waves
;
3604 uint32_t queue_scratch_size
= queue
->scratch_size_per_wave
* queue
->scratch_waves
;
3605 if (scratch_size
> queue_scratch_size
) {
3606 scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3611 RADV_BO_PRIORITY_SCRATCH
);
3615 scratch_bo
= queue
->scratch_bo
;
3617 uint32_t compute_scratch_size
= compute_scratch_size_per_wave
* compute_scratch_waves
;
3618 uint32_t compute_queue_scratch_size
= queue
->compute_scratch_size_per_wave
* queue
->compute_scratch_waves
;
3619 if (compute_scratch_size
> compute_queue_scratch_size
) {
3620 compute_scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3621 compute_scratch_size
,
3625 RADV_BO_PRIORITY_SCRATCH
);
3626 if (!compute_scratch_bo
)
3630 compute_scratch_bo
= queue
->compute_scratch_bo
;
3632 if (esgs_ring_size
> queue
->esgs_ring_size
) {
3633 esgs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3638 RADV_BO_PRIORITY_SCRATCH
);
3642 esgs_ring_bo
= queue
->esgs_ring_bo
;
3643 esgs_ring_size
= queue
->esgs_ring_size
;
3646 if (gsvs_ring_size
> queue
->gsvs_ring_size
) {
3647 gsvs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3652 RADV_BO_PRIORITY_SCRATCH
);
3656 gsvs_ring_bo
= queue
->gsvs_ring_bo
;
3657 gsvs_ring_size
= queue
->gsvs_ring_size
;
3660 if (add_tess_rings
) {
3661 tess_rings_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3662 tess_offchip_ring_offset
+ tess_offchip_ring_size
,
3666 RADV_BO_PRIORITY_SCRATCH
);
3670 tess_rings_bo
= queue
->tess_rings_bo
;
3674 assert(queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
);
3676 /* 4 streamout GDS counters.
3677 * We need 256B (64 dw) of GDS, otherwise streamout hangs.
3679 gds_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3683 RADV_BO_PRIORITY_SCRATCH
);
3687 gds_bo
= queue
->gds_bo
;
3691 assert(queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
);
3693 gds_oa_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3697 RADV_BO_PRIORITY_SCRATCH
);
3701 gds_oa_bo
= queue
->gds_oa_bo
;
3704 if (scratch_bo
!= queue
->scratch_bo
||
3705 esgs_ring_bo
!= queue
->esgs_ring_bo
||
3706 gsvs_ring_bo
!= queue
->gsvs_ring_bo
||
3707 tess_rings_bo
!= queue
->tess_rings_bo
||
3708 add_sample_positions
) {
3710 if (gsvs_ring_bo
|| esgs_ring_bo
||
3711 tess_rings_bo
|| add_sample_positions
) {
3712 size
= 112; /* 2 dword + 2 padding + 4 dword * 6 */
3713 if (add_sample_positions
)
3714 size
+= 128; /* 64+32+16+8 = 120 bytes */
3716 else if (scratch_bo
)
3717 size
= 8; /* 2 dword */
3719 descriptor_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3723 RADEON_FLAG_CPU_ACCESS
|
3724 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
3725 RADEON_FLAG_READ_ONLY
,
3726 RADV_BO_PRIORITY_DESCRIPTOR
);
3730 descriptor_bo
= queue
->descriptor_bo
;
3732 if (descriptor_bo
!= queue
->descriptor_bo
) {
3733 uint32_t *map
= (uint32_t*)queue
->device
->ws
->buffer_map(descriptor_bo
);
3738 uint64_t scratch_va
= radv_buffer_get_va(scratch_bo
);
3739 uint32_t rsrc1
= S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
3740 S_008F04_SWIZZLE_ENABLE(1);
3741 map
[0] = scratch_va
;
3745 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_rings_bo
|| add_sample_positions
)
3746 fill_geom_tess_rings(queue
, map
, add_sample_positions
,
3747 esgs_ring_size
, esgs_ring_bo
,
3748 gsvs_ring_size
, gsvs_ring_bo
,
3749 tess_factor_ring_size
,
3750 tess_offchip_ring_offset
,
3751 tess_offchip_ring_size
,
3754 queue
->device
->ws
->buffer_unmap(descriptor_bo
);
3757 for(int i
= 0; i
< 3; ++i
) {
3758 struct radeon_cmdbuf
*cs
= NULL
;
3759 cs
= queue
->device
->ws
->cs_create(queue
->device
->ws
,
3760 queue
->queue_family_index
? RING_COMPUTE
: RING_GFX
);
3767 radv_cs_add_buffer(queue
->device
->ws
, cs
, scratch_bo
);
3769 /* Emit initial configuration. */
3770 switch (queue
->queue_family_index
) {
3771 case RADV_QUEUE_GENERAL
:
3772 radv_init_graphics_state(cs
, queue
);
3774 case RADV_QUEUE_COMPUTE
:
3775 radv_init_compute_state(cs
, queue
);
3777 case RADV_QUEUE_TRANSFER
:
3781 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_rings_bo
) {
3782 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3783 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
3785 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3786 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
3789 radv_emit_gs_ring_sizes(queue
, cs
, esgs_ring_bo
, esgs_ring_size
,
3790 gsvs_ring_bo
, gsvs_ring_size
);
3791 radv_emit_tess_factor_ring(queue
, cs
, hs_offchip_param
,
3792 tess_factor_ring_size
, tess_rings_bo
);
3793 radv_emit_global_shader_pointers(queue
, cs
, descriptor_bo
);
3794 radv_emit_compute_scratch(queue
, cs
, compute_scratch_size_per_wave
,
3795 compute_scratch_waves
, compute_scratch_bo
);
3796 radv_emit_graphics_scratch(queue
, cs
, scratch_size_per_wave
,
3797 scratch_waves
, scratch_bo
);
3798 radv_emit_trap_handler(queue
, cs
, queue
->device
->tma_bo
);
3801 radv_cs_add_buffer(queue
->device
->ws
, cs
, gds_bo
);
3803 radv_cs_add_buffer(queue
->device
->ws
, cs
, gds_oa_bo
);
3805 if (queue
->device
->trace_bo
)
3806 radv_cs_add_buffer(queue
->device
->ws
, cs
, queue
->device
->trace_bo
);
3808 if (queue
->device
->border_color_data
.bo
)
3809 radv_cs_add_buffer(queue
->device
->ws
, cs
,
3810 queue
->device
->border_color_data
.bo
);
3813 si_cs_emit_cache_flush(cs
,
3814 queue
->device
->physical_device
->rad_info
.chip_class
,
3816 queue
->queue_family_index
== RING_COMPUTE
&&
3817 queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
,
3818 (queue
->queue_family_index
== RADV_QUEUE_COMPUTE
? RADV_CMD_FLAG_CS_PARTIAL_FLUSH
: (RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
)) |
3819 RADV_CMD_FLAG_INV_ICACHE
|
3820 RADV_CMD_FLAG_INV_SCACHE
|
3821 RADV_CMD_FLAG_INV_VCACHE
|
3822 RADV_CMD_FLAG_INV_L2
|
3823 RADV_CMD_FLAG_START_PIPELINE_STATS
, 0);
3824 } else if (i
== 1) {
3825 si_cs_emit_cache_flush(cs
,
3826 queue
->device
->physical_device
->rad_info
.chip_class
,
3828 queue
->queue_family_index
== RING_COMPUTE
&&
3829 queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
,
3830 RADV_CMD_FLAG_INV_ICACHE
|
3831 RADV_CMD_FLAG_INV_SCACHE
|
3832 RADV_CMD_FLAG_INV_VCACHE
|
3833 RADV_CMD_FLAG_INV_L2
|
3834 RADV_CMD_FLAG_START_PIPELINE_STATS
, 0);
3837 if (queue
->device
->ws
->cs_finalize(cs
) != VK_SUCCESS
)
3841 if (queue
->initial_full_flush_preamble_cs
)
3842 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
3844 if (queue
->initial_preamble_cs
)
3845 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
3847 if (queue
->continue_preamble_cs
)
3848 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
3850 queue
->initial_full_flush_preamble_cs
= dest_cs
[0];
3851 queue
->initial_preamble_cs
= dest_cs
[1];
3852 queue
->continue_preamble_cs
= dest_cs
[2];
3854 if (scratch_bo
!= queue
->scratch_bo
) {
3855 if (queue
->scratch_bo
)
3856 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
3857 queue
->scratch_bo
= scratch_bo
;
3859 queue
->scratch_size_per_wave
= scratch_size_per_wave
;
3860 queue
->scratch_waves
= scratch_waves
;
3862 if (compute_scratch_bo
!= queue
->compute_scratch_bo
) {
3863 if (queue
->compute_scratch_bo
)
3864 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
3865 queue
->compute_scratch_bo
= compute_scratch_bo
;
3867 queue
->compute_scratch_size_per_wave
= compute_scratch_size_per_wave
;
3868 queue
->compute_scratch_waves
= compute_scratch_waves
;
3870 if (esgs_ring_bo
!= queue
->esgs_ring_bo
) {
3871 if (queue
->esgs_ring_bo
)
3872 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
3873 queue
->esgs_ring_bo
= esgs_ring_bo
;
3874 queue
->esgs_ring_size
= esgs_ring_size
;
3877 if (gsvs_ring_bo
!= queue
->gsvs_ring_bo
) {
3878 if (queue
->gsvs_ring_bo
)
3879 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
3880 queue
->gsvs_ring_bo
= gsvs_ring_bo
;
3881 queue
->gsvs_ring_size
= gsvs_ring_size
;
3884 if (tess_rings_bo
!= queue
->tess_rings_bo
) {
3885 queue
->tess_rings_bo
= tess_rings_bo
;
3886 queue
->has_tess_rings
= true;
3889 if (gds_bo
!= queue
->gds_bo
) {
3890 queue
->gds_bo
= gds_bo
;
3891 queue
->has_gds
= true;
3894 if (gds_oa_bo
!= queue
->gds_oa_bo
) {
3895 queue
->gds_oa_bo
= gds_oa_bo
;
3896 queue
->has_gds_oa
= true;
3899 if (descriptor_bo
!= queue
->descriptor_bo
) {
3900 if (queue
->descriptor_bo
)
3901 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
3903 queue
->descriptor_bo
= descriptor_bo
;
3906 if (add_sample_positions
)
3907 queue
->has_sample_positions
= true;
3909 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
3910 *initial_preamble_cs
= queue
->initial_preamble_cs
;
3911 *continue_preamble_cs
= queue
->continue_preamble_cs
;
3912 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
3913 *continue_preamble_cs
= NULL
;
3916 for (int i
= 0; i
< ARRAY_SIZE(dest_cs
); ++i
)
3918 queue
->device
->ws
->cs_destroy(dest_cs
[i
]);
3919 if (descriptor_bo
&& descriptor_bo
!= queue
->descriptor_bo
)
3920 queue
->device
->ws
->buffer_destroy(descriptor_bo
);
3921 if (scratch_bo
&& scratch_bo
!= queue
->scratch_bo
)
3922 queue
->device
->ws
->buffer_destroy(scratch_bo
);
3923 if (compute_scratch_bo
&& compute_scratch_bo
!= queue
->compute_scratch_bo
)
3924 queue
->device
->ws
->buffer_destroy(compute_scratch_bo
);
3925 if (esgs_ring_bo
&& esgs_ring_bo
!= queue
->esgs_ring_bo
)
3926 queue
->device
->ws
->buffer_destroy(esgs_ring_bo
);
3927 if (gsvs_ring_bo
&& gsvs_ring_bo
!= queue
->gsvs_ring_bo
)
3928 queue
->device
->ws
->buffer_destroy(gsvs_ring_bo
);
3929 if (tess_rings_bo
&& tess_rings_bo
!= queue
->tess_rings_bo
)
3930 queue
->device
->ws
->buffer_destroy(tess_rings_bo
);
3931 if (gds_bo
&& gds_bo
!= queue
->gds_bo
)
3932 queue
->device
->ws
->buffer_destroy(gds_bo
);
3933 if (gds_oa_bo
&& gds_oa_bo
!= queue
->gds_oa_bo
)
3934 queue
->device
->ws
->buffer_destroy(gds_oa_bo
);
3936 return vk_error(queue
->device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
3939 static VkResult
radv_alloc_sem_counts(struct radv_device
*device
,
3940 struct radv_winsys_sem_counts
*counts
,
3942 struct radv_semaphore_part
**sems
,
3943 const uint64_t *timeline_values
,
3947 int syncobj_idx
= 0, non_reset_idx
= 0, sem_idx
= 0, timeline_idx
= 0;
3949 if (num_sems
== 0 && _fence
== VK_NULL_HANDLE
)
3952 for (uint32_t i
= 0; i
< num_sems
; i
++) {
3953 switch(sems
[i
]->kind
) {
3954 case RADV_SEMAPHORE_SYNCOBJ
:
3955 counts
->syncobj_count
++;
3956 counts
->syncobj_reset_count
++;
3958 case RADV_SEMAPHORE_WINSYS
:
3959 counts
->sem_count
++;
3961 case RADV_SEMAPHORE_NONE
:
3963 case RADV_SEMAPHORE_TIMELINE
:
3964 counts
->syncobj_count
++;
3966 case RADV_SEMAPHORE_TIMELINE_SYNCOBJ
:
3967 counts
->timeline_syncobj_count
++;
3972 if (_fence
!= VK_NULL_HANDLE
) {
3973 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
3975 struct radv_fence_part
*part
=
3976 fence
->temporary
.kind
!= RADV_FENCE_NONE
?
3977 &fence
->temporary
: &fence
->permanent
;
3978 if (part
->kind
== RADV_FENCE_SYNCOBJ
)
3979 counts
->syncobj_count
++;
3982 if (counts
->syncobj_count
|| counts
->timeline_syncobj_count
) {
3983 counts
->points
= (uint64_t *)malloc(
3984 sizeof(*counts
->syncobj
) * counts
->syncobj_count
+
3985 (sizeof(*counts
->syncobj
) + sizeof(*counts
->points
)) * counts
->timeline_syncobj_count
);
3986 if (!counts
->points
)
3987 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3988 counts
->syncobj
= (uint32_t*)(counts
->points
+ counts
->timeline_syncobj_count
);
3991 if (counts
->sem_count
) {
3992 counts
->sem
= (struct radeon_winsys_sem
**)malloc(sizeof(struct radeon_winsys_sem
*) * counts
->sem_count
);
3994 free(counts
->syncobj
);
3995 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3999 non_reset_idx
= counts
->syncobj_reset_count
;
4001 for (uint32_t i
= 0; i
< num_sems
; i
++) {
4002 switch(sems
[i
]->kind
) {
4003 case RADV_SEMAPHORE_NONE
:
4004 unreachable("Empty semaphore");
4006 case RADV_SEMAPHORE_SYNCOBJ
:
4007 counts
->syncobj
[syncobj_idx
++] = sems
[i
]->syncobj
;
4009 case RADV_SEMAPHORE_WINSYS
:
4010 counts
->sem
[sem_idx
++] = sems
[i
]->ws_sem
;
4012 case RADV_SEMAPHORE_TIMELINE
: {
4013 pthread_mutex_lock(&sems
[i
]->timeline
.mutex
);
4014 struct radv_timeline_point
*point
= NULL
;
4016 point
= radv_timeline_add_point_locked(device
, &sems
[i
]->timeline
, timeline_values
[i
]);
4018 point
= radv_timeline_find_point_at_least_locked(device
, &sems
[i
]->timeline
, timeline_values
[i
]);
4021 pthread_mutex_unlock(&sems
[i
]->timeline
.mutex
);
4024 counts
->syncobj
[non_reset_idx
++] = point
->syncobj
;
4026 /* Explicitly remove the semaphore so we might not find
4027 * a point later post-submit. */
4032 case RADV_SEMAPHORE_TIMELINE_SYNCOBJ
:
4033 counts
->syncobj
[counts
->syncobj_count
+ timeline_idx
] = sems
[i
]->syncobj
;
4034 counts
->points
[timeline_idx
] = timeline_values
[i
];
4040 if (_fence
!= VK_NULL_HANDLE
) {
4041 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
4043 struct radv_fence_part
*part
=
4044 fence
->temporary
.kind
!= RADV_FENCE_NONE
?
4045 &fence
->temporary
: &fence
->permanent
;
4046 if (part
->kind
== RADV_FENCE_SYNCOBJ
)
4047 counts
->syncobj
[non_reset_idx
++] = part
->syncobj
;
4050 assert(MAX2(syncobj_idx
, non_reset_idx
) <= counts
->syncobj_count
);
4051 counts
->syncobj_count
= MAX2(syncobj_idx
, non_reset_idx
);
4057 radv_free_sem_info(struct radv_winsys_sem_info
*sem_info
)
4059 free(sem_info
->wait
.points
);
4060 free(sem_info
->wait
.sem
);
4061 free(sem_info
->signal
.points
);
4062 free(sem_info
->signal
.sem
);
4066 static void radv_free_temp_syncobjs(struct radv_device
*device
,
4068 struct radv_semaphore_part
*sems
)
4070 for (uint32_t i
= 0; i
< num_sems
; i
++) {
4071 radv_destroy_semaphore_part(device
, sems
+ i
);
4076 radv_alloc_sem_info(struct radv_device
*device
,
4077 struct radv_winsys_sem_info
*sem_info
,
4079 struct radv_semaphore_part
**wait_sems
,
4080 const uint64_t *wait_values
,
4081 int num_signal_sems
,
4082 struct radv_semaphore_part
**signal_sems
,
4083 const uint64_t *signal_values
,
4087 memset(sem_info
, 0, sizeof(*sem_info
));
4089 ret
= radv_alloc_sem_counts(device
, &sem_info
->wait
, num_wait_sems
, wait_sems
, wait_values
, VK_NULL_HANDLE
, false);
4092 ret
= radv_alloc_sem_counts(device
, &sem_info
->signal
, num_signal_sems
, signal_sems
, signal_values
, fence
, true);
4094 radv_free_sem_info(sem_info
);
4096 /* caller can override these */
4097 sem_info
->cs_emit_wait
= true;
4098 sem_info
->cs_emit_signal
= true;
4103 radv_finalize_timelines(struct radv_device
*device
,
4104 uint32_t num_wait_sems
,
4105 struct radv_semaphore_part
**wait_sems
,
4106 const uint64_t *wait_values
,
4107 uint32_t num_signal_sems
,
4108 struct radv_semaphore_part
**signal_sems
,
4109 const uint64_t *signal_values
,
4110 struct list_head
*processing_list
)
4112 for (uint32_t i
= 0; i
< num_wait_sems
; ++i
) {
4113 if (wait_sems
[i
] && wait_sems
[i
]->kind
== RADV_SEMAPHORE_TIMELINE
) {
4114 pthread_mutex_lock(&wait_sems
[i
]->timeline
.mutex
);
4115 struct radv_timeline_point
*point
=
4116 radv_timeline_find_point_at_least_locked(device
, &wait_sems
[i
]->timeline
, wait_values
[i
]);
4117 point
->wait_count
-= 2;
4118 pthread_mutex_unlock(&wait_sems
[i
]->timeline
.mutex
);
4121 for (uint32_t i
= 0; i
< num_signal_sems
; ++i
) {
4122 if (signal_sems
[i
] && signal_sems
[i
]->kind
== RADV_SEMAPHORE_TIMELINE
) {
4123 pthread_mutex_lock(&signal_sems
[i
]->timeline
.mutex
);
4124 struct radv_timeline_point
*point
=
4125 radv_timeline_find_point_at_least_locked(device
, &signal_sems
[i
]->timeline
, signal_values
[i
]);
4126 signal_sems
[i
]->timeline
.highest_submitted
=
4127 MAX2(signal_sems
[i
]->timeline
.highest_submitted
, point
->value
);
4128 point
->wait_count
-= 2;
4129 radv_timeline_trigger_waiters_locked(&signal_sems
[i
]->timeline
, processing_list
);
4130 pthread_mutex_unlock(&signal_sems
[i
]->timeline
.mutex
);
4131 } else if (signal_sems
[i
] && signal_sems
[i
]->kind
== RADV_SEMAPHORE_TIMELINE_SYNCOBJ
) {
4132 signal_sems
[i
]->timeline_syncobj
.max_point
=
4133 MAX2(signal_sems
[i
]->timeline_syncobj
.max_point
, signal_values
[i
]);
4139 radv_sparse_buffer_bind_memory(struct radv_device
*device
,
4140 const VkSparseBufferMemoryBindInfo
*bind
)
4142 RADV_FROM_HANDLE(radv_buffer
, buffer
, bind
->buffer
);
4145 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
4146 struct radv_device_memory
*mem
= NULL
;
4148 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
4149 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
4151 result
= device
->ws
->buffer_virtual_bind(buffer
->bo
,
4152 bind
->pBinds
[i
].resourceOffset
,
4153 bind
->pBinds
[i
].size
,
4154 mem
? mem
->bo
: NULL
,
4155 bind
->pBinds
[i
].memoryOffset
);
4156 if (result
!= VK_SUCCESS
)
4164 radv_sparse_image_opaque_bind_memory(struct radv_device
*device
,
4165 const VkSparseImageOpaqueMemoryBindInfo
*bind
)
4167 RADV_FROM_HANDLE(radv_image
, image
, bind
->image
);
4170 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
4171 struct radv_device_memory
*mem
= NULL
;
4173 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
4174 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
4176 result
= device
->ws
->buffer_virtual_bind(image
->bo
,
4177 bind
->pBinds
[i
].resourceOffset
,
4178 bind
->pBinds
[i
].size
,
4179 mem
? mem
->bo
: NULL
,
4180 bind
->pBinds
[i
].memoryOffset
);
4181 if (result
!= VK_SUCCESS
)
4189 radv_get_preambles(struct radv_queue
*queue
,
4190 const VkCommandBuffer
*cmd_buffers
,
4191 uint32_t cmd_buffer_count
,
4192 struct radeon_cmdbuf
**initial_full_flush_preamble_cs
,
4193 struct radeon_cmdbuf
**initial_preamble_cs
,
4194 struct radeon_cmdbuf
**continue_preamble_cs
)
4196 uint32_t scratch_size_per_wave
= 0, waves_wanted
= 0;
4197 uint32_t compute_scratch_size_per_wave
= 0, compute_waves_wanted
= 0;
4198 uint32_t esgs_ring_size
= 0, gsvs_ring_size
= 0;
4199 bool tess_rings_needed
= false;
4200 bool gds_needed
= false;
4201 bool gds_oa_needed
= false;
4202 bool sample_positions_needed
= false;
4204 for (uint32_t j
= 0; j
< cmd_buffer_count
; j
++) {
4205 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
4208 scratch_size_per_wave
= MAX2(scratch_size_per_wave
, cmd_buffer
->scratch_size_per_wave_needed
);
4209 waves_wanted
= MAX2(waves_wanted
, cmd_buffer
->scratch_waves_wanted
);
4210 compute_scratch_size_per_wave
= MAX2(compute_scratch_size_per_wave
,
4211 cmd_buffer
->compute_scratch_size_per_wave_needed
);
4212 compute_waves_wanted
= MAX2(compute_waves_wanted
,
4213 cmd_buffer
->compute_scratch_waves_wanted
);
4214 esgs_ring_size
= MAX2(esgs_ring_size
, cmd_buffer
->esgs_ring_size_needed
);
4215 gsvs_ring_size
= MAX2(gsvs_ring_size
, cmd_buffer
->gsvs_ring_size_needed
);
4216 tess_rings_needed
|= cmd_buffer
->tess_rings_needed
;
4217 gds_needed
|= cmd_buffer
->gds_needed
;
4218 gds_oa_needed
|= cmd_buffer
->gds_oa_needed
;
4219 sample_positions_needed
|= cmd_buffer
->sample_positions_needed
;
4222 return radv_get_preamble_cs(queue
, scratch_size_per_wave
, waves_wanted
,
4223 compute_scratch_size_per_wave
, compute_waves_wanted
,
4224 esgs_ring_size
, gsvs_ring_size
, tess_rings_needed
,
4225 gds_needed
, gds_oa_needed
, sample_positions_needed
,
4226 initial_full_flush_preamble_cs
,
4227 initial_preamble_cs
, continue_preamble_cs
);
4230 struct radv_deferred_queue_submission
{
4231 struct radv_queue
*queue
;
4232 VkCommandBuffer
*cmd_buffers
;
4233 uint32_t cmd_buffer_count
;
4235 /* Sparse bindings that happen on a queue. */
4236 VkSparseBufferMemoryBindInfo
*buffer_binds
;
4237 uint32_t buffer_bind_count
;
4238 VkSparseImageOpaqueMemoryBindInfo
*image_opaque_binds
;
4239 uint32_t image_opaque_bind_count
;
4242 VkShaderStageFlags wait_dst_stage_mask
;
4243 struct radv_semaphore_part
**wait_semaphores
;
4244 uint32_t wait_semaphore_count
;
4245 struct radv_semaphore_part
**signal_semaphores
;
4246 uint32_t signal_semaphore_count
;
4249 uint64_t *wait_values
;
4250 uint64_t *signal_values
;
4252 struct radv_semaphore_part
*temporary_semaphore_parts
;
4253 uint32_t temporary_semaphore_part_count
;
4255 struct list_head queue_pending_list
;
4256 uint32_t submission_wait_count
;
4257 struct radv_timeline_waiter
*wait_nodes
;
4259 struct list_head processing_list
;
4262 struct radv_queue_submission
{
4263 const VkCommandBuffer
*cmd_buffers
;
4264 uint32_t cmd_buffer_count
;
4266 /* Sparse bindings that happen on a queue. */
4267 const VkSparseBufferMemoryBindInfo
*buffer_binds
;
4268 uint32_t buffer_bind_count
;
4269 const VkSparseImageOpaqueMemoryBindInfo
*image_opaque_binds
;
4270 uint32_t image_opaque_bind_count
;
4273 VkPipelineStageFlags wait_dst_stage_mask
;
4274 const VkSemaphore
*wait_semaphores
;
4275 uint32_t wait_semaphore_count
;
4276 const VkSemaphore
*signal_semaphores
;
4277 uint32_t signal_semaphore_count
;
4280 const uint64_t *wait_values
;
4281 uint32_t wait_value_count
;
4282 const uint64_t *signal_values
;
4283 uint32_t signal_value_count
;
4287 radv_queue_trigger_submission(struct radv_deferred_queue_submission
*submission
,
4289 struct list_head
*processing_list
);
4292 radv_create_deferred_submission(struct radv_queue
*queue
,
4293 const struct radv_queue_submission
*submission
,
4294 struct radv_deferred_queue_submission
**out
)
4296 struct radv_deferred_queue_submission
*deferred
= NULL
;
4297 size_t size
= sizeof(struct radv_deferred_queue_submission
);
4299 uint32_t temporary_count
= 0;
4300 for (uint32_t i
= 0; i
< submission
->wait_semaphore_count
; ++i
) {
4301 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, submission
->wait_semaphores
[i
]);
4302 if (semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
)
4306 size
+= submission
->cmd_buffer_count
* sizeof(VkCommandBuffer
);
4307 size
+= submission
->buffer_bind_count
* sizeof(VkSparseBufferMemoryBindInfo
);
4308 size
+= submission
->image_opaque_bind_count
* sizeof(VkSparseImageOpaqueMemoryBindInfo
);
4309 size
+= submission
->wait_semaphore_count
* sizeof(struct radv_semaphore_part
*);
4310 size
+= temporary_count
* sizeof(struct radv_semaphore_part
);
4311 size
+= submission
->signal_semaphore_count
* sizeof(struct radv_semaphore_part
*);
4312 size
+= submission
->wait_value_count
* sizeof(uint64_t);
4313 size
+= submission
->signal_value_count
* sizeof(uint64_t);
4314 size
+= submission
->wait_semaphore_count
* sizeof(struct radv_timeline_waiter
);
4316 deferred
= calloc(1, size
);
4318 return VK_ERROR_OUT_OF_HOST_MEMORY
;
4320 deferred
->queue
= queue
;
4322 deferred
->cmd_buffers
= (void*)(deferred
+ 1);
4323 deferred
->cmd_buffer_count
= submission
->cmd_buffer_count
;
4324 memcpy(deferred
->cmd_buffers
, submission
->cmd_buffers
,
4325 submission
->cmd_buffer_count
* sizeof(*deferred
->cmd_buffers
));
4327 deferred
->buffer_binds
= (void*)(deferred
->cmd_buffers
+ submission
->cmd_buffer_count
);
4328 deferred
->buffer_bind_count
= submission
->buffer_bind_count
;
4329 memcpy(deferred
->buffer_binds
, submission
->buffer_binds
,
4330 submission
->buffer_bind_count
* sizeof(*deferred
->buffer_binds
));
4332 deferred
->image_opaque_binds
= (void*)(deferred
->buffer_binds
+ submission
->buffer_bind_count
);
4333 deferred
->image_opaque_bind_count
= submission
->image_opaque_bind_count
;
4334 memcpy(deferred
->image_opaque_binds
, submission
->image_opaque_binds
,
4335 submission
->image_opaque_bind_count
* sizeof(*deferred
->image_opaque_binds
));
4337 deferred
->flush_caches
= submission
->flush_caches
;
4338 deferred
->wait_dst_stage_mask
= submission
->wait_dst_stage_mask
;
4340 deferred
->wait_semaphores
= (void*)(deferred
->image_opaque_binds
+ deferred
->image_opaque_bind_count
);
4341 deferred
->wait_semaphore_count
= submission
->wait_semaphore_count
;
4343 deferred
->signal_semaphores
= (void*)(deferred
->wait_semaphores
+ deferred
->wait_semaphore_count
);
4344 deferred
->signal_semaphore_count
= submission
->signal_semaphore_count
;
4346 deferred
->fence
= submission
->fence
;
4348 deferred
->temporary_semaphore_parts
= (void*)(deferred
->signal_semaphores
+ deferred
->signal_semaphore_count
);
4349 deferred
->temporary_semaphore_part_count
= temporary_count
;
4351 uint32_t temporary_idx
= 0;
4352 for (uint32_t i
= 0; i
< submission
->wait_semaphore_count
; ++i
) {
4353 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, submission
->wait_semaphores
[i
]);
4354 if (semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
) {
4355 deferred
->wait_semaphores
[i
] = &deferred
->temporary_semaphore_parts
[temporary_idx
];
4356 deferred
->temporary_semaphore_parts
[temporary_idx
] = semaphore
->temporary
;
4357 semaphore
->temporary
.kind
= RADV_SEMAPHORE_NONE
;
4360 deferred
->wait_semaphores
[i
] = &semaphore
->permanent
;
4363 for (uint32_t i
= 0; i
< submission
->signal_semaphore_count
; ++i
) {
4364 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, submission
->signal_semaphores
[i
]);
4365 if (semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
) {
4366 deferred
->signal_semaphores
[i
] = &semaphore
->temporary
;
4368 deferred
->signal_semaphores
[i
] = &semaphore
->permanent
;
4372 deferred
->wait_values
= (void*)(deferred
->temporary_semaphore_parts
+ temporary_count
);
4373 memcpy(deferred
->wait_values
, submission
->wait_values
, submission
->wait_value_count
* sizeof(uint64_t));
4374 deferred
->signal_values
= deferred
->wait_values
+ submission
->wait_value_count
;
4375 memcpy(deferred
->signal_values
, submission
->signal_values
, submission
->signal_value_count
* sizeof(uint64_t));
4377 deferred
->wait_nodes
= (void*)(deferred
->signal_values
+ submission
->signal_value_count
);
4378 /* This is worst-case. radv_queue_enqueue_submission will fill in further, but this
4379 * ensure the submission is not accidentally triggered early when adding wait timelines. */
4380 deferred
->submission_wait_count
= 1 + submission
->wait_semaphore_count
;
4387 radv_queue_enqueue_submission(struct radv_deferred_queue_submission
*submission
,
4388 struct list_head
*processing_list
)
4390 uint32_t wait_cnt
= 0;
4391 struct radv_timeline_waiter
*waiter
= submission
->wait_nodes
;
4392 for (uint32_t i
= 0; i
< submission
->wait_semaphore_count
; ++i
) {
4393 if (submission
->wait_semaphores
[i
]->kind
== RADV_SEMAPHORE_TIMELINE
) {
4394 pthread_mutex_lock(&submission
->wait_semaphores
[i
]->timeline
.mutex
);
4395 if (submission
->wait_semaphores
[i
]->timeline
.highest_submitted
< submission
->wait_values
[i
]) {
4397 waiter
->value
= submission
->wait_values
[i
];
4398 waiter
->submission
= submission
;
4399 list_addtail(&waiter
->list
, &submission
->wait_semaphores
[i
]->timeline
.waiters
);
4402 pthread_mutex_unlock(&submission
->wait_semaphores
[i
]->timeline
.mutex
);
4406 pthread_mutex_lock(&submission
->queue
->pending_mutex
);
4408 bool is_first
= list_is_empty(&submission
->queue
->pending_submissions
);
4409 list_addtail(&submission
->queue_pending_list
, &submission
->queue
->pending_submissions
);
4411 pthread_mutex_unlock(&submission
->queue
->pending_mutex
);
4413 /* If there is already a submission in the queue, that will decrement the counter by 1 when
4414 * submitted, but if the queue was empty, we decrement ourselves as there is no previous
4416 uint32_t decrement
= submission
->wait_semaphore_count
- wait_cnt
+ (is_first
? 1 : 0);
4417 return radv_queue_trigger_submission(submission
, decrement
, processing_list
);
4421 radv_queue_submission_update_queue(struct radv_deferred_queue_submission
*submission
,
4422 struct list_head
*processing_list
)
4424 pthread_mutex_lock(&submission
->queue
->pending_mutex
);
4425 list_del(&submission
->queue_pending_list
);
4427 /* trigger the next submission in the queue. */
4428 if (!list_is_empty(&submission
->queue
->pending_submissions
)) {
4429 struct radv_deferred_queue_submission
*next_submission
=
4430 list_first_entry(&submission
->queue
->pending_submissions
,
4431 struct radv_deferred_queue_submission
,
4432 queue_pending_list
);
4433 radv_queue_trigger_submission(next_submission
, 1, processing_list
);
4435 pthread_mutex_unlock(&submission
->queue
->pending_mutex
);
4437 pthread_cond_broadcast(&submission
->queue
->device
->timeline_cond
);
4441 radv_queue_submit_deferred(struct radv_deferred_queue_submission
*submission
,
4442 struct list_head
*processing_list
)
4444 RADV_FROM_HANDLE(radv_fence
, fence
, submission
->fence
);
4445 struct radv_queue
*queue
= submission
->queue
;
4446 struct radeon_winsys_ctx
*ctx
= queue
->hw_ctx
;
4447 uint32_t max_cs_submission
= queue
->device
->trace_bo
? 1 : RADV_MAX_IBS_PER_SUBMIT
;
4448 struct radeon_winsys_fence
*base_fence
= NULL
;
4449 bool do_flush
= submission
->flush_caches
|| submission
->wait_dst_stage_mask
;
4450 bool can_patch
= true;
4452 struct radv_winsys_sem_info sem_info
;
4454 struct radeon_cmdbuf
*initial_preamble_cs
= NULL
;
4455 struct radeon_cmdbuf
*initial_flush_preamble_cs
= NULL
;
4456 struct radeon_cmdbuf
*continue_preamble_cs
= NULL
;
4459 /* Under most circumstances, out fences won't be temporary.
4460 * However, the spec does allow it for opaque_fd.
4462 * From the Vulkan 1.0.53 spec:
4464 * "If the import is temporary, the implementation must
4465 * restore the semaphore to its prior permanent state after
4466 * submitting the next semaphore wait operation."
4468 struct radv_fence_part
*part
=
4469 fence
->temporary
.kind
!= RADV_FENCE_NONE
?
4470 &fence
->temporary
: &fence
->permanent
;
4471 if (part
->kind
== RADV_FENCE_WINSYS
)
4472 base_fence
= part
->fence
;
4475 result
= radv_get_preambles(queue
, submission
->cmd_buffers
,
4476 submission
->cmd_buffer_count
,
4477 &initial_preamble_cs
,
4478 &initial_flush_preamble_cs
,
4479 &continue_preamble_cs
);
4480 if (result
!= VK_SUCCESS
)
4483 result
= radv_alloc_sem_info(queue
->device
,
4485 submission
->wait_semaphore_count
,
4486 submission
->wait_semaphores
,
4487 submission
->wait_values
,
4488 submission
->signal_semaphore_count
,
4489 submission
->signal_semaphores
,
4490 submission
->signal_values
,
4492 if (result
!= VK_SUCCESS
)
4495 for (uint32_t i
= 0; i
< submission
->buffer_bind_count
; ++i
) {
4496 result
= radv_sparse_buffer_bind_memory(queue
->device
,
4497 submission
->buffer_binds
+ i
);
4498 if (result
!= VK_SUCCESS
)
4502 for (uint32_t i
= 0; i
< submission
->image_opaque_bind_count
; ++i
) {
4503 result
= radv_sparse_image_opaque_bind_memory(queue
->device
,
4504 submission
->image_opaque_binds
+ i
);
4505 if (result
!= VK_SUCCESS
)
4509 if (!submission
->cmd_buffer_count
) {
4510 result
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
,
4511 &queue
->device
->empty_cs
[queue
->queue_family_index
],
4515 if (result
!= VK_SUCCESS
)
4518 struct radeon_cmdbuf
**cs_array
= malloc(sizeof(struct radeon_cmdbuf
*) *
4519 (submission
->cmd_buffer_count
));
4521 for (uint32_t j
= 0; j
< submission
->cmd_buffer_count
; j
++) {
4522 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, submission
->cmd_buffers
[j
]);
4523 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
4525 cs_array
[j
] = cmd_buffer
->cs
;
4526 if ((cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT
))
4529 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_PENDING
;
4532 for (uint32_t j
= 0; j
< submission
->cmd_buffer_count
; j
+= advance
) {
4533 struct radeon_cmdbuf
*initial_preamble
= (do_flush
&& !j
) ? initial_flush_preamble_cs
: initial_preamble_cs
;
4534 const struct radv_winsys_bo_list
*bo_list
= NULL
;
4536 advance
= MIN2(max_cs_submission
,
4537 submission
->cmd_buffer_count
- j
);
4539 if (queue
->device
->trace_bo
)
4540 *queue
->device
->trace_id_ptr
= 0;
4542 sem_info
.cs_emit_wait
= j
== 0;
4543 sem_info
.cs_emit_signal
= j
+ advance
== submission
->cmd_buffer_count
;
4545 if (unlikely(queue
->device
->use_global_bo_list
)) {
4546 pthread_mutex_lock(&queue
->device
->bo_list
.mutex
);
4547 bo_list
= &queue
->device
->bo_list
.list
;
4550 result
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
, cs_array
+ j
,
4551 advance
, initial_preamble
, continue_preamble_cs
,
4553 can_patch
, base_fence
);
4555 if (unlikely(queue
->device
->use_global_bo_list
))
4556 pthread_mutex_unlock(&queue
->device
->bo_list
.mutex
);
4558 if (result
!= VK_SUCCESS
)
4561 if (queue
->device
->trace_bo
) {
4562 radv_check_gpu_hangs(queue
, cs_array
[j
]);
4565 if (queue
->device
->tma_bo
) {
4566 radv_check_trap_handler(queue
);
4573 radv_free_temp_syncobjs(queue
->device
,
4574 submission
->temporary_semaphore_part_count
,
4575 submission
->temporary_semaphore_parts
);
4576 radv_finalize_timelines(queue
->device
,
4577 submission
->wait_semaphore_count
,
4578 submission
->wait_semaphores
,
4579 submission
->wait_values
,
4580 submission
->signal_semaphore_count
,
4581 submission
->signal_semaphores
,
4582 submission
->signal_values
,
4584 /* Has to happen after timeline finalization to make sure the
4585 * condition variable is only triggered when timelines and queue have
4587 radv_queue_submission_update_queue(submission
, processing_list
);
4588 radv_free_sem_info(&sem_info
);
4593 if (result
!= VK_SUCCESS
&& result
!= VK_ERROR_DEVICE_LOST
) {
4594 /* When something bad happened during the submission, such as
4595 * an out of memory issue, it might be hard to recover from
4596 * this inconsistent state. To avoid this sort of problem, we
4597 * assume that we are in a really bad situation and return
4598 * VK_ERROR_DEVICE_LOST to ensure the clients do not attempt
4599 * to submit the same job again to this device.
4601 result
= radv_device_set_lost(queue
->device
, "vkQueueSubmit() failed");
4604 radv_free_temp_syncobjs(queue
->device
,
4605 submission
->temporary_semaphore_part_count
,
4606 submission
->temporary_semaphore_parts
);
4612 radv_process_submissions(struct list_head
*processing_list
)
4614 while(!list_is_empty(processing_list
)) {
4615 struct radv_deferred_queue_submission
*submission
=
4616 list_first_entry(processing_list
, struct radv_deferred_queue_submission
, processing_list
);
4617 list_del(&submission
->processing_list
);
4619 VkResult result
= radv_queue_submit_deferred(submission
, processing_list
);
4620 if (result
!= VK_SUCCESS
)
4627 wait_for_submission_timelines_available(struct radv_deferred_queue_submission
*submission
,
4630 struct radv_device
*device
= submission
->queue
->device
;
4631 uint32_t syncobj_count
= 0;
4632 uint32_t syncobj_idx
= 0;
4634 for (uint32_t i
= 0; i
< submission
->wait_semaphore_count
; ++i
) {
4635 if (submission
->wait_semaphores
[i
]->kind
!= RADV_SEMAPHORE_TIMELINE_SYNCOBJ
)
4638 if (submission
->wait_semaphores
[i
]->timeline_syncobj
.max_point
>= submission
->wait_values
[i
])
4646 uint64_t *points
= malloc((sizeof(uint64_t) + sizeof(uint32_t)) * syncobj_count
);
4648 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4650 uint32_t *syncobj
= (uint32_t*)(points
+ syncobj_count
);
4652 for (uint32_t i
= 0; i
< submission
->wait_semaphore_count
; ++i
) {
4653 if (submission
->wait_semaphores
[i
]->kind
!= RADV_SEMAPHORE_TIMELINE_SYNCOBJ
)
4656 if (submission
->wait_semaphores
[i
]->timeline_syncobj
.max_point
>= submission
->wait_values
[i
])
4659 syncobj
[syncobj_idx
] = submission
->wait_semaphores
[i
]->syncobj
;
4660 points
[syncobj_idx
] = submission
->wait_values
[i
];
4663 bool success
= device
->ws
->wait_timeline_syncobj(device
->ws
, syncobj
, points
, syncobj_idx
, true, true, timeout
);
4666 return success
? VK_SUCCESS
: VK_TIMEOUT
;
4669 static void* radv_queue_submission_thread_run(void *q
)
4671 struct radv_queue
*queue
= q
;
4673 pthread_mutex_lock(&queue
->thread_mutex
);
4674 while (!p_atomic_read(&queue
->thread_exit
)) {
4675 struct radv_deferred_queue_submission
*submission
= queue
->thread_submission
;
4676 struct list_head processing_list
;
4677 VkResult result
= VK_SUCCESS
;
4679 pthread_cond_wait(&queue
->thread_cond
, &queue
->thread_mutex
);
4682 pthread_mutex_unlock(&queue
->thread_mutex
);
4684 /* Wait at most 5 seconds so we have a chance to notice shutdown when
4685 * a semaphore never gets signaled. If it takes longer we just retry
4686 * the wait next iteration. */
4687 result
= wait_for_submission_timelines_available(submission
,
4688 radv_get_absolute_timeout(5000000000));
4689 if (result
!= VK_SUCCESS
) {
4690 pthread_mutex_lock(&queue
->thread_mutex
);
4694 /* The lock isn't held but nobody will add one until we finish
4695 * the current submission. */
4696 p_atomic_set(&queue
->thread_submission
, NULL
);
4698 list_inithead(&processing_list
);
4699 list_addtail(&submission
->processing_list
, &processing_list
);
4700 result
= radv_process_submissions(&processing_list
);
4702 pthread_mutex_lock(&queue
->thread_mutex
);
4704 pthread_mutex_unlock(&queue
->thread_mutex
);
4709 radv_queue_trigger_submission(struct radv_deferred_queue_submission
*submission
,
4711 struct list_head
*processing_list
)
4713 struct radv_queue
*queue
= submission
->queue
;
4715 if (p_atomic_add_return(&submission
->submission_wait_count
, -decrement
))
4718 if (wait_for_submission_timelines_available(submission
, radv_get_absolute_timeout(0)) == VK_SUCCESS
) {
4719 list_addtail(&submission
->processing_list
, processing_list
);
4723 pthread_mutex_lock(&queue
->thread_mutex
);
4725 /* A submission can only be ready for the thread if it doesn't have
4726 * any predecessors in the same queue, so there can only be one such
4727 * submission at a time. */
4728 assert(queue
->thread_submission
== NULL
);
4730 /* Only start the thread on demand to save resources for the many games
4731 * which only use binary semaphores. */
4732 if (!queue
->thread_running
) {
4733 ret
= pthread_create(&queue
->submission_thread
, NULL
,
4734 radv_queue_submission_thread_run
, queue
);
4736 pthread_mutex_unlock(&queue
->thread_mutex
);
4737 return vk_errorf(queue
->device
->instance
,
4738 VK_ERROR_DEVICE_LOST
,
4739 "Failed to start submission thread");
4741 queue
->thread_running
= true;
4744 queue
->thread_submission
= submission
;
4745 pthread_mutex_unlock(&queue
->thread_mutex
);
4747 pthread_cond_signal(&queue
->thread_cond
);
4751 static VkResult
radv_queue_submit(struct radv_queue
*queue
,
4752 const struct radv_queue_submission
*submission
)
4754 struct radv_deferred_queue_submission
*deferred
= NULL
;
4756 VkResult result
= radv_create_deferred_submission(queue
, submission
, &deferred
);
4757 if (result
!= VK_SUCCESS
)
4760 struct list_head processing_list
;
4761 list_inithead(&processing_list
);
4763 result
= radv_queue_enqueue_submission(deferred
, &processing_list
);
4764 if (result
!= VK_SUCCESS
) {
4765 /* If anything is in the list we leak. */
4766 assert(list_is_empty(&processing_list
));
4769 return radv_process_submissions(&processing_list
);
4773 radv_queue_internal_submit(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
)
4775 struct radeon_winsys_ctx
*ctx
= queue
->hw_ctx
;
4776 struct radv_winsys_sem_info sem_info
;
4779 result
= radv_alloc_sem_info(queue
->device
, &sem_info
, 0, NULL
, 0, 0,
4780 0, NULL
, VK_NULL_HANDLE
);
4781 if (result
!= VK_SUCCESS
)
4784 result
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
, &cs
, 1,
4785 NULL
, NULL
, &sem_info
, NULL
,
4787 radv_free_sem_info(&sem_info
);
4788 if (result
!= VK_SUCCESS
)
4795 /* Signals fence as soon as all the work currently put on queue is done. */
4796 static VkResult
radv_signal_fence(struct radv_queue
*queue
,
4799 return radv_queue_submit(queue
, &(struct radv_queue_submission
) {
4804 static bool radv_submit_has_effects(const VkSubmitInfo
*info
)
4806 return info
->commandBufferCount
||
4807 info
->waitSemaphoreCount
||
4808 info
->signalSemaphoreCount
;
4811 VkResult
radv_QueueSubmit(
4813 uint32_t submitCount
,
4814 const VkSubmitInfo
* pSubmits
,
4817 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
4819 uint32_t fence_idx
= 0;
4820 bool flushed_caches
= false;
4822 if (radv_device_is_lost(queue
->device
))
4823 return VK_ERROR_DEVICE_LOST
;
4825 if (fence
!= VK_NULL_HANDLE
) {
4826 for (uint32_t i
= 0; i
< submitCount
; ++i
)
4827 if (radv_submit_has_effects(pSubmits
+ i
))
4830 fence_idx
= UINT32_MAX
;
4832 for (uint32_t i
= 0; i
< submitCount
; i
++) {
4833 if (!radv_submit_has_effects(pSubmits
+ i
) && fence_idx
!= i
)
4836 VkPipelineStageFlags wait_dst_stage_mask
= 0;
4837 for (unsigned j
= 0; j
< pSubmits
[i
].waitSemaphoreCount
; ++j
) {
4838 wait_dst_stage_mask
|= pSubmits
[i
].pWaitDstStageMask
[j
];
4841 const VkTimelineSemaphoreSubmitInfo
*timeline_info
=
4842 vk_find_struct_const(pSubmits
[i
].pNext
, TIMELINE_SEMAPHORE_SUBMIT_INFO
);
4844 result
= radv_queue_submit(queue
, &(struct radv_queue_submission
) {
4845 .cmd_buffers
= pSubmits
[i
].pCommandBuffers
,
4846 .cmd_buffer_count
= pSubmits
[i
].commandBufferCount
,
4847 .wait_dst_stage_mask
= wait_dst_stage_mask
,
4848 .flush_caches
= !flushed_caches
,
4849 .wait_semaphores
= pSubmits
[i
].pWaitSemaphores
,
4850 .wait_semaphore_count
= pSubmits
[i
].waitSemaphoreCount
,
4851 .signal_semaphores
= pSubmits
[i
].pSignalSemaphores
,
4852 .signal_semaphore_count
= pSubmits
[i
].signalSemaphoreCount
,
4853 .fence
= i
== fence_idx
? fence
: VK_NULL_HANDLE
,
4854 .wait_values
= timeline_info
? timeline_info
->pWaitSemaphoreValues
: NULL
,
4855 .wait_value_count
= timeline_info
&& timeline_info
->pWaitSemaphoreValues
? timeline_info
->waitSemaphoreValueCount
: 0,
4856 .signal_values
= timeline_info
? timeline_info
->pSignalSemaphoreValues
: NULL
,
4857 .signal_value_count
= timeline_info
&& timeline_info
->pSignalSemaphoreValues
? timeline_info
->signalSemaphoreValueCount
: 0,
4859 if (result
!= VK_SUCCESS
)
4862 flushed_caches
= true;
4865 if (fence
!= VK_NULL_HANDLE
&& !submitCount
) {
4866 result
= radv_signal_fence(queue
, fence
);
4867 if (result
!= VK_SUCCESS
)
4875 radv_get_queue_family_name(struct radv_queue
*queue
)
4877 switch (queue
->queue_family_index
) {
4878 case RADV_QUEUE_GENERAL
:
4880 case RADV_QUEUE_COMPUTE
:
4882 case RADV_QUEUE_TRANSFER
:
4885 unreachable("Unknown queue family");
4889 VkResult
radv_QueueWaitIdle(
4892 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
4894 if (radv_device_is_lost(queue
->device
))
4895 return VK_ERROR_DEVICE_LOST
;
4897 pthread_mutex_lock(&queue
->pending_mutex
);
4898 while (!list_is_empty(&queue
->pending_submissions
)) {
4899 pthread_cond_wait(&queue
->device
->timeline_cond
, &queue
->pending_mutex
);
4901 pthread_mutex_unlock(&queue
->pending_mutex
);
4903 if (!queue
->device
->ws
->ctx_wait_idle(queue
->hw_ctx
,
4904 radv_queue_family_to_ring(queue
->queue_family_index
),
4905 queue
->queue_idx
)) {
4906 return radv_device_set_lost(queue
->device
,
4907 "Failed to wait for a '%s' queue "
4908 "to be idle. GPU hang ?",
4909 radv_get_queue_family_name(queue
));
4915 VkResult
radv_DeviceWaitIdle(
4918 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4920 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
4921 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++) {
4923 radv_QueueWaitIdle(radv_queue_to_handle(&device
->queues
[i
][q
]));
4925 if (result
!= VK_SUCCESS
)
4932 VkResult
radv_EnumerateInstanceExtensionProperties(
4933 const char* pLayerName
,
4934 uint32_t* pPropertyCount
,
4935 VkExtensionProperties
* pProperties
)
4937 VK_OUTARRAY_MAKE(out
, pProperties
, pPropertyCount
);
4939 for (int i
= 0; i
< RADV_INSTANCE_EXTENSION_COUNT
; i
++) {
4940 if (radv_instance_extensions_supported
.extensions
[i
]) {
4941 vk_outarray_append(&out
, prop
) {
4942 *prop
= radv_instance_extensions
[i
];
4947 return vk_outarray_status(&out
);
4950 VkResult
radv_EnumerateDeviceExtensionProperties(
4951 VkPhysicalDevice physicalDevice
,
4952 const char* pLayerName
,
4953 uint32_t* pPropertyCount
,
4954 VkExtensionProperties
* pProperties
)
4956 RADV_FROM_HANDLE(radv_physical_device
, device
, physicalDevice
);
4957 VK_OUTARRAY_MAKE(out
, pProperties
, pPropertyCount
);
4959 for (int i
= 0; i
< RADV_DEVICE_EXTENSION_COUNT
; i
++) {
4960 if (device
->supported_extensions
.extensions
[i
]) {
4961 vk_outarray_append(&out
, prop
) {
4962 *prop
= radv_device_extensions
[i
];
4967 return vk_outarray_status(&out
);
4970 PFN_vkVoidFunction
radv_GetInstanceProcAddr(
4971 VkInstance _instance
,
4974 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
4976 /* The Vulkan 1.0 spec for vkGetInstanceProcAddr has a table of exactly
4977 * when we have to return valid function pointers, NULL, or it's left
4978 * undefined. See the table for exact details.
4983 #define LOOKUP_RADV_ENTRYPOINT(entrypoint) \
4984 if (strcmp(pName, "vk" #entrypoint) == 0) \
4985 return (PFN_vkVoidFunction)radv_##entrypoint
4987 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceExtensionProperties
);
4988 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceLayerProperties
);
4989 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceVersion
);
4990 LOOKUP_RADV_ENTRYPOINT(CreateInstance
);
4992 /* GetInstanceProcAddr() can also be called with a NULL instance.
4993 * See https://gitlab.khronos.org/vulkan/vulkan/issues/2057
4995 LOOKUP_RADV_ENTRYPOINT(GetInstanceProcAddr
);
4997 #undef LOOKUP_RADV_ENTRYPOINT
4999 if (instance
== NULL
)
5002 int idx
= radv_get_instance_entrypoint_index(pName
);
5004 return instance
->dispatch
.entrypoints
[idx
];
5006 idx
= radv_get_physical_device_entrypoint_index(pName
);
5008 return instance
->physical_device_dispatch
.entrypoints
[idx
];
5010 idx
= radv_get_device_entrypoint_index(pName
);
5012 return instance
->device_dispatch
.entrypoints
[idx
];
5017 /* The loader wants us to expose a second GetInstanceProcAddr function
5018 * to work around certain LD_PRELOAD issues seen in apps.
5021 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
5022 VkInstance instance
,
5026 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
5027 VkInstance instance
,
5030 return radv_GetInstanceProcAddr(instance
, pName
);
5034 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetPhysicalDeviceProcAddr(
5035 VkInstance _instance
,
5039 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetPhysicalDeviceProcAddr(
5040 VkInstance _instance
,
5043 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
5045 if (!pName
|| !instance
)
5048 int idx
= radv_get_physical_device_entrypoint_index(pName
);
5052 return instance
->physical_device_dispatch
.entrypoints
[idx
];
5055 PFN_vkVoidFunction
radv_GetDeviceProcAddr(
5059 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5061 if (!device
|| !pName
)
5064 int idx
= radv_get_device_entrypoint_index(pName
);
5068 return device
->dispatch
.entrypoints
[idx
];
5071 bool radv_get_memory_fd(struct radv_device
*device
,
5072 struct radv_device_memory
*memory
,
5075 struct radeon_bo_metadata metadata
;
5077 if (memory
->image
) {
5078 if (memory
->image
->tiling
!= VK_IMAGE_TILING_LINEAR
)
5079 radv_init_metadata(device
, memory
->image
, &metadata
);
5080 device
->ws
->buffer_set_metadata(memory
->bo
, &metadata
);
5083 return device
->ws
->buffer_get_fd(device
->ws
, memory
->bo
,
5089 radv_free_memory(struct radv_device
*device
,
5090 const VkAllocationCallbacks
* pAllocator
,
5091 struct radv_device_memory
*mem
)
5096 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
5097 if (mem
->android_hardware_buffer
)
5098 AHardwareBuffer_release(mem
->android_hardware_buffer
);
5102 if (device
->overallocation_disallowed
) {
5103 mtx_lock(&device
->overallocation_mutex
);
5104 device
->allocated_memory_size
[mem
->heap_index
] -= mem
->alloc_size
;
5105 mtx_unlock(&device
->overallocation_mutex
);
5108 radv_bo_list_remove(device
, mem
->bo
);
5109 device
->ws
->buffer_destroy(mem
->bo
);
5113 vk_object_base_finish(&mem
->base
);
5114 vk_free2(&device
->vk
.alloc
, pAllocator
, mem
);
5117 static VkResult
radv_alloc_memory(struct radv_device
*device
,
5118 const VkMemoryAllocateInfo
* pAllocateInfo
,
5119 const VkAllocationCallbacks
* pAllocator
,
5120 VkDeviceMemory
* pMem
)
5122 struct radv_device_memory
*mem
;
5124 enum radeon_bo_domain domain
;
5127 assert(pAllocateInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO
);
5129 const VkImportMemoryFdInfoKHR
*import_info
=
5130 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_FD_INFO_KHR
);
5131 const VkMemoryDedicatedAllocateInfo
*dedicate_info
=
5132 vk_find_struct_const(pAllocateInfo
->pNext
, MEMORY_DEDICATED_ALLOCATE_INFO
);
5133 const VkExportMemoryAllocateInfo
*export_info
=
5134 vk_find_struct_const(pAllocateInfo
->pNext
, EXPORT_MEMORY_ALLOCATE_INFO
);
5135 const struct VkImportAndroidHardwareBufferInfoANDROID
*ahb_import_info
=
5136 vk_find_struct_const(pAllocateInfo
->pNext
,
5137 IMPORT_ANDROID_HARDWARE_BUFFER_INFO_ANDROID
);
5138 const VkImportMemoryHostPointerInfoEXT
*host_ptr_info
=
5139 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_HOST_POINTER_INFO_EXT
);
5141 const struct wsi_memory_allocate_info
*wsi_info
=
5142 vk_find_struct_const(pAllocateInfo
->pNext
, WSI_MEMORY_ALLOCATE_INFO_MESA
);
5144 if (pAllocateInfo
->allocationSize
== 0 && !ahb_import_info
&&
5145 !(export_info
&& (export_info
->handleTypes
& VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID
))) {
5146 /* Apparently, this is allowed */
5147 *pMem
= VK_NULL_HANDLE
;
5151 mem
= vk_zalloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*mem
), 8,
5152 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5154 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5156 vk_object_base_init(&device
->vk
, &mem
->base
,
5157 VK_OBJECT_TYPE_DEVICE_MEMORY
);
5159 if (wsi_info
&& wsi_info
->implicit_sync
)
5160 flags
|= RADEON_FLAG_IMPLICIT_SYNC
;
5162 if (dedicate_info
) {
5163 mem
->image
= radv_image_from_handle(dedicate_info
->image
);
5164 mem
->buffer
= radv_buffer_from_handle(dedicate_info
->buffer
);
5170 float priority_float
= 0.5;
5171 const struct VkMemoryPriorityAllocateInfoEXT
*priority_ext
=
5172 vk_find_struct_const(pAllocateInfo
->pNext
,
5173 MEMORY_PRIORITY_ALLOCATE_INFO_EXT
);
5175 priority_float
= priority_ext
->priority
;
5177 unsigned priority
= MIN2(RADV_BO_PRIORITY_APPLICATION_MAX
- 1,
5178 (int)(priority_float
* RADV_BO_PRIORITY_APPLICATION_MAX
));
5180 mem
->user_ptr
= NULL
;
5183 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
5184 mem
->android_hardware_buffer
= NULL
;
5187 if (ahb_import_info
) {
5188 result
= radv_import_ahb_memory(device
, mem
, priority
, ahb_import_info
);
5189 if (result
!= VK_SUCCESS
)
5191 } else if(export_info
&& (export_info
->handleTypes
& VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID
)) {
5192 result
= radv_create_ahb_memory(device
, mem
, priority
, pAllocateInfo
);
5193 if (result
!= VK_SUCCESS
)
5195 } else if (import_info
) {
5196 assert(import_info
->handleType
==
5197 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT
||
5198 import_info
->handleType
==
5199 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
5200 mem
->bo
= device
->ws
->buffer_from_fd(device
->ws
, import_info
->fd
,
5203 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE
;
5206 close(import_info
->fd
);
5209 if (mem
->image
&& mem
->image
->plane_count
== 1 &&
5210 !vk_format_is_depth_or_stencil(mem
->image
->vk_format
)) {
5211 struct radeon_bo_metadata metadata
;
5212 device
->ws
->buffer_get_metadata(mem
->bo
, &metadata
);
5214 struct radv_image_create_info create_info
= {
5215 .no_metadata_planes
= true,
5216 .bo_metadata
= &metadata
5219 /* This gives a basic ability to import radeonsi images
5220 * that don't have DCC. This is not guaranteed by any
5221 * spec and can be removed after we support modifiers. */
5222 result
= radv_image_create_layout(device
, create_info
, mem
->image
);
5223 if (result
!= VK_SUCCESS
) {
5224 device
->ws
->buffer_destroy(mem
->bo
);
5228 } else if (host_ptr_info
) {
5229 assert(host_ptr_info
->handleType
== VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT
);
5230 mem
->bo
= device
->ws
->buffer_from_ptr(device
->ws
, host_ptr_info
->pHostPointer
,
5231 pAllocateInfo
->allocationSize
,
5234 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE
;
5237 mem
->user_ptr
= host_ptr_info
->pHostPointer
;
5240 uint64_t alloc_size
= align_u64(pAllocateInfo
->allocationSize
, 4096);
5241 uint32_t heap_index
;
5243 heap_index
= device
->physical_device
->memory_properties
.memoryTypes
[pAllocateInfo
->memoryTypeIndex
].heapIndex
;
5244 domain
= device
->physical_device
->memory_domains
[pAllocateInfo
->memoryTypeIndex
];
5245 flags
|= device
->physical_device
->memory_flags
[pAllocateInfo
->memoryTypeIndex
];
5247 if (!dedicate_info
&& !import_info
&& (!export_info
|| !export_info
->handleTypes
)) {
5248 flags
|= RADEON_FLAG_NO_INTERPROCESS_SHARING
;
5249 if (device
->use_global_bo_list
) {
5250 flags
|= RADEON_FLAG_PREFER_LOCAL_BO
;
5254 if (device
->overallocation_disallowed
) {
5255 uint64_t total_size
=
5256 device
->physical_device
->memory_properties
.memoryHeaps
[heap_index
].size
;
5258 mtx_lock(&device
->overallocation_mutex
);
5259 if (device
->allocated_memory_size
[heap_index
] + alloc_size
> total_size
) {
5260 mtx_unlock(&device
->overallocation_mutex
);
5261 result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
5264 device
->allocated_memory_size
[heap_index
] += alloc_size
;
5265 mtx_unlock(&device
->overallocation_mutex
);
5268 mem
->bo
= device
->ws
->buffer_create(device
->ws
, alloc_size
, device
->physical_device
->rad_info
.max_alignment
,
5269 domain
, flags
, priority
);
5272 if (device
->overallocation_disallowed
) {
5273 mtx_lock(&device
->overallocation_mutex
);
5274 device
->allocated_memory_size
[heap_index
] -= alloc_size
;
5275 mtx_unlock(&device
->overallocation_mutex
);
5277 result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
5281 mem
->heap_index
= heap_index
;
5282 mem
->alloc_size
= alloc_size
;
5286 result
= radv_bo_list_add(device
, mem
->bo
);
5287 if (result
!= VK_SUCCESS
)
5291 *pMem
= radv_device_memory_to_handle(mem
);
5296 radv_free_memory(device
, pAllocator
,mem
);
5301 VkResult
radv_AllocateMemory(
5303 const VkMemoryAllocateInfo
* pAllocateInfo
,
5304 const VkAllocationCallbacks
* pAllocator
,
5305 VkDeviceMemory
* pMem
)
5307 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5308 return radv_alloc_memory(device
, pAllocateInfo
, pAllocator
, pMem
);
5311 void radv_FreeMemory(
5313 VkDeviceMemory _mem
,
5314 const VkAllocationCallbacks
* pAllocator
)
5316 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5317 RADV_FROM_HANDLE(radv_device_memory
, mem
, _mem
);
5319 radv_free_memory(device
, pAllocator
, mem
);
5322 VkResult
radv_MapMemory(
5324 VkDeviceMemory _memory
,
5325 VkDeviceSize offset
,
5327 VkMemoryMapFlags flags
,
5330 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5331 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
5339 *ppData
= mem
->user_ptr
;
5341 *ppData
= device
->ws
->buffer_map(mem
->bo
);
5348 return vk_error(device
->instance
, VK_ERROR_MEMORY_MAP_FAILED
);
5351 void radv_UnmapMemory(
5353 VkDeviceMemory _memory
)
5355 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5356 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
5361 if (mem
->user_ptr
== NULL
)
5362 device
->ws
->buffer_unmap(mem
->bo
);
5365 VkResult
radv_FlushMappedMemoryRanges(
5367 uint32_t memoryRangeCount
,
5368 const VkMappedMemoryRange
* pMemoryRanges
)
5373 VkResult
radv_InvalidateMappedMemoryRanges(
5375 uint32_t memoryRangeCount
,
5376 const VkMappedMemoryRange
* pMemoryRanges
)
5381 void radv_GetBufferMemoryRequirements(
5384 VkMemoryRequirements
* pMemoryRequirements
)
5386 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5387 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
5389 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
5391 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
5392 pMemoryRequirements
->alignment
= 4096;
5394 pMemoryRequirements
->alignment
= 16;
5396 pMemoryRequirements
->size
= align64(buffer
->size
, pMemoryRequirements
->alignment
);
5399 void radv_GetBufferMemoryRequirements2(
5401 const VkBufferMemoryRequirementsInfo2
*pInfo
,
5402 VkMemoryRequirements2
*pMemoryRequirements
)
5404 radv_GetBufferMemoryRequirements(device
, pInfo
->buffer
,
5405 &pMemoryRequirements
->memoryRequirements
);
5406 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
5407 switch (ext
->sType
) {
5408 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS
: {
5409 VkMemoryDedicatedRequirements
*req
=
5410 (VkMemoryDedicatedRequirements
*) ext
;
5411 req
->requiresDedicatedAllocation
= false;
5412 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
5421 void radv_GetImageMemoryRequirements(
5424 VkMemoryRequirements
* pMemoryRequirements
)
5426 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5427 RADV_FROM_HANDLE(radv_image
, image
, _image
);
5429 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
5431 pMemoryRequirements
->size
= image
->size
;
5432 pMemoryRequirements
->alignment
= image
->alignment
;
5435 void radv_GetImageMemoryRequirements2(
5437 const VkImageMemoryRequirementsInfo2
*pInfo
,
5438 VkMemoryRequirements2
*pMemoryRequirements
)
5440 radv_GetImageMemoryRequirements(device
, pInfo
->image
,
5441 &pMemoryRequirements
->memoryRequirements
);
5443 RADV_FROM_HANDLE(radv_image
, image
, pInfo
->image
);
5445 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
5446 switch (ext
->sType
) {
5447 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS
: {
5448 VkMemoryDedicatedRequirements
*req
=
5449 (VkMemoryDedicatedRequirements
*) ext
;
5450 req
->requiresDedicatedAllocation
= image
->shareable
&&
5451 image
->tiling
!= VK_IMAGE_TILING_LINEAR
;
5452 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
5461 void radv_GetImageSparseMemoryRequirements(
5464 uint32_t* pSparseMemoryRequirementCount
,
5465 VkSparseImageMemoryRequirements
* pSparseMemoryRequirements
)
5470 void radv_GetImageSparseMemoryRequirements2(
5472 const VkImageSparseMemoryRequirementsInfo2
*pInfo
,
5473 uint32_t* pSparseMemoryRequirementCount
,
5474 VkSparseImageMemoryRequirements2
*pSparseMemoryRequirements
)
5479 void radv_GetDeviceMemoryCommitment(
5481 VkDeviceMemory memory
,
5482 VkDeviceSize
* pCommittedMemoryInBytes
)
5484 *pCommittedMemoryInBytes
= 0;
5487 VkResult
radv_BindBufferMemory2(VkDevice device
,
5488 uint32_t bindInfoCount
,
5489 const VkBindBufferMemoryInfo
*pBindInfos
)
5491 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
5492 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
5493 RADV_FROM_HANDLE(radv_buffer
, buffer
, pBindInfos
[i
].buffer
);
5496 buffer
->bo
= mem
->bo
;
5497 buffer
->offset
= pBindInfos
[i
].memoryOffset
;
5505 VkResult
radv_BindBufferMemory(
5508 VkDeviceMemory memory
,
5509 VkDeviceSize memoryOffset
)
5511 const VkBindBufferMemoryInfo info
= {
5512 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO
,
5515 .memoryOffset
= memoryOffset
5518 return radv_BindBufferMemory2(device
, 1, &info
);
5521 VkResult
radv_BindImageMemory2(VkDevice device
,
5522 uint32_t bindInfoCount
,
5523 const VkBindImageMemoryInfo
*pBindInfos
)
5525 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
5526 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
5527 RADV_FROM_HANDLE(radv_image
, image
, pBindInfos
[i
].image
);
5530 image
->bo
= mem
->bo
;
5531 image
->offset
= pBindInfos
[i
].memoryOffset
;
5541 VkResult
radv_BindImageMemory(
5544 VkDeviceMemory memory
,
5545 VkDeviceSize memoryOffset
)
5547 const VkBindImageMemoryInfo info
= {
5548 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO
,
5551 .memoryOffset
= memoryOffset
5554 return radv_BindImageMemory2(device
, 1, &info
);
5557 static bool radv_sparse_bind_has_effects(const VkBindSparseInfo
*info
)
5559 return info
->bufferBindCount
||
5560 info
->imageOpaqueBindCount
||
5561 info
->imageBindCount
||
5562 info
->waitSemaphoreCount
||
5563 info
->signalSemaphoreCount
;
5566 VkResult
radv_QueueBindSparse(
5568 uint32_t bindInfoCount
,
5569 const VkBindSparseInfo
* pBindInfo
,
5572 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
5574 uint32_t fence_idx
= 0;
5576 if (radv_device_is_lost(queue
->device
))
5577 return VK_ERROR_DEVICE_LOST
;
5579 if (fence
!= VK_NULL_HANDLE
) {
5580 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
)
5581 if (radv_sparse_bind_has_effects(pBindInfo
+ i
))
5584 fence_idx
= UINT32_MAX
;
5586 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
5587 if (i
!= fence_idx
&& !radv_sparse_bind_has_effects(pBindInfo
+ i
))
5590 const VkTimelineSemaphoreSubmitInfo
*timeline_info
=
5591 vk_find_struct_const(pBindInfo
[i
].pNext
, TIMELINE_SEMAPHORE_SUBMIT_INFO
);
5593 VkResult result
= radv_queue_submit(queue
, &(struct radv_queue_submission
) {
5594 .buffer_binds
= pBindInfo
[i
].pBufferBinds
,
5595 .buffer_bind_count
= pBindInfo
[i
].bufferBindCount
,
5596 .image_opaque_binds
= pBindInfo
[i
].pImageOpaqueBinds
,
5597 .image_opaque_bind_count
= pBindInfo
[i
].imageOpaqueBindCount
,
5598 .wait_semaphores
= pBindInfo
[i
].pWaitSemaphores
,
5599 .wait_semaphore_count
= pBindInfo
[i
].waitSemaphoreCount
,
5600 .signal_semaphores
= pBindInfo
[i
].pSignalSemaphores
,
5601 .signal_semaphore_count
= pBindInfo
[i
].signalSemaphoreCount
,
5602 .fence
= i
== fence_idx
? fence
: VK_NULL_HANDLE
,
5603 .wait_values
= timeline_info
? timeline_info
->pWaitSemaphoreValues
: NULL
,
5604 .wait_value_count
= timeline_info
&& timeline_info
->pWaitSemaphoreValues
? timeline_info
->waitSemaphoreValueCount
: 0,
5605 .signal_values
= timeline_info
? timeline_info
->pSignalSemaphoreValues
: NULL
,
5606 .signal_value_count
= timeline_info
&& timeline_info
->pSignalSemaphoreValues
? timeline_info
->signalSemaphoreValueCount
: 0,
5609 if (result
!= VK_SUCCESS
)
5613 if (fence
!= VK_NULL_HANDLE
&& !bindInfoCount
) {
5614 result
= radv_signal_fence(queue
, fence
);
5615 if (result
!= VK_SUCCESS
)
5623 radv_destroy_fence_part(struct radv_device
*device
,
5624 struct radv_fence_part
*part
)
5626 switch (part
->kind
) {
5627 case RADV_FENCE_NONE
:
5629 case RADV_FENCE_WINSYS
:
5630 device
->ws
->destroy_fence(part
->fence
);
5632 case RADV_FENCE_SYNCOBJ
:
5633 device
->ws
->destroy_syncobj(device
->ws
, part
->syncobj
);
5635 case RADV_FENCE_WSI
:
5636 part
->fence_wsi
->destroy(part
->fence_wsi
);
5639 unreachable("Invalid fence type");
5642 part
->kind
= RADV_FENCE_NONE
;
5646 radv_destroy_fence(struct radv_device
*device
,
5647 const VkAllocationCallbacks
*pAllocator
,
5648 struct radv_fence
*fence
)
5650 radv_destroy_fence_part(device
, &fence
->temporary
);
5651 radv_destroy_fence_part(device
, &fence
->permanent
);
5653 vk_object_base_finish(&fence
->base
);
5654 vk_free2(&device
->vk
.alloc
, pAllocator
, fence
);
5657 VkResult
radv_CreateFence(
5659 const VkFenceCreateInfo
* pCreateInfo
,
5660 const VkAllocationCallbacks
* pAllocator
,
5663 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5664 const VkExportFenceCreateInfo
*export
=
5665 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_FENCE_CREATE_INFO
);
5666 VkExternalFenceHandleTypeFlags handleTypes
=
5667 export
? export
->handleTypes
: 0;
5668 struct radv_fence
*fence
;
5670 fence
= vk_zalloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*fence
), 8,
5671 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5673 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5675 vk_object_base_init(&device
->vk
, &fence
->base
, VK_OBJECT_TYPE_FENCE
);
5677 if (device
->always_use_syncobj
|| handleTypes
) {
5678 fence
->permanent
.kind
= RADV_FENCE_SYNCOBJ
;
5680 bool create_signaled
= false;
5681 if (pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
)
5682 create_signaled
= true;
5684 int ret
= device
->ws
->create_syncobj(device
->ws
, create_signaled
,
5685 &fence
->permanent
.syncobj
);
5687 radv_destroy_fence(device
, pAllocator
, fence
);
5688 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5691 fence
->permanent
.kind
= RADV_FENCE_WINSYS
;
5693 fence
->permanent
.fence
= device
->ws
->create_fence();
5694 if (!fence
->permanent
.fence
) {
5695 vk_free2(&device
->vk
.alloc
, pAllocator
, fence
);
5696 radv_destroy_fence(device
, pAllocator
, fence
);
5697 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5699 if (pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
)
5700 device
->ws
->signal_fence(fence
->permanent
.fence
);
5703 *pFence
= radv_fence_to_handle(fence
);
5709 void radv_DestroyFence(
5712 const VkAllocationCallbacks
* pAllocator
)
5714 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5715 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
5720 radv_destroy_fence(device
, pAllocator
, fence
);
5723 static bool radv_all_fences_plain_and_submitted(struct radv_device
*device
,
5724 uint32_t fenceCount
, const VkFence
*pFences
)
5726 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5727 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5729 struct radv_fence_part
*part
=
5730 fence
->temporary
.kind
!= RADV_FENCE_NONE
?
5731 &fence
->temporary
: &fence
->permanent
;
5732 if (part
->kind
!= RADV_FENCE_WINSYS
||
5733 !device
->ws
->is_fence_waitable(part
->fence
))
5739 static bool radv_all_fences_syncobj(uint32_t fenceCount
, const VkFence
*pFences
)
5741 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5742 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5744 struct radv_fence_part
*part
=
5745 fence
->temporary
.kind
!= RADV_FENCE_NONE
?
5746 &fence
->temporary
: &fence
->permanent
;
5747 if (part
->kind
!= RADV_FENCE_SYNCOBJ
)
5753 VkResult
radv_WaitForFences(
5755 uint32_t fenceCount
,
5756 const VkFence
* pFences
,
5760 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5762 if (radv_device_is_lost(device
))
5763 return VK_ERROR_DEVICE_LOST
;
5765 timeout
= radv_get_absolute_timeout(timeout
);
5767 if (device
->always_use_syncobj
&&
5768 radv_all_fences_syncobj(fenceCount
, pFences
))
5770 uint32_t *handles
= malloc(sizeof(uint32_t) * fenceCount
);
5772 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5774 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5775 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5777 struct radv_fence_part
*part
=
5778 fence
->temporary
.kind
!= RADV_FENCE_NONE
?
5779 &fence
->temporary
: &fence
->permanent
;
5781 assert(part
->kind
== RADV_FENCE_SYNCOBJ
);
5782 handles
[i
] = part
->syncobj
;
5785 bool success
= device
->ws
->wait_syncobj(device
->ws
, handles
, fenceCount
, waitAll
, timeout
);
5788 return success
? VK_SUCCESS
: VK_TIMEOUT
;
5791 if (!waitAll
&& fenceCount
> 1) {
5792 /* Not doing this by default for waitAll, due to needing to allocate twice. */
5793 if (device
->physical_device
->rad_info
.drm_minor
>= 10 && radv_all_fences_plain_and_submitted(device
, fenceCount
, pFences
)) {
5794 uint32_t wait_count
= 0;
5795 struct radeon_winsys_fence
**fences
= malloc(sizeof(struct radeon_winsys_fence
*) * fenceCount
);
5797 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5799 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5800 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5802 struct radv_fence_part
*part
=
5803 fence
->temporary
.kind
!= RADV_FENCE_NONE
?
5804 &fence
->temporary
: &fence
->permanent
;
5805 assert(part
->kind
== RADV_FENCE_WINSYS
);
5807 if (device
->ws
->fence_wait(device
->ws
, part
->fence
, false, 0)) {
5812 fences
[wait_count
++] = part
->fence
;
5815 bool success
= device
->ws
->fences_wait(device
->ws
, fences
, wait_count
,
5816 waitAll
, timeout
- radv_get_current_time());
5819 return success
? VK_SUCCESS
: VK_TIMEOUT
;
5822 while(radv_get_current_time() <= timeout
) {
5823 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5824 if (radv_GetFenceStatus(_device
, pFences
[i
]) == VK_SUCCESS
)
5831 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5832 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5833 bool expired
= false;
5835 struct radv_fence_part
*part
=
5836 fence
->temporary
.kind
!= RADV_FENCE_NONE
?
5837 &fence
->temporary
: &fence
->permanent
;
5839 switch (part
->kind
) {
5840 case RADV_FENCE_NONE
:
5842 case RADV_FENCE_WINSYS
:
5843 if (!device
->ws
->is_fence_waitable(part
->fence
)) {
5844 while (!device
->ws
->is_fence_waitable(part
->fence
) &&
5845 radv_get_current_time() <= timeout
)
5849 expired
= device
->ws
->fence_wait(device
->ws
,
5855 case RADV_FENCE_SYNCOBJ
:
5856 if (!device
->ws
->wait_syncobj(device
->ws
,
5857 &part
->syncobj
, 1, true,
5861 case RADV_FENCE_WSI
: {
5862 VkResult result
= part
->fence_wsi
->wait(part
->fence_wsi
, timeout
);
5863 if (result
!= VK_SUCCESS
)
5868 unreachable("Invalid fence type");
5875 VkResult
radv_ResetFences(VkDevice _device
,
5876 uint32_t fenceCount
,
5877 const VkFence
*pFences
)
5879 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5881 for (unsigned i
= 0; i
< fenceCount
; ++i
) {
5882 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5884 /* From the Vulkan 1.0.53 spec:
5886 * "If any member of pFences currently has its payload
5887 * imported with temporary permanence, that fence’s prior
5888 * permanent payload is irst restored. The remaining
5889 * operations described therefore operate on the restored
5892 if (fence
->temporary
.kind
!= RADV_FENCE_NONE
)
5893 radv_destroy_fence_part(device
, &fence
->temporary
);
5895 struct radv_fence_part
*part
= &fence
->permanent
;
5897 switch (part
->kind
) {
5898 case RADV_FENCE_WSI
:
5899 device
->ws
->reset_fence(part
->fence
);
5901 case RADV_FENCE_SYNCOBJ
:
5902 device
->ws
->reset_syncobj(device
->ws
, part
->syncobj
);
5905 unreachable("Invalid fence type");
5912 VkResult
radv_GetFenceStatus(VkDevice _device
, VkFence _fence
)
5914 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5915 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
5917 struct radv_fence_part
*part
=
5918 fence
->temporary
.kind
!= RADV_FENCE_NONE
?
5919 &fence
->temporary
: &fence
->permanent
;
5921 if (radv_device_is_lost(device
))
5922 return VK_ERROR_DEVICE_LOST
;
5924 switch (part
->kind
) {
5925 case RADV_FENCE_NONE
:
5927 case RADV_FENCE_WINSYS
:
5928 if (!device
->ws
->fence_wait(device
->ws
, part
->fence
, false, 0))
5929 return VK_NOT_READY
;
5931 case RADV_FENCE_SYNCOBJ
: {
5932 bool success
= device
->ws
->wait_syncobj(device
->ws
,
5933 &part
->syncobj
, 1, true, 0);
5935 return VK_NOT_READY
;
5938 case RADV_FENCE_WSI
: {
5939 VkResult result
= part
->fence_wsi
->wait(part
->fence_wsi
, 0);
5940 if (result
!= VK_SUCCESS
) {
5941 if (result
== VK_TIMEOUT
)
5942 return VK_NOT_READY
;
5948 unreachable("Invalid fence type");
5955 // Queue semaphore functions
5958 radv_create_timeline(struct radv_timeline
*timeline
, uint64_t value
)
5960 timeline
->highest_signaled
= value
;
5961 timeline
->highest_submitted
= value
;
5962 list_inithead(&timeline
->points
);
5963 list_inithead(&timeline
->free_points
);
5964 list_inithead(&timeline
->waiters
);
5965 pthread_mutex_init(&timeline
->mutex
, NULL
);
5969 radv_destroy_timeline(struct radv_device
*device
,
5970 struct radv_timeline
*timeline
)
5972 list_for_each_entry_safe(struct radv_timeline_point
, point
,
5973 &timeline
->free_points
, list
) {
5974 list_del(&point
->list
);
5975 device
->ws
->destroy_syncobj(device
->ws
, point
->syncobj
);
5978 list_for_each_entry_safe(struct radv_timeline_point
, point
,
5979 &timeline
->points
, list
) {
5980 list_del(&point
->list
);
5981 device
->ws
->destroy_syncobj(device
->ws
, point
->syncobj
);
5984 pthread_mutex_destroy(&timeline
->mutex
);
5988 radv_timeline_gc_locked(struct radv_device
*device
,
5989 struct radv_timeline
*timeline
)
5991 list_for_each_entry_safe(struct radv_timeline_point
, point
,
5992 &timeline
->points
, list
) {
5993 if (point
->wait_count
|| point
->value
> timeline
->highest_submitted
)
5996 if (device
->ws
->wait_syncobj(device
->ws
, &point
->syncobj
, 1, true, 0)) {
5997 timeline
->highest_signaled
= point
->value
;
5998 list_del(&point
->list
);
5999 list_add(&point
->list
, &timeline
->free_points
);
6004 static struct radv_timeline_point
*
6005 radv_timeline_find_point_at_least_locked(struct radv_device
*device
,
6006 struct radv_timeline
*timeline
,
6009 radv_timeline_gc_locked(device
, timeline
);
6011 if (p
<= timeline
->highest_signaled
)
6014 list_for_each_entry(struct radv_timeline_point
, point
,
6015 &timeline
->points
, list
) {
6016 if (point
->value
>= p
) {
6017 ++point
->wait_count
;
6024 static struct radv_timeline_point
*
6025 radv_timeline_add_point_locked(struct radv_device
*device
,
6026 struct radv_timeline
*timeline
,
6029 radv_timeline_gc_locked(device
, timeline
);
6031 struct radv_timeline_point
*ret
= NULL
;
6032 struct radv_timeline_point
*prev
= NULL
;
6035 if (p
<= timeline
->highest_signaled
)
6038 list_for_each_entry(struct radv_timeline_point
, point
,
6039 &timeline
->points
, list
) {
6040 if (point
->value
== p
) {
6044 if (point
->value
< p
)
6048 if (list_is_empty(&timeline
->free_points
)) {
6049 ret
= malloc(sizeof(struct radv_timeline_point
));
6050 r
= device
->ws
->create_syncobj(device
->ws
, false, &ret
->syncobj
);
6056 ret
= list_first_entry(&timeline
->free_points
, struct radv_timeline_point
, list
);
6057 list_del(&ret
->list
);
6059 device
->ws
->reset_syncobj(device
->ws
, ret
->syncobj
);
6063 ret
->wait_count
= 1;
6066 list_add(&ret
->list
, &prev
->list
);
6068 list_addtail(&ret
->list
, &timeline
->points
);
6075 radv_timeline_wait(struct radv_device
*device
,
6076 struct radv_timeline
*timeline
,
6078 uint64_t abs_timeout
)
6080 pthread_mutex_lock(&timeline
->mutex
);
6082 while(timeline
->highest_submitted
< value
) {
6083 struct timespec abstime
;
6084 timespec_from_nsec(&abstime
, abs_timeout
);
6086 pthread_cond_timedwait(&device
->timeline_cond
, &timeline
->mutex
, &abstime
);
6088 if (radv_get_current_time() >= abs_timeout
&& timeline
->highest_submitted
< value
) {
6089 pthread_mutex_unlock(&timeline
->mutex
);
6094 struct radv_timeline_point
*point
= radv_timeline_find_point_at_least_locked(device
, timeline
, value
);
6095 pthread_mutex_unlock(&timeline
->mutex
);
6099 bool success
= device
->ws
->wait_syncobj(device
->ws
, &point
->syncobj
, 1, true, abs_timeout
);
6101 pthread_mutex_lock(&timeline
->mutex
);
6102 point
->wait_count
--;
6103 pthread_mutex_unlock(&timeline
->mutex
);
6104 return success
? VK_SUCCESS
: VK_TIMEOUT
;
6108 radv_timeline_trigger_waiters_locked(struct radv_timeline
*timeline
,
6109 struct list_head
*processing_list
)
6111 list_for_each_entry_safe(struct radv_timeline_waiter
, waiter
,
6112 &timeline
->waiters
, list
) {
6113 if (waiter
->value
> timeline
->highest_submitted
)
6116 radv_queue_trigger_submission(waiter
->submission
, 1, processing_list
);
6117 list_del(&waiter
->list
);
6122 void radv_destroy_semaphore_part(struct radv_device
*device
,
6123 struct radv_semaphore_part
*part
)
6125 switch(part
->kind
) {
6126 case RADV_SEMAPHORE_NONE
:
6128 case RADV_SEMAPHORE_WINSYS
:
6129 device
->ws
->destroy_sem(part
->ws_sem
);
6131 case RADV_SEMAPHORE_TIMELINE
:
6132 radv_destroy_timeline(device
, &part
->timeline
);
6134 case RADV_SEMAPHORE_SYNCOBJ
:
6135 case RADV_SEMAPHORE_TIMELINE_SYNCOBJ
:
6136 device
->ws
->destroy_syncobj(device
->ws
, part
->syncobj
);
6139 part
->kind
= RADV_SEMAPHORE_NONE
;
6142 static VkSemaphoreTypeKHR
6143 radv_get_semaphore_type(const void *pNext
, uint64_t *initial_value
)
6145 const VkSemaphoreTypeCreateInfo
*type_info
=
6146 vk_find_struct_const(pNext
, SEMAPHORE_TYPE_CREATE_INFO
);
6149 return VK_SEMAPHORE_TYPE_BINARY
;
6152 *initial_value
= type_info
->initialValue
;
6153 return type_info
->semaphoreType
;
6157 radv_destroy_semaphore(struct radv_device
*device
,
6158 const VkAllocationCallbacks
*pAllocator
,
6159 struct radv_semaphore
*sem
)
6161 radv_destroy_semaphore_part(device
, &sem
->temporary
);
6162 radv_destroy_semaphore_part(device
, &sem
->permanent
);
6163 vk_object_base_finish(&sem
->base
);
6164 vk_free2(&device
->vk
.alloc
, pAllocator
, sem
);
6167 VkResult
radv_CreateSemaphore(
6169 const VkSemaphoreCreateInfo
* pCreateInfo
,
6170 const VkAllocationCallbacks
* pAllocator
,
6171 VkSemaphore
* pSemaphore
)
6173 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6174 const VkExportSemaphoreCreateInfo
*export
=
6175 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_SEMAPHORE_CREATE_INFO
);
6176 VkExternalSemaphoreHandleTypeFlags handleTypes
=
6177 export
? export
->handleTypes
: 0;
6178 uint64_t initial_value
= 0;
6179 VkSemaphoreTypeKHR type
= radv_get_semaphore_type(pCreateInfo
->pNext
, &initial_value
);
6181 struct radv_semaphore
*sem
= vk_alloc2(&device
->vk
.alloc
, pAllocator
,
6183 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
6185 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6187 vk_object_base_init(&device
->vk
, &sem
->base
,
6188 VK_OBJECT_TYPE_SEMAPHORE
);
6190 sem
->temporary
.kind
= RADV_SEMAPHORE_NONE
;
6191 sem
->permanent
.kind
= RADV_SEMAPHORE_NONE
;
6193 if (type
== VK_SEMAPHORE_TYPE_TIMELINE
&&
6194 device
->physical_device
->rad_info
.has_timeline_syncobj
) {
6195 int ret
= device
->ws
->create_syncobj(device
->ws
, false, &sem
->permanent
.syncobj
);
6197 radv_destroy_semaphore(device
, pAllocator
, sem
);
6198 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6200 device
->ws
->signal_syncobj(device
->ws
, sem
->permanent
.syncobj
, initial_value
);
6201 sem
->permanent
.timeline_syncobj
.max_point
= initial_value
;
6202 sem
->permanent
.kind
= RADV_SEMAPHORE_TIMELINE_SYNCOBJ
;
6203 } else if (type
== VK_SEMAPHORE_TYPE_TIMELINE
) {
6204 radv_create_timeline(&sem
->permanent
.timeline
, initial_value
);
6205 sem
->permanent
.kind
= RADV_SEMAPHORE_TIMELINE
;
6206 } else if (device
->always_use_syncobj
|| handleTypes
) {
6207 assert (device
->physical_device
->rad_info
.has_syncobj
);
6208 int ret
= device
->ws
->create_syncobj(device
->ws
, false,
6209 &sem
->permanent
.syncobj
);
6211 radv_destroy_semaphore(device
, pAllocator
, sem
);
6212 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6214 sem
->permanent
.kind
= RADV_SEMAPHORE_SYNCOBJ
;
6216 sem
->permanent
.ws_sem
= device
->ws
->create_sem(device
->ws
);
6217 if (!sem
->permanent
.ws_sem
) {
6218 radv_destroy_semaphore(device
, pAllocator
, sem
);
6219 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6221 sem
->permanent
.kind
= RADV_SEMAPHORE_WINSYS
;
6224 *pSemaphore
= radv_semaphore_to_handle(sem
);
6228 void radv_DestroySemaphore(
6230 VkSemaphore _semaphore
,
6231 const VkAllocationCallbacks
* pAllocator
)
6233 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6234 RADV_FROM_HANDLE(radv_semaphore
, sem
, _semaphore
);
6238 radv_destroy_semaphore(device
, pAllocator
, sem
);
6242 radv_GetSemaphoreCounterValue(VkDevice _device
,
6243 VkSemaphore _semaphore
,
6246 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6247 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, _semaphore
);
6249 if (radv_device_is_lost(device
))
6250 return VK_ERROR_DEVICE_LOST
;
6252 struct radv_semaphore_part
*part
=
6253 semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
? &semaphore
->temporary
: &semaphore
->permanent
;
6255 switch (part
->kind
) {
6256 case RADV_SEMAPHORE_TIMELINE
: {
6257 pthread_mutex_lock(&part
->timeline
.mutex
);
6258 radv_timeline_gc_locked(device
, &part
->timeline
);
6259 *pValue
= part
->timeline
.highest_signaled
;
6260 pthread_mutex_unlock(&part
->timeline
.mutex
);
6263 case RADV_SEMAPHORE_TIMELINE_SYNCOBJ
: {
6264 return device
->ws
->query_syncobj(device
->ws
, part
->syncobj
, pValue
);
6266 case RADV_SEMAPHORE_NONE
:
6267 case RADV_SEMAPHORE_SYNCOBJ
:
6268 case RADV_SEMAPHORE_WINSYS
:
6269 unreachable("Invalid semaphore type");
6271 unreachable("Unhandled semaphore type");
6276 radv_wait_timelines(struct radv_device
*device
,
6277 const VkSemaphoreWaitInfo
* pWaitInfo
,
6278 uint64_t abs_timeout
)
6280 if ((pWaitInfo
->flags
& VK_SEMAPHORE_WAIT_ANY_BIT_KHR
) && pWaitInfo
->semaphoreCount
> 1) {
6282 for(uint32_t i
= 0; i
< pWaitInfo
->semaphoreCount
; ++i
) {
6283 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, pWaitInfo
->pSemaphores
[i
]);
6284 VkResult result
= radv_timeline_wait(device
, &semaphore
->permanent
.timeline
, pWaitInfo
->pValues
[i
], 0);
6286 if (result
== VK_SUCCESS
)
6289 if (radv_get_current_time() > abs_timeout
)
6294 for(uint32_t i
= 0; i
< pWaitInfo
->semaphoreCount
; ++i
) {
6295 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, pWaitInfo
->pSemaphores
[i
]);
6296 VkResult result
= radv_timeline_wait(device
, &semaphore
->permanent
.timeline
, pWaitInfo
->pValues
[i
], abs_timeout
);
6298 if (result
!= VK_SUCCESS
)
6304 radv_WaitSemaphores(VkDevice _device
,
6305 const VkSemaphoreWaitInfo
* pWaitInfo
,
6308 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6310 if (radv_device_is_lost(device
))
6311 return VK_ERROR_DEVICE_LOST
;
6313 uint64_t abs_timeout
= radv_get_absolute_timeout(timeout
);
6315 if (radv_semaphore_from_handle(pWaitInfo
->pSemaphores
[0])->permanent
.kind
== RADV_SEMAPHORE_TIMELINE
)
6316 return radv_wait_timelines(device
, pWaitInfo
, abs_timeout
);
6318 if (pWaitInfo
->semaphoreCount
> UINT32_MAX
/ sizeof(uint32_t))
6319 return vk_errorf(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
, "semaphoreCount integer overflow");
6321 bool wait_all
= !(pWaitInfo
->flags
& VK_SEMAPHORE_WAIT_ANY_BIT_KHR
);
6322 uint32_t *handles
= malloc(sizeof(*handles
) * pWaitInfo
->semaphoreCount
);
6324 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6326 for (uint32_t i
= 0; i
< pWaitInfo
->semaphoreCount
; ++i
) {
6327 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, pWaitInfo
->pSemaphores
[i
]);
6328 handles
[i
] = semaphore
->permanent
.syncobj
;
6331 bool success
= device
->ws
->wait_timeline_syncobj(device
->ws
, handles
, pWaitInfo
->pValues
,
6332 pWaitInfo
->semaphoreCount
, wait_all
, false,
6335 return success
? VK_SUCCESS
: VK_TIMEOUT
;
6339 radv_SignalSemaphore(VkDevice _device
,
6340 const VkSemaphoreSignalInfo
* pSignalInfo
)
6342 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6343 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, pSignalInfo
->semaphore
);
6345 struct radv_semaphore_part
*part
=
6346 semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
? &semaphore
->temporary
: &semaphore
->permanent
;
6348 switch(part
->kind
) {
6349 case RADV_SEMAPHORE_TIMELINE
: {
6350 pthread_mutex_lock(&part
->timeline
.mutex
);
6351 radv_timeline_gc_locked(device
, &part
->timeline
);
6352 part
->timeline
.highest_submitted
= MAX2(part
->timeline
.highest_submitted
, pSignalInfo
->value
);
6353 part
->timeline
.highest_signaled
= MAX2(part
->timeline
.highest_signaled
, pSignalInfo
->value
);
6355 struct list_head processing_list
;
6356 list_inithead(&processing_list
);
6357 radv_timeline_trigger_waiters_locked(&part
->timeline
, &processing_list
);
6358 pthread_mutex_unlock(&part
->timeline
.mutex
);
6360 VkResult result
= radv_process_submissions(&processing_list
);
6362 /* This needs to happen after radv_process_submissions, so
6363 * that any submitted submissions that are now unblocked get
6364 * processed before we wake the application. This way we
6365 * ensure that any binary semaphores that are now unblocked
6366 * are usable by the application. */
6367 pthread_cond_broadcast(&device
->timeline_cond
);
6371 case RADV_SEMAPHORE_TIMELINE_SYNCOBJ
: {
6372 part
->timeline_syncobj
.max_point
= MAX2(part
->timeline_syncobj
.max_point
, pSignalInfo
->value
);
6373 device
->ws
->signal_syncobj(device
->ws
, part
->syncobj
, pSignalInfo
->value
);
6376 case RADV_SEMAPHORE_NONE
:
6377 case RADV_SEMAPHORE_SYNCOBJ
:
6378 case RADV_SEMAPHORE_WINSYS
:
6379 unreachable("Invalid semaphore type");
6384 static void radv_destroy_event(struct radv_device
*device
,
6385 const VkAllocationCallbacks
* pAllocator
,
6386 struct radv_event
*event
)
6389 device
->ws
->buffer_destroy(event
->bo
);
6391 vk_object_base_finish(&event
->base
);
6392 vk_free2(&device
->vk
.alloc
, pAllocator
, event
);
6395 VkResult
radv_CreateEvent(
6397 const VkEventCreateInfo
* pCreateInfo
,
6398 const VkAllocationCallbacks
* pAllocator
,
6401 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6402 struct radv_event
*event
= vk_alloc2(&device
->vk
.alloc
, pAllocator
,
6404 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
6407 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6409 vk_object_base_init(&device
->vk
, &event
->base
, VK_OBJECT_TYPE_EVENT
);
6411 event
->bo
= device
->ws
->buffer_create(device
->ws
, 8, 8,
6413 RADEON_FLAG_VA_UNCACHED
| RADEON_FLAG_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
,
6414 RADV_BO_PRIORITY_FENCE
);
6416 radv_destroy_event(device
, pAllocator
, event
);
6417 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
6420 event
->map
= (uint64_t*)device
->ws
->buffer_map(event
->bo
);
6422 radv_destroy_event(device
, pAllocator
, event
);
6423 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
6426 *pEvent
= radv_event_to_handle(event
);
6431 void radv_DestroyEvent(
6434 const VkAllocationCallbacks
* pAllocator
)
6436 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6437 RADV_FROM_HANDLE(radv_event
, event
, _event
);
6442 radv_destroy_event(device
, pAllocator
, event
);
6445 VkResult
radv_GetEventStatus(
6449 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6450 RADV_FROM_HANDLE(radv_event
, event
, _event
);
6452 if (radv_device_is_lost(device
))
6453 return VK_ERROR_DEVICE_LOST
;
6455 if (*event
->map
== 1)
6456 return VK_EVENT_SET
;
6457 return VK_EVENT_RESET
;
6460 VkResult
radv_SetEvent(
6464 RADV_FROM_HANDLE(radv_event
, event
, _event
);
6470 VkResult
radv_ResetEvent(
6474 RADV_FROM_HANDLE(radv_event
, event
, _event
);
6481 radv_destroy_buffer(struct radv_device
*device
,
6482 const VkAllocationCallbacks
*pAllocator
,
6483 struct radv_buffer
*buffer
)
6485 if ((buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
) && buffer
->bo
)
6486 device
->ws
->buffer_destroy(buffer
->bo
);
6488 vk_object_base_finish(&buffer
->base
);
6489 vk_free2(&device
->vk
.alloc
, pAllocator
, buffer
);
6492 VkResult
radv_CreateBuffer(
6494 const VkBufferCreateInfo
* pCreateInfo
,
6495 const VkAllocationCallbacks
* pAllocator
,
6498 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6499 struct radv_buffer
*buffer
;
6501 if (pCreateInfo
->size
> RADV_MAX_MEMORY_ALLOCATION_SIZE
)
6502 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
6504 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO
);
6506 buffer
= vk_alloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*buffer
), 8,
6507 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
6509 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6511 vk_object_base_init(&device
->vk
, &buffer
->base
, VK_OBJECT_TYPE_BUFFER
);
6513 buffer
->size
= pCreateInfo
->size
;
6514 buffer
->usage
= pCreateInfo
->usage
;
6517 buffer
->flags
= pCreateInfo
->flags
;
6519 buffer
->shareable
= vk_find_struct_const(pCreateInfo
->pNext
,
6520 EXTERNAL_MEMORY_BUFFER_CREATE_INFO
) != NULL
;
6522 if (pCreateInfo
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
) {
6523 buffer
->bo
= device
->ws
->buffer_create(device
->ws
,
6524 align64(buffer
->size
, 4096),
6525 4096, 0, RADEON_FLAG_VIRTUAL
,
6526 RADV_BO_PRIORITY_VIRTUAL
);
6528 radv_destroy_buffer(device
, pAllocator
, buffer
);
6529 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
6533 *pBuffer
= radv_buffer_to_handle(buffer
);
6538 void radv_DestroyBuffer(
6541 const VkAllocationCallbacks
* pAllocator
)
6543 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6544 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
6549 radv_destroy_buffer(device
, pAllocator
, buffer
);
6552 VkDeviceAddress
radv_GetBufferDeviceAddress(
6554 const VkBufferDeviceAddressInfo
* pInfo
)
6556 RADV_FROM_HANDLE(radv_buffer
, buffer
, pInfo
->buffer
);
6557 return radv_buffer_get_va(buffer
->bo
) + buffer
->offset
;
6561 uint64_t radv_GetBufferOpaqueCaptureAddress(VkDevice device
,
6562 const VkBufferDeviceAddressInfo
* pInfo
)
6567 uint64_t radv_GetDeviceMemoryOpaqueCaptureAddress(VkDevice device
,
6568 const VkDeviceMemoryOpaqueCaptureAddressInfo
* pInfo
)
6573 static inline unsigned
6574 si_tile_mode_index(const struct radv_image_plane
*plane
, unsigned level
, bool stencil
)
6577 return plane
->surface
.u
.legacy
.stencil_tiling_index
[level
];
6579 return plane
->surface
.u
.legacy
.tiling_index
[level
];
6582 static uint32_t radv_surface_max_layer_count(struct radv_image_view
*iview
)
6584 return iview
->type
== VK_IMAGE_VIEW_TYPE_3D
? iview
->extent
.depth
: (iview
->base_layer
+ iview
->layer_count
);
6588 radv_init_dcc_control_reg(struct radv_device
*device
,
6589 struct radv_image_view
*iview
)
6591 unsigned max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_256B
;
6592 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
6593 unsigned max_compressed_block_size
;
6594 unsigned independent_128b_blocks
;
6595 unsigned independent_64b_blocks
;
6597 if (!radv_dcc_enabled(iview
->image
, iview
->base_mip
))
6600 if (!device
->physical_device
->rad_info
.has_dedicated_vram
) {
6601 /* amdvlk: [min-compressed-block-size] should be set to 32 for
6602 * dGPU and 64 for APU because all of our APUs to date use
6603 * DIMMs which have a request granularity size of 64B while all
6604 * other chips have a 32B request size.
6606 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
6609 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6610 max_compressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
6611 independent_64b_blocks
= 0;
6612 independent_128b_blocks
= 1;
6614 independent_128b_blocks
= 0;
6616 if (iview
->image
->info
.samples
> 1) {
6617 if (iview
->image
->planes
[0].surface
.bpe
== 1)
6618 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
6619 else if (iview
->image
->planes
[0].surface
.bpe
== 2)
6620 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
6623 if (iview
->image
->usage
& (VK_IMAGE_USAGE_SAMPLED_BIT
|
6624 VK_IMAGE_USAGE_TRANSFER_SRC_BIT
|
6625 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
)) {
6626 /* If this DCC image is potentially going to be used in texture
6627 * fetches, we need some special settings.
6629 independent_64b_blocks
= 1;
6630 max_compressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
6632 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
6633 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
6634 * big as possible for better compression state.
6636 independent_64b_blocks
= 0;
6637 max_compressed_block_size
= max_uncompressed_block_size
;
6641 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
6642 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size
) |
6643 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
6644 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks
) |
6645 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks
);
6649 radv_initialise_color_surface(struct radv_device
*device
,
6650 struct radv_color_buffer_info
*cb
,
6651 struct radv_image_view
*iview
)
6653 const struct vk_format_description
*desc
;
6654 unsigned ntype
, format
, swap
, endian
;
6655 unsigned blend_clamp
= 0, blend_bypass
= 0;
6657 const struct radv_image_plane
*plane
= &iview
->image
->planes
[iview
->plane_id
];
6658 const struct radeon_surf
*surf
= &plane
->surface
;
6660 desc
= vk_format_description(iview
->vk_format
);
6662 memset(cb
, 0, sizeof(*cb
));
6664 /* Intensity is implemented as Red, so treat it that way. */
6665 cb
->cb_color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == VK_SWIZZLE_1
);
6667 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+ plane
->offset
;
6669 cb
->cb_color_base
= va
>> 8;
6671 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
6672 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6673 cb
->cb_color_attrib3
|= S_028EE0_COLOR_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
6674 S_028EE0_FMASK_SW_MODE(surf
->u
.gfx9
.fmask
.swizzle_mode
) |
6675 S_028EE0_CMASK_PIPE_ALIGNED(1) |
6676 S_028EE0_DCC_PIPE_ALIGNED(surf
->u
.gfx9
.dcc
.pipe_aligned
);
6678 struct gfx9_surf_meta_flags meta
= {
6683 if (surf
->dcc_offset
)
6684 meta
= surf
->u
.gfx9
.dcc
;
6686 cb
->cb_color_attrib
|= S_028C74_COLOR_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
6687 S_028C74_FMASK_SW_MODE(surf
->u
.gfx9
.fmask
.swizzle_mode
) |
6688 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
6689 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
6690 cb
->cb_mrt_epitch
= S_0287A0_EPITCH(surf
->u
.gfx9
.surf
.epitch
);
6693 cb
->cb_color_base
+= surf
->u
.gfx9
.surf_offset
>> 8;
6694 cb
->cb_color_base
|= surf
->tile_swizzle
;
6696 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[iview
->base_mip
];
6697 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
6699 cb
->cb_color_base
+= level_info
->offset
>> 8;
6700 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
6701 cb
->cb_color_base
|= surf
->tile_swizzle
;
6703 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
6704 slice_tile_max
= (level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1;
6705 tile_mode_index
= si_tile_mode_index(plane
, iview
->base_mip
, false);
6707 cb
->cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
6708 cb
->cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
6709 cb
->cb_color_cmask_slice
= surf
->u
.legacy
.cmask_slice_tile_max
;
6711 cb
->cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
6713 if (radv_image_has_fmask(iview
->image
)) {
6714 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
6715 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(surf
->u
.legacy
.fmask
.pitch_in_pixels
/ 8 - 1);
6716 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(surf
->u
.legacy
.fmask
.tiling_index
);
6717 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(surf
->u
.legacy
.fmask
.slice_tile_max
);
6719 /* This must be set for fast clear to work without FMASK. */
6720 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
6721 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
6722 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
6723 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
6727 /* CMASK variables */
6728 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
6729 va
+= surf
->cmask_offset
;
6730 cb
->cb_color_cmask
= va
>> 8;
6732 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
6733 va
+= surf
->dcc_offset
;
6735 if (radv_dcc_enabled(iview
->image
, iview
->base_mip
) &&
6736 device
->physical_device
->rad_info
.chip_class
<= GFX8
)
6737 va
+= plane
->surface
.u
.legacy
.level
[iview
->base_mip
].dcc_offset
;
6739 unsigned dcc_tile_swizzle
= surf
->tile_swizzle
;
6740 dcc_tile_swizzle
&= (surf
->dcc_alignment
- 1) >> 8;
6742 cb
->cb_dcc_base
= va
>> 8;
6743 cb
->cb_dcc_base
|= dcc_tile_swizzle
;
6745 /* GFX10 field has the same base shift as the GFX6 field. */
6746 uint32_t max_slice
= radv_surface_max_layer_count(iview
) - 1;
6747 cb
->cb_color_view
= S_028C6C_SLICE_START(iview
->base_layer
) |
6748 S_028C6C_SLICE_MAX_GFX10(max_slice
);
6750 if (iview
->image
->info
.samples
> 1) {
6751 unsigned log_samples
= util_logbase2(iview
->image
->info
.samples
);
6753 cb
->cb_color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
6754 S_028C74_NUM_FRAGMENTS(log_samples
);
6757 if (radv_image_has_fmask(iview
->image
)) {
6758 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+ surf
->fmask_offset
;
6759 cb
->cb_color_fmask
= va
>> 8;
6760 cb
->cb_color_fmask
|= surf
->fmask_tile_swizzle
;
6762 cb
->cb_color_fmask
= cb
->cb_color_base
;
6765 ntype
= radv_translate_color_numformat(iview
->vk_format
,
6767 vk_format_get_first_non_void_channel(iview
->vk_format
));
6768 format
= radv_translate_colorformat(iview
->vk_format
);
6769 if (format
== V_028C70_COLOR_INVALID
|| ntype
== ~0u)
6770 radv_finishme("Illegal color\n");
6771 swap
= radv_translate_colorswap(iview
->vk_format
, false);
6772 endian
= radv_colorformat_endian_swap(format
);
6774 /* blend clamp should be set for all NORM/SRGB types */
6775 if (ntype
== V_028C70_NUMBER_UNORM
||
6776 ntype
== V_028C70_NUMBER_SNORM
||
6777 ntype
== V_028C70_NUMBER_SRGB
)
6780 /* set blend bypass according to docs if SINT/UINT or
6781 8/24 COLOR variants */
6782 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
6783 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
6784 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
6789 if ((ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) &&
6790 (format
== V_028C70_COLOR_8
||
6791 format
== V_028C70_COLOR_8_8
||
6792 format
== V_028C70_COLOR_8_8_8_8
))
6793 ->color_is_int8
= true;
6795 cb
->cb_color_info
= S_028C70_FORMAT(format
) |
6796 S_028C70_COMP_SWAP(swap
) |
6797 S_028C70_BLEND_CLAMP(blend_clamp
) |
6798 S_028C70_BLEND_BYPASS(blend_bypass
) |
6799 S_028C70_SIMPLE_FLOAT(1) |
6800 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
6801 ntype
!= V_028C70_NUMBER_SNORM
&&
6802 ntype
!= V_028C70_NUMBER_SRGB
&&
6803 format
!= V_028C70_COLOR_8_24
&&
6804 format
!= V_028C70_COLOR_24_8
) |
6805 S_028C70_NUMBER_TYPE(ntype
) |
6806 S_028C70_ENDIAN(endian
);
6807 if (radv_image_has_fmask(iview
->image
)) {
6808 cb
->cb_color_info
|= S_028C70_COMPRESSION(1);
6809 if (device
->physical_device
->rad_info
.chip_class
== GFX6
) {
6810 unsigned fmask_bankh
= util_logbase2(surf
->u
.legacy
.fmask
.bankh
);
6811 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
6814 if (radv_image_is_tc_compat_cmask(iview
->image
)) {
6815 /* Allow the texture block to read FMASK directly
6816 * without decompressing it. This bit must be cleared
6817 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
6818 * otherwise the operation doesn't happen.
6820 cb
->cb_color_info
|= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
6822 /* Set CMASK into a tiling format that allows the
6823 * texture block to read it.
6825 cb
->cb_color_info
|= S_028C70_CMASK_ADDR_TYPE(2);
6829 if (radv_image_has_cmask(iview
->image
) &&
6830 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_FAST_CLEARS
))
6831 cb
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
6833 if (radv_dcc_enabled(iview
->image
, iview
->base_mip
))
6834 cb
->cb_color_info
|= S_028C70_DCC_ENABLE(1);
6836 cb
->cb_dcc_control
= radv_init_dcc_control_reg(device
, iview
);
6838 /* This must be set for fast clear to work without FMASK. */
6839 if (!radv_image_has_fmask(iview
->image
) &&
6840 device
->physical_device
->rad_info
.chip_class
== GFX6
) {
6841 unsigned bankh
= util_logbase2(surf
->u
.legacy
.bankh
);
6842 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
6845 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
6846 const struct vk_format_description
*format_desc
= vk_format_description(iview
->image
->vk_format
);
6848 unsigned mip0_depth
= iview
->image
->type
== VK_IMAGE_TYPE_3D
?
6849 (iview
->extent
.depth
- 1) : (iview
->image
->info
.array_size
- 1);
6850 unsigned width
= iview
->extent
.width
/ (iview
->plane_id
? format_desc
->width_divisor
: 1);
6851 unsigned height
= iview
->extent
.height
/ (iview
->plane_id
? format_desc
->height_divisor
: 1);
6853 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6854 cb
->cb_color_view
|= S_028C6C_MIP_LEVEL_GFX10(iview
->base_mip
);
6856 cb
->cb_color_attrib3
|= S_028EE0_MIP0_DEPTH(mip0_depth
) |
6857 S_028EE0_RESOURCE_TYPE(surf
->u
.gfx9
.resource_type
) |
6858 S_028EE0_RESOURCE_LEVEL(1);
6860 cb
->cb_color_view
|= S_028C6C_MIP_LEVEL_GFX9(iview
->base_mip
);
6861 cb
->cb_color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
6862 S_028C74_RESOURCE_TYPE(surf
->u
.gfx9
.resource_type
);
6865 cb
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(width
- 1) |
6866 S_028C68_MIP0_HEIGHT(height
- 1) |
6867 S_028C68_MAX_MIP(iview
->image
->info
.levels
- 1);
6872 radv_calc_decompress_on_z_planes(struct radv_device
*device
,
6873 struct radv_image_view
*iview
)
6875 unsigned max_zplanes
= 0;
6877 assert(radv_image_is_tc_compat_htile(iview
->image
));
6879 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
6880 /* Default value for 32-bit depth surfaces. */
6883 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
&&
6884 iview
->image
->info
.samples
> 1)
6887 max_zplanes
= max_zplanes
+ 1;
6889 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
) {
6890 /* Do not enable Z plane compression for 16-bit depth
6891 * surfaces because isn't supported on GFX8. Only
6892 * 32-bit depth surfaces are supported by the hardware.
6893 * This allows to maintain shader compatibility and to
6894 * reduce the number of depth decompressions.
6898 if (iview
->image
->info
.samples
<= 1)
6900 else if (iview
->image
->info
.samples
<= 4)
6911 radv_initialise_ds_surface(struct radv_device
*device
,
6912 struct radv_ds_buffer_info
*ds
,
6913 struct radv_image_view
*iview
)
6915 unsigned level
= iview
->base_mip
;
6916 unsigned format
, stencil_format
;
6917 uint64_t va
, s_offs
, z_offs
;
6918 bool stencil_only
= false;
6919 const struct radv_image_plane
*plane
= &iview
->image
->planes
[0];
6920 const struct radeon_surf
*surf
= &plane
->surface
;
6922 assert(vk_format_get_plane_count(iview
->image
->vk_format
) == 1);
6924 memset(ds
, 0, sizeof(*ds
));
6925 switch (iview
->image
->vk_format
) {
6926 case VK_FORMAT_D24_UNORM_S8_UINT
:
6927 case VK_FORMAT_X8_D24_UNORM_PACK32
:
6928 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
6929 ds
->offset_scale
= 2.0f
;
6931 case VK_FORMAT_D16_UNORM
:
6932 case VK_FORMAT_D16_UNORM_S8_UINT
:
6933 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
6934 ds
->offset_scale
= 4.0f
;
6936 case VK_FORMAT_D32_SFLOAT
:
6937 case VK_FORMAT_D32_SFLOAT_S8_UINT
:
6938 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
6939 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
6940 ds
->offset_scale
= 1.0f
;
6942 case VK_FORMAT_S8_UINT
:
6943 stencil_only
= true;
6949 format
= radv_translate_dbformat(iview
->image
->vk_format
);
6950 stencil_format
= surf
->has_stencil
?
6951 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
6953 uint32_t max_slice
= radv_surface_max_layer_count(iview
) - 1;
6954 ds
->db_depth_view
= S_028008_SLICE_START(iview
->base_layer
) |
6955 S_028008_SLICE_MAX(max_slice
);
6956 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6957 ds
->db_depth_view
|= S_028008_SLICE_START_HI(iview
->base_layer
>> 11) |
6958 S_028008_SLICE_MAX_HI(max_slice
>> 11);
6961 ds
->db_htile_data_base
= 0;
6962 ds
->db_htile_surface
= 0;
6964 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
6965 s_offs
= z_offs
= va
;
6967 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
6968 assert(surf
->u
.gfx9
.surf_offset
== 0);
6969 s_offs
+= surf
->u
.gfx9
.stencil_offset
;
6971 ds
->db_z_info
= S_028038_FORMAT(format
) |
6972 S_028038_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
)) |
6973 S_028038_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
6974 S_028038_MAXMIP(iview
->image
->info
.levels
- 1) |
6975 S_028038_ZRANGE_PRECISION(1);
6976 ds
->db_stencil_info
= S_02803C_FORMAT(stencil_format
) |
6977 S_02803C_SW_MODE(surf
->u
.gfx9
.stencil
.swizzle_mode
);
6979 if (device
->physical_device
->rad_info
.chip_class
== GFX9
) {
6980 ds
->db_z_info2
= S_028068_EPITCH(surf
->u
.gfx9
.surf
.epitch
);
6981 ds
->db_stencil_info2
= S_02806C_EPITCH(surf
->u
.gfx9
.stencil
.epitch
);
6984 ds
->db_depth_view
|= S_028008_MIPID(level
);
6985 ds
->db_depth_size
= S_02801C_X_MAX(iview
->image
->info
.width
- 1) |
6986 S_02801C_Y_MAX(iview
->image
->info
.height
- 1);
6988 if (radv_htile_enabled(iview
->image
, level
)) {
6989 ds
->db_z_info
|= S_028038_TILE_SURFACE_ENABLE(1);
6991 if (radv_image_is_tc_compat_htile(iview
->image
)) {
6992 unsigned max_zplanes
=
6993 radv_calc_decompress_on_z_planes(device
, iview
);
6995 ds
->db_z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
);
6997 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6998 ds
->db_z_info
|= S_028040_ITERATE_FLUSH(1);
6999 ds
->db_stencil_info
|= S_028044_ITERATE_FLUSH(1);
7001 ds
->db_z_info
|= S_028038_ITERATE_FLUSH(1);
7002 ds
->db_stencil_info
|= S_02803C_ITERATE_FLUSH(1);
7006 if (!surf
->has_stencil
)
7007 /* Use all of the htile_buffer for depth if there's no stencil. */
7008 ds
->db_stencil_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
7009 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
7011 ds
->db_htile_data_base
= va
>> 8;
7012 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1) |
7013 S_028ABC_PIPE_ALIGNED(1);
7015 if (device
->physical_device
->rad_info
.chip_class
== GFX9
) {
7016 ds
->db_htile_surface
|= S_028ABC_RB_ALIGNED(1);
7020 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[level
];
7023 level_info
= &surf
->u
.legacy
.stencil_level
[level
];
7025 z_offs
+= surf
->u
.legacy
.level
[level
].offset
;
7026 s_offs
+= surf
->u
.legacy
.stencil_level
[level
].offset
;
7028 ds
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview
->image
));
7029 ds
->db_z_info
= S_028040_FORMAT(format
) | S_028040_ZRANGE_PRECISION(1);
7030 ds
->db_stencil_info
= S_028044_FORMAT(stencil_format
);
7032 if (iview
->image
->info
.samples
> 1)
7033 ds
->db_z_info
|= S_028040_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
));
7035 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
7036 struct radeon_info
*info
= &device
->physical_device
->rad_info
;
7037 unsigned tiling_index
= surf
->u
.legacy
.tiling_index
[level
];
7038 unsigned stencil_index
= surf
->u
.legacy
.stencil_tiling_index
[level
];
7039 unsigned macro_index
= surf
->u
.legacy
.macro_tile_index
;
7040 unsigned tile_mode
= info
->si_tile_mode_array
[tiling_index
];
7041 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
7042 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
7045 tile_mode
= stencil_tile_mode
;
7047 ds
->db_depth_info
|=
7048 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
7049 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
7050 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
7051 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
7052 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
7053 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
7054 ds
->db_z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
7055 ds
->db_stencil_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
7057 unsigned tile_mode_index
= si_tile_mode_index(&iview
->image
->planes
[0], level
, false);
7058 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
7059 tile_mode_index
= si_tile_mode_index(&iview
->image
->planes
[0], level
, true);
7060 ds
->db_stencil_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
7062 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
7065 ds
->db_depth_size
= S_028058_PITCH_TILE_MAX((level_info
->nblk_x
/ 8) - 1) |
7066 S_028058_HEIGHT_TILE_MAX((level_info
->nblk_y
/ 8) - 1);
7067 ds
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1);
7069 if (radv_htile_enabled(iview
->image
, level
)) {
7070 ds
->db_z_info
|= S_028040_TILE_SURFACE_ENABLE(1);
7072 if (!surf
->has_stencil
&&
7073 !radv_image_is_tc_compat_htile(iview
->image
))
7074 /* Use all of the htile_buffer for depth if there's no stencil. */
7075 ds
->db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
7077 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
7079 ds
->db_htile_data_base
= va
>> 8;
7080 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
7082 if (radv_image_is_tc_compat_htile(iview
->image
)) {
7083 unsigned max_zplanes
=
7084 radv_calc_decompress_on_z_planes(device
, iview
);
7086 ds
->db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
7087 ds
->db_z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes
);
7092 ds
->db_z_read_base
= ds
->db_z_write_base
= z_offs
>> 8;
7093 ds
->db_stencil_read_base
= ds
->db_stencil_write_base
= s_offs
>> 8;
7096 VkResult
radv_CreateFramebuffer(
7098 const VkFramebufferCreateInfo
* pCreateInfo
,
7099 const VkAllocationCallbacks
* pAllocator
,
7100 VkFramebuffer
* pFramebuffer
)
7102 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7103 struct radv_framebuffer
*framebuffer
;
7104 const VkFramebufferAttachmentsCreateInfo
*imageless_create_info
=
7105 vk_find_struct_const(pCreateInfo
->pNext
,
7106 FRAMEBUFFER_ATTACHMENTS_CREATE_INFO
);
7108 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
);
7110 size_t size
= sizeof(*framebuffer
);
7111 if (!imageless_create_info
)
7112 size
+= sizeof(struct radv_image_view
*) * pCreateInfo
->attachmentCount
;
7113 framebuffer
= vk_alloc2(&device
->vk
.alloc
, pAllocator
, size
, 8,
7114 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
7115 if (framebuffer
== NULL
)
7116 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
7118 vk_object_base_init(&device
->vk
, &framebuffer
->base
,
7119 VK_OBJECT_TYPE_FRAMEBUFFER
);
7121 framebuffer
->attachment_count
= pCreateInfo
->attachmentCount
;
7122 framebuffer
->width
= pCreateInfo
->width
;
7123 framebuffer
->height
= pCreateInfo
->height
;
7124 framebuffer
->layers
= pCreateInfo
->layers
;
7125 if (imageless_create_info
) {
7126 for (unsigned i
= 0; i
< imageless_create_info
->attachmentImageInfoCount
; ++i
) {
7127 const VkFramebufferAttachmentImageInfo
*attachment
=
7128 imageless_create_info
->pAttachmentImageInfos
+ i
;
7129 framebuffer
->width
= MIN2(framebuffer
->width
, attachment
->width
);
7130 framebuffer
->height
= MIN2(framebuffer
->height
, attachment
->height
);
7131 framebuffer
->layers
= MIN2(framebuffer
->layers
, attachment
->layerCount
);
7134 for (uint32_t i
= 0; i
< pCreateInfo
->attachmentCount
; i
++) {
7135 VkImageView _iview
= pCreateInfo
->pAttachments
[i
];
7136 struct radv_image_view
*iview
= radv_image_view_from_handle(_iview
);
7137 framebuffer
->attachments
[i
] = iview
;
7138 framebuffer
->width
= MIN2(framebuffer
->width
, iview
->extent
.width
);
7139 framebuffer
->height
= MIN2(framebuffer
->height
, iview
->extent
.height
);
7140 framebuffer
->layers
= MIN2(framebuffer
->layers
, radv_surface_max_layer_count(iview
));
7144 *pFramebuffer
= radv_framebuffer_to_handle(framebuffer
);
7148 void radv_DestroyFramebuffer(
7151 const VkAllocationCallbacks
* pAllocator
)
7153 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7154 RADV_FROM_HANDLE(radv_framebuffer
, fb
, _fb
);
7158 vk_object_base_finish(&fb
->base
);
7159 vk_free2(&device
->vk
.alloc
, pAllocator
, fb
);
7162 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode
)
7164 switch (address_mode
) {
7165 case VK_SAMPLER_ADDRESS_MODE_REPEAT
:
7166 return V_008F30_SQ_TEX_WRAP
;
7167 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT
:
7168 return V_008F30_SQ_TEX_MIRROR
;
7169 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE
:
7170 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
7171 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER
:
7172 return V_008F30_SQ_TEX_CLAMP_BORDER
;
7173 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE
:
7174 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
7176 unreachable("illegal tex wrap mode");
7182 radv_tex_compare(VkCompareOp op
)
7185 case VK_COMPARE_OP_NEVER
:
7186 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
7187 case VK_COMPARE_OP_LESS
:
7188 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
7189 case VK_COMPARE_OP_EQUAL
:
7190 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
7191 case VK_COMPARE_OP_LESS_OR_EQUAL
:
7192 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
7193 case VK_COMPARE_OP_GREATER
:
7194 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
7195 case VK_COMPARE_OP_NOT_EQUAL
:
7196 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
7197 case VK_COMPARE_OP_GREATER_OR_EQUAL
:
7198 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
7199 case VK_COMPARE_OP_ALWAYS
:
7200 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
7202 unreachable("illegal compare mode");
7208 radv_tex_filter(VkFilter filter
, unsigned max_ansio
)
7211 case VK_FILTER_NEAREST
:
7212 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
:
7213 V_008F38_SQ_TEX_XY_FILTER_POINT
);
7214 case VK_FILTER_LINEAR
:
7215 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
:
7216 V_008F38_SQ_TEX_XY_FILTER_BILINEAR
);
7217 case VK_FILTER_CUBIC_IMG
:
7219 fprintf(stderr
, "illegal texture filter");
7225 radv_tex_mipfilter(VkSamplerMipmapMode mode
)
7228 case VK_SAMPLER_MIPMAP_MODE_NEAREST
:
7229 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
7230 case VK_SAMPLER_MIPMAP_MODE_LINEAR
:
7231 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
7233 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
7238 radv_tex_bordercolor(VkBorderColor bcolor
)
7241 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK
:
7242 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK
:
7243 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
7244 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK
:
7245 case VK_BORDER_COLOR_INT_OPAQUE_BLACK
:
7246 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK
;
7247 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE
:
7248 case VK_BORDER_COLOR_INT_OPAQUE_WHITE
:
7249 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE
;
7250 case VK_BORDER_COLOR_FLOAT_CUSTOM_EXT
:
7251 case VK_BORDER_COLOR_INT_CUSTOM_EXT
:
7252 return V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
;
7260 radv_tex_aniso_filter(unsigned filter
)
7274 radv_tex_filter_mode(VkSamplerReductionMode mode
)
7277 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT
:
7278 return V_008F30_SQ_IMG_FILTER_MODE_BLEND
;
7279 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT
:
7280 return V_008F30_SQ_IMG_FILTER_MODE_MIN
;
7281 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT
:
7282 return V_008F30_SQ_IMG_FILTER_MODE_MAX
;
7290 radv_get_max_anisotropy(struct radv_device
*device
,
7291 const VkSamplerCreateInfo
*pCreateInfo
)
7293 if (device
->force_aniso
>= 0)
7294 return device
->force_aniso
;
7296 if (pCreateInfo
->anisotropyEnable
&&
7297 pCreateInfo
->maxAnisotropy
> 1.0f
)
7298 return (uint32_t)pCreateInfo
->maxAnisotropy
;
7303 static inline int S_FIXED(float value
, unsigned frac_bits
)
7305 return value
* (1 << frac_bits
);
7308 static uint32_t radv_register_border_color(struct radv_device
*device
,
7309 VkClearColorValue value
)
7313 pthread_mutex_lock(&device
->border_color_data
.mutex
);
7315 for (slot
= 0; slot
< RADV_BORDER_COLOR_COUNT
; slot
++) {
7316 if (!device
->border_color_data
.used
[slot
]) {
7317 /* Copy to the GPU wrt endian-ness. */
7318 util_memcpy_cpu_to_le32(&device
->border_color_data
.colors_gpu_ptr
[slot
],
7320 sizeof(VkClearColorValue
));
7322 device
->border_color_data
.used
[slot
] = true;
7327 pthread_mutex_unlock(&device
->border_color_data
.mutex
);
7332 static void radv_unregister_border_color(struct radv_device
*device
,
7335 pthread_mutex_lock(&device
->border_color_data
.mutex
);
7337 device
->border_color_data
.used
[slot
] = false;
7339 pthread_mutex_unlock(&device
->border_color_data
.mutex
);
7343 radv_init_sampler(struct radv_device
*device
,
7344 struct radv_sampler
*sampler
,
7345 const VkSamplerCreateInfo
*pCreateInfo
)
7347 uint32_t max_aniso
= radv_get_max_anisotropy(device
, pCreateInfo
);
7348 uint32_t max_aniso_ratio
= radv_tex_aniso_filter(max_aniso
);
7349 bool compat_mode
= device
->physical_device
->rad_info
.chip_class
== GFX8
||
7350 device
->physical_device
->rad_info
.chip_class
== GFX9
;
7351 unsigned filter_mode
= V_008F30_SQ_IMG_FILTER_MODE_BLEND
;
7352 unsigned depth_compare_func
= V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
7353 bool trunc_coord
= pCreateInfo
->minFilter
== VK_FILTER_NEAREST
&& pCreateInfo
->magFilter
== VK_FILTER_NEAREST
;
7354 bool uses_border_color
= pCreateInfo
->addressModeU
== VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER
||
7355 pCreateInfo
->addressModeV
== VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER
||
7356 pCreateInfo
->addressModeW
== VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER
;
7357 VkBorderColor border_color
= uses_border_color
? pCreateInfo
->borderColor
: VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK
;
7358 uint32_t border_color_ptr
;
7360 const struct VkSamplerReductionModeCreateInfo
*sampler_reduction
=
7361 vk_find_struct_const(pCreateInfo
->pNext
,
7362 SAMPLER_REDUCTION_MODE_CREATE_INFO
);
7363 if (sampler_reduction
)
7364 filter_mode
= radv_tex_filter_mode(sampler_reduction
->reductionMode
);
7366 if (pCreateInfo
->compareEnable
)
7367 depth_compare_func
= radv_tex_compare(pCreateInfo
->compareOp
);
7369 sampler
->border_color_slot
= RADV_BORDER_COLOR_COUNT
;
7371 if (border_color
== VK_BORDER_COLOR_FLOAT_CUSTOM_EXT
|| border_color
== VK_BORDER_COLOR_INT_CUSTOM_EXT
) {
7372 const VkSamplerCustomBorderColorCreateInfoEXT
*custom_border_color
=
7373 vk_find_struct_const(pCreateInfo
->pNext
,
7374 SAMPLER_CUSTOM_BORDER_COLOR_CREATE_INFO_EXT
);
7376 assert(custom_border_color
);
7378 sampler
->border_color_slot
=
7379 radv_register_border_color(device
, custom_border_color
->customBorderColor
);
7381 /* Did we fail to find a slot? */
7382 if (sampler
->border_color_slot
== RADV_BORDER_COLOR_COUNT
) {
7383 fprintf(stderr
, "WARNING: no free border color slots, defaulting to TRANS_BLACK.\n");
7384 border_color
= VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK
;
7388 /* If we don't have a custom color, set the ptr to 0 */
7389 border_color_ptr
= sampler
->border_color_slot
!= RADV_BORDER_COLOR_COUNT
7390 ? sampler
->border_color_slot
7393 sampler
->state
[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo
->addressModeU
)) |
7394 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo
->addressModeV
)) |
7395 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo
->addressModeW
)) |
7396 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
7397 S_008F30_DEPTH_COMPARE_FUNC(depth_compare_func
) |
7398 S_008F30_FORCE_UNNORMALIZED(pCreateInfo
->unnormalizedCoordinates
? 1 : 0) |
7399 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
7400 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
7401 S_008F30_DISABLE_CUBE_WRAP(0) |
7402 S_008F30_COMPAT_MODE(compat_mode
) |
7403 S_008F30_FILTER_MODE(filter_mode
) |
7404 S_008F30_TRUNC_COORD(trunc_coord
));
7405 sampler
->state
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo
->minLod
, 0, 15), 8)) |
7406 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo
->maxLod
, 0, 15), 8)) |
7407 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
7408 sampler
->state
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo
->mipLodBias
, -16, 16), 8)) |
7409 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo
->magFilter
, max_aniso
)) |
7410 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo
->minFilter
, max_aniso
)) |
7411 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo
->mipmapMode
)) |
7412 S_008F38_MIP_POINT_PRECLAMP(0));
7413 sampler
->state
[3] = (S_008F3C_BORDER_COLOR_PTR(border_color_ptr
) |
7414 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(border_color
)));
7416 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
7417 sampler
->state
[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
7419 sampler
->state
[2] |=
7420 S_008F38_DISABLE_LSB_CEIL(device
->physical_device
->rad_info
.chip_class
<= GFX8
) |
7421 S_008F38_FILTER_PREC_FIX(1) |
7422 S_008F38_ANISO_OVERRIDE_GFX8(device
->physical_device
->rad_info
.chip_class
>= GFX8
);
7426 VkResult
radv_CreateSampler(
7428 const VkSamplerCreateInfo
* pCreateInfo
,
7429 const VkAllocationCallbacks
* pAllocator
,
7430 VkSampler
* pSampler
)
7432 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7433 struct radv_sampler
*sampler
;
7435 const struct VkSamplerYcbcrConversionInfo
*ycbcr_conversion
=
7436 vk_find_struct_const(pCreateInfo
->pNext
,
7437 SAMPLER_YCBCR_CONVERSION_INFO
);
7439 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO
);
7441 sampler
= vk_alloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*sampler
), 8,
7442 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
7444 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
7446 vk_object_base_init(&device
->vk
, &sampler
->base
,
7447 VK_OBJECT_TYPE_SAMPLER
);
7449 radv_init_sampler(device
, sampler
, pCreateInfo
);
7451 sampler
->ycbcr_sampler
= ycbcr_conversion
? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion
->conversion
): NULL
;
7452 *pSampler
= radv_sampler_to_handle(sampler
);
7457 void radv_DestroySampler(
7460 const VkAllocationCallbacks
* pAllocator
)
7462 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7463 RADV_FROM_HANDLE(radv_sampler
, sampler
, _sampler
);
7468 if (sampler
->border_color_slot
!= RADV_BORDER_COLOR_COUNT
)
7469 radv_unregister_border_color(device
, sampler
->border_color_slot
);
7471 vk_object_base_finish(&sampler
->base
);
7472 vk_free2(&device
->vk
.alloc
, pAllocator
, sampler
);
7475 /* vk_icd.h does not declare this function, so we declare it here to
7476 * suppress Wmissing-prototypes.
7478 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
7479 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
);
7481 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
7482 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
)
7484 /* For the full details on loader interface versioning, see
7485 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
7486 * What follows is a condensed summary, to help you navigate the large and
7487 * confusing official doc.
7489 * - Loader interface v0 is incompatible with later versions. We don't
7492 * - In loader interface v1:
7493 * - The first ICD entrypoint called by the loader is
7494 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
7496 * - The ICD must statically expose no other Vulkan symbol unless it is
7497 * linked with -Bsymbolic.
7498 * - Each dispatchable Vulkan handle created by the ICD must be
7499 * a pointer to a struct whose first member is VK_LOADER_DATA. The
7500 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
7501 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
7502 * vkDestroySurfaceKHR(). The ICD must be capable of working with
7503 * such loader-managed surfaces.
7505 * - Loader interface v2 differs from v1 in:
7506 * - The first ICD entrypoint called by the loader is
7507 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
7508 * statically expose this entrypoint.
7510 * - Loader interface v3 differs from v2 in:
7511 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
7512 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
7513 * because the loader no longer does so.
7515 *pSupportedVersion
= MIN2(*pSupportedVersion
, 4u);
7519 VkResult
radv_GetMemoryFdKHR(VkDevice _device
,
7520 const VkMemoryGetFdInfoKHR
*pGetFdInfo
,
7523 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7524 RADV_FROM_HANDLE(radv_device_memory
, memory
, pGetFdInfo
->memory
);
7526 assert(pGetFdInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR
);
7528 /* At the moment, we support only the below handle types. */
7529 assert(pGetFdInfo
->handleType
==
7530 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT
||
7531 pGetFdInfo
->handleType
==
7532 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
7534 bool ret
= radv_get_memory_fd(device
, memory
, pFD
);
7536 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
7540 static uint32_t radv_compute_valid_memory_types_attempt(struct radv_physical_device
*dev
,
7541 enum radeon_bo_domain domains
,
7542 enum radeon_bo_flag flags
,
7543 enum radeon_bo_flag ignore_flags
)
7545 /* Don't count GTT/CPU as relevant:
7547 * - We're not fully consistent between the two.
7548 * - Sometimes VRAM gets VRAM|GTT.
7550 const enum radeon_bo_domain relevant_domains
= RADEON_DOMAIN_VRAM
|
7554 for (unsigned i
= 0; i
< dev
->memory_properties
.memoryTypeCount
; ++i
) {
7555 if ((domains
& relevant_domains
) != (dev
->memory_domains
[i
] & relevant_domains
))
7558 if ((flags
& ~ignore_flags
) != (dev
->memory_flags
[i
] & ~ignore_flags
))
7567 static uint32_t radv_compute_valid_memory_types(struct radv_physical_device
*dev
,
7568 enum radeon_bo_domain domains
,
7569 enum radeon_bo_flag flags
)
7571 enum radeon_bo_flag ignore_flags
= ~(RADEON_FLAG_NO_CPU_ACCESS
| RADEON_FLAG_GTT_WC
);
7572 uint32_t bits
= radv_compute_valid_memory_types_attempt(dev
, domains
, flags
, ignore_flags
);
7575 ignore_flags
|= RADEON_FLAG_NO_CPU_ACCESS
;
7576 bits
= radv_compute_valid_memory_types_attempt(dev
, domains
, flags
, ignore_flags
);
7581 VkResult
radv_GetMemoryFdPropertiesKHR(VkDevice _device
,
7582 VkExternalMemoryHandleTypeFlagBits handleType
,
7584 VkMemoryFdPropertiesKHR
*pMemoryFdProperties
)
7586 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7588 switch (handleType
) {
7589 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
: {
7590 enum radeon_bo_domain domains
;
7591 enum radeon_bo_flag flags
;
7592 if (!device
->ws
->buffer_get_flags_from_fd(device
->ws
, fd
, &domains
, &flags
))
7593 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7595 pMemoryFdProperties
->memoryTypeBits
= radv_compute_valid_memory_types(device
->physical_device
, domains
, flags
);
7599 /* The valid usage section for this function says:
7601 * "handleType must not be one of the handle types defined as
7604 * So opaque handle types fall into the default "unsupported" case.
7606 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7610 static VkResult
radv_import_opaque_fd(struct radv_device
*device
,
7614 uint32_t syncobj_handle
= 0;
7615 int ret
= device
->ws
->import_syncobj(device
->ws
, fd
, &syncobj_handle
);
7617 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7620 device
->ws
->destroy_syncobj(device
->ws
, *syncobj
);
7622 *syncobj
= syncobj_handle
;
7628 static VkResult
radv_import_sync_fd(struct radv_device
*device
,
7632 /* If we create a syncobj we do it locally so that if we have an error, we don't
7633 * leave a syncobj in an undetermined state in the fence. */
7634 uint32_t syncobj_handle
= *syncobj
;
7635 if (!syncobj_handle
) {
7636 bool create_signaled
= fd
== -1 ? true : false;
7638 int ret
= device
->ws
->create_syncobj(device
->ws
, create_signaled
,
7641 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
7645 device
->ws
->signal_syncobj(device
->ws
, syncobj_handle
, 0);
7649 int ret
= device
->ws
->import_syncobj_from_sync_file(device
->ws
, syncobj_handle
, fd
);
7651 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7655 *syncobj
= syncobj_handle
;
7660 VkResult
radv_ImportSemaphoreFdKHR(VkDevice _device
,
7661 const VkImportSemaphoreFdInfoKHR
*pImportSemaphoreFdInfo
)
7663 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7664 RADV_FROM_HANDLE(radv_semaphore
, sem
, pImportSemaphoreFdInfo
->semaphore
);
7666 struct radv_semaphore_part
*dst
= NULL
;
7667 bool timeline
= sem
->permanent
.kind
== RADV_SEMAPHORE_TIMELINE_SYNCOBJ
;
7669 if (pImportSemaphoreFdInfo
->flags
& VK_SEMAPHORE_IMPORT_TEMPORARY_BIT
) {
7671 dst
= &sem
->temporary
;
7673 dst
= &sem
->permanent
;
7676 uint32_t syncobj
= (dst
->kind
== RADV_SEMAPHORE_SYNCOBJ
||
7677 dst
->kind
== RADV_SEMAPHORE_TIMELINE_SYNCOBJ
) ? dst
->syncobj
: 0;
7679 switch(pImportSemaphoreFdInfo
->handleType
) {
7680 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
:
7681 result
= radv_import_opaque_fd(device
, pImportSemaphoreFdInfo
->fd
, &syncobj
);
7683 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
:
7685 result
= radv_import_sync_fd(device
, pImportSemaphoreFdInfo
->fd
, &syncobj
);
7688 unreachable("Unhandled semaphore handle type");
7691 if (result
== VK_SUCCESS
) {
7692 dst
->syncobj
= syncobj
;
7693 dst
->kind
= RADV_SEMAPHORE_SYNCOBJ
;
7695 dst
->kind
= RADV_SEMAPHORE_TIMELINE_SYNCOBJ
;
7696 dst
->timeline_syncobj
.max_point
= 0;
7703 VkResult
radv_GetSemaphoreFdKHR(VkDevice _device
,
7704 const VkSemaphoreGetFdInfoKHR
*pGetFdInfo
,
7707 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7708 RADV_FROM_HANDLE(radv_semaphore
, sem
, pGetFdInfo
->semaphore
);
7710 uint32_t syncobj_handle
;
7712 if (sem
->temporary
.kind
!= RADV_SEMAPHORE_NONE
) {
7713 assert(sem
->temporary
.kind
== RADV_SEMAPHORE_SYNCOBJ
||
7714 sem
->temporary
.kind
== RADV_SEMAPHORE_TIMELINE_SYNCOBJ
);
7715 syncobj_handle
= sem
->temporary
.syncobj
;
7717 assert(sem
->permanent
.kind
== RADV_SEMAPHORE_SYNCOBJ
||
7718 sem
->permanent
.kind
== RADV_SEMAPHORE_TIMELINE_SYNCOBJ
);
7719 syncobj_handle
= sem
->permanent
.syncobj
;
7722 switch(pGetFdInfo
->handleType
) {
7723 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
:
7724 ret
= device
->ws
->export_syncobj(device
->ws
, syncobj_handle
, pFd
);
7726 return vk_error(device
->instance
, VK_ERROR_TOO_MANY_OBJECTS
);
7728 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
:
7729 ret
= device
->ws
->export_syncobj_to_sync_file(device
->ws
, syncobj_handle
, pFd
);
7731 return vk_error(device
->instance
, VK_ERROR_TOO_MANY_OBJECTS
);
7733 if (sem
->temporary
.kind
!= RADV_SEMAPHORE_NONE
) {
7734 radv_destroy_semaphore_part(device
, &sem
->temporary
);
7736 device
->ws
->reset_syncobj(device
->ws
, syncobj_handle
);
7740 unreachable("Unhandled semaphore handle type");
7746 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
7747 VkPhysicalDevice physicalDevice
,
7748 const VkPhysicalDeviceExternalSemaphoreInfo
*pExternalSemaphoreInfo
,
7749 VkExternalSemaphoreProperties
*pExternalSemaphoreProperties
)
7751 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
7752 VkSemaphoreTypeKHR type
= radv_get_semaphore_type(pExternalSemaphoreInfo
->pNext
, NULL
);
7754 if (type
== VK_SEMAPHORE_TYPE_TIMELINE
&& pdevice
->rad_info
.has_timeline_syncobj
&&
7755 pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
) {
7756 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
7757 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
7758 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT
|
7759 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
7760 } else if (type
== VK_SEMAPHORE_TYPE_TIMELINE
) {
7761 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= 0;
7762 pExternalSemaphoreProperties
->compatibleHandleTypes
= 0;
7763 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= 0;
7765 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
7766 } else if (pdevice
->rad_info
.has_syncobj_wait_for_submit
&&
7767 (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
||
7768 pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
)) {
7769 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
;
7770 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
;
7771 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT
|
7772 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
7773 } else if (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
) {
7774 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
7775 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
7776 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT
|
7777 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
7779 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= 0;
7780 pExternalSemaphoreProperties
->compatibleHandleTypes
= 0;
7781 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= 0;
7785 VkResult
radv_ImportFenceFdKHR(VkDevice _device
,
7786 const VkImportFenceFdInfoKHR
*pImportFenceFdInfo
)
7788 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7789 RADV_FROM_HANDLE(radv_fence
, fence
, pImportFenceFdInfo
->fence
);
7790 struct radv_fence_part
*dst
= NULL
;
7793 if (pImportFenceFdInfo
->flags
& VK_FENCE_IMPORT_TEMPORARY_BIT
) {
7794 dst
= &fence
->temporary
;
7796 dst
= &fence
->permanent
;
7799 uint32_t syncobj
= dst
->kind
== RADV_FENCE_SYNCOBJ
? dst
->syncobj
: 0;
7801 switch(pImportFenceFdInfo
->handleType
) {
7802 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
:
7803 result
= radv_import_opaque_fd(device
, pImportFenceFdInfo
->fd
, &syncobj
);
7805 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
:
7806 result
= radv_import_sync_fd(device
, pImportFenceFdInfo
->fd
, &syncobj
);
7809 unreachable("Unhandled fence handle type");
7812 if (result
== VK_SUCCESS
) {
7813 dst
->syncobj
= syncobj
;
7814 dst
->kind
= RADV_FENCE_SYNCOBJ
;
7820 VkResult
radv_GetFenceFdKHR(VkDevice _device
,
7821 const VkFenceGetFdInfoKHR
*pGetFdInfo
,
7824 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7825 RADV_FROM_HANDLE(radv_fence
, fence
, pGetFdInfo
->fence
);
7828 struct radv_fence_part
*part
=
7829 fence
->temporary
.kind
!= RADV_FENCE_NONE
?
7830 &fence
->temporary
: &fence
->permanent
;
7832 switch(pGetFdInfo
->handleType
) {
7833 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
:
7834 ret
= device
->ws
->export_syncobj(device
->ws
, part
->syncobj
, pFd
);
7836 return vk_error(device
->instance
, VK_ERROR_TOO_MANY_OBJECTS
);
7838 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
:
7839 ret
= device
->ws
->export_syncobj_to_sync_file(device
->ws
,
7840 part
->syncobj
, pFd
);
7842 return vk_error(device
->instance
, VK_ERROR_TOO_MANY_OBJECTS
);
7844 if (part
== &fence
->temporary
) {
7845 radv_destroy_fence_part(device
, part
);
7847 device
->ws
->reset_syncobj(device
->ws
, part
->syncobj
);
7851 unreachable("Unhandled fence handle type");
7857 void radv_GetPhysicalDeviceExternalFenceProperties(
7858 VkPhysicalDevice physicalDevice
,
7859 const VkPhysicalDeviceExternalFenceInfo
*pExternalFenceInfo
,
7860 VkExternalFenceProperties
*pExternalFenceProperties
)
7862 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
7864 if (pdevice
->rad_info
.has_syncobj_wait_for_submit
&&
7865 (pExternalFenceInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
||
7866 pExternalFenceInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
)) {
7867 pExternalFenceProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
;
7868 pExternalFenceProperties
->compatibleHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
;
7869 pExternalFenceProperties
->externalFenceFeatures
= VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT
|
7870 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
7872 pExternalFenceProperties
->exportFromImportedHandleTypes
= 0;
7873 pExternalFenceProperties
->compatibleHandleTypes
= 0;
7874 pExternalFenceProperties
->externalFenceFeatures
= 0;
7879 radv_CreateDebugReportCallbackEXT(VkInstance _instance
,
7880 const VkDebugReportCallbackCreateInfoEXT
* pCreateInfo
,
7881 const VkAllocationCallbacks
* pAllocator
,
7882 VkDebugReportCallbackEXT
* pCallback
)
7884 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
7885 return vk_create_debug_report_callback(&instance
->debug_report_callbacks
,
7886 pCreateInfo
, pAllocator
, &instance
->alloc
,
7891 radv_DestroyDebugReportCallbackEXT(VkInstance _instance
,
7892 VkDebugReportCallbackEXT _callback
,
7893 const VkAllocationCallbacks
* pAllocator
)
7895 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
7896 vk_destroy_debug_report_callback(&instance
->debug_report_callbacks
,
7897 _callback
, pAllocator
, &instance
->alloc
);
7901 radv_DebugReportMessageEXT(VkInstance _instance
,
7902 VkDebugReportFlagsEXT flags
,
7903 VkDebugReportObjectTypeEXT objectType
,
7906 int32_t messageCode
,
7907 const char* pLayerPrefix
,
7908 const char* pMessage
)
7910 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
7911 vk_debug_report(&instance
->debug_report_callbacks
, flags
, objectType
,
7912 object
, location
, messageCode
, pLayerPrefix
, pMessage
);
7916 radv_GetDeviceGroupPeerMemoryFeatures(
7919 uint32_t localDeviceIndex
,
7920 uint32_t remoteDeviceIndex
,
7921 VkPeerMemoryFeatureFlags
* pPeerMemoryFeatures
)
7923 assert(localDeviceIndex
== remoteDeviceIndex
);
7925 *pPeerMemoryFeatures
= VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT
|
7926 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT
|
7927 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT
|
7928 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT
;
7931 static const VkTimeDomainEXT radv_time_domains
[] = {
7932 VK_TIME_DOMAIN_DEVICE_EXT
,
7933 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT
,
7934 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT
,
7937 VkResult
radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
7938 VkPhysicalDevice physicalDevice
,
7939 uint32_t *pTimeDomainCount
,
7940 VkTimeDomainEXT
*pTimeDomains
)
7943 VK_OUTARRAY_MAKE(out
, pTimeDomains
, pTimeDomainCount
);
7945 for (d
= 0; d
< ARRAY_SIZE(radv_time_domains
); d
++) {
7946 vk_outarray_append(&out
, i
) {
7947 *i
= radv_time_domains
[d
];
7951 return vk_outarray_status(&out
);
7955 radv_clock_gettime(clockid_t clock_id
)
7957 struct timespec current
;
7960 ret
= clock_gettime(clock_id
, ¤t
);
7961 if (ret
< 0 && clock_id
== CLOCK_MONOTONIC_RAW
)
7962 ret
= clock_gettime(CLOCK_MONOTONIC
, ¤t
);
7966 return (uint64_t) current
.tv_sec
* 1000000000ULL + current
.tv_nsec
;
7969 VkResult
radv_GetCalibratedTimestampsEXT(
7971 uint32_t timestampCount
,
7972 const VkCalibratedTimestampInfoEXT
*pTimestampInfos
,
7973 uint64_t *pTimestamps
,
7974 uint64_t *pMaxDeviation
)
7976 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7977 uint32_t clock_crystal_freq
= device
->physical_device
->rad_info
.clock_crystal_freq
;
7979 uint64_t begin
, end
;
7980 uint64_t max_clock_period
= 0;
7982 begin
= radv_clock_gettime(CLOCK_MONOTONIC_RAW
);
7984 for (d
= 0; d
< timestampCount
; d
++) {
7985 switch (pTimestampInfos
[d
].timeDomain
) {
7986 case VK_TIME_DOMAIN_DEVICE_EXT
:
7987 pTimestamps
[d
] = device
->ws
->query_value(device
->ws
,
7989 uint64_t device_period
= DIV_ROUND_UP(1000000, clock_crystal_freq
);
7990 max_clock_period
= MAX2(max_clock_period
, device_period
);
7992 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT
:
7993 pTimestamps
[d
] = radv_clock_gettime(CLOCK_MONOTONIC
);
7994 max_clock_period
= MAX2(max_clock_period
, 1);
7997 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT
:
7998 pTimestamps
[d
] = begin
;
8006 end
= radv_clock_gettime(CLOCK_MONOTONIC_RAW
);
8009 * The maximum deviation is the sum of the interval over which we
8010 * perform the sampling and the maximum period of any sampled
8011 * clock. That's because the maximum skew between any two sampled
8012 * clock edges is when the sampled clock with the largest period is
8013 * sampled at the end of that period but right at the beginning of the
8014 * sampling interval and some other clock is sampled right at the
8015 * begining of its sampling period and right at the end of the
8016 * sampling interval. Let's assume the GPU has the longest clock
8017 * period and that the application is sampling GPU and monotonic:
8020 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
8021 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
8025 * GPU -----_____-----_____-----_____-----_____
8028 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
8029 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
8031 * Interval <----------------->
8032 * Deviation <-------------------------->
8036 * m = read(monotonic) 2
8039 * We round the sample interval up by one tick to cover sampling error
8040 * in the interval clock
8043 uint64_t sample_interval
= end
- begin
+ 1;
8045 *pMaxDeviation
= sample_interval
+ max_clock_period
;
8050 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
8051 VkPhysicalDevice physicalDevice
,
8052 VkSampleCountFlagBits samples
,
8053 VkMultisamplePropertiesEXT
* pMultisampleProperties
)
8055 if (samples
& (VK_SAMPLE_COUNT_2_BIT
|
8056 VK_SAMPLE_COUNT_4_BIT
|
8057 VK_SAMPLE_COUNT_8_BIT
)) {
8058 pMultisampleProperties
->maxSampleLocationGridSize
= (VkExtent2D
){ 2, 2 };
8060 pMultisampleProperties
->maxSampleLocationGridSize
= (VkExtent2D
){ 0, 0 };
8064 VkResult
radv_CreatePrivateDataSlotEXT(
8066 const VkPrivateDataSlotCreateInfoEXT
* pCreateInfo
,
8067 const VkAllocationCallbacks
* pAllocator
,
8068 VkPrivateDataSlotEXT
* pPrivateDataSlot
)
8070 RADV_FROM_HANDLE(radv_device
, device
, _device
);
8071 return vk_private_data_slot_create(&device
->vk
, pCreateInfo
, pAllocator
,
8075 void radv_DestroyPrivateDataSlotEXT(
8077 VkPrivateDataSlotEXT privateDataSlot
,
8078 const VkAllocationCallbacks
* pAllocator
)
8080 RADV_FROM_HANDLE(radv_device
, device
, _device
);
8081 vk_private_data_slot_destroy(&device
->vk
, privateDataSlot
, pAllocator
);
8084 VkResult
radv_SetPrivateDataEXT(
8086 VkObjectType objectType
,
8087 uint64_t objectHandle
,
8088 VkPrivateDataSlotEXT privateDataSlot
,
8091 RADV_FROM_HANDLE(radv_device
, device
, _device
);
8092 return vk_object_base_set_private_data(&device
->vk
, objectType
,
8093 objectHandle
, privateDataSlot
,
8097 void radv_GetPrivateDataEXT(
8099 VkObjectType objectType
,
8100 uint64_t objectHandle
,
8101 VkPrivateDataSlotEXT privateDataSlot
,
8104 RADV_FROM_HANDLE(radv_device
, device
, _device
);
8105 vk_object_base_get_private_data(&device
->vk
, objectType
, objectHandle
,
8106 privateDataSlot
, pData
);