radv: add a LLVM version string workaround for SotTR and ACO
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "dirent.h"
29 #include <errno.h>
30 #include <fcntl.h>
31 #include <linux/audit.h>
32 #include <linux/bpf.h>
33 #include <linux/filter.h>
34 #include <linux/seccomp.h>
35 #include <linux/unistd.h>
36 #include <stdbool.h>
37 #include <stddef.h>
38 #include <stdio.h>
39 #include <string.h>
40 #include <sys/prctl.h>
41 #include <sys/wait.h>
42 #include <unistd.h>
43 #include <fcntl.h>
44
45 #include "radv_debug.h"
46 #include "radv_private.h"
47 #include "radv_shader.h"
48 #include "radv_cs.h"
49 #include "util/disk_cache.h"
50 #include "vk_util.h"
51 #include <xf86drm.h>
52 #include <amdgpu.h>
53 #include "drm-uapi/amdgpu_drm.h"
54 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
55 #include "winsys/null/radv_null_winsys_public.h"
56 #include "ac_llvm_util.h"
57 #include "vk_format.h"
58 #include "sid.h"
59 #include "git_sha1.h"
60 #include "util/build_id.h"
61 #include "util/debug.h"
62 #include "util/mesa-sha1.h"
63 #include "util/timespec.h"
64 #include "util/u_atomic.h"
65 #include "compiler/glsl_types.h"
66 #include "util/xmlpool.h"
67
68 static struct radv_timeline_point *
69 radv_timeline_find_point_at_least_locked(struct radv_device *device,
70 struct radv_timeline *timeline,
71 uint64_t p);
72
73 static struct radv_timeline_point *
74 radv_timeline_add_point_locked(struct radv_device *device,
75 struct radv_timeline *timeline,
76 uint64_t p);
77
78 static void
79 radv_timeline_trigger_waiters_locked(struct radv_timeline *timeline,
80 struct list_head *processing_list);
81
82 static
83 void radv_destroy_semaphore_part(struct radv_device *device,
84 struct radv_semaphore_part *part);
85
86 static int
87 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
88 {
89 struct mesa_sha1 ctx;
90 unsigned char sha1[20];
91 unsigned ptr_size = sizeof(void*);
92
93 memset(uuid, 0, VK_UUID_SIZE);
94 _mesa_sha1_init(&ctx);
95
96 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
97 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
98 return -1;
99
100 _mesa_sha1_update(&ctx, &family, sizeof(family));
101 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
102 _mesa_sha1_final(&ctx, sha1);
103
104 memcpy(uuid, sha1, VK_UUID_SIZE);
105 return 0;
106 }
107
108 static void
109 radv_get_driver_uuid(void *uuid)
110 {
111 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
112 }
113
114 static void
115 radv_get_device_uuid(struct radeon_info *info, void *uuid)
116 {
117 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
118 }
119
120 static uint64_t
121 radv_get_visible_vram_size(struct radv_physical_device *device)
122 {
123 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
124 }
125
126 static uint64_t
127 radv_get_vram_size(struct radv_physical_device *device)
128 {
129 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
130 }
131
132 static void
133 radv_physical_device_init_mem_types(struct radv_physical_device *device)
134 {
135 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
136 uint64_t vram_size = radv_get_vram_size(device);
137 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
138 device->memory_properties.memoryHeapCount = 0;
139 if (vram_size > 0) {
140 vram_index = device->memory_properties.memoryHeapCount++;
141 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
142 .size = vram_size,
143 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
144 };
145 }
146
147 if (device->rad_info.gart_size > 0) {
148 gart_index = device->memory_properties.memoryHeapCount++;
149 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
150 .size = device->rad_info.gart_size,
151 .flags = 0,
152 };
153 }
154
155 if (visible_vram_size) {
156 visible_vram_index = device->memory_properties.memoryHeapCount++;
157 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
158 .size = visible_vram_size,
159 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
160 };
161 }
162
163 unsigned type_count = 0;
164
165 if (device->rad_info.has_dedicated_vram) {
166 if (vram_index >= 0) {
167 device->memory_domains[type_count] = RADEON_DOMAIN_VRAM;
168 device->memory_flags[type_count] = RADEON_FLAG_NO_CPU_ACCESS;
169 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
170 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
171 .heapIndex = vram_index,
172 };
173 }
174 } else {
175 if (visible_vram_index >= 0) {
176 device->memory_domains[type_count] = RADEON_DOMAIN_VRAM;
177 device->memory_flags[type_count] = RADEON_FLAG_NO_CPU_ACCESS;
178 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
179 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
180 .heapIndex = visible_vram_index,
181 };
182 }
183 }
184
185 if (gart_index >= 0) {
186 device->memory_domains[type_count] = RADEON_DOMAIN_GTT;
187 device->memory_flags[type_count] = RADEON_FLAG_GTT_WC | RADEON_FLAG_CPU_ACCESS;
188 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
189 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
190 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
191 .heapIndex = gart_index,
192 };
193 }
194 if (visible_vram_index >= 0) {
195 device->memory_domains[type_count] = RADEON_DOMAIN_VRAM;
196 device->memory_flags[type_count] = RADEON_FLAG_CPU_ACCESS;
197 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
198 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
199 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
200 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
201 .heapIndex = visible_vram_index,
202 };
203 }
204
205 if (gart_index >= 0) {
206 device->memory_domains[type_count] = RADEON_DOMAIN_GTT;
207 device->memory_flags[type_count] = RADEON_FLAG_CPU_ACCESS;
208 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
209 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
210 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
211 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
212 .heapIndex = gart_index,
213 };
214 }
215 device->memory_properties.memoryTypeCount = type_count;
216
217 if (device->rad_info.has_l2_uncached) {
218 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
219 VkMemoryType mem_type = device->memory_properties.memoryTypes[i];
220
221 if ((mem_type.propertyFlags & (VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
222 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT)) ||
223 mem_type.propertyFlags == VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT) {
224
225 VkMemoryPropertyFlags property_flags = mem_type.propertyFlags |
226 VK_MEMORY_PROPERTY_DEVICE_COHERENT_BIT_AMD |
227 VK_MEMORY_PROPERTY_DEVICE_UNCACHED_BIT_AMD;
228
229 device->memory_domains[type_count] = device->memory_domains[i];
230 device->memory_flags[type_count] = device->memory_flags[i] | RADEON_FLAG_VA_UNCACHED;
231 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
232 .propertyFlags = property_flags,
233 .heapIndex = mem_type.heapIndex,
234 };
235 }
236 }
237 device->memory_properties.memoryTypeCount = type_count;
238 }
239 }
240
241 static const char *
242 radv_get_compiler_string(struct radv_physical_device *pdevice)
243 {
244 if (pdevice->use_aco) {
245 /* Some games like SotTR apply shader workarounds if the LLVM
246 * version is too old or if the LLVM version string is
247 * missing. This gives 2-5% performance with SotTR and ACO.
248 */
249 if (driQueryOptionb(&pdevice->instance->dri_options,
250 "radv_report_llvm9_version_string")) {
251 return "ACO/LLVM 9.0.1";
252 }
253
254 return "ACO";
255 }
256
257 return "LLVM " MESA_LLVM_VERSION_STRING;
258 }
259
260 static VkResult
261 radv_physical_device_try_create(struct radv_instance *instance,
262 drmDevicePtr drm_device,
263 struct radv_physical_device **device_out)
264 {
265 VkResult result;
266 int fd = -1;
267 int master_fd = -1;
268
269 if (drm_device) {
270 const char *path = drm_device->nodes[DRM_NODE_RENDER];
271 drmVersionPtr version;
272
273 fd = open(path, O_RDWR | O_CLOEXEC);
274 if (fd < 0) {
275 if (instance->debug_flags & RADV_DEBUG_STARTUP)
276 radv_logi("Could not open device '%s'", path);
277
278 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
279 }
280
281 version = drmGetVersion(fd);
282 if (!version) {
283 close(fd);
284
285 if (instance->debug_flags & RADV_DEBUG_STARTUP)
286 radv_logi("Could not get the kernel driver version for device '%s'", path);
287
288 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
289 "failed to get version %s: %m", path);
290 }
291
292 if (strcmp(version->name, "amdgpu")) {
293 drmFreeVersion(version);
294 close(fd);
295
296 if (instance->debug_flags & RADV_DEBUG_STARTUP)
297 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
298
299 return VK_ERROR_INCOMPATIBLE_DRIVER;
300 }
301 drmFreeVersion(version);
302
303 if (instance->debug_flags & RADV_DEBUG_STARTUP)
304 radv_logi("Found compatible device '%s'.", path);
305 }
306
307 struct radv_physical_device *device =
308 vk_zalloc2(&instance->alloc, NULL, sizeof(*device), 8,
309 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
310 if (!device) {
311 result = vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
312 goto fail_fd;
313 }
314
315 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
316 device->instance = instance;
317
318 if (drm_device) {
319 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
320 instance->perftest_flags);
321 } else {
322 device->ws = radv_null_winsys_create();
323 }
324
325 if (!device->ws) {
326 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
327 "failed to initialize winsys");
328 goto fail_alloc;
329 }
330
331 if (drm_device && instance->enabled_extensions.KHR_display) {
332 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
333 if (master_fd >= 0) {
334 uint32_t accel_working = 0;
335 struct drm_amdgpu_info request = {
336 .return_pointer = (uintptr_t)&accel_working,
337 .return_size = sizeof(accel_working),
338 .query = AMDGPU_INFO_ACCEL_WORKING
339 };
340
341 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
342 close(master_fd);
343 master_fd = -1;
344 }
345 }
346 }
347
348 device->master_fd = master_fd;
349 device->local_fd = fd;
350 device->ws->query_info(device->ws, &device->rad_info);
351
352 device->use_aco = instance->perftest_flags & RADV_PERFTEST_ACO;
353
354 snprintf(device->name, sizeof(device->name),
355 "AMD RADV %s (%s)",
356 device->rad_info.name, radv_get_compiler_string(device));
357
358 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
359 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
360 "cannot generate UUID");
361 goto fail_wsi;
362 }
363
364 /* These flags affect shader compilation. */
365 uint64_t shader_env_flags = (device->use_aco ? 0x2 : 0);
366
367 /* The gpu id is already embedded in the uuid so we just pass "radv"
368 * when creating the cache.
369 */
370 char buf[VK_UUID_SIZE * 2 + 1];
371 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
372 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
373
374 if (device->rad_info.chip_class < GFX8)
375 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
376
377 radv_get_driver_uuid(&device->driver_uuid);
378 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
379
380 device->out_of_order_rast_allowed = device->rad_info.has_out_of_order_rast &&
381 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
382
383 device->dcc_msaa_allowed =
384 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
385
386 device->use_shader_ballot = (device->use_aco && device->rad_info.chip_class >= GFX8) ||
387 (device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT);
388
389 device->use_ngg = device->rad_info.chip_class >= GFX10 &&
390 device->rad_info.family != CHIP_NAVI14 &&
391 !(device->instance->debug_flags & RADV_DEBUG_NO_NGG);
392
393 /* TODO: Implement NGG GS with ACO. */
394 device->use_ngg_gs = device->use_ngg && !device->use_aco;
395 device->use_ngg_streamout = false;
396
397 /* Determine the number of threads per wave for all stages. */
398 device->cs_wave_size = 64;
399 device->ps_wave_size = 64;
400 device->ge_wave_size = 64;
401
402 if (device->rad_info.chip_class >= GFX10) {
403 if (device->instance->perftest_flags & RADV_PERFTEST_CS_WAVE_32)
404 device->cs_wave_size = 32;
405
406 /* For pixel shaders, wave64 is recommanded. */
407 if (device->instance->perftest_flags & RADV_PERFTEST_PS_WAVE_32)
408 device->ps_wave_size = 32;
409
410 if (device->instance->perftest_flags & RADV_PERFTEST_GE_WAVE_32)
411 device->ge_wave_size = 32;
412 }
413
414 radv_physical_device_init_mem_types(device);
415
416 radv_physical_device_get_supported_extensions(device,
417 &device->supported_extensions);
418
419 if (drm_device)
420 device->bus_info = *drm_device->businfo.pci;
421
422 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
423 ac_print_gpu_info(&device->rad_info);
424
425 /* The WSI is structured as a layer on top of the driver, so this has
426 * to be the last part of initialization (at least until we get other
427 * semi-layers).
428 */
429 result = radv_init_wsi(device);
430 if (result != VK_SUCCESS) {
431 vk_error(instance, result);
432 goto fail_disk_cache;
433 }
434
435 *device_out = device;
436
437 return VK_SUCCESS;
438
439 fail_disk_cache:
440 disk_cache_destroy(device->disk_cache);
441 fail_wsi:
442 device->ws->destroy(device->ws);
443 fail_alloc:
444 vk_free(&instance->alloc, device);
445 fail_fd:
446 close(fd);
447 if (master_fd != -1)
448 close(master_fd);
449 return result;
450 }
451
452 static void
453 radv_physical_device_destroy(struct radv_physical_device *device)
454 {
455 radv_finish_wsi(device);
456 device->ws->destroy(device->ws);
457 disk_cache_destroy(device->disk_cache);
458 close(device->local_fd);
459 if (device->master_fd != -1)
460 close(device->master_fd);
461 vk_free(&device->instance->alloc, device);
462 }
463
464 static void *
465 default_alloc_func(void *pUserData, size_t size, size_t align,
466 VkSystemAllocationScope allocationScope)
467 {
468 return malloc(size);
469 }
470
471 static void *
472 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
473 size_t align, VkSystemAllocationScope allocationScope)
474 {
475 return realloc(pOriginal, size);
476 }
477
478 static void
479 default_free_func(void *pUserData, void *pMemory)
480 {
481 free(pMemory);
482 }
483
484 static const VkAllocationCallbacks default_alloc = {
485 .pUserData = NULL,
486 .pfnAllocation = default_alloc_func,
487 .pfnReallocation = default_realloc_func,
488 .pfnFree = default_free_func,
489 };
490
491 static const struct debug_control radv_debug_options[] = {
492 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
493 {"nodcc", RADV_DEBUG_NO_DCC},
494 {"shaders", RADV_DEBUG_DUMP_SHADERS},
495 {"nocache", RADV_DEBUG_NO_CACHE},
496 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
497 {"nohiz", RADV_DEBUG_NO_HIZ},
498 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
499 {"allbos", RADV_DEBUG_ALL_BOS},
500 {"noibs", RADV_DEBUG_NO_IBS},
501 {"spirv", RADV_DEBUG_DUMP_SPIRV},
502 {"vmfaults", RADV_DEBUG_VM_FAULTS},
503 {"zerovram", RADV_DEBUG_ZERO_VRAM},
504 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
505 {"preoptir", RADV_DEBUG_PREOPTIR},
506 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
507 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
508 {"info", RADV_DEBUG_INFO},
509 {"errors", RADV_DEBUG_ERRORS},
510 {"startup", RADV_DEBUG_STARTUP},
511 {"checkir", RADV_DEBUG_CHECKIR},
512 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
513 {"nobinning", RADV_DEBUG_NOBINNING},
514 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT},
515 {"nongg", RADV_DEBUG_NO_NGG},
516 {"noshaderballot", RADV_DEBUG_NO_SHADER_BALLOT},
517 {"allentrypoints", RADV_DEBUG_ALL_ENTRYPOINTS},
518 {"metashaders", RADV_DEBUG_DUMP_META_SHADERS},
519 {"nomemorycache", RADV_DEBUG_NO_MEMORY_CACHE},
520 {NULL, 0}
521 };
522
523 const char *
524 radv_get_debug_option_name(int id)
525 {
526 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
527 return radv_debug_options[id].string;
528 }
529
530 static const struct debug_control radv_perftest_options[] = {
531 {"localbos", RADV_PERFTEST_LOCAL_BOS},
532 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
533 {"bolist", RADV_PERFTEST_BO_LIST},
534 {"shader_ballot", RADV_PERFTEST_SHADER_BALLOT},
535 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
536 {"cswave32", RADV_PERFTEST_CS_WAVE_32},
537 {"pswave32", RADV_PERFTEST_PS_WAVE_32},
538 {"gewave32", RADV_PERFTEST_GE_WAVE_32},
539 {"dfsm", RADV_PERFTEST_DFSM},
540 {"aco", RADV_PERFTEST_ACO},
541 {NULL, 0}
542 };
543
544 const char *
545 radv_get_perftest_option_name(int id)
546 {
547 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
548 return radv_perftest_options[id].string;
549 }
550
551 static void
552 radv_handle_per_app_options(struct radv_instance *instance,
553 const VkApplicationInfo *info)
554 {
555 const char *name = info ? info->pApplicationName : NULL;
556
557 if (!name)
558 return;
559
560 if (!strcmp(name, "DOOM_VFR")) {
561 /* Work around a Doom VFR game bug */
562 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
563 } else if (!strcmp(name, "MonsterHunterWorld.exe")) {
564 /* Workaround for a WaW hazard when LLVM moves/merges
565 * load/store memory operations.
566 * See https://reviews.llvm.org/D61313
567 */
568 if (LLVM_VERSION_MAJOR < 9)
569 instance->debug_flags |= RADV_DEBUG_NO_LOAD_STORE_OPT;
570 } else if (!strcmp(name, "Wolfenstein: Youngblood")) {
571 if (!(instance->debug_flags & RADV_DEBUG_NO_SHADER_BALLOT) &&
572 !(instance->perftest_flags & RADV_PERFTEST_ACO)) {
573 /* Force enable VK_AMD_shader_ballot because it looks
574 * safe and it gives a nice boost (+20% on Vega 56 at
575 * this time). It also prevents corruption on LLVM.
576 */
577 instance->perftest_flags |= RADV_PERFTEST_SHADER_BALLOT;
578 }
579 } else if (!strcmp(name, "Fledge")) {
580 /*
581 * Zero VRAM for "The Surge 2"
582 *
583 * This avoid a hang when when rendering any level. Likely
584 * uninitialized data in an indirect draw.
585 */
586 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
587 } else if (!strcmp(name, "No Man's Sky")) {
588 /* Work around a NMS game bug */
589 instance->debug_flags |= RADV_DEBUG_DISCARD_TO_DEMOTE;
590 }
591 }
592
593 static const char radv_dri_options_xml[] =
594 DRI_CONF_BEGIN
595 DRI_CONF_SECTION_PERFORMANCE
596 DRI_CONF_ADAPTIVE_SYNC("true")
597 DRI_CONF_VK_X11_OVERRIDE_MIN_IMAGE_COUNT(0)
598 DRI_CONF_VK_X11_STRICT_IMAGE_COUNT("false")
599 DRI_CONF_RADV_REPORT_LLVM9_VERSION_STRING("false")
600 DRI_CONF_SECTION_END
601
602 DRI_CONF_SECTION_DEBUG
603 DRI_CONF_VK_WSI_FORCE_BGRA8_UNORM_FIRST("false")
604 DRI_CONF_SECTION_END
605 DRI_CONF_END;
606
607 static void radv_init_dri_options(struct radv_instance *instance)
608 {
609 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
610 driParseConfigFiles(&instance->dri_options,
611 &instance->available_dri_options,
612 0, "radv", NULL,
613 instance->engineName,
614 instance->engineVersion);
615 }
616
617 VkResult radv_CreateInstance(
618 const VkInstanceCreateInfo* pCreateInfo,
619 const VkAllocationCallbacks* pAllocator,
620 VkInstance* pInstance)
621 {
622 struct radv_instance *instance;
623 VkResult result;
624
625 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
626 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
627 if (!instance)
628 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
629
630 vk_object_base_init(NULL, &instance->base, VK_OBJECT_TYPE_INSTANCE);
631
632 if (pAllocator)
633 instance->alloc = *pAllocator;
634 else
635 instance->alloc = default_alloc;
636
637 if (pCreateInfo->pApplicationInfo) {
638 const VkApplicationInfo *app = pCreateInfo->pApplicationInfo;
639
640 instance->engineName =
641 vk_strdup(&instance->alloc, app->pEngineName,
642 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
643 instance->engineVersion = app->engineVersion;
644 instance->apiVersion = app->apiVersion;
645 }
646
647 if (instance->apiVersion == 0)
648 instance->apiVersion = VK_API_VERSION_1_0;
649
650 /* Get secure compile thread count. NOTE: We cap this at 32 */
651 #define MAX_SC_PROCS 32
652 char *num_sc_threads = getenv("RADV_SECURE_COMPILE_THREADS");
653 if (num_sc_threads)
654 instance->num_sc_threads = MIN2(strtoul(num_sc_threads, NULL, 10), MAX_SC_PROCS);
655
656 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
657 radv_debug_options);
658
659 /* Disable memory cache when secure compile is set */
660 if (radv_device_use_secure_compile(instance))
661 instance->debug_flags |= RADV_DEBUG_NO_MEMORY_CACHE;
662
663 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
664 radv_perftest_options);
665
666 if (instance->perftest_flags & RADV_PERFTEST_ACO)
667 fprintf(stderr, "WARNING: Experimental compiler backend enabled. Here be dragons! Incorrect rendering, GPU hangs and/or resets are likely\n");
668
669 if (instance->debug_flags & RADV_DEBUG_STARTUP)
670 radv_logi("Created an instance");
671
672 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
673 int idx;
674 for (idx = 0; idx < RADV_INSTANCE_EXTENSION_COUNT; idx++) {
675 if (!strcmp(pCreateInfo->ppEnabledExtensionNames[i],
676 radv_instance_extensions[idx].extensionName))
677 break;
678 }
679
680 if (idx >= RADV_INSTANCE_EXTENSION_COUNT ||
681 !radv_instance_extensions_supported.extensions[idx]) {
682 vk_free2(&default_alloc, pAllocator, instance);
683 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
684 }
685
686 instance->enabled_extensions.extensions[idx] = true;
687 }
688
689 bool unchecked = instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS;
690
691 for (unsigned i = 0; i < ARRAY_SIZE(instance->dispatch.entrypoints); i++) {
692 /* Vulkan requires that entrypoints for extensions which have
693 * not been enabled must not be advertised.
694 */
695 if (!unchecked &&
696 !radv_instance_entrypoint_is_enabled(i, instance->apiVersion,
697 &instance->enabled_extensions)) {
698 instance->dispatch.entrypoints[i] = NULL;
699 } else {
700 instance->dispatch.entrypoints[i] =
701 radv_instance_dispatch_table.entrypoints[i];
702 }
703 }
704
705 for (unsigned i = 0; i < ARRAY_SIZE(instance->physical_device_dispatch.entrypoints); i++) {
706 /* Vulkan requires that entrypoints for extensions which have
707 * not been enabled must not be advertised.
708 */
709 if (!unchecked &&
710 !radv_physical_device_entrypoint_is_enabled(i, instance->apiVersion,
711 &instance->enabled_extensions)) {
712 instance->physical_device_dispatch.entrypoints[i] = NULL;
713 } else {
714 instance->physical_device_dispatch.entrypoints[i] =
715 radv_physical_device_dispatch_table.entrypoints[i];
716 }
717 }
718
719 for (unsigned i = 0; i < ARRAY_SIZE(instance->device_dispatch.entrypoints); i++) {
720 /* Vulkan requires that entrypoints for extensions which have
721 * not been enabled must not be advertised.
722 */
723 if (!unchecked &&
724 !radv_device_entrypoint_is_enabled(i, instance->apiVersion,
725 &instance->enabled_extensions, NULL)) {
726 instance->device_dispatch.entrypoints[i] = NULL;
727 } else {
728 instance->device_dispatch.entrypoints[i] =
729 radv_device_dispatch_table.entrypoints[i];
730 }
731 }
732
733 instance->physical_devices_enumerated = false;
734 list_inithead(&instance->physical_devices);
735
736 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
737 if (result != VK_SUCCESS) {
738 vk_free2(&default_alloc, pAllocator, instance);
739 return vk_error(instance, result);
740 }
741
742 glsl_type_singleton_init_or_ref();
743
744 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
745
746 radv_init_dri_options(instance);
747 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
748
749 *pInstance = radv_instance_to_handle(instance);
750
751 return VK_SUCCESS;
752 }
753
754 void radv_DestroyInstance(
755 VkInstance _instance,
756 const VkAllocationCallbacks* pAllocator)
757 {
758 RADV_FROM_HANDLE(radv_instance, instance, _instance);
759
760 if (!instance)
761 return;
762
763 list_for_each_entry_safe(struct radv_physical_device, pdevice,
764 &instance->physical_devices, link) {
765 radv_physical_device_destroy(pdevice);
766 }
767
768 vk_free(&instance->alloc, instance->engineName);
769
770 VG(VALGRIND_DESTROY_MEMPOOL(instance));
771
772 glsl_type_singleton_decref();
773
774 driDestroyOptionCache(&instance->dri_options);
775 driDestroyOptionInfo(&instance->available_dri_options);
776
777 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
778
779 vk_object_base_finish(&instance->base);
780 vk_free(&instance->alloc, instance);
781 }
782
783 static VkResult
784 radv_enumerate_physical_devices(struct radv_instance *instance)
785 {
786 if (instance->physical_devices_enumerated)
787 return VK_SUCCESS;
788
789 instance->physical_devices_enumerated = true;
790
791 /* TODO: Check for more devices ? */
792 drmDevicePtr devices[8];
793 VkResult result = VK_SUCCESS;
794 int max_devices;
795
796 if (getenv("RADV_FORCE_FAMILY")) {
797 /* When RADV_FORCE_FAMILY is set, the driver creates a nul
798 * device that allows to test the compiler without having an
799 * AMDGPU instance.
800 */
801 struct radv_physical_device *pdevice;
802
803 result = radv_physical_device_try_create(instance, NULL, &pdevice);
804 if (result != VK_SUCCESS)
805 return result;
806
807 list_addtail(&pdevice->link, &instance->physical_devices);
808 return VK_SUCCESS;
809 }
810
811 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
812
813 if (instance->debug_flags & RADV_DEBUG_STARTUP)
814 radv_logi("Found %d drm nodes", max_devices);
815
816 if (max_devices < 1)
817 return vk_error(instance, VK_SUCCESS);
818
819 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
820 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
821 devices[i]->bustype == DRM_BUS_PCI &&
822 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
823
824 struct radv_physical_device *pdevice;
825 result = radv_physical_device_try_create(instance, devices[i],
826 &pdevice);
827 /* Incompatible DRM device, skip. */
828 if (result == VK_ERROR_INCOMPATIBLE_DRIVER) {
829 result = VK_SUCCESS;
830 continue;
831 }
832
833 /* Error creating the physical device, report the error. */
834 if (result != VK_SUCCESS)
835 break;
836
837 list_addtail(&pdevice->link, &instance->physical_devices);
838 }
839 }
840 drmFreeDevices(devices, max_devices);
841
842 /* If we successfully enumerated any devices, call it success */
843 return result;
844 }
845
846 VkResult radv_EnumeratePhysicalDevices(
847 VkInstance _instance,
848 uint32_t* pPhysicalDeviceCount,
849 VkPhysicalDevice* pPhysicalDevices)
850 {
851 RADV_FROM_HANDLE(radv_instance, instance, _instance);
852 VK_OUTARRAY_MAKE(out, pPhysicalDevices, pPhysicalDeviceCount);
853
854 VkResult result = radv_enumerate_physical_devices(instance);
855 if (result != VK_SUCCESS)
856 return result;
857
858 list_for_each_entry(struct radv_physical_device, pdevice,
859 &instance->physical_devices, link) {
860 vk_outarray_append(&out, i) {
861 *i = radv_physical_device_to_handle(pdevice);
862 }
863 }
864
865 return vk_outarray_status(&out);
866 }
867
868 VkResult radv_EnumeratePhysicalDeviceGroups(
869 VkInstance _instance,
870 uint32_t* pPhysicalDeviceGroupCount,
871 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
872 {
873 RADV_FROM_HANDLE(radv_instance, instance, _instance);
874 VK_OUTARRAY_MAKE(out, pPhysicalDeviceGroupProperties,
875 pPhysicalDeviceGroupCount);
876
877 VkResult result = radv_enumerate_physical_devices(instance);
878 if (result != VK_SUCCESS)
879 return result;
880
881 list_for_each_entry(struct radv_physical_device, pdevice,
882 &instance->physical_devices, link) {
883 vk_outarray_append(&out, p) {
884 p->physicalDeviceCount = 1;
885 memset(p->physicalDevices, 0, sizeof(p->physicalDevices));
886 p->physicalDevices[0] = radv_physical_device_to_handle(pdevice);
887 p->subsetAllocation = false;
888 }
889 }
890
891 return vk_outarray_status(&out);
892 }
893
894 void radv_GetPhysicalDeviceFeatures(
895 VkPhysicalDevice physicalDevice,
896 VkPhysicalDeviceFeatures* pFeatures)
897 {
898 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
899 memset(pFeatures, 0, sizeof(*pFeatures));
900
901 *pFeatures = (VkPhysicalDeviceFeatures) {
902 .robustBufferAccess = true,
903 .fullDrawIndexUint32 = true,
904 .imageCubeArray = true,
905 .independentBlend = true,
906 .geometryShader = true,
907 .tessellationShader = true,
908 .sampleRateShading = true,
909 .dualSrcBlend = true,
910 .logicOp = true,
911 .multiDrawIndirect = true,
912 .drawIndirectFirstInstance = true,
913 .depthClamp = true,
914 .depthBiasClamp = true,
915 .fillModeNonSolid = true,
916 .depthBounds = true,
917 .wideLines = true,
918 .largePoints = true,
919 .alphaToOne = true,
920 .multiViewport = true,
921 .samplerAnisotropy = true,
922 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
923 .textureCompressionASTC_LDR = false,
924 .textureCompressionBC = true,
925 .occlusionQueryPrecise = true,
926 .pipelineStatisticsQuery = true,
927 .vertexPipelineStoresAndAtomics = true,
928 .fragmentStoresAndAtomics = true,
929 .shaderTessellationAndGeometryPointSize = true,
930 .shaderImageGatherExtended = true,
931 .shaderStorageImageExtendedFormats = true,
932 .shaderStorageImageMultisample = true,
933 .shaderUniformBufferArrayDynamicIndexing = true,
934 .shaderSampledImageArrayDynamicIndexing = true,
935 .shaderStorageBufferArrayDynamicIndexing = true,
936 .shaderStorageImageArrayDynamicIndexing = true,
937 .shaderStorageImageReadWithoutFormat = true,
938 .shaderStorageImageWriteWithoutFormat = true,
939 .shaderClipDistance = true,
940 .shaderCullDistance = true,
941 .shaderFloat64 = true,
942 .shaderInt64 = true,
943 .shaderInt16 = !pdevice->use_aco || pdevice->rad_info.chip_class >= GFX8,
944 .sparseBinding = true,
945 .variableMultisampleRate = true,
946 .inheritedQueries = true,
947 };
948 }
949
950 void radv_GetPhysicalDeviceFeatures2(
951 VkPhysicalDevice physicalDevice,
952 VkPhysicalDeviceFeatures2 *pFeatures)
953 {
954 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
955 vk_foreach_struct(ext, pFeatures->pNext) {
956 switch (ext->sType) {
957 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
958 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
959 features->variablePointersStorageBuffer = true;
960 features->variablePointers = true;
961 break;
962 }
963 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
964 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
965 features->multiview = true;
966 features->multiviewGeometryShader = true;
967 features->multiviewTessellationShader = true;
968 break;
969 }
970 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
971 VkPhysicalDeviceShaderDrawParametersFeatures *features =
972 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
973 features->shaderDrawParameters = true;
974 break;
975 }
976 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
977 VkPhysicalDeviceProtectedMemoryFeatures *features =
978 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
979 features->protectedMemory = false;
980 break;
981 }
982 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
983 VkPhysicalDevice16BitStorageFeatures *features =
984 (VkPhysicalDevice16BitStorageFeatures*)ext;
985 bool enable = !pdevice->use_aco || pdevice->rad_info.chip_class >= GFX8;
986 features->storageBuffer16BitAccess = enable;
987 features->uniformAndStorageBuffer16BitAccess = enable;
988 features->storagePushConstant16 = enable;
989 features->storageInputOutput16 = pdevice->rad_info.has_double_rate_fp16 && !pdevice->use_aco && LLVM_VERSION_MAJOR >= 9;
990 break;
991 }
992 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
993 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
994 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
995 features->samplerYcbcrConversion = true;
996 break;
997 }
998 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES: {
999 VkPhysicalDeviceDescriptorIndexingFeatures *features =
1000 (VkPhysicalDeviceDescriptorIndexingFeatures*)ext;
1001 features->shaderInputAttachmentArrayDynamicIndexing = true;
1002 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
1003 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
1004 features->shaderUniformBufferArrayNonUniformIndexing = true;
1005 features->shaderSampledImageArrayNonUniformIndexing = true;
1006 features->shaderStorageBufferArrayNonUniformIndexing = true;
1007 features->shaderStorageImageArrayNonUniformIndexing = true;
1008 features->shaderInputAttachmentArrayNonUniformIndexing = true;
1009 features->shaderUniformTexelBufferArrayNonUniformIndexing = true;
1010 features->shaderStorageTexelBufferArrayNonUniformIndexing = true;
1011 features->descriptorBindingUniformBufferUpdateAfterBind = true;
1012 features->descriptorBindingSampledImageUpdateAfterBind = true;
1013 features->descriptorBindingStorageImageUpdateAfterBind = true;
1014 features->descriptorBindingStorageBufferUpdateAfterBind = true;
1015 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
1016 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
1017 features->descriptorBindingUpdateUnusedWhilePending = true;
1018 features->descriptorBindingPartiallyBound = true;
1019 features->descriptorBindingVariableDescriptorCount = true;
1020 features->runtimeDescriptorArray = true;
1021 break;
1022 }
1023 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
1024 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
1025 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
1026 features->conditionalRendering = true;
1027 features->inheritedConditionalRendering = false;
1028 break;
1029 }
1030 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
1031 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
1032 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
1033 features->vertexAttributeInstanceRateDivisor = true;
1034 features->vertexAttributeInstanceRateZeroDivisor = true;
1035 break;
1036 }
1037 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
1038 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
1039 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
1040 features->transformFeedback = true;
1041 features->geometryStreams = !pdevice->use_ngg_streamout;
1042 break;
1043 }
1044 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES: {
1045 VkPhysicalDeviceScalarBlockLayoutFeatures *features =
1046 (VkPhysicalDeviceScalarBlockLayoutFeatures *)ext;
1047 features->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
1048 break;
1049 }
1050 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
1051 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
1052 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
1053 features->memoryPriority = true;
1054 break;
1055 }
1056 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
1057 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
1058 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
1059 features->bufferDeviceAddress = true;
1060 features->bufferDeviceAddressCaptureReplay = false;
1061 features->bufferDeviceAddressMultiDevice = false;
1062 break;
1063 }
1064 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES: {
1065 VkPhysicalDeviceBufferDeviceAddressFeatures *features =
1066 (VkPhysicalDeviceBufferDeviceAddressFeatures *)ext;
1067 features->bufferDeviceAddress = true;
1068 features->bufferDeviceAddressCaptureReplay = false;
1069 features->bufferDeviceAddressMultiDevice = false;
1070 break;
1071 }
1072 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
1073 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
1074 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
1075 features->depthClipEnable = true;
1076 break;
1077 }
1078 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES: {
1079 VkPhysicalDeviceHostQueryResetFeatures *features =
1080 (VkPhysicalDeviceHostQueryResetFeatures *)ext;
1081 features->hostQueryReset = true;
1082 break;
1083 }
1084 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES: {
1085 VkPhysicalDevice8BitStorageFeatures *features =
1086 (VkPhysicalDevice8BitStorageFeatures *)ext;
1087 bool enable = !pdevice->use_aco || pdevice->rad_info.chip_class >= GFX8;
1088 features->storageBuffer8BitAccess = enable;
1089 features->uniformAndStorageBuffer8BitAccess = enable;
1090 features->storagePushConstant8 = enable;
1091 break;
1092 }
1093 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_FLOAT16_INT8_FEATURES: {
1094 VkPhysicalDeviceShaderFloat16Int8Features *features =
1095 (VkPhysicalDeviceShaderFloat16Int8Features*)ext;
1096 features->shaderFloat16 = pdevice->rad_info.has_double_rate_fp16 && !pdevice->use_aco;
1097 features->shaderInt8 = !pdevice->use_aco || pdevice->rad_info.chip_class >= GFX8;
1098 break;
1099 }
1100 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES: {
1101 VkPhysicalDeviceShaderAtomicInt64Features *features =
1102 (VkPhysicalDeviceShaderAtomicInt64Features *)ext;
1103 features->shaderBufferInt64Atomics = LLVM_VERSION_MAJOR >= 9;
1104 features->shaderSharedInt64Atomics = LLVM_VERSION_MAJOR >= 9;
1105 break;
1106 }
1107 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DEMOTE_TO_HELPER_INVOCATION_FEATURES_EXT: {
1108 VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT *features =
1109 (VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT *)ext;
1110 features->shaderDemoteToHelperInvocation = pdevice->use_aco;
1111 break;
1112 }
1113 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
1114 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
1115 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
1116
1117 features->inlineUniformBlock = true;
1118 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
1119 break;
1120 }
1121 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
1122 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
1123 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
1124 features->computeDerivativeGroupQuads = false;
1125 features->computeDerivativeGroupLinear = true;
1126 break;
1127 }
1128 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
1129 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
1130 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
1131 features->ycbcrImageArrays = true;
1132 break;
1133 }
1134 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES: {
1135 VkPhysicalDeviceUniformBufferStandardLayoutFeatures *features =
1136 (VkPhysicalDeviceUniformBufferStandardLayoutFeatures *)ext;
1137 features->uniformBufferStandardLayout = true;
1138 break;
1139 }
1140 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT: {
1141 VkPhysicalDeviceIndexTypeUint8FeaturesEXT *features =
1142 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT *)ext;
1143 features->indexTypeUint8 = pdevice->rad_info.chip_class >= GFX8;
1144 break;
1145 }
1146 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGELESS_FRAMEBUFFER_FEATURES: {
1147 VkPhysicalDeviceImagelessFramebufferFeatures *features =
1148 (VkPhysicalDeviceImagelessFramebufferFeatures *)ext;
1149 features->imagelessFramebuffer = true;
1150 break;
1151 }
1152 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR: {
1153 VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *features =
1154 (VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *)ext;
1155 features->pipelineExecutableInfo = true;
1156 break;
1157 }
1158 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CLOCK_FEATURES_KHR: {
1159 VkPhysicalDeviceShaderClockFeaturesKHR *features =
1160 (VkPhysicalDeviceShaderClockFeaturesKHR *)ext;
1161 features->shaderSubgroupClock = true;
1162 features->shaderDeviceClock = false;
1163 break;
1164 }
1165 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_FEATURES_EXT: {
1166 VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT *features =
1167 (VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT *)ext;
1168 features->texelBufferAlignment = true;
1169 break;
1170 }
1171 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_FEATURES: {
1172 VkPhysicalDeviceTimelineSemaphoreFeatures *features =
1173 (VkPhysicalDeviceTimelineSemaphoreFeatures *) ext;
1174 features->timelineSemaphore = true;
1175 break;
1176 }
1177 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_FEATURES_EXT: {
1178 VkPhysicalDeviceSubgroupSizeControlFeaturesEXT *features =
1179 (VkPhysicalDeviceSubgroupSizeControlFeaturesEXT *)ext;
1180 features->subgroupSizeControl = true;
1181 features->computeFullSubgroups = true;
1182 break;
1183 }
1184 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COHERENT_MEMORY_FEATURES_AMD: {
1185 VkPhysicalDeviceCoherentMemoryFeaturesAMD *features =
1186 (VkPhysicalDeviceCoherentMemoryFeaturesAMD *)ext;
1187 features->deviceCoherentMemory = pdevice->rad_info.has_l2_uncached;
1188 break;
1189 }
1190 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_SUBGROUP_EXTENDED_TYPES_FEATURES: {
1191 VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures *features =
1192 (VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures *)ext;
1193 features->shaderSubgroupExtendedTypes = !pdevice->use_aco;
1194 break;
1195 }
1196 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SEPARATE_DEPTH_STENCIL_LAYOUTS_FEATURES_KHR: {
1197 VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR *features =
1198 (VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR *)ext;
1199 features->separateDepthStencilLayouts = true;
1200 break;
1201 }
1202 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES: {
1203 VkPhysicalDeviceVulkan11Features *features =
1204 (VkPhysicalDeviceVulkan11Features *)ext;
1205 bool storage16_enable = !pdevice->use_aco || pdevice->rad_info.chip_class >= GFX8;
1206 features->storageBuffer16BitAccess = storage16_enable;
1207 features->uniformAndStorageBuffer16BitAccess = storage16_enable;
1208 features->storagePushConstant16 = storage16_enable;
1209 features->storageInputOutput16 = pdevice->rad_info.has_double_rate_fp16 && !pdevice->use_aco && LLVM_VERSION_MAJOR >= 9;
1210 features->multiview = true;
1211 features->multiviewGeometryShader = true;
1212 features->multiviewTessellationShader = true;
1213 features->variablePointersStorageBuffer = true;
1214 features->variablePointers = true;
1215 features->protectedMemory = false;
1216 features->samplerYcbcrConversion = true;
1217 features->shaderDrawParameters = true;
1218 break;
1219 }
1220 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES: {
1221 VkPhysicalDeviceVulkan12Features *features =
1222 (VkPhysicalDeviceVulkan12Features *)ext;
1223 bool int8_enable = !pdevice->use_aco || pdevice->rad_info.chip_class >= GFX8;
1224 features->samplerMirrorClampToEdge = true;
1225 features->drawIndirectCount = true;
1226 features->storageBuffer8BitAccess = int8_enable;
1227 features->uniformAndStorageBuffer8BitAccess = int8_enable;
1228 features->storagePushConstant8 = int8_enable;
1229 features->shaderBufferInt64Atomics = LLVM_VERSION_MAJOR >= 9;
1230 features->shaderSharedInt64Atomics = LLVM_VERSION_MAJOR >= 9;
1231 features->shaderFloat16 = pdevice->rad_info.has_double_rate_fp16 && !pdevice->use_aco;
1232 features->shaderInt8 = int8_enable;
1233 features->descriptorIndexing = true;
1234 features->shaderInputAttachmentArrayDynamicIndexing = true;
1235 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
1236 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
1237 features->shaderUniformBufferArrayNonUniformIndexing = true;
1238 features->shaderSampledImageArrayNonUniformIndexing = true;
1239 features->shaderStorageBufferArrayNonUniformIndexing = true;
1240 features->shaderStorageImageArrayNonUniformIndexing = true;
1241 features->shaderInputAttachmentArrayNonUniformIndexing = true;
1242 features->shaderUniformTexelBufferArrayNonUniformIndexing = true;
1243 features->shaderStorageTexelBufferArrayNonUniformIndexing = true;
1244 features->descriptorBindingUniformBufferUpdateAfterBind = true;
1245 features->descriptorBindingSampledImageUpdateAfterBind = true;
1246 features->descriptorBindingStorageImageUpdateAfterBind = true;
1247 features->descriptorBindingStorageBufferUpdateAfterBind = true;
1248 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
1249 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
1250 features->descriptorBindingUpdateUnusedWhilePending = true;
1251 features->descriptorBindingPartiallyBound = true;
1252 features->descriptorBindingVariableDescriptorCount = true;
1253 features->runtimeDescriptorArray = true;
1254 features->samplerFilterMinmax = true;
1255 features->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
1256 features->imagelessFramebuffer = true;
1257 features->uniformBufferStandardLayout = true;
1258 features->shaderSubgroupExtendedTypes = !pdevice->use_aco;
1259 features->separateDepthStencilLayouts = true;
1260 features->hostQueryReset = true;
1261 features->timelineSemaphore = pdevice->rad_info.has_syncobj_wait_for_submit;
1262 features->bufferDeviceAddress = true;
1263 features->bufferDeviceAddressCaptureReplay = false;
1264 features->bufferDeviceAddressMultiDevice = false;
1265 features->vulkanMemoryModel = false;
1266 features->vulkanMemoryModelDeviceScope = false;
1267 features->vulkanMemoryModelAvailabilityVisibilityChains = false;
1268 features->shaderOutputViewportIndex = true;
1269 features->shaderOutputLayer = true;
1270 features->subgroupBroadcastDynamicId = true;
1271 break;
1272 }
1273 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_FEATURES_EXT: {
1274 VkPhysicalDeviceLineRasterizationFeaturesEXT *features =
1275 (VkPhysicalDeviceLineRasterizationFeaturesEXT *)ext;
1276 features->rectangularLines = false;
1277 features->bresenhamLines = true;
1278 features->smoothLines = false;
1279 features->stippledRectangularLines = false;
1280 features->stippledBresenhamLines = true;
1281 features->stippledSmoothLines = false;
1282 break;
1283 }
1284 case VK_STRUCTURE_TYPE_DEVICE_MEMORY_OVERALLOCATION_CREATE_INFO_AMD: {
1285 VkDeviceMemoryOverallocationCreateInfoAMD *features =
1286 (VkDeviceMemoryOverallocationCreateInfoAMD *)ext;
1287 features->overallocationBehavior = true;
1288 break;
1289 }
1290 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ROBUSTNESS_2_FEATURES_EXT: {
1291 VkPhysicalDeviceRobustness2FeaturesEXT *features =
1292 (VkPhysicalDeviceRobustness2FeaturesEXT *)ext;
1293 features->robustBufferAccess2 = true;
1294 features->robustImageAccess2 = true;
1295 features->nullDescriptor = true;
1296 break;
1297 }
1298 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PRIVATE_DATA_FEATURES_EXT: {
1299 VkPhysicalDevicePrivateDataFeaturesEXT *features =
1300 (VkPhysicalDevicePrivateDataFeaturesEXT *)ext;
1301 features->privateData = true;
1302 break;
1303 }
1304 default:
1305 break;
1306 }
1307 }
1308 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
1309 }
1310
1311 static size_t
1312 radv_max_descriptor_set_size()
1313 {
1314 /* make sure that the entire descriptor set is addressable with a signed
1315 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1316 * be at most 2 GiB. the combined image & samples object count as one of
1317 * both. This limit is for the pipeline layout, not for the set layout, but
1318 * there is no set limit, so we just set a pipeline limit. I don't think
1319 * any app is going to hit this soon. */
1320 return ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
1321 - MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1322 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1323 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1324 32 /* sampler, largest when combined with image */ +
1325 64 /* sampled image */ +
1326 64 /* storage image */);
1327 }
1328
1329 void radv_GetPhysicalDeviceProperties(
1330 VkPhysicalDevice physicalDevice,
1331 VkPhysicalDeviceProperties* pProperties)
1332 {
1333 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1334 VkSampleCountFlags sample_counts = 0xf;
1335
1336 size_t max_descriptor_set_size = radv_max_descriptor_set_size();
1337
1338 VkPhysicalDeviceLimits limits = {
1339 .maxImageDimension1D = (1 << 14),
1340 .maxImageDimension2D = (1 << 14),
1341 .maxImageDimension3D = (1 << 11),
1342 .maxImageDimensionCube = (1 << 14),
1343 .maxImageArrayLayers = (1 << 11),
1344 .maxTexelBufferElements = UINT32_MAX,
1345 .maxUniformBufferRange = UINT32_MAX,
1346 .maxStorageBufferRange = UINT32_MAX,
1347 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1348 .maxMemoryAllocationCount = UINT32_MAX,
1349 .maxSamplerAllocationCount = 64 * 1024,
1350 .bufferImageGranularity = 64, /* A cache line */
1351 .sparseAddressSpaceSize = RADV_MAX_MEMORY_ALLOCATION_SIZE, /* buffer max size */
1352 .maxBoundDescriptorSets = MAX_SETS,
1353 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1354 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1355 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1356 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1357 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1358 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1359 .maxPerStageResources = max_descriptor_set_size,
1360 .maxDescriptorSetSamplers = max_descriptor_set_size,
1361 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1362 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1363 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1364 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1365 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1366 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1367 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1368 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1369 .maxVertexInputBindings = MAX_VBS,
1370 .maxVertexInputAttributeOffset = 2047,
1371 .maxVertexInputBindingStride = 2048,
1372 .maxVertexOutputComponents = 128,
1373 .maxTessellationGenerationLevel = 64,
1374 .maxTessellationPatchSize = 32,
1375 .maxTessellationControlPerVertexInputComponents = 128,
1376 .maxTessellationControlPerVertexOutputComponents = 128,
1377 .maxTessellationControlPerPatchOutputComponents = 120,
1378 .maxTessellationControlTotalOutputComponents = 4096,
1379 .maxTessellationEvaluationInputComponents = 128,
1380 .maxTessellationEvaluationOutputComponents = 128,
1381 .maxGeometryShaderInvocations = 127,
1382 .maxGeometryInputComponents = 64,
1383 .maxGeometryOutputComponents = 128,
1384 .maxGeometryOutputVertices = 256,
1385 .maxGeometryTotalOutputComponents = 1024,
1386 .maxFragmentInputComponents = 128,
1387 .maxFragmentOutputAttachments = 8,
1388 .maxFragmentDualSrcAttachments = 1,
1389 .maxFragmentCombinedOutputResources = 8,
1390 .maxComputeSharedMemorySize = 32768,
1391 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1392 .maxComputeWorkGroupInvocations = 1024,
1393 .maxComputeWorkGroupSize = {
1394 1024,
1395 1024,
1396 1024
1397 },
1398 .subPixelPrecisionBits = 8,
1399 .subTexelPrecisionBits = 8,
1400 .mipmapPrecisionBits = 8,
1401 .maxDrawIndexedIndexValue = UINT32_MAX,
1402 .maxDrawIndirectCount = UINT32_MAX,
1403 .maxSamplerLodBias = 16,
1404 .maxSamplerAnisotropy = 16,
1405 .maxViewports = MAX_VIEWPORTS,
1406 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1407 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1408 .viewportSubPixelBits = 8,
1409 .minMemoryMapAlignment = 4096, /* A page */
1410 .minTexelBufferOffsetAlignment = 4,
1411 .minUniformBufferOffsetAlignment = 4,
1412 .minStorageBufferOffsetAlignment = 4,
1413 .minTexelOffset = -32,
1414 .maxTexelOffset = 31,
1415 .minTexelGatherOffset = -32,
1416 .maxTexelGatherOffset = 31,
1417 .minInterpolationOffset = -2,
1418 .maxInterpolationOffset = 2,
1419 .subPixelInterpolationOffsetBits = 8,
1420 .maxFramebufferWidth = (1 << 14),
1421 .maxFramebufferHeight = (1 << 14),
1422 .maxFramebufferLayers = (1 << 10),
1423 .framebufferColorSampleCounts = sample_counts,
1424 .framebufferDepthSampleCounts = sample_counts,
1425 .framebufferStencilSampleCounts = sample_counts,
1426 .framebufferNoAttachmentsSampleCounts = sample_counts,
1427 .maxColorAttachments = MAX_RTS,
1428 .sampledImageColorSampleCounts = sample_counts,
1429 .sampledImageIntegerSampleCounts = sample_counts,
1430 .sampledImageDepthSampleCounts = sample_counts,
1431 .sampledImageStencilSampleCounts = sample_counts,
1432 .storageImageSampleCounts = sample_counts,
1433 .maxSampleMaskWords = 1,
1434 .timestampComputeAndGraphics = true,
1435 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1436 .maxClipDistances = 8,
1437 .maxCullDistances = 8,
1438 .maxCombinedClipAndCullDistances = 8,
1439 .discreteQueuePriorities = 2,
1440 .pointSizeRange = { 0.0, 8192.0 },
1441 .lineWidthRange = { 0.0, 8192.0 },
1442 .pointSizeGranularity = (1.0 / 8.0),
1443 .lineWidthGranularity = (1.0 / 8.0),
1444 .strictLines = false, /* FINISHME */
1445 .standardSampleLocations = true,
1446 .optimalBufferCopyOffsetAlignment = 128,
1447 .optimalBufferCopyRowPitchAlignment = 128,
1448 .nonCoherentAtomSize = 64,
1449 };
1450
1451 *pProperties = (VkPhysicalDeviceProperties) {
1452 .apiVersion = radv_physical_device_api_version(pdevice),
1453 .driverVersion = vk_get_driver_version(),
1454 .vendorID = ATI_VENDOR_ID,
1455 .deviceID = pdevice->rad_info.pci_id,
1456 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1457 .limits = limits,
1458 .sparseProperties = {0},
1459 };
1460
1461 strcpy(pProperties->deviceName, pdevice->name);
1462 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1463 }
1464
1465 static void
1466 radv_get_physical_device_properties_1_1(struct radv_physical_device *pdevice,
1467 VkPhysicalDeviceVulkan11Properties *p)
1468 {
1469 assert(p->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES);
1470
1471 memcpy(p->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1472 memcpy(p->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1473 memset(p->deviceLUID, 0, VK_LUID_SIZE);
1474 /* The LUID is for Windows. */
1475 p->deviceLUIDValid = false;
1476 p->deviceNodeMask = 0;
1477
1478 p->subgroupSize = RADV_SUBGROUP_SIZE;
1479 p->subgroupSupportedStages = VK_SHADER_STAGE_ALL_GRAPHICS |
1480 VK_SHADER_STAGE_COMPUTE_BIT;
1481 p->subgroupSupportedOperations = VK_SUBGROUP_FEATURE_BASIC_BIT |
1482 VK_SUBGROUP_FEATURE_VOTE_BIT |
1483 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1484 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1485 VK_SUBGROUP_FEATURE_CLUSTERED_BIT |
1486 VK_SUBGROUP_FEATURE_QUAD_BIT;
1487
1488 if (((pdevice->rad_info.chip_class == GFX6 ||
1489 pdevice->rad_info.chip_class == GFX7) && !pdevice->use_aco) ||
1490 pdevice->rad_info.chip_class >= GFX8) {
1491 p->subgroupSupportedOperations |= VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1492 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1493 }
1494 p->subgroupQuadOperationsInAllStages = true;
1495
1496 p->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1497 p->maxMultiviewViewCount = MAX_VIEWS;
1498 p->maxMultiviewInstanceIndex = INT_MAX;
1499 p->protectedNoFault = false;
1500 p->maxPerSetDescriptors = RADV_MAX_PER_SET_DESCRIPTORS;
1501 p->maxMemoryAllocationSize = RADV_MAX_MEMORY_ALLOCATION_SIZE;
1502 }
1503
1504 static void
1505 radv_get_physical_device_properties_1_2(struct radv_physical_device *pdevice,
1506 VkPhysicalDeviceVulkan12Properties *p)
1507 {
1508 assert(p->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES);
1509
1510 p->driverID = VK_DRIVER_ID_MESA_RADV;
1511 snprintf(p->driverName, VK_MAX_DRIVER_NAME_SIZE, "radv");
1512 snprintf(p->driverInfo, VK_MAX_DRIVER_INFO_SIZE,
1513 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1 " (%s)",
1514 radv_get_compiler_string(pdevice));
1515 p->conformanceVersion = (VkConformanceVersion) {
1516 .major = 1,
1517 .minor = 2,
1518 .subminor = 0,
1519 .patch = 0,
1520 };
1521
1522 /* On AMD hardware, denormals and rounding modes for fp16/fp64 are
1523 * controlled by the same config register.
1524 */
1525 if (pdevice->rad_info.has_double_rate_fp16) {
1526 p->denormBehaviorIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
1527 p->roundingModeIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
1528 } else {
1529 p->denormBehaviorIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL_KHR;
1530 p->roundingModeIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL_KHR;
1531 }
1532
1533 /* Do not allow both preserving and flushing denorms because different
1534 * shaders in the same pipeline can have different settings and this
1535 * won't work for merged shaders. To make it work, this requires LLVM
1536 * support for changing the register. The same logic applies for the
1537 * rounding modes because they are configured with the same config
1538 * register. TODO: we can enable a lot of these for ACO when it
1539 * supports all stages.
1540 */
1541 p->shaderDenormFlushToZeroFloat32 = true;
1542 p->shaderDenormPreserveFloat32 = false;
1543 p->shaderRoundingModeRTEFloat32 = true;
1544 p->shaderRoundingModeRTZFloat32 = false;
1545 p->shaderSignedZeroInfNanPreserveFloat32 = true;
1546
1547 p->shaderDenormFlushToZeroFloat16 = false;
1548 p->shaderDenormPreserveFloat16 = pdevice->rad_info.has_double_rate_fp16;
1549 p->shaderRoundingModeRTEFloat16 = pdevice->rad_info.has_double_rate_fp16;
1550 p->shaderRoundingModeRTZFloat16 = false;
1551 p->shaderSignedZeroInfNanPreserveFloat16 = pdevice->rad_info.has_double_rate_fp16;
1552
1553 p->shaderDenormFlushToZeroFloat64 = false;
1554 p->shaderDenormPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8;
1555 p->shaderRoundingModeRTEFloat64 = pdevice->rad_info.chip_class >= GFX8;
1556 p->shaderRoundingModeRTZFloat64 = false;
1557 p->shaderSignedZeroInfNanPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8;
1558
1559 p->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1560 p->shaderUniformBufferArrayNonUniformIndexingNative = false;
1561 p->shaderSampledImageArrayNonUniformIndexingNative = false;
1562 p->shaderStorageBufferArrayNonUniformIndexingNative = false;
1563 p->shaderStorageImageArrayNonUniformIndexingNative = false;
1564 p->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1565 p->robustBufferAccessUpdateAfterBind = false;
1566 p->quadDivergentImplicitLod = false;
1567
1568 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1569 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1570 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1571 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1572 32 /* sampler, largest when combined with image */ +
1573 64 /* sampled image */ +
1574 64 /* storage image */);
1575 p->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1576 p->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1577 p->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1578 p->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1579 p->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1580 p->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1581 p->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1582 p->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1583 p->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1584 p->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1585 p->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1586 p->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1587 p->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1588 p->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1589 p->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1590
1591 /* We support all of the depth resolve modes */
1592 p->supportedDepthResolveModes = VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1593 VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
1594 VK_RESOLVE_MODE_MIN_BIT_KHR |
1595 VK_RESOLVE_MODE_MAX_BIT_KHR;
1596
1597 /* Average doesn't make sense for stencil so we don't support that */
1598 p->supportedStencilResolveModes = VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1599 VK_RESOLVE_MODE_MIN_BIT_KHR |
1600 VK_RESOLVE_MODE_MAX_BIT_KHR;
1601
1602 p->independentResolveNone = true;
1603 p->independentResolve = true;
1604
1605 /* GFX6-8 only support single channel min/max filter. */
1606 p->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1607 p->filterMinmaxSingleComponentFormats = true;
1608
1609 p->maxTimelineSemaphoreValueDifference = UINT64_MAX;
1610
1611 p->framebufferIntegerColorSampleCounts = VK_SAMPLE_COUNT_1_BIT;
1612 }
1613
1614 void radv_GetPhysicalDeviceProperties2(
1615 VkPhysicalDevice physicalDevice,
1616 VkPhysicalDeviceProperties2 *pProperties)
1617 {
1618 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1619 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1620
1621 VkPhysicalDeviceVulkan11Properties core_1_1 = {
1622 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES,
1623 };
1624 radv_get_physical_device_properties_1_1(pdevice, &core_1_1);
1625
1626 VkPhysicalDeviceVulkan12Properties core_1_2 = {
1627 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES,
1628 };
1629 radv_get_physical_device_properties_1_2(pdevice, &core_1_2);
1630
1631 #define CORE_RENAMED_PROPERTY(major, minor, ext_property, core_property) \
1632 memcpy(&properties->ext_property, &core_##major##_##minor.core_property, \
1633 sizeof(core_##major##_##minor.core_property))
1634
1635 #define CORE_PROPERTY(major, minor, property) \
1636 CORE_RENAMED_PROPERTY(major, minor, property, property)
1637
1638 vk_foreach_struct(ext, pProperties->pNext) {
1639 switch (ext->sType) {
1640 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1641 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1642 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1643 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1644 break;
1645 }
1646 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1647 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1648 CORE_PROPERTY(1, 1, deviceUUID);
1649 CORE_PROPERTY(1, 1, driverUUID);
1650 CORE_PROPERTY(1, 1, deviceLUID);
1651 CORE_PROPERTY(1, 1, deviceLUIDValid);
1652 break;
1653 }
1654 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1655 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1656 CORE_PROPERTY(1, 1, maxMultiviewViewCount);
1657 CORE_PROPERTY(1, 1, maxMultiviewInstanceIndex);
1658 break;
1659 }
1660 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1661 VkPhysicalDevicePointClippingProperties *properties =
1662 (VkPhysicalDevicePointClippingProperties*)ext;
1663 CORE_PROPERTY(1, 1, pointClippingBehavior);
1664 break;
1665 }
1666 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1667 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1668 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1669 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1670 break;
1671 }
1672 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1673 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1674 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1675 properties->minImportedHostPointerAlignment = 4096;
1676 break;
1677 }
1678 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1679 VkPhysicalDeviceSubgroupProperties *properties =
1680 (VkPhysicalDeviceSubgroupProperties*)ext;
1681 CORE_PROPERTY(1, 1, subgroupSize);
1682 CORE_RENAMED_PROPERTY(1, 1, supportedStages,
1683 subgroupSupportedStages);
1684 CORE_RENAMED_PROPERTY(1, 1, supportedOperations,
1685 subgroupSupportedOperations);
1686 CORE_RENAMED_PROPERTY(1, 1, quadOperationsInAllStages,
1687 subgroupQuadOperationsInAllStages);
1688 break;
1689 }
1690 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1691 VkPhysicalDeviceMaintenance3Properties *properties =
1692 (VkPhysicalDeviceMaintenance3Properties*)ext;
1693 CORE_PROPERTY(1, 1, maxPerSetDescriptors);
1694 CORE_PROPERTY(1, 1, maxMemoryAllocationSize);
1695 break;
1696 }
1697 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES: {
1698 VkPhysicalDeviceSamplerFilterMinmaxProperties *properties =
1699 (VkPhysicalDeviceSamplerFilterMinmaxProperties *)ext;
1700 CORE_PROPERTY(1, 2, filterMinmaxImageComponentMapping);
1701 CORE_PROPERTY(1, 2, filterMinmaxSingleComponentFormats);
1702 break;
1703 }
1704 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1705 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1706 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1707
1708 /* Shader engines. */
1709 properties->shaderEngineCount =
1710 pdevice->rad_info.max_se;
1711 properties->shaderArraysPerEngineCount =
1712 pdevice->rad_info.max_sh_per_se;
1713 properties->computeUnitsPerShaderArray =
1714 pdevice->rad_info.num_good_cu_per_sh;
1715 properties->simdPerComputeUnit =
1716 pdevice->rad_info.num_simd_per_compute_unit;
1717 properties->wavefrontsPerSimd =
1718 pdevice->rad_info.max_wave64_per_simd;
1719 properties->wavefrontSize = 64;
1720
1721 /* SGPR. */
1722 properties->sgprsPerSimd =
1723 pdevice->rad_info.num_physical_sgprs_per_simd;
1724 properties->minSgprAllocation =
1725 pdevice->rad_info.min_sgpr_alloc;
1726 properties->maxSgprAllocation =
1727 pdevice->rad_info.max_sgpr_alloc;
1728 properties->sgprAllocationGranularity =
1729 pdevice->rad_info.sgpr_alloc_granularity;
1730
1731 /* VGPR. */
1732 properties->vgprsPerSimd =
1733 pdevice->rad_info.num_physical_wave64_vgprs_per_simd;
1734 properties->minVgprAllocation =
1735 pdevice->rad_info.min_wave64_vgpr_alloc;
1736 properties->maxVgprAllocation =
1737 pdevice->rad_info.max_vgpr_alloc;
1738 properties->vgprAllocationGranularity =
1739 pdevice->rad_info.wave64_vgpr_alloc_granularity;
1740 break;
1741 }
1742 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_2_AMD: {
1743 VkPhysicalDeviceShaderCoreProperties2AMD *properties =
1744 (VkPhysicalDeviceShaderCoreProperties2AMD *)ext;
1745
1746 properties->shaderCoreFeatures = 0;
1747 properties->activeComputeUnitCount =
1748 pdevice->rad_info.num_good_compute_units;
1749 break;
1750 }
1751 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1752 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1753 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1754 properties->maxVertexAttribDivisor = UINT32_MAX;
1755 break;
1756 }
1757 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES: {
1758 VkPhysicalDeviceDescriptorIndexingProperties *properties =
1759 (VkPhysicalDeviceDescriptorIndexingProperties*)ext;
1760 CORE_PROPERTY(1, 2, maxUpdateAfterBindDescriptorsInAllPools);
1761 CORE_PROPERTY(1, 2, shaderUniformBufferArrayNonUniformIndexingNative);
1762 CORE_PROPERTY(1, 2, shaderSampledImageArrayNonUniformIndexingNative);
1763 CORE_PROPERTY(1, 2, shaderStorageBufferArrayNonUniformIndexingNative);
1764 CORE_PROPERTY(1, 2, shaderStorageImageArrayNonUniformIndexingNative);
1765 CORE_PROPERTY(1, 2, shaderInputAttachmentArrayNonUniformIndexingNative);
1766 CORE_PROPERTY(1, 2, robustBufferAccessUpdateAfterBind);
1767 CORE_PROPERTY(1, 2, quadDivergentImplicitLod);
1768 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSamplers);
1769 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindUniformBuffers);
1770 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageBuffers);
1771 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSampledImages);
1772 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageImages);
1773 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindInputAttachments);
1774 CORE_PROPERTY(1, 2, maxPerStageUpdateAfterBindResources);
1775 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSamplers);
1776 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffers);
1777 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffersDynamic);
1778 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffers);
1779 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffersDynamic);
1780 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSampledImages);
1781 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageImages);
1782 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindInputAttachments);
1783 break;
1784 }
1785 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1786 VkPhysicalDeviceProtectedMemoryProperties *properties =
1787 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1788 CORE_PROPERTY(1, 1, protectedNoFault);
1789 break;
1790 }
1791 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1792 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1793 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1794 properties->primitiveOverestimationSize = 0;
1795 properties->maxExtraPrimitiveOverestimationSize = 0;
1796 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1797 properties->primitiveUnderestimation = false;
1798 properties->conservativePointAndLineRasterization = false;
1799 properties->degenerateTrianglesRasterized = false;
1800 properties->degenerateLinesRasterized = false;
1801 properties->fullyCoveredFragmentShaderInputVariable = false;
1802 properties->conservativeRasterizationPostDepthCoverage = false;
1803 break;
1804 }
1805 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1806 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1807 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1808 properties->pciDomain = pdevice->bus_info.domain;
1809 properties->pciBus = pdevice->bus_info.bus;
1810 properties->pciDevice = pdevice->bus_info.dev;
1811 properties->pciFunction = pdevice->bus_info.func;
1812 break;
1813 }
1814 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES: {
1815 VkPhysicalDeviceDriverProperties *properties =
1816 (VkPhysicalDeviceDriverProperties *) ext;
1817 CORE_PROPERTY(1, 2, driverID);
1818 CORE_PROPERTY(1, 2, driverName);
1819 CORE_PROPERTY(1, 2, driverInfo);
1820 CORE_PROPERTY(1, 2, conformanceVersion);
1821 break;
1822 }
1823 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1824 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1825 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1826 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1827 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1828 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1829 properties->maxTransformFeedbackStreamDataSize = 512;
1830 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1831 properties->maxTransformFeedbackBufferDataStride = 512;
1832 properties->transformFeedbackQueries = !pdevice->use_ngg_streamout;
1833 properties->transformFeedbackStreamsLinesTriangles = !pdevice->use_ngg_streamout;
1834 properties->transformFeedbackRasterizationStreamSelect = false;
1835 properties->transformFeedbackDraw = true;
1836 break;
1837 }
1838 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1839 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1840 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1841
1842 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1843 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1844 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1845 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1846 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1847 break;
1848 }
1849 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT: {
1850 VkPhysicalDeviceSampleLocationsPropertiesEXT *properties =
1851 (VkPhysicalDeviceSampleLocationsPropertiesEXT *)ext;
1852 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_2_BIT |
1853 VK_SAMPLE_COUNT_4_BIT |
1854 VK_SAMPLE_COUNT_8_BIT;
1855 properties->maxSampleLocationGridSize = (VkExtent2D){ 2 , 2 };
1856 properties->sampleLocationCoordinateRange[0] = 0.0f;
1857 properties->sampleLocationCoordinateRange[1] = 0.9375f;
1858 properties->sampleLocationSubPixelBits = 4;
1859 properties->variableSampleLocations = false;
1860 break;
1861 }
1862 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES: {
1863 VkPhysicalDeviceDepthStencilResolveProperties *properties =
1864 (VkPhysicalDeviceDepthStencilResolveProperties *)ext;
1865 CORE_PROPERTY(1, 2, supportedDepthResolveModes);
1866 CORE_PROPERTY(1, 2, supportedStencilResolveModes);
1867 CORE_PROPERTY(1, 2, independentResolveNone);
1868 CORE_PROPERTY(1, 2, independentResolve);
1869 break;
1870 }
1871 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_PROPERTIES_EXT: {
1872 VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT *properties =
1873 (VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT *)ext;
1874 properties->storageTexelBufferOffsetAlignmentBytes = 4;
1875 properties->storageTexelBufferOffsetSingleTexelAlignment = true;
1876 properties->uniformTexelBufferOffsetAlignmentBytes = 4;
1877 properties->uniformTexelBufferOffsetSingleTexelAlignment = true;
1878 break;
1879 }
1880 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT_CONTROLS_PROPERTIES : {
1881 VkPhysicalDeviceFloatControlsProperties *properties =
1882 (VkPhysicalDeviceFloatControlsProperties *)ext;
1883 CORE_PROPERTY(1, 2, denormBehaviorIndependence);
1884 CORE_PROPERTY(1, 2, roundingModeIndependence);
1885 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat16);
1886 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat16);
1887 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat16);
1888 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat16);
1889 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat16);
1890 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat32);
1891 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat32);
1892 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat32);
1893 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat32);
1894 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat32);
1895 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat64);
1896 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat64);
1897 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat64);
1898 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat64);
1899 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat64);
1900 break;
1901 }
1902 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_PROPERTIES: {
1903 VkPhysicalDeviceTimelineSemaphoreProperties *properties =
1904 (VkPhysicalDeviceTimelineSemaphoreProperties *) ext;
1905 CORE_PROPERTY(1, 2, maxTimelineSemaphoreValueDifference);
1906 break;
1907 }
1908 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_PROPERTIES_EXT: {
1909 VkPhysicalDeviceSubgroupSizeControlPropertiesEXT *props =
1910 (VkPhysicalDeviceSubgroupSizeControlPropertiesEXT *)ext;
1911 props->minSubgroupSize = 64;
1912 props->maxSubgroupSize = 64;
1913 props->maxComputeWorkgroupSubgroups = UINT32_MAX;
1914 props->requiredSubgroupSizeStages = 0;
1915
1916 if (pdevice->rad_info.chip_class >= GFX10) {
1917 /* Only GFX10+ supports wave32. */
1918 props->minSubgroupSize = 32;
1919 props->requiredSubgroupSizeStages = VK_SHADER_STAGE_COMPUTE_BIT;
1920 }
1921 break;
1922 }
1923 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES:
1924 radv_get_physical_device_properties_1_1(pdevice, (void *)ext);
1925 break;
1926 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES:
1927 radv_get_physical_device_properties_1_2(pdevice, (void *)ext);
1928 break;
1929 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_PROPERTIES_EXT: {
1930 VkPhysicalDeviceLineRasterizationPropertiesEXT *props =
1931 (VkPhysicalDeviceLineRasterizationPropertiesEXT *)ext;
1932 props->lineSubPixelPrecisionBits = 4;
1933 break;
1934 }
1935 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ROBUSTNESS_2_PROPERTIES_EXT: {
1936 VkPhysicalDeviceRobustness2PropertiesEXT *properties =
1937 (VkPhysicalDeviceRobustness2PropertiesEXT *)ext;
1938 properties->robustStorageBufferAccessSizeAlignment = 4;
1939 properties->robustUniformBufferAccessSizeAlignment = 4;
1940 break;
1941 }
1942 default:
1943 break;
1944 }
1945 }
1946 }
1947
1948 static void radv_get_physical_device_queue_family_properties(
1949 struct radv_physical_device* pdevice,
1950 uint32_t* pCount,
1951 VkQueueFamilyProperties** pQueueFamilyProperties)
1952 {
1953 int num_queue_families = 1;
1954 int idx;
1955 if (pdevice->rad_info.num_rings[RING_COMPUTE] > 0 &&
1956 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1957 num_queue_families++;
1958
1959 if (pQueueFamilyProperties == NULL) {
1960 *pCount = num_queue_families;
1961 return;
1962 }
1963
1964 if (!*pCount)
1965 return;
1966
1967 idx = 0;
1968 if (*pCount >= 1) {
1969 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1970 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1971 VK_QUEUE_COMPUTE_BIT |
1972 VK_QUEUE_TRANSFER_BIT |
1973 VK_QUEUE_SPARSE_BINDING_BIT,
1974 .queueCount = 1,
1975 .timestampValidBits = 64,
1976 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1977 };
1978 idx++;
1979 }
1980
1981 if (pdevice->rad_info.num_rings[RING_COMPUTE] > 0 &&
1982 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1983 if (*pCount > idx) {
1984 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1985 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1986 VK_QUEUE_TRANSFER_BIT |
1987 VK_QUEUE_SPARSE_BINDING_BIT,
1988 .queueCount = pdevice->rad_info.num_rings[RING_COMPUTE],
1989 .timestampValidBits = 64,
1990 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1991 };
1992 idx++;
1993 }
1994 }
1995 *pCount = idx;
1996 }
1997
1998 void radv_GetPhysicalDeviceQueueFamilyProperties(
1999 VkPhysicalDevice physicalDevice,
2000 uint32_t* pCount,
2001 VkQueueFamilyProperties* pQueueFamilyProperties)
2002 {
2003 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
2004 if (!pQueueFamilyProperties) {
2005 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
2006 return;
2007 }
2008 VkQueueFamilyProperties *properties[] = {
2009 pQueueFamilyProperties + 0,
2010 pQueueFamilyProperties + 1,
2011 pQueueFamilyProperties + 2,
2012 };
2013 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
2014 assert(*pCount <= 3);
2015 }
2016
2017 void radv_GetPhysicalDeviceQueueFamilyProperties2(
2018 VkPhysicalDevice physicalDevice,
2019 uint32_t* pCount,
2020 VkQueueFamilyProperties2 *pQueueFamilyProperties)
2021 {
2022 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
2023 if (!pQueueFamilyProperties) {
2024 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
2025 return;
2026 }
2027 VkQueueFamilyProperties *properties[] = {
2028 &pQueueFamilyProperties[0].queueFamilyProperties,
2029 &pQueueFamilyProperties[1].queueFamilyProperties,
2030 &pQueueFamilyProperties[2].queueFamilyProperties,
2031 };
2032 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
2033 assert(*pCount <= 3);
2034 }
2035
2036 void radv_GetPhysicalDeviceMemoryProperties(
2037 VkPhysicalDevice physicalDevice,
2038 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
2039 {
2040 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2041
2042 *pMemoryProperties = physical_device->memory_properties;
2043 }
2044
2045 static void
2046 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
2047 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
2048 {
2049 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2050 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
2051 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
2052 uint64_t vram_size = radv_get_vram_size(device);
2053 uint64_t gtt_size = device->rad_info.gart_size;
2054 uint64_t heap_budget, heap_usage;
2055
2056 /* For all memory heaps, the computation of budget is as follow:
2057 * heap_budget = heap_size - global_heap_usage + app_heap_usage
2058 *
2059 * The Vulkan spec 1.1.97 says that the budget should include any
2060 * currently allocated device memory.
2061 *
2062 * Note that the application heap usages are not really accurate (eg.
2063 * in presence of shared buffers).
2064 */
2065 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
2066 uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;
2067
2068 if ((device->memory_domains[i] & RADEON_DOMAIN_VRAM) && (device->memory_flags[i] & RADEON_FLAG_NO_CPU_ACCESS)) {
2069 heap_usage = device->ws->query_value(device->ws,
2070 RADEON_ALLOCATED_VRAM);
2071
2072 heap_budget = vram_size -
2073 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
2074 heap_usage;
2075
2076 memoryBudget->heapBudget[heap_index] = heap_budget;
2077 memoryBudget->heapUsage[heap_index] = heap_usage;
2078 } else if (device->memory_domains[i] & RADEON_DOMAIN_VRAM) {
2079 heap_usage = device->ws->query_value(device->ws,
2080 RADEON_ALLOCATED_VRAM_VIS);
2081
2082 heap_budget = visible_vram_size -
2083 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
2084 heap_usage;
2085
2086 memoryBudget->heapBudget[heap_index] = heap_budget;
2087 memoryBudget->heapUsage[heap_index] = heap_usage;
2088 } else {
2089 assert(device->memory_domains[i] & RADEON_DOMAIN_GTT);
2090
2091 heap_usage = device->ws->query_value(device->ws,
2092 RADEON_ALLOCATED_GTT);
2093
2094 heap_budget = gtt_size -
2095 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
2096 heap_usage;
2097
2098 memoryBudget->heapBudget[heap_index] = heap_budget;
2099 memoryBudget->heapUsage[heap_index] = heap_usage;
2100 }
2101 }
2102
2103 /* The heapBudget and heapUsage values must be zero for array elements
2104 * greater than or equal to
2105 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
2106 */
2107 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
2108 memoryBudget->heapBudget[i] = 0;
2109 memoryBudget->heapUsage[i] = 0;
2110 }
2111 }
2112
2113 void radv_GetPhysicalDeviceMemoryProperties2(
2114 VkPhysicalDevice physicalDevice,
2115 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
2116 {
2117 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
2118 &pMemoryProperties->memoryProperties);
2119
2120 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
2121 vk_find_struct(pMemoryProperties->pNext,
2122 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
2123 if (memory_budget)
2124 radv_get_memory_budget_properties(physicalDevice, memory_budget);
2125 }
2126
2127 VkResult radv_GetMemoryHostPointerPropertiesEXT(
2128 VkDevice _device,
2129 VkExternalMemoryHandleTypeFlagBits handleType,
2130 const void *pHostPointer,
2131 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
2132 {
2133 RADV_FROM_HANDLE(radv_device, device, _device);
2134
2135 switch (handleType)
2136 {
2137 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
2138 const struct radv_physical_device *physical_device = device->physical_device;
2139 uint32_t memoryTypeBits = 0;
2140 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
2141 if (physical_device->memory_domains[i] == RADEON_DOMAIN_GTT &&
2142 !(physical_device->memory_flags[i] & RADEON_FLAG_GTT_WC)) {
2143 memoryTypeBits = (1 << i);
2144 break;
2145 }
2146 }
2147 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
2148 return VK_SUCCESS;
2149 }
2150 default:
2151 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
2152 }
2153 }
2154
2155 static enum radeon_ctx_priority
2156 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
2157 {
2158 /* Default to MEDIUM when a specific global priority isn't requested */
2159 if (!pObj)
2160 return RADEON_CTX_PRIORITY_MEDIUM;
2161
2162 switch(pObj->globalPriority) {
2163 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
2164 return RADEON_CTX_PRIORITY_REALTIME;
2165 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
2166 return RADEON_CTX_PRIORITY_HIGH;
2167 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
2168 return RADEON_CTX_PRIORITY_MEDIUM;
2169 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
2170 return RADEON_CTX_PRIORITY_LOW;
2171 default:
2172 unreachable("Illegal global priority value");
2173 return RADEON_CTX_PRIORITY_INVALID;
2174 }
2175 }
2176
2177 static int
2178 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
2179 uint32_t queue_family_index, int idx,
2180 VkDeviceQueueCreateFlags flags,
2181 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
2182 {
2183 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2184 queue->device = device;
2185 queue->queue_family_index = queue_family_index;
2186 queue->queue_idx = idx;
2187 queue->priority = radv_get_queue_global_priority(global_priority);
2188 queue->flags = flags;
2189
2190 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
2191 if (!queue->hw_ctx)
2192 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2193
2194 list_inithead(&queue->pending_submissions);
2195 pthread_mutex_init(&queue->pending_mutex, NULL);
2196
2197 return VK_SUCCESS;
2198 }
2199
2200 static void
2201 radv_queue_finish(struct radv_queue *queue)
2202 {
2203 pthread_mutex_destroy(&queue->pending_mutex);
2204
2205 if (queue->hw_ctx)
2206 queue->device->ws->ctx_destroy(queue->hw_ctx);
2207
2208 if (queue->initial_full_flush_preamble_cs)
2209 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2210 if (queue->initial_preamble_cs)
2211 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2212 if (queue->continue_preamble_cs)
2213 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2214 if (queue->descriptor_bo)
2215 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2216 if (queue->scratch_bo)
2217 queue->device->ws->buffer_destroy(queue->scratch_bo);
2218 if (queue->esgs_ring_bo)
2219 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2220 if (queue->gsvs_ring_bo)
2221 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2222 if (queue->tess_rings_bo)
2223 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
2224 if (queue->gds_bo)
2225 queue->device->ws->buffer_destroy(queue->gds_bo);
2226 if (queue->gds_oa_bo)
2227 queue->device->ws->buffer_destroy(queue->gds_oa_bo);
2228 if (queue->compute_scratch_bo)
2229 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2230 }
2231
2232 static void
2233 radv_bo_list_init(struct radv_bo_list *bo_list)
2234 {
2235 pthread_mutex_init(&bo_list->mutex, NULL);
2236 bo_list->list.count = bo_list->capacity = 0;
2237 bo_list->list.bos = NULL;
2238 }
2239
2240 static void
2241 radv_bo_list_finish(struct radv_bo_list *bo_list)
2242 {
2243 free(bo_list->list.bos);
2244 pthread_mutex_destroy(&bo_list->mutex);
2245 }
2246
2247 VkResult radv_bo_list_add(struct radv_device *device,
2248 struct radeon_winsys_bo *bo)
2249 {
2250 struct radv_bo_list *bo_list = &device->bo_list;
2251
2252 if (bo->is_local)
2253 return VK_SUCCESS;
2254
2255 if (unlikely(!device->use_global_bo_list))
2256 return VK_SUCCESS;
2257
2258 pthread_mutex_lock(&bo_list->mutex);
2259 if (bo_list->list.count == bo_list->capacity) {
2260 unsigned capacity = MAX2(4, bo_list->capacity * 2);
2261 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
2262
2263 if (!data) {
2264 pthread_mutex_unlock(&bo_list->mutex);
2265 return VK_ERROR_OUT_OF_HOST_MEMORY;
2266 }
2267
2268 bo_list->list.bos = (struct radeon_winsys_bo**)data;
2269 bo_list->capacity = capacity;
2270 }
2271
2272 bo_list->list.bos[bo_list->list.count++] = bo;
2273 pthread_mutex_unlock(&bo_list->mutex);
2274 return VK_SUCCESS;
2275 }
2276
2277 void radv_bo_list_remove(struct radv_device *device,
2278 struct radeon_winsys_bo *bo)
2279 {
2280 struct radv_bo_list *bo_list = &device->bo_list;
2281
2282 if (bo->is_local)
2283 return;
2284
2285 if (unlikely(!device->use_global_bo_list))
2286 return;
2287
2288 pthread_mutex_lock(&bo_list->mutex);
2289 /* Loop the list backwards so we find the most recently added
2290 * memory first. */
2291 for(unsigned i = bo_list->list.count; i-- > 0;) {
2292 if (bo_list->list.bos[i] == bo) {
2293 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
2294 --bo_list->list.count;
2295 break;
2296 }
2297 }
2298 pthread_mutex_unlock(&bo_list->mutex);
2299 }
2300
2301 static void
2302 radv_device_init_gs_info(struct radv_device *device)
2303 {
2304 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
2305 device->physical_device->rad_info.family);
2306 }
2307
2308 static int radv_get_device_extension_index(const char *name)
2309 {
2310 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
2311 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
2312 return i;
2313 }
2314 return -1;
2315 }
2316
2317 static int
2318 radv_get_int_debug_option(const char *name, int default_value)
2319 {
2320 const char *str;
2321 int result;
2322
2323 str = getenv(name);
2324 if (!str) {
2325 result = default_value;
2326 } else {
2327 char *endptr;
2328
2329 result = strtol(str, &endptr, 0);
2330 if (str == endptr) {
2331 /* No digits founs. */
2332 result = default_value;
2333 }
2334 }
2335
2336 return result;
2337 }
2338
2339 static int install_seccomp_filter() {
2340
2341 struct sock_filter filter[] = {
2342 /* Check arch is 64bit x86 */
2343 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, arch))),
2344 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, AUDIT_ARCH_X86_64, 0, 12),
2345
2346 /* Futex is required for mutex locks */
2347 #if defined __NR__newselect
2348 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2349 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR__newselect, 11, 0),
2350 #elif defined __NR_select
2351 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2352 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_select, 11, 0),
2353 #else
2354 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2355 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_pselect6, 11, 0),
2356 #endif
2357
2358 /* Allow system exit calls for the forked process */
2359 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2360 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_exit_group, 9, 0),
2361
2362 /* Allow system read calls */
2363 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2364 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_read, 7, 0),
2365
2366 /* Allow system write calls */
2367 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2368 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_write, 5, 0),
2369
2370 /* Allow system brk calls (we need this for malloc) */
2371 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2372 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_brk, 3, 0),
2373
2374 /* Futex is required for mutex locks */
2375 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2376 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_futex, 1, 0),
2377
2378 /* Return error if we hit a system call not on the whitelist */
2379 BPF_STMT(BPF_RET + BPF_K, SECCOMP_RET_ERRNO | (EPERM & SECCOMP_RET_DATA)),
2380
2381 /* Allow whitelisted system calls */
2382 BPF_STMT(BPF_RET + BPF_K, SECCOMP_RET_ALLOW),
2383 };
2384
2385 struct sock_fprog prog = {
2386 .len = (unsigned short)(sizeof(filter) / sizeof(filter[0])),
2387 .filter = filter,
2388 };
2389
2390 if (prctl(PR_SET_NO_NEW_PRIVS, 1, 0, 0, 0))
2391 return -1;
2392
2393 if (prctl(PR_SET_SECCOMP, SECCOMP_MODE_FILTER, &prog))
2394 return -1;
2395
2396 return 0;
2397 }
2398
2399 /* Helper function with timeout support for reading from the pipe between
2400 * processes used for secure compile.
2401 */
2402 bool radv_sc_read(int fd, void *buf, size_t size, bool timeout)
2403 {
2404 fd_set fds;
2405 struct timeval tv;
2406
2407 FD_ZERO(&fds);
2408 FD_SET(fd, &fds);
2409
2410 while (true) {
2411 /* We can't rely on the value of tv after calling select() so
2412 * we must reset it on each iteration of the loop.
2413 */
2414 tv.tv_sec = 5;
2415 tv.tv_usec = 0;
2416
2417 int rval = select(fd + 1, &fds, NULL, NULL, timeout ? &tv : NULL);
2418
2419 if (rval == -1) {
2420 /* select error */
2421 return false;
2422 } else if (rval) {
2423 ssize_t bytes_read = read(fd, buf, size);
2424 if (bytes_read < 0)
2425 return false;
2426
2427 buf += bytes_read;
2428 size -= bytes_read;
2429 if (size == 0)
2430 return true;
2431 } else {
2432 /* select timeout */
2433 return false;
2434 }
2435 }
2436 }
2437
2438 static bool radv_close_all_fds(const int *keep_fds, int keep_fd_count)
2439 {
2440 DIR *d;
2441 struct dirent *dir;
2442 d = opendir("/proc/self/fd");
2443 if (!d)
2444 return false;
2445 int dir_fd = dirfd(d);
2446
2447 while ((dir = readdir(d)) != NULL) {
2448 if (dir->d_name[0] == '.')
2449 continue;
2450
2451 int fd = atoi(dir->d_name);
2452 if (fd == dir_fd)
2453 continue;
2454
2455 bool keep = false;
2456 for (int i = 0; !keep && i < keep_fd_count; ++i)
2457 if (keep_fds[i] == fd)
2458 keep = true;
2459
2460 if (keep)
2461 continue;
2462
2463 close(fd);
2464 }
2465 closedir(d);
2466 return true;
2467 }
2468
2469 static bool secure_compile_open_fifo_fds(struct radv_secure_compile_state *sc,
2470 int *fd_server, int *fd_client,
2471 unsigned process, bool make_fifo)
2472 {
2473 bool result = false;
2474 char *fifo_server_path = NULL;
2475 char *fifo_client_path = NULL;
2476
2477 if (asprintf(&fifo_server_path, "/tmp/radv_server_%s_%u", sc->uid, process) == -1)
2478 goto open_fifo_exit;
2479
2480 if (asprintf(&fifo_client_path, "/tmp/radv_client_%s_%u", sc->uid, process) == -1)
2481 goto open_fifo_exit;
2482
2483 if (make_fifo) {
2484 int file1 = mkfifo(fifo_server_path, 0666);
2485 if(file1 < 0)
2486 goto open_fifo_exit;
2487
2488 int file2 = mkfifo(fifo_client_path, 0666);
2489 if(file2 < 0)
2490 goto open_fifo_exit;
2491 }
2492
2493 *fd_server = open(fifo_server_path, O_RDWR);
2494 if(*fd_server < 1)
2495 goto open_fifo_exit;
2496
2497 *fd_client = open(fifo_client_path, O_RDWR);
2498 if(*fd_client < 1) {
2499 close(*fd_server);
2500 goto open_fifo_exit;
2501 }
2502
2503 result = true;
2504
2505 open_fifo_exit:
2506 free(fifo_server_path);
2507 free(fifo_client_path);
2508
2509 return result;
2510 }
2511
2512 static void run_secure_compile_device(struct radv_device *device, unsigned process,
2513 int fd_idle_device_output)
2514 {
2515 int fd_secure_input;
2516 int fd_secure_output;
2517 bool fifo_result = secure_compile_open_fifo_fds(device->sc_state,
2518 &fd_secure_input,
2519 &fd_secure_output,
2520 process, false);
2521
2522 enum radv_secure_compile_type sc_type;
2523
2524 const int needed_fds[] = {
2525 fd_secure_input,
2526 fd_secure_output,
2527 fd_idle_device_output,
2528 };
2529
2530 if (!fifo_result || !radv_close_all_fds(needed_fds, ARRAY_SIZE(needed_fds)) ||
2531 install_seccomp_filter() == -1) {
2532 sc_type = RADV_SC_TYPE_INIT_FAILURE;
2533 } else {
2534 sc_type = RADV_SC_TYPE_INIT_SUCCESS;
2535 device->sc_state->secure_compile_processes[process].fd_secure_input = fd_secure_input;
2536 device->sc_state->secure_compile_processes[process].fd_secure_output = fd_secure_output;
2537 }
2538
2539 write(fd_idle_device_output, &sc_type, sizeof(sc_type));
2540
2541 if (sc_type == RADV_SC_TYPE_INIT_FAILURE)
2542 goto secure_compile_exit;
2543
2544 while (true) {
2545 radv_sc_read(fd_secure_input, &sc_type, sizeof(sc_type), false);
2546
2547 if (sc_type == RADV_SC_TYPE_COMPILE_PIPELINE) {
2548 struct radv_pipeline *pipeline;
2549 bool sc_read = true;
2550
2551 pipeline = vk_zalloc2(&device->vk.alloc, NULL, sizeof(*pipeline), 8,
2552 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2553
2554 pipeline->device = device;
2555
2556 /* Read pipeline layout */
2557 struct radv_pipeline_layout layout;
2558 sc_read = radv_sc_read(fd_secure_input, &layout, sizeof(struct radv_pipeline_layout), true);
2559 sc_read &= radv_sc_read(fd_secure_input, &layout.num_sets, sizeof(uint32_t), true);
2560 if (!sc_read)
2561 goto secure_compile_exit;
2562
2563 for (uint32_t set = 0; set < layout.num_sets; set++) {
2564 uint32_t layout_size;
2565 sc_read &= radv_sc_read(fd_secure_input, &layout_size, sizeof(uint32_t), true);
2566 if (!sc_read)
2567 goto secure_compile_exit;
2568
2569 layout.set[set].layout = malloc(layout_size);
2570 layout.set[set].layout->layout_size = layout_size;
2571 sc_read &= radv_sc_read(fd_secure_input, layout.set[set].layout,
2572 layout.set[set].layout->layout_size, true);
2573 }
2574
2575 pipeline->layout = &layout;
2576
2577 /* Read pipeline key */
2578 struct radv_pipeline_key key;
2579 sc_read &= radv_sc_read(fd_secure_input, &key, sizeof(struct radv_pipeline_key), true);
2580
2581 /* Read pipeline create flags */
2582 VkPipelineCreateFlags flags;
2583 sc_read &= radv_sc_read(fd_secure_input, &flags, sizeof(VkPipelineCreateFlags), true);
2584
2585 /* Read stage and shader information */
2586 uint32_t num_stages;
2587 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
2588 sc_read &= radv_sc_read(fd_secure_input, &num_stages, sizeof(uint32_t), true);
2589 if (!sc_read)
2590 goto secure_compile_exit;
2591
2592 for (uint32_t i = 0; i < num_stages; i++) {
2593
2594 /* Read stage */
2595 gl_shader_stage stage;
2596 sc_read &= radv_sc_read(fd_secure_input, &stage, sizeof(gl_shader_stage), true);
2597
2598 VkPipelineShaderStageCreateInfo *pStage = calloc(1, sizeof(VkPipelineShaderStageCreateInfo));
2599
2600 /* Read entry point name */
2601 size_t name_size;
2602 sc_read &= radv_sc_read(fd_secure_input, &name_size, sizeof(size_t), true);
2603 if (!sc_read)
2604 goto secure_compile_exit;
2605
2606 char *ep_name = malloc(name_size);
2607 sc_read &= radv_sc_read(fd_secure_input, ep_name, name_size, true);
2608 pStage->pName = ep_name;
2609
2610 /* Read shader module */
2611 size_t module_size;
2612 sc_read &= radv_sc_read(fd_secure_input, &module_size, sizeof(size_t), true);
2613 if (!sc_read)
2614 goto secure_compile_exit;
2615
2616 struct radv_shader_module *module = malloc(module_size);
2617 sc_read &= radv_sc_read(fd_secure_input, module, module_size, true);
2618 pStage->module = radv_shader_module_to_handle(module);
2619
2620 /* Read specialization info */
2621 bool has_spec_info;
2622 sc_read &= radv_sc_read(fd_secure_input, &has_spec_info, sizeof(bool), true);
2623 if (!sc_read)
2624 goto secure_compile_exit;
2625
2626 if (has_spec_info) {
2627 VkSpecializationInfo *specInfo = malloc(sizeof(VkSpecializationInfo));
2628 pStage->pSpecializationInfo = specInfo;
2629
2630 sc_read &= radv_sc_read(fd_secure_input, &specInfo->dataSize, sizeof(size_t), true);
2631 if (!sc_read)
2632 goto secure_compile_exit;
2633
2634 void *si_data = malloc(specInfo->dataSize);
2635 sc_read &= radv_sc_read(fd_secure_input, si_data, specInfo->dataSize, true);
2636 specInfo->pData = si_data;
2637
2638 sc_read &= radv_sc_read(fd_secure_input, &specInfo->mapEntryCount, sizeof(uint32_t), true);
2639 if (!sc_read)
2640 goto secure_compile_exit;
2641
2642 VkSpecializationMapEntry *mapEntries = malloc(sizeof(VkSpecializationMapEntry) * specInfo->mapEntryCount);
2643 for (uint32_t j = 0; j < specInfo->mapEntryCount; j++) {
2644 sc_read &= radv_sc_read(fd_secure_input, &mapEntries[j], sizeof(VkSpecializationMapEntry), true);
2645 if (!sc_read)
2646 goto secure_compile_exit;
2647 }
2648
2649 specInfo->pMapEntries = mapEntries;
2650 }
2651
2652 pStages[stage] = pStage;
2653 }
2654
2655 /* Compile the shaders */
2656 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
2657 radv_create_shaders(pipeline, device, NULL, &key, pStages, flags, NULL, stage_feedbacks);
2658
2659 /* free memory allocated above */
2660 for (uint32_t set = 0; set < layout.num_sets; set++)
2661 free(layout.set[set].layout);
2662
2663 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
2664 if (!pStages[i])
2665 continue;
2666
2667 free((void *) pStages[i]->pName);
2668 free(radv_shader_module_from_handle(pStages[i]->module));
2669 if (pStages[i]->pSpecializationInfo) {
2670 free((void *) pStages[i]->pSpecializationInfo->pData);
2671 free((void *) pStages[i]->pSpecializationInfo->pMapEntries);
2672 free((void *) pStages[i]->pSpecializationInfo);
2673 }
2674 free((void *) pStages[i]);
2675 }
2676
2677 vk_free(&device->vk.alloc, pipeline);
2678
2679 sc_type = RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED;
2680 write(fd_secure_output, &sc_type, sizeof(sc_type));
2681
2682 } else if (sc_type == RADV_SC_TYPE_DESTROY_DEVICE) {
2683 goto secure_compile_exit;
2684 }
2685 }
2686
2687 secure_compile_exit:
2688 close(fd_secure_input);
2689 close(fd_secure_output);
2690 close(fd_idle_device_output);
2691 _exit(0);
2692 }
2693
2694 static enum radv_secure_compile_type fork_secure_compile_device(struct radv_device *device, unsigned process)
2695 {
2696 int fd_secure_input[2];
2697 int fd_secure_output[2];
2698
2699 /* create pipe descriptors (used to communicate between processes) */
2700 if (pipe(fd_secure_input) == -1 || pipe(fd_secure_output) == -1)
2701 return RADV_SC_TYPE_INIT_FAILURE;
2702
2703
2704 int sc_pid;
2705 if ((sc_pid = fork()) == 0) {
2706 device->sc_state->secure_compile_thread_counter = process;
2707 run_secure_compile_device(device, process, fd_secure_output[1]);
2708 } else {
2709 if (sc_pid == -1)
2710 return RADV_SC_TYPE_INIT_FAILURE;
2711
2712 /* Read the init result returned from the secure process */
2713 enum radv_secure_compile_type sc_type;
2714 bool sc_read = radv_sc_read(fd_secure_output[0], &sc_type, sizeof(sc_type), true);
2715
2716 if (sc_type == RADV_SC_TYPE_INIT_FAILURE || !sc_read) {
2717 close(fd_secure_input[0]);
2718 close(fd_secure_input[1]);
2719 close(fd_secure_output[1]);
2720 close(fd_secure_output[0]);
2721 int status;
2722 waitpid(sc_pid, &status, 0);
2723
2724 return RADV_SC_TYPE_INIT_FAILURE;
2725 } else {
2726 assert(sc_type == RADV_SC_TYPE_INIT_SUCCESS);
2727 write(device->sc_state->secure_compile_processes[process].fd_secure_output, &sc_type, sizeof(sc_type));
2728
2729 close(fd_secure_input[0]);
2730 close(fd_secure_input[1]);
2731 close(fd_secure_output[1]);
2732 close(fd_secure_output[0]);
2733
2734 int status;
2735 waitpid(sc_pid, &status, 0);
2736 }
2737 }
2738
2739 return RADV_SC_TYPE_INIT_SUCCESS;
2740 }
2741
2742 /* Run a bare bones fork of a device that was forked right after its creation.
2743 * This device will have low overhead when it is forked again before each
2744 * pipeline compilation. This device sits idle and its only job is to fork
2745 * itself.
2746 */
2747 static void run_secure_compile_idle_device(struct radv_device *device, unsigned process,
2748 int fd_secure_input, int fd_secure_output)
2749 {
2750 enum radv_secure_compile_type sc_type = RADV_SC_TYPE_INIT_SUCCESS;
2751 device->sc_state->secure_compile_processes[process].fd_secure_input = fd_secure_input;
2752 device->sc_state->secure_compile_processes[process].fd_secure_output = fd_secure_output;
2753
2754 write(fd_secure_output, &sc_type, sizeof(sc_type));
2755
2756 while (true) {
2757 radv_sc_read(fd_secure_input, &sc_type, sizeof(sc_type), false);
2758
2759 if (sc_type == RADV_SC_TYPE_FORK_DEVICE) {
2760 sc_type = fork_secure_compile_device(device, process);
2761
2762 if (sc_type == RADV_SC_TYPE_INIT_FAILURE)
2763 goto secure_compile_exit;
2764
2765 } else if (sc_type == RADV_SC_TYPE_DESTROY_DEVICE) {
2766 goto secure_compile_exit;
2767 }
2768 }
2769
2770 secure_compile_exit:
2771 close(fd_secure_input);
2772 close(fd_secure_output);
2773 _exit(0);
2774 }
2775
2776 static void destroy_secure_compile_device(struct radv_device *device, unsigned process)
2777 {
2778 int fd_secure_input = device->sc_state->secure_compile_processes[process].fd_secure_input;
2779
2780 enum radv_secure_compile_type sc_type = RADV_SC_TYPE_DESTROY_DEVICE;
2781 write(fd_secure_input, &sc_type, sizeof(sc_type));
2782
2783 close(device->sc_state->secure_compile_processes[process].fd_secure_input);
2784 close(device->sc_state->secure_compile_processes[process].fd_secure_output);
2785
2786 int status;
2787 waitpid(device->sc_state->secure_compile_processes[process].sc_pid, &status, 0);
2788 }
2789
2790 static VkResult fork_secure_compile_idle_device(struct radv_device *device)
2791 {
2792 device->sc_state = vk_zalloc(&device->vk.alloc,
2793 sizeof(struct radv_secure_compile_state),
2794 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2795
2796 mtx_init(&device->sc_state->secure_compile_mutex, mtx_plain);
2797
2798 pid_t upid = getpid();
2799 time_t seconds = time(NULL);
2800
2801 char *uid;
2802 if (asprintf(&uid, "%ld_%ld", (long) upid, (long) seconds) == -1)
2803 return VK_ERROR_INITIALIZATION_FAILED;
2804
2805 device->sc_state->uid = uid;
2806
2807 uint8_t sc_threads = device->instance->num_sc_threads;
2808 int fd_secure_input[MAX_SC_PROCS][2];
2809 int fd_secure_output[MAX_SC_PROCS][2];
2810
2811 /* create pipe descriptors (used to communicate between processes) */
2812 for (unsigned i = 0; i < sc_threads; i++) {
2813 if (pipe(fd_secure_input[i]) == -1 ||
2814 pipe(fd_secure_output[i]) == -1) {
2815 return VK_ERROR_INITIALIZATION_FAILED;
2816 }
2817 }
2818
2819 device->sc_state->secure_compile_processes = vk_zalloc(&device->vk.alloc,
2820 sizeof(struct radv_secure_compile_process) * sc_threads, 8,
2821 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2822
2823 for (unsigned process = 0; process < sc_threads; process++) {
2824 if ((device->sc_state->secure_compile_processes[process].sc_pid = fork()) == 0) {
2825 device->sc_state->secure_compile_thread_counter = process;
2826 run_secure_compile_idle_device(device, process, fd_secure_input[process][0], fd_secure_output[process][1]);
2827 } else {
2828 if (device->sc_state->secure_compile_processes[process].sc_pid == -1)
2829 return VK_ERROR_INITIALIZATION_FAILED;
2830
2831 /* Read the init result returned from the secure process */
2832 enum radv_secure_compile_type sc_type;
2833 bool sc_read = radv_sc_read(fd_secure_output[process][0], &sc_type, sizeof(sc_type), true);
2834
2835 bool fifo_result;
2836 if (sc_read && sc_type == RADV_SC_TYPE_INIT_SUCCESS) {
2837 fifo_result = secure_compile_open_fifo_fds(device->sc_state,
2838 &device->sc_state->secure_compile_processes[process].fd_server,
2839 &device->sc_state->secure_compile_processes[process].fd_client,
2840 process, true);
2841
2842 device->sc_state->secure_compile_processes[process].fd_secure_input = fd_secure_input[process][1];
2843 device->sc_state->secure_compile_processes[process].fd_secure_output = fd_secure_output[process][0];
2844 }
2845
2846 if (sc_type == RADV_SC_TYPE_INIT_FAILURE || !sc_read || !fifo_result) {
2847 close(fd_secure_input[process][0]);
2848 close(fd_secure_input[process][1]);
2849 close(fd_secure_output[process][1]);
2850 close(fd_secure_output[process][0]);
2851 int status;
2852 waitpid(device->sc_state->secure_compile_processes[process].sc_pid, &status, 0);
2853
2854 /* Destroy any forks that were created sucessfully */
2855 for (unsigned i = 0; i < process; i++) {
2856 destroy_secure_compile_device(device, i);
2857 }
2858
2859 return VK_ERROR_INITIALIZATION_FAILED;
2860 }
2861 }
2862 }
2863 return VK_SUCCESS;
2864 }
2865
2866 static void
2867 radv_device_init_dispatch(struct radv_device *device)
2868 {
2869 const struct radv_instance *instance = device->physical_device->instance;
2870 const struct radv_device_dispatch_table *dispatch_table_layer = NULL;
2871 bool unchecked = instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS;
2872 int radv_thread_trace = radv_get_int_debug_option("RADV_THREAD_TRACE", -1);
2873
2874 if (radv_thread_trace >= 0) {
2875 /* Use device entrypoints from the SQTT layer if enabled. */
2876 dispatch_table_layer = &sqtt_device_dispatch_table;
2877 }
2878
2879 for (unsigned i = 0; i < ARRAY_SIZE(device->dispatch.entrypoints); i++) {
2880 /* Vulkan requires that entrypoints for extensions which have not been
2881 * enabled must not be advertised.
2882 */
2883 if (!unchecked &&
2884 !radv_device_entrypoint_is_enabled(i, instance->apiVersion,
2885 &instance->enabled_extensions,
2886 &device->enabled_extensions)) {
2887 device->dispatch.entrypoints[i] = NULL;
2888 } else if (dispatch_table_layer &&
2889 dispatch_table_layer->entrypoints[i]) {
2890 device->dispatch.entrypoints[i] =
2891 dispatch_table_layer->entrypoints[i];
2892 } else {
2893 device->dispatch.entrypoints[i] =
2894 radv_device_dispatch_table.entrypoints[i];
2895 }
2896 }
2897 }
2898
2899 static VkResult
2900 radv_create_pthread_cond(pthread_cond_t *cond)
2901 {
2902 pthread_condattr_t condattr;
2903 if (pthread_condattr_init(&condattr)) {
2904 return VK_ERROR_INITIALIZATION_FAILED;
2905 }
2906
2907 if (pthread_condattr_setclock(&condattr, CLOCK_MONOTONIC)) {
2908 pthread_condattr_destroy(&condattr);
2909 return VK_ERROR_INITIALIZATION_FAILED;
2910 }
2911 if (pthread_cond_init(cond, &condattr)) {
2912 pthread_condattr_destroy(&condattr);
2913 return VK_ERROR_INITIALIZATION_FAILED;
2914 }
2915 pthread_condattr_destroy(&condattr);
2916 return VK_SUCCESS;
2917 }
2918
2919 static VkResult
2920 check_physical_device_features(VkPhysicalDevice physicalDevice,
2921 const VkPhysicalDeviceFeatures *features)
2922 {
2923 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2924 VkPhysicalDeviceFeatures supported_features;
2925 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
2926 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
2927 VkBool32 *enabled_feature = (VkBool32 *)features;
2928 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
2929 for (uint32_t i = 0; i < num_features; i++) {
2930 if (enabled_feature[i] && !supported_feature[i])
2931 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
2932 }
2933
2934 return VK_SUCCESS;
2935 }
2936
2937 VkResult radv_CreateDevice(
2938 VkPhysicalDevice physicalDevice,
2939 const VkDeviceCreateInfo* pCreateInfo,
2940 const VkAllocationCallbacks* pAllocator,
2941 VkDevice* pDevice)
2942 {
2943 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2944 VkResult result;
2945 struct radv_device *device;
2946
2947 bool keep_shader_info = false;
2948 bool robust_buffer_access = false;
2949 bool overallocation_disallowed = false;
2950
2951 /* Check enabled features */
2952 if (pCreateInfo->pEnabledFeatures) {
2953 result = check_physical_device_features(physicalDevice,
2954 pCreateInfo->pEnabledFeatures);
2955 if (result != VK_SUCCESS)
2956 return result;
2957
2958 if (pCreateInfo->pEnabledFeatures->robustBufferAccess)
2959 robust_buffer_access = true;
2960 }
2961
2962 vk_foreach_struct_const(ext, pCreateInfo->pNext) {
2963 switch (ext->sType) {
2964 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FEATURES_2: {
2965 const VkPhysicalDeviceFeatures2 *features = (const void *)ext;
2966 result = check_physical_device_features(physicalDevice,
2967 &features->features);
2968 if (result != VK_SUCCESS)
2969 return result;
2970
2971 if (features->features.robustBufferAccess)
2972 robust_buffer_access = true;
2973 break;
2974 }
2975 case VK_STRUCTURE_TYPE_DEVICE_MEMORY_OVERALLOCATION_CREATE_INFO_AMD: {
2976 const VkDeviceMemoryOverallocationCreateInfoAMD *overallocation = (const void *)ext;
2977 if (overallocation->overallocationBehavior == VK_MEMORY_OVERALLOCATION_BEHAVIOR_DISALLOWED_AMD)
2978 overallocation_disallowed = true;
2979 break;
2980 }
2981 default:
2982 break;
2983 }
2984 }
2985
2986 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
2987 sizeof(*device), 8,
2988 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2989 if (!device)
2990 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2991
2992 vk_device_init(&device->vk, pCreateInfo,
2993 &physical_device->instance->alloc, pAllocator);
2994
2995 device->instance = physical_device->instance;
2996 device->physical_device = physical_device;
2997
2998 device->ws = physical_device->ws;
2999
3000 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
3001 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
3002 int index = radv_get_device_extension_index(ext_name);
3003 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
3004 vk_free(&device->vk.alloc, device);
3005 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
3006 }
3007
3008 device->enabled_extensions.extensions[index] = true;